From d97e25ac134c927d5e42fdc4388a845b7a118f9f Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 4 Mar 2022 07:19:45 -0700 Subject: [PATCH] Merge 4.16 Change-Id: I11db70a8e25a6656c5ec640a703e7b06d5a3672e --- 3rdparty/amd_blobs | 2 +- 3rdparty/arm-trusted-firmware | 2 +- 3rdparty/blobs | 2 +- 3rdparty/chromeec | 2 +- 3rdparty/intel-microcode | 2 +- 3rdparty/qc_blobs | 2 +- 3rdparty/vboot | 2 +- Documentation/acpi/gpio.md | 9 - Documentation/community/index.md | 7 + Documentation/community/services.md | 2 +- Documentation/contributing/gsoc.md | 249 + Documentation/contributing/index.md | 6 + Documentation/distributions.md | 7 + .../getting_started/gerrit_guidelines.md | 6 +- Documentation/getting_started/gpio.md | 47 + Documentation/index.md | 10 +- Documentation/mainboard/acer/g43t-am3.md | 177 + Documentation/mainboard/asrock/h77pro4-m.md | 174 + .../mainboard/emulation/qemu-power9.md | 52 + Documentation/mainboard/facebook/fbg1701.md | 5 +- Documentation/mainboard/index.md | 9 + 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.../google/hatch/variants/palkia/gpio.c | 3 +- .../google/hatch/variants/puff/data.vbt | Bin 0 -> 4608 bytes .../google/hatch/variants/puff/gpio.c | 2 + .../google/hatch/variants/scout/gpio.c | 2 + .../hatch/variants/scout/overridetree.cb | 19 +- .../google/hatch/variants/stryke/Makefile.inc | 12 - .../google/hatch/variants/stryke/gpio.c | 97 - .../variants/stryke/include/variant/ec.h | 8 - .../variants/stryke/include/variant/gpio.h | 14 - .../hatch/variants/stryke/overridetree.cb | 218 - .../google/hatch/variants/wyvern/data.vbt | Bin 0 -> 4608 bytes .../google/hatch/variants/wyvern/gpio.c | 2 + src/mainboard/google/herobrine/Kconfig | 30 +- src/mainboard/google/herobrine/Kconfig.name | 7 + src/mainboard/google/herobrine/board.h | 32 +- src/mainboard/google/herobrine/boardid.c | 19 +- src/mainboard/google/herobrine/bootblock.c | 12 + src/mainboard/google/herobrine/chromeos.c | 37 +- src/mainboard/google/herobrine/mainboard.c | 48 +- src/mainboard/google/herobrine/romstage.c | 12 +- src/mainboard/google/jecht/Kconfig | 21 +- src/mainboard/google/jecht/Kconfig.name | 4 - src/mainboard/google/jecht/chromeos.c | 26 +- src/mainboard/google/jecht/devicetree.cb | 2 +- src/mainboard/google/jecht/mainboard.c | 2 - src/mainboard/google/jecht/onboard.h | 6 + .../guado/include/variant/acpi/thermal.asl | 24 +- .../jecht/include/variant/acpi/thermal.asl | 24 +- .../rikku/include/variant/acpi/thermal.asl | 24 +- .../tidus/include/variant/acpi/thermal.asl | 26 +- src/mainboard/google/kahlee/Kconfig | 21 + src/mainboard/google/kahlee/Kconfig.name | 13 +- src/mainboard/google/kahlee/OemCustomize.c | 4 +- .../google/kahlee/bootblock/bootblock.c | 26 - src/mainboard/google/kahlee/chromeos.c | 8 + src/mainboard/google/kahlee/ec.c | 2 +- src/mainboard/google/kahlee/mainboard.c | 3 +- src/mainboard/google/kahlee/smihandler.c | 1 - .../kahlee/variants/baseboard/OemCustomize.c | 2 +- .../include/baseboard/acpi/sleep.asl | 4 +- .../include/baseboard/acpi/thermal.asl | 8 +- .../google/kahlee/variants/baseboard/memory.c | 4 +- src/mainboard/google/kukui/Kconfig | 1 + src/mainboard/google/kukui/Kconfig.name | 12 +- src/mainboard/google/kukui/chromeos.c | 6 + src/mainboard/google/kukui/sdram_configs.c | 17 + src/mainboard/google/link/Kconfig | 25 +- src/mainboard/google/link/chromeos.c | 16 +- src/mainboard/google/link/devicetree.cb | 2 +- src/mainboard/google/link/early_init.c | 6 +- src/mainboard/google/link/mainboard.c | 3 - src/mainboard/google/link/onboard.h | 4 + src/mainboard/google/mistral/chromeos.c | 8 + src/mainboard/google/nyan/chromeos.c | 6 + src/mainboard/google/nyan/mainboard.c | 1 - src/mainboard/google/nyan_big/chromeos.c | 6 + src/mainboard/google/nyan_big/mainboard.c | 1 - src/mainboard/google/nyan_blaze/chromeos.c | 6 + src/mainboard/google/nyan_blaze/mainboard.c | 1 - src/mainboard/google/oak/chromeos.c | 6 + src/mainboard/google/oak/mainboard.c | 1 - src/mainboard/google/octopus/Kconfig | 89 +- src/mainboard/google/octopus/Kconfig.name | 100 +- src/mainboard/google/octopus/chromeos.c | 8 + src/mainboard/google/octopus/default.fmd | 2 +- src/mainboard/google/octopus/mainboard.c | 27 +- src/mainboard/google/octopus/romstage.c | 2 +- src/mainboard/google/octopus/smihandler.c | 1 - .../google/octopus/variants/baseboard/gpio.c | 5 +- .../baseboard/include/baseboard/cbi_ssfc.h | 1 + .../google/octopus/variants/baseboard/nhlt.c | 4 +- .../octopus/variants/bloog/Makefile.inc | 2 + .../octopus/variants/bloog/blooguard-data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/bloog/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/bobba/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/bobba/variant.c | 1 - .../google/octopus/variants/casta/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/dood/variant.c | 1 - .../google/octopus/variants/fleex/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/garg/Makefile.inc | 4 + .../google/octopus/variants/garg/data.vbt | Bin 0 -> 5632 bytes .../octopus/variants/garg/garfour-data.vbt | Bin 0 -> 5632 bytes .../variants/garg/garfour-hdmi-data.vbt | Bin 0 -> 5632 bytes .../octopus/variants/garg/garg-hdmi-data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/garg/variant.c | 1 - .../google/octopus/variants/lick/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/meep/Makefile.inc | 3 + .../google/octopus/variants/meep/data.vbt | Bin 0 -> 5632 bytes .../octopus/variants/meep/dorp-hdmi-data.vbt | Bin 0 -> 5632 bytes .../octopus/variants/meep/vortininja-data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/phaser/data.vbt | Bin 0 -> 5632 bytes .../google/octopus/variants/yorp/data.vbt | Bin 0 -> 5632 bytes src/mainboard/google/parrot/Kconfig | 30 +- src/mainboard/google/parrot/acpi_tables.c | 1 - src/mainboard/google/parrot/chromeos.c | 30 +- src/mainboard/google/parrot/devicetree.cb | 2 +- src/mainboard/google/parrot/early_init.c | 6 +- src/mainboard/google/parrot/ec.c | 1 - src/mainboard/google/parrot/mainboard.c | 2 - src/mainboard/google/parrot/onboard.h | 9 + src/mainboard/google/peach_pit/chromeos.c | 7 + src/mainboard/google/poppy/Kconfig | 168 +- src/mainboard/google/poppy/Kconfig.name | 29 +- src/mainboard/google/poppy/chromeos.c | 9 +- src/mainboard/google/poppy/mainboard.c | 2 - .../google/poppy/variants/atlas/devicetree.cb | 2 - .../google/poppy/variants/atlas/gpio.c | 3 + .../poppy/variants/baseboard/devicetree.cb | 2 - .../google/poppy/variants/baseboard/gpio.c | 6 +- .../google/poppy/variants/nami/devicetree.cb | 2 - .../google/poppy/variants/nami/gpio.c | 3 + .../google/poppy/variants/nami/mainboard.c | 2 +- .../poppy/variants/nautilus/devicetree.cb | 2 - .../google/poppy/variants/nautilus/gpio.c | 3 + .../poppy/variants/nocturne/devicetree.cb | 2 - .../google/poppy/variants/nocturne/ec.c | 1 - .../google/poppy/variants/nocturne/gpio.c | 3 + .../poppy/variants/rammus/devicetree.cb | 2 - .../google/poppy/variants/rammus/gpio.c | 3 + .../poppy/variants/soraka/devicetree.cb | 2 - .../google/poppy/variants/soraka/gpio.c | 4 + src/mainboard/google/rambi/Kconfig | 91 +- src/mainboard/google/rambi/Kconfig.name | 16 - src/mainboard/google/rambi/chromeos.c | 10 + src/mainboard/google/rambi/mainboard.c | 3 - src/mainboard/google/reef/Kconfig | 38 +- src/mainboard/google/reef/Kconfig.name | 15 - src/mainboard/google/reef/chromeos.c | 8 + src/mainboard/google/reef/default.fmd | 2 +- src/mainboard/google/reef/mainboard.c | 2 - src/mainboard/google/reef/smihandler.c | 1 - .../google/reef/variants/baseboard/gpio.c | 5 +- .../google/reef/variants/coral/Makefile.inc | 8 + .../reef/variants/coral/astronaut-data.vbt | Bin 0 -> 6656 bytes .../reef/variants/coral/babymega-data.vbt | Bin 0 -> 6656 bytes .../reef/variants/coral/babytiger-data.vbt | Bin 0 -> 6656 bytes .../google/reef/{ => variants/coral}/data.vbt | Bin 6656 -> 6656 bytes .../reef/variants/coral/epaulette-data.vbt | Bin 0 -> 6656 bytes .../google/reef/variants/coral/gpio.c | 5 +- .../google/reef/variants/coral/mainboard.c | 68 +- .../reef/variants/coral/nasher-data.vbt | Bin 0 -> 6656 bytes .../variants/coral/rabbid_rugged-data.vbt | Bin 0 -> 6656 bytes .../google/reef/variants/coral/santa-data.vbt | Bin 0 -> 6656 bytes .../nasher/include/variant/acpi/dptf.asl | 4 - .../reef/variants/nasher/include/variant/ec.h | 4 - .../variants/nasher/include/variant/gpio.h | 4 - .../google/reef/variants/pyro/data.vbt | Bin 0 -> 6656 bytes .../google/reef/variants/reef/data.vbt | Bin 0 -> 6656 bytes .../google/reef/variants/sand/data.vbt | Bin 0 -> 6656 bytes .../google/reef/variants/snappy/data.vbt | Bin 0 -> 6656 bytes src/mainboard/google/sarien/Kconfig | 33 +- src/mainboard/google/sarien/Kconfig.name | 6 +- src/mainboard/google/sarien/chromeos.c | 39 +- src/mainboard/google/sarien/data.vbt | Bin 0 -> 6144 bytes src/mainboard/google/sarien/ramstage.c | 8 - .../sarien/variants/arcada/devicetree.cb | 2 +- .../sarien/variants/sarien/devicetree.cb | 2 +- src/mainboard/google/skyrim/Kconfig | 59 + src/mainboard/google/skyrim/Kconfig.name | 5 + src/mainboard/google/skyrim/Makefile.inc | 15 + src/mainboard/google/skyrim/board_info.txt | 6 + src/mainboard/google/skyrim/bootblock.c | 18 + src/mainboard/google/skyrim/chromeos.c | 26 + src/mainboard/google/skyrim/chromeos.fmd | 34 + src/mainboard/google/skyrim/dsdt.asl | 27 + src/mainboard/google/skyrim/ec.c | 34 + src/mainboard/google/skyrim/mainboard.c | 34 + .../google/skyrim/port_descriptors.c | 11 + .../skyrim/variants/baseboard/Makefile.inc | 5 + .../skyrim/variants/baseboard/devicetree.cb | 18 + .../google/skyrim/variants/baseboard/gpio.c | 176 + .../baseboard/include/baseboard/baseboard.h | 6 + .../variants/baseboard/include/baseboard/ec.h | 80 + .../baseboard/include/baseboard/gpio.h | 11 + .../baseboard/include/baseboard/variants.h | 28 + .../skyrim/variants/baseboard/smihandler.c | 26 + .../variants/skyrim/include/variant/ec.h | 3 + .../skyrim/variants/skyrim/overridetree.cb | 9 + src/mainboard/google/slippy/Kconfig | 35 +- src/mainboard/google/slippy/Kconfig.name | 4 - src/mainboard/google/slippy/acpi/thermal.asl | 10 +- src/mainboard/google/slippy/acpi_tables.c | 1 - src/mainboard/google/slippy/chromeos.c | 12 +- src/mainboard/google/slippy/mainboard.c | 2 - src/mainboard/google/slippy/onboard.h | 3 + .../google/slippy/variants/falco/romstage.c | 1 - .../google/slippy/variants/leon/romstage.c | 1 - .../peppy/include/variant/acpi/mainboard.asl | 4 +- .../google/slippy/variants/peppy/romstage.c | 1 - .../google/slippy/variants/wolf/romstage.c | 1 - src/mainboard/google/smaug/chromeos.c | 6 + src/mainboard/google/storm/chromeos.c | 9 +- src/mainboard/google/stout/Kconfig | 29 +- src/mainboard/google/stout/acpi_tables.c | 1 - src/mainboard/google/stout/chromeos.c | 7 +- src/mainboard/google/stout/devicetree.cb | 2 +- src/mainboard/google/stout/early_init.c | 6 +- src/mainboard/google/stout/ec.c | 1 - src/mainboard/google/stout/mainboard.c | 2 - src/mainboard/google/stout/onboard.h | 3 + src/mainboard/google/trogdor/board.h | 4 +- src/mainboard/google/trogdor/chromeos.c | 8 + src/mainboard/google/trogdor/mainboard.c | 37 +- src/mainboard/google/trogdor/romstage.c | 2 +- src/mainboard/google/veyron/chromeos.c | 8 +- src/mainboard/google/veyron/mainboard.c | 1 - src/mainboard/google/veyron/romstage.c | 1 - src/mainboard/google/veyron_mickey/chromeos.c | 9 +- .../google/veyron_mickey/mainboard.c | 1 - src/mainboard/google/veyron_mickey/romstage.c | 1 - src/mainboard/google/veyron_rialto/chromeos.c | 9 +- .../google/veyron_rialto/mainboard.c | 1 - src/mainboard/google/veyron_rialto/romstage.c | 1 - src/mainboard/google/volteer/Kconfig | 105 +- src/mainboard/google/volteer/Kconfig.name | 55 +- src/mainboard/google/volteer/chromeos.c | 8 + src/mainboard/google/volteer/mainboard.c | 3 - .../volteer/variants/baseboard/devicetree.cb | 11 +- .../google/volteer/variants/baseboard/gpio.c | 6 +- .../variants/baseboard/include/baseboard/ec.h | 6 +- .../google/volteer/variants/chronicler/gpio.c | 1 - .../volteer/variants/chronicler/memory.c | 6 + .../variants/chronicler/overridetree.cb | 23 +- .../volteer/variants/collis/Makefile.inc | 2 + .../google/volteer/variants/collis/gpio.c | 3 + .../volteer/variants/collis/overridetree.cb | 20 +- .../google/volteer/variants/collis/variant.c | 22 + .../volteer/variants/copano/Makefile.inc | 2 + .../google/volteer/variants/copano/gpio.c | 3 + .../volteer/variants/copano/overridetree.cb | 20 +- .../google/volteer/variants/copano/variant.c | 22 + .../volteer/variants/delbin/Makefile.inc | 2 + .../volteer/variants/delbin/overridetree.cb | 19 +- .../google/volteer/variants/delbin/variant.c | 22 + .../volteer/variants/drobit/Makefile.inc | 2 + .../volteer/variants/drobit/overridetree.cb | 19 +- .../google/volteer/variants/drobit/variant.c | 22 + .../volteer/variants/eldrid/overridetree.cb | 8 +- .../volteer/variants/elemi/overridetree.cb | 8 +- .../google/volteer/variants/halvor/gpio.c | 3 + .../volteer/variants/lindar/overridetree.cb | 8 +- .../google/volteer/variants/terrador/gpio.c | 3 + .../volteer/variants/terrador/overridetree.cb | 8 +- .../google/volteer/variants/todor/gpio.c | 3 + .../volteer/variants/todor/overridetree.cb | 8 +- .../google/volteer/variants/voema/gpio.c | 3 + .../volteer/variants/voema/overridetree.cb | 9 +- .../volteer/variants/volet/overridetree.cb | 8 +- .../volteer/variants/volteer/overridetree.cb | 8 +- .../volteer/variants/volteer2/overridetree.cb | 8 +- .../volteer/variants/voxel/overridetree.cb | 8 +- src/mainboard/google/zork/Kconfig | 19 +- src/mainboard/google/zork/Kconfig.name | 14 +- src/mainboard/google/zork/Makefile.inc | 1 + src/mainboard/google/zork/chromeos.c | 8 + src/mainboard/google/zork/mainboard.c | 2 - src/mainboard/google/zork/smihandler.c | 1 - .../zork/variants/baseboard/Makefile.inc | 4 - .../baseboard/gpio_baseboard_common.c | 31 - .../baseboard/gpio_baseboard_dalboz.c | 46 +- .../baseboard/gpio_baseboard_trembyle.c | 46 +- .../google/zork/variants/baseboard/helpers.c | 3 + .../include/baseboard/acpi/thermal.asl | 6 +- .../baseboard/include/baseboard/variants.h | 8 +- .../google/zork/variants/dalboz/variant.c | 2 - .../zork/variants/shuboz/overridetree.cb | 86 + .../zork/variants/shuboz/spd/Makefile.inc | 1 + .../variants/shuboz/spd/dram_id.generated.txt | 1 + .../variants/shuboz/spd/mem_parts_used.txt | 1 + .../google/zork/variants/shuboz/variant.c | 2 +- .../zork/variants/vilboz/spd/Makefile.inc | 4 + .../variants/vilboz/spd/dram_id.generated.txt | 4 + .../variants/vilboz/spd/mem_parts_used.txt | 4 + .../google/zork/variants/vilboz/variant.c | 2 +- src/mainboard/google/zork/verstage.c | 25 + src/mainboard/hp/280_g2/Kconfig | 3 + src/mainboard/hp/280_g2/devicetree.cb | 1 - src/mainboard/hp/abm/mainboard.c | 1 - .../hp/compaq_8200_elite_sff/devicetree.cb | 2 +- src/mainboard/hp/folio_9480m/romstage.c | 1 - .../hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 +- .../hp/pavilion_m6_1035dx/acpi/mainboard.asl | 2 +- .../hp/pavilion_m6_1035dx/mainboard.c | 1 - .../hp/snb_ivb_laptops/devicetree.cb | 2 +- .../hp/z220_sff_workstation/devicetree.cb | 2 +- src/mainboard/ibase/mb899/Kconfig | 3 + src/mainboard/intel/adlrvp/Kconfig | 49 +- src/mainboard/intel/adlrvp/Kconfig.name | 6 + src/mainboard/intel/adlrvp/Makefile.inc | 3 + src/mainboard/intel/adlrvp/board_id.c | 1 - src/mainboard/intel/adlrvp/bootblock.c | 86 - src/mainboard/intel/adlrvp/chromeos.c | 19 +- src/mainboard/intel/adlrvp/chromeos.fmd | 4 +- src/mainboard/intel/adlrvp/devicetree.cb | 23 +- src/mainboard/intel/adlrvp/devicetree_m.cb | 4 +- src/mainboard/intel/adlrvp/devicetree_n.cb | 292 + src/mainboard/intel/adlrvp/early_gpio.c | 164 +- src/mainboard/intel/adlrvp/early_gpio_m.c | 4 +- src/mainboard/intel/adlrvp/early_gpio_n.c | 30 + src/mainboard/intel/adlrvp/gpio.c | 7 +- src/mainboard/intel/adlrvp/gpio_m.c | 1 - src/mainboard/intel/adlrvp/gpio_n.c | 216 + .../intel/adlrvp/include/baseboard/ec.h | 4 +- .../intel/adlrvp/include/baseboard/gpio.h | 2 + .../intel/adlrvp/include/baseboard/variants.h | 2 + src/mainboard/intel/adlrvp/mainboard.c | 15 +- src/mainboard/intel/adlrvp/memory.c | 67 +- src/mainboard/intel/adlrvp/ramstage.c | 1 + .../intel/adlrvp/romstage_fsp_params.c | 25 +- src/mainboard/intel/adlrvp/spd/Makefile.inc | 2 +- .../intel/adlrvp/spd/adlrvp_n_lp5.spd.hex | 32 + .../variants/adlrvp_m_ext_ec/overridetree.cb | 8 +- .../adlrvp/variants/adlrvp_n/overridetree.cb | 4 + .../variants/adlrvp_n_ext_ec/overridetree.cb | 89 + .../variants/adlrvp_p_ext_ec/overridetree.cb | 12 +- .../variants/adlrvp_p_mchp/overridetree.cb | 8 +- src/mainboard/intel/baskingridge/Kconfig | 3 + src/mainboard/intel/baskingridge/chromeos.c | 12 +- src/mainboard/intel/baskingridge/mainboard.c | 2 - src/mainboard/intel/baskingridge/onboard.h | 12 + src/mainboard/intel/baskingridge/romstage.c | 1 - .../intel/cedarisland_crb/bootblock.c | 2 +- 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| 2 +- src/soc/amd/common/block/acpi/gpio.c | 8 +- src/soc/amd/common/block/acpi/ivrs.c | 1 - .../block/acpimmio/print_reset_status.c | 5 +- src/soc/amd/common/block/aoac/aoac.c | 4 +- src/soc/amd/common/block/apob/Makefile.inc | 4 + src/soc/amd/common/block/apob/apob_cache.c | 16 +- src/soc/amd/common/block/cpu/Kconfig | 9 +- src/soc/amd/common/block/cpu/mca/mca_bert.c | 2 +- src/soc/amd/common/block/cpu/mca/mcax_bert.c | 2 +- .../amd/common/block/cpu/noncar/Makefile.inc | 2 + src/soc/amd/common/block/cpu/noncar/cpu.c | 7 + .../amd/common/block/cpu/noncar/early_cache.c | 81 + .../cpu/noncar/memlayout_transfer_buffer.inc | 8 +- .../common/block/cpu/noncar/memlayout_x86.ld | 30 +- src/soc/amd/common/block/cpu/noncar/memmap.c | 2 +- src/soc/amd/common/block/cpu/smm/finalize.c | 2 + src/soc/amd/common/block/cpu/smm/smm_helper.c | 2 +- .../amd/common/block/cpu/update_microcode.c | 16 +- .../block/data_fabric/data_fabric_helper.c | 4 +- src/soc/amd/common/block/gpio/gpio.c | 11 +- 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.../amd/common/block/include/amdblocks/lpc.h | 17 +- .../amd/common/block/include/amdblocks/psp.h | 5 +- .../common/block/include/amdblocks/psp_efs.h | 4 +- .../amd/common/block/include/amdblocks/spi.h | 11 +- src/soc/amd/common/block/iommu/iommu.c | 5 +- src/soc/amd/common/block/lpc/Kconfig | 14 + src/soc/amd/common/block/lpc/espi_def.h | 54 + src/soc/amd/common/block/lpc/espi_util.c | 376 +- src/soc/amd/common/block/lpc/lpc.c | 5 +- src/soc/amd/common/block/lpc/lpc_util.c | 17 +- src/soc/amd/common/block/lpc/spi_dma.c | 16 +- src/soc/amd/common/block/pci/acpi_prt.c | 1 - src/soc/amd/common/block/pci/amd_pci_mmconf.c | 4 +- src/soc/amd/common/block/pci/amd_pci_util.c | 2 +- src/soc/amd/common/block/pci/pcie_gpp.c | 3 +- src/soc/amd/common/block/pm/pmlib.c | 2 +- src/soc/amd/common/block/psp/Kconfig | 16 + src/soc/amd/common/block/psp/Makefile.inc | 11 +- src/soc/amd/common/block/psp/efs_fmap_check.c | 9 + src/soc/amd/common/block/psp/psp.c | 23 - src/soc/amd/common/block/psp/psp_def.h | 21 +- src/soc/amd/common/block/psp/psp_gen1.c | 58 + src/soc/amd/common/block/psp/psp_gen2.c | 44 +- src/soc/amd/common/block/sata/sata.c | 2 - src/soc/amd/common/block/smbus/sm.c | 1 + src/soc/amd/common/block/smu/smu.c | 2 +- src/soc/amd/common/block/spi/Kconfig | 2 +- src/soc/amd/common/block/spi/fch_spi.c | 2 +- src/soc/amd/common/block/spi/fch_spi_ctrl.c | 53 +- src/soc/amd/common/block/spi/fch_spi_util.c | 3 + src/soc/amd/common/fsp/dmi.c | 9 +- src/soc/amd/common/fsp/fsp_reset.c | 2 +- src/soc/amd/common/fsp/fsp_validate.c | 41 +- src/soc/amd/common/fsp/pci/pci_routing_info.c | 2 +- src/soc/amd/common/pi/agesawrapper.c | 4 +- src/soc/amd/common/pi/amd_late_init.c | 7 +- src/soc/amd/common/pi/def_callouts.c | 2 +- src/soc/amd/common/pi/refcode_loader.c | 2 - src/soc/amd/common/pi/s3_resume.c | 2 +- src/soc/amd/common/psp_verstage/Kconfig | 16 + src/soc/amd/common/psp_verstage/fch.c | 24 +- .../psp_verstage/include/arch/smp/spinlock.h | 15 - .../psp_verstage/include/psp_verstage.h | 13 +- src/soc/amd/common/psp_verstage/printk.c | 9 +- .../amd/common/psp_verstage/psp_verstage.c | 163 +- .../amd/common/psp_verstage/vboot_crypto.c | 10 +- src/soc/amd/common/vboot/vboot_bootblock.c | 32 +- src/soc/amd/picasso/Kconfig | 61 +- src/soc/amd/picasso/Makefile.inc | 23 +- src/soc/amd/picasso/acpi.c | 10 +- src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 6 +- src/soc/amd/picasso/agesa_acpi.c | 4 +- src/soc/amd/picasso/bootblock.c | 81 +- src/soc/amd/picasso/chip.h | 1 + src/soc/amd/picasso/config.c | 2 +- src/soc/amd/picasso/cpu.c | 8 +- src/soc/amd/picasso/data_fabric.c | 12 +- src/soc/amd/picasso/early_fch.c | 1 - src/soc/amd/picasso/fch.c | 3 - src/soc/amd/picasso/fsp_m_params.c | 2 +- src/soc/amd/picasso/fsp_s_params.c | 1 - src/soc/amd/picasso/fw.cfg | 16 +- src/soc/amd/picasso/i2c.c | 28 +- src/soc/amd/picasso/include/soc/acpi.h | 3 + src/soc/amd/picasso/include/soc/data_fabric.h | 4 + src/soc/amd/picasso/include/soc/iomap.h | 9 +- src/soc/amd/picasso/include/soc/smi.h | 5 +- src/soc/amd/picasso/include/soc/southbridge.h | 45 - src/soc/amd/picasso/psp_verstage/Makefile.inc | 1 + src/soc/amd/picasso/psp_verstage/chipset.c | 11 +- src/soc/amd/picasso/psp_verstage/uart.c | 11 + src/soc/amd/picasso/root_complex.c | 4 +- src/soc/amd/picasso/smihandler.c | 3 +- src/soc/amd/sabrina/Kconfig | 480 ++ src/soc/amd/sabrina/Makefile.inc | 295 + src/soc/amd/sabrina/acpi.c | 365 + src/soc/amd/sabrina/acpi/globalnvs.asl | 22 + src/soc/amd/sabrina/acpi/mmio.asl | 383 + src/soc/amd/sabrina/acpi/pci0.asl | 86 + src/soc/amd/sabrina/acpi/pci_int_defs.asl | 71 + src/soc/amd/sabrina/acpi/rtc_workaround.asl | 28 + src/soc/amd/sabrina/acpi/soc.asl | 43 + src/soc/amd/sabrina/agesa_acpi.c | 28 + src/soc/amd/sabrina/aoac.c | 60 + src/soc/amd/sabrina/bootblock.c | 52 + src/soc/amd/sabrina/chip.c | 113 + src/soc/amd/sabrina/chip.h | 107 + src/soc/amd/sabrina/chipset.cb | 93 + src/soc/amd/sabrina/config.c | 14 + src/soc/amd/sabrina/cpu.c | 83 + src/soc/amd/sabrina/data_fabric.c | 153 + src/soc/amd/sabrina/early_fch.c | 82 + src/soc/amd/sabrina/fch.c | 233 + src/soc/amd/sabrina/fsp_m_params.c | 156 + src/soc/amd/sabrina/fsp_s_params.c | 43 + src/soc/amd/sabrina/fw.cfg | 42 + src/soc/amd/sabrina/gpio.c | 39 + src/soc/amd/sabrina/i2c.c | 62 + src/soc/amd/sabrina/include/soc/acpi.h | 23 + .../sabrina/include/soc/amd_pci_int_defs.h | 62 + src/soc/amd/sabrina/include/soc/aoac_defs.h | 23 + src/soc/amd/sabrina/include/soc/cpu.h | 8 + src/soc/amd/sabrina/include/soc/data_fabric.h | 17 + src/soc/amd/sabrina/include/soc/gpio.h | 324 + src/soc/amd/sabrina/include/soc/i2c.h | 28 + src/soc/amd/sabrina/include/soc/iomap.h | 57 + src/soc/amd/sabrina/include/soc/lpc.h | 24 + src/soc/amd/sabrina/include/soc/msr.h | 27 + src/soc/amd/sabrina/include/soc/nvs.h | 29 + src/soc/amd/sabrina/include/soc/pci_devs.h | 129 + .../include/soc/platform_descriptors.h | 19 + .../amd/sabrina/include/soc/psp_transfer.h | 60 + .../sabrina/include/soc/psp_verstage_addr.h | 25 + src/soc/amd/sabrina/include/soc/smi.h | 189 + src/soc/amd/sabrina/include/soc/smu.h | 23 + src/soc/amd/sabrina/include/soc/southbridge.h | 125 + src/soc/amd/sabrina/include/soc/uart.h | 11 + src/soc/amd/sabrina/mca.c | 56 + src/soc/amd/sabrina/preload.c | 13 + src/soc/amd/sabrina/psp_verstage/Makefile.inc | 17 + src/soc/amd/sabrina/psp_verstage/chipset.c | 46 + src/soc/amd/sabrina/psp_verstage/svc.c | 137 + src/soc/amd/sabrina/psp_verstage/svc.h | 59 + src/soc/amd/sabrina/psp_verstage/uart.c | 11 + src/soc/amd/sabrina/reset.c | 31 + src/soc/amd/sabrina/romstage.c | 36 + src/soc/amd/sabrina/root_complex.c | 229 + src/soc/amd/sabrina/smihandler.c | 154 + src/soc/amd/sabrina/smu.c | 17 + src/soc/amd/sabrina/uart.c | 127 + src/soc/amd/sabrina/xhci.c | 54 + src/soc/amd/stoneyridge/Kconfig | 9 +- src/soc/amd/stoneyridge/Makefile.inc | 16 +- src/soc/amd/stoneyridge/acpi.c | 106 +- src/soc/amd/stoneyridge/aoac.c | 39 + src/soc/amd/stoneyridge/chip.c | 1 - src/soc/amd/stoneyridge/chip.h | 1 + src/soc/amd/stoneyridge/cpu.c | 11 +- src/soc/amd/stoneyridge/early_fch.c | 173 + src/soc/amd/stoneyridge/fch.c | 199 + src/soc/amd/stoneyridge/fch_agesa.c | 60 + src/soc/amd/stoneyridge/i2c.c | 6 + src/soc/amd/stoneyridge/include/soc/acpi.h | 3 + src/soc/amd/stoneyridge/include/soc/iomap.h | 5 - .../amd/stoneyridge/include/soc/pci_devs.h | 55 +- src/soc/amd/stoneyridge/include/soc/smi.h | 5 +- .../amd/stoneyridge/include/soc/southbridge.h | 39 - src/soc/amd/stoneyridge/memmap.c | 1 - src/soc/amd/stoneyridge/northbridge.c | 3 +- src/soc/amd/stoneyridge/psp.c | 31 +- src/soc/amd/stoneyridge/romstage.c | 5 +- src/soc/amd/stoneyridge/smihandler.c | 1 + src/soc/amd/stoneyridge/southbridge.c | 486 -- src/soc/cavium/cn81xx/Kconfig | 4 +- src/soc/cavium/cn81xx/cpu.c | 4 +- src/soc/cavium/cn81xx/ecam0.c | 6 +- src/soc/example/min86/Kconfig | 2 +- src/soc/intel/alderlake/acpi/scs.asl | 76 + .../alderlake/bootblock/pmc_descriptor.c | 89 + src/soc/intel/alderlake/retimer.c | 32 + src/soc/intel/common/block/acpi/cpu_hybrid.c | 124 + src/soc/intel/common/block/acpi/sgx.c | 58 + .../block/include/intelblocks/cse_layout.h | 105 + .../block/include/intelblocks/p2sblib.h | 19 + src/soc/intel/common/block/p2sb/p2sblib.c | 92 + .../common/block/thermal/thermal_common.c | 29 + .../intel/common/block/thermal/thermal_pci.c | 40 + .../intel/common/block/thermal/thermal_pmc.c | 54 + src/soc/intel/tigerlake/pcie_rp.c | 88 + src/soc/intel/tigerlake/retimer.c | 32 + src/soc/mediatek/common/Kconfig | 19 +- src/soc/mediatek/common/dram_init.c | 1 - src/soc/mediatek/common/dsi.c | 3 +- src/soc/mediatek/common/flash_controller.c | 1 - src/soc/mediatek/common/i2c.c | 271 +- .../common/include/soc/devapc_common.h | 50 + src/soc/mediatek/common/include/soc/dpm.h | 1 - .../common/include/soc/dramc_param_common.h | 102 + src/soc/mediatek/common/include/soc/emi.h | 6 +- .../mediatek/common/include/soc/i2c_common.h | 23 +- src/soc/mediatek/common/include/soc/msdc.h | 10 +- .../common/include/soc/pmic_wrap_common.h | 9 +- .../mediatek/common/include/soc/regulator.h | 9 +- .../mediatek/common/include/soc/timer_v2.h | 13 + .../common/include/soc/tracker_common.h | 36 +- .../mediatek/common/include/soc/tracker_v1.h | 16 + .../mediatek/common/include/soc/tracker_v2.h | 31 + .../mediatek/common/include/soc/usb_common.h | 9 +- src/soc/mediatek/common/include/soc/wdt.h | 2 +- src/soc/mediatek/common/memory.c | 84 +- .../mmu_operations.c => common/mmu_cmops.c} | 4 +- src/soc/mediatek/common/pmic_wrap.c | 9 +- src/soc/mediatek/common/pmif_spi.c | 1 - src/soc/mediatek/common/spm.c | 5 +- src/soc/mediatek/common/tracker.c | 86 +- src/soc/mediatek/common/tracker_v1.c | 21 + src/soc/mediatek/common/tracker_v2.c | 82 + src/soc/mediatek/common/usb.c | 11 +- src/soc/mediatek/common/wdt.c | 13 +- src/soc/mediatek/mt8173/da9212.c | 4 +- src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 2 +- .../mt8173/dramc_pi_calibration_api.c | 2 +- src/soc/mediatek/mt8173/i2c.c | 6 +- src/soc/mediatek/mt8173/include/soc/i2c.h | 5 + src/soc/mediatek/mt8173/mt6311.c | 4 +- src/soc/mediatek/mt8183/i2c.c | 10 +- src/soc/mediatek/mt8183/include/soc/i2c.h | 5 + src/soc/mediatek/mt8186/Kconfig | 41 + src/soc/mediatek/mt8186/Makefile.inc | 99 + src/soc/mediatek/mt8186/bootblock.c | 19 + src/soc/mediatek/mt8186/ddp.c | 164 + src/soc/mediatek/mt8186/devapc.c | 1325 +++ src/soc/mediatek/mt8186/emi.c | 18 + src/soc/mediatek/mt8186/gic.c | 20 + src/soc/mediatek/mt8186/gpio.c | 97 + src/soc/mediatek/mt8186/i2c.c | 142 + .../mediatek/mt8186/include/soc/addressmap.h | 93 + src/soc/mediatek/mt8186/include/soc/auxadc.h | 28 + src/soc/mediatek/mt8186/include/soc/ddp.h | 260 + src/soc/mediatek/mt8186/include/soc/devapc.h | 93 + src/soc/mediatek/mt8186/include/soc/dfd.h | 12 + .../mediatek/mt8186/include/soc/dramc_param.h | 86 + .../mediatek/mt8186/include/soc/dramc_soc.h | 56 + src/soc/mediatek/mt8186/include/soc/dsi.h | 60 + src/soc/mediatek/mt8186/include/soc/efuse.h | 17 + src/soc/mediatek/mt8186/include/soc/gic.h | 13 + src/soc/mediatek/mt8186/include/soc/gpio.h | 626 ++ .../mediatek/mt8186/include/soc/gpio_base.h | 24 + src/soc/mediatek/mt8186/include/soc/i2c.h | 70 + .../mediatek/mt8186/include/soc/infracfg.h | 547 ++ src/soc/mediatek/mt8186/include/soc/mcucfg.h | 947 ++ .../mediatek/mt8186/include/soc/memlayout.ld | 62 + src/soc/mediatek/mt8186/include/soc/mt6366.h | 87 + src/soc/mediatek/mt8186/include/soc/pll.h | 525 ++ .../mediatek/mt8186/include/soc/pmic_wrap.h | 440 + src/soc/mediatek/mt8186/include/soc/rtc.h | 240 + src/soc/mediatek/mt8186/include/soc/spi.h | 36 + src/soc/mediatek/mt8186/include/soc/spm.h | 874 ++ src/soc/mediatek/mt8186/include/soc/symbols.h | 10 + src/soc/mediatek/mt8186/include/soc/timer.h | 13 + src/soc/mediatek/mt8186/include/soc/tracker.h | 8 + src/soc/mediatek/mt8186/include/soc/usb.h | 29 + src/soc/mediatek/mt8186/msdc.c | 107 + src/soc/mediatek/mt8186/mt6366.c | 959 +++ src/soc/mediatek/mt8186/mtcmos.c | 23 + src/soc/mediatek/mt8186/pll.c | 574 ++ src/soc/mediatek/mt8186/pmic_wrap.c | 330 + src/soc/mediatek/mt8186/rtc.c | 361 + src/soc/mediatek/mt8186/soc.c | 46 + src/soc/mediatek/mt8186/spi.c | 187 + src/soc/mediatek/mt8186/spm.c | 684 ++ src/soc/mediatek/mt8186/timer.c | 16 + src/soc/mediatek/mt8186/usb.c | 16 + src/soc/mediatek/mt8186/wdt.c | 20 + src/soc/mediatek/mt8192/Kconfig | 2 +- src/soc/mediatek/mt8192/Makefile.inc | 8 +- src/soc/mediatek/mt8192/bootblock.c | 2 + src/soc/mediatek/mt8192/i2c.c | 9 +- .../mediatek/mt8192/include/soc/dramc_param.h | 74 +- src/soc/mediatek/mt8192/include/soc/i2c.h | 5 + src/soc/mediatek/mt8192/include/soc/mcucfg.h | 2 +- src/soc/mediatek/mt8192/include/soc/spm.h | 1 - src/soc/mediatek/mt8192/include/soc/tracker.h | 8 + src/soc/mediatek/mt8192/msdc.c | 90 + src/soc/mediatek/mt8192/pll.c | 20 +- src/soc/mediatek/mt8192/soc.c | 2 - src/soc/mediatek/mt8192/spm.c | 1 - src/soc/mediatek/mt8195/Kconfig | 3 +- src/soc/mediatek/mt8195/Makefile.inc | 19 +- src/soc/mediatek/mt8195/apusys.c | 31 + src/soc/mediatek/mt8195/apusys_devapc.c | 287 + src/soc/mediatek/mt8195/bootblock.c | 2 + src/soc/mediatek/mt8195/devapc.c | 375 +- src/soc/mediatek/mt8195/dp_intf.c | 3 - src/soc/mediatek/mt8195/dpm_4ch.c | 2 +- src/soc/mediatek/mt8195/dptx.c | 3 +- src/soc/mediatek/mt8195/dptx_hal.c | 6 +- src/soc/mediatek/mt8195/i2c.c | 255 +- .../mediatek/mt8195/include/soc/addressmap.h | 6 +- src/soc/mediatek/mt8195/include/soc/apusys.h | 31 + .../mt8195/include/soc/apusys_devapc.h | 39 + src/soc/mediatek/mt8195/include/soc/devapc.h | 66 +- .../mediatek/mt8195/include/soc/dramc_param.h | 74 +- src/soc/mediatek/mt8195/include/soc/i2c.h | 4 + src/soc/mediatek/mt8195/include/soc/mcucfg.h | 2 +- src/soc/mediatek/mt8195/include/soc/spm.h | 1 - src/soc/mediatek/mt8195/include/soc/timer.h | 12 - src/soc/mediatek/mt8195/include/soc/tracker.h | 8 + src/soc/mediatek/mt8195/include/soc/usb.h | 17 +- src/soc/mediatek/mt8195/mmu_operations.c | 38 - src/soc/mediatek/mt8195/msdc.c | 108 + src/soc/mediatek/mt8195/mt6360.c | 1 - src/soc/mediatek/mt8195/mt6691.c | 2 +- src/soc/mediatek/mt8195/pll.c | 20 +- src/soc/mediatek/mt8195/soc.c | 4 +- src/soc/mediatek/mt8195/spm.c | 1 - src/soc/mediatek/mt8195/usb.c | 28 + src/soc/mediatek/mt8195/wdt.c | 12 + src/soc/nvidia/tegra/usb.c | 2 +- src/soc/nvidia/tegra124/sor.c | 10 +- src/soc/nvidia/tegra124/verstage.c | 2 +- src/soc/nvidia/tegra210/dp.c | 2 +- src/soc/nvidia/tegra210/dsi.c | 2 +- src/soc/nvidia/tegra210/funitcfg.c | 2 +- .../nvidia/tegra210/include/soc/verstage.h | 8 - src/soc/nvidia/tegra210/sor.c | 9 +- src/soc/qualcomm/common/clock.c | 10 +- src/soc/qualcomm/common/gpio.c | 4 +- .../qualcomm/common/include/soc/gpio_common.h | 2 + .../common/include/soc/symbols_common.h | 2 + .../common/include/soc/usb/qmp_usb_phy.h | 31 + .../common/include/soc/usb/qusb_phy.h | 96 + .../common/include/soc/usb/snps_usb_phy.h | 42 + .../common/include/soc/usb/usb_common.h | 35 + .../usb.c => common/usb/qmpv3_usb_phy.c} | 348 +- src/soc/qualcomm/common/usb/qmpv4_usb_phy.c | 411 + src/soc/qualcomm/common/usb/qusb_phy.c | 139 + src/soc/qualcomm/common/usb/snps_usb_phy.c | 86 + src/soc/qualcomm/common/usb/usb.c | 141 + .../qualcomm/ipq40xx/include/soc/verstage.h | 8 - src/soc/qualcomm/ipq40xx/spi.c | 2 - src/soc/qualcomm/sc7180/Makefile.inc | 6 +- src/soc/qualcomm/sc7180/clock.c | 1 - src/soc/qualcomm/sc7180/display/dsi.c | 19 +- src/soc/qualcomm/sc7180/display/dsi_phy_pll.c | 1 - src/soc/qualcomm/sc7180/display/mdss.c | 1 - .../sc7180/include/soc/display/mdssreg.h | 1 - src/soc/qualcomm/sc7180/include/soc/usb.h | 82 - src/soc/qualcomm/sc7180/memlayout.ld | 5 +- src/soc/qualcomm/sc7180/qcom_qup_se.c | 1 - src/soc/qualcomm/sc7280/Kconfig | 1 + src/soc/qualcomm/sc7280/Makefile.inc | 35 + src/soc/qualcomm/sc7280/carve_out.c | 22 + src/soc/qualcomm/sc7280/clock.c | 1 - src/soc/qualcomm/sc7280/cpucp_load_reset.c | 34 + .../qualcomm/sc7280/include/soc/addressmap.h | 13 + src/soc/qualcomm/sc7280/include/soc/cpucp.h | 45 + src/soc/qualcomm/sc7280/memlayout.ld | 4 +- src/soc/qualcomm/sc7280/soc.c | 13 +- src/soc/rockchip/common/rk808.c | 2 +- src/soc/rockchip/rk3288/crypto.c | 2 +- src/soc/rockchip/rk3288/sdram.c | 5 +- src/soc/rockchip/rk3399/display.c | 5 +- src/soc/samsung/exynos5250/usb.c | 6 +- src/soc/samsung/exynos5420/dp.c | 10 +- src/soc/samsung/exynos5420/dp_lowlevel.c | 16 - src/soc/samsung/exynos5420/usb.c | 12 +- src/soc/ti/am335x/mmc.c | 2 +- src/southbridge/amd/agesa/hudson/fadt.c | 3 +- src/southbridge/amd/agesa/hudson/hudson.c | 6 +- src/southbridge/amd/agesa/hudson/lpc.c | 4 +- src/southbridge/amd/agesa/hudson/reset.c | 8 +- src/southbridge/amd/agesa/hudson/smbus.c | 19 +- src/southbridge/amd/agesa/hudson/smi_util.c | 2 +- src/southbridge/amd/cimx/sb800/acpi/fch.asl | 189 +- src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 7 - .../amd/cimx/sb800/acpi/misc_io.asl | 171 + .../amd/cimx/sb800/amd_pci_int_defs.h | 6 +- src/southbridge/amd/cimx/sb800/cfg.c | 1 + src/southbridge/amd/cimx/sb800/fadt.c | 3 +- src/southbridge/amd/cimx/sb800/fan.c | 2 - src/southbridge/amd/cimx/sb800/lpc.c | 4 +- src/southbridge/amd/cimx/sb800/reset.c | 2 +- src/southbridge/amd/cimx/sb800/smbus.c | 39 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/common/amd_pci_util.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 5 +- src/southbridge/amd/pi/hudson/fadt.c | 3 +- src/southbridge/amd/pi/hudson/lpc.c | 6 +- src/southbridge/amd/pi/hudson/reset.c | 8 +- src/southbridge/amd/pi/hudson/sm.c | 1 + src/southbridge/amd/pi/hudson/smbus.c | 19 +- src/southbridge/amd/pi/hudson/smi_util.c | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 1 - src/southbridge/intel/bd82x6x/acpi/lpc.asl | 10 +- src/southbridge/intel/bd82x6x/acpi/usb.asl | 2 +- src/southbridge/intel/bd82x6x/azalia.c | 118 +- src/southbridge/intel/bd82x6x/chip.h | 4 +- src/southbridge/intel/bd82x6x/early_me.c | 5 +- src/southbridge/intel/bd82x6x/early_me_mrc.c | 8 +- src/southbridge/intel/bd82x6x/me.c | 2 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/me_common.c | 2 +- src/southbridge/intel/bd82x6x/me_smm.c | 1 - src/southbridge/intel/bd82x6x/pch.c | 2 +- src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/bd82x6x/usb_ehci.c | 2 +- src/southbridge/intel/common/acpi_pirq_gen.c | 1 - src/southbridge/intel/common/firmware/Kconfig | 2 +- src/southbridge/intel/common/hpet.c | 4 +- src/southbridge/intel/common/rcba_pirq.c | 2 +- src/southbridge/intel/common/spi.c | 6 +- src/southbridge/intel/i82371eb/acpi/intx.asl | 2 +- src/southbridge/intel/i82371eb/acpi/pirq.asl | 2 +- src/southbridge/intel/i82371eb/bootblock.c | 3 +- src/southbridge/intel/i82371eb/early_pm.c | 3 +- src/southbridge/intel/i82371eb/early_smbus.c | 3 +- src/southbridge/intel/i82801dx/Makefile.inc | 6 +- src/southbridge/intel/i82801dx/lpc.c | 16 +- src/southbridge/intel/i82801gx/Kconfig | 1 - src/southbridge/intel/i82801gx/acpi/lpc.asl | 10 +- src/southbridge/intel/i82801gx/azalia.c | 107 +- src/southbridge/intel/i82801gx/chip.h | 4 +- src/southbridge/intel/i82801gx/early_init.c | 1 - src/southbridge/intel/i82801gx/pcie.c | 4 +- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801ix/Kconfig | 1 - src/southbridge/intel/i82801ix/Makefile.inc | 6 +- src/southbridge/intel/i82801ix/acpi/lpc.asl | 10 +- src/southbridge/intel/i82801ix/azalia.c | 118 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/i82801jx/Kconfig | 1 - src/southbridge/intel/i82801jx/acpi/lpc.asl | 10 +- src/southbridge/intel/i82801jx/azalia.c | 118 +- src/southbridge/intel/i82870/ioapic.c | 1 - src/southbridge/intel/ibexpeak/Kconfig | 1 - src/southbridge/intel/ibexpeak/Makefile.inc | 1 + src/southbridge/intel/ibexpeak/azalia.c | 159 +- src/southbridge/intel/ibexpeak/early_pch.c | 6 + src/southbridge/intel/ibexpeak/lpc.c | 10 +- src/southbridge/intel/ibexpeak/me.c | 2 +- src/southbridge/intel/ibexpeak/me.h | 2 + src/southbridge/intel/ibexpeak/pch.h | 1 + src/southbridge/intel/ibexpeak/sata.c | 8 +- .../intel/ibexpeak/setup_heci_uma.c | 229 + src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/ibexpeak/thermal.c | 2 +- src/southbridge/intel/ibexpeak/usb_ehci.c | 2 +- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/acpi/lpc.asl | 10 +- src/southbridge/intel/lynxpoint/azalia.c | 20 +- src/southbridge/intel/lynxpoint/chip.h | 2 +- src/southbridge/intel/lynxpoint/early_me.c | 49 +- src/southbridge/intel/lynxpoint/hda_verb.c | 110 - src/southbridge/intel/lynxpoint/hda_verb.h | 2 - src/southbridge/intel/lynxpoint/me.c | 185 +- src/southbridge/intel/lynxpoint/me.h | 278 +- src/southbridge/intel/lynxpoint/me_status.c | 52 +- src/southbridge/intel/lynxpoint/pch.c | 1 - src/southbridge/intel/lynxpoint/pcie.c | 4 +- src/southbridge/intel/lynxpoint/serialio.c | 4 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/superio/fintek/f71808a/f71808a_hwm.c | 2 +- src/superio/fintek/f71869ad/f71869ad_hwm.c | 2 +- src/superio/fintek/f81866d/f81866d_hwm.c | 2 +- src/superio/fintek/f81866d/f81866d_uart.c | 2 +- src/superio/ite/it8613e/superio.c | 2 +- src/superio/ite/it8623e/superio.c | 2 +- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8720f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 2 +- src/superio/ite/it8772f/superio.c | 4 +- src/superio/ite/it8783ef/superio.c | 2 +- src/superio/ite/it8786e/superio.c | 2 +- src/superio/nuvoton/nct5104d/superio.c | 4 +- src/superio/nuvoton/nct5572d/superio.c | 1 - src/superio/nuvoton/npcd378/superio.c | 2 +- src/superio/smsc/lpc47n207/early_serial.c | 2 +- src/superio/smsc/lpc47n217/superio.c | 4 +- src/superio/smsc/lpc47n227/superio.c | 4 +- src/superio/smsc/sch5545/sch5545_early_init.c | 7 + src/superio/smsc/sch5545/superio.c | 23 +- src/superio/winbond/w83627hf/acpi/superio.asl | 46 +- src/superio/winbond/w83667hg-a/superio.c | 1 - src/superio/winbond/w83977tf/acpi/superio.asl | 4 +- .../amd/agesa/f14/Config/PlatformInstall.h | 4 +- .../amd/agesa/f15tn/Config/PlatformInstall.h | 4 +- .../Proc/CPU/Family/0x15/cpuF15MmioMap.c | 2 +- .../amd/agesa/f16kb/Config/PlatformInstall.h | 4 +- .../Proc/CPU/Family/0x16/cpuF16MmioMap.c | 2 +- src/vendorcode/amd/cimx/sb800/OEM.h | 2 +- src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 15 +- src/vendorcode/amd/fsp/cezanne/dmi_info.h | 3 + .../include/bl_uapp/bl_syscall_public.h | 30 + src/vendorcode/amd/fsp/picasso/FspmUpd.h | 5 + src/vendorcode/amd/fsp/sabrina/FspGuids.h | 20 + src/vendorcode/amd/fsp/sabrina/FspUpd.h | 22 + src/vendorcode/amd/fsp/sabrina/FspUsb.h | 56 + src/vendorcode/amd/fsp/sabrina/FspmUpd.h | 115 + src/vendorcode/amd/fsp/sabrina/FspsUpd.h | 26 + .../amd/fsp/sabrina/bl_uapp/bl_uapp_end.S | 44 + .../fsp/sabrina/bl_uapp/bl_uapp_header.inc | 64 + .../amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S | 71 + src/vendorcode/amd/fsp/sabrina/dmi_info.h | 239 + src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h | 58 + .../include/bl_uapp/bl_errorcodes_public.h | 37 + .../include/bl_uapp/bl_syscall_public.h | 319 + .../amd/fsp/sabrina/platform_descriptors.h | 218 + .../eltan/security/verified_boot/Makefile.inc | 5 + .../security/verified_boot/vboot_check.c | 8 +- src/vendorcode/google/chromeos/acpi.c | 5 - .../google/chromeos/acpi/chromeos.asl | 2 + src/vendorcode/google/chromeos/acpi/gnvs.asl | 4 +- src/vendorcode/google/chromeos/chromeos.h | 15 +- .../google/chromeos/cr50_enable_update.c | 13 +- src/vendorcode/google/chromeos/elog.c | 9 +- src/vendorcode/google/chromeos/gnvs.c | 7 + src/vendorcode/google/chromeos/gnvs.h | 2 - src/vendorcode/google/chromeos/sar.c | 24 +- .../google/chromeos/vpd_calibration.c | 1 + src/vendorcode/intel/Kconfig | 20 +- src/vendorcode/intel/Makefile.inc | 5 + .../IntelFsp2Pkg/Include/FspEas.h | 18 + .../IntelFsp2Pkg/Include/FspEas/FspApi.h | 485 ++ .../IntelFsp2Pkg/Include/FspGlobalData.h | 78 + .../IntelFsp2Pkg/Include/FspMeasurePointId.h | 56 + .../IntelFsp2Pkg/Include/FspStatusCode.h | 40 + .../IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 235 + .../Include/Guid/FspNonVolatileStorageHob2.h | 24 + .../IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h | 17 + .../Include/Library/CacheAsRamLib.h | 24 + .../IntelFsp2Pkg/Include/Library/CacheLib.h | 56 + .../Include/Library/DebugDeviceLib.h | 23 + .../Include/Library/FspCommonLib.h | 308 + .../Include/Library/FspPlatformLib.h | 125 + .../Include/Library/FspSecPlatformLib.h | 96 + .../Include/Library/FspSwitchStackLib.h | 55 + .../Include/Ppi/FspmArchConfigPpi.h | 47 + .../IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h | 52 + .../MdePkg/Include/AArch64/ProcessorBind.h | 207 + .../MdePkg/Include/Arm/ProcessorBind.h | 240 + .../edk2-stable202111/MdePkg/Include/Base.h | 1326 +++ .../MdePkg/Include/Ebc/ProcessorBind.h | 156 + .../MdePkg/Include/Guid/Acpi.h | 40 + .../MdePkg/Include/Guid/Apriori.h | 24 + .../MdePkg/Include/Guid/AprioriFileName.h | 38 + .../MdePkg/Include/Guid/Btt.h | 222 + .../MdePkg/Include/Guid/CapsuleReport.h | 128 + .../MdePkg/Include/Guid/Cper.h | 1252 +++ .../MdePkg/Include/Guid/DebugImageInfoTable.h | 74 + .../MdePkg/Include/Guid/DxeServices.h | 22 + .../MdePkg/Include/Guid/EventGroup.h | 46 + .../MdePkg/Include/Guid/EventLegacyBios.h | 22 + .../MdePkg/Include/Guid/FileInfo.h | 65 + .../MdePkg/Include/Guid/FileSystemInfo.h | 57 + .../Include/Guid/FileSystemVolumeLabelInfo.h | 31 + .../Include/Guid/FirmwareContentsSigned.h | 20 + .../MdePkg/Include/Guid/FirmwareFileSystem2.h | 34 + .../MdePkg/Include/Guid/FirmwareFileSystem3.h | 24 + .../MdePkg/Include/Guid/FmpCapsule.h | 101 + .../MdePkg/Include/Guid/GlobalVariable.h | 186 + .../MdePkg/Include/Guid/Gpt.h | 37 + .../MdePkg/Include/Guid/GraphicsInfoHob.h | 45 + .../Include/Guid/HardwareErrorVariable.h | 22 + .../Include/Guid/HiiFormMapMethodGuid.h | 19 + .../MdePkg/Include/Guid/HiiKeyBoardLayout.h | 21 + .../Include/Guid/HiiPlatformSetupFormset.h | 33 + .../MdePkg/Include/Guid/HobList.h | 24 + .../MdePkg/Include/Guid/ImageAuthentication.h | 346 + .../MdePkg/Include/Guid/JsonCapsule.h | 98 + .../MdePkg/Include/Guid/LinuxEfiInitrdMedia.h | 30 + .../MdePkg/Include/Guid/MdePkgTokenSpace.h | 19 + .../MdePkg/Include/Guid/MemoryAllocationHob.h | 28 + .../Include/Guid/MemoryAttributesTable.h | 28 + .../Include/Guid/MemoryOverwriteControl.h | 70 + .../MdePkg/Include/Guid/Mps.h | 29 + .../MdePkg/Include/Guid/PcAnsi.h | 52 + .../MdePkg/Include/Guid/RtPropertiesTable.h | 69 + .../MdePkg/Include/Guid/SmBios.h | 32 + .../MdePkg/Include/Guid/SmramMemoryReserve.h | 45 + .../Include/Guid/StatusCodeDataTypeId.h | 803 ++ .../MdePkg/Include/Guid/SystemResourceTable.h | 133 + .../MdePkg/Include/Guid/VectorHandoffTable.h | 27 + .../MdePkg/Include/Guid/WinCertificate.h | 122 + .../MdePkg/Include/Ia32/Nasm.inc | 72 + .../MdePkg/Include/Ia32/ProcessorBind.h | 322 + .../MdePkg/Include/IndustryStandard/Acpi.h | 16 + .../MdePkg/Include/IndustryStandard/Acpi10.h | 666 ++ .../MdePkg/Include/IndustryStandard/Acpi20.h | 539 ++ .../MdePkg/Include/IndustryStandard/Acpi30.h | 723 ++ .../MdePkg/Include/IndustryStandard/Acpi40.h | 1303 +++ .../MdePkg/Include/IndustryStandard/Acpi50.h | 2119 +++++ .../MdePkg/Include/IndustryStandard/Acpi51.h | 2139 +++++ .../MdePkg/Include/IndustryStandard/Acpi60.h | 2392 +++++ .../MdePkg/Include/IndustryStandard/Acpi61.h | 2424 ++++++ .../MdePkg/Include/IndustryStandard/Acpi62.h | 2960 +++++++ .../MdePkg/Include/IndustryStandard/Acpi63.h | 2960 +++++++ .../MdePkg/Include/IndustryStandard/Acpi64.h | 3148 +++++++ .../MdePkg/Include/IndustryStandard/AcpiAml.h | 184 + .../AlertStandardFormatTable.h | 140 + .../IndustryStandard/ArmErrorSourceTable.h | 357 + .../MdePkg/Include/IndustryStandard/Atapi.h | 851 ++ .../Include/IndustryStandard/Bluetooth.h | 56 + .../MdePkg/Include/IndustryStandard/Bmp.h | 42 + .../MdePkg/Include/IndustryStandard/Cxl.h | 22 + .../MdePkg/Include/IndustryStandard/Cxl11.h | 659 ++ .../IndustryStandard/DebugPort2Table.h | 75 + .../Include/IndustryStandard/DebugPortTable.h | 44 + .../MdePkg/Include/IndustryStandard/Dhcp.h | 283 + .../DmaRemappingReportingTable.h | 291 + .../Include/IndustryStandard/ElTorito.h | 141 + .../MdePkg/Include/IndustryStandard/Emmc.h | 291 + .../HighPrecisionEventTimerTable.h | 62 + .../MdePkg/Include/IndustryStandard/Hsti.h | 76 + .../MdePkg/Include/IndustryStandard/Http11.h | 252 + .../IndustryStandard/IScsiBootFirmwareTable.h | 161 + .../IndustryStandard/IoRemappingTable.h | 203 + .../MdePkg/Include/IndustryStandard/Ipmi.h | 55 + .../IpmiFruInformationStorage.h | 86 + .../Include/IndustryStandard/IpmiNetFnApp.h | 1029 +++ .../IndustryStandard/IpmiNetFnBridge.h | 237 + .../IndustryStandard/IpmiNetFnChassis.h | 462 + .../IndustryStandard/IpmiNetFnFirmware.h | 38 + .../IpmiNetFnGroupExtension.h | 20 + .../IndustryStandard/IpmiNetFnSensorEvent.h | 46 + .../IndustryStandard/IpmiNetFnStorage.h | 783 ++ .../IndustryStandard/IpmiNetFnTransport.h | 885 ++ .../IndustryStandard/LegacyBiosMpTable.h | 288 + .../IndustryStandard/LowPowerIdleTable.h | 76 + .../MdePkg/Include/IndustryStandard/Mbr.h | 54 + ...emoryMappedConfigurationSpaceAccessTable.h | 49 + .../MemoryOverwriteRequestControlLock.h | 37 + .../MdePkg/Include/IndustryStandard/Nvme.h | 942 ++ .../MdePkg/Include/IndustryStandard/Pci.h | 15 + .../MdePkg/Include/IndustryStandard/Pci22.h | 861 ++ .../MdePkg/Include/IndustryStandard/Pci23.h | 127 + .../MdePkg/Include/IndustryStandard/Pci30.h | 73 + .../Include/IndustryStandard/PciCodeId.h | 94 + .../Include/IndustryStandard/PciExpress21.h | 715 ++ .../Include/IndustryStandard/PciExpress30.h | 51 + .../Include/IndustryStandard/PciExpress31.h | 72 + .../Include/IndustryStandard/PciExpress40.h | 111 + .../Include/IndustryStandard/PciExpress50.h | 136 + .../MdePkg/Include/IndustryStandard/PeImage.h | 762 ++ .../MdePkg/Include/IndustryStandard/Scsi.h | 426 + .../MdePkg/Include/IndustryStandard/Sd.h | 175 + .../Include/IndustryStandard/SdramSpd.h | 68 + .../Include/IndustryStandard/SdramSpdDdr3.h | 763 ++ .../Include/IndustryStandard/SdramSpdDdr4.h | 952 ++ .../Include/IndustryStandard/SdramSpdLpDdr.h | 468 + .../SerialPortConsoleRedirectionTable.h | 177 + ...ServiceProcessorManagementInterfaceTable.h | 98 + .../MdePkg/Include/IndustryStandard/SmBios.h | 2724 ++++++ .../MdePkg/Include/IndustryStandard/SmBus.h | 75 + .../MdePkg/Include/IndustryStandard/Spdm.h | 320 + .../IndustryStandard/TcgPhysicalPresence.h | 123 + .../Include/IndustryStandard/TcgStorageCore.h | 395 + .../Include/IndustryStandard/TcgStorageOpal.h | 243 + .../Include/IndustryStandard/TcpaAcpi.h | 52 + .../MdePkg/Include/IndustryStandard/Tls1.h | 101 + .../MdePkg/Include/IndustryStandard/Tpm12.h | 2167 +++++ .../MdePkg/Include/IndustryStandard/Tpm20.h | 1814 ++++ .../Include/IndustryStandard/Tpm2Acpi.h | 66 + .../MdePkg/Include/IndustryStandard/TpmPtp.h | 517 ++ .../MdePkg/Include/IndustryStandard/TpmTis.h | 181 + .../MdePkg/Include/IndustryStandard/Udf.h | 141 + .../IndustryStandard/UefiTcgPlatform.h | 500 ++ .../MdePkg/Include/IndustryStandard/Usb.h | 380 + .../IndustryStandard/WatchdogActionTable.h | 90 + .../IndustryStandard/WatchdogResourceTable.h | 50 + .../WindowsSmmSecurityMitigationTable.h | 33 + .../IndustryStandard/WindowsUxCapsule.h | 41 + .../MdePkg/Include/Library/BaseLib.h | 7656 +++++++++++++++++ .../MdePkg/Include/Library/BaseMemoryLib.h | 483 ++ .../Include/Library/CacheMaintenanceLib.h | 206 + .../MdePkg/Include/Library/CpuLib.h | 45 + .../MdePkg/Include/Library/DebugLib.h | 638 ++ .../Include/Library/DebugPrintErrorLevelLib.h | 37 + .../MdePkg/Include/Library/DevicePathLib.h | 561 ++ .../Include/Library/DxeCoreEntryPoint.h | 93 + .../MdePkg/Include/Library/DxeServicesLib.h | 324 + .../Include/Library/DxeServicesTableLib.h | 28 + .../Include/Library/ExtractGuidedSectionLib.h | 278 + .../MdePkg/Include/Library/FileHandleLib.h | 501 ++ .../MdePkg/Include/Library/HobLib.h | 560 ++ .../MdePkg/Include/Library/HstiLib.h | 152 + .../MdePkg/Include/Library/IoLib.h | 2809 ++++++ .../Include/Library/MemoryAllocationLib.h | 487 ++ .../Include/Library/MmServicesTableLib.h | 19 + .../Include/Library/MmUnblockMemoryLib.h | 44 + .../Include/Library/OrderedCollectionLib.h | 419 + .../MdePkg/Include/Library/PcdLib.h | 1734 ++++ .../MdePkg/Include/Library/PciCf8Lib.h | 1088 +++ .../MdePkg/Include/Library/PciExpressLib.h | 1057 +++ .../MdePkg/Include/Library/PciLib.h | 1056 +++ .../Include/Library/PciSegmentInfoLib.h | 36 + .../MdePkg/Include/Library/PciSegmentLib.h | 1043 +++ .../Include/Library/PeCoffExtraActionLib.h | 47 + .../Include/Library/PeCoffGetEntryPointLib.h | 116 + .../MdePkg/Include/Library/PeCoffLib.h | 386 + .../Include/Library/PeiCoreEntryPoint.h | 132 + .../MdePkg/Include/Library/PeiServicesLib.h | 559 ++ .../Library/PeiServicesTablePointerLib.h | 68 + .../MdePkg/Include/Library/PeimEntryPoint.h | 103 + .../MdePkg/Include/Library/PerformanceLib.h | 766 ++ .../MdePkg/Include/Library/PostCodeLib.h | 144 + .../MdePkg/Include/Library/PrintLib.h | 935 ++ .../Include/Library/RegisterFilterLib.h | 243 + .../Include/Library/ReportStatusCodeLib.h | 486 ++ .../Include/Library/ResourcePublicationLib.h | 36 + .../MdePkg/Include/Library/RngLib.h | 80 + .../MdePkg/Include/Library/S3BootScriptLib.h | 595 ++ .../MdePkg/Include/Library/S3IoLib.h | 2670 ++++++ .../MdePkg/Include/Library/S3PciLib.h | 1045 +++ .../MdePkg/Include/Library/S3PciSegmentLib.h | 1031 +++ .../MdePkg/Include/Library/S3SmbusLib.h | 448 + .../MdePkg/Include/Library/S3StallLib.h | 32 + .../MdePkg/Include/Library/SafeIntLib.h | 3013 +++++++ .../MdePkg/Include/Library/SerialPortLib.h | 174 + .../MdePkg/Include/Library/SmbusLib.h | 491 ++ .../Include/Library/SmiHandlerProfileLib.h | 81 + .../MdePkg/Include/Library/SmmIoLib.h | 36 + .../MdePkg/Include/Library/SmmLib.h | 83 + .../MdePkg/Include/Library/SmmMemLib.h | 132 + .../Include/Library/SmmPeriodicSmiLib.h | 178 + .../Include/Library/SmmServicesTableLib.h | 37 + .../Library/StandaloneMmDriverEntryPoint.h | 150 + .../Include/Library/SynchronizationLib.h | 287 + .../MdePkg/Include/Library/TimerLib.h | 108 + .../Library/UefiApplicationEntryPoint.h | 148 + .../Library/UefiBootServicesTableLib.h | 28 + .../Include/Library/UefiDecompressLib.h | 102 + .../Include/Library/UefiDriverEntryPoint.h | 189 + .../MdePkg/Include/Library/UefiLib.h | 1761 ++++ .../MdePkg/Include/Library/UefiRuntimeLib.h | 581 ++ .../Library/UefiRuntimeServicesTableLib.h | 26 + .../MdePkg/Include/Library/UefiScsiLib.h | 1303 +++ .../MdePkg/Include/Library/UefiUsbLib.h | 557 ++ .../MdePkg/Include/Library/UnitTestLib.h | 844 ++ .../MdePkg/Include/Pi/PiBootMode.h | 36 + .../MdePkg/Include/Pi/PiDependency.h | 41 + .../MdePkg/Include/Pi/PiDxeCis.h | 738 ++ .../MdePkg/Include/Pi/PiFirmwareFile.h | 509 ++ .../MdePkg/Include/Pi/PiFirmwareVolume.h | 247 + .../MdePkg/Include/Pi/PiHob.h | 512 ++ .../MdePkg/Include/Pi/PiI2c.h | 301 + .../MdePkg/Include/Pi/PiMmCis.h | 345 + .../MdePkg/Include/Pi/PiMultiPhase.h | 211 + .../MdePkg/Include/Pi/PiPeiCis.h | 1061 +++ .../MdePkg/Include/Pi/PiS3BootScript.h | 53 + .../MdePkg/Include/Pi/PiSmmCis.h | 200 + .../MdePkg/Include/Pi/PiStatusCode.h | 1207 +++ .../edk2-stable202111/MdePkg/Include/PiDxe.h | 19 + .../edk2-stable202111/MdePkg/Include/PiMm.h | 19 + .../edk2-stable202111/MdePkg/Include/PiPei.h | 21 + .../edk2-stable202111/MdePkg/Include/PiSmm.h | 19 + .../MdePkg/Include/Ppi/BlockIo.h | 232 + .../MdePkg/Include/Ppi/BlockIo2.h | 217 + .../MdePkg/Include/Ppi/BootInRecoveryMode.h | 24 + .../MdePkg/Include/Ppi/Capsule.h | 130 + .../MdePkg/Include/Ppi/CpuIo.h | 422 + .../MdePkg/Include/Ppi/Decompress.h | 68 + .../MdePkg/Include/Ppi/DelayedDispatch.h | 85 + .../MdePkg/Include/Ppi/DeviceRecoveryModule.h | 138 + .../MdePkg/Include/Ppi/DxeIpl.h | 66 + .../MdePkg/Include/Ppi/EndOfPeiPhase.h | 25 + .../MdePkg/Include/Ppi/FirmwareVolume.h | 288 + .../MdePkg/Include/Ppi/FirmwareVolumeInfo.h | 62 + .../MdePkg/Include/Ppi/FirmwareVolumeInfo2.h | 66 + .../MdePkg/Include/Ppi/Graphics.h | 79 + .../Include/Ppi/GuidedSectionExtraction.h | 98 + .../MdePkg/Include/Ppi/I2cMaster.h | 102 + .../MdePkg/Include/Ppi/IsaHc.h | 113 + .../MdePkg/Include/Ppi/LoadFile.h | 71 + .../MdePkg/Include/Ppi/LoadImage.h | 46 + .../MdePkg/Include/Ppi/MasterBootMode.h | 26 + .../MdePkg/Include/Ppi/MemoryDiscovered.h | 26 + .../MdePkg/Include/Ppi/MmAccess.h | 155 + .../MdePkg/Include/Ppi/MmCommunication.h | 72 + .../MdePkg/Include/Ppi/MmConfiguration.h | 62 + .../MdePkg/Include/Ppi/MmControl.h | 90 + .../MdePkg/Include/Ppi/MpServices.h | 277 + .../MdePkg/Include/Ppi/Pcd.h | 854 ++ .../MdePkg/Include/Ppi/PcdInfo.h | 99 + .../MdePkg/Include/Ppi/PciCfg2.h | 178 + .../MdePkg/Include/Ppi/PeiCoreFvLocation.h | 42 + .../MdePkg/Include/Ppi/PiPcd.h | 426 + .../MdePkg/Include/Ppi/PiPcdInfo.h | 76 + .../MdePkg/Include/Ppi/ReadOnlyVariable2.h | 111 + .../MdePkg/Include/Ppi/RecoveryModule.h | 81 + .../Include/Ppi/ReportStatusCodeHandler.h | 76 + .../MdePkg/Include/Ppi/Reset.h | 38 + .../MdePkg/Include/Ppi/Reset2.h | 32 + .../MdePkg/Include/Ppi/S3Resume2.h | 86 + .../MdePkg/Include/Ppi/SecHobData.h | 59 + .../Include/Ppi/SecPlatformInformation.h | 182 + .../Include/Ppi/SecPlatformInformation2.h | 79 + .../MdePkg/Include/Ppi/Security2.h | 95 + .../MdePkg/Include/Ppi/Smbus2.h | 197 + .../MdePkg/Include/Ppi/Stall.h | 56 + .../MdePkg/Include/Ppi/StatusCode.h | 35 + .../MdePkg/Include/Ppi/SuperIo.h | 183 + .../MdePkg/Include/Ppi/TemporaryRamDone.h | 46 + .../MdePkg/Include/Ppi/TemporaryRamSupport.h | 60 + .../MdePkg/Include/Ppi/VectorHandoffInfo.h | 69 + .../MdePkg/Include/Protocol/AbsolutePointer.h | 202 + .../Protocol/AcpiSystemDescriptionTable.h | 263 + .../MdePkg/Include/Protocol/AcpiTable.h | 124 + .../Include/Protocol/AdapterInformation.h | 254 + .../MdePkg/Include/Protocol/Arp.h | 379 + .../MdePkg/Include/Protocol/AtaPassThru.h | 468 + .../Include/Protocol/AuthenticationInfo.h | 231 + .../MdePkg/Include/Protocol/Bds.h | 66 + .../MdePkg/Include/Protocol/Bis.h | 445 + .../MdePkg/Include/Protocol/BlockIo.h | 235 + .../MdePkg/Include/Protocol/BlockIo2.h | 200 + .../MdePkg/Include/Protocol/BlockIoCrypto.h | 524 ++ .../Include/Protocol/BluetoothAttribute.h | 277 + .../MdePkg/Include/Protocol/BluetoothConfig.h | 523 ++ .../MdePkg/Include/Protocol/BluetoothHc.h | 418 + .../MdePkg/Include/Protocol/BluetoothIo.h | 411 + .../Include/Protocol/BluetoothLeConfig.h | 630 ++ .../Include/Protocol/BootManagerPolicy.h | 132 + .../Protocol/BusSpecificDriverOverride.h | 66 + .../MdePkg/Include/Protocol/Capsule.h | 29 + .../MdePkg/Include/Protocol/ComponentName.h | 123 + .../MdePkg/Include/Protocol/ComponentName2.h | 166 + .../MdePkg/Include/Protocol/Cpu.h | 294 + .../MdePkg/Include/Protocol/CpuIo2.h | 136 + .../MdePkg/Include/Protocol/DebugPort.h | 140 + .../MdePkg/Include/Protocol/DebugSupport.h | 827 ++ .../MdePkg/Include/Protocol/Decompress.h | 116 + .../Include/Protocol/DeferredImageLoad.h | 74 + .../MdePkg/Include/Protocol/DeviceIo.h | 262 + .../MdePkg/Include/Protocol/DevicePath.h | 1379 +++ .../Include/Protocol/DevicePathFromText.h | 66 + .../Include/Protocol/DevicePathToText.h | 79 + .../Include/Protocol/DevicePathUtilities.h | 186 + .../MdePkg/Include/Protocol/Dhcp4.h | 774 ++ .../MdePkg/Include/Protocol/Dhcp6.h | 780 ++ .../MdePkg/Include/Protocol/DiskInfo.h | 221 + .../MdePkg/Include/Protocol/DiskIo.h | 111 + .../MdePkg/Include/Protocol/DiskIo2.h | 166 + .../MdePkg/Include/Protocol/Dns4.h | 537 ++ .../MdePkg/Include/Protocol/Dns6.h | 533 ++ .../MdePkg/Include/Protocol/DriverBinding.h | 195 + .../Include/Protocol/DriverConfiguration.h | 161 + .../Include/Protocol/DriverConfiguration2.h | 184 + .../Include/Protocol/DriverDiagnostics.h | 125 + .../Include/Protocol/DriverDiagnostics2.h | 105 + .../Include/Protocol/DriverFamilyOverride.h | 60 + .../MdePkg/Include/Protocol/DriverHealth.h | 241 + .../Protocol/DriverSupportedEfiVersion.h | 40 + .../Include/Protocol/DxeMmReadyToLock.h | 19 + .../Include/Protocol/DxeSmmReadyToLock.h | 34 + .../MdePkg/Include/Protocol/Eap.h | 156 + .../Include/Protocol/EapConfiguration.h | 153 + .../MdePkg/Include/Protocol/EapManagement.h | 397 + .../MdePkg/Include/Protocol/EapManagement2.h | 81 + .../MdePkg/Include/Protocol/Ebc.h | 308 + .../MdePkg/Include/Protocol/EdidActive.h | 46 + .../MdePkg/Include/Protocol/EdidDiscovered.h | 44 + .../MdePkg/Include/Protocol/EdidOverride.h | 61 + .../MdePkg/Include/Protocol/EraseBlock.h | 99 + .../Include/Protocol/FirmwareManagement.h | 564 ++ .../MdePkg/Include/Protocol/FirmwareVolume2.h | 756 ++ .../Include/Protocol/FirmwareVolumeBlock.h | 360 + .../MdePkg/Include/Protocol/FormBrowser2.h | 174 + .../MdePkg/Include/Protocol/Ftp4.h | 518 ++ .../MdePkg/Include/Protocol/GraphicsOutput.h | 270 + .../Protocol/GuidedSectionExtraction.h | 135 + .../MdePkg/Include/Protocol/Hash.h | 169 + .../MdePkg/Include/Protocol/Hash2.h | 196 + .../MdePkg/Include/Protocol/HiiConfigAccess.h | 220 + .../Include/Protocol/HiiConfigKeyword.h | 199 + .../Include/Protocol/HiiConfigRouting.h | 417 + .../MdePkg/Include/Protocol/HiiDatabase.h | 528 ++ .../MdePkg/Include/Protocol/HiiFont.h | 469 + .../MdePkg/Include/Protocol/HiiImage.h | 353 + .../MdePkg/Include/Protocol/HiiImageDecoder.h | 200 + .../MdePkg/Include/Protocol/HiiImageEx.h | 248 + .../MdePkg/Include/Protocol/HiiPackageList.h | 27 + .../MdePkg/Include/Protocol/HiiPopup.h | 78 + .../MdePkg/Include/Protocol/HiiString.h | 238 + .../MdePkg/Include/Protocol/Http.h | 516 ++ .../Include/Protocol/HttpBootCallback.h | 94 + .../MdePkg/Include/Protocol/HttpUtilities.h | 118 + .../Protocol/I2cBusConfigurationManagement.h | 165 + .../MdePkg/Include/Protocol/I2cEnumerate.h | 104 + .../MdePkg/Include/Protocol/I2cHost.h | 146 + .../MdePkg/Include/Protocol/I2cIo.h | 166 + .../MdePkg/Include/Protocol/I2cMaster.h | 186 + .../Include/Protocol/IScsiInitiatorName.h | 81 + .../Include/Protocol/IdeControllerInit.h | 559 ++ .../Protocol/IncompatiblePciDeviceSupport.h | 167 + .../MdePkg/Include/Protocol/Ip4.h | 606 ++ .../MdePkg/Include/Protocol/Ip4Config.h | 176 + .../MdePkg/Include/Protocol/Ip4Config2.h | 317 + .../MdePkg/Include/Protocol/Ip6.h | 947 ++ .../MdePkg/Include/Protocol/Ip6Config.h | 368 + .../MdePkg/Include/Protocol/IpSec.h | 218 + .../MdePkg/Include/Protocol/IpSecConfig.h | 801 ++ .../MdePkg/Include/Protocol/IsaHc.h | 110 + .../MdePkg/Include/Protocol/Kms.h | 1337 +++ .../MdePkg/Include/Protocol/LegacyRegion2.h | 233 + .../Include/Protocol/LegacySpiController.h | 259 + .../MdePkg/Include/Protocol/LegacySpiFlash.h | 195 + .../Include/Protocol/LegacySpiSmmController.h | 30 + .../Include/Protocol/LegacySpiSmmFlash.h | 30 + .../MdePkg/Include/Protocol/LoadFile.h | 82 + .../MdePkg/Include/Protocol/LoadFile2.h | 79 + .../MdePkg/Include/Protocol/LoadedImage.h | 82 + .../MdePkg/Include/Protocol/ManagedNetwork.h | 366 + .../MdePkg/Include/Protocol/Metronome.h | 74 + .../MdePkg/Include/Protocol/MmAccess.h | 127 + .../MdePkg/Include/Protocol/MmBase.h | 81 + .../MdePkg/Include/Protocol/MmCommunication.h | 87 + .../Include/Protocol/MmCommunication2.h | 69 + .../MdePkg/Include/Protocol/MmConfiguration.h | 64 + .../MdePkg/Include/Protocol/MmControl.h | 100 + .../MdePkg/Include/Protocol/MmCpu.h | 241 + .../MdePkg/Include/Protocol/MmCpuIo.h | 90 + .../MdePkg/Include/Protocol/MmEndOfDxe.h | 24 + .../MdePkg/Include/Protocol/MmGpiDispatch.h | 119 + .../Include/Protocol/MmIoTrapDispatch.h | 130 + .../MdePkg/Include/Protocol/MmMp.h | 333 + .../Include/Protocol/MmPciRootBridgeIo.h | 31 + .../Protocol/MmPeriodicTimerDispatch.h | 164 + .../Include/Protocol/MmPowerButtonDispatch.h | 111 + .../MdePkg/Include/Protocol/MmReadyToLock.h | 26 + .../Protocol/MmReportStatusCodeHandler.h | 78 + .../Protocol/MmStandbyButtonDispatch.h | 113 + .../MdePkg/Include/Protocol/MmStatusCode.h | 59 + .../MdePkg/Include/Protocol/MmSwDispatch.h | 130 + .../MdePkg/Include/Protocol/MmSxDispatch.h | 129 + .../MdePkg/Include/Protocol/MmUsbDispatch.h | 124 + .../Include/Protocol/MonotonicCounter.h | 22 + .../MdePkg/Include/Protocol/MpService.h | 676 ++ .../MdePkg/Include/Protocol/Mtftp4.h | 587 ++ .../MdePkg/Include/Protocol/Mtftp6.h | 820 ++ .../Protocol/NetworkInterfaceIdentifier.h | 112 + .../MdePkg/Include/Protocol/NvdimmLabel.h | 345 + .../Include/Protocol/NvmExpressPassthru.h | 283 + .../MdePkg/Include/Protocol/PartitionInfo.h | 68 + .../MdePkg/Include/Protocol/Pcd.h | 861 ++ .../MdePkg/Include/Protocol/PcdInfo.h | 102 + .../Include/Protocol/PciEnumerationComplete.h | 24 + .../PciHostBridgeResourceAllocation.h | 422 + .../MdePkg/Include/Protocol/PciHotPlugInit.h | 272 + .../Include/Protocol/PciHotPlugRequest.h | 164 + .../MdePkg/Include/Protocol/PciIo.h | 551 ++ .../MdePkg/Include/Protocol/PciOverride.h | 40 + .../MdePkg/Include/Protocol/PciPlatform.h | 338 + .../MdePkg/Include/Protocol/PciRootBridgeIo.h | 436 + .../MdePkg/Include/Protocol/PiPcd.h | 418 + .../MdePkg/Include/Protocol/PiPcdInfo.h | 77 + .../MdePkg/Include/Protocol/Pkcs7Verify.h | 223 + .../Include/Protocol/PlatformDriverOverride.h | 134 + .../Protocol/PlatformToDriverConfiguration.h | 349 + .../MdePkg/Include/Protocol/PxeBaseCode.h | 930 ++ .../Include/Protocol/PxeBaseCodeCallBack.h | 124 + .../MdePkg/Include/Protocol/RamDisk.h | 100 + .../MdePkg/Include/Protocol/RealTimeClock.h | 30 + .../MdePkg/Include/Protocol/RedfishDiscover.h | 193 + .../Protocol/RegularExpressionProtocol.h | 175 + .../Protocol/ReportStatusCodeHandler.h | 91 + .../MdePkg/Include/Protocol/Reset.h | 25 + .../Include/Protocol/ResetNotification.h | 80 + .../MdePkg/Include/Protocol/Rest.h | 88 + .../MdePkg/Include/Protocol/RestEx.h | 390 + .../Include/Protocol/RestJsonStructure.h | 161 + .../MdePkg/Include/Protocol/Rng.h | 150 + .../MdePkg/Include/Protocol/Runtime.h | 122 + .../MdePkg/Include/Protocol/S3SaveState.h | 170 + .../MdePkg/Include/Protocol/S3SmmSaveState.h | 40 + .../MdePkg/Include/Protocol/ScsiIo.h | 311 + .../MdePkg/Include/Protocol/ScsiPassThru.h | 377 + .../MdePkg/Include/Protocol/ScsiPassThruExt.h | 388 + .../MdePkg/Include/Protocol/SdMmcPassThru.h | 258 + .../MdePkg/Include/Protocol/Security.h | 97 + .../MdePkg/Include/Protocol/Security2.h | 101 + .../MdePkg/Include/Protocol/SecurityPolicy.h | 20 + .../MdePkg/Include/Protocol/SerialIo.h | 309 + .../MdePkg/Include/Protocol/ServiceBinding.h | 88 + .../MdePkg/Include/Protocol/Shell.h | 1262 +++ .../Include/Protocol/ShellDynamicCommand.h | 79 + .../MdePkg/Include/Protocol/ShellParameters.h | 54 + .../Include/Protocol/SimpleFileSystem.h | 556 ++ .../MdePkg/Include/Protocol/SimpleNetwork.h | 675 ++ .../MdePkg/Include/Protocol/SimplePointer.h | 137 + .../MdePkg/Include/Protocol/SimpleTextIn.h | 127 + .../MdePkg/Include/Protocol/SimpleTextInEx.h | 317 + .../MdePkg/Include/Protocol/SimpleTextOut.h | 409 + .../MdePkg/Include/Protocol/SmartCardEdge.h | 736 ++ .../MdePkg/Include/Protocol/SmartCardReader.h | 319 + .../MdePkg/Include/Protocol/Smbios.h | 207 + .../MdePkg/Include/Protocol/SmbusHc.h | 289 + .../MdePkg/Include/Protocol/SmmAccess2.h | 38 + .../MdePkg/Include/Protocol/SmmBase2.h | 79 + .../Include/Protocol/SmmCommunication.h | 27 + .../Include/Protocol/SmmConfiguration.h | 78 + .../MdePkg/Include/Protocol/SmmControl2.h | 35 + .../MdePkg/Include/Protocol/SmmCpu.h | 130 + .../MdePkg/Include/Protocol/SmmCpuIo2.h | 35 + .../MdePkg/Include/Protocol/SmmEndOfDxe.h | 26 + .../MdePkg/Include/Protocol/SmmGpiDispatch2.h | 43 + .../Include/Protocol/SmmIoTrapDispatch2.h | 47 + .../Include/Protocol/SmmPciRootBridgeIo.h | 28 + .../Protocol/SmmPeriodicTimerDispatch2.h | 156 + .../Protocol/SmmPowerButtonDispatch2.h | 36 + .../MdePkg/Include/Protocol/SmmReadyToLock.h | 28 + .../Protocol/SmmReportStatusCodeHandler.h | 29 + .../Protocol/SmmStandbyButtonDispatch2.h | 36 + .../MdePkg/Include/Protocol/SmmStatusCode.h | 25 + .../MdePkg/Include/Protocol/SmmSwDispatch2.h | 128 + .../MdePkg/Include/Protocol/SmmSxDispatch2.h | 32 + .../MdePkg/Include/Protocol/SmmUsbDispatch2.h | 41 + .../Include/Protocol/SpiConfiguration.h | 287 + .../MdePkg/Include/Protocol/SpiHc.h | 188 + .../MdePkg/Include/Protocol/SpiIo.h | 286 + .../MdePkg/Include/Protocol/SpiNorFlash.h | 256 + .../Include/Protocol/SpiSmmConfiguration.h | 30 + .../MdePkg/Include/Protocol/SpiSmmHc.h | 30 + .../MdePkg/Include/Protocol/SpiSmmNorFlash.h | 30 + .../MdePkg/Include/Protocol/StatusCode.h | 53 + .../Include/Protocol/StorageSecurityCommand.h | 206 + .../MdePkg/Include/Protocol/SuperIo.h | 169 + .../MdePkg/Include/Protocol/SuperIoControl.h | 86 + .../MdePkg/Include/Protocol/Supplicant.h | 458 + .../MdePkg/Include/Protocol/TapeIo.h | 231 + .../MdePkg/Include/Protocol/Tcg2Protocol.h | 335 + .../MdePkg/Include/Protocol/TcgService.h | 195 + .../MdePkg/Include/Protocol/Tcp4.h | 571 ++ .../MdePkg/Include/Protocol/Tcp6.h | 858 ++ .../MdePkg/Include/Protocol/Timer.h | 174 + .../MdePkg/Include/Protocol/Timestamp.h | 95 + .../MdePkg/Include/Protocol/Tls.h | 511 ++ .../MdePkg/Include/Protocol/TlsConfig.h | 127 + .../MdePkg/Include/Protocol/TrEEProtocol.h | 243 + .../MdePkg/Include/Protocol/Udp4.h | 439 + .../MdePkg/Include/Protocol/Udp6.h | 574 ++ .../MdePkg/Include/Protocol/UfsDeviceConfig.h | 137 + .../MdePkg/Include/Protocol/UgaDraw.h | 160 + .../MdePkg/Include/Protocol/UgaIo.h | 191 + .../Include/Protocol/UnicodeCollation.h | 186 + .../Include/Protocol/Usb2HostController.h | 658 ++ .../MdePkg/Include/Protocol/UsbFunctionIo.h | 684 ++ .../Include/Protocol/UsbHostController.h | 502 ++ .../MdePkg/Include/Protocol/UsbIo.h | 506 ++ .../MdePkg/Include/Protocol/UserCredential.h | 286 + .../MdePkg/Include/Protocol/UserCredential2.h | 308 + .../MdePkg/Include/Protocol/UserManager.h | 618 ++ .../MdePkg/Include/Protocol/Variable.h | 39 + .../MdePkg/Include/Protocol/VariableWrite.h | 39 + .../MdePkg/Include/Protocol/VlanConfig.h | 137 + .../MdePkg/Include/Protocol/WatchdogTimer.h | 138 + .../MdePkg/Include/Protocol/WiFi.h | 1123 +++ .../MdePkg/Include/Protocol/WiFi2.h | 407 + .../MdePkg/Include/Register/Amd/Cpuid.h | 737 ++ .../MdePkg/Include/Register/Amd/Fam17Msr.h | 136 + .../MdePkg/Include/Register/Amd/Ghcb.h | 282 + .../MdePkg/Include/Register/Amd/Msr.h | 23 + .../Include/Register/Intel/ArchitecturalMsr.h | 6572 ++++++++++++++ .../MdePkg/Include/Register/Intel/Cpuid.h | 4075 +++++++++ .../MdePkg/Include/Register/Intel/LocalApic.h | 183 + .../MdePkg/Include/Register/Intel/Microcode.h | 194 + .../MdePkg/Include/Register/Intel/Msr.h | 44 + .../Include/Register/Intel/Msr/AtomMsr.h | 784 ++ .../Include/Register/Intel/Msr/BroadwellMsr.h | 354 + .../Include/Register/Intel/Msr/Core2Msr.h | 1068 +++ .../Include/Register/Intel/Msr/CoreMsr.h | 1056 +++ .../Include/Register/Intel/Msr/GoldmontMsr.h | 2539 ++++++ .../Register/Intel/Msr/GoldmontPlusMsr.h | 266 + .../Include/Register/Intel/Msr/HaswellEMsr.h | 6400 ++++++++++++++ .../Include/Register/Intel/Msr/HaswellMsr.h | 2631 ++++++ .../Include/Register/Intel/Msr/IvyBridgeMsr.h | 2887 +++++++ .../Include/Register/Intel/Msr/NehalemMsr.h | 7424 ++++++++++++++++ .../MdePkg/Include/Register/Intel/Msr/P6Msr.h | 1658 ++++ .../Include/Register/Intel/Msr/Pentium4Msr.h | 2724 ++++++ .../Include/Register/Intel/Msr/PentiumMMsr.h | 678 ++ .../Include/Register/Intel/Msr/PentiumMsr.h | 139 + .../Register/Intel/Msr/SandyBridgeMsr.h | 4791 +++++++++++ .../Register/Intel/Msr/SilvermontMsr.h | 1612 ++++ .../Include/Register/Intel/Msr/SkylakeMsr.h | 3810 ++++++++ .../Include/Register/Intel/Msr/Xeon5600Msr.h | 197 + .../Include/Register/Intel/Msr/XeonDMsr.h | 1267 +++ .../Include/Register/Intel/Msr/XeonE7Msr.h | 367 + .../Include/Register/Intel/Msr/XeonPhiMsr.h | 1673 ++++ .../Register/Intel/SmramSaveStateMap.h | 184 + .../MdePkg/Include/Register/Intel/StmApi.h | 948 ++ .../Register/Intel/StmResourceDescriptor.h | 222 + .../Include/Register/Intel/StmStatusCode.h | 72 + .../MdePkg/Include/RiscV64/ProcessorBind.h | 173 + .../edk2-stable202111/MdePkg/Include/Uefi.h | 21 + .../MdePkg/Include/Uefi/UefiAcpiDataTable.h | 23 + .../MdePkg/Include/Uefi/UefiBaseType.h | 311 + .../MdePkg/Include/Uefi/UefiGpt.h | 139 + .../Uefi/UefiInternalFormRepresentation.h | 2130 +++++ .../MdePkg/Include/Uefi/UefiMultiPhase.h | 229 + .../MdePkg/Include/Uefi/UefiPxe.h | 1786 ++++ .../MdePkg/Include/Uefi/UefiSpec.h | 2240 +++++ .../MdePkg/Include/X64/Nasm.inc | 88 + .../MdePkg/Include/X64/ProcessorBind.h | 341 + .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 235 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util/mainboard/google/brask/template/include/variant/ec.h create mode 100644 util/mainboard/google/brask/template/include/variant/gpio.h create mode 100644 util/mainboard/google/brask/template/overridetree.cb create mode 100644 util/nixshell/documentation.nix create mode 100644 util/spd_tools/src/spd_gen/lp5.go diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 428da69162..9e8f457edc 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 428da691621f810b6b94fc715116a914c8dd859f +Subproject commit 9e8f457edcc359552a5d0113568a2d1670009178 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 586aafa3a4..e0a6a512b5 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 586aafa3a4b13971339f78e430075592c3fe74b5 +Subproject commit e0a6a512b51558b64eb500e6b731e4c743050af2 diff --git a/3rdparty/blobs b/3rdparty/blobs index f388b6794e..f14575cb99 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 +Subproject commit f14575cb9924b051cedfb4c1f62e3640b25f9dbd diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 4c21b57eb9..e486b388a7 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 4c21b57eb9619cc3dc86d11226917d25f62f1bc8 +Subproject commit e486b388a73f1e19f3142774d0b3ee166e8f41ff diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 3f97690f0d..115c3e4cda 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 3f97690f0da8011f52209b232450a1e5c4f2e1f6 +Subproject commit 115c3e4cdad6a9d84bf06e066162c5c546a9d2c3 diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 98db38671b..9ab0f0b71c 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 98db38671b651dd7e7966fb629d65ff5dd23865b +Subproject commit 9ab0f0b71c25aa8414e72040bad6fe12b0ccb3f3 diff --git a/3rdparty/vboot b/3rdparty/vboot index 13f601fbd4..25b9493525 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 13f601fbd4c1b128f333391e4552082594f0ff25 +Subproject commit 25b9493525325dfb5bc2c36321c43ec7665060fa diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md index 470a55fa45..2d38f99582 100644 --- a/Documentation/acpi/gpio.md +++ b/Documentation/acpi/gpio.md @@ -84,15 +84,6 @@ the raw Rx gpio value. ## Implementation Details -ACPI library in coreboot will provide weak definitions for all the -above functions with error messages indicating that these functions -are being used. This allows drivers to conditionally make use of GPIOs -based on device-tree entries or any other config option. It is -recommended that the SoC code in coreboot should provide -implementations of all the above functions generating ACPI AML code -irrespective of them being used in any driver. This allows mainboards -to use any drivers and take advantage of this common infrastructure. - Platforms are restricted to using Local5, Local6 and Local7 variables only in implementations of the above functions. Any AML methods called by the above functions do not have any such restrictions on use of diff --git a/Documentation/community/index.md b/Documentation/community/index.md new file mode 100644 index 0000000000..30420ae903 --- /dev/null +++ b/Documentation/community/index.md @@ -0,0 +1,7 @@ +# Community + +* [Code of Conduct](code_of_conduct.md) +* [Language style](language_style.md) +* [Community forums](forums.md) +* [Project services](services.md) +* [coreboot at conferences](conferences.md) diff --git a/Documentation/community/services.md b/Documentation/community/services.md index 07c6f2c688..a7f13eefb5 100644 --- a/Documentation/community/services.md +++ b/Documentation/community/services.md @@ -1,6 +1,6 @@ # Accounts on coreboot.org -There are a number of places where you can benefit from creaating an account +There are a number of places where you can benefit from creating an account in our community. Since there is no single sign-on system in place (at this time), they come with their own setup routines. diff --git a/Documentation/contributing/gsoc.md b/Documentation/contributing/gsoc.md new file mode 100644 index 0000000000..bcc732ab4c --- /dev/null +++ b/Documentation/contributing/gsoc.md @@ -0,0 +1,249 @@ +# Google Summer of Code + + +## Contacts + +If you are interested in participating in GSoC as a contributor or mentor, +please have a look at our [community forums] and reach out to us. Working closely +with the community is highly encouraged, as we've seen that our most successful +contributors are generally very involved. + +Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for +2022. Please feel free to reach out to them directly if you have any questions. + + +## Why work on coreboot for GSoC? + + * coreboot offers you the opportunity to work with various architectures + right on the iron. coreboot supports both current and older silicon for a + wide variety of chips and technologies. + + * coreboot has a worldwide developer and user base. + + * We are a very passionate team, so you will interact directly with the + project initiators and project leaders. + + * We have a large, helpful community. coreboot has some extremely talented + and helpful experts in firmware involved in the project. They are ready to + assist and mentor contributors participating in GSoC. + + * One of the last areas where open source software is not common is firmware. + Running proprietary firmware can have severe effects on user's freedom and + security. coreboot has a mission to change that by providing a common + framework for initial hardware initialization and you can help us succeed. + + +## Contributor requirements & commitments + +Google Summer of Code is a significant time commitment for you. Medium-sized +projects are estimated to take 175 hours, while large-sized projects are +estimated to take 350 hours. Depending on the project size, this means we +expect you to work roughly half-time or full-time on your project during the +three months of coding. We expect to be able to see this level of effort in the +results. + +The standard program duration is 12 weeks and in consultation with the mentor +it can be extended up to 22 weeks. Please keep in mind that the actual number +of hours you spend on the project highly depends on your skills and previous +experience. + +Make sure that your schedule (exams, courses, day job) gives you a sufficient +amount of spare time. If this is not the case, then you should not apply. + + +### Before applying + + * Join the [mailing list] and our other [community forums]. Introduce yourself + and mention that you are a prospective GSoC contributor. Ask questions and + discuss the project that you are considering. Community involvement is a + key component of coreboot development. + + * You accept our [Code of Conduct] and [Language style]. + + * Demonstrate that you can work with the coreboot codebase. + + * Look over some of the development processes guidelines: [Getting started], + [Tutorial], [Flashing firmware tutorial] and [Coding style]. + + * Download, build and boot coreboot in QEMU or on real hardware. Please email + your serial output results to the [mailing list]. + + * Look through some patches on Gerrit to get an understanding of the review + process and common issues. + + * Get signed up for Gerrit and push at least one patch to Gerrit for review. + Check Easy projects or ask for simple tasks on the [mailing list] or on our + other [community forums] if you need ideas. + + +### During the program + + * To pass and to be paid by Google requires that you meet certain milestones. + + * First, you must be in good standing with the community before the official + start of the program. We expect you to post some design emails to the + [mailing list], and get feedback on them, both before applying, and during + the "community bonding period" between acceptance and official start. + + * You must have made progress and committed significant code before the + mid-term point and by the final. + + * We require that accepted contributors to maintain a blog, where you are + expected to write about your project *WEEKLY*. This is a way to measure + progress and for the community at large to be able to help you. GSoC is + *NOT* a private contract between your mentor and you. + + * You must be active in the community on IRC and the [mailing list]. + + * You are expected to work on development publicly, and to push commits to the + project on a regular basis. Depending on the project and what your mentor + agrees to, these can be published directly to the project or to a public + repository such as Gitlab or Github. If you are not publishing directly to + the project codebase, be aware that we do not want large dumps of code that + need to be rushed to meet the mid-term and final goals. + +We don't expect our contributors to be experts in our problem domain, but we +don't want you to fail because some basic misunderstanding was in your way of +completing the task. + + +## Projects + +There are many development tasks available in coreboot. We prepared some ideas +for Summer of Code projects. These are projects that we think can be managed in +the timeline of GSoC, and they cover areas where coreboot is trying to reach +new users and new use cases. + +Of course your application does not have to be based on any of the ideas listed. +It is entirely possible that you have a great idea that we just didn't think of +yet. Please let us know! + +The blog posts related to previous GSoC projects might give some insights to +what it is like to be a coreboot GSoC contributor. + + +## coreboot Summer of Code Application + +coreboot welcomes contributors from all backgrounds and levels of experience. + +Your application should include a complete project proposal. You should +document that you have the knowledge and the ability to complete your proposed +project. This may require a little research and understanding of coreboot prior +to sending your application. The community and coreboot project mentors are your +best resource in fleshing out your project ideas and helping with a project +timeline. We recommend that you get feedback and recommendations on your +proposal before the application deadline. + +Please complete the standard GSoC application and project proposal. Provide the +following information as part of your application. Make sure to provide multiple +ways of communicating in case your equipment (such as a laptop) is lost, +damaged, or stolen, or in case of a natural disaster that disrupts internet +service. You risk automatically failing if your mentor cannot contact you and if +you cannot provide updates according to GSoC deadlines. + +**Personal Information** + + * Name + + * Email and contact options (IRC, Matrix, …) + + * Phone number (optional, but recommended) + + * Timezone, Usual working hours (UTC) + + * School / University, Degree Program, expected graduation date + + * Short bio / Overview of your background + + * What are your other time commitments? Do you have a job, classes, vacations? + When and how long? + +**Software experience** + +If applicable, please provide the following information: + + * Portfolio, Website, blog, microblog, Github, Gitlab, ... + + * Links to one or more patches submitted + + * Links to posts on the [mailing list] with the serial output of your build. + + * Please comment on your software and firmware experience. + + * Have you contributed to an open source project? Which one? What was your + experience? + + * What was your experience while building and running coreboot? Did you have + problems? + +**Your project** + + * Provide an overview of your project (in your own words). + + * Provide a breakdown of your project in small specific weekly goals. Think + about the potential timeline. + + * How will you accomplish this goal? What is your working style? + + * Explain what risks or potential problems your project might experience. + + * What would you expect as a minimum level of success? + + * Do you have a stretch goal? + +**Other** + + * Resume (optional) + + +### Advice on how to apply + + * [GSoC Contributor Guide] + + * The Drupal project has a great page on how to write an GSoC application. + + * Secrets for GSoC success: [2] + + +## Mentors + +Each accepted project will have at least one mentor. We will match mentors and +contributors based on the project and experience level. If possible, we also +will try to match their time zones. + +Mentors are expected to stay in frequent contact with the contributor and +provide guidance such as code reviews, pointers to useful documentation, etc. +This should generally be a time commitment of several hours per week. + +Some projects might have more than one mentor, who can serve as a backup. They +are expected to coordinate with each other and a contributor on a regular basis, +and keep track of the contributor process. They should be able to take over +mentoring duty if one of the mentors is unavailable (vacations, sickness, +emergencies). + + +### Volunteering to be a mentor + +If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide]. +This will give you a better idea of expectations, and where to go for help. +After that, contact Org Admins (see coreboot contacts section above). + +The following coreboot developers have volunteered to be GSoC 2022 mentors. +Please stop by in our community forums and say hi to them and ask them +questions. + + * Tim Wawrzynczak + * Raul Rangel + * Ron Minnich + + +[community forums]: ../community/forums.md +[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org +[Getting started]: ../getting_started/index.md +[Tutorial]: ../tutorial/index.md +[Flashing firmware tutorial]: ../flash_tutorial/index.md +[Coding style]: coding_style.md +[Code of Conduct]: ../community/code_of_conduct.md +[Language style]: ../community/language_style.md +[GSoC Contributor Guide]: https://google.github.io/gsocguides/student +[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor diff --git a/Documentation/contributing/index.md b/Documentation/contributing/index.md new file mode 100644 index 0000000000..f9db1bc821 --- /dev/null +++ b/Documentation/contributing/index.md @@ -0,0 +1,6 @@ +# Contributing + +* [Coding Style](coding_style.md) +* [Project Ideas](project_ideas.md) +* [Documentation Ideas](documentation_ideas.md) +* [Google Summer of Code](gsoc.md) diff --git a/Documentation/distributions.md b/Documentation/distributions.md index efdcf1b9c7..4d69fcc9d3 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -24,6 +24,13 @@ ships with coreboot and support upstream maintenance for the devices through a third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io). +### Star Labs + +[Star Labs](https://starlabs.systems/) offers a range of laptops designed and +built specifically for Linux that are available with coreboot firmware. They +use Tianocore as the payload and include an NVRAM option to disable the +Intel Management Engine. + ### System76 [System76](https://system76.com/) manufactures Linux laptops, desktops, and diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 8c91615604..68b5cc43c0 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -193,8 +193,10 @@ the wip flag: * When pushing patches that are not for submission, these should be marked as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as private changes, so that only explicitly added reviewers will see them. These -sorts of patches are frequently posted as ideas or RFCs for the community -to look at. To push a private change, use the command: +sorts of patches are frequently posted as ideas or RFCs for the community to +look at. Note that private changes can still be fetched from Gerrit by anybody +who knows their commit ID, so don't use this for sensitive changes. To push +a private change, use the command: git push origin HEAD:refs/for/master%private * Multiple push options can be combined: diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 5d5623a5d9..5f30ea7c38 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -162,6 +162,53 @@ The first is configuring a pin as an output, when it was designed to be an input. There is a real risk in this case of short-circuiting a component which could cause catastrophic failures, up to and including your mainboard! +### Intel SoCs + +As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register +supports four different types of GPIO reset as: + +| PAD Reset Config | Platform Reset | GPP | GPD | +|-------------------------------------------------|----------------|-----|-----| +| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N | +| | Cold Reset | N | N | +| | S3/S4/S5 | N | N | +| | Global Reset | N | N | +| | Deep Sx | Y | N | +| | G3 | Y | N | +| 01 - Deep | Warm Reset | Y | Y | +| | Cold Reset | Y | Y | +| | S3/S4/S5 | N | N | +| | Global Reset | Y | Y | +| | Deep Sx | Y | Y | +| | G3 | Y | Y | +| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | +| | Cold Reset | Y | Y | +| | S3/S4/S5 | Y | Y | +| | Global Reset | Y | Y | +| | Deep Sx | Y | Y | +| | G3 | Y | Y | +| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N | +| | Cold Reset | - | N | +| | S3/S4/S5 | - | N | +| | Global Reset | - | N | +| | Deep Sx | - | Y | +| | G3 | - | Y | + +Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking +specific register fields in the PAD configuration register. + +The Pad Config Lock registers reset type is default hardcoded to **Power Good** and +it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP, +the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`. + +This would create confusion where the Pad configuration is returned to its `default` +value but remains `locked`, this would prevent software to reprogram the GPP. +Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry. + +Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset +Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are +always in sync and can be reset at the same time. + ## Soft Straps Soft straps, that can be configured by the vendor in the Intel Flash Image Tool diff --git a/Documentation/index.md b/Documentation/index.md index bdfb6bf622..1fa29ced72 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -168,14 +168,8 @@ Contents: * [Getting Started](getting_started/index.md) * [Tutorial](tutorial/index.md) -* [Coding Style](contributing/coding_style.md) -* [Project Ideas](contributing/project_ideas.md) -* [Documentation Ideas](contributing/documentation_ideas.md) -* [Code of Conduct](community/code_of_conduct.md) -* [Language style](community/language_style.md) -* [Community forums](community/forums.md) -* [Project services](community/services.md) -* [coreboot at conferences](community/conferences.md) +* [Contributing](contributing/index.md) +* [Community](community/index.md) * [Payloads](payloads.md) * [Distributions](distributions.md) * [Technotes](technotes/index.md) diff --git a/Documentation/mainboard/acer/g43t-am3.md b/Documentation/mainboard/acer/g43t-am3.md new file mode 100644 index 0000000000..2e9b8d658c --- /dev/null +++ b/Documentation/mainboard/acer/g43t-am3.md @@ -0,0 +1,177 @@ +# Acer G43T-AM3 + +The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the +Acer models Aspire M3800, Aspire M5800 and possibly more. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | Intel G43 (called x4x in coreboot code) | ++------------------+--------------------------------------------------+ +| Southbridge | Intel ICH10R (called i82801jx in coreboot code) | ++------------------+--------------------------------------------------+ +| CPU socket | LGA 775 | ++------------------+--------------------------------------------------+ +| RAM | 4 x DDR3-1066 | ++------------------+--------------------------------------------------+ +| SuperIO | ITE IT8720F | ++------------------+--------------------------------------------------+ +| Audio | Realtek ALC888S | ++------------------+--------------------------------------------------+ +| Network | Intel 82567V-2 Gigabit Ethernet | ++------------------+--------------------------------------------------+ +``` + +There is no serial port. Serial console output is possible by soldering +to a point at the corresponding Super I/O pin and patching the +mainboard-specific code accordingly. + +## Status + +### Working + +Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12 +(linux-4.19.50). + ++ Intel Core 2 processors at up to FSB 1333 ++ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB) ++ Integrated graphics (libgfxinit) ++ HDMI and VGA ports ++ Both PCI slots ++ Both PCI-e slots ++ USB (8 internal, 4 external) ++ All six SATA ports ++ Onboard Ethernet ++ Onboard sound card with output on the rear stereo connector ++ PS/2 mouse and keyboard + + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500 + + With FILO it works without further settings ++ Temperature readings from the Super I/O (including the CPU temperature + via PECI) ++ Super I/O EC automatic fan control ++ S3 suspend/resume ++ Poweroff + +### Not working + ++ DDR3 memory with 512Mx8 chips (G43 limitation) ++ 4x4GB of DDR3 memory (works, but showed a single bit error within one + pass of Memtest86+ 5.01) ++ Super I/O voltage reading conversions + +### Untested + ++ Other audio jacks or the front panel header ++ S/PDIF output ++ On-board Firewire ++ Wake-on-LAN + +## Flashing coreboot + +```eval_rst ++-------------------+---------------------+ +| Type | Value | ++===================+=====================+ +| Socketed flash | No | ++-------------------+---------------------+ +| Model | Macronix MX25L1605D | ++-------------------+---------------------+ +| Size | 2 MiB | ++-------------------+---------------------+ +| Package | 8-Pin SOP | ++-------------------+---------------------+ +| Write protection | No | ++-------------------+---------------------+ +| Dual BIOS feature | No | ++-------------------+---------------------+ +| Internal flashing | Yes | ++-------------------+---------------------+ +``` + +The flash is divided into the following regions, as obtained with +`ifdtool -f rom.layout backup.rom`: +``` +00000000:00001fff fd +00100000:001fffff bios +00006000:000fffff me +00002000:00005fff gbe +``` + +In general, flashing is possible internally and from an external header. It +might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E` +is the correct one, not `MX25L1605`. + +### Internal flashing + +Internal access to the flash chip is unrestricted. When installing coreboot, +only the BIOS region should be updated by passing the `--ifd` and `-i bios` +parameters to flashrom. A full backup is advisable. + +Here is an example: + +``` +$ sudo flashrom \ + -p internal \ + -c "MX25L1605D/MX25L1608D/MX25L1673E" \ + -r backup.rom +$ sudo flashrom \ + -p internal \ + -c "MX25L1605D/MX25L1608D/MX25L1673E" \ + --ifd -i bios \ + -w coreboot.rom +``` + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +### External flashing + +The SPI flash chip on this board can be flashed externally through the +SPI_ROM1 header while the board is off and disconnected from power. There +seems to be a diode that prevents the external programmer from powering the +whole board. + +The signal assigment on the header is identical to the pinout of the flash +chip. The pinout diagram below is valid when the PCI slots are on the left +and the CPU is on the right. Note that HOLD# and WP# must be pulled high +(to VCC) to be able to flash the chip. + + +---+---+ + SPI_CSn <- | x | x | -> VCC + +---+---+ + SPI_MISO <- | x | x | -> HOLDn + +---+---+ + WPn <- | x | x | -> SPI_CLK + +---+---+ + GND <- | x | x | -> SPI_MOSI + +---+---+ + +## Intel Management Engine + +The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE +jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash +Descriptor Security Override Strap" to be set. This disables the ME and also +disables any read/write restrictions to the flash chip that may be set in the +Intel Flash Descriptor (IFD) (none on this board). Note that changing this +jumper only comes into effect when starting the board from a shutdown or +suspend state, not during normal operation. + +To completely remove the ME blob from the flash image and to decrease the size +of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can +be used with the `-t`, `-r` and `-S` options. + +## Fan control + +There are two fan connectors that can be controlled individually. CPU_FAN +can only control a fan by a PWM signal and SYS_FAN only by voltage. See +the mainboard's `devicetree.cb` file for how coreboot configures the Super +I/O to control the fans. + +## Variants + +Various similar mainboards exist, like the Acer Q45T-AM. During a discussion +in #coreboot on IRC, ECS was suspected to be the original designer of this +series of mainboards. They have similar models such as the ECS G43T-WM. diff --git a/Documentation/mainboard/asrock/h77pro4-m.md b/Documentation/mainboard/asrock/h77pro4-m.md new file mode 100644 index 0000000000..45c603d7a3 --- /dev/null +++ b/Documentation/mainboard/asrock/h77pro4-m.md @@ -0,0 +1,174 @@ +# ASRock H77 Pro4-M + +The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy +Bridge and Ivy Bridge CPUs. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | Intel H77 (bd82x6x) | ++------------------+--------------------------------------------------+ +| CPU socket | LGA 1155 | ++------------------+--------------------------------------------------+ +| RAM | 4 x DDR3-1600 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6776 | ++------------------+--------------------------------------------------+ +| Audio | Realtek ALC892 | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111E | ++------------------+--------------------------------------------------+ +| Serial | Internal header (RS-232) | ++------------------+--------------------------------------------------+ +``` + +## Status + +Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12 +(linux-4.19.50). + +### Working + +- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) +- Native RAM initialization with four DIMMs +- PS/2 combined port (mouse or keyboard) +- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) +- PCIe graphics in the PEG slot +- All three additional PCIe slots +- All rear and internal USB2 ports +- All rear and internal USB3 ports +- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) +- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) +- Rear eSATA connector (multiplexed with one ASM1061 port) +- Gigabit Ethernet +- Console output on the serial port +- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via +extlinux +- Internal flashing with flashrom-1.2, see +[Internal Programming](#internal-programming) +- External flashing with flashrom-1.2 and a Raspberry Pi 1 +- S3 suspend/resume from either Linux or Windows 10 +- Poweroff + +### Not working + +- Booting from the two SATA ports provided by the ASM1061 +- Automatic fan control with the NCT6776D Super I/O + +### Untested + +- EHCI debug +- S/PDIF audio +- Other audio jacks than the green one, and the front panel header +- Parallel port +- Infrared/CIR +- Wakeup from anything but the power button + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | W25Q64.V | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +The flash is divided into the following regions, as obtained with +`ifdtool -f rom.layout backup.rom`: +``` +00000000:00000fff fd +00200000:007fffff bios +00001000:001fffff me +``` + +### Internal programming + +The main SPI flash can be accessed using flashrom. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region (Management Engine or flash descriptor), then an external +programmer is required. + +The following command may be used to flash coreboot: + +``` +$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom +``` + +The use of `--noverify-all` is required since the Management Engine +region is not readable even by the host. + +```eval_rst +In addition to the information here, please see the +:doc:`../../flash_tutorial/index`. +``` + +## Hardware monitoring and fan control + +There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share +a single fan tachometer input on the Super I/O while some dedicated logic +selects which one is allowed to reach it. Two GPIO pins on the Super I/O are +used to control that logic. The firmware has to set them; coreboot selects +CPU_FAN1 by default, but the user can change that setting if it was built with +CONFIG_USE_OPTION_TABLE: + +``` +$ sudo nvramtool -e cpu_fan_header +[..] +$ sudo nvramtool -w cpu_fan_header=CPU_FAN2 +$ sudo nvramtool -w cpu_fan_header=None +$ sudo nvramtool -w cpu_fan_header=Both +``` + +The setting will take effect after a reboot. Selecting and connecting both fan +headers is possible but the Super I/O will report wrong fan speeds. + +Currently there is no automatic, OS-independent fan control, but a software +like `fancontrol` from the lm-sensors package can be used instead. + +## Serial port header + +Serial port 1, provided by the Super I/O, is exposed on a pin header. The +RS-232 signals are assigned to the header so that its pin numbers map directly +to the pin numbers of a DE-9 connector. If your serial port doesn't seem to +work, check if your bracket expects a different assignment. Also don't try to +connect it directly to a device that operates at TTL levels - it would need a +level converter like a MAX232. + +Here is a top view of the serial port header found on this board: + + +---+---+ + N/C | | 9 | RI -> pin 9 + +---+---+ + Pin 8 <- CTS | 8 | 7 | RTS -> pin 7 + +---+---+ + Pin 6 <- DSR | 6 | 5 | GND -> pin 5 + +---+---+ + Pin 4 <- DTR | 4 | 3 | TxD -> pin 3 + +---+---+ + Pin 2 <- RxD | 2 | 1 | DCD -> pin 1 + +---+---+ + +## eSATA + +The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share +the same controller port on the ASM1061. Attaching an eSATA drive causes a +multiplexer chip to disconnect the internal port from the SATA controller and +connect the eSATA port instead. This can be seen on GP23 of the Super I/O +GPIOs: it is '0' when something is connected to the eSATA port and '1' +otherwise. diff --git a/Documentation/mainboard/emulation/qemu-power9.md b/Documentation/mainboard/emulation/qemu-power9.md new file mode 100644 index 0000000000..be7a8398e7 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-power9.md @@ -0,0 +1,52 @@ +# QEMU PPC64 emulator +This page describes how to build and run coreboot for QEMU/PPC64. + +## Building coreboot +```bash +make defconfig KBUILD_DEFCONFIG=configs/config.emulation_qemu_power9 +make +``` + +This builds coreboot with no payload. + +## Payloads +You can configure ELF or `skiboot` payload via `make menuconfig`. In either case +you might need to adjust "ROM chip size" and make it large enough to accommodate +the payload (see how much space it needs in the error you get if it doesn't +fit). + +## Running coreboot in QEMU +```bash +qemu-system-ppc64 -M powernv,hb-mode=on \ + -cpu power9 \ + -bios build/coreboot.rom \ + -drive file=build/coreboot.rom,if=mtd \ + -serial stdio \ + -display none +``` + +- The default CPU in QEMU for AArch64 is a 604. You specify a suitable +PowerPC CPU via `-cpu power9`. +- By default Hostboot mode is off and needs to be turned on to run coreboot +as a firmware rather than like an OS. +- `-bios` specifies initial program (bootloader should suffice, but whole image +works fine too). +- `-drive` specifies image for emulated flash device. + +## Running with a kernel +Loading `skiboot` (built automatically by coreboot or otherwise) allows +specifying kernel and root file system to be run. + +```bash +qemu-system-ppc64 -M powernv,hb-mode=on \ + -cpu power9 \ + -bios build/coreboot.rom \ + -drive file=build/coreboot.rom,if=mtd \ + -serial stdio \ + -display none \ + -kernel zImage \ + -initrd initrd.cpio.xz +``` + +- Specify path to your kernel via `-kernel`. +- Specify path to your rootfs via `-initrd`. diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md index e711ef3126..1c72d6c542 100644 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -5,10 +5,7 @@ This page describes how to run coreboot on the Facebook FBG1701. FBG1701 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory - Rev 1.3 Onboard Kingston B5116ECMDXGGB memory - -Use make menuconfig to configure `onboard memory manufacturer Samsung` in -Mainboard menu. + Rev 1.3 and 1.4 Onboard Kingston B5116ECMDXGGB memory ## Required blobs diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 9b8220ed8e..67af86f058 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -6,11 +6,16 @@ This section contains documentation about coreboot on specific mainboards. - [X210](51nb/x210.md) +## Acer + +- [G43T-AM3](acer/g43t-am3.md) + ## AMD - [padmelon](amd/padmelon/padmelon.md) ## ASRock +- [H77 Pro4-M](asrock/h77pro4-m.md) - [H81M-HDS](asrock/h81m-hds.md) - [H110M-DVS](asrock/h110m-dvs.md) @@ -172,6 +177,10 @@ The boards in this section are not real mainboards, but emulators. - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) +## Star Labs Systems + +- [StarBook Mk V](starlabs/starbook_tgl.md) + ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 8906ad89b0..3f8053848f 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -7,7 +7,16 @@ Delta Lake server platform. OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both [Delta Lake server design spec] and [Yosemite-V3 design -spec] were contributed to [OCP]. +spec] were [OCP] accepted. + +On the other hand, Wiwynn's Yosemite-V3 system and Delta Lake server product +along with its OSF implementation, which is based on FSP/coreboot/LinuxBoot +stack, was [OCP] accepted; For details, check: +- [The OCP blog] +- [The Wiwynn Press Release] +- [The Wiwynn's Yosemite-V3 product in OCP market place] +Wiwynn and 9Elements formed a partnership to offer the Wiwynn's Yosemite-V3 +product and OSF for it. Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server. Intel Cooper Lake Scalable Processor was launched in Q2 2020. @@ -15,7 +24,7 @@ Intel Cooper Lake Scalable Processor was launched in Q2 2020. Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers (blades) in one sled. -The Yosemite-V3 system is in mass production. Facebook, Intel and partners +The Yosemite-V3 system is in mass production. Meta, Intel and partners jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The OSF solution reached production quality for some use cases in July, 2021. @@ -187,6 +196,9 @@ and [u-root] as initramfs. [OCP]: https://www.opencompute.org [Delta Lake server design spec]: https://www.opencompute.org/documents/delta-lake-1s-server-design-specification-1v05-pdf [Yosemite-V3 design spec]: https://www.opencompute.org/documents/ocp-yosemite-v3-platform-design-specification-1v16-pdf +[The OCP blog]: https://www.opencompute.org/blog/open-system-firmware-for-ocp-server-deltalake-is-published +[The Wiwynn Press Release]: https://www.prnewswire.com/news-releases/wiwynn-successfully-implemented-open-system-firmware-on-its-ocp-yosemite-v3-server-301417374.html?tc=eml_cleartime +[The Wiwynn's Yosemite-V3 product in OCP market place]: https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server [osf-builder]: https://github.com/facebookincubator/osf-builder [OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule [flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/starlabs/BiosLock.jpg b/Documentation/mainboard/starlabs/BiosLock.jpg new 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b/Documentation/mainboard/starlabs/starbook_tgl.md new file mode 100644 index 0000000000..b69073c2e8 --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_tgl.md @@ -0,0 +1,154 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-1165G7 (Tiger Lake) + - Intel i3-1110G4 (Tiger Lake) +- EC + - ITE IT5570E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - eDP 14-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR4 SODIMM +- Networking + - AX201 2230 WiFi / Bluetooth +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - Thunderbolt 4.0 (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + - USB 2.0 Type-A (right) + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ + +#### **Requirements:** + +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. +![fwupd version](fwupdVersion.png) +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1\. Start with your LabTop turned off\. Turn it on whilst holding the **F2** key to access the BIOS settings. +2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\. +3\. Press `Enter` to change this setting from **Enabled** to **Disabled** + +![Disable BIOS Lock](BiosLock.jpg) + +4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: +![Switch Branch](SwitchBranch.png) +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 40589a1234..4f2b00e153 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -142,7 +142,7 @@ primarily to serve the needs of the server market. coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory. This release has support for SkyLake-SP (SKX-SP) which is the 2nd -generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation +generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation or the latest generation [2] on market. With this release, the codebase for multiple generations of Xeon-SP diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md index 97ed37c0ad..087513e34e 100644 --- a/Documentation/releases/coreboot-4.15-relnotes.md +++ b/Documentation/releases/coreboot-4.15-relnotes.md @@ -1,18 +1,22 @@ -Upcoming release - coreboot 4.15 +coreboot 4.15 ================================ -The 4.15 release is planned for November 1st, 2021. +coreboot 4.15 was released on November 5th, 2021. -Since 4.14 there have been more than 2448 new commits by more than 219 developers. +Since 4.14 there have been more than 2597 new commits by more than 219 developers. Of these, over 73 contributed to coreboot for the first time. Welcome to the project! - - Thank you to all the developers who continue to make coreboot the great open source firmware project that it is. +Important Announcement +---------------------- +We are going to be changing the cadence from every 6 months, to every 3 months. +That means the 4.16 release will be coming in February, 2022. + + New mainboards -------------- * Asus p8h61-m_pro_cm6630 @@ -23,11 +27,19 @@ New mainboards * Siemens mc_ehl * SuperMicro x9sae * System76 addw1 +* System76 addw2 +* System76 bonw14 * System76 darp6 * System76 darp7 +* System76 galp2 +* System76 galp3 +* System76 galp3-b * System76 galp4 * System76 galp5 +* System76 gaze14 * System76 lemp10 +* System76 oryp7 +* System76 oryp8 Removed mainboards ------------------ diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md index 16a57273d2..3abf72865d 100644 --- a/Documentation/releases/coreboot-4.16-relnotes.md +++ b/Documentation/releases/coreboot-4.16-relnotes.md @@ -1,16 +1,340 @@ -Upcoming release - coreboot 4.16 -================================ +coreboot 4.16 +======================================================================== -The 4.16 release is planned for May 2022. +The 4.16 release was done on February 25th, 2022. -Update this document with changes that should be in the release notes. +Since 4.15 there have been more than 1770 new commits by more than 170 +developers. Of these, more than 35 contributed to coreboot for the +first time. -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +Welcome to the project! + +Thank you to all the developers who continue to make coreboot the +great open source firmware project that it is. + +New mainboards: +--------------- +* Acer Aspire VN7-572G +* AMD Chausie +* ASROCK H77 Pro4-M +* ASUS P8Z77-M +* Emulation QEMU power9 +* Google Agah +* Google Anahera4ES +* Google Banshee +* Google Beadrix +* Google Brya4ES +* Google Crota +* Google Dojo +* Google Gimble4ES +* Google Herobrine_Rev0 +* Google Kingler +* Google Kinox +* Google Krabby +* Google Moli +* Google Nereid +* Google Nivviks +* Google Primus4ES +* Google Redrix4ES +* Google Skyrim +* Google Taeko4ES +* Google Taniks +* Google Vell +* Google Volmar +* Intel Alderlake-N RVP +* Prodrive Atlas +* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7) +* System76 gaze16 3050 +* System76 gaze16 3060 +* System76 gaze16 3060-b + +Removed mainboards: +------------------- +* Google -> Corsola +* Google -> Nasher +* Google -> Stryke + +Added processors: +----------------- +* src/cpu/power9 +* src/soc/amd/sabrina + +Submodule Updates +----------------- +* /3rdparty/amd_blobs (6 commits) +* /3rdparty/arm-trusted-firmware (965 commits) +* /3rdparty/blobs (30 commits) +* /3rdparty/chromeec (2212 commits) +* /3rdparty/intel-microcode (1 commits) +* /3rdparty/qc_blobs (13 commits) +* /3rdparty/vboot (44 commits) + +Plans to move platform support to a branch: +------------------------------------------- +After the 4.18 release in November 2022, we plan to move support for any +boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was +introduced more than a year ago and with minor changes most platforms +were able to work just fine with it. A major difference is that V3 uses +just one continuous region below 4G to allocate all PCI memory BAR's. V4 +uses all available space below 4G and if asked to, also above 4G too. +This makes it important that SoC code properly reports all fixed +resources. + +Currently only AGESA platforms have issues with it. On Gerrit both +attempts to fix AMD AGESA codebases to use V4 and compatibility modes +inside the V4 allocator have been proposed, but both efforts seem +stalled. See the (not yet merged) documentation +[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's +details. It looks like properly reporting all fixed resources is the +issue. + +At this point, we are not specifying which platforms this will include +as there are a number of patches to fix these issues in flight. +Hopefully, all platforms will end up being migrated to the v4 resource +allocator so that none of the platforms need to be supported on the +branch. + +Additionally, even if the support for the platform is moved to a branch, +it can be brought back to ToT if they're fixed to support the v4 +allocator. + +Plans for Code Deprecation +-------------------------- +As of release 4.18 (November 2022) we plan to deprecate LEGACY_SMP_INIT. +This also includes the codepath for SMM_ASEG. This code is used to start +APs and do some feature programming on each AP, but also set up SMM. +This has largely been superseded by PARALLEL_MP, which should be able to +cover all use cases of LEGACY_SMP_INIT, with little code changes. The +reason for deprecation is that having 2 codepaths to do the virtually +the same increases maintenance burden on the community a lot, while also +being rather confusing. + +A few things are lacking in PARALLEL_MP init: +- Support for !CONFIG_SMP on single core systems. It's likely easy to + extend PARALLEL_MP or write some code that just does CPU detection on + the BSP CPU. +- Support SMM in the legacy ASEG (0xa0000 - 0xb0000) region. A POC + showed that it's not that hard to do with PARALLEL_MP + https://review.coreboot.org/c/coreboot/+/58700 + +No platforms in the tree have any hardware limitations that would block +migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase. Significant changes ------------------- +This is, of course, not a complete list of all changes in the 4.16 +coreboot release, but a sampling of some of the more interesting and +significant changes. -### Add significant changes here +### Option to disable Intel Management Engine +Disable the Intel (Converged Security) Management Engine ((CS)ME) via +HECI based on Intel Core processors from Skylake to Alder Lake. State is +set based on a CMOS value of `me_state`. A value of `0` will result in a +(CS)ME state of `0` (working) and value of `1` will result in a (CS)ME +state of `3` (disabled). For an example CMOS layout and more info, see +[cse.c](../../src/soc/intel/common/block/cse/cse.c). + + +### Add [AMD] apcb_v3_edit tool +apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject +up to 16 SPDs into an existing APCB. The APCB must have a magic number +at the top of each SPD slot. + + +### Allow enable/disable ME via CMOS +Add .enable method that will set the CSME state. The state is based on +the new CMOS option me_state, with values of 0 and 1. The method is very +stable when switching between different firmware platforms. + +This method should not be used in combination with USE_ME_CLEANER. + +State 1 will result in: +ME: Current Working State : 4 +ME: Current Operation State : 1 +ME: Current Operation Mode : 3 +ME: Error Code : 2 + +State 0 will result in: +ME: Current Working State : 5 +ME: Current Operation State : 1 +ME: Current Operation Mode : 0 +ME: Error Code : 0 + + +### Move LAPIC configuration to MP init +Implementation for setup_lapic() did two things -- call enable_lapic() +and virtual_wire_mode_init(). + +In PARALLEL_MP case enable_lapic() was redundant as it was already +executed prior to initialize_cpu() call. For the !PARALLEL_MP case +enable_lapic() is added to AP CPUs. + + +### Add ANSI escape sequences for highlighting +Add ANSI escape sequences to highlight a log line based on its loglevel +to the output of "interactive" consoles that are meant to be displayed +on a terminal (e.g. UART). This should help make errors and warnings +stand out better among the usual spew of debug messages. For users whose +terminal or use case doesn't support these sequences for some reason (or +who simply don't like them), they can be disabled with a Kconfig. + +While ANSI escape sequences can be used to add color, minicom (the +presumably most common terminal emulator for UART endpoints?) doesn't +support color output unless explicitly enabled (via -c command line +flag), and other terminal emulators may have similar restrictions, so in +an effort to make this as widely useful by default as possible I have +chosen not to use color codes and implement this highlighting via +bolding, underlining and inverting alone (which seem to go through in +all cases). If desired, support for separate color highlighting could be +added via Kconfig later. + + +### Add cbmem_dump_console +This function is similar to cbmem_dump_console_to_uart except it uses +the normally configured consoles. A console_paused flag was added to +prevent the cbmem console from writing to itself. + + +### Add coreboot-configurator +A simple GUI to change CMOS settings in coreboot's CBFS, via the +nvramtool utility. Testing on Debian, Ubuntu and Manjaro with coreboot +4.14+, but should work with any distribution or coreboot release that +has an option table. For more info, please check the +[README](https://web.archive.org/web/20220225194308/https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/coreboot-configurator/README.md). + + +### Update live ISO configs to NixOS 21.11 +Update configs so that they work with NixOS 21.11. Drop `iasl` package +since it was replaced with `acpica-tools`. + + +### Move to U-Boot v2021.10 +Move to building the latest U-Boot. + + +### Support systems with >128 cores +Each time the spinlock is acquired a byte is decreased and then the +sign of the byte is checked. If there are more than 128 cores the sign +check will overflow. An easy fix is to increase the word size of the +spinlock acquiring and releasing. + + +### Add [samsung] sx9360 [proximity sensor] driver +Add driver for setting up Semtech sx9360 SAR sensor. +The driver is based on sx9310.c. The core of the driver is the same, but +the bindings are slightly different. + +Registers are documented [in the kernel tree:](https://web.archive.org/web/20220225182803/https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/) +Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml + + +### Add driver for Genesys Logic [SD Controller] GL9750 +The device is a PCIe Gen1 to SD 3.0 card reader controller to be +used in the Chromebook. The datasheet name is GL9750S and the revision +is 01. + +The patch disables ASPM L0s. + + +### Add support for Realtek RT8125 +The Realtek RT8168 and RT8125 have a similar programming interface, +therefore add the PCI device ID for the RT8125 into driver for support. + + +### Add Fibocom 5G WWAN ACPI support +Support PXSX._RST and PXSX.MRST._RST for warm and cold reset. +PXSX._RST is invoked on driver removal. + +build dependency: + soc/intel/common/block/pcie/rtd3 + +This driver will use the rtd3 methods for the same parent in the device +tree. The rtd3 chip needs to be added on the same root port in the +devicetree separately. + + +### Fix bug in vr_config +The `cpu_get_power_max()` function returns the TDP in milliwatts, but +the vr_config code interprets the value in watts. Divide the value by +1000 to fix this. + +This also fixes an integer overflow when `cpu_get_power_max()` returns +a value greater than 65535 (UINT16_MAX). + + +### Make mixed topology work +When using a mixed memory topology with DDR4, it's not possible to boot +when no DIMMs are installed, even though memory-down is available. This +happens because the DIMM SPD length defaults to 256 when no DIMM SPD is +available. Relax the length check when no DIMMs are present to overcome +this problem. + + +### Add FSP 2.3 support +FSP 2.3 specification introduces following changes: + +1. FSP_INFO_HEADER changes + Updated SpecVersion from 0x22 to 0x23 + Updated HeaderRevision from 5 to 6 + Added ExtendedImageRevision + FSP_INFO_HEADER length changed to 0x50 + +2. Added FSP_NON_VOLATILE_STORAGE_HOB2 + +Following changes are implemented in the patch to support FSP 2.3: + +- Add Kconfig option +- Update FSP build binary version info based on ExtendedImageRevision + field in header +- New NV HOB related changes will be pushed as part of another patch + + +### Join hash calculation for verification and measurement +This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT +is enabled from the lookup step into the code where a file is actually +loaded or mapped from flash. This has the advantage that CBFS routines +which just look up a file to inspect its metadata (e.g. cbfs_get_size()) +do not cause the file to be measured twice. It also removes the existing +inefficiency that files are loaded twice when measurement is enabled +(once to measure and then again when they are used). When CBFS +verification is enabled and uses the same hash algorithm as the TPM, we +are even able to only hash the file a single time and use the result for +both purposes. + + +### Skip FSP Notify APIs +Alder Lake SoC deselects Kconfigs as below: +- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT +- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +to skip FSP notify APIs (Ready to boot and End of Firmware) and make +use of native coreboot driver to perform SoC recommended operations +prior booting to payload/OS. + +Additionally, created a helper function `heci_finalize()` to keep HECI +related operations separated for easy guarding again config. + +TODO: coreboot native implementation to skip FSP notify phase API (post +pci enumeration) is still WIP. + + +### Add support for PCIe Resizable BARs +Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can +indicates support for "Resizable BARs" via a PCIe extended capability. + +When support this capability is indicated by the device, the size of +each BAR is determined in a different way than the normal "moving +bits" method. Instead, a pair of capability and control registers is +allocated in config space for each BAR, which can be used to both +indicate the different sizes the device is capable of supporting for +the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and +to also inform the device of the size that the allocator actually +reserved for the MMIO range. + +This patch adds a Kconfig for a mainboard to select if it knows that it +will have a device that requires this support during PCI enumeration. +If so, there is a corresponding Kconfig to indicate the maximum number +of bits of address space to hand out to devices this way (again, limited +by what devices can support and each individual system may want to +support, but just like above, this number can range from 20 to 63) If +the device can support more bits than this Kconfig, the resource request +is truncated to the number indicated by this Kconfig. diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md new file mode 100644 index 0000000000..4c2a1d56de --- /dev/null +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -0,0 +1,19 @@ +Upcoming release - coreboot 4.17 +================================ + +The 4.17 release is planned for May, 2022. + +We are continuing the quarterly release cadence in order to enable others to +release quarterly on a fresher version of coreboot. + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 157f631f57..e783802fb9 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -16,6 +16,7 @@ Release notes for previous releases * [4.13 - November 2020](coreboot-4.13-relnotes.md) * [4.14 - May 2021](coreboot-4.14-relnotes.md) * [4.15 - November 2021](coreboot-4.15-relnotes.md) +* [4.16 - Feb 2022](coreboot-4.16-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -23,8 +24,13 @@ names etc. * [checklist](checklist.md) +For release related communications consider using a template so everything +important is taken care of. + +* [templates](templates.md) + Upcoming release ---------------- Please add to the release notes as changes are added: -* [4.16 - May 2022](coreboot-4.16-relnotes.md) +* [4.17 - May 2022](coreboot-4.17-relnotes.md) diff --git a/Documentation/releases/templates.md b/Documentation/releases/templates.md new file mode 100644 index 0000000000..86973eb7a3 --- /dev/null +++ b/Documentation/releases/templates.md @@ -0,0 +1,83 @@ +# Communication templates related to release management + +## Deprecation notices + +Deprecation notices are part of release notes to act as a warning: at some +point in the future some part of coreboot gets removed. That point must be +at least 6 months after the release of the notice and it must be right after +some release: That is, the specified release must still contain the part in +question while one git commit later it might be removed. + +The usual reason is progress: Infrastructure module X has been replaced by +infrastructure module X+1. Removing X helps keep the sources manageable +and likely opens opportunities to improve the codebase even more. +Sometimes everything using some module has been converted to its successor +already and it's natural for such modules to be removed. Even then it might +be useful to add an entry to the release notes to make everybody aware of +such a change, for maintainers of incomplete boards that they might keep in +their local trees and also to give credit to the developers of that change. + +However this template isn't about such cases. Sometimes the tree contains +mainboards that rely on X and can't be easily migrated to X+1, often because +no active developer has access to these mainboards, and that is where this +type of deprecation notice comes in: + +A deprecation notice shall outline what is being removed, when it is planned +for removal (always directly _after_ a future release so it remains clear when +something is part of coreboot and when it isn't anymore) and which devices +would be affected at the time of writing. Since past deprecation notices have +been read as "we plan to remove mainboards A, B, and C", sparking outrage +with the devoted users of A, B, or C, some care is necessary to make clear +which parts are slated for removal and which parts are merely consequences +if no action is taken. Or put differently: It should be obvious that besides +the deprecation plan, there is a call to action to save a couple of devices +from becoming officially unsupported. + +As such, consider the following template when announcing a deprecation: + +### The Thing to remove + +A short description of the Thing slated for removal. + +A short rationale why it's being removed (e.g. new and better Thing exists +in parallel; new Thing already demonstrated to work in this many releases; +removing Thing enables this or that improvement) + +Timeline: Announced here, Thing will be removed right after the release X +months out (where X >= 6) + +#### Call to action + +Removing Thing requires work on a number of (boards, chipsets, …) that didn't +make the switch yet. The work approximately looks like this: (e.g. pointers to +commits where a board has been successfully migrated from Thing to new Thing). + +Working on migrating away from Thing involves (hardware components, coreboot +systems, …) 1, 2, and 3. It's difficult to do on the remaining devices because +... + +Parts of the tree that need work to become independent of Thing. + - chipset A + - board A1 + - board A2 + - chipset B + - board B1 + +We prefer to move them along, but if we don't see any maintenance in our tree +we'll have to assume that there's no more interest in these platforms. As a +consequence these devices either have to work without Thing by the removal +date or they will be removed together with Thing. (side note: these removals +aren't the law, so if there's work in progress to move boards off X and a +roadmap that makes it probable to succeed, just not within the announced +deprecation timeline, we can still decide to postpone the actual removal by +one release. This needn't be put in the release notes themselves though or +it might encourage people to look for simple escape hatches.) + +(If there are developers offering to write patches: ) +There are developers interested in helping move these forward but they can't +test any changes for lack of equipment. If you have an affected device and +can run tests on it, please reach out to developers α, β, and γ. + +(Otherwise maybe something more generic like this: ) +If you want to take this on, the coreboot developer community will try to +help you: Reach out through one of our [forums](../community/forums.md). diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 685f63703a..75d20eeb39 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -1,6 +1,7 @@ # vboot-enabled devices ## AMD +- Chausie - Majolica ## Clevo @@ -29,8 +30,37 @@ - Panther (ASUS Chromebox CN60) - Tricky (Dell Chromebox 3010) - Zako (HP Chromebox G1) +- Agah +- Anahera +- Anahera4ES +- Brask +- Brya 0 +- Brya4ES +- Felwinter +- Gimble +- Gimble4ES +- Kano +- Nivviks +- Nereid +- Primus +- Primus4ES +- Redrix +- Redrix4ES +- Taeko +- Taeko4ES +- Taniks +- Vell +- Volmar +- Banshee +- Crota +- Moli +- Kinox - Butterfly (HP Pavilion Chromebook 14) - Cherry +- Dojo +- Tomato +- Kingler +- Krabby - Banon (Acer Chromebook 15 (CB3-532)) - Celes (Samsung Chromebook 3) - Cyan (Acer Chromebook R11 (C738T)) @@ -66,60 +96,68 @@ - Nefario - Rainier - Guybrush -- Akemi -- Dratini -- Duffy Legacy (32MB) -- Duffy -- Faffy -- Hatch -- Jinlon -- Kaisa Legacy (32MB) -- Kaisa -- Kohaku -- Kindred -- Helios -- Mushu -- Palkia -- Nightfury -- Noibat -- Puff -- Helios_Diskswap -- Stryke -- Wyvern -- Dooly +- Nipperkin +- Dewatt +- Akemi (IdeaPad Flex 5/5i Chromebook) - Ambassador +- Dooly +- Dratini (HP Pro c640 Chromebook) +- Duffy Legacy (32MB) +- Duffy (ASUS Chromebox 4) +- Faffy (ASUS Fanless Chromebox) - Genesis +- Hatch +- Helios (ASUS Chromebook Flip C436FA) +- Helios_Diskswap +- Jinlon (HP Elite c1030 Chromebook) +- Kaisa Legacy (32MB) +- Kaisa (Acer Chromebox CXI4) +- Kindred (Acer Chromebook 712) +- Kohaku (Samsung Galaxy Chromebook) +- Moonbuggy +- Mushu +- Nightfury (Samsung Galaxy Chromebook 2) +- Noibat (HP Chromebox G3) +- Palkia +- Puff +- Scout +- Wyvern (CTL Chromebox CBx2) - Herobrine +- Herobrine_Rev0 +- Senor +- Piglin +- Hoglin - Guado (ASUS Chromebox CN62) - Jecht - Rikku (Acer Chromebox CXI2) - Tidus (Lenovo ThinkCentre Chromebox) -- Aleena -- Careena +- Aleena/Kasumi (Acer Chromebook 315 (CB315-2H), 311 (C721) / Spin 311 (R721T)) +- Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6) - Grunt -- Liara +- Liara (Lenovo 14e Chromebook, Chromebook S345-14) - Nuwani -- Treeya +- Treeya (Lenovo 100e/300e Gen2 AMD) - Kukui -- Krane -- Kodama +- Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook) +- Kodama (Lenovo 10e Chromebook Tablet) - Kakadu - Flapjack - Katsu - Jacuzzi -- Juniper +- Juniper (Acer Chromebook Spin 311 (CP311-3H)) - Kappa -- Damu +- Damu (ASUS Chromebook Flip CM3 (CM3200)) - Cerise - Stern - Willow -- Esche -- Burnet +- Esche (HP Chromebook 11MK G9 EE) +- Burnet (HP Chromebook x360 11MK G3 EE) - Fennel - Cozmo - Makomo +- Munna +- Pico - Link (Google Chromebook Pixel (2013)) -- Mancomb - Mistral - Nyan - Nyan Big (Acer Chromebook 13 (CB5-311)) @@ -132,7 +170,7 @@ - Atlas (Google Pixelbook Go) - Poppy - Nami -- Nautilus (Samsung Chromebook Plus (V2 / LTE)) +- Nautilus (Samsung Chromebook Plus V2, V2 LTE) - Nocturne (Google Pixel Slate) - Rammus (Asus Chromebook C425, Flip C433, Flip C434) - Soraka (HP Chromebook x2) @@ -156,10 +194,9 @@ - Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook) - Sand (Acer Chromebook 15 CB515-1HT/1H) - Snappy (HP Chromebook x360 11 G1 EE) -- Nasher - Coral -- Arcada -- Sarien +- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise) +- Sarien (Dell Latitude 5400 Chromebook Enterprise) - Falco (HP Chromebook 14) - Leon (Toshiba Chromebook) - Peppy (Acer C720/C720P Chromebook) @@ -177,8 +214,8 @@ - Pazquel - Pompom - Quackingstick -- Trogdor - Wormdingler +- Trogdor - Veyron_Jaq (Haier Chromebook 11) - Veyron_Jerry (Hisense Chromebook 11) - Veyron_Mighty (Haier Chromebook 11(edu)) @@ -187,15 +224,15 @@ - Veyron_Mickey (Asus Chromebit CS10) - Veyron_Rialto - Dalboz -- Vilboz -- Ezkinil -- Morphius +- Vilboz (Lenovo 100e/300e Gen3 AMD) +- Ezkinil (Acer Chromebook Spin 514) +- Morphius (Lenovo ThinkPad C13 Yoga Chromebook) - Trembyle -- Berknip -- Woomax -- Dirinboz +- Berknip (HP Pro c645 Chromebook Enterprise) +- Woomax (ASUS Chromebook Flip CM5) +- Dirinboz (HP Chromebook 14a-nd0097nr) - Shuboz -- Gumboz +- Gumboz (HP Chromebook x360 14a) ## HP - Z220 SFF Workstation @@ -203,8 +240,11 @@ ## Intel - Alderlake-P RVP - Alderlake-P RVP with Chrome EC +- Alderlake-P RVP with Microchip EC - Alderlake-M RVP - Alderlake-M RVP with Chrome EC +- Alderlake-N RVP +- Alderlake-N RVP with Chrome EC - Basking Ridge CRB - Coffeelake U SO-DIMM DDR4 RVP - Coffeelake H SO-DIMM DDR4 RVP11 diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44beea..feeb5e9433 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,18 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into +coreboot, e.g. on how to configure a board in devicetree when that affects +the way FSP works: + +* It should be possible to replace FSP based boot with a native coreboot + implementation for a given chipset without touching the mainboard code. +* The devicetree configures coreboot and part of what coreboot does with the + information is setting some FSP UPDs. The devicetree isn't supposed to + directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md index e91ebc3abb..009d3293f0 100644 --- a/Documentation/superio/nuvoton/nct5539d.md +++ b/Documentation/superio/nuvoton/nct5539d.md @@ -1,9 +1,9 @@ -# NCT5539D SuperIO +# NCT5539D Super I/O -The SuperIO has the ID `0xd121` and the source can be found in +The Super I/O has the ID `0xd121` and the source can be found in `src/superio/nuvoton/nct5539d/`. ## For developers -The SuperIO generates ACPI using the +The Super I/O generates ACPI using the [SSDT generator for generic SuperIOs](../common/ssdt.md). diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index 4ac857473d..f24b0b6ec7 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -12,37 +12,24 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your username for the account will be the username of the account you used to sign-in with. (ex. your Google username). -## Step 2a: Set up RSA Private/Public Key +## Step 2a: Set up SSH keys If you prefer to use an HTTP password instead, skip to Step 2b. -For the most up-to-date instructions on how to set up SSH keys with Gerrit go to - -and follow the instructions there. Then, skip to Step 3. - -Additionally, that section of the Web site provides explanation on starting -an ssh-agent, which may be particularly helpful for those who anticipate -frequently uploading changes. - -If you instead prefer to have review.coreboot.org specific instructions, -follow the steps below. Note that this particular section may have the -most up-to-date instructions. - -If you do not have an RSA key set up on your account already (as is the case +If you do not have an SSH key set up on your account already (as is the case with a newly created account), follow the instructions below; otherwise, doing so could overwrite an existing key. -In the upper right corner, select your name and click on **Settings**. -Select **SSH Public Keys** on the left-hand side. - -In a terminal, run `ssh-keygen` and confirm the default path `.ssh/id_rsa`. +In a terminal, run `ssh-keygen -t ed25519` and confirm the default path +`.ssh/id_ed25519`. Make a passphrase -- remember this phrase. It will be needed whenever you use -this RSA Public Key. **Note:** You might want to use a short password, or +this public key. **Note:** You might want to use a short password, or forego the password altogether as you will be using it very often. -Open `id_rsa.pub`, copy all contents and paste into the textbox under -"Add SSH Public Key" in the https://review.coreboot.org webpage. +Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix +as you need to send the public key) into the textbox "New SSH Key" at +https://review.coreboot.org/settings/#SSHKeys and save it. ## Step 2b: Set up an HTTP Password @@ -173,7 +160,9 @@ When you are done with your commit, run `git push` to push your commit to coreboot.org. **Note:** To submit as a private patch, use `git push origin HEAD:refs/for/master%private`. Submitting as a private patch means that your commit will be on review.coreboot.org, but is only visible to -yourself and those you add as reviewers. +yourself and those you add as reviewers. This mode isn't perfect: Somebody who +knows the commit ID can still fetch the change and everything it refers (e.g. +parent commits). This has been a quick primer on how to submit a change to Gerrit for review using git. You may wish to review the [Gerrit code review workflow diff --git a/Documentation/util.md b/Documentation/util.md index 8c6bcb7fca..b618dccc44 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -12,6 +12,8 @@ settings. `Perl` * __apcb__ - AMD PSP Control Block tools * _apcb_edit.py_ - This tool allows patching an existing APCB binary with specific SPDs and GPIO selection pins. `Python3` + * _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3 +binary with specific SPDs. `Python3` * __archive__ - Concatenate files and create an archive `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` diff --git a/MAINTAINERS b/MAINTAINERS index 84e855c4d5..a8d279c739 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,7 +141,9 @@ AMD family 17h and 19h reference boards M: Marshall Dawson M: Felix Held M: Jason Glenesk +M: Fred Reitberger S: Maintained +F: src/mainboard/amd/chausie/ F: src/mainboard/amd/majolica/ F: src/mainboard/amd/mandolin/ @@ -219,25 +221,18 @@ F: src/mainboard/clevo/ FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks -M: Wim Vervoorn +M: Erik van den Bogaert S: Maintained F: src/mainboard/facebook/fbg1701/ FACEBOOK MONOLITH MAINBOARD M: Frans Hendriks -M: Wim Vervoorn +M: Erik van den Bogaert S: Maintained F: src/mainboard/facebook/monolith/ -GETAC P470 MAINBOARD -M: Patrick Georgi -S: Maintained -F: src/mainboard/getac/p470/ - - - GIGABYTE GA-D510UD MAINBOARD M: Angel Pons S: Maintained @@ -401,7 +396,7 @@ F: src/mainboard/pcengines/ PORTWELL PQ-M107 MAINBOARD M: Frans Hendriks -M: Wim Vervoorn +M: Erik van den Bogaert S: Maintained F: src/mainboard/portwell/m107/ @@ -451,6 +446,13 @@ F: src/mainboard/siemens/mc_apl1/ +STAR LABS MAINBOARDS +M: Sean Rhodes +S: Maintained +F: src/mainboard/starlabs/ + + + SYSTEM76 MAINBOARDS M: Jeremy Soller M: Tim Crawford @@ -523,6 +525,11 @@ M: Alexander Couzens S: Maintained F: src/ec/lenovo/ +STARLABS EC +M: Sean Rhodes +S: Maintained +F: src/ec/starlabs/ + SYSTEM76 EC M: Jeremy Soller M: Tim Crawford @@ -607,6 +614,7 @@ M: Marshall Dawson M: Felix Held M: Jason Glenesk M: Raul E Rangel +M: Fred Reitberger S: Maintained F: src/soc/amd/cezanne/ F: src/vendorcode/amd/fsp/cezanne/ @@ -616,6 +624,7 @@ M: Marshall Dawson M: Felix Held M: Jason Glenesk M: Raul E Rangel +M: Fred Reitberger S: Maintained F: src/soc/amd/common/ @@ -624,10 +633,21 @@ M: Marshall Dawson M: Felix Held M: Jason Glenesk M: Raul E Rangel +M: Fred Reitberger S: Maintained F: src/soc/amd/picasso/ F: src/vendorcode/amd/fsp/picasso/ +AMD Sabrina +M: Marshall Dawson +M: Felix Held +M: Jason Glenesk +M: Raul E Rangel +M: Fred Reitberger +S: Maintained +F: src/soc/amd/sabrina/ +F: src/vendorcode/amd/fsp/sabrina/ + AMD Stoneyridge M: Marshall Dawson M: Felix Held @@ -719,7 +739,6 @@ F: payloads/external/LinuxBoot/ ################################################################################ ABUILD -M: Patrick Georgi M: Martin Roth S: Supported F: util/abuild/ @@ -728,7 +747,6 @@ BOARD STATUS F: util/board_status/ BUILD SYSTEM -M: Patrick Georgi M: Martin Roth S: Supported F: Makefile @@ -752,7 +770,6 @@ F: .git* F: /util/gitconfig LINT SCRIPTS -M: Patrick Georgi M: Martin Roth S: Supported F: util/lint/ @@ -876,7 +893,7 @@ F: *.ld ELTAN VENDORCODE M: Frans Hendriks -M: Wim Vervoorn +M: Erik van den Bogaert S: Maintained F: src/vendorcode/eltan/ @@ -890,6 +907,7 @@ TESTS M: Jakub Czapiga S: Maintained F: tests/ +F: payloads/libpayload/tests/ MISSING: TIMERS / DELAYS @@ -927,7 +945,6 @@ MISSING: SPI CODE OF CONDUCT M: Stefan Reinauer -M: Patrick Georgi M: Ronald Minnich M: Martin Roth S: Maintained diff --git a/Makefile b/Makefile index 97ed805a67..a9fbe98fe4 100644 --- a/Makefile +++ b/Makefile @@ -20,17 +20,6 @@ VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib) COREBOOT_EXPORTS := COREBOOT_EXPORTS COREBOOT_EXPORTS += top src srck obj objutil objk -# reproducible builds -LANG:=C -LC_ALL:=C -TZ:=UTC0 -ifneq ($(NOCOMPILE),1) -SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p') -endif -# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system -# are reproducible -export LANG LC_ALL TZ SOURCE_DATE_EPOCH - DOTCONFIG ?= $(top)/.config KCONFIG_CONFIG = $(DOTCONFIG) KCONFIG_AUTOADS := $(obj)/cb-config.ads @@ -63,6 +52,7 @@ ifneq ($(V),1) ifneq ($(Q),) .SILENT: MAKEFLAGS += -s +quiet_errors := 2>/dev/null endif endif @@ -175,6 +165,17 @@ $(error $(xcompile) deleted because it's invalid. \ Restarting the build should fix that, or explain the problem) endif +# reproducible builds +LANG:=C +LC_ALL:=C +TZ:=UTC0 +ifneq ($(NOCOMPILE),1) +SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p') +endif +# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system +# are reproducible +export LANG LC_ALL TZ SOURCE_DATE_EPOCH + ifneq ($(CONFIG_MMX),y) CFLAGS_x86_32 += -mno-mmx endif diff --git a/Makefile.inc b/Makefile.inc index b784f3eee8..f58418951b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -189,29 +189,29 @@ ramstage-generic-ccopts += -D__RAMSTAGE__ ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif - ifneq ($(UPDATED_SUBMODULES),1) # try to fetch non-optional submodules if the source is under git -forgetthis:=$(if $(GIT),$(shell git submodule update --init)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init $(quiet_errors))) # Checkout Cmocka repository -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))) ifeq ($(CONFIG_USE_BLOBS),y) # These items are necessary because each has update=none in .gitmodules. They are ignored # until expressly requested and enabled with --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))) ifeq ($(CONFIG_FSP_USE_REPO),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))) endif ifeq ($(CONFIG_USE_AMD_BLOBS),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))) endif ifeq ($(CONFIG_USE_QC_BLOBS),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))) endif endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES + endif postcar-c-deps:=$$(OPTION_TABLE_H) @@ -263,15 +263,24 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150 # Redundant offset remarks are not useful in any way and are masking useful # ones that might indicate an issue so it is better to hide them. REDUNDANT_OFFSET_REMARK = 2158 -# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code. -# See cb:38802 -# "Multiple types (Device object requires either a _HID or _ADR, but not both)" -MULTIPLE_TYPES_WARNING = 3073 +# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: +# 1) If _PRS is present, must have _CRS and _SRS +# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) +# 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) +# 4) If _SRS is present, probably should have a _DIS (Remark only) +# A warning will be issued for each of these cases. +# For existing ASL code, ignore this warnings +IASL_MISSING_DEPENDENCY = 3141 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK) -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) -IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING) +ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y) + IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY) +build_complete:: + printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n" + printf "*** If _PRS is present, must have _CRS and _SRS ***\n" + printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n" + printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n" endif IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST)) @@ -280,6 +289,9 @@ define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml $(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw $(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +$(CONFIG_CBFS_PREFIX)/$(1).aml-align = 64 +endif cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml -include $(obj)/$(1).d $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @@ -441,6 +453,7 @@ ADAFLAGS_common += -pipe -g -nostdinc ADAFLAGS_common += -Wstrict-aliasing -Wshadow ADAFLAGS_common += -fno-common -fomit-frame-pointer ADAFLAGS_common += -ffunction-sections -fdata-sections +ADAFLAGS_common += -fno-pie # Ada warning options: # # a Activate most optional warnings. @@ -588,6 +601,8 @@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py +APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage FUTILITY?=$(objutil)/futility/futility @@ -1214,6 +1229,10 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +$(CONFIG_CBFS_PREFIX)/ramstage-align := 64 +endif cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB) diff --git a/configs/config.emulation_qemu_power9 b/configs/config.emulation_qemu_power9 new file mode 100644 index 0000000000..7f64ee8506 --- /dev/null +++ b/configs/config.emulation_qemu_power9 @@ -0,0 +1 @@ +CONFIG_BOARD_EMULATION_QEMU_POWER9=y diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index 85f5499986..3cff03389d 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -8,3 +8,4 @@ CONFIG_DEBUG_PIRQ=y CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_BOOT_STATE=y CONFIG_DEBUG_ADA_CODE=y +CONFIG_CPU_QEMU_X86_PARALLEL_MP=y diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index 08f0c70347..49354a8188 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,6 +1,5 @@ CONFIG_VENDOR_FACEBOOK=y CONFIG_BOARD_FACEBOOK_FBG1701=y -CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04" diff --git a/configs/config.google_trogdor.build_test b/configs/config.google_trogdor.build_test new file mode 100644 index 0000000000..88c0dd04fc --- /dev/null +++ b/configs/config.google_trogdor.build_test @@ -0,0 +1,8 @@ +# Config to build test some optional Kconfigs on an Arm platform +CONFIG_USE_BLOBS=y +CONFIG_USE_QC_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_TROGDOR=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_PAYLOAD_NONE=y diff --git a/configs/config.google_volteer.build_test_purposes b/configs/config.google_volteer.build_test_purposes index 8531b79ea7..6843aeb289 100644 --- a/configs/config.google_volteer.build_test_purposes +++ b/configs/config.google_volteer.build_test_purposes @@ -30,3 +30,4 @@ CONFIG_DEBUG_MALLOC=y CONFIG_DEBUG_CONSOLE_INIT=y CONFIG_DEBUG_SPI_FLASH=y CONFIG_DEBUG_BOOT_STATE=y +CONFIG_CBFS_VERIFICATION=y diff --git a/configs/config.prodrive_hermes b/configs/config.prodrive_hermes new file mode 100644 index 0000000000..34556cc3be --- /dev/null +++ b/configs/config.prodrive_hermes @@ -0,0 +1,13 @@ +# Settings used by Prodrive to build coreboot for the Hermes +CONFIG_VENDOR_PRODRIVE=y +CONFIG_BOARD_PRODRIVE_HERMES=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V." +CONFIG_POST_IO=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_HERMES_USES_SPS_FIRMWARE=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_V2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y +CONFIG_POST_DEVICE_LPC=y +CONFIG_MAINBOARD_SERIAL_NUMBER="N/A" diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index d89b5ba503..a182bd65ad 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -28,6 +28,7 @@ payloads/external/tianocore \ payloads/external/GRUB2 \ payloads/external/LinuxBoot \ payloads/external/Yabits \ +payloads/external/skiboot \ force-payload: @@ -48,5 +49,16 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) +ifeq ($(CONFIG_PAYLOAD_NONE),y) +files_added:: warn_no_payload +endif + +warn_no_payload: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without a payload. Writing\n" + printf "a coreboot image without a payload to your board's\n" + printf "flash chip will result in a non-booting system. You\n" + printf "can use cbfstool to add a payload to the image.\n\n" + .PHONY: force-payload coreinfo nvramcui -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload diff --git a/payloads/external/.gitignore b/payloads/external/.gitignore index ebca42908b..9aaa95c038 100644 --- a/payloads/external/.gitignore +++ b/payloads/external/.gitignore @@ -8,3 +8,5 @@ tint/tint/ U-Boot/u-boot/ Memtest86Plus/memtest86plus/ iPXE/ipxe/ +skiboot/skiboot +skiboot/build diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index b8c2d570d0..e805a07b0a 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -136,22 +136,29 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D # Tianocore -payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG) +$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG) $(MAKE) -C payloads/external/tianocore all \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ - CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \ - CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ - CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \ - CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ + CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \ + CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \ CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ - CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ + CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ + CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ + CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \ CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \ + CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ + CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ - CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ + CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \ + CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \ + CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \ + CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \ + CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ + CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ @@ -161,6 +168,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI OBJCOPY_arm=$(OBJCOPY_arm) \ OBJCOPY_arm64=$(OBJCOPY_arm64) \ MFLAGS= MAKEFLAGS= + mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@ # FILO @@ -197,8 +205,9 @@ payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 # U-Boot -payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) +payloads/external/U-Boot/build/u-boot.bin u-boot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ + STABLE_COMMIT_ID=$(CONFIG_UBOOT_STABLE_COMMIT_ID) \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) @@ -331,3 +340,10 @@ payloads/external/Yabits/uefi/build/uefi.elf yabits: payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf: $(MAKE) -C payloads/external/BOOTBOOT all + +# skiboot + +payloads/external/skiboot/build/skiboot.elf: + $(MAKE) -C payloads/external/skiboot all \ + CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \ + CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION) diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index 9e51ae17cc..06b4b73849 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -3,13 +3,18 @@ if PAYLOAD_UBOOT config PAYLOAD_SPECIFIC_OPTIONS def_bool y select PAYLOAD_IS_FLAT_BINARY + select WANT_LINEAR_FRAMEBUFFER + +config UBOOT_STABLE_COMMIT_ID + string + default "v2021.07" choice prompt "U-Boot version" default UBOOT_STABLE config UBOOT_STABLE - bool "v2019.4" + bool "v2021.07" help Stable U-Boot version @@ -32,9 +37,9 @@ config PAYLOAD_CONFIGFILE from the U-Boot config directory config PAYLOAD_FILE - default "payloads/external/U-Boot/u-boot/u-boot-dtb.bin" + default "payloads/external/U-Boot/build/u-boot.bin" config PAYLOAD_OPTIONS - default "-l 0x1110000 -e 0x1110015" + default "-l 0x1110000 -e 0x1110000" endif diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 38dfe99a0e..07b6f48609 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -1,15 +1,15 @@ ## SPDX-License-Identifier: GPL-2.0-only -# 2019-4 tag -STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066 - TAG-$(CONFIG_UBOOT_MASTER)=origin/master TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID) project_name=U-Boot project_dir=u-boot project_git_repo=http://git.denx.de/u-boot.git -project_config_file=$(project_dir)/.config +project_build_dir=build +project_config_file=$(project_build_dir)/.config + +make_args=-C $(project_dir) O=../build unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -23,7 +23,7 @@ all: build $(project_dir): echo " Cloning $(project_name) from Git" - git clone $(project_git_repo) $(project_dir) + git clone $(project_git_repo) -b $(TAG-y) $(project_dir) fetch: $(project_dir) ifeq ($(CONFIG_UBOOT_MASTER),y) @@ -31,11 +31,11 @@ ifeq ($(CONFIG_UBOOT_MASTER),y) git fetch #master doesn't get a file, so it's continuously updated - rm -f $(project_dir)/$(STABLE_COMMIT_ID) + rm -f $(STABLE_COMMIT_ID) else cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ]; \ then echo " Fetching new commits from the $(project_name) git repo"; git fetch; fi - touch $(project_dir)/$(STABLE_COMMIT_ID) + touch $(STABLE_COMMIT_ID) endif checkout: fetch @@ -43,26 +43,26 @@ checkout: fetch cd $(project_dir); git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y) config: checkout + mkdir -p $(project_build_dir) rm -f $(project_config_file) ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") cat $(CONFIG_PAYLOAD_CONFIGFILE)" > tag-$(project_config_file) + $(MAKE) $(make_args) olddefconfig else echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist" false endif else - cat $(project_dir)/configs/coreboot_defconfig >> $(project_config_file) + $(MAKE) $(make_args) coreboot_defconfig endif - $(MAKE) -C $(project_dir) olddefconfig - build: config echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir) + $(MAKE) $(make_args) clean: - test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0 + test -d $(project_dir) && $(MAKE) $(make_args) clean || exit 0 distclean: rm -rf $(project_dir) diff --git a/payloads/external/skiboot/Kconfig b/payloads/external/skiboot/Kconfig new file mode 100644 index 0000000000..3198358ecb --- /dev/null +++ b/payloads/external/skiboot/Kconfig @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if PAYLOAD_SKIBOOT + +config PAYLOAD_FILE + default "payloads/external/skiboot/build/skiboot.elf" + +config SKIBOOT_GIT_REPO + string "Git repository of skiboot payload" + default "https://github.com/open-power/skiboot" + help + Git repository which will be used to clone skiboot. + +config SKIBOOT_REVISION + string "Revision of skiboot payload" + default "d93ddbd39b4eeac0bc11dacbdadea76df2996c13" if BOARD_EMULATION_QEMU_POWER9 + help + Revision, that skiboot repository will be checked out to, before building + an image. + +endif # PAYLOAD_SKIBOOT diff --git a/payloads/external/skiboot/Kconfig.name b/payloads/external/skiboot/Kconfig.name new file mode 100644 index 0000000000..92d47e1782 --- /dev/null +++ b/payloads/external/skiboot/Kconfig.name @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config PAYLOAD_SKIBOOT + bool "skiboot" + depends on ARCH_PPC64 + help + Select this option if you want to build a coreboot image + with a skiboot payload. diff --git a/payloads/external/skiboot/Makefile b/payloads/external/skiboot/Makefile new file mode 100644 index 0000000000..5cf630ea25 --- /dev/null +++ b/payloads/external/skiboot/Makefile @@ -0,0 +1,36 @@ +## SPDX-License-Identifier: GPL-2.0-only + +build_dir=$(CURDIR)/build +skiboot_dir=$(CURDIR)/skiboot +skiboot_git_repo=$(CONFIG_SKIBOOT_GIT_REPO) +skiboot_revision=$(CONFIG_SKIBOOT_REVISION) +skiboot_elf=$(build_dir)/skiboot.elf +skiboot_cross=$(or $(CROSS),powerpc64-linux-gnu-) + +unexport $(COREBOOT_EXPORTS) + +.PHONY: all clean distclean + +all: $(skiboot_elf) + +$(skiboot_elf): | $(skiboot_dir) $(build_dir) + +$(MAKE) -C $(skiboot_dir) CROSS="$(skiboot_cross)" + cp $(skiboot_dir)/skiboot.elf $@ + # skiboot is always built with debug information due to unconditional -ggdb + $(skiboot_cross)strip $@ + +$(skiboot_dir): + git clone $(skiboot_git_repo) $(skiboot_dir) + git -C $(skiboot_dir) checkout $(skiboot_revision) + +$(build_dir): + mkdir -p $(build_dir) + +distclean: clean + rm -rf $(skiboot_dir) + +clean: + # Redefine RM because it's used like `$(RM) non-existent-file` + # Also ignore useless messages about removing test files + [ ! -d $(skiboot_dir) ] || $(MAKE) -C $(skiboot_dir) RM="rm -rf" clean > /dev/null + rm -rf $(build_dir) diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index b7069aaddd..4194290747 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -2,7 +2,7 @@ if PAYLOAD_TIANOCORE config PAYLOAD_FILE string "Tianocore binary" - default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd" + default "$(obj)/UEFIPAYLOAD.fd" help The result of a UefiPayloadPkg build @@ -35,13 +35,30 @@ config TIANOCORE_COREBOOTPAYLOAD Select this option to build using MrChromebox's older (now deprecated) CorebootPayloadPkg-based Tianocore branch +config TIANOCORE_CUSTOM + bool "Custom" + help + Specify your own edk2 repository and branch to use. + endchoice -config TIANOCORE_REVISION_ID - string "Insert a commit's SHA-1 or a branch name" +config TIANOCORE_REPOSITORY + string "URL to git repository for edk2" + default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM + default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD help - The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master" - for master branch of Tianocore release on github. + coreboot supports an array of build options which can be found below. These options + will only have an effect if the relevant options exist in the target repository. + +config TIANOCORE_TAG_OR_REV + string "Insert a commit's SHA-1 or a branch name" + default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD + default "origin/master" if TIANOCORE_UPSTREAM + default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD + help + The commit's SHA-1 or branch name of the revision to use. This must exist in + TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e. + "origin/uefipayload_202202" choice prompt "Tianocore build" @@ -64,32 +81,33 @@ endchoice if TIANOCORE_UEFIPAYLOAD -config TIANOCORE_CBMEM_LOGGING - bool "Enable Tianocore logging to CBMEM" +config TIANOCORE_ABOVE_4G_MEMORY + bool "Enable above 4G memory" + default n help - Select this option if you want to enable Tianocore logging to CBMEM. - You may want to increase the default cbmem buffer size when selecting - this option, especially if using a debug (vs release) build. - Selecting this option will increase the payload size in CBFS by ~220KB. + Select this option to enable Above 4G Decode. This will allow the + payload to use all of the memory, rather than an maximum of 4G. -config TIANOCORE_BOOTSPLASH_IMAGE - bool "Use a custom bootsplash image" + Disabling memory above 4G is useful for bootloaders that are not + fully 64-bit aware such as Qubes R4.0.4 bootloader. + + +config TIANOCORE_BOOTSPLASH_FILE + string "Tianocore Bootsplash path and filename" + default "bootsplash.bmp" help Select this option if you have a bootsplash image that you would like to be used. If this option is not selected, the default coreboot logo (European Brown Hare) will used. -config TIANOCORE_BOOTSPLASH_FILE - string "Tianocore Bootsplash path and filename" - depends on TIANOCORE_BOOTSPLASH_IMAGE - default "bootsplash.bmp" - help The path and filename of the file to use as graphical bootsplash - image. The file must be an uncompressed BMP. + image. The file must be an uncompressed BMP, in BMP 3 format. + + Linux can create these with the below command: + `convert splosh.bmp BMP3:splash.bmp` This image will also be used as the BGRT boot image, which may - persist through your OS boot process, and will be displayed - vertically centered 38.2% from the top of the display. + persist through your OS boot process. See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and Microsoft's documentation on BGRT positioning: @@ -101,16 +119,61 @@ config TIANOCORE_BOOTSPLASH_FILE If an absolute path is not given, the path will assumed to be relative to the coreboot root directory. -config TIANOCORE_ABOVE_4G_MEMORY - bool "Enable above 4G memory" +config TIANOCORE_BOOT_MANAGER_ESCAPE + bool "Use Escape key for Boot Manager" default n help - Select this option to enable Above 4G Decode. This will allow the - payload to use all of the memory, rather than an maximum of 4G. + Use Escape as the hot-key to access the Boot Manager. This replaces + the default key of F2. - Disabling this option, which will reserve memory above 4G, is - useful for bootloaders that are not fully 64-bit aware such as - Qubes R4.0.4 bootloader. +config TIANOCORE_BOOT_TIMEOUT + int + default 2 + help + The length of time in seconds for which the boot splash/menu prompt will be displayed. + For boards with an internal display, the default value of 2s is generally sufficient. + For boards with an external display, a value of 5s is generally sufficient. + +config TIANOCORE_CBMEM_LOGGING + bool "Enable Tianocore logging to CBMEM" + help + Select this option if you want to enable Tianocore logging to CBMEM. + You may want to increase the default cbmem buffer size when selecting + this option, especially if using a debug (vs release) build. + Selecting this option will increase the payload size in CBFS by 0x10000. + +config TIANOCORE_FOLLOW_BGRT_SPEC + bool "Center logo 38.2% from the top of screen" + default n + help + Follow the BGRT Specification implemented by Microsoft and + the Boot Logo 38.2% will be vertically centered 38.2% from + the top of the display. + +config TIANOCORE_HAVE_EFI_SHELL + bool "Include EFI Shell" + default y + help + Include the EFI shell Binary + +config TIANOCORE_PRIORITIZE_INTERNAL + bool "Prioritize internal boot devices" + default y + help + Prioritize internal boot devices over external devices + +config TIANOCORE_PS2_SUPPORT + bool "Support PS/2 Keyboards" + default y + help + Include support for PS/2 keyboards + +config TIANOCORE_SD_MMC_TIMEOUT + int "Timeout in μs for initializing SD Card reader" + default 1000 + help + The amount of time allowed to initialize the SD Card reader and/or eMMC drive. + Most only require 1000μs, but certain readers can take 1000000μs. endif @@ -123,12 +186,4 @@ config TIANOCORE_USE_8254_TIMER endif -config TIANOCORE_BOOT_TIMEOUT - int - default 2 - help - The length of time in seconds for which the boot splash/menu prompt will be displayed. - For boards with an internal display, the default value of 2s is generally sufficient. - For boards without an internal display, a value of 5s is generally sufficient. - endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 0c5fdb3a52..873ef46cfe 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -3,84 +3,112 @@ # force the shell to bash - the edksetup.sh script doesn't work with dash export SHELL := env bash -project_name=Tianocore -project_dir=$(CURDIR)/tianocore -project_git_repo=https://github.com/mrchromebox/edk2 -project_git_branch=uefipayload_202107 -upstream_git_repo=https://github.com/tianocore/edk2 - -build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE +project_name = Tianocore +project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY))) +BUILD_STR = -a IA32 -a X64 -t COREBOOT ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) -project_git_branch=coreboot_fb -bootloader=CorebootPayloadPkg +BUILD_STR += -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc else -bootloader=UefiPayloadPkg +BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc +endif +BUILD_STR += -D BOOTLOADER=COREBOOT -q + +# +# EDK II has the following build options relevant to coreboot: +# +# +# OPTION = DEFAULT_VALUE +# +# ABOVE_4G_MEMORY = TRUE +ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y) +BUILD_STR += -D ABOVE_4G_MEMORY=FALSE +endif +# BOOTSPLASH_IMAGE = FALSE +ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),) +BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE +endif +# BOOT_MANAGER_ESCAPE = FALSE +ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y) +BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE +endif +# BUILD_TARGETS = DEBUG +ifeq ($(CONFIG_TIANOCORE_RELEASE),y) +BUILD_STR += -b RELEASE +endif +# FOLLOW_BGRT_SPEC = FALSE +ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y) +BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE +endif +# PRIORITIZE_INTERNAL = FALSE +ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y) +BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE +endif +# PS2_KEYBOARD_ENABLE = FALSE +ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y) +BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE +endif +# PLATFORM_BOOT_TIMEOUT = 3 +ifneq ($(TIANOCORE_BOOT_TIMEOUT),) +BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) +endif +# SIO_BUS_ENABLE = FALSE +ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y) +BUILD_STR += -D SIO_BUS_ENABLE=TRUE +endif +# SHELL_TYPE = BUILD_SHELL +ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y) +BUILD_STR += -D SHELL_TYPE=NONE +endif +# USE_CBMEM_FOR_CONSOLE = FALSE +ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) +BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE +endif +# SD_MMC_TIMEOUT = 1000000 +ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),) +BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) +endif +# +# The below are legacy options only available in CorebootPayloadPkg: +# +# PCIE_BASE = 0 +ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),) +BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) +endif +# USE_HPET_TIMER = FALSE +ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y) +BUILD_STR += -D USE_HPET_TIMER=TRUE endif -ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y) -TAG=upstream/master -else -TAG=origin/$(project_git_branch) -endif - -ifneq ($(CONFIG_TIANOCORE_REVISION_ID),) -TAG=$(CONFIG_TIANOCORE_REVISION_ID) -endif +bootloader = $(word 8,$(subst /, ,$(BUILD_STR))) export EDK_TOOLS_PATH=$(project_dir)/BaseTools -ifeq ($(CONFIG_TIANOCORE_DEBUG),y) -BUILD_TYPE=DEBUG -else -BUILD_TYPE=RELEASE -endif - -ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y) -CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE -endif - -ifeq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y) -4G=-D ABOVE_4G_MEMORY=TRUE -else -4G=-D ABOVE_4G_MEMORY=FALSE -endif - -TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) - -ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) -TIMER=-DUSE_HPET_TIMER -endif - -ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) -BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE -else -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) -endif - all: clean build $(project_dir): - echo " Cloning $(project_name) from Git" - git clone --branch $(project_git_branch) $(project_git_repo) $(project_dir); \ - cd $(project_dir); \ - git remote add upstream $(upstream_git_repo) + echo " Cloning $(project_name) from $(CONFIG_TIANOCORE_REPOSITORY)" + git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \ + cd $(project_dir); update: $(project_dir) + if [ ! -d "$(project_dir)" ]; then \ + git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \ + fi cd $(project_dir); \ - echo " Fetching new commits from the $(project_name) repo"; \ - git fetch --multiple origin upstream 2>/dev/null; \ - if ! git rev-parse --verify -q $(TAG) >/dev/null; then \ - echo " $(TAG) is not a valid git reference"; \ + echo " Fetching new commits from $(CONFIG_TIANOCORE_REPOSITORY)"; \ + git fetch origin 2>/dev/null; \ + if ! git rev-parse --verify -q $(CONFIG_TIANOCORE_TAG_OR_REV) >/dev/null; then \ + echo " $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \ exit 1; \ fi; \ if git status --ignore-submodules=dirty | grep -qv clean; then \ - echo " Checking out $(project_name) revision $(TAG)"; \ - git checkout --detach $(TAG); \ + echo " Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \ + git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \ else \ echo " Working directory not clean; will not overwrite"; \ fi; \ - git submodule update --init + git submodule update --init --checkout checktools: echo "Checking uuid-dev..." @@ -94,15 +122,15 @@ checktools: ( echo " Not found."; echo "Error: Please install nasm."; exit 1 ) build: update checktools - unset CC; $(MAKE) -C $(project_dir)/BaseTools - echo " build $(project_name) $(TAG)" + unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1 + echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)" if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ - /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ - *) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ + /*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ + BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ + *) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ + BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ esac \ fi; \ cd $(project_dir); \ @@ -114,13 +142,14 @@ build: update checktools cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + mkdir -p $(project_dir)/../output + mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \ git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 distclean: - rm -rf $(project_dir) + rm -rf */ .PHONY: all update checktools config build clean distclean diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 382f5af751..4f8896aa6e 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -208,11 +208,7 @@ config PDCURSES endchoice -config CBFS - bool "CBFS support" - default y - help - CBFS is the archive format of coreboot +source "libcbfs/Kconfig" config LZMA bool "LZMA decoder" @@ -227,6 +223,9 @@ config LZ4 help Decoder implementation for the LZ4 compression algorithm. Adds standalone functions (CBFS support coming soon). + +source "vboot/Kconfig" + endmenu menu "Console Options" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index ee83a0aeca..0104a11fbc 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -29,16 +29,23 @@ ## SUCH DAMAGE. ## +ifneq ($(words $(CURDIR)),1) + $(error ERROR: Path to the main directory cannot contain spaces) +endif + ifeq ($(INNER_SCANBUILD),y) CC_real:=$(CC) endif export top := $(CURDIR) +export coreboottop ?= $(abspath $(top)/../../) export src := src export srck := $(abspath $(top)/../../util/kconfig) export obj ?= build export objutil ?= $(obj)/util export objk := $(objutil)/lp_kconfig +export absobj := $(abspath $(obj)) +VBOOT_SOURCE ?= $(coreboottop)/3rdparty/vboot export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf @@ -289,9 +296,11 @@ includemakefiles= \ $(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \ $(foreach class,$(classes), \ $(eval $(class)-srcs+= \ + $$(subst $(absobj)/,$(obj)/, \ $$(subst $(top)/,, \ - $$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \ - $(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))) + $$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \ + $(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))) + # For each path in $(subdirs) call includemakefiles # Repeat until subdirs is empty @@ -310,8 +319,15 @@ else include $(TOPLEVEL)/tests/Makefile.inc endif -src-to-obj=$(addsuffix .$(1).o, $(basename $(addprefix $(obj)/, $($(1)-srcs)))) -$(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class)))) +# Converts one or more source file paths to the corresponding build/ paths. +# $1 lib name +# $2 file path (list) +src-to-obj=\ + $(addsuffix .$(1).o,\ + $(basename \ + $(addprefix $(obj)/,\ + $(subst $(coreboottop)/,coreboot/,$(2))))) +$(foreach class,$(classes),$(eval $(class)-objs+=$(call src-to-obj,$(class),$($(class)-srcs)))) allsrcs:=$(foreach var, $(addsuffix -srcs,$(classes)), $($(var))) allobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var))) @@ -325,7 +341,7 @@ define create_cc_template # $4 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template -$(obj)/$$(1).$(1).o: $$(1).$(2) $(obj)/libpayload-config.h $(4) +$$(call src-to-obj,$(1), $$(1).$(2)): $$(1).$(2) $(obj)/libpayload-config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC) $(3) -MMD $$$$(CFLAGS) $(EXTRA_CFLAGS) -c -o $$$$@ $$$$< en$(EMPTY)def @@ -340,7 +356,7 @@ $(foreach class,$(classes), \ foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(basename $(file))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) -DEPENDENCIES = $(allobjs:.o=.d) +DEPENDENCIES = $($(filter %.o,%(allobjs)):.o=.d) -include $(DEPENDENCIES) printall: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 8e0a3d6f77..430994b366 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -46,6 +46,8 @@ classes-$(CONFIG_LP_CBFS) += libcbfs classes-$(CONFIG_LP_LZMA) += liblzma classes-$(CONFIG_LP_LZ4) += liblz4 classes-$(CONFIG_LP_REMOTEGDB) += libgdb +classes-$(CONFIG_LP_VBOOT_LIB) += vboot_fw +classes-$(CONFIG_LP_VBOOT_LIB) += tlcl libraries := $(classes-y) classes-y += head.o @@ -55,9 +57,12 @@ subdirs-$(CONFIG_LP_CURSES) += curses subdirs-$(CONFIG_LP_CBFS) += libcbfs subdirs-$(CONFIG_LP_LZMA) += liblzma subdirs-$(CONFIG_LP_LZ4) += liblz4 +subdirs-$(CONFIG_LP_VBOOT_LIB) += vboot INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) INCLUDES += -include include/kconfig.h -include include/compiler.h +INCLUDES += -I$(coreboottop)/src/commonlib/bsd/include +INCLUDES += -I$(VBOOT_SOURCE)/firmware/include CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer @@ -90,11 +95,11 @@ includes-handler= \ $(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs)) printf " AR $(subst $(CURDIR)/,,$(@))\n" - $(AR) rc $@ $^ + printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M $(obj)/%.a: $$(%-objs) printf " AR $(subst $(CURDIR)/,,$(@))\n" - $(AR) rc $@ $^ + printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M $(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o printf " CP $(subst $(CURDIR)/,,$(@))\n" @@ -115,10 +120,24 @@ install: real-target install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \ install -m 644 $$file $(DESTDIR)/libpayload/$$file; \ done + for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \ + dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \ + install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \ + install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \ + done install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include $(foreach item,$(includes), \ install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \ install -m 644 $(call extract_nth,1,$(item)) $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); ) + printf " INSTALL $(DESTDIR)/libpayload/vboot\n" + install -m 755 -d $(DESTDIR)/libpayload/vboot + for file in `find $(VBOOT_SOURCE)/firmware/include \ + $(VBOOT_SOURCE)/firmware/2lib/include \ + -iname '*.h' -type f \ + | sed 's,$(VBOOT_SOURCE)/firmware/,,'`; do \ + install -m 755 -d $(DESTDIR)/libpayload/vboot/$$(dirname $$file); \ + install -m 644 $(VBOOT_SOURCE)/firmware/$$file $(DESTDIR)/libpayload/vboot/$$file ; \ + done printf " INSTALL $(DESTDIR)/libpayload/bin\n" install -m 755 -d $(DESTDIR)/libpayload/bin install -m 755 bin/lpgcc $(DESTDIR)/libpayload/bin diff --git a/payloads/libpayload/arch/mock/Makefile.inc b/payloads/libpayload/arch/mock/Makefile.inc index f15f0f9f1d..415886af60 100644 --- a/payloads/libpayload/arch/mock/Makefile.inc +++ b/payloads/libpayload/arch/mock/Makefile.inc @@ -5,3 +5,5 @@ head.o-y += head.c libc-y += virtual.c libcbfs-$(CONFIG_LP_CBFS) += mock_media.c + +CFLAGS += -Wno-address-of-packed-member diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 41228f2e12..e010329eba 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -42,6 +42,7 @@ libc-$(CONFIG_LP_GPL) += string.c libgdb-y += gdb.c libcbfs-$(CONFIG_LP_CBFS) += rom_media.c +libcbfs-$(CONFIG_LP_CBFS) += boot_media.c # Multiboot support is configurable libc-$(CONFIG_LP_MULTIBOOT) += multiboot.c diff --git a/payloads/libpayload/arch/x86/boot_media.c b/payloads/libpayload/arch/x86/boot_media.c new file mode 100644 index 0000000000..99fb4e3c2a --- /dev/null +++ b/payloads/libpayload/arch/x86/boot_media.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#include +#include +#include +#include +#include +#include + +__attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t size) +{ + /* Memory-mapping usually only works for the top 16MB. */ + if (!lib_sysinfo.boot_media_size || lib_sysinfo.boot_media_size - offset > 16 * MiB) + return CB_ERR_ARG; + const void *const ptr = phys_to_virt(0 - lib_sysinfo.boot_media_size + offset); + memcpy(buf, ptr, size); + return size; +} diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 38ede875c7..cad13963ec 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -47,20 +47,12 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) info->x86_rom_var_mtrr_index = rom_mtrr->index; } -static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) -{ - info->mrc_cache = get_cbmem_addr(ptr); -} - int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) { switch(rec->tag) { case CB_TAG_X86_ROM_MTRR: cb_parse_x86_rom_var_mtrr(rec, info); break; - case CB_TAG_MRC_CACHE: - cb_parse_mrc_cache(rec, info); - break; default: return 0; } diff --git a/payloads/libpayload/bin/lp.functions b/payloads/libpayload/bin/lp.functions index fd26956243..d641e69991 100644 --- a/payloads/libpayload/bin/lp.functions +++ b/payloads/libpayload/bin/lp.functions @@ -63,3 +63,9 @@ if [ -d $BASE/../include ]; then else _INCDIR=$LIBPAYLOAD_PREFIX/include fi + +if [ -d $BASE/../vboot ]; then + _VBOOTINCDIR=$BASE/../vboot/include +else + _VBOOTINCDIR=$LIBPAYLOAD_PREFIX/../vboot/include +fi diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 3a76f13d17..8bc46a6580 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -167,6 +167,11 @@ if [ $_LIBDIR = $_OBJ ]; then if [ "$CONFIG_LP_TINYCURSES" = y ]; then _CFLAGS="$_CFLAGS -I$BASE/../curses" fi + + _CFLAGS="$_CFLAGS -I$BASE/../../../src/commonlib/bsd/include" + _CFLAGS="$_CFLAGS -I$BASE/../../../3rdparty/vboot/firmware/include" +else + _CFLAGS="$_CFLAGS -I$_VBOOTINCDIR" fi # Check for the -fno-stack-protector silliness @@ -177,7 +182,7 @@ trygccoption -fno-stack-protector _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static" +_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then diff --git a/payloads/libpayload/include/assert.h b/payloads/libpayload/include/assert.h index 50847a3b47..2152af4f7a 100644 --- a/payloads/libpayload/include/assert.h +++ b/payloads/libpayload/include/assert.h @@ -29,6 +29,17 @@ #include #include +#ifdef __TEST__ + +/* CMocka function redefinition */ +void mock_assert(const int result, const char *const expression, const char *const file, + const int line); + +#define MOCK_ASSERT(result, expression) mock_assert((result), (expression), __FILE__, __LINE__) +#define assert(statement) MOCK_ASSERT(!!(statement), #statement) + +#else + // assert's existence depends on NDEBUG state on _last_ inclusion of assert.h, // so don't guard this against double-includes. #ifdef NDEBUG @@ -43,3 +54,5 @@ abort(); \ } #endif + +#endif /* __TEST__ */ diff --git a/payloads/libpayload/include/boot_device.h b/payloads/libpayload/include/boot_device.h new file mode 100644 index 0000000000..a946545792 --- /dev/null +++ b/payloads/libpayload/include/boot_device.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _BOOT_DEVICE_H +#define _BOOT_DEVICE_H + +#include + +/** + * This is a boot device access function, which is used by libpayload to read data from + * the flash memory (or other boot device). It has to be implemented by payloads that want + * to use FMAP or libcbfs. + * + * @param buf The output buffer to which the data should be written to. + * @param offset Absolute offset in bytes of the requested boot device memory area. Not aligned. + * @param size Size in bytes of the requested boot device memory area. Not aligned. + * + * @returns Number of bytes returned to the buffer, or negative value on error. Typically should + * be equal to the `size`, and not aligned forcefully. + */ +ssize_t boot_device_read(void *buf, size_t offset, size_t size); + +#endif /* _BOOT_DEVICE_H */ diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index ab23b02e03..23b96695ef 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -1,82 +1,146 @@ -/* - * - * Copyright (C) 2008 Jordan Crouse - * Copyright (C) 2013 Google, Inc. - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CBFS_H_ #define _CBFS_H_ -#include +#include +#include +#include +#include -/* legacy APIs */ -const struct cbfs_header *get_cbfs_header(void); -struct cbfs_file *cbfs_find(const char *name); -void *cbfs_find_file(const char *name, int type); -int cbfs_execute_stage(struct cbfs_media *media, const char *name); -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device); -void *cbfs_load_payload(struct cbfs_media *media, const char *name); -void *cbfs_load_stage(struct cbfs_media *media, const char *name); +/********************************************************************************************** + * CBFS FILE ACCESS APIs * + **********************************************************************************************/ -/* Simple buffer for streaming media. */ -struct cbfs_simple_buffer { - char *buffer; - size_t allocated; - size_t size; - size_t last_allocate; -}; +/* For documentation look in src/include/cbfs.h file in the main coreboot source tree. */ -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count); +static inline size_t cbfs_load(const char *name, void *buf, size_t size); +static inline size_t cbfs_ro_load(const char *name, void *buf, size_t size); +static inline size_t cbfs_unverified_area_load(const char *area, const char *name, void *buf, + size_t size); -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address); +static inline void *cbfs_map(const char *name, size_t *size_out); +static inline void *cbfs_ro_map(const char *name, size_t *size_out); +static inline void *cbfs_unverified_area_map(const char *area, const char *name, + size_t *size_out); -// Utility functions -int run_address(void *f); +void cbfs_unmap(void *mapping); -/* Defined in individual arch / board implementation. */ -int init_default_cbfs_media(struct cbfs_media *media); +static inline size_t cbfs_get_size(const char *name); +static inline size_t cbfs_ro_get_size(const char *name); + +static inline enum cbfs_type cbfs_get_type(const char *name); +static inline enum cbfs_type cbfs_ro_get_type(const char *name); + +static inline bool cbfs_file_exists(const char *name); +static inline bool cbfs_ro_file_exists(const char *name); + +/********************************************************************************************** + * INTERNAL HELPERS FOR INLINES, DO NOT USE. * + **********************************************************************************************/ +ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mdata); + +void *_cbfs_load(const char *name, void *buf, size_t *size_inout, bool force_ro); + +void *_cbfs_unverified_area_load(const char *area, const char *name, void *buf, + size_t *size_inout); + +/********************************************************************************************** + * INLINE IMPLEMENTATIONS * + **********************************************************************************************/ + +static inline void *cbfs_map(const char *name, size_t *size_out) +{ + return _cbfs_load(name, NULL, size_out, false); +} + +static inline void *cbfs_ro_map(const char *name, size_t *size_out) +{ + return _cbfs_load(name, NULL, size_out, true); +} + +static inline void *cbfs_unverified_area_map(const char *area, const char *name, + size_t *size_out) +{ + return _cbfs_unverified_area_load(area, name, NULL, size_out); +} + +static inline size_t cbfs_load(const char *name, void *buf, size_t size) +{ + if (_cbfs_load(name, buf, &size, false)) + return size; + else + return 0; +} + +static inline size_t cbfs_ro_load(const char *name, void *buf, size_t size) +{ + if (_cbfs_load(name, buf, &size, true)) + return size; + else + return 0; +} + +static inline size_t cbfs_unverified_area_load(const char *area, const char *name, void *buf, + size_t size) +{ + if (_cbfs_unverified_area_load(area, name, buf, &size)) + return size; + else + return 0; +} + +static inline size_t cbfs_get_size(const char *name) +{ + union cbfs_mdata mdata; + if (_cbfs_boot_lookup(name, false, &mdata) < 0) + return 0; + else + return be32toh(mdata.h.len); +} + +static inline size_t cbfs_ro_get_size(const char *name) +{ + union cbfs_mdata mdata; + if (_cbfs_boot_lookup(name, true, &mdata) < 0) + return 0; + else + return be32toh(mdata.h.len); +} + +static inline enum cbfs_type cbfs_get_type(const char *name) +{ + union cbfs_mdata mdata; + if (_cbfs_boot_lookup(name, false, &mdata) < 0) + return CBFS_TYPE_NULL; + else + return be32toh(mdata.h.type); +} + +static inline enum cbfs_type cbfs_ro_get_type(const char *name) +{ + union cbfs_mdata mdata; + if (_cbfs_boot_lookup(name, true, &mdata) < 0) + return CBFS_TYPE_NULL; + else + return be32toh(mdata.h.type); +} + +static inline bool cbfs_file_exists(const char *name) +{ + union cbfs_mdata mdata; + return _cbfs_boot_lookup(name, false, &mdata) >= 0; +} + +static inline bool cbfs_ro_file_exists(const char *name) +{ + union cbfs_mdata mdata; + return _cbfs_boot_lookup(name, true, &mdata) >= 0; +} + + +/* Legacy API. Designated for removal in the future. */ +#include #endif diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index fc4caa4417..4a638d971a 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -45,139 +45,14 @@ #ifndef _CBFS_CORE_H_ #define _CBFS_CORE_H_ +#include #include #include #include #include -/** These are standard values for the known compression - alogrithms that coreboot knows about for stages and - payloads. Of course, other CBFS users can use whatever - values they want, as long as they understand them. */ - -#define CBFS_COMPRESS_NONE 0 -#define CBFS_COMPRESS_LZMA 1 -#define CBFS_COMPRESS_LZ4 2 - -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_TYPE_STAGE 0x10 -#define CBFS_TYPE_SELF 0x20 -#define CBFS_TYPE_FIT 0x21 -#define CBFS_TYPE_OPTIONROM 0x30 -#define CBFS_TYPE_BOOTSPLASH 0x40 -#define CBFS_TYPE_RAW 0x50 -#define CBFS_TYPE_VSA 0x51 -#define CBFS_TYPE_MBI 0x52 -#define CBFS_TYPE_MICROCODE 0x53 -#define CBFS_TYPE_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -#define CBFS_HEADER_MAGIC 0x4F524243 -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 -#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 - #define CBFS_HEADER_INVALID_ADDRESS ((void*)(0xffffffff)) -/* this is the master cbfs header - it must be located somewhere available - * to bootblock (to load romstage). The last 4 bytes in the image contain its - * relative offset from the end of the image (as a 32-bit signed integer). */ - -struct cbfs_header { - uint32_t magic; - uint32_t version; - uint32_t romsize; - uint32_t bootblocksize; - uint32_t align; /* fixed to 64 bytes */ - uint32_t offset; - uint32_t architecture; - uint32_t pad[1]; -} __packed; - -/* this used to be flexible, but wasn't ever set to something different. */ -#define CBFS_ALIGNMENT 64 - -/* "Unknown" refers to CBFS headers version 1, - * before the architecture was defined (i.e., x86 only). - */ -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 -#define CBFS_ARCHITECTURE_ARM64 0x00000011 - -/** This is a component header - every entry in the CBFS - will have this header. - - This is how the component is arranged in the ROM: - - -------------- <- 0 - component header - -------------- <- sizeof(struct component) - component name - -------------- <- offset - data - ... - -------------- <- offset + len -*/ - -#define CBFS_FILE_MAGIC "LARCHIVE" - -struct cbfs_file { - char magic[8]; - uint32_t len; - uint32_t type; - uint32_t attributes_offset; - uint32_t offset; - char filename[]; -} __packed; - -/* Depending on how the header was initialized, it may be backed with 0x00 or - * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ - -/* The common fields of extended cbfs file attributes. - Attributes are expected to start with tag/len, then append their - specific fields. */ -struct cbfs_file_attribute { - uint32_t tag; - /* len covers the whole structure, incl. tag and len */ - uint32_t len; - uint8_t data[0]; -} __packed; - -struct cbfs_file_attr_compression { - uint32_t tag; - uint32_t len; - /* whole file compression format. 0 if no compression. */ - uint32_t compression; - uint32_t decompressed_size; -} __packed; - -struct cbfs_file_attr_hash { - uint32_t tag; - uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; -} __packed; - -/*** Component sub-headers ***/ - -/* Following are component sub-headers for the "standard" - component types */ - -/** This is the sub-header for stage components. Stages are - loaded by coreboot during the normal boot process */ - struct cbfs_stage { uint32_t compression; /** Compression type */ uint64_t entry; /** entry point */ @@ -186,33 +61,6 @@ struct cbfs_stage { uint32_t memlen; /** total length of object in memory */ } __packed; -/** this is the sub-header for payload components. Payloads - are loaded by coreboot at the end of the boot process */ - -struct cbfs_payload_segment { - uint32_t type; - uint32_t compression; - uint32_t offset; - uint64_t load_addr; - uint32_t len; - uint32_t mem_len; -} __packed; - -struct cbfs_payload { - struct cbfs_payload_segment segments; -}; - -#define PAYLOAD_SEGMENT_CODE 0x45444F43 -#define PAYLOAD_SEGMENT_DATA 0x41544144 -#define PAYLOAD_SEGMENT_BSS 0x20535342 -#define PAYLOAD_SEGMENT_PARAMS 0x41524150 -#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 - -struct cbfs_optionrom { - uint32_t compression; - uint32_t len; -} __packed; - #define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) diff --git a/payloads/libpayload/include/cbfs_glue.h b/payloads/libpayload/include/cbfs_glue.h new file mode 100644 index 0000000000..00d0ea943a --- /dev/null +++ b/payloads/libpayload/include/cbfs_glue.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _CBFS_CBFS_GLUE_H +#define _CBFS_CBFS_GLUE_H + +#include +#include +#include + +#define CBFS_ENABLE_HASHING CONFIG(LP_CBFS_VERIFICATION) + +#define ERROR(...) printf("CBFS ERROR: " __VA_ARGS__) +#define LOG(...) printf("CBFS: " __VA_ARGS__) +#define DEBUG(...) \ + do { \ + if (CONFIG(LP_DEBUG_CBFS)) \ + printf("CBFS DEBUG: " __VA_ARGS__); \ + } while (0) + +struct cbfs_dev { + size_t offset; + size_t size; +}; + +struct cbfs_boot_device { + struct cbfs_dev dev; + void *mcache; + size_t mcache_size; +}; + +typedef const struct cbfs_dev *cbfs_dev_t; + +static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size) +{ + if (offset + size < offset || offset + size > dev->size) + return CB_ERR_ARG; + + return boot_device_read(buffer, dev->offset + offset, size); +} + +static inline size_t cbfs_dev_size(cbfs_dev_t dev) +{ + return dev->size; +} + +#endif /* _CBFS_CBFS_GLUE_H */ diff --git a/payloads/libpayload/include/cbfs_legacy.h b/payloads/libpayload/include/cbfs_legacy.h new file mode 100644 index 0000000000..c98da0c112 --- /dev/null +++ b/payloads/libpayload/include/cbfs_legacy.h @@ -0,0 +1,82 @@ +/* + * + * Copyright (C) 2008 Jordan Crouse + * Copyright (C) 2013 Google, Inc. + * + * This file is dual-licensed. You can choose between: + * - The GNU GPL, version 2, as published by the Free Software Foundation + * - The revised BSD license (without advertising clause) + * + * --------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * --------------------------------------------------------------------------- + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * --------------------------------------------------------------------------- + */ + +#ifndef _CBFS_LEGACY_H_ +#define _CBFS_LEGACY_H_ + +#include + +/* legacy APIs */ +const struct cbfs_header *get_cbfs_header(void); +struct cbfs_file *cbfs_find(const char *name); +void *cbfs_find_file(const char *name, int type); + +int cbfs_execute_stage(struct cbfs_media *media, const char *name); +void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, + uint16_t device); +void *cbfs_load_payload(struct cbfs_media *media, const char *name); +void *cbfs_load_stage(struct cbfs_media *media, const char *name); + +/* Simple buffer for streaming media. */ +struct cbfs_simple_buffer { + char *buffer; + size_t allocated; + size_t size; + size_t last_allocate; +}; + +void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, + struct cbfs_media *media, + size_t offset, size_t count); + +void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, + const void *address); + +// Utility functions +int run_address(void *f); + +/* Defined in individual arch / board implementation. */ +int init_default_cbfs_media(struct cbfs_media *media); + +#endif diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 914cfa5683..3fd3fc85e1 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -321,6 +321,16 @@ struct cb_boot_media_params { uint64_t boot_media_size; }; + +struct cb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + struct cb_tsc_info { uint32_t tag; uint32_t size; @@ -443,6 +453,4 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -/* Helper functions */ -uintptr_t get_cbmem_addr(const void *cbmem_tab_entry); #endif diff --git a/payloads/libpayload/include/fmap.h b/payloads/libpayload/include/fmap.h new file mode 100644 index 0000000000..53ebe23dcb --- /dev/null +++ b/payloads/libpayload/include/fmap.h @@ -0,0 +1,12 @@ +/* SPDX_License-Identifier: BSD-3-Clause */ + +#ifndef _FMAP_H +#define _FMAP_H + +#include +#include + +/* Looks for area with |name| in FlashMap. Requires lib_sysinfo.fmap_cache. */ +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size); + +#endif /* _FMAP_H */ diff --git a/payloads/libpayload/include/fmap_serialized.h b/payloads/libpayload/include/fmap_serialized.h deleted file mode 100644 index 53a09af7a8..0000000000 --- a/payloads/libpayload/include/fmap_serialized.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2010, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#ifndef FLASHMAP_SERIALIZED_H__ -#define FLASHMAP_SERIALIZED_H__ - -#include - -#define FMAP_SIGNATURE "__FMAP__" -#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ -#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */ -#define FMAP_STRLEN 32 /* maximum length for strings, */ - /* including null-terminator */ - -enum fmap_flags { - FMAP_AREA_STATIC = 1 << 0, - FMAP_AREA_COMPRESSED = 1 << 1, - FMAP_AREA_RO = 1 << 2, - FMAP_AREA_PRESERVE = 1 << 3, -}; - -/* Mapping of volatile and static regions in firmware binary */ -struct fmap_area { - uint32_t offset; /* offset relative to base */ - uint32_t size; /* size in bytes */ - uint8_t name[FMAP_STRLEN]; /* descriptive name */ - uint16_t flags; /* flags for this area */ -} __packed; - -struct fmap { - uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */ - uint8_t ver_major; /* major version */ - uint8_t ver_minor; /* minor version */ - uint64_t base; /* address of the firmware binary */ - uint32_t size; /* size of firmware binary in bytes */ - uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */ - uint16_t nareas; /* number of areas described by - fmap_areas[] below */ - struct fmap_area areas[]; -} __packed; - -#endif /* FLASHMAP_SERIALIZED_H__ */ diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index e08d211983..8d8336f559 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -45,10 +45,11 @@ #include #include #include +#include #include #include #include -#include +#include #include #include #include @@ -457,6 +458,8 @@ static inline int clz(u32 x) static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */ +static inline int __fls(u32 x) { return log2(x); } static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) @@ -466,6 +469,7 @@ static inline int clz64(u64 x) static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } +static inline int __fls64(u64 x) { return log2_64(x); } /** @} */ /** diff --git a/payloads/libpayload/include/mock/arch/io.h b/payloads/libpayload/include/mock/arch/io.h index 2bb625562e..08c992f060 100644 --- a/payloads/libpayload/include/mock/arch/io.h +++ b/payloads/libpayload/include/mock/arch/io.h @@ -26,4 +26,21 @@ void write16(volatile void *addr, uint16_t val); void write32(volatile void *addr, uint32_t val); void write64(volatile void *addr, uint64_t val); +/* x86 I/O functions */ +unsigned int inl(int port); +unsigned short inw(int port); +unsigned char inb(int port); + +void outl(unsigned int val, int port); +void outw(unsigned short val, int port); +void outb(unsigned char val, int port); + +void outsl(int port, const void *addr, unsigned long count); +void outsw(int port, const void *addr, unsigned long count); +void outsb(int port, const void *addr, unsigned long count); + +void insl(int port, void *addr, unsigned long count); +void insw(int port, void *addr, unsigned long count); +void insb(int port, void *addr, unsigned long count); + #endif /* _ARCH_IO_H */ diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b34476d25e..376f298c77 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -150,6 +150,12 @@ struct sysinfo_t { #endif /* USB Type-C Port Configuration Info */ uintptr_t type_c_info; + + /* CBFS RW/RO Metadata Cache */ + uintptr_t cbfs_ro_mcache_offset; + uint32_t cbfs_ro_mcache_size; + uintptr_t cbfs_rw_mcache_offset; + uint32_t cbfs_rw_mcache_size; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bd1041166e..72d7664b1a 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -29,6 +29,7 @@ #include #include +#include #include #include @@ -41,12 +42,6 @@ /* === Parsing code === */ /* This is the generic parsing code. */ -uintptr_t get_cbmem_addr(const void *const cbmem_tab_entry) -{ - const struct cb_cbmem_tab *const cbmem = cbmem_tab_entry; - return cbmem->cbmem_tab; -} - static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { struct cb_memory *mem = ptr; @@ -83,11 +78,6 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) info->cb_serial = virt_to_phys(ptr); } -static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info) -{ - info->vboot_workbuf = get_cbmem_addr(ptr); -} - static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info) { struct lb_range *vbnv = (struct lb_range *)ptr; @@ -128,26 +118,6 @@ static void cb_parse_mac_addresses(unsigned char *ptr, info->macs[i] = macs->mac_addrs[i]; } -static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) -{ - info->tstamp_table = get_cbmem_addr(ptr); -} - -static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) -{ - info->cbmem_cons = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_gnvs = get_cbmem_addr(ptr); -} - -static void cb_parse_acpi_cnvs(unsigned char *ptr, struct sysinfo_t *info) -{ - info->acpi_cnvs = get_cbmem_addr(ptr); -} - static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { struct cb_board_config *const config = (struct cb_board_config *)ptr; @@ -188,11 +158,6 @@ static void cb_parse_string(const void *const ptr, uintptr_t *const info) *info = virt_to_phys(str->string); } -static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) -{ - info->wifi_calibration = get_cbmem_addr(ptr); -} - static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) { struct lb_range *ramoops = (struct lb_range *)ptr; @@ -236,21 +201,6 @@ static void cb_parse_boot_media_params(unsigned char *ptr, info->boot_media_size = bmp->boot_media_size; } -static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) -{ - info->chromeos_vpd = get_cbmem_addr(ptr); -} - -static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) -{ - info->fmap_cache = get_cbmem_addr(ptr); -} - -static void cb_parse_type_c_info(void *ptr, struct sysinfo_t *info) -{ - info->type_c_info = get_cbmem_addr(ptr); -} - #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -264,6 +214,57 @@ static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) } #endif +static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info) +{ + const struct cb_cbmem_entry *cbmem_entry = ptr; + + if (cbmem_entry->size != sizeof(*cbmem_entry)) + return; + + switch (cbmem_entry->id) { + case CBMEM_ID_ACPI_CNVS: + info->acpi_cnvs = cbmem_entry->address; + break; + case CBMEM_ID_ACPI_GNVS: + info->acpi_gnvs = cbmem_entry->address; + break; + case CBMEM_ID_CBFS_RO_MCACHE: + info->cbfs_ro_mcache_offset = cbmem_entry->address; + info->cbfs_ro_mcache_size = cbmem_entry->entry_size; + break; + case CBMEM_ID_CBFS_RW_MCACHE: + info->cbfs_rw_mcache_offset = cbmem_entry->address; + info->cbfs_rw_mcache_size = cbmem_entry->entry_size; + break; + case CBMEM_ID_CONSOLE: + info->cbmem_cons = cbmem_entry->address; + break; + case CBMEM_ID_MRCDATA: + info->mrc_cache = cbmem_entry->address; + break; + case CBMEM_ID_VBOOT_WORKBUF: + info->vboot_workbuf = cbmem_entry->address; + break; + case CBMEM_ID_TIMESTAMP: + info->tstamp_table = cbmem_entry->address; + break; + case CBMEM_ID_VPD: + info->chromeos_vpd = cbmem_entry->address; + break; + case CBMEM_ID_FMAP: + info->fmap_cache = cbmem_entry->address; + break; + case CBMEM_ID_WIFI_CALIBRATION: + info->wifi_calibration = cbmem_entry->address; + break; + case CBMEM_ID_TYPE_C_INFO: + info->type_c_info = cbmem_entry->address; + break; + default: + break; + } +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -372,33 +373,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; - case CB_TAG_VBOOT_WORKBUF: - cb_parse_vboot_workbuf(ptr, info); - break; case CB_TAG_MAC_ADDRS: cb_parse_mac_addresses(ptr, info); break; case CB_TAG_SERIALNO: cb_parse_string(ptr, &info->serialno); break; - case CB_TAG_TIMESTAMPS: - cb_parse_tstamp(ptr, info); - break; - case CB_TAG_CBMEM_CONSOLE: - cb_parse_cbmem_cons(ptr, info); - break; - case CB_TAG_ACPI_GNVS: - cb_parse_acpi_gnvs(ptr, info); - break; - case CB_TAG_ACPI_CNVS: - cb_parse_acpi_cnvs(ptr, info); - break; case CB_TAG_BOARD_CONFIG: cb_parse_board_config(ptr, info); break; - case CB_TAG_WIFI_CALIBRATION: - cb_parse_wifi_calibration(ptr, info); - break; case CB_TAG_RAM_OOPS: cb_parse_ramoops(ptr, info); break; @@ -414,20 +397,14 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_BOOT_MEDIA_PARAMS: cb_parse_boot_media_params(ptr, info); break; + case CB_TAG_CBMEM_ENTRY: + cb_parse_cbmem_entry(ptr, info); + break; #if CONFIG(LP_TIMER_RDTSC) case CB_TAG_TSC_INFO: cb_parse_tsc_info(ptr, info); break; #endif - case CB_TAG_VPD: - cb_parse_vpd(ptr, info); - break; - case CB_TAG_FMAP: - cb_parse_fmap_cache(ptr, info); - break; - case CB_TAG_TYPE_C_INFO: - cb_parse_type_c_info(ptr, info); - break; default: cb_parse_arch_specific(rec, info); break; diff --git a/payloads/libpayload/libc/fmap.c b/payloads/libpayload/libc/fmap.c index b7d64918ac..2d185a7c60 100644 --- a/payloads/libpayload/libc/fmap.c +++ b/payloads/libpayload/libc/fmap.c @@ -28,10 +28,60 @@ #include #include +#include #include #include -#include +#include #include +#include + +/* Private fmap cache. */ +static struct fmap *_fmap_cache; + +static cb_err_t fmap_find_area(struct fmap *fmap, const char *name, size_t *offset, + size_t *size) +{ + for (size_t i = 0; i < le32toh(fmap->nareas); ++i) { + if (strncmp((const char *)fmap->areas[i].name, name, FMAP_STRLEN) != 0) + continue; + if (offset) + *offset = le32toh(fmap->areas[i].offset); + if (size) + *size = le32toh(fmap->areas[i].size); + return CB_SUCCESS; + } + + return CB_ERR; +} + +static bool fmap_is_signature_valid(struct fmap *fmap) +{ + return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)) == 0; +} + +static bool fmap_setup_cache(void) +{ + /* Use FMAP cache if available */ + if (lib_sysinfo.fmap_cache + && fmap_is_signature_valid((struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache))) { + _fmap_cache = (struct fmap *)phys_to_virt(lib_sysinfo.fmap_cache); + return true; + } + + return false; +} + +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size) +{ + if (!_fmap_cache && !fmap_setup_cache()) + return CB_ERR; + + return fmap_find_area(_fmap_cache, name, offset, size); +} + +/*********************************************************************************************** + * LEGACY CODE * + **********************************************************************************************/ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, uint32_t * const offset, uint32_t * const size) diff --git a/payloads/libpayload/libcbfs/Kconfig b/payloads/libpayload/libcbfs/Kconfig new file mode 100644 index 0000000000..d5b24debf5 --- /dev/null +++ b/payloads/libpayload/libcbfs/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later + +config CBFS + bool "CBFS support" + default y + help + CBFS is the archive format of coreboot + +if CBFS + +config DEBUG_CBFS + bool "Output verbose CBFS debug messages" + default n + help + This option enables additional CBFS related debug messages. + +config ENABLE_CBFS_FALLBACK + bool "Fallback to RO (COREBOOT) region" + default n + help + When this option is enabled, the CBFS code will look for a file in the + RO (COREBOOT) region, if it isn't available in the active RW region. + This option makes sense only if CONFIG_VBOOT was enabled in the coreboot. + +config CBFS_VERIFICATION + bool "Enable CBFS verification" + depends on VBOOT_LIB + help + This option enables hash verification of CBFS files in RO (COREBOOT) and RW regions. + +endif diff --git a/payloads/libpayload/libcbfs/Makefile.inc b/payloads/libpayload/libcbfs/Makefile.inc index 85ef485822..53e6f7fa43 100644 --- a/payloads/libpayload/libcbfs/Makefile.inc +++ b/payloads/libpayload/libcbfs/Makefile.inc @@ -28,3 +28,9 @@ libcbfs-$(CONFIG_LP_CBFS) += cbfs.c libcbfs-$(CONFIG_LP_CBFS) += ram_media.c +libcbfs-$(CONFIG_LP_CBFS) += cbfs_legacy.c + +ifeq ($(CONFIG_LP_CBFS),y) +libcbfs-srcs += $(coreboottop)/src/commonlib/bsd/cbfs_private.c +libcbfs-srcs += $(coreboottop)/src/commonlib/bsd/cbfs_mcache.c +endif diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index d24b528ded..6a996b7ad2 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -1,243 +1,225 @@ -/* - * - * Copyright (C) 2011 secunet Security Networks AG - * Copyright (C) 2013 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#define LIBPAYLOAD - -#ifdef LIBPAYLOAD -# include -# if CONFIG(LP_LZMA) -# include -# define CBFS_CORE_WITH_LZMA -# endif -# if CONFIG(LP_LZ4) -# include -# define CBFS_CORE_WITH_LZ4 -# endif -# define CBFS_MINI_BUILD -#elif defined(__SMM__) -# define CBFS_MINI_BUILD -#else -# define CBFS_CORE_WITH_LZMA -# define CBFS_CORE_WITH_LZ4 -# include -#endif +/* SPDX-License-Identifier: BSD-3-Clause */ +#include +#include +#include #include +#include +#include +#include +#include +#include +#include #include +#include -#ifdef LIBPAYLOAD -# include -# define DEBUG(x...) -# define LOG(x...) -# define ERROR(x...) printf(x) -#else -# include -# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -# define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -# if CONFIG_LP_DEBUG_CBFS -# define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -# else -# define DEBUG(x...) -# endif -#endif -#include "cbfs_core.c" - -#ifndef __SMM__ -static inline int tohex4(unsigned int c) +static const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) { - return (c <= 9) ? (c + '0') : (c - 10 + 'a'); + static struct cbfs_boot_device ro; + static struct cbfs_boot_device rw; + + if (!force_ro) { + if (!rw.dev.size) { + rw.dev.offset = lib_sysinfo.cbfs_offset; + rw.dev.size = lib_sysinfo.cbfs_size; + rw.mcache = phys_to_virt(lib_sysinfo.cbfs_rw_mcache_offset); + rw.mcache_size = lib_sysinfo.cbfs_rw_mcache_size; + } + return &rw; + } + + if (ro.dev.size) + return &ro; + + if (fmap_locate_area("COREBOOT", &ro.dev.offset, &ro.dev.size)) + return NULL; + + ro.mcache = phys_to_virt(lib_sysinfo.cbfs_ro_mcache_offset); + ro.mcache_size = lib_sysinfo.cbfs_ro_mcache_size; + + return &ro; } -static void tohex16(unsigned int val, char* dest) +ssize_t _cbfs_boot_lookup(const char *name, bool force_ro, union cbfs_mdata *mdata) { - dest[0] = tohex4(val>>12); - dest[1] = tohex4((val>>8) & 0xf); - dest[2] = tohex4((val>>4) & 0xf); - dest[3] = tohex4(val & 0xf); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd) + return CB_ERR; + + size_t data_offset; + cb_err_t err = CB_CBFS_CACHE_FULL; + if (cbd->mcache_size) + err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, name, mdata, + &data_offset); + + if (err == CB_CBFS_CACHE_FULL) + err = cbfs_lookup(&cbd->dev, name, mdata, &data_offset, NULL); + + /* Fallback to RO if possible. */ + if (CONFIG(LP_ENABLE_CBFS_FALLBACK) && !force_ro && err == CB_CBFS_NOT_FOUND) { + LOG("Fall back to RO region for '%s'\n", name); + return _cbfs_boot_lookup(name, true, mdata); + } + + if (err) { + if (err == CB_CBFS_NOT_FOUND) + LOG("'%s' not found.\n", name); + else + ERROR("Error %d when looking up '%s'\n", err, name); + return err; + } + + return cbd->dev.offset + data_offset; } -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device) +void cbfs_unmap(void *mapping) { - char name[17] = "pciXXXX,XXXX.rom"; - - tohex16(vendor, name+3); - tohex16(device, name+8); - - return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); + free(mapping); } -void * cbfs_load_stage(struct cbfs_media *media, const char *name) +static bool cbfs_file_hash_mismatch(const void *buffer, size_t size, + const union cbfs_mdata *mdata, bool skip_verification) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); - /* this is a mess. There is no ntohll. */ - /* for now, assume compatible byte order until we solve this. */ - uintptr_t entry; - uint32_t final_size; + if (!CONFIG(LP_CBFS_VERIFICATION) || skip_verification) + return false; - if (stage == NULL) - return (void *) -1; + const struct vb2_hash *hash = cbfs_file_hash(mdata); + if (!hash) { + ERROR("'%s' does not have a file hash!\n", mdata->h.filename); + return true; + } + if (vb2_hash_verify(buffer, size, hash) != VB2_SUCCESS) { + ERROR("'%s' file hash mismatch!\n", mdata->h.filename); + return true; + } - LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n", - name, - (void*)(uintptr_t) stage->load, stage->memlen, - stage->entry); + return false; +} - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - stage->len, - (void *) (uintptr_t) stage->load, - stage->memlen); - if (!final_size) { - entry = -1; +static size_t cbfs_load_and_decompress(size_t offset, size_t in_size, void *buffer, + size_t buffer_size, uint32_t compression, + const union cbfs_mdata *mdata, bool skip_verification) +{ + void *load = buffer; + size_t out_size = 0; + + DEBUG("Decompressing %zu bytes from '%s' to %p with algo %d\n", in_size, + mdata->h.filename, buffer, compression); + + if (compression != CBFS_COMPRESS_NONE) { + load = malloc(in_size); + if (!load) { + ERROR("'%s' buffer allocation failed\n", mdata->h.filename); + return 0; + } + } + + if (boot_device_read(load, offset, in_size) != in_size) { + ERROR("'%s' failed to read contents of file\n", mdata->h.filename); goto out; } - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); - - DEBUG("stage loaded.\n"); - - entry = stage->entry; - // entry = ntohll(stage->entry); + if (cbfs_file_hash_mismatch(buffer, in_size, mdata, skip_verification)) + goto out; + switch (compression) { + case CBFS_COMPRESS_NONE: + out_size = in_size; + break; + case CBFS_COMPRESS_LZ4: + if (!CONFIG(LP_LZ4)) + goto out; + out_size = ulz4fn(load, in_size, buffer, buffer_size); + break; + case CBFS_COMPRESS_LZMA: + if (!CONFIG(LP_LZMA)) + goto out; + out_size = ulzman(load, in_size, buffer, buffer_size); + break; + default: + ERROR("'%s' decompression algo %d not supported\n", mdata->h.filename, + compression); + } out: - free(stage); - return (void *) entry; + if (load != buffer) + free(load); + return out_size; } -int cbfs_execute_stage(struct cbfs_media *media, const char *name) +static void *do_load(union cbfs_mdata *mdata, ssize_t offset, void *buf, size_t *size_inout, + bool skip_verification) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); - - if (stage == NULL) - return 1; - - if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) { - LOG("Unable to run %s: Compressed file" - "Not supported for in-place execution\n", name); - free(stage); - return 1; + bool malloced = false; + size_t out_size; + uint32_t compression = CBFS_COMPRESS_NONE; + const struct cbfs_file_attr_compression *cattr = + cbfs_find_attr(mdata, CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr)); + if (cattr) { + compression = be32toh(cattr->compression); + out_size = be32toh(cattr->decompressed_size); + } else { + out_size = be32toh(mdata->h.len); } - LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry)); - int result = run_address((void *)(uintptr_t)ntohll(stage->entry)); - free(stage); - return result; + if (buf) { + if (!size_inout || *size_inout < out_size) { + ERROR("'%s' buffer too small\n", mdata->h.filename); + return NULL; + } + } else { + buf = malloc(out_size); + if (!buf) { + ERROR("'%s' allocation failure\n", mdata->h.filename); + return NULL; + } + malloced = true; + } + + if (cbfs_load_and_decompress(offset, be32toh(mdata->h.len), buf, out_size, compression, + mdata, skip_verification) + != out_size) { + if (malloced) + free(buf); + return NULL; + } + if (size_inout) + *size_inout = out_size; + + return buf; } -void *cbfs_load_payload(struct cbfs_media *media, const char *name) +void *_cbfs_load(const char *name, void *buf, size_t *size_inout, bool force_ro) { - return (struct cbfs_payload *)cbfs_get_file_content( - media, name, CBFS_TYPE_SELF, NULL); -} + ssize_t offset; + union cbfs_mdata mdata; -struct cbfs_file *cbfs_find(const char *name) { - struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name); - struct cbfs_media *m = &handle->media; - void *ret; + DEBUG("%s(name='%s', buf=%p, force_ro=%s)\n", __func__, name, buf, + force_ro ? "true" : "false"); - if (!handle) + offset = _cbfs_boot_lookup(name, force_ro, &mdata); + if (offset < 0) return NULL; - ret = m->map(m, handle->media_offset, - handle->content_offset + handle->content_size); - if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - free(handle); + return do_load(&mdata, offset, buf, size_inout, false); +} + +void *_cbfs_unverified_area_load(const char *area, const char *name, void *buf, + size_t *size_inout) +{ + struct cbfs_dev dev; + union cbfs_mdata mdata; + size_t data_offset; + + DEBUG("%s(area='%s', name='%s', buf=%p)\n", __func__, area, name, buf); + + if (fmap_locate_area(area, &dev.offset, &dev.size) != CB_SUCCESS) + return NULL; + + if (cbfs_lookup(&dev, name, &mdata, &data_offset, NULL)) { + ERROR("'%s' not found in '%s'\n", name, area); return NULL; } - free(handle); - return ret; + return do_load(&mdata, dev.offset + data_offset, buf, size_inout, true); } - -void *cbfs_find_file(const char *name, int type) { - return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL); -} - -const struct cbfs_header *get_cbfs_header(void) { - return cbfs_get_header(CBFS_DEFAULT_MEDIA); -} - -/* Simple buffer */ - -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated; - DEBUG("simple_buffer_map(offset=%zu, count=%zu): " - "allocated=%zu, size=%zu, last_allocate=%zu\n", - offset, count, buffer->allocated, buffer->size, - buffer->last_allocate); - if (buffer->allocated + count >= buffer->size) - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - if (media->read(media, address, offset, count) != count) { - ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", - count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - buffer->allocated += count; - buffer->last_allocate = count; - return address; -} - -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { - // TODO Add simple buffer management so we can free more than last - // allocated one. - DEBUG("simple_buffer_unmap(address=%p): " - "allocated=%zu, size=%zu, last_allocate=%zu\n", - address, buffer->allocated, buffer->size, - buffer->last_allocate); - if ((buffer->buffer + buffer->allocated - buffer->last_allocate) == - address) { - buffer->allocated -= buffer->last_allocate; - buffer->last_allocate = 0; - } - return NULL; -} - -/** - * run_address is passed the address of a function taking no parameters and - * jumps to it, returning the result. - * @param f the address to call as a function. - * @return value returned by the function. - */ - -int run_address(void *f) -{ - int (*v) (void); - v = f; - return v(); -} - -#endif diff --git a/payloads/libpayload/libcbfs/cbfs_legacy.c b/payloads/libpayload/libcbfs/cbfs_legacy.c new file mode 100644 index 0000000000..d24b528ded --- /dev/null +++ b/payloads/libpayload/libcbfs/cbfs_legacy.c @@ -0,0 +1,243 @@ +/* + * + * Copyright (C) 2011 secunet Security Networks AG + * Copyright (C) 2013 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#define LIBPAYLOAD + +#ifdef LIBPAYLOAD +# include +# if CONFIG(LP_LZMA) +# include +# define CBFS_CORE_WITH_LZMA +# endif +# if CONFIG(LP_LZ4) +# include +# define CBFS_CORE_WITH_LZ4 +# endif +# define CBFS_MINI_BUILD +#elif defined(__SMM__) +# define CBFS_MINI_BUILD +#else +# define CBFS_CORE_WITH_LZMA +# define CBFS_CORE_WITH_LZ4 +# include +#endif + +#include +#include + +#ifdef LIBPAYLOAD +# include +# define DEBUG(x...) +# define LOG(x...) +# define ERROR(x...) printf(x) +#else +# include +# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) +# define LOG(x...) printk(BIOS_INFO, "CBFS: " x) +# if CONFIG_LP_DEBUG_CBFS +# define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) +# else +# define DEBUG(x...) +# endif +#endif + +#include "cbfs_core.c" + +#ifndef __SMM__ +static inline int tohex4(unsigned int c) +{ + return (c <= 9) ? (c + '0') : (c - 10 + 'a'); +} + +static void tohex16(unsigned int val, char* dest) +{ + dest[0] = tohex4(val>>12); + dest[1] = tohex4((val>>8) & 0xf); + dest[2] = tohex4((val>>4) & 0xf); + dest[3] = tohex4(val & 0xf); +} + +void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, + uint16_t device) +{ + char name[17] = "pciXXXX,XXXX.rom"; + + tohex16(vendor, name+3); + tohex16(device, name+8); + + return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); +} + +void * cbfs_load_stage(struct cbfs_media *media, const char *name) +{ + struct cbfs_stage *stage = (struct cbfs_stage *) + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + /* this is a mess. There is no ntohll. */ + /* for now, assume compatible byte order until we solve this. */ + uintptr_t entry; + uint32_t final_size; + + if (stage == NULL) + return (void *) -1; + + LOG("loading stage %s @ %p (%d bytes), entry @ 0x%llx\n", + name, + (void*)(uintptr_t) stage->load, stage->memlen, + stage->entry); + + final_size = cbfs_decompress(stage->compression, + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + stage->len, + (void *) (uintptr_t) stage->load, + stage->memlen); + if (!final_size) { + entry = -1; + goto out; + } + + memset((void *)((uintptr_t)stage->load + final_size), 0, + stage->memlen - final_size); + + DEBUG("stage loaded.\n"); + + entry = stage->entry; + // entry = ntohll(stage->entry); + +out: + free(stage); + return (void *) entry; +} + +int cbfs_execute_stage(struct cbfs_media *media, const char *name) +{ + struct cbfs_stage *stage = (struct cbfs_stage *) + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + + if (stage == NULL) + return 1; + + if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) { + LOG("Unable to run %s: Compressed file" + "Not supported for in-place execution\n", name); + free(stage); + return 1; + } + + LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry)); + int result = run_address((void *)(uintptr_t)ntohll(stage->entry)); + free(stage); + return result; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + return (struct cbfs_payload *)cbfs_get_file_content( + media, name, CBFS_TYPE_SELF, NULL); +} + +struct cbfs_file *cbfs_find(const char *name) { + struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name); + struct cbfs_media *m = &handle->media; + void *ret; + + if (!handle) + return NULL; + + ret = m->map(m, handle->media_offset, + handle->content_offset + handle->content_size); + if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + free(handle); + return NULL; + } + + free(handle); + return ret; +} + +void *cbfs_find_file(const char *name, int type) { + return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL); +} + +const struct cbfs_header *get_cbfs_header(void) { + return cbfs_get_header(CBFS_DEFAULT_MEDIA); +} + +/* Simple buffer */ + +void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, + struct cbfs_media *media, + size_t offset, size_t count) { + void *address = buffer->buffer + buffer->allocated; + DEBUG("simple_buffer_map(offset=%zu, count=%zu): " + "allocated=%zu, size=%zu, last_allocate=%zu\n", + offset, count, buffer->allocated, buffer->size, + buffer->last_allocate); + if (buffer->allocated + count >= buffer->size) + return CBFS_MEDIA_INVALID_MAP_ADDRESS; + if (media->read(media, address, offset, count) != count) { + ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", + count, offset); + return CBFS_MEDIA_INVALID_MAP_ADDRESS; + } + buffer->allocated += count; + buffer->last_allocate = count; + return address; +} + +void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, + const void *address) { + // TODO Add simple buffer management so we can free more than last + // allocated one. + DEBUG("simple_buffer_unmap(address=%p): " + "allocated=%zu, size=%zu, last_allocate=%zu\n", + address, buffer->allocated, buffer->size, + buffer->last_allocate); + if ((buffer->buffer + buffer->allocated - buffer->last_allocate) == + address) { + buffer->allocated -= buffer->last_allocate; + buffer->last_allocate = 0; + } + return NULL; +} + +/** + * run_address is passed the address of a function taking no parameters and + * jumps to it, returning the result. + * @param f the address to call as a function. + * @return value returned by the function. + */ + +int run_address(void *f) +{ + int (*v) (void); + v = f; + return v(); +} + +#endif diff --git a/payloads/libpayload/tests/Makefile.inc b/payloads/libpayload/tests/Makefile.inc index 9ae84426b8..529524ca32 100644 --- a/payloads/libpayload/tests/Makefile.inc +++ b/payloads/libpayload/tests/Makefile.inc @@ -11,8 +11,6 @@ testobj := $(obj)/tests endif coverage-dir := $(testobj)/coverage_reports -coreboottop := ../../ - cmockasrc := $(coreboottop)/3rdparty/cmocka cmockaobj := $(objutil)/cmocka CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so @@ -34,16 +32,19 @@ TEST_CONFIG_ := CONFIG_LP_ # Default includes TEST_CFLAGS := -include include/kconfig.h -include include/compiler.h TEST_CFLAGS += -Iinclude -Iinclude/mock +TEST_CFLAGS += -I$(coreboottop)/src/commonlib/bsd/include TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) +TEST_CFLAGS += -I$(VBOOT_SOURCE)/firmware/include # Test specific includes -TEST_CFLAGS += -I$(testsrc)/include -I$(testsrc)/include/mocks +TEST_CFLAGS += -I$(testsrc)/include TEST_CFLAGS += -I$(cmockasrc)/include # Minimal subset of warnings and errors. Tests can be less strict than actual build. TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla TEST_CFLAGS += -Wwrite-strings -Wno-trigraphs -Wimplicit-fallthrough TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror +TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin @@ -140,10 +141,10 @@ $($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) objcopy_wrap_flags=''; \ for sym in $$($(1)-mocks); do \ sym_line="$$$$($(HOSTOBJDUMP) -t $$@.orig \ - | grep -E \"[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$\")"; \ + | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s+$$$$sym$$$$")"; \ if [ ! -z "$$$$sym_line" ] ; then \ - addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \ - section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \ + addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \ + section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \ objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \ fi \ done ; \ diff --git a/payloads/libpayload/tests/drivers/Makefile.inc b/payloads/libpayload/tests/drivers/Makefile.inc index e39921a33f..7705473ef7 100644 --- a/payloads/libpayload/tests/drivers/Makefile.inc +++ b/payloads/libpayload/tests/drivers/Makefile.inc @@ -6,4 +6,3 @@ speaker-test-srcs += tests/drivers/speaker-test.c speaker-test-mocks += inb speaker-test-mocks += outb speaker-test-mocks += arch_ndelay -speaker-test-cflags += -include $(testsrc)/include/mocks/x86_io.h diff --git a/payloads/libpayload/tests/drivers/speaker-test.c b/payloads/libpayload/tests/drivers/speaker-test.c index 199fa58864..a677fa46ca 100644 --- a/payloads/libpayload/tests/drivers/speaker-test.c +++ b/payloads/libpayload/tests/drivers/speaker-test.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include /* Include source to gain access to private defines */ #include "../drivers/speaker.c" diff --git a/payloads/libpayload/tests/include/mocks/cbfs_util.h b/payloads/libpayload/tests/include/mocks/cbfs_util.h new file mode 100644 index 0000000000..b0a1e79831 --- /dev/null +++ b/payloads/libpayload/tests/include/mocks/cbfs_util.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef MOCKS_CBFS_UTIL_H +#define MOCKS_CBFS_UTIL_H + +#include +#include +#include + +#define BE32(be32) EMPTY_WRAP(\ + ((be32) >> 24) & 0xff, ((be32) >> 16) & 0xff, \ + ((be32) >> 8) & 0xff, ((be32) >> 0) & 0xff) + +#define BE64(be64) EMPTY_WRAP( \ + BE32(((be64) >> 32) & 0xFFFFFFFF), \ + BE32(((be64) >> 0) & 0xFFFFFFFF)) + +#define LE32(val32) EMPTY_WRAP(\ + ((val32) >> 0) & 0xff, ((val32) >> 8) & 0xff, \ + ((val32) >> 16) & 0xff, ((val32) >> 24) & 0xff) + +#define LE64(val64) EMPTY_WRAP( \ + BE32(((val64) >> 0) & 0xFFFFFFFF), \ + BE32(((val64) >> 32) & 0xFFFFFFFF)) + +#define FILENAME_SIZE 16 + +struct cbfs_test_file { + struct cbfs_file header; + u8 filename[FILENAME_SIZE]; + u8 attrs_and_data[200]; +}; + +#define TEST_MCACHE_SIZE (2 * MiB) + +#define HEADER_INITIALIZER(ftype, attr_len, file_len) { \ + .magic = CBFS_FILE_MAGIC, \ + .len = htobe32(file_len), \ + .type = htobe32(ftype), \ + .attributes_offset = \ + htobe32(attr_len ? sizeof(struct cbfs_file) + FILENAME_SIZE : 0), \ + .offset = htobe32(sizeof(struct cbfs_file) + FILENAME_SIZE + attr_len), \ +} + +#define HASH_ATTR_SIZE (offsetof(struct cbfs_file_attr_hash, hash.raw) + VB2_SHA256_DIGEST_SIZE) + +/* This macro basically does nothing but suppresses linter messages */ +#define EMPTY_WRAP(...) __VA_ARGS__ + +#define TEST_DATA_1_FILENAME "test/data/1" +#define TEST_DATA_1_SIZE sizeof((u8[]){TEST_DATA_1}) +#define TEST_DATA_1 EMPTY_WRAP( \ + '!', '"', '#', '$', '%', '&', '\'', '(', ')', '*', '+', ',', '-', '.', '/', \ + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', \ + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', \ + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', \ + '[', '\\', ']', '^', '_', '`', \ + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', \ + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z') + +#define TEST_DATA_2_FILENAME "test/data/2" +#define TEST_DATA_2_SIZE sizeof((u8[]){TEST_DATA_2}) +#define TEST_DATA_2 EMPTY_WRAP( \ + 0x9d, 0xa9, 0x91, 0xac, 0x5d, 0xb2, 0x70, 0x76, 0x37, 0x94, 0x94, 0xa8, 0x8b, 0x78, \ + 0xb9, 0xaa, 0x1a, 0x8e, 0x9a, 0x16, 0xbe, 0xdc, 0x29, 0x42, 0x46, 0x58, 0xd4, 0x37, \ + 0x94, 0xca, 0x05, 0xdb, 0x54, 0xfa, 0xd8, 0x6e, 0x54, 0xd8, 0x30, 0x46, 0x5d, 0x62, \ + 0xc2, 0xce, 0xd8, 0x74, 0x60, 0xaf, 0x83, 0x8f, 0xfa, 0x97, 0xdd, 0x6e, 0xcb, 0x60, \ + 0xfa, 0xed, 0x8b, 0x55, 0x9e, 0xc1, 0xc2, 0x18, 0x4f, 0xe2, 0x28, 0x7e, 0xd7, 0x2f, \ + 0xa2, 0x86, 0xfb, 0x4d, 0x3e, 0x00, 0x5a, 0xf7, 0xc2, 0xad, 0x0e, 0xa7, 0xa2, 0xf7, \ + 0x38, 0x66, 0xe6, 0x5c, 0x76, 0x98, 0x89, 0x63, 0xeb, 0xc5, 0xf5, 0xb7, 0xa7, 0x58, \ + 0xe0, 0xf0, 0x2e, 0x2f, 0xb0, 0x95, 0xb7, 0x43, 0x28, 0x19, 0x2d, 0xef, 0x1a, 0xb3, \ + 0x42, 0x31, 0x55, 0x0f, 0xbc, 0xcd, 0x01, 0xe5, 0x39, 0x18, 0x88, 0x83, 0xb2, 0xc5, \ + 0x4b, 0x3b, 0x38, 0xe7) + +#define TEST_DATA_INT_1_FILENAME "test-int-1" +#define TEST_DATA_INT_1_SIZE 8 +#define TEST_DATA_INT_1 0xFEDCBA9876543210ULL + +#define TEST_DATA_INT_2_FILENAME "test-int-2" +#define TEST_DATA_INT_2_SIZE 8 +#define TEST_DATA_INT_2 0x10FE32DC54A97698ULL + +#define TEST_DATA_INT_3_FILENAME "test-int-3" +#define TEST_DATA_INT_3_SIZE 8 +#define TEST_DATA_INT_3 0xFA57F003B0036667ULL + +#define TEST_SHA256 \ + EMPTY_WRAP(0xef, 0xc7, 0xb1, 0x0a, 0xbf, 0x54, 0x2f, 0xaa, 0x12, 0xa6, 0xeb, 0xf, \ + 0xff, 0xf4, 0x19, 0xc1, 0x63, 0xf4, 0x60, 0x50, 0xc5, 0xb0, 0xbe, 0x37, \ + 0x32, 0x11, 0x19, 0x63, 0x61, 0xe0, 0x53, 0xe0) + +#define INVALID_SHA256 \ + EMPTY_WRAP('T', 'h', 'i', 's', ' ', 'i', 's', ' ', 'n', 'o', 't', ' ', 'a', ' ', 'v', \ + 'a', 'l', 'i', 'd', ' ', 'S', 'H', 'A', '2', '5', '6', '!', '!', '!', '!', \ + '!', '!') + +extern const u8 test_data_1[TEST_DATA_1_SIZE]; +extern const u8 test_data_2[TEST_DATA_2_SIZE]; +extern const u8 test_data_int_1[TEST_DATA_INT_1_SIZE]; +extern const u8 test_data_int_2[TEST_DATA_INT_2_SIZE]; +extern const u8 test_data_int_3[TEST_DATA_INT_3_SIZE]; + +extern const u8 good_hash[VB2_SHA256_DIGEST_SIZE]; +extern const u8 bad_hash[VB2_SHA256_DIGEST_SIZE]; + +extern const struct cbfs_test_file file_no_hash; +extern const struct cbfs_test_file file_valid_hash; +extern const struct cbfs_test_file file_broken_hash; +extern const struct cbfs_test_file test_file_1; +extern const struct cbfs_test_file test_file_2; +extern const struct cbfs_test_file test_file_int_1; +extern const struct cbfs_test_file test_file_int_2; +extern const struct cbfs_test_file test_file_int_3; + +#endif /* MOCKS_CBFS_UTIL_H */ diff --git a/payloads/libpayload/tests/include/mocks/x86_io.h b/payloads/libpayload/tests/include/mocks/x86_io.h deleted file mode 100644 index c35a57263c..0000000000 --- a/payloads/libpayload/tests/include/mocks/x86_io.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef TESTS_MOCKS_X86_IO_H_ -#define TESTS_MOCKS_X86_IO_H_ - -unsigned int inl(int port); - -unsigned short inw(int port); - -unsigned char inb(int port); - -void outl(unsigned int val, int port); - -void outw(unsigned short val, int port); - -void outb(unsigned char val, int port); - -void outsl(int port, const void *addr, unsigned long count); - -void outsw(int port, const void *addr, unsigned long count); - -void outsb(int port, const void *addr, unsigned long count); - -void insl(int port, void *addr, unsigned long count); - -void insw(int port, void *addr, unsigned long count); - -void insb(int port, void *addr, unsigned long count); - -#endif diff --git a/payloads/libpayload/tests/libc/Makefile.inc b/payloads/libpayload/tests/libc/Makefile.inc new file mode 100644 index 0000000000..5f92bdf0a8 --- /dev/null +++ b/payloads/libpayload/tests/libc/Makefile.inc @@ -0,0 +1,3 @@ +tests-y += fmap_locate_area-test + +fmap_locate_area-test-srcs += tests/libc/fmap_locate_area-test.c diff --git a/payloads/libpayload/tests/libc/fmap_locate_area-test.c b/payloads/libpayload/tests/libc/fmap_locate_area-test.c new file mode 100644 index 0000000000..ce7c36b373 --- /dev/null +++ b/payloads/libpayload/tests/libc/fmap_locate_area-test.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../libc/fmap.c" + +#include +#include + + +/* Mocks */ +struct sysinfo_t lib_sysinfo; +unsigned long virtual_offset = 0; + +static void reset_fmap_cache(void) +{ + _fmap_cache = NULL; +} + +static int setup_fmap_test(void **state) +{ + reset_fmap_cache(); + lib_sysinfo.fmap_cache = 0; + return 0; +} + +static void test_fmap_locate_area_no_fmap_available(void **state) +{ + size_t offset = 0; + size_t size = 0; + + assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size)); +} + +static void test_fmap_locate_area_incorrect_signature(void **state) +{ + size_t offset = 0; + size_t size = 0; + struct fmap mock_fmap = { + .signature = "NOT_MAP", + }; + lib_sysinfo.fmap_cache = (uintptr_t)&mock_fmap; + + assert_int_equal(-1, fmap_locate_area("COREBOOT", &offset, &size)); +} + +static void test_fmap_locate_area_success(void **state) +{ + size_t offset = 0; + size_t size = 0; + struct fmap mock_fmap = { + .signature = FMAP_SIGNATURE, + .ver_major = 1, + .ver_minor = 1, + .base = 0xAABB, + .size = 0x10000, + .nareas = 3, + }; + struct fmap_area area_1 = { + .size = 0x1100, + .offset = 0x11, + .name = {'F', 'I', 'R', 'S', 'T', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + struct fmap_area area_2 = { + .size = 0x2200, + .offset = 0x1111, + .name = {'S', 'E', 'C', 'O', 'N', 'D', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + struct fmap_area area_3 = { + .size = 0x100, + .offset = 0x3311, + .name = {'T', 'H', 'I', 'R', 'D', '_', 'A', 'R', 'E', 'A', 0}, + .flags = 0, + }; + u8 fmap_buffer[sizeof(struct fmap) + 3 * sizeof(struct fmap_area)]; + memcpy(fmap_buffer, &mock_fmap, sizeof(mock_fmap)); + memcpy(&fmap_buffer[sizeof(mock_fmap)], &area_1, sizeof(area_1)); + memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1)], &area_2, sizeof(area_2)); + memcpy(&fmap_buffer[sizeof(mock_fmap) + sizeof(area_1) + sizeof(area_2)], &area_3, + sizeof(area_3)); + + /* Cache only */ + reset_fmap_cache(); + lib_sysinfo.fmap_cache = (uintptr_t)fmap_buffer; + + assert_int_equal(0, fmap_locate_area("FIRST_AREA", &offset, &size)); + assert_int_equal(area_1.offset, offset); + assert_int_equal(area_1.size, size); + + assert_int_equal(0, fmap_locate_area("THIRD_AREA", &offset, &size)); + assert_int_equal(area_3.offset, offset); + assert_int_equal(area_3.size, size); + + assert_int_equal(0, fmap_locate_area("SECOND_AREA", &offset, &size)); + assert_int_equal(area_2.offset, offset); + assert_int_equal(area_2.size, size); + + reset_fmap_cache(); +} + +#define FMAP_LOCATE_AREA_TEST(fn) cmocka_unit_test_setup(fn, setup_fmap_test) + +int main(void) +{ + const struct CMUnitTest tests[] = { + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_no_fmap_available), + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_incorrect_signature), + FMAP_LOCATE_AREA_TEST(test_fmap_locate_area_success), + }; + + return lp_run_group_tests(tests, NULL, NULL); +} diff --git a/payloads/libpayload/tests/libcbfs/Makefile.inc b/payloads/libpayload/tests/libcbfs/Makefile.inc new file mode 100644 index 0000000000..ad4efedcba --- /dev/null +++ b/payloads/libpayload/tests/libcbfs/Makefile.inc @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only + +tests-y += cbfs-lookup-no-fallback-test +tests-y += cbfs-lookup-has-fallback-test +tests-y += cbfs-verification-no-sha512-test +tests-y += cbfs-verification-has-sha512-test +tests-y += cbfs-no-verification-no-sha512-test +tests-y += cbfs-no-verification-has-sha512-test + + +cbfs-lookup-no-fallback-test-srcs += tests/libcbfs/cbfs-lookup-test.c +cbfs-lookup-no-fallback-test-srcs += tests/mocks/cbfs_file_mock.c +cbfs-lookup-no-fallback-test-config += CONFIG_LP_ENABLE_CBFS_FALLBACK=0 +cbfs-lookup-no-fallback-test-config += CONFIG_LP_LZ4=1 +cbfs-lookup-no-fallback-test-config += CONFIG_LP_LZMA=1 + +$(call copy-test,cbfs-lookup-no-fallback-test,cbfs-lookup-has-fallback-test) +cbfs-lookup-has-fallback-test-config += CONFIG_LP_ENABLE_CBFS_FALLBACK=1 + +cbfs-verification-no-sha512-test-srcs += tests/libcbfs/cbfs-verification-test.c +cbfs-verification-no-sha512-test-srcs += tests/mocks/cbfs_file_mock.c +cbfs-verification-no-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=1 +cbfs-verification-no-sha512-test-config += VB2_SUPPORT_SHA512=0 + +$(call copy-test,cbfs-verification-no-sha512-test,cbfs-verification-has-sha512-test) +cbfs-verification-has-sha512-test-config += VB2_SUPPORT_SHA512=1 + +$(call copy-test,cbfs-verification-no-sha512-test,cbfs-no-verification-no-sha512-test) +cbfs-verification-has-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=0 + +$(call copy-test,cbfs-verification-no-sha512-test,cbfs-no-verification-has-sha512-test) +cbfs-verification-has-sha512-test-config += CONFIG_LP_CBFS_VERIFICATION=0 +cbfs-verification-has-sha512-test-config += VB2_SUPPORT_SHA512=1 diff --git a/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c b/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c new file mode 100644 index 0000000000..0f840763a8 --- /dev/null +++ b/payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c @@ -0,0 +1,729 @@ +/* SPDX-License-Identifier: GPL-2.0.-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../libcbfs/cbfs.c" + +/* Mocks */ + +unsigned long virtual_offset = 0; +struct sysinfo_t lib_sysinfo; + +unsigned long ulzman(const unsigned char *src, unsigned long srcn, unsigned char *dst, + unsigned long dstn) +{ + assert_true(dstn != 0); + check_expected(srcn); + check_expected(dstn); + memcpy(dst, src, dstn); + return dstn; +} + +size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) +{ + assert_non_null(dstn); + check_expected(srcn); + check_expected(dstn); + memcpy(dst, src, dstn); + return dstn; +} + +static size_t test_fmap_offset = 0; +static size_t test_fmap_size = 0; +static cb_err_t test_fmap_result = CB_SUCCESS; + +static void set_fmap_locate_area_results(size_t offset, size_t size, size_t result) +{ + test_fmap_offset = offset; + test_fmap_size = size; + test_fmap_result = result; +} + +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size) +{ + *offset = test_fmap_offset; + *size = test_fmap_size; + return test_fmap_result; +} + +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out) +{ + assert_non_null(mcache); + assert_true(mcache_size > 0 && mcache_size % CBFS_MCACHE_ALIGNMENT == 0); + assert_non_null(mdata_out); + assert_non_null(data_offset_out); + + check_expected(name); + + cb_err_t ret = mock_type(cb_err_t); + if (ret != CB_SUCCESS) + return ret; + + memcpy(mdata_out, mock_ptr_type(const union cbfs_mdata *), sizeof(union cbfs_mdata)); + *data_offset_out = mock_type(size_t); + return CB_SUCCESS; +} + +static void expect_cbfs_mcache_lookup(const char *name, cb_err_t err, + const union cbfs_mdata *mdata, size_t data_offset_out) +{ + expect_string(cbfs_mcache_lookup, name, name); + will_return(cbfs_mcache_lookup, err); + + if (err == CB_SUCCESS) { + will_return(cbfs_mcache_lookup, mdata); + will_return(cbfs_mcache_lookup, data_offset_out); + } +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash) +{ + assert_non_null(dev); + check_expected(name); + + cb_err_t ret = mock_type(cb_err_t); + if (ret != CB_SUCCESS) + return ret; + + memcpy(mdata_out, mock_ptr_type(const union cbfS_mdata *), sizeof(union cbfs_mdata)); + *data_offset_out = mock_type(size_t); + return CB_SUCCESS; +} + +static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata, + size_t data_offset_out) +{ + expect_string(cbfs_lookup, name, name); + will_return(cbfs_lookup, err); + + if (err == CB_SUCCESS) { + will_return(cbfs_lookup, mdata); + will_return(cbfs_lookup, data_offset_out); + } +} + +const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check) +{ + return mock_ptr_type(void *); +} + +static bool force_single_boot_device_size_failure = false; + +ssize_t boot_device_read(void *buf, size_t offset, size_t size) +{ + memcpy(buf, (void *)offset, size); + if (force_single_boot_device_size_failure) { + force_single_boot_device_size_failure = false; + return CB_ERR; + } + return size; +} + +/* Utils */ + +static size_t get_cbfs_file_size(const void *file_ptr) +{ + const struct cbfs_file *f = file_ptr; + return be32toh(f->offset) + be32toh(f->len); +} + +static void create_cbfs(const struct cbfs_test_file *files[], const size_t nfiles, + uint8_t *buffer, const size_t buffer_size) +{ + uint8_t *data_ptr = buffer; + size_t file_size = 0; + memset(buffer, 0, buffer_size); + for (size_t i = 0; i < nfiles; ++i) { + if (files[i] == NULL) { + file_size = CBFS_ALIGNMENT; + assert_true(&data_ptr[file_size] < &buffer[buffer_size]); + } else { + file_size = get_cbfs_file_size(files[i]); + assert_true(&data_ptr[file_size] < &buffer[buffer_size]); + memcpy(data_ptr, files[i], file_size); + } + data_ptr = &data_ptr[file_size]; + data_ptr = &buffer[ALIGN_UP((uintptr_t)data_ptr - (uintptr_t)buffer, + CBFS_ALIGNMENT)]; + } +} + +static size_t get_created_cbfs_file_start_offset(const struct cbfs_test_file *files[], + const size_t nfile) +{ + size_t offset_out = 0; + size_t offset = 0; + for (size_t i = 0; i < nfile; ++i) { + offset = files[i] ? get_cbfs_file_size(files[i]) : CBFS_ALIGNMENT; + offset_out = ALIGN_UP(offset_out + offset, CBFS_ALIGNMENT); + } + return offset_out; +} + +/* Setup */ + +static uint8_t + aligned_cbfs_ro_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT * 50)] __aligned( + CBFS_ALIGNMENT); +static const size_t aligned_cbfs_ro_buffer_size = sizeof(aligned_cbfs_ro_buffer); +static uint8_t + aligned_cbfs_rw_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT * 50)] __aligned( + CBFS_ALIGNMENT); +static const size_t aligned_cbfs_rw_buffer_size = sizeof(aligned_cbfs_rw_buffer); + +static uint8_t *unaligned_cbfs_ro_buffer = &aligned_cbfs_ro_buffer[5]; +static const size_t unaligned_cbfs_ro_buffer_size = aligned_cbfs_ro_buffer_size - 5; +static uint8_t *unaligned_cbfs_rw_buffer = &aligned_cbfs_rw_buffer[5]; +static const size_t unaligned_cbfs_rw_buffer_size = aligned_cbfs_rw_buffer_size - 5; + +struct cbfs_test_state { + uint8_t *cbfs_ro_buf; + uint64_t cbfs_ro_size; + uint8_t *cbfs_rw_buf; + uint64_t cbfs_rw_size; + + size_t mcache_ro_offset; + size_t mcache_ro_size; + size_t mcache_rw_offset; + size_t mcache_rw_size; + + struct cbfs_test_setup { + bool unaligned; + bool init_ro; + bool init_rw; + } ex; +}; + + +/* Because of how CMocka works, it should be called in the test function, or in the setup + function only if CBFS API capable of initializing RO CBFS boot device is called. */ +static void setup_cbfs_boot_device(struct cbfs_test_state *s) +{ + set_fmap_locate_area_results(0, 0, CB_SUCCESS); + lib_sysinfo.cbfs_ro_mcache_offset = 0; + lib_sysinfo.cbfs_ro_mcache_size = 0; + memset((void *)cbfs_get_boot_device(true), 0, sizeof(struct cbfs_boot_device)); + if (s->ex.init_ro) { + set_fmap_locate_area_results((size_t)s->cbfs_ro_buf, s->cbfs_ro_size, + CB_SUCCESS); + lib_sysinfo.cbfs_ro_mcache_offset = s->mcache_ro_offset; + lib_sysinfo.cbfs_ro_mcache_size = s->mcache_ro_size; + } + + lib_sysinfo.cbfs_offset = 0; + lib_sysinfo.cbfs_size = 0; + lib_sysinfo.cbfs_rw_mcache_offset = 0; + lib_sysinfo.cbfs_rw_mcache_size = 0; + memset((void *)cbfs_get_boot_device(false), 0, sizeof(struct cbfs_boot_device)); + if (s->ex.init_rw) { + lib_sysinfo.cbfs_offset = (uint64_t)s->cbfs_rw_buf; + lib_sysinfo.cbfs_size = s->cbfs_rw_size; + lib_sysinfo.cbfs_rw_mcache_offset = s->mcache_rw_offset; + lib_sysinfo.cbfs_rw_mcache_size = s->mcache_rw_size; + } +} + +static int setup_cbfs_test(void **state) +{ + struct cbfs_test_state *s = calloc(1, sizeof(*s)); + + if (!s) + return 1; + + if (*state) + memcpy(&s->ex, *state, sizeof(s->ex)); + + if (s->ex.init_ro) { + if (s->ex.unaligned) { + s->cbfs_ro_buf = unaligned_cbfs_ro_buffer; + s->cbfs_ro_size = unaligned_cbfs_ro_buffer_size; + } else { + s->cbfs_ro_buf = aligned_cbfs_ro_buffer; + s->cbfs_ro_size = aligned_cbfs_ro_buffer_size; + } + } + + if (s->ex.init_rw) { + if (s->ex.unaligned) { + s->cbfs_rw_buf = unaligned_cbfs_rw_buffer; + s->cbfs_rw_size = unaligned_cbfs_rw_buffer_size; + } else { + s->cbfs_rw_buf = aligned_cbfs_rw_buffer; + s->cbfs_rw_size = aligned_cbfs_rw_buffer_size; + } + } + + *state = s; + + return 0; +} + +static int teardown_cbfs_test(void **state) +{ + if (*state) + free(*state); + + return 0; +} + +/* Tests */ + +static void test_cbfs_boot_device_init(void **state) +{ + const struct cbfs_boot_device *cbd = NULL; + + /* No valid RO, should fail */ + set_fmap_locate_area_results(0, 0, CB_ERR); + lib_sysinfo.cbfs_offset = 0; + lib_sysinfo.cbfs_size = 0; + lib_sysinfo.cbfs_rw_mcache_size = 0; + lib_sysinfo.cbfs_rw_mcache_offset = 0; + lib_sysinfo.cbfs_ro_mcache_offset = 0; + lib_sysinfo.cbfs_ro_mcache_size = 0; + assert_int_equal(NULL, cbfs_get_boot_device(true)); + assert_null(cbfs_ro_map("file", NULL)); + + /* Valid RO */ + set_fmap_locate_area_results(0x12345678, 0x90ABCDEF, CB_SUCCESS); + lib_sysinfo.cbfs_ro_mcache_offset = 0x600D41C3; + lib_sysinfo.cbfs_ro_mcache_size = 0xBADBEEFF; + cbd = cbfs_get_boot_device(true); + assert_non_null(cbd); + assert_int_equal(0x12345678, cbd->dev.offset); + assert_int_equal(0x90ABCDEF, cbd->dev.size); + assert_int_equal(0xBADBEEFF, cbd->mcache_size); + assert_int_equal(0x600D41C3, cbd->mcache); + + lib_sysinfo.cbfs_offset = 0xAABBCCDD; + lib_sysinfo.cbfs_size = 0x1000; + lib_sysinfo.cbfs_rw_mcache_offset = 0x8F8F8F8F; + lib_sysinfo.cbfs_rw_mcache_size = 0x500; + cbd = cbfs_get_boot_device(false); + assert_non_null(cbd); + assert_int_equal(0xAABBCCDD, cbd->dev.offset); + assert_int_equal(0x1000, cbd->dev.size); + assert_int_equal(0x8F8F8F8F, cbd->mcache); + assert_int_equal(0x500, cbd->mcache_size); +} + +/* This test checks cbfs_map() basic cases and covers only RW CBFS. */ +void test_cbfs_map(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_int_1, &test_file_2, NULL, &test_file_int_3, + &test_file_int_2, NULL, NULL, &test_file_1, + }; + uint8_t *cbfs_buf = NULL; + size_t foffset = 0; + + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_rw_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 0); + expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_1.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_map(TEST_DATA_INT_1_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_1_SIZE, size_out); + assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 1); + expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_2.header.offset)); + will_return(cbfs_find_attr, &test_file_2.attrs_and_data); + expect_value(ulzman, srcn, TEST_DATA_2_SIZE); + expect_value(ulzman, dstn, TEST_DATA_2_SIZE); + mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_2_SIZE, size_out); + assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 3); + expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_3.header.offset)); + will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data); + expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE); + expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE); + mapping = cbfs_map(TEST_DATA_INT_3_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_3_SIZE, size_out); + assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 4); + expect_cbfs_lookup(TEST_DATA_INT_2_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_2.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_map(TEST_DATA_INT_2_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_2_SIZE, size_out); + assert_memory_equal(test_data_int_2, mapping, TEST_DATA_INT_2_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 7); + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_1.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size_out); + assert_memory_equal(test_data_1, mapping, TEST_DATA_1_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0); + if (s->ex.init_rw && CONFIG(LP_ENABLE_CBFS_FALLBACK)) + expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0); + mapping = cbfs_map("invalid_file", &size_out); + assert_null(mapping); +} + +static void test_cbfs_invalid_compression_algo(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + uint8_t *cbfs_buf = NULL; + struct cbfs_test_file *f; + struct cbfs_file_attr_compression *comp; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_2, + }; + + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_rw_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + f = (struct cbfs_test_file *)cbfs_buf; + comp = (struct cbfs_file_attr_compression *)&f->attrs_and_data[0]; + comp->compression = 0xFFFFFFF0; + + size_out = 0; + expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS, (const union cbfs_mdata *)cbfs_buf, + be32toh(test_file_1.header.offset)); + will_return(cbfs_find_attr, comp); + mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out); + assert_null(mapping); +} + +static void test_cbfs_io_error(void **state) +{ + struct cbfs_test_state *s = *state; + setup_cbfs_boot_device(s); + + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_CBFS_IO, 0, 0); + assert_null(cbfs_map(TEST_DATA_1_FILENAME, NULL)); +} + +static void test_cbfs_successful_fallback_to_ro(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_1, &test_file_2, &test_file_int_1, + &test_file_int_1, &test_file_int_2, &test_file_int_3, + }; + uint8_t *cbfs_buf = NULL; + size_t foffset = 0; + + if (!CONFIG(LP_ENABLE_CBFS_FALLBACK)) { + print_message("Skipping test, because LP_ENABLE_CBFS_FALLBACK == 0\n"); + skip(); + } + + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_ro_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_ro_buf, s->cbfs_ro_size); + if (s->ex.init_rw) + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files) - 2, s->cbfs_rw_buf, + s->cbfs_rw_size); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 1); + expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_CBFS_NOT_FOUND, 0, 0); + expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_2.header.offset)); + will_return(cbfs_find_attr, &test_file_2.attrs_and_data); + expect_value(ulzman, srcn, TEST_DATA_2_SIZE); + expect_value(ulzman, dstn, TEST_DATA_2_SIZE); + mapping = cbfs_map(TEST_DATA_2_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_2_SIZE, size_out); + assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 5); + expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_CBFS_NOT_FOUND, 0, 0); + expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_3.header.offset)); + will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data); + expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE); + expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE); + mapping = cbfs_map(TEST_DATA_INT_3_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_3_SIZE, size_out); + assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE); + cbfs_unmap(mapping); +} + +static void test_cbfs_load(void **state) +{ + struct cbfs_test_state *s = *state; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_int_1, &test_file_2, NULL, &test_file_int_3, + &test_file_int_2, NULL, NULL, &test_file_1, + }; + uint8_t *cbfs_buf = NULL; + uint8_t load_buf[1 * KiB]; + size_t foffset = 0; + + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_rw_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + /* Successful load */ + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 0); + expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_1.header.offset)); + will_return(cbfs_find_attr, NULL); + size_out = cbfs_load(TEST_DATA_INT_1_FILENAME, load_buf, sizeof(load_buf)); + assert_int_equal(TEST_DATA_INT_1_SIZE, size_out); + assert_memory_equal(test_data_int_1, load_buf, TEST_DATA_INT_1_SIZE); + + /* Buffer too small */ + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 7); + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_1.header.offset)); + will_return(cbfs_find_attr, NULL); + size_out = cbfs_load(TEST_DATA_1_FILENAME, load_buf, TEST_DATA_1_SIZE / 2); + assert_int_equal(0, size_out); +} + +static void test_cbfs_map_with_mcache(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_int_2, &test_file_1, NULL, + &test_file_int_3, &test_file_int_1, &test_file_2, + }; + uint8_t *cbfs_buf = NULL; + size_t foffset = 0; + + /* Will not be accessed, just needs to be valid. */ + s->mcache_ro_offset = ALIGN_UP(0x1000, CBFS_MCACHE_ALIGNMENT); + s->mcache_ro_size = ALIGN_UP(0x500, CBFS_MCACHE_ALIGNMENT); + s->mcache_rw_offset = ALIGN_UP(0x3000, CBFS_MCACHE_ALIGNMENT); + s->mcache_rw_size = ALIGN_UP(0x600, CBFS_MCACHE_ALIGNMENT); + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_rw_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 4); + expect_cbfs_mcache_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_1.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_map(TEST_DATA_INT_1_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_1_SIZE, size_out); + assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE); + cbfs_unmap(mapping); +} + +static void test_cbfs_boot_device_read_failure(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_int_3, &test_file_1, NULL, + &test_file_int_3, &test_file_int_1, &test_file_2, + }; + uint8_t *cbfs_buf = NULL; + size_t foffset = 0; + + setup_cbfs_boot_device(s); + cbfs_buf = s->cbfs_rw_buf; + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 1); + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_1.header.offset)); + will_return(cbfs_find_attr, NULL); + force_single_boot_device_size_failure = true; + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size_out); + assert_null(mapping); +} + +/* This test uses RW CBFS only */ +static void test_cbfs_unverified_area_map(void **state) +{ + struct cbfs_test_state *s = *state; + void *mapping = NULL; + size_t size_out = 0; + const struct cbfs_test_file *cbfs_files[] = { + &test_file_int_1, &test_file_2, NULL, &test_file_int_3, + &test_file_int_2, NULL, NULL, &test_file_1, + }; + uint8_t *cbfs_buf = NULL; + size_t foffset = 0; + + cbfs_buf = s->cbfs_rw_buf; + set_fmap_locate_area_results((size_t)cbfs_buf, s->cbfs_rw_size, CB_SUCCESS); + create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), s->cbfs_rw_buf, s->cbfs_rw_size); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 0); + expect_cbfs_lookup(TEST_DATA_INT_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_1.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_1_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_1_SIZE, size_out); + assert_memory_equal(test_data_int_1, mapping, TEST_DATA_INT_1_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 1); + expect_cbfs_lookup(TEST_DATA_2_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_2.header.offset)); + will_return(cbfs_find_attr, &test_file_2.attrs_and_data); + expect_value(ulzman, srcn, TEST_DATA_2_SIZE); + expect_value(ulzman, dstn, TEST_DATA_2_SIZE); + mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_2_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_2_SIZE, size_out); + assert_memory_equal(test_data_2, mapping, TEST_DATA_2_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 3); + expect_cbfs_lookup(TEST_DATA_INT_3_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_3.header.offset)); + will_return(cbfs_find_attr, &test_file_int_3.attrs_and_data); + expect_value(ulz4fn, srcn, TEST_DATA_INT_3_SIZE); + expect_value(ulz4fn, dstn, TEST_DATA_INT_3_SIZE); + mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_3_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_3_SIZE, size_out); + assert_memory_equal(test_data_int_3, mapping, TEST_DATA_INT_3_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 4); + expect_cbfs_lookup(TEST_DATA_INT_2_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_int_2.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_INT_2_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_INT_2_SIZE, size_out); + assert_memory_equal(test_data_int_2, mapping, TEST_DATA_INT_2_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + foffset = get_created_cbfs_file_start_offset(cbfs_files, 7); + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&cbfs_buf[foffset], + foffset + be32toh(test_file_1.header.offset)); + will_return(cbfs_find_attr, NULL); + mapping = cbfs_unverified_area_map("TEST_AREA", TEST_DATA_1_FILENAME, &size_out); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size_out); + assert_memory_equal(test_data_1, mapping, TEST_DATA_1_SIZE); + cbfs_unmap(mapping); + + size_out = 0; + expect_cbfs_lookup("invalid_file", CB_CBFS_NOT_FOUND, 0, 0); + mapping = cbfs_unverified_area_map("TEST_AREA", "invalid_file", &size_out); + assert_null(mapping); +} + +#define TEST_CBFS_NAME_ALIGN_RO_RW(fn, test_name, enable_unaligned, enable_init_ro, \ + enable_init_rw) \ + ((struct CMUnitTest){ \ + .name = (test_name), \ + .test_func = (fn), \ + .setup_func = setup_cbfs_test, \ + .teardown_func = teardown_cbfs_test, \ + .initial_state = \ + &(struct cbfs_test_setup){ \ + .unaligned = enable_unaligned, \ + .init_ro = enable_init_ro, \ + .init_rw = enable_init_rw, \ + }, \ + }) + +#define TEST_CBFS_LOOKUP(fn) \ + EMPTY_WRAP(TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW, aligned", false, false, true), \ + TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW, unaligned", true, false, true)) + +#define TEST_CBFS_RO_FALLBACK(fn) \ + EMPTY_WRAP(TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW+RO, aligned", false, true, true), \ + TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RW+RO, unaligned", true, true, true), \ + TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RO, aligned", false, true, false), \ + TEST_CBFS_NAME_ALIGN_RO_RW(fn, #fn ", RO, unaligned", true, true, false)) + + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_cbfs_boot_device_init), + TEST_CBFS_LOOKUP(test_cbfs_map), + TEST_CBFS_LOOKUP(test_cbfs_invalid_compression_algo), + TEST_CBFS_LOOKUP(test_cbfs_io_error), + TEST_CBFS_RO_FALLBACK(test_cbfs_successful_fallback_to_ro), + TEST_CBFS_LOOKUP(test_cbfs_load), + TEST_CBFS_LOOKUP(test_cbfs_map_with_mcache), + TEST_CBFS_LOOKUP(test_cbfs_boot_device_read_failure), + TEST_CBFS_LOOKUP(test_cbfs_unverified_area_map), + }; + + return lp_run_group_tests(tests, NULL, NULL); +} diff --git a/payloads/libpayload/tests/libcbfs/cbfs-verification-test.c b/payloads/libpayload/tests/libcbfs/cbfs-verification-test.c new file mode 100644 index 0000000000..2ab3d5302d --- /dev/null +++ b/payloads/libpayload/tests/libcbfs/cbfs-verification-test.c @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "../libcbfs/cbfs.c" + +/* Mocks */ + +unsigned long virtual_offset = 0; +struct sysinfo_t lib_sysinfo; + +size_t vb2_digest_size(enum vb2_hash_algorithm hash_alg) +{ + if (hash_alg != VB2_HASH_SHA256) { + fail_msg("Unsupported hash algorithm: %d\n", hash_alg); + return 0; + } + + return VB2_SHA256_DIGEST_SIZE; +} + +vb2_error_t vb2_hash_verify(const void *buf, uint32_t size, const struct vb2_hash *hash) +{ + check_expected_ptr(buf); + check_expected(size); + + assert_int_equal(hash->algo, VB2_HASH_SHA256); + + if (!memcmp(hash->sha256, good_hash, sizeof(good_hash))) + return VB2_SUCCESS; + + if (!memcmp(hash->sha256, bad_hash, sizeof(bad_hash))) + return VB2_ERROR_SHA_MISMATCH; + + fail_msg("%s called with bad hash", __func__); + return VB2_ERROR_SHA_MISMATCH; +} + +unsigned long ulzman(const unsigned char *src, unsigned long srcn, unsigned char *dst, + unsigned long dstn) +{ + fail_msg("Unexpected call to %s", __func__); + return 0; +} + +size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) +{ + fail_msg("Unexpected call to %s", __func__); + return 0; +} + +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out) +{ + return CB_CBFS_CACHE_FULL; +} + +cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, + size_t *data_offset_out, struct vb2_hash *metadata_hash) +{ + assert_non_null(dev); + check_expected(name); + + cb_err_t ret = mock_type(cb_err_t); + if (ret != CB_SUCCESS) + return ret; + + memcpy(mdata_out, mock_ptr_type(const union cbfs_mdata *), sizeof(union cbfs_mdata)); + *data_offset_out = mock_type(size_t); + return CB_SUCCESS; +} + +static void expect_cbfs_lookup(const char *name, cb_err_t err, const union cbfs_mdata *mdata, + size_t data_offset_out) +{ + expect_string(cbfs_lookup, name, name); + will_return(cbfs_lookup, err); + + if (err == CB_SUCCESS) { + will_return(cbfs_lookup, mdata); + will_return(cbfs_lookup, data_offset_out); + } +} + +const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check) +{ + return mock_ptr_type(void *); +} + +cb_err_t fmap_locate_area(const char *name, size_t *offset, size_t *size) +{ + *offset = 0; + *size = 0; + return CB_SUCCESS; +} + +ssize_t boot_device_read(void *buf, size_t offset, size_t size) +{ + /* Offset should be based on an address from lib_sysinfo.cbfs_offset */ + memcpy(buf, (void *)offset, size); + + return size; +} + +const struct vb2_hash *cbfs_file_hash(const union cbfs_mdata *mdata) +{ + return mock_ptr_type(const struct vb2_hash *); +} + +/* Utils */ + +static void clear_cbfs_boot_devices(void) +{ + lib_sysinfo.cbfs_ro_mcache_offset = 0; + lib_sysinfo.cbfs_ro_mcache_size = 0; + lib_sysinfo.cbfs_offset = 0; + lib_sysinfo.cbfs_size = 0; + lib_sysinfo.cbfs_rw_mcache_offset = 0; + lib_sysinfo.cbfs_rw_mcache_size = 0; + memset((void *)cbfs_get_boot_device(true), 0, sizeof(struct cbfs_boot_device)); + memset((void *)cbfs_get_boot_device(false), 0, sizeof(struct cbfs_boot_device)); +} + +void set_cbfs(uint64_t offset, size_t size) +{ + clear_cbfs_boot_devices(); + lib_sysinfo.cbfs_offset = offset; + lib_sysinfo.cbfs_size = size; +} + +/* Tests */ + +static int setup_test_cbfs(void **state) +{ + clear_cbfs_boot_devices(); + return 0; +} + +static void test_cbfs_map_no_hash(void **state) +{ + void *mapping = NULL; + size_t size = 0; + + set_cbfs((uint64_t)&file_no_hash, sizeof(file_no_hash)); + + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&file_no_hash, + be32toh(file_no_hash.header.offset)); + will_return(cbfs_find_attr, NULL); + + if (CONFIG(LP_CBFS_VERIFICATION)) { + /* File with no hash. No hash causes hash mismatch by default, + so mapping will not be completed successfully. */ + will_return(cbfs_file_hash, NULL); + mapping = cbfs_map(TEST_DATA_1_FILENAME, NULL); + assert_null(mapping); + } else { + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size); + assert_memory_equal(test_data_1, mapping, size); + cbfs_unmap(mapping); + } +} + +static void test_cbfs_map_valid_hash(void **state) +{ + void *mapping = NULL; + size_t size = 0; + struct vb2_hash hash = { + .algo = VB2_HASH_SHA256, + }; + memcpy(&hash.sha256, good_hash, VB2_SHA256_DIGEST_SIZE); + + set_cbfs((uint64_t)&file_valid_hash, sizeof(file_valid_hash)); + + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&file_valid_hash, + be32toh(file_valid_hash.header.offset)); + will_return(cbfs_find_attr, NULL); + + + if (CONFIG(LP_CBFS_VERIFICATION)) { + will_return(cbfs_file_hash, &hash); + expect_memory(vb2_hash_verify, buf, + &file_valid_hash.attrs_and_data[HASH_ATTR_SIZE], HASH_ATTR_SIZE); + expect_value(vb2_hash_verify, size, TEST_DATA_1_SIZE); + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size); + assert_memory_equal(mapping, &file_valid_hash.attrs_and_data[HASH_ATTR_SIZE], + size); + } else { + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size); + assert_memory_equal(test_data_1, mapping, size); + cbfs_unmap(mapping); + } +} + +static void test_cbfs_map_invalid_hash(void **state) +{ + void *mapping = NULL; + size_t size = 0; + struct vb2_hash hash = { + .algo = VB2_HASH_SHA256, + }; + memcpy(&hash.sha256, bad_hash, VB2_SHA256_DIGEST_SIZE); + + set_cbfs((uint64_t)&file_broken_hash, sizeof(file_broken_hash)); + + expect_cbfs_lookup(TEST_DATA_1_FILENAME, CB_SUCCESS, + (const union cbfs_mdata *)&file_broken_hash, + be32toh(file_broken_hash.header.offset)); + will_return(cbfs_find_attr, NULL); + + if (CONFIG(LP_CBFS_VERIFICATION)) { + will_return(cbfs_file_hash, &hash); + expect_memory(vb2_hash_verify, buf, + &file_broken_hash.attrs_and_data[HASH_ATTR_SIZE], HASH_ATTR_SIZE); + expect_value(vb2_hash_verify, size, TEST_DATA_1_SIZE); + mapping = cbfs_map(TEST_DATA_1_FILENAME, NULL); + assert_null(mapping); + } else { + mapping = cbfs_map(TEST_DATA_1_FILENAME, &size); + assert_non_null(mapping); + assert_int_equal(TEST_DATA_1_SIZE, size); + assert_memory_equal(test_data_1, mapping, size); + cbfs_unmap(mapping); + } +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_cbfs_map_no_hash, setup_test_cbfs), + cmocka_unit_test_setup(test_cbfs_map_valid_hash, setup_test_cbfs), + cmocka_unit_test_setup(test_cbfs_map_invalid_hash, setup_test_cbfs), + }; + + return lp_run_group_tests(tests, NULL, NULL); +} diff --git a/payloads/libpayload/tests/mocks/cbfs_file_mock.c b/payloads/libpayload/tests/mocks/cbfs_file_mock.c new file mode 100644 index 0000000000..3ad078c7b0 --- /dev/null +++ b/payloads/libpayload/tests/mocks/cbfs_file_mock.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + + +const u8 test_data_1[TEST_DATA_1_SIZE] = { TEST_DATA_1 }; +const u8 test_data_2[TEST_DATA_2_SIZE] = { TEST_DATA_2 }; +const u8 test_data_int_1[TEST_DATA_INT_1_SIZE] = { LE64(TEST_DATA_INT_1) }; +const u8 test_data_int_2[TEST_DATA_INT_2_SIZE] = { LE64(TEST_DATA_INT_2) }; +const u8 test_data_int_3[TEST_DATA_INT_3_SIZE] = { LE64(TEST_DATA_INT_3) }; + +const u8 good_hash[VB2_SHA256_DIGEST_SIZE] = { TEST_SHA256 }; +const u8 bad_hash[VB2_SHA256_DIGEST_SIZE] = { INVALID_SHA256 }; + +const struct cbfs_test_file file_no_hash = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_1_SIZE), + .filename = TEST_DATA_1_FILENAME, + .attrs_and_data = { + TEST_DATA_1, + }, +}; + +const struct cbfs_test_file file_valid_hash = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, HASH_ATTR_SIZE, TEST_DATA_1_SIZE), + .filename = TEST_DATA_1_FILENAME, + .attrs_and_data = { + BE32(CBFS_FILE_ATTR_TAG_HASH), + BE32(HASH_ATTR_SIZE), + BE32(VB2_HASH_SHA256), + TEST_SHA256, + TEST_DATA_1, + }, +}; + +const struct cbfs_test_file file_broken_hash = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, HASH_ATTR_SIZE, TEST_DATA_1_SIZE), + .filename = TEST_DATA_1_FILENAME, + .attrs_and_data = { + BE32(CBFS_FILE_ATTR_TAG_HASH), + BE32(HASH_ATTR_SIZE), + BE32(VB2_HASH_SHA256), + INVALID_SHA256, + TEST_DATA_1, + }, +}; + +const struct cbfs_test_file test_file_1 = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_1_SIZE), + .filename = TEST_DATA_1_FILENAME, + .attrs_and_data = { + TEST_DATA_1, + }, +}; + +const struct cbfs_test_file test_file_2 = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, sizeof(struct cbfs_file_attr_compression), + TEST_DATA_2_SIZE), + .filename = TEST_DATA_2_FILENAME, + .attrs_and_data = { + BE32(CBFS_FILE_ATTR_TAG_COMPRESSION), + BE32(sizeof(struct cbfs_file_attr_compression)), + BE32(CBFS_COMPRESS_LZMA), + BE32(TEST_DATA_2_SIZE), + TEST_DATA_2, + }, +}; + +const struct cbfs_test_file test_file_int_1 = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_INT_1_SIZE), + .filename = TEST_DATA_INT_1_FILENAME, + .attrs_and_data = { + LE64(TEST_DATA_INT_1), + }, +}; + +const struct cbfs_test_file test_file_int_2 = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_INT_2_SIZE), + .filename = TEST_DATA_INT_2_FILENAME, + .attrs_and_data = { + LE64(TEST_DATA_INT_2), + }, +}; + +const struct cbfs_test_file test_file_int_3 = { + .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, sizeof(struct cbfs_file_attr_compression), + TEST_DATA_INT_3_SIZE), + .filename = TEST_DATA_INT_3_FILENAME, + .attrs_and_data = { + BE32(CBFS_FILE_ATTR_TAG_COMPRESSION), + BE32(sizeof(struct cbfs_file_attr_compression)), + BE32(CBFS_COMPRESS_LZ4), + BE32(TEST_DATA_INT_3_SIZE), + LE64(TEST_DATA_INT_3), + }, +}; diff --git a/payloads/libpayload/tests/mocks/die.c b/payloads/libpayload/tests/mocks/die.c new file mode 100644 index 0000000000..a67105a12b --- /dev/null +++ b/payloads/libpayload/tests/mocks/die.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void die_work(const char *file, const char *func, int line, const char *fmt, ...) +{ + /* Failing asserts are jumping to the user code (test) if expect_assert_failed() was + previously called. Otherwise it jumps to the cmocka code and fails the test. */ + mock_assert(false, "Mock assetion called", file, line); + + /* Should never be reached */ + print_error("%s() called...\n", __func__); + while (1) + ; +} diff --git a/payloads/libpayload/vboot/Kconfig b/payloads/libpayload/vboot/Kconfig new file mode 100644 index 0000000000..e712fbbb66 --- /dev/null +++ b/payloads/libpayload/vboot/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +config VBOOT_LIB + bool "Compile verified boot (vboot) library" + default y if CHROMEOS + default n + help + This option enables compiling and building vboot libraries vboot_fw and tlcl. + +if VBOOT_LIB + +config VBOOT_TPM2_MODE + bool "TPM2 Mode" + default y + help + This option enables TPM 2.0 support in vboot. Disabling it allows using TPM 1.2. + +config VBOOT_X86_SHA_EXT + bool "x86 SHA Extension" + default y if CHROMEOS + default n + depends on ARCH_X86 + help + This option enables SHA256 implementation using x86 SHA processor extension + instructions: sha256msg1, sha256msg2, sha256rnds2. + +endif diff --git a/payloads/libpayload/vboot/Makefile.inc b/payloads/libpayload/vboot/Makefile.inc new file mode 100644 index 0000000000..bd1afa811b --- /dev/null +++ b/payloads/libpayload/vboot/Makefile.inc @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: BSD-3-Clause + +VBOOT_BUILD_DIR ?= $(abspath $(obj)/external/vboot) +VBOOT_FW_LIB = $(VBOOT_BUILD_DIR)/vboot_fw.a +TLCL_LIB = $(VBOOT_BUILD_DIR)/tlcl.a + +vboot_fw-objs += $(VBOOT_FW_LIB) +tlcl-objs += $(TLCL_LIB) + +kconfig-to-binary=$(if $(strip $(1)),1,0) +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst include/%.h,$(top)/include/%.h,\ + $(filter-out -I$(obj),$(1)))) + +ifeq ($(CONFIG_LP_ARCH_MOCK),) +VBOOT_CFLAGS += $(call vboot-fixup-includes,$(CFLAGS)) +VBOOT_CFLAGS += -I$(abspath $(obj)) +endif + +# Enable vboot debug by default +VBOOT_CFLAGS += -DVBOOT_DEBUG + +VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm +VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86 +VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 + +ifeq ($(CONFIG_LP_ARCH_MOCK)$(VBOOT_FIRMWARE_ARCH-y),) +$(error vboot requires architecture to be set in the configuration) +endif + +$(VBOOT_FW_LIB): $(obj)/libpayload-config.h + @printf " MAKE $(subst $(obj)/,,$(@))\n" + +$(Q) FIRMWARE_ARCH="$(VBOOT_FIRMWARE_ARCH-y)" \ + CC="$(CC)" \ + CFLAGS="$(VBOOT_CFLAGS)" \ + $(MAKE) -C "$(VBOOT_SOURCE)" \ + TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \ + X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \ + UNROLL_LOOPS=1 \ + BUILD="$(VBOOT_BUILD_DIR)" \ + V=$(V) \ + $(VBOOT_BUILD_DIR)/vboot_fw.a tlcl + +$(TLCL_LIB): $(VBOOT_FW_LIB) + +.PHONY: $(VBOOT_FW_LIB) $(TLCL_LIB) diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json index 68e241ac22..8ddd61b757 100644 --- a/spd/lp4x/memory_parts.json +++ b/spd/lp4x/memory_parts.json @@ -339,6 +339,18 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "MT53E2G32D4NQ-046 WT:C", + "attribs": { + "densityPerChannelGb": 16, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] } diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt index b9e817cba3..42e35b12b2 100644 --- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt @@ -29,3 +29,4 @@ H54G46CYRBX267,spd-1.hex H54G56CYRBX247,spd-3.hex K4U6E3S4AB-MGCL,spd-1.hex K4UBE3D4AB-MGCL,spd-3.hex +MT53E2G32D4NQ-046 WT:C,spd-7.hex diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt index cedc678682..475487174e 100644 --- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt @@ -29,3 +29,4 @@ H54G46CYRBX267,spd-1.hex H54G56CYRBX247,spd-3.hex K4U6E3S4AB-MGCL,spd-1.hex K4UBE3D4AB-MGCL,spd-3.hex +MT53E2G32D4NQ-046 WT:C,spd-10.hex diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json new file mode 100644 index 0000000000..164d837ff0 --- /dev/null +++ b/spd/lp5/memory_parts.json @@ -0,0 +1,54 @@ +{ + "parts": [ + { + "name": "MT62F512M32D2DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 6400 + } + }, + { + "name": "MT62F1G32D4DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + }, + { + "name": "H9JCNNNCP3MLYR-N6E", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + }, + { + "name": "K3LKBKB0BM-MGCP", + "attribs": { + "densityPerDieGb": 16, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 6400 + } + }, + { + "name": "H9JCNNNBK3MLYR-N6E", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 6400 + } + } + ] +} diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt new file mode 100644 index 0000000000..356c99aa6f --- /dev/null +++ b/spd/lp5/platforms_manifest.generated.txt @@ -0,0 +1,5 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + +ADL,set-0 +SBR,set-1 diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt new file mode 100644 index 0000000000..2d1c643fe1 --- /dev/null +++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt @@ -0,0 +1,8 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + +MT62F512M32D2DR-031 WT:B,spd-1.hex +MT62F1G32D4DR-031 WT:B,spd-2.hex +H9JCNNNCP3MLYR-N6E,spd-2.hex +K3LKBKB0BM-MGCP,spd-3.hex +H9JCNNNBK3MLYR-N6E,spd-1.hex diff --git a/spd/lp5/set-0/spd-1.hex b/spd/lp5/set-0/spd-1.hex new file mode 100644 index 0000000000..6b4ba9fe84 --- /dev/null +++ b/spd/lp5/set-0/spd-1.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-0/spd-2.hex b/spd/lp5/set-0/spd-2.hex new file mode 100644 index 0000000000..92a9046753 --- /dev/null +++ b/spd/lp5/set-0/spd-2.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 00 00 00 0A 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-0/spd-3.hex b/spd/lp5/set-0/spd-3.hex new file mode 100644 index 0000000000..b960e31ff8 --- /dev/null +++ b/spd/lp5/set-0/spd-3.hex @@ -0,0 +1,32 @@ +23 10 13 0E 16 22 95 08 00 00 00 00 02 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-0/spd-empty.hex b/spd/lp5/set-0/spd-empty.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/spd/lp5/set-0/spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/parts_spd_manifest.generated.txt b/spd/lp5/set-1/parts_spd_manifest.generated.txt new file mode 100644 index 0000000000..2d1c643fe1 --- /dev/null +++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt @@ -0,0 +1,8 @@ +# Generated by: +# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 + +MT62F512M32D2DR-031 WT:B,spd-1.hex +MT62F1G32D4DR-031 WT:B,spd-2.hex +H9JCNNNCP3MLYR-N6E,spd-2.hex +K3LKBKB0BM-MGCP,spd-3.hex +H9JCNNNBK3MLYR-N6E,spd-1.hex diff --git a/spd/lp5/set-1/spd-1.hex b/spd/lp5/set-1/spd-1.hex new file mode 100644 index 0000000000..0ac396bd3b --- /dev/null +++ b/spd/lp5/set-1/spd-1.hex @@ -0,0 +1,32 @@ +23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-2.hex b/spd/lp5/set-1/spd-2.hex new file mode 100644 index 0000000000..33da5d70be --- /dev/null +++ b/spd/lp5/set-1/spd-2.hex @@ -0,0 +1,32 @@ +23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-3.hex b/spd/lp5/set-1/spd-3.hex new file mode 100644 index 0000000000..b1893db69b --- /dev/null +++ b/spd/lp5/set-1/spd-3.hex @@ -0,0 +1,32 @@ +23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-empty.hex b/spd/lp5/set-1/spd-empty.hex new file mode 100644 index 0000000000..1a5be53170 --- /dev/null +++ b/spd/lp5/set-1/spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/Kconfig b/src/Kconfig index be269b6195..d57ce90140 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -395,16 +395,6 @@ config FW_CONFIG Enable support for probing devices with fw_config. This is a simple bitmask broken into fields and options for probing. -config FW_CONFIG_SOURCE_CBFS - bool "Obtain Firmware Configuration value from CBFS" - depends on FW_CONFIG - default n - help - With this option enabled coreboot will look for the 32bit firmware - configuration value in CBFS at the selected prefix with the file name - "fw_config". This option will override other sources and allow the - local image to preempt the mainboard selected source. - config FW_CONFIG_SOURCE_CHROMEEC_CBI bool "Obtain Firmware Configuration value from Google Chrome EC CBI" depends on FW_CONFIG && EC_GOOGLE_CHROMEEC @@ -415,6 +405,27 @@ config FW_CONFIG_SOURCE_CHROMEEC_CBI is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was found in CBFS. +config FW_CONFIG_SOURCE_CBFS + bool "Obtain Firmware Configuration value from CBFS" + depends on FW_CONFIG + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in CBFS at the selected prefix with the file name + "fw_config". This option will override other sources and allow the + local image to preempt the mainboard selected source and can be used as + FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option. + +config FW_CONFIG_SOURCE_VPD + bool "Obtain Firmware Configuration value from VPD" + depends on FW_CONFIG && VPD + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in VPD key name "fw_config". This option will + override other sources and allow the local image to preempt the mainboard + selected source and can be used for other FW_CONFIG_SOURCEs fallback option. + config HAVE_RAMPAYLOAD bool @@ -677,12 +688,12 @@ config TIMER_QUEUE config COOP_MULTITASKING def_bool n - depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2 + select TIMER_QUEUE + depends on ARCH_X86 && CPU_INFO_V2 help Cooperative multitasking allows callbacks to be multiplexed on the - main thread of ramstage. With this enabled it allows for multiple - execution paths to take place when they have udelay() calls within - their code. + main thread. With this enabled it allows for multiple execution paths + to take place when they have udelay() calls within their code. config NUM_THREADS int @@ -785,6 +796,21 @@ config GENERATE_SMBIOS_TABLES If unsure, say Y. +config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE + bool + depends on ARCH_X86 + help + If enabled, only generate SMBIOS Type 41 entries for PCI devices in + the devicetree for which Type 41 information is provided, e.g. with + the `smbios_dev_info` devicetree syntax. This is useful to manually + assign specific instance IDs to onboard devices irrespective of the + device traversal order. It is assumed that instance IDs for devices + of the same class are unique. + When disabled, coreboot autogenerates SMBIOS Type 41 entries for all + appropriate PCI devices in the devicetree. Instance IDs are assigned + successive numbers from a monotonically increasing counter, with one + counter for each device class. + config SMBIOS_PROVIDED_BY_MOBO bool default n @@ -852,7 +878,7 @@ config GDB_STUB depends on DRIVERS_UART help If enabled, you will be able to set breakpoints for gdb debugging. - See src/arch/x86/lib/c_start.S for details. + See src/arch/x86/c_start.S for details. config GDB_WAIT bool "Wait for a GDB connection in the ramstage" @@ -1153,7 +1179,7 @@ config DEBUG_INTEL_ME endif config DEBUG_FUNC - bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 + bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL default n help This option enables additional function entry and exit debug messages diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 282d734bd7..4e2b8dfcd9 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include #include @@ -266,7 +268,8 @@ void acpi_create_madt(acpi_madt_t *madt) static unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); + CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, + CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); return current; } @@ -291,7 +294,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->length = sizeof(acpi_mcfg_t); header->revision = get_acpi_table_revision(MCFG); - if (CONFIG(MMCONF_SUPPORT)) + if (CONFIG(ECAM_MMCONF_SUPPORT)) current = acpi_fill_mcfg(current); /* (Re)calculate length and checksum. */ @@ -846,10 +849,10 @@ void acpi_create_hpet(acpi_hpet_t *hpet) addr->space_id = ACPI_ADDRESS_SPACE_MEMORY; addr->bit_width = 64; addr->bit_offset = 0; - addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; - addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32; + addr->addrl = HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = ((unsigned long long)HPET_BASE_ADDRESS) >> 32; - hpet->id = *(unsigned int *)CONFIG_HPET_ADDRESS; + hpet->id = read32p(HPET_BASE_ADDRESS); hpet->number = 0; hpet->min_tick = CONFIG_HPET_MIN_TICKS; @@ -1248,7 +1251,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, printk(BIOS_INFO, "%s: Device not enabled\n", __func__); return current; } - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_ERR, "%s: Unable to find resource for %s\n", __func__, dev_path(dev)); @@ -1506,6 +1509,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = asl_revision; + fadt->FADT_MinorVersion = get_acpi_fadt_minor_version(); fadt->firmware_ctrl = (unsigned long) facs; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; @@ -1576,6 +1580,17 @@ unsigned long __weak fw_cfg_acpi_tables(unsigned long start) return 0; } +void preload_acpi_dsdt(void) +{ + const char *file = CONFIG_CBFS_PREFIX "/dsdt.aml"; + + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", file); + cbfs_preload(file); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -1932,11 +1947,16 @@ __weak int acpi_get_gpe(int gpe) return -1; /* implemented by SOC */ } +u8 get_acpi_fadt_minor_version(void) +{ + return ACPI_FADT_MINOR_VERSION_0; +} + int get_acpi_table_revision(enum acpi_tables table) { switch (table) { case FADT: - return ACPI_FADT_REV_ACPI_6_0; + return ACPI_FADT_REV_ACPI_6; case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 3; case MCFG: diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 2b74261a2f..acef34d455 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -10,8 +10,6 @@ #define ACPIGEN_MAXLEN 0xfffff -#define CPPC_PACKAGE_NAME "GCPC" - #include #include #include @@ -408,8 +406,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } -void acpigen_write_processor_package(const char *const name, - const unsigned int first_core, +void acpigen_write_processor_package(const char *const name, const unsigned int first_core, const unsigned int core_count) { unsigned int i; @@ -432,8 +429,7 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores) acpigen_write_method("\\_SB.CNOT", 1); for (core_id = 0; core_id < number_of_cores; core_id++) { char buffer[DEVICE_PATH_MAX]; - snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, - core_id); + snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, core_id); acpigen_emit_byte(NOTIFY_OP); acpigen_emit_namestring(buffer); acpigen_emit_byte(ARG0_OP); @@ -516,22 +512,19 @@ static void acpigen_write_field_length(uint32_t len) acpigen_emit_byte(emit[j]); } -static void acpigen_write_field_offset(uint32_t offset, - uint32_t current_bit_pos) +static void acpigen_write_field_offset(uint32_t offset, uint32_t current_bit_pos) { uint32_t diff_bits; if (offset < current_bit_pos) { - printk(BIOS_WARNING, "%s: Cannot move offset backward", - __func__); + printk(BIOS_WARNING, "%s: Cannot move offset backward", __func__); return; } diff_bits = offset - current_bit_pos; /* Upper limit */ if (diff_bits > 0xFFFFFFF) { - printk(BIOS_WARNING, "%s: Offset very large to encode", - __func__); + printk(BIOS_WARNING, "%s: Offset very large to encode", __func__); return; } @@ -603,8 +596,7 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou current_bit_pos = l[i].bits; break; default: - printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" - , __func__, l[i].type); + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type); break; } } @@ -632,8 +624,8 @@ void acpigen_write_field(const char *name, const struct fieldlist *l, size_t cou * PMCS, 2 * } */ -void acpigen_write_indexfield(const char *idx, const char *data, - struct fieldlist *l, size_t count, uint8_t flags) +void acpigen_write_indexfield(const char *idx, const char *data, struct fieldlist *l, + size_t count, uint8_t flags) { uint16_t i; uint32_t current_bit_pos = 0; @@ -660,8 +652,7 @@ void acpigen_write_indexfield(const char *idx, const char *data, current_bit_pos = l[i].bits; break; default: - printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" - , __func__, l[i].type); + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n", __func__, l[i].type); break; } } @@ -947,8 +938,8 @@ void acpigen_write_PRW(u32 wake, u32 level) acpigen_pop_len(); } -void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, - u32 busmLat, u32 control, u32 status) +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, + u32 status) { acpigen_write_package(6); acpigen_write_dword(coreFreq); @@ -959,8 +950,8 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, acpigen_write_dword(status); acpigen_pop_len(); - printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", - coreFreq, power, control, status); + printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", coreFreq, power, + control, status); } void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries) @@ -1195,14 +1186,12 @@ void acpigen_write_resourcetemplate_footer(void) acpigen_pop_len(); } -static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, - struct resource *res) +static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, struct resource *res) { acpigen_write_mem32fixed(0, res->base, res->size); } -static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, - struct resource *res) +static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, struct resource *res) { resource_t base = res->base; resource_t size = res->size; @@ -1221,13 +1210,13 @@ void acpigen_write_mainboard_resource_template(void) /* Add reserved memory ranges. */ search_global_resources( IORESOURCE_MEM | IORESOURCE_RESERVE, - IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, acpigen_add_mainboard_rsvd_mem32, 0); /* Add reserved io ranges. */ search_global_resources( IORESOURCE_IO | IORESOURCE_RESERVE, - IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, acpigen_add_mainboard_rsvd_io, 0); acpigen_write_resourcetemplate_footer(); @@ -1637,8 +1626,7 @@ void acpigen_write_pld(const struct acpi_pld *pld) acpigen_pop_len(); } -void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), - size_t count, void *arg) +void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *), size_t count, void *arg) { struct dsm_uuid id = DSM_UUID(uuid, callbacks, count, arg); acpigen_write_dsm_uuid_arr(&id, 1); @@ -1785,8 +1773,7 @@ void acpigen_write_CPPC_package(const struct cppc_config *config) max = CPPC_MAX_FIELDS_VER_3; break; default: - printk(BIOS_ERR, "ERROR: CPPC version %u is not implemented\n", - config->version); + printk(BIOS_ERR, "CPPC version %u is not implemented\n", config->version); return; } acpigen_write_name(CPPC_PACKAGE_NAME); @@ -1887,8 +1874,7 @@ void acpigen_write_rom(void *bios, const size_t length) acpigen_write_method_serialized("_ROM", 2); /* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */ - struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, - (uintptr_t)bios, length); + struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, (uintptr_t)bios, length); acpigen_write_opregion(&opreg); struct fieldlist l[] = { @@ -1901,8 +1887,7 @@ void acpigen_write_rom(void *bios, const size_t length) * Offset (0), * RBF0, 0x80000 * } */ - acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC | - FIELD_NOLOCK | FIELD_PRESERVE); + acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); /* Store (Arg0, Local0) */ acpigen_write_store(); @@ -2060,8 +2045,8 @@ void acpigen_get_tx_gpio(const struct acpi_gpio *gpio) } /* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ -void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, - u16 range_min, u16 range_max, u16 translation, u16 length) +void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min, + u16 range_max, u16 translation, u16 length) { acpigen_emit_byte(0x88); /* Byte 1+2: length (0x000d) */ @@ -2083,8 +2068,8 @@ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran } /* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */ -void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, - u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length) +void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, u32 gran, + u32 range_min, u32 range_max, u32 translation, u32 length) { acpigen_emit_byte(0x87); /* Byte 1+2: length (0023) */ @@ -2112,8 +2097,8 @@ static void acpigen_emit_qword(u64 data) } /* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ -void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, - u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length) +void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, + u64 range_min, u64 range_max, u64 translation, u64 length) { acpigen_emit_byte(0x8a); /* Byte 1+2: length (0x002b) */ diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index ea1efcfb43..f2ae769a60 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -70,6 +70,8 @@ static const char *namestring_of(enum dptf_participant participant) return "TSR2"; case DPTF_TEMP_SENSOR_3: return "TSR3"; + case DPTF_TEMP_SENSOR_4: + return "TSR4"; case DPTF_TPCH: return "TPCH"; default: diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl index c778376bf2..74193e1fa4 100644 --- a/src/acpi/acpigen_extern.asl +++ b/src/acpi/acpigen_extern.asl @@ -11,7 +11,3 @@ External (GNVS, OpRegionObj) External (DNVS, OpRegionObj) #endif - -#if CONFIG(CHROMEOS_NVS) -External (CNVS, OpRegionObj) -#endif diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index c65790db56..7928dad9da 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include @@ -56,6 +55,7 @@ static const uint32_t action_keymaps[] = { KEY_PRIVACY_SCREEN_TOGGLE), [PS2_KEY_MICMUTE] = KEYMAP(0x9b, KEY_MICMUTE), /* e01b */ [PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE), /* e01e */ + [PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL), /* e0d5 */ }; /* Keymap for numeric keypad keys */ diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 7448b3b569..e32dfc46b6 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include +#include #include #include @@ -132,5 +132,8 @@ void acpigen_write_typec_connector(const struct typec_connector_class_config *co add_custom_dsd_property(dsd, port_number); acpi_dp_write(dsd); + /* Add PLD */ + acpigen_write_pld(config->pld); + acpigen_pop_len(); /* Device */ } diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index ff148aef74..b8be798117 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -4,7 +4,6 @@ #if CONFIG(CHROMEOS_NVS) /* Chrome OS specific */ -#include #include #endif @@ -31,13 +30,13 @@ Method (_PIC, 1) PICM = Arg0 } -#if CONFIG(MMCONF_SUPPORT) +#if CONFIG(ECAM_MMCONF_SUPPORT) Scope(\_SB) { /* Base address of PCIe config space */ - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) + Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS) /* Length of PCIe config space, 1MB each bus */ - Name(PCLN, CONFIG_MMCONF_LENGTH) + Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH) /* PCIe Configuration Space */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 8024783af7..6de345fad1 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/acpi/sata.c b/src/acpi/sata.c index 04676a64a5..282d366473 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index c27c6f2dd3..af4ca7cf15 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -5,7 +5,6 @@ #include #include #include -#include #include /* Specification-defined prefix for SoundWire properties. */ diff --git a/src/arch/arm/include/armv4/arch/cpu.h b/src/arch/arm/include/armv4/arch/cpu.h index 8a1b00ebeb..4c6cdf883e 100644 --- a/src/arch/arm/include/armv4/arch/cpu.h +++ b/src/arch/arm/include/armv4/arch/cpu.h @@ -3,6 +3,8 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +static inline void cpu_relax(void) { } + #define asmlinkage #endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h deleted file mode 100644 index 0a3a4d4676..0000000000 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _ARCH_SMP_SPINLOCK_H -#define _ARCH_SMP_SPINLOCK_H - -#define DECLARE_SPIN_LOCK(x) -#define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while (0) -#define spin_lock(lock) do {} while (0) -#define spin_unlock(lock) do {} while (0) - -#include -#define boot_cpu() 1 - -#endif diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 3f1f1ae811..e3154e9488 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -6,6 +6,8 @@ #include #include +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index c8eba8dc1e..7f1c8f8921 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include @@ -53,7 +52,7 @@ static bool decompress_kernel_header(const struct fit_image_node *node) scratch.raw, sizeof(scratch.raw)); break; default: - printk(BIOS_ERR, "ERROR: Unsupported compression algorithm!\n"); + printk(BIOS_ERR, "Unsupported compression algorithm!\n"); return false; } @@ -62,8 +61,7 @@ static bool decompress_kernel_header(const struct fit_image_node *node) die("ERROR: Partial decompression ran over scratchbuf!\n"); if (scratch.header.magic != KERNEL_HEADER_MAGIC) { - printk(BIOS_ERR, - "ERROR: Invalid kernel magic: %#.8x\n != %#.8x\n", + printk(BIOS_ERR, "Invalid kernel magic: %#.8x\n != %#.8x\n", scratch.header.magic, KERNEL_HEADER_MAGIC); return false; } diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 15b2065443..e5e8a7cad3 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -3,6 +3,9 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +/* TODO: Implement using SEV/WFE if this is ever actually used. */ +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { }; diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index d1774a1d15..8ccd62bfab 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -9,7 +9,8 @@ ppc64_asm_flags = ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y) -bootblock-y = bootblock.S stages.c +bootblock-y = bootblock_crt0.S +bootblock-y += arch_timer.c bootblock-y += boot.c bootblock-y += rom_media.c bootblock-y += \ @@ -34,6 +35,7 @@ endif ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y) +romstage-y += arch_timer.c romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c @@ -64,6 +66,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y) ramstage-y += rom_media.c ramstage-y += stages.c +ramstage-y += arch_timer.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += \ diff --git a/src/arch/ppc64/arch_timer.c b/src/arch/ppc64/arch_timer.c new file mode 100644 index 0000000000..799bff03e1 --- /dev/null +++ b/src/arch/ppc64/arch_timer.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Refer to hostboot/src/kernel/timemgr.C */ + +/* Time base frequency is 512 MHz so 512 ticks per usec */ +#define TB_TICKS_PER_USEC 512 + +__weak void init_timer(void) { /* do nothing */ } + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint64_t last_value; +} mono_counter; + +void timer_monotonic_get(struct mono_time *mt) +{ + uint64_t current_tick; + uint64_t usecs_elapsed; + + if (!mono_counter.initialized) { + mono_counter.last_value = read_spr(SPR_TB); + mono_counter.initialized = 1; + } + + current_tick = read_spr(SPR_TB); + usecs_elapsed = (current_tick - mono_counter.last_value) / TB_TICKS_PER_USEC; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +} diff --git a/src/arch/ppc64/boot.c b/src/arch/ppc64/boot.c index dc4bb422a3..bbd0d39e98 100644 --- a/src/arch/ppc64/boot.c +++ b/src/arch/ppc64/boot.c @@ -2,9 +2,28 @@ #include +#if ENV_PAYLOAD_LOADER + +/* + * Payload's entry point is an offset to the real entry point, not to OPD + * (Official Procedure Descriptor) for entry point. + */ +void arch_prog_run(struct prog *prog) +{ + asm volatile( + "mtctr %1\n" + "mr 3, %0\n" + "bctr\n" + :: "r"(prog_entry_arg(prog)), "r"(prog_entry(prog)) : "memory"); +} + +#else + void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); doit(prog_entry_arg(prog)); } + +#endif diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S deleted file mode 100644 index b443f056d1..0000000000 --- a/src/arch/ppc64/bootblock.S +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Early initialization code for POWER8. - */ - -.section ".text._start", "ax", %progbits -.globl _start -.org 0x100, 0xff -_start: - b _start diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S new file mode 100644 index 0000000000..5a9496024e --- /dev/null +++ b/src/arch/ppc64/bootblock_crt0.S @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early initialization code for POWER8/POWER9. + */ + +#include + +#define FIXUP_ENDIAN \ + tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ + b $+44; /* Skip trampoline if endian is good */ \ + .long 0xa600607d; /* mfmsr r11 */ \ + .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0x00004039; /* li r10,0 */ \ + .long 0x6401417d; /* mtmsrd r10,1 */ \ + .long 0x05009f42; /* bcl 20,31,$+4 */ \ + .long 0xa602487d; /* mflr r10 */ \ + .long 0x14004a39; /* addi r10,r10,20 */ \ + .long 0xa6035a7d; /* mtsrr0 r10 */ \ + .long 0xa6037b7d; /* mtsrr1 r11 */ \ + .long 0x2400004c /* rfid */ + +/* Load an immediate 64-bit value into a register */ +#define LOAD_IMM64(r, e) \ + lis r,(e)@highest; \ + ori r,r,(e)@higher; \ + rldicr r,r, 32, 31; \ + oris r,r, (e)@h; \ + ori r,r, (e)@l; + +.section ".text._start", "ax", %progbits +.globl _start +_start: + /* QEMU with hb-mode=on starts at address 0x10, while hardware at 0x0 */ + nop + nop + nop + nop + FIXUP_ENDIAN + + /* Store FDT address provided by QEMU in %r3 to pass it later to + * payload */ + mtspr SPR_HSPRG0, %r3 + + /* Set program priority to medium */ + or %r2, %r2, %r2 + + /* Stack */ + lis %r1, _estack@ha + addi %r1, %r1, _estack@l + + /* Clear .bss section */ + /* Currently not needed, .bss is zeroed in the file. If it were to be + * used, make sure that .bss is 128B aligned (size of cache line), + * otherwise dcbz will clear (part of) .opd section! */ +/* + lis %r5, _bss@ha + addi %r5, %r5, _bss@l + lis %r6, _ebss@ha + addi %r6, %r6, _ebss@l + addi %r6, %r6, -1 +1: + dcbz 0, %r5 + addi %r5, %r5, 128 + cmpld cr7, %r5, %r6 + blt cr7, 1b +*/ + + /* This is tested by checkstack() just before jumping to payload */ + LOAD_IMM64(%r3, 0xDEADBEEFDEADBEEF) + lis %r5, _stack@ha + addi %r5, %r5, _stack@l + subi %r5, %r5, 8 + sub %r4, %r1, %r5 + sradi %r4, %r4, 3 /* Divide by 8 */ + mtctr %r4 +1: + stdu %r3, 8(%r5) + bc 25, 0, 1b + + /* Enable floating point and vector operations */ + /* Vector operations are sometimes generated for code like + * 'uint8_t x[32] = {0}', this results in an exception when vector + * registers (VEC) are not enabled. VSX (vector-scalar extension) is + * also enabled, there is no reason not to. Floating point must also be + * enabled for VSX. + */ + mfmsr %r3 + ori %r3, %r3, 0x2000 /* FP = 1 */ + oris %r3, %r3, 0x0280 /* VEC = 1, VSX = 1 */ + mtmsr %r3 + + /* Load official procedure descriptor address for main() */ + lis %r12, main@ha + addi %r12, %r12, main@l + + /* Load TOC pointer and jump to main() */ + ld %r2, 8(%r12) + b main diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h index 79f15b1eb3..8ff857675c 100644 --- a/src/arch/ppc64/include/arch/byteorder.h +++ b/src/arch/ppc64/include/arch/byteorder.h @@ -5,4 +5,16 @@ #define __BIG_ENDIAN 4321 +#define PPC_BIT(bit) (0x8000000000000000UL >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + +#ifndef __ASSEMBLER__ + +#include +#define PPC_SHIFT(val, lsb) (((uint64_t)(val)) << (63 - (lsb))) + +#else +#define PPC_SHIFT(val, lsb) ((val) << (63 - (lsb))) +#endif + #endif /* _BYTEORDER_H */ diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 5e5ba30ab5..638406d640 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -5,6 +5,8 @@ #include +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index f8c1121f1a..cfaae33f60 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -5,31 +5,66 @@ #include +/* Set MSB to 1 to ignore HRMOR */ +#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 +#define LPCHC_IO_SPACE 0xD0010000 +#define FLASH_IO_SPACE 0xFC000000 +#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) +#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE) +#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000 + +/* Enforce In-order Execution of I/O */ +static inline void eieio(void) +{ + asm volatile("eieio" ::: "memory"); +} + static inline void outb(uint8_t value, uint16_t port) { + asm volatile("stbcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline void outw(uint16_t value, uint16_t port) { + asm volatile("sthcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline void outl(uint32_t value, uint16_t port) { + asm volatile("stwcix %0, %1, %2" :: "r"(value), "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); } static inline uint8_t inb(uint16_t port) { - return 0; + uint8_t buffer; + asm volatile("lbzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; } static inline uint16_t inw(uint16_t port) { - return 0; + uint16_t buffer; + asm volatile("lhzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; } static inline uint32_t inl(uint16_t port) { - return 0; + uint32_t buffer; + asm volatile("lwzcix %0, %1, %2" : "=r"(buffer) : "b"(LPC_BASE_ADDR), "r"(port)); + eieio(); + return buffer; +} + +static inline void report_istep(uint8_t step, uint8_t substep) +{ + outb(step, 0x81); + outb(substep, 0x82); } #endif diff --git a/src/arch/ppc64/include/arch/mmio.h b/src/arch/ppc64/include/arch/mmio.h index 6428043727..c93e570d3e 100644 --- a/src/arch/ppc64/include/arch/mmio.h +++ b/src/arch/ppc64/include/arch/mmio.h @@ -5,38 +5,97 @@ #include -/* NOTE: These are just stubs; if the architecture requires special - * care to avoid posted writes or cachelines, it is not yet done here. +/* NOTE: In some cases accesses to MMIO must be separated by eieio instruction + * to prevent reordering. This is not included in functions below (performance + * reasons) and must be called explicitly. Function eieio() is defined in io.h. */ static inline uint8_t read8(const volatile void *addr) { - return *(volatile uint8_t *)addr; + uint8_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lbzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline uint16_t read16(const volatile void *addr) { - return *(volatile uint16_t *)addr; + uint16_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lhzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline uint32_t read32(const volatile void *addr) { - return *(volatile uint32_t *)addr; + uint32_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lwzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; +} + +static inline uint64_t read64(const volatile void *addr) +{ + uint64_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "ldcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline void write8(volatile void *addr, uint8_t val) { - *(volatile uint8_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stbcix %0, 0, %1" :: + "r"(val), "r"(addr)); } static inline void write16(volatile void *addr, uint16_t val) { - *(volatile uint16_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "sthcix %0, 0, %1" :: + "r"(val), "r"(addr)); } static inline void write32(volatile void *addr, uint32_t val) { - *(volatile uint32_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stwcix %0, 0, %1" :: + "r"(val), "r"(addr)); +} + +static inline void write64(volatile void *addr, uint64_t val) +{ + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stdcix %0, 0, %1" :: + "r"(val), "r"(addr)); } #endif /* __ARCH_MMIO_H__ */ diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index 7d849e4cdb..2fd47669a8 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 20ed723bf5..01b9efaba8 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -13,10 +13,23 @@ #include #include +#include void stage_entry(uintptr_t stage_arg) { +#if ENV_RAMSTAGE + uint64_t hrmor; +#endif + if (!ENV_ROMSTAGE_OR_BEFORE) _cbmem_top_ptr = stage_arg; + +#if ENV_RAMSTAGE + hrmor = read_spr(SPR_HRMOR); + asm volatile("sync; isync" ::: "memory"); + write_spr(SPR_HRMOR, 0); + asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); +#endif + main(); } diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h index 798f879a32..023e8c3acd 100644 --- a/src/arch/riscv/include/arch/barrier.h +++ b/src/arch/riscv/include/arch/barrier.h @@ -7,4 +7,6 @@ static inline void mb(void) { asm volatile("fence"); } static inline void rmb(void) { asm volatile("fence"); } static inline void wmb(void) { asm volatile("fence"); } +#define barrier() { asm volatile ("fence" ::: "memory"); } + #endif /* __ARCH_BARRIER_H__ */ diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 7cf94615a6..d51d8a9200 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -6,6 +6,8 @@ #include #include +static inline void cpu_relax(void) { } + #define asmlinkage struct cpu_driver { diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index b316ff078d..968fdc6c70 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -3,11 +3,9 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#include +#include #include -#define barrier() { asm volatile ("fence" ::: "memory"); } - typedef struct { atomic_t lock; } spinlock_t; diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 1d58602627..0a93763cb0 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include -#include +#include #include +#include void smp_pause(int working_hartid) { diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 6af3fa8b69..4052b2e182 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -191,12 +191,8 @@ config CMOS_DEFAULT_FILE default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT -config HPET_ADDRESS_OVERRIDE - def_bool n - -config HPET_ADDRESS +config HPET_MIN_TICKS hex - default 0xfed00000 if !HPET_ADDRESS_OVERRIDE config C_ENV_BOOTBLOCK_SIZE hex @@ -340,4 +336,23 @@ config MEMLAYOUT_LD_FILE string default "src/arch/x86/memlayout.ld" +# Some EC need an "EC firmware pointer" (a data structure hinting the address +# of its firmware blobs) being put at a fixed position. Its space +# (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a +# stage. Different EC may have different format and/or value for it. The actual +# address of EC firmware pointer should be provided in the Kconfig of the EC +# requiring it, and its value could be filled by linking a read-only global +# data object to the section above. + +config ECFW_PTR_ADDR + hex + help + Address of reserved space for EC firmware pointer, which should not + overlap other data such as reset vector or FIT pointer if present. + +config ECFW_PTR_SIZE + int + help + Size of reserved space for EC firmware pointer + endif diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index e91ddac82d..458bcc637e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -43,6 +43,13 @@ cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) pci$(stripped_vgabios_dgpu_id).rom-type := optionrom +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +pci$(stripped_vgabios_id).rom-align := 64 +pci$(stripped_second_vbios_id).rom-align := 64 +pci$(stripped_vgabios_dgpu_id).rom-align := 64 +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + ############################################################################### # common support for early assembly includes ############################################################################### diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index fd071f8fdb..cee85e5a5c 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -51,7 +51,7 @@ Method(DINI) Method(THRE) { and(CLSR, 0x20, local0) - while (Lequal(local0, Zero)) { + while (local0 == 0) { and(CLSR, 0x20, local0) } } @@ -72,7 +72,7 @@ Method(OUTX, 1) */ Method(OUTC, 1) { - if (LEqual(Arg0, 0x0a)) { + if (Arg0 == 0x0a) { OUTX(0x0d) } OUTX(Arg0) @@ -133,7 +133,7 @@ Method(DBGD, 1) Method(DBGO, 1) { /* DINI() */ - if (LEqual(ObjectType(Arg0), 1)) { + if (ObjectType(Arg0) == 1) { if (LGreater(Arg0, 0xffff)) { DBGD(Arg0) } else { @@ -149,11 +149,11 @@ Method(DBGO, 1) store(0, Local1) while (One) { store(GETC(BDBG, Local1), Local0) - if (LEqual(Local0, 0)) { + if (Local0 == 0) { return (0) } OUTC(Local0) - Increment(Local1) + Local1++ } } return (0) diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index 2600d0b5eb..e47b7f25a8 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -24,7 +24,7 @@ Method(SLEN, 1) Method(S2BF, 1, Serialized) { - Add(SLEN(Arg0), One, Local0) + Local0 = SLEN(Arg0) + 1 Name(BUFF, Buffer(Local0) {}) Store(Arg0, BUFF) Return(BUFF) @@ -41,8 +41,8 @@ Method(SCMP, 2) Store(MIN(Local5, Local6), Local7) While(LLess(Local4, Local7)) { - Store(Derefof(Index(Local0, Local4)), Local2) - Store(Derefof(Index(Local1, Local4)), Local3) + Store(Derefof(Local0[Local4]), Local2) + Store(Derefof(Local1[Local4]), Local3) if (LGreater(Local2, Local3)) { Return(One) } else { @@ -50,7 +50,7 @@ Method(SCMP, 2) Return(Ones) } } - Increment(Local4) + Local4++ } if (LLess(Local4, Local5)) { Return(One) @@ -78,11 +78,11 @@ Method(WCMP, 2) Store(SLEN(Arg1), Local3) While(LLess(Local2, Local3)) { - if (LNotEqual(Derefof(Index(Local0, Local2)), - Derefof(Index(Local1, Local2)))) { + if (LNotEqual(Derefof(Local0[Local2]), + Derefof(Local1[Local2]))) { Return(0) } - Increment(Local2) + Local2++ } Return(One) } diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index a9c06f48fe..8559c06dfb 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -127,7 +127,7 @@ static acpi_generic_error_status_t *new_bert_status(void) status = bert_allocate_storage(sizeof(*status)); if (!status) { - printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n"); + printk(BIOS_ERR, "New BERT error entry would exceed available region\n"); return NULL; } @@ -159,13 +159,13 @@ static acpi_hest_generic_data_v300_t *new_generic_error_entry( acpi_hest_generic_data_v300_t *entry; if (bert_entry_count(status) == GENERIC_ERR_STS_ENTRY_COUNT_MAX) { - printk(BIOS_ERR, "Error: New BERT error would exceed maximum entries\n"); + printk(BIOS_ERR, "New BERT error would exceed maximum entries\n"); return NULL; } entry = bert_allocate_storage(sizeof(*entry)); if (!entry) { - printk(BIOS_ERR, "Error: New BERT error entry would exceed available region\n"); + printk(BIOS_ERR, "New BERT error entry would exceed available region\n"); return NULL; } @@ -191,7 +191,7 @@ static size_t sizeof_error_section(guid_t *guid) return sizeof(cper_fw_err_rec_section_t); /* else if ... sizeof(structures not yet defined) */ - printk(BIOS_ERR, "Error: Requested size of unrecognized CPER GUID\n"); + printk(BIOS_ERR, "Requested size of unrecognized CPER GUID\n"); return 0; } @@ -199,7 +199,7 @@ void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_ { void *cl_data = bert_allocate_storage(cl_size); if (!cl_data) { - printk(BIOS_ERR, "Error: Crashlog entry (size %zu) would exceed available region\n", + printk(BIOS_ERR, "Crashlog entry (size %zu) would exceed available region\n", cl_size); return NULL; } @@ -348,7 +348,7 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx( return NULL; if (cper_ia32x64_proc_num_ctxs(x86err) == I32X64SEC_VALID_CTXNUM_MAX) { - printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed max allowable contexts\n", + printk(BIOS_ERR, "New IA32X64 %s context entry would exceed max allowable contexts\n", ctx_names[type]); return NULL; } @@ -356,7 +356,7 @@ cper_ia32x64_context_t *new_cper_ia32x64_ctx( size = cper_ia32x64_ctx_sz_bytype(type, num); ctx = bert_allocate_storage(size); if (!ctx) { - printk(BIOS_ERR, "Error: New IA32X64 %s context entry would exceed available region\n", + printk(BIOS_ERR, "New IA32X64 %s context entry would exceed available region\n", ctx_names[type]); return NULL; } @@ -402,14 +402,14 @@ cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check( return NULL; if (cper_ia32x64_proc_num_chks(x86err) == I32X64SEC_VALID_ERRNUM_MAX) { - printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed max allowable errors\n", + printk(BIOS_ERR, "New IA32X64 %s check entry would exceed max allowable errors\n", check_names[type]); return NULL; } check = bert_allocate_storage(sizeof(*check)); if (!check) { - printk(BIOS_ERR, "Error: New IA32X64 %s check entry would exceed available region\n", + printk(BIOS_ERR, "New IA32X64 %s check entry would exceed available region\n", check_names[type]); return NULL; } @@ -518,7 +518,7 @@ acpi_generic_error_status_t *bert_new_event(guid_t *guid) size += sizeof_error_section(guid); if (size > bert_storage_remaining()) { - printk(BIOS_ERR, "Error: Not enough BERT region space to add event for type %s\n", + printk(BIOS_ERR, "Not enough BERT region space to add event for type %s\n", generic_error_name(guid)); return NULL; } @@ -571,7 +571,7 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr( */ __weak void bert_reserved_region(void **start, size_t *size) { - printk(BIOS_ERR, "Error: %s not implemented. BERT region generation disabled\n", + printk(BIOS_ERR, "%s not implemented. BERT region generation disabled\n", __func__); *start = NULL; *size = 0; diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 4ab2275998..0b908bbec6 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -31,7 +31,7 @@ SECTIONS { */ PROGRAM_SZ = SIZEOF(.text) + 512; - . = MIN(_ID_SECTION, _FIT_POINTER) - EARLYASM_SZ; + . = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ; . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); BOOTBLOCK_TOP = .; .init (.) : { @@ -56,6 +56,13 @@ SECTIONS { _ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR; _ID_SECTION = _ID_SECTION_END - SIZEOF(.id); + . = _ECFW_PTR; + .ecfw_ptr (.): { + ASSERT((SIZEOF(.ecfw_ptr) == CONFIG_ECFW_PTR_SIZE), "Size of ecfw_ptr is incorrect"); + KEEP(*(.ecfw_ptr)); + } + _ECFW_PTR = SIZEOF(.ecfw_ptr) ? CONFIG_ECFW_PTR_ADDR : _X86_RESET_VECTOR; + . = _FIT_POINTER; .fit_pointer (.): { KEEP(*(.fit_pointer)); diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index c3fdfd9f17..84fbed2956 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -4,7 +4,7 @@ #include #include -/* Place the stack in the bss section. It's not necessary to define it in the +/* Place the stack in the bss section. It's not necessary to define it in * the linker script. */ .section .bss, "aw", @nobits .global _stack diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 527a3cb13a..9b89ffbdf9 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -62,7 +62,7 @@ _start: btl $CPUID_FEATURE_CLFLUSH_BIT, %edx jnc skip_clflush #if ENV_X86_64 - movabs _cbmem_top_ptr, %rax + movabs $_cbmem_top_ptr, %rax clflush (%rax) #else clflush _cbmem_top_ptr diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index b569178ab8..64f7a799b0 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -11,7 +11,7 @@ vendor: part: .asciz CONFIG_MAINBOARD_PART_NUMBER -#if ENV_X86_64 +#if ENV_X86_64 || defined(__clang__) .long 0xffffffff - ver + 1 /* Reverse offset to the version */ .long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */ .long 0xffffffff - part + 1 /* Reverse offset to the part number */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 9a3b63d6b3..d3f50bf794 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -3,7 +3,6 @@ #ifndef ARCH_CPU_H #define ARCH_CPU_H -#include #include /* diff --git a/src/arch/x86/include/arch/hpet.h b/src/arch/x86/include/arch/hpet.h new file mode 100644 index 0000000000..224279eb6f --- /dev/null +++ b/src/arch/x86/include/arch/hpet.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARCH_X86_HPET_H +#define ARCH_X86_HPET_H + +#define HPET_BASE_ADDRESS 0xfed00000 + +#endif /* ARCH_X86_HPET_H */ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 61dd106513..5e69288f92 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -69,7 +69,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) outl(value, 0xCFC); } -#if !CONFIG(MMCONF_SUPPORT) +#if !CONFIG(ECAM_MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 317e597cff..51a578442e 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -4,6 +4,8 @@ #define ARCH_I386_PCI_OPS_H #include +#if CONFIG(ECAM_MMCONF_SUPPORT) #include +#endif #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 0c06c22bba..cb25531b15 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -15,10 +15,6 @@ typedef struct { #define SPIN_LOCK_UNLOCKED { 1 } -#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE - -#if STAGE_HAS_SPINLOCKS - #define DECLARE_SPIN_LOCK(x) \ static spinlock_t x = SPIN_LOCK_UNLOCKED; @@ -29,17 +25,17 @@ typedef struct { * We make no fairness assumptions. They have a cost. */ #define barrier() __asm__ __volatile__("" : : : "memory") -#define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) +#define spin_is_locked(x) (*(volatile int *)(&(x)->lock) <= 0) #define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) #undef barrier #define spin_lock_string \ "\n1:\t" \ - "lock ; decb %0\n\t" \ + "lock ; decl %0\n\t" \ "js 2f\n" \ ".section .text.lock,\"ax\"\n" \ "2:\t" \ - "cmpb $0,%0\n\t" \ + "cmpl $0,%0\n\t" \ "rep;nop\n\t" \ "jle 2b\n\t" \ "jmp 1b\n" \ @@ -49,7 +45,7 @@ typedef struct { * This works. Despite all the confusion. */ #define spin_unlock_string \ - "movb $1,%0" + "movl $1,%0" static __always_inline void spin_lock(spinlock_t *lock) { @@ -71,14 +67,4 @@ static __always_inline void spin_unlock(spinlock_t *lock) : "=m" (lock->lock) : : "memory"); } -#else - -#define DECLARE_SPIN_LOCK(x) -#define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while (0) -#define spin_lock(lock) do {} while (0) -#define spin_unlock(lock) do {} while (0) - -#endif - #endif /* ARCH_SMP_SPINLOCK_H */ diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index ea429713ae..c48ce86c47 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -224,6 +224,9 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, unsigned long *current, int *handle, int type16_handle) { + struct spd_info info; + get_spd_info(dimm->ddr_type, dimm->mod_type, &info); + struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE, sizeof(*t), *handle); @@ -244,24 +247,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, } t->data_width = 8 * (1 << (dimm->bus_width & 0x7)); t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3); - - switch (dimm->mod_type) { - case SPD_RDIMM: - case SPD_MINI_RDIMM: - t->form_factor = MEMORY_FORMFACTOR_RIMM; - break; - case SPD_UDIMM: - case SPD_MICRO_DIMM: - case SPD_MINI_UDIMM: - t->form_factor = MEMORY_FORMFACTOR_DIMM; - break; - case SPD_SODIMM: - t->form_factor = MEMORY_FORMFACTOR_SODIMM; - break; - default: - t->form_factor = MEMORY_FORMFACTOR_UNKNOWN; - break; - } + t->form_factor = info.form_factor; smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t); smbios_fill_dimm_serial_number(dimm, t); @@ -278,19 +264,8 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, t->maximum_voltage = dimm->vdd_voltage; /* Fill in type detail */ - switch (dimm->mod_type) { - case SPD_RDIMM: - case SPD_MINI_RDIMM: - t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; - break; - case SPD_UDIMM: - case SPD_MINI_UDIMM: - t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; - break; - default: - t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; - break; - } + t->type_detail = info.type_detail; + /* Synchronous = 1 */ t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS; /* no handle for error information */ @@ -1177,30 +1152,55 @@ static u8 smbios_get_device_type_from_dev(struct device *dev) } } +static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id) +{ +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + *instance_id = dev->smbios_instance_id; + return dev->smbios_instance_id_valid; +#else + static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; + + if (device_type == SMBIOS_DEVICE_TYPE_OTHER || + device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + return false; + + if (device_type > SMBIOS_DEVICE_TYPE_COUNT) + return false; + + *instance_id = type41_inst_cnt[device_type]++; + return true; +#endif +} + +static const char *smbios_get_type41_refdes(struct device *dev) +{ +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + if (dev->smbios_refdes) + return dev->smbios_refdes; +#endif + return get_pci_subclass_name(dev); +} + static int smbios_generate_type41_from_devtree(struct device *dev, int *handle, unsigned long *current) { - static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {}; - if (dev->path.type != DEVICE_PATH_PCI) return 0; if (!dev->on_mainboard) return 0; - u8 device_type = smbios_get_device_type_from_dev(dev); + const u8 device_type = smbios_get_device_type_from_dev(dev); - if (device_type == SMBIOS_DEVICE_TYPE_OTHER || - device_type == SMBIOS_DEVICE_TYPE_UNKNOWN) + u8 instance_id; + + if (!smbios_get_type41_instance_id(dev, device_type, &instance_id)) return 0; - if (device_type > SMBIOS_DEVICE_TYPE_COUNT) - return 0; - - const char *name = get_pci_subclass_name(dev); + const char *name = smbios_get_type41_refdes(dev); return smbios_write_type41(current, handle, name, // name - type41_inst_cnt[device_type]++, // inst + instance_id, // inst 0, // segment dev->bus->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 09ec0eaaa3..1018dce335 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -36,7 +36,7 @@ static unsigned long write_pirq_table(unsigned long rom_table_end) // much space it's going to need. if (new_high_table_pointer > (high_table_pointer + MAX_PIRQ_TABLE_SIZE)) - printk(BIOS_ERR, "ERROR: Increase PIRQ size.\n"); + printk(BIOS_ERR, "Increase PIRQ size.\n"); printk(BIOS_DEBUG, "PIRQ table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } @@ -64,7 +64,7 @@ static unsigned long write_mptable(unsigned long rom_table_end) // much space it's going to need. if (new_high_table_pointer > (high_table_pointer + MAX_MP_TABLE_SIZE)) - printk(BIOS_ERR, "ERROR: Increase MP table size.\n"); + printk(BIOS_ERR, "Increase MP table size.\n"); printk(BIOS_DEBUG, "MP table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); @@ -102,7 +102,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end) new_high_table_pointer = write_acpi_tables(high_table_pointer); if (new_high_table_pointer > (high_table_pointer + max_acpi_size)) - printk(BIOS_ERR, "ERROR: Increase ACPI size\n"); + printk(BIOS_ERR, "Increase ACPI size\n"); printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); @@ -127,8 +127,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end) writes longest size available. */ memcpy(low_rsdp, high_rsdp, sizeof(acpi_rsdp_t)); } else { - printk(BIOS_ERR, - "ERROR: Didn't find RSDP in high table.\n"); + printk(BIOS_ERR, "Didn't find RSDP in high table.\n"); } rom_table_end = ALIGN_UP(rom_table_end + sizeof(acpi_rsdp_t), 16); } else { @@ -159,7 +158,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end) if (new_high_table_pointer > (high_table_pointer + MAX_SMBIOS_SIZE)) - printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n"); + printk(BIOS_ERR, "Increase SMBIOS size\n"); printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 53975bcad8..2477e07268 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -22,15 +22,11 @@ smm-y += region.c postcar-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c +ifeq ($(CONFIG_FSP_M_XIP),) +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +endif ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c -bootblock-y += cbfs.c -verstage-y += cbfs.c -romstage-y += cbfs.c -ramstage-y += cbfs.c -smm-y += cbfs.c -postcar-y += cbfs.c - bootblock-y += bsd/cbfs_private.c verstage-y += bsd/cbfs_private.c romstage-y += bsd/cbfs_private.c diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h similarity index 92% rename from src/commonlib/include/commonlib/cbmem_id.h rename to src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index a9cf7bdcf6..d4191e3ddf 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CBMEM_ID_H_ #define _CBMEM_ID_H_ @@ -7,7 +7,7 @@ #define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_CNVS 0x434e5653 #define CBMEM_ID_ACPI_GNVS 0x474e5653 -#define CMBMEM_ID_ACPI_HEST 0x48455354 +#define CBMEM_ID_ACPI_HEST 0x48455354 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 @@ -79,13 +79,14 @@ #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TYPE_C_INFO 0x54595045 +#define CBMEM_ID_MEM_CHIP_INFO 0x5048434D #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ - { CMBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ + { CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ @@ -104,8 +105,10 @@ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_HOB_POINTER, "HOB " }, \ + { CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \ { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ + { CBMEM_ID_MDATA_HASH, "METADATA HASH" }, \ { CBMEM_ID_MEMINFO, "MEM INFO " }, \ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ { CBMEM_ID_MMC_STATUS, "MMC STATUS " }, \ @@ -133,6 +136,7 @@ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ + { CBMEM_ID_TPM_PPI, "TPM PPI " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ @@ -147,5 +151,8 @@ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ - { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} + { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ + { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ + { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h index 4dd09bc90c..ebf017900d 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -35,6 +35,10 @@ #define __always_inline inline __attribute__((always_inline)) #endif +#ifndef __fallthrough +#define __fallthrough __attribute__((__fallthrough__)) +#endif + /* This evaluates to the type of the first expression, unless that is constant in which case it evaluates to the type of the second. This is useful when assigning macro parameters to temporary variables, because that would diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 7e564fca21..29c781b6f5 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -305,6 +305,10 @@ struct elog_event_mem_cache_update { #define ELOG_TYPE_MI_HRPC 0xb4 #define ELOG_TYPE_MI_HR 0xb5 +/* Chrome OS diagnostics-related events */ +#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6 +#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01 + struct elog_event_extended_event { uint8_t event_type; uint32_t event_complement; diff --git a/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h index 3a87cda1c4..2e539dafb5 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h +++ b/src/commonlib/bsd/include/commonlib/bsd/sysincludes.h @@ -1,6 +1,23 @@ /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ #if defined(__FreeBSD__) #include +#elif defined(__APPLE__) +#include + +#define htobe16(x) OSSwapHostToBigInt16(x) +#define htole16(x) OSSwapHostToLittleInt16(x) +#define be16toh(x) OSSwapBigToHostInt16(x) +#define le16toh(x) OSSwapLittleToHostInt16(x) + +#define htobe32(x) OSSwapHostToBigInt32(x) +#define htole32(x) OSSwapHostToLittleInt32(x) +#define be32toh(x) OSSwapBigToHostInt32(x) +#define le32toh(x) OSSwapLittleToHostInt32(x) + +#define htobe64(x) OSSwapHostToBigInt64(x) +#define htole64(x) OSSwapHostToLittleInt64(x) +#define be64toh(x) OSSwapBigToHostInt64(x) +#define le64toh(x) OSSwapLittleToHostInt64(x) #else #include #endif diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c deleted file mode 100644 index e7f800c67a..0000000000 --- a/src/commonlib/cbfs.c +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -static size_t cbfs_next_offset(const struct region_device *cbfs, - const struct cbfsf *f) -{ - size_t offset; - - if (f == NULL) - return 0; - - /* The region_device objects store absolute offsets over the whole - * region. Therefore a relative offset needs to be calculated. */ - offset = rdev_relative_offset(cbfs, &f->data); - offset += region_device_sz(&f->data); - - return ALIGN_UP(offset, CBFS_ALIGNMENT); -} - -static int cbfs_end(const struct region_device *cbfs, size_t offset) -{ - if (offset >= region_device_sz(cbfs)) - return 1; - - return 0; -} - -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh) -{ - size_t offset; - - offset = cbfs_next_offset(cbfs, prev); - - /* Try to scan the entire cbfs region looking for file name. */ - while (1) { - struct cbfs_file file; - const size_t fsz = sizeof(file); - - DEBUG("Checking offset %zx\n", offset); - - /* End of region. */ - if (cbfs_end(cbfs, offset)) - return 1; - - /* Can't read file. Nothing else to do but bail out. */ - if (rdev_readat(cbfs, &file, offset, fsz) != fsz) - break; - - if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { - offset++; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - file.len = read_be32(&file.len); - file.offset = read_be32(&file.offset); - - DEBUG("File @ offset %zx size %x\n", offset, file.len); - - /* Keep track of both the metadata and the data for the file. */ - if (rdev_chain(&fh->metadata, cbfs, offset, file.offset)) - break; - - if (rdev_chain(&fh->data, cbfs, offset + file.offset, file.len)) - break; - - /* Success. */ - return 0; - } - - return -1; -} - -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset) -{ - struct cbfs_file_attribute *attr; - - if (!last_offset) { - struct cbfs_file *file = metadata; - size_t start_offset = read_be32(&file->attributes_offset); - if (start_offset <= sizeof(struct cbfs_file) || - start_offset + sizeof(*attr) > metadata_size) - return 0; - return start_offset; - } - - attr = metadata + last_offset; - size_t next_offset = last_offset + read_be32(&attr->len); - - if (next_offset + sizeof(*attr) > metadata_size) - return 0; - return next_offset; -} - -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size) -{ - size_t metadata_size = region_device_sz(&fh->metadata); - void *metadata = rdev_mmap_full(&fh->metadata); - size_t offs = 0; - - if (!metadata) - return -1; - - while ((offs = cbfs_for_each_attr(metadata, metadata_size, offs))) { - struct cbfs_file_attr_compression *attr = metadata + offs; - if (read_be32(&attr->tag) != CBFS_FILE_ATTR_TAG_COMPRESSION) - continue; - - *algo = read_be32(&attr->compression); - *size = read_be32(&attr->decompressed_size); - rdev_munmap(&fh->metadata, metadata); - return 0; - } - - *algo = CBFS_COMPRESS_NONE; - *size = region_device_sz(&fh->data); - rdev_munmap(&fh->metadata, metadata); - return 0; -} - -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype) -{ - const size_t sz = sizeof(*ftype); - - if (rdev_readat(&fh->metadata, ftype, - offsetof(struct cbfs_file, type), sz) != sz) - return -1; - - *ftype = read_be32(ftype); - - return 0; -} - -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type) -{ - struct cbfsf *prev; - - LOG("Locating '%s'\n", name); - - prev = NULL; - - while (1) { - int ret; - char *fname; - int name_match; - const size_t fsz = sizeof(struct cbfs_file); - - ret = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - /* Either failed to read or hit the end of the region. */ - if (ret < 0 || ret > 0) - break; - - fname = rdev_mmap(&fh->metadata, fsz, - region_device_sz(&fh->metadata) - fsz); - - if (fname == NULL) - break; - - name_match = !strcmp(fname, name); - rdev_munmap(&fh->metadata, fname); - - if (!name_match) { - DEBUG(" Unmatched '%s' at %zx\n", fname, - rdev_relative_offset(cbfs, &fh->metadata)); - continue; - } - - if (type != NULL) { - uint32_t ftype; - - if (cbfsf_file_type(fh, &ftype)) - break; - - if (*type != 0 && *type != ftype) { - DEBUG(" Unmatched type %x at %zx\n", ftype, - rdev_relative_offset(cbfs, - &fh->metadata)); - continue; - } - // *type being 0 means we want to know ftype. - // We could just do a blind assignment but - // if type is pointing to read-only memory - // that might be bad. - if (*type == 0) - *type = ftype; - } - - LOG("Found @ offset %zx size %zx\n", - rdev_relative_offset(cbfs, &fh->metadata), - region_device_sz(&fh->data)); - - /* Success. */ - return 0; - } - - LOG("'%s' not found.\n", name); - return -1; -} - -static int cbfs_extend_hash_buffer(struct vb2_digest_context *ctx, - void *buf, size_t sz) -{ - return vb2_digest_extend(ctx, buf, sz); -} - -static int cbfs_extend_hash(struct vb2_digest_context *ctx, - const struct region_device *rdev) -{ - uint8_t buffer[1024]; - size_t sz_left; - size_t offset; - - sz_left = region_device_sz(rdev); - offset = 0; - - while (sz_left) { - int rv; - size_t block_sz = MIN(sz_left, sizeof(buffer)); - - if (rdev_readat(rdev, buffer, offset, block_sz) != block_sz) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_buffer(ctx, buffer, block_sz); - - if (rv) - return rv; - - sz_left -= block_sz; - offset += block_sz; - } - - return VB2_SUCCESS; -} - -/* Include offsets of child regions within the parent into the hash. */ -static int cbfs_extend_hash_with_offset(struct vb2_digest_context *ctx, - const struct region_device *p, - const struct region_device *c) -{ - int32_t soffset; - int rv; - - soffset = rdev_relative_offset(p, c); - - if (soffset < 0) - return VB2_ERROR_UNKNOWN; - - /* All offsets in big endian format. */ - write_be32(&soffset, soffset); - - rv = cbfs_extend_hash_buffer(ctx, &soffset, sizeof(soffset)); - - if (rv) - return rv; - - return cbfs_extend_hash(ctx, c); -} - -/* Hash in the potential CBFS header sitting at the beginning of the CBFS - * region as well as relative offset at the end. */ -static int cbfs_extend_hash_master_header(struct vb2_digest_context *ctx, - const struct region_device *cbfs) -{ - struct region_device rdev; - int rv; - - if (rdev_chain(&rdev, cbfs, 0, sizeof(struct cbfs_header))) - return VB2_ERROR_UNKNOWN; - - rv = cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); - - if (rv) - return rv; - - /* Include potential relative offset at end of region. */ - if (rdev_chain(&rdev, cbfs, region_device_sz(cbfs) - sizeof(int32_t), - sizeof(int32_t))) - return VB2_ERROR_UNKNOWN; - - return cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); -} - -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz) -{ - struct vb2_digest_context ctx; - int rv; - struct cbfsf f; - struct cbfsf *prev; - struct cbfsf *fh; - - rv = vb2_digest_init(&ctx, hash_alg); - - if (rv) - return rv; - - rv = cbfs_extend_hash_master_header(&ctx, cbfs); - if (rv) - return rv; - - prev = NULL; - fh = &f; - - while (1) { - uint32_t ftype; - - rv = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - if (rv < 0) - return VB2_ERROR_UNKNOWN; - - /* End of CBFS. */ - if (rv > 0) - break; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->metadata); - - if (rv) - return rv; - - /* Include data contents in hash if file is non-empty. */ - if (cbfsf_file_type(fh, &ftype)) - return VB2_ERROR_UNKNOWN; - - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) - continue; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); - - if (rv) - return rv; - } - - return vb2_digest_finalize(&ctx, digest, digest_sz); -} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h deleted file mode 100644 index 6565c1dcd3..0000000000 --- a/src/commonlib/include/commonlib/cbfs.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _COMMONLIB_CBFS_H_ -#define _COMMONLIB_CBFS_H_ - -#include -#include -#include - -/* Object representing cbfs files. */ -struct cbfsf { - struct region_device metadata; - struct region_device data; - union cbfs_mdata mdata; -}; - -/* Locate file by name and optional type. Returns 0 on success else < 0 on - * error.*/ -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type); - -static inline void cbfs_file_data(struct region_device *data, - const struct cbfsf *file) -{ - rdev_chain_full(data, &file->data); -} - -static inline void cbfs_file_metadata(struct region_device *metadata, - const struct cbfsf *file) -{ - rdev_chain_full(metadata, &file->metadata); -} - -/* - * Provide a handle to each cbfs file within a cbfs. The prev pointer represents - * the previous file (NULL on first invocation). The next object gets filled - * out with the next file. This returns < 0 on error, 0 on finding the next - * file, and > 0 at end of cbfs. - */ -int cbfs_for_each_file(const struct region_device *cbfs, - const struct cbfsf *prev, struct cbfsf *fh); - -/* - * Return the offset for each CBFS attribute in a CBFS file metadata region. - * The metadata must already be fully mapped by the caller. Will return the - * offset (relative to the start of the metadata) or 0 when there are no - * further attributes. Should be called with 0 to begin, then always with - * the previously returned value until it returns 0. - */ -size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, - size_t last_offset); - -/* - * Find out the decompression algorithm and decompressed size of a non-stage - * CBFS file (by parsing its metadata attributes), and return them with - * out-parameters. Returns 0 on success and < 0 on error. - */ -int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size); - -/* - * Return the CBFS file type as out-parameter. - * Returns 0 on success and < 0 on error. - */ -int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype); - -/* - * Perform the vb2 hash over the CBFS region skipping empty file contents. - * Caller is responsible for providing the hash algorithm as well as storage - * for the final digest. Return 0 on success or non-zero on error. - */ -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz); - -#endif diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h index f2687509af..34d9824179 100644 --- a/src/commonlib/include/commonlib/loglevel.h +++ b/src/commonlib/include/commonlib/loglevel.h @@ -157,4 +157,64 @@ #define BIOS_NEVER 9 /** @} */ +#ifndef __ASSEMBLER__ + +/* + * When printing logs, lines should be printed with the following prefixes in + * front of them according to the BIOS_LOG_PREFIX_PATTERN printf() pattern. + */ +#define BIOS_LOG_PREFIX_PATTERN "[%.5s] " +#define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW +static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = { + /* Note: These strings are *not* null-terminated to save space. */ + [BIOS_EMERG] = "EMERG", + [BIOS_ALERT] = "ALERT", + [BIOS_CRIT] = "CRIT ", + [BIOS_ERR] = "ERROR", + [BIOS_WARNING] = "WARN ", + [BIOS_NOTICE] = "NOTE ", + [BIOS_INFO] = "INFO ", + [BIOS_DEBUG] = "DEBUG", + [BIOS_SPEW] = "SPEW ", +}; + +/* + * When printing to terminals supporting ANSI escape sequences, the following + * escape sequences can be printed to highlight the respective log levels + * according to the BIOS_LOG_ESCAPE_PATTERN printf() pattern. At the end of a + * line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET seqence. + * + * The escape sequences used here set flags with the following meanings: + * 1 = bold, 4 = underlined, 5 = blinking, 7 = inverted + */ +#define BIOS_LOG_ESCAPE_PATTERN "\x1b[%sm" +#define BIOS_LOG_ESCAPE_RESET "\x1b[0m" +static const char bios_log_escape[BIOS_LOG_PREFIX_MAX_LEVEL + 1][8] = { + [BIOS_EMERG] = "1;4;5;7", + [BIOS_ALERT] = "1;4;7", + [BIOS_CRIT] = "1;7", + [BIOS_ERR] = "7", + [BIOS_WARNING] = "1;4", + [BIOS_NOTICE] = "1", + [BIOS_INFO] = "0", + [BIOS_DEBUG] = "0", + [BIOS_SPEW] = "0", +}; + +/* + * When storing console logs somewhere for later retrieval, log level prefixes + * and escape sequences should not be stored raw to preserve space. Instead, a + * non-printable control character marker is inserted into the log to indicate + * the log level. Decoders reading this character should translate it back into + * the respective escape sequence and prefix. If a decoder doesn't support this + * feature, the non-printable character should usually be harmless. + */ +#define BIOS_LOG_MARKER_START 0x10 +#define BIOS_LOG_MARKER_END (BIOS_LOG_MARKER_START + BIOS_LOG_PREFIX_MAX_LEVEL) +#define BIOS_LOG_IS_MARKER(c) ((c) >= BIOS_LOG_MARKER_START && (c) <= BIOS_LOG_MARKER_END) +#define BIOS_LOG_LEVEL_TO_MARKER(level) (BIOS_LOG_MARKER_START + (level)) +#define BIOS_LOG_MARKER_TO_LEVEL(c) ((c) - BIOS_LOG_MARKER_START) + +#endif /* __ASSEMBLER__ */ + #endif /* LOGLEVEL_H */ diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index 6c85397314..42b5d1ed96 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -3,6 +3,7 @@ #ifndef _MEM_POOL_H_ #define _MEM_POOL_H_ +#include #include #include @@ -16,23 +17,23 @@ * were chosen to optimize for the CBFS cache case which may need two buffers * to map a single compressed file, and will free them in reverse order.) * - * The memory returned by allocations are at least 8 byte aligned. Note - * that this requires the backing buffer to start on at least an 8 byte - * alignment. + * You must ensure the backing buffer is 'alignment' aligned. */ struct mem_pool { uint8_t *buf; size_t size; + size_t alignment; uint8_t *last_alloc; uint8_t *second_to_last_alloc; size_t free_offset; }; -#define MEM_POOL_INIT(buf_, size_) \ +#define MEM_POOL_INIT(buf_, size_, alignment_) \ { \ .buf = (buf_), \ .size = (size_), \ + .alignment = (alignment_), \ .last_alloc = NULL, \ .second_to_last_alloc = NULL, \ .free_offset = 0, \ @@ -46,10 +47,15 @@ static inline void mem_pool_reset(struct mem_pool *mp) } /* Initialize a memory pool. */ -static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz) +static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz, + size_t alignment) { + assert(alignment); + assert((uintptr_t)buf % alignment == 0); + mp->buf = buf; mp->size = sz; + mp->alignment = alignment; mem_pool_reset(mp); } diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 5d73d9e199..25efcc8724 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -163,7 +163,7 @@ static inline int rdev_chain_full(struct region_device *child, * * You must ensure the buffer is large enough to hold the full region_device. */ -static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b) +static inline ssize_t rdev_read_full(const struct region_device *rd, void *b) { return rdev_readat(rd, b, 0, region_device_sz(rd)); } diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 98fe552b47..492508ef40 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -7,7 +7,7 @@ struct timestamp_entry { uint32_t entry_id; - uint64_t entry_stamp; + int64_t entry_stamp; } __packed; struct timestamp_table { @@ -56,6 +56,8 @@ enum timestamp_id { TS_DELAY_END = 111, TS_READ_UCODE_START = 112, TS_READ_UCODE_END = 113, + TS_ELOG_INIT_START = 114, + TS_ELOG_INIT_END = 115, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -117,9 +119,10 @@ enum timestamp_id { TS_ME_ICC_CONFIG_START = 945, TS_ME_HOST_BOOT_PREP_DONE = 946, TS_ME_RECEIVED_CRDA_FROM_PMC = 947, - TS_FIT_UCODE_LOADED = 948, + TS_START_CSE_FW_SYNC = 948, + TS_END_CSE_FW_SYNC = 949, - /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ + /* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, TS_FSP_MEMORY_INIT_END = 951, TS_FSP_TEMP_RAM_EXIT_START = 952, @@ -137,6 +140,9 @@ enum timestamp_id { TS_FSP_MEMORY_INIT_LOAD = 970, TS_FSP_SILICON_INIT_LOAD = 971, + /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ + TS_ME_ROM_START = 990, + /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ /* Depthcharge entry IDs start at 1000 */ @@ -200,6 +206,8 @@ static const struct timestamp_id_to_name { { TS_DELAY_END, "Forced delay end" }, { TS_READ_UCODE_START, "started reading uCode" }, { TS_READ_UCODE_END, "finished reading uCode" }, + { TS_ELOG_INIT_START, "started elog init" }, + { TS_ELOG_INIT_END, "finished elog init" }, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, @@ -276,7 +284,9 @@ static const struct timestamp_id_to_name { { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"}, { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, - { TS_FIT_UCODE_LOADED, "CPU has loaded UCODE/PCODE from FIT"}, + { TS_START_CSE_FW_SYNC, "starting CSE firmware sync"}, + { TS_END_CSE_FW_SYNC, "finished CSE firmware sync"}, + { TS_ME_ROM_START, "CSME ROM started execution"}, /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index c300c65d6e..d82ab18bd7 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -7,8 +7,11 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz) { void *p; - /* Make all allocations be at least 8 byte aligned. */ - sz = ALIGN_UP(sz, 8); + if (mp->alignment == 0) + return NULL; + + /* We assume that mp->buf started mp->alignment aligned */ + sz = ALIGN_UP(sz, mp->alignment); /* Determine if any space available. */ if ((mp->size - mp->free_offset) < sz) diff --git a/src/commonlib/storage/sd_mmc.h b/src/commonlib/storage/sd_mmc.h index 9f6c077ab1..411a4a3052 100644 --- a/src/commonlib/storage/sd_mmc.h +++ b/src/commonlib/storage/sd_mmc.h @@ -71,7 +71,7 @@ int sd_set_partition(struct storage_media *media, if (CONFIG(SDHC_TRACE)) \ printk(BIOS_DEBUG, format); \ } while (0) -#define sdhc_error(format...) printk(BIOS_ERR, "ERROR: " format) +#define sdhc_error(format...) printk(BIOS_ERR, format) /* Card/device debug functions */ #define sd_mmc_debug(format...) \ @@ -84,6 +84,6 @@ int sd_set_partition(struct storage_media *media, if (CONFIG(SD_MMC_TRACE)) \ printk(BIOS_DEBUG, format); \ } while (0) -#define sd_mmc_error(format...) printk(BIOS_ERR, "ERROR: " format) +#define sd_mmc_error(format...) printk(BIOS_ERR, format) #endif /* __COMMONLIB_STORAGE_SD_MMC_H__ */ diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 6d39a45f5e..16420d99fa 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -6,14 +6,15 @@ #include "bouncebuf.h" #include #include +#include #include #include #include +#include #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" #include -#include #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \ @@ -411,36 +412,6 @@ static int sdhci_set_clock(struct sdhci_ctrlr *sdhci_ctrlr, unsigned int clock) return 0; } -/* Find leftmost set bit in a 32 bit integer */ -static int fls(u32 x) -{ - int r = 32; - - if (!x) - return 0; - if (!(x & 0xffff0000u)) { - x <<= 16; - r -= 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r -= 1; - } - return r; -} - static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr, unsigned short power) { @@ -718,7 +689,7 @@ static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr) if (rv) return rv; /* The error has been already reported */ - sdhci_set_power(sdhci_ctrlr, fls(ctrlr->voltages) - 1); + sdhci_set_power(sdhci_ctrlr, __fls(ctrlr->voltages)); if (ctrlr->caps & DRVR_CAP_NO_CD) { unsigned int status; diff --git a/src/console/Kconfig b/src/console/Kconfig index 4c2e768685..37d8fefe96 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -47,7 +47,7 @@ config FIXED_UART_FOR_CONSOLE specific UART has to be used (e.g. when the platform code performs dangerous configurations). -if CONSOLE_SERIAL +if CONSOLE_SERIAL || CONSOLE_CBMEM_DUMP_TO_UART comment "I/O mapped, 8250-compatible" depends on DRIVERS_UART_8250IO @@ -255,6 +255,14 @@ config CONSOLE_CBMEM_DUMP_TO_UART serial output in case serial console is disabled and the device resets itself while trying to boot the payload. +config CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS + bool + help + Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not + have the ability to log to the UART, so their console messages are + inaccessible until the boot processes gets into the payload or OS. + This feature will dump the pre-bootblock CBMEM console immediately + after the bootblock console is initialized. endif config CONSOLE_SPI_FLASH @@ -387,6 +395,15 @@ config DEFAULT_CONSOLE_LOGLEVEL endif +config CONSOLE_USE_ANSI_ESCAPES + bool "Use ANSI escape sequences for console highlighting" + default y + help + If enabled, certain consoles (e.g. UART) that are meant to be read on + a terminal will use ANSI escape sequences (like `ESC [1m`) to + highlight lines based on their log level. Disable this if your + terminal does not support ANSI escape sequences. + config NO_POST bool "Don't show any POST codes" default n diff --git a/src/console/console.c b/src/console/console.c index 67da10794e..f37f120f82 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -11,6 +11,8 @@ #include #include +/* Note: when adding a new console, make sure you update the definition of + HAS_ONLY_FAST_CONSOLES in ! */ void console_hw_init(void) { __cbmemc_init(); @@ -25,28 +27,35 @@ void console_hw_init(void) __system76_ec_init(); } -void console_tx_byte(unsigned char byte) +void console_interactive_tx_byte(unsigned char byte, void *data_unused) { - __cbmemc_tx_byte(byte); - __spkmodem_tx_byte(byte); - __qemu_debugcon_tx_byte(byte); - - /* Some consoles want newline conversion - * to keep terminals happy. - */ if (byte == '\n') { + /* Some consoles want newline conversion to keep terminals happy. */ __uart_tx_byte('\r'); __usb_tx_byte('\r'); } + __spkmodem_tx_byte(byte); + __qemu_debugcon_tx_byte(byte); __uart_tx_byte(byte); __ne2k_tx_byte(byte); __usb_tx_byte(byte); __spiconsole_tx_byte(byte); - __flashconsole_tx_byte(byte); __system76_ec_tx_byte(byte); } +void console_stored_tx_byte(unsigned char byte, void *data_unused) +{ + __flashconsole_tx_byte(byte); + __cbmemc_tx_byte(byte); +} + +void console_tx_byte(unsigned char byte) +{ + console_interactive_tx_byte(byte, NULL); + console_stored_tx_byte(byte, NULL); +} + void console_tx_flush(void) { __uart_tx_flush(); diff --git a/src/console/init.c b/src/console/init.c index 4427d681e2..4f93997f95 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -13,7 +14,7 @@ static int console_inited; static int console_loglevel; -static inline int get_log_level(void) +int get_log_level(void) { if (console_inited == 0) return -1; @@ -59,6 +60,9 @@ void console_init(void) console_inited = 1; + if (ENV_BOOTBLOCK && CONFIG(CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS)) + cbmem_dump_console(); + printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", coreboot_version, coreboot_extra_version, coreboot_build, get_log_level()); diff --git a/src/console/post.c b/src/console/post.c index 21ab00084a..1d99a2e9dd 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -19,7 +19,7 @@ void post_code(uint8_t value) arch_post_code(value); if (CONFIG(CONSOLE_POST)) - printk(BIOS_EMERG, "POST: 0x%02x\n", value); + printk(BIOS_INFO, "POST: 0x%02x\n", value); mainboard_post(value); } diff --git a/src/console/printk.c b/src/console/printk.c index 1ed39cb5ff..eb35c53f22 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -59,37 +59,90 @@ void do_putchar(unsigned char byte) console_time_stop(); } -static void wrap_putchar(unsigned char byte, void *data) +union log_state { + void *as_ptr; + struct { + uint8_t level; + uint8_t speed; + }; +}; + +#define LOG_FAST(state) (HAS_ONLY_FAST_CONSOLES || ((state).speed == CONSOLE_LOG_FAST)) + +static void wrap_interactive_printf(const char *fmt, ...) { - console_tx_byte(byte); + va_list args; + va_start(args, fmt); + vtxprintf(console_interactive_tx_byte, fmt, args, NULL); + va_end(args); } -static void wrap_putchar_cbmemc(unsigned char byte, void *data) +static void line_start(union log_state state) { - __cbmemc_tx_byte(byte); + if (state.level > BIOS_LOG_PREFIX_MAX_LEVEL) + return; + + /* Stored consoles just get a single control char marker to save space. If we are in + LOG_FAST mode, just write the marker to CBMC and exit -- the rest of this function + implements the LOG_ALL case. */ + unsigned char marker = BIOS_LOG_LEVEL_TO_MARKER(state.level); + if (LOG_FAST(state)) { + __cbmemc_tx_byte(marker); + return; + } + console_stored_tx_byte(marker, NULL); + + /* Interactive consoles get a `[DEBUG] ` style readable prefix, + and potentially an escape sequence for highlighting. */ + if (CONFIG(CONSOLE_USE_ANSI_ESCAPES)) + wrap_interactive_printf(BIOS_LOG_ESCAPE_PATTERN, bios_log_escape[state.level]); + wrap_interactive_printf(BIOS_LOG_PREFIX_PATTERN, bios_log_prefix[state.level]); +} + +static void line_end(union log_state state) +{ + if (CONFIG(CONSOLE_USE_ANSI_ESCAPES) && !LOG_FAST(state)) + wrap_interactive_printf(BIOS_LOG_ESCAPE_RESET); +} + +static void wrap_putchar(unsigned char byte, void *data) +{ + union log_state state = { .as_ptr = data }; + static bool line_started = false; + + if (byte == '\n') { + line_end(state); + line_started = false; + } else if (!line_started) { + line_start(state); + line_started = true; + } + + if (LOG_FAST(state)) + __cbmemc_tx_byte(byte); + else + console_tx_byte(byte); } int vprintk(int msg_level, const char *fmt, va_list args) { - int i, log_this; + union log_state state = { .level = msg_level }; + int i; if (CONFIG(SQUELCH_EARLY_SMP) && ENV_ROMSTAGE_OR_BEFORE && !boot_cpu()) return 0; - log_this = console_log_level(msg_level); - if (log_this < CONSOLE_LOG_FAST) + state.speed = console_log_level(msg_level); + if (state.speed < CONSOLE_LOG_FAST) return 0; spin_lock(&console_lock); console_time_run(); - if (log_this == CONSOLE_LOG_FAST) { - i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL); - } else { - i = vtxprintf(wrap_putchar, fmt, args, NULL); + i = vtxprintf(wrap_putchar, fmt, args, state.as_ptr); + if (LOG_FAST(state)) console_tx_flush(); - } console_time_stop(); diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 2a5143070d..f8055dadcc 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -244,7 +244,7 @@ repeat: case 'X': flags |= LARGE; - /* fall through */ + __fallthrough; case 'x': base = 16; break; @@ -252,6 +252,7 @@ repeat: case 'd': case 'i': flags |= SIGN; + __fallthrough; case 'u': break; diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index ec2f19fd18..2d90638bd5 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += intel subdirs-y += ti subdirs-$(CONFIG_ARCH_X86) += x86 subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 +subdirs-$(CONFIG_CPU_POWER9) += power9 $(eval $(call create_class_compiler,cpu_microcode,x86_32)) ################################################################################ @@ -56,7 +57,12 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +cpu_microcode_blob.bin-align := 64 +else cpu_microcode_blob.bin-align := 16 +endif ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 15622c94e6..266fc89bc8 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -12,7 +12,6 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select SMM_ASEG select SSE2 if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 103903fc1e..fc1b878e63 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -2,12 +2,5 @@ config CPU_AMD_AGESA_FAMILY14 bool + select NO_SMM select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY14 - -config CPU_ADDR_BITS - int - default 36 - -endif diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index b47c4f0f65..16caf40f15 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 78234b663e..8b67a95b9d 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -25,9 +24,7 @@ static void model_14_init(struct device *dev) disable_cache(); /* * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. - * TODO: - * amd_setup_mtrrs(); + * by coreboot. */ /* Enable access to AMD RdDram and WrDram extension bits */ @@ -59,9 +56,6 @@ static void model_14_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 8c52e9a9b6..0cccaa6f00 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -3,12 +3,5 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select IDS_OPTIONS_HOOKED_UP + select SMM_ASEG select X86_AMD_FIXED_MTRRS - -if CPU_AMD_AGESA_FAMILY15_TN - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index a5914475e8..ca51196c66 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -9,4 +9,4 @@ ramstage-y += model_15_init.c smm-y += udelay.c subdirs-y += ../../mtrr -subdirs-y += ../../smm +subdirs-$(CONFIG_SMM_LEGACY_ASEG) += ../../smm diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index ebfa07da08..feb85bfe43 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 245cdf34f9..77f9e9a8c6 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -25,9 +24,10 @@ static void model_15_init(struct device *dev) u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); @@ -58,9 +58,6 @@ static void model_15_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index e41ddece4d..60bf64f2db 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -2,14 +2,11 @@ config CPU_AMD_AGESA_FAMILY16_KB bool + select SMM_ASEG select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB -config CPU_ADDR_BITS - int - default 40 - config FORCE_AM1_SOCKET_SUPPORT bool default n diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 3771a064c7..5e43b17d3b 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index c86f8acdef..2ced7b9851 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -23,9 +22,10 @@ static void model_16_init(struct device *dev) u32 siblings; #endif - //enable_cache(); - //amd_setup_mtrrs(); - //x86_mtrr_check(); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); @@ -56,9 +56,6 @@ static void model_16_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index fc3212f1fc..d17eedd919 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -3,72 +3,11 @@ #include #include #include -#include -#include -#include #include -#include - -/* These will likely move to some device node or cbmem. */ -static uint64_t amd_topmem = 0; -static uint64_t amd_topmem2 = 0; - -uint64_t bsp_topmem(void) -{ - return amd_topmem; -} - -uint64_t bsp_topmem2(void) -{ - return amd_topmem2; -} - -/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, - * so they can be distributed to AP CPUs. Not strictly MTRRs, - * but this is not that bad a place to have this code. - */ -void setup_bsp_ramtop(void) -{ - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; -} - -static void setup_ap_ramtop(void) -{ - msr_t msr; - uint64_t v; - - v = bsp_topmem(); - if (!v) - return; - - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM, msr); - - v = bsp_topmem2(); - msr.hi = v >> 32; - msr.lo = (uint32_t) v; - wrmsr(TOP_MEM2, msr); -} void add_uma_resource_below_tolm(struct device *nb, int idx) { - uint32_t topmem = bsp_topmem(); + uint32_t topmem = amd_topmem(); uint32_t top_of_cacheable = restore_top_of_low_cacheable(); if (top_of_cacheable == topmem) @@ -82,79 +21,3 @@ void add_uma_resource_below_tolm(struct device *nb, int idx) uma_resource(nb, idx, uma_base / KiB, uma_size / KiB); } - -void amd_setup_mtrrs(void) -{ - unsigned long address_bits; - unsigned long i; - msr_t msr, sys_cfg; - // Test if this CPU is a Fam 0Fh rev. F or later - const int cpu_id = cpuid_eax(0x80000001); - printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); - const int has_tom2wb = - // ExtendedFamily > 0 - (((cpu_id>>20)&0xf) > 0) || - // Family == 0F - ((((cpu_id>>8)&0xf) == 0xf) && - // Rev>=F deduced from rev tables - (((cpu_id>>16)&0xf) >= 0x4)); - if (has_tom2wb) - printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); - - /* Enable the access to AMD RdDram and WrDram extension bits */ - disable_cache(); - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - enable_cache(); - - /* Setup fixed MTRRs, but do not enable them just yet. */ - x86_setup_fixed_mtrrs_no_enable(); - - disable_cache(); - - setup_ap_ramtop(); - - /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ - sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1 << 32) { - sys_cfg.lo |= SYSCFG_MSR_TOM2En; - if (has_tom2wb) - sys_cfg.lo |= SYSCFG_MSR_TOM2WB; - } - - /* zero the IORR's before we enable to prevent - * undefined side effects. - */ - msr.lo = msr.hi = 0; - for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++) - wrmsr(i, msr); - - /* Enable Variable Mtrrs - * Enable the RdMem and WrMem bits in the fixed mtrrs. - * Disable access to the RdMem and WrMem in the fixed mtrr. - */ - sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn; - sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_fixed_mtrr(); - - enable_cache(); - - //K8 could be 40, and GH could be 48 - address_bits = CONFIG_CPU_ADDR_BITS; - - /* AMD specific cpuid function to query number of address bits */ - if (cpuid_eax(0x80000000) >= 0x80000008) - address_bits = cpuid_eax(0x80000008) & 0xff; - - /* Now that I have mapped what is memory and what is not - * Set up the mtrrs so we can cache the memory. - */ - - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need - // variable MTRR to span memory above 4GB - // Lower revisions K8 need variable MTRR over 4GB - x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1); -} diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 5296ee6399..6fd6332eec 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -5,11 +5,3 @@ config CPU_AMD_PI_00730F01 select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED - -if CPU_AMD_PI_00730F01 - -config CPU_ADDR_BITS - int - default 40 - -endif diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 9b208ecc4c..689fdecd15 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -32,7 +33,7 @@ void amd_initcpuio(void) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; + PciData = (HPET_BASE_ADDRESS >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a5a8064737..c743ffe3c5 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -23,27 +22,9 @@ static void model_16_init(struct device *dev) msr_t msr; u32 siblings; - /* - * All cores are initialized sequentially, so the solution for APs will be created - * before they start. - */ - x86_setup_mtrrs_with_detect(); - /* - * Enable ROM caching on BSP we just lost when creating MTRR solution, for faster - * execution of e.g. AmdInitLate - */ - if (boot_cpu()) { - mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - } - x86_mtrr_check(); - /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - if (CONFIG(LOGICAL_CPUS)) { siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index aff8d7dc97..2336d68f96 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -10,7 +10,7 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select SMM_ASEG + select NO_SMM select SSE2 if CPU_AMD_PI diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc index a645122f44..97a669455d 100644 --- a/src/cpu/amd/smm/Makefile.inc +++ b/src/cpu/amd/smm/Makefile.inc @@ -1,2 +1,2 @@ -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_init.c +ramstage-y += smm_init.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index 909f75ac40..ef0a5d9044 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -8,6 +8,7 @@ void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); +void set_feature_ctrl_vmx_arg(bool enable); void set_feature_ctrl_lock(void); /* diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 765a174dd1..24e3eeb60b 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "common.h" @@ -16,11 +15,10 @@ void set_vmx_and_lock(void) set_feature_ctrl_lock(); } -void set_feature_ctrl_vmx(void) +void set_feature_ctrl_vmx_arg(bool enable) { msr_t msr; uint32_t feature_flag; - int enable = CONFIG(ENABLE_VMX); feature_flag = cpu_get_feature_flags_ecx(); /* Check that the VMX is supported before reading or writing the MSR. */ @@ -62,6 +60,12 @@ void set_feature_ctrl_vmx(void) printk(BIOS_DEBUG, "VMX status: %s\n", enable ? "enabled" : "disabled"); } + +void set_feature_ctrl_vmx(void) +{ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX)); +} + void set_feature_ctrl_lock(void) { msr_t msr; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2ab77b3044..90ac5f4fad 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -541,9 +540,7 @@ static void cpu_core_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); @@ -588,8 +585,8 @@ static void pre_mp_init(void) static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 93d29d4d29..9fde031418 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -#include /* Intel hyper-threading requires serialized CPU init. */ diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 3e4de1fa31..02e6032265 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -12,18 +11,6 @@ #include "chip.h" -static void init_timer(void) -{ - /* Set the APIC timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); -} - #define MSR_BBL_CR_CTL3 0x11e static void configure_c_states(const int quad) @@ -268,12 +255,6 @@ static void model_1067x_init(struct device *cpu) fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - - /* Initialize the APIC timer */ - init_timer(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 9a1fc42d3e..bc53214310 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -23,7 +23,7 @@ static void pre_mp_init(void) static int get_cpu_count(void) { const struct cpuid_result cpuid1 = cpuid(1); - const char cores = (cpuid1.ebx >> 16) & 0xf; + const unsigned int cores = (cpuid1.ebx >> 16) & 0xf; printk(BIOS_DEBUG, "CPU has %u cores.\n", cores); diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index ac45cfafe2..85f6288719 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -8,14 +8,5 @@ config CPU_INTEL_MODEL_106CX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS - select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - -if CPU_INTEL_MODEL_106CX - -config CPU_ADDR_BITS - int - default 32 - -endif diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 278d8dea81..4cf16d8831 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -67,9 +66,6 @@ static void model_106cx_init(struct device *cpu) fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 9c8b18039f..251fd75b50 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,6 +20,7 @@ #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_POWER_CTL 0x1fc diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 30519c0256..35b153eb4b 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -91,9 +91,7 @@ static void model_2065x_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); @@ -124,8 +122,8 @@ static void pre_mp_init(void) static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d240f53761..52d11d72fe 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -338,9 +337,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); @@ -380,8 +377,8 @@ static void pre_mp_init(void) static int get_cpu_count(void) { msr_t msr; - int num_threads; - int num_cores; + unsigned int num_threads; + unsigned int num_cores; msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 9a17f7093f..15246b6396 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -19,9 +18,6 @@ static void model_65x_init(struct device *dev) enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 6a2689ddb1..d524705031 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -22,9 +21,6 @@ static void model_67x_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 2344cb7e9f..0b5d4541b9 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -26,9 +25,6 @@ static void model_68x_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index f27a63ac50..0e54f934e6 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -26,9 +25,6 @@ static void model_6bx_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 34646ad5e9..bfa4a3e5f1 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -106,9 +105,6 @@ static void model_6ex_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23935..a481a674f6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -120,9 +119,6 @@ static void model_6fx_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 48a045ecc8..f9afc6cbad 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include @@ -16,9 +15,6 @@ static void model_6xx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 9f365c6ebc..294d579f8e 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -23,9 +22,6 @@ static void model_f2x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index ba3a4d60da..fdc5a1ef1d 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -23,9 +22,6 @@ static void model_f3x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index ee6761ed13..b495dee585 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -2,16 +2,12 @@ #include #include -#include #include static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 5105f095e9..681ca41682 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX select MMX - select SSE select CPU_HAS_L2_ENABLE_MSR config DCACHE_RAM_BASE diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 7d0bce704e..3c9f262e3f 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -10,7 +10,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_F4X select CPU_INTEL_MODEL_1067X select MMX - select SSE select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 50eb7e3f0c..4e74eb4fad 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX select MMX - select SSE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index a7c8ab1bb8..4b99acead2 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -3,7 +3,6 @@ config CPU_INTEL_SOCKET_P select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX select MMX - select SSE if CPU_INTEL_SOCKET_P diff --git a/src/cpu/power9/Kconfig b/src/cpu/power9/Kconfig new file mode 100644 index 0000000000..c3a628cc34 --- /dev/null +++ b/src/cpu/power9/Kconfig @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config CPU_POWER9 + bool + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 diff --git a/src/cpu/power9/Makefile.inc b/src/cpu/power9/Makefile.inc new file mode 100644 index 0000000000..2fe9e57a96 --- /dev/null +++ b/src/cpu/power9/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += power9.c + +bootblock-y += scom.c +romstage-y += scom.c diff --git a/src/cpu/power9/power9.c b/src/cpu/power9/power9.c new file mode 100644 index 0000000000..fd33ff219b --- /dev/null +++ b/src/cpu/power9/power9.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static void power9_cpu_init(struct device *dev) +{ +} + +static struct device_operations cpu_dev_ops = { + .init = power9_cpu_init, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, +}; + +struct chip_operations cpu_power8_qemu_ops = { + CHIP_NAME("POWER9 CPU") +}; diff --git a/src/cpu/power9/scom.c b/src/cpu/power9/scom.c new file mode 100644 index 0000000000..e55d149bff --- /dev/null +++ b/src/cpu/power9/scom.c @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include // HMER +#include + +#define XSCOM_DATA_IND_READ PPC_BIT(0) +#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32) +#define XSCOM_DATA_IND_ERR PPC_BITMASK(33, 35) +#define XSCOM_DATA_IND_DATA PPC_BITMASK(48, 63) +#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12, 63) +#define XSCOM_IND_MAX_RETRIES 10 + +#define XSCOM_RCVED_STAT_REG 0x00090018 +#define XSCOM_LOG_REG 0x00090012 +#define XSCOM_ERR_REG 0x00090013 + +uint64_t read_scom_direct(uint64_t reg_address) +{ + uint64_t val; + uint64_t hmer = 0; + do { + /* + * Clearing HMER on every SCOM access seems to slow down CCS up + * to a point where it starts hitting timeout on "less ideal" + * DIMMs for write centering. Clear it only if this do...while + * executes more than once. + */ + if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) + clear_hmer(); + + eieio(); + asm volatile( + "ldcix %0, %1, %2" : + "=r"(val) : + "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), + "r"(reg_address << 3)); + eieio(); + hmer = read_hmer(); + } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); + + if (hmer & SPR_HMER_XSCOM_STATUS) { + reset_scom_engine(); + /* + * All F's are returned in case of error, but code polls for a set bit + * after changes that can make such error appear (e.g. clock settings). + * Return 0 so caller won't have to test for all F's in that case. + */ + return 0; + } + return val; +} + +void write_scom_direct(uint64_t reg_address, uint64_t data) +{ + uint64_t hmer = 0; + do { + /* See comment in read_scom_direct() */ + if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED) + clear_hmer(); + + eieio(); + asm volatile( + "stdcix %0, %1, %2":: + "r"(data), + "b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR), + "r"(reg_address << 3)); + eieio(); + hmer = read_hmer(); + } while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED); + + if (hmer & SPR_HMER_XSCOM_STATUS) + reset_scom_engine(); +} + +void write_scom_indirect(uint64_t reg_address, uint64_t value) +{ + uint64_t addr; + uint64_t data; + addr = reg_address & 0x7FFFFFFF; + data = reg_address & XSCOM_ADDR_IND_ADDR; + data |= value & XSCOM_ADDR_IND_DATA; + + write_scom_direct(addr, data); + + for (int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + data = read_scom_direct(addr); + if ((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + return; + } else if (data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "SCOM WR error %16.16llx = %16.16llx : %16.16llx\n", + reg_address, value, data); + } + // TODO: delay? + } +} + +uint64_t read_scom_indirect(uint64_t reg_address) +{ + uint64_t addr; + uint64_t data; + addr = reg_address & 0x7FFFFFFF; + data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR); + + write_scom_direct(addr, data); + + for (int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) { + data = read_scom_direct(addr); + if ((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) { + break; + } else if (data & XSCOM_DATA_IND_COMPLETE) { + printk(BIOS_EMERG, "SCOM RD error %16.16llx : %16.16llx\n", + reg_address, data); + } + // TODO: delay? + } + + return data & XSCOM_DATA_IND_DATA; +} + +/* This function should be rarely called, don't make it inlined */ +void reset_scom_engine(void) +{ + /* + * With cross-CPU SCOM accesses, first register should be cleared on the + * executing CPU, the other two on target CPU. In that case it may be + * necessary to do the remote writes in assembly directly to skip checking + * HMER and possibly end in a loop. + */ + write_scom_direct(XSCOM_RCVED_STAT_REG, 0); + write_scom_direct(XSCOM_LOG_REG, 0); + write_scom_direct(XSCOM_ERR_REG, 0); + clear_hmer(); + eieio(); +} diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 9f01007e2a..f0cdb58604 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -2,11 +2,9 @@ #include #include -#include static void qemu_cpu_init(struct device *dev) { - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 4d1149ee6c..3ac86a9df1 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -68,7 +68,6 @@ __longmode_compatibility: movl %eax, %es movl %eax, %ss movl %eax, %fs - movl %eax, %gs /* Disable paging. */ movl %cr0, %eax diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index eea104bcf3..c27f540ba3 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -15,6 +15,10 @@ protected_mode_call_narg: push %r14 push %r15 + /* Backup gs to stack */ + movl %gs, %eax + push %rax + /* Arguments to stack */ push %rdi push %rsi @@ -23,9 +27,9 @@ protected_mode_call_narg: #include - movl -48(%ebp), %eax /* Argument count */ - movl -64(%ebp), %edx /* Argument 0 */ - movl -72(%ebp), %ecx /* Argument 1 */ + movl -56(%ebp), %eax /* Argument count */ + movl -72(%ebp), %edx /* Argument 0 */ + movl -80(%ebp), %ecx /* Argument 1 */ /* Align the stack */ andl $0xFFFFFFF0, %esp @@ -46,7 +50,7 @@ protected_mode_call_narg: pushl %edx /* Argument 0 */ 1: - movl -56(%ebp), %ebx /* Function to call */ + movl -64(%ebp), %ebx /* Function to call */ call *%ebx movl %eax, %ebx @@ -57,6 +61,8 @@ protected_mode_call_narg: movl %ebx, %eax /* Restore registers */ + mov -48(%rbp), %rbx + movl %ebx, %gs mov -40(%rbp), %r15 mov -32(%rbp), %r14 mov -24(%rbp), %r13 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index fb5b5413b9..86f31e05c7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,12 +1,13 @@ config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT - depends on SMP select CPU_INFO_V2 help This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs. + The code also works for just initialising the BSP in case there + are no APs. config PARALLEL_MP_AP_WORK def_bool n @@ -90,10 +91,6 @@ config SETUP_XIP_CACHE non-eviction mode and therefore need to be careful to avoid eviction. -config CPU_ADDR_BITS - int - default 36 - config LOGICAL_CPUS bool default y @@ -117,6 +114,12 @@ config SMM_TSEG default y depends on !(NO_SMM || SMM_ASEG) +config SMM_LEGACY_ASEG + bool + default y if HAVE_SMI_HANDLER && SMM_ASEG && LEGACY_SMP_INIT + help + SMM support without PARALLEL_MP, to be deprecated. + if SMM_TSEG config SMM_MODULE_HEAP_SIZE @@ -150,17 +153,6 @@ config SMM_LAPIC_REMAP_MITIGATION default y if NORTHBRIDGE_INTEL_IRONLAKE default n -config SERIALIZED_SMM_INITIALIZATION - bool - default n - help - On some CPUs, there is a race condition in SMM. - This can occur when both hyperthreads change SMM state - variables in parallel without coordination. - Setting this option serializes the SMM initialization - to avoid an ugly hang in the boot process at the cost - of a slightly longer boot time. - config X86_AMD_FIXED_MTRRS bool default n @@ -168,15 +160,15 @@ config X86_AMD_FIXED_MTRRS This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config X86_AMD_INIT_SIPI +config X86_INIT_NEED_1_SIPI bool default n help This option limits the number of SIPI signals sent during during the common AP setup. Intel documentation specifies an INIT SIPI SIPI - sequence, however this doesn't work on some AMD platforms. These - newer AMD platforms don't need the 10ms wait between INIT and SIPI, - so skip that too to save some time. + sequence, however this doesn't work on some AMD and Intel platforms. + These newer AMD and Intel platforms don't need the 10ms wait between + INIT and SIPI, so skip that too to save some time. config SOC_SETS_MSRS bool diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index b9f6417a22..b9705286f8 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -8,7 +8,10 @@ all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c + ramstage-y += backup_default_smm.c +ramstage-y += smi_trigger.c +smm-y += smi_trigger.c subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index b4d3c4de42..76f2d89db9 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -10,23 +11,52 @@ void enable_lapic(void) { + uintptr_t apic_base; + bool use_x2apic; msr_t msr; msr = rdmsr(LAPIC_BASE_MSR); - msr.hi &= 0xffffff00; - msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; - msr.lo |= LAPIC_DEFAULT_BASE; - msr.lo |= LAPIC_BASE_MSR_ENABLE; - wrmsr(LAPIC_BASE_MSR, msr); + if (!(msr.lo & LAPIC_BASE_MSR_ENABLE)) { + msr.hi &= 0xffffff00; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; + msr.lo |= LAPIC_BASE_MSR_ENABLE; + wrmsr(LAPIC_BASE_MSR, msr); + msr = rdmsr(LAPIC_BASE_MSR); + } + + ASSERT(msr.lo & LAPIC_BASE_MSR_ENABLE); + + apic_base = msr.lo & LAPIC_BASE_MSR_ADDR_MASK; + ASSERT(apic_base == LAPIC_DEFAULT_BASE); + + if (CONFIG(XAPIC_ONLY)) { + use_x2apic = false; + } else { + use_x2apic = !!(cpu_get_feature_flags_ecx() & CPUID_X2APIC); + ASSERT(CONFIG(X2APIC_RUNTIME) || use_x2apic); + } + + if (use_x2apic == !!(msr.lo & LAPIC_BASE_MSR_X2APIC_MODE)) { + printk(BIOS_INFO, "LAPIC 0x%x in %s mode.\n", lapicid(), + use_x2apic ? "X2APIC" : "XAPIC"); + } else if (use_x2apic) { + msr.lo |= LAPIC_BASE_MSR_X2APIC_MODE; + wrmsr(LAPIC_BASE_MSR, msr); + msr = rdmsr(LAPIC_BASE_MSR); + ASSERT(!!(msr.lo & LAPIC_BASE_MSR_X2APIC_MODE)); + printk(BIOS_INFO, "LAPIC 0x%x switched to X2APIC mode.\n", lapicid()); + } else { + die("Switching from X2APIC to XAPIC mode is not implemented."); + } - printk(BIOS_INFO, "Setting up local APIC 0x%x\n", lapicid()); } void disable_lapic(void) { msr_t msr; msr = rdmsr(LAPIC_BASE_MSR); - msr.lo &= ~LAPIC_BASE_MSR_ENABLE; + msr.lo &= ~(LAPIC_BASE_MSR_ENABLE | LAPIC_BASE_MSR_X2APIC_MODE); wrmsr(LAPIC_BASE_MSR, msr); } @@ -35,13 +65,7 @@ uintptr_t cpu_get_lapic_addr(void) return LAPIC_DEFAULT_BASE; } -/* See if I need to initialize the local APIC */ -static int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static void lapic_virtual_wire_mode_init(void) +void setup_lapic_interrupts(void) { /* * Set Task Priority to 'accept all'. @@ -64,17 +88,3 @@ static void lapic_virtual_wire_mode_init(void) lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } - -void setup_lapic(void) -{ - /* Enable the local APIC */ - if (need_lapic_init()) - enable_lapic(); - else if (!CONFIG(UDELAY_LAPIC)) - disable_lapic(); - - /* This programming is for PIC mode i8259 interrupts to be delivered to CPU - while LAPIC is enabled. */ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); -} diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index c35888a7fd..2cb84594e9 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -298,6 +298,11 @@ asmlinkage void secondary_cpu_init(unsigned int index) cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); #endif + + /* Ensure the local APIC is enabled */ + enable_lapic(); + setup_lapic_interrupts(); + cpu_initialize(index); spin_unlock(&start_cpu_lock); @@ -332,37 +337,6 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) } -static void smm_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) -{ - struct device *cpu; - int pre_count = atomic_read(&active_cpus); - - /* Loop through the cpus once to let them run through SMM relocator */ - - for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { - if (cpu->path.type != DEVICE_PATH_APIC) - continue; - - printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", - cpu->path.apic.apic_id); - - if (cpu == bsp_cpu) - continue; - - if (!cpu->enabled) - continue; - - if (!start_cpu(cpu)) - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU 0x%02x would not start!\n", - cpu->path.apic.apic_id); - - /* FIXME: endless loop */ - while (atomic_read(&active_cpus) != pre_count) - ; - } -} - static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -407,8 +381,12 @@ void initialize_cpus(struct bus *cpu_bus) info = cpu_info(); /* Ensure the local APIC is enabled */ - if (is_smp_boot()) + if (is_smp_boot()) { enable_lapic(); + setup_lapic_interrupts(); + } else { + disable_lapic(); + } /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; @@ -422,7 +400,7 @@ void initialize_cpus(struct bus *cpu_bus) if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); - if (!CONFIG(SERIALIZED_SMM_INITIALIZATION)) + if (CONFIG(SMM_LEGACY_ASEG)) smm_init(); /* Initialize the bootstrap processor */ @@ -435,19 +413,8 @@ void initialize_cpus(struct bus *cpu_bus) if (is_smp_boot()) wait_other_cpus_stop(cpu_bus); - if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) { - /* At this point, all APs are sleeping: - * smm_init() will queue a pending SMI on all cpus - * and smm_other_cpus() will start them one by one */ - smm_init(); - - if (is_smp_boot()) { - last_cpu_index = 0; - smm_other_cpus(cpu_bus, info->cpu); - } - } - - smm_init_completion(); + if (CONFIG(SMM_LEGACY_ASEG)) + smm_init_completion(); if (is_smp_boot()) recover_lowest_1M(); diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c index e933ce4c47..1affe15bed 100644 --- a/src/cpu/x86/lapic/lapic_cpu_stop.c +++ b/src/cpu/x86/lapic/lapic_cpu_stop.c @@ -55,7 +55,7 @@ void stop_this_cpu(void) printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); mdelay(10); @@ -63,7 +63,7 @@ void stop_this_cpu(void) dprintk(BIOS_SPEW, "Deasserting INIT.\n"); /* Deassert the LAPIC INIT */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); halt(); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c99732fb39..1f1f968ae7 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -185,6 +185,7 @@ static void asmlinkage ap_init(void) /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); info->cpu = cpus_dev[info->index]; @@ -423,8 +424,7 @@ static enum cb_err send_sipi_to_aps(int ap_count, atomic_t *num_aps, int sipi_ve printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, - 0); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "timed out.\n"); @@ -454,9 +454,6 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); - int x2apic_mode = is_x2apic_mode(); - printk(BIOS_DEBUG, "Starting CPUs in %s mode\n", x2apic_mode ? "x2apic" : "xapic"); - if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy...\n"); if (apic_wait_timeout(1000 /* 1 ms */, 50) != CB_SUCCESS) { @@ -467,9 +464,9 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap } /* Send INIT IPI to all but self. */ - lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT); - if (!CONFIG(X86_AMD_INIT_SIPI)) { + if (!CONFIG(X86_INIT_NEED_1_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); @@ -547,6 +544,7 @@ static void init_bsp(struct bus *cpu_bus) /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); /* Set the device path of the boot CPU. */ cpu_path.type = DEVICE_PATH_APIC; @@ -593,6 +591,10 @@ static enum cb_err mp_init(struct bus *cpu_bus, struct mp_params *p) return CB_ERR; } + /* We just need to run things on the BSP */ + if (!CONFIG(SMP)) + return bsp_do_flight_plan(p); + /* Default to currently running CPU. */ num_cpus = allocate_cpu_devices(cpu_bus, p); @@ -648,7 +650,7 @@ void smm_initiate_relocation_parallel(void) printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); + lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI); if (lapic_busy()) { if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) { @@ -758,22 +760,17 @@ static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) } static enum cb_err install_relocation_handler(int num_cpus, size_t real_save_state_size, - size_t save_state_size, uintptr_t perm_smbase) + size_t save_state_size) { struct smm_loader_params smm_params = { - .per_cpu_stack_size = CONFIG_SMM_STUB_STACK_SIZE, - .num_concurrent_stacks = num_cpus, + .num_cpus = num_cpus, .real_cpu_save_state_size = real_save_state_size, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = 1, .handler = smm_do_relocation, }; - /* Allow callback to override parameters. */ - if (mp_state.ops.adjust_smm_params != NULL) - mp_state.ops.adjust_smm_params(&smm_params, 0); - - if (smm_setup_relocation_handler((void *)perm_smbase, &smm_params)) { + if (smm_setup_relocation_handler(&smm_params)) { printk(BIOS_ERR, "%s: smm setup failed\n", __func__); return CB_ERR; } @@ -796,20 +793,15 @@ static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase, * size and save state size for each CPU. */ struct smm_loader_params smm_params = { - .per_cpu_stack_size = CONFIG_SMM_MODULE_STACK_SIZE, - .num_concurrent_stacks = num_cpus, + .num_cpus = num_cpus, .real_cpu_save_state_size = real_save_state_size, .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = num_cpus, }; - /* Allow callback to override parameters. */ - if (mp_state.ops.adjust_smm_params != NULL) - mp_state.ops.adjust_smm_params(&smm_params, 1); - printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase); - if (smm_load_module((void *)smbase, smsize, &smm_params)) + if (smm_load_module(smbase, smsize, &smm_params)) return CB_ERR; adjust_smm_apic_id_map(&smm_params); @@ -827,10 +819,15 @@ static void load_smm_handlers(void) if (!is_smm_enabled()) return; + if (smm_setup_stack(mp_state.perm_smbase, mp_state.perm_smsize, mp_state.cpu_count, + CONFIG_SMM_MODULE_STACK_SIZE)) { + printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); + smm_disable(); + } + /* Install handlers. */ if (install_relocation_handler(mp_state.cpu_count, real_save_state_size, - smm_save_state_size, mp_state.perm_smbase) != - CB_SUCCESS) { + smm_save_state_size) != CB_SUCCESS) { printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); smm_disable(); } @@ -1061,20 +1058,11 @@ static size_t smm_stub_size(void) return rmodule_memory_size(&smm_stub); } -static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops) { - /* - * Make copy of the ops so that defaults can be set in the non-const - * structure if needed. - */ - memcpy(&state->ops, ops, sizeof(*ops)); - - if (ops->get_cpu_count != NULL) - state->cpu_count = ops->get_cpu_count(); - if (ops->get_smm_info != NULL) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, - &state->smm_real_save_state_size); + &state->smm_real_save_state_size); state->smm_save_state_size = MAX(state->smm_real_save_state_size, smm_stub_size()); @@ -1090,11 +1078,25 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) * Default to smm_initiate_relocation() if trigger callback isn't * provided. */ - if (CONFIG(HAVE_SMI_HANDLER) && - ops->per_cpu_smm_trigger == NULL) + if (ops->per_cpu_smm_trigger == NULL) mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation; } +static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) +{ + /* + * Make copy of the ops so that defaults can be set in the non-const + * structure if needed. + */ + memcpy(&state->ops, ops, sizeof(*ops)); + + if (ops->get_cpu_count != NULL) + state->cpu_count = ops->get_cpu_count(); + + if (CONFIG(HAVE_SMI_HANDLER)) + fill_mp_state_smm(state, ops); +} + static enum cb_err do_mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) { enum cb_err ret; diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f1d36dac1d..185014e716 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -409,7 +409,7 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state, resource_t mask; if (var_state->mtrr_index >= total_mtrrs) { - printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n", + printk(BIOS_ERR, "Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n", var_state->mtrr_index, total_mtrrs); return; } diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smi_trigger.c similarity index 100% rename from src/cpu/x86/smm/smi_trigger.c rename to src/cpu/x86/smi_trigger.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 4d1cdf86ee..36aa113443 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += smm_module_loader.c -ramstage-y += smi_trigger.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) @@ -29,7 +28,6 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif smm-y += save_state.c -smm-y += smi_trigger.c ifeq ($(CONFIG_SMM_TSEG),y) diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index f9ebba4e32..cab691d974 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -193,8 +193,8 @@ RMODULE_ENTRY(smm_handler_start); * are linked at. */ int __weak mainboard_io_trap_handler(int smif) { return 0; } void __weak cpu_smi_handler(void) {} -void __weak northbridge_smi_handler() {} -void __weak southbridge_smi_handler() {} +void __weak northbridge_smi_handler(void) {} +void __weak southbridge_smi_handler(void) {} void __weak mainboard_smi_gpi(u32 gpi_sts) {} int __weak mainboard_smi_apmc(u8 data) { return 0; } void __weak mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 101b7c5bff..beddb3cd81 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -239,32 +240,26 @@ static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, return 1; } -/* - * Place stacks in base -> base + size region, but ensure the stacks don't - * overlap the staggered entry points. - */ -static void *smm_stub_place_stacks(char *base, struct smm_loader_params *params) +static uintptr_t stack_top; +static size_t g_stack_size; + +int smm_setup_stack(const uintptr_t perm_smbase, const size_t perm_smram_size, + const unsigned int total_cpus, const size_t stack_size) { - size_t total_stack_size; - char *stacks_top; + /* Need a minimum stack size and alignment. */ + if (stack_size <= SMM_MINIMUM_STACK_SIZE || (stack_size & 3) != 0) { + printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); + return -1; + } - /* If stack space is requested assume the space lives in the lower - * half of SMRAM. */ - total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; - printk(BIOS_DEBUG, "%s: cpus: %zx : stack space: needed -> %zx\n", - __func__, params->num_concurrent_stacks, - total_stack_size); - - /* There has to be at least one stack user. */ - if (params->num_concurrent_stacks < 1) - return NULL; - - /* Stacks extend down to SMBASE */ - stacks_top = &base[total_stack_size]; - printk(BIOS_DEBUG, "%s: exit, stack_top %p\n", __func__, stacks_top); - - return stacks_top; + const size_t total_stack_size = total_cpus * stack_size; + if (total_stack_size >= perm_smram_size) { + printk(BIOS_ERR, "%s: Stack won't fit smram\n", __func__); + return -1; + } + stack_top = perm_smbase + total_stack_size; + g_stack_size = stack_size; + return 0; } /* @@ -284,7 +279,7 @@ static int smm_stub_place_staggered_entry_points(char *base, if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { rc = smm_place_entry_code((uintptr_t)base, params->num_concurrent_save_states, - (uintptr_t)params->stack_top, params); + stack_top, params); } return rc; } @@ -309,20 +304,17 @@ static int smm_stub_place_staggered_entry_points(char *base, * permanent SMM handler. * The CPU stack is decided at runtime in the stub and is treaded as a continuous * region. As this might not fit the default SMRAM region, the same region used - * by the permanent handler can be used during relocation. This is done via the - * smram_start argument. + * by the permanent handler can be used during relocation. */ -static int smm_module_setup_stub(void *const smbase, const size_t smm_size, +static int smm_module_setup_stub(const uintptr_t smbase, const size_t smm_size, struct smm_loader_params *params, - void *const fxsave_area, - void *const smram_start) + void *const fxsave_area) { size_t total_save_state_size; size_t smm_stub_size; - char *smm_stub_loc; - void *stacks_top; + uintptr_t smm_stub_loc; size_t size; - char *base; + uintptr_t base; size_t i; struct smm_stub_params *stub_params; struct rmodule smm_stub; @@ -330,7 +322,7 @@ static int smm_module_setup_stub(void *const smbase, const size_t smm_size, size = smm_size; /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ - if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { + if (params->num_cpus > CONFIG_MAX_CPUS) { printk(BIOS_ERR, "%s: not enough stacks\n", __func__); return -1; } @@ -361,18 +353,10 @@ static int smm_module_setup_stub(void *const smbase, const size_t smm_size, return -1; } - /* Need a minimum stack size and alignment. */ - if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || - (params->per_cpu_stack_size & 3) != 0) { - printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); - return -1; - } - - smm_stub_loc = NULL; smm_stub_size = rmodule_memory_size(&smm_stub); /* Put the stub at the main entry point */ - smm_stub_loc = &base[SMM_ENTRY_OFFSET]; + smm_stub_loc = base + SMM_ENTRY_OFFSET; /* Stub is too big to fit. */ if (smm_stub_size > (size - SMM_ENTRY_OFFSET)) { @@ -380,42 +364,32 @@ static int smm_module_setup_stub(void *const smbase, const size_t smm_size, return -1; } - /* The stacks, if requested, live in the lower half of SMRAM space - * for default handler, but for relocated handler it lives at the beginning - * of SMRAM which is TSEG base - */ - stacks_top = smm_stub_place_stacks(smram_start, params); - if (stacks_top == NULL) { + if (stack_top == 0) { printk(BIOS_ERR, "%s: error assigning stacks\n", __func__); return -1; } - params->stack_top = stacks_top; /* Load the stub. */ - if (rmodule_load(smm_stub_loc, &smm_stub)) { + if (rmodule_load((void *)smm_stub_loc, &smm_stub)) { printk(BIOS_ERR, "%s: load module failed\n", __func__); return -1; } - if (!smm_stub_place_staggered_entry_points(base, params, &smm_stub)) { + if (!smm_stub_place_staggered_entry_points((void *)base, params, &smm_stub)) { printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); return -1; } /* Setup the parameters for the stub code. */ stub_params = rmodule_parameters(&smm_stub); - stub_params->stack_top = (uintptr_t)stacks_top; - stub_params->stack_size = params->per_cpu_stack_size; + stub_params->stack_top = stack_top; + stub_params->stack_size = g_stack_size; stub_params->c_handler = (uintptr_t)params->handler; stub_params->fxsave_area = (uintptr_t)fxsave_area; stub_params->fxsave_area_size = FXSAVE_SIZE; - const size_t total_stack_size = - params->num_concurrent_stacks * params->per_cpu_stack_size; - printk(BIOS_DEBUG, "%s: stack_end = 0x%zx\n", - __func__, stub_params->stack_top - total_stack_size); printk(BIOS_DEBUG, "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); - printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n", + printk(BIOS_DEBUG, "%s: per cpu stack_size = 0x%x\n", __func__, stub_params->stack_size); printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, stub_params->start32_offset); @@ -423,13 +397,13 @@ static int smm_module_setup_stub(void *const smbase, const size_t smm_size, __func__, smm_size); /* Initialize the APIC id to CPU number table to be 1:1 */ - for (i = 0; i < params->num_concurrent_stacks; i++) + for (i = 0; i < params->num_cpus; i++) stub_params->apic_id_to_cpu[i] = i; /* Allow the initiator to manipulate SMM stub parameters. */ params->stub_params = stub_params; - printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p\n", + printk(BIOS_DEBUG, "SMM Module: stub loaded at %lx. Will call %p\n", smm_stub_loc, params->handler); return 0; } @@ -440,9 +414,9 @@ static int smm_module_setup_stub(void *const smbase, const size_t smm_size, * assumption is that the stub will be entered from the default SMRAM * location: 0x30000 -> 0x40000. */ -int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_params *params) +int smm_setup_relocation_handler(struct smm_loader_params *params) { - void *smram = (void *)(SMM_DEFAULT_BASE); + uintptr_t smram = SMM_DEFAULT_BASE; printk(BIOS_SPEW, "%s: enter\n", __func__); /* There can't be more than 1 concurrent save state for the relocation * handler because all CPUs default to 0x30000 as SMBASE. */ @@ -455,12 +429,12 @@ int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_par /* Since the relocation handler always uses stack, adjust the number * of concurrent stack users to be CONFIG_MAX_CPUS. */ - if (params->num_concurrent_stacks == 0) - params->num_concurrent_stacks = CONFIG_MAX_CPUS; + if (params->num_cpus == 0) + params->num_cpus = CONFIG_MAX_CPUS; printk(BIOS_SPEW, "%s: exit\n", __func__); return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, - params, fxsave_area_relocation, perm_smram); + params, fxsave_area_relocation); } /* @@ -489,7 +463,8 @@ int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_par * expects a region large enough to encompass the handler and stacks * as well as the SMM_DEFAULT_SIZE. */ -int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) +int smm_load_module(const uintptr_t smram_base, const size_t smram_size, + struct smm_loader_params *params) { struct rmodule smm_mod; struct smm_runtime *handler_mod_params; @@ -500,16 +475,16 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) size_t fxsave_size; void *fxsave_area; size_t total_size = 0; - char *base; - void *smram_start = smram; - if (size <= SMM_DEFAULT_SIZE) + uintptr_t base; /* The base for the permanent handler */ + + if (smram_size <= SMM_DEFAULT_SIZE) return -1; /* Load main SMI handler at the top of SMRAM * everything else will go below */ - base = smram; - base += size; + base = smram_base; + base += smram_size; /* Fail if can't parse the smm rmodule. */ if (rmodule_parse(&_binary_smm_start, &smm_mod)) @@ -517,13 +492,11 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Clear SMM region */ if (CONFIG(DEBUG_SMI)) - memset(smram, 0xcd, size); + memset((void *)smram_base, 0xcd, smram_size); - total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; + total_stack_size = stack_top - smram_base; total_size += total_stack_size; /* Stacks are the base of SMRAM */ - params->stack_top = smram + total_stack_size; /* MSEG starts at the top of SMRAM and works down */ if (CONFIG(STM)) { @@ -533,8 +506,8 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* FXSAVE goes below MSEG */ if (CONFIG(SSE)) { - fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; - fxsave_area = base - fxsave_size; + fxsave_size = FXSAVE_SIZE * params->num_cpus; + fxsave_area = (char *)base - fxsave_size; base -= fxsave_size; total_size += fxsave_size; } else { @@ -546,8 +519,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) base -= handler_size; total_size += handler_size; module_alignment = rmodule_load_alignment(&smm_mod); - alignment_size = module_alignment - - ((uintptr_t)base % module_alignment); + alignment_size = module_alignment - (base % module_alignment); if (alignment_size != module_alignment) { handler_size += alignment_size; base += alignment_size; @@ -555,10 +527,10 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) printk(BIOS_DEBUG, "%s: total_smm_space_needed %zx, available -> %zx\n", - __func__, total_size, size); + __func__, total_size, smram_size); /* Does the required amount of memory exceed the SMRAM region size? */ - if (total_size > size) { + if (total_size > smram_size) { printk(BIOS_ERR, "%s: need more SMRAM\n", __func__); return -1; } @@ -568,23 +540,19 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) return -1; } - if (rmodule_load(base, &smm_mod)) + if (rmodule_load((void *)base, &smm_mod)) return -1; params->handler = rmodule_entry(&smm_mod); handler_mod_params = rmodule_parameters(&smm_mod); - handler_mod_params->smbase = (uintptr_t)smram; - handler_mod_params->smm_size = size; + handler_mod_params->smbase = smram_base; + handler_mod_params->smm_size = smram_size; handler_mod_params->save_state_size = params->real_cpu_save_state_size; - handler_mod_params->num_cpus = params->num_concurrent_stacks; + handler_mod_params->num_cpus = params->num_cpus; handler_mod_params->gnvs_ptr = (uintptr_t)acpi_get_gnvs(); - printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", - __func__, smram); - printk(BIOS_DEBUG, "%s: smram_end: %p\n", - __func__, smram + size); - printk(BIOS_DEBUG, "%s: stack_top: %p\n", - __func__, params->stack_top); + printk(BIOS_DEBUG, "%s: smram_start: 0x%lx\n", __func__, smram_base); + printk(BIOS_DEBUG, "%s: smram_end: %lx\n", __func__, smram_base + smram_size); printk(BIOS_DEBUG, "%s: handler start %p\n", __func__, params->handler); printk(BIOS_DEBUG, "%s: handler_size %zx\n", @@ -610,18 +578,17 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) * will be staggered below */ base -= SMM_CODE_SEGMENT_SIZE; - printk(BIOS_DEBUG, "%s: cpu0 entry: %p\n", - __func__, base); + printk(BIOS_DEBUG, "%s: cpu0 entry: %lx\n", __func__, base); - if (!smm_create_map((uintptr_t)base, params->num_concurrent_save_states, params)) { + if (!smm_create_map(base, params->num_concurrent_save_states, params)) { printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); return -1; } - for (int i = 0; i < params->num_concurrent_stacks; i++) { + for (int i = 0; i < params->num_cpus; i++) { handler_mod_params->save_state_top[i] = cpus[i].ss_start + params->per_cpu_save_state_size; } - return smm_module_setup_stub(base, size, params, fxsave_area, smram_start); + return smm_module_setup_stub(base, smram_size, params, fxsave_area); } diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index 1302bb0f14..f6aecd0557 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -61,7 +61,7 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size) void stage_cache_external_region(void **base, size_t *size) { if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + printk(BIOS_ERR, "No cache SMM subregion.\n"); *base = NULL; *size = 0; } diff --git a/src/device/Kconfig b/src/device/Kconfig index ea3e241c82..7f20d709ad 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -499,13 +499,21 @@ config PCI if PCI -config NO_MMCONF_SUPPORT +config NO_ECAM_MMCONF_SUPPORT bool default n + help + Disable the use of the Enhanced Configuration + Access mechanism (ECAM) method for accessing PCI config + address space. -config MMCONF_SUPPORT +config ECAM_MMCONF_SUPPORT bool - default !NO_MMCONF_SUPPORT + default !NO_ECAM_MMCONF_SUPPORT + help + Enable the use of the Enhanced Configuration + Access mechanism (ECAM) method for accessing PCI config + address space. config PCIX_PLUGIN_SUPPORT bool @@ -519,14 +527,6 @@ config AZALIA_PLUGIN_SUPPORT bool default n -config AZALIA_MAX_CODECS - int - depends on AZALIA_PLUGIN_SUPPORT - default 3 - range 1 15 - help - The maximum number of codecs supported on a single HD Audio controller. - config AZALIA_LOCK_DOWN_R_WO_GCAP def_bool n depends on AZALIA_PLUGIN_SUPPORT @@ -540,20 +540,20 @@ config PCIEXP_PLUGIN_SUPPORT bool default y -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS hex - depends on MMCONF_SUPPORT + depends on ECAM_MMCONF_SUPPORT -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int - depends on MMCONF_SUPPORT + depends on ECAM_MMCONF_SUPPORT -config MMCONF_LENGTH +config ECAM_MMCONF_LENGTH hex - depends on MMCONF_SUPPORT - default 0x04000000 if MMCONF_BUS_NUMBER = 64 - default 0x08000000 if MMCONF_BUS_NUMBER = 128 - default 0x10000000 if MMCONF_BUS_NUMBER = 256 + depends on ECAM_MMCONF_SUPPORT + default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 + default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 + default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 default 0x0 config PCI_ALLOW_BUS_MASTER @@ -619,11 +619,40 @@ config PCIEXP_CLK_PM config PCIEXP_L1_SUB_STATE prompt "Enable PCIe ASPM L1 SubState" bool - depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT) + depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) default n help Detect and enable ASPM on PCIe links. +config PCIEXP_SUPPORT_RESIZABLE_BARS + prompt "Support PCIe Resizable BARs" + bool + depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT) + default n + help + When enabled, this will check PCIe devices for Resizable BAR support, + and if found, will use this to discover the preferred BAR sizes of + the device in preference over the traditional moving bits method. The + amount of address space given out to devices in this manner (since + it can range up to 8 EB) can be limited with the + PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below. + +if PCIEXP_SUPPORT_RESIZABLE_BARS + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + int "Bits of address space to give to Resizable BARs" + range 20 63 # 1 MiB - 8 EiB + default 29 # 512 MiB + help + This is the maximum number of bits of address space to allocate for + PCIe devices with resizable BARs. For instance, if a device requests + 30 bits of address space (1 GiB), but this field is set to 29, then + the device will only be allocated 29 bits worth of address space (512 + MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come + from the Resizable BAR portion of the PCIe spec (7.8.6). + +endif # PCIEXP_SUPPORT_RESIZABLE_BARS + config PCIEXP_HOTPLUG prompt "Enable PCIe Hotplug Support" bool @@ -635,8 +664,8 @@ if PCIEXP_HOTPLUG config PCIEXP_HOTPLUG_BUSES int "PCI Express Hotplug Buses" - default 8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 64 - default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128 + default 8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 64 + default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128 default 32 help This is the number of buses allocated for hotplug PCI express diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 70f8348a7c..4ac585dac1 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -50,7 +50,6 @@ int azalia_exit_reset(u8 *base) static u16 codec_detect(u8 *base) { struct stopwatch sw; - const u16 codec_mask = (1 << CONFIG_AZALIA_MAX_CODECS) - 1; u16 reg16; if (azalia_exit_reset(base) < 0) @@ -61,9 +60,9 @@ static u16 codec_detect(u8 *base) write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); } - /* clear STATESTS bits (BAR + 0xe)[2:0] */ + /* clear STATESTS bits (BAR + 0x0e)[14:0] */ reg16 = read16(base + HDA_STATESTS_REG); - reg16 |= codec_mask; + reg16 |= 0x7fff; write16(base + HDA_STATESTS_REG, reg16); /* Wait for readback of register to @@ -86,9 +85,9 @@ static u16 codec_detect(u8 *base) if (azalia_exit_reset(base) < 0) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0] */ + /* Read in Codec location (BAR + 0x0e)[14:0] */ reg16 = read16(base + HDA_STATESTS_REG); - reg16 &= codec_mask; + reg16 &= 0x7fff; if (!reg16) goto no_codec; @@ -227,7 +226,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) { } -static void codec_init(struct device *dev, u8 *base, int addr) +void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes) { u32 reg32; const u32 *verb; @@ -252,7 +251,7 @@ static void codec_init(struct device *dev, u8 *base, int addr) /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); + verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); @@ -261,19 +260,22 @@ static void codec_init(struct device *dev, u8 *base, int addr) printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size); /* 3 */ - azalia_program_verb_table(base, verb, verb_size); - printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); + const int rc = azalia_program_verb_table(base, verb, verb_size); + if (rc < 0) + printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n"); + else + printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); mainboard_azalia_program_runtime_verbs(base, reg32); } -static void codecs_init(struct device *dev, u8 *base, u16 codec_mask) +void azalia_codecs_init(u8 *base, u16 codec_mask) { int i; - for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) { + for (i = 14; i >= 0; i--) { if (codec_mask & (1 << i)) - codec_init(dev, base, i); + azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size); } azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size); @@ -285,7 +287,7 @@ void azalia_audio_init(struct device *dev) struct resource *res; u16 codec_mask; - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -297,7 +299,7 @@ void azalia_audio_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/device/device_util.c b/src/device/device_util.c index 7b72a94811..039e562b43 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index, void mmconf_resource(struct device *dev, unsigned long index) { struct resource *resource = new_resource(dev, index); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_LENGTH; + resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_ECAM_MMCONF_LENGTH; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 0eba0e384c..2ade8ef098 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -322,13 +322,13 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) printram("SPD contains 0x%02x bytes\n", spd_size); if (spd_size < 64 || eeprom_size < 64) { - printk(BIOS_WARNING, "ERROR: SPD to small\n"); + printk(BIOS_ERR, "SPD too small\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { - printk(BIOS_WARNING, "ERROR: SPD checksum error\n"); + printk(BIOS_ERR, "SPD checksum error\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_CRC_ERROR; } @@ -336,8 +336,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { - printk(BIOS_WARNING, - "ERROR: Unsupported SPD revision %01x.%01x\n", + printk(BIOS_ERR, "Unsupported SPD revision %01x.%01x\n", reg8 >> 4, reg8 & 0xf); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; @@ -348,7 +347,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) reg8 = spd[2]; printram(" Type : 0x%02x\n", reg8); if (reg8 != 0x08) { - printk(BIOS_WARNING, "ERROR: Unsupported SPD type %x\n", reg8); + printk(BIOS_ERR, "Unsupported SPD type %x\n", reg8); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 0a32d02de9..b99730d45b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, switch (info->dimm_type) { case SPD_DDR3_DIMM_TYPE_SO_DIMM: - dimm->mod_type = SPD_SODIMM; + dimm->mod_type = DDR3_SPD_SODIMM; break; case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: - dimm->mod_type = SPD_72B_SO_CDIMM; + dimm->mod_type = DDR3_SPD_72B_SO_CDIMM; break; case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = SPD_72B_SO_RDIMM; + dimm->mod_type = DDR3_SPD_72B_SO_RDIMM; break; case SPD_DDR3_DIMM_TYPE_UDIMM: - dimm->mod_type = SPD_UDIMM; + dimm->mod_type = DDR3_SPD_UDIMM; break; case SPD_DDR3_DIMM_TYPE_RDIMM: - dimm->mod_type = SPD_RDIMM; + dimm->mod_type = DDR3_SPD_RDIMM; break; case SPD_DDR3_DIMM_TYPE_UNDEFINED: default: diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index c5a8d13f53..a66ee86fd1 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -143,7 +143,7 @@ uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) return speed_attr->reported_mts; } } - printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range\n", speed_mhz); + printk(BIOS_ERR, "DDR4 speed of %d MHz is out of range\n", speed_mhz); return 0; } @@ -299,16 +299,16 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel switch (info->dimm_type) { case SPD_DDR4_DIMM_TYPE_SO_DIMM: - dimm->mod_type = SPD_SODIMM; + dimm->mod_type = DDR4_SPD_SODIMM; break; case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = SPD_72B_SO_RDIMM; + dimm->mod_type = DDR4_SPD_72B_SO_RDIMM; break; case SPD_DDR4_DIMM_TYPE_UDIMM: - dimm->mod_type = SPD_UDIMM; + dimm->mod_type = DDR4_SPD_UDIMM; break; case SPD_DDR4_DIMM_TYPE_RDIMM: - dimm->mod_type = SPD_RDIMM; + dimm->mod_type = DDR4_SPD_RDIMM; break; default: dimm->mod_type = SPD_UNDEFINED; diff --git a/src/device/dram/lpddr4.c b/src/device/dram/lpddr4.c index 3c686d0107..625aff295e 100644 --- a/src/device/dram/lpddr4.c +++ b/src/device/dram/lpddr4.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -95,6 +94,6 @@ uint16_t lpddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) return speed_attr->reported_mts; } } - printk(BIOS_ERR, "ERROR: LPDDR4 speed of %d MHz is out of range\n", speed_mhz); + printk(BIOS_ERR, "LPDDR4 speed of %d MHz is out of range\n", speed_mhz); return 0; } diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index 0b2dd49eee..11808e2cf3 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include const char *spd_manufacturer_name(const uint16_t mod_id) { @@ -38,3 +39,219 @@ const char *spd_manufacturer_name(const uint16_t mod_id) return NULL; } } + +static void convert_default_module_type_to_spd_info(struct spd_info *info) +{ + info->form_factor = MEMORY_FORMFACTOR_UNKNOWN; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; +} + +static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type, + struct spd_info *info) +{ + switch (module_type) { + case DDR2_SPD_RDIMM: + case DDR2_SPD_MINI_RDIMM: + info->form_factor = MEMORY_FORMFACTOR_RIMM; + info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; + break; + case DDR2_SPD_UDIMM: + case DDR2_SPD_MINI_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; + break; + case DDR2_SPD_MICRO_DIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + case DDR2_SPD_SODIMM: + info->form_factor = MEMORY_FORMFACTOR_SODIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type, + struct spd_info *info) +{ + switch (module_type) { + case DDR3_SPD_RDIMM: + case DDR3_SPD_MINI_RDIMM: + info->form_factor = MEMORY_FORMFACTOR_RIMM; + info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; + break; + case DDR3_SPD_UDIMM: + case DDR3_SPD_MINI_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; + break; + case DDR3_SPD_MICRO_DIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + case DDR3_SPD_SODIMM: + case DDR3_SPD_72B_SO_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_SODIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type, + struct spd_info *info) +{ + switch (module_type) { + case DDR4_SPD_RDIMM: + case DDR4_SPD_MINI_RDIMM: + info->form_factor = MEMORY_FORMFACTOR_RIMM; + info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; + break; + case DDR4_SPD_UDIMM: + case DDR4_SPD_MINI_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; + break; + case DDR4_SPD_SODIMM: + case DDR4_SPD_72B_SO_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_SODIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type, + struct spd_info *info) +{ + switch (module_type) { + case DDR5_SPD_RDIMM: + case DDR5_SPD_MINI_RDIMM: + info->form_factor = MEMORY_FORMFACTOR_RIMM; + info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; + break; + case DDR5_SPD_UDIMM: + case DDR5_SPD_MINI_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_DIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; + break; + case DDR5_SPD_SODIMM: + case DDR5_SPD_72B_SO_UDIMM: + info->form_factor = MEMORY_FORMFACTOR_SODIMM; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + case DDR5_SPD_2DPC: + info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type, + struct spd_info *info) +{ + switch (module_type) { + case LPX_SPD_NONDIMM: + info->form_factor = MEMORY_FORMFACTOR_ROC; + info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info) +{ + switch (memory_type) { + case MEMORY_TYPE_DDR2: + convert_ddr2_module_type_to_spd_info(module_type, info); + break; + case MEMORY_TYPE_DDR3: + convert_ddr3_module_type_to_spd_info(module_type, info); + break; + case MEMORY_TYPE_DDR4: + convert_ddr4_module_type_to_spd_info(module_type, info); + break; + case MEMORY_TYPE_DDR5: + convert_ddr5_module_type_to_spd_info(module_type, info); + break; + case MEMORY_TYPE_LPDDR3: + case MEMORY_TYPE_LPDDR4: + case MEMORY_TYPE_LPDDR5: + convert_lpx_module_type_to_spd_info(module_type, info); + break; + default: + convert_default_module_type_to_spd_info(info); + break; + } +} + +static uint8_t convert_default_form_factor_to_module_type(void) +{ + return SPD_UNDEFINED; +} + +static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type, + smbios_memory_form_factor form_factor) +{ + uint8_t module_type; + + switch (form_factor) { + case MEMORY_FORMFACTOR_DIMM: + return DDR2_SPD_UDIMM; + case MEMORY_FORMFACTOR_RIMM: + return DDR2_SPD_RDIMM; + case MEMORY_FORMFACTOR_SODIMM: + module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM + : DDR3_SPD_SODIMM; + return module_type; + default: + return convert_default_form_factor_to_module_type(); + } +} + +static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor form_factor) +{ + switch (form_factor) { + case MEMORY_FORMFACTOR_ROC: + return LPX_SPD_NONDIMM; + default: + return convert_default_form_factor_to_module_type(); + } +} + +uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type, + smbios_memory_form_factor form_factor) +{ + uint8_t module_type; + + switch (memory_type) { + case MEMORY_TYPE_DDR2: + case MEMORY_TYPE_DDR3: + case MEMORY_TYPE_DDR4: + case MEMORY_TYPE_DDR5: + module_type = convert_ddrx_form_factor_to_module_type(memory_type, form_factor); + break; + case MEMORY_TYPE_LPDDR3: + case MEMORY_TYPE_LPDDR4: + case MEMORY_TYPE_LPDDR5: + module_type = convert_lpx_form_factor_to_module_type(form_factor); + break; + default: + module_type = convert_default_form_factor_to_module_type(); + break; + } + + return module_type; +} diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 224e49b97d..7972011a3f 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -89,14 +90,19 @@ static int intXX_exception_handler(void) .edi=X86_EDI, .vector=M.x86.intno, .error_code=0, // FIXME: fill in - .eip=X86_EIP, .cs=X86_CS, +#if ENV_X86_64 + .rip=X86_EIP, + .rflags=X86_EFLAGS +#else + .eip=X86_EIP, .eflags=X86_EFLAGS +#endif }; struct eregs *regs = ®_info; printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", - regs->vector); + (uint32_t)regs->vector); x86_exception(regs); // Call coreboot exception handler return 0; // Never really returns @@ -227,7 +233,7 @@ static u8 vbe_get_ctrl_info(vbe_info_block *info) 0x0000, buffer_seg, buffer_adr); /* If the VBE function completed successfully, 0x0 is returned in AH */ if (X86_AH) { - printk(BIOS_WARNING, "Warning: Error from VGA BIOS in %s\n", __func__); + printk(BIOS_WARNING, "Error from VGA BIOS in %s\n", __func__); return 1; } memcpy(info, buffer, sizeof(vbe_info_block)); diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 051a601569..2a4e6f86fd 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -103,7 +103,7 @@ read_io(void *addr, size_t sz) { unsigned int ret; /* since we are using inb instructions, we need the port number as 16bit value */ - u16 port = (u16)(u32) addr; + u16 port = (u16)(uintptr_t) addr; switch (sz) { case 1: @@ -125,7 +125,7 @@ read_io(void *addr, size_t sz) static int write_io(void *addr, unsigned int value, size_t sz) { - u16 port = (u16)(u32) addr; + u16 port = (u16)(uintptr_t) addr; switch (sz) { /* since we are using inb instructions, we need the port number as 16bit value */ case 1: diff --git a/src/device/oprom/yabel/pmm.c b/src/device/oprom/yabel/pmm.c index d7e1f7beba..e30a86b52e 100644 --- a/src/device/oprom/yabel/pmm.c +++ b/src/device/oprom/yabel/pmm.c @@ -104,7 +104,7 @@ u8 pmm_setup(u16 segment, u16 offset) /* handle the selfdefined interrupt, this is executed, when the PMM Entry Point * is executed, it must handle all PMM requests */ -void pmm_handleInt() +void pmm_handleInt(void) { u32 rval = 0; u16 function, flags; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4b5e73b806..2acc517804 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -309,6 +310,127 @@ struct msix_entry *pci_msix_get_table(struct device *dev) return (struct msix_entry *)((uintptr_t)res->base + offset); } +static unsigned int get_rebar_offset(const struct device *dev, unsigned long index) +{ + uint32_t offset = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_RESIZABLE_BAR); + if (!offset) + return 0; + + /* Convert PCI_BASE_ADDRESS_0, ..._1, ..._2 into 0, 1, 2... */ + const unsigned int find_bar_idx = (index - PCI_BASE_ADDRESS_0) / + sizeof(uint32_t); + + /* Although all of the Resizable BAR Control Registers contain an + "NBARs" field, it is only valid in the Control Register for BAR 0 */ + const uint32_t rebar_ctrl0 = pci_read_config32(dev, offset + PCI_REBAR_CTRL_OFFSET); + const unsigned int nbars = (rebar_ctrl0 & PCI_REBAR_CTRL_NBARS_MASK) >> + PCI_REBAR_CTRL_NBARS_SHIFT; + + for (unsigned int i = 0; i < nbars; i++, offset += sizeof(uint64_t)) { + const uint32_t rebar_ctrl = pci_read_config32( + dev, offset + PCI_REBAR_CTRL_OFFSET); + const uint32_t bar_idx = rebar_ctrl & PCI_REBAR_CTRL_IDX_MASK; + if (bar_idx == find_bar_idx) + return offset; + } + + return 0; +} + +/* Bit 20 = 1 MiB, bit 21 = 2 MiB, bit 22 = 4 MiB, ... bit 63 = 8 EiB */ +static uint64_t get_rebar_sizes_mask(const struct device *dev, + unsigned long index) +{ + uint64_t size_mask = 0ULL; + const uint32_t offset = get_rebar_offset(dev, index); + if (!offset) + return 0; + + /* Get 1 MB - 128 TB support from CAP register */ + const uint32_t cap = pci_read_config32(dev, offset + PCI_REBAR_CAP_OFFSET); + /* Shift the bits from 4-31 to 0-27 (i.e., down by 4 bits) */ + size_mask |= ((cap & PCI_REBAR_CAP_SIZE_MASK) >> 4); + + /* Get 256 TB - 8 EB support from CTRL register and store it in bits 28-43 */ + const uint64_t ctrl = pci_read_config32(dev, offset + PCI_REBAR_CTRL_OFFSET); + /* Shift ctrl mask from bit 16 to bit 28, so that the two + masks (fom cap and ctrl) form a contiguous bitmask when + concatenated (i.e., up by 12 bits). */ + size_mask |= ((ctrl & PCI_REBAR_CTRL_SIZE_MASK) << 12); + + /* Now that the mask occupies bits 0-43, shift it up to 20-63, so they + represent the actual powers of 2. */ + return size_mask << 20; +} + +static void pci_store_rebar_size(const struct device *dev, + const struct resource *resource) +{ + const unsigned int num_bits = __fls64(resource->size); + const uint32_t offset = get_rebar_offset(dev, resource->index); + if (!offset) + return; + + pci_update_config32(dev, offset + PCI_REBAR_CTRL_OFFSET, + ~PCI_REBAR_CTRL_SIZE_MASK, + num_bits << PCI_REBAR_CTRL_SIZE_SHIFT); +} + +static void configure_adjustable_base(const struct device *dev, + unsigned long index, + struct resource *res) +{ + /* + * Excerpt from an implementation note from the PCIe spec: + * + * System software uses this capability in place of the above mentioned + * method of determining the resource size[0], and prior to assigning + * the base address to the BAR. Potential usable resource sizes are + * reported by the Function via its Resizable BAR Capability and Control + * registers. It is intended that the software allocate the largest of + * the reported sizes that it can, since allocating less address space + * than the largest reported size can result in lower + * performance. Software then writes the size to the Resizable BAR + * Control register for the appropriate BAR for the Function. Following + * this, the base address is written to the BAR. + * + * [0] Referring to using the moving bits in the BAR to determine the + * requested size of the MMIO region + */ + const uint64_t size_mask = get_rebar_sizes_mask(dev, index); + if (!size_mask) + return; + + int max_requested_bits = __fls64(size_mask); + if (max_requested_bits > CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS) { + printk(BIOS_WARNING, "WARNING: Device %s requests a BAR with" + "%u bits of address space, which coreboot is not" + "configured to hand out, truncating to %u bits\n", + dev_path(dev), max_requested_bits, + CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS); + max_requested_bits = CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS; + } + + if (!(res->flags & IORESOURCE_PCI64) && max_requested_bits > 32) { + printk(BIOS_ERR, "ERROR: Resizable BAR requested" + "above 32 bits, but PCI function reported a" + "32-bit BAR."); + return; + } + + /* Configure the resource parameters for the adjustable BAR */ + res->size = 1ULL << max_requested_bits; + res->align = max_requested_bits; + res->gran = max_requested_bits; + res->limit = (res->flags & IORESOURCE_PCI64) ? UINT64_MAX : UINT32_MAX; + res->flags |= IORESOURCE_PCIE_RESIZABLE_BAR; + + printk(BIOS_INFO, "%s: Adjusting resource index %lu: base: %llx size: %llx " + "align: %d gran: %d limit: %llx\n", + dev_path(dev), res->index, res->base, res->size, + res->align, res->gran, res->limit); +} + /** * Read the base address registers for a given device. * @@ -323,6 +445,11 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + + const bool is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE) != 0; + if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && is_pcie) + configure_adjustable_base(dev, index, resource); + index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } @@ -497,7 +624,7 @@ static void pci_store_bridge_resource(const struct device *const dev, } else { /* Don't let me think I stored the resource. */ resource->flags &= ~IORESOURCE_STORED; - printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n", resource->index); + printk(BIOS_ERR, "invalid resource->index %lx\n", resource->index); } } @@ -510,7 +637,7 @@ static void pci_set_resource(struct device *dev, struct resource *resource) we can treat it like an empty resource. */ resource->size = 0; } else { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", + printk(BIOS_ERR, "%s %02lx %s size: 0x%010llx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; @@ -547,11 +674,17 @@ static void pci_set_resource(struct device *dev, struct resource *resource) /* Now store the resource. */ resource->flags |= IORESOURCE_STORED; - if (resource->flags & IORESOURCE_PCI_BRIDGE) - pci_store_bridge_resource(dev, resource); - else + if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { + if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && + (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR)) + pci_store_rebar_size(dev, resource); + pci_store_resource(dev, resource); + } else { + pci_store_bridge_resource(dev, resource); + } + report_resource_stored(dev, resource, ""); } @@ -1203,6 +1336,33 @@ static void pci_scan_hidden_device(struct device *dev) dev->device, dev->ops ? "" : " No operations"); } +/** + * A PCIe Downstream Port normally leads to a Link with only Device 0 on it + * (PCIe spec r5.0, sec 7.3.1). As an optimization, scan only for Device 0 in + * that situation. + * + * @param bus Pointer to the bus structure. + */ +static bool pci_bus_only_one_child(struct bus *bus) +{ + struct device *bridge = bus->dev; + u16 pcie_pos, pcie_flags_reg; + int pcie_type; + + if (!bridge) + return false; + + pcie_pos = pci_find_capability(bridge, PCI_CAP_ID_PCIE); + if (!pcie_pos) + return false; + + pcie_flags_reg = pci_read_config16(bridge, pcie_pos + PCI_EXP_FLAGS); + + pcie_type = (pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; + + return pciexp_is_downstream_port(pcie_type); +} + /** * Scan a PCI bus. * @@ -1232,6 +1392,9 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, post_code(0x24); + if (pci_bus_only_one_child(bus)) + max_devfn = MIN(max_devfn, 0x07); + /* * Probe all devices/functions on this bus with some optimization for * non-existence and single function devices. @@ -1445,6 +1608,11 @@ void pci_domain_scan_bus(struct device *dev) pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); } +void pci_dev_disable_bus_master(const struct device *dev) +{ + pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0); +} + /** * Take an INT_PIN number (0, 1 - 4) and convert * it to a string ("NO PIN", "PIN A" - "PIN D") @@ -1582,8 +1750,7 @@ int get_pci_irq_pins(struct device *dev, struct device **parent_bdg) /* Make sure the swizzle returned valid structures */ if (parent_bdg == NULL) { - printk(BIOS_WARNING, - "Warning: Could not find parent bridge for this device!\n"); + printk(BIOS_WARNING, "Could not find parent bridge for this device!\n"); return -2; } } else { /* Device is not behind a bridge */ @@ -1638,9 +1805,4 @@ void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4]) i8259_configure_irq_trigger(irq, IRQ_LEVEL_TRIGGERED); } } - -void pci_dev_disable_bus_master(const struct device *dev) -{ - pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0); -} #endif diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 76d5e96aec..a4ef4053a3 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -7,7 +7,7 @@ #include #include -u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; +u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS; /** * Given a device, a capability type, and a last position, return the next diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 895c5b7737..70ffe48b26 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -16,6 +16,21 @@ void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; } u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } +void vga_oprom_preload(void) +{ +/* The CONFIG_VGA_BIOS_ID symbol is only defined when VGA_BIOS is selected */ +#if CONFIG(VGA_BIOS) + const char name[] = "pci" CONFIG_VGA_BIOS_ID ".rom"; + + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading VGA ROM %s\n", name); + + cbfs_preload(name); +#endif +} + static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) { char name[17] = "pciXXXX,XXXX.rom"; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index d8ed5d9e3d..c52530196d 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -8,29 +8,39 @@ #include #include -unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap) +static unsigned int pciexp_get_ext_cap_offset(const struct device *dev, unsigned int cap, + unsigned int offset) { - unsigned int this_cap_offset, next_cap_offset; - unsigned int this_cap, cafe; - - this_cap_offset = PCIE_EXT_CAP_OFFSET; + unsigned int this_cap_offset = offset; + unsigned int next_cap_offset, this_cap, cafe; do { this_cap = pci_read_config32(dev, this_cap_offset); - next_cap_offset = this_cap >> 20; - this_cap &= 0xffff; cafe = pci_read_config32(dev, this_cap_offset + 4); - cafe &= 0xffff; - if (this_cap == cap) + if ((this_cap & 0xffff) == cap) { return this_cap_offset; - else if (cafe == cap) + } else if ((cafe & 0xffff) == cap) { return this_cap_offset + 4; - else + } else { + next_cap_offset = this_cap >> 20; this_cap_offset = next_cap_offset; + } } while (next_cap_offset != 0); return 0; } +unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap, + unsigned int pos) +{ + const unsigned int next_cap_offset = pci_read_config32(dev, pos) >> 20; + return pciexp_get_ext_cap_offset(dev, cap, next_cap_offset); +} + +unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap) +{ + return pciexp_get_ext_cap_offset(dev, cap, PCIE_EXT_CAP_OFFSET); +} + /* * Re-train a PCIe link */ @@ -181,7 +191,7 @@ static void pciexp_enable_ltr(struct device *dev) (void)_pciexp_enable_ltr(parent, parent_cap, dev, cap); } -static bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop) +bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop) { /* Walk the hierarchy up to find get_ltr_max_latencies(). */ do { diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 88072b9a77..85daec7fc5 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -126,12 +126,12 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) if (resource->flags & IORESOURCE_IRQ && (resource->index != PNP_IDX_IRQ0) && (resource->index != PNP_IDX_IRQ1)) - printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " + printk(BIOS_WARNING, "%s %02lx %s size: " "0x%010llx not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); else - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " + printk(BIOS_ERR, "%s %02lx %s size: 0x%010llx " "not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; @@ -145,7 +145,7 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) } else if (resource->flags & IORESOURCE_IRQ) { pnp_set_irq(dev, resource->index, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", + printk(BIOS_ERR, "%s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } @@ -213,7 +213,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask) /* If none of the mask bits is set, the resource would occupy the whole IO space leading to IO resource conflicts with the other devices */ if (!mask) { - printk(BIOS_ERR, "ERROR: device %s index %d has no mask.\n", + printk(BIOS_ERR, "device %s index %d has no mask.\n", dev_path(dev), index); return; } @@ -241,8 +241,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask) If there is any zero in between the block of ones, it is ignored in the calculation of the resource size and limit. */ if (mask != (resource->limit ^ (resource->size - 1))) - printk(BIOS_WARNING, - "WARNING: mask of device %s index %d is wrong.\n", + printk(BIOS_WARNING, "mask of device %s index %d is wrong.\n", dev_path(dev), index); } diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index a880ce7e01..c589553698 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -20,7 +20,7 @@ static void set_range_uc(u32 base, u32 size) for (i = 0; i < max_var_mtrrs; i++) { msr = rdmsr(MTRR_PHYS_MASK(i)); if (!(msr.lo & MTRR_PHYS_MASK_VALID)) - break; + break; } if (i == max_var_mtrrs) die("Run out of unused MTRRs\n"); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index b8f38ce4ee..871054b92c 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -36,22 +36,18 @@ static void romstage_main(void) struct postcar_frame pcf; struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - unsigned int initial_apic_id = initial_lapicid(); int cbmem_initted = 0; fill_sysinfo(cb); - if (initial_apic_id == 0) { + timestamp_add_now(TS_START_ROMSTAGE); - timestamp_add_now(TS_START_ROMSTAGE); + board_BeforeAgesa(cb); - board_BeforeAgesa(cb); - - console_init(); - } + console_init(); printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n", - initial_apic_id, cpuid_eax(1)); + initial_lapicid(), cpuid_eax(1)); set_ap_entry_ptr(ap_romstage_main); diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 11e9ed1796..e3a511131f 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -6,11 +6,12 @@ #include #include #include +#include #include "anx7625.h" #define ANXERROR(format, ...) \ - printk(BIOS_ERR, "ERROR: %s: " format, __func__, ##__VA_ARGS__) + printk(BIOS_ERR, "%s: " format, __func__, ##__VA_ARGS__) #define ANXINFO(format, ...) \ printk(BIOS_INFO, "%s: " format, __func__, ##__VA_ARGS__) #define ANXDEBUG(format, ...) \ @@ -54,9 +55,11 @@ static int i2c_access_workaround(uint8_t bus, uint8_t saddr) } ret = i2c_writeb(bus, saddr, offset, 0x00); - if (ret < 0) + if (ret < 0) { ANXERROR("Failed to access %#x:%#x\n", saddr, offset); - return ret; + return ret; + } + return 0; } static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset, @@ -70,7 +73,7 @@ static int anx7625_reg_read(uint8_t bus, uint8_t saddr, uint8_t offset, ANXERROR("Failed to read i2c reg=%#x:%#x\n", saddr, offset); return ret; } - return *val; + return 0; } static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr, @@ -80,10 +83,12 @@ static int anx7625_reg_block_read(uint8_t bus, uint8_t saddr, uint8_t reg_addr, i2c_access_workaround(bus, saddr); ret = i2c_read_bytes(bus, saddr, reg_addr, buf, len); - if (ret < 0) + if (ret < 0) { ANXERROR("Failed to read i2c block=%#x:%#x[len=%#x]\n", saddr, reg_addr, len); - return ret; + return ret; + } + return 0; } static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr, @@ -93,10 +98,11 @@ static int anx7625_reg_write(uint8_t bus, uint8_t saddr, uint8_t reg_addr, i2c_access_workaround(bus, saddr); ret = i2c_writeb(bus, saddr, reg_addr, reg_val); - if (ret < 0) + if (ret < 0) { ANXERROR("Failed to write i2c id=%#x:%#x\n", saddr, reg_addr); - - return ret; + return ret; + } + return 0; } static int anx7625_write_or(uint8_t bus, uint8_t saddr, uint8_t offset, @@ -128,30 +134,22 @@ static int anx7625_write_and(uint8_t bus, uint8_t saddr, uint8_t offset, static int wait_aux_op_finish(uint8_t bus) { uint8_t val; - int ret = -1; - int loop; + int ret; - for (loop = 0; loop < 150; loop++) { - mdelay(2); - anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); - if (!(val & AP_AUX_CTRL_OP_EN)) { - ret = 0; - break; - } - } - - if (ret != 0) { + if (!retry(150, + (anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val), + !(val & AP_AUX_CTRL_OP_EN)), mdelay(2))) { ANXERROR("Timed out waiting aux operation.\n"); - return ret; + return -1; } ret = anx7625_reg_read(bus, RX_P0_ADDR, AP_AUX_CTRL_STATUS, &val); if (ret < 0 || val & 0x0F) { ANXDEBUG("aux status %02x\n", val); - ret = -1; + return -1; } - return ret; + return 0; } static unsigned long gcd(unsigned long a, unsigned long b) @@ -210,7 +208,7 @@ static int anx7625_calculate_m_n(u32 pixelclock, ANXERROR("pixelclock %u higher than %lu, " "output may be unstable\n", pixelclock, PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); - return 1; + return -1; } if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { @@ -218,7 +216,7 @@ static int anx7625_calculate_m_n(u32 pixelclock, ANXERROR("pixelclock %u lower than %lu, " "output may be unstable\n", pixelclock, PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); - return 1; + return -1; } post_divider = 1; @@ -237,7 +235,7 @@ static int anx7625_calculate_m_n(u32 pixelclock, if (post_divider > POST_DIVIDER_MAX) { ANXERROR("cannot find property post_divider(%d)\n", post_divider); - return 1; + return -1; } } @@ -256,7 +254,7 @@ static int anx7625_calculate_m_n(u32 pixelclock, if (pixelclock * post_divider > PLL_OUT_FREQ_ABS_MAX) { ANXINFO("act clock(%u) large than maximum(%lu)\n", pixelclock * post_divider, PLL_OUT_FREQ_ABS_MAX); - return 1; + return -1; } *m = pixelclock; @@ -292,10 +290,12 @@ static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider) ret |= anx7625_write_or(bus, RX_P1_ADDR, MIPI_DIGITAL_PLL_7, MIPI_PLL_RESET_N); - if (ret < 0) + if (ret < 0) { ANXERROR("IO error.\n"); + return ret; + } - return ret; + return 0; } static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) @@ -305,10 +305,8 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) int ret; uint8_t post_divider = 0; - ret = anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n, - &post_divider); - - if (ret != 0) { + if (anx7625_calculate_m_n(dt->pixelclock * 1000, &m, &n, + &post_divider) < 0) { ANXERROR("cannot get property m n value.\n"); return -1; } @@ -385,10 +383,12 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt) ret |= anx7625_odfc_config(bus, post_divider - 1); - if (ret < 0) + if (ret < 0) { ANXERROR("mipi dsi setup IO error.\n"); + return ret; + } - return ret; + return 0; } static int anx7625_swap_dsi_lane3(uint8_t bus) @@ -400,7 +400,7 @@ static int anx7625_swap_dsi_lane3(uint8_t bus) ret = anx7625_reg_read(bus, RX_P1_ADDR, MIPI_SWAP, &val); if (ret < 0) { ANXERROR("IO error: access MIPI_SWAP.\n"); - return -1; + return ret; } val |= (1 << MIPI_SWAP_CH3); @@ -461,10 +461,12 @@ static int anx7625_api_dsi_config(uint8_t bus, struct display_timing *dt) ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x00); ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_LANE_CTRL_10, 0x80); - if (ret < 0) + if (ret < 0) { ANXERROR("IO error: mipi dsi enable init failed.\n"); + return ret; + } - return ret; + return 0; } static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) @@ -487,12 +489,13 @@ static int anx7625_dsi_config(uint8_t bus, struct display_timing *dt) /* clear mute flag */ ret |= anx7625_write_and(bus, RX_P0_ADDR, AP_AV_STATUS, ~AP_MIPI_MUTE); - if (ret < 0) + if (ret < 0) { ANXERROR("IO error: enable mipi rx failed.\n"); - else - ANXINFO("success to config DSI\n"); + return ret; + } - return ret; + ANXINFO("success to config DSI\n"); + return 0; } static int sp_tx_rst_aux(uint8_t bus) @@ -549,34 +552,32 @@ static int sp_tx_get_edid_block(uint8_t bus) static int edid_read(uint8_t bus, uint8_t offset, uint8_t *pblock_buf) { - uint8_t c, cnt = 0; + int ret, cnt; - c = 0; for (cnt = 0; cnt < 3; cnt++) { sp_tx_aux_wr(bus, offset); /* set I2C read com 0x01 mot = 0 and read 16 bytes */ - c = sp_tx_aux_rd(bus, 0xf1); + ret = sp_tx_aux_rd(bus, 0xf1); - if (c == 1) { + if (ret < 0) { sp_tx_rst_aux(bus); ANXERROR("edid read failed, reset!\n"); - cnt++; } else { - anx7625_reg_block_read(bus, RX_P0_ADDR, - AP_AUX_BUFF_START, - MAX_DPCD_BUFFER_SIZE, pblock_buf); - return 0; + if (anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, + pblock_buf) >= 0) + return 0; } } - return 1; + return -1; } static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf, uint8_t offset) { - uint8_t c, cnt = 0; - int ret; + int ret, cnt; /* write address only */ ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x30); @@ -598,21 +599,21 @@ static int segments_edid_read(uint8_t bus, uint8_t segment, uint8_t *buf, for (cnt = 0; cnt < 3; cnt++) { sp_tx_aux_wr(bus, offset); /* set I2C read com 0x01 mot = 0 and read 16 bytes */ - c = sp_tx_aux_rd(bus, 0xf1); + ret = sp_tx_aux_rd(bus, 0xf1); - if (c == 1) { - ret = sp_tx_rst_aux(bus); + if (ret < 0) { + sp_tx_rst_aux(bus); ANXERROR("segment read failed, reset!\n"); - cnt++; } else { - ret = anx7625_reg_block_read(bus, RX_P0_ADDR, - AP_AUX_BUFF_START, - MAX_DPCD_BUFFER_SIZE, buf); - return ret; + if (anx7625_reg_block_read(bus, RX_P0_ADDR, + AP_AUX_BUFF_START, + MAX_DPCD_BUFFER_SIZE, + buf) >= 0) + return 0; } } - return ret; + return -1; } static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, @@ -621,9 +622,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, uint8_t offset, edid_pos; int count, blocks_num; uint8_t pblock_buf[MAX_DPCD_BUFFER_SIZE]; - uint8_t i; - uint8_t g_edid_break = 0; - int ret; + int i, ret, g_edid_break = 0; /* address initial */ ret = anx7625_reg_write(bus, RX_P0_ADDR, AP_AUX_ADDR_7_0, 0x50); @@ -637,7 +636,7 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, blocks_num = sp_tx_get_edid_block(bus); if (blocks_num < 0) - return blocks_num; + return -1; count = 0; @@ -647,10 +646,10 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, case 1: for (i = 0; i < 8; i++) { offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; - g_edid_break = edid_read(bus, offset, - pblock_buf); + g_edid_break = !!edid_read(bus, offset, + pblock_buf); - if (g_edid_break == 1) + if (g_edid_break) break; if (offset <= size - MAX_DPCD_BUFFER_SIZE) @@ -668,11 +667,11 @@ static int sp_tx_edid_read(uint8_t bus, uint8_t *pedid_blocks_buf, edid_pos = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; - if (g_edid_break == 1) + if (g_edid_break) break; segments_edid_read(bus, count / 2, - pblock_buf, offset); + pblock_buf, offset); if (edid_pos <= size - MAX_DPCD_BUFFER_SIZE) memcpy(&pedid_blocks_buf[edid_pos], pblock_buf, @@ -834,12 +833,13 @@ int anx7625_dp_start(uint8_t bus, const struct edid *edid) anx7625_parse_edid(edid, &dt); ret = anx7625_dsi_config(bus, &dt); - if (ret < 0) + if (ret < 0) { ANXERROR("MIPI phy setup error.\n"); - else - ANXINFO("MIPI phy setup OK.\n"); + return ret; + } - return ret; + ANXINFO("MIPI phy setup OK.\n"); + return 0; } int anx7625_dp_get_edid(uint8_t bus, struct edid *out) @@ -866,13 +866,8 @@ int anx7625_dp_get_edid(uint8_t bus, struct edid *out) int anx7625_init(uint8_t bus) { int retry_hpd_change = 50; - int retry_power_on = 3; - while (--retry_power_on) { - if (anx7625_power_on_init(bus) == 0) - break; - } - if (!retry_power_on) { + if (!retry(3, anx7625_power_on_init(bus) >= 0)) { ANXERROR("Failed to power on.\n"); return -1; } diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 30d11313cb..8dccb45322 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -3,7 +3,6 @@ * Authors: Dave Airlie */ -#include #include #include "ast_drv.h" @@ -213,7 +212,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) ast->dp501_fw_addr = NULL; } } - /* fallthrough */ + __fallthrough; case 0x0c: ast->tx_chip_type = AST_TX_DP501; } diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index b25d742f01..6c63931f13 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -22,7 +22,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) struct drm_framebuffer *fb = crtc->primary->fb; /* PCI BAR 0 */ - struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0); + struct resource *res = probe_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_ERR, "BAR0 resource not found.\n"); return -EIO; diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index ca2ec6ecd6..37df182a8d 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -16,6 +16,7 @@ #include #include #include +#include #define ELOG_MIN_AVAILABLE_ENTRIES 2 /* Shrink when this many can't fit */ #define ELOG_SHRINK_PERCENTAGE 25 /* Percent of total area to remove */ @@ -749,6 +750,9 @@ int elog_init(void) } elog_state.elog_initialized = ELOG_BROKEN; + if (!ENV_SMM) + timestamp_add_now(TS_ELOG_INIT_START); + elog_debug("%s()\n", __func__); /* Set up the backing store */ @@ -781,6 +785,10 @@ int elog_init(void) if (ENV_PAYLOAD_LOADER) elog_add_boot_count(); + + if (!ENV_SMM) + timestamp_add_now(TS_ELOG_INIT_END); + return 0; } diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c index 90e1e5d105..7cd8a3651f 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.c +++ b/src/drivers/generic/bayhub_lv2/lv2.c @@ -6,11 +6,32 @@ #include #include #include +#include #include #include #include "chip.h" #include "lv2.h" +/* + * This chip has an errata where PCIe config space registers 0x234, 0x248, and + * 0x24C only support DWORD access, therefore reprogram these in the `finalize` + * callback. + */ +static void lv2_enable_ltr(struct device *dev) +{ + u16 max_snoop, max_nosnoop; + if (!pciexp_get_ltr_max_latencies(dev, &max_snoop, &max_nosnoop)) + return; + + const unsigned int ltr_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID); + if (!ltr_cap) + return; + + pci_write_config32(dev, ltr_cap + PCI_LTR_MAX_SNOOP, (max_snoop << 16) | max_nosnoop); + printk(BIOS_INFO, "%s: Re-programmed LTR max latencies using chip-specific quirk\n", + dev_path(dev)); +} + static void lv2_enable(struct device *dev) { struct drivers_generic_bayhub_lv2_config *config = dev->chip_info; @@ -45,6 +66,7 @@ static struct device_operations lv2_ops = { .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .enable = lv2_enable, + .final = lv2_enable_ltr, }; static const unsigned short pci_device_ids[] = { diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index b286af3c14..0097c594af 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include "chip.h" #include diff --git a/src/drivers/genesyslogic/gl9750/Kconfig b/src/drivers/genesyslogic/gl9750/Kconfig new file mode 100644 index 0000000000..f3449b0d87 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_GENESYSLOGIC_GL9750 + bool "Genesys Logic GL9750" + help + GL9750 is a PCI Express Rev. 1.1 compliant card reader controller + which integrates PCI Express PHY, memory card access interface, + regulators (3.3V-to-1.2V) and card power switch. Enabling this driver + will disable L0s support, which will allow the device to enter the + PCIe L1 link state. diff --git a/src/drivers/genesyslogic/gl9750/Makefile.inc b/src/drivers/genesyslogic/gl9750/Makefile.inc new file mode 100644 index 0000000000..0f771cc335 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9750) += gl9750.c diff --git a/src/drivers/genesyslogic/gl9750/gl9750.c b/src/drivers/genesyslogic/gl9750/gl9750.c new file mode 100644 index 0000000000..ca5cd096a5 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/gl9750.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Driver for Genesys Logic GL9750 */ + +#include +#include +#include +#include +#include +#include "gl9750.h" + +static void gl9750_enable(struct device *dev) +{ + printk(BIOS_INFO, "GL9750: configure ASPM\n"); + + /* Set Vendor Config to be configurable */ + pci_or_config32(dev, CFG, CFG_EN); + + /* + * When both ASPM L0s and L1 are supported, GL9750 may not enter L1. + * So disable L0s support. + */ + pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT); + + /* Set Vendor Config to be non-configurable */ + pci_and_config32(dev, CFG, ~CFG_EN); +} + +static struct device_operations gl9750_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .enable = gl9750_enable +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_GLI_9750, + 0 +}; + +static const struct pci_driver genesyslogic_gl9750 __pci_driver = { + .ops = &gl9750_ops, + .vendor = PCI_VENDOR_ID_GLI, + .devices = pci_device_ids, +}; + +struct chip_operations drivers_generic_genesyslogic_gl9750_ops = { + CHIP_NAME("Genesys Logic GL9750") +}; diff --git a/src/drivers/genesyslogic/gl9750/gl9750.h b/src/drivers/genesyslogic/gl9750/gl9750.h new file mode 100644 index 0000000000..e446caefb9 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/gl9750.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_GENESYSLOGIC_GL9750_H +#define DRIVERS_GENESYSLOGIC_GL9750_H + +/* Definitions for Genesys Logic GL9750 */ + +#define CFG 0x800 +#define CFG_EN 0x1 +#define CFG2 0x848 +#define CFG2_L0S_SUPPORT (0x1 << 6) + +#endif /* DRIVERS_GENESYSLOGIC_GL9750_H */ diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index becc2edaf0..d60082372b 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -29,6 +29,8 @@ struct drivers_gfx_generic_privacy_screen_config { struct drivers_gfx_generic_device_config { /* ACPI device name of the output device */ const char *name; + /* Value to use for _HID Name, will take precedence over _ADR */ + const char *hid; /* The address of the output device. See section A.3.2 */ unsigned int addr; /* Electronic privacy screen specific config */ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 98bde79cdc..7c6076c9f4 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -121,7 +121,11 @@ static void gfx_fill_ssdt_generator(const struct device *dev) for (i = 0; i < config->device_count; i++) { acpigen_write_device(config->device[i].name); - acpigen_write_name_integer("_ADR", config->device[i].addr); + if (config->device[i].hid) + acpigen_write_name_string("_HID", config->device[i].hid); + else + acpigen_write_name_integer("_ADR", config->device[i].addr); + acpigen_write_name_integer("_STA", 0xF); gfx_fill_privacy_screen_dsm(&config->device[i].privacy); acpigen_pop_len(); /* Device */ diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index a6498fb1c3..2cc236e81b 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "dw_i2c.h" /* Use a ~10ms timeout for various operations */ @@ -42,7 +43,7 @@ struct freq { enum { CONTROL_MASTER_MODE = (1 << 0), CONTROL_SPEED_SS = (1 << 1), - CONTROL_SPEED_FS = (1 << 2), + CONTROL_SPEED_FS = (2 << 1), CONTROL_SPEED_HS = (3 << 1), CONTROL_SPEED_MASK = (3 << 1), CONTROL_10BIT_SLAVE = (1 << 3), @@ -264,7 +265,7 @@ static void dw_i2c_enable(struct dw_i2c_regs *regs) } /* Disable this I2C controller */ -static int dw_i2c_disable(struct dw_i2c_regs *regs) +static enum cb_err dw_i2c_disable(struct dw_i2c_regs *regs) { uint32_t enable = read32(®s->enable); @@ -277,14 +278,14 @@ static int dw_i2c_disable(struct dw_i2c_regs *regs) stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US); while (read32(®s->enable_status) & ENABLE_CONTROLLER) if (stopwatch_expired(&sw)) - return -1; + return CB_ERR; } - return 0; + return CB_SUCCESS; } /* Wait for this I2C controller to go idle for transmit */ -static int dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs) +static enum cb_err dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs) { struct stopwatch sw; @@ -300,17 +301,17 @@ static int dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs) /* Check for TX FIFO empty to indicate TX idle */ if (status & STATUS_TX_FIFO_EMPTY) - return 0; + return CB_SUCCESS; } /* Timed out while waiting for bus to go idle */ - return -1; + return CB_ERR; } /* Transfer one byte of one segment, sending stop bit if requested */ -static int dw_i2c_transfer_byte(struct dw_i2c_regs *regs, - const struct i2c_msg *segment, - size_t byte, int send_stop) +static enum cb_err dw_i2c_transfer_byte(struct dw_i2c_regs *regs, + const struct i2c_msg *segment, + size_t byte, int send_stop) { struct stopwatch sw; uint32_t cmd = CMD_DATA_CMD; /* Read op */ @@ -322,7 +323,7 @@ static int dw_i2c_transfer_byte(struct dw_i2c_regs *regs, while (!(read32(®s->status) & STATUS_TX_FIFO_NOT_FULL)) { if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "I2C transmit timeout\n"); - return -1; + return CB_ERR; } } cmd = segment->buf[byte]; @@ -339,27 +340,27 @@ static int dw_i2c_transfer_byte(struct dw_i2c_regs *regs, while (!(read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY)) { if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "I2C receive timeout\n"); - return -1; + return CB_ERR; } } segment->buf[byte] = read32(®s->cmd_data); } - return 0; + return CB_SUCCESS; } -static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, - size_t count) +static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, + size_t count) { struct stopwatch sw; struct dw_i2c_regs *regs; size_t byte; - int ret = -1; + enum cb_err ret = CB_ERR; regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); if (!regs) { printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); - return -1; + return CB_ERR; } /* The assumption is that the host controller is disabled -- either @@ -387,8 +388,8 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, * Repeated start will be automatically generated * by the controller on R->W or W->R switch. */ - if (dw_i2c_transfer_byte(regs, segments, byte, - count == 0) < 0) { + if (dw_i2c_transfer_byte(regs, segments, byte, count == 0) != + CB_SUCCESS) { printk(BIOS_ERR, "I2C %s failed: bus %u " "addr 0x%02x\n", (segments->flags & I2C_M_RD) ? @@ -429,7 +430,7 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, } /* Wait for the bus to go idle */ - if (dw_i2c_wait_for_bus_idle(regs)) { + if (dw_i2c_wait_for_bus_idle(regs) != CB_SUCCESS) { printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); goto out; } @@ -444,7 +445,7 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, read32(®s->cmd_data); } - ret = 0; + ret = CB_SUCCESS; out: read32(®s->clear_intr); @@ -452,7 +453,7 @@ out: return ret; } -int dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count) +static enum cb_err dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count) { const struct i2c_msg *orig_msg = msg; size_t i; @@ -467,8 +468,8 @@ int dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count) for (i = 0, start = 0; i < count; i++, msg++) { if (addr != msg->slave) { - if (_dw_i2c_transfer(bus, &orig_msg[start], i - start)) - return -1; + if (_dw_i2c_transfer(bus, &orig_msg[start], i - start) != CB_SUCCESS) + return CB_ERR; start = i; addr = msg->slave; } @@ -480,22 +481,22 @@ int dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count) /* Global I2C bus handler, defined in include/device/i2c_simple.h */ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *msg, int count) { - return dw_i2c_transfer(bus, msg, count < 0 ? 0 : count); + return dw_i2c_transfer(bus, msg, count < 0 ? 0 : count) == CB_SUCCESS ? 0 : -1; } -static int dw_i2c_set_speed_config(unsigned int bus, - const struct dw_i2c_speed_config *config) +static enum cb_err dw_i2c_set_speed_config(unsigned int bus, + const struct dw_i2c_speed_config *config) { struct dw_i2c_regs *regs; void *hcnt_reg, *lcnt_reg; regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); if (!regs || !config) - return -1; + return CB_ERR; /* Nothing to do if no values are set */ if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold) - return 0; + return CB_SUCCESS; if (config->speed >= I2C_SPEED_HIGH) { /* High and Fast Ultra speed */ @@ -521,14 +522,14 @@ static int dw_i2c_set_speed_config(unsigned int bus, if (config->sda_hold) write32(®s->sda_hold, config->sda_hold); - return 0; + return CB_SUCCESS; } -static int dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, - enum i2c_speed speed, - const struct dw_i2c_bus_config *bcfg, - int ic_clk, - struct dw_i2c_speed_config *config) +static enum cb_err dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, + enum i2c_speed speed, + const struct dw_i2c_bus_config *bcfg, + int ic_clk, + struct dw_i2c_speed_config *config) { const struct i2c_descriptor *bus; const struct soc_clock *soc; @@ -541,13 +542,13 @@ static int dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, if (bus == NULL) { printk(BIOS_ERR, "dw_i2c: invalid bus speed %d\n", speed); - return -1; + return CB_ERR; } if (soc == NULL) { printk(BIOS_ERR, "dw_i2c: invalid SoC clock speed %d MHz\n", ic_clk); - return -1; + return CB_ERR; } /* Get the proper spike suppression count based on target speed. */ @@ -582,7 +583,7 @@ static int dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, if (hcnt < 0 || lcnt < 0) { printk(BIOS_ERR, "dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt); - return -1; + return CB_ERR; } /* Now add things back up to ensure the period is hit. If off, @@ -611,10 +612,10 @@ static int dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, printk(DW_I2C_DEBUG, "dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt, config->sda_hold); - return 0; + return CB_SUCCESS; } -int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, +enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, enum i2c_speed speed, const struct dw_i2c_bus_config *bcfg, struct dw_i2c_speed_config *config) @@ -633,15 +634,15 @@ int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, if (bcfg->speed_config[i].speed != speed) continue; memcpy(config, &bcfg->speed_config[i], sizeof(*config)); - return 0; + return CB_SUCCESS; } /* Use the time calculation. */ return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config); } -static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, - const struct dw_i2c_bus_config *bcfg) +static enum cb_err dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, + const struct dw_i2c_bus_config *bcfg) { struct dw_i2c_regs *regs; struct dw_i2c_speed_config config; @@ -650,7 +651,7 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, /* Clock must be provided by Kconfig */ regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); if (!regs || !speed) - return -1; + return CB_ERR; control = read32(®s->control); control &= ~CONTROL_SPEED_MASK; @@ -667,8 +668,8 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, } /* Generate speed config based on clock */ - if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) < 0) - return -1; + if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) != CB_SUCCESS) + return CB_ERR; /* Select this speed in the control register */ write32(®s->control, control); @@ -676,7 +677,7 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, /* Write the speed config that was generated earlier */ dw_i2c_set_speed_config(bus, &config); - return 0; + return CB_SUCCESS; } /* @@ -685,33 +686,33 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, * The bus speed can be passed in Hz or using values from device/i2c.h and * will default to I2C_SPEED_FAST if it is not provided. */ -int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) +enum cb_err dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) { struct dw_i2c_regs *regs; enum i2c_speed speed; if (!bcfg) - return -1; + return CB_ERR; speed = bcfg->speed ? : I2C_SPEED_FAST; regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); if (!regs) { printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); - return -1; + return CB_ERR; } if (read32(®s->comp_type) != DW_I2C_COMP_TYPE) { printk(BIOS_ERR, "I2C bus %u has unknown type 0x%x.\n", bus, read32(®s->comp_type)); - return -1; + return CB_ERR; } printk(BIOS_DEBUG, "I2C bus %u version 0x%x\n", bus, read32(®s->comp_version)); - if (dw_i2c_disable(regs) < 0) { + if (dw_i2c_disable(regs) != CB_SUCCESS) { printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); - return -1; + return CB_ERR; } /* Put controller in master mode with restart enabled */ @@ -719,9 +720,9 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) CONTROL_RESTART_ENABLE); /* Set bus speed to FAST by default */ - if (dw_i2c_set_speed(bus, speed, bcfg) < 0) { + if (dw_i2c_set_speed(bus, speed, bcfg) != CB_SUCCESS) { printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus); - return -1; + return CB_ERR; } /* Set RX/TX thresholds to smallest values */ @@ -734,7 +735,7 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); - return 0; + return CB_SUCCESS; } /* @@ -828,7 +829,7 @@ void dw_i2c_acpi_fill_ssdt(const struct device *dev) /* Report currently used timing values for the OS driver */ acpigen_write_scope(path); - if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) >= 0) { + if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) == CB_SUCCESS) { dw_i2c_acpi_write_speed_config(&sgen); } /* Now check if there are more speed settings available and report them as well. */ diff --git a/src/drivers/i2c/designware/dw_i2c.h b/src/drivers/i2c/designware/dw_i2c.h index e20a5d1d7e..464facfeed 100644 --- a/src/drivers/i2c/designware/dw_i2c.h +++ b/src/drivers/i2c/designware/dw_i2c.h @@ -5,7 +5,7 @@ #include #include -#include +#include #if CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG) #define DW_I2C_DEBUG BIOS_DEBUG @@ -95,33 +95,17 @@ uintptr_t dw_i2c_base_address(unsigned int bus); /* * Initialize this bus controller and set the speed - * Return value: - * -1 = failure - * 0 = success */ -int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg); +enum cb_err dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg); /* * Generate speed config based on clock - * Return value: - * -1 = failure - * 0 = success */ -int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, +enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, enum i2c_speed speed, const struct dw_i2c_bus_config *bcfg, struct dw_i2c_speed_config *config); -/* - * Process given I2C segments in a single transfer - * Return value: - * -1 = failure - * 0 = success - */ -int dw_i2c_transfer(unsigned int bus, - const struct i2c_msg *segments, - size_t count); - /* * Map an i2c host controller device to a logical bus number. * Return value: diff --git a/src/drivers/i2c/gpiomux/bus/bus.c b/src/drivers/i2c/gpiomux/bus/bus.c index 0bcf36a3f4..2bdb103016 100644 --- a/src/drivers/i2c/gpiomux/bus/bus.c +++ b/src/drivers/i2c/gpiomux/bus/bus.c @@ -5,8 +5,8 @@ #include #include #include -#include #include + #include "chip.h" static const char *i2c_gpiomux_bus_acpi_name(const struct device *dev) diff --git a/src/drivers/i2c/gpiomux/mux/mux.c b/src/drivers/i2c/gpiomux/mux/mux.c index c1ae758226..fa1b18cde2 100644 --- a/src/drivers/i2c/gpiomux/mux/mux.c +++ b/src/drivers/i2c/gpiomux/mux/mux.c @@ -5,8 +5,8 @@ #include #include #include -#include #include + #include "chip.h" static const char *i2c_gpiomux_mux_acpi_name(const struct device *dev) diff --git a/src/drivers/i2c/max98390/max98390.c b/src/drivers/i2c/max98390/max98390.c index 08ed625163..664a7109fe 100644 --- a/src/drivers/i2c/max98390/max98390.c +++ b/src/drivers/i2c/max98390/max98390.c @@ -73,7 +73,7 @@ static void max98390_fill_ssdt(const struct device *dev) CONFIG_MAINBOARD_PART_NUMBER); if (chars >= sizeof(dsm_name)) - printk(BIOS_ERR, "ERROR: String too long in %s\n", __func__); + printk(BIOS_ERR, "String too long in %s\n", __func__); acpi_dp_add_string(dp, "maxim,dsm_param_name", dsm_name); } diff --git a/src/drivers/i2c/sx9360/Kconfig b/src/drivers/i2c/sx9360/Kconfig new file mode 100644 index 0000000000..ea28564fb9 --- /dev/null +++ b/src/drivers/i2c/sx9360/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_SX9360 + bool + default n + depends on HAVE_ACPI_TABLES + help + Board has a Semtech SX9360 proximity sensor. diff --git a/src/drivers/i2c/sx9360/Makefile.inc b/src/drivers/i2c/sx9360/Makefile.inc new file mode 100644 index 0000000000..695bb527c7 --- /dev/null +++ b/src/drivers/i2c/sx9360/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_SX9360) += sx9360.c diff --git a/src/drivers/i2c/sx9360/chip.h b/src/drivers/i2c/sx9360/chip.h new file mode 100644 index 0000000000..397ea3f5d2 --- /dev/null +++ b/src/drivers/i2c/sx9360/chip.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_I2C_SX9360_CHIP_H__ +#define __DRIVERS_I2C_SX9360_CHIP_H__ + +#include +#include + +struct drivers_i2c_sx9360_config { + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; + + /* + * Registers definition in the kernel source tree at: + * Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml + */ + + /* Raw Proximity filter strength: When not set, disabled. */ + uint32_t proxraw_strength; + + /* Average Proximity filter strength: When not set, disabled. */ + uint32_t avg_pos_strength; + + /* Capacitance measure resolution. Driver default: 128. */ + uint32_t resolution; +}; + +#endif /* __DRIVERS_I2C_SX9360_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9360/sx9360.c b/src/drivers/i2c/sx9360/sx9360.c new file mode 100644 index 0000000000..9ea4c8b90c --- /dev/null +++ b/src/drivers/i2c/sx9360/sx9360.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define I2C_SX9360_ACPI_ID "STH9360" +#define I2C_SX9360_CHIP_NAME "Semtech SX9360" + +static void i2c_sx9360_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_sx9360_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + + if (!scope || !config) + return; + + if (config->speed) + i2c.speed = config->speed; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", I2C_SX9360_ACPI_ID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); + + /* + * Format described in linux kernel documentation. See + * https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9360.yaml + */ + acpi_dp_add_integer(dsd, "semtech,proxraw-strength", + config->proxraw_strength); + acpi_dp_add_integer(dsd, "semtech,avg-pos-strength", + config->avg_pos_strength); + acpi_dp_add_integer(dsd, "semtech,resolution", + config->resolution); + + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +static const char *i2c_sx9360_acpi_name(const struct device *dev) +{ + static char name[5]; + + snprintf(name, sizeof(name), "SX%02.2X", dev->path.i2c.device); + return name; +} + +static struct device_operations i2c_sx9360_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = i2c_sx9360_acpi_name, + .acpi_fill_ssdt = i2c_sx9360_fill_ssdt, +}; + +static void i2c_sx9360_enable(struct device *dev) +{ + struct drivers_i2c_sx9360_config *config = config_of(dev); + + if (!is_dev_enabled(dev)) + return; + + dev->ops = &i2c_sx9360_ops; + + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_sx9360_ops = { + CHIP_NAME(I2C_SX9360_CHIP_NAME) + .enable_dev = i2c_sx9360_enable +}; diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index df622f079d..dcf9060952 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -31,12 +31,12 @@ config DRIVER_TIS_DEFAULT default y config DRIVER_TPM_I2C_BUS - hex "I2C TPM chip bus" + hex default 0x9 # FIXME, workaround for Kconfig BS depends on I2C_TPM config DRIVER_TPM_I2C_ADDR - hex "I2C TPM chip address" + hex default 0x2 # FIXME, workaround for Kconfig BS depends on I2C_TPM diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 07791c33a4..07052f6f0d 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -11,6 +11,7 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) { + struct acpi_dp *dsd; struct drivers_i2c_tpm_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); struct acpi_i2c i2c = { @@ -47,6 +48,22 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) acpigen_write_resourcetemplate_footer(); + /* _DSD, Device-Specific Data */ + dsd = acpi_dp_new_table("_DSD"); + switch (config->power_managed_mode) { + case TPM_FIRMWARE_POWER_MANAGED: + acpi_dp_add_integer(dsd, "firmware-power-managed", 1); + break; + case TPM_KERNEL_POWER_MANAGED: + acpi_dp_add_integer(dsd, "firmware-power-managed", 0); + break; + case TPM_DEFAULT_POWER_MANAGED: + default: + /* Leave firmware-power-managed unset */ + break; + } + acpi_dp_write(dsd); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index 0ab10d7560..4eac7e16f4 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -3,6 +3,12 @@ #include #include +enum tpm_power_managed_mode { + TPM_DEFAULT_POWER_MANAGED = 0, + TPM_FIRMWARE_POWER_MANAGED, + TPM_KERNEL_POWER_MANAGED, +}; + struct drivers_i2c_tpm_config { const char *hid; /* ACPI _HID (required) */ const char *desc; /* Device Description */ @@ -10,4 +16,5 @@ struct drivers_i2c_tpm_config { enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ struct acpi_irq irq; /* Interrupt */ struct acpi_gpio irq_gpio; /* GPIO interrupt */ + enum tpm_power_managed_mode power_managed_mode; /* TPM power managed mode */ }; diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index a8a310fc7f..415285297d 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -49,7 +49,7 @@ __weak int tis_plat_irq_status(void) static int warning_displayed; if (!warning_displayed) { - printk(BIOS_WARNING, "WARNING: %s() not implemented, wasting 20ms to wait on" + printk(BIOS_WARNING, "%s() not implemented, wasting 20ms to wait on" " Cr50!\n", __func__); warning_displayed = 1; } @@ -59,7 +59,7 @@ __weak int tis_plat_irq_status(void) } /* Wait for interrupt to indicate the TPM is ready */ -static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) +static int cr50_i2c_wait_tpm_ready(void) { struct stopwatch sw; @@ -76,7 +76,6 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) /* * cr50_i2c_read() - read from TPM register * - * @chip: TPM chip information * @addr: register address to read from * @buffer: provided by caller * @len: number of bytes to read @@ -87,8 +86,7 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) * * Return -1 on error, 0 on success. */ -static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, - uint8_t *buffer, size_t len) +static int cr50_i2c_read(uint8_t addr, uint8_t *buffer, size_t len) { if (tpm_dev.addr == 0) return -1; @@ -103,7 +101,7 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, } /* Wait for TPM to be ready with response data */ - if (cr50_i2c_wait_tpm_ready(chip) < 0) + if (cr50_i2c_wait_tpm_ready() < 0) return -1; /* Read response data from the TPM */ @@ -118,7 +116,6 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, /* * cr50_i2c_write() - write to TPM register * - * @chip: TPM chip information * @addr: register address to write to * @buffer: data to write * @len: number of bytes to write @@ -129,8 +126,7 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr, * * Returns -1 on error, 0 on success. */ -static int cr50_i2c_write(struct tpm_chip *chip, - uint8_t addr, uint8_t *buffer, size_t len) +static int cr50_i2c_write(uint8_t addr, uint8_t *buffer, size_t len) { if (tpm_dev.addr == 0) return -1; @@ -151,7 +147,7 @@ static int cr50_i2c_write(struct tpm_chip *chip, } /* Wait for TPM to be ready */ - return cr50_i2c_wait_tpm_ready(chip); + return cr50_i2c_wait_tpm_ready(); } /* @@ -161,7 +157,7 @@ static int cr50_i2c_write(struct tpm_chip *chip, * This function will make sure that the AP does not proceed with boot until * TPM finished reset processing. */ -static int process_reset(struct tpm_chip *chip) +static int process_reset(void) { struct stopwatch sw; int rv = 0; @@ -180,7 +176,7 @@ static int process_reset(struct tpm_chip *chip) const uint8_t mask = TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY; - rv = cr50_i2c_read(chip, TPM_ACCESS(0), + rv = cr50_i2c_read(TPM_ACCESS(0), &access, sizeof(access)); if (rv || ((access & mask) == mask)) { /* @@ -212,12 +208,12 @@ static int process_reset(struct tpm_chip *chip) * the RO did not release it), or not yet claimed, if this is verstage or the * older RO did release it. */ -static int claim_locality(struct tpm_chip *chip) +static int claim_locality(void) { uint8_t access; const uint8_t mask = TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY; - if (cr50_i2c_read(chip, TPM_ACCESS(0), &access, sizeof(access))) + if (cr50_i2c_read(TPM_ACCESS(0), &access, sizeof(access))) return -1; if ((access & mask) == mask) { @@ -226,11 +222,11 @@ static int claim_locality(struct tpm_chip *chip) } access = TPM_ACCESS_REQUEST_USE; - if (cr50_i2c_write(chip, TPM_ACCESS(0), + if (cr50_i2c_write(TPM_ACCESS(0), &access, sizeof(access))) return -1; - if (cr50_i2c_read(chip, TPM_ACCESS(0), &access, sizeof(access))) + if (cr50_i2c_read(TPM_ACCESS(0), &access, sizeof(access))) return -1; if ((access & mask) != mask) { @@ -245,7 +241,7 @@ static int claim_locality(struct tpm_chip *chip) static uint8_t cr50_i2c_tis_status(struct tpm_chip *chip) { uint8_t buf[4]; - if (cr50_i2c_read(chip, TPM_STS(chip->vendor.locality), + if (cr50_i2c_read(TPM_STS(chip->vendor.locality), buf, sizeof(buf)) < 0) { printk(BIOS_ERR, "%s: Failed to read status\n", __func__); return 0; @@ -257,7 +253,7 @@ static uint8_t cr50_i2c_tis_status(struct tpm_chip *chip) static void cr50_i2c_tis_ready(struct tpm_chip *chip) { uint8_t buf[4] = { TPM_STS_COMMAND_READY }; - cr50_i2c_write(chip, TPM_STS(chip->vendor.locality), buf, sizeof(buf)); + cr50_i2c_write(TPM_STS(chip->vendor.locality), buf, sizeof(buf)); mdelay(CR50_TIMEOUT_SHORT_MS); } @@ -272,7 +268,7 @@ static int cr50_i2c_wait_burststs(struct tpm_chip *chip, uint8_t mask, stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_LONG_MS); while (!stopwatch_expired(&sw)) { - if (cr50_i2c_read(chip, TPM_STS(chip->vendor.locality), + if (cr50_i2c_read(TPM_STS(chip->vendor.locality), buf, sizeof(buf)) != 0) { mdelay(CR50_TIMEOUT_SHORT_MS); continue; @@ -310,7 +306,7 @@ static int cr50_i2c_tis_recv(struct tpm_chip *chip, uint8_t *buf, } /* Read first chunk of burstcnt bytes */ - if (cr50_i2c_read(chip, addr, buf, burstcnt) != 0) { + if (cr50_i2c_read(addr, buf, burstcnt) != 0) { printk(BIOS_ERR, "%s: Read failed\n", __func__); goto out_err; } @@ -331,7 +327,7 @@ static int cr50_i2c_tis_recv(struct tpm_chip *chip, uint8_t *buf, goto out_err; len = MIN(burstcnt, expected - current); - if (cr50_i2c_read(chip, addr, buf + current, len) != 0) { + if (cr50_i2c_read(addr, buf + current, len) != 0) { printk(BIOS_ERR, "%s: Read failed\n", __func__); goto out_err; } @@ -390,7 +386,7 @@ static int cr50_i2c_tis_send(struct tpm_chip *chip, uint8_t *buf, size_t len) /* Use burstcnt - 1 to account for the address byte * that is inserted by cr50_i2c_write() */ limit = MIN(burstcnt - 1, len); - if (cr50_i2c_write(chip, TPM_DATA_FIFO(chip->vendor.locality), + if (cr50_i2c_write(TPM_DATA_FIFO(chip->vendor.locality), &buf[sent], limit) != 0) { printk(BIOS_ERR, "%s: Write failed\n", __func__); goto out_err; @@ -409,7 +405,7 @@ static int cr50_i2c_tis_send(struct tpm_chip *chip, uint8_t *buf, size_t len) } /* Start the TPM command */ - if (cr50_i2c_write(chip, TPM_STS(chip->vendor.locality), tpm_go, + if (cr50_i2c_write(TPM_STS(chip->vendor.locality), tpm_go, sizeof(tpm_go)) < 0) { printk(BIOS_ERR, "%s: Start command failed\n", __func__); goto out_err; @@ -445,16 +441,17 @@ static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid) int retries; /* - * 150 ms should be enough to synchronize with the TPM even under the + * 1s should be enough to synchronize with the TPM even under the * worst nested reset request conditions. In vast majority of cases - * there would be no wait at all. + * there would be no wait at all. If this probe fails, boot likely + * cannot proceed, so an extra long timeout is appropriate. */ printk(BIOS_INFO, "Probing TPM I2C: "); - for (retries = 15; retries > 0; retries--) { + for (retries = 100; retries > 0; retries--) { int rc; - rc = cr50_i2c_read(chip, TPM_DID_VID(0), (uint8_t *)did_vid, 4); + rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4); /* Exit once DID and VID verified */ if (!rc && (*did_vid == CR50_DID_VID)) { @@ -492,10 +489,10 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr) return -1; if (ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK) - if (process_reset(chip)) + if (process_reset()) return -1; - if (claim_locality(chip)) + if (claim_locality()) return -1; printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index c6ead0f6ed..71a25b606e 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -192,7 +192,7 @@ static void write_generic_devices(const struct drivers_intel_dptf_config *config get_STA_value(config, DPTF_CHARGER), platform_info); - for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < 4; ++i, ++participant) { + for (i = 0, participant = DPTF_TEMP_SENSOR_0; i < DPTF_MAX_TSR; ++i, ++participant) { snprintf(name, sizeof(name), "TSR%1d", i); dptf_write_generic_participant(name, DPTF_GENERIC_PARTICIPANT_TYPE_TSR, NULL, get_STA_value(config, participant), @@ -449,7 +449,7 @@ static void write_options(const struct drivers_intel_dptf_config *config) acpigen_pop_len(); /* Scope */ /* TSR options */ - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { if (is_participant_used(config, p) && (config->options.tsr[i].hysteresis || config->options.tsr[i].desc)) { dptf_write_scope(p); diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index e20d5277ed..6a19b870f2 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -181,7 +181,7 @@ CAR_init_done: pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2A) + post_code(0x2a) /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c index 7aaba82e6b..875fcf218f 100644 --- a/src/drivers/intel/fsp1_1/fsp_relocate.c +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -15,14 +15,14 @@ int fsp_relocate(struct prog *fsp_relocd) void *new_loc = cbfs_cbmem_alloc(prog_name(fsp_relocd), CBMEM_ID_REFCODE, &size); if (new_loc == NULL) { - printk(BIOS_ERR, "ERROR: Unable to load FSP into memory.\n"); + printk(BIOS_ERR, "Unable to load FSP into memory.\n"); return -1; } fih_offset = fsp1_1_relocate((uintptr_t)new_loc, new_loc, size); if (fih_offset <= 0) { - printk(BIOS_ERR, "ERROR: FSP relocation failure.\n"); + printk(BIOS_ERR, "FSP relocation failure.\n"); return -1; } diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index c74955e9d3..78700a9b0c 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -193,8 +193,7 @@ void raminit(struct romstage_params *params) /* Verify all the HOBs are present */ if (fsp_verification_failure) - printk(BIOS_ERR, - "ERROR - Missing one or more required FSP HOBs!\n"); + printk(BIOS_ERR, "Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ if (CONFIG(DISPLAY_HOBS)) @@ -209,8 +208,7 @@ void raminit(struct romstage_params *params) if ((fsp_memory != NULL) && (cbmem_root != NULL) && (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { fsp_verification_failure = 1; - printk(BIOS_ERR, - "ERROR - FSP reserved memory above CBMEM root!\n"); + printk(BIOS_ERR, "FSP reserved memory above CBMEM root!\n"); } /* Verify that the FSP memory was properly reserved */ @@ -218,7 +216,7 @@ void raminit(struct romstage_params *params) (fsp_memory->PhysicalStart != (unsigned int)fsp_reserved_memory_area))) { fsp_verification_failure = 1; - printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n"); + printk(BIOS_ERR, "Reserving FSP memory area!\n"); if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) { size_t delta_bytes = smm_base diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index dcb32c7907..d85ba7cfc5 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -20,7 +20,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) /* Verify the HOBs */ if (hob_list_ptr == NULL) { - printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); + printk(BIOS_ERR, "HOB pointer is NULL!\n"); return; } @@ -41,8 +41,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) !get_next_guid_hob(&graphics_info_guid, hob_list_ptr) && CONFIG(DISPLAY_HOBS)) { printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); - printk(BIOS_ERR, - "ERROR - Missing one or more required FSP HOBs!\n"); + printk(BIOS_ERR, "Missing one or more required FSP HOBs!\n"); } } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 62b112a3be..3ed73d32c9 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -18,7 +18,6 @@ #include #include #include -#include static void raminit_common(struct romstage_params *params) { @@ -104,9 +103,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) timestamp_add_now(TS_START_ROMSTAGE); /* Display parameters */ - if (!CONFIG(NO_MMCONF_SUPPORT)) - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); + if (!CONFIG(NO_ECAM_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_ECAM_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); /* Display FSP banner */ diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index ba93baa4de..fdea4b886f 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -29,6 +29,16 @@ config PLATFORM_USES_FSP2_2 3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. +config PLATFORM_USES_FSP2_3 + bool + default n + select PLATFORM_USES_FSP2_2 + help + Include FSP 2.3 wrappers and functionality. + Features added into FSP 2.3 specification that impact coreboot are: + 1. Added ExtendedImageRevision field in FSP_INFO_HEADER + 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 + if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 @@ -218,6 +228,16 @@ config FSP_COMPRESS_FSP_M_LZ4 bool depends on !FSP_M_XIP +config FSP_ALIGNMENT_FSP_S + int + help + Sets the CBFS alignment for FSP-S + +config FSP_ALIGNMENT_FSP_M + int + help + Sets the CBFS alignment for FSP-M + config FSP_M_ADDR hex help @@ -290,4 +310,46 @@ config FSPS_USE_MULTI_PHASE_INIT SoC users to select this Kconfig to set EnableMultiPhaseSiliconInit to enable and execute FspMultiPhaseSiInit() API. +config USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + bool + help + The FSP API is used to notify the FSP about different phases in the boot process. + The current FSP specification supports three notify phases: + - Post PCI enumeration + - Ready to Boot + - End of Firmware + This option allows FSP to execute Notify Phase API (Post PCI enumeration). + SoC users can override this config to use coreboot native implementations + to perform the required lock down and chipset register configuration prior + to executing any 3rd-party code during PCI enumeration (i.e. Option ROM). + + coreboot native implementation to skip FSP Notify Phase (Post PCI enumeration) + is still WIP. + +config USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + bool + help + The FSP API is used to notify the FSP about different phases in the boot process. + The current FSP specification supports three notify phases: + - Post PCI enumeration + - Ready to Boot + - End of Firmware + This option allows FSP to execute Notify Phase API (Ready to Boot). + SoC users can override this config to use coreboot native implementations + to perform the required lock down and chipset register configuration prior + boot to payload. + +config USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + bool + help + The FSP API is used to notify the FSP about different phases in the boot process. + The current FSP specification supports three notify phases: + - Post PCI enumeration + - Ready to Boot + - End of Firmware + This option allows FSP to execute Notify Phase API (End of Firmware). + SoC users can override this config to use coreboot native implementations + to perform the required lock down and chipset register configuration prior + boot to payload. + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 92ebf24e5d..eaf99d1492 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -65,6 +65,9 @@ endif ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y) $(FSP_M_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),) +$(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M) +endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS) $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) @@ -75,6 +78,9 @@ endif ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif +ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),) +$(FSP_S_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_S) +endif ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 323c799987..8c0d67daeb 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include +#include #include asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) @@ -32,6 +34,41 @@ static void fsp_gpio_config_check(enum fsp_call_phase phase, const char *call_st } } +enum fsp_log_level fsp_map_console_log_level(void) +{ + enum fsp_log_level fsp_debug_level; + + switch (get_log_level()) { + case BIOS_EMERG: + case BIOS_ALERT: + case BIOS_CRIT: + case BIOS_ERR: + fsp_debug_level = FSP_LOG_LEVEL_ERR; + break; + case BIOS_WARNING: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN; + break; + case BIOS_NOTICE: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN_INFO; + break; + case BIOS_INFO: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT; + break; + case BIOS_DEBUG: + case BIOS_SPEW: + fsp_debug_level = FSP_LOG_LEVEL_VERBOSE; + break; + default: + fsp_debug_level = FSP_LOG_LEVEL_DISABLE; + break; + } + + if (!CONFIG(DEBUG_RAM_SETUP)) + fsp_debug_level = MIN(fsp_debug_level, FSP_LOG_LEVEL_ERR_WARN_INFO); + + return fsp_debug_level; +} + /*----------- * MemoryInit *----------- diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index fd8316e01d..c9c99f9bc1 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -286,7 +286,6 @@ void fsp_display_fvi_version_hob(void) { const uint8_t *hob_uuid; const struct hob_header *hob = fsp_get_hob_list(); - size_t size; if (!hob) return; @@ -300,7 +299,6 @@ void fsp_display_fvi_version_hob(void) hob_uuid = hob_header_to_struct(hob); if (fsp_guid_compare(hob_uuid, uuid_fv_info)) { - size = hob->length - (HOB_HEADER_LEN + 16); display_fsp_version_info_hob(hob); } } diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 4f9366657d..d209e4ce2d 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -6,35 +6,48 @@ void fsp_print_header_info(const struct fsp_header *hdr) { union fsp_revision revision; + union extended_fsp_revision ext_revision; + ext_revision.val = 0; + int i; - revision.val = hdr->fsp_revision; + /* For FSP 2.3 and later use extended image revision field present in header + * for build number and revision calculation */ + if (CONFIG(PLATFORM_USES_FSP2_3)) + ext_revision.val = hdr->extended_image_revision; + revision.val = hdr->image_revision; printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4), hdr->spec_version & 0xf); printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", - revision.rev.major, - revision.rev.minor, - revision.rev.revision, - revision.rev.bld_num); + revision.rev.major, + revision.rev.minor, + ((ext_revision.rev.revision << 8) | revision.rev.revision), + ((ext_revision.rev.bld_num << 8) | revision.rev.bld_num)); printk(BIOS_SPEW, "Type: %s/%s\n", (hdr->component_attribute & 1) ? "release" : "debug", (hdr->component_attribute & 2) ? "official" : "test"); - printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n", - hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size); + + printk(BIOS_SPEW, "image ID: "); + for (i = 0; i < FSP_IMAGE_ID_LENGTH; i++) + printk(BIOS_SPEW, "%c", hdr->image_id[i]); + printk(BIOS_SPEW, "\n"); + + printk(BIOS_SPEW, " base 0x%zx + 0x%zx\n", + (size_t)hdr->image_base, (size_t)hdr->image_size); printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", (size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size); if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", - (size_t)hdr->memory_init_entry_offset); + (size_t)hdr->fsp_memory_init_entry_offset); } if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", - (size_t)hdr->silicon_init_entry_offset); + (size_t)hdr->fsp_silicon_init_entry_offset); if (CONFIG(PLATFORM_USES_FSP2_2)) printk(BIOS_SPEW, "\tMultiPhaseSiInit offset 0x%zx\n", - (size_t)hdr->multi_phase_si_init_entry_offset); + (size_t)hdr->fsp_multi_phase_si_init_entry_offset); printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", (size_t)hdr->notify_phase_entry_offset); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 68b84703ca..c035452e05 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -32,7 +32,9 @@ enum fsp_notify_phase { }; /* Main FSP stages */ +void preload_fspm(void); void fsp_memory_init(bool s3wake); +void preload_fsps(void); void fsp_silicon_init(void); /* diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index be7dd3a1a8..b6f982ac63 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -5,7 +5,17 @@ #include +enum fsp_log_level { + FSP_LOG_LEVEL_DISABLE = 0, + FSP_LOG_LEVEL_ERR, + FSP_LOG_LEVEL_ERR_WARN, + FSP_LOG_LEVEL_ERR_WARN_INFO, + FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT, + FSP_LOG_LEVEL_VERBOSE +}; + /* FSP debug API */ +enum fsp_log_level fsp_map_console_log_level(void); void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 5b6318cb7c..fceebec7ed 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -10,26 +10,34 @@ #define FSP_HDR_ATTRIB_FSPT 1 #define FSP_HDR_ATTRIB_FSPM 2 #define FSP_HDR_ATTRIB_FSPS 3 +#define FSP_IMAGE_ID_LENGTH 8 #if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { - uint32_t fsp_revision; - uint32_t image_size; - uint32_t image_base; - uint16_t image_attribute; - uint8_t spec_version; - uint16_t component_attribute; - uint32_t cfg_region_offset; - uint32_t cfg_region_size; - uint32_t temp_ram_init_entry; - uint32_t temp_ram_exit_entry; - uint32_t notify_phase_entry_offset; - uint32_t memory_init_entry_offset; - uint32_t silicon_init_entry_offset; - uint32_t multi_phase_si_init_entry_offset; - char image_id[sizeof(uint64_t) + 1]; - uint8_t revision; -} __packed; + uint32_t signature; //FSPH + uint32_t header_length; + uint8_t res1[2]; + uint8_t spec_version; + uint8_t header_revision; + uint32_t image_revision; + char image_id[FSP_IMAGE_ID_LENGTH]; // not zero terminated + uint32_t image_size; + uint32_t image_base; + uint16_t image_attribute; + uint16_t component_attribute; + uint32_t cfg_region_offset; + uint32_t cfg_region_size; + uint32_t res2; + uint32_t temp_ram_init_entry_offset; //initial stack + uint32_t res3; + uint32_t notify_phase_entry_offset; + uint32_t fsp_memory_init_entry_offset; + uint32_t temp_ram_exit_entry_offset; + uint32_t fsp_silicon_init_entry_offset; + uint32_t fsp_multi_phase_si_init_entry_offset; + uint16_t extended_image_revision; + uint16_t res4; +} __packed; #else #error You need to implement this struct for x86_64 FSP #endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d05b644886..7347034550 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -60,6 +60,14 @@ union fsp_revision { } rev; }; +union extended_fsp_revision { + uint16_t val; + struct { + uint8_t bld_num; + uint8_t revision; + } rev; +}; + #if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0c9fe97188..b7e81f0915 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -36,7 +36,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) mrc_data = fsp_find_nv_storage_data(&mrc_data_size); if (!mrc_data) { - printk(BIOS_ERR, "ERROR: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + printk(BIOS_ERR, "FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); return; } @@ -48,7 +48,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) */ if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, mrc_data_size) < 0) - printk(BIOS_ERR, "ERROR: Failed to stash MRC data\n"); + printk(BIOS_ERR, "Failed to stash MRC data\n"); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -64,7 +64,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, range_entry_size(&fsp_mem))) { if (CONFIG(HAVE_ACPI_RESUME)) { - printk(BIOS_ERR, "ERROR: Failed to recover CBMEM in S3 resume.\n"); + printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ /* FIXME: A "system" reset is likely enough: */ full_reset(); @@ -206,7 +206,7 @@ uint8_t fsp_memory_soc_version(void) static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) { /* Use the full FSP version by default. */ - uint32_t ver = hdr->fsp_revision; + uint32_t ver = hdr->image_revision; if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) return ver; @@ -291,7 +291,7 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ - fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset); + fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); post_code(POST_FSP_MEMORY_INIT); @@ -309,9 +309,8 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { - printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); die_with_post_code(POST_RAM_FAILURE, - "FspMemoryInit returned an error!\n"); + "FspMemoryInit returned with error 0x%08x!\n", status); } do_fsp_post_memory_init(s3wake, fsp_version); @@ -340,6 +339,15 @@ static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unus return (void *)fspm_begin; } +void preload_fspm(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS); + cbfs_preload(CONFIG_FSP_M_CBFS); +} + void fsp_memory_init(bool s3wake) { struct range_entry prog_ranges[2]; diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 311ce46f19..30d61c971d 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -4,56 +4,91 @@ #include #include #include -#include #include +#include +#include + +struct fsp_notify_phase_data { + enum fsp_notify_phase notify_phase; + bool skip; + uint8_t post_code_before; + uint8_t post_code_after; + enum timestamp_id timestamp_before; + enum timestamp_id timestamp_after; +}; + +static const struct fsp_notify_phase_data notify_data[] = { + { + .notify_phase = AFTER_PCI_ENUM, + .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM), + .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE, + .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE, + .timestamp_before = TS_FSP_BEFORE_ENUMERATE, + .timestamp_after = TS_FSP_AFTER_ENUMERATE, + }, + { + .notify_phase = READY_TO_BOOT, + .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT), + .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE, + .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE, + .timestamp_before = TS_FSP_BEFORE_FINALIZE, + .timestamp_after = TS_FSP_AFTER_FINALIZE, + }, + { + .notify_phase = END_OF_FIRMWARE, + .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE), + .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, + .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, + .timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE, + .timestamp_after = TS_FSP_AFTER_END_OF_FIRMWARE, + }, +}; + +static const struct fsp_notify_phase_data *get_notify_phase_data(enum fsp_notify_phase phase) +{ + for (size_t i = 0; i < ARRAY_SIZE(notify_data); i++) { + if (notify_data[i].notify_phase == phase) + return ¬ify_data[i]; + } + die("Unknown FSP notify phase %u\n", phase); +} static void fsp_notify(enum fsp_notify_phase phase) { - uint32_t ret; - fsp_notify_fn fspnotify; + const struct fsp_notify_phase_data *data = get_notify_phase_data(phase); struct fsp_notify_params notify_params = { .phase = phase }; + fsp_notify_fn fspnotify; + uint32_t ret; + + if (data->skip) { + printk(BIOS_INFO, "coreboot skipped calling FSP notify phase: %08x.\n", phase); + return; + } if (!fsps_hdr.notify_phase_entry_offset) die("Notify_phase_entry_offset is zero!\n"); - fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base + + fspnotify = (void *)(uintptr_t)(fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); fsp_before_debug_notify(fspnotify, ¬ify_params); - if (phase == AFTER_PCI_ENUM) { - timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); - post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); - } else if (phase == READY_TO_BOOT) { - timestamp_add_now(TS_FSP_BEFORE_FINALIZE); - post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); - } else if (phase == END_OF_FIRMWARE) { - timestamp_add_now(TS_FSP_BEFORE_END_OF_FIRMWARE); - post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE); - } + timestamp_add_now(data->timestamp_before); + post_code(data->post_code_before); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)¬ify_params); else ret = fspnotify(¬ify_params); - if (phase == AFTER_PCI_ENUM) { - timestamp_add_now(TS_FSP_AFTER_ENUMERATE); - post_code(POST_FSP_NOTIFY_AFTER_ENUMERATE); - } else if (phase == READY_TO_BOOT) { - timestamp_add_now(TS_FSP_AFTER_FINALIZE); - post_code(POST_FSP_NOTIFY_AFTER_FINALIZE); - } else if (phase == END_OF_FIRMWARE) { - timestamp_add_now(TS_FSP_AFTER_END_OF_FIRMWARE); - post_code(POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE); - } + timestamp_add_now(data->timestamp_after); + post_code(data->post_code_after); + fsp_debug_after_notify(ret); /* Handle any errors returned by FspNotify */ fsp_handle_reset(ret); - if (ret != FSP_SUCCESS) { - printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", ret); - die("FspNotify returned an error!\n"); - } + if (ret != FSP_SUCCESS) + die("FspNotify returned with error 0x%08x!\n", ret); /* Allow the platform to run something after FspNotify */ platform_fsp_notify_status(phase); @@ -70,14 +105,10 @@ static void fsp_notify_dummy(void *arg) fsp_notify(END_OF_FIRMWARE); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, - (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, - (void *) READY_TO_BOOT); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, - (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, (void *)AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, (void *)READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, (void *)READY_TO_BOOT); -__weak void platform_fsp_notify_status( - enum fsp_notify_phase phase) +__weak void platform_fsp_notify_status(enum fsp_notify_phase phase) { } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b3e60c25c3..05cea11d55 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -75,7 +75,7 @@ static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint3 bool fsp_is_multi_phase_init_enabled(void) { return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && - (fsps_hdr.multi_phase_si_init_entry_offset != 0); + (fsps_hdr.fsp_multi_phase_si_init_entry_offset != 0); } static void fsp_fill_common_arch_params(FSPS_UPD *supd) @@ -127,7 +127,7 @@ static void do_silicon_init(struct fsp_header *hdr) /* Call SiliconInit */ silicon_init = (void *) (uintptr_t)(hdr->image_base + - hdr->silicon_init_entry_offset); + hdr->fsp_silicon_init_entry_offset); fsp_debug_before_silicon_init(silicon_init, supd, upd); timestamp_add_now(TS_FSP_SILICON_INIT_START); @@ -162,7 +162,7 @@ static void do_silicon_init(struct fsp_header *hdr) /* Call MultiPhaseSiInit */ multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base + - hdr->multi_phase_si_init_entry_offset); + hdr->fsp_multi_phase_si_init_entry_offset); /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */ if (multi_phase_si_init == NULL) @@ -230,6 +230,15 @@ void fsps_load(void) load_done = 1; } +void preload_fsps(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS); + cbfs_preload(CONFIG_FSP_S_CBFS); +} + void fsp_silicon_init(void) { timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 5d7cbd4ebb..87b77bcefa 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -25,14 +25,12 @@ static void fsp_temp_ram_exit(void) if (fsp_validate_component(&hdr, mapping, size) != CB_SUCCESS) die("Invalid FSPM header!\n"); - temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry_offset); printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); status = temp_ram_exit(NULL); - if (status != FSP_SUCCESS) { - printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); - die("TempRamExit returned an error!\n"); - } + if (status != FSP_SUCCESS) + die("TempRamExit returned with error 0x%08x!\n", status); cbfs_unmap(mapping); } diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 112801333f..2537b383ab 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -14,7 +14,9 @@ static uint32_t fsp_hdr_get_expected_min_length(void) { - if (CONFIG(PLATFORM_USES_FSP2_2)) + if (CONFIG(PLATFORM_USES_FSP2_3)) + return 80; + else if (CONFIG(PLATFORM_USES_FSP2_2)) return 76; else if (CONFIG(PLATFORM_USES_FSP2_1)) return 72; @@ -24,11 +26,9 @@ static uint32_t fsp_hdr_get_expected_min_length(void) return dead_code_t(uint32_t); } -static bool looks_like_fsp_header(const uint8_t *raw_hdr) +static bool looks_like_fsp_header(struct fsp_header *hdr) { - uint32_t fsp_header_length = read32(raw_hdr + 4); - - if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) { + if (memcmp(&hdr->signature, FSP_HDR_SIGNATURE, 4)) { printk(BIOS_ALERT, "Did not find a valid FSP signature\n"); return false; } @@ -37,8 +37,8 @@ static bool looks_like_fsp_header(const uint8_t *raw_hdr) fields in FSP_INFO_HEADER. The new fields will be ignored based on the reported FSP version. This check ensures that the reported header length is at least what the reported FSP version requires so that we do not access any out-of-bound bytes. */ - if (fsp_header_length < fsp_hdr_get_expected_min_length()) { - printk(BIOS_ALERT, "FSP header has invalid length: %d\n", fsp_header_length); + if (hdr->header_length < fsp_hdr_get_expected_min_length()) { + printk(BIOS_ALERT, "FSP header has invalid length: %d\n", hdr->header_length); return false; } @@ -47,30 +47,10 @@ static bool looks_like_fsp_header(const uint8_t *raw_hdr) enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) { - const uint8_t *raw_hdr = fsp_blob; - - if (!looks_like_fsp_header(raw_hdr)) + memcpy(hdr, fsp_blob, sizeof(struct fsp_header)); + if (!looks_like_fsp_header(hdr)) return CB_ERR; - hdr->spec_version = read8(raw_hdr + 10); - hdr->revision = read8(raw_hdr + 11); - hdr->fsp_revision = read32(raw_hdr + 12); - memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id)); - hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0'; - hdr->image_size = read32(raw_hdr + 24); - hdr->image_base = read32(raw_hdr + 28); - hdr->image_attribute = read16(raw_hdr + 32); - hdr->component_attribute = read16(raw_hdr + 34); - hdr->cfg_region_offset = read32(raw_hdr + 36); - hdr->cfg_region_size = read32(raw_hdr + 40); - hdr->temp_ram_init_entry = read32(raw_hdr + 48); - hdr->temp_ram_exit_entry = read32(raw_hdr + 64); - hdr->notify_phase_entry_offset = read32(raw_hdr + 56); - hdr->memory_init_entry_offset = read32(raw_hdr + 60); - hdr->silicon_init_entry_offset = read32(raw_hdr + 68); - if (CONFIG(PLATFORM_USES_FSP2_2)) - hdr->multi_phase_si_init_entry_offset = read32(raw_hdr + 72); - return CB_SUCCESS; } @@ -163,8 +143,8 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea if (!dest) return CB_ERR; - /* Don't allow FSP-M relocation. */ - if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) { + /* Don't allow FSP-M relocation when XIP. */ + if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) { printk(BIOS_ERR, "Unable to relocate FSP component!\n"); return CB_ERR; } @@ -188,7 +168,7 @@ void fsp_get_version(char *buf) struct fsp_header *hdr = &fsps_hdr; union fsp_revision revision; - revision.val = hdr->fsp_revision; + revision.val = hdr->image_revision; snprintf(buf, FSP_VER_LEN, "%u.%u-%u.%u.%u.%u", (hdr->spec_version >> 4), hdr->spec_version & 0xf, revision.rev.major, revision.rev.minor, revision.rev.revision, revision.rev.bld_num); diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 964d13e30c..5588e5af7b 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -8,6 +8,7 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c +ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y) # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ @@ -15,11 +16,10 @@ add_vbt_to_cbfs= \ $(eval $1-file := $2) \ $(eval $1-type := raw) \ $(eval $1-compression := lzma) - -ifeq ($(CONFIG_INTEL_GMA_ADD_VBT),y) -$(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) endif +$(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) + ifeq ($(CONFIG_GFX_GMA),y) $(call add-special-class,gfxinit) diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 79960e1586..739b91c859 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -9,7 +9,7 @@ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) If (LEqual (Local0, Ones)) { - Return (Subtract(SizeOf(BRIG), One)) + Return (SizeOf(BRIG) - 1) } Return (Local0) } @@ -40,9 +40,9 @@ Store (BRID (XBQC ()), Local0) If (LNotEqual (Local0, 2)) { - Decrement (Local0) + Local0-- } - XBCM (DerefOf (Index (BRIG, Local0))) + XBCM (DerefOf (BRIG[Local0])) } } @@ -56,10 +56,10 @@ Notify (LCD0, 0x86) } Else { Store (BRID (XBQC ()), Local0) - If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One))) + If (LNotEqual (Local0, SizeOf(BRIG) - 1)) { - Increment (Local0) + Local0++ } - XBCM (DerefOf (Index (BRIG, Local0))) + XBCM (DerefOf (BRIG[Local0])) } } diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 0ab93d803a..11d8fcd88a 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -53,7 +53,7 @@ /* Always keep BCLP up to date, even if driver is not ready. It requires a full 8-bit brightness value. 255 = 100% */ - Store (Divide (Multiply (Arg0, 255), 100), Local1) + Store (Arg0 * 255 / 100, Local1) If (LGreater(Local1, 255)) { Store (255, Local1) } @@ -83,7 +83,7 @@ Return (Ones) } } - Decrement (Local0) + Local0-- } Return (Ones) @@ -100,12 +100,12 @@ /* Divide round closest */ Method (DRCL, 2) { - Return (Divide (Add (Arg0, Divide (Arg1, 2)), Arg1)) + Return ((Arg0 + Arg1 / 2) / Arg1) } Method (XBCM, 1, NotSerialized) { - Store (DRCL (Multiply (Arg0, BCLM), 100), BCLV) + Store (DRCL (Arg0 * BCLM, 100), BCLV) } /* Find value closest to BCLV in BRIG (which must be ordered) */ @@ -117,26 +117,24 @@ Return (Zero) } /* Local0: current percentage */ - Store (DRCL (Multiply (BCLV, 100), BCLM), Local0) + Store (DRCL (BCLV * 100, BCLM), Local0) /* Local1: loop index (selectable values start at 2 in BRIG) */ Store (2, Local1) - While (LLess (Local1, Subtract (SizeOf (BRIG), 1))) { + While (LLess (Local1, SizeOf (BRIG) - 1)) { /* Local[23]: adjacent values in BRIG */ - Store (DeRefOf (Index (BRIG, Local1)), Local2) - Store (DeRefOf (Index (BRIG, Add (Local1, 1))), Local3) + Store (DeRefOf (BRIG[Local1]), Local2) + Store (DeRefOf (BRIG[Local1 + 1]), Local3) If (LLess (Local0, Local3)) { - If (LOr (LLess (Local0, Local2), - LLess (Subtract (Local0, Local2), - Subtract (Local3, Local0)))) { + If (LLess (Local0, Local2) || LLess (Local0 - Local2, Local3 - Local0)) { Return (Local2) } Else { Return (Local3) } } - Increment (Local1) + Local1++ } /* Didn't find greater/equal value: use the last */ diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index ec79e39a60..d846c813d8 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -5,7 +5,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -134,6 +136,15 @@ static void camera_fill_cio2(const struct device *dev) snprintf(name, sizeof(name), "port%u", i); port_name[i] = strdup(name); + if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) { + u32 cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_ALDERLAKE_A0 || cpu_id == CPUID_ALDERLAKE_A1 || + cpu_id == CPUID_ALDERLAKE_N_A0) + acpi_dp_add_integer(dsd, "is_es", 1); + else + acpi_dp_add_integer(dsd, "is_es", 0); + } + acpi_dp_add_child(dsd, port_name[i], port_table); } @@ -847,6 +858,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope) acpigen_write_name_integer("_UID", config->acpi_uid); acpigen_write_name_string("_DDN", config->chip_name); acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_method("_DSC", 0); + acpigen_write_return_integer(config->max_dstate_for_probe); + acpigen_pop_len(); /* Method _DSC */ /* Resources */ acpigen_write_name("_CRS"); diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index c6ead1ffd6..9d8291e4d5 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -12,7 +12,7 @@ #define MAX_LINK_FREQ_ENTRIES 4 #define MAX_CLK_CONFIGS 2 #define MAX_GPIO_CONFIGS 4 -#define MAX_PWR_OPS 5 +#define MAX_PWR_OPS 6 #define MAX_GUARDED_RESOURCES 10 #define IMGCLKOUT_0 0 #define IMGCLKOUT_1 1 @@ -257,6 +257,17 @@ struct drivers_intel_mipi_camera_config { bool has_power_resource; /* Perform low power probe */ bool low_power_probe; + /* + * This will create a _DSC method in ACPI which returns an integer, to tell the kernel + * the highest allowed D state for a device during probe + * Number State Description + * 0 D0 Device fully powered on + * 1 D1 + * 2 D2 + * 3 D3hot + * 4 D3cold Off + */ + uint8_t max_dstate_for_probe; }; #endif diff --git a/src/drivers/intel/pmc_mux/conn/chip.h b/src/drivers/intel/pmc_mux/conn/chip.h index 96347ae4a0..08a08e184d 100644 --- a/src/drivers/intel/pmc_mux/conn/chip.h +++ b/src/drivers/intel/pmc_mux/conn/chip.h @@ -6,10 +6,10 @@ #include struct drivers_intel_pmc_mux_conn_config { - /* 1-based port numbers (from SoC point of view) */ - int usb2_port_number; - /* 1-based port numbers (from SoC point of view) */ - int usb3_port_number; + /* A pointer to the SoC's USB-2 device */ + DEVTREE_CONST struct device *usb2_port; + /* A pointer to the SoC's USB-3 device */ + DEVTREE_CONST struct device *usb3_port; /* Orientation of the sideband signals (SBU) */ enum type_c_orientation sbu_orientation; /* Orientation of the High Speed lines */ diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index caff166392..de8f2be306 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -16,6 +16,11 @@ static void conn_init(struct device *dev) total_conn_count++; } +static unsigned int get_usb_port_number(const struct device *usb_port) +{ + return usb_port->path.usb.port_id + 1; +} + static struct type_c_info *conn_get_cbmem_buffer(void) { struct type_c_info *info; @@ -51,18 +56,18 @@ static void conn_write_cbmem_entry(struct device *dev) info = conn_get_cbmem_buffer(); if (!info || (info->port_count >= total_conn_count)) { - printk(BIOS_ERR, "ERROR: No space for Type-C port info!\n"); + printk(BIOS_ERR, "No space for Type-C port info!\n"); return; } count = info->port_count; port_info = &info->port_info[count]; - port_info->usb2_port_number = config->usb2_port_number; - port_info->usb3_port_number = config->usb3_port_number; + port_info->usb2_port_number = get_usb_port_number(config->usb2_port); + port_info->usb3_port_number = get_usb_port_number(config->usb3_port); port_info->sbu_orientation = config->sbu_orientation; port_info->data_orientation = config->hsl_orientation; - printk(BIOS_INFO, "added type-c port%ld info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n", + printk(BIOS_INFO, "added type-c port%zu info to cbmem: usb2:%d usb3:%d sbu:%d data:%d\n", count, port_info->usb2_port_number, port_info->usb3_port_number, port_info->sbu_orientation, port_info->data_orientation); @@ -109,8 +114,8 @@ static void conn_fill_ssdt(const struct device *dev) /* _DSD, Device-Specific Data */ dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_integer(dsd, "usb2-port-number", config->usb2_port_number); - acpi_dp_add_integer(dsd, "usb3-port-number", config->usb3_port_number); + acpi_dp_add_integer(dsd, "usb2-port-number", get_usb_port_number(config->usb2_port)); + acpi_dp_add_integer(dsd, "usb3-port-number", get_usb_port_number(config->usb3_port)); /* * The kernel assumes that these Type-C signals (SBUs and HSLs) follow the CC lines, @@ -161,8 +166,8 @@ bool intel_pmc_mux_conn_get_ports(const struct device *conn, unsigned int *usb2_ return false; mux_config = conn->chip_info; - *usb2_port = mux_config->usb2_port_number; - *usb3_port = mux_config->usb3_port_number; + *usb2_port = get_usb_port_number(mux_config->usb2_port); + *usb3_port = get_usb_port_number(mux_config->usb3_port); return true; }; diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index e54952598c..0c027eb968 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -341,6 +341,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) static char dfp[DEVICE_PATH_MAX]; struct acpi_pld pld; uint8_t dfp_port, usb_port; + int ec_port = 0; usb4_retimer_scope = acpi_device_scope(dev); if (!usb4_retimer_scope || !config) @@ -365,8 +366,14 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) usb_device = config->dfp[dfp_port].typec_port; usb_port = usb_device->path.usb.port_id; + ec_port = retimer_get_index_for_typec(usb_port); + if (ec_port == -1) { + printk(BIOS_ERR, "%s: No relative EC port found for TC port %d\n", + __func__, usb_port); + continue; + } /* DFPx */ - snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port); + snprintf(dfp, sizeof(dfp), "DFP%1d", ec_port); acpigen_write_device(dfp); /* _ADR part is for the lane adapter */ acpigen_write_ADR(dfp_port*2 + 1); @@ -396,7 +403,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); - usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID, + usb4_retimer_write_dsm(ec_port, INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->dfp[dfp_port].power_gpio); /* Default case: Return (Buffer (One) { 0x0 }) */ @@ -408,7 +415,7 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) acpigen_pop_len(); /* Host Router */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + printk(BIOS_INFO, "%s.HR: %s at %s\n", usb4_retimer_scope, dev->chip_ops->name, dev_path(dev)); } @@ -436,3 +443,20 @@ __weak const char *ec_retimer_fw_update_path(void) __weak void ec_retimer_fw_update(uint8_t data) { } + +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. + * For example, board might have enabled TCSS port 1 and 3 as per physical + * port mapping. Since only 2 TCSS ports are enabled EC will index it as port 0 + * and port 1. So there will be an issue when coreboot sends command to EC for + * port 3 (with coreboot index of 2). EC will produce an error due to wrong index. + * + * Note: Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +__weak int retimer_get_index_for_typec(uint8_t typec_port) +{ + /* By default assume that retimer port index = Type C port */ + return (int)typec_port; +} diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h index 5a040a0d47..ff87c19618 100644 --- a/src/drivers/intel/usb4/retimer/retimer.h +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -30,5 +30,15 @@ struct usb4_retimer_dsm_uuid { const char *ec_retimer_fw_update_path(void); void ec_retimer_fw_update(uint8_t data); +/* + * This function will convert CPU physical port mapping to abstract + * EC port mapping. For example, board might have enabled TCSS port 1 + * and 3 as per physical port mapping. Since only 2 TCSS ports are enabled + * EC will name it as port 0 and port 1. So there will be mismatch when + * coreboot sends index for port 3. + * Each SoC code using retimer driver needs to implement this function + * since SoC will have physical port details. + */ +int retimer_get_index_for_typec(uint8_t typec_port); #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 31ac6c0d9c..d26a9b752b 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -189,7 +189,7 @@ static enum cb_err read_fru_chassis_info_area(const int port, const uint8_t id, info->chassis_custom = malloc(info->custom_count * sizeof(char *)); if (!info->chassis_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %zu bytes for " "chassis custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; @@ -288,7 +288,7 @@ static enum cb_err read_fru_board_info_area(const int port, const uint8_t id, info->board_custom = malloc(info->custom_count * sizeof(char *)); if (!info->board_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %zu bytes for " "board custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; @@ -395,7 +395,7 @@ static enum cb_err read_fru_product_info_area(const int port, const uint8_t id, info->product_custom = malloc(info->custom_count * sizeof(char *)); if (!info->product_custom) { - printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + printk(BIOS_ERR, "%s failed to malloc %zu bytes for " "product custom data array.\n", __func__, info->custom_count * sizeof(char *)); ret = CB_ERR; diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index ff187663c9..4ffa91fe23 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -247,7 +247,7 @@ ipmi_write_acpi_tables(const struct device *dev, unsigned long current, break; default: printk(BIOS_ERR, "IPMI: Unsupported register spacing for SPMI\n"); - /* fall through */ + __fallthrough; case 1: addr.bit_offset = 8; break; @@ -369,7 +369,7 @@ static int ipmi_smbios_data(struct device *dev, int *handle, break; default: printk(BIOS_ERR, "IPMI: Unsupported register spacing for SMBIOS\n"); - /* fall through */ + __fallthrough; case 1: register_spacing = 0 << 6; break; diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index 60983b4568..d900272e38 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -111,7 +111,7 @@ struct fru_product_info { char *asset_tag; char *fru_file_id; char **product_custom; - int custom_count; /* Number of custom fields */ + size_t custom_count; /* Number of custom fields */ }; struct fru_board_info { @@ -121,7 +121,7 @@ struct fru_board_info { char *part_number; char *fru_file_id; char **board_custom; - int custom_count; + size_t custom_count; }; struct fru_chassis_info { @@ -129,7 +129,7 @@ struct fru_chassis_info { char *chassis_partnumber; char *serial_number; char **chassis_custom; - int custom_count; + size_t custom_count; }; struct fru_info_str { diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 841c97ea3d..473d78c9a2 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -255,7 +255,7 @@ static int mrc_cache_get_latest_slot_info(const char *name, /* No data to return. */ if (region_file_data(cache_file, rdev) < 0) { - printk(BIOS_ERR, "MRC: no data in '%s'\n", name); + printk(BIOS_NOTICE, "MRC: no data in '%s'\n", name); return fail_bad_data ? -1 : 0; } diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 97ad14091d..e44195c50f 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -30,7 +30,7 @@ static u8 get_hex_digit(const u8 c) ret = c - 'a' + 0x0a; } if (ret > 0x0f) { - printk(BIOS_ERR, "Error: Invalid hex digit found: " + printk(BIOS_ERR, "Invalid hex digit found: " "%c - 0x%02x\n", (char)c, c); ret = 0; } @@ -106,7 +106,7 @@ static int atl1e_eeprom_exist(u32 mem_base) static void atl1e_init(struct device *dev) { /* Get the resource of the NIC mmio */ - struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct resource *nic_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (nic_res == NULL) { printk(BIOS_ERR, "atl1e: resource not found\n"); diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 9b6a4e550b..f253cae005 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -8,6 +8,11 @@ struct drivers_net_config { uint16_t customized_leds; + /* RTL8125 LED settings */ + uint8_t led_feature; + uint16_t customized_led0; + uint16_t customized_led2; + unsigned int wake; /* Wake pin for ACPI _PRW */ /* Does the device have a power resource? */ @@ -26,6 +31,9 @@ struct drivers_net_config { * the device number is and the valid range is [1-10]. */ uint8_t device_index; + + /* Allow kernel driver to enable ASPM L1.2. */ + bool enable_aspm_l1_2; }; #endif /* __DRIVERS_R8168_CHIP_H__ */ diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 971f31dd83..83d4ccfb22 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -84,7 +84,7 @@ static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); while (cnt--) { - outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); } /* #warning "Add timeout" @@ -307,7 +307,6 @@ static void read_resources(struct device *dev) res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - return; } static struct device_operations ne2k_ops = { diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 18e2aff7c5..3432249f8a 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -28,10 +29,15 @@ #define CMD_REG 0x37 #define CMD_REG_RESET 0x10 #define CMD_LED0_LED1 0x18 +#define CMD_LED_FEATURE 0x94 +#define CMD_LEDSEL0 0x18 +#define CMD_LEDSEL2 0x84 #define CFG_9346 0x50 #define CFG_9346_LOCK 0x00 #define CFG_9346_UNLOCK 0xc0 +#define CMD_REG_ASPM 0xb0 +#define ASPM_L1_2_MASK 0xe059000f #define DEVICE_INDEX_BYTE 12 #define MAX_DEVICE_SUPPORT 10 @@ -72,7 +78,7 @@ static u8 get_hex_digit(const u8 c) ret = c - 'a' + 0x0a; } if (ret > 0x0f) { - printk(BIOS_ERR, "Error: Invalid hex digit found: " + printk(BIOS_ERR, "Invalid hex digit found: " "%c - 0x%02x\n", (char)c, c); ret = 0; } @@ -90,7 +96,7 @@ static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) size_t offset; if (fmap_locate_area_as_rdev("RO_VPD", &rdev)) { - printk(BIOS_ERR, "Error: Couldn't find RO_VPD region."); + printk(BIOS_ERR, "Couldn't find RO_VPD region."); return CB_ERR; } search_address = rdev_mmap_full(&rdev); @@ -104,8 +110,7 @@ static enum cb_err fetch_mac_vpd_key(u8 *macstrbuf, const char *vpd_key) search_length); if (offset == search_length) { - printk(BIOS_ERR, - "Error: Could not locate '%s' in VPD\n", vpd_key); + printk(BIOS_ERR, "Could not locate '%s' in VPD\n", vpd_key); rdev_munmap(&rdev, search_address); return CB_ERR; } @@ -241,6 +246,20 @@ static void program_mac_address(struct device *dev, u16 io_base) printk(BIOS_DEBUG, "done\n"); } +static void enable_aspm_l1_2(u16 io_base) +{ + printk(BIOS_INFO, "rtl: Enable ASPM L1.2\n"); + + /* Disable register protection */ + outb(CFG_9346_UNLOCK, io_base + CFG_9346); + + /* Enable ASPM_L1.2 */ + outl(ASPM_L1_2_MASK, io_base + CMD_REG_ASPM); + + /* Lock config regs */ + outb(CFG_9346_LOCK, io_base + CFG_9346); +} + static void r8168_set_customized_led(struct device *dev, u16 io_base) { struct drivers_net_config *config = dev->chip_info; @@ -248,28 +267,69 @@ static void r8168_set_customized_led(struct device *dev, u16 io_base) if (!config) return; - /* Read the customized LED setting from devicetree */ - printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + if (dev->device == PCI_DEVICE_ID_REALTEK_8125) { + /* Set LED global Feature register */ + outb(config->led_feature, io_base + CMD_LED_FEATURE); + printk(BIOS_DEBUG, "r8125: read back LED global feature setting as 0x%x\n", + inb(io_base + CMD_LED_FEATURE)); - /* - * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration - * Starting from offset 0x18 - * Bit[15:12] LED Feature Control(FC) - * Bit[11:08] LED Select for PINLED2 - * Bit[07:04] LED Select for PINLED1 - * Bit[03:00] LED Select for PINLED0 - * - * Speed Link10M Link100M Link1000M ACT/Full - * LED0 Bit0 Bit1 Bit2 Bit3 - * LED1 Bit4 Bit5 Bit6 Bit7 - * LED2 Bit8 Bit9 Bit10 Bit11 - * FC Bit12 Bit13 Bit14 Bit15 - */ + /* + * Refer to RTL8125 datasheet 5.Customizable LED Configuration + * Register Name IO Address + * LEDSEL0 0x18 + * LEDSEL2 0x84 + * LEDFEATURE 0x94 + * + * LEDSEL Bit[] Description + * Bit0 Link10M + * Bit1 Link100M + * Bit3 Link1000M + * Bit5 Link2.5G + * Bit9 ACT + * Bit10 preboot enable + * Bit11 lp enable + * Bit12 active low/high + * + * LEDFEATURE Description + * Bit0 LED Table V1/V2 + * Bit1~3 Reserved + * Bit4~5 LED Blinking Duty Cycle 12.5%/ 25%/ 50%/ 75% + * Bit6~7 LED Blinking Freq. 240ms/160ms/80ms/Link-Speed-Dependent + */ - /* Set customized LED registers */ - outw(config->customized_leds, io_base + CMD_LED0_LED1); - printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", - inw(io_base + CMD_LED0_LED1)); + /* Set customized LED0 register */ + outw(config->customized_led0, io_base + CMD_LEDSEL0); + printk(BIOS_DEBUG, "r8125: read back LED0 setting as 0x%x\n", + inw(io_base + CMD_LEDSEL0)); + + /* Set customized LED2 register */ + outw(config->customized_led2, io_base + CMD_LEDSEL2); + printk(BIOS_DEBUG, "r8125: read back LED2 setting as 0x%x\n", + inw(io_base + CMD_LEDSEL2)); + } else { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + + /* + * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration + * Starting from offset 0x18 + * Bit[15:12] LED Feature Control(FC) + * Bit[11:08] LED Select for PINLED2 + * Bit[07:04] LED Select for PINLED1 + * Bit[03:00] LED Select for PINLED0 + * + * Speed Link10M Link100M Link1000M ACT/Full + * LED0 Bit0 Bit1 Bit2 Bit3 + * LED1 Bit4 Bit5 Bit6 Bit7 + * LED2 Bit8 Bit9 Bit10 Bit11 + * FC Bit12 Bit13 Bit14 Bit15 + */ + + /* Set customized LED registers */ + outw(config->customized_leds, io_base + CMD_LED0_LED1); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LED0_LED1)); + } } static void r8168_init(struct device *dev) @@ -294,6 +354,10 @@ static void r8168_init(struct device *dev) /* Program customized LED mode */ if (CONFIG(RT8168_SET_LED_MODE)) r8168_set_customized_led(dev, io_base); + + struct drivers_net_config *config = dev->chip_info; + if (CONFIG(PCIEXP_ASPM) && config->enable_aspm_l1_2) + enable_aspm_l1_2(io_base); } #if CONFIG(HAVE_ACPI_TABLES) @@ -360,10 +424,16 @@ static struct device_operations r8168_ops = { #endif }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_REALTEK_8168, + PCI_DEVICE_ID_REALTEK_8125, + 0 +}; + static const struct pci_driver r8168_driver __pci_driver = { .ops = &r8168_ops, - .vendor = 0x10ec, - .device = 0x8168, + .vendor = PCI_VENDOR_ID_REALTEK, + .devices = pci_device_ids, }; struct chip_operations drivers_net_ops = { diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index 93121f2094..587eae1d9c 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -5,7 +5,7 @@ #include #include #include - +#include #include "ps8640.h" int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out) @@ -80,3 +80,101 @@ int ps8640_init(uint8_t bus, uint8_t chip) return 0; } + +static cb_err_t ps8640_bridge_aux_request(uint8_t bus, + uint8_t chip, + unsigned int target_reg, + unsigned int total_size, + enum aux_request request, + uint8_t *data) +{ + int i; + uint32_t length; + uint8_t buf; + uint8_t reg; + int ret; + + if (target_reg & ~SWAUX_ADDR_MASK) + return CB_ERR; + + while (total_size) { + length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES); + total_size -= length; + + ret = i2c_writeb(bus, chip, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); + if (ret) + return CB_ERR; + + enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size); + if (i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_23_16, + (target_reg >> 16) | (cmd << 4)) || + i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_15_8, target_reg >> 8) || + i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_7_0, target_reg)) { + return CB_ERR; + } + + if (dp_aux_request_is_write(request)) { + reg = PAGE0_SWAUX_WDATA; + for (i = 0; i < length; i++) { + ret = i2c_writeb(bus, chip, reg++, *data++); + if (ret) + return CB_ERR; + } + } else { + if (length == 0) + i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, SWAUX_NO_PAYLOAD); + else + i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, length - 1); + } + + ret = i2c_writeb(bus, chip, PAGE0_SWAUX_CTRL, SWAUX_SEND); + if (ret) + return CB_ERR; + + if (!wait_ms(100, !i2c_readb(bus, chip, PAGE0_SWAUX_CTRL, &buf) && + !(buf & SWAUX_SEND))) + return CB_ERR; + + if (i2c_readb(bus, chip, PAGE0_SWAUX_STATUS, &buf)) + return CB_ERR; + + switch (buf & SWAUX_STATUS_MASK) { + case SWAUX_STATUS_NACK: + case SWAUX_STATUS_I2C_NACK: + case SWAUX_STATUS_INVALID: + case SWAUX_STATUS_TIMEOUT: + return CB_ERR; + case SWAUX_STATUS_ACKM: + length = buf & SWAUX_M_MASK; + break; + } + + if (length && !dp_aux_request_is_write(request)) { + reg = PAGE0_SWAUX_RDATA; + for (i = 0; i < length; i++) { + if (i2c_readb(bus, chip, reg++, &buf)) + return CB_ERR; + *data++ = buf; + } + } + } + + return CB_SUCCESS; +} + +void ps8640_backlight_enable(uint8_t bus, uint8_t chip) +{ + uint8_t val; + + val = DP_BACKLIGHT_CONTROL_MODE_DPCD; + ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1, + DPCD_WRITE, &val); + + val = 0xff; + ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1, + DPCD_WRITE, &val); + + val = DP_BACKLIGHT_ENABLE; + ps8640_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1, + DPCD_WRITE, &val); +} diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index 06daad4e3a..fb78be6bd7 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -24,11 +24,33 @@ enum { }; enum { - EDID_LENGTH = 128, - EDID_I2C_ADDR = 0x50, - EDID_EXTENSION_FLAG = 0x7e, + PAGE0_AUXCH_CFG3 = 0x76, + AUXCH_CFG3_RESET = 0xff, + PAGE0_SWAUX_ADDR_7_0 = 0x7d, + PAGE0_SWAUX_ADDR_15_8 = 0x7e, + PAGE0_SWAUX_ADDR_23_16 = 0x7f, + SWAUX_ADDR_MASK = 0xfffff, + PAGE0_SWAUX_LENGTH = 0x80, + SWAUX_LENGTH_MASK = 0xf, + SWAUX_NO_PAYLOAD = BIT(7), + PAGE0_SWAUX_WDATA = 0x81, + PAGE0_SWAUX_RDATA = 0x82, + PAGE0_SWAUX_CTRL = 0x83, + SWAUX_SEND = BIT(0), + PAGE0_SWAUX_STATUS = 0x84, + SWAUX_M_MASK = 0x1f, + SWAUX_STATUS_MASK = (0x7 << 5), + SWAUX_STATUS_NACK = (0x1 << 5), + SWAUX_STATUS_DEFER = (0x2 << 5), + SWAUX_STATUS_ACKM = (0x3 << 5), + SWAUX_STATUS_INVALID = (0x4 << 5), + SWAUX_STATUS_I2C_NACK = (0x5 << 5), + SWAUX_STATUS_I2C_DEFER = (0x6 << 5), + SWAUX_STATUS_TIMEOUT = (0x7 << 5), }; int ps8640_init(uint8_t bus, uint8_t chip); int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out); +void ps8640_backlight_enable(uint8_t bus, uint8_t chip); + #endif diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 1474b57057..e8e2345133 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -100,7 +100,7 @@ static enum cb_err cmos_get_uint_option(unsigned int *dest, const char *name) } if (ce->config != 'e' && ce->config != 'h') { - printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name); + printk(BIOS_ERR, "CMOS option '%s' is not of integer type.\n", name); return CB_ERR_ARG; } @@ -176,7 +176,7 @@ static enum cb_err cmos_set_uint_option(const char *name, unsigned int *value) } if (ce->config != 'e' && ce->config != 'h') { - printk(BIOS_ERR, "ERROR: CMOS option '%s' is not of integer type.\n", name); + printk(BIOS_ERR, "CMOS option '%s' is not of integer type.\n", name); return CB_ERR_ARG; } diff --git a/src/drivers/pcie/generic/Kconfig b/src/drivers/pcie/generic/Kconfig new file mode 100644 index 0000000000..2a68708f61 --- /dev/null +++ b/src/drivers/pcie/generic/Kconfig @@ -0,0 +1,11 @@ +config DRIVERS_PCIE_GENERIC + bool + default n + depends on HAVE_ACPI_TABLES + help + This driver allows attaching arbitrary ACPI properties to + arbitrary PCI root ports or devices. Currently it supports one + property, "UntrustedDevice". This property indicates to the + operating system that the PCIe device may be considered + untrusted, and appropriate policies, e.g. IOMMU isolation, + should take place. diff --git a/src/drivers/pcie/generic/Makefile.inc b/src/drivers/pcie/generic/Makefile.inc new file mode 100644 index 0000000000..f634f256a8 --- /dev/null +++ b/src/drivers/pcie/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_PCIE_GENERIC) += generic.c diff --git a/src/drivers/pcie/generic/chip.h b/src/drivers/pcie/generic/chip.h new file mode 100644 index 0000000000..3be57de530 --- /dev/null +++ b/src/drivers/pcie/generic/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _PCIE_GENERIC_H_ +#define _PCIE_GENERIC_H_ + +#include + +struct drivers_pcie_generic_config { + bool is_untrusted; +}; + +#endif /* _PCIE_GENERIC_H_ */ diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c new file mode 100644 index 0000000000..2daebdae04 --- /dev/null +++ b/src/drivers/pcie/generic/generic.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "chip.h" + +static const char *pcie_generic_acpi_name(const struct device *dev) +{ + return "DEV0"; +} + +static void pcie_generic_fill_ssdt(const struct device *dev) +{ + struct drivers_pcie_generic_config *config; + struct acpi_dp *dsd; + + if (!is_dev_enabled(dev)) + return; + + pci_rom_ssdt(dev); + + config = dev->chip_info; + if (!config || !config->is_untrusted || !dev->bus || !dev->bus->dev) + return; + + const char *scope = acpi_device_path(dev->bus->dev); + const char *name = acpi_device_name(dev); + + acpigen_write_scope(scope); + acpigen_write_device(name); + acpigen_write_ADR_pci_device(dev); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "UntrustedDevice", 1); + acpi_dp_write(dsd); + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + printk(BIOS_INFO, "%s.%s: Enable ACPI properties for %s (%s)\n", scope, name, + dev_path(dev), dev->chip_ops->name); +} + +struct device_operations pcie_generic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, + .acpi_name = pcie_generic_acpi_name, + .acpi_fill_ssdt = pcie_generic_fill_ssdt, +}; + +static void pcie_generic_enable(struct device *dev) +{ + dev->ops = &pcie_generic_ops; +} + +struct chip_operations drivers_pcie_generic_ops = { + CHIP_NAME("PCIe Device") + .enable_dev = pcie_generic_enable +}; diff --git a/src/drivers/siemens/nc_fpga/Kconfig b/src/drivers/siemens/nc_fpga/Kconfig index 1cd797772f..f4f1e972ef 100644 --- a/src/drivers/siemens/nc_fpga/Kconfig +++ b/src/drivers/siemens/nc_fpga/Kconfig @@ -5,3 +5,8 @@ config DRIVER_SIEMENS_NC_FPGA config NC_FPGA_NOTIFY_CB_READY bool default n + +config NC_FPGA_POST_CODE + bool + default n + select EARLY_PCI_BRIDGE diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc index ac2875f52f..95ec00aedc 100644 --- a/src/drivers/siemens/nc_fpga/Makefile.inc +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -1,3 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c + +all-$(CONFIG_NC_FPGA_POST_CODE) += nc_fpga_early.c + +ifeq ($(CONFIG_NC_FPGA_POST_CODE),y) +CPPFLAGS_common += -I$(src)/drivers/siemens/nc_fpga +endif diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 08e88565c1..0b4c7d47ea 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -142,9 +142,21 @@ static void set_fw_done(void *unused) BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_fw_done, NULL); #endif +static void nc_fpga_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + if (CONFIG(NC_FPGA_POST_CODE)) { + /* Re-initialize base address after set_resources for POST display + to work properly.*/ + nc_fpga_remap(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf); + } +} + + static struct device_operations nc_fpga_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = nc_fpga_set_resources, .enable_resources = pci_dev_enable_resources, .init = nc_fpga_init, }; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index 2096de79b7..39cc04e993 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -17,6 +17,7 @@ #define NC_DIAG_FW_DONE 0x10000 #define NC_BL_BRIGHTNESS_OFFSET 0x88 #define NC_BL_PWM_OFFSET 0x8C +#define NC_FPGA_POST_OFFSET 0xE0 #define NC_FANMON_CTRL_OFFSET 0x400 #define MAX_NUM_SENSORS 8 @@ -58,4 +59,7 @@ typedef struct { uint32_t fanmon; } __packed fan_ctrl_t; +void nc_fpga_post(uint8_t value); +void nc_fpga_remap(uint32_t new_mmio); + #endif /* _SIEMENS_NC_FPGA_H_ */ diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c new file mode 100644 index 0000000000..6ec0349922 --- /dev/null +++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "nc_fpga.h" + +static DEVTREE_CONST uint32_t fpga_bar = CONFIG_EARLY_PCI_MMIO_BASE; +static bool nc_fpga_present = false; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0); + uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID); + + if (id != (0x4091 << 16 | PCI_VENDOR_ID_SIEMENS)) + return -1; + + /* Setup base address for BAR0. */ + pci_s_write_config32(pci_dev, PCI_BASE_ADDRESS_0, mmio_base); + /* Enable memory access for pci_dev. */ + u16 reg16 = pci_s_read_config16(pci_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_s_write_config16(pci_dev, PCI_COMMAND, reg16); + nc_fpga_present = true; + + return 0; +} + +void nc_fpga_remap(uint32_t new_mmio) +{ +#if ENV_RAMSTAGE + fpga_bar = new_mmio; +#endif +} + +void nc_fpga_post(uint8_t value) +{ + /* The function pci_earyl_device_probe is called in bootblock and romstage. Make sure + that in these stages the initialization code was successful before the POST code + value is written to the register. */ + if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && nc_fpga_present == false) + return; + write32((void *)(fpga_bar + NC_FPGA_POST_OFFSET), value); +} diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 13b7312242..3e20e3e66d 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -19,27 +19,10 @@ config SMMSTORE_V2 By using version 2 you cannot make use of software that expects a version 1 SMMSTORE. -config SMMSTORE_IN_CBFS - bool - default n - help - Select this if you want to add an SMMSTORE region to a - cbfsfile in a cbfs FMAP region - if SMMSTORE -config SMMSTORE_REGION - string "fmap region in which SMM store file is kept" if SMMSTORE_IN_CBFS - default "RW_LEGACY" if CHROMEOS && SMMSTORE_IN_CBFS - default "COREBOOT" if SMMSTORE_IN_CBFS - default "SMMSTORE" - -config SMMSTORE_FILENAME - string "SMM store file name" if SMMSTORE_IN_CBFS - default "smm_store" config SMMSTORE_SIZE hex "size of the SMMSTORE FMAP region" - depends on !SMMSTORE_IN_CBFS default 0x40000 help Sets the size of the default SMMSTORE FMAP region. diff --git a/src/drivers/smmstore/Makefile.inc b/src/drivers/smmstore/Makefile.inc index 90bcdece9d..6d9a9d6a2f 100644 --- a/src/drivers/smmstore/Makefile.inc +++ b/src/drivers/smmstore/Makefile.inc @@ -1,4 +1,9 @@ ramstage-$(CONFIG_SMMSTORE) += store.c + +ifeq ($(CONFIG_SMMSTORE),y) +$(call src-to-obj,ramstage,$(dir)/store.c) : $(obj)/fmap_config.h +$(call src-to-obj,smm,$(dir)/store.c) : $(obj)/fmap_config.h +endif ramstage-$(CONFIG_SMMSTORE_V2) += ramstage.c smm-$(CONFIG_SMMSTORE) += store.c smi.c diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index a12cd58e10..6ba3f53695 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -1,14 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include +#include #include #include #include #include #include +#define SMMSTORE_REGION "SMMSTORE" + + +_Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START, SMM_BLOCK_SIZE), + "SMMSTORE FMAP region not aligned to 64K"); + +_Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, + "SMMSTORE FMAP region must be at least 64K"); + /* * The region format is still not finalized, but so far it looks like this: * ( @@ -33,26 +42,11 @@ static enum cb_err lookup_store_region(struct region *region) { - if (CONFIG(SMMSTORE_IN_CBFS)) { - struct cbfsf file; - if (cbfs_locate_file_in_region(&file, - CONFIG_SMMSTORE_REGION, - CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store file in region '%s'\n", - CONFIG_SMMSTORE_REGION); - return CB_ERR; - } - struct region_device rdev; - cbfs_file_data(&rdev, &file); - *region = *region_device_region(&rdev); - } else { - if (fmap_locate_area(CONFIG_SMMSTORE_REGION, region)) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store FMAP region '%s'\n", - CONFIG_SMMSTORE_REGION); - return CB_ERR; - } + if (fmap_locate_area(SMMSTORE_REGION, region)) { + printk(BIOS_WARNING, + "smm store: Unable to find SMM store FMAP region '%s'\n", + SMMSTORE_REGION); + return CB_ERR; } return CB_SUCCESS; diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 13a73b8df2..b7650dd31d 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -162,6 +162,17 @@ config SPI_FLASH_HAS_VOLATILE_GROUP Allows chipset to group write/erase operations under a single volatile group. +config SPI_FLASH_EXIT_4_BYTE_ADDR_MODE + bool + default n + help + This will send an Exit 4-Byte Address Mode (E9h) command before the first + access to the SPI flash. On some platforms with SPI flashes larger than 32MB, + the SPI flash may power up in 4-byte addressing mode and this command needs + to be sent before coreboot's 3-byte address commands can be interpreted correctly. + On flashes that don't support 4-byte addressing mode or where it is already + disabled, this command should be a no-op. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 116daf9088..e6ec7bd8d5 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -98,8 +98,18 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len, if (deduct_opcode_len) cmd_len--; - if (deduct_cmd_len && (ctrlr_max > cmd_len)) - ctrlr_max -= cmd_len; + /* Subtract command length from useable buffer size. If + deduct_opcode_len is set, only subtract the number command bytes + after the opcode. If the adjusted cmd_len is larger than ctrlr_max + return 0 to inidicate an error. */ + if (deduct_cmd_len) { + if (ctrlr_max >= cmd_len) { + ctrlr_max -= cmd_len; + } else { + ctrlr_max = 0; + printk(BIOS_WARNING, "%s: Command longer than buffer\n", __func__); + } + } return MIN(ctrlr_max, buf_len); } diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f3cecd5fc6..ded88eda09 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -515,6 +515,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) " CONFIG_ROM_SIZE 0x%x!!\n", flash->size, CONFIG_ROM_SIZE); } + + if (CONFIG(SPI_FLASH_EXIT_4_BYTE_ADDR_MODE) && ENV_INITIAL_STAGE) + spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); + return 0; } diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 4a7beeab3e..e3883112ee 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -22,6 +22,8 @@ #define CMD_BLOCK_ERASE 0xD8 +#define CMD_EXIT_4BYTE_ADDR_MODE 0xe9 + /* Common status */ #define STATUS_WIP 0x01 diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c index 99c6aace25..1fe83f66e7 100644 --- a/src/drivers/spi/spiconsole.c +++ b/src/drivers/spi/spiconsole.c @@ -9,7 +9,6 @@ static struct spi_slave slave; void spiconsole_init(void) { spi_init(); spi_setup_slave(0, 0, &slave); - return; } /* @@ -49,6 +48,4 @@ void spiconsole_tx_byte(unsigned char c) { msg.header.msg_length = 0; } - - return; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 30b18761ef..9c7baa9d3a 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -74,7 +74,7 @@ __weak int tis_plat_irq_status(void) static int warning_displayed; if (!warning_displayed) { - printk(BIOS_WARNING, "WARNING: %s() not implemented, wasting 10ms to wait on" + printk(BIOS_WARNING, "%s() not implemented, wasting 10ms to wait on" " Cr50!\n", __func__); warning_displayed = 1; } @@ -492,7 +492,7 @@ static void cr50_set_board_cfg(void) /* The high bit is set, meaning that the Cr50 is already locked on a particular * value for the register, but not the one we wanted. */ printk(BIOS_ERR, - "ERROR: Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", + "Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", board_cfg_value, CR50_BOARD_CFG_VALUE); return; } diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 2ba0977547..2130e33ccf 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include +#include #include #include #include @@ -31,14 +31,6 @@ #define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ #define DP_LANE_COUNT_MASK 0xf -/* Backlight configuration */ -#define DP_BACKLIGHT_MODE_SET 0x721 -#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3 -#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2 -#define DP_DISPLAY_CONTROL_REGISTER 0x720 -#define DP_BACKLIGHT_ENABLE 0x1 -#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722 - /* link configuration */ #define DP_LINK_BW_SET 0x100 #define DP_LINK_BW_1_62 0x06 @@ -132,17 +124,6 @@ enum vstream_config { VSTREAM_ENABLE = 1, }; -enum i2c_over_aux { - I2C_OVER_AUX_WRITE_MOT_0 = 0x0, - I2C_OVER_AUX_READ_MOT_0 = 0x1, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, - I2C_OVER_AUX_WRITE_MOT_1 = 0x4, - I2C_OVER_AUX_READ_MOT_1 = 0x5, - I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, - NATIVE_AUX_WRITE = 0x8, - NATIVE_AUX_READ = 0x9, -}; - enum aux_cmd_status { NAT_I2C_FAIL = 1 << 6, AUX_SHORT = 1 << 5, @@ -166,21 +147,6 @@ enum ml_tx_mode { REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb, }; -enum aux_request { - DPCD_READ, - DPCD_WRITE, - I2C_RAW_READ, - I2C_RAW_WRITE, - I2C_RAW_READ_AND_STOP, - I2C_RAW_WRITE_AND_STOP, -}; - -enum { - EDID_LENGTH = 128, - EDID_I2C_ADDR = 0x50, - EDID_EXTENSION_FLAG = 0x7e, -}; - /* * LUT index corresponds to register value and LUT values corresponds * to dp data rate supported by the bridge in Mbps unit. @@ -189,41 +155,6 @@ static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = { 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -static bool request_is_write(enum aux_request request) -{ - switch (request) { - case I2C_RAW_WRITE_AND_STOP: - case I2C_RAW_WRITE: - case DPCD_WRITE: - return true; - default: - return false; - } -} - -static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this) -{ - switch (request) { - case I2C_RAW_WRITE_AND_STOP: - if (!remaining_after_this) - return I2C_OVER_AUX_WRITE_MOT_0; - /* fallthrough */ - case I2C_RAW_WRITE: - return I2C_OVER_AUX_WRITE_MOT_1; - case I2C_RAW_READ_AND_STOP: - if (!remaining_after_this) - return I2C_OVER_AUX_READ_MOT_0; - /* fallthrough */ - case I2C_RAW_READ: - return I2C_OVER_AUX_READ_MOT_1; - case DPCD_WRITE: - return NATIVE_AUX_WRITE; - case DPCD_READ: - default: - return NATIVE_AUX_READ; - } -} - static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, uint8_t chip, unsigned int target_reg, @@ -241,10 +172,10 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT); while (total_size) { - length = MIN(total_size, 16); + length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES); total_size -= length; - enum i2c_over_aux cmd = get_aux_cmd(request, total_size); + enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size); if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) || i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) || i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) || @@ -252,7 +183,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length)) return CB_ERR; - if (request_is_write(request)) { + if (dp_aux_request_is_write(request)) { reg = SN_AUX_WDATA_REG_0; for (i = 0; i < length; i++) if (i2c_writeb(bus, chip, reg++, *data++)) @@ -263,17 +194,17 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus, return CB_ERR; if (!wait_ms(100, !i2c_readb(bus, chip, SN_AUX_CMD_REG, &buf) && !(buf & AUX_CMD_SEND))) { - printk(BIOS_ERR, "ERROR: AUX_CMD_SEND not acknowledged\n"); + printk(BIOS_ERR, "AUX_CMD_SEND not acknowledged\n"); return CB_ERR; } if (i2c_readb(bus, chip, SN_AUX_CMD_STATUS_REG, &buf)) return CB_ERR; if (buf & (NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT)) { - printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", buf); + printk(BIOS_ERR, "AUX command failed, status = %#x\n", buf); return CB_ERR; } - if (!request_is_write(request)) { + if (!dp_aux_request_is_write(request)) { reg = SN_AUX_RDATA_REG_0; for (i = 0; i < length; i++) { if (i2c_readb(bus, chip, reg++, &buf)) @@ -299,7 +230,7 @@ cb_err_t sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) err = sn65dsi86_bridge_aux_request(bus, chip, EDID_I2C_ADDR, EDID_LENGTH, I2C_RAW_READ_AND_STOP, edid); if (err) { - printk(BIOS_ERR, "ERROR: Failed to read EDID.\n"); + printk(BIOS_ERR, "Failed to read EDID.\n"); return err; } @@ -318,7 +249,7 @@ cb_err_t sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out) } if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { - printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + printk(BIOS_ERR, "Failed to decode EDID.\n"); return CB_ERR; } @@ -370,13 +301,13 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate default: printk(BIOS_ERR, "Unexpected max rate (%#x); assuming 5.4 GHz\n", (int)dpcd_val); - /* fall through */ + __fallthrough; case DP_LINK_BW_5_4: rate_valid[7] = 1; - /* fall through */ + __fallthrough; case DP_LINK_BW_2_7: rate_valid[4] = 1; - /* fall through */ + __fallthrough; case DP_LINK_BW_1_62: rate_valid[1] = 1; break; @@ -433,7 +364,7 @@ static void sn65dsi86_bridge_set_dp_clock_range(uint8_t bus, uint8_t chip, if (dp_rate_idx < ARRAY_SIZE(sn65dsi86_bridge_dp_rate_lut)) i2c_write_field(bus, chip, SN_DATARATE_CONFIG_REG, dp_rate_idx, 8, 5); else - printk(BIOS_ERR, "ERROR: valid dp rate not found"); + printk(BIOS_ERR, "valid dp rate not found"); } static void sn65dsi86_bridge_set_bridge_active_timing(uint8_t bus, @@ -476,7 +407,7 @@ static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip) if (!wait_ms(500, !(i2c_readb(bus, chip, SN_DPPLL_SRC_REG, &buf)) && (buf & BIT(7)))) { - printk(BIOS_ERR, "ERROR: PLL lock failure\n"); + printk(BIOS_ERR, "PLL lock failure\n"); } /* @@ -495,14 +426,14 @@ static void sn65dsi86_bridge_link_training(uint8_t bus, uint8_t chip) if (!wait_ms(500, !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && (buf == NORMAL_MODE || buf == MAIN_LINK_OFF))) { - printk(BIOS_ERR, "ERROR: unexpected link training state: %#x\n", buf); + printk(BIOS_ERR, "unexpected link training state: %#x\n", buf); return; } if (buf == NORMAL_MODE) return; } - printk(BIOS_ERR, "ERROR: Link training failed 10 times\n"); + printk(BIOS_ERR, "Link training failed 10 times\n"); } void sn65dsi86_backlight_enable(uint8_t bus, uint8_t chip) diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c index 88dd649954..6b02d45247 100644 --- a/src/drivers/tpm/ppi.c +++ b/src/drivers/tpm/ppi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c index 1e3a7fcb27..23236ff555 100644 --- a/src/drivers/tpm/ppi_stub.c +++ b/src/drivers/tpm/ppi_stub.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 41b870fbf7..beba4012e2 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -5,7 +5,7 @@ config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. bool "Serial port on SuperIO" - depends on ARCH_X86 + depends on ARCH_X86 || ARCH_PPC64 default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 8ba39efc6d..59e8ff2840 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h index 28dc21caa4..35a6845554 100644 --- a/src/drivers/uart/uart8250reg.h +++ b/src/drivers/uart/uart8250reg.h @@ -3,16 +3,18 @@ #ifndef UART8250REG_H #define UART8250REG_H +#include + /* Data */ #define UART8250_RBR 0x00 #define UART8250_TBR 0x00 /* Control */ #define UART8250_IER 0x01 -#define UART8250_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART8250_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART8250_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART8250_IER_RDI 0x01 /* Enable receiver data interrupt */ +#define UART8250_IER_MSI BIT(3) /* Enable Modem status interrupt */ +#define UART8250_IER_RLSI BIT(2) /* Enable receiver line status interrupt */ +#define UART8250_IER_THRI BIT(1) /* Enable Transmitter holding register int. */ +#define UART8250_IER_RDI BIT(0) /* Enable receiver data interrupt */ #define UART8250_IIR 0x02 #define UART8250_IIR_NO_INT 0x01 /* No interrupts pending */ @@ -24,18 +26,15 @@ #define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART8250_FCR 0x02 -#define UART8250_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART8250_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART8250_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART8250_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ - -#define UART8250_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART8250_FCR_TXSR 0x04 /* Transmitter soft reset */ +#define UART8250_FCR_FIFO_EN BIT(0) /* Fifo enable */ +#define UART8250_FCR_CLEAR_RCVR BIT(1) /* Clear the RCVR FIFO */ +#define UART8250_FCR_CLEAR_XMIT BIT(2) /* Clear the XMIT FIFO */ +#define UART8250_FCR_DMA_SELECT BIT(3) /* For DMA applications */ +#define UART8250_FCR_TRIGGER_MASK (3 << 6) /* Mask for the FIFO trigger range */ +#define UART8250_FCR_TRIGGER_1 (0 << 6) /* Mask for trigger set at 1 */ +#define UART8250_FCR_TRIGGER_4 (1 << 6) /* Mask for trigger set at 4 */ +#define UART8250_FCR_TRIGGER_8 (2 << 6) /* Mask for trigger set at 8 */ +#define UART8250_FCR_TRIGGER_14 (3 << 6) /* Mask for trigger set at 14 */ #define UART8250_LCR 0x03 #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ @@ -43,20 +42,19 @@ #define UART8250_LCR_WLS_6 0x01 /* 6 bit character length */ #define UART8250_LCR_WLS_7 0x02 /* 7 bit character length */ #define UART8250_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART8250_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART8250_LCR_PEN 0x08 /* Parity enable */ -#define UART8250_LCR_EPS 0x10 /* Even Parity Select */ -#define UART8250_LCR_STKP 0x20 /* Stick Parity */ -#define UART8250_LCR_SBRK 0x40 /* Set Break */ -#define UART8250_LCR_BKSE 0x80 /* Bank select enable */ -#define UART8250_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART8250_LCR_STB BIT(2) /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART8250_LCR_PEN BIT(3) /* Parity enable */ +#define UART8250_LCR_EPS BIT(4) /* Even Parity Select */ +#define UART8250_LCR_STKP BIT(5) /* Stick Parity */ +#define UART8250_LCR_SBRK BIT(6) /* Set Break */ +#define UART8250_LCR_DLAB BIT(7) /* Divisor latch access bit */ #define UART8250_MCR 0x04 -#define UART8250_MCR_DTR 0x01 /* DTR */ -#define UART8250_MCR_RTS 0x02 /* RTS */ -#define UART8250_MCR_OUT1 0x04 /* Out 1 */ -#define UART8250_MCR_OUT2 0x08 /* Out 2 */ -#define UART8250_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART8250_MCR_DTR BIT(0) /* DTR */ +#define UART8250_MCR_RTS BIT(1) /* RTS */ +#define UART8250_MCR_OUT1 BIT(2) /* Out 1 */ +#define UART8250_MCR_OUT2 BIT(3) /* Out 2 */ +#define UART8250_MCR_LOOP BIT(4) /* Enable loopback test mode */ #define UART8250_MCR_DMA_EN 0x04 #define UART8250_MCR_TX_DFR 0x08 @@ -66,24 +64,24 @@ /* Status */ #define UART8250_LSR 0x05 -#define UART8250_LSR_DR 0x01 /* Data ready */ -#define UART8250_LSR_OE 0x02 /* Overrun */ -#define UART8250_LSR_PE 0x04 /* Parity error */ -#define UART8250_LSR_FE 0x08 /* Framing error */ -#define UART8250_LSR_BI 0x10 /* Break */ -#define UART8250_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART8250_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART8250_LSR_ERR 0x80 /* Error */ +#define UART8250_LSR_DR BIT(0) /* Data ready */ +#define UART8250_LSR_OE BIT(1) /* Overrun */ +#define UART8250_LSR_PE BIT(2) /* Parity error */ +#define UART8250_LSR_FE BIT(3) /* Framing error */ +#define UART8250_LSR_BI BIT(4) /* Break */ +#define UART8250_LSR_THRE BIT(5) /* Xmit holding register empty */ +#define UART8250_LSR_TEMT BIT(6) /* Xmitter empty */ +#define UART8250_LSR_ERR BIT(7) /* Error */ #define UART8250_MSR 0x06 -#define UART8250_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART8250_MSR_RI 0x40 /* Ring Indicator */ -#define UART8250_MSR_DSR 0x20 /* Data Set Ready */ -#define UART8250_MSR_CTS 0x10 /* Clear to Send */ -#define UART8250_MSR_DDCD 0x08 /* Delta DCD */ -#define UART8250_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART8250_MSR_DDSR 0x02 /* Delta DSR */ -#define UART8250_MSR_DCTS 0x01 /* Delta CTS */ +#define UART8250_MSR_DCD BIT(7) /* Data Carrier Detect */ +#define UART8250_MSR_RI BIT(6) /* Ring Indicator */ +#define UART8250_MSR_DSR BIT(5) /* Data Set Ready */ +#define UART8250_MSR_CTS BIT(4) /* Clear to Send */ +#define UART8250_MSR_DDCD BIT(3) /* Delta DCD */ +#define UART8250_MSR_TERI BIT(2) /* Trailing edge ring indicator */ +#define UART8250_MSR_DDSR BIT(1) /* Delta DSR */ +#define UART8250_MSR_DCTS BIT(0) /* Delta CTS */ #define UART8250_SCR 0x07 #define UART8250_SPR 0x07 diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index d59ca32504..8e854264a2 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -75,7 +75,7 @@ static void pci_ehci_set_resources(struct device *dev) if (ehci_drv_ops->set_resources) ehci_drv_ops->set_resources(dev); - res = find_resource(dev, EHCI_BAR_INDEX); + res = probe_resource(dev, EHCI_BAR_INDEX); if (!res) return; diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index a099b3be37..396097c9d9 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -67,7 +67,7 @@ static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev) /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ if (rdev_readat(rdev, &info, 0, sizeof(info)) != sizeof(info)) { - printk(BIOS_ERR, "ERROR: Failed to read %s header.\n", + printk(BIOS_ERR, "Failed to read %s header.\n", fmap_name); goto fail; } @@ -75,13 +75,13 @@ static void init_vpd_rdev(const char *fmap_name, struct region_device *rdev) if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) == 0) { if (rdev_chain(rdev, rdev, sizeof(info), info.size)) { - printk(BIOS_ERR, "ERROR: %s info size too large.\n", + printk(BIOS_ERR, "%s info size too large.\n", fmap_name); goto fail; } } else if (info.header.tlv.type == VPD_TYPE_TERMINATOR || info.header.tlv.type == VPD_TYPE_IMPLICIT_TERMINATOR) { - printk(BIOS_WARNING, "WARNING: %s is uninitialized or empty.\n", + printk(BIOS_WARNING, "%s is uninitialized or empty.\n", fmap_name); goto fail; } @@ -151,7 +151,7 @@ static void cbmem_add_cros_vpd(int is_recovery) if (ro_size) { if (rdev_readat(&ro_vpd, cbmem->blob, 0, ro_size) != ro_size) { - printk(BIOS_ERR, "ERROR: Couldn't read RO VPD\n"); + printk(BIOS_ERR, "Couldn't read RO VPD\n"); cbmem->ro_size = ro_size = 0; } timestamp_add_now(TS_END_COPYVPD_RO); @@ -160,7 +160,7 @@ static void cbmem_add_cros_vpd(int is_recovery) if (rw_size) { if (rdev_readat(&rw_vpd, cbmem->blob + ro_size, 0, rw_size) != rw_size) { - printk(BIOS_ERR, "ERROR: Couldn't read RW VPD\n"); + printk(BIOS_ERR, "Couldn't read RW VPD\n"); cbmem->rw_size = rw_size = 0; } timestamp_add_now(TS_END_COPYVPD_RW); diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 11fc0e084f..7c606f9099 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -26,6 +26,9 @@ /* Unique ID for the WIFI _DSM */ #define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" +/* Unique ID for the Wifi _DSD */ +#define ACPI_DSD_UNTRUSTED_UUID "88566a92-1a61-466d-949a-6d12809d480c" + __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { return -1; @@ -209,7 +212,7 @@ static void sar_emit_wrds(const struct sar_profile *sar) * }) */ if (sar->revision > MAX_SAR_REVISION) { - printk(BIOS_ERR, "ERROR: Invalid SAR table revision: %d\n", sar->revision); + printk(BIOS_ERR, "Invalid SAR table revision: %d\n", sar->revision); return; } @@ -255,12 +258,12 @@ static void sar_emit_ewrd(const struct sar_profile *sar) * }) */ if (sar->revision > MAX_SAR_REVISION) { - printk(BIOS_ERR, "ERROR: Invalid SAR table revision: %d\n", sar->revision); + printk(BIOS_ERR, "Invalid SAR table revision: %d\n", sar->revision); return; } if (sar->dsar_set_count == 0) { - printk(BIOS_WARNING, "WARNING: DSAR set count is 0\n"); + printk(BIOS_WARNING, "DSAR set count is 0\n"); return; } @@ -273,7 +276,7 @@ static void sar_emit_ewrd(const struct sar_profile *sar) * Emit 'Domain Type' + 'Dynamic SAR Enable' + 'Extended SAR sets count' * + number of bytes for Set#2 & 3 & 4 */ - package_size = 1 + 1 + 1 + table_size * sar->dsar_set_count; + package_size = 1 + 1 + 1 + table_size * MAX_DSAR_SET_COUNT; acpigen_write_package(package_size); acpigen_write_dword(DOMAIN_TYPE_WIFI); acpigen_write_dword(1); @@ -338,7 +341,7 @@ static void sar_emit_wgds(struct geo_profile *wgds) * }) */ if (wgds->revision > MAX_GEO_OFFSET_REVISION) { - printk(BIOS_ERR, "ERROR: Invalid WGDS revision: %d\n", wgds->revision); + printk(BIOS_ERR, "Invalid WGDS revision: %d\n", wgds->revision); return; } @@ -472,7 +475,7 @@ static void emit_sar_acpi_structures(const struct device *dev) /* Retrieve the sar limits data */ if (get_wifi_sar_limits(&sar_limits) < 0) { - printk(BIOS_ERR, "ERROR: failed getting SAR limits!\n"); + printk(BIOS_ERR, "failed getting SAR limits!\n"); return; } @@ -508,10 +511,22 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco /* Scope */ acpigen_write_scope(scope); - /* Wake capabilities */ - if (config) + if (config) { + /* Wake capabilities */ acpigen_write_PRW(config->wake, ACPI_S3); + /* Add _DSD for UntrustedDevice property. */ + if (config->is_untrusted) { + struct acpi_dp *dsd, *pkg; + + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(ACPI_DSD_UNTRUSTED_UUID); + acpi_dp_add_integer(pkg, "UntrustedDevice", 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + } + } + /* Fill regulatory domain structure */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) { /* diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index e3b0ba5698..35726f2171 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -9,6 +9,9 @@ */ struct drivers_wifi_generic_config { unsigned int wake; + /* When set to true, this will add a _DSD which contains a single + property, `UntrustedDevice`, set to 1, to the ACPI Device. */ + bool is_untrusted; }; #endif /* _GENERIC_WIFI_H_ */ diff --git a/src/drivers/wifi/generic/smbios.c b/src/drivers/wifi/generic/smbios.c index db22de9793..9c83df655e 100644 --- a/src/drivers/wifi/generic/smbios.c +++ b/src/drivers/wifi/generic/smbios.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "wifi_private.h" diff --git a/src/drivers/wwan/fm/Kconfig b/src/drivers/wwan/fm/Kconfig new file mode 100644 index 0000000000..bed3b2e5ac --- /dev/null +++ b/src/drivers/wwan/fm/Kconfig @@ -0,0 +1,11 @@ +config DRIVERS_WWAN_FM350GL + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + help + This driver is for Fibocom FM350-GL PCIe 5G WWAN. + When enabled, this driver will add support for ACPI controlled + WWAN using GPIOs for power/reset control of the device. + This driver depends on rtd3 driver code to build as it needs to + point to the rtd3 chip on the same parent for the methods provided + only for the same root port. diff --git a/src/drivers/wwan/fm/Makefile.inc b/src/drivers/wwan/fm/Makefile.inc new file mode 100644 index 0000000000..8074a0869a --- /dev/null +++ b/src/drivers/wwan/fm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_WWAN_FM350GL) += acpi_fm350gl.c diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c new file mode 100644 index 0000000000..67bd4a14e6 --- /dev/null +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include "chip.h" +#include "soc/intel/common/block/pcie/rtd3/chip.h" + +/* FCPO# to RESET# delay time during WWAN ON */ +#define FM350GL_TN2B 20 +/* RESET# to PERST# delay time during WWAN ON */ +#define FM350GL_TB2R 80 +/* The delay between de-assertion of PERST# to change of PDS state from 0 to 1 during WWAN ON */ +#define FM350GL_TR2P 0 +/* RESET# to FCPO# delay time during WWAN OFF */ +#define FM350GL_TB2F 10 +/* Time to allow the WWAN module to fully discharge any residual voltages before FCPO# could be + de-asserted again. */ +#define FM350GL_TFDI 500 +/* The delay between assertion and de-assertion RESET# during FLDR */ +#define FM350GL_TBTG 10 +/* The delay between de-assertion of RESET# and change of PDS state from 0 to 1 after FLDR */ +#define FM350GL_TBTP 170 +/* PERST# to RESET# delay time during WWAN OFF */ +#define FM350GL_TR2B 10 +/* 20s HW initialization needed after de-assertion of PERST# + However, it is not required and is not proper place to ensure HW initialization in ACPI. The + delay here is to ensure the following reset or RTD3 _OFF method won't be called immediately. + */ +#define FM350GL_TIME_HW_INIT 100 + +enum reset_type { + RESET_TYPE_WARM = 0, + RESET_TYPE_COLD = 1 +}; + +/* + * Returns the RTD3 PM methods requested and available to the device. + */ +static enum acpi_pcie_rp_pm_emit +wwan_fm350gl_get_rtd3_method_support(const struct drivers_wwan_fm_config *config) +{ + const struct soc_intel_common_block_pcie_rtd3_config *rtd3_config; + + rtd3_config = config_of(config->rtd3dev); + + return rtd3_config->ext_pm_support; +} + +/* + * Generate first half reset flow (FHRF) method. + * Arg0 = RESET_TYPE_WARM: warm reset + * Arg0 = 1RESET_TYPE_COLD: cold reset + */ +static void wwan_fm350gl_acpi_method_fhrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("FHRF", 1); + { + /* LOCAL0 = PERST# */ + acpigen_get_tx_gpio(&config->perst_gpio); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); + { + if (wwan_fm350gl_get_rtd3_method_support(config) & + ACPI_PCIE_RP_EMIT_L23) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "DL23")); + } + /* assert PERST# pin */ + acpigen_enable_tx_gpio(&config->perst_gpio); + } + acpigen_write_if_end(); /* If */ + acpigen_write_sleep(FM350GL_TR2B); + /* assert RESET# pin */ + acpigen_enable_tx_gpio(&config->reset_gpio); + /* warm reset */ + acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_WARM); + { + acpigen_write_sleep(FM350GL_TBTG); + } + /* cold reset */ + acpigen_write_else(); + { + acpigen_write_if_lequal_op_int(ARG0_OP, RESET_TYPE_COLD); + { + /* disable source clock */ + if (wwan_fm350gl_get_rtd3_method_support(config) & + ACPI_PCIE_RP_EMIT_SRCK) { + acpigen_emit_namestring(acpi_device_path_join( + parent_dev, "SRCK")); + acpigen_emit_byte(ZERO_OP); + } + acpigen_write_sleep(FM350GL_TB2F); + /* assert FCPO# pin */ + acpigen_enable_tx_gpio(&config->fcpo_gpio); + acpigen_write_sleep(FM350GL_TFDI); + } + acpigen_write_if_end(); /* If */ + } + acpigen_pop_len(); /* Else */ + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate second half reset flow (SHRF) method. + */ +static void wwan_fm350gl_acpi_method_shrf(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("SHRF", 0); + { + /* call rtd3 method to Disable ModPHY Power Gating. */ + if (wwan_fm350gl_get_rtd3_method_support(config) & + ACPI_PCIE_RP_EMIT_PSD0) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "PSD0")); + } + /* call rtd3 method to Enable SRC Clock. */ + if (wwan_fm350gl_get_rtd3_method_support(config) & + ACPI_PCIE_RP_EMIT_SRCK) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "SRCK")); + acpigen_emit_byte(ONE_OP); + } + /* De-assert FCPO# GPIO. */ + acpigen_disable_tx_gpio(&config->fcpo_gpio); + acpigen_write_sleep(FM350GL_TN2B); + /* De-assert RESET# GPIO. */ + acpigen_disable_tx_gpio(&config->reset_gpio); + acpigen_write_sleep(FM350GL_TB2R); + /* De-assert PERST# GPIO. */ + acpigen_disable_tx_gpio(&config->perst_gpio); + /* Call rtd3 method to trigger L2/L3 ready exit flow in root port */ + if (wwan_fm350gl_get_rtd3_method_support(config) & + ACPI_PCIE_RP_EMIT_L23) { + acpigen_emit_namestring(acpi_device_path_join(parent_dev, + "L23D")); + } + acpigen_write_sleep(FM350GL_TIME_HW_INIT); + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate _RST method. This is to perform a soft reset. It is added under + * PXSX. This is called during device driver removal. + */ +static void wwan_fm350gl_acpi_method_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + { + /* Perform 1st Half of FLDR Flow for soft reset: FHRF(0) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(RESET_TYPE_WARM); + /* Perform 2nd Half of FLDR Flow: SHRF() */ + acpigen_emit_namestring("SHRF"); + /* Indicates that the following _Off will be skipped. */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "RTD3.OFSK")); + } + acpigen_write_method_end(); /* Method */ +} + +/* + * Generate _RST method. This is to perform a cold reset. This reset will be + * included under PXSX.MRST. This method is used during device firmware update. + */ +static void wwan_fm350gl_acpi_method_mrst_rst(const struct device *parent_dev, + const struct drivers_wwan_fm_config *config) +{ + acpigen_write_method_serialized("_RST", 0); + { + /* Perform 1st Half of FLDR Flow for cold reset: FHRF (1) */ + acpigen_emit_namestring("FHRF"); + acpigen_emit_byte(RESET_TYPE_COLD); + /* Perform 2nd Half of FLDR Flow: SHRF () */ + acpigen_emit_namestring("SHRF"); + /* Indicate kernel ACPI PM to skip _off RTD3 after reset at the end of + driver removal */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(acpi_device_path_join(parent_dev, "RTD3.OFSK")); + } + acpigen_write_method_end(); /* Method */ +} + +static const char *wwan_fm350gl_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static void wwan_fm350gl_acpi_fill_ssdt(const struct device *dev) +{ + const struct drivers_wwan_fm_config *config = config_of(dev); + const struct device *parent = dev->bus->dev; + const char *scope = acpi_device_path(parent); + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->fcpo_gpio.pin_count && !config->reset_gpio.pin_count && + !config->perst_gpio.pin_count) { + printk(BIOS_ERR, "%s: FCPO, RESET, PERST GPIO required for %s.\n", + __func__, scope); + return; + } + printk(BIOS_INFO, "%s: Enable WWAN for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + acpigen_write_scope(scope); + { + acpigen_write_device(wwan_fm350gl_acpi_name(dev)); + { + acpigen_write_ADR(0); + if (config->name) + acpigen_write_name_string("_DDN", config->name); + if (config->desc) + acpigen_write_name_unicode("_STR", config->desc); + wwan_fm350gl_acpi_method_fhrf(parent, config); + wwan_fm350gl_acpi_method_shrf(parent, config); + wwan_fm350gl_acpi_method_rst(parent, config); + /* NOTE: the 5G driver will call MRST._RST to trigger a cold reset + * during firmware update. + */ + acpigen_write_device("MRST"); + { + acpigen_write_ADR(0); + wwan_fm350gl_acpi_method_mrst_rst(parent, config); + } + acpigen_write_device_end(); /* Device */ + } + acpigen_write_device_end(); /* Device */ + } + acpigen_write_scope_end(); /* Scope */ +} + +static struct device_operations wwan_fm350gl_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = wwan_fm350gl_acpi_fill_ssdt, + .acpi_name = wwan_fm350gl_acpi_name, +}; + +static void wwan_fm350gl_acpi_enable(struct device *dev) +{ + dev->ops = &wwan_fm350gl_ops; +} + +struct chip_operations drivers_wwan_fm_ops = { + CHIP_NAME("Fibocom FM-350-GL") + .enable_dev = wwan_fm350gl_acpi_enable +}; diff --git a/src/drivers/wwan/fm/chip.h b/src/drivers/wwan/fm/chip.h new file mode 100644 index 0000000000..635178bd16 --- /dev/null +++ b/src/drivers/wwan/fm/chip.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_WWAN_FM_CHIP_H__ +#define __DRIVERS_WWAN_FM_CHIP_H__ + +struct drivers_wwan_fm_config { + const char *name; + const char *desc; + /* GPIO used for FULL_CARD_POWER_OFF# */ + struct acpi_gpio fcpo_gpio; + + /* GPIO used for RESET# */ + struct acpi_gpio reset_gpio; + + /* GPIO used for PERST# */ + struct acpi_gpio perst_gpio; + + /* GPIO used for wake */ + struct acpi_gpio wake_gpio; + + /* Pointer to the corresponding RTD3 */ + DEVTREE_CONST struct device *rtd3dev; +}; + +#endif /* __DRIVERS_WWAN_FM_CHIP_H__ */ diff --git a/src/ec/apple/acpi/battery.asl b/src/ec/apple/acpi/battery.asl index 291451f414..6d4ab57c63 100644 --- a/src/ec/apple/acpi/battery.asl +++ b/src/ec/apple/acpi/battery.asl @@ -91,13 +91,13 @@ Device(BAT0) Method(_BIF, 0, NotSerialized) { - Index(BATS, 0x01) = ^^SBRW(0x0B, 0x18) * 10 - Index(BATS, 0x02) = ^^SBRW(0x0B, 0x10) * 10 + BATS[1] = ^^SBRW(0x0B, 0x18) * 10 + BATS[2] = ^^SBRW(0x0B, 0x10) * 10 - Index(BATS, 0x04) = ^^SBRW(0x0B, 0x19) - Index(BATS, 0x09) = ^^SBRB(0x0B, 0x21) - Index(BATS, 0x0B) = ^^SBRB(0x0B, 0x22) - Index(BATS, 0x0C) = ^^SBRB(0x0B, 0x20) + BATS[4] = ^^SBRW(0x0B, 0x19) + BATS[9] = ^^SBRB(0x0B, 0x21) + BATS[11] = ^^SBRB(0x0B, 0x22) + BATS[12] = ^^SBRB(0x0B, 0x20) Return(BATS) } @@ -124,7 +124,7 @@ Device(BAT0) } Local1 = ^^SBRW(0x0B, 0x09) - Index(BATI, 0x03) = Local1 + BATI[3] = Local1 Local0 = ^^SBRW(0x0B, 0x0A) /* Sign-extend Local0. */ @@ -136,16 +136,16 @@ Device(BAT0) } Local0 *= Local1 - Index(BATI, 1) = Local0 / 1000 - Index(BATI, 2) = ^^SBRW(0x0B, 0x0F) * 10 + BATI[1] = Local0 / 1000 + BATI[2] = ^^SBRW(0x0B, 0x0F) * 10 If (HPAC) { If (!(^^SBRW(0x0B, 0x16) & 0x40)) { - Index(BATI, 0) = 2 + BATI[0] = 2 } Else { - Index(BATI, 0) = 0 + BATI[0] = 0 } } Else { - Index(BATI, 0) = 1 + BATI[0] = 1 } Return(BATI) diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index eb0b5ff5ad..6389383b21 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -113,7 +113,6 @@ static void ene932_init(struct device *dev) printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); pc_keyboard_init(NO_AUX_DEVICE); - } static struct device_operations ops = { diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index d9304c13b7..ce4462debf 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -22,7 +22,7 @@ Method (BTSW, 1) While (LNotEqual (BTIX, Arg0)) { Sleep (1) - Decrement (Local0) + Local0-- If (LEqual (Local0, Zero)) { Return (One) @@ -68,27 +68,27 @@ Method (BBIF, 2, Serialized) Return (Arg1) } // Last Full Charge Capacity - Store (BTDF, Index (Arg1, 2)) + Store (BTDF, Arg1[2]) // Design Voltage - Store (BTDV, Index (Arg1, 4)) + Store (BTDV, Arg1[4]) // Design Capacity Store (BTDA, Local0) - Store (Local0, Index (Arg1, 1)) + Store (Local0, Arg1[1]) // Design Capacity of Warning - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (Arg1, 5)) + Divide (Local0 * DWRN, 100, , Local2) + Store (Local2, Arg1[5]) // Design Capacity of Low - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (Arg1, 6)) + Divide (Local0 * DLOW, 100, , Local2) + Store (Local2, Arg1[6]) // Get battery info from mainboard - Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 9)) - Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 10)) - Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 12)) + Store (ToString(Concatenate(BMOD, 0x00)), Arg1[9]) + Store (ToString(Concatenate(BSER, 0x00)), Arg1[10]) + Store (ToString(Concatenate(BMFG, 0x00)), Arg1[12]) Release (^BATM) Return (Arg1) @@ -108,30 +108,30 @@ Method (BBIX, 2, Serialized) Return (Arg1) } // Last Full Charge Capacity - Store (BTDF, Index (Arg1, 3)) + Store (BTDF, Arg1[3]) // Design Voltage - Store (BTDV, Index (Arg1, 5)) + Store (BTDV, Arg1[5]) // Design Capacity Store (BTDA, Local0) - Store (Local0, Index (Arg1, 2)) + Store (Local0, Arg1[2]) // Design Capacity of Warning - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (Arg1, 6)) + Divide (Local0 * DWRN, 100, , Local2) + Store (Local2, Arg1[6]) // Design Capacity of Low - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (Arg1, 7)) + Divide (Local0 * DLOW, 100, , Local2) + Store (Local2, Arg1[7]) // Cycle Count - Store (BTCC, Index (Arg1, 8)) + Store (BTCC, Arg1[8]) // Get battery info from mainboard - Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 16)) - Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 17)) - Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 19)) + Store (ToString(Concatenate(BMOD, 0x00)), Arg1[16]) + Store (ToString(Concatenate(BSER, 0x00)), Arg1[17]) + Store (ToString(Concatenate(BMFG, 0x00)), Arg1[19]) Release (^BATM) Return (Arg1) @@ -177,7 +177,7 @@ Method (BBST, 4, Serialized) If (BFCR) { Or (Local1, 0x04, Local1) } - Store (Local1, Index (Arg1, 0)) + Store (Local1, Arg1[0]) // Notify if battery state has changed since last time If (LNotEqual (Local1, DeRefOf (Arg2))) { @@ -195,13 +195,13 @@ Method (BBST, 4, Serialized) // // 1: BATTERY PRESENT RATE // - Store (BTPR, Index (Arg1, 1)) + Store (BTPR, Arg1[1]) // // 2: BATTERY REMAINING CAPACITY // Store (BTRA, Local1) - If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) { + If (Arg3 && ACEX && !(BFDC && BFCG)) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. @@ -210,18 +210,17 @@ Method (BBST, 4, Serialized) // See if within ~6% of full ShiftRight (Local2, 4, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + If (LGreater (Local1, Local2 - Local3) && LLess (Local1, Local2 + Local3)) { Store (Local2, Local1) } } - Store (Local1, Index (Arg1, 2)) + Store (Local1, Arg1[2]) // // 3: BATTERY PRESENT VOLTAGE // - Store (BTVO, Index (Arg1, 3)) + Store (BTVO, Arg1[3]) Release (^BATM) Return (Arg1) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 7b1a66391c..69d608b65c 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -198,7 +198,7 @@ Device (EC0) } /* Adjust by offset to get Kelvin */ - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS /* Convert to 1/10 Kelvin */ Multiply (Local0, 10, Local0) @@ -209,7 +209,7 @@ Device (EC0) // Lid Closed Event Method (_Q01, 0, NotSerialized) { - Store ("EC: LID CLOSE", Debug) + Printf ("EC: LID CLOSE") Store (LIDS, \LIDS) #ifdef EC_ENABLE_LID_SWITCH Notify (LID0, 0x80) @@ -219,7 +219,7 @@ Device (EC0) // Lid Open Event Method (_Q02, 0, NotSerialized) { - Store ("EC: LID OPEN", Debug) + Printf ("EC: LID OPEN") Store (LIDS, \LIDS) Notify (CREC, 0x2) #ifdef EC_ENABLE_LID_SWITCH @@ -230,13 +230,13 @@ Device (EC0) // Power Button Method (_Q03, 0, NotSerialized) { - Store ("EC: POWER BUTTON", Debug) + Printf ("EC: POWER BUTTON") } // AC Connected Method (_Q04, 0, NotSerialized) { - Store ("EC: AC CONNECTED", Debug) + Printf ("EC: AC CONNECTED") Store (ACEX, \PWRS) Notify (AC, 0x80) #ifdef DPTF_ENABLE_CHARGER @@ -250,7 +250,7 @@ Device (EC0) // AC Disconnected Method (_Q05, 0, NotSerialized) { - Store ("EC: AC DISCONNECTED", Debug) + Printf ("EC: AC DISCONNECTED") Store (ACEX, \PWRS) Notify (AC, 0x80) #ifdef DPTF_ENABLE_CHARGER @@ -264,21 +264,21 @@ Device (EC0) // Battery Low Event Method (_Q06, 0, NotSerialized) { - Store ("EC: BATTERY LOW", Debug) + Printf ("EC: BATTERY LOW") Notify (BAT0, 0x80) } // Battery Critical Event Method (_Q07, 0, NotSerialized) { - Store ("EC: BATTERY CRITICAL", Debug) + Printf ("EC: BATTERY CRITICAL") Notify (BAT0, 0x80) } // Battery Info Event Method (_Q08, 0, NotSerialized) { - Store ("EC: BATTERY INFO", Debug) + Printf ("EC: BATTERY INFO") Notify (BAT0, 0x81) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE If (CondRefOf (BAT1)) { @@ -290,41 +290,41 @@ Device (EC0) // Thermal Overload Event Method (_Q0A, 0, NotSerialized) { - Store ("EC: THERMAL OVERLOAD", Debug) + Printf ("EC: THERMAL OVERLOAD") Notify (\_TZ, 0x80) } // Thermal Event Method (_Q0B, 0, NotSerialized) { - Store ("EC: THERMAL", Debug) + Printf ("EC: THERMAL") Notify (\_TZ, 0x80) } // USB Charger Method (_Q0C, 0, NotSerialized) { - Store ("EC: USB CHARGER", Debug) + Printf ("EC: USB CHARGER") } // Key Pressed Method (_Q0D, 0, NotSerialized) { - Store ("EC: KEY PRESSED", Debug) + Printf ("EC: KEY PRESSED") Notify (CREC, 0x2) } // Thermal Shutdown Imminent Method (_Q10, 0, NotSerialized) { - Store ("EC: THERMAL SHUTDOWN", Debug) + Printf ("EC: THERMAL SHUTDOWN") Notify (\_TZ, 0x80) } // Battery Shutdown Imminent Method (_Q11, 0, NotSerialized) { - Store ("EC: BATTERY SHUTDOWN", Debug) + Printf ("EC: BATTERY SHUTDOWN") Notify (BAT0, 0x80) } @@ -332,7 +332,7 @@ Device (EC0) Method (_Q12, 0, NotSerialized) { #ifdef EC_ENABLE_THROTTLING_HANDLER - Store ("EC: THROTTLE START", Debug) + Printf ("EC: THROTTLE START") \_TZ.THRT (1) #endif } @@ -341,7 +341,7 @@ Device (EC0) Method (_Q13, 0, NotSerialized) { #ifdef EC_ENABLE_THROTTLING_HANDLER - Store ("EC: THROTTLE STOP", Debug) + Printf ("EC: THROTTLE STOP") \_TZ.THRT (0) #endif } @@ -350,7 +350,7 @@ Device (EC0) // PD event Method (_Q16, 0, NotSerialized) { - Store ("EC: GOT PD EVENT", Debug) + Printf ("EC: GOT PD EVENT") Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) } #endif @@ -358,7 +358,7 @@ Device (EC0) // Battery Status Method (_Q17, 0, NotSerialized) { - Store ("EC: BATTERY STATUS", Debug) + Printf ("EC: BATTERY STATUS") Notify (BAT0, 0x80) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE If (CondRefOf (BAT1)) { @@ -370,7 +370,7 @@ Device (EC0) // MKBP interrupt. Method (_Q1B, 0, NotSerialized) { - Store ("EC: MKBP", Debug) + Printf ("EC: MKBP") Notify (CREC, 0x80) } @@ -378,7 +378,7 @@ Device (EC0) // USB MUX Interrupt Method (_Q1C, 0, NotSerialized) { - Store ("EC: USB MUX", Debug) + Printf ("EC: USB MUX") Notify (\_SB.PCI0.LPCB.EC0.CREC.ECPD, 0x80) } #endif @@ -386,7 +386,7 @@ Device (EC0) // TABLET mode switch Event Method (_Q1D, 0, NotSerialized) { - Store ("EC: TABLET mode switch Event", Debug) + Printf ("EC: TABLET mode switch Event") Notify (CREC, 0x2) #ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES \_SB.DPTF.TPET() @@ -426,7 +426,7 @@ Device (EC0) Divide (ToInteger (Arg1), 10, , Local1) /* Adjust by EC temperature offset */ - Subtract (Local1, ^TOFS, ^PATT) + ^PATT = Local1 - ^TOFS /* Set commit value with SELECT=0 and ENABLE=1 */ Store (0x02, ^PATC) @@ -453,7 +453,7 @@ Device (EC0) Divide (ToInteger (Arg1), 10, , Local1) /* Adjust by EC temperature offset */ - Subtract (Local1, ^TOFS, ^PATT) + ^PATT = Local1 - ^TOFS /* Set commit value with SELECT=1 and ENABLE=1 */ Store (0x03, ^PATC) @@ -489,7 +489,7 @@ Device (EC0) */ Method (_Q09, 0, NotSerialized) { - If (LNot(Acquire (^PATM, 1000))) { + If (!Acquire (^PATM, 1000)) { /* Read sensor ID for event */ Store (^PATI, Local0) @@ -542,7 +542,7 @@ Device (EC0) If (LEqual (^DDPN, 0)) { Return (^TBMD) } Else { - Subtract (^DDPN, 1, Local0) + Local0 = ^DDPN - 1 Return (Local0) } } diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 642c31385a..5d5392609f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -975,7 +975,7 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) retry: if (google_chromeec_command(&cmd)) { - printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n", + printk(BIOS_ERR, "failed to %s vbnv_ec context: %d\n", is_read ? "read" : "write", (int)cmd.cmd_code); mdelay(10); /* just in case */ if (--retries) @@ -1775,7 +1775,6 @@ int google_chromeec_regulator_enable(uint32_t index, uint8_t enable) int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) { - struct ec_params_regulator_is_enabled params = { .index = index, }; diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 059836485f..3d781287ee 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -59,7 +60,12 @@ static void get_usb_port_references(int port_number, struct device **usb2_port, * Check for a matching port number (the 'token' field in 'group'). Note that * 'port_number' is 0-based, whereas the 'token' field is 1-based. */ - if (config->group.token != (port_number + 1)) + int group_token; + if (config->use_custom_pld) + group_token = config->custom_pld.group.token; + else + group_token = config->group.token; + if (group_token != (port_number + 1)) continue; switch (port->path.usb.port_type) { @@ -105,7 +111,8 @@ static const char *port_location_to_str(enum ec_pd_port_location port_location) return "BACK_LEFT"; case EC_PD_PORT_LOCATION_BACK_RIGHT: return "BACK_RIGHT"; - case EC_PD_PORT_LOCATION_UNKNOWN: /* intentional fallthrough */ + case EC_PD_PORT_LOCATION_UNKNOWN: + __fallthrough; default: return "UNKNOWN"; } @@ -117,17 +124,46 @@ static void add_port_location(struct acpi_dp *dsd, int port_number) acpi_dp_add_string(dsd, "port-location", port_location_to_str(port_caps.port_location)); } +static void get_pld_from_usb_ports(struct acpi_pld *pld, + struct device *usb2_port, struct device *usb3_port, + struct device *usb4_port) +{ + struct drivers_usb_acpi_config *config = NULL; + + if (usb4_port) + config = usb4_port->chip_info; + else if (usb3_port) + config = usb3_port->chip_info; + else if (usb2_port) + config = usb2_port->chip_info; + + if (config) { + if (config->use_custom_pld) + *pld = config->custom_pld; + else + acpi_pld_fill_usb(pld, config->type, &config->group); + } +} + static void fill_ssdt_typec_device(const struct device *dev) { struct ec_google_chromeec_config *config = dev->chip_info; int rv; int i; - unsigned int num_ports; + unsigned int num_ports = 0; struct device *usb2_port; struct device *usb3_port; struct device *usb4_port; + struct acpi_pld pld = {0}; + uint32_t pcap_mask = 0; - if (google_chromeec_get_num_pd_ports(&num_ports)) + rv = google_chromeec_get_num_pd_ports(&num_ports); + if (rv || num_ports == 0) + return; + + /* If we can't get port caps, we shouldn't bother creating a device. */ + rv = google_chromeec_get_cmd_versions(EC_CMD_GET_PD_PORT_CAPS, &pcap_mask); + if (rv || pcap_mask == 0) return; acpigen_write_scope(acpi_device_path(dev)); @@ -146,16 +182,20 @@ static void fill_ssdt_typec_device(const struct device *dev) usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); + get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port); + struct typec_connector_class_config typec_config = { - .power_role = port_caps.power_role_cap, - .try_power_role = port_caps.try_power_role_cap, - .data_role = port_caps.data_role_cap, + .power_role = (enum usb_typec_power_role)port_caps.power_role_cap, + .try_power_role = + (enum usb_typec_try_power_role)port_caps.try_power_role_cap, + .data_role = (enum usb_typec_data_role)port_caps.data_role_cap, .usb2_port = usb2_port, .usb3_port = usb3_port, .usb4_port = usb4_port, .orientation_switch = config->mux_conn[i], .usb_role_switch = config->mux_conn[i], .mode_switch = config->mux_conn[i], + .pld = &pld, }; acpigen_write_typec_connector(&typec_config, i, add_port_location); @@ -186,6 +226,7 @@ static const enum ps2_action_key ps2_enum_val[] = { [TK_PREV_TRACK] = PS2_KEY_PREV_TRACK, [TK_KBD_BKLIGHT_TOGGLE] = PS2_KEY_KBD_BKLIGHT_TOGGLE, [TK_MICMUTE] = PS2_KEY_MICMUTE, + [TK_MENU] = PS2_KEY_MENU, }; static void fill_ssdt_ps2_keyboard(const struct device *dev) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index bbe34be71a..33045cf97a 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -177,7 +177,7 @@ extern "C" { #define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * @@ -185,6 +185,10 @@ extern "C" { */ #define EC_TEMP_SENSOR_B_ENTRIES 8 +/* Max temp sensor entries for host commands */ +#define EC_MAX_TEMP_SENSOR_ENTRIES (EC_TEMP_SENSOR_ENTRIES + \ + EC_TEMP_SENSOR_B_ENTRIES) + /* Special values for mapped temperature sensors */ #define EC_TEMP_SENSOR_NOT_PRESENT 0xff #define EC_TEMP_SENSOR_ERROR 0xfe @@ -1499,6 +1503,10 @@ enum ec_feature_code { * mux. */ EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, + /* + * The EC supports entering and residing in S4. + */ + EC_FEATURE_S4_RESIDENCY = 44, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -1765,6 +1773,8 @@ struct ec_params_flash_erase_v1 { #define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) +/* Error - Unknown error */ +#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) /** @@ -2706,6 +2716,8 @@ enum motionsensor_chip { MOTIONSENSE_CHIP_ICM42607 = 26, MOTIONSENSE_CHIP_BMA422 = 27, MOTIONSENSE_CHIP_BMI323 = 28, + MOTIONSENSE_CHIP_BMI220 = 29, + MOTIONSENSE_CHIP_CM32183 = 30, MOTIONSENSE_CHIP_MAX, }; @@ -2856,7 +2868,7 @@ struct ec_params_motion_sense { */ struct __ec_todo_unpacked { /* Data to set or EC_MOTION_SENSE_NO_VALUE to read. - * kb_wake_angle: angle to wake up AP. + * kb_wake_angle: angle to wakup AP. */ int16_t data; } kb_wake_angle; @@ -6051,7 +6063,10 @@ struct ec_params_set_cbi { * - The semantic meaning of an entry should not change. * - Do not exceed 2^15 - 1 for reset reasons or 2^16 - 1 for shutdown reasons. */ -enum chipset_reset_reason { +enum chipset_shutdown_reason { + /* + * Beginning of reset reasons. + */ CHIPSET_RESET_BEGIN = 0, CHIPSET_RESET_UNKNOWN = CHIPSET_RESET_BEGIN, /* Custom reason defined by a board.c or baseboard.c file */ @@ -6075,13 +6090,11 @@ enum chipset_reset_reason { /* EC detected an AP watchdog event. */ CHIPSET_RESET_AP_WATCHDOG, - CHIPSET_RESET_COUNT, -}; + CHIPSET_RESET_COUNT, /* End of reset reasons. */ -/* - * AP hard shutdowns are logged on the same path as resets. - */ -enum chipset_shutdown_reason { + /* + * Beginning of shutdown reasons. + */ CHIPSET_SHUTDOWN_BEGIN = BIT(15), CHIPSET_SHUTDOWN_POWERFAIL = CHIPSET_SHUTDOWN_BEGIN, /* Forcing a shutdown as part of EC initialization */ @@ -6103,7 +6116,7 @@ enum chipset_shutdown_reason { /* Force a chipset shutdown from the power button through EC */ CHIPSET_SHUTDOWN_BUTTON, - CHIPSET_SHUTDOWN_COUNT, + CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */ }; @@ -6410,6 +6423,7 @@ enum action_key { TK_PREV_TRACK = 17, TK_KBD_BKLIGHT_TOGGLE = 18, TK_MICMUTE = 19, + TK_MENU = 20, }; /* @@ -6619,6 +6633,7 @@ enum typec_control_command { TYPEC_CONTROL_COMMAND_EXIT_MODES, TYPEC_CONTROL_COMMAND_CLEAR_EVENTS, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY, }; /* Modes (USB or alternate) that a type-C port may enter. */ @@ -6628,6 +6643,12 @@ enum typec_mode { TYPEC_MODE_USB4, }; +/* Replies the AP may specify to the TBT EnterMode command as a UFP */ +enum typec_tbt_ufp_reply { + TYPEC_TBT_UFP_REPLY_NAK, + TYPEC_TBT_UFP_REPLY_ACK, +}; + struct ec_params_typec_control { uint8_t port; uint8_t command; /* enum typec_control_command */ @@ -6639,8 +6660,12 @@ struct ec_params_typec_control { * the command version when adding new sub-commands. */ union { + /* Used for CLEAR_EVENTS */ uint32_t clear_events_mask; - uint8_t mode_to_enter; /* enum typec_mode */ + /* Used for ENTER_MODE - enum typec_mode */ + uint8_t mode_to_enter; + /* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */ + uint8_t tbt_ufp_reply; uint8_t placeholder[128]; }; } __ec_align1; @@ -6932,8 +6957,9 @@ enum pchg_state { /* Port number is encoded in bit[28:31]. */ #define EC_MKBP_PCHG_PORT_SHIFT 28 -/* Utility macro for converting MKBP event to port number. */ +/* Utility macros for converting MKBP event <-> port number. */ #define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) +#define EC_MKBP_PCHG_PORT_TO_EVENT(p) (BIT((p) + EC_MKBP_PCHG_PORT_SHIFT)) /* Utility macro for extracting event bits. */ #define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \ & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0)) @@ -6942,6 +6968,7 @@ enum pchg_state { #define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) #define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) #define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) +#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) enum ec_pchg_update_cmd { /* Reset chip to normal mode. */ @@ -7006,6 +7033,31 @@ enum ec_set_base_state_cmd { EC_SET_BASE_STATE_RESET, }; +#define EC_CMD_I2C_CONTROL 0x0139 + +/* Subcommands for I2C control */ + +enum ec_i2c_control_command { + EC_I2C_CONTROL_GET_SPEED, + EC_I2C_CONTROL_SET_SPEED, +}; + +#define EC_I2C_CONTROL_SPEED_UNKNOWN 0 + +struct ec_params_i2c_control { + uint8_t port; /* I2C port number */ + uint8_t cmd; /* enum ec_i2c_control_command */ + union { + uint16_t speed_khz; + } cmd_params; +} __ec_align_size1; + +struct ec_response_i2c_control { + union { + uint16_t speed_khz; + } cmd_response; +} __ec_align_size1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 631f16ebce..94b13fb5d1 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -265,7 +265,7 @@ static void write_dppm_methods(const struct device *ec) /* Local0 = ToInteger(Arg0) */ acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_write_if_lequal_op_int(LOCAL0_OP, i); acpigen_notify(name, THERMAL_EVENT); @@ -277,7 +277,7 @@ static void write_dppm_methods(const struct device *ec) /* TPET */ acpigen_write_method("TPET", 0); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) { + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { snprintf(name, sizeof(name), "^TSR%1d", i); acpigen_notify(name, TRIP_POINTS_CHANGED_EVENT); } @@ -355,6 +355,6 @@ void ec_fill_dptf_helpers(const struct device *ec) write_charger_methods(ec); write_fan_methods(ec); - for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) + for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) write_thermal_methods(ec, p, i); } diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index 4bd259018c..f708b3e680 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -3,7 +3,7 @@ #include #include #include -#include +#include #define VBOOT_HASH_VSLOT 0 #define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT)) diff --git a/src/ec/hp/kbc1126/Kconfig b/src/ec/hp/kbc1126/Kconfig index cb4ddec7e4..5e6edd6a69 100644 --- a/src/ec/hp/kbc1126/Kconfig +++ b/src/ec/hp/kbc1126/Kconfig @@ -27,6 +27,12 @@ config KBC1126_FIRMWARE Select this option to add the two firmware blobs for KBC1126. You need these two blobs to power on your machine. +config ECFW_PTR_ADDR + default 0xffffff00 + +config ECFW_PTR_SIZE + default 8 + config KBC1126_FW1 string "KBC1126 firmware #1 path and filename" depends on KBC1126_FIRMWARE @@ -37,9 +43,9 @@ config KBC1126_FW1 vendor firmware. config KBC1126_FW1_OFFSET - string "Offset of KBC1126 firmware #1" + hex "Offset of KBC1126 firmware #1" depends on KBC1126_FIRMWARE - default "0xfffe8000" + default 0xfffe8000 config KBC1126_FW2 string "KBC1126 filename #2 path and filename" @@ -51,8 +57,8 @@ config KBC1126_FW2 vendor firmware. config KBC1126_FW2_OFFSET - string "Offset of KBC1126 firmware #2" + hex "Offset of KBC1126 firmware #2" depends on KBC1126_FIRMWARE - default "0xfffd0000" + default 0xfffd0000 endif diff --git a/src/ec/hp/kbc1126/Makefile.inc b/src/ec/hp/kbc1126/Makefile.inc index 4d7d46d9e7..3f7fa19b5d 100644 --- a/src/ec/hp/kbc1126/Makefile.inc +++ b/src/ec/hp/kbc1126/Makefile.inc @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS),y) -KBC1126_EC_INSERT:=$(top)/util/kbc1126/kbc1126_ec_insert + +bootblock-y += ecfw_ptr.c ifeq ($(CONFIG_KBC1126_FIRMWARE),y) cbfs-files-y += ecfw1.bin @@ -16,15 +17,6 @@ ecfw2.bin-position := $(CONFIG_KBC1126_FW2_OFFSET) ecfw2.bin-type := raw endif -$(call add_intermediate, kbc1126_ec_insert) -ifeq ($(CONFIG_KBC1126_FIRMWARE),y) - printf " Building kbc1126_ec_insert.\n" - $(MAKE) -C util/kbc1126 - printf " KBC1126 Inserting KBC1126 firmware blobs.\n" - $(KBC1126_EC_INSERT) $(obj)/coreboot.pre \ - $(CONFIG_KBC1126_FW1_OFFSET) $(CONFIG_KBC1126_FW2_OFFSET) -endif - build_complete:: ifeq ($(CONFIG_KBC1126_FIRMWARE),) printf "\n** WARNING **\n" diff --git a/src/ec/hp/kbc1126/acpi/ac.asl b/src/ec/hp/kbc1126/acpi/ac.asl index f9d346b816..f058cef9f2 100644 --- a/src/ec/hp/kbc1126/acpi/ac.asl +++ b/src/ec/hp/kbc1126/acpi/ac.asl @@ -65,7 +65,7 @@ Device (AC) Method (_Q06, 0, NotSerialized) { - Store ("EC: AC STATUS", Debug) + Printf ("EC: AC STATUS") PWUP (0x05, (0x02 | 0x01)) If (BTDR (0x02)) { diff --git a/src/ec/hp/kbc1126/acpi/battery.asl b/src/ec/hp/kbc1126/acpi/battery.asl index 6669726c7d..5a5632b92a 100644 --- a/src/ec/hp/kbc1126/acpi/battery.asl +++ b/src/ec/hp/kbc1126/acpi/battery.asl @@ -230,7 +230,7 @@ Method (\ISTR, 2, Serialized) { Local1-- Divide (Local0, 10, Local2, Local0) - Add (Local2, 48, Index (NUMB, Local1)) + NUMB[Local1] = Local2 + 48 } ToString (NUMB, Arg1, Local3) Return (Local3) @@ -437,7 +437,7 @@ Method (SBTN, 2, Serialized) Method (_Q03, 0, NotSerialized) { - Store ("EC: _Q03", Debug) + Printf ("EC: _Q03") Acquire (BTMX, 0xFFFF) Local0 = NDCB Release (BTMX) @@ -447,7 +447,7 @@ Method (_Q03, 0, NotSerialized) Method (_Q08, 0, NotSerialized) { - Store ("EC: PRIMARY BATTERY ATTACHED/DETACHED", Debug) + Printf ("EC: PRIMARY BATTERY ATTACHED/DETACHED") PWUP (0x06, 0x01) Local0 = GBAP () If ((Local0 != 0x02)) @@ -467,7 +467,7 @@ Method (_Q08, 0, NotSerialized) Method (_Q09, 0, NotSerialized) { - Store ("EC: PRIMARY BATTERY STATUS", Debug) + Printf ("EC: PRIMARY BATTERY STATUS") PWUP (0x04, 0x01) If (BTDR (0x02)) { @@ -477,7 +477,7 @@ Method (_Q09, 0, NotSerialized) Method (_Q18, 0, NotSerialized) { - Store("EC: SECONDARY BATTERY ATTACHED/DETACHED", Debug) + Printf ("EC: SECONDARY BATTERY ATTACHED/DETACHED") PWUP (0x06, 0x02) Local0 = GBAP () If ((Local0 != 0x01)) @@ -497,7 +497,7 @@ Method (_Q18, 0, NotSerialized) Method (_Q19, 0, NotSerialized) { - Store ("EC: SECONDARY BATTERY STATUS", Debug) + Printf ("EC: SECONDARY BATTERY STATUS") PWUP (0x04, 0x02) If (BTDR (0x02)) { diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index 81bdff969a..4c0056dcc6 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -202,27 +202,27 @@ Device (EC0) Method (_Q04, 0, NotSerialized) { - Store ("EC: _Q04", Debug) + Printf ("EC: _Q04") PNOT() } Method (_Q05, 0, NotSerialized) { - Store ("EC: _Q05", Debug) + Printf ("EC: _Q05") } Method (_Q0B, 0, NotSerialized) { - Store ("EC: _Q0B", Debug) + Printf ("EC: _Q0B") } Method (_Q0C, 0, NotSerialized) { - Store ("EC: _Q0C", Debug) + Printf ("EC: _Q0C") } Method (_Q0D, 0, NotSerialized) { - Store ("EC: _Q0D", Debug) + Printf ("EC: _Q0D") } } diff --git a/src/ec/hp/kbc1126/acpi/lid.asl b/src/ec/hp/kbc1126/acpi/lid.asl index 24941684a8..1a5134ff9a 100644 --- a/src/ec/hp/kbc1126/acpi/lid.asl +++ b/src/ec/hp/kbc1126/acpi/lid.asl @@ -12,6 +12,6 @@ Device (LID) Method (_Q0A, 0, NotSerialized) { - Store ("EC: LID STATUS", Debug) + Printf ("EC: LID STATUS") Notify (LID, 0x80) } diff --git a/src/ec/hp/kbc1126/ecfw_ptr.c b/src/ec/hp/kbc1126/ecfw_ptr.c new file mode 100644 index 0000000000..8a29c6cd33 --- /dev/null +++ b/src/ec/hp/kbc1126/ecfw_ptr.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "ecfw_ptr.h" + +/* + * Address info for EC SMSC KBC1098/KBC1126 to find their firmware blobs, + * linked to CONFIG_ECFW_PTR_ADDR via src/arch/x86/bootblock.ld + */ +__attribute__((used, __section__(".ecfw_ptr"))) +const struct ecfw_ptr ecfw_ptr = { + .fw1.off = cpu_to_be16((uint16_t)(CONFIG_KBC1126_FW1_OFFSET >> 8)), + .fw1.inv = cpu_to_be16((uint16_t)~(CONFIG_KBC1126_FW1_OFFSET >> 8)), + .fw2.off = cpu_to_be16((uint16_t)(CONFIG_KBC1126_FW2_OFFSET >> 8)), + .fw2.inv = cpu_to_be16((uint16_t)~(CONFIG_KBC1126_FW2_OFFSET >> 8)), +}; diff --git a/src/ec/hp/kbc1126/ecfw_ptr.h b/src/ec/hp/kbc1126/ecfw_ptr.h new file mode 100644 index 0000000000..acf54f20dd --- /dev/null +++ b/src/ec/hp/kbc1126/ecfw_ptr.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _EC_HP_KBC1126_PTR_H +#define _EC_HP_KBC1126_PTR_H + +#include + +struct __attribute__((__packed__)) ecfw_addr { + /* 8-byte offset of firmware blob in big endian */ + uint16_t off; + /* bitwise inverse of "off", for error checking */ + uint16_t inv; +}; + +struct __attribute__((__packed__)) ecfw_ptr { + struct ecfw_addr fw1; + struct ecfw_addr fw2; +}; + +#endif diff --git a/src/ec/kontron/it8516e/acpi/pm_channels.asl b/src/ec/kontron/it8516e/acpi/pm_channels.asl index ebfd87289b..0ac04673b2 100644 --- a/src/ec/kontron/it8516e/acpi/pm_channels.asl +++ b/src/ec/kontron/it8516e/acpi/pm_channels.asl @@ -36,7 +36,7 @@ Device (PM1) { Return (0) } Multiply (Local0, 10, Local0) /* Convert to 10th °C */ - Return (Add (Local0, 2732)) /* Return as 10th Kelvin */ + Return (Local0 + 2732) /* Return as 10th Kelvin */ } } #endif @@ -91,8 +91,8 @@ Device (PM2) { Release (EC_MUTEX) Or (ShiftLeft (Local1, 8), Local0, Local0) - Store (Divide (Multiply (Local0, 10), 64), Local0) /* Convert to 10th °C */ - Return (Add (Local0, 2732)) /* Return as 10th Kelvin */ + Store (Local0 * 10 / 64, Local0) /* Convert to 10th °C */ + Return (Local0 + 2732) /* Return as 10th Kelvin */ } } #endif diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 0489bac042..31d927d029 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -82,13 +82,13 @@ static void kempld_enable_dev(struct device *const dev) dev->ops = &kempld_uart_ops; break; } - /* Fall through. */ + __fallthrough; case 1: if (dev->path.generic.subid == 0) { kempld_i2c_device_init(dev); break; } - /* Fall through. */ + __fallthrough; default: printk(BIOS_WARNING, "KEMPLD: Spurious device %s.\n", dev_path(dev)); break; diff --git a/src/ec/kontron/kempld/kempld_gpio.c b/src/ec/kontron/kempld/kempld_gpio.c index 8699c1f477..3a3b19dfdc 100644 --- a/src/ec/kontron/kempld/kempld_gpio.c +++ b/src/ec/kontron/kempld/kempld_gpio.c @@ -2,7 +2,7 @@ #include #include -#include + #include "chip.h" #include "kempld.h" #include "kempld_internal.h" diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index fe2d2875c7..85cfdb5186 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -12,7 +12,7 @@ Scope(\_TZ) Method(C2K, 1, NotSerialized) { Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) + Local0 += 2732 if (LLessEqual(Local0, 2732)) { Return (3000) } @@ -73,7 +73,7 @@ External (\PPKG, MethodObj) Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + If (!MEB1 && LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128)) { Return (C2K(40)) } Store (1, MEB1) @@ -85,11 +85,11 @@ External (\PPKG, MethodObj) Store (GPSV (), Local0) /* Active fan 10 degree below passive threshold */ - Subtract (Local0, 10, Local0) + Local0 -= 10 If (\FLVL) { /* Turn of 5 degree below trip point */ - Subtract (Local0, 5, Local0) + Local0 -= 5 } Return (C2K (Local0)) @@ -160,7 +160,7 @@ External (\PPKG, MethodObj) Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { + If (!MEB2 && LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128)) { Return (C2K(40)) } Store (1, MEB2) diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index eca0d4471d..48e76dc5b1 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -37,13 +37,13 @@ Device (HKEY) Store (BTN, Local0) If (LNotEqual (Local0, Zero)) { Store (Zero, BTN) - Add (Local0, 0x1000, Local0) + Local0 += 0x1000 Return (Local0) } Store (BTAB, Local0) If (LNotEqual (Local0, Zero)) { Store (Zero, BTAB) - Add (Local0, 0x5000, Local0) + Local0 += 0x5000 Return (Local0) } Return (Zero) @@ -51,7 +51,7 @@ Device (HKEY) /* Report event */ Method (RHK, 1, NotSerialized) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) + ShiftLeft (One, Arg0 - 1, Local0) If (And (EMSK, Local0)) { Store (Arg0, BTN) Notify (HKEY, 0x80) @@ -60,7 +60,7 @@ Device (HKEY) /* Report tablet */ Method (RTAB, 1, NotSerialized) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) + ShiftLeft (One, Arg0 - 1, Local0) If (And (ETAB, Local0)) { Store (Arg0, BTAB) Notify (HKEY, 0x80) @@ -84,7 +84,7 @@ Device (HKEY) /* Enable/disable event. */ Method (MHKM, 2, NotSerialized) { If (LLessEqual (Arg0, 0x20)) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) + ShiftLeft (One, Arg0 - 1, Local0) If (Arg1) { Or (DHKN, Local0, DHKN) diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index d1aa9fe0c5..440c2fc4dd 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -4,7 +4,6 @@ #define EC_LENOVO_H8EC_CHIP_H struct ec_lenovo_h8_config { - u8 config0; u8 config1; u8 config2; diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index b081ec8f22..bbe6490f0c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -18,7 +18,6 @@ void h8_trackpoint_enable(int on) { ec_write(H8_TRACKPOINT_CTRL, on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); - } /* Controls radio-off pin in WLAN MiniPCIe slot. */ @@ -119,7 +118,6 @@ void h8_disable_event(int event) return; ec_clr_bit(0x10 + (event >> 3), event & 7); - } void h8_usb_always_on_enable(enum usb_always_on on) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index ebcbcde089..c232a51222 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -25,7 +25,6 @@ void pmh7_dock_event_enable(int onoff) pmh7_register_set_bit(0x60, 3); else pmh7_register_clear_bit(0x60, 3); - } void pmh7_touchpad_enable(int onoff) diff --git a/src/ec/purism/librem-ec/acpi/ec.asl b/src/ec/purism/librem-ec/acpi/ec.asl index bc225e713e..4e7b4a1f15 100644 --- a/src/ec/purism/librem-ec/acpi/ec.asl +++ b/src/ec/purism/librem-ec/acpi/ec.asl @@ -34,7 +34,7 @@ Device (\_SB.PCI0.LPCB.EC0) Name (ECOK, Zero) Method (_REG, 2, Serialized) // _REG: Region Availability { - Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1)) If ((Arg0 == 0x03) && (Arg1 == One)) { // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys ECOS = 1 @@ -63,7 +63,7 @@ Device (\_SB.PCI0.LPCB.EC0) } Method (PTS, 1, Serialized) { - Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + Printf ("EC: PTS: %o", ToHexString(Arg0)) If (ECOK) { // Clear wake cause WFNO = Zero @@ -71,7 +71,7 @@ Device (\_SB.PCI0.LPCB.EC0) } Method (WAK, 1, Serialized) { - Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + Printf ("EC: WAK: %o", ToHexString(Arg0)) If (ECOK) { // Set current AC state ^^^^AC.ACFG = ADP @@ -91,42 +91,42 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q0A, 0, NotSerialized) // Touchpad Toggle { - Debug = "EC: Touchpad Toggle" + Printf ("EC: Touchpad Toggle") } Method (_Q0B, 0, NotSerialized) // Screen Toggle { - Debug = "EC: Screen Toggle" + Printf ("EC: Screen Toggle") } Method (_Q0C, 0, NotSerialized) // Mute { - Debug = "EC: Mute" + Printf ("EC: Mute") } Method (_Q0D, 0, NotSerialized) // Keyboard Backlight { - Debug = "EC: Keyboard Backlight" + Printf ("EC: Keyboard Backlight") } Method (_Q0E, 0, NotSerialized) // Volume Down { - Debug = "EC: Volume Down" + Printf ("EC: Volume Down") } Method (_Q0F, 0, NotSerialized) // Volume Up { - Debug = "EC: Volume Up" + Printf ("EC: Volume Up") } Method (_Q10, 0, NotSerialized) // Switch Video Mode { - Debug = "EC: Switch Video Mode" + Printf ("EC: Switch Video Mode") } Method (_Q11, 0, NotSerialized) // Brightness Down { - Debug = "EC: Brightness Down" + Printf ("EC: Brightness Down") if (^^^^HIDD.HRDY) { ^^^^HIDD.HPEM (20) } @@ -134,7 +134,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q12, 0, NotSerialized) // Brightness Up { - Debug = "EC: Brightness Up" + Printf ("EC: Brightness Up") if (^^^^HIDD.HRDY) { ^^^^HIDD.HPEM (19) } @@ -142,12 +142,12 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q13, 0, NotSerialized) // Camera Toggle { - Debug = "EC: Camera Toggle" + Printf ("EC: Camera Toggle") } Method (_Q14, 0, NotSerialized) // Airplane Mode { - Debug = "EC: Airplane Mode" + Printf ("EC: Airplane Mode") if (^^^^HIDD.HRDY) { ^^^^HIDD.HPEM (8) } @@ -156,13 +156,13 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q15, 0, NotSerialized) // Suspend Button { - Debug = "EC: Suspend Button" + Printf ("EC: Suspend Button") Notify (SLPB, 0x80) } Method (_Q16, 0, NotSerialized) // AC Detect { - Debug = "EC: AC Detect" + Printf ("EC: AC Detect") ^^^^AC.ACFG = ADP Notify (AC, 0x80) // Status Change If (BAT0) @@ -174,25 +174,25 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q17, 0, NotSerialized) // BAT0 Update { - Debug = "EC: BAT0 Update (17)" + Printf ("EC: BAT0 Update (17)") Notify (^^^^BAT0, 0x81) // Information Change } Method (_Q19, 0, NotSerialized) // BAT0 Update { - Debug = "EC: BAT0 Update (19)" + Printf ("EC: BAT0 Update (19)") Notify (^^^^BAT0, 0x81) // Information Change } Method (_Q1B, 0, NotSerialized) // Lid Close { - Debug = "EC: Lid Close" + Printf ("EC: Lid Close") Notify (LID0, 0x80) } Method (_Q1C, 0, NotSerialized) // Thermal Trip { - Debug = "EC: Thermal Trip" + Printf ("EC: Thermal Trip") /* TODO Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change Notify (\_TZ.TZ0, 0x80) // Thermal Status Change @@ -201,7 +201,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q1D, 0, NotSerialized) // Power Button { - Debug = "EC: Power Button" + Printf ("EC: Power Button") Notify (PWRB, 0x80) } @@ -209,22 +209,22 @@ Device (\_SB.PCI0.LPCB.EC0) { Local0 = OEM4 If (Local0 == 0x8A) { - Debug = "EC: White Keyboard Backlight" + Printf ("EC: White Keyboard Backlight") Notify (^^^^LIEC, 0x80) } ElseIf (Local0 == 0x9F) { - Debug = "EC: Color Keyboard Toggle" + Printf ("EC: Color Keyboard Toggle") Notify (^^^^LIEC, 0x81) } ElseIf (Local0 == 0x81) { - Debug = "EC: Color Keyboard Down" + Printf ("EC: Color Keyboard Down") Notify (^^^^LIEC, 0x82) } ElseIf (Local0 == 0x82) { - Debug = "EC: Color Keyboard Up" + Printf ("EC: Color Keyboard Up") Notify (^^^^LIEC, 0x83) } ElseIf (Local0 == 0x80) { - Debug = "EC: Color Keyboard Color Change" + Printf ("EC: Color Keyboard Color Change") Notify (^^^^LIEC, 0x84) } Else { - Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + Printf ("EC: Other: %o", ToHexString(Local0)) } } diff --git a/src/ec/purism/librem-ec/acpi/librem-ec.asl b/src/ec/purism/librem-ec/acpi/librem-ec.asl index 5914d1722c..ea227c74be 100644 --- a/src/ec/purism/librem-ec/acpi/librem-ec.asl +++ b/src/ec/purism/librem-ec/acpi/librem-ec.asl @@ -11,13 +11,13 @@ Device (LIEC) { Name (_UID, 0) Method (RSET, 0, Serialized) { - Debug = "LIEC: RSET" + Printf ("LIEC: RSET") SAPL(0) SKBL(0) } Method (INIT, 0, Serialized) { - Debug = "LIEC: INIT" + Printf ("LIEC: INIT") RSET() If (^^PCI0.LPCB.EC0.ECOK) { // Set flags to use software control @@ -29,7 +29,7 @@ Device (LIEC) { } Method (FINI, 0, Serialized) { - Debug = "LIEC: FINI" + Printf ("LIEC: FINI") RSET() If (^^PCI0.LPCB.EC0.ECOK) { // Set flags to use hardware control diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index a14c737aad..1f1cf9729a 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -12,7 +12,7 @@ Device (EC0) { Name (_HID, EISAID ("PNP0C09")) Name (_UID, 1) - Name (_GPE, Add(EC_SCI_GPI, 16)) // GPE for Runtime SCI + Name (_GPE, EC_SCI_GPI + 16) // GPE for Runtime SCI OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) Field (ERAM, ByteAcc, Lock, Preserve) @@ -135,13 +135,11 @@ Device (EC0) // Find and program number of P-States Store (SizeOf (\_SB.CP00._PSS), MPST) - Store ("Programming number of P-states: ", Debug) - Store (MPST, Debug) + Printf ("Programming number of P-states: %o", MPST) // Find and program the current P-State Store(\_SB.CP00._PPC, NPST) - Store ("Programming Current P-state: ", Debug) - Store (NPST, Debug) + Printf ("Programming Current P-state: %o", NPST) } /* @@ -163,26 +161,26 @@ Device (EC0) // Wifi Button Event Method (_Q07) { - Store ("Wifi Button Event 0x07", Debug) + Printf ("Wifi Button Event 0x07") } // Thermal Event Method (_Q08) { - Store ("Thermal Event 0x08", Debug) + Printf ("Thermal Event 0x08") Notify(\_TZ.THRM, 0x80) } // Pstate Down Method (_Q0E) { - Store ("Pstate Event 0x0E", Debug) + Printf ("Pstate Event 0x0E") Store(\_SB.CP00._PPC, Local0) - Subtract(PPCM, 0x01, Local1) + Local1 = PPCM - 1 If(LLess(Local0, Local1)) { - Increment(Local0) + Local0++ \PPCN () } @@ -192,11 +190,11 @@ Device (EC0) // Pstate Up Method (_Q0F) { - Store ("Pstate Event 0x0F", Debug) + Printf ("Pstate Event 0x0F") Store(\_SB.CP00._PPC, Local0) If(Local0) { - Decrement(Local0) + Local0-- \PPCN () } @@ -206,7 +204,7 @@ Device (EC0) // AC Power Connected Method (_Q10, 0, NotSerialized) { - Store ("AC Insertion Event 0x10", Debug) + Printf ("AC Insertion Event 0x10") Store (One, \PWRS) Notify (AC, 0x80) Notify (BATX, 0x80) @@ -216,7 +214,7 @@ Device (EC0) // AC Power Removed Method (_Q11, 0, NotSerialized) { - Store ("AC Detach Event 0x11", Debug) + Printf ("AC Detach Event 0x11") Store (Zero, \PWRS) Notify (AC, 0x80) Notify (BATX, 0x80) @@ -226,7 +224,7 @@ Device (EC0) // Battery State Change - Attach Event Method (_Q12, 0, NotSerialized) { - Store ("Battery Insertion Event 0x12", Debug) + Printf ("Battery Insertion Event 0x12") Notify (BATX, 0x81) Notify (BATX, 0x80) @@ -236,7 +234,7 @@ Device (EC0) // Battery State Change - Detach Event Method (_Q13, 0, NotSerialized) { - Store ("Battery Detach Event 0x13", Debug) + Printf ("Battery Detach Event 0x13") Notify (BATX, 0x81) Notify (BATX, 0x80) @@ -247,7 +245,7 @@ Device (EC0) // Battery State Change Event Method (_Q14, 0, NotSerialized) { - Store ("Battery State Change Event 0x14", Debug) + Printf ("Battery State Change Event 0x14") Notify (BATX, 0x80) } @@ -255,7 +253,7 @@ Device (EC0) // Lid Switch Event Method (_Q06) { - Store ("Lid Switch Event 0x06", Debug) + Printf ("Lid Switch Event 0x06") sleep(20) Store (LIDF, \LIDS) Notify (\_SB.LID0, 0x80) diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index c7b934877c..4b4f5328fc 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -103,7 +103,6 @@ void ec_mem_write(u8 addr, u8 data) ec_write_cmd(EC_CMD_WRITE_RAM); ec_write_ib(addr); ec_write_ib(data); - return; } static void ene_kb3940q_log_events(void) diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 768f2b12e4..4fcc30c82d 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -67,7 +67,7 @@ Device (BATX) { // EC Is not ready Sleep (5) - Decrement (Local0) + Local0-- If (LEqual (Local0, Zero)) { Break @@ -106,7 +106,7 @@ Device (BATX) // ACPI spec : 0 - mWh : 1 - mAh // Store(SBCM, Local7) - XOr (Local7, One, Index (PBIF, 0)) + XOr (Local7, One, PBIF[0]) // // Information ID 0 - @@ -119,11 +119,11 @@ Device (BATX) // If (Local7) { - Multiply (SBFC, 10, Index (PBIF, 2)) + Multiply (SBFC, 10, PBIF[2]) } Else { - Store (SBFC, Index (PBIF, 2)) + Store (SBFC, PBIF[2]) } // @@ -143,24 +143,24 @@ Device (BATX) { Store (SBDC, Local0) } - Store (Local0, Index(PBIF, One)) + Store (Local0, PBIF[1]) // // Design capacity of High (5%) // Design capacity of Low (1%) // - Divide (Local0, 20, , Index (PBIF, 5)) - Divide (Local0, 100, , Index (PBIF, 6)) + Divide (Local0, 20, , PBIF[5]) + Divide (Local0, 100, , PBIF[6]) // // Design voltage // - Store (SBDV, Index (PBIF, 4)) + Store (SBDV, PBIF[4]) // // Serial Number // - Store (ToHexString (SBSN), Index (PBIF, 10)) + Store (ToHexString (SBSN), PBIF[10]) // // Information ID 4 - @@ -171,7 +171,7 @@ Device (BATX) // // Battery Type - Device Chemistry // - Store (ToString (Concatenate(SBCH, 0x00)), Index (PBIF, 11)) + Store (ToString (Concatenate(SBCH, 0x00)), PBIF[11]) // // Information ID 5 - @@ -182,7 +182,7 @@ Device (BATX) // // OEM Information - Manufacturer Name // - Store (ToString (Concatenate(SBMN, 0x00)), Index (PBIF, 12)) + Store (ToString (Concatenate(SBMN, 0x00)), PBIF[12]) // // Information ID 6 - @@ -193,7 +193,7 @@ Device (BATX) // // Model Number - Device Name // - Store (ToString (Concatenate(SBDN, 0x00)), Index (PBIF, 9)) + Store (ToString (Concatenate(SBDN, 0x00)), PBIF[9]) Return (PBIF) } @@ -255,7 +255,7 @@ Device (BATX) // Flag if the battery level is critical And (Local0, 0x04, Local4) Or (Local1, Local4, Local1) - Store (Local1, Index (PBST, 0)) + Store (Local1, PBST[0]) // // 1: BATTERY PRESENT RATE/CURRENT @@ -265,7 +265,7 @@ Device (BATX) { If (And (Local0, 1)) { - Subtract (0x10000, Local1, Local1) + Local1 = 0x10000 - Local1 } Else { @@ -275,21 +275,21 @@ Device (BATX) } Else { - If (LNot (AND (Local0, 2))) + If (!(AND (Local0, 2))) { // Battery is not charging Store (Zero, Local1) } } - XOr (DerefOf (Index (PBIF, Zero)), One, Local6) + XOr (DerefOf (PBIF[0]), One, Local6) If (Local6) { Multiply (ECVO, Local1, Local1) Divide (Local1, 1000, , Local1) } - Store (Local1, Index (PBST, One)) + Store (Local1, PBST[1]) // // 2: BATTERY REMAINING CAPACITY @@ -306,7 +306,7 @@ Device (BATX) Store (ECRC, Local1) } - If (LAnd (BFWK, LAnd (ACPW, LNot (Local0)))) + If (BFWK && ACPW && !Local0) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery @@ -317,18 +317,17 @@ Device (BATX) // See if within ~3% of full ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + If (LGreater (Local1, Local2 - Local3) && LLess (Local1, Local2 + Local3)) { Store (Local2, Local1) } } - Store (Local1, Index (PBST, 2)) + Store (Local1, PBST[2]) // // 3: BATTERY PRESENT VOLTAGE // - Store (ECVO, Index (PBST, 3)) + Store (ECVO, PBST[3]) Return (PBST) } diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 36f966f94d..3d1e2442bd 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -10,7 +10,7 @@ Device (EC0) { Name (_HID, EISAID ("PNP0C09")) Name (_UID, 1) - Name (_GPE, Add(EC_SCI_GPI, 16)) // GPE for Runtime SCI + Name (_GPE, EC_SCI_GPI + 16) // GPE for Runtime SCI // EC RAM fields OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) @@ -556,8 +556,7 @@ Device (EC0) // TODO Which temperature corresponds to the CPU? Store (TMP0, Local0) /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) - + Local0++ } /* Attention Codes diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl index fad69b802a..0cc41a178b 100644 --- a/src/ec/smsc/mec1308/acpi/battery.asl +++ b/src/ec/smsc/mec1308/acpi/battery.asl @@ -81,15 +81,15 @@ Device (BAT0) Method (_BIF, 0, Serialized) { // Update fields from EC - Store (SWAB (BTDA), Index (PBIF, 1)) - Store (SWAB (BTDF), Index (PBIF, 2)) - Store (SWAB (BTDV), Index (PBIF, 4)) - Store (SWAB (BTDL), Index (PBIF, 6)) + Store (SWAB (BTDA), PBIF[1]) + Store (SWAB (BTDF), PBIF[2]) + Store (SWAB (BTDV), PBIF[4]) + Store (SWAB (BTDL), PBIF[6]) // Get battery info from mainboard - Store (\BATM, Index (PBIF, 9)) - Store (\BATS, Index (PBIF, 10)) - Store (\BATV, Index (PBIF, 12)) + Store (\BATM, PBIF[9]) + Store (\BATS, PBIF[10]) + Store (\BATV, PBIF[12]) Return (PBIF) } @@ -120,7 +120,7 @@ Device (BAT0) // Flag if the battery level is critical And (Local0, 0x04, Local4) Or (Local1, Local4, Local1) - Store (Local1, Index (PBST, 0)) + Store (Local1, PBST[0]) // Notify if battery state has changed since last time If (LNotEqual (Local1, BSTP)) { @@ -133,24 +133,22 @@ Device (BAT0) // Store (SWAB (BTPR), Local1) - If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), - LGreaterEqual (Local1, 0x8000))) { + If (LNotEqual (Local1, 0xFFFFFFFF) && LGreaterEqual (Local1, 0x8000)) { Xor (Local1, 0xFFFF, Local1) - Increment (Local1) + Local1++ } - Store (Local1, Index (PBST, 1)) + Store (Local1, PBST[1]) // // 2: BATTERY REMAINING CAPACITY // Store (SWAB (BTRA), Local1) - If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), - LGreaterEqual (Local1, 0x8000))) { + If (LNotEqual (Local1, 0xFFFFFFFF) && LGreaterEqual (Local1, 0x8000)) { Xor (Local1, 0xFFFF, Local1) - Increment (Local1) + Local1++ } - If (LAnd (BFWK, LAnd (ACEX, LNot (Local0)))) { + If (BFWK && ACEX && !Local0) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. @@ -159,18 +157,18 @@ Device (BAT0) // See if within ~3% of full ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + If (LGreater (Local1, Local2 - Local3) && + LLess (Local1, Local2 + Local3)) { Store (Local2, Local1) } } - Store (Local1, Index (PBST, 2)) + Store (Local1, PBST[2]) // // 3: BATTERY PRESENT VOLTAGE // - Store (SWAB (BTVO), Index (PBST, 3)) + Store (SWAB (BTVO), PBST[3]) Return (PBST) } diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl index c7b180dc3e..23b4c692d6 100644 --- a/src/ec/smsc/mec1308/acpi/ec.asl +++ b/src/ec/smsc/mec1308/acpi/ec.asl @@ -69,7 +69,7 @@ Device (EC0) // Force a read of CPU temperature Store (CPUT, Local0) /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) + Local0++ } PowerResource (FNP0, 0, 0) diff --git a/src/ec/starlabs/it8987/Kconfig b/src/ec/starlabs/it8987/Kconfig deleted file mode 100644 index ba9e908077..0000000000 --- a/src/ec/starlabs/it8987/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -config EC_STARLABS_IT8987 - bool - select EC_ACPI - help - Interface to IT8987 embedded controller principally in Star Labs notebooks. diff --git a/src/ec/starlabs/it8987/Makefile.inc b/src/ec/starlabs/it8987/Makefile.inc deleted file mode 100644 index b021d0ff38..0000000000 --- a/src/ec/starlabs/it8987/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -PHONY+=add_ite_fw -INTERMEDIATE+=add_ite_fw - -ifeq ($(CONFIG_EC_STARLABS_IT8987),y) -all-y += ec.c -smm-$(CONFIG_DEBUG_SMI) += ec.c -endif - -ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN),y) - -ifeq ($(CONFIG_EC_STARLABS_IT8987_BIN_PATH),) -files_added:: warn_no_ite_fw -endif - -add_ite_fw: $(obj)/coreboot.pre - $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_IT8987_BIN_PATH) -u -endif - -PHONY+=warn_no_ite_fw -warn_no_ite_fw: - printf "\n\t** WARNING **\n" - printf "coreboot has been built without the IT8987 EC Firmware.\n" - printf "Do not flash this image. Your LabTop Mk IV's power button\n" - printf "may not respond when you press it.\n\n" diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl deleted file mode 100644 index 97ae1474a7..0000000000 --- a/src/ec/starlabs/it8987/acpi/ac.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (ADP1) -{ - Name (_HID, "ACPI0003") - Name (_PCL, Package () { \_SB }) - - Method (_STA, 0, NotSerialized) // _STA: Status - { - If (ECON == 1) - { - Local0 = 0x0F - } - Else - { - Local0 = 0 - } - Return (Local0) - } - - Method (_PSR, 0, NotSerialized) // _PSR: Power Source - { - If (ECWR & 0x01) - { - \PWRS = 1 - } - Else - { - \PWRS = 0 - } - Return (\PWRS) - } -} - -Method (_QA0, 0, NotSerialized) // AC Power Connected -{ - If (ECWR & 0x01) - { - \PWRS = 1 - } - Else - { - \PWRS = 0 - } - - // 500ms delay - Not used in coreboot - // Sleep (500) - Notify (BAT0, 0x81) - // Sleep (500) - Notify (ADP1, 0x80) -} - -Method(_Q0B, 0, NotSerialized) // Battery Connected -{ - // 500ms delay - Not used in coreboot - // Sleep (500) - Notify (BAT0, 0x81) - // Sleep (500) - Notify (BAT0, 0x80) -} diff --git a/src/ec/starlabs/it8987/acpi/battery.asl b/src/ec/starlabs/it8987/acpi/battery.asl deleted file mode 100644 index 8936701d1d..0000000000 --- a/src/ec/starlabs/it8987/acpi/battery.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (BAT0) -{ - Name (_HID, EISAID ("PNP0C0A")) - Name (_UID, 1) - Name (_PCL, Package () { \_SB }) - - // Battery Slot Status - Method (_STA, 0, Serialized) - { - If (ECWR & 0x02) - { - Return (0x1F) - } - Return (0x0F) - } - - // Default Static Battery Information - Name (BPKG, Package (13) - { - 1, // 0: Power Unit - 0xFFFFFFFF, // 1: Design Capacity - 0xFFFFFFFF, // 2: Last Full Charge Capacity - 1, // 3: Battery Technology(Rechargeable) - 0xFFFFFFFF, // 4: Design Voltage 10.8V - 0, // 5: Design capacity of warning - 0, // 6: Design capacity of low - 0x64, // 7: Battery capacity granularity 1 - 0, // 8: Battery capacity granularity 2 - "CN6613-2S3P", // 9: Model Number - "6UA3", // 10: Serial Number - "Real", // 11: Battery Type - "GDPT" // 12: OEM Information - }) - - Method (_BIF, 0, Serialized) - { - BPKG[1] = B1DC - BPKG[2] = B1FC - BPKG[4] = B1FV - If (B1FC) - { - BPKG[5] = B1FC / 10 - BPKG[6] = B1FC / 25 - BPKG[7] = B1DC / 100 - } - - Return (BPKG) - } - - Name (PKG1, Package (4) - { - 0xFFFFFFFF, // Battery State - 0xFFFFFFFF, // Battery Present Rate - 0xFFFFFFFF, // Battery Remaining Capacity - 0xFFFFFFFF, // Battery Present Voltage - }) - - Method (_BST, 0, Serialized) - { - - - PKG1[0] = B1ST & 0x07 - If (B1ST & 0x01) - { - PKG1[1] = B1CR - } - Else - { - PKG1[1] = B1CR - } - PKG1[2] = B1RC - PKG1[3] = B1VT - Return (PKG1) - } -} diff --git a/src/ec/starlabs/it8987/acpi/cmos.asl b/src/ec/starlabs/it8987/acpi/cmos.asl deleted file mode 100644 index 052094c2ea..0000000000 --- a/src/ec/starlabs/it8987/acpi/cmos.asl +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -OperationRegion (CMOS, SystemIO, 0x70, 0x02) -Field (CMOS, ByteAcc, NoLock, Preserve) -{ - NVRI, 8, - NVRD, 8 -} - -IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve) -{ - Offset (0x40), - KBBL, 8, // Keyboard backlight timeout - FNSW, 8, // Ctrl Fn Reverse (make keyboard Apple-like) - - Offset (0x7D), - FNLC, 8 // Current state of Fn Lock key. -} diff --git a/src/ec/starlabs/it8987/acpi/ec.asl b/src/ec/starlabs/it8987/acpi/ec.asl deleted file mode 100644 index 451cdf125a..0000000000 --- a/src/ec/starlabs/it8987/acpi/ec.asl +++ /dev/null @@ -1,379 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define ASL_PVOL_DEFOF_NUM 0xe8 - -Scope(\) -{ - // These fields come from the Global NVS area - Field (GNVS,AnyAcc,Lock,Preserve) - { - Offset(33), - B2SC, 8, // (33) Battery 2 Stored Capacity - Offset(36), - B2SS, 8 // (36) Battery 2 Stored Status - } -} - -Scope (\_SB) -{ - #include "hid.asl" -} - -Scope (\_SB.PCI0) -{ - // Add the entries for the PS/2 keyboard and mouse. - #include -} - -Scope (\_SB.PCI0.LPCB) -{ - // Include the definitions for accessing CMOS. - #include "cmos.asl" - - // Our embedded controller device. - Device (H_EC) - { - Name (_HID, EISAID ("PNP0C09")) // ACPI Embedded Controller - Name (_UID, 1) - Name (_GPE, EC_GPE_SCI) - - // ECDT (Embedded Controller Boot Resources Table) Check to correct - // ECAV flag in the beginning - Name(ECTK, 1) - Name(ECFG, 0) - Name(WIBT, 0) - Name(APST, 0) - - Name(ECON, 1) // AC debug - Name(BNUM, 0) // Number Of Batteries Present - Name(PVOL, ASL_PVOL_DEFOF_NUM) - Name(B1CC, 0) - Name(B2CC, 0) - - Name(B2ST, 0) - Name(CFAN, 0) - Name(CMDR, 0) - Name(DOCK, 0) - Name(EJET, 0) - Name(MCAP, 0) - Name(PLMX, 0) - Name(PECH, 0) - Name(PECL, 0) - Name(PENV, 0) - Name(PINV, 0) - Name(PPSH, 0) - Name(PPSL, 0) - Name(PSTP, 0) - Name(RPWR, 0) - Name(LIDS, 0) - Name(SLPC, 0) - Name(VPWR, 0) - Name(WTMS, 0) - Name(AWT2, 0) - Name(AWT1, 0) - Name(AWT0, 0) - Name(DLED, 0) - Name(IBT1, 0) - Name(ECAV, 1) // Support DPTF feature - Name(SPT2, 0) - Name(PB10, 0) - Name(IWCW, 0) - Name(IWCR, 0) - Name(BTEN, 0) - Mutex(ECMT, 0) - - Method (_CRS, 0, Serialized) - { - Name (BFFR, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 0x00, 0x01) - IO (Decode16, 0x66, 0x66, 0x00, 0x01) - }) - Return (BFFR) - } - - Method (_STA, 0, NotSerialized) - { - If ((ECON == 1)) - { - Return (0x0F) - } - - Return (0x00) - } - - Name (ECOK, Zero) - Method(_REG, 2, NotSerialized) - { - If ((Arg0 == 0x03) && (Arg1 == 0x01)) - { - ECOS = 1 - ECAV = 1 - - // Unconditionally fix up the Battery and Power State. - - // Initialize the Number of Present Batteries. - // 1 = Real Battery 1 is present - // 2 = Real Battery 2 is present - // 3 = Real Battery 1 and 2 are present - BNUM = 0 - BNUM |= ((ECRD (RefOf (ECWR)) & 0x02) >> 1) - - // Save the current Power State for later. - // Store (PWRS, Local0) - - // Initialize the Power State. - // BNUM = 0 = Virtual Power State - // BNUM > 0 = Real Power State - If (BNUM == 0x00) - { - \PWRS = ECRD (RefOf (VPWR)) - } - Else - { - \PWRS = (ECRD (RefOf (ECWR)) & 0x01) - } - PNOT() - - /* Initialize LID switch state */ - \LIDS = LIDS - } - - // Flag that the OS supports ACPI. - \_SB.PCI0.LPCB.H_EC.ECOS = 1 - } - - Name (S3OS, Zero) - Method (PTS, 1, Serialized) - { - Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) - If (ECOK) { - S3OS = ECOS - } - \_SB.PCI0.LPCB.H_EC.ECOS = 0 - } - - Method (WAK, 1, Serialized) - { - Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) - If (ECOK) { - ECOS = S3OS - } - \_SB.PCI0.LPCB.H_EC.ECOS = 1 - } - - OperationRegion (SIPR, SystemIO, 0xB2, 0x1) - Field (SIPR, ByteAcc, Lock, Preserve) - { - SMB2, 8 - } - - // EC RAM fields - OperationRegion(ECF2, EmbeddedControl, 0, 0xFF) - Field (ECF2, ByteAcc, Lock, Preserve) - { - XXX0, 8, // EC Firmware main- version number. - XXX1, 8, // EC Firmware sub- version number. - XXX2, 8, // EC Firmware test- version number. - - Offset(0x06), - SKID, 8, // SKU ID - - Offset(0x11), - KBCD, 8, // Key / Touch Pad disable/enable bit - ECOS, 8, // Enter OS flag - HDAO, 8, - ECHK, 8, // Hot keys flag - - Offset(0x18), - KLBS, 8, // Keyboard backlight begin. - KLBE, 8, // Keyboard backlight status. - - Offset(0x1A), - KBLT, 8, // Keyboard Backlight Timeout - PWPF, 8, // Power Profile - - Offset(0x1E), - BTHP,8, // Health Battery Percentage - - Offset(0x20), - RCMD, 8, // Same function as IO 66 port to send EC command - RCST, 8, // Report status for the result of command execution - - Offset(0x2C), - FNST, 8, // FN LOCK key status. - - Offset(0x3F), - SFAN, 8, // Set Fan Speed. - BTMP, 16, // Battery Temperature. - BCNT, 16, // Battery Cycle Count. - FRMP, 16, // Fan Current Speed. - - Offset(0x60), - TSR1, 8, // Thermal Sensor Register 1 [CPU VR (IMVP) Temp on RVP] - TSR2, 8, // Thermal Sensor Register 2 [Heat exchanger fan temp on RVP] - TER4, 8, // Thermal Sensor Register 3 (skin temperature) - - Offset(0x63), - TSI,4, // [0..3] 0 = SEN1 - CPU VR temperature sensor - // 1 = SEN2 - Heat Exchanger temperature sensor - // 2 = SEN3 - Skin temperature sensor - // 3 = SEN4 - Ambient temperature sensor - // 4 = SEN5 - DIMM temperature sensor [IR sensor 1 on WSB] - // 5 = SEN6 - not used on RVP - HYST, 4, // [4..7] - Hysteresis in degC. - TSHT, 8, // Thermal Sensor (N) high trip point(set default value =70) - TSLT, 8, // Thermal Sensor (N) low trip point (set default value =70) - TSSR, 8, // TSSR- thermal sensor status register (set bit2 =1) - // BIT0:SEN1 - CPU VR Temp Sensor Trip Flag - // BIT1:SEN2 - Fan Temp Sensor Trip Flag - // BIT2:SEN3 - Skin Temp Sensor Trip Flag - // BIT3:SEN4 - Ambient Temp Sensor Trip Flag - // BIT4:Reserved - // BIT5:Reserved - // BIT6:Reserved - // BIT7:Reserved - CHGR, 16, // Charge Rate - - Offset(0x70), - CPTM, 8, // CPU Temperature - - Offset(0x72), - TER2, 8, // Charger Temperature, Charger thermistor support - - Offset(0x7F), - LSTE, 1, // Lid feature - // BIT0LID GPI - , 7, // Reserved - - Offset(0x80), - ECWR, 8, // AC & Battery status - XX10, 8, // Battery#1 Model Number Code - XX11, 16, // Battery#1 Serial Number - B1DC, 16, // Battery#1 Design Capacity - B1FV, 16, // Battery#1 Design Voltage - B1FC, 16, // Battery#1 Last Full Charge Capacity - XX15, 16, // Battery#1 Trip Point - B1ST, 8, // Battery#1 State - B1CR, 16, // Battery#1 Present Rate - B1RC, 16, // Battery#1 Remaining Capacity - B1VT, 16, // Battery#1 Present Voltage - BPCN, 8, // Battery#1 Remaining percentage - - // USB Type C Mailbox Interface// PPM->OPM Message In - Offset(0xc0), - MGI0, 8, - MGI1, 8, - MGI2, 8, - MGI3, 8, - MGI4, 8, - MGI5, 8, - MGI6, 8, - MGI7, 8, - MGI8, 8, - MGI9, 8, - MGIA, 8, - MGIB, 8, - MGIC, 8, - MGID, 8, - MGIE, 8, - MGIF, 8, - - // USB Type C Mailbox Interface// OPM->PPM Message Out - MGO0, 8, - MGO1, 8, - MGO2, 8, - MGO3, 8, - MGO4, 8, - MGO5, 8, - MGO6, 8, - MGO7, 8, - MGO8, 8, - MGO9, 8, - MGOA, 8, - MGOB, 8, - MGOC, 8, - MGOD, 8, - MGOE, 8, - MGOF, 8, - - // USB Type C UCSI DATA Structure. - VER1, 8, - VER2, 8, - RSV1, 8, - RSV2, 8, - - // PPM->OPM CCI indicator - CCI0, 8, - CCI1, 8, - CCI2, 8, - CCI3, 8, - - // OPM->PPM Control message - CTL0, 8, - CTL1, 8, - CTL2, 8, - CTL3, 8, - CTL4, 8, - CTL5, 8, - CTL6, 8, - CTL7, 8, - - Offset(0xF0), - , 3,// BIT0 .. BIT2 Reserved - TPCC, 1,// BIT3 TypeC connection bit - , 2,// BIT4 .. BIT5 Reserved - DRMD, 1,// Bit6 Dual Role Mode. 0->DFP: Host mode; 1->UFP: Device Mode. - , 1,// BIT7 Reserved - } - - Method (ECMD, 0, Serialized) - { - } - - Method (ECWT, 2, Serialized,,, {IntObj, FieldUnitObj}) - { - Local0 = Acquire (ECMT, 1000) - If (Local0 == 0x00) - { - If (ECAV) - { - // Execute write to Embedded Controller - Arg1 = Arg0 - } - Release (ECMT) - } - } - - Method (ECRD, 1, Serialized, 0, IntObj, FieldUnitObj) - { - Local0 = Acquire (ECMT, 1000) - If (Local0 == 0) - { - If (ECAV) - { - // Execute read from Embedded Controller - Local1 = DerefOf (Arg0) - Release (ECMT) - Return (Local1) - } - Else - { - Release (ECMT) - } - } - Return (Local1) - } - - // Include the other parts of the Embedded Controller ASL. - #include "keyboard.asl" - #include "battery.asl" - #include "ac.asl" - #include "lid.asl" - - // Method(_Q45) // SMM Mode - Not used in coreboot - // { - // SMB2 = 0xC1 - // } - } -} diff --git a/src/ec/starlabs/it8987/acpi/hid.asl b/src/ec/starlabs/it8987/acpi/hid.asl deleted file mode 100644 index 25e3cd2ec9..0000000000 --- a/src/ec/starlabs/it8987/acpi/hid.asl +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (HIDD) -{ - Name (_HID, "INT33D5") - Name (HBSY, Zero) - Name (HIDX, Zero) - Name (HMDE, Zero) - Name (HRDY, Zero) - Name (BTLD, Zero) - Name (BTS1, Zero) - Name (HEB1, 0x3003) - - Method (_STA, 0, Serialized) // _STA: Status - { - If ((OSYS >= 0x07DD)) - { - Return (0x0F) - } - Else - { - Return (Zero) - } - } - - Method (HDDM, 0, Serialized) - { - Store ("-----> HDDM", Debug) - Name (DPKG, Package (0x04) - { - 0x11111111, - 0x22222222, - 0x33333333, - 0x44444444 - }) - Return (DPKG) - } - - Method (HDEM, 0, Serialized) - { - Store ("-----> HDEM", Debug) - HBSY = Zero - If ((HMDE == Zero)) - { - Return (HIDX) - } - Return (HMDE) - } - - Method (HDMM, 0, Serialized) - { - Store ("-----> HDMM", Debug) - Return (HMDE) - } - - Method (HDSM, 1, Serialized) - { - Store ("-----> HDSM", Debug) - HRDY = Arg0 - } - - Method (HPEM, 1, Serialized) - { - Store ("-----> HPEM", Debug) - HBSY = One - HIDX = Arg0 - - Notify (HIDD, 0xC0) - Local0 = Zero - While ((Local0 < 0xFA) && HBSY) - { - Sleep (0x04) - Local0++ - } - - If (HBSY == One) - { - HBSY = Zero - HIDX = Zero - Return (One) - } - Else - { - Return (Zero) - } - } - - Method (BTNL, 0, Serialized) - { - Store ("-----> BTNL", Debug) - If (CondRefOf (\_SB.PWRB.PBST)) - { - \_SB.PWRB.PBST = Zero - Notify (PWRB, One) // Device Check - } - - BTLD = One -// If ((AEAB == One)) -// { - BTS1 = 0x1F - \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } -// Else -// { -// BTS1 = Zero -// } - } - - Method (BTNE, 1, Serialized) - { - Store ("-----> BTNE", Debug) -// If ((AEAB == One)) -// { - BTS1 = ((Arg0 & 0x1E) | One) - \_SB.PCI0.LPCB.H_EC.ECWT (BTS1, RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } - } - - Method (BTNS, 0, Serialized) - { - Store ("-----> BTNS", Debug) -// If ((AEAB == One)) -// { - BTS1 = \_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.BTEN)) -// } - Return (BTS1) - } - - Method (BTNC, 0, Serialized) - { - Store ("-----> BTNC", Debug) -// If ((AEAB == One)) -// { - Return (0x1F) -// } -// Else -// { -// Return (Zero) -// } - } - - Name (HEB2, Zero) - Method (HEBC, 0, Serialized) - { - Store ("-----> HEBC", Debug) -// If ((AHDB == One)) -// { -// Return (\HEB1) -// } -// Else -// { - Return (Zero) -// } - } - - Method (H2BC, 0, Serialized) - { - Store ("-----> H2BC", Debug) -// If ((AHDB == One)) -// { -// Return (\HEB1) -// } -// Else -// { - Return (Zero) -// } - } - - Method (HEEC, 0, Serialized) - { - Store ("-----> HEEC", Debug) -// If ((AHDB == One)) -// { - Return (HEB2) /* \_SB_.HIDD.HEB2 */ -// } -// Else -// { -// Return (Zero) -// } - } - - Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method - { - If ((Arg0 == ToUUID ("eeec56b3-4442-408f-a792-4edd4d758054"))) - { - If ((One == ToInteger (Arg1))) - { - Switch (ToInteger (Arg2)) - { - Case (Zero) - { - Return (Buffer (0x02) - { - 0xFF, 0x03 - }) - } - Case (One) - { - BTNL () - } - Case (0x02) - { - Return (HDMM ()) - } - Case (0x03) - { - HDSM (DerefOf (Arg3 [Zero])) - } - Case (0x04) - { - Return (HDEM ()) - } - Case (0x05) - { - Return (BTNS ()) - } - Case (0x06) - { - BTNE (DerefOf (Arg3 [Zero])) - } - Case (0x07) - { - Return (HEBC ()) - } - Case (0x08) - { - } - Case (0x09) - { - Return (H2BC ()) - } - } - } - } - - Return (Buffer (One) - { - 0x00 - }) - } -} - -Method (PWPR, 0, Serialized) -{ - Notify (HIDD, 0xCE) -} - -Method (PWRR, 0, Serialized) -{ - Notify (HIDD, 0xCF) -} diff --git a/src/ec/starlabs/it8987/acpi/lid.asl b/src/ec/starlabs/it8987/acpi/lid.asl deleted file mode 100644 index 22e8eeb818..0000000000 --- a/src/ec/starlabs/it8987/acpi/lid.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (LID0) -{ - Name (_HID, EisaId ("PNP0C0D")) - - Method (_STA, 0, NotSerialized) - { - DEBUG = "---> IT8987 LID: _STA" - Return (0x0F) - } - - Method (_PSW, 1, NotSerialized) - { - DEBUG = Concatenate ("---> IT8987 LID: _PSW", ToHexString(Arg0)) - } - - Method (_LID, 0, NotSerialized) - { - DEBUG = "---> IT8987 LID: _LID" - If (\_SB.PCI0.LPCB.H_EC.ECRD (RefOf (\_SB.PCI0.LPCB.H_EC.LSTE)) == 0x01) - { - Local0 = 1 - } - else - { - Local0 = 0 - } - Return (Local0) - } -} - -Method (_Q0C, 0, NotSerialized) // Lid close event -{ - DEBUG = "---> IT8987 LID: Q0C (close event)" - LIDS = 0 - \LIDS = LIDS - Notify (LID0, 0x80) -} - -Method (_Q0D, 0, NotSerialized) // Lid open event -{ - DEBUG = "---> IT8987 LID: Q0D (open event)" - LIDS = 1 - \LIDS = LIDS - Notify (LID0, 0x80) -} diff --git a/src/ec/starlabs/it8987/acpi/thermal.asl b/src/ec/starlabs/it8987/acpi/thermal.asl deleted file mode 100644 index 6bf25bf7b6..0000000000 --- a/src/ec/starlabs/it8987/acpi/thermal.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Method(_QF0) // Thermal event. -{ - If (LEqual (DBGS, 0x00)) - { - /* Only handle the numerous thermal events if we are */ - /* NOT doing ACPI Debugging. */ - If (CondRefOf (\_TZ.TZ01)) - { - Notify (\_TZ.TZ01, 0x80) - } - } -} diff --git a/src/ec/starlabs/it8987/chip.h b/src/ec/starlabs/it8987/chip.h deleted file mode 100644 index a940a46acb..0000000000 --- a/src/ec/starlabs/it8987/chip.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _EC_STARLABS_IT8987_CHIP_H -#define _EC_STARLABS_IT8987_CHIP_H - -struct ec_starlabs_it8987_config { - u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ -}; - -#endif /* _EC_STARLABS_IT8987_CHIP_H */ diff --git a/src/ec/starlabs/it8987/ec.c b/src/ec/starlabs/it8987/ec.c deleted file mode 100644 index b555d28b84..0000000000 --- a/src/ec/starlabs/it8987/ec.c +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -#include "ec.h" -#include "chip.h" - -u16 it8987_get_version(void) -{ - return (ec_read(0x00) << 8) | ec_read(0x01); -} - -static void it8987_init(struct device *dev) -{ - if (!dev->enabled) - return; - - /* - * The address/data IO port pair for the IT8987 EC are configurable - * through the EC domain and are fixed by the EC's firmware blob. If - * the value(s) passed through the "dev" structure don't match the - * expected values then output severe warnings. - */ - if (dev->path.pnp.port != IT8987E_FIXED_ADDR) { - printk(BIOS_ERR, "IT8987: Incorrect ports defined in devicetree.cb.\n"); - printk(BIOS_ERR, "IT8987: Serious operational issues will arise.\n"); - return; - } - - u8 chipid1 = pnp_read_index(dev->path.pnp.port, IT8987_CHIPID1); - u8 chipid2 = pnp_read_index(dev->path.pnp.port, IT8987_CHIPID2); - if (chipid1 != IT8987_CHIPID1_VAL || chipid2 != IT8987_CHIPID2_VAL) { - printk(BIOS_DEBUG, "IT8987: Device not found.\n"); - return; - } - - printk(BIOS_DEBUG, "IT8987: Initializing keyboard.\n"); - pc_keyboard_init(NO_AUX_DEVICE); - - /* Enable the keyboard backlight support. */ - ec_write(0x18, 0xaa); - ec_write(0x19, 0xdd); - - /* Set the timeout for the keyboard backlight. */ - ec_write(ECRAM_KBL_TIMEOUT, get_uint_option("kbl_timeout", 0)); - - /* - * Set the correct state for the Ctrl Fn Reverse option. This - * swaps the Ctrl and Fn keys to make it like an Apple keyboard. - */ - ec_write(ECRAM_FN_CTRL_REVERSE, get_uint_option("fn_ctrl_swap", 0)); - /* - * Copy the stored state of the fn_lock_state CMOS variable to the - * corresponding location within the EC RAM. - */ - ec_write(ECRAM_FN_LOCK_STATE, get_uint_option("fn_lock_state", 0)); -} - -static struct device_operations ops = { - .init = it8987_init, - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, -}; - -static struct pnp_info pnp_dev_info[] = { - { NULL, 0, 0, 0, } -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations ec_starlabs_it8987_ops = { - CHIP_NAME("ITE IT8987 EC") - .enable_dev = enable_dev -}; diff --git a/src/ec/starlabs/it8987/ec.h b/src/ec/starlabs/it8987/ec.h deleted file mode 100644 index c6d5a7a28e..0000000000 --- a/src/ec/starlabs/it8987/ec.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * EC communication interface for ITE IT8987 Embedded Controller. - */ - -#ifndef _EC_STARLABS_IT8987_H -#define _EC_STARLABS_IT8987_H - -/* - * Define the expected value of the PNP base address that is fixed through - * the BADRSEL register controlled within the EC domain by the binary blob. - */ -#define IT8987E_FIXED_ADDR 0x4e - -/* Logical device number (LDN) assignments. */ -#define IT8987E_SP1 0x01 /* Com1 */ -#define IT8987E_SP2 0x02 /* Com2 */ -#define IT8987E_SWUC 0x04 /* System Wake-Up */ -#define IT8987E_KBCM 0x05 /* PS/2 mouse */ -#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ -#define IT8987E_IR 0x0a /* Consumer IR */ -#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ -#define IT8987E_RTCT 0x10 /* RTC-like Timer */ -#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ -#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ -#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ -#define IT8987E_PECI 0x14 /* Platform EC Interface */ -#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ -#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ -#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ - -/* Host domain registers. */ -#define IT8987_CHIPID1 0x20 /* Device ID register 1 */ -#define IT8987_CHIPID2 0x21 /* Device ID register 2 */ - -/* IT8987 chip ID byte values. */ -#define IT8987_CHIPID1_VAL 0x89 -#define IT8987_CHIPID2_VAL 0x87 - -/* EC RAM offsets. */ -#define ECRAM_KBL_TIMEOUT 0x07 -#define ECRAM_FN_CTRL_REVERSE 0x08 -#define ECRAM_FN_LOCK_STATE 0x2C - -u16 it8987_get_version(void); - -#endif diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig new file mode 100644 index 0000000000..67582ac4a7 --- /dev/null +++ b/src/ec/starlabs/merlin/Kconfig @@ -0,0 +1,61 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_STARLABS_ITE + bool + select EC_ACPI + help + Interface to ITE embedded controller principally in Star Labs notebooks. + Works with closed-source ITE firmware versions: + TGL - 1.00 or later + CML - 1.04 or later + KBL - 3.12 or later + And open-source Merlin firmware version 1.00 or later + +config EC_STARLABS_NEED_ITE_BIN + bool + depends on EC_STARLABS_ITE + help + Select if the mainboard requires EC firmware in the main flash chip. + +config EC_STARLABS_ADD_ITE_BIN + bool "Add Star Labs EC binary file" + default n + depends on EC_STARLABS_NEED_ITE_BIN + help + Select to add an EC firmware binary into the coreboot image. EC firmware + is necessary, flashing a coreboot image without EC firmware will render + your laptop unusable. + +config EC_STARLABS_ITE_BIN_PATH + string "Star Labs EC binary file path" + depends on EC_STARLABS_ADD_ITE_BIN + +config EC_STARLABS_KBL_LEVELS + bool + default n + depends on EC_STARLABS_ITE + help + Select if the mainboard supports multiple levels of brightness for the keyboard. + +config EC_STARLABS_FAN + bool + default n + depends on EC_STARLABS_ITE + help + Select if the mainboard has a fan. + +config EC_STARLABS_MERLIN + bool "Use open-source Merlin EC Firmware" + default n + depends on EC_STARLABS_ITE + help + Use open source embedded controller firmware. Both firmwares have the + same features but differ in licensing and compilers. + +config EC_VARIANT_DIR + string + default "merlin" if EC_STARLABS_MERLIN + +config EC_GPE_SCI + hex + default 0x50 diff --git a/src/ec/starlabs/merlin/Makefile.inc b/src/ec/starlabs/merlin/Makefile.inc new file mode 100644 index 0000000000..e6721f5e93 --- /dev/null +++ b/src/ec/starlabs/merlin/Makefile.inc @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_EC_STARLABS_ITE),y) + +PHONY+=add_ite_fw +INTERMEDIATE+=add_ite_fw + +EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR)) +CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR) + +all-y += ec.c + +ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y) +ifeq ($(CONFIG_EC_STARLABS_ADD_ITE_BIN),y) +add_ite_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_EC_STARLABS_ITE_BIN_PATH) -u +else +files_added:: warn_no_ite_fw + +PHONY+=warn_no_ite_fw +warn_no_ite_fw: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the ITE EC Firmware.\n" + printf "Do not flash this image. Your laptop's power button\n" + printf "may not respond when you press it.\n\n" +endif +endif +endif diff --git a/src/ec/starlabs/merlin/acpi/ac.asl b/src/ec/starlabs/merlin/acpi/ac.asl new file mode 100644 index 0000000000..808d5754ab --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/ac.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Method (_STA) + { + Return (0x0F) + } + Method (_PSR, 0) + { + PWRS = ECPS & 0x01 + Return(PWRS) + } + Method (_PCL, 0) + { + Return ( + Package() { _SB } + ) + } +} diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl new file mode 100644 index 0000000000..b428458b2b --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/battery.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EisaId("PNP0C0A")) + Name (_UID, 0) + Method (_STA, 0, NotSerialized) + { + // Battery Status + // 0x80 BIT1 0x01 = Present + // 0x80 BIT1 0x00 = Not Present + If(ECPS & 0x02) + { + Return(0x1F) + } + Return(0x0F) + } + Name (BPKG, Package(13) + { + 1, // 0: Power Unit + 0xFFFFFFFF, // 1: Design Capacity + 0xFFFFFFFF, // 2: Last Full Charge Capacity + 1, // 3: Battery Technology(Rechargeable) + 0xFFFFFFFF, // 4: Design Voltage 10.8V + 0, // 5: Design capacity of warning + 0, // 6: Design capacity of low + 100, // 7: Battery capacity granularity 1 + 0, // 8: Battery capacity granularity 2 + "597077-3S", // 9: Model Number + "3ICP6/70/77", // 10: Serial Number + "Real", // 11: Battery Type + "DGFGE" // 12: OEM Information + }) + Method (_BIF, 0, Serialized) + { + BPKG[1] = B1DC + BPKG[2] = B1FC + BPKG[4] = B1DV + If(B1FC) + { + BPKG[5] = B1FC / 10 + BPKG[6] = B1FC / 100 + BPKG[7] = B1DC / 100 + } + Return(BPKG) + } + Name (PKG1, Package (4) + { + 0xFFFFFFFF, // Battery State + 0xFFFFFFFF, // Battery Present Rate + 0xFFFFFFFF, // Battery Remaining Capacity + 0xFFFFFFFF, // Battery Present Voltage + }) + Method (_BST, 0, NotSerialized) + { + PKG1[0] = (B1ST & 0x07) + PKG1[1] = B1PR + PKG1[2] = B1RC + PKG1[3] = B1PV + Return(PKG1) + } + Method (_PCL, 0, NotSerialized) + { + Return ( + Package() { _SB } + ) + } +} diff --git a/src/ec/starlabs/merlin/acpi/cmos.asl b/src/ec/starlabs/merlin/acpi/cmos.asl new file mode 100644 index 0000000000..f4468f75e4 --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/cmos.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (CMOS, SystemIO, 0x70, 0x2) +Field (CMOS, ByteAcc, NoLock, Preserve) +{ + IND1, 8, + DAT1, 8, +} + +IndexField (IND1, DAT1, ByteAcc, NoLock, Preserve) +{ + Offset (0x4b), + KLTC, 8, // Keyboard Backlight Timeout + FCLS, 8, // Ctrl Fn Reverse (make keyboard Apple-like) + MXCH, 8, // Max Charge Level + FNMD, 8, // Fan Mode +} + +OperationRegion (CMS2, SystemIO, 0x72, 0x2) +Field (CMS2, ByteAcc, NoLock, Preserve) +{ + IND2, 8, + DAT2, 8, +} + +IndexField (IND2, DAT2, ByteAcc, NoLock, Preserve) +{ + Offset (0x80), + FLKC, 8, // Function Lock State + TPLC, 8, // Trackpad State + KLBC, 8, // Keyboard Backlight Brightness + KLSC, 8, // Keyboard Backlight State +} diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl new file mode 100644 index 0000000000..c540c03d7a --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/ec.asl @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ubtc.asl" + +Scope (\_SB.PCI0.LPCB) +{ + #include "cmos.asl" + + Device (EC) + { + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0x01) + Name (_GPE, CONFIG_EC_GPE_SCI) + Name (ECAV, 0x00) + Name (ECTK, 0x01) + Name (B2ST, 0x00) + Name (CFAN, 0x00) + Name (CMDR, 0x00) + Name (DOCK, 0x00) + Name (PLMX, 0x00) + Name (PECH, 0x00) + Name (PECL, 0x00) + Name (PENV, 0x00) + Name (PINV, 0x00) + Name (PPSH, 0x00) + Name (PPSL, 0x00) + Name (PSTP, 0x00) + Name (RPWR, 0x00) + Name (VPWR, 0x00) + Name (WTMS, 0x00) + Name (AWT2, 0x00) + Name (AWT1, 0x00) + Name (AWT0, 0x00) + Name (DLED, 0x00) + Name (SPT2, 0x00) + Name (PB10, 0x00) + Name (IWCW, 0x00) + Name (IWCR, 0x00) + Name (PVOL, 0x00) + Mutex (ECMT, 0x00) + + Name(BFFR, ResourceTemplate() + { + IO(Decode16, 0x0062, 0x0062, 0x00, 0x01) + IO(Decode16, 0x0066, 0x0066, 0x00, 0x01) + }) + + Method (_CRS, 0, Serialized) + { + + Return(BFFR) + } + + Method (_STA, 0, NotSerialized) + { + \LIDS = 0x03 + Return (0x0F) + } + + OperationRegion (SIPR, SystemIO, 0xB2, 0x1) + Field (SIPR, ByteAcc, Lock, Preserve) { + SMB2, 8 + } + + #include "emem.asl" + + // ECRD (Embedded Controller Read Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: + // Arg0 = Object to Read + // + // Return Value: + // Read Value + // + Method (ECRD, 1, Serialized, 0, IntObj, FieldUnitObj) + { + // + // Check for ECDT support, set ECAV to One if ECDT is supported by OS + // Only check once at beginning since ECAV might be clear later in certain conditions + // + If (ECTK) { + If (_REV >= 0x02) { + ECAV = 0x01 + } + ECTK = 0x00 // Clear flag for checking once only + } + + Local0 = Acquire (ECMT, 1000) // Save Acquired Result + If (Local0 == 0x00) // Check for Mutex Acquisition + { + If (ECAV) { + Local1 = DerefOf (Arg0) // Execute Read from EC + Release (ECMT) + Return (Local1) + } Else { + Release (ECMT) + } + } + Return(0) // Return in case Arg0 doesn't exist + } + + // ECWR (Embedded Controller Write Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: + // Arg0 = Value to Write + // Arg1 = Object to Write to + // + // Return Value: + // None + // + Method (ECWR, 2, Serialized,,,{IntObj, FieldUnitObj}) + { + Local0 = Acquire (ECMT, 1000) // Save Acquired Result + If (Local0 == 0x00) // Check for Mutex Acquisition + { + If (ECAV) { + Arg1 = Arg0 // Execute Write to EC + Local1 = 0x00 + While (1) { + If (Arg0 == DerefOf (Arg1)) { + Break + } + Sleep (1) + Arg1 = Arg0 + Local1 += 1 + If (Local1 == 0x03) { + Break + } + } + } + Release (ECMT) + } + } + + #include "ac.asl" + #include "battery.asl" + #include "events.asl" + #include "lid.asl" + #include "typec.asl" + + Method (_REG, 2, NotSerialized) + { + If ((Arg0 == 0x03) && (Arg1 == 0x01)) + { + // Load EC Driver + ECAV = 0x01 + + // Initialise the Lid State + \LIDS = LSTE + + // Initialise the OS State + OSFG = 0x01 + + // Initialise the Power State + PWRS = (ECRD (RefOf(ECPS)) & 0x01) + + // Inform the platform code + PNOT() + } + } + } +} diff --git a/src/ec/starlabs/merlin/acpi/hid.asl b/src/ec/starlabs/merlin/acpi/hid.asl new file mode 100644 index 0000000000..5449807e0f --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/hid.asl @@ -0,0 +1,371 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) // HID Device +{ + Name (_HID, "INTC1051") // Intel Ultrabook HID Platform Event Driver. + Name (HBSY, 0) // HID Busy + Name (HIDX, 0) // HID Index + Name (HMDE, 0) // HID Mode + Name (HRDY, 0) // HID Ready + Name (BTLD, 0) // Button Driver Loaded + Name (BTS1, 0) // Button Status + Method (_STA, 0, Serialized) // Status Method + { + // Usually, ACPI will check if the OS is 0x07DD (2013 - Windows 8.1ish) + // before showing the HID event filter. Seeing as we use Linux we show + // it regardless. + Return (0x0F) + } + // + // HID Driver Descriptor Method - Called by HID Driver during initialization + // to obtain HID Descriptor information. + // + // Input: + // None + // + // Output: + // Package containing a complete HID Descriptor information. + // + Name(DPKG, Package(4) + { + 0x11111111, + 0x22222222, + 0x33333333, + 0x44444444, + }) + Method (HDDM, 0, Serialized) + { + Return(DPKG) + } + // + // HID Driver Event Method - Called by HID Driver to get the specific + // platform event. + // + // Input: + // None + // + // Output: + // Mode 0 = Index of HID Input Report, per pre-defined Table. + // Mode 1 = Package containing a complete HID Input Report. + // + Method (HDEM, 0, Serialized) + { + HBSY = 0x00 // Clear HID Busy. + // Simple Mode is hardcoded for now. Return Simple Mode HID Index Value. + If (HMDE == 0x00) + { + Return(HIDX) + } + Return(HMDE) + } + // + // HID Driver Mode Method - Called by HID Driver during initialization to get + // the platform mode of operation. + // + // Input: + // None + // + // Output: + // 0 = Simple Mode. + // 1 = Advanced Mode. + // + Method (HDMM, 0, Serialized) + { + Return(HMDE) // Return Mode of operation. + } + // + // HID Driver Status Method - called by HID Driver to report platform readiness status. + // + // Input: Driver Status. + // 0 = Driver Unloaded. + // 1 = Driver Loaded and Ready. + // + // Output: None + // + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 // Store HID Ready Status. + // Eventually code will communicate to platform the Driver status (enabled/disabled). + } + // + // HID Platform Event Method - called by Platform to communicate HID Event to Driver. + // + // Input: + // Mode 0 = Index of HID Event. + // Mode 1 = Package containing a complete HID Report. + // + Method (HPEM, 1, Serialized) // HID Platform Event Method. + { + HBSY = 0x01 // Set HID Busy. + // Simple Mode is hardcoded for now. Simply store HID Index value. + If (HMDE == 0x00) + { + HIDX = Arg0 + } Else { + HIDX = Arg0 + } + Notify (\_SB.HIDD, 0xC0) // Notify Driver to get HID Event. + Local0 = 0x00 // Initialize Local0 as a timeout counter. + While((Local0 < 250) && HBSY) // Wait <= 1 second for Driver to ACK success. + { + Sleep (4) // Delay 4 ms. + Local0++ // Increment Timeout. + } + If (HBSY == 0x01) // Failure? + { + HBSY = 0x00 // Yes. Clear HID Busy Flag. + HIDX = 0x00 // Set HID Simple Mode Index = 0 = Undefined. + Return (0x01) // Return Failure. + } Else { + Return (0x00) // Return Success. + } + } + // + // HID Button Load Method - called by Platform to say HID driver is capable of receiving + // 5-button array notifications. + // + // Input: + // None + // + // Output: + // None + // + Method (BTNL, 0, Serialized) // HID Button Enable/Disable Method + { + BTS1 = 0x00 + } + // + // HID Button Enable/Disable Method - called by Platform to disable/enable notification based + // on button press + // + // Input: + // Arg0 = Bit mask of buttons to Enable or Disable: + // 1 == Button should be Enabled + // 0 == Button should be Disabled + // Bits[0]: Power Button N/A to disable + // Bits[1]: Windows Button + // Bits[2]: Volume Up Button + // Bits[3]: Volume Down Button + // Bits[4]: Rotation Lock Button + // Bits[5:31]: Reserved + // + // Output: + // None + // + Method (BTNE, 1, Serialized) // HID Button Enable/Disable Method + { + Return (BTS1) + } + // + // HID Button Status - called by Platform to get what buttons are enabled and disabled + // + // Input: + // None + // + // Output: + // Bit mask of buttons' current status: + // 1 == Button is Enabled + // 0 == Button is Disabled + // Bits[0]: Power Button N/A to disable + // Bits[1]: Windows Button + // Bits[2]: Volume Up Button + // Bits[3]: Volume Down Button + // Bits[4]: Rotation Lock Button + // Bits[5:31]: Reserved + // + Method (BTNS, 0, Serialized) + { + Return (BTS1) + } + // + // HID Button Capabilities Method - called by Platform to determine what buttons are supported + // + // Input: + // None + // + // Output: + // Bit mask of buttons supported: + // 1 == Button is Supported + // 0 == Button is not Supported + // Bits[0]: Power Button (Must be 1) + // Bits[1]: Windows Button + // Bits[2]: Volume Up Button + // Bits[3]: Volume Down Button + // Bits[4]: Rotation Lock Button + // Bits[5:31]: Reserved + // + Method (BTNC, 0, Serialized) // HID Button Capabilities Method + { + Return(0x1F) + } + + // + // HEBC: HID Event Base Capabilities [31:0]- To specify the base button capabilities supported + // on platform by returning a ULONG value with the following bit level definition + // + // Input: + // None + // + // 0 = Button not supported + // 1 = Button supported + // Output: + // Bits [0] - Windows Button (Windows 8.1 supported), Rotation Lock (Windows 8.1 supported): + // Num Lock, Home, End, Page Up, Page Down + // Bits [1] - Wireless Radio Control + // Bits [2] - System Power Down (Windows 8.1 supported) + // Bits [3] - System Hibernate + // Bits [4] - System Sleep/ System Wake + // Bits [5] - Scan Next Track + // Bits [6] - Scan Previous Track + // Bits [7] - Stop + // Bits [8] - Play/Pause + // Bits [9] - Mute + // Bits [10] - Volume Increment (Windows 8.1 supported) + // Bits [11] - Volume Decrement (Windows 8.1 supported) + // Bits [12] - Display Brightness Increment + // Bits [13] - Display Brightness Decrement + // Bits [14] - Lock Tablet + // Bits [15] - Release Tablet + // Bits [16] - Toggle Bezel + // Bits [17] - 5 button array (Windows 10 supported): + // (Power, Windows Home, Volume Up, Volume Down, Rotation Lock) + // Bits [18] - Button 1 + // Bits [19] - Button 2 + // Bits [20] - Button 3 + // Bits [21] - Button 4 + // Bits [22] - Button 5 + // Bits [23-31] - reserved + // + // Modify below table if the target platform has different capabilities. Each bit + // corresponding the above table definition. + // + Name (HEB2, 0) // Extended 32bit capability definition for future enhancements. + Method (HEBC, 0, Serialized) { + // It's possible to return (\HEB1) + Return (0x00) + } + Method (H2BC, 0, Serialized) { + // It's possible to return (\HEB1) + Return (0x00) + } + // + // HEEC- Hid Event Extended Capabilities [32:63] + // + Method (HEEC, 0, Serialized) { + // It's possible to return (\HEB2) + Return(0x00) + } + // + // HIDD _DSM + // _DSM : Device Specific Method for the Windows Compatible Button Array. + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) + { + // Compare passed in UUID to supported UUID. + If (Arg0 == ToUUID ("EEEC56B3-4442-408F-A792-4EDD4D758054")) + { + If (0x01 == ToInteger(Arg1)) // Revision 1. + { + Switch (ToInteger(Arg2)) // Switch to Function Index. + { + // + // Function 0, Query of supported functions. + // + Case (0x00) + { + Return (Buffer() {0xFF, 0x03}) // Total 9 function indices are supported including this. + } + // + // Function 1, BTNL. Button Load Method. No Input/Output. + // + Case (0x01) + { + BTNL() + } + // + // Function 2, HDMM. HID Driver Mode Method. + // Input:None + // Output:HDMM output. See HDMM + // + Case (0x02) + { + Return (HDMM()) + } + // + // Function 3, HDSM. HID Driver Status Method. + // Input: 0 - The driver is not available. 1 - The driver is available. + // Output: None + // + Case (0x03) + { + HDSM (DeRefOf(Arg3[0])) + } + // + // Function 4, HDEM. HID Driver Event Method. + // Input: None. + // Output: Package contains Supported Keys (Mode 0) + // + Case (0x04) + { + Return (HDEM()) + } + // + // Function 5 BTNS. Button Status Method. + // Input: None. + // Output: Int32 which contains a bit map of Buttons' enable/disable states + // + Case (0x05) + { + Return (BTNS()) + } + // + // Function 6 BTNE. Button Enable/Disable Method. + // Input: Int32 Bit mask of buttons enable/disable control: + // 1 = Button should be Enabled + // 0 = Button should be Disabled + // Output: None. + // + Case (0x06) + { + BTNE (DeRefOf(Arg3[0])) + } + // + // Function 7 HEBC. Button implemented state. + // Input: None + // Output: Int32 Bit map which shows what buttons are implemented on this system. + // + Case (0x07) + { + Return (HEBC()) + } + // + // Function 8 VGBS. Virtual GPIO Button Status. + // Input: None + // Output: Intger Bit map which shows what Virtual GPIO Button status. Currently only + // Dock/Slate modes are supported. + // + Case (0x08) + { + Return (0x00) + } + // + // Function 9 H2BC. Button implemented state. + // Input: None + // Output: Int32 Bit map which shows what buttons are implemented on this system. + // + Case (0x09) + { + Return (H2BC()) + } + } + } + } + // If the code falls through to this point, just return a buffer of 0. + Return (Buffer() {0x00}) + } +} diff --git a/src/ec/starlabs/it8987/acpi/keyboard.asl b/src/ec/starlabs/merlin/acpi/keyboard.asl similarity index 50% rename from src/ec/starlabs/it8987/acpi/keyboard.asl rename to src/ec/starlabs/merlin/acpi/keyboard.asl index f5b1d52631..fc7b1e4072 100644 --- a/src/ec/starlabs/it8987/acpi/keyboard.asl +++ b/src/ec/starlabs/merlin/acpi/keyboard.asl @@ -2,35 +2,35 @@ Method(_Q80) // Volume up { - Store ("-----> _Q80", Debug) + Printf ("-----> _Q80") Notify (\_SB.HIDD, 0xC4) Notify (\_SB.HIDD, 0xC5) - Store ("<----- _Q80", Debug) + Printf ("<----- _Q80") } Method(_Q81) // Volume down { - Store ("-----> _Q81", Debug) + Printf ("-----> _Q81") Notify (\_SB.HIDD, 0xC6) Notify (\_SB.HIDD, 0xC7) - Store ("<----- _Q81", Debug) + Printf ("<----- _Q81") } Method(_Q99) // Wireless mode { - Store ("-----> _Q99", Debug) - \_SB.HIDD.HPEM(8) - Store ("<----- _Q80", Debug) + Printf ("-----> _Q99") + ^^^^HIDD.HPEM (8) + Printf ("<----- _Q99") } Method(_Q06) // Brightness decrease { - \_SB.PCI0.GFX0.DECB() + ^^^^HIDD.HPEM (19) } -Method(_Q07) // Brightness increase +Method(_Q05) // Brightness increase { - \_SB.PCI0.GFX0.INCB() + ^^^^HIDD.HPEM (20) } Method(_Q08) // FN lock QEvent @@ -40,24 +40,20 @@ Method(_Q08) // FN lock QEvent Method(_Q54) // Power Button Event { - Store ("-----> _Q54", Debug) - If (CondRefOf (\_SB.PWRB)) - { - Notify(\_SB.PWRB, 0x80) - } - Store ("<----- _Q54", Debug) + Printf ("-----> _Q54") + Printf ("<----- _Q54") } Method(_QD5) // 10 second power button press { - Store ("-----> _QD5", Debug) + Printf ("-----> _QD5") \_SB.PWPR() - Store ("<----- _QD5", Debug) + Printf ("<----- _QD5") } Method(_QD6) // 10 second power button de-press { - Store ("-----> _QD6", Debug) + Printf ("-----> _QD6") \_SB.PWRR() - Store ("<----- _QD6", Debug) + Printf ("<----- _QD6") } diff --git a/src/ec/starlabs/merlin/acpi/lid.asl b/src/ec/starlabs/merlin/acpi/lid.asl new file mode 100644 index 0000000000..8b0edb55eb --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/lid.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Method (_STA) + { + Return (0x0F) + } + Method (_LID,0) + { + // 0x00 == Closed + // 0x01 == Open + Return (^^LSTE) + } +} diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl new file mode 100644 index 0000000000..08ca787113 --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (RPTS, 1, NotSerialized) +{ + \_SB.PCI0.LPCB.EC.OSFG = 0x00 + + If ((Arg0 == 0x04) || (Arg0 == 0x05)) + { + /* Store current EC settings in CMOS */ + \_SB.PCI0.LPCB.TPLC = \_SB.PCI0.LPCB.EC.TPLE + \_SB.PCI0.LPCB.FLKC = \_SB.PCI0.LPCB.EC.FLKE + \_SB.PCI0.LPCB.KLSC = \_SB.PCI0.LPCB.EC.KLSE + \_SB.PCI0.LPCB.KLBC = \_SB.PCI0.LPCB.EC.KLBE + } +} + +Method (RWAK, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC.OSFG = 0x01 + + /* Restore EC settings from CMOS */ + \_SB.PCI0.LPCB.EC.TPLE = \_SB.PCI0.LPCB.TPLC + \_SB.PCI0.LPCB.EC.FLKE = \_SB.PCI0.LPCB.FLKC + \_SB.PCI0.LPCB.EC.KLSE = \_SB.PCI0.LPCB.KLSC + \_SB.PCI0.LPCB.EC.KLBE = \_SB.PCI0.LPCB.KLBC +} diff --git a/src/ec/starlabs/merlin/acpi/typec.asl b/src/ec/starlabs/merlin/acpi/typec.asl new file mode 100644 index 0000000000..1acc8a4427 --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/typec.asl @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (UCSW, 0, Serialized) +{ + Sleep (50) + MGO0 = ^^^^UBTC.MGO0 + MGO1 = ^^^^UBTC.MGO1 + MGO2 = ^^^^UBTC.MGO2 + MGO3 = ^^^^UBTC.MGO3 + MGO4 = ^^^^UBTC.MGO4 + MGO5 = ^^^^UBTC.MGO5 + MGO6 = ^^^^UBTC.MGO6 + MGO7 = ^^^^UBTC.MGO7 + MGO8 = ^^^^UBTC.MGO7 + MGO9 = ^^^^UBTC.MGO9 + MGOA = ^^^^UBTC.MGOA + MGOB = ^^^^UBTC.MGOB + MGOC = ^^^^UBTC.MGOC + MGOD = ^^^^UBTC.MGOD + MGOE = ^^^^UBTC.MGOE + MGOF = ^^^^UBTC.MGOF + CTL0 = ^^^^UBTC.CTL0 + CTL1 = ^^^^UBTC.CTL1 + CTL2 = ^^^^UBTC.CTL2 + CTL3 = ^^^^UBTC.CTL3 + CTL4 = ^^^^UBTC.CTL4 + CTL5 = ^^^^UBTC.CTL5 + CTL6 = ^^^^UBTC.CTL6 + CTL7 = ^^^^UBTC.CTL7 + OPWE = 0xE0 +} + +Method (UCSR, 0, Serialized) +{ + Sleep (50) + ^^^^UBTC.MGI0 = MGI0 + ^^^^UBTC.MGI1 = MGI1 + ^^^^UBTC.MGI2 = MGI2 + ^^^^UBTC.MGI3 = MGI3 + ^^^^UBTC.MGI4 = MGI4 + ^^^^UBTC.MGI5 = MGI5 + ^^^^UBTC.MGI6 = MGI6 + ^^^^UBTC.MGI7 = MGI7 + ^^^^UBTC.MGI8 = MGI8 + ^^^^UBTC.MGI9 = MGI9 + ^^^^UBTC.MGIA = MGIA + ^^^^UBTC.MGIB = MGIB + ^^^^UBTC.MGIC = MGIC + ^^^^UBTC.MGID = MGID + ^^^^UBTC.MGIE = MGIE + ^^^^UBTC.MGIF = MGIF + ^^^^UBTC.CCI0 = CCI0 + ^^^^UBTC.CCI1 = CCI1 + ^^^^UBTC.CCI2 = CCI2 + ^^^^UBTC.CCI3 = CCI3 +} + +Method (UCEV, 0, Serialized) +{ + Sleep (50) + ^^^^UBTC.MGI0 = MGI0 + ^^^^UBTC.MGI1 = MGI1 + ^^^^UBTC.MGI2 = MGI2 + ^^^^UBTC.MGI3 = MGI3 + ^^^^UBTC.MGI4 = MGI4 + ^^^^UBTC.MGI5 = MGI5 + ^^^^UBTC.MGI6 = MGI6 + ^^^^UBTC.MGI7 = MGI7 + ^^^^UBTC.MGI8 = MGI8 + ^^^^UBTC.MGI9 = MGI9 + ^^^^UBTC.MGIA = MGIA + ^^^^UBTC.MGIB = MGIB + ^^^^UBTC.MGIC = MGIC + ^^^^UBTC.MGID = MGID + ^^^^UBTC.MGIE = MGIE + ^^^^UBTC.MGIF = MGIF + ^^^^UBTC.CCI0 = CCI0 + ^^^^UBTC.CCI1 = CCI1 + ^^^^UBTC.CCI2 = CCI2 + ^^^^UBTC.CCI3 = CCI3 + Notify (^^^^UBTC, 0x80) +} diff --git a/src/ec/starlabs/merlin/acpi/ubtc.asl b/src/ec/starlabs/merlin/acpi/ubtc.asl new file mode 100644 index 0000000000..f29fb9d6cd --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/ubtc.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External(\_SB.UBTC, DeviceObj) +External(\_SB.UBTC.MGI0, IntObj) +External(\_SB.UBTC.MGI1, IntObj) +External(\_SB.UBTC.MGI2, IntObj) +External(\_SB.UBTC.MGI3, IntObj) +External(\_SB.UBTC.MGI4, IntObj) +External(\_SB.UBTC.MGI5, IntObj) +External(\_SB.UBTC.MGI6, IntObj) +External(\_SB.UBTC.MGI7, IntObj) +External(\_SB.UBTC.MGI8, IntObj) +External(\_SB.UBTC.MGI9, IntObj) +External(\_SB.UBTC.MGIA, IntObj) +External(\_SB.UBTC.MGIB, IntObj) +External(\_SB.UBTC.MGIC, IntObj) +External(\_SB.UBTC.MGID, IntObj) +External(\_SB.UBTC.MGIE, IntObj) +External(\_SB.UBTC.MGIF, IntObj) + +External(\_SB.UBTC.CTL0, IntObj) +External(\_SB.UBTC.CTL1, IntObj) +External(\_SB.UBTC.CTL2, IntObj) +External(\_SB.UBTC.CTL3, IntObj) +External(\_SB.UBTC.CTL4, IntObj) +External(\_SB.UBTC.CTL5, IntObj) +External(\_SB.UBTC.CTL6, IntObj) +External(\_SB.UBTC.CTL7, IntObj) + +External(\_SB.UBTC.MGO0, IntObj) +External(\_SB.UBTC.MGO1, IntObj) +External(\_SB.UBTC.MGO2, IntObj) +External(\_SB.UBTC.MGO3, IntObj) +External(\_SB.UBTC.MGO4, IntObj) +External(\_SB.UBTC.MGO5, IntObj) +External(\_SB.UBTC.MGO6, IntObj) +External(\_SB.UBTC.MGO7, IntObj) +External(\_SB.UBTC.MGO8, IntObj) +External(\_SB.UBTC.MGO9, IntObj) +External(\_SB.UBTC.MGOA, IntObj) +External(\_SB.UBTC.MGOB, IntObj) +External(\_SB.UBTC.MGOC, IntObj) +External(\_SB.UBTC.MGOD, IntObj) +External(\_SB.UBTC.MGOE, IntObj) +External(\_SB.UBTC.MGOF, IntObj) + +External(\_SB.UBTC.CCI0, IntObj) +External(\_SB.UBTC.CCI1, IntObj) +External(\_SB.UBTC.CCI2, IntObj) +External(\_SB.UBTC.CCI3, IntObj) diff --git a/src/ec/starlabs/merlin/ec.c b/src/ec/starlabs/merlin/ec.c new file mode 100644 index 0000000000..40be138a82 --- /dev/null +++ b/src/ec/starlabs/merlin/ec.c @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "ec.h" +#include "ecdefs.h" + +uint16_t it_get_version(void) +{ + return (ec_read(ECRAM_MAJOR_VERSION) << 8) | ec_read(ECRAM_MINOR_VERSION); +} + +static uint8_t get_ec_value_from_option(const char *name, + unsigned int fallback, + const uint8_t *lut, + size_t lut_size) +{ + unsigned int index = get_uint_option(name, fallback); + if (index >= lut_size) + index = fallback; + return lut[index]; +} + +static uint16_t ite_get_chip_id(unsigned int port) +{ + return (pnp_read_index(port, ITE_CHIPID1) << 8) | + pnp_read_index(port, ITE_CHIPID2); +} + +static void merlin_init(struct device *dev) +{ + if (!dev->enabled) + return; + + /* + * The address/data IO port pair for the ite EC are configurable + * through the EC domain and are fixed by the EC's firmware blob. If + * the value(s) passed through the "dev" structure don't match the + * expected values then output severe warnings. + */ + if (dev->path.pnp.port != ITE_FIXED_ADDR) { + printk(BIOS_ERR, "ITE: Incorrect ports defined in devicetree.cb.\n"); + printk(BIOS_ERR, "ITE: Serious operational issues will arise.\n"); + return; + } + + const uint16_t chip_id = ite_get_chip_id(dev->path.pnp.port); + + if (chip_id != ITE_CHIPID_VAL) { + printk(BIOS_ERR, "ITE: Expected chip ID 0x%04x, but got 0x%04x instead.\n", + ITE_CHIPID_VAL, chip_id); + return; + } + + pc_keyboard_init(NO_AUX_DEVICE); + + /* + * Restore settings from CMOS into EC RAM: + * + * kbl_timeout + * fn_ctrl_swap + * max_charge + * fan_mode + * fn_lock_state + * trackpad_state + * kbl_brightness + * kbl_state + */ + + /* + * Keyboard Backlight Timeout + * + * Setting: kbl_timeout + * + * Values: 30 Seconds, 1 Minute, 3 Minutes, 5 Minutes, Never + * Default: 30 Seconds + * + */ + const uint8_t kbl_timeout[] = { + SEC_30, + MIN_1, + MIN_3, + MIN_5, + NEVER + }; + + ec_write(ECRAM_KBL_TIMEOUT, + get_ec_value_from_option("kbl_timeout", + 0, + kbl_timeout, + ARRAY_SIZE(kbl_timeout))); + + /* + * Fn Ctrl Reverse + * + * Setting: fn_ctrl_swap + * + * Values: Enabled, Disabled + * Default: Disabled + * + */ + const uint8_t fn_ctrl_swap[] = { + FN_CTRL, + CTRL_FN + }; + + ec_write(ECRAM_FN_CTRL_REVERSE, + get_ec_value_from_option("fn_ctrl_swap", + 1, + fn_ctrl_swap, + ARRAY_SIZE(fn_ctrl_swap))); + + /* + * Maximum Charge Level + * + * Setting: max_charge + * + * Values: 60%, 80%, 100% + * Default: 100% + * + */ + const uint8_t max_charge[] = { + CHARGE_100, + CHARGE_80, + CHARGE_60 + }; + + ec_write(ECRAM_MAX_CHARGE, + get_ec_value_from_option("max_charge", + 0, + max_charge, + ARRAY_SIZE(max_charge))); + + /* + * Fan Mode + * + * Setting: fan_mode + * + * Values: Quiet, Normal, Aggressive + * Default: Normal + * + */ + const uint8_t fan_mode[] = { + FAN_NORMAL, + FAN_AGGRESSIVE, + FAN_QUIET + }; + + if (CONFIG(EC_STARLABS_FAN)) + ec_write(ECRAM_FAN_MODE, + get_ec_value_from_option("fan_mode", + 0, + fan_mode, + ARRAY_SIZE(fan_mode))); + + /* + * Function Lock + * + * Setting: fn_lock_state + * + * Values: Locked, Unlocked + * Default: Locked + * + */ + const uint8_t fn_lock_state[] = { + UNLOCKED, + LOCKED + }; + + ec_write(ECRAM_FN_LOCK_STATE, + get_ec_value_from_option("fn_lock_state", + 1, + fn_lock_state, + ARRAY_SIZE(fn_lock_state))); + + /* + * Trackpad State + * + * Setting: trackpad_state + * + * Values: Enabled, Disabled + * Default: Enabled + * + */ + const uint8_t trackpad_state[] = { + TRACKPAD_ENABLED, + TRACKPAD_DISABLED + }; + + ec_write(ECRAM_TRACKPAD_STATE, + get_ec_value_from_option("trackpad_state", + 0, + trackpad_state, + ARRAY_SIZE(trackpad_state))); + + /* + * Keyboard Backlight Brightness + * + * Setting: kbl_brightness + * + * Values: Off, Low, High / Off, On + * Default: Low + * + */ + const uint8_t kbl_brightness[] = { + KBL_ON, + KBL_OFF, + KBL_LOW, + KBL_HIGH + }; + + if (CONFIG(EC_STARLABS_KBL_LEVELS)) + ec_write(ECRAM_KBL_BRIGHTNESS, + get_ec_value_from_option("kbl_brightness", + 2, + kbl_brightness, + ARRAY_SIZE(kbl_brightness))); + else + ec_write(ECRAM_KBL_BRIGHTNESS, + get_ec_value_from_option("kbl_brightness", + 0, + kbl_brightness, + ARRAY_SIZE(kbl_brightness))); + + /* + * Keyboard Backlight State + * + * Setting: kbl_state + * + * Values: Off, On + * Default: On + * + */ + const uint8_t kbl_state[] = { + KBL_DISABLED, + KBL_ENABLED + }; + + ec_write(ECRAM_KBL_STATE, + get_ec_value_from_option("kbl_state", + 1, + kbl_state, + ARRAY_SIZE(kbl_state))); +} + +static struct device_operations ops = { + .init = merlin_init, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 (UART1) */ + { NULL, ITE_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + /* Serial Port 2 (UART2) */ + { NULL, ITE_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + /* System Wake-Up Control (SWUC) */ + { NULL, ITE_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* KBC / Mouse Interface */ + { NULL, ITE_SWUC, PNP_IRQ0, }, + /* KBC / Keyboard Interface */ + { NULL, ITE_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + /* Consumer IR (CIR) */ + { NULL, ITE_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + /* Shared Memory / Flash Interface (SMFI) */ + { NULL, ITE_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* RTC-like Timer (RCTC) */ + { NULL, ITE_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + 0xfffe, 0xfffe, 0xfffe, 0xfffe, }, + /* Power Management I/F Channel 1 (PMC1) */ + { NULL, ITE_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + /* Power Management I/F Channel 2 (PMC2) */ + { NULL, ITE_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, 0x07fc, + 0x07fc, 0xfff0, }, + /* Serial Peripheral Interface (SSPI) */ + { NULL, ITE_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + /* Platform Environment Control Interface (PECI) */ + { NULL, ITE_PECI, PNP_IRQ0, 0xfff8, }, + /* Power Management I/F Channel 3 (PMC3) */ + { NULL, ITE_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + /* Power Management I/F Channel 4 (PMC4) */ + { NULL, ITE_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + /* Power Management I/F Channel 5 (PMC5) */ + { NULL, ITE_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_starlabs_merlin_ops = { + CHIP_NAME("ITE EC") + .enable_dev = enable_dev +}; diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h new file mode 100644 index 0000000000..8f8bb99368 --- /dev/null +++ b/src/ec/starlabs/merlin/ec.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller. + */ + +#ifndef _EC_STARLABS_ITE_H +#define _EC_STARLABS_ITE_H + +/* + * Define the expected value of the PNP base address that is fixed through + * the BADRSEL register controlled within the EC domain by the EC Firmware. + */ +#define ITE_FIXED_ADDR 0x4e + +/* Logical device number (LDN) assignments. */ +#define ITE_SP1 0x01 /* Serial Port 1 (UART) */ +#define ITE_SP2 0x02 /* Serial Port 2 (UART) */ +#define ITE_SWUC 0x04 /* System Wake-Up Control (SWUC) */ +#define ITE_KBCM 0x05 /* KBC / Mouse Interface */ +#define ITE_KBCK 0x06 /* KBC / Keyboard Interface */ +#define ITE_IR 0x0a /* Consumer IR (CIR) */ +#define ITE_SMFI 0x0f /* Shared Memory / Flash Interface (SMFI) */ +#define ITE_RTCT 0x10 /* RTC-like Timer (RCTC) */ +#define ITE_PMC1 0x11 /* Power Management I/F Channel 1 (PMC1) */ +#define ITE_PMC2 0x12 /* Power Management I/F Channel 2 (PMC2) */ +#define ITE_SSPI 0x13 /* Serial Peripheral Interface (SSPI) */ +#define ITE_PECI 0x14 /* Platform Environment Control Interface (PECI) */ +#define ITE_PMC3 0x17 /* Power Management I/F Channel 3 (PMC3) */ +#define ITE_PMC4 0x18 /* Power Management I/F Channel 4 (PMC4) */ +#define ITE_PMC5 0x19 /* Power Management I/F Channel 5 (PMC5) */ + +/* Host domain registers. */ +#define ITE_CHIPID1 0x20 /* Device ID register 1 */ +#define ITE_CHIPID2 0x21 /* Device ID register 2 */ + +/* EC RAM common offsets */ +#define ECRAM_MAJOR_VERSION 0x00 +#define ECRAM_MINOR_VERSION 0x01 + +/* + * CMOS Settings + */ + +/* Keyboard Backlight Timeout */ +#define SEC_30 0x00 +#define MIN_1 0x01 +#define MIN_3 0x02 +#define MIN_5 0x03 +#define NEVER 0x04 + +/* Fn Ctrl Swap */ +#define FN_CTRL 0x00 +#define CTRL_FN 0x01 + +/* Max Charge Setting */ +#define CHARGE_100 0x00 +#define CHARGE_80 0xbb +#define CHARGE_60 0xaa + +/* Fan Mode Setting */ +#define FAN_NORMAL 0x00 +#define FAN_AGGRESSIVE 0xbb +#define FAN_QUIET 0xaa + +/* Fn Lock State */ +#define UNLOCKED 0x00 +#define LOCKED 0x01 + +/* Trackpad State */ +#define TRACKPAD_ENABLED 0x00 +#define TRACKPAD_DISABLED 0x22 + +/* Keyboard Brightness Levels */ +#define KBL_ON 0xdd +#define KBL_OFF 0xcc +#define KBL_LOW 0xbb +#define KBL_HIGH 0xaa + +/* Keyboard Backlight State */ +#define KBL_DISABLED 0x00 +#define KBL_ENABLED 0xdd + +uint16_t it_get_version(void); + +#endif diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h new file mode 100644 index 0000000000..1057da83ff --- /dev/null +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * EC communication interface for ITE Embedded Controller. + */ + +#ifndef _EC_STARLABS_APL_EC_DEFS_H +#define _EC_STARLABS_APL_EC_DEFS_H + +/* IT8987 chip ID byte values. */ +#define ITE_CHIPID_VAL 0x8987 + +/* EC RAM offsets. */ +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x18 +#define ECRAM_KBL_BRIGHTNESS 0x19 +#define ECRAM_KBL_TIMEOUT 0x1a +#define ECRAM_FN_LOCK_STATE 0x2c +#define ECRAM_FN_CTRL_REVERSE 0x2d +#define ECRAM_MAX_CHARGE 0x46 +#define ECRAM_FAN_MODE dead_code_t(uint8_t) + +#endif diff --git a/src/ec/starlabs/merlin/variants/apl/emem.asl b/src/ec/starlabs/merlin/variants/apl/emem.asl new file mode 100644 index 0000000000..d30b58c5bf --- /dev/null +++ b/src/ec/starlabs/merlin/variants/apl/emem.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + FRMF, 8, // Force Mirror Flag + TXEL, 8, // TXE Lock + + Offset(0x10), + CPWR, 8, // Control Power + CDEV, 8, // Control Device + OSFG, 8, // OS Flag + CWFU, 8, // CW2015 Full + TPLE, 8, // Trackpad State + AFG3, 8, // After G3 + CLTP, 8, // Close Trackpad + WKOL, 8, // Wake on Lid + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + + Offset(0x1a), + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x22), + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x2c), + FLKE, 8, // Function Lock State + + Offset(0x30), + STEF, 8, // Sensor T Error F + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + LEDF, 8, // LED Control Flag + LIDF, 8, // Lid Flag + KBFL, 8, // Keyboard Flag + CYCC, 8, // Cycle Count + + Offset(0x46), + BFCP, 8, // Battery Full Charge Percentage + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7e), + OCTF, 8, // OEM Control Flag + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + BT1T, 16, // Bt1 Temperature + BT1C, 8, // Bt1 Control + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xbf), + EJ8A, 8, // EJ898A Firmware Version + + Offset(0xc0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xd0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xe0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xf0), + P0SD, 8, // PD Port Status DD + P0S4, 8, // PD Port Status 4 + P0S5, 8, // PD Port Status 5 + P0SE, 8, // PD Port Status E + P0SA, 8, // PD Port Status 10 + P0SB, 8, // PD Port Status 11 + + Offset(0xfd), + STCD, 8, // Shutdown Code + EJ8R, 8, // EJ898A Need Reboot + EJ8E, 8, // EJ898A Error +} diff --git a/src/ec/starlabs/merlin/variants/apl/events.asl b/src/ec/starlabs/merlin/variants/apl/events.asl new file mode 100644 index 0000000000..e2c301bb43 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/apl/events.asl @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q07, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Function Lock +{ + FLKC = FLKE +} +// +// TODO: +// Below Q Events need to be added +// +// Method (_Q04, 0, NotSerialized) // Event: Trackpad Lock +// { +// TPLC = TPLE +// } +// +// Method (_Q__, 0, NotSerialized) // Event: Keyboard Backlight Brightness +// { +// KLBC = KLBE +// } +// + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} diff --git a/src/ec/starlabs/merlin/variants/cml/ecdefs.h b/src/ec/starlabs/merlin/variants/cml/ecdefs.h new file mode 100644 index 0000000000..42b4d44d52 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cml/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_CML_EC_DEFS_H +#define _EC_STARLABS_CML_EC_DEFS_H + +/* IT8987 chip ID byte values */ +#define ITE_CHIPID_VAL 0x8987 + +/* EC RAM offsets */ +#define ECRAM_KBL_TIMEOUT 0x07 +#define ECRAM_FN_CTRL_REVERSE 0x08 +#define ECRAM_FAN_MODE 0x09 +#define ECRAM_MAX_CHARGE 0x10 +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x18 +#define ECRAM_KBL_BRIGHTNESS 0x19 +#define ECRAM_FN_LOCK_STATE 0x2c + +#endif diff --git a/src/ec/starlabs/merlin/variants/cml/emem.asl b/src/ec/starlabs/merlin/variants/cml/emem.asl new file mode 100644 index 0000000000..97845cd387 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cml/emem.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + FRMF, 8, // Force Mirror Flag + TXEL, 8, // TXE Lock + SSIT, 8, // Show Setup Items + KLTE, 8, // Keyboard Backlight Timeout + FCLA, 8, // Fn Ctrl Reverse + FANM, 8, // Fan Mode + + Offset(0x0a), + P0MV, 8, // PD Port 0 Major Version + P0SV, 8, // PD Port 0 Minor Version + P1MV, 8, // PD Port 1 Major Version + P1SV, 8, // PD Port 1 Minor Version + + Offset(0x10), + BFCP, 8, // Battery Full Charge Percentage + CDEV, 8, // Control Device + OSFG, 8, // OS Flag + + Offset(0x14), + TPLE, 8, // Trackpad State + AFG3, 8, // After G3 + CLTP, 8, // Close Trackpad + WKOL, 8, // Wake on Lid + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + + Offset(0x1a), + CWFU, 8, // CW2015 Full + + Offset(0x1c), + WIFI, 8, // WiFi Enable + + Offset(0x22), + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + FLKE, 8, // Function Lock State + MICF, 8, // Mic Flag + MUTF, 8, // Mute Flag + BC12, 8, // BC12 Flag + + Offset(0x30), + STEF, 8, // Sensor T Error F + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x4c), + PJN0, 8, // Project Name 0 + PJN1, 8, // Project Name 1 + PJN2, 8, // Project Name 2 + PJN3, 8, // Project Name 3 + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7f), + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + BT1T, 16, // Bt1 Temperature + BT1C, 8, // Bt1 Control + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xa0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xb0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xc0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xe6), + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable +} diff --git a/src/ec/starlabs/merlin/variants/cml/events.asl b/src/ec/starlabs/merlin/variants/cml/events.asl new file mode 100644 index 0000000000..2eedb8e6cc --- /dev/null +++ b/src/ec/starlabs/merlin/variants/cml/events.asl @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_QA0, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q07, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Function Lock +{ + FLKC = FLKE +} + +Method (_Q04, 0, NotSerialized) // Event: Trackpad Lock +{ + TPLC = TPLE +} +// +// TODO: +// Below Q Events need to be added +// +Method (_Q11) // Event: Keyboard Backlight Brightness +{ + KLBC = KLBE +} + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q40, 0, NotSerialized) // Event: AC and DC Power +{ + SMB2 = 0xC6 +} + +Method (_Q41, 0, NotSerialized) // Event: Battery Charge between 0% and 20% +{ + SMB2 = 0xC7 +} + +Method (_Q42, 0, NotSerialized) // Event: Battery Charge between 20% and 60% +{ + SMB2 = 0xC8 +} + +Method (_Q43, 0, NotSerialized) // Event: Battery Charge between 60% and 100% +{ + SMB2 = 0xC9 +} + +Method (_Q44, 0, NotSerialized) // Event: AC Power Only +{ + SMB2 = 0xCA +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} + +/* + * The below events are unique to this platform. + */ + + +Method (_Q02, 0, NotSerialized) // Event: APP +{ + Printf ("EC: APP") +} + +Method (_Q82, 0, NotSerialized) // Event: MIC +{ + Printf ("EC: MIC") +} + +Method (_Q83, 0, NotSerialized) // Event: MUTE +{ + Printf ("EC: MUTE") +} diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h new file mode 100644 index 0000000000..5f43991aef --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * EC communication interface for ITE Embedded Controller. + */ + +#ifndef _EC_STARLABS_GLK_EC_DEFS_H +#define _EC_STARLABS_GLK_EC_DEFS_H + +/* IT8987 chip ID byte values. */ +#define ITE_CHIPID_VAL 0x8987 + +/* EC RAM offsets. */ +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x18 +#define ECRAM_KBL_BRIGHTNESS 0x19 +#define ECRAM_KBL_TIMEOUT 0x1a +#define ECRAM_FN_LOCK_STATE 0x2c +#define ECRAM_FN_CTRL_REVERSE 0x2d +#define ECRAM_MAX_CHARGE 0x46 +#define ECRAM_FAN_MODE dead_code_t(uint8_t) + +#endif diff --git a/src/ec/starlabs/merlin/variants/glk/emem.asl b/src/ec/starlabs/merlin/variants/glk/emem.asl new file mode 100644 index 0000000000..d30b58c5bf --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glk/emem.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + FRMF, 8, // Force Mirror Flag + TXEL, 8, // TXE Lock + + Offset(0x10), + CPWR, 8, // Control Power + CDEV, 8, // Control Device + OSFG, 8, // OS Flag + CWFU, 8, // CW2015 Full + TPLE, 8, // Trackpad State + AFG3, 8, // After G3 + CLTP, 8, // Close Trackpad + WKOL, 8, // Wake on Lid + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + + Offset(0x1a), + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x22), + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x2c), + FLKE, 8, // Function Lock State + + Offset(0x30), + STEF, 8, // Sensor T Error F + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + LEDF, 8, // LED Control Flag + LIDF, 8, // Lid Flag + KBFL, 8, // Keyboard Flag + CYCC, 8, // Cycle Count + + Offset(0x46), + BFCP, 8, // Battery Full Charge Percentage + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7e), + OCTF, 8, // OEM Control Flag + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + BT1T, 16, // Bt1 Temperature + BT1C, 8, // Bt1 Control + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xbf), + EJ8A, 8, // EJ898A Firmware Version + + Offset(0xc0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xd0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xe0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xf0), + P0SD, 8, // PD Port Status DD + P0S4, 8, // PD Port Status 4 + P0S5, 8, // PD Port Status 5 + P0SE, 8, // PD Port Status E + P0SA, 8, // PD Port Status 10 + P0SB, 8, // PD Port Status 11 + + Offset(0xfd), + STCD, 8, // Shutdown Code + EJ8R, 8, // EJ898A Need Reboot + EJ8E, 8, // EJ898A Error +} diff --git a/src/ec/starlabs/merlin/variants/glk/events.asl b/src/ec/starlabs/merlin/variants/glk/events.asl new file mode 100644 index 0000000000..e2c301bb43 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glk/events.asl @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q07, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Function Lock +{ + FLKC = FLKE +} +// +// TODO: +// Below Q Events need to be added +// +// Method (_Q04, 0, NotSerialized) // Event: Trackpad Lock +// { +// TPLC = TPLE +// } +// +// Method (_Q__, 0, NotSerialized) // Event: Keyboard Backlight Brightness +// { +// KLBC = KLBE +// } +// + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h new file mode 100644 index 0000000000..36cd0207ab --- /dev/null +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_KBL_EC_DEFS_H +#define _EC_STARLABS_KBL_EC_DEFS_H + +/* IT8987 chip ID byte values */ +#define ITE_CHIPID_VAL 0x8987 + +/* EC RAM offsets */ +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x18 +#define ECRAM_KBL_BRIGHTNESS 0x19 +#define ECRAM_KBL_TIMEOUT 0x1a +#define ECRAM_FN_LOCK_STATE 0x2c +#define ECRAM_FAN_MODE 0x42 +#define ECRAM_FN_CTRL_REVERSE 0x43 +#define ECRAM_MAX_CHARGE 0xff /* TODO: Add */ + +#endif diff --git a/src/ec/starlabs/merlin/variants/kbl/emem.asl b/src/ec/starlabs/merlin/variants/kbl/emem.asl new file mode 100644 index 0000000000..66699175c5 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/kbl/emem.asl @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + FRMF, 8, // Force Mirror Flag + + Offset(0x0c), + ECBY, 8, // Build Year + ECBM, 8, // Build Month + ECBD, 8, // Build Day + ECBI, 8, // Build Index + + Offset(0x10), + CPWR, 8, // Control Power + CDEV, 8, // Control Device + OSFG, 8, // OS Flag + + Offset(0x14), + TPLE, 8, // Trackpad State + + Offset(0x18), + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x20), + TCHC, 8, // Thermal Charge CMD + TCHF, 8, // Thermal Charge Flag + + Offset(0x2c), + FLKE, 8, // Function Lock State + + Offset(0x30), + STEF, 8, // Sensor T Error F + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + + Offset(0x42), + FANM, 8, // Fan Mode + KBFL, 8, // Keyboard Flag + + Offset(0x50), + CHRA, 16, // Charge Rate + CHIC, 16, // Charge Input Current + CHVL, 16, // Charge Vlot + CHOP, 16, // Charge Option + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7e), + OCTF, 8, // OEM Control Flag + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xbf), + EJ8A, 8, // EJ898A Firmware Version + + Offset(0xc0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xd0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xe0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xf0), + P0SD, 8, // PD Port Status DD + P0S4, 8, // PD Port Status 4 + P0S5, 8, // PD Port Status 5 + P0SE, 8, // PD Port Status E + P0SA, 8, // PD Port Status 10 + P0SB, 8, // PD Port Status 11 + + Offset(0xfd), + STCD, 8, // Shutdown Code + EJ8R, 8, // EJ898A Need Reboot + EJ8E, 8, // EJ898A Error +} diff --git a/src/ec/starlabs/merlin/variants/kbl/events.asl b/src/ec/starlabs/merlin/variants/kbl/events.asl new file mode 100644 index 0000000000..966365cbc6 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/kbl/events.asl @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q07, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Function Lock +{ + FLKC = FLKE +} +// +// TODO: +// Below Q Events need to be added +// +// Method (_Q04, 0, NotSerialized) // Event: Trackpad Lock +// { +// TPLC = TPLE +// } +// +// Method (_Q__, 0, NotSerialized) // Event: Keyboard Backlight Brightness +// { +// KLBC = KLBE +// KLSC = KLSE +// } +// + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +// +// TODO: +// Below Q Events need to be added +// +// Method (_Q40, 0, NotSerialized) // Event: AC and DC Power +// { +// SMB2 = 0xC6 +// } +// +// Method (_Q41, 0, NotSerialized) // Event: Battery Charge between 0% and 20% +// { +// SMB2 = 0xC7 +// } +// +// Method (_Q42, 0, NotSerialized) // Event: Battery Charge between 20% and 60% +// { +// SMB2 = 0xC8 +// } +// +// Method (_Q43, 0, NotSerialized) // Event: Battery Charge between 60% and 100% +// { +// SMB2 = 0xC9 +// } +// +// Method (_Q44, 0, NotSerialized) // Event: AC Power Only +// { +// SMB2 = 0xCA +// } + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} + +/* + * The below events are unique to this platform. + */ + + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 +{ + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC: THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q38, 0, NotSerialized) // Event: CPU_DN_SPEED +{ + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN +{ + Printf ("EC: SHUTDOWN") +} + +Method (_Q01, 0, NotSerialized) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02, 0, NotSerialized) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03, 0, NotSerialized) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04, 0, NotSerialized) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q05, 0, NotSerialized) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q09, 0, NotSerialized) // Event: F9 Hot Key +{ + Printf ("EC: F9") +} + +Method (_Q10, 0, NotSerialized) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q11, 0, NotSerialized) // Event: F11 Hot Key +{ + Printf ("EC: F11") +} + +Method (_Q12, 0, NotSerialized) // Event: F12 Hot Key +{ + Printf ("EC: F6") +} diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h new file mode 100644 index 0000000000..48357d964a --- /dev/null +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_MERLIN_EC_DEFS_H +#define _EC_STARLABS_MERLIN_EC_DEFS_H + +/* IT5570 chip ID byte values */ +#define ITE_CHIPID_VAL 0x5570 + +/* EC RAM offsets */ +#define ECRAM_FN_CTRL_REVERSE 0x30 +#define ECRAM_FN_LOCK_STATE 0x31 +#define ECRAM_TRACKPAD_STATE 0x32 +#define ECRAM_KBL_BRIGHTNESS 0x33 +#define ECRAM_KBL_STATE 0x34 +#define ECRAM_KBL_TIMEOUT 0x35 +#define ECRAM_FAN_MODE 0x50 +#define ECRAM_MAX_CHARGE 0x51 + +#endif diff --git a/src/ec/starlabs/merlin/variants/merlin/emem.asl b/src/ec/starlabs/merlin/variants/merlin/emem.asl new file mode 100644 index 0000000000..06749f02e3 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/merlin/emem.asl @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), // Versions: + SKUI, 8, // SKU ID + BDID, 8, // Board ID + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + OSFG, 8, // OS Flag + + Offset(0x10), // Build Time: + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x20), // Build Date: + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x30), // Keyboard: + FCLA, 8, // Fn Ctrl Reverse + FLKE, 8, // Function Lock State + TPLE, 8, // Trackpad State + KLBE, 8, // Keyboard Backlight Brightness + KLSE, 8, // Keyboard Backlight State + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x40), // Flags: + SHIP, 8, // Shipping Mode Flag + CSFG, 8, // Modern Standby Flag + KBCD, 8, // Rotate Flag + WIFI, 8, // WiFi Enable + AUDI, 8, // Control Audio + + Offset(0x50), // Devices: + FANM, 8, // Fan Mode + BFCP, 8, // Battery Full Charge Percentage + + Offset(0x60), // Recovery: + BSRC, 8, // BIOS Recover + + Offset(0x70), // Temperatures: + TSE1, 8, // Sensor 1 Temperature + TSE2, 8, // Sensor 2 Temperature + TSE3, 8, // Sensor 3 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + SURF, 8, // Chassis Surface Temperature + CHAR, 8, // Charger Temperature + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + + Offset(0x7f), // Lid: + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), // Battery: + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BATT, 16, // Battery Temperature + BATC, 8, // Battery Temperature Ces + + // Unicorn - doesn't actually exist + Offset(0x9d), // OPM: + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xb0), // MGO; + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xc0), // CCI: + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), // MGI: + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe6), // Delays: + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable + + Offset(0xf7), // Thunderbolt: + TBTC, 8, // Thunderbolt Command + TBTP, 8, // Thunderbolt Data Port + TBTD, 8, // Thunderbolt Data + TBTA, 8, // Thunderbolt Acknowledge + TBTG, 16, // Thunderbolt DBG Data +} diff --git a/src/ec/starlabs/merlin/variants/merlin/events.asl b/src/ec/starlabs/merlin/variants/merlin/events.asl new file mode 100644 index 0000000000..a7328561e3 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/merlin/events.asl @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q05) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q06) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q87) // Event: Function Lock +{ + FLKC = FLKE +} + +Method (_Q88) // Event: Trackpad Lock +{ + TPLC = TPLE +} +Method (_Q11) // Event: Keyboard Backlight Brightness +{ + KLBC = KLBE + KLSC = KLSE +} + +Method (_Q99) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5) // Event: 10 Second Power Button Pressed +{ + Printf ("EC: 10 Second Power Button Pressed") +} + +Method (_QD6) // Event: 10 Second Power Button Released +{ + Printf ("EC: 10 Second Power Button Release") +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q40) // Event: AC_DC +{ + SMB2 = 0xC6 +} + +Method (_Q41) // Event: DC_20_0 +{ + SMB2 = 0xC7 +} + +Method (_Q42) // Event: DC_60_20 +{ + SMB2 = 0xC9 +} + +Method (_Q43) // Event: DC_100_60 +{ + SMB2 = 0xC9 +} + +Method (_Q44) // Event: AC_ONLY +{ + SMB2 = 0xCA +} + +Method (_Q80, 0, NotSerialized) // Event: VOLUME_UP +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: VOLUME_DOWN +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: PWRBTN +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} + +/* + * The below events are unique to this platform. + */ + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} + +Method (_Q01) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q08) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q09) // Event: F6 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q07) // Event: F7 Hot Key +{ + Printf ("EC: F7") +} + +Method (_Q10) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q12) // Event: F12 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 +{ + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC: THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q38, 0, NotSerialized) // Event: CPU_DN_SPEED +{ + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN +{ + Printf ("EC: SHUTDOWN") +} + +Method (_Q45) // Event: SENSOR_T76 +{ + SMB2 = 0xCB +} + +Method (_Q48, 0, NotSerialized) // Event: Fan Turbo On +{ + Printf ("EC: Fan Turbo On") +} + +Method (_Q49, 0, NotSerialized) // Event: Fan Turbo Off +{ + Printf ("EC: Fan Turbo Off") +} diff --git a/src/ec/starlabs/merlin/variants/tgl/ecdefs.h b/src/ec/starlabs/merlin/variants/tgl/ecdefs.h new file mode 100644 index 0000000000..3441bc073f --- /dev/null +++ b/src/ec/starlabs/merlin/variants/tgl/ecdefs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * EC communication interface for ITE Embedded Controller + */ + +#ifndef _EC_STARLABS_TGL_EC_DEFS_H +#define _EC_STARLABS_TGL_EC_DEFS_H + +/* IT5570 chip ID byte values */ +#define ITE_CHIPID_VAL 0x5570 + +/* EC RAM offsets */ +#define ECRAM_KBL_BRIGHTNESS 0x09 +#define ECRAM_KBL_TIMEOUT 0x10 +#define ECRAM_KBL_STATE 0x0a +#define ECRAM_TRACKPAD_STATE 0x0c +#define ECRAM_FN_LOCK_STATE 0x0f +#define ECRAM_FN_CTRL_REVERSE 0x17 +#define ECRAM_MAX_CHARGE 0x1a +#define ECRAM_FAN_MODE 0x1b + +#endif diff --git a/src/ec/starlabs/merlin/variants/tgl/emem.asl b/src/ec/starlabs/merlin/variants/tgl/emem.asl new file mode 100644 index 0000000000..09ddc4db45 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/tgl/emem.asl @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + OSFG, 8, // OS Flag + FRMF, 8, // Force Mirror Flag + + Offset(0x07), + SKUI, 8, // SKU ID + CSFG, 8, // Modern Standby Flag + KLBE, 8, // Keyboard Backlight Brightness + KLSE, 8, // Keyboard Backlight State + BDID, 8, // Board ID + TPLE, 8, // Trackpad State + KBCD, 8, // Rotate Flag + WIFI, 8, // WiFi Enable + FLKE, 8, // Function Lock State + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x13), + AUDI, 8, // Control Audio + + Offset(0x15), + SURF, 8, // Chassis Surface Temperature + CHAR, 8, // Charger Temperature + FCLA, 8, // Fn Ctrl Reverse + + Offset(0x1a), + BFCP, 8, // Battery Full Charge Percentage + FANM, 8, // Fan Mode + + Offset(0x1d), + BSRC, 8, // BIOS Recover + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x4B), + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x68), + BATT, 16, // Battery Temperature + BATC, 8, // Battery Temperature Ces + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + TSE1, 8, // Sensor 1 Temperature + TSE3, 8, // Sensor 3 Temperature + + Offset(0x7f), + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xb0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xc0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xd0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xe6), + ECWD, 16, // EC Wakeup Delay + ECWE, 8, // EC Wakeup Enable + + Offset(0xf7), + TBTC, 8, // Thunderbolt Command + TBTP, 8, // Thunderbolt Data Port + TBTD, 8, // Thunderbolt Data + TBTA, 8, // Thunderbolt Acknowledge + TBTG, 16, // Thunderbolt DBG Data +} diff --git a/src/ec/starlabs/merlin/variants/tgl/events.asl b/src/ec/starlabs/merlin/variants/tgl/events.asl new file mode 100644 index 0000000000..6963500d18 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/tgl/events.asl @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q05, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q06, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q87, 0, NotSerialized) // Event: Function Lock +{ + FLKC = FLKE +} + +Method (_Q88, 0, NotSerialized) // Event: Trackpad Lock +{ + TPLC = TPLE +} +Method (_Q4A) // Event: Keyboard Backlight Brightness +{ + KLSC = KLSE + KLBC = KLBE +} + +Method (_Q99, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +Method (_Q22, 0, NotSerialized) // Event: CHARGER_T +{ + Printf ("EC: CHARGER_T") +} + +Method (_Q40, 0, NotSerialized) // Event: AC and DC Power +{ + SMB2 = 0xC6 +} + +Method (_Q41, 0, NotSerialized) // Event: Battery Charge between 0% and 20% +{ + SMB2 = 0xC7 +} + +Method (_Q42, 0, NotSerialized) // Event: Battery Charge between 20% and 60% +{ + SMB2 = 0xC8 +} + +Method (_Q43, 0, NotSerialized) // Event: Battery Charge between 60% and 100% +{ + SMB2 = 0xC9 +} + +Method (_Q44, 0, NotSerialized) // Event: AC Power Only +{ + SMB2 = 0xCA +} + +Method (_Q80, 0, NotSerialized) // Event: Volume Up +{ + Printf ("EC: VOLUME_UP") +} + +Method (_Q81, 0, NotSerialized) // Event: Volume Down +{ + Printf ("EC: VOLUME_DOWN") +} + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_QF0, 0, NotSerialized) // Event: Temperature Report +{ + Printf ("EC: Temperature Report") +} + +Method (_QF1, 0, NotSerialized) // Event: Temperature Trigger +{ + // Notify (SEN3, 0x90) +} + +/* + * The below events are unique to this platform. + */ + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +} + +Method (_Q85, 0, NotSerialized) // Event: HOME +{ + Printf ("EC: HOME") +} + +Method (_Q01, 0, NotSerialized) // Event: F1 Hot Key +{ + Printf ("EC: F1") +} + +Method (_Q02, 0, NotSerialized) // Event: F2 Hot Key +{ + Printf ("EC: F2") +} + +Method (_Q03, 0, NotSerialized) // Event: F3 Hot Key +{ + Printf ("EC: F3") +} + +Method (_Q04, 0, NotSerialized) // Event: F4 Hot Key +{ + Printf ("EC: F4") +} + +Method (_Q08, 0, NotSerialized) // Event: F5 Hot Key +{ + Printf ("EC: F5") +} + +Method (_Q09, 0, NotSerialized) // Event: F6 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q07, 0, NotSerialized) // Event: F7 Hot Key +{ + Printf ("EC: F7") +} + +Method (_Q10, 0, NotSerialized) // Event: F10 Hot Key +{ + Printf ("EC: F10") +} + +Method (_Q12, 0, NotSerialized) // Event: F12 Hot Key +{ + Printf ("EC: F6") +} + +Method (_Q0E, 0, NotSerialized) // Event: SLEEP +{ + Printf ("EC: SLEEP") +} + +Method (_Q13, 0, NotSerialized) // Event: BRIGHTNESS +{ + Printf ("EC: BRIGHTNESS") +} + +Method (_Q20, 0, NotSerialized) // Event: CPU_T +{ + Printf ("EC: CPU_T") +} + +Method (_Q21, 0, NotSerialized) // Event: SKIN_T +{ + Printf ("EC: SKIN_T") +} + +Method (_Q30, 0, NotSerialized) // Event: THROT_OFF +{ + Printf ("EC: THROT_OFF") +} + +Method (_Q31, 0, NotSerialized) // Event: THROT_LV1 +{ + Printf ("EC: THROT_LV1") +} + +Method (_Q32, 0, NotSerialized) // Event: THROT_LV2 +{ + Printf ("EC: THROT_LV2") +} + +Method (_Q33, 0, NotSerialized) // Event: THROT_LV3 +{ + Printf ("EC: THROT_LV3") +} + +Method (_Q34, 0, NotSerialized) // Event: THROT_LV4 +{ + Printf ("EC: THROT_LV4") +} + +Method (_Q35, 0, NotSerialized) // Event: THROT_LV5 +{ + Printf ("EC: THROT_LV5") +} + +Method (_Q36, 0, NotSerialized) // Event: THROT_LV6 +{ + Printf ("EC: THROT_LV6") +} + +Method (_Q37, 0, NotSerialized) // Event: THROT_LV7 +{ + Printf ("EC: THROT_LV7") +} + +Method (_Q38, 0, NotSerialized) // Event: CPU_DN_SPEED +{ + Printf ("EC: CPU_DN_SPEED") +} + +Method (_Q3C, 0, NotSerialized) // Event: CPU_UP_SPEED +{ + Printf ("EC: CPU_UP_SPEED") +} + +Method (_Q3D, 0, NotSerialized) // Event: CPU_TURBO_OFF +{ + Printf ("EC: CPU_TURBO_OFF") +} + +Method (_Q3E, 0, NotSerialized) // Event: CPU_TURBO_ON +{ + Printf ("EC: CPU_TURBO_ON") +} + +Method (_Q3F, 0, NotSerialized) // Event: SHUTDOWN +{ + Printf ("EC: SHUTDOWN") +} + +Method (_Q45, 0, NotSerialized) // Event: SENSOR_T76 +{ + SMB2 = 0xCB +} + +Method (_Q48, 0, NotSerialized) // Event: Fan Turbo On +{ + Printf ("EC: Fan Turbo On") +} + +Method (_Q49, 0, NotSerialized) // Event: Fan Turbo Off +{ + Printf ("EC: Fan Turbo Off") +} diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 4f059bb947..05267a142f 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -31,14 +31,6 @@ #define SLP_TYP_S5 5 #endif -/* ACPI Device Sleep States */ -#define ACPI_DEVICE_SLEEP_D0 0 -#define ACPI_DEVICE_SLEEP_D1 1 -#define ACPI_DEVICE_SLEEP_D2 2 -#define ACPI_DEVICE_SLEEP_D3 3 -#define ACPI_DEVICE_SLEEP_D3_HOT ACPI_DEVICE_SLEEP_D3 -#define ACPI_DEVICE_SLEEP_D3_COLD 4 - #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ #define ACPI_DSDT_REV_1 0x01 /* DSDT revision: ACPI v1 */ @@ -52,6 +44,15 @@ #include #include +enum acpi_device_sleep_states { + ACPI_DEVICE_SLEEP_D0 = 0, + ACPI_DEVICE_SLEEP_D1 = 1, + ACPI_DEVICE_SLEEP_D2 = 2, + ACPI_DEVICE_SLEEP_D3 = 3, + ACPI_DEVICE_SLEEP_D3_HOT = ACPI_DEVICE_SLEEP_D3, + ACPI_DEVICE_SLEEP_D3_COLD = 4, +}; + #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ @@ -745,8 +746,8 @@ typedef struct acpi_fadt { u32 flags; acpi_addr_t reset_reg; u8 reset_value; - u16 ARM_boot_arch; /* Revision 6 only, Revision 5: Must be zero */ - u8 FADT_MinorVersion; /* Revision 6 only, Revision 5: Must be zero */ + u16 ARM_boot_arch; /* Must be zero if ACPI Revision <= 5.0 */ + u8 FADT_MinorVersion; /* Must be zero if ACPI Revision <= 5.0 */ u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -767,12 +768,21 @@ typedef struct acpi_fadt { } __packed acpi_fadt_t; /* FADT TABLE Revision values */ -#define ACPI_FADT_REV_ACPI_1_0 1 -#define ACPI_FADT_REV_ACPI_2_0 3 -#define ACPI_FADT_REV_ACPI_3_0 4 -#define ACPI_FADT_REV_ACPI_4_0 4 -#define ACPI_FADT_REV_ACPI_5_0 5 -#define ACPI_FADT_REV_ACPI_6_0 6 +#define ACPI_FADT_REV_ACPI_1 1 +#define ACPI_FADT_REV_ACPI_2 3 +#define ACPI_FADT_REV_ACPI_3 4 +#define ACPI_FADT_REV_ACPI_4 4 +#define ACPI_FADT_REV_ACPI_5 5 +#define ACPI_FADT_REV_ACPI_6 6 + +/* FADT Minor Version value: + * Bits 0-3: minor version + * Bits 4-7: Errata + * value of 1 means this is compatible with Errata A, + * value of 2 would be compatible with Errata B, and so on + * Version 6.3 Errata A would be: (1 << 4) | 3 + */ +#define ACPI_FADT_MINOR_VERSION_0 0 /* coreboot currently use this version */ /* Flags for p_lvl2_lat and p_lvl3_lat */ #define ACPI_FADT_C2_NOT_SUPPORTED 101 @@ -1215,6 +1225,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); unsigned long fw_cfg_acpi_tables(unsigned long start); /* These are implemented by the target port or north/southbridge. */ +void preload_acpi_dsdt(void); unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); @@ -1230,9 +1241,6 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt); void acpi_fill_gnvs(void); void acpi_fill_cnvs(void); -void update_ssdt(void *ssdt); -void update_ssdtx(void *ssdtx, int i); - unsigned long acpi_fill_lpit(unsigned long current); /* These can be used by the target port. */ @@ -1249,8 +1257,6 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, - u8 lint); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint); @@ -1435,6 +1441,7 @@ static inline uintptr_t acpi_align_current(uintptr_t current) * be made into a weak function if there is ever a need to override the * coreboot default ACPI spec version supported. */ int get_acpi_table_revision(enum acpi_tables table); +u8 get_acpi_fadt_minor_version(void); #endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) diff --git a/src/include/acpi/acpi_pld.h b/src/include/acpi/acpi_pld.h index 5a7663c177..f89a68054e 100644 --- a/src/include/acpi/acpi_pld.h +++ b/src/include/acpi/acpi_pld.h @@ -68,6 +68,33 @@ enum acpi_pld_rotate { .position = __position, \ } +/* + * ACPI specification 6.3 third paragraph of section 6.1.8: + * All Panel references (Top, Bottom, Right, Left, etc.) are interpreted + * as though the user is facing the front of the system. + * + * A `_PLD` describes the offset and rotation of a single device connection point + * from an `origin` that resides in the lower left hand corner of its Panel. + */ + +#define ACPI_PLD_TYPE_A(__panel, __horiz, __grp) \ + { \ + .visible = true, \ + .panel = PLD_PANEL_##__panel, \ + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, \ + .horizontal_position = PLD_HORIZONTAL_POSITION_##__horiz, \ + .group = __grp, \ + } + +#define ACPI_PLD_TYPE_C(__panel, __horiz, __grp) \ + { \ + .visible = true, \ + .panel = PLD_PANEL_##__panel, \ + .shape = PLD_SHAPE_OVAL, \ + .horizontal_position = PLD_HORIZONTAL_POSITION_##__horiz, \ + .group = __grp, \ + } + struct acpi_pld_group { uint8_t token; uint8_t position; diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 463c16d2b2..2a3e930d4d 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -235,6 +235,8 @@ struct dsm_uuid { #define CPPC_VERSION_2 2 #define CPPC_VERSION_3 3 +#define CPPC_PACKAGE_NAME "GCPC" + /*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ enum cppc_fields { CPPC_HIGHEST_PERF, /* can be DWORD */ @@ -298,6 +300,8 @@ struct cppc_config { cppc_entry_t entries[CPPC_MAX_FIELDS_VER_3]; }; +#define ACPI_MUTEX_NO_TIMEOUT 0xffff + void acpigen_write_return_integer(uint64_t arg); void acpigen_write_return_namestr(const char *arg); void acpigen_write_return_string(const char *arg); diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index de57adc5f5..758398d8e4 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -24,6 +24,7 @@ enum dptf_participant { DPTF_TEMP_SENSOR_1, DPTF_TEMP_SENSOR_2, DPTF_TEMP_SENSOR_3, + DPTF_TEMP_SENSOR_4, DPTF_TPCH, DPTF_PARTICIPANT_COUNT, }; @@ -44,7 +45,7 @@ enum { DPTF_FIELD_UNUSED = 0xFFFFFFFFull, /* Max supported by DPTF */ - DPTF_MAX_TSR = 4, + DPTF_MAX_TSR = 5, }; /* Active Policy */ diff --git a/src/include/acpi/acpigen_ps2_keybd.h b/src/include/acpi/acpigen_ps2_keybd.h index e32ca2a334..7dd82822f7 100644 --- a/src/include/acpi/acpigen_ps2_keybd.h +++ b/src/include/acpi/acpigen_ps2_keybd.h @@ -26,6 +26,7 @@ enum ps2_action_key { PS2_KEY_PREV_TRACK, PS2_KEY_KBD_BKLIGHT_TOGGLE, PS2_KEY_MICMUTE, + PS2_KEY_MENU, }; #define PS2_MIN_TOP_ROW_KEYS 10 diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h index efc31f349b..8042874ba1 100644 --- a/src/include/acpi/acpigen_usb.h +++ b/src/include/acpi/acpigen_usb.h @@ -3,6 +3,8 @@ #ifndef ACPI_ACPIGEN_USB_H #define ACPI_ACPIGEN_USB_H +#include + enum usb_typec_power_role { TYPEC_POWER_ROLE_SOURCE, TYPEC_POWER_ROLE_SINK, @@ -39,6 +41,7 @@ enum usb_typec_data_role { * host or device, for the USB port * @mode_switch: Reference to the ACPI device that controls routing of data lines to * various endpoints (xHCI, DP, etc.) on the SoC. + * @pld: Reference to PLD information. */ struct typec_connector_class_config { enum usb_typec_power_role power_role; @@ -50,6 +53,7 @@ struct typec_connector_class_config { const struct device *orientation_switch; const struct device *usb_role_switch; const struct device *mode_switch; + const struct acpi_pld *pld; }; typedef void (*add_custom_dsd_property_cb)(struct acpi_dp *dsd, int port_number); diff --git a/src/include/bootmode.h b/src/include/bootmode.h index aadecba334..da2dbf6565 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -11,6 +11,7 @@ int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); +int get_ec_is_trusted(void); /* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 0d8ac60375..5731d6efd8 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -5,8 +5,9 @@ #include #include -#include #include +#include +#include #include #include #include @@ -54,6 +55,11 @@ * section), even when running in an RW stage from one of the RW CBFSs. Only relevant if * CONFIG(VBOOT) is set. * + * ..._unverified_area_...: Will look for the CBFS file in the named FMAP area, rather than + * any of the default (RO or RW) CBFSs. Files accessed this way are *not* verified in any + * way (even if CONFIG(CBFS_VERIFICATION) is enabled) and should always be treated as + * untrusted (potentially malicious) data. Mutually exclusive with the ..._ro_... variant. + * * ..._type_...: May pass in an extra enum cbfs_type *type parameter. If the value it points to * is CBFS_TYPE_QUERY, it will be replaced with the actual CBFS type of the found file. If * it is anything else, the type will be compared with the actually found type, and the @@ -75,11 +81,15 @@ static inline size_t cbfs_type_load(const char *name, void *buf, size_t size, enum cbfs_type *type); static inline size_t cbfs_ro_type_load(const char *name, void *buf, size_t size, enum cbfs_type *type); +static inline size_t cbfs_unverified_area_load(const char *area, const char *name, + void *buf, size_t size); static inline void *cbfs_map(const char *name, size_t *size_out); static inline void *cbfs_ro_map(const char *name, size_t *size_out); static inline void *cbfs_type_map(const char *name, size_t *size_out, enum cbfs_type *type); static inline void *cbfs_ro_type_map(const char *name, size_t *size_out, enum cbfs_type *type); +static inline void *cbfs_unverified_area_map(const char *area, const char *name, + size_t *size_out); static inline void *cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out); @@ -89,6 +99,9 @@ static inline void *cbfs_type_alloc(const char *name, cbfs_allocator_t allocator size_t *size_out, enum cbfs_type *type); static inline void *cbfs_ro_type_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out, enum cbfs_type *type); +static inline void *cbfs_unverified_area_alloc(const char *area, const char *name, + cbfs_allocator_t allocator, void *arg, + size_t *size_out); static inline void *cbfs_cbmem_alloc(const char *name, uint32_t cbmem_id, size_t *size_out); static inline void *cbfs_ro_cbmem_alloc(const char *name, uint32_t cbmem_id, size_t *size_out); @@ -96,6 +109,23 @@ static inline void *cbfs_type_cbmem_alloc(const char *name, uint32_t cbmem_id, s enum cbfs_type *type); static inline void *cbfs_ro_type_cbmem_alloc(const char *name, uint32_t cbmem_id, size_t *size_out, enum cbfs_type *type); +static inline void *cbfs_unverified_area_cbmem_alloc(const char *area, const char *name, + uint32_t cbmem_id, size_t *size_out); + +/* + * Starts the processes of preloading a file into RAM. + * + * This method depends on COOP_MULTITASKING to parallelize the loading. This method is only + * effective when the underlying rdev supports DMA operations. + * + * When `cbfs_load`, `cbfs_alloc`, or `cbfs_map` are called after a preload has been started, + * they will wait for the preload to complete (if it hasn't already) and then perform + * verification and/or decompression. + * + * This method does not have a return value because the system should boot regardless if this + * method succeeds or fails. + */ +void cbfs_preload(const char *name); /* Removes a previously allocated CBFS mapping. Should try to unmap mappings in strict LIFO order where possible, since mapping backends often don't support more complicated cases. */ @@ -104,6 +134,20 @@ void cbfs_unmap(void *mapping); /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); +/* Returns the size of a CBFS file, or 0 on error. Avoid using this function to allocate space, + and instead use cbfs_alloc() so the file only needs to be looked up once. */ +static inline size_t cbfs_get_size(const char *name); +static inline size_t cbfs_ro_get_size(const char *name); + +/* Returns the type of a CBFS file, or CBFS_TYPE_NULL on error. Use cbfs_type_load() instead of + this where possible to avoid looking up the file more than once. */ +static inline enum cbfs_type cbfs_get_type(const char *name); +static inline enum cbfs_type cbfs_ro_get_type(const char *name); + +/* Check whether a CBFS file exists. */ +static inline bool cbfs_file_exists(const char *name); +static inline bool cbfs_ro_file_exists(const char *name); + /********************************************************************************************** * BOOT DEVICE HELPER APIs * @@ -145,22 +189,18 @@ cb_err_t cbfs_init_boot_device(const struct cbfs_boot_device *cbd, struct vb2_hash *metadata_hash); -/********************************************************************************************** - * LEGACY APIs, TO BE DEPRECATED/REPLACED * - **********************************************************************************************/ - -/* Locate file by name and optional type. Return 0 on success. < 0 on error. */ -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type); - /********************************************************************************************** * INTERNAL HELPERS FOR INLINES, DO NOT USE. * **********************************************************************************************/ +cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev); + void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out, bool force_ro, enum cbfs_type *type); +void *_cbfs_unverified_area_alloc(const char *area, const char *name, + cbfs_allocator_t allocator, void *arg, size_t *size_out); + struct _cbfs_default_allocator_arg { void *buf; size_t buf_size; @@ -196,6 +236,13 @@ static inline void *cbfs_ro_type_alloc(const char *name, cbfs_allocator_t alloca return _cbfs_alloc(name, allocator, arg, size_out, true, type); } +static inline void *cbfs_unverified_area_alloc(const char *area, const char *name, + cbfs_allocator_t allocator, void *arg, + size_t *size_out) +{ + return _cbfs_unverified_area_alloc(area, name, allocator, arg, size_out); +} + static inline void *cbfs_map(const char *name, size_t *size_out) { return cbfs_type_map(name, size_out, NULL); @@ -216,6 +263,12 @@ static inline void *cbfs_ro_type_map(const char *name, size_t *size_out, enum cb return cbfs_ro_type_alloc(name, NULL, NULL, size_out, type); } +static inline void *cbfs_unverified_area_map(const char *area, const char *name, + size_t *size_out) +{ + return _cbfs_unverified_area_alloc(area, name, NULL, NULL, size_out); +} + static inline size_t _cbfs_load(const char *name, void *buf, size_t size, bool force_ro, enum cbfs_type *type) { @@ -248,6 +301,16 @@ static inline size_t cbfs_ro_type_load(const char *name, void *buf, size_t size, return _cbfs_load(name, buf, size, true, type); } +static inline size_t cbfs_unverified_area_load(const char *area, const char *name, + void *buf, size_t size) +{ + struct _cbfs_default_allocator_arg arg = { .buf = buf, .buf_size = size }; + if (_cbfs_unverified_area_alloc(area, name, _cbfs_default_allocator, &arg, &size)) + return size; + else + return 0; +} + static inline void *cbfs_cbmem_alloc(const char *name, uint32_t cbmem_id, size_t *size_out) { return cbfs_type_cbmem_alloc(name, cbmem_id, size_out, NULL); @@ -272,4 +335,65 @@ static inline void *cbfs_ro_type_cbmem_alloc(const char *name, uint32_t cbmem_id size_out, type); } +static inline void *cbfs_unverified_area_cbmem_alloc(const char *area, const char *name, + uint32_t cbmem_id, size_t *size_out) +{ + return _cbfs_unverified_area_alloc(area, name, _cbfs_cbmem_allocator, + (void *)(uintptr_t)cbmem_id, size_out); +} + +static inline size_t cbfs_get_size(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return 0; + return be32toh(mdata.h.len); +} + +static inline size_t cbfs_ro_get_size(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return 0; + return be32toh(mdata.h.len); +} + +static inline enum cbfs_type cbfs_get_type(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return CBFS_TYPE_NULL; + return be32toh(mdata.h.type); +} + +static inline enum cbfs_type cbfs_ro_get_type(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return CBFS_TYPE_NULL; + return be32toh(mdata.h.type); +} + +static inline bool cbfs_file_exists(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, false, &mdata, &rdev) != CB_SUCCESS) + return false; + return true; +} + +static inline bool cbfs_ro_file_exists(const char *name) +{ + union cbfs_mdata mdata; + struct region_device rdev; + if (_cbfs_boot_lookup(name, true, &mdata, &rdev) != CB_SUCCESS) + return false; + return true; +} + #endif diff --git a/src/include/cbfs_private.h b/src/include/cbfs_private.h deleted file mode 100644 index 8e9803616f..0000000000 --- a/src/include/cbfs_private.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CBFS_PRIVATE_H_ -#define _CBFS_PRIVATE_H_ - -#include -#include -#include - -/* - * This header contains low-level CBFS APIs that should only be used by code - * that really needs this level of access. Most code (particularly platform - * code) should use the higher-level CBFS APIs in . Code using these - * APIs needs to take special care to ensure CBFS file data is verified (in a - * TOCTOU-safe manner) before access (TODO: add details on how to do this once - * file verification code is in). - */ - -/* Find by name, load metadata into |mdata| and chain file data to |rdev|. */ -cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, - union cbfs_mdata *mdata, struct region_device *rdev); - -#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ec2b928ff8..cd7751cab1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -3,7 +3,7 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ -#include +#include #include #include #include diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 3eb278db98..4f03a45e74 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -3,6 +3,7 @@ #define _CONSOLE_CBMEM_CONSOLE_H_ #include +#include void cbmemc_init(void); void cbmemc_tx_byte(unsigned char data); @@ -19,5 +20,11 @@ static inline void __cbmemc_init(void) {} static inline void __cbmemc_tx_byte(u8 data) {} #endif +/* + * Copy an external cbmem_console into the active cbmem_console. + */ +void cbmemc_copy_in(void *buffer, size_t size); + +void cbmem_dump_console_to_uart(void); void cbmem_dump_console(void); #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 8849df363c..e4090af48b 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -47,6 +47,7 @@ static inline int get_console_loglevel(void) ENV_LIBAGESA || (ENV_SMM && CONFIG(DEBUG_SMI))) #if __CONSOLE_ENABLE__ +int get_log_level(void); void console_init(void); int console_log_level(int msg_level); @@ -60,8 +61,20 @@ void do_putchar(unsigned char byte); long console_time_get_and_reset(void); void console_time_report(void); +/* + * "Fast" basically means only the CBMEM console right now. This is used to still + * print debug messages there when loglevel disables the other consoles. It is also + * used to compile-time eliminate code paths that only affect "interactive" consoles + * (which are all "slow") when none of those are enabled. + */ enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; +#define HAS_ONLY_FAST_CONSOLES !(CONFIG(SPKMODEM) || CONFIG(CONSOLE_QEMU_DEBUGCON) || \ + CONFIG(CONSOLE_SERIAL) || CONFIG(CONSOLE_NE2K) || CONFIG(CONSOLE_USB) || \ + CONFIG(EM100PRO_SPI_CONSOLE) || CONFIG(CONSOLE_SPI_FLASH) || \ + CONFIG(CONSOLE_SYSTEM76_EC)) + #else +static inline int get_log_level(void) { return -1; } static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } static inline int diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 44d96e2cc3..f8b1216aac 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -10,6 +10,11 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* Interactive consoles that are usually displayed in real time on a terminal. */ +void console_interactive_tx_byte(unsigned char byte, void *data_unused); +/* Consoles that store logs on some medium for later retrieval. */ +void console_stored_tx_byte(unsigned char byte, void *data_unused); + /* * Write number_of_bytes data bytes from buffer to the serial device. * If number_of_bytes is zero, wait until all serial data is output. diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 800661b797..74075944bb 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -2,5 +2,6 @@ #define CPU_AMD_MICROCODE_H void amd_update_microcode_from_cbfs(void); +void preload_microcode(void); #endif /* CPU_AMD_MICROCODE_H */ diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 608a9df1ec..6fe1628bc0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -43,7 +43,6 @@ #include #include -void amd_setup_mtrrs(void); struct device; void add_uma_resource_below_tolm(struct device *nb, int idx); @@ -67,10 +66,16 @@ static __always_inline void wrmsr_amd(unsigned int index, msr_t msr) ); } -/* To distribute topmem MSRs to APs. */ -void setup_bsp_ramtop(void); -uint64_t bsp_topmem(void); -uint64_t bsp_topmem2(void); +static inline uint64_t amd_topmem(void) +{ + return rdmsr(TOP_MEM).lo; +} + +static inline uint64_t amd_topmem2(void) +{ + msr_t msr = rdmsr(TOP_MEM2); + return (uint64_t)msr.hi << 32 | msr.lo; +} #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 7d3c715b53..cf59fd2054 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -56,5 +56,6 @@ #define CPUID_ALDERLAKE_A1 0x906a1 #define CPUID_ALDERLAKE_A2 0x906a2 #define CPUID_ALDERLAKE_A3 0x906a4 +#define CPUID_ALDERLAKE_N_A0 0xb06e0 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/cpu/power/scom.h b/src/include/cpu/power/scom.h new file mode 100644 index 0000000000..ef5796c4e1 --- /dev/null +++ b/src/include/cpu/power/scom.h @@ -0,0 +1,161 @@ +#ifndef CPU_PPC64_SCOM_H +#define CPU_PPC64_SCOM_H + +#include // PPC_BIT(), PPC_BITMASK() + +// 32b SCOM address: +// +// 8 7 6 5 4 3 2 1 +// +// | | | | | 1 1| |1 1 1 1| |1 1 1 1| |2 2 2 2| |2 2 2 2| |2 2 3 3| +// |0 1 2 3| |4 5 6 7| |8 9 0 1| |2 3 4 5| |6 7 8 9| |0 1 2 3| |4 5 6 7| |8 9 0 1| +// {A}{ B } { C } { D }{ E }{ F } +// +// A - Is multiCast if bit 1 = 0x1 +// B - Contains Chiplet ID (6 bits) [2:7] +// C - Contains Port Number (4 bits) [12:15] +// D - Ring (4 bits) [18:21] +// E - Sat ID (4 bits) [22:25] +// F - Sat Offset (6 bits) [26:31] +// +// For 64b SCOM address all of the fields are shifted 32b to the right: +// A - Is multiCast if bit 33 = 0x1 +// B - Contains Chiplet ID (6 bits) [34:39] +// C - Contains Port Number (4 bits) [44:47] +// D - Ring (4 bits) [50:53] +// E - Sat ID (4 bits) [54:57] +// F - Sat Offset (6 bits) [58:63] +// Higher bits specify indirect address + +#define XSCOM_ADDR_IND_FLAG PPC_BIT(0) +#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11, 31) +#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48, 63) + +#ifndef __ASSEMBLER__ +#include +#include +#include + +// TODO: these are probably specific to POWER9 +typedef enum { + PIB_CHIPLET_ID = 0x00, ///< PIB chiplet + PERV_CHIPLET_ID = 0x01, ///< TP chiplet + N0_CHIPLET_ID = 0x02, ///< Nest0 (North) chiplet + N1_CHIPLET_ID = 0x03, ///< Nest1 (East) chiplet + N2_CHIPLET_ID = 0x04, ///< Nest2 (South) chiplet + N3_CHIPLET_ID = 0x05, ///< Nest3 (West) chiplet + XB_CHIPLET_ID = 0x06, ///< XBus chiplet + MC01_CHIPLET_ID = 0x07, ///< MC01 (West) chiplet + MC23_CHIPLET_ID = 0x08, ///< MC23 (East) chiplet + OB0_CHIPLET_ID = 0x09, ///< OBus0 chiplet + OB1_CHIPLET_ID = 0x0A, ///< OBus1 chiplet (Cumulus only) + OB2_CHIPLET_ID = 0x0B, ///< OBus2 chiplet (Cumulus only) + OB3_CHIPLET_ID = 0x0C, ///< OBus3 chiplet + PCI0_CHIPLET_ID = 0x0D, ///< PCIe0 chiplet + PCI1_CHIPLET_ID = 0x0E, ///< PCIe1 chiplet + PCI2_CHIPLET_ID = 0x0F, ///< PCIe2 chiplet + EP00_CHIPLET_ID = 0x10, ///< Quad0 chiplet (EX0/1) + EP01_CHIPLET_ID = 0x11, ///< Quad1 chiplet (EX2/3) + EP02_CHIPLET_ID = 0x12, ///< Quad2 chiplet (EX4/5) + EP03_CHIPLET_ID = 0x13, ///< Quad3 chiplet (EX6/7) + EP04_CHIPLET_ID = 0x14, ///< Quad4 chiplet (EX8/9) + EP05_CHIPLET_ID = 0x15, ///< Quad5 chiplet (EX10/11) + EC00_CHIPLET_ID = 0x20, ///< Core0 chiplet (Quad0, EX0, C0) + EC01_CHIPLET_ID = 0x21, ///< Core1 chiplet (Quad0, EX0, C1) + EC02_CHIPLET_ID = 0x22, ///< Core2 chiplet (Quad0, EX1, C0) + EC03_CHIPLET_ID = 0x23, ///< Core3 chiplet (Quad0, EX1, C1) + EC04_CHIPLET_ID = 0x24, ///< Core4 chiplet (Quad1, EX2, C0) + EC05_CHIPLET_ID = 0x25, ///< Core5 chiplet (Quad1, EX2, C1) + EC06_CHIPLET_ID = 0x26, ///< Core6 chiplet (Quad1, EX3, C0) + EC07_CHIPLET_ID = 0x27, ///< Core7 chiplet (Quad1, EX3, C1) + EC08_CHIPLET_ID = 0x28, ///< Core8 chiplet (Quad2, EX4, C0) + EC09_CHIPLET_ID = 0x29, ///< Core9 chiplet (Quad2, EX4, C1) + EC10_CHIPLET_ID = 0x2A, ///< Core10 chiplet (Quad2, EX5, C0) + EC11_CHIPLET_ID = 0x2B, ///< Core11 chiplet (Quad2, EX5, C1) + EC12_CHIPLET_ID = 0x2C, ///< Core12 chiplet (Quad3, EX6, C0) + EC13_CHIPLET_ID = 0x2D, ///< Core13 chiplet (Quad3, EX6, C1) + EC14_CHIPLET_ID = 0x2E, ///< Core14 chiplet (Quad3, EX7, C0) + EC15_CHIPLET_ID = 0x2F, ///< Core15 chiplet (Quad3, EX7, C1) + EC16_CHIPLET_ID = 0x30, ///< Core16 chiplet (Quad4, EX8, C0) + EC17_CHIPLET_ID = 0x31, ///< Core17 chiplet (Quad4, EX8, C1) + EC18_CHIPLET_ID = 0x32, ///< Core18 chiplet (Quad4, EX9, C0) + EC19_CHIPLET_ID = 0x33, ///< Core19 chiplet (Quad4, EX9, C1) + EC20_CHIPLET_ID = 0x34, ///< Core20 chiplet (Quad5, EX10, C0) + EC21_CHIPLET_ID = 0x35, ///< Core21 chiplet (Quad5, EX10, C1) + EC22_CHIPLET_ID = 0x36, ///< Core22 chiplet (Quad5, EX11, C0) + EC23_CHIPLET_ID = 0x37 ///< Core23 chiplet (Quad5, EX11, C1) +} chiplet_id_t; + +void reset_scom_engine(void); + +uint64_t read_scom_direct(uint64_t reg_address); +void write_scom_direct(uint64_t reg_address, uint64_t data); + +uint64_t read_scom_indirect(uint64_t reg_address); +void write_scom_indirect(uint64_t reg_address, uint64_t data); + +static inline void write_scom(uint64_t addr, uint64_t data) +{ + if (addr & XSCOM_ADDR_IND_FLAG) + write_scom_indirect(addr, data); + else + write_scom_direct(addr, data); +} + +static inline uint64_t read_scom(uint64_t addr) +{ + if (addr & XSCOM_ADDR_IND_FLAG) + return read_scom_indirect(addr); + else + return read_scom_direct(addr); +} + +static inline void scom_and_or(uint64_t addr, uint64_t and, uint64_t or) +{ + uint64_t data = read_scom(addr); + write_scom(addr, (data & and) | or); +} + +static inline void scom_and(uint64_t addr, uint64_t and) +{ + scom_and_or(addr, and, 0); +} + +static inline void scom_or(uint64_t addr, uint64_t or) +{ + scom_and_or(addr, ~0, or); +} + +static inline void write_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t data) +{ + addr &= ~PPC_BITMASK(34, 39); + addr |= ((chiplet & 0x3F) << 24); + write_scom(addr, data); +} + +static inline uint64_t read_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr) +{ + addr &= ~PPC_BITMASK(34, 39); + addr |= ((chiplet & 0x3F) << 24); + return read_scom(addr); +} + +static inline void scom_and_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, + uint64_t and, uint64_t or) +{ + uint64_t data = read_scom_for_chiplet(chiplet, addr); + write_scom_for_chiplet(chiplet, addr, (data & and) | or); +} + +static inline void scom_and_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t and) +{ + scom_and_or_for_chiplet(chiplet, addr, and, 0); +} + +static inline void scom_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t or) +{ + scom_and_or_for_chiplet(chiplet, addr, ~0, or); +} + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_PPC64_SCOM_H */ diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h new file mode 100644 index 0000000000..3b229f73a3 --- /dev/null +++ b/src/include/cpu/power/spr.h @@ -0,0 +1,73 @@ +#ifndef CPU_PPC64_SPR_H +#define CPU_PPC64_SPR_H + +#include // PPC_BIT() + +#define SPR_TB 0x10C + +#define SPR_PVR 0x11F +#define SPR_PVR_REV_MASK (PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63)) +#define SPR_PVR_REV(maj, min) (PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63)) + +#define SPR_HSPRG0 0x130 +#define SPR_HSPRG1 0x131 + +#define SPR_HRMOR 0x139 + +#define SPR_HMER 0x150 +/* Bits in HMER/HMEER */ +#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0) +#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2) +#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3) +#define SPR_HMER_TFAC_ERROR PPC_BIT(4) +#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5) +#define SPR_HMER_XSCOM_FAIL PPC_BIT(8) +#define SPR_HMER_XSCOM_DONE PPC_BIT(9) +#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11) +#define SPR_HMER_WARN_RISE PPC_BIT(14) +#define SPR_HMER_WARN_FALL PPC_BIT(15) +#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16) +#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17) +#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20) +#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21, 23) +#define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23) + +#ifndef __ASSEMBLER__ +#include + +static inline uint64_t read_spr(int spr) +{ + uint64_t val; + asm volatile("mfspr %0,%1" : "=r"(val) : "i"(spr) : "memory"); + return val; +} + +static inline void write_spr(int spr, uint64_t val) +{ + asm volatile("mtspr %0, %1" :: "i"(spr), "r"(val) : "memory"); +} + +static inline uint64_t read_hmer(void) +{ + return read_spr(SPR_HMER); +} + +static inline void clear_hmer(void) +{ + write_spr(SPR_HMER, 0); +} + +static inline uint64_t read_msr(void) +{ + uint64_t val; + asm volatile("mfmsr %0" : "=r"(val) :: "memory"); + return val; +} + +static inline uint64_t pvr_revision(void) +{ + return read_spr(SPR_PVR) & SPR_PVR_REV_MASK; +} + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_PPC64_SPR_H */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 05d096e318..c509e61b08 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -18,9 +18,9 @@ static __always_inline void xapic_write(unsigned int reg, uint32_t v) write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); } -static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) +static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t icrhi) { - xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + xapic_write(LAPIC_ICR2, icrhi); xapic_write(LAPIC_ICR, icrlow); } @@ -51,15 +51,15 @@ static __always_inline void x2apic_write(unsigned int reg, uint32_t v) wrmsr(index, msr); } -static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) +static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t icrhi) { msr_t icr; - icr.hi = apicid; + icr.hi = icrhi; icr.lo = icrlow; wrmsr(X2APIC_MSR_ICR_ADDRESS, icr); } -static inline bool is_x2apic_mode(void) +static __always_inline bool is_x2apic_mode(void) { if (CONFIG(XAPIC_ONLY)) return false; @@ -112,7 +112,7 @@ static __always_inline void lapic_send_ipi(uint32_t icrlow, uint32_t apicid) if (is_x2apic_mode()) x2apic_send_ipi(icrlow, apicid); else - xapic_send_ipi(icrlow, apicid); + xapic_send_ipi(icrlow, SET_LAPIC_DEST_FIELD(apicid)); } static __always_inline int lapic_busy(void) @@ -143,6 +143,25 @@ static __always_inline unsigned int lapicid(void) return lapicid; } +static __always_inline void lapic_send_ipi_self(uint32_t icrlow) +{ + int i = 1000; + + /* LAPIC_DEST_SELF does not support all delivery mode -fields. */ + lapic_send_ipi(icrlow, lapicid()); + + /* In case of X2APIC force a short delay, to prevent deadlock in a case + * the immediately following code acquires some lock, like with printk(). + */ + while (CONFIG(X2APIC_ONLY) && i--) + cpu_relax(); +} + +static __always_inline void lapic_send_ipi_others(uint32_t icrlow) +{ + lapic_send_ipi(LAPIC_DEST_ALLBUT | icrlow, 0); +} + #if !CONFIG(AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_stop.c @@ -158,6 +177,6 @@ void stop_this_cpu(void); void enable_lapic(void); void disable_lapic(void); -void setup_lapic(void); +void setup_lapic_interrupts(void); #endif /* CPU_X86_LAPIC_H */ diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 7ed82dda42..1b4c956b59 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -3,7 +3,6 @@ #ifndef _X86_MP_H_ #define _X86_MP_H_ -#include #include #include @@ -45,17 +44,6 @@ struct mp_ops { * can load the microcode in parallel. */ void (*get_microcode_info)(const void **microcode, int *parallel); - /* - * Optionally adjust SMM handler parameters to override the default - * values. The is_perm variable indicates if the parameters to adjust - * are for the relocation handler or the permanent handler. This - * function is therefore called twice -- once for each handler. - * By default the parameters for each SMM handler are: - * stack_size num_concurrent_stacks num_concurrent_save_states - * relo: save_state_size get_cpu_count() 1 - * perm: save_state_size get_cpu_count() get_cpu_count() - */ - void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); /* * Optionally provide a callback prior to the APs starting SMM * relocation or CPU driver initialization. However, note that @@ -93,13 +81,11 @@ struct mp_ops { * 3. get_smm_info() * 4. get_microcode_info() * 5. adjust_cpu_apic_entry() for each number of get_cpu_count() - * 6. adjust_smm_params(is_perm = 0) - * 7. adjust_smm_params(is_perm = 1) - * 8. pre_mp_smm_init() - * 9. per_cpu_smm_trigger() in parallel for all cpus which calls + * 6. pre_mp_smm_init() + * 7. per_cpu_smm_trigger() in parallel for all cpus which calls * relocation_handler() in SMM. - * 10. mp_initialize_cpu() for each cpu - * 11. post_mp_init() + * 8. mp_initialize_cpu() for each cpu + * 9. post_mp_init() */ enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops); diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index a8d5e2211b..4d1cb68279 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -24,6 +24,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define CPUID_DCA (1 << 18) +#define CPUID_X2APIC (1 << 21) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) diff --git a/src/include/cpu/x86/smi_deprecated.h b/src/include/cpu/x86/smi_deprecated.h index 6213915eee..262aa0b695 100644 --- a/src/include/cpu/x86/smi_deprecated.h +++ b/src/include/cpu/x86/smi_deprecated.h @@ -3,16 +3,8 @@ #ifndef __X86_SMI_DEPRECATED_H__ #define __X86_SMI_DEPRECATED_H__ -#include - -#if CONFIG(PARALLEL_MP) || !CONFIG(HAVE_SMI_HANDLER) -/* Empty stubs for platforms without SMI handlers. */ -static inline void smm_init(void) { } -static inline void smm_init_completion(void) { } -#else void smm_init(void); void smm_init_completion(void); -#endif /* Entry from smmhandler.S. */ void smi_handler(void); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 08404d0320..8ea8336a2d 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -120,10 +120,7 @@ static inline bool smm_points_to_smram(const void *ptr, const size_t len) /* SMM Module Loading API */ /* The smm_loader_params structure provides direction to the SMM loader: - * - stack_top - optional external stack provided to loader. It must be at - * least per_cpu_stack_size * num_concurrent_stacks in size. - * - per_cpu_stack_size - stack size per CPU for smm modules. - * - num_concurrent_stacks - number of concurrent cpus in handler needing stack + * - num_cpus - number of concurrent cpus in handler needing stack * optional for setting up relocation handler. * - per_cpu_save_state_size - the SMM save state size per cpu * - num_concurrent_save_states - number of concurrent cpus needing save state @@ -135,9 +132,7 @@ static inline bool smm_points_to_smram(const void *ptr, const size_t len) * handle sparse APIC id space. */ struct smm_loader_params { - void *stack_top; - size_t per_cpu_stack_size; - size_t num_concurrent_stacks; + size_t num_cpus; size_t real_cpu_save_state_size; size_t per_cpu_save_state_size; @@ -148,9 +143,11 @@ struct smm_loader_params { struct smm_stub_params *stub_params; }; -/* Both of these return 0 on success, < 0 on failure. */ -int smm_setup_relocation_handler(void * const perm_smram, struct smm_loader_params *params); -int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); +/* All of these return 0 on success, < 0 on failure. */ +int smm_setup_stack(const uintptr_t perm_smbase, const size_t perm_smram_size, + const unsigned int total_cpus, const size_t stack_size); +int smm_setup_relocation_handler(struct smm_loader_params *params); +int smm_load_module(uintptr_t smram_base, size_t smram_size, struct smm_loader_params *params); u32 smm_get_cpu_smbase(unsigned int cpu_num); diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9010507aee..1562e25c48 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -23,6 +23,8 @@ int azalia_enter_reset(u8 *base); int azalia_exit_reset(u8 *base); u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb); int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size); +void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes); +void azalia_codecs_init(u8 *base, u16 codec_mask); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; @@ -126,26 +128,27 @@ enum azalia_pin_location_2 { ARRAY_SIZE(pc_beep_verbs); \ const u32 cim_verb_data_size = sizeof(cim_verb_data) -#define AZALIA_PIN_CFG(codec, pin, val) \ - (((codec) << 28) | ((pin) << 20) | (0x71c << 8) \ - | ((val) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71d << 8) \ - | (((val) >> 8) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71e << 8) \ - | (((val) >> 16) & 0xff)), \ - (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \ - | (((val) >> 24) & 0xff)) +#define AZALIA_VERB_12B(codec, pin, verb, val) \ + ((codec) << 28 | (pin) << 20 | (verb) << 8 | (val)) -#define AZALIA_PIN_CFG_NC(n) (0x411111f0 | (n & 0xf)) +#define AZALIA_PIN_CFG(codec, pin, val) \ + AZALIA_VERB_12B(codec, pin, 0x71c, ((val) >> 0) & 0xff), \ + AZALIA_VERB_12B(codec, pin, 0x71d, ((val) >> 8) & 0xff), \ + AZALIA_VERB_12B(codec, pin, 0x71e, ((val) >> 16) & 0xff), \ + AZALIA_VERB_12B(codec, pin, 0x71f, ((val) >> 24) & 0xff) -#define AZALIA_RESET(pin) \ - (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00), \ - (((pin) << 20) | 0x7ff00), (((pin) << 20) | 0x7ff00) +#define AZALIA_PIN_CFG_NC(n) (0x411111f0 | ((n) & 0xf)) -#define AZALIA_SUBVENDOR(codec, val) \ - (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \ - (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \ - (((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \ - (((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff)) +#define AZALIA_RESET(pin) \ + AZALIA_VERB_12B(0, pin, 0x7ff, 0), \ + AZALIA_VERB_12B(0, pin, 0x7ff, 0), \ + AZALIA_VERB_12B(0, pin, 0x7ff, 0), \ + AZALIA_VERB_12B(0, pin, 0x7ff, 0) + +#define AZALIA_SUBVENDOR(codec, val) \ + AZALIA_VERB_12B(codec, 1, 0x720, ((val) >> 0) & 0xff), \ + AZALIA_VERB_12B(codec, 1, 0x721, ((val) >> 8) & 0xff), \ + AZALIA_VERB_12B(codec, 1, 0x722, ((val) >> 16) & 0xff), \ + AZALIA_VERB_12B(codec, 1, 0x723, ((val) >> 24) & 0xff) #endif /* DEVICE_AZALIA_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index 8610e0a4c6..237d836147 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -148,6 +148,17 @@ struct device { u8 smbios_slot_data_width; u8 smbios_slot_length; const char *smbios_slot_designation; + +#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE) + /* + * These fields are intentionally guarded so that attempts to use + * the corresponding devicetree syntax without selecting the Kconfig + * option result in build-time errors. Smaller size is a side effect. + */ + bool smbios_instance_id_valid; + u8 smbios_instance_id; + const char *smbios_refdes; +#endif #endif #endif DEVTREE_CONST void *chip_info; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 9ec5248af7..b109a15a61 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -32,21 +32,6 @@ #define SPD_DIMM_PART_LEN 18 /** @} */ -/** - * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) - * - * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically - * disabled. - * @{ - */ -#if CONFIG(DEBUG_RAM_SETUP) -#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) -#else -#define printram(x, ...) -#endif -/** @} */ - /* * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR3. DDR2 SPDs have a different structure. diff --git a/src/include/device/dram/spd.h b/src/include/device/dram/spd.h index c677f4ce9b..1a86ea374f 100644 --- a/src/include/device/dram/spd.h +++ b/src/include/device/dram/spd.h @@ -3,8 +3,18 @@ #ifndef DEVICE_DRAM_SPD_H #define DEVICE_DRAM_SPD_H +#include #include const char *spd_manufacturer_name(const uint16_t mod_id); +struct spd_info { + uint16_t type_detail; + uint8_t form_factor; +}; + +void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info); +uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type, + smbios_memory_form_factor form_factor); + #endif /* DEVICE_DRAM_SPD_H */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 22a5390e05..1c4a3e76ef 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -385,6 +385,7 @@ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ @@ -459,10 +460,11 @@ #define PCI_EXT_CAP_ID_PWR 4 /* Extended Capability lists*/ -#define PCIE_EXT_CAP_OFFSET 0x100 -#define PCIE_EXT_CAP_AER_ID 0x0001 -#define PCIE_EXT_CAP_L1SS_ID 0x001E -#define PCIE_EXT_CAP_LTR_ID 0x0018 +#define PCIE_EXT_CAP_OFFSET 0x100 +#define PCIE_EXT_CAP_AER_ID 0x0001 +#define PCIE_EXT_CAP_L1SS_ID 0x001E +#define PCIE_EXT_CAP_LTR_ID 0x0018 +#define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015 /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ @@ -526,6 +528,16 @@ #define PCI_LTR_MAX_SNOOP 4 #define PCI_LTR_MAX_NOSNOOP 6 +/* PCIe Resizable BARs */ +#define PCI_REBAR_CAP_OFFSET 0x4 +#define PCI_REBAR_CAP_SIZE_MASK 0xfffffff0 +#define PCI_REBAR_CTRL_OFFSET 0x8 +#define PCI_REBAR_CTRL_NBARS_MASK 0xe0 +#define PCI_REBAR_CTRL_NBARS_SHIFT 5 +#define PCI_REBAR_CTRL_IDX_MASK 0x07 +#define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000 +#define PCI_REBAR_CTRL_SIZE_SHIFT 16 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0e4da41921..042e10efef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -374,10 +374,12 @@ #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C +#define PCI_DEVICE_ID_ATI_FAM17H_MODELA0H_GPU 0x1506 #define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE 0x1638 #define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_BARCELO 0x15e7 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE #define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_HDA0 0x1637 +#define PCI_DEVICE_ID_ATI_FAM17H_MODELA0H_HDA0 0x1640 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 @@ -503,12 +505,14 @@ #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 #define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 +#define PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB 0x14B5 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 #define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 +#define PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB_IOMMU 0x14B6 #define PCI_DEVICE_ID_AMD_SB900_LPC 0x780E #define PCI_DEVICE_ID_AMD_SB900_SATA 0x7800 @@ -582,15 +586,19 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP 0x14BA #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC 0x14B9 #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI0 0x1503 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_XHCI1 0x1504 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA @@ -607,6 +615,14 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF0 0x1724 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF1 0x1725 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF2 0x1726 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF3 0x1727 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF4 0x1728 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF5 0x1729 +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF6 0x172A +#define PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF7 0x172B #define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A #define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B #define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C @@ -620,8 +636,6 @@ #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1 0x7917 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 -#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 #define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 @@ -1283,8 +1297,10 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_DEVICE_ID_REALTEK_5261 0x5261 #define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8125 0x8125 #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 #define PCI_VENDOR_ID_TYAN 0x10f1 #define PCI_VENDOR_ID_XILINX 0x10ee @@ -2066,8 +2082,9 @@ #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea #define PCI_VENDOR_ID_GLI 0x17a0 -#define PCI_DEVICE_ID_GLI_9763E 0xe763 +#define PCI_DEVICE_ID_GLI_9750 0x9750 #define PCI_DEVICE_ID_GLI_9755 0x9755 +#define PCI_DEVICE_ID_GLI_9763E 0xe763 #define PCI_VENDOR_ID_XGI 0x18ca #define PCI_DEVICE_ID_XGI_20 0x0020 @@ -2738,38 +2755,38 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 /* Intel Denverton (Atom C3000 family) */ -#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980 -#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9 -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa -#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab -#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac -#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2 -#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2 -#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0 -#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1 -#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2 -#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3 -#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4 -#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5 -#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6 -#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8 -#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5 -#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6 -#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8 -#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9 -#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db -#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc -#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd -#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de -#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df -#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0 -#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1 +#define PCI_DEVICE_ID_INTEL_DNV_SA 0x1980 +#define PCI_DEVICE_ID_INTEL_DNVAD_SA 0x1995 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP0 0x19a4 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP1 0x19a5 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP2 0x19a6 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP3 0x19a7 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP4 0x19a8 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP5 0x19a9 +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP6 0x19aa +#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP7 0x19ab +#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19ac +#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_1 0x19b2 +#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_2 0x19c2 +#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 +#define PCI_DEVICE_ID_INTEL_DNV_LAN_1 0x19d1 +#define PCI_DEVICE_ID_INTEL_DNV_LAN_2 0x19d2 +#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_1 0x19d3 +#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_2 0x19d4 +#define PCI_DEVICE_ID_INTEL_DNV_ME_KT 0x19d5 +#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_3 0x19d6 +#define PCI_DEVICE_ID_INTEL_DNV_HSUART 0x19d8 +#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_1 0x19e5 +#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_2 0x19e6 +#define PCI_DEVICE_ID_INTEL_DNV_IE_KT 0x19e8 +#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_3 0x19e9 +#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db +#define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc +#define PCI_DEVICE_ID_INTEL_DNV_P2SB 0x19dd +#define PCI_DEVICE_ID_INTEL_DNV_PMC 0x19de +#define PCI_DEVICE_ID_INTEL_DNV_SMBUS_LEGACY 0x19df +#define PCI_DEVICE_ID_INTEL_DNV_SPI 0x19e0 +#define PCI_DEVICE_ID_INTEL_DNV_TRACEHUB 0x19e1 /* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */ #define PCI_DID_INTEL_IBEXPEAK_LPC_P55 0x3b02 @@ -3022,38 +3039,38 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_29 0x7a9d #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_30 0x7a9e #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_0 0x5480 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_1 0x5481 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_2 0x5482 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_3 0x5483 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_4 0x5484 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_5 0x5485 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_6 0x5486 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_7 0x5487 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_8 0x5488 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_9 0x5489 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_10 0x548a -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_11 0x548b -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_12 0x548c -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_13 0x548d -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_14 0x548e -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_15 0x548f -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_16 0x5490 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_17 0x5491 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_18 0x5482 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_19 0x5493 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_20 0x5494 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_21 0x5495 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_22 0x5496 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_23 0x5497 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_24 0x5498 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_25 0x5499 -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_26 0x549a -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_27 0x549b -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_28 0x548c -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e -#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_0 0x5480 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_1 0x5481 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_2 0x5482 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_3 0x5483 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_4 0x5484 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_5 0x5485 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_6 0x5486 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_7 0x5487 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_8 0x5488 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_9 0x5489 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_10 0x548a +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_11 0x548b +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_12 0x548c +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_13 0x548d +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_14 0x548e +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_15 0x548f +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_16 0x5490 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_17 0x5491 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_18 0x5492 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_19 0x5493 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_20 0x5494 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_21 0x5495 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_22 0x5496 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_23 0x5497 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_24 0x5498 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_25 0x5499 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_26 0x549a +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_27 0x549b +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_28 0x548c +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_29 0x549d +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_30 0x549e +#define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_31 0x549f #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 @@ -3334,6 +3351,10 @@ #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6 0x4b3d #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7 0x4b3e +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1 0x464d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2 0x460d +#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3 0x463d + #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1 0x51b8 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2 0x51b9 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3 0x51ba @@ -3376,16 +3397,18 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP27 0x7aca #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP1 0x54b8 -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP2 0x54b9 -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP3 0x54ba -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP4 0x54bb +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP1 0x54b8 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP2 0x54b9 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP3 0x54ba +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP4 0x54bb #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP5 0x54bc #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP6 0x54bd -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP7 0x54be +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP7 0x54be #define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP8 0x54bf -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP9 0x54b0 -#define PCI_DEVICE_ID_INTEL_ADP_M_PCIE_RP10 0x54b1 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP9 0x54b0 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PCIE_RP10 0x54b1 +#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP11 0x54b2 +#define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP12 0x54b3 /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 @@ -3478,7 +3501,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1 #define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 -#define PCI_DEVICE_ID_INTEL_ADP_M_PMC 0x54a1 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_PMC 0x54a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3582,12 +3605,12 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_I2C4 0x7afc #define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C0 0x54e8 -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C1 0x54e9 -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C2 0x54ea -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C3 0x54eb -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C4 0x54c5 -#define PCI_DEVICE_ID_INTEL_ADP_M_I2C5 0x54c6 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C0 0x54e8 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C1 0x54e9 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C2 0x54ea +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C3 0x54eb +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C4 0x54c5 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C5 0x54c6 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 @@ -3654,10 +3677,10 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_UART5 0x7ade #define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf -#define PCI_DEVICE_ID_INTEL_ADP_M_UART0 0x54a8 -#define PCI_DEVICE_ID_INTEL_ADP_M_UART1 0x54a9 -#define PCI_DEVICE_ID_INTEL_ADP_M_UART2 0x54c7 -#define PCI_DEVICE_ID_INTEL_ADP_M_UART3 0x54da +#define PCI_DEVICE_ID_INTEL_ADP_M_N_UART0 0x54a8 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_UART1 0x54a9 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_UART2 0x54c7 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_UART3 0x54da /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 @@ -3734,9 +3757,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_SPI5 0x7aee #define PCI_DEVICE_ID_INTEL_ADP_S_SPI6 0x7aef -#define PCI_DEVICE_ID_INTEL_ADP_M_HWSEQ_SPI 0x54a4 -#define PCI_DEVICE_ID_INTEL_ADP_M_SPI0 0x54aa -#define PCI_DEVICE_ID_INTEL_ADP_M_SPI1 0x54ab +#define PCI_DEVICE_ID_INTEL_ADP_M_N_HWSEQ_SPI 0x54a4 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_SPI0 0x54aa +#define PCI_DEVICE_ID_INTEL_ADP_M_N_SPI1 0x54ab #define PCI_DEVICE_ID_INTEL_ADP_M_SPI2 0x54fb #define PCI_DEVICE_ID_INTEL_SPR_HWSEQ_SPI 0x1bca @@ -3879,10 +3902,17 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4 0x46a8 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5 0x46b3 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_7 0x4628 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_8 0x46b1 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_9 0x4626 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa #define PCI_DEVICE_ID_INTEL_ADL_M_GT3 0x46c3 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT1 0x46D0 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT2 0x46D1 +#define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2 + /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3961,6 +3991,8 @@ #define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x4532 #define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518 #define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A +#define PCI_DEVICE_ID_INTEL_EHL_ID_14 0x4536 +#define PCI_DEVICE_ID_INTEL_EHL_ID_15 0x451C #define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22 #define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26 #define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12 @@ -3990,8 +4022,14 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_7 0x4601 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f +#define PCI_DEVICE_ID_INTEL_ADL_P_ID_10 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_1 0x4602 #define PCI_DEVICE_ID_INTEL_ADL_M_ID_2 0x460a +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_1 0x4617 +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_3 0x461c +#define PCI_DEVICE_ID_INTEL_ADL_N_ID_4 0x4614 + /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 #define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 @@ -4012,7 +4050,7 @@ #define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3 #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 -#define PCI_DEVICE_ID_INTEL_ADP_M_SMBUS 0x54a3 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_SMBUS 0x54a3 /* Intel EHCI device IDs */ #define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4074,13 +4112,9 @@ #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef #define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef -#define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef #define PCI_DEVICE_ID_INTEL_TGL_H_SRAM 0x43ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def -#define PCI_DEVICE_ID_INTEL_ADP_P_SRAM 0x7a6f -#define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 -#define PCI_DEVICE_ID_INTEL_ADP_M_SRAM 0x54ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4112,13 +4146,13 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_AUDIO_8 0x7ad7 #define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_1 0x54c8 -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_2 0x54c9 -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_3 0x54ca -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_4 0x54cb -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_5 0x54cc -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_6 0x54cd -#define PCI_DEVICE_ID_INTEL_ADP_M_AUDIO_7 0x54ce +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_1 0x54c8 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_2 0x54c9 +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_3 0x54ca +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_4 0x54cb +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_5 0x54cc +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_6 0x54cd +#define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_7 0x54ce /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a @@ -4196,6 +4230,10 @@ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b #define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4 #define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4 +#define PCI_DEVICE_ID_INTEL_ADP_EMMC 0x54c4 + +/* Intel UFS device Ids */ +#define PCI_DEVICE_ID_INTEL_ADP_UFS 0x54ff /* Intel Thunderbolt device Ids */ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP0 0x9a23 @@ -4253,6 +4291,7 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_IPU 0x9a39 #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 #define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d +#define PCI_DEVICE_ID_INTEL_ADL_N_IPU 0x462e /* Intel Dynamic Tuning Technology Device */ #define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 @@ -4286,6 +4325,18 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_0 0x43f5 #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_1 0x43f6 #define PCI_DEVICE_ID_INTEL_TGL_H_CNVI_BT_2 0x43f7 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_0 0x54f0 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2 +#define PCI_DEVICE_ID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3 + +/* Intel Crashlog */ +#define PCI_DEVICE_ID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d +#define PCI_DEVICE_ID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d +#define PCI_DEVICE_ID_INTEL_ADP_S_PMC_CRASHLOG_SRAM 0x7aa7 +#define PCI_DEVICE_ID_INTEL_ADP_P_PMC_CRASHLOG_SRAM 0x51ef +#define PCI_DEVICE_ID_INTEL_ADP_N_PMC_CRASHLOG_SRAM 0x54ef +#define PCI_DEVICE_ID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 8798405776..89c99062d2 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -7,10 +7,6 @@ #include #include -/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we - * prevent some sub-optimal constant folding. */ -extern u8 *const pci_mmconf; - /* Using a unique datatype for MMIO writes makes the pointers to _not_ * qualify for pointer aliasing with any other objects in memory. * @@ -29,46 +25,74 @@ union pci_bank { uint32_t reg32[4096 / sizeof(uint32_t)]; }; +#if CONFIG(ECAM_MMCONF_SUPPORT) + +#if CONFIG_ECAM_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!" +#endif + +#if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH +#error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!" +#endif + +/* By not assigning this to CONFIG_ECAM_MMCONF_BASE_ADDRESS here we + prevent some sub-optimal constant folding. */ +extern u8 *const pci_mmconf; + static __always_inline -volatile union pci_bank *pcicfg(pci_devfn_t dev) +volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; } +#else + +/* For platforms not supporting ECAM, they need to define pci_map_bus function + * in their platform-specific code */ +volatile union pci_bank *pci_map_bus(pci_devfn_t dev); + +#endif + +/* + * Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ + static __always_inline -uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) +uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg8[reg]; + return pci_map_bus(dev)->reg8[reg]; } static __always_inline -uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) +uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline -uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) +uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) { - return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline -void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) +void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { - pcicfg(dev)->reg8[reg] = value; + pci_map_bus(dev)->reg8[reg] = value; } static __always_inline -void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) +void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { - pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; + pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline -void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) +void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { - pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; + pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)] = value; } /* @@ -80,72 +104,19 @@ void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) static __always_inline uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg) { - return (uint8_t *)&pcicfg(dev)->reg8[reg]; + return (uint8_t *)&pci_map_bus(dev)->reg8[reg]; } static __always_inline uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg) { - return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; + return (uint16_t *)&pci_map_bus(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg) { - return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; + return (uint32_t *)&pci_map_bus(dev)->reg32[reg / sizeof(uint32_t)]; } -#if CONFIG(MMCONF_SUPPORT) - -#if CONFIG_MMCONF_BASE_ADDRESS == 0 -#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" -#endif - -#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH -#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!" -#endif - -/* Avoid name collisions as different stages have different signature - * for these functions. The _s_ stands for simple, fundamental IO or - * MMIO variant. - */ - -static __always_inline -uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config8(dev, reg); -} - -static __always_inline -uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config16(dev, reg); -} - -static __always_inline -uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg) -{ - return pci_mmio_read_config32(dev, reg); -} - -static __always_inline -void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) -{ - pci_mmio_write_config8(dev, reg, value); -} - -static __always_inline -void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) -{ - pci_mmio_write_config16(dev, reg, value); -} - -static __always_inline -void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) -{ - pci_mmio_write_config32(dev, reg, value); -} - -#endif - #endif /* _PCI_MMIO_CFG_H */ diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 8b04d09987..25bca4003a 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -35,6 +35,7 @@ struct pci_data { uint16_t reserved_2; }; +void vga_oprom_preload(void); struct rom_header *pci_rom_probe(const struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 014fcb18b1..30c2a54620 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -30,5 +30,17 @@ void pciexp_hotplug_scan_bridge(struct device *dev); extern struct device_operations default_pciexp_hotplug_ops_bus; -unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); +unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap); +unsigned int pciexp_find_next_extended_cap(const struct device *dev, unsigned int cap, + unsigned int offset); + +static inline bool pciexp_is_downstream_port(int type) +{ + return type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM || + type == PCI_EXP_TYPE_PCIE_BRIDGE; +} + +bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop); + #endif /* DEVICE_PCIEXP_H */ diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 098d0b653a..fb1f691190 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -36,8 +36,9 @@ #define IORESOURCE_FIXED 0x80000000 /* PCI specific resource bits (IORESOURCE_BITS) */ -#define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */ -#define IORESOURCE_PCI_BRIDGE (1<<1) /* A bridge pci resource */ +#define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */ +#define IORESOURCE_PCI_BRIDGE (1<<1) /* A bridge pci resource */ +#define IORESOURCE_PCIE_RESIZABLE_BAR (1<<2) /* A Resizable BAR */ typedef u64 resource_t; struct resource { diff --git a/src/include/device/usbc_mux.h b/src/include/device/usbc_mux.h index e395d2dd62..0648a74f66 100644 --- a/src/include/device/usbc_mux.h +++ b/src/include/device/usbc_mux.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __USBC_MUX_H__ +#define __USBC_MUX_H__ + /* struct to hold all USB-C mux related variables */ struct usbc_mux_info { bool dp; /* DP connected */ @@ -67,3 +70,5 @@ struct usbc_ops { }; const struct usbc_ops *usbc_get_ops(void); + +#endif /* __USBC_MUX_H__ */ diff --git a/src/include/dimm_info_util.h b/src/include/dimm_info_util.h index d20e8cddfc..e7285d5c93 100644 --- a/src/include/dimm_info_util.h +++ b/src/include/dimm_info_util.h @@ -12,7 +12,7 @@ * Use this when setting dimm_info.bus_width if the raw SPD values are not * available. */ -uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, +uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width, uint16_t data_width); /** @@ -28,7 +28,7 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size, * * Use this when setting dimm_info.mod_type. */ -uint8_t -smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor); +uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type, + smbios_memory_form_factor form_factor); #endif diff --git a/src/include/dp_aux.h b/src/include/dp_aux.h new file mode 100644 index 0000000000..ce93383a63 --- /dev/null +++ b/src/include/dp_aux.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DP_AUX_H_ +#define _DP_AUX_H_ + +#include + +enum { + EDID_LENGTH = 128, + EDID_I2C_ADDR = 0x50, + EDID_EXTENSION_FLAG = 0x7e, +}; + +enum i2c_over_aux { + I2C_OVER_AUX_WRITE_MOT_0 = 0x0, + I2C_OVER_AUX_READ_MOT_0 = 0x1, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2, + I2C_OVER_AUX_WRITE_MOT_1 = 0x4, + I2C_OVER_AUX_READ_MOT_1 = 0x5, + I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6, + NATIVE_AUX_WRITE = 0x8, + NATIVE_AUX_READ = 0x9, +}; + +enum aux_request { + DPCD_READ, + DPCD_WRITE, + I2C_RAW_READ, + I2C_RAW_WRITE, + I2C_RAW_READ_AND_STOP, + I2C_RAW_WRITE_AND_STOP, +}; + +/* Backlight configuration */ +#define DP_BACKLIGHT_MODE_SET 0x721 +#define DP_BACKLIGHT_CONTROL_MODE_MASK 0x3 +#define DP_BACKLIGHT_CONTROL_MODE_DPCD 0x2 +#define DP_DISPLAY_CONTROL_REGISTER 0x720 +#define DP_BACKLIGHT_ENABLE 0x1 +#define DP_BACKLIGHT_BRIGHTNESS_MSB 0x722 + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + + +bool dp_aux_request_is_write(enum aux_request request); +enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this); + +#endif diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 8766183d7a..be96e3fd3a 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -5,6 +5,7 @@ #define __EFI_DATATYPE_H__ #include #include +#include /* Basic Data types */ /* 8-byte unsigned value. */ @@ -38,6 +39,8 @@ typedef EFI_STATUS efi_return_status_t; /* Data structure */ /* Data structure for EFI_PEI_SERVICE. */ typedef EFI_PEI_SERVICES efi_pei_services; +/* Data structure for EFI_PHYSICAL_ADDRESS */ +typedef EFI_PHYSICAL_ADDRESS efi_physical_address; /* Structure that describes information about a logical CPU. */ typedef EFI_PROCESSOR_INFORMATION efi_processor_information; diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 07ddd31ce8..83445ecea0 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -4,7 +4,6 @@ #define __FRAMEBUFFER_INFO_H_ #include -#include #include struct fb_info; diff --git a/src/include/lib.h b/src/include/lib.h index 8e8bab55c1..863888e16b 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -53,13 +53,16 @@ static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +/* Find Last Set: __fls(1) == 0, __fls(5) == 2, __fls(1 << 31) == 31 */ +static inline int __fls(u32 x) { return log2(x); } -/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ -static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2_ceil(5) == 3 */ +static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x - 1) + 1; } static inline int popcnt64(u64 x) { return __builtin_popcountll(x); } static inline int clz64(u64 x) { return x ? __builtin_clzll(x) : sizeof(x) * 8; } static inline int log2_64(u64 x) { return sizeof(x) * 8 - clz64(x) - 1; } static inline int __ffs64(u64 x) { return log2_64(x & (u64)(-(s64)x)); } +static inline int __fls64(u64 x) { return log2_64(x); } #endif /* __LIB_H__ */ diff --git a/src/include/list.h b/src/include/list.h index 6f0b54d818..bfd92a747b 100644 --- a/src/include/list.h +++ b/src/include/list.h @@ -15,6 +15,8 @@ void list_remove(struct list_node *node); void list_insert_after(struct list_node *node, struct list_node *after); // Insert list_node node before list_node before in a doubly linked list. void list_insert_before(struct list_node *node, struct list_node *before); +// Appends the node to the end of the list. +void list_append(struct list_node *node, struct list_node *head); #define list_for_each(ptr, head, member) \ for ((ptr) = container_of((head).next, typeof(*(ptr)), member); \ diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 2f1399388f..9d02aef558 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -5,7 +5,6 @@ #define _MEMORY_INFO_H_ #include -#include #define DIMM_INFO_SERIAL_SIZE 4 #define DIMM_INFO_PART_NUMBER_SIZE 33 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 5b9a94df06..ba42465046 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -145,6 +145,13 @@ int legacy_romstage_select_and_load(struct prog *romstage); * RAMSTAGE LOADING * ************************/ +/* + * Asynchronously preloads ramstage. + * + * This should be called early on to allow ramstage to load before + * `run_ramstage` is called. + */ +void preload_ramstage(void); /* Run ramstage from romstage. */ void run_ramstage(void); diff --git a/src/include/rules.h b/src/include/rules.h index ec3d22d7d1..02b55c5f8a 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -292,6 +292,24 @@ #define ENV_INITIAL_STAGE ENV_BOOTBLOCK #endif +#if ENV_X86 +#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE +#elif ENV_RISCV +#define STAGE_HAS_SPINLOCKS 1 +#else +#define STAGE_HAS_SPINLOCKS 0 +#endif + +/* When set is included for the spinlock implementation. */ +#define ENV_STAGE_SUPPORTS_SMP (CONFIG(SMP) && STAGE_HAS_SPINLOCKS) + +#if ENV_X86 && CONFIG(COOP_MULTITASKING) && (ENV_RAMSTAGE || ENV_ROMSTAGE) +/* TODO: Enable in all x86 stages */ +#define ENV_STAGE_SUPPORTS_COOP 1 +#else +#define ENV_STAGE_SUPPORTS_COOP 0 +#endif + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index 8554aa0589..116830cd74 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef SMP_SPINLOCK_H #define SMP_SPINLOCK_H -#if CONFIG(SMP) +#if ENV_STAGE_SUPPORTS_SMP #include #else /* !CONFIG_SMP */ diff --git a/src/include/spd.h b/src/include/spd.h index ec5296ec2f..8493d40b6e 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -197,17 +197,70 @@ enum spd_memory_type { #define MODULE_BUFFERED 1 #define MODULE_REGISTERED 2 -/* Byte 3: Module type information */ #define SPD_UNDEFINED 0x00 -#define SPD_RDIMM 0x01 -#define SPD_UDIMM 0x02 -#define SPD_SODIMM 0x04 -#define SPD_72B_SO_CDIMM 0x06 -#define SPD_72B_SO_RDIMM 0x07 -#define SPD_MICRO_DIMM 0x08 -#define SPD_MINI_RDIMM 0x10 -#define SPD_MINI_UDIMM 0x20 - #define SPD_ECC_8BIT (1<<3) +#define SPD_ECC_8BIT_LP5_DDR5 (1<<4) + +/* Byte 3: Module type information */ +enum ddr2_module_type { + DDR2_SPD_RDIMM = 0x01, + DDR2_SPD_UDIMM = 0x02, + DDR2_SPD_SODIMM = 0x04, + DDR2_SPD_72B_SO_CDIMM = 0x06, + DDR2_SPD_72B_SO_RDIMM = 0x07, + DDR2_SPD_MICRO_DIMM = 0x08, + DDR2_SPD_MINI_RDIMM = 0x10, + DDR2_SPD_MINI_UDIMM = 0x20, +}; + +enum ddr3_module_type { + DDR3_SPD_RDIMM = 0x01, + DDR3_SPD_UDIMM = 0x02, + DDR3_SPD_SODIMM = 0x03, + DDR3_SPD_MICRO_DIMM = 0x04, + DDR3_SPD_MINI_RDIMM = 0x05, + DDR3_SPD_MINI_UDIMM = 0x06, + DDR3_SPD_MINI_CDIMM = 0x07, + DDR3_SPD_72B_SO_UDIMM = 0x08, + DDR3_SPD_72B_SO_RDIMM = 0x09, + DDR3_SPD_72B_SO_CDIMM = 0x0a, + DDR3_SPD_LRDIMM = 0x0b, + DDR3_SPD_16B_SO_DIMM = 0x0c, + DDR3_SPD_32B_SO_RDIMM = 0x0d, +}; + +enum ddr4_module_type { + DDR4_SPD_RDIMM = 0x01, + DDR4_SPD_UDIMM = 0x02, + DDR4_SPD_SODIMM = 0x03, + DDR4_SPD_LRDIMM = 0x04, + DDR4_SPD_MINI_RDIMM = 0x05, + DDR4_SPD_MINI_UDIMM = 0x06, + DDR4_SPD_72B_SO_UDIMM = 0x08, + DDR4_SPD_72B_SO_RDIMM = 0x09, + DDR4_SPD_16B_SO_DIMM = 0x0c, + DDR4_SPD_32B_SO_RDIMM = 0x0d, +}; + +enum ddr5_module_type { + DDR5_SPD_RDIMM = 0x01, + DDR5_SPD_UDIMM = 0x02, + DDR5_SPD_SODIMM = 0x03, + DDR5_SPD_LRDIMM = 0x04, + DDR5_SPD_MINI_RDIMM = 0x05, + DDR5_SPD_MINI_UDIMM = 0x06, + DDR5_SPD_72B_SO_UDIMM = 0x08, + DDR5_SPD_72B_SO_RDIMM = 0x09, + DDR5_SPD_SOLDERED_DOWN = 0x0b, + DDR5_SPD_16B_SO_DIMM = 0x0c, + DDR5_SPD_32B_SO_RDIMM = 0x0d, + DDR5_SPD_1DPC = 0x0e, + DDR5_SPD_2DPC = 0x0f, +}; + +enum lpx_module_type { + LPX_SPD_LPDIMM = 0x07, + LPX_SPD_NONDIMM = 0x0e, +}; #endif diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 77a3c09a79..acb22ec1d2 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -111,7 +111,8 @@ enum ctrlr_prot_type { enum { /* Deduct the command length from the spi_crop_chunk() calculation for - sizing a transaction. */ + sizing a transaction. If SPI_CNTRLR_DEDUCT_OPCODE_LEN is set, only + the bytes after the command byte will be deducted. */ SPI_CNTRLR_DEDUCT_CMD_LEN = 1 << 0, /* Remove the opcode size from the command length used in the spi_crop_chunk() calculation. Controllers which have a dedicated diff --git a/src/include/symbols.h b/src/include/symbols.h index 52624d4e4c..3e4694b90d 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -52,7 +52,6 @@ DECLARE_REGION(asan_shadow) /* Regions for execution units. */ -DECLARE_REGION(payload_preload_cache) DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ DECLARE_REGION(program) diff --git a/src/include/thread.h b/src/include/thread.h index 62c6283acf..f414db0281 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -4,8 +4,7 @@ #include #include -#include -#include +#include struct thread_mutex { bool locked; @@ -38,7 +37,7 @@ int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), /* Waits until the thread has terminated and returns the error code */ enum cb_err thread_join(struct thread_handle *handle); -#if (ENV_RAMSTAGE || ENV_ROMSTAGE) && CONFIG(COOP_MULTITASKING) +#if ENV_STAGE_SUPPORTS_COOP struct thread { int id; diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 647cd13897..cbe9934069 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -19,7 +19,7 @@ void timestamp_init(uint64_t base); * inside REGION(timestamp) before cbmem comes online. For later stages, timestamps * added before cbmem_[recovery|initialize] calls will be lost. */ -void timestamp_add(enum timestamp_id id, uint64_t ts_time); +void timestamp_add(enum timestamp_id id, int64_t ts_time); /* Calls timestamp_add with current timestamp. */ void timestamp_add_now(enum timestamp_id id); diff --git a/src/include/types.h b/src/include/types.h index cbdb67a0ca..8724d4b01f 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -5,6 +5,7 @@ /* types.h is supposed to provide the standard headers defined in here: */ #include +#include #include #include #include diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 0f651b346a..014230012d 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -70,7 +70,7 @@ config HWBASE_DYNAMIC_MMIO config HWBASE_DEFAULT_MMCONF hex - default MMCONF_BASE_ADDRESS + default ECAM_MMCONF_BASE_ADDRESS config HWBASE_DIRECT_PCIDEV def_bool y @@ -99,13 +99,18 @@ config NO_CBFS_MCACHE lookup must re-read the same CBFS directory entries from flash to find the respective file. -config PAYLOAD_PRELOAD +config CBFS_CACHE_ALIGN + int + default 8 + help + Sets the alignment of the buffers returned by the cbfs_cache. + +config CBFS_PRELOAD bool depends on COOP_MULTITASKING help - On some systems with SPI DMA controllers, it is possible to preload - the payload while ramstage is executing. This can be selected by the - SoC to enable payload preloading. - - The SoC needs to define a payload_preload_cache region where the - raw payload can be placed. + When enabled it will be possible to preload CBFS files into the + cbfs_cache. This helps reduce boot time by loading the files + in the background before they are actually required. This feature + depends on the read-only boot_device having a DMA controller to + perform the background transfer. diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification index fa90d9d9af..9a9ba3189d 100644 --- a/src/lib/Kconfig.cbfs_verification +++ b/src/lib/Kconfig.cbfs_verification @@ -2,33 +2,41 @@ # # This file is sourced from src/security/Kconfig for menuconfig convenience. -#menu "CBFS verification" # TODO: enable once it works +menu "CBFS verification" config CBFS_VERIFICATION - bool # TODO: make user selectable once it works + bool "Enable CBFS verification" depends on !VBOOT_STARTS_BEFORE_BOOTBLOCK # this is gonna get tricky... select VBOOT_LIB help - Work in progress. Do not use (yet). + Say yes here to enable code that cryptographically verifies each CBFS + file as it gets loaded by chaining it to a trust anchor that is + embedded in the bootblock. This only makes sense if you use some + out-of-band mechanism to guarantee the integrity of the bootblock + itself, such as Intel Boot Guard or flash write-protection. + + If a CBFS image was created with this option enabled, cbfstool will + automatically update the hash embedded in the bootblock whenever it + modifies the CBFS. + +if CBFS_VERIFICATION config TOCTOU_SAFETY - bool - depends on CBFS_VERIFICATION + bool "Protect against time-of-check vs. time-of-use vulnerabilities" depends on !NO_FMAP_CACHE depends on !NO_CBFS_MCACHE depends on !USE_OPTION_TABLE && !FSP_CAR # Known to access CBFS before CBMEM init + depends on !VBOOT # TODO: can only allow this once vboot fully integrated + depends on NO_XIP_EARLY_STAGES help - Work in progress. Not actually TOCTOU safe yet. Do not use. + Say yes here to eliminate time-of-check vs. time-of-use vulnerabilities + for CBFS verification. This means that data from flash must be verified + every time it is loaded (not just the first time), which requires a bit + more overhead and is incompatible with certain configurations. - Design idea here is that mcache overflows in this mode are only legal - for the RW CBFS, because it's relatively easy to retrieve the RW - metadata hash from persistent vboot context at any time, but the RO - metadata hash is lost after the bootblock is unloaded. This avoids the - need to carry yet another piece forward through the stages. Mcache - overflows are mostly a concern for RW updates (if an update adds more - files than originally planned for), for the RO section it should - always be possible to dimension the mcache correctly beforehand, so - this should be an acceptable limitation. + Using this option only makes sense when the mechanism securing the + bootblock is also safe against these vulnerabilities (i.e. there's no + point in enabling this when you just rely on flash write-protection). config CBFS_HASH_ALGO int @@ -37,9 +45,13 @@ config CBFS_HASH_ALGO default 3 if CBFS_HASH_SHA512 choice - prompt "--> hash type" - depends on CBFS_VERIFICATION + prompt "Hash algorithm" default CBFS_HASH_SHA256 + help + Select the hash algorithm used in CBFS verification. Note that SHA-1 is + generally considered insecure today and should not be used without good + reason. When using CBFS verification together with measured boot, using + the same hash algorithm (usually SHA-256) for both is more efficient. config CBFS_HASH_SHA1 bool "SHA-1" @@ -52,4 +64,6 @@ config CBFS_HASH_SHA512 endchoice -#endmenu +endif + +endmenu diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 693a526b66..8d235a98d8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -28,6 +28,8 @@ CFLAGS_ramstage += $(CFLAGS_asan) $(obj)/ramstage/lib/asan.o: CFLAGS_asan = endif +all-y += list.c + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -59,7 +61,6 @@ bootblock-y += memchr.c bootblock-y += memcmp.c bootblock-y += boot_device.c bootblock-y += fmap.c -bootblcok-y += rtc.c verstage-y += prog_loaders.c verstage-y += prog_ops.c @@ -147,6 +148,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c +ramstage-y += dp_aux.c ramstage-y += edid.c ramstage-y += edid_fill_fb.c ramstage-y += memrange.c @@ -154,7 +156,6 @@ ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c -ramstage-y += list.c ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index 1fe23c2828..e9d4287d21 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -51,7 +51,7 @@ static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag) case BM_MEM_TABLE: return LB_MEM_TABLE; default: - printk(BIOS_ERR, "ERROR: Unsupported tag %u\n", tag); + printk(BIOS_ERR, "Unsupported tag %u\n", tag); return LB_MEM_RESERVED; } } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 322f161a0e..2d98c44a79 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,37 +3,39 @@ #include #include #include -#include #include +#include #include -#include #include #include #include +#include #include #include #include #include #include #include +#include #include #if ENV_STAGE_HAS_DATA_SECTION -struct mem_pool cbfs_cache = MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache)); +struct mem_pool cbfs_cache = + MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); #else -struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0); +struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); #endif static void switch_to_postram_cache(int unused) { if (_preram_cbfs_cache != _postram_cbfs_cache) - mem_pool_init(&cbfs_cache, _postram_cbfs_cache, - REGION_SIZE(postram_cbfs_cache)); + mem_pool_init(&cbfs_cache, _postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), + CONFIG_CBFS_CACHE_ALIGN); } ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache); -cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, - union cbfs_mdata *mdata, struct region_device *rdev) +cb_err_t _cbfs_boot_lookup(const char *name, bool force_ro, + union cbfs_mdata *mdata, struct region_device *rdev) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); if (!cbd) @@ -55,14 +57,14 @@ cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, RO CBFS would have been caught when building the mcache in cbfs_get boot_device(). (Note that TOCTOU_SAFETY implies !NO_CBFS_MCACHE.) */ assert(cbd == vboot_get_cbfs_boot_device()); - /* TODO: set metadata_hash to RW metadata hash here. */ + die("TODO: set metadata_hash to RW metadata hash here.\n"); } err = cbfs_lookup(&cbd->rdev, name, mdata, &data_offset, metadata_hash); } if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && err == CB_CBFS_NOT_FOUND) { printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", name); - return cbfs_boot_lookup(name, true, mdata, rdev); + return _cbfs_boot_lookup(name, true, mdata, rdev); } if (err) { if (err == CB_CBFS_NOT_FOUND) @@ -78,32 +80,9 @@ cb_err_t cbfs_boot_lookup(const char *name, bool force_ro, if (rdev_chain(rdev, &cbd->rdev, data_offset, be32toh(mdata->h.len))) return CB_ERR; - if (tspi_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) { - printk(BIOS_ERR, "CBFS ERROR: error when measuring '%s'\n", name); - } - return CB_SUCCESS; } -int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) -{ - if (cbfs_boot_lookup(name, false, &fh->mdata, &fh->data)) - return -1; - - size_t msize = be32toh(fh->mdata.h.offset); - if (rdev_chain_mem(&fh->metadata, &fh->mdata, msize)) - return -1; - - if (type) { - if (!*type) - *type = be32toh(fh->mdata.h.type); - else if (*type != be32toh(fh->mdata.h.type)) - return -1; - } - - return 0; -} - void cbfs_unmap(void *mapping) { /* @@ -116,27 +95,6 @@ void cbfs_unmap(void *mapping) mem_pool_free(&cbfs_cache, mapping); } -int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, - const char *name, uint32_t *type) -{ - struct region_device rdev; - int ret = 0; - if (fmap_locate_area_as_rdev(region_name, &rdev)) { - LOG("%s region not found while looking for %s\n", region_name, name); - return -1; - } - - uint32_t dummy_type = 0; - if (!type) - type = &dummy_type; - - ret = cbfs_locate(fh, &rdev, name, type); - if (!ret) - if (tspi_measure_cbfs_hook(&rdev, name, *type)) - LOG("error measuring %s in region %s\n", name, region_name); - return ret; -} - static inline bool fsps_env(void) { /* FSP-S is assumed to be loaded in ramstage. */ @@ -187,30 +145,54 @@ static inline bool cbfs_lzma_enabled(void) return true; } -static inline bool cbfs_file_hash_mismatch(const void *buffer, size_t size, - const struct vb2_hash *file_hash) +static bool cbfs_file_hash_mismatch(const void *buffer, size_t size, + const union cbfs_mdata *mdata, bool skip_verification) { - /* Avoid linking hash functions when verification is disabled. */ - if (!CONFIG(CBFS_VERIFICATION)) + /* Avoid linking hash functions when verification and measurement are disabled. */ + if (!CONFIG(CBFS_VERIFICATION) && !CONFIG(TPM_MEASURED_BOOT)) return false; - /* If there is no file hash, always count that as a mismatch. */ - if (file_hash && vb2_hash_verify(buffer, size, file_hash) == VB2_SUCCESS) - return false; + const struct vb2_hash *hash = NULL; - printk(BIOS_CRIT, "CBFS file hash mismatch!\n"); - return true; + if (CONFIG(CBFS_VERIFICATION) && !skip_verification) { + hash = cbfs_file_hash(mdata); + if (!hash) { + ERROR("'%s' does not have a file hash!\n", mdata->h.filename); + return true; + } + if (vb2_hash_verify(buffer, size, hash) != VB2_SUCCESS) { + ERROR("'%s' file hash mismatch!\n", mdata->h.filename); + return true; + } + } + + if (CONFIG(TPM_MEASURED_BOOT) && !ENV_SMM) { + struct vb2_hash calculated_hash; + + /* No need to re-hash file if we already have it from verification. */ + if (!hash || hash->algo != TPM_MEASURE_ALGO) { + vb2_hash_calculate(buffer, size, TPM_MEASURE_ALGO, &calculated_hash); + hash = &calculated_hash; + } + + if (tspi_cbfs_measurement(mdata->h.filename, be32toh(mdata->h.type), hash)) + ERROR("failed to measure '%s' into TCPA log\n", mdata->h.filename); + /* We intentionally continue to boot on measurement errors. */ + } + + return false; } static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *buffer, size_t buffer_size, uint32_t compression, - const struct vb2_hash *file_hash) + const union cbfs_mdata *mdata, bool skip_verification) { size_t in_size = region_device_sz(rdev); size_t out_size = 0; void *map; - DEBUG("Decompressing %zu bytes to %p with algo %d\n", in_size, buffer, compression); + DEBUG("Decompressing %zu bytes from '%s' to %p with algo %d\n", + in_size, mdata->h.filename, buffer, compression); switch (compression) { case CBFS_COMPRESS_NONE: @@ -218,7 +200,7 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b return 0; if (rdev_readat(rdev, buffer, 0, in_size) != in_size) return 0; - if (cbfs_file_hash_mismatch(buffer, in_size, file_hash)) + if (cbfs_file_hash_mismatch(buffer, in_size, mdata, skip_verification)) return 0; return in_size; @@ -232,7 +214,7 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b if (map == NULL) return 0; - if (!cbfs_file_hash_mismatch(map, in_size, file_hash)) { + if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) { timestamp_add_now(TS_START_ULZ4F); out_size = ulz4fn(map, in_size, buffer, buffer_size); timestamp_add_now(TS_END_ULZ4F); @@ -249,7 +231,7 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b if (map == NULL) return 0; - if (!cbfs_file_hash_mismatch(map, in_size, file_hash)) { + if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) { /* Note: timestamp not useful for memory-mapped media (x86) */ timestamp_add_now(TS_START_ULZMA); out_size = ulzman(map, in_size, buffer, buffer_size); @@ -265,17 +247,216 @@ static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *b } } +struct cbfs_preload_context { + struct region_device rdev; + struct thread_handle handle; + struct list_node list_node; + void *buffer; + char name[]; +}; + +static struct list_node cbfs_preload_context_list; + +static struct cbfs_preload_context *alloc_cbfs_preload_context(size_t additional) +{ + struct cbfs_preload_context *context; + size_t size = sizeof(*context) + additional; + + context = mem_pool_alloc(&cbfs_cache, size); + + if (!context) + return NULL; + + memset(context, 0, size); + + return context; +} + +static void append_cbfs_preload_context(struct cbfs_preload_context *context) +{ + list_append(&context->list_node, &cbfs_preload_context_list); +} + +static void free_cbfs_preload_context(struct cbfs_preload_context *context) +{ + list_remove(&context->list_node); + + mem_pool_free(&cbfs_cache, context); +} + +static enum cb_err cbfs_preload_thread_entry(void *arg) +{ + struct cbfs_preload_context *context = arg; + + if (rdev_read_full(&context->rdev, context->buffer) < 0) { + ERROR("%s(name='%s') readat failed\n", __func__, context->name); + return CB_ERR; + } + + return CB_SUCCESS; +} + +void cbfs_preload(const char *name) +{ + struct region_device rdev; + union cbfs_mdata mdata; + struct cbfs_preload_context *context; + bool force_ro = false; + size_t size; + + if (!CONFIG(CBFS_PRELOAD)) + dead_code(); + + /* We don't want to cross the vboot boundary */ + if (ENV_ROMSTAGE && CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return; + + DEBUG("%s(name='%s')\n", __func__, name); + + if (_cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + return; + + size = region_device_sz(&rdev); + + context = alloc_cbfs_preload_context(strlen(name) + 1); + if (!context) { + ERROR("%s(name='%s') failed to allocate preload context\n", __func__, name); + return; + } + + context->buffer = mem_pool_alloc(&cbfs_cache, size); + if (context->buffer == NULL) { + ERROR("%s(name='%s') failed to allocate %zu bytes for preload buffer\n", + __func__, name, size); + goto out; + } + + context->rdev = rdev; + strcpy(context->name, name); + + append_cbfs_preload_context(context); + + if (thread_run(&context->handle, cbfs_preload_thread_entry, context) == 0) + return; + + ERROR("%s(name='%s') failed to start preload thread\n", __func__, name); + mem_pool_free(&cbfs_cache, context->buffer); + +out: + free_cbfs_preload_context(context); +} + +static struct cbfs_preload_context *find_cbfs_preload_context(const char *name) +{ + struct cbfs_preload_context *context; + + list_for_each(context, cbfs_preload_context_list, list_node) { + if (strcmp(context->name, name) == 0) + return context; + } + + return NULL; +} + +static enum cb_err get_preload_rdev(struct region_device *rdev, const char *name) +{ + enum cb_err err; + struct cbfs_preload_context *context; + + if (!CONFIG(CBFS_PRELOAD) || !ENV_STAGE_SUPPORTS_COOP) + return CB_ERR_ARG; + + context = find_cbfs_preload_context(name); + if (!context) + return CB_ERR_ARG; + + err = thread_join(&context->handle); + if (err != CB_SUCCESS) { + ERROR("%s(name='%s') Preload thread failed: %u\n", __func__, name, err); + + goto out; + } + + if (rdev_chain_mem(rdev, context->buffer, region_device_sz(&context->rdev)) != 0) { + ERROR("%s(name='%s') chaining failed\n", __func__, name); + + err = CB_ERR; + goto out; + } + + err = CB_SUCCESS; + + DEBUG("%s(name='%s') preload successful\n", __func__, name); + +out: + free_cbfs_preload_context(context); + + return err; +} + +static void *do_alloc(union cbfs_mdata *mdata, struct region_device *rdev, + cbfs_allocator_t allocator, void *arg, size_t *size_out, + bool skip_verification) +{ + size_t size = region_device_sz(rdev); + void *loc = NULL; + + uint32_t compression = CBFS_COMPRESS_NONE; + const struct cbfs_file_attr_compression *cattr = cbfs_find_attr(mdata, + CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr)); + if (cattr) { + compression = be32toh(cattr->compression); + size = be32toh(cattr->decompressed_size); + } + + if (size_out) + *size_out = size; + + /* allocator == NULL means do a cbfs_map() */ + if (allocator) { + loc = allocator(arg, size, mdata); + } else if (compression == CBFS_COMPRESS_NONE) { + void *mapping = rdev_mmap_full(rdev); + if (!mapping) + return NULL; + if (cbfs_file_hash_mismatch(mapping, size, mdata, skip_verification)) { + rdev_munmap(rdev, mapping); + return NULL; + } + return mapping; + } else if (!cbfs_cache.size) { + /* In order to use the cbfs_cache you need to add a CBFS_CACHE to your + * memlayout. For stages that don't have .data sections (x86 pre-RAM), + * it is not possible to add a CBFS_CACHE. */ + ERROR("Cannot map compressed file %s without cbfs_cache\n", mdata->h.filename); + return NULL; + } else { + loc = mem_pool_alloc(&cbfs_cache, size); + } + + if (!loc) { + ERROR("'%s' allocation failure\n", mdata->h.filename); + return NULL; + } + + size = cbfs_load_and_decompress(rdev, loc, size, compression, mdata, skip_verification); + if (!size) + return NULL; + + return loc; +} + void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, size_t *size_out, bool force_ro, enum cbfs_type *type) { struct region_device rdev; + bool preload_successful = false; union cbfs_mdata mdata; - void *loc; DEBUG("%s(name='%s', alloc=%p(%p), force_ro=%s, type=%d)\n", __func__, name, allocator, arg, force_ro ? "true" : "false", type ? *type : -1); - if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + if (_cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) return NULL; if (type) { @@ -289,59 +470,41 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, } } - size_t size = region_device_sz(&rdev); - uint32_t compression = CBFS_COMPRESS_NONE; - const struct cbfs_file_attr_compression *cattr = cbfs_find_attr(&mdata, - CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr)); - if (cattr) { - compression = be32toh(cattr->compression); - size = be32toh(cattr->decompressed_size); - } + /* Update the rdev with the preload content */ + if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) + preload_successful = true; - if (size_out) - *size_out = size; + void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, false); - const struct vb2_hash *file_hash = NULL; - if (CONFIG(CBFS_VERIFICATION)) - file_hash = cbfs_file_hash(&mdata); + /* When using cbfs_preload we need to free the preload buffer after populating the + * destination buffer. We know we must have a mem_rdev here, so extra mmap is fine. */ + if (preload_successful) + cbfs_unmap(rdev_mmap_full(&rdev)); - /* allocator == NULL means do a cbfs_map() */ - if (allocator) { - loc = allocator(arg, size, &mdata); - } else if (compression == CBFS_COMPRESS_NONE) { - void *mapping = rdev_mmap_full(&rdev); + return ret; +} - if (!mapping) - return NULL; +void *_cbfs_unverified_area_alloc(const char *area, const char *name, + cbfs_allocator_t allocator, void *arg, size_t *size_out) +{ + struct region_device area_rdev, file_rdev; + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_file_hash_mismatch(mapping, size, file_hash)) { - rdev_munmap(&rdev, mapping); - return NULL; - } + DEBUG("%s(area='%s', name='%s', alloc=%p(%p))\n", __func__, area, name, allocator, arg); - return mapping; - } else if (!cbfs_cache.size) { - /* - * In order to use the cbfs_cache you need to add a CBFS_CACHE to your - * memlayout. For stages that don't have .data sections (x86 pre-RAM), - * it is not possible to add a CBFS_CACHE. - */ - ERROR("Cannot map compressed file %s without cbfs_cache\n", mdata.h.filename); + if (fmap_locate_area_as_rdev(area, &area_rdev)) return NULL; - } else { - loc = mem_pool_alloc(&cbfs_cache, size); - } - if (!loc) { - ERROR("'%s' allocation failure\n", mdata.h.filename); + if (cbfs_lookup(&area_rdev, name, &mdata, &data_offset, NULL)) { + ERROR("'%s' not found in '%s'\n", name, area); return NULL; } - size = cbfs_load_and_decompress(&rdev, loc, size, compression, file_hash); - if (!size) + if (rdev_chain(&file_rdev, &area_rdev, data_offset, be32toh(mdata.h.len))) return NULL; - return loc; + return do_alloc(&mdata, &file_rdev, allocator, arg, size_out, true); } void *_cbfs_default_allocator(void *arg, size_t size, const union cbfs_mdata *unused) @@ -365,7 +528,7 @@ cb_err_t cbfs_prog_stage_load(struct prog *pstage) prog_locate_hook(pstage); - if ((err = cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev))) + if ((err = _cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev))) return err; assert(be32toh(mdata.h.type) == CBFS_TYPE_STAGE); @@ -386,17 +549,13 @@ cb_err_t cbfs_prog_stage_load(struct prog *pstage) prog_set_entry(pstage, prog_start(pstage) + be32toh(sattr->entry_offset), NULL); - const struct vb2_hash *file_hash = NULL; - if (CONFIG(CBFS_VERIFICATION)) - file_hash = cbfs_file_hash(&mdata); - /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { void *mapping = rdev_mmap_full(&rdev); rdev_munmap(&rdev, mapping); - if (cbfs_file_hash_mismatch(mapping, region_device_sz(&rdev), file_hash)) + if (cbfs_file_hash_mismatch(mapping, region_device_sz(&rdev), &mdata, false)) return CB_CBFS_HASH_MISMATCH; if (mapping == prog_start(pstage)) return CB_SUCCESS; @@ -413,7 +572,7 @@ cb_err_t cbfs_prog_stage_load(struct prog *pstage) } size_t fsize = cbfs_load_and_decompress(&rdev, prog_start(pstage), prog_size(pstage), - compression, file_hash); + compression, &mdata, false); if (!fsize) return CB_ERR; @@ -522,7 +681,7 @@ static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); void *cbmem_mcache = cbmem_add(cbmem_id, real_size); if (!cbmem_mcache) { - printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", + printk(BIOS_ERR, "Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", cbmem_id, real_size); return; } diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index a7d67a3981..0c56095732 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include +#include /* * Structure describing console buffer. It is overlaid on a flat memory area, @@ -37,6 +39,8 @@ _Static_assert(CONFIG_CONSOLE_CBMEM_BUFFER_SIZE <= MAX_SIZE, static struct cbmem_console *current_console; +static bool console_paused; + /* * While running from ROM, before DRAM is initialized, some area in cache as * RAM space is used for the console buffer storage. The size and location of @@ -88,7 +92,7 @@ void cbmemc_init(void) void cbmemc_tx_byte(unsigned char data) { - if (!current_console || !current_console->size) + if (!current_console || !current_console->size || console_paused) return; u32 flags = current_console->cursor & ~CURSOR_MASK; @@ -135,6 +139,16 @@ static void copy_console_buffer(struct cbmem_console *src_cons_p) src_cons_p->size = 0; } +void cbmemc_copy_in(void *buffer, size_t size) +{ + struct cbmem_console *previous = (void *)buffer; + + if (!buffer_valid(previous, size)) + return; + + copy_console_buffer(previous); +} + static void cbmemc_reinit(int is_recovery) { const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; @@ -154,18 +168,53 @@ RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) POSTCAR_CBMEM_INIT_HOOK(cbmemc_reinit) #if CONFIG(CONSOLE_CBMEM_DUMP_TO_UART) +void cbmem_dump_console_to_uart(void) +{ + u32 cursor; + unsigned int console_index; + + if (!current_console) + return; + + console_index = get_uart_for_console(); + + uart_init(console_index); + if (current_console->cursor & OVERFLOW) { + for (cursor = current_console->cursor & CURSOR_MASK; + cursor < current_console->size; cursor++) { + if (BIOS_LOG_IS_MARKER(current_console->body[cursor])) + continue; + if (current_console->body[cursor] == '\n') + uart_tx_byte(console_index, '\r'); + uart_tx_byte(console_index, current_console->body[cursor]); + } + } + for (cursor = 0; cursor < (current_console->cursor & CURSOR_MASK); cursor++) { + if (BIOS_LOG_IS_MARKER(current_console->body[cursor])) + continue; + if (current_console->body[cursor] == '\n') + uart_tx_byte(console_index, '\r'); + uart_tx_byte(console_index, current_console->body[cursor]); + } +} +#endif + void cbmem_dump_console(void) { u32 cursor; if (!current_console) return; - uart_init(0); + console_paused = true; + if (current_console->cursor & OVERFLOW) for (cursor = current_console->cursor & CURSOR_MASK; cursor < current_console->size; cursor++) - uart_tx_byte(0, current_console->body[cursor]); + if (!BIOS_LOG_IS_MARKER(current_console->body[cursor])) + do_putchar(current_console->body[cursor]); for (cursor = 0; cursor < (current_console->cursor & CURSOR_MASK); cursor++) - uart_tx_byte(0, current_console->body[cursor]); + if (!BIOS_LOG_IS_MARKER(current_console->body[cursor])) + do_putchar(current_console->body[cursor]); + + console_paused = false; } -#endif diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 28cc242f1c..b45c9505f8 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -13,7 +13,7 @@ void stage_cache_add(int stage_id, const struct prog *stage) meta = cbmem_add(CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); if (meta == NULL) { - printk(BIOS_ERR, "Error: Can't add %x metadata to cbmem\n", + printk(BIOS_ERR, "Can't add %x metadata to cbmem\n", CBMEM_ID_STAGEx_META + stage_id); return; } @@ -23,7 +23,7 @@ void stage_cache_add(int stage_id, const struct prog *stage) c = cbmem_add(CBMEM_ID_STAGEx_CACHE + stage_id, prog_size(stage)); if (c == NULL) { - printk(BIOS_ERR, "Error: Can't add stage_cache %x to cbmem\n", + printk(BIOS_ERR, "Can't add stage_cache %x to cbmem\n", CBMEM_ID_STAGEx_CACHE + stage_id); return; } @@ -51,7 +51,7 @@ void stage_cache_get_raw(int stage_id, void **base, size_t *size) e = cbmem_entry_find(CBMEM_ID_STAGEx_RAW + stage_id); if (e == NULL) { - printk(BIOS_ERR, "Error: Can't find raw %x data in cbmem\n", + printk(BIOS_ERR, "Can't find raw %x data in cbmem\n", CBMEM_ID_STAGEx_RAW + stage_id); return; } @@ -72,7 +72,7 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) meta = cbmem_find(CBMEM_ID_STAGEx_META + stage_id); if (meta == NULL) { - printk(BIOS_ERR, "Error: Can't find %x metadata in cbmem\n", + printk(BIOS_ERR, "Can't find %x metadata in cbmem\n", CBMEM_ID_STAGEx_META + stage_id); return; } @@ -80,7 +80,7 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) e = cbmem_entry_find(CBMEM_ID_STAGEx_CACHE + stage_id); if (e == NULL) { - printk(BIOS_ERR, "Error: Can't find stage_cache %x in cbmem\n", + printk(BIOS_ERR, "Can't find stage_cache %x in cbmem\n", CBMEM_ID_STAGEx_CACHE + stage_id); return; } diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 3821e5cced..fb3ce905bf 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -1501,7 +1501,7 @@ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay) uint32_t phandle_base = tree->max_phandle; uint32_t new_max = dt_adjust_all_phandles(overlay->root, phandle_base); if (!new_max) { - printk(BIOS_DEBUG, "ERROR: invalid phandles in overlay\n"); + printk(BIOS_ERR, "invalid phandles in overlay\n"); return -1; } tree->max_phandle = new_max; @@ -1512,7 +1512,7 @@ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay) "/__local_fixups__", NULL, NULL, 0); if (local_fixups && dt_fixup_locals(overlay->root, local_fixups, phandle_base) < 0) { - printk(BIOS_DEBUG, "ERROR: invalid local fixups in overlay\n"); + printk(BIOS_ERR, "invalid local fixups in overlay\n"); return -1; } @@ -1536,8 +1536,7 @@ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay) "/__symbols__", NULL, NULL, 0); if (fixups && dt_fixup_all_externals(tree, symbols, overlay, fixups, overlay_symbols) < 0) { - printk(BIOS_DEBUG, - "ERROR: cannot match external fixups from overlay\n"); + printk(BIOS_ERR, "cannot match external fixups from overlay\n"); return -1; } @@ -1546,7 +1545,7 @@ int dt_apply_overlay(struct device_tree *tree, struct device_tree *overlay) struct device_tree_node *fragment; list_for_each(fragment, overlay->root->children, list_node) if (dt_import_fragment(tree, fragment, overlay_symbols) < 0) { - printk(BIOS_DEBUG, "ERROR: bad DT fragment '%s'\n", + printk(BIOS_ERR, "bad DT fragment '%s'\n", fragment->name); return -1; } diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c index fb8e06f149..3507366a3d 100644 --- a/src/lib/dimm_info_util.c +++ b/src/lib/dimm_info_util.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, uint16_t data_width) +uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width, + uint16_t data_width) { uint8_t out; @@ -38,7 +40,10 @@ uint8_t smbios_bus_width_to_spd_width(uint16_t total_width, uint16_t data_width) switch (extension_bits) { case 8: - out |= SPD_ECC_8BIT; + if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5) + out |= SPD_ECC_8BIT_LP5_DDR5; + else + out |= SPD_ECC_8BIT; break; case 0: /* No extension bits */ @@ -68,18 +73,8 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size, uint32_t extended_size) return memory_size; } -uint8_t -smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor) +uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type, + smbios_memory_form_factor form_factor) { - /* This switch reverses the switch in smbios.c */ - switch (form_factor) { - case MEMORY_FORMFACTOR_DIMM: - return SPD_UDIMM; - case MEMORY_FORMFACTOR_RIMM: - return SPD_RDIMM; - case MEMORY_FORMFACTOR_SODIMM: - return SPD_SODIMM; - default: - return SPD_UNDEFINED; - } + return convert_form_factor_to_module_type(memory_type, form_factor); } diff --git a/src/lib/dp_aux.c b/src/lib/dp_aux.c new file mode 100644 index 0000000000..6a925f13f6 --- /dev/null +++ b/src/lib/dp_aux.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +bool dp_aux_request_is_write(enum aux_request request) +{ + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + case I2C_RAW_WRITE: + case DPCD_WRITE: + return true; + default: + return false; + } +} + +enum i2c_over_aux dp_get_aux_cmd(enum aux_request request, uint32_t remaining_after_this) +{ + switch (request) { + case I2C_RAW_WRITE_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_WRITE_MOT_0; + __fallthrough; + case I2C_RAW_WRITE: + return I2C_OVER_AUX_WRITE_MOT_1; + case I2C_RAW_READ_AND_STOP: + if (!remaining_after_this) + return I2C_OVER_AUX_READ_MOT_0; + __fallthrough; + case I2C_RAW_READ: + return I2C_OVER_AUX_READ_MOT_1; + case DPCD_WRITE: + return NATIVE_AUX_WRITE; + case DPCD_READ: + default: + return NATIVE_AUX_READ; + } +} diff --git a/src/lib/edid.c b/src/lib/edid.c index 55876e8a7c..06b9ceefc1 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1183,13 +1183,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) switch (edid[0x13]) { case 4: c.claims_one_point_four = 1; - /* fall through */ + __fallthrough; case 3: c.claims_one_point_three = 1; - /* fall through */ + __fallthrough; case 2: c.claims_one_point_two = 1; - /* fall through */ + __fallthrough; default: c.claims_one_point_oh = 1; } @@ -1507,7 +1507,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n"); else if (!c.has_name_descriptor || !c.has_range_descriptor) - printk(BIOS_WARNING, "WARNING: EDID block does NOT " + printk(BIOS_WARNING, "EDID block does NOT " "fully conform to EDID 1.3.\n"); if (c.nonconformant_digital_display) diff --git a/src/lib/fit.c b/src/lib/fit.c index 748cd611a4..08fd0455b3 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -2,7 +2,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include @@ -79,7 +78,7 @@ static struct fit_image_node *find_image(const char *name) if (!strcmp(image->name, name)) return image; } - printk(BIOS_ERR, "ERROR: Cannot find image node %s!\n", name); + printk(BIOS_ERR, "Cannot find image node %s!\n", name); return NULL; } @@ -414,8 +413,7 @@ static int fit_update_compat(struct fit_config_node *config) uint32_t fdt_offset = be32_to_cpu(fdt_header->structure_offset); if (config->fdt->compression != CBFS_COMPRESS_NONE) { - printk(BIOS_ERR, - "ERROR: config %s has a compressed FDT without " + printk(BIOS_ERR, "config %s has a compressed FDT without " "external compatible property, skipping.\n", config->name); return -1; @@ -423,15 +421,13 @@ static int fit_update_compat(struct fit_config_node *config) /* FDT overlays are not supported in legacy FIT images. */ if (config->overlays.next) { - printk(BIOS_ERR, - "ERROR: config %s has overlay but no compat!\n", + printk(BIOS_ERR, "config %s has overlay but no compat!\n", config->name); return -1; } if (fdt_find_compat(fdt_blob, fdt_offset, &config->compat)) { - printk(BIOS_ERR, - "ERROR: Can't find compat string in FDT %s " + printk(BIOS_ERR, "Can't find compat string in FDT %s " "for config %s, skipping.\n", config->fdt->name, config->name); return -1; @@ -468,7 +464,7 @@ struct fit_config_node *fit_load(void *fit) struct device_tree *tree = fdt_unflatten(fit); if (!tree) { - printk(BIOS_ERR, "ERROR: Failed to unflatten FIT image!\n"); + printk(BIOS_ERR, "Failed to unflatten FIT image!\n"); return NULL; } @@ -495,21 +491,19 @@ struct fit_config_node *fit_load(void *fit) /* Process and list the configs. */ list_for_each(config, config_nodes, list_node) { if (!config->kernel) { - printk(BIOS_ERR, - "ERROR: config %s has no kernel, skipping.\n", + printk(BIOS_ERR, "config %s has no kernel, skipping.\n", config->name); continue; } if (!config->fdt) { - printk(BIOS_ERR, - "ERROR: config %s has no FDT, skipping.\n", + printk(BIOS_ERR, "config %s has no FDT, skipping.\n", config->name); continue; } if (config->ramdisk && config->ramdisk->compression < 0) { - printk(BIOS_WARNING, "WARN: Ramdisk is compressed with " + printk(BIOS_WARNING, "Ramdisk is compressed with " "an unsupported algorithm, discarding config %s." "\n", config->name); continue; diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 9613418b95..d61bfd5c4e 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -36,7 +35,7 @@ static bool extract(struct region *region, struct fit_image_node *node) size_t true_size = 0; if (node->size == 0) { - printk(BIOS_ERR, "ERROR: The %s size is 0\n", node->name); + printk(BIOS_ERR, "The %s size is 0\n", node->name); return true; } @@ -51,7 +50,7 @@ static bool extract(struct region *region, struct fit_image_node *node) comp_name = "Decompressing LZ4"; break; default: - printk(BIOS_ERR, "ERROR: Unsupported compression\n"); + printk(BIOS_ERR, "Unsupported compression\n"); return true; } @@ -77,7 +76,7 @@ static bool extract(struct region *region, struct fit_image_node *node) } if (!true_size) { - printk(BIOS_ERR, "ERROR: %s decompression failed!\n", + printk(BIOS_ERR, "%s decompression failed!\n", comp_name); return true; } @@ -177,13 +176,13 @@ void fit_payload(struct prog *payload, void *data) struct fit_config_node *config = fit_load(data); if (!config) { - printk(BIOS_ERR, "ERROR: Could not load FIT\n"); + printk(BIOS_ERR, "Could not load FIT\n"); return; } dt = unpack_fdt(config->fdt); if (!dt) { - printk(BIOS_ERR, "ERROR: Failed to unflatten the FDT.\n"); + printk(BIOS_ERR, "Failed to unflatten the FDT.\n"); return; } @@ -191,7 +190,7 @@ void fit_payload(struct prog *payload, void *data) list_for_each(chain, config->overlays, list_node) { struct device_tree *overlay = unpack_fdt(chain->overlay); if (!overlay || dt_apply_overlay(dt, overlay)) { - printk(BIOS_ERR, "ERROR: Failed to apply overlay %s!\n", + printk(BIOS_ERR, "Failed to apply overlay %s!\n", chain->overlay->name); } } @@ -214,7 +213,7 @@ void fit_payload(struct prog *payload, void *data) /* Invoke arch specific payload placement and fixups */ if (!fit_payload_arch(payload, config, &kernel, &fdt, &initrd)) { - printk(BIOS_ERR, "ERROR: Failed to find free memory region\n"); + printk(BIOS_ERR, "Failed to find free memory region\n"); bootmem_dump_ranges(); return; } @@ -228,7 +227,7 @@ void fit_payload(struct prog *payload, void *data) if (config->ramdisk && extract(&initrd, config->ramdisk)) { - printk(BIOS_ERR, "ERROR: Failed to extract initrd\n"); + printk(BIOS_ERR, "Failed to extract initrd\n"); prog_set_entry(payload, NULL, NULL); return; } @@ -236,7 +235,7 @@ void fit_payload(struct prog *payload, void *data) timestamp_add_now(TS_KERNEL_DECOMPRESSION); if (extract(&kernel, config->kernel)) { - printk(BIOS_ERR, "ERROR: Failed to extract kernel\n"); + printk(BIOS_ERR, "Failed to extract kernel\n"); prog_set_entry(payload, NULL, NULL); return; } diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 6ff8431b04..251125522e 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -80,7 +80,7 @@ static void setup_preram_cache(struct region_device *cache_rdev) if (!verify_fmap(fmap)) goto register_cache; - printk(BIOS_ERR, "ERROR: FMAP cache corrupted?!\n"); + printk(BIOS_ERR, "FMAP cache corrupted?!\n"); if (CONFIG(TOCTOU_SAFETY)) die("TOCTOU safety relies on FMAP cache"); } @@ -301,13 +301,13 @@ static void fmap_setup_cbmem_cache(int unused) const size_t s = region_device_sz(&fmrd); struct fmap *fmap = cbmem_add(CBMEM_ID_FMAP, s); if (!fmap) { - printk(BIOS_ERR, "ERROR: Failed to allocate CBMEM\n"); + printk(BIOS_ERR, "Failed to allocate CBMEM\n"); return; } const ssize_t ret = rdev_readat(&fmrd, fmap, 0, s); if (ret != s) { - printk(BIOS_ERR, "ERROR: Failed to read FMAP into CBMEM\n"); + printk(BIOS_ERR, "Failed to read FMAP into CBMEM\n"); cbmem_entry_remove(cbmem_entry_find(CBMEM_ID_FMAP)); return; } diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index 8e45c004fb..72cf225cae 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -11,6 +11,7 @@ #include #include #include +#include uint64_t fw_config_get(void) { @@ -21,30 +22,40 @@ uint64_t fw_config_get(void) if (fw_config_value_initialized) return fw_config_value; fw_config_value_initialized = true; - - /* Look in CBFS to allow override of value. */ - if (CONFIG(FW_CONFIG_SOURCE_CBFS)) { - if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value, - sizeof(fw_config_value)) != sizeof(fw_config_value)) { - printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", - __func__); - fw_config_value = UNDEFINED_FW_CONFIG; - } else { - printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", - fw_config_value); - return fw_config_value; - } - } + fw_config_value = UNDEFINED_FW_CONFIG; /* Read the value from EC CBI. */ if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) { - if (google_chromeec_cbi_get_fw_config(&fw_config_value)) { - printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); - fw_config_value = UNDEFINED_FW_CONFIG; - } + if (google_chromeec_cbi_get_fw_config(&fw_config_value)) + printk(BIOS_WARNING, "%s: Could not get fw_config from CBI\n", + __func__); + else + printk(BIOS_INFO, "FW_CONFIG value from CBI is 0x%" PRIx64 "\n", + fw_config_value); + } + + /* Look in CBFS to allow override of value. */ + if (CONFIG(FW_CONFIG_SOURCE_CBFS) && fw_config_value == UNDEFINED_FW_CONFIG) { + if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value, + sizeof(fw_config_value)) != sizeof(fw_config_value)) + printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", + __func__); + else + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n", + fw_config_value); + } + + if (CONFIG(FW_CONFIG_SOURCE_VPD) && fw_config_value == UNDEFINED_FW_CONFIG) { + int vpd_value; + if (vpd_get_int("fw_config", VPD_RW_THEN_RO, &vpd_value)) { + fw_config_value = vpd_value; + printk(BIOS_INFO, "FW_CONFIG value from VPD is 0x%" PRIx64 "\n", + fw_config_value); + } else + printk(BIOS_WARNING, "%s: Could not get fw_config from vpd\n", + __func__); } - printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value); return fw_config_value; } diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index e7405648d6..065ba71404 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -13,6 +13,7 @@ ADAFLAGS_libgnat-$(1) := \ -I$$(src)/lib/gnat/ \ $$(GCC_ADAFLAGS_$(1)) \ -Werror \ + -fno-pie \ libgnat-$(1)-y += a-unccon.ads libgnat-$(1)-y += ada.ads diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index fe8e53f83a..b646e0c13c 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include static boot_state_t bs_pre_device(void *arg); @@ -290,6 +290,9 @@ static void bs_call_callbacks(struct boot_state *state, mono_time_diff_microseconds(&mt_start, &mt_stop) / USECS_PER_MSEC); } + + bs_run_timers(0); + continue; } @@ -355,6 +358,8 @@ static void bs_walk_state_machine(void) bs_sample_time(state); + bs_run_timers(0); + bs_call_callbacks(state, current_phase.seq); if (CONFIG(DEBUG_BOOT_STATE)) diff --git a/src/lib/list.c b/src/lib/list.c index 01d5c8914e..c3f8ee42c8 100644 --- a/src/lib/list.c +++ b/src/lib/list.c @@ -28,3 +28,11 @@ void list_insert_before(struct list_node *node, struct list_node *before) if (node->prev) node->prev->next = node; } + +void list_append(struct list_node *node, struct list_node *head) +{ + while (head->next) + head = head->next; + + list_insert_after(node, head); +} diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 1a361ea3b9..25a8836c36 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -75,7 +75,15 @@ static int load_relocatable_ramstage(struct prog *ramstage) return rmodule_stage_load(&rmod_ram); } +void preload_ramstage(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + printk(BIOS_DEBUG, "Preloading ramstage\n"); + + cbfs_preload(CONFIG_CBFS_PREFIX "/ramstage"); +} void run_ramstage(void) { struct prog ramstage = @@ -127,81 +135,47 @@ fail: static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); -static struct thread_handle payload_preload_handle; - -static enum cb_err payload_preload_thread_entry(void *arg) -{ - size_t size; - struct prog *payload = &global_payload; - - printk(BIOS_DEBUG, "Preloading payload\n"); - - payload->cbfs_type = CBFS_TYPE_QUERY; - - size = cbfs_type_load(prog_name(payload), _payload_preload_cache, - REGION_SIZE(payload_preload_cache), &payload->cbfs_type); - - if (!size) { - printk(BIOS_ERR, "ERROR: Preloading payload failed\n"); - return CB_ERR; - } - - printk(BIOS_DEBUG, "Preloading payload complete\n"); - - return CB_SUCCESS; -} - void payload_preload(void) { - struct thread_handle *handle = &payload_preload_handle; - - if (!CONFIG(PAYLOAD_PRELOAD)) + if (!CONFIG(CBFS_PRELOAD)) return; - if (thread_run(handle, payload_preload_thread_entry, NULL)) - printk(BIOS_ERR, "ERROR: Failed to start payload preload thread\n"); + cbfs_preload(global_payload.name); } void payload_load(void) { struct prog *payload = &global_payload; - struct thread_handle *handle = &payload_preload_handle; - void *mapping = NULL; - void *buffer; + void *mapping; timestamp_add_now(TS_LOAD_PAYLOAD); if (prog_locate_hook(payload)) goto out; - if (CONFIG(PAYLOAD_PRELOAD) && thread_join(handle) == CB_SUCCESS) { - buffer = _payload_preload_cache; - } else { - payload->cbfs_type = CBFS_TYPE_QUERY; - mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type); - buffer = mapping; - } + payload->cbfs_type = CBFS_TYPE_QUERY; + mapping = cbfs_type_map(prog_name(payload), NULL, &payload->cbfs_type); - if (!buffer) + if (!mapping) goto out; switch (prog_cbfs_type(payload)) { case CBFS_TYPE_SELF: /* Simple ELF */ - selfload_mapped(payload, buffer, BM_MEM_RAM); + selfload_mapped(payload, mapping, BM_MEM_RAM); break; case CBFS_TYPE_FIT: /* Flattened image tree */ if (CONFIG(PAYLOAD_FIT_SUPPORT)) { - fit_payload(payload, buffer); + fit_payload(payload, mapping); break; - } /* else fall-through */ + } + __fallthrough; default: die_with_post_code(POST_INVALID_ROM, "Unsupported payload type %d.\n", payload->cbfs_type); break; } - if (mapping) - cbfs_unmap(mapping); + cbfs_unmap(mapping); out: if (prog_entry(payload) == NULL) die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n"); diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index be36141e26..44830a8537 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -154,21 +154,21 @@ bool check_if_dimm_changed(u8 *spd_cache, struct spd_block *blk) bool dimm_present_in_cache; bool dimm_changed = false; /* Check if the dimm is the same with last system boot. */ - for (i = 0; i < SC_SPD_NUMS && dimm_changed == false; i++) { + for (i = 0; i < SC_SPD_NUMS && !dimm_changed; i++) { /* Return true if any error happened here. */ if (get_spd_sn(blk->addr_map[i], &sn) == CB_ERR) return true; dimm_present_in_cache = get_cached_dimm_present(spd_cache, i); /* Dimm is not present now. */ if (sn == 0xffffffff) { - if (dimm_present_in_cache == false) + if (!dimm_present_in_cache) printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is not present\n", i); else { printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d lost\n", i); dimm_changed = true; } } else { /* Dimm is present now. */ - if (dimm_present_in_cache == true) { + if (dimm_present_in_cache) { if (memcmp(&sn, spd_cache + SC_SPD_OFFSET(i) + DDR4_SPD_SN_OFF, SPD_SN_LEN) == 0) printk(BIOS_NOTICE, "SPD_CACHE: DIMM%d is the same\n", @@ -195,7 +195,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) /* Find the first present SPD */ for (i = 0; i < SC_SPD_NUMS; i++) - if (get_cached_dimm_present(spd_cache, i) == true) + if (get_cached_dimm_present(spd_cache, i)) break; if (i == SC_SPD_NUMS) { @@ -211,7 +211,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) blk->len = SPD_PAGE_LEN; for (i = 0; i < SC_SPD_NUMS; i++) - if (get_cached_dimm_present(spd_cache, i) == true) + if (get_cached_dimm_present(spd_cache, i)) blk->spd_array[i] = spd_cache + SC_SPD_OFFSET(i); else blk->spd_array[i] = NULL; diff --git a/src/lib/string.c b/src/lib/string.c index 9677520137..a9515f70ce 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -1,6 +1,5 @@ #include #include -#include #include #include #include diff --git a/src/lib/thread.c b/src/lib/thread.c index da6189d6f1..adfc298a71 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -283,15 +282,14 @@ int thread_run(struct thread_handle *handle, enum cb_err (*func)(void *), void * current = current_thread(); if (!thread_can_yield(current)) { - printk(BIOS_ERR, - "thread_run() called from non-yielding context!\n"); + printk(BIOS_ERR, "%s() called from non-yielding context!\n", __func__); return -1; } t = get_free_thread(); if (t == NULL) { - printk(BIOS_ERR, "thread_run() No more threads!\n"); + printk(BIOS_ERR, "%s: No more threads!\n", __func__); return -1; } @@ -318,15 +316,14 @@ int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), current = current_thread(); if (!thread_can_yield(current)) { - printk(BIOS_ERR, - "thread_run() called from non-yielding context!\n"); + printk(BIOS_ERR, "%s() called from non-yielding context!\n", __func__); return -1; } t = get_free_thread(); if (t == NULL) { - printk(BIOS_ERR, "thread_run() No more threads!\n"); + printk(BIOS_ERR, "%s: No more threads!\n", __func__); return -1; } @@ -398,10 +395,10 @@ enum cb_err thread_join(struct thread_handle *handle) if (handle->state == THREAD_UNINITIALIZED) return CB_ERR_ARG; - stopwatch_init(&sw); - printk(BIOS_SPEW, "waiting for thread\n"); + stopwatch_init(&sw); + while (handle->state != THREAD_DONE) assert(thread_yield() == 0); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7347d07b16..b92975fb13 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -102,7 +102,7 @@ static const char *timestamp_name(enum timestamp_id id) } static void timestamp_add_table_entry(struct timestamp_table *ts_table, - enum timestamp_id id, uint64_t ts_time) + enum timestamp_id id, int64_t ts_time) { struct timestamp_entry *tse; @@ -114,10 +114,10 @@ static void timestamp_add_table_entry(struct timestamp_table *ts_table, tse->entry_stamp = ts_time; if (ts_table->num_entries == ts_table->max_entries) - printk(BIOS_ERR, "ERROR: Timestamp table full\n"); + printk(BIOS_ERR, "Timestamp table full\n"); } -void timestamp_add(enum timestamp_id id, uint64_t ts_time) +void timestamp_add(enum timestamp_id id, int64_t ts_time) { struct timestamp_table *ts_table; @@ -127,7 +127,7 @@ void timestamp_add(enum timestamp_id id, uint64_t ts_time) ts_table = timestamp_table_get(); if (!ts_table) { - printk(BIOS_ERR, "ERROR: No timestamp table found\n"); + printk(BIOS_ERR, "No timestamp table found\n"); return; } @@ -135,7 +135,7 @@ void timestamp_add(enum timestamp_id id, uint64_t ts_time) timestamp_add_table_entry(ts_table, id, ts_time); if (CONFIG(TIMESTAMPS_ON_CONSOLE)) - printk(BIOS_INFO, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); + printk(BIOS_INFO, "Timestamp - %s: %lld\n", timestamp_name(id), ts_time); } void timestamp_add_now(enum timestamp_id id) @@ -155,7 +155,7 @@ void timestamp_init(uint64_t base) ts_cache = timestamp_cache_get(); if (!ts_cache) { - printk(BIOS_ERR, "ERROR: No timestamp cache to init\n"); + printk(BIOS_ERR, "No timestamp cache to init\n"); return; } @@ -170,7 +170,7 @@ static void timestamp_sync_cache_to_cbmem(struct timestamp_table *ts_cbmem_table ts_cache_table = timestamp_table_get(); if (!ts_cache_table) { - printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); + printk(BIOS_ERR, "No timestamp cache found\n"); return; } @@ -223,7 +223,7 @@ static void timestamp_reinit(int is_recovery) } if (ts_cbmem_table == NULL) { - printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + printk(BIOS_ERR, "No timestamp table allocated\n"); timestamp_table_set(NULL); return; } @@ -253,7 +253,7 @@ void timestamp_rescale_table(uint16_t N, uint16_t M) /* No timestamp table found */ if (ts_table == NULL) { - printk(BIOS_ERR, "ERROR: No timestamp table found\n"); + printk(BIOS_ERR, "No timestamp table found\n"); return; } diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index f9022a4c75..bf5c9b095b 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -37,19 +37,19 @@ Device (BAT) Method (_BIF, 0, Serialized) { /* Design Capacity */ - Store (DGCP * 10000 / DGVO, Index (PBIF, 1)) + Store (DGCP * 10000 / DGVO, PBIF[1]) /* Last Full Charge Capacity */ - Store (FLCP * 10000 / DGVO, Index (PBIF, 2)) + Store (FLCP * 10000 / DGVO, PBIF[2]) /* Design Voltage */ - Store (DGVO, Index (PBIF, 4)) + Store (DGVO, PBIF[4]) /* Design Capacity of Warning */ - Store (BDW * 10000 / DGVO, Index (PBIF, 5)) + Store (BDW * 10000 / DGVO, PBIF[5]) /* Design Capacity of Low */ - Store (BDL, Index (PBIF, 6)) + Store (BDL, PBIF[6]) Return (PBIF) } @@ -70,22 +70,22 @@ Device (BAT) * bit 1 = charging * bit 2 = critical level */ - Store (BSTS, Index (PBST, 0)) + Store (BSTS, PBST[0]) /* * 1: BATTERY PRESENT RATE */ - Store (BPR, Index (PBST, 1)) + Store (BPR, PBST[1]) /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRC * 10000 / DGVO, Index (PBST, 2)) + Store (BRC * 10000 / DGVO, PBST[2]) /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BPV, Index (PBST, 3)) + Store (BPV, PBST[3]) Return (PBST) } diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 5950dec685..ab8787c32c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "1" - register "SataMode" = "0" # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 register "SataPortsEnable[0]" = "1" @@ -48,7 +47,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000000..449eeee39a --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,110 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_HID + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_INTEL_PTT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CRB_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config CBFS_SIZE + default 0x600000 + +config CONSOLE_SERIAL + default n + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if INCLUDE_EC_FIRMWARE + +config INCLUDE_EC_FIRMWARE + bool "Include EC firmware blob" + help + If corrupted, the EC can recover its firmware from the SPI flash. + +config EC_FIRMWARE_FILE + string "Location of EC firmware blob" + depends on INCLUDE_EC_FIRMWARE + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/ec.bin" + +config EC_USE_LGMR + bool "Use LPC generic memory range for EC" + help + Using MMIO accesses for EC range can improve performance. + +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio" + select NHLT_DMIC_1CH + # It appears OS chooses blob? + select NHLT_DMIC_2CH +# select NHLT_DMIC_4CH # Wrong lie to tell? Double-check blob. + +config LINEAR_FRAMEBUFFER_MAX_HEIGHT + default 1080 + +config LINEAR_FRAMEBUFFER_MAX_WIDTH + default 1920 + +config MAINBOARD_DIR + default "acer/aspire_vn7_572g" + +config MAINBOARD_FAMILY + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + default "Aspire VN7-572G" + +config MAINBOARD_SUPPORTS_KABYLAKE_DUAL + default n + +config MAINBOARD_SUPPORTS_KABYLAKE_QUAD + default n + +config MAX_CPUS + default 4 + +config ME_CLEANER_ARGS + default "-s" + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config POST_IO + default n + +config UART_FOR_CONSOLE + default 2 + +config VGA_BIOS_DGPU_ID + default "10de,139a" + +config VGA_BIOS_ID + default "8086,1916" + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000000..b881680e4e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000000..79c66c597e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += die.c + +bootblock-y += bootblock.c +bootblock-y += ec.c +bootblock-y += gpio_early.c + +ramstage-y += ec.c +ramstage-y += gpio.c + +smm-y += die.c +smm-y += ec.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +files_added:: +ifeq ($(CONFIG_INCLUDE_EC_FIRMWARE),y) + $(CBFSTOOL) $(obj)/coreboot.rom write -r EC -f $(CONFIG_EC_FIRMWARE_FILE) --fill-upward +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ac.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ac.asl new file mode 100644 index 0000000000..c92cbd9c76 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ac.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (ADP1) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { +#if CONFIG(EC_USE_LGMR) + Return (MACS) +#else + Return (EACS) +#endif + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/battery.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/battery.asl new file mode 100644 index 0000000000..1f4fb47ba5 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/battery.asl @@ -0,0 +1,416 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if !CONFIG(EC_USE_LGMR) +/* TODO: Consider actually enforcing mutex? */ +Mutex (BMTX, 0) +#endif +Name (B0ST, 0) /* Battery 0 status */ + +/* + * EC Registers + * + * "EBID" is the battery page selector. + * + * + * Data on the 128 bits following offset + * 0xE0 is accessed in the following order: + * + * Information: + * Page 0: EBCM # start on page 0 # + * Page 0: EBFC + * Page 1: EBDC # switch to page 1 # + * Page 1: EBDV + * Page 1: EBSN + * Page 3: EBDN # switch to page 3 # + * Page 4: EBCH # switch to page 4 # + * Page 2: EBMN # switch to page 2 # + * + * Status: + * Page 0: EBAC # start on page 0 # + * Page 0: EBRC + * Page 0: EBFC + * Page 0: EBVO + */ +/* Page 0 */ +Field (RAM, ByteAcc, Lock, Preserve) +{ + Offset (0xE0), + EBRC, 16, /* Battery remaining capacity */ + EBFC, 16, /* Battery full charge capacity */ + EBPE, 16, + EBAC, 16, /* Battery present rate */ + EBVO, 16, /* Battery voltage */ + , 15, + EBCM, 1, /* Battery charging */ + EBCU, 16, + EBTV, 16, +} + +/* Page 1 */ +Field (RAM, ByteAcc, Lock, Preserve) +{ + Offset (0xE0), + EBDC, 16, /* Battery design capacity */ + EBDV, 16, /* Battery design voltage */ + EBSN, 16, /* Battery serial number */ +} + +/* Page 2 */ +Field (RAM, ByteAcc, NoLock, Preserve) +{ + Offset (0xE0), + EBMN, 128, /* Battery manufacturer */ +} + +/* Page 3 */ +Field (RAM, ByteAcc, NoLock, Preserve) +{ + Offset (0xE0), + EBDN, 128, /* Battery model */ +} + +/* Page 4 */ +Field (RAM, ByteAcc, NoLock, Preserve) +{ + Offset (0xE0), + EBCH, 128, /* Battery type */ +} + +#if CONFIG(EC_USE_LGMR) +OperationRegion (MBB0, SystemMemory, (LGMR + 0x80), 0xFF) +Field (MBB0, ByteAcc, Lock, Preserve) +{ + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16, +} + +Field (MBB0, ByteAcc, Lock, Preserve) +{ + Offset (0x10), + MBDC, 16, + MBDV, 16, + MBSN, 16, +} + +Field (MBB0, ByteAcc, Lock, Preserve) +{ + Offset (0x40), + MBMN, 128, +} + +Field (MBB0, ByteAcc, Lock, Preserve) +{ + Offset (0x50), + MBDN, 256, +} + +Field (MBB0, ByteAcc, Lock, Preserve) +{ + Offset (0x70), + MBCH, 128, +} +#endif + +/* + * Arg0: Battery number + * Arg1: Battery Information Package + * Arg2: Status + */ +#if !CONFIG(EC_USE_LGMR) +Method (GBIF, 3, Serialized) +{ + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another function +#else +Method (GBIF, 3, NotSerialized) +{ +#endif + If (Arg2) + { + Arg1[1] = 0xFFFFFFFF + Arg1[2] = 0xFFFFFFFF + Arg1[4] = 0xFFFFFFFF + Arg1[5] = 0 + Arg1[6] = 0 + } + Else + { +#if CONFIG(EC_USE_LGMR) + Local0 = MBCM +#else + EBID = 0 // We don't know which page was active + Local0 = EBCM +#endif + Arg1[0] = (Local0 ^ 1) + +#if CONFIG(EC_USE_LGMR) + Local2 = MBFC + Local1 = MBDC +#else + Local2 = EBFC + EBID = 1 + Local1 = EBDC +#endif + If (Local0) + { + Local2 *= 10 + Local1 *= 10 + } + + Arg1[1] = Local1 // Design capacity + Arg1[2] = Local2 // Last full charge capacity +#if CONFIG(EC_USE_LGMR) + Arg1[4] = MBDV // Design voltage +#else + Arg1[4] = EBDV // Design voltage +#endif + Local6 = (Local2 / 100) // Warning capacities; Remainders ignored + Arg1[5] = (Local6 * 7) /* Low: 7% */ + Arg1[6] = ((Local6 * 11) / 2) /* Very low: 5.5% */ +#if CONFIG(EC_USE_LGMR) + Local7 = MBSN +#else + Local7 = EBSN +#endif + Name (SERN, Buffer (0x06) { " " }) + /* + * Convert hex to decimal. + * - There appears to be a bug in the vendor's implementation: + * The correct answer has, or can have, 5 digits, so Local6 = 5. + * Also see "SERN" buffer. + * - Userspace prints reversed serial number? + */ + Local6 = 4 + While (Local7) + { + Divide (Local7, 10, Local5, Local7) + SERN[Local6] = (Local5 + 0x30) // Add 0x30 to get numeric ASCII + Local6-- + } + + Arg1[10] = SERN // Serial number +#if CONFIG(EC_USE_LGMR) + Arg1[9] = MBDN // Model number + Arg1[11] = MBCH // Battery type + Arg1[12] = MBMN // OEM information +#else + EBID = 3 + Arg1[9] = EBDN // Model number + EBID = 4 + Arg1[11] = EBCH // Battery type + EBID = 2 + Arg1[12] = EBMN // OEM information +#endif + } + +#if !CONFIG(EC_USE_LGMR) + Release (BMTX) +#endif + Return (Arg1) +} + +/* + * Arg0: Battery number + * Arg1: State information + * Arg2: Power units + * Arg3: Battery Status Package + */ +Method (GBST, 4, NotSerialized) // All on one page +{ +#if !CONFIG(EC_USE_LGMR) + Acquire (BMTX, 0xFFFF) // Due to EC paging, don't run this with another function +#endif + If (Arg1 & 0x02) // BIT1 in "MB0S/EB0S" + { + Local0 = 2 + If (Arg1 & 0x20) // "EB0F" + { + Local0 = 0 + } + } + ElseIf (Arg1 & 0x04) // BIT2 in "MB0S/EB0S" + { + Local0 = 1 + } + Else + { + Local0 = 0 + } + + If (Arg1 & 0x10) // "EB0L" + { + Local0 |= 0x04 + } + + If (Arg1 & 0x01) // "EB0A" + { + /* + * Present rate is a 16bit signed int, positive while charging + * and negative while discharging. + */ +#if CONFIG(EC_USE_LGMR) + Local1 = MBAC + Local2 = MBRC + If (MACS) // Charging +#else + EBID = 0 // We don't know which page was active + Local1 = EBAC + Local2 = EBRC + If (EACS) // Charging +#endif + { + If (Arg1 & 0x20) // "EB0F" + { +#if CONFIG(EC_USE_LGMR) + Local2 = MBFC +#else + Local2 = EBFC +#endif + } + } + + If (Arg2) + { + Local2 *= 10 + } + +#if CONFIG(EC_USE_LGMR) + Local3 = MBVO +#else + Local3 = EBVO +#endif + /* + * The present rate value should be positive unless discharging. If so, + * negate present rate. + */ + If (Local1 >= 0x8000) + { + If (Local0 & 0x01) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = 0 // Full battery, force to 0 + } + } + /* + * If that was not the case, we have an EC bug or inconsistency + * and force the value to 0. + */ + ElseIf ((Local0 & 0x02) == 0) + { + Local1 = 0 + } + + If (Arg2) + { + Local1 *= Local3 + Local1 /= 1000 /* Remainder ignored by vendor */ + } + } + Else + { + Local0 = 0 + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3[0] = Local0 + Arg3[1] = Local1 + Arg3[2] = Local2 + Arg3[3] = Local3 + +#if !CONFIG(EC_USE_LGMR) + Release (BMTX) +#endif + Return (Arg3) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 0) // _UID: Unique ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + + Name (B0IP, Package (0x0D) + { + 1, /* 0x00: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 1, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0, /* 0x05: Design Capacity of Warning */ + 0, /* 0x06: Design Capacity of Low */ + 1, /* 0x07: Capacity Granularity 1 */ + 1, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0 /* 0x0c: OEM Information */ + }) + Name (B0SP, Package (0x04) + { + 0, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + /* Bitwise AND by vendor is lossy? */ + Local1 = EB0A + If (Local1 & 0x40) + { + Local1 = 0 + } + + B0ST = Local1 + If (Local1) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST + Local7 = 20 + While (Local6 && Local7) + { + If (EB0R) + { + Local6 = 0 + } + Else + { + Sleep (500) + Local7-- + } + } + + Return (GBIF (0, B0IP, Local6)) + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP[0]) ^ 1) +#if CONFIG(EC_USE_LGMR) + Local5 = MB0S +#else + Local5 = EB0S +#endif + Return (GBST (0, Local5, Local0, B0SP)) + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl new file mode 100644 index 0000000000..14c5e303d1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/brightness_levels.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (0x67) + { + 80, /* default AC */ + 50, /* default battery */ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 51, + 52, + 53, + 54, + 55, + 56, + 57, + 58, + 59, + 60, + 61, + 62, + 63, + 64, + 65, + 66, + 67, + 68, + 69, + 70, + 71, + 72, + 73, + 74, + 75, + 76, + 77, + 78, + 79, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 88, + 89, + 90, + 91, + 92, + 93, + 94, + 95, + 96, + 97, + 98, + 99, + 100, + }) +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000000..3a22d389b3 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,422 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Global TODO: (externally: Optimus GC6 and GPS) + * - TRPS: This is SMI 0xDD, likely in SmmOemDriver. This SW SMI adds to and executes + * a table of function pointers produced throughout the OEM 'value-add' stack. + * - Arg0 - "SFUN" - is index into "$FNC" pointer table? It's easier to + * correlate *CommonService use: Offset 13 creates TRPS handlers. + * - Known functions: + * - 0x80 calls offset 0 in ACER_BOOT_DEVICE_SERVICE_PROTOCOL_GUID. + * - NB: efiXplorer can miss InstallProtocolInterface() when Interface is local + * - 0x81 toggles Intel Dynamic Acceleration in IA32_MISC_ENABLE MSR. + * - 0x82 does switch on "OSYS" to set EC byte. Suspect this is for OS features. + * (A CVE exists in the vendor code only if it never sets the offset in the buffer.) + * - RBEC/WBEC/MBEC: This is SMI 0xDD, "functions" 0x10, 0x11 and 0x12 in SmmKbcDriver, + * added into SmmCommonService table at its protocol notify. Performs read, write + * and read-modify-write from buffer. We will use ACPI instead. + * - WMI: This is likely SMI 0xD0 in A01WMISmmCallback. This SW SMI likely uses the WMI + * object and consumes the OEM 'value-add' stack for EC and presumably the A01* + * OEM/ODM 'value-add' stack. An SSDT contains the device and EC0 provides "GCMS" + * and "GOTS" method helpers. + * + * Generally, more information is needed. + * TODO: Implement more board features: lid and touchpad trigger wake from S3, + * Fn-Ctrl swap, sticky Fn keys and always-on USB charger. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50) // _GPE: General Purpose Events + Name (\ECOK, 0) +#if CONFIG(EC_USE_LGMR) + Name (LGMR, 0xFE800000) // Static, may depend on EC configuration. Unsure which register. +#endif + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + #define EC_SC_IO 0x66 + #define EC_DATA_IO 0x62 + #include + +#if CONFIG(EC_USE_LGMR) + OperationRegion (ECMB, SystemMemory, LGMR, 0x200) +#endif + OperationRegion (RAM, EmbeddedControl, 0, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, /* EC commands */ + ETID, 8, /* Thermal page selector */ + EBID, 8, /* Battery page selector */ + Offset (0x06), + CMD2, 8, /* param 2: UNUSED */ + CMD1, 8, /* param 1: UNUSED */ + CMD0, 8, /* param 0 to EC command */ + Offset (0x0A), + , 1, + , 1, + Offset (0x10), + EQEN, 1, /* EQ enable */ + ETEE, 1, /* TODO */ + Offset (0x4E), + ISEN, 1, /* TODO */ + Offset (0x4F), + ECTP, 8, /* Touchpad ID */ + Offset (0x51), + , 3, + TPEN, 1, /* Touchpad enable */ + Offset (0x52), + WLEX, 1, /* WLAN present */ + BTEX, 1, /* Bluetooth present */ + EX3G, 1, /* 3G */ + , 3, + RFEX, 1, /* RF present */ +/* + * NOTE: Some reverse engineering, as well as corroborating vendor's hidden SetupUtility + * options with the EC's memory space, suggests that offset 0x55 might be the battery + * threshold + * - TODO: Actually diff changes in modified vendor FW + */ + Offset (0x57), + , 7, + AHKB, 1, /* Hotkey triggered */ + AHKE, 8, /* Hotkey data */ + Offset (0x5C), + Offset (0x5D), + Offset (0x6C), + PWLT, 1, /* NVIDIA GPS: Panel? */ + , 3, + GCON, 1, /* Enter Optimus GC6 */ + Offset (0x70), + , 1, + ELID, 1, /* Lid state */ + , 3, + EACS, 1, /* AC state */ + Offset (0x71), + WLEN, 1, /* WLAN enable */ + BTEN, 1, /* Bluetooth enable */ + , 3, + ISS3, 1, + ISS4, 1, + ISS5, 1, + , 4, + EIDW, 1, /* Device wake */ + Offset (0x74), + , 2, + , 1, + TPEX, 1, /* Touchpad present */ + Offset (0x75), + BLST, 1, /* Bluetooth state */ + LMIB, 1, /* TODO */ + Offset (0x76), + ECSS, 4, /* EC Notify of power state */ + EOSS, 4, /* EC Notify of power state */ + Offset (0x88), /* TODO: Aliased to "EB0S" */ + EB0A, 1, + , 2, + EB0R, 1, + EB0L, 1, + EB0F, 1, + EB0N, 1, + Offset (0x90), + SCPM, 1, /* Set cooling policy */ + Offset (0x92), /* TODO: Aliased to "ETAF" */ + ESSF, 1, + ECTT, 1, + EDTT, 1, + EOSD, 1, /* Trip */ + EVTP, 1, + ECP1, 1, + , 1, + ECP2, 1, + Offset (0xA8), + ES0T, 8, /* Temperature */ + ES1T, 8, /* Temperature */ + Offset (0xD0), + ESP0, 8, /* Passive temp */ + ESC0, 8, /* Critical temp */ + ESP1, 8, /* Passive temp */ + ESC1, 8, /* Critical temp */ + } + /* Aliases several battery registers */ + Field (RAM, ByteAcc, Lock, Preserve) + { + Offset (0x88), + EB0S, 8, /* Battery 0 state */ + } + /* Aliases several thermal registers */ + Field (RAM, ByteAcc, Lock, Preserve) + { + Offset (0x92), + ETAF, 8, + } + +#if CONFIG(EC_USE_LGMR) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x02), + , 1, + MLID, 1, + , 3, + MACS, 1, + Offset (0x06), + MBTP, 8, + Offset (0x08), + MB0S, 8, + Offset (0x20), + MS0T, 8, + MS1T, 8, + MS2T, 8, + MS3T, 8, + MS4T, 8, + MS5T, 8, + Offset (0x53), + MCSS, 1, + MCTT, 1, + MDTT, 1, + MOSD, 1, + MVTP, 1, + Offset (0x54), + MSP0, 8, + MSC0, 8, + MCC0, 8, + MSC1, 8, + } +#endif + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (Arg0 == 3) + { + ECOK = Arg1 // OS can clear region availability + If (Arg1 == 1) // On initialise + { + TINI () + EOSS = 0x05 + /* OSYS retrieved by SMM, Arg3 is unused */ +// TRPS (0x82, 1, 0) + + /* + * Other pages return valid data too, but this seems to be + * the page we are expecting - persistently in ectool dump + * with vendor firmware + * FIXME: Contents of other pages? + */ + ETID = 0x20 + } + } + + /* iGFX RC method call stripped */ + } + + Method (TINI, 0, NotSerialized) + { + If (ECOK) + { + ETAF = 0 + ETEE = 1 + } + Else + { + EC_WRITE (0x92, 0) // ETAF = 0 + MBEC (0x10, 0xFD, 0x02) // ETEE = 1 + } + } + + Name (RFST, 0) /* RF state */ + Method (ECPS, 1, NotSerialized) // _PTS: Prepare To Sleep + { + ECSS = Arg0 + /* OSYS retrieved by SMM */ +// TRPS (0x82, 0x02, Arg0) + If ((Arg0 == 3) || (Arg0 == 4)) + { + RFST = RFEX + } + } + + Method (ECWK, 1, NotSerialized) // _WAK: Wake + { + EQEN = 1 + EOSS = Arg0 + TINI () + Notify (BAT0, 0x81) // Information Change + /* OSYS retrieved by SMM */ +// TRPS (0x82, 0x03, Arg0) + If ((Arg0 == 3) || (Arg0 == 4)) + { + RFEX = RFST + Notify (SLPB, 0x02) // Device Wake + } + /* iGFX RC method call stripped */ + } + + Method (MBEC, 3, Serialized) + { + Local0 = EC_READ (Arg0) + Local0 &= Arg1 + Local0 |= Arg2 + EC_WRITE (Arg0, Local0) + } + + /* Graphical hotkey */ + Method (_Q19, 0, NotSerialized) + { + Debug = "Graphical hotkey display switching not implemented in coreboot!" + } + + /* Increase brightness */ + Method (_Q1C, 0, NotSerialized) + { + ^^^GFX0.INCB () + } + + /* Decrease brightness */ + Method (_Q1D, 0, NotSerialized) + { + ^^^GFX0.DECB () + } + + /* Hotkeys */ + Method (_Q2C, 0, NotSerialized) + { + If (LMIB) + { + If (!AHKB) /* Else, WMI clears its buffer? */ + { + Local1 = AHKE + If ((Local1 > 0) && (Local1 < 0x80)) + { + Debug = "Hotkeys - TODO: Airplane mode?" + /* WMI -> "GCMS" method */ + } + ElseIf ((Local1 > 0x80) && (Local1 < 0xA0)) + { + /* TODO: Not working when called by HID mode. What does WMI do here? */ + TPEN ^= 1 + } + } + } + } + + Method (_Q36, 0, NotSerialized) + { + If (ECOK) + { + EOSD = 1 // Thermal trip + } + Else + { + MBEC (0x92, 0xF7, 0x08) // EOSD = 1 + } + + Sleep (500) + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + Notify (\_TZ.TZ00, 0x80) // Thermal Status Change + } + + Method (_Q3F, 0, NotSerialized) + { + /* Arg3 is unused */ +// TRPS (0x80, 0, 0) + } + + Method (_Q40, 0, NotSerialized) + { + Notify (BAT0, 0x81) // Information Change + } + + Method (_Q41, 0, NotSerialized) + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery status change */ + Method (_Q48, 0, NotSerialized) + { + Notify (BAT0, 0x80) + } + + /* Battery critical? */ + Method (_Q4C, 0, NotSerialized) + { + If (B0ST) + { + Notify (BAT0, 0x80) // Status Change + } + } + + /* AC status change: present */ + Method (_Q50, 0, NotSerialized) + { + Notify (ADP1, 0x80) + } + + /* AC status change: not present */ + Method (_Q51, 0, NotSerialized) + { + Notify (ADP1, 0x80) + } + + /* Lid status change: open */ + Method (_Q52, 0, NotSerialized) + { + Notify (LID0, 0x80) + } + + /* Lid status change: close */ + Method (_Q53, 0, NotSerialized) + { + Notify (LID0, 0x80) + } + + Method (_Q60, 0, NotSerialized) + { + Debug = "EC Query (0x60): WMI" + } + + Method (_Q61, 0, NotSerialized) + { + Debug = "EC Query (0x61): WMI" + } + + Method (_Q62, 0, NotSerialized) + { + Debug = "EC Query (0x62): Optimus GC6 or NVIDIA GPS" + } + + Method (_Q63, 0, NotSerialized) + { + Debug = "EC Query (0x63): Optimus GC6 or NVIDIA GPS" + } + + Method (_Q67, 0, NotSerialized) + { + Debug = "EC Query (0x67): NVIDIA GPS" + } + + Method (_Q68, 0, NotSerialized) + { + Debug = "EC Query (0x68): NVIDIA GPS" + } + + Method (_Q6C, 0, NotSerialized) + { + /* Arg3 is unused */ +// TRPS (0x81, 0, 0) + } + + Method (_Q6D, 0, NotSerialized) + { + /* Arg3 is unused */ +// TRPS (0x81, 1, 0) + } + + #include "ac.asl" + #include "battery.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000000..a3c48b290d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// TODO: Does board actually support DPTF? +#include "thermal.asl" + +Scope (_SB) +{ + Method (MPTS, 1, NotSerialized) // _PTS: Prepare To Sleep + { + ^PCI0.LPCB.EC0.ECPS (Arg0) + /* TBT and DTS not supported, TPM.PTS can be called elsewhere */ + } + + Method (MWAK, 1, Serialized) // _WAK: Wake + { + ^PCI0.LPCB.EC0.ECWK (Arg0) + /* No GPIO expander, 8254 clock-gating and PCIe PME can be performed elsewhere */ + + If ((Arg0 == 3) || (Arg0 == 4)) + { + /* DTS and TBT not supported, iGFX RC variable update stripped */ + LIDS = ^LID0._LID () + Notify (LID0, 0x80) // Status Change + /* TODO: Bus checks? Based on KabylakeOpenBoardPkg - Platform.asl + perhaps not (Warm insertion/removal not possible on mobile */ + } + } + + Method (MS0X, 1, Serialized) // S0ix hook. Porting "GUAM" method - "Global User Absent Mode" + { + If (Arg0 == 0) + { + /* Exit "Connected Standby" */ +#if 1 // EC Notification + ^PCI0.LPCB.EC0.EOSS = 0 +#endif + /* TODO: P-state capping, PL setting? */ + } + ElseIf (Arg0 == 1) + { + /* Enter "Connected Standby" */ +#if 1 // EC Notification + ^PCI0.LPCB.EC0.ECSS = 0x08 +#endif + /* TODO: P-state capping, PL setting? */ + } + } + + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID + Method (_LID, 0, NotSerialized) // _LID: Lid Status + { +#if CONFIG(EC_USE_LGMR) + Return (^^PCI0.LPCB.EC0.MLID) +#else + Return (^^PCI0.LPCB.EC0.ELID) +#endif + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + ^^PCI0.LPCB.EC0.EIDW = Arg0 + } + + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E") /* Sleep Button Device */) // _HID: Hardware ID + Name (_PRW, Package () { 0x0A, 3 }) // _PRW: Power Resources for Wake + } +} + +Scope (_GPE) +{ + /* TODO - Remaining Level-Triggered GPEs: PCH GPE, PCIe PME, TBT, DTS, GFX SCI and tier-2 (RTD3) */ + Method (_L0A, 0, NotSerialized) + { + Notify (\_SB.SLPB, 0x02) // Device Wake + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/thermal.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/thermal.asl new file mode 100644 index 0000000000..7d175a23e5 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/thermal.asl @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_TZ) +{ + Name (CRT0, 0) + Name (PSV0, 0) + ThermalZone (TZ01) + { + Method (_TMP, 0, Serialized) // _TMP: Temperature + { +#if CONFIG(EC_USE_LGMR) + Local0 = \_SB.PCI0.LPCB.EC0.MS0T + Local1 = \_SB.PCI0.LPCB.EC0.MCSS + /* Suppress warning over reading status flag by dummy OR */ + Or (Local1, 1, Local1) + Local2 = \_SB.PCI0.LPCB.EC0.MOSD +#else + Local0 = \_SB.PCI0.LPCB.EC0.ES0T + /* "MCSS": Considering neighbouring bits, likely + "ESSF" in thermals, not "ECSS" in power notifications */ + Local1 = \_SB.PCI0.LPCB.EC0.ESSF + Or (Local1, 1, Local1) + Local2 = \_SB.PCI0.LPCB.EC0.EOSD +#endif + If (Local2) // Thermal trip + { + If (Local0 <= CRT0) + { + Local0 = (CRT0 + 2) + } + } + + Return (C2K (Local0)) + } + + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature + { +#if CONFIG(EC_USE_LGMR) + Local0 = \_SB.PCI0.LPCB.EC0.MSC0 +#else + Local0 = \_SB.PCI0.LPCB.EC0.ESC0 +#endif + If ((Local0 >= 128) || (Local0 < 30)) + { + Local0 = 120 + } + + CRT0 = Local0 + Return (C2K (Local0)) + } + + Method (_SCP, 1, Serialized) // _SCP: Set Cooling Policy + { + If (ECOK) + { + \_SB.PCI0.LPCB.EC0.SCPM = Arg0 + } + Else + { + /* MBEC: Called SMI function 0x12 */ + \_SB.PCI0.LPCB.EC0.MBEC (0x90, 0xFE, Arg0) // SCPM = Arg0 + } + } + + Method (_PSV, 0, Serialized) // _PSV: Passive Temperature + { +#if CONFIG(EC_USE_LGMR) + Local0 = \_SB.PCI0.LPCB.EC0.MSP0 +#else + Local0 = \_SB.PCI0.LPCB.EC0.ESP0 +#endif + If ((Local0 >= 128) || (Local0 < 30)) + { + Local0 = 30 + } + + PSV0 = Local0 + Return (C2K (Local0)) + } + } + + ThermalZone (TZ00) + { + Method (_TMP, 0, Serialized) // _TMP: Temperature + { +#if CONFIG(EC_USE_LGMR) + Local0 = \_SB.PCI0.LPCB.EC0.MS1T +#else + Local0 = \_SB.PCI0.LPCB.EC0.ES1T +#endif + + Return (C2K (Local0)) + } + + Method (_CRT, 0, Serialized) // _CRT: Critical Temperature + { +#if CONFIG(EC_USE_LGMR) + Local0 = \_SB.PCI0.LPCB.EC0.MSC1 +#else + Local0 = \_SB.PCI0.LPCB.EC0.ESC1 +#endif + If ((Local0 >= 128) || (Local0 < 30)) + { + Local0 = 120 + } + + Return (C2K (Local0)) + } + } + + Method (C2K, 1, NotSerialized) + { + Local0 = Arg0 + If ((Local0 >= 127) || (Local0 <= 16)) + { + Local0 = 30 + } + + Return ((Local0 * 10) + 2732) // Celsius to centi-Kelvin + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/board.fmd b/src/mainboard/acer/aspire_vn7_572g/board.fmd new file mode 100644 index 0000000000..44d8a0cd13 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board.fmd @@ -0,0 +1,16 @@ +# NOTE: Use CONSOLE for SMM debugging +FLASH 8M { + SI_ALL 2M { + SI_DESC 0x1000 + SI_ME 0x1ff000 + } + SI_BIOS 6M { + EC 0x20000 + RW_MRC_CACHE 0x10000 + # SMMSTORE requires 64k alignment + SMMSTORE 0x40000 + CONSOLE 0x20000 + FMAP 0x200 + COREBOOT(CBFS) 0x56fe00 + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000000..f16707ed89 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/bootblock.c b/src/mainboard/acer/aspire_vn7_572g/bootblock.c new file mode 100644 index 0000000000..ce150fdce7 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/bootblock.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "include/ec.h" +#include "include/gpio.h" + +#define ADC_3V_10BIT_GRANULARITY_MAX (3005 / 1023) +#define PCB_VER_AD 1 +#define MODEL_ID_AD 3 + +#define DGPU_PRESENT GPP_A20 /* Active low */ +#define DGPU_HOLD_RST GPP_B4 /* Active low */ +#define DGPU_PWR_EN GPP_B21 /* Active low */ + +/* TODO/NB: Detection is still unreliable. Is a wait required? */ +static void board_detect(void) +{ + printk(BIOS_DEBUG, "Mainboard: Detecting board SKU\n"); + + uint16_t data_buffer = read_ec_adc_converter(MODEL_ID_AD); + printk(BIOS_DEBUG, "BoardId (raw) = 0x%x\n", data_buffer); + printk(BIOS_DEBUG, "BoardId: "); + /* Board by max millivoltage range (of 10-bit, 3.005 V ADC) */ + if (data_buffer <= (1374 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_ERR, "Reserved?\n"); + } else if (data_buffer <= (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_DEBUG, "Aspire VN7-792G (Newgate-SLS_dGPU)\n"); + printk(BIOS_CRIT, "WARNING: This board is unsupported!\n"); + printk(BIOS_CRIT, "Damage may result from programming incorrect GPIO table!\n"); + } else if (data_buffer <= (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_DEBUG, "Aspire VN7-592G (Rayleigh-SLS_960M)\n"); + printk(BIOS_CRIT, "WARNING: This board is unsupported!\n"); + printk(BIOS_CRIT, "Damage may result from programming incorrect GPIO table!\n"); + } else { + printk(BIOS_DEBUG, "Aspire VN7-572G (Rayleigh-SL_dGPU)\n"); + } + + data_buffer = read_ec_adc_converter(PCB_VER_AD); + printk(BIOS_DEBUG, "PCB version (raw) = 0x%x\n", data_buffer); + printk(BIOS_DEBUG, "PCB version: "); + /* PCB by max millivoltage range (of 10-bit, 3.005 V ADC) */ + if (data_buffer <= (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_ERR, "Reserved?\n"); + } else if (data_buffer <= (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_DEBUG, "-1\n"); + } else if (data_buffer <= (2493 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_DEBUG, "SC\n"); + } else if (data_buffer <= (2759 / ADC_3V_10BIT_GRANULARITY_MAX)) { + printk(BIOS_DEBUG, "SB\n"); + } else { + printk(BIOS_DEBUG, "SA\n"); + } +} + +static void dgpu_power_on(void) +{ + if (!gpio_get(DGPU_PRESENT)) { + printk(BIOS_DEBUG, "dGPU present, enable power...\n"); + gpio_set(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST# + mdelay(2); + gpio_set(DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN# + mdelay(7); + gpio_set(DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST# + mdelay(30); + } else { + printk(BIOS_DEBUG, "dGPU not present, disable power...\n"); + gpio_set(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST# + gpio_set(DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN# + } +} + +void bootblock_mainboard_init(void) +{ + /* NB: Relocated from _early_init() so that debug logging works. + * However, if we use this to ensure that the user flashed the correct + * (future) variant, this must occur before any GPIOs are programmed. + */ + board_detect(); + dgpu_power_on(); +} + +void bootblock_mainboard_early_init(void) +{ + mainboard_config_stage_gpios(); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/cmos.default b/src/mainboard/acer/aspire_vn7_572g/cmos.default new file mode 100644 index 0000000000..642e3414c3 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +legacy_8254_timer=Disable diff --git a/src/mainboard/acer/aspire_vn7_572g/cmos.layout b/src/mainboard/acer/aspire_vn7_572g/cmos.layout new file mode 100644 index 0000000000..7afff9ccf3 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# start-bit length config config-ID name +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 1 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +392 24 r 0 cmos_post_offset +416 4 e 2 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +420 2 e 3 power_on_after_fail +422 1 e 4 legacy_8254_timer + +# ----------------------------------------------------------------- +# vboot nv area +816 64 r 0 boot_count_offset +880 128 r 0 vbnv + +# ----------------------------------------------------------------- +# coreboot config options: check sums +1008 16 h 0 check_sum +#1024 1024 r 0 upper_bank + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Fallback +1 1 Normal +2 0 Emergency +2 1 Alert +2 2 Critical +2 3 Error +2 4 Warning +2 5 Notice +2 6 Info +2 7 Debug +2 8 Spew +3 0 Disable +3 1 Enable +3 2 Keep +4 0 Disable +4 1 Enable +# ----------------------------------------------------------------- +checksums + +checksum 416 815 1008 diff --git a/src/mainboard/acer/aspire_vn7_572g/data.vbt b/src/mainboard/acer/aspire_vn7_572g/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..b8a0ab84de5bc800fa616eed7b14d20bb3662948 GIT binary patch literal 4608 zcmeHKTWl0%6h1Sv*MDbrXQu?VE7rp$u&uP6EwEry!tAA`OBZ&xTWT9kx`kb}aiOIx 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z5gcX(B=*~D8ObNs^v`9XLG7wobD@u9#W*`Dlv>8&SW9I#A8gQ6wB~|l(^fGmRI%)= zC5uo;d3Nl~Iznh#oQsN4r--xm=^EC;89r1j?HxW?ymu}# z;jNKJyCTiGOf3AbsLceIYac!Vj@{>|MxXnS+n#Ftb4ShH4J>{D;RKmz$S-I4?K*clF-iqvFRO literal 0 HcmV?d00001 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000000..409e3097bc --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,336 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| I2C0 | Touchscreen | + #| I2C1 | Touchpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 128, + .scl_hcnt = 160, + .sda_hold = 30, + } + }, + }" + + # TODO: Drop once CB:55224 is merged + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1025 0x1037 inherit + device ref system_agent on + # Enable "Enhanced Intel SpeedStep" + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activation value to 97C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "3" # TCC of 97C + + register "SaGv" = "SaGv_Enabled" + + # VR Slew rate setting for improving audible noise + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "3" # Fast/16 + register "SlowSlewRateForGt" = "3" # Fast/16 + register "SlowSlewRateForSa" = "0" # Fast/2 + register "FastPkgCRampDisableIa" = "0" + register "FastPkgCRampDisableGt" = "0" + register "FastPkgCRampDisableSa" = "0" + + # PL1, PL2 override 35W, PL4 override 43W + register "power_limits_config" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 35, + .tdp_pl4 = 43, + }" + + # ISL95857 VR + # Send VR specific command for PS4 exit issue + register "SendVrMbxCmd" = "2" + # Send VR mailbox command for IA/GT/SA rails + register "IslVrCmd" = "2" + end + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 150, // T3 + .down_delay_ms = 50, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_on_delay_ms = 1, // T7 + .backlight_off_delay_ms = 200, // T9 + .backlight_pwm_hz = 1000, + }" + + # IGD Displays; LFP and 3*EFP + # FIXME: VBT does not define EFP3, board has no EFP2? + register "gfx" = "{ + .use_spread_spectrum_clock = 1, + .ndid = 4, .did = { 0x0400, 0x0300, 0x0301, 0x0302 } + }" + + register "PrimaryDisplay" = "Display_Switchable" + end + device ref sa_thermal off end + device ref chap off end + device ref gmm off end + device ref south_xhci on + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_17MV, + .tx_emp_enable = USB2_DE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port (right) + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_17MV, + .tx_emp_enable = USB2_DE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port (right) + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_17MV, + .tx_emp_enable = USB2_DE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC_SKIP)" # Touchscreen + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD + register "usb2_ports[8]" = "USB2_PORT_FLEX(OC_SKIP)" # Finger-printer + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right); Capable of OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_UNUSED" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Touchscreen"" + register "type" = "UPC_TYPE_UNUSED" + register "group" = "ACPI_PLD_GROUP(0, 6)" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Webcam"" + register "type" = "UPC_TYPE_UNUSED" + register "group" = "ACPI_PLD_GROUP(0, 7)" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 SD"" + register "type" = "UPC_TYPE_UNUSED" + register "group" = "ACPI_PLD_GROUP(0, 8)" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Finger-printer"" + register "type" = "UPC_TYPE_UNUSED" + register "group" = "ACPI_PLD_GROUP(0, 9)" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 3.3 on end + end + end + end + end + device ref south_xdci off end + device ref thermal on end + device ref cio off end + device ref i2c0 on + chip drivers/i2c/hid + register "generic.name" = ""TPL0"" + register "generic.hid" = ""ELAN2259"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.device_present_gpio" = "GPP_B15" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.name" = ""TPD0"" + register "generic.hid" = ""SYN1B7F"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" +# register "generic.wake" = "GPE0_DW2_16" # FIXME: Use EC's GPE? + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/hid + register "generic.name" = ""TPD1"" + register "generic.hid" = ""ELAN0501"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on end + end + end + device ref heci1 on end + device ref sata on + register "SataMode" = "SATA_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" # HDD; BIT1 in 92h-93h + register "SataPortsEnable[2]" = "1" # ODD; BIT2 in 92h-93h + end + device ref uart2 on end + # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text) + device ref pcie_rp1 on + register "PcieRpEnable[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" + end # PCI Express Port 1 (dGPU; x4) + device ref pcie_rp7 on + register "PcieRpEnable[6]" = "1" + register "PcieRpAdvancedErrorReporting[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "3" + register "PcieRpMaxPayload[6]" = "RpMaxPayload_256" + end # PCI Express Port 7 (NGFF; x2) + device ref pcie_rp9 on + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" + end # PCI Express Port 9 (LAN) + device ref pcie_rp10 on + register "PcieRpEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "2" + register "PcieRpMaxPayload[9]" = "RpMaxPayload_256" + # ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors) + register "pcie_rp_aspm[9]" = "AspmL1" + end # PCI Express Port 10 (WLAN) + # Although vendor's platform NVS area shows SCS is enabled, the SD card reader is actually connected over USB + device ref lpc_espi on + register "lpc_iod" = "0x0010" # 80h-81h; ComB: 2F8h-2FFh (COM 2) + register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_KBC_60_64 + | LPC_IOE_EC_62_66 | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F" # 82h-83h + register "gen3_dec" = "0x00040069" # 8Ch-8Fh; EC (sideband): Port 68h/6Ch + register "gen4_dec" = "0x000c1201" # 90h-93h; EC (index): Port 1200h + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end + device ref p2sb on end + device ref pmc on + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" # 3:0 in pwrmbase+0120h + register "gpe0_dw1" = "GPP_D" # 7:4 in pwrmbase+0120h + register "gpe0_dw2" = "GPP_E" # 11:8 in pwrmbase+0120h + + # Enable S0ix + register "s0ix_enable" = "1" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h + end + device ref hda on + register "DspEnable" = "1" + # PchHdaDspEndpointDmic is only to be returned to reference code + # DXE phase as HOB, used to select blob for NHLT + end + device ref smbus on end + device ref fast_spi on end + device ref tracehub off end + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/die.c b/src/mainboard/acer/aspire_vn7_572g/die.c new file mode 100644 index 0000000000..ed459e7602 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/die.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void die_notify(void) +{ + if (ENV_POSTCAR) { + return; + } + + /* Make SATA LED blink */ + while (1) { + gpio_set(GPP_E8, 1); + mdelay(100); + gpio_set(GPP_E8, 0); + mdelay(100); + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000000..2944688fe1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include + #include + #include + #include + #include + + /* SW SMI ports */ + OperationRegion (DPRT, SystemIO, 0xB2, 2) + Field (DPRT, ByteAcc, Lock, Preserve) + { + SSMP, 8, + SSDP, 8 + } + + Name (ESMI, 0xDD) // NOTE: Could insert into SSDT at runtime + /* Returns a non-zero integer if SMI function failed */ + Method (TRPS, 3, Serialized) + { + Debug = Concatenate ("SMIF: ", ToHexString (Arg0)) + Debug = Concatenate ("Param0: ", ToHexString (Arg1)) + Debug = Concatenate ("Param1: ", ToHexString (Arg2)) + + Local0 = Arg1 + Local0 |= (Arg2 << 4) + Debug = Concatenate ("Local0: ", ToHexString (Local0)) + + SMIF = Arg0 + SSDP = Local0 + /* NOTE: To use a general IO trap, program the range + into a PCR_PSTH_TRPREGx. Otherwise, this is APM. */ + SSMP = ESMI + Return (SMIF) + } + + Device (\_SB.PCI0) + { + #include + #include + #include "acpi/brightness_levels.asl" + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ec.c b/src/mainboard/acer/aspire_vn7_572g/ec.c new file mode 100644 index 0000000000..570e2829f3 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ec.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "include/ec.h" + +/* + * Notes: + * - ACPI "CMDB": Writing to this offset is equivalent to sending commands. + * The CMDx bytes contain the command parameters. + * + * TODO - Implement: + * - Commands: 0x58, 0xE1 and 0xE2 + * - 0x51, 0x52: EC flash write? + * - ACPI CMDB: 0x63 and 0x64, 0xC7 + * - 0x0B: Flash lock/write (Set offset 0x0B?) + * - Key/recovery detection? + * + * Vendor's protocols: + * - Only read and write are used. + * - Query, ACPI "CMDB" processing and command 58 are unused. + * - Equivalent KbcPeim is an unused PPI. + * + * NB: Also look for potential EC library + */ + +#define EC_INDEX_IO_PORT 0x1200 +#define EC_INDEX_IO_HIGH_ADDR_PORT (EC_INDEX_IO_PORT + 1) +#define EC_INDEX_IO_LOW_ADDR_PORT (EC_INDEX_IO_PORT + 2) +#define EC_INDEX_IO_DATA_PORT (EC_INDEX_IO_PORT + 3) + +uint8_t ec_cmd_90_read(uint8_t addr) +{ + /* EC ports: 0x62/0x66 */ + send_ec_command(0x90); + send_ec_data(addr); + return recv_ec_data(); +} + +void ec_cmd_91_write(uint8_t addr, uint8_t data) +{ + /* EC ports: 0x62/0x66 */ + send_ec_command(0x91); + send_ec_data(addr); + send_ec_data(data); +} + +uint8_t ec_cmd_94_query(void) +{ + send_ec_command(0x94); + return recv_ec_data(); +} + +uint8_t ec_idx_read(uint16_t addr) +{ + outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); + outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT); + return inb(EC_INDEX_IO_DATA_PORT); +} + +void ec_idx_write(uint16_t addr, uint8_t data) +{ + outb((uint8_t) (addr >> 8), EC_INDEX_IO_HIGH_ADDR_PORT); + outb((uint8_t) addr, EC_INDEX_IO_LOW_ADDR_PORT); + outb(data, EC_INDEX_IO_DATA_PORT); +} + +/* TODO: Check if ADC is valid. Are there 4, or actually 8 ADCs? */ +uint16_t read_ec_adc_converter(uint8_t adc) +{ + uint8_t adc_converters_enabled; // Contains some ADCs and some DACs + uint8_t idx_data; + uint16_t adc_data; + + /* Backup enabled ADCs */ + adc_converters_enabled = ec_idx_read(0xff15); // ADDAEN + + /* Enable desired ADC in bitmask (not enabled by EC FW, not used by vendor FW) */ + ec_idx_write(0xff15, adc_converters_enabled | ((1 << adc) & 0xf)); // ADDAEN + + /* Sample the desired ADC in binary field; OR the start bit */ + ec_idx_write(0xff18, ((adc << 1) & 0xf) | 1); // ADCTRL + + /* Read the desired ADC */ + idx_data = ec_idx_read(0xff19); // ADCDAT + adc_data = (idx_data << 2); + /* Lower 2-bits of 10-bit ADC are in high bits of next register */ + idx_data = ec_idx_read(0xff1a); // ECIF + adc_data |= ((idx_data & 0xc0) >> 6); + + /* Restore enabled ADCs */ + ec_idx_write(0xff15, adc_converters_enabled); // ADDAEN + + return adc_data; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads b/src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads new file mode 100644 index 0000000000..fc8bacc933 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-only + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.c b/src/mainboard/acer/aspire_vn7_572g/gpio.c new file mode 100644 index 0000000000..ebb954f3a8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.c @@ -0,0 +1,374 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "include/gpio.h" + +/* + * TODO: Vendor configures many NC pads as _TERM_GPO. Why? + * - On direction: Are some of these comments illusory? At least some pads + * are bidirectional on the other side of the GPIO. + */ +/* NB: Do not reconfigure pads used by Optimus, their assertion state may be lost */ + +/* + * TODO: Newgate-SLS and Rayleigh-SLS have PCH-H and use the same ProgramGPIOPei module. + * The GPIO tables retrieved from PCDs are ignored. However, progress on those SKUs + * is held up because the final table passed to function similar to RC's + * GpioConfigureSklPch() is neither, but a zero-assigned variable. The code may be + * computing and dereferencing address pointers from a blob of internal data. + */ + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + // RCIN# <= H_RCIN# + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + // LAD0 (ESPI_IO0) <=> LPC_AD_CPU_P0 + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + // LAD1 (ESPI_IO1) <=> LPC_AD_CPU_P1 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + // LAD2 (ESPI_IO2) <=> LPC_AD_CPU_P2 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + // LAD3 (ESPI_IO3) <=> LPC_AD_CPU_P3 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + // LFRAME# (ESPI_CS#) => LPC_FRAME#_CPU + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + // SERIRQ <=> INT_SERIRQ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + // PIRQA# = PIRQA# + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + // CLKRUN# <= PM_CLKRUN#_EC + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + // CLKOUT_LPC0 (ESPI_CLK) <= LPC_CLK_CPU_P0 + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + // CLKOUT_LPC1 <= LPC_CLK_CPU_P1 + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + // GPIO (PME#) // NC + PAD_CFG_TERM_GPO(GPP_A11, 1, DN_20K, DEEP), + // GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <= GC6_FB_EN + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + // SUSWARN#/SUSPWRDNACK = PM_SUSACK# + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + // SUS_STAT# (ESPI_RESET#) => PM_SUS_STAT# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + // SUS_ACK# = PM_SUSACK# + PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), + // GPIO (SD_1P8_SEL) // NC + PAD_NC(GPP_A16, DN_20K), + // GPIO (SD_PWR_EN#/ISH_GP7) // NC + PAD_NC(GPP_A17, DN_20K), + // GPIO (ISH_GP0) => GSENSOR_INT# + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI), + // GPIO (ISH_GP1) // NC + PAD_NC(GPP_A19, DN_20K), + // GPIO (ISH_GP3) // NC + PAD_NC(GPP_A21, DN_20K), + // GPIO (ISH_GP4) <= GPU_EVENT# + PAD_CFG_GPO(GPP_A22, 1, DEEP), + // GPIO (ISH_GP5) // NC + PAD_NC(GPP_A23, DN_20K), + + /* ------- GPIO Group GPP_B ------- */ + // CORE_VID0 // V0.85A_VID0 + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + // CORE_VID1 // V0.85A_VID1 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + // GPIO (CPU_GP2) <= TP_IN# + // TODO: APIC-routed pads don't have host owners? + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP), + // SRCCLKREQ0# <= PEG_CLKREQ_CPU# + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + // SRCCLKREQ1# <= LAN_CLKREQ_CPU# + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + // SRCCLKREQ2# <= WLAN_CLKREQ_CPU# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + // SRCCLKREQ3# <= MSATA_CLKREQ_CPU# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + // SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT") + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + // SRCCLKREQ5# // SRCCLKREQ5# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + // GPIO (EXT_PWR_GATE#) = EXT_PWR_GATE# + PAD_CFG_TERM_GPO(GPP_B11, 1, DN_20K, DEEP), + // GPIO (SLP_S0#) // NC + PAD_CFG_TERM_GPO(GPP_B12, 1, DN_20K, DEEP), + // PLTRST# => PLT_RST# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + // GPIO (SPKR) => HDA_SPKR (Strap - Top Swap Override) + PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), + // GPIO (GSPI0_CS#) = TOUCH_DET# + PAD_CFG_GPO(GPP_B15, 0, DEEP), + // GPIO (GSPI0_CLK) // NC + PAD_CFG_GPO(GPP_B16, 0, DEEP), + // GPIO (GSPI0_MISO) // NC ("Remove TBT") + PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT), + // GPIO (GSPI0_MOSI) => GPP_B18/GSPI0_MOSI (Strap - No reboot) + PAD_CFG_TERM_GPO(GPP_B18, 1, DN_20K, DEEP), + // GPIO (GSPI1_CS#) => RTC_DET# + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), + // GPIO (GSPI1_CLK) <= PSW_CLR# + PAD_CFG_GPI_TRIG_OWN(GPP_B20, DN_20K, DEEP, OFF, ACPI), + // GPIO (GSPI1_MOSI) => GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap) + PAD_CFG_TERM_GPO(GPP_B22, 1, DN_20K, DEEP), + // GPIO (SML1ALERT#/PCHHOT#) => GPP_B23 (Strap) + PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + // SMBCLK <= SMB_CLK + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // SMBDATA = SMB_DATA + PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), + // GPIO (SMBALERT#) => GPP_C2 (Strap - TLS Confidentiality) + PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), + // GPIO (SML0CLK) // NC + PAD_CFG_TERM_GPO(GPP_C3, 1, DN_20K, DEEP), + // GPIO (SML0DATA) // NC + PAD_CFG_TERM_GPO(GPP_C4, 1, DN_20K, DEEP), + // GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC) + PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, DEEP), + // RESERVED (SML1CLK) <=> SML1_CLK (KBC) + // RESERVED (SML1DATA) <=> SML1_DATA (KBC) + // GPIO (UART0_RXD) // NC + PAD_CFG_TERM_GPO(GPP_C8, 1, DN_20K, DEEP), + // GPIO (UART0_TXD) // NC + PAD_CFG_TERM_GPO(GPP_C9, 1, DN_20K, DEEP), + // GPIO (UART0_RTS#) // NC + PAD_CFG_TERM_GPO(GPP_C10, 1, DN_20K, DEEP), + // GPIO (UART0_CTS#) // NC + PAD_CFG_TERM_GPO(GPP_C11, 1, DN_20K, DEEP), + // GPIO (UART1_RXD/ISH_UART1_RXD) // NC + PAD_NC(GPP_C12, DN_20K), + // GPIO (UART1_TXD/ISH_UART1_TXD) // NC + PAD_NC(GPP_C13, DN_20K), + // GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC + PAD_NC(GPP_C14, DN_20K), + // GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC + PAD_NC(GPP_C15, DN_20K), + // I2C0_SDA <=> I2C0_DATA_CPU (Touch Panel) + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + // I2C0_SCL <=> I2C0_CLK_CPU (Touch Panel) + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + // I2C1_SDA <=> I2C1_DATA_CPU (Touch Pad) + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + // I2C1_SCL <=> I2C1_CLK_CPU (Touch Pad) + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + // UART2_RXD = LPSS_UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD = LPSS_UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // UART2_RTS# = LPSS_UART2_RTS# + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + // UART2_CTS# = LPSS_UART2_CTS# + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_D ------- */ + // GPIO (SPI1_CS#) // NC + PAD_CFG_TERM_GPO(GPP_D0, 1, DN_20K, DEEP), + // GPIO (SPI1_CLK) // NC + PAD_CFG_TERM_GPO(GPP_D1, 1, DN_20K, DEEP), + // SPI1_MISO // NC + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + // SPI1_MOSI // NC + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + // GPIO (FLASHTRIG) // NC + PAD_CFG_TERM_GPO(GPP_D4, 1, DN_20K, DEEP), + // GPIO (ISH_I2C0_SDA) // NC + PAD_NC(GPP_D5, DN_20K), + // GPIO (ISH_I2C0_SCL) // NC + PAD_NC(GPP_D6, DN_20K), + // GPIO (ISH_I2C1_SDA) // NC + PAD_NC(GPP_D7, DN_20K), + // GPIO (ISH_I2C1_SCL) // NC + PAD_NC(GPP_D8, DN_20K), + // GPIO // NC + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), + // GPIO => TOUCH_S_RST# + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), + // GPIO // NC + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), + // GPIO // NC ("Remove TBT") + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), + // GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC + PAD_CFG_TERM_GPO(GPP_D13, 1, DN_20K, DEEP), + // GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC + PAD_CFG_TERM_GPO(GPP_D14, 1, DN_20K, DEEP), + // GPIO (ISH_UART0_RTS#) // NC + PAD_CFG_TERM_GPO(GPP_D15, 1, DN_20K, DEEP), + // GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC + PAD_CFG_TERM_GPO(GPP_D16, 1, DN_20K, DEEP), + // GPIO (DMIC_CLK1) // NC + PAD_NC(GPP_D17, DN_20K), + // GPIO (DMIC_DATA1) // NC + PAD_NC(GPP_D18, DN_20K), + // DMIC_CLK0 => DMIC_CLK_CON_R + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + // DMIC_DATA0 => DMIC_PCH_DATA + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + // SPI1_IO2 // NC + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + // SPI1_IO3 // NC + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + // GPIO (I2S_MCLK) // NC + PAD_NC(GPP_D23, DN_20K), + + /* ------- GPIO Group GPP_E ------- */ + // SATAXPCIE0 (SATAGP0) = SATAGP0 + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + // SATAXPCIE1 (SATAGP1) // NC + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + // SATAXPCIE2 (SATAGP2) = SATAGP2 + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + // GPIO (CPU_GP0) // NC + PAD_CFG_GPO(GPP_E3, 1, DEEP), + // GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH") + PAD_CFG_TERM_GPO(GPP_E4, 1, DN_20K, DEEP), + // GPIO (DEVSLP1) // NC + PAD_CFG_TERM_GPO(GPP_E5, 1, DN_20K, DEEP), + // GPIO (DEVSLP2) // NC + PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, DEEP), + // GPIO (CPU_GP1) <= TOUCH_INT# + PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, DEEP), + // SATALED# = SATA_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + // USB2_OC0# = USB_OC# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + // USB2_OC1# // USB_OC# + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + // USB2_OC2# // USB_OC# + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + // USB2_OC3# // USB_OC# + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + // DDPB_HPD0 <= DDI1_HDMI_HPD_CPU + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + // DDPC_HPD1 // NC ("Remove HPD") + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + // GPIO (DDPD_HPD2) <= EC_SMI# + // FIXME: Vendor configures as _TERM_GPO. Why? + PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, LEVEL, INVERT), + // GPIO (DDPE_HPD3) <= EC_SCI# + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), + // EDP_HPD <= eDP_HPD_CPU + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + // DDPB_CTRLCLK <=> DDI1_HDMI_CLK_CPU + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + // DDPB_CTRLDATA <=> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detected) + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + // DDPC_CTRLCLK // NC + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + // DDPC_CTRLDATA => DDPC_CDA (Strap - Display Port C Detected) + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), + // GPIO // NC + // TODO: Vendor configures as _GPIO_BIDIRECT. Why? + PAD_NC(GPP_E22, NONE), + // GPIO => DDPD_CDA (Strap - Display Port D Detected) + PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + // GPIO (BATLOW#) = BATLOW + PAD_CFG_TERM_GPO(GPD0, 1, DN_20K, PWROK), + // ACPRESENT <= AC_PRESENT + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + // GPIO (LAN_WAKE#) = GPD2/LAN_WAKE# + PAD_CFG_TERM_GPO(GPD2, 1, DN_20K, PWROK), + // PWRBTN# <= PM_PWRBTN# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + // SLP_S3# => PM_SLP_S3# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + // SLP_S4# => PM_SLP_S4# + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + // SLP_A# // NC + PAD_CFG_NF(GPD6, DN_20K, PWROK, NF1), + // GPIO (RSVD#AT15) // NC + PAD_CFG_TERM_GPO(GPD7, 1, DN_20K, PWROK), + // SUSCLK => SUS_CLK_CPU + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + // SLP_WLAN# // NC + PAD_CFG_NF(GPD9, DN_20K, PWROK, NF1), + // SLP_S5# // NC + PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1), + // GPIO (LANPHYPC) // NC + PAD_CFG_TERM_GPO(GPD11, 1, DN_20K, PWROK), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + // GPIO (I2S2_SCLK) // NC + PAD_NC(GPP_F0, DN_20K), + // GPIO (I2S2_SFRM) // NC + PAD_NC(GPP_F1, DN_20K), + // GPIO (I2S2_TXD) // NC + PAD_NC(GPP_F2, DN_20K), + // GPIO (I2S2_RXD) // NC + PAD_NC(GPP_F3, DN_20K), + // GPIO (I2C2_SDA) // NC + PAD_NC(GPP_F4, DN_20K), + // GPIO (I2C2_SCL) // NC + PAD_NC(GPP_F5, DN_20K), + // GPIO (I2C3_SDA) // NC + PAD_NC(GPP_F6, DN_20K), + // GPIO (I2C3_SCL) // NC + PAD_NC(GPP_F7, DN_20K), + // GPIO (I2C4_SDA) // NC + PAD_CFG_TERM_GPO(GPP_F8, 1, DN_20K, DEEP), + // GPIO (I2C4_SCL) // NC + PAD_CFG_TERM_GPO(GPP_F9, 1, DN_20K, DEEP), + // GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC + PAD_NC(GPP_F10, DN_20K), + // GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC + PAD_NC(GPP_F11, DN_20K), + // GPIO (EMMC_CMD) // NC + PAD_NC(GPP_F12, DN_20K), + // GPIO (EMMC_DATA0) // NC + PAD_NC(GPP_F13, DN_20K), + // GPIO (EMMC_DATA1) // NC + PAD_NC(GPP_F14, DN_20K), + // GPIO (EMMC_DATA2) // NC + PAD_NC(GPP_F15, DN_20K), + // GPIO (EMMC_DATA3) // NC + PAD_NC(GPP_F16, DN_20K), + // GPIO (EMMC_DATA4) // NC + PAD_NC(GPP_F17, DN_20K), + // GPIO (EMMC_DATA5) // NC + PAD_NC(GPP_F18, DN_20K), + // GPIO (EMMC_DATA6) // NC + PAD_NC(GPP_F19, DN_20K), + // GPIO (EMMC_DATA7) // NC + PAD_NC(GPP_F20, DN_20K), + // GPIO (EMMC_RCLK) // NC + PAD_NC(GPP_F21, DN_20K), + // GPIO (EMMC_CLK) // NC + PAD_NC(GPP_F22, DN_20K), + // GPIO // NC + PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP), + + /* ------- GPIO Group GPP_G ------- */ + // GPIO (SD_CMD) // NC + PAD_NC(GPP_G0, DN_20K), + // GPIO (SD_DATA0) // NC + PAD_NC(GPP_G1, DN_20K), + // GPIO (SD_DATA1) // NC + PAD_NC(GPP_G2, DN_20K), + // GPIO (SD_DATA2) // NC + PAD_NC(GPP_G3, DN_20K), + // GPIO (SD_DATA3) // NC + // TODO: Vendor configures as _GPO. Why? + PAD_NC(GPP_G4, NONE), + // GPIO (SD_CD#) // NC + PAD_NC(GPP_G5, DN_20K), + // GPIO (SD_CLK) // NC + PAD_NC(GPP_G6, DN_20K), + // GPIO (SD_WP) // NC + PAD_NC(GPP_G7, DN_20K), +}; + +void mainboard_config_stage_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio_early.c b/src/mainboard/acer/aspire_vn7_572g/gpio_early.c new file mode 100644 index 0000000000..ad66661273 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio_early.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "include/gpio.h" + +/* Early pad configuration */ +static const struct pad_config early_gpio_table[] = { + // GPIO (ISH_GP2) = DGPU_PRESENT + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, ACPI), + // GPIO (VRALERT#) <= DGPU_PWROK + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, ACPI), + // GPIO (CPU_GP3) => DGPU_HOLD_RST# + PAD_CFG_GPO(GPP_B4, 1, DEEP), + // GPIO (GSPI1_MISO) => DGPU_PWR_EN# + PAD_CFG_TERM_GPO(GPP_B21, 1, DN_20K, DEEP), + // UART2_RXD = LPSS_UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD = LPSS_UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // SATALED# = SATA_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +}; + +void mainboard_config_stage_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000000..20197d1d22 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Convert to macros */ + +#include + +const u32 cim_verb_data[] = { + /* --- Codec #0 --- */ + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 20, /* Number of jacks (NID entries) */ + + /* Codec Address: Bits 31:28 */ + /* Node ID: Bits 27:20 */ + /* Verb ID: Bits 19:8 / Bits 19:16 */ + /* Payload: Bits 7:0 / Bits 15:0 */ + + /* Reset Codec */ + AZALIA_RESET(0x1), + /* NOTE: Corrected the table in vendor FW, programming subsystem after reset */ + /* HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x10251037), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x12, 0x411111c0), + AZALIA_PIN_CFG(0, 0x14, 0x90172120), /* Speaker */ + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x02211030), /* Headphone */ + + /* + * See data blob in "InstallPchHdaVerbTablePei" of vendor firmware + * (some appear in https://github.com/torvalds/linux/blob/master/sound/pci/hda/patch_realtek.c). + * - Largely coefficient programming (undocumented): Select coeff; write data + * - Also programs speaker amplifier gain + * - Sets speaker output + * NOTE: NID 0x20 holds the "Realtek Defined Hidden registers" + */ + 0x02050038, /* Set coeff idx: 0x38 */ + 0x02048981, /* Set processing coeff: 0x8981 */ + 0x02050045, /* Set coeff idx: 0x45 */ + 0x0204c489, /* Set processing coeff: 0xc489 */ + + 0x02050037, /* Set coeff idx: 0x37 */ + 0x02044a05, /* Set processing coeff: 0x4a05 */ + 0x05750003, /* Set coeff idx on NID 0x57?: 0x3 */ + 0x057486a6, /* Set processing coeff on NID 0x57?: 0x86a6 */ + + 0x02050046, /* Set coeff idx: 0x46 */ + 0x02040004, /* Set processing coeff: 0x4 */ + 0x0205001b, /* Set coeff idx: 0x1b */ + 0x02040a0b, /* Set processing coeff: 0xa0b */ + + 0x02050008, /* Set coeff idx: 0x8 */ + 0x02046a0c, /* Set processing coeff: 0x6a0c */ + 0x02050009, /* Set coeff idx: 0x9 */ + 0x0204e003, /* Set processing coeff: 0xe003 */ + + 0x0205000a, /* Set coeff idx: 0xa */ + 0x02047770, /* Set processing coeff: 0x7770 */ + 0x02050040, /* Set coeff idx: 0x40 */ + 0x02049800, /* Set processing coeff: 0x9800 */ + + 0x02050010, /* Set coeff idx: 0x10 */ + 0x02040e20, /* Set processing coeff: 0xe20 */ + 0x0205000d, /* Set coeff idx: 0xd */ + 0x02042801, /* Set processing coeff: 0x2801 */ + + 0x0143b000, /* Sends unknown verb 0x3B to speaker */ + 0x0143b000, /* Repeated for units? */ + 0x01470740, /* Set widget control on speaker: Output; VrefEn: Hi-Z (disabled) */ + 0x01470740, /* Repeated for units? */ + + 0x01470740, /* Repeated for units? */ + 0x01470740, /* Repeated for units? */ + 0x02050010, /* Set coeff idx: 0x10 */ + 0x02040f20, /* Set processing coeff: 0xf20 */ + + /* --- Codec #2 --- */ + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 5, /* Number of jacks (NID entries) */ + + /* Codec Address: Bits 31:28 */ + /* Node ID: Bits 27:20 */ + /* Verb ID: Bits 19:8 */ + /* Payload: Bits 7:0 */ + + /* NOTE: Corrected the table in vendor FW, using codec address 0x2, not 0x0 */ + + /* Enable the third converter and pin first */ + 0x20878101, + 0x20878101, + 0x20878101, + 0x20878101, + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + + /* Disable the third converter and third pin */ + 0x20878100, + 0x20878100, + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/include/ec.h b/src/mainboard/acer/aspire_vn7_572g/include/ec.h new file mode 100644 index 0000000000..49651decfb --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/include/ec.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +uint8_t ec_cmd_90_read(uint8_t addr); +void ec_cmd_91_write(uint8_t addr, uint8_t data); +uint8_t ec_cmd_94_query(void); +uint8_t ec_idx_read(uint16_t addr); +void ec_idx_write(uint16_t addr, uint8_t data); +/* TODO: Check if ADC is valid. */ +uint16_t read_ec_adc_converter(uint8_t adc); + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/include/gpio.h b/src/mainboard/acer/aspire_vn7_572g/include/gpio.h new file mode 100644 index 0000000000..ed8518ed64 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/include/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_config_stage_gpios(void); + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000000..eba9e9856e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "include/ec.h" +#include "include/gpio.h" + +static unsigned long mainboard_write_acpi_tables( + const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + if (!nhlt) { + return start_addr; + } + + /* Override subsystem ID */ + nhlt->subsystem_id = 0x10251037; + + /* 1 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 1) != 0) { + printk(BIOS_ERR, "Couldn't add 1CH DMIC array.\n"); + } + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2) != 0) { + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + } + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) { + acpi_add_table(rsdp, (void *)start_addr); + } + + return end_addr; +} + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + + if (CONFIG(INCLUDE_NHLT_BLOBS)) { + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + } +} + +/* Update the EC's clock. */ +static void ec_send_time(void) +{ + struct rtc_time time; + uint8_t ec_time_byte; + + rtc_get(&time); + + /* RTC time could be negative (before 2016) */ + int32_t ec_time = ((time.year << 26) + (time.mon << 22) + (time.mday << 17) + + (time.hour << 12) + (time.min << 6) + (time.sec) + /* 16 years */ + - 0x40000000); + + printk(BIOS_DEBUG, "EC: reporting present time 0x%x\n", ec_time); + send_ec_command(0xE0); + for (int i = 0; i < 4; i++) { + /* Shift bytes */ + ec_time_byte = (uint8_t) (ec_time >> (i * 8)); + printk(BIOS_DEBUG, "EC: Sending 0x%x (iteration %d)\n", ec_time_byte, i); + send_ec_data(ec_time_byte); + } + + printk(BIOS_DEBUG, "EC: response 0x%x\n", recv_ec_data()); +} + +static void ec_requests_time(void) +{ + /* This is executed as protocol notify in vendor's RtKbcDriver + when *CommonService protocol is installed. Effectively, + this code could execute from the entrypoint */ + uint8_t dat = ec_cmd_90_read(0x79); + if (dat & 1) { + ec_send_time(); + } +} + +/* + * Init from vendor's PeiOemModule. KbcPeim does not appear to be used + * (It implements commands also found in RtKbcDriver and SmmKbcDriver). + * + * Mostly, this puts the system back to sleep if the lid is closed during + * an S3 resume. + */ +static void ec_init(void) +{ + /* This is called via a "$FNC" in a PeiOemModule pointer table, + with "$DPX" on SiInit */ + outb(0x5A, 0x6C); // 6Ch is the EC sideband port + if (acpi_is_wakeup_s3()) { + /* "MLID" in LGMR-based memory map is equivalent to "ELID" in EC-based + memory map. Vendor firmware accesses through LGMR; remapped + - ec_cmd* function calls will not remapped */ + uint8_t power_state = ec_read(0x70); + if (!(power_state & 2)) { // Lid is closed + uint8_t out_data = ec_cmd_90_read(0x0A); + if (!(out_data & 2)) { + ec_cmd_91_write(0x0A, out_data | 2); + } + + /* Clear below events and go back to sleep */ + /* Clear ABase PM1_STS - RW/1C set bits */ + pmc_clear_pm1_status(); + /* Clear ABase GPE0_STS[127:96] - RW/1C set bits */ + uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); + outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); + /* Clear xHCI PM_CS[PME_Status] - RW/1C - + and disable xHCI PM_CS[PME_En] */ + pci_update_config16(PCH_DEV_XHCI, 0x74, ~0x100, 0x8000); + + /* Enter S3 sleep */ + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S3 << SLP_TYP_SHIFT)); + halt(); + } + } +} + +static void mainboard_init(void *chip_info) +{ + mainboard_config_stage_gpios(); + /* Notify EC */ + ec_init(); + /* Program the same 64K range of EC memory as vendor FW + - Open unconditionally, user can select whether ACPI uses LGMR */ + lpc_open_mmio_window(0xFE800000, 0x10000); + /* EC is notified of platform resets with UEFI firmware, but coreboot + does not offer this service to boards */ + ec_requests_time(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000000..74e1438118 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + + /* TODO: Search vendor FW for Dq/Dqs */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + const uint16_t rcomp_resistors[3] = { 121, 80, 100 }; + /* Also the default values in FSP binary */ + const uint16_t rcomp_targets[5] = { 100, 40, 40, 23, 40 }; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + + mem_cfg->CaVrefConfig = 2; + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; + + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[1] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[1] = 1; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/smihandler.c b/src/mainboard/acer/aspire_vn7_572g/smihandler.c new file mode 100644 index 0000000000..88ec10d190 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/smihandler.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* + * TODO: Perform RE of protocols in vendor firmware: + * - gEfiSmmSxDispatch2ProtocolGuid + * - gEfiSmmPowerButtonDispatch2ProtocolGuid + * + * However, note that first glance suggests that no handlers + * will be very interesting and that gEfiSmmGpiDispatch2ProtocolGuid + * was unused (as I recall). + * + * Also, consider gEfiSmmIoTrapDispatch2ProtocolGuid, but + * this is less likely. + */ + +/* Keep in sync with dsdt.asl; could insert into SSDT at runtime */ +#define APM_CNT_BOARD_SMI 0xDD + +/* Toggle TURBO_MODE_DISABLE bit in IA32_MISC_ENABLE MSR + when requested by EC. */ +static void toggle_turbo_disable(uint8_t function_parameter_0) +{ + if (function_parameter_0 == 1) { + printk(BIOS_DEBUG, "EC: Enabling Intel Turbo Mode\n"); + msr_unset(IA32_MISC_ENABLE, 0x4000000000); + } else if (function_parameter_0 == 0) { + printk(BIOS_DEBUG, "EC: Disabling Intel Turbo Mode\n"); + msr_set(IA32_MISC_ENABLE, 0x4000000000); + } +} + +/* Set WiFi and BT enable bits in EC RAM. */ +static void enable_rf_by_capability(void) +{ + /* FIXME: We're not tracking (driver) 'capabilities' at the moment (must we?), + so we just enable WiFi and BT here. If this was tracked, then + bits may be cleared here */ + uint8_t rf_register = ec_read(0x71); + ec_write(0x71, rf_register | 0x03); +} + +/* Set OS capability bits in EC RAM. */ +static void handle_acpi_osys(void) +{ + uint8_t os_support; + + /* TODO: Add _OSI method support to coreboot and make this work */ + printk(BIOS_DEBUG, "GNVS.OSYS = %d\n", gnvs->unused_was_osys); + switch (gnvs->unused_was_osys) { + /* Linux */ + case 1000: + os_support = 64; + break; + /* Windows versions by year */ + case 2009: + os_support = 3; + break; + case 2012: + os_support = 4; + break; + case 2013: + os_support = 5; + break; + case 2015: + os_support = 6; + break; + /* Operating system unknown */ + default: + printk(BIOS_DEBUG, "GNVS.OSYS not supported!\n"); + printk(BIOS_DEBUG, "No capabilities!\n"); + os_support = 0; + break; + } + + ec_write(0x5C, os_support); +} + +/* Handles EC's _REG, _PTS and _WAK methods. + Partially involves setting EC RAM offsets based on GNVS.OSYS - OS capabilities? */ +static void handle_acpi_wake_event( + uint8_t function_parameter_0, uint8_t function_parameter_1) +{ + switch (function_parameter_0) { + case 1: + printk(BIOS_DEBUG, "EC: Called for _REG method - OS initialise\n"); + enable_rf_by_capability(); + handle_acpi_osys(); + // NOTE: Not handling (driver) 'capabilities' + break; + case 2: + printk(BIOS_DEBUG, "EC: Called for _PTS method - Entering sleep\n"); + // NOTE: Not saving (driver) 'capabilities' + // NOTE: Not saving and restoring EC RAM offset 0x4F + break; + case 3: + printk(BIOS_DEBUG, "EC: Called for _WAK method - Sleep resume\n"); + enable_rf_by_capability(); + handle_acpi_osys(); + // NOTE: Not saving and restoring EC RAM offset 0x4F + break; + default: + printk(BIOS_DEBUG, "function_parameter_0 is invalid!\n"); + break; + } +} + +/* TODO: Reverse engineer 0x80 function and implement if necessary */ +static void ec_smi_handler(uint8_t smif) +{ + uint8_t smm_data_port; + uint8_t function_parameter_0; + uint8_t function_parameter_1; + + /* Parameters encoded onto SMI data port because PRMx NVS are not present + - Callers must only use 4 bits per argument + - _PTS and _WAK are required to call in spec-compliant way */ + smm_data_port = inb(APM_STS); + function_parameter_0 = smm_data_port & ~0xF0; + function_parameter_1 = smm_data_port >> 4; + + printk(BIOS_DEBUG, "Function 0x%x(0x%x, 0x%x) called\n", + smif, function_parameter_0, function_parameter_1); + switch (smif) { + case 0x80: + printk(BIOS_WARNING, "Function 0x80 is unimplemented!\n"); + printk(BIOS_DEBUG, "Function calls offset 0 in ACER_BOOT_DEVICE_SERVICE_PROTOCOL_GUID\n"); + break; + case 0x81: + toggle_turbo_disable(function_parameter_0); + break; + case 0x82: + handle_acpi_wake_event(function_parameter_0, function_parameter_1); + break; + default: + /* Not handled */ + printk(BIOS_DEBUG, "Requested function is unknown!\n"); + return; + } + + /* + * gnvs->smif: + * - On success, the handler returns 0 + * - On failure, the handler returns a value != 0 + */ + gnvs->smif = 0; +} + +int mainboard_smi_apmc(u8 data) +{ + /* TODO: Continue SmmKbcDriver RE of common service registration and confirm */ + switch (data) { + case APM_CNT_BOARD_SMI: + if (gnvs) { + ec_smi_handler(gnvs->smif); + } + break; + case APM_CNT_ACPI_ENABLE: /* Events generate SCIs for OS */ + /* use 0x68/0x6C to prevent races with userspace */ + ec_set_ports(0x6C, 0x68); + /* discard all events */ + ec_clear_out_queue(); + /* Tests at runtime show this re-enables charging and battery reporting */ + send_ec_command(0xE9); /* Vendor implements using ACPI "CMDB" register" */ + send_ec_data(0x81); + /* TODO: Set touchpad GPP owner to ACPI? */ + break; + case APM_CNT_ACPI_DISABLE: /* Events generate SMIs for SMM */ + /* use 0x68/0x6C to prevent races with userspace */ + ec_set_ports(0x6C, 0x68); + /* discard all events */ + ec_clear_out_queue(); + /* Tests at runtime show this disables charging and battery reporting */ + send_ec_command(0xE9); /* Vendor implements using ACPI "CMDB" register" */ + send_ec_data(0x80); + /* TODO: Set touchpad GPP owner to GPIO? */ + break; + default: + break; + } + return 0; +} diff --git a/src/mainboard/acer/g43t-am3/Kconfig b/src/mainboard/acer/g43t-am3/Kconfig index 1d4fd53f97..dd2bf3f9f4 100644 --- a/src/mainboard/acer/g43t-am3/Kconfig +++ b/src/mainboard/acer/g43t-am3/Kconfig @@ -2,6 +2,9 @@ if BOARD_ACER_G43T_AM3 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_LGA775 diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index bc91630bf6..f87046acb3 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -12,7 +11,7 @@ #include #include #include -#include +#include #include "gpio.h" #include "mainboard.h" diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig new file mode 100644 index 0000000000..31bb069003 --- /dev/null +++ b/src/mainboard/amd/chausie/Kconfig @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AMD_CHAUSIE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select SOC_AMD_SABRINA + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select AMD_SOC_CONSOLE_UART + select MAINBOARD_HAS_CHROMEOS + +config FMDFILE + default "src/mainboard/amd/chausie/chromeos.fmd" if CHROMEOS + default "src/mainboard/amd/chausie/board.fmd" + +config MAINBOARD_DIR + default "amd/chausie" + +config MAINBOARD_PART_NUMBER + default "CHAUSIE" + +config AMD_FWM_POSITION_INDEX + int + default 3 if CHROMEOS + help + TODO: might need to be adapted for better placement of files in cbfs + +config CHAUSIE_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config CHAUSIE_MCHP_SIG_FILE + string + depends on CHAUSIE_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/chausie/EC_chausie_sig.bin" + help + The EC sig blob is the first 4kBytes of the firmware image. + The first 4 bytes form a pointer (with CRC) to where the EC firmware + is located + +config CHAUSIE_MCHP_FW_FILE + string + depends on CHAUSIE_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/chausie/EC_chausie.bin" + help + The EC firmware blob is at the CHAUSIE_MCHP_FW_OFFSET offset of the + firmware image. + +config CHAUSIE_MCHP_FW_OFFSET + hex + depends on CHAUSIE_HAVE_MCHP_FW + default 0xB80000 + help + The EC firmware blob defaults to the 4MByte offset of the firmware + image. If this offset needs to change, a new signature block must be + generated with the updated offset. + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 3 # Quad IO (1-1-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_CHAUSIE diff --git a/src/mainboard/amd/chausie/Kconfig.name b/src/mainboard/amd/chausie/Kconfig.name new file mode 100644 index 0000000000..d9d8d400ed --- /dev/null +++ b/src/mainboard/amd/chausie/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_CHAUSIE + bool "Chausie" diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc new file mode 100644 index 0000000000..e4944002f1 --- /dev/null +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c + +romstage-y += port_descriptors.c + +ramstage-y += chromeos.c +ramstage-y += gpio.c + +#TODO: add APCB binaries +#APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin +#APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin + +ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_CHAUSIE_MCHP_SIG_FILE) --fill-upward + +# calculate the absolute position from the config offset +CHAUSIE_EC_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(CONFIG_ROM_SIZE)) $(CONFIG_CHAUSIE_MCHP_FW_OFFSET) 1) + +cbfs-files-y += apu/ecfw +apu/ecfw-file := $(CONFIG_CHAUSIE_MCHP_FW_FILE) +apu/ecfw-position := $(CHAUSIE_EC_POSITION) +apu/ecfw-type := raw + +else +files_added:: warn_no_mchp +endif # CONFIG_CHAUSIE_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the Microchip EC FW.\n" + printf "Do not flash this image. Your Chausie's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/chausie/board.fmd b/src/mainboard/amd/chausie/board.fmd new file mode 100644 index 0000000000..ec87bbaddb --- /dev/null +++ b/src/mainboard/amd/chausie/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 4K + RW_MRC_CACHE 96K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/chausie/board_info.txt b/src/mainboard/amd/chausie/board_info.txt new file mode 100644 index 0000000000..b351b8e696 --- /dev/null +++ b/src/mainboard/amd/chausie/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/chausie/bootblock.c b/src/mainboard/amd/chausie/bootblock.c new file mode 100644 index 0000000000..f768f3f778 --- /dev/null +++ b/src/mainboard/amd/chausie/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); +} diff --git a/src/mainboard/amd/chausie/chromeos.c b/src/mainboard/amd/chausie/chromeos.c new file mode 100644 index 0000000000..062fdad290 --- /dev/null +++ b/src/mainboard/amd/chausie/chromeos.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = {}; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Chausie doesn't have a write protect pin */ + return 0; +} + +static const struct cros_gpio cros_gpios[] = { + /* No ChromeOS GPIOs */ +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/amd/chausie/chromeos.fmd b/src/mainboard/amd/chausie/chromeos.fmd new file mode 100644 index 0000000000..e913e398bf --- /dev/null +++ b/src/mainboard/amd/chausie/chromeos.fmd @@ -0,0 +1,34 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + EC 4K + RW_MRC_CACHE(PRESERVE) 96K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb new file mode 100644 index 0000000000..1d4d9dae1e --- /dev/null +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/sabrina + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + register "pspp_policy" = "DXIO_PSPP_BALANCED" + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_0 on end # NVMe + device ref gpp_bridge_1 on end + device ref gpp_bridge_2 on end # WWAN + device ref gpp_bridge_3 on end # LAN + device ref gpp_bridge_4 on end # WLAN + device ref gpp_bridge_5 on end + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + +end diff --git a/src/mainboard/amd/chausie/dsdt.asl b/src/mainboard/amd/chausie/dsdt.asl new file mode 100644 index 0000000000..7b8982a645 --- /dev/null +++ b/src/mainboard/amd/chausie/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include + + #include +} diff --git a/src/mainboard/amd/chausie/early_gpio.c b/src/mainboard/amd/chausie/early_gpio.c new file mode 100644 index 0000000000..0929c7b8d1 --- /dev/null +++ b/src/mainboard/amd/chausie/early_gpio.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* TPM IRQ */ + PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), + /* Enable UART 2 */ + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/chausie/gpio.c b/src/mainboard/amd/chausie/gpio.c new file mode 100644 index 0000000000..4411bea294 --- /dev/null +++ b/src/mainboard/amd/chausie/gpio.c @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* INT_CLKREQ */ + PAD_GPI(GPIO_3, PULL_UP), + /* UART_WAKE_L_M2_APU */ + PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), + /* MPM_EVENT_L, input or OD output */ + PAD_GPI(GPIO_5, PULL_UP), + /* TPNL_INT_L */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* EC SCI */ + PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW), + /* TPAD_INT_L */ + PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), + /* FP_IRQ_INT */ + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + /* Unused */ + PAD_NC(GPIO_10), + /* HP_MIC_DET_L */ + PAD_GPI(GPIO_11, PULL_UP), + /* ALIGN_FLAG_MU_L */ + PAD_GPO(GPIO_12, HIGH), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* WAKE_ON_WAN_L */ + PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), + /* PCIE_WLAN_WAKE_L */ + PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_NONE), + /* PCIE_LOM_WAKE_L */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* GPIO_28: Not available */ + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* GPIO_31: Not available */ + /* LPC_RST_L */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), + /* GPIO_33 - GPIO_39: Not available */ + /* USB2_HDR_P0/1_SMI */ + PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), + /* GPIO_41: Not available */ + /* SSD_AUX_RESET_L */ + PAD_GPO(GPIO_42, HIGH), + /* GPIO_43 - GPIO_66: Not available */ + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* GPIO_70 - GPIO_73: Not available */ + /* SPI1_CS1_L */ + PAD_NF(GPIO_74, SPI1_CS1_L, PULL_NONE), + /* GPIO_75: Not available */ + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* SPI1_CS1_L */ + PAD_NF(GPIO_78, SPI1_CS2_L, PULL_NONE), + /* GPIO_79: Not available */ + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* GPIO_82 - GPIO_83: Not available */ + /* FANIN0 */ + PAD_NF(GPIO_84, FANIN0, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* GPIO_86 - GPIO_88: Not available */ + /* I2S CODEC INT */ + PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), + /* ALERT_L_M2_SSD0 */ + PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), + /* CLK_REQ0_L */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_112: Not available */ + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_129: Not available */ + /* TPM IRQ */ + PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW), + /* CLK_REQ3_L */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), + /* GPIO_132 - GPIO_135: Not available */ + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* GPIO_137: Not available */ + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* ALERT_L_M2_WWAN */ + PAD_SCI(GPIO_139, PULL_UP, EDGE_LOW), + /* UART0_CTS_L */ + PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_RTS_L */ + PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* CAM_FW_UPDATE_WP_L */ + PAD_GPO(GPIO_144, LOW), + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/chausie/gpio.h b/src/mainboard/amd/chausie/gpio.h new file mode 100644 index 0000000000..04c98c50df --- /dev/null +++ b/src/mainboard/amd/chausie/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/chausie/mainboard.c b/src/mainboard/amd/chausie/mainboard.c new file mode 100644 index 0000000000..2966b554b3 --- /dev/null +++ b/src/mainboard/amd/chausie/mainboard.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "gpio.h" + +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} chausie_fch[] = { + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(chausie_fch); i++) { + entry = chausie_fch + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +static void pirq_setup(void) +{ + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_program_gpios(); +} + +static void mainboard_enable(struct device *dev) +{ + init_tables(); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c new file mode 100644 index 0000000000..46afa77599 --- /dev/null +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = { + { /* MXM */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 1, + .device_number = 2, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .gpio_group_id = GPIO_40, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* DT */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 2, + .function_number = 2, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4_GFX, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* WWAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 2, + .function_number = 3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* LAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 6, + .end_logical_lane = 6, + .device_number = 2, + .function_number = 4, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 7, + .end_logical_lane = 7, + .device_number = 2, + .function_number = 5, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TB */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 6, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SATA */ + .engine_type = SATA_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .channel_type = SATA_CHANNEL_LONG, + } +}; + +static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } +}; + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + *dxio_descs = chausie_czn_dxio_descriptors; + *dxio_num = ARRAY_SIZE(chausie_czn_dxio_descriptors); + *ddi_descs = chausie_czn_ddi_descriptors; + *ddi_num = ARRAY_SIZE(chausie_czn_ddi_descriptors); +} diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index 0febf2971c..46b6707b53 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -34,4 +34,12 @@ config STONEYRIDGE_LEGACY_FREE bool default y +if !EM100 +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz +endif + endif # BOARD_AMD_GARDENIA diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 210a05b720..d86313fd2f 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #define DIMMS_PER_CHANNEL 2 diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index a480f362ed..0543c31ec2 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include "../gpio.h" diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index 3e9500dbe8..d01bdfd112 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -3,6 +3,8 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include + const struct soc_amd_gpio *early_gpio_table(size_t *size); const struct soc_amd_gpio *gpio_table(size_t *size); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index ae72b33e43..b9c2eaf1c3 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include +#include #include #include "gpio.h" diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 846dae9552..d364649207 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c index c73e047933..14f89d182e 100644 --- a/src/mainboard/amd/majolica/chromeos.c +++ b/src/mainboard/amd/majolica/chromeos.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 7bb0db1e33..9758e9cf2d 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -14,10 +14,10 @@ chip soc/amd/cezanne }" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" register "s0ix_enable" = "true" diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 2dd2d57241..199cf4702e 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -2,12 +2,10 @@ #include #include -#include #include #include #include #include -#include /* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -38,23 +36,25 @@ static const struct fch_irq_routing { uint8_t pic_irq_num; uint8_t apic_irq_num; } majolica_fch[] = { - { PIRQ_A, PIRQ_NC, PIRQ_NC }, - { PIRQ_B, PIRQ_NC, PIRQ_NC }, - { PIRQ_C, PIRQ_NC, PIRQ_NC }, - { PIRQ_D, PIRQ_NC, PIRQ_NC }, - { PIRQ_E, PIRQ_NC, PIRQ_NC }, - { PIRQ_F, PIRQ_NC, PIRQ_NC }, - { PIRQ_G, PIRQ_NC, PIRQ_NC }, - { PIRQ_H, PIRQ_NC, PIRQ_NC }, + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, - { PIRQ_GPIO, 7, 7 }, - { PIRQ_I2C2, PIRQ_NC, PIRQ_NC }, - { PIRQ_I2C3, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, { PIRQ_UART0, 4, 4 }, { PIRQ_UART1, 3, 3 }, @@ -95,8 +95,6 @@ static void mainboard_enable(struct device *dev) init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/majolica/port_descriptors.c b/src/mainboard/amd/majolica/port_descriptors.c index 9c771f4742..4cbccf626a 100644 --- a/src/mainboard/amd/majolica/port_descriptors.c +++ b/src/mainboard/amd/majolica/port_descriptors.c @@ -3,6 +3,7 @@ #include #include #include +#include static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = { { /* MXM */ @@ -92,7 +93,7 @@ static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = { } }; -static const fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { +static fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = { { /* DDI0 - DP */ .connector_type = DDI_DP, .aux_index = DDI_AUX1, @@ -124,6 +125,9 @@ void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + majolica_czn_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; + *dxio_descs = majolica_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(majolica_czn_dxio_descriptors); *ddi_descs = majolica_czn_ddi_descriptors; diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index a66db78772..ccea7c7ee4 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -10,7 +9,7 @@ #include #include #include -#include +#include #include "gpio.h" /* TODO: recheck IRQ tables */ diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index f605b3f138..3ebc0c1cd5 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 96f8696ba8..3c6449753b 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -58,4 +58,12 @@ config HWM_PORT If changed, make sure fan_init.c IO window setting. The HWM (Hardware Monitor) is used for fan control within padmelon. +if !EM100 +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz +endif + endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index 7ea46f8359..e65f750cd5 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #define DIMMS_PER_CHANNEL 1 diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index c93ef52582..f1b6822f8b 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c index 9c18d30a23..0de2c0a190 100644 --- a/src/mainboard/amd/padmelon/gpio.c +++ b/src/mainboard/amd/padmelon/gpio.c @@ -2,6 +2,7 @@ #include #include +#include #include #include "gpio.h" diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index 51b0f90c41..3b643ed3fe 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include #include #include +#include #include #include diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2651ecf748..9c4ba53ca4 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 11d2af183b..e7ca602a90 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 313a71564f..e290133d92 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index bdc66ad349..7c31d216c2 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 81541f37f5..9850a9056f 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl index 7216d33a21..f8c7b2e23a 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -37,7 +37,7 @@ Device (MBRS) CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM) And (\_SB.PCI0.RLAR, 0x03FF, Local1) - Increment (Local1) + Local1++ If (LGreater (Local1, 0x40)) { ShiftLeft (Local1, 0x1A, LELM) @@ -49,10 +49,10 @@ Device (MBRS) CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) - Decrement (Local1) + Local1-- If (LGreater (Local1, 0x10)) { - Subtract (Local1, 0x0F, Local1) + Local1 -= 0x0F Store (ShiftLeft (Local1, 0x14), MEM2) Store (0x01000000, MS00) Store (MS00, MS01) diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0ba808d255..400a5d7092 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Method (_CRS, 0, NotSerialized) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (IO_APIC_ADDR, 0x01, MEMH) - Subtract (IO_APIC_ADDR, MEML, LENM) + MEMH = IO_APIC_ADDR - 1 + LENM = IO_APIC_ADDR - MEML Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index 20400c38ee..9b16070167 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -113,7 +113,7 @@ Device (ICH0) CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL) Store (PBAR, Local0) - If ( Land(Local0, 0x01) ) + If (Local0 && 1) { And (Local0, 0xFFFE, Local0) Store (Local0, IOA1) @@ -128,7 +128,7 @@ Device (ICH0) CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL) Store (GBAR, Local0) - If ( Land(Local0, 0x01) ) { + If (Local0 && 1) { And (Local0, 0xFFFE, Local0) Store (Local0, IOS1) Store (Local0, IOS2) diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl index 98890322c3..d3ae8676cb 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -144,7 +144,7 @@ Method (MLED, 1, NotSerialized) Store (0x00, LED1) } - If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02))) + If (LEqual (Arg0, 0x01) || LEqual (Arg0, 0x02)) { Store (0x01, LED1) } @@ -154,7 +154,7 @@ Method (MLED, 1, NotSerialized) Store (0x02, LED1) } - If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05))) + If (LEqual (Arg0, 0x04) || LEqual (Arg0, 0x05)) { Store (0x03, LED1) } diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 8f7573a9c7..6ea033ec32 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x00fc0701" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" device pci 16.0 on # Management Engine Interface 1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 93d37dcac0..0f7d0a87d5 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 75efb9e69c..25b157d8a3 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 6b0f809807..68255f9946 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3a55f9e1f3..7f84adb5b7 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "asrock/h110m" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index aed9184e99..a45127c0b3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -101,9 +101,6 @@ chip soc/intel/skylake device pci 15.3 off end # I2C #3 device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 9b2193b587..18a1eb8471 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -455,7 +455,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), }; -/* Early pad configuration in romstage */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig b/src/mainboard/asrock/h77pro4-m/Kconfig new file mode 100644 index 0000000000..50bf86c9db --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_H77PRO4_M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asrock/h77pro4-m" + +config MAINBOARD_PART_NUMBER + default "H77 Pro4-M" + +endif diff --git a/src/mainboard/asrock/h77pro4-m/Kconfig.name b/src/mainboard/asrock/h77pro4-m/Kconfig.name new file mode 100644 index 0000000000..03873b96f0 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H77PRO4_M + bool "H77 Pro4-M" diff --git a/src/mainboard/asrock/h77pro4-m/Makefile.inc b/src/mainboard/asrock/h77pro4-m/Makefile.inc new file mode 100644 index 0000000000..a0d1155a9a --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h77pro4-m/acpi/ec.asl b/src/mainboard/asrock/h77pro4-m/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asrock/h77pro4-m/acpi/platform.asl b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl new file mode 100644 index 0000000000..146be6592e --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/h77pro4-m/acpi/superio.asl b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/asrock/h77pro4-m/board_info.txt b/src/mainboard/asrock/h77pro4-m/board_info.txt new file mode 100644 index 0000000000..5f86088de5 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asrock/h77pro4-m/cmos.default b/src/mainboard/asrock/h77pro4-m/cmos.default new file mode 100644 index 0000000000..23386fb6d3 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M +cpu_fan_tach_src=CPU_FAN1 diff --git a/src/mainboard/asrock/h77pro4-m/cmos.layout b/src/mainboard/asrock/h77pro4-m/cmos.layout new file mode 100644 index 0000000000..ac88ee9621 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/cmos.layout @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: mainboard-specific +421 2 e 7 cpu_fan_tach_src + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# cpu_fan_header (select which header provides the tachometer +# signal to the Super I/O on its CPUFANIN input) +7 0 None +7 1 CPU_FAN1 +7 2 CPU_FAN2 +7 3 Both + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asrock/h77pro4-m/data.vbt b/src/mainboard/asrock/h77pro4-m/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..52a8268f3359e08c0d58d63f107cfa8b82687e94 GIT binary patch literal 3902 zcmdT{U2GIp6h5;v`*(MSZl@KtYiUlAz_#>fy42b@7}>%uKS?QN z`3WRqM{NXSVpd}i5zR&uf;#(->nKVu&$55aNR&#PC2&B*=Q^XA7Z9Cq^RP z$#>7aXV3lS-gD2ncXn+in#R;h^>WXF!e zRG~O|u#m@8=7k9Av=WOR+B22M(L;N;7m9tTbCET6b$4v+MpQO-c6E1#m98*iSm{%G z`@&C4EH*eWwmBJ3MAGrGQ5>7VSUeR;r3N=g6E9+NVr)1bji(1=5;K-Euy5vQanG*Z z2Qf6zLM)2XPJ~@(Oc@9E6=ymyGBt%0y3GNcC>$sh4;S(s64MDTfk)r~I49I_z;S_159+`$pcgw$0}iPTpu!cy;B(8sW024f$e}|wK#So^%YgV@x}H{m z)pr?Ps<7JlJNc*#gho)p-95d1{c1EeG(3_>PNXy0tuJY>z5d2r5bl(K7Rzx|t>6?$ z@*z0JJK#9q3mb$o{Oa;R*eyehkRj|Q9CI@`PI#B_5#b!+BH=5-*MuJk*9bQVzY)O0 zfD!5mO@t63Oz0;J5t4+hggjxI;5r0%Dh>_YhO0ErlC`D;zX0#FfOf{xpRx4bo3z7J zm?eFdG?X@~O2zGlyOr+(P^oyH)n}j*1Gxoa7SpgL6NcpZq}5N8)a|lXzf$q$s2ir| z(beoTpm==Ti|;HnYcxqK8&IDw=bTxs%f+Hm>wW`=v-og>#gWy|_;kC{lo1C@xHeVKv=&KH_{{&n? zv*YfsDj$^p*Lrvy&) zm}CK^6;6$VqAD|Wrl#p!=aH-9!F6i(R8=$lysB)!5LVSoRZSoSJ+r*&OtELy3C1B$ zEv{sQC$(JqH3A?ugrEU#)6)PY4#9lp>BcahHtt?4sIxrzEiBMUxZu9Uov3>}Tl%`} zl}e?t2d;Rv5?)>H_vF@?qnhk!LIHB>fxmoB%lp8;=fy9)@;6@gy%%qLWs$L!4Evcp z%2<}+t4uC2cADWOCSPXkCx#B6T<>E|K8*R~jF07f_@+-jm&5K)%owG!))FfGYDB{n1BNl88@v5S(_dQ;FG zS2?Yg;*+AlQxs_zvkuXaw>UpZXU%%LGnOu&0>=s_r`s$nH5T2V>dOoomGVTwerk`r--3d9|b@R&XREliDl=Ujd(cSQeGIJTcadD zT(!u+gHLahC+#pOt?GPkF0TZ}&1+Gg15e?oGyKDtG#Dh4!HG6jaXkp-B(73KWk4Tg z_<=7`KGGaCcdro-56?|UpBC8P+pcEY@9hN-H3kEHM!A;Hixw4f8r0?d{#t#MIS26T zEz#yp^}jLOupe9_{`HVOKQd2WwU4B(JW$%6fVYOonQ>sS1(Nh%w~adqzwmzohUI;T literal 0 HcmV?d00001 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb new file mode 100644 index 0000000000..86468c1e54 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x1849 0x0100 + end + device pci 01.0 on end # PEG - slot "PCIE1" + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0102 + end + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane + subsystemid 0x1849 0x1e18 + end + device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane + subsystemid 0x1849 0x1e16 + end + device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + subsystemid 0x1849 0x1e1e + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e4a + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT1 + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIO base + io 0x60 = 0x0 + irq 0xf0 = 0x3e # + GPIO1 direction + irq 0xf1 = 0xde # + GPIO1 value + end + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + irq 0xe1 = 0x0c # + GPIO2 value + end + device pnp 2e.309 on # GPIO3 + irq 0xe4 = 0xf7 # + GPIO3 direction + irq 0xe5 = 0x08 # + GPIO3 value + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + enable 3VSBSW# + irq 0xf0 = 0x20 # + pin 70 = 3VSBSW + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-Pull or Open-drain + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep Sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA (AHCI) + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/h77pro4-m/dsdt.asl b/src/mainboard/asrock/h77pro4-m/dsdt.asl new file mode 100644 index 0000000000..33cd0e5d0b --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c new file mode 100644 index 0000000000..48024cba5c --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define GPIO6789_DEV PNP_DEV(0x2e, NCT6776_GPIO6789_V) + +/* As defined in cmos.layout */ +enum cpu_fan_tach_src { + CPU_FAN_HEADER_NONE, + CPU_FAN_HEADER_1, + CPU_FAN_HEADER_2, + CPU_FAN_HEADER_BOTH +}; + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, +}; + +/* + * The tachometer signal that goes to CPUFANIN of the Super I/O is set via + * GPIOs. + * + * When GP77 (register E1h[7]) is '0', CPU_FAN1 is connected. + * When GP76 (register E1h[6]) is '0', CPU_FAN2 is connected. + * When both are '0' and both fans are connected, wrong readings will + * be reported. + */ +static u8 get_cpufanin_gpio_config(void) +{ + switch (get_uint_option("cpu_fan_tach_src", CPU_FAN_HEADER_1)) { + case CPU_FAN_HEADER_NONE: + return 0xff; + case CPU_FAN_HEADER_1: + default: + return 0x7f; + case CPU_FAN_HEADER_2: + return 0xbf; + case CPU_FAN_HEADER_BOTH: + return 0x3f; + } +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Configure Super I/O pins */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x08); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + + /* GP77 and GP76 are outputs. They set the tachometer input on CPUFANIN. */ + pnp_set_logical_device(GPIO6789_DEV); + pnp_write_config(GPIO6789_DEV, 0xe0, 0x3f); + pnp_write_config(GPIO6789_DEV, 0xe1, get_cpufanin_gpio_config()); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads new file mode 100644 index 0000000000..b05255dea2 --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D connector + HDMI3, -- HDMI connector + Analog, -- D-Sub connector + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h77pro4-m/gpio.c b/src/mainboard/asrock/h77pro4-m/gpio.c new file mode 100644 index 0000000000..84f4564fff --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c new file mode 100644 index 0000000000..51133e7c7c --- /dev/null +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 7b9df5824c..0da310c4d0 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -2,6 +2,9 @@ if BOARD_ASROCK_H81M_HDS +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index cc9a04fad6..3573d690be 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 56510d50bf..e2abfb4246 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 26bbd0e414..800364062a 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 20085d1d7f..9d2cb16251 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,5 +1,8 @@ if BOARD_ASUS_AM1I_A +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index e10591032f..0c00e6362f 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 2d1de391e0..37bce31c80 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig index eeec4e7882..48e4220e78 100644 --- a/src/mainboard/asus/h61-series/Kconfig +++ b/src/mainboard/asus/h61-series/Kconfig @@ -14,6 +14,9 @@ config BOARD_ASUS_H61_SERIES if BOARD_ASUS_H61_SERIES +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config MAINBOARD_DIR default "asus/h61-series" diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9f7f63e5f3..7ee69e41a2 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -18,6 +18,7 @@ chip northbridge/intel/i440bx # Northbridge device pnp 3f0.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 0 end device pnp 3f0.2 on # COM1 io 0x60 = 0x3f8 @@ -34,6 +35,9 @@ chip northbridge/intel/i440bx # Northbridge irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 3f0.7 on # GPIO 1 + io 0x60 = 0 + io 0x62 = 0 + irq 0x70 = 0 end device pnp 3f0.8 on # GPIO 2 end diff --git a/src/mainboard/asus/p5qpl-am/Kconfig b/src/mainboard/asus/p5qpl-am/Kconfig index 2359e324d8..100f5918e7 100644 --- a/src/mainboard/asus/p5qpl-am/Kconfig +++ b/src/mainboard/asus/p5qpl-am/Kconfig @@ -2,6 +2,9 @@ if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_LGA775 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 4ecb4b4d38..7968345698 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -24,6 +24,7 @@ config VARIANT_DIR default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V + default "p8z77-m" if BOARD_ASUS_P8Z77_M config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -31,6 +32,7 @@ config MAINBOARD_PART_NUMBER default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V + default "P8Z77-M" if BOARD_ASUS_P8Z77_M config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index b4d89481c2..822f5d4d45 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -38,3 +38,9 @@ config BOARD_ASUS_P8Z77_V select MAINBOARD_USES_IFD_GBE_REGION select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT + +config BOARD_ASUS_P8Z77_M + bool "P8Z77-M" + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6779D diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt new file mode 100644 index 0000000000..96774748a7 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8Z77M/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default new file mode 100644 index 0000000000..3cc854d6c3 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Disable +sata_mode=AHCI +#usb3_xxxx options are only used with MRC blob, ignored otherwise +usb3_mode=Enable +usb3_drv=Enable +usb3_streams=Enable diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout new file mode 100644 index 0000000000..3053b8d913 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout @@ -0,0 +1,136 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 2 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# usb3_mode +# Controls how the motherboard's USB3 ports act at boot time +421 2 e 8 usb3_mode + +# usb3_drv +# Load (or not) pre-OS xHCI USB3 bios driver +# +423 1 e 1 usb3_drv + +# usb3_streams +# Streams can provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +424 1 e 1 usb3_streams + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible +6 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 1024M + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto + +# ----------------------------------------------------------------- +# +# +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/data.vbt 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+ +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + {1, 2, 0}, /* Port 0: USB3 front internal header, top */ + {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 2, 1}, /* Port 2: USB3 rear, top */ + {1, 2, 1}, /* Port 3: USB3 rear, bottom */ + {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ + {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ + {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ + {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ + {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ + {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ + {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ + {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* + * TODO: Put PCIe root port 7 (00:1c.6) into subtractive decode and have it accept I/O + * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 + * bridge to this port, to receive POST codes. + */ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei) +{ + uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */ + uint16_t usbcfg[16][3] = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, + {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, + {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} + }; + + memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr)); + + pei->gbe_enable = 0; /* Board uses no Intel GbE but a RTL8111F */ + pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */ + + memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg)); + + /* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */ + pei->ddr3lv_support = 1; + /* + * PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability! + */ + pei->pcie_init = 1; + /* + * 4 bit switch mask. 0=not switchable, 1=switchable + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf + */ + pei->usb3.hs_port_switch_mask = 0xf; + /* + * USB 3 mode settings. + * These are obtained from option table then bit masked to keep within range. + */ + /* + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver + * and reboots, it will keep the USB3.0 speed + */ + pei->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3; + /* 1=Load xHCI pre-OS drv */ + pei->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1; + /* + * 0=Don't use xHCI streams for better compatibility + * 1=use xHCI streams for better speed + */ + pei->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1; +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads new file mode 100644 index 0000000000..1bf8323f1b --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D port + HDMI3, -- HDMI port + Analog, -- VGA port + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c new file mode 100644 index 0000000000..c1012e3f82 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/gpio.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c new file mode 100644 index 0000000000..5830331a7c --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, 0x90430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, 0x01446140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb new file mode 100644 index 0000000000..9659ed14a3 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -0,0 +1,81 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + + device pci 1c.0 on end # PCIe Port #1 (PCIe x4 slot) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 (PCIe x1 slot) + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 (PCI slot via ASM1083) + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 # COM1 address + irq 0x70 = 4 + # Below are global config settings to replicate OEM + drq 0x26 = 0x10 # Before accessing CR10/11/13/14, CR26:4 must be set to 1 + drq 0x13 = 0xff # IRQs 0-15 active low + drq 0x14 = 0xff + drq 0x1a = 0x02 + drq 0x1b = 0x60 + drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + drq 0xf0 = 0x82 # KBC 12Mhz/A20 speed/sw KBRST + drq 0x2a = 0x48 # UART A, PS/2 mouse, PS/2 keyboard + drq 0x22 = 0xd7 # Power down UART B and LPT + end + device pnp 2e.6 off end # CIR + device pnp 2e.8 on # WDT1 + drq 0xe0 = 0x7f # GP07 output + drq 0xe1 = 0x80 # GP07 high + end + device pnp 2e.a on # ACPI + drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility + drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME + end + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0x290 # HWM address + io 0x62 = 0 # SB-TSI address (not used) + drq 0xe4 = 0xf9 # GP50, GP52, PWROK# + drq 0xf0 = 0x3e # Enable all fan input debouncers + end + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD select + drq 0xe4 = 0xfc # GP50,GP51 PP + drq 0xe6 = 0x7f # GP7x OD + end + device pnp 2e.9 off end # GPIO 8 + device pnp 2e.308 on end # GPIO by I/O + device pnp 2e.108 on end # GPIO 0 + device pnp 2e.109 on end # GPIO 1 + device pnp 2e.209 on # GPIO 2 + drq 0xe0 = 0xbf # GP26 output + drq 0xe1 = 0xc0 # GP26 high + end + device pnp 2e.309 off end # GPIO 3 + device pnp 2e.409 off end # GPIO 4 + device pnp 2e.509 on # GPIO 5 + drq 0xf4 = 0xfc # GP50,GP51 output + drq 0xf5 = 0xc4 # GP50,GP51 low + end + device pnp 2e.609 off end # GPIO 6 + device pnp 2e.709 off end # GPIO 7 + end + end + end + end +end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 8653cec2c5..374ff9dd71 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -1,4 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#include #include #include #include @@ -85,11 +87,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index 9dcf2b7376..0162547431 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3 device pci 1c.1 on end # PCIe Port 2 RTL8111F diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 2b8da6e3f4..cd1645123e 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -2,6 +2,9 @@ if BOARD_ODE_E20XX +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index 9baf0eaf67..b183970a25 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c index f605b3f138..3ebc0c1cd5 100644 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ b/src/mainboard/biostar/a68n_5200/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 5b70202bd1..a3d6e32b96 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -2,6 +2,9 @@ if BOARD_BIOSTAR_AM1ML +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index a7ef85bc4a..d300a45ce4 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index db4d1acb75..d22f57419a 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -60,9 +60,7 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end device ref thermal on end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref sata on register "SataSalpSupport" = "0" # Ports diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index b3b1a1cfad..6979615953 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -37,7 +37,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx register "gen3_dec" = "0x000406f1" register "gen4_dec" = "0x000c06a1" register "gpi7_routing" = "2" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" # Intense PC SATA portmap: # Port 0: internal 2.5" bay diff --git a/src/mainboard/dell/optiplex_9010/Kconfig b/src/mainboard/dell/optiplex_9010/Kconfig index ac0912b367..01edd243fc 100644 --- a/src/mainboard/dell/optiplex_9010/Kconfig +++ b/src/mainboard/dell/optiplex_9010/Kconfig @@ -1,5 +1,8 @@ if BOARD_DELL_OPTIPLEX_9010 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_12288 @@ -19,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select PCIEXP_L1_SUB_STATE + select DRIVERS_UART_8250IO config MAINBOARD_DIR default "dell/optiplex_9010" diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index ec585b9f80..ef0a0e3174 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge device pci 06.0 off end # PEG2 chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "gpe0_en" = "0x00000146" + register "gpe0_en" = "0x00002a46" register "alt_gp_smi_en" = "0x0004" register "gpi2_routing" = "1" register "gpi12_routing" = "2" @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" register "gen4_dec" = "0x001c0901" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x7" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/dell/optiplex_9010/romstage.c b/src/mainboard/dell/optiplex_9010/romstage.c index 36af6e49c0..889b06d962 100644 --- a/src/mainboard/dell/optiplex_9010/romstage.c +++ b/src/mainboard/dell/optiplex_9010/romstage.c @@ -5,12 +5,25 @@ #include #include #include +#include #include #include #include #include "sch5545_ec.h" +void mainboard_late_rcba_config(void) +{ + DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); + DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); + DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); + DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); + DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); +} + void mainboard_early_init(int s3resume) { uint16_t ec_fw_version; diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 11d2af183b..e7ca602a90 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1b9edf04b9..f02c92dad4 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -3,25 +3,25 @@ if BOARD_EMULATION_QEMU_X86_I440FX config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_QEMU_X86 - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_256 if !VBOOT + select BOARD_ROMSIZE_KB_4096 if !VBOOT select BOARD_ROMSIZE_KB_16384 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_ASAN_IN_ROMSTAGE select NO_SMM select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_MEMORY_MAPPED config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index cac74ee435..7bd1c02121 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,10 +1,10 @@ -romstage-y += fw_cfg.c romstage-y += memmap.c -postcar-y += fw_cfg.c postcar-y += memmap.c postcar-y += exit_car.S -ramstage-y += fw_cfg.c ramstage-y += memmap.c ramstage-y += northbridge.c + +all-y += fw_cfg.c +all-y += bootmode.c diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index da670cf889..e9b48584ac 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + /**************************************************************** * HPET ****************************************************************/ @@ -8,7 +10,7 @@ Scope(\_SB) { Device(HPET) { Name(_HID, EISAID("PNP0103")) Name(_UID, 0) - OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400) + OperationRegion(HPTM, SystemMemory, HPET_BASE_ADDRESS, 0x400) Field(HPTM, DWordAcc, Lock, Preserve) { VEND, 32, PRD, 32, @@ -27,7 +29,7 @@ Scope(\_SB) { } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadOnly, - 0xFED00000, // Address Base + HPET_BASE_ADDRESS, // Address Base 0x00000400, // Address Length ) }) diff --git a/src/mainboard/emulation/qemu-i440fx/bootmode.c b/src/mainboard/emulation/qemu-i440fx/bootmode.c new file mode 100644 index 0000000000..12990b2552 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/bootmode.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include "fw_cfg.h" + +/* + * Enable recovery mode with fw_cfg option to qemu: + * -fw_cfg name=opt/cros/recovery,string=1 + */ +int get_recovery_mode_switch(void) +{ + FWCfgFile f; + + if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { + uint8_t rec_mode; + if (f.size != 1) { + printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); + return 0; + } + fw_cfg_get(f.select, &rec_mode, f.size); + if (rec_mode == '1') { + printk(BIOS_INFO, "Recovery is enabled.\n"); + return 1; + } + } + + return 0; +} diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 01be2c3cea..3206e4cec7 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -133,7 +133,7 @@ int fw_cfg_max_cpus(void) unsigned short max_cpus; if (!fw_cfg_present()) - return -1; + return 0; fw_cfg_get(FW_CFG_MAX_CPUS, &max_cpus, sizeof(max_cpus)); return max_cpus; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index e972f54261..817d1a58f5 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -69,18 +69,18 @@ typedef struct FWCfgFile { uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; char name[FW_CFG_MAX_FILE_PATH]; -} FWCfgFile; +} __packed FWCfgFile; typedef struct FWCfgFiles { uint32_t count; FWCfgFile f[]; -} FWCfgFiles; +} __packed FWCfgFiles; typedef struct FwCfgE820Entry { uint64_t address; uint64_t length; uint32_t type; -} FwCfgE820Entry __attribute((__aligned__(4))); +} __packed FwCfgE820Entry __attribute((__aligned__(4))); #define SMBIOS_FIELD_ENTRY 0 @@ -91,7 +91,7 @@ typedef struct FwCfgSmbios { uint8_t headertype; uint8_t tabletype; uint16_t fieldoffset; -} FwCfgSmbios; +} __packed FwCfgSmbios; /* FW_CFG_ID bits */ #define FW_CFG_VERSION 0x01 @@ -113,6 +113,6 @@ typedef struct FwCfgDmaAccess { uint32_t control; uint32_t length; uint64_t address; -} FwCfgDmaAccess; +} __packed FwCfgDmaAccess; #endif /* FW_CFG_IF_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index d041b0c673..06aa83af50 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -8,10 +8,8 @@ #include #include #include -#include #include #include -#include #include #include #include "memory.h" @@ -265,11 +263,11 @@ static void cpu_bus_init(struct device *dev) static void cpu_bus_scan(struct device *bus) { - int max_cpus = fw_cfg_max_cpus(); + unsigned int max_cpus = fw_cfg_max_cpus(); struct device *cpu; int i; - if (max_cpus < 0) + if (max_cpus == 0) return; /* * Do not install more CPUs than supported by coreboot. diff --git a/src/mainboard/emulation/qemu-power9/Kconfig b/src/mainboard/emulation/qemu-power9/Kconfig new file mode 100644 index 0000000000..94c5a59cd5 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/Kconfig @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# To execute, do: +# qemu-system-ppc64 -M powernv --cpu power9 --bios 'build/coreboot.rom' + +if BOARD_EMULATION_QEMU_POWER9 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_POWER9 + select BOARD_ROMSIZE_KB_1024 + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + select BOOT_DEVICE_NOT_SPI_FLASH + select MISSING_BOARD_RESET + +config MEMLAYOUT_LD_FILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" + +config MAINBOARD_DIR + string + default "emulation/qemu-power9" + +config MAINBOARD_PART_NUMBER + string + default "QEMU POWER9" + +config MAX_CPUS + int + default 1 + +config MAINBOARD_VENDOR + string + default "Emulation" + +config DRAM_SIZE_MB + int + default 32768 + +endif # BOARD_EMULATION_QEMU_POWER9 diff --git a/src/mainboard/emulation/qemu-power9/Kconfig.name b/src/mainboard/emulation/qemu-power9/Kconfig.name new file mode 100644 index 0000000000..1f5d4e177c --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_POWER9 + bool "QEMU power9" diff --git a/src/mainboard/emulation/qemu-power9/Makefile.inc b/src/mainboard/emulation/qemu-power9/Makefile.inc new file mode 100644 index 0000000000..ace00a75b7 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += cbmem.c +romstage-y += romstage.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/emulation/qemu-power9/board_info.txt b/src/mainboard/emulation/qemu-power9/board_info.txt new file mode 100644 index 0000000000..11820e7187 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/board_info.txt @@ -0,0 +1,2 @@ +Board name: QEMU POWER9 +Category: emulation diff --git a/src/mainboard/emulation/qemu-power9/cbmem.c b/src/mainboard/emulation/qemu-power9/cbmem.c new file mode 100644 index 0000000000..1b7b690883 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/cbmem.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void *cbmem_top_chipset(void) +{ + return (void *)(probe_ramsize(0, CONFIG_DRAM_SIZE_MB) * MiB); +} diff --git a/src/mainboard/emulation/qemu-power9/devicetree.cb b/src/mainboard/emulation/qemu-power9/devicetree.cb new file mode 100644 index 0000000000..7ea6247070 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip cpu/power9 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/emulation/qemu-power9/mainboard.c b/src/mainboard/emulation/qemu-power9/mainboard.c new file mode 100644 index 0000000000..6c178af4ab --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void mainboard_enable(struct device *dev) +{ + if (!dev) + die("No dev0; die\n"); + ram_resource(dev, 0, 0, (unsigned long)cbmem_top() / KiB); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-power9/memlayout.ld b/src/mainboard/emulation/qemu-power9/memlayout.ld new file mode 100644 index 0000000000..8209433020 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/memlayout.ld @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +SECTIONS +{ + DRAM_START(0x0) + + BOOTBLOCK(0, 32K) + + ROMSTAGE(0x1f00000, 1M) + +#if !ENV_RAMSTAGE + STACK(0x2000000, 32K) +#endif + + FMAP_CACHE(0x2108000, 4K) + CBFS_MCACHE(0x2109000, 8K) + TIMESTAMP(0x210b000, 4K) + CBFS_CACHE(0x210c000, 512K) + PRERAM_CBMEM_CONSOLE(0x218c000, 128K) + + /* By default all memory addresses are affected by the value of HRMOR + * (Hypervisor Real Mode Offset Register) which is ORed to them. HRMOR + * has initial value of 0x8000000 in QEMU and is changed to 0 in + * ramstage. This means that before ramstage 0 actually points to + * 0x8000000. */ +#if ENV_RAMSTAGE + STACK(0xa000000, 32K) +#endif + RAMSTAGE(0xa008000, 1M) +} diff --git a/src/mainboard/emulation/qemu-power9/ramstage.c b/src/mainboard/emulation/qemu-power9/ramstage.c new file mode 100644 index 0000000000..c92587b696 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * Payload's entry point is an offset to the real entry point, not to OPD + * (Official Procedure Descriptor) for entry point. + * + * Also pass FDT address to payload stored in SPR_HSPRG0 by bootblock. + */ +void platform_prog_run(struct prog *prog) +{ + asm volatile( + "mfspr %%r27, %0\n" /* pass pointer to FDT */ + "mtctr %2\n" + "mr 3, %1\n" + "bctr\n" + :: "i"(SPR_HSPRG0), "r"(prog_entry_arg(prog)), "r"(prog_entry(prog)) + : "memory"); +} diff --git a/src/mainboard/emulation/qemu-power9/romstage.c b/src/mainboard/emulation/qemu-power9/romstage.c new file mode 100644 index 0000000000..4a3ed8304c --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void main(void) +{ + console_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 04dce28261..1fc82b5ff0 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -16,12 +16,12 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select BOOT_DEVICE_NOT_SPI_FLASH + select BOOT_DEVICE_MEMORY_MAPPED config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS - select VBOOT_NO_BOARD_SUPPORT if !CHROMEOS select GBB_FLAG_DISABLE_LID_SHUTDOWN select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC @@ -57,10 +57,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "QEMU x86 q35/ich9" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xb0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 6d5c29e7fd..dc4e794368 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,23 +1,21 @@ bootblock-y += bootblock.c bootblock-y += memmap.c -romstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memmap.c romstage-y += memmap.c -postcar-y += ../qemu-i440fx/fw_cfg.c postcar-y += ../qemu-i440fx/memmap.c postcar-y += ../qemu-i440fx/exit_car.S postcar-y += memmap.c -ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += memmap.c ramstage-y += cpu.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c +all-y += ../qemu-i440fx/fw_cfg.c +all-y += ../qemu-i440fx/bootmode.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-y += smi.c diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index ec86c70a3c..98fcb629fe 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -11,12 +11,12 @@ static void bootblock_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index 1af2e02adb..c4770ffd7d 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include -#include +#include #include -#include "../qemu-i440fx/fw_cfg.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -16,35 +16,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - -/* - * Enable recovery mode with fw_cfg option to qemu: - * -fw_cfg name=opt/cros/recovery,string=1 - */ -int get_recovery_mode_switch(void) -{ - FWCfgFile f; - - if (!fw_cfg_check_file(&f, "opt/cros/recovery")) { - uint8_t rec_mode; - if (f.size != 1) { - printk(BIOS_ERR, "opt/cros/recovery invalid size %d\n", f.size); - return 0; - } - fw_cfg_get(f.select, &rec_mode, f.size); - if (rec_mode == '1') { - printk(BIOS_INFO, "Recovery is enabled.\n"); - return 1; - } - } - - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"), }; @@ -53,3 +24,10 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index 5c4292138d..7d5180e819 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -14,7 +14,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -24,7 +24,7 @@ static uint32_t encode_pciexbar_length(void) uint32_t make_pciexbar(void) { - return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; } /* Check that MCFG is active. If it's not, QEMU was started for machine PC */ diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e6e2e47e1f..e2254be3e2 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -2,6 +2,9 @@ if BOARD_FACEBOOK_FBG1701 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index fd005a6bf2..7a31309a06 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -18,13 +18,24 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - u8 spd_index = 0; + u8 spd_index; - if (!CONFIG(ONBOARD_SAMSUNG_MEM)) { - if (cpld_read_pcb_version() <= 7) - spd_index = 1; - else - spd_index = 2; + switch (cpld_read_pcb_version()) { + case 0: /* intentional fallthrough */ + case 1: /* intentional fallthrough */ + case 2: /* intentional fallthrough */ + case 3: /* intentional fallthrough */ + case 4: /* intentional fallthrough */ + case 5: + spd_index = 0; + break; + case 6: /* intentional fallthrough */ + case 7: + spd_index = 1; + break; + default: + spd_index = 2; + break; } memory_params->PcdMemoryTypeEnable = MEM_DDR3; diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 50738f49d9..33e4526f5a 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -1,5 +1,8 @@ if BOARD_FACEBOOK_MONOLITH +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 @@ -13,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select VPD +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CBFS_SIZE default 0x00900000 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 023ace9224..05bcc12257 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ @@ -224,6 +223,7 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 6ddc7dffc1..33d5e6da2a 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -2,6 +2,9 @@ if BOARD_FOXCONN_D41S +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_FCBGA559 diff --git a/src/mainboard/foxconn/g41s-k/Kconfig b/src/mainboard/foxconn/g41s-k/Kconfig index c5a0642cd3..83136d31b4 100644 --- a/src/mainboard/foxconn/g41s-k/Kconfig +++ b/src/mainboard/foxconn/g41s-k/Kconfig @@ -2,6 +2,9 @@ if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_LGA775 diff --git a/src/mainboard/gigabyte/ga-d510ud/Kconfig b/src/mainboard/gigabyte/ga-d510ud/Kconfig index 731b9f40ee..4739f81b03 100644 --- a/src/mainboard/gigabyte/ga-d510ud/Kconfig +++ b/src/mainboard/gigabyte/ga-d510ud/Kconfig @@ -2,6 +2,9 @@ if BOARD_GIGABYTE_GA_D510UD +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h index fdd5de0cd1..954ef21e58 100644 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ b/src/mainboard/gizmosphere/gizmo/OptionsIds.h @@ -32,5 +32,4 @@ //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE - #endif diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl index 705abf17f6..44e7b68eac 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl @@ -30,7 +30,6 @@ Scope(\_GPE) { /* Start Scope GPE */ /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 33415f9b97..f7e9a0184e 100644 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -3,7 +3,7 @@ chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on chip cpu/amd/agesa/family14 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on @@ -19,7 +19,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 8.0 off end # NB/SB Link P2P bridge end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index fbe2daf100..c50f4b935e 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index a722980ed7..534a1ad465 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 6f8f24281a..1aa8876ca4 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -40,3 +40,9 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(GPIO_H1_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7704899f16..bbca4b83ba 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -142,72 +142,6 @@ static bool configure_display(void) return true; } -static void configure_emmc(void) -{ - void *gpio_base = (void *)IOCFG_TL_BASE; - int i; - - const gpio_t emmc_pu_pin[] = { - GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), - GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), - GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), - GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), - GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), - }; - - const gpio_t emmc_pd_pin[] = { - GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) - gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) - gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ - clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); - - mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); -} - -static void configure_sdcard(void) -{ - void *gpio_base = (void *)IOCFG_RM_BASE; - void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; - void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; - uint8_t enable = 1; - int i; - - const gpio_t sdcard_pu_pin[] = { - GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), - GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), - GPIO(MSDC1_CMD), - }; - - const gpio_t sdcard_pd_pin[] = { - GPIO(MSDC1_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) - gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) - gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set sdcard cmd/dat/clk pins driving to 8mA */ - clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); - - /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ - clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); - - /* set sdcard dat1 pin to msdc1 mode */ - clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); - - mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); - mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); -} - static void configure_audio(void) { /* Audio PWR */ @@ -222,8 +156,8 @@ static void configure_audio(void) static void mainboard_init(struct device *dev) { - configure_emmc(); - configure_sdcard(); + mtk_msdc_configure_emmc(true); + mtk_msdc_configure_sdcard(); configure_audio(); setup_usb_host(); diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 61447fdacb..ead4c3b5ea 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -1,24 +1,52 @@ - config BOARD_GOOGLE_BASEBOARD_AURON def_bool n - select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT + select INTEL_INT15 select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select INTEL_INT15 - select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_BUDDY - select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_BUDDY + select SOC_INTEL_BROADWELL + +config BOARD_GOOGLE_AURON_PAINE + select BOARD_GOOGLE_BASEBOARD_AURON + select HAVE_SPD_IN_CBFS + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_AURON_YUNA + select BOARD_GOOGLE_BASEBOARD_AURON + select HAVE_SPD_IN_CBFS + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_BUDDY + select BOARD_GOOGLE_BASEBOARD_AURON + +config BOARD_GOOGLE_GANDOF + select BOARD_GOOGLE_BASEBOARD_AURON + select HAVE_SPD_IN_CBFS + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_LULU + select BOARD_GOOGLE_BASEBOARD_AURON + select HAVE_SPD_IN_CBFS + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_SAMUS + select BOARD_GOOGLE_BASEBOARD_AURON + select HAVE_SPD_IN_CBFS + select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_AURON +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH @@ -46,11 +74,6 @@ config MAINBOARD_PART_NUMBER config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "samus" if BOARD_GOOGLE_SAMUS - default "" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/auron/Kconfig.name b/src/mainboard/google/auron/Kconfig.name index 19fd4d7fcc..4ac0368cc3 100644 --- a/src/mainboard/google/auron/Kconfig.name +++ b/src/mainboard/google/auron/Kconfig.name @@ -2,24 +2,18 @@ comment "Auron" config BOARD_GOOGLE_AURON_PAINE bool "-> Auron_Paine (Acer C740 Chromebook)" - select BOARD_GOOGLE_BASEBOARD_AURON config BOARD_GOOGLE_AURON_YUNA bool "-> Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))" - select BOARD_GOOGLE_BASEBOARD_AURON config BOARD_GOOGLE_BUDDY bool "-> Buddy (Acer Chromebase 24)" - select BOARD_GOOGLE_BASEBOARD_AURON config BOARD_GOOGLE_GANDOF bool "-> Gandof (Toshiba Chromebook 2 (2015))" - select BOARD_GOOGLE_BASEBOARD_AURON config BOARD_GOOGLE_LULU bool "-> Lulu (Dell Chromebook 13 7310)" - select BOARD_GOOGLE_BASEBOARD_AURON config BOARD_GOOGLE_SAMUS bool "-> Samus (Google Chromebook Pixel (2015))" - select BOARD_GOOGLE_BASEBOARD_AURON diff --git a/src/mainboard/google/auron/acpi/thermal.asl b/src/mainboard/google/auron/acpi/thermal.asl index fd05e7350f..898ef26ef2 100644 --- a/src/mainboard/google/auron/acpi/thermal.asl +++ b/src/mainboard/google/auron/acpi/thermal.asl @@ -92,8 +92,7 @@ Scope (\_TZ) Local1 = CTOK (\TCRT) If (Local0 >= Local1) { - Debug = "CRITICAL TEMPERATURE" - Debug = Local0 + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for EC to re-poll Sleep (1000) @@ -101,8 +100,7 @@ Scope (\_TZ) // Re-read temperature from EC Local0 = TCHK () - Debug = "RE-READ TEMPERATURE" - Debug = Local0 + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 50eeddce0a..9807acec36 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -1,12 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include -/* SPI Write protect is GPIO 16 */ -#define CROS_WP_GPIO 58 +#include "onboard.h" + +/* EC_IN_RW is GPIO 25 in samus and 14 otherwise */ +#if CONFIG(BOARD_GOOGLE_SAMUS) +#define EC_IN_RW_GPIO 25 +#else +#define EC_IN_RW_GPIO 14 +#endif void fill_lb_gpios(struct lb_gpios *gpios) { @@ -32,3 +40,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(EC_IN_RW_GPIO); +} diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index d4482b01ba..a3ee95bd0b 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include "ec.h" diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 12d5a68da6..f465d0775d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include "ec.h" #include "variant.h" @@ -29,7 +28,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/auron/onboard.h b/src/mainboard/google/auron/onboard.h new file mode 100644 index 0000000000..6d4ff28dd8 --- /dev/null +++ b/src/mainboard/google/auron/onboard.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AURON_ONBOARD_H +#define AURON_ONBOARD_H + +/* SPI Write protect is GPIO 58 */ +#define CROS_WP_GPIO 58 + +#endif diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 0570cdca55..ad8e50c4b6 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -33,7 +33,7 @@ chip soc/intel/broadwell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 0a92efe70b..cfb48123b4 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -36,7 +36,7 @@ chip soc/intel/broadwell # Force enable ASPM for PCIe Port 3 register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 00b33ad4ab..d6da71c6f3 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -1,21 +1,39 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO def_bool n - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_ITE_IT8772F + +config BOARD_GOOGLE_MCCLOUD + select BOARD_GOOGLE_BASEBOARD_BELTINO + +config BOARD_GOOGLE_MONROE + select BOARD_GOOGLE_BASEBOARD_BELTINO + +config BOARD_GOOGLE_PANTHER + select BOARD_GOOGLE_BASEBOARD_BELTINO + +config BOARD_GOOGLE_TRICKY + select BOARD_GOOGLE_BASEBOARD_BELTINO + +config BOARD_GOOGLE_ZAKO + select BOARD_GOOGLE_BASEBOARD_BELTINO if BOARD_GOOGLE_BASEBOARD_BELTINO +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/beltino/Kconfig.name b/src/mainboard/google/beltino/Kconfig.name index f75f4289ba..6c3913d1f4 100644 --- a/src/mainboard/google/beltino/Kconfig.name +++ b/src/mainboard/google/beltino/Kconfig.name @@ -2,20 +2,15 @@ comment "Beltino" config BOARD_GOOGLE_MCCLOUD bool "-> Mccloud (Acer Chromebox CXI)" - select BOARD_GOOGLE_BASEBOARD_BELTINO config BOARD_GOOGLE_MONROE bool "-> Monroe (LG Chromebase 22CV241 & 22CB25S)" - select BOARD_GOOGLE_BASEBOARD_BELTINO config BOARD_GOOGLE_PANTHER bool "-> Panther (ASUS Chromebox CN60)" - select BOARD_GOOGLE_BASEBOARD_BELTINO config BOARD_GOOGLE_TRICKY bool "-> Tricky (Dell Chromebox 3010)" - select BOARD_GOOGLE_BASEBOARD_BELTINO config BOARD_GOOGLE_ZAKO bool "-> Zako (HP Chromebox G1)" - select BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 96acaeb975..c6b686ee6c 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -94,8 +94,7 @@ Scope (\_TZ) Local1 = CTOK (\TMAX) If (Local0 >= Local1) { - Debug = "CRITICAL TEMPERATURE" - Debug = Local0 + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for SuperIO to re-poll Sleep (1000) @@ -103,8 +102,7 @@ Scope (\_TZ) // Re-read temperature from SuperIO Local0 = TCHK () - Debug = "RE-READ TEMPERATURE" - Debug = Local0 + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index c3c90a4e5b..33f4b6bf3d 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index a33caca37a..db646495de 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -6,10 +6,9 @@ #include #include #include +#include #include - -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -26,6 +25,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -44,11 +53,11 @@ void init_bootmode_straps(void) const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); /* Developer: Virtual */ @@ -65,3 +74,10 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8c54f6a6d0..8eada25326 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -44,7 +44,7 @@ chip northbridge/intel/haswell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7eba3c2c2f..b35e005405 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "onboard.h" @@ -25,7 +24,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/beltino/onboard.h b/src/mainboard/google/beltino/onboard.h index 2cced23900..8bd21ce3d5 100644 --- a/src/mainboard/google/beltino/onboard.h +++ b/src/mainboard/google/beltino/onboard.h @@ -16,6 +16,12 @@ /* WLAN wake is GPIO 10 */ #define WLAN_WAKE_GPIO 10 +/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + +/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + /* IT8772F defs */ #define IT8772F_BASE 0x2e #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index a818d87f1c..ecf54905e6 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e6e44e2f56..f7bd715f5d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,34 +1,26 @@ -config BOARD_GOOGLE_BASEBOARD_BRYA - def_bool n - select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS - select HAVE_SPD_IN_CBFS - select SYSTEM_TYPE_LAPTOP - -config BOARD_GOOGLE_BASEBOARD_BRASK - def_bool n - select SPD_CACHE_IN_FMAP - -if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK - config BOARD_GOOGLE_BRYA_COMMON - def_bool y + def_bool n + select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_ALC1015 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_NAU8825 select DRIVERS_I2C_SX9324 select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_USB4_RETIMER - select DRIVERS_SPI_ACPI + select DRIVERS_PCIE_GENERIC select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 + select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC + select DRIVERS_WWAN_FM350GL select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID @@ -41,20 +33,52 @@ config BOARD_GOOGLE_BRYA_COMMON select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_ALDERLAKE + select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P + +config BOARD_GOOGLE_BASEBOARD_BRYA + def_bool n + select BOARD_GOOGLE_BRYA_COMMON + select HAVE_SLP_S0_GATE + select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE + select SOC_INTEL_ALDERLAKE_PCH_P + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_BASEBOARD_BRASK + def_bool n + select BOARD_GOOGLE_BRYA_COMMON + select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP + select HAVE_SLP_S0_GATE + select MEMORY_SODIMM + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_ALDERLAKE_PCH_P + +config BOARD_GOOGLE_BASEBOARD_NISSA + def_bool n + select BOARD_GOOGLE_BRYA_COMMON + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select MEMORY_SOLDERDOWN + select SOC_INTEL_ALDERLAKE_PCH_N + select SYSTEM_TYPE_LAPTOP + +if BOARD_GOOGLE_BRYA_COMMON + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y config BASEBOARD_DIR string default "brya" if BOARD_GOOGLE_BASEBOARD_BRYA default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK + default "nissa" if BOARD_GOOGLE_BASEBOARD_NISSA config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select VBOOT_LID_SWITCH config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" @@ -69,12 +93,38 @@ config DEVICETREE config DRIVER_TPM_I2C_BUS hex - default 0x3 + default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x3 if BOARD_GOOGLE_BRYA4ES + default 0x1 if BOARD_GOOGLE_BRASK + default 0x1 if BOARD_GOOGLE_PRIMUS + default 0x3 if BOARD_GOOGLE_PRIMUS4ES + default 0x1 if BOARD_GOOGLE_GIMBLE + default 0x3 if BOARD_GOOGLE_GIMBLE4ES + default 0x1 if BOARD_GOOGLE_REDRIX + default 0x3 if BOARD_GOOGLE_REDRIX4ES + default 0x1 if BOARD_GOOGLE_KANO + default 0x1 if BOARD_GOOGLE_TAEKO + default 0x3 if BOARD_GOOGLE_TAEKO4ES + default 0x1 if BOARD_GOOGLE_FELWINTER + default 0x1 if BOARD_GOOGLE_ANAHERA + default 0x3 if BOARD_GOOGLE_ANAHERA4ES + default 0x1 if BOARD_GOOGLE_VELL + default 0x1 if BOARD_GOOGLE_TANIKS + default 0x0 if BOARD_GOOGLE_NIVVIKS + default 0x0 if BOARD_GOOGLE_NEREID + default 0x3 if BOARD_GOOGLE_AGAH + default 0x1 if BOARD_GOOGLE_VOLMAR + default 0x1 if BOARD_GOOGLE_BANSHEE + default 0x1 if BOARD_GOOGLE_KINOX config DRIVER_TPM_I2C_ADDR hex default 0x50 +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + config TPM_TIS_ACPI_INTERRUPT int default 13 # GPE0_DW0_13 (GPP_A13_IRQ) @@ -89,28 +139,65 @@ config MAINBOARD_FAMILY string default "Google_Brya" if BOARD_GOOGLE_BASEBOARD_BRYA default "Google_Brask" if BOARD_GOOGLE_BASEBOARD_BRASK + default "Google_Nissa" if BOARD_GOOGLE_BASEBOARD_NISSA config MAINBOARD_PART_NUMBER default "Brya" if BOARD_GOOGLE_BRYA0 + default "Brya4ES" if BOARD_GOOGLE_BRYA4ES default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS + default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES default "Gimble" if BOARD_GOOGLE_GIMBLE + default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX + default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES default "Kano" if BOARD_GOOGLE_KANO default "Taeko" if BOARD_GOOGLE_TAEKO + default "Taeko4ES" if BOARD_GOOGLE_TAEKO4ES default "Felwinter" if BOARD_GOOGLE_FELWINTER default "Anahera" if BOARD_GOOGLE_ANAHERA + default "Anahera4ES" if BOARD_GOOGLE_ANAHERA4ES + default "Vell" if BOARD_GOOGLE_VELL + default "Taniks" if BOARD_GOOGLE_TANIKS + default "Nivviks" if BOARD_GOOGLE_NIVVIKS + default "Nereid" if BOARD_GOOGLE_NEREID + default "Agah" if BOARD_GOOGLE_AGAH + default "Volmar" if BOARD_GOOGLE_VOLMAR + default "Banshee" if BOARD_GOOGLE_BANSHEE + default "Crota" if BOARD_GOOGLE_CROTA + default "Moli" if BOARD_GOOGLE_MOLI + default "Kinox" if BOARD_GOOGLE_KINOX config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 + default "brya4es" if BOARD_GOOGLE_BRYA4ES default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS + default "primus4es" if BOARD_GOOGLE_PRIMUS4ES default "gimble" if BOARD_GOOGLE_GIMBLE + default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX + default "redrix4es" if BOARD_GOOGLE_REDRIX4ES default "kano" if BOARD_GOOGLE_KANO default "taeko" if BOARD_GOOGLE_TAEKO + default "taeko4es" if BOARD_GOOGLE_TAEKO4ES default "felwinter" if BOARD_GOOGLE_FELWINTER default "anahera" if BOARD_GOOGLE_ANAHERA + default "anahera4es" if BOARD_GOOGLE_ANAHERA4ES + default "vell" if BOARD_GOOGLE_VELL + default "taniks" if BOARD_GOOGLE_TANIKS + default "nivviks" if BOARD_GOOGLE_NIVVIKS + default "nereid" if BOARD_GOOGLE_NEREID + default "agah" if BOARD_GOOGLE_AGAH + default "volmar" if BOARD_GOOGLE_VOLMAR + default "banshee" if BOARD_GOOGLE_BANSHEE + default "crota" if BOARD_GOOGLE_CROTA + default "moli" if BOARD_GOOGLE_MOLI + default "kinox" if BOARD_GOOGLE_KINOX + +config VBOOT + select VBOOT_EARLY_EC_SYNC + select VBOOT_LID_SWITCH config DIMM_SPD_SIZE default 512 @@ -125,6 +212,41 @@ config HAVE_WWAN_POWER_SEQUENCE Select this if the variant has a WWAN module and requires the poweroff sequence to be performed on shutdown. Must define WWAN_FCPO, WWAN_RST and WWAN_PERST GPIOs in variant.h, as well as T1_OFF_MS (time between PERST & RST) and T2_OFF_MS (time - between RST and FCPO). + between RST and FCPO). WWAN_PERST and T1_OFF_MS are only necessary for PCIe WWAN + (when HAVE_PCIE_WWAN is also selected). -endif # BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK +config HAVE_PCIE_WWAN + def_bool n + +config USE_PM_ACPI_TIMER + default y if BOARD_GOOGLE_PRIMUS4ES + default n + +choice + prompt "Cache as RAM (CAR) setup configuration to use" + default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID + default USE_ADL_ENEM + +config USE_ADL_ENEM + bool "eNEM: when selected, the variant will use eNEM instead of regular NEM." + select INTEL_CAR_NEM_ENHANCED + +config USE_ADL_NEM + bool "NEM: when selected, the variant will use regular NEM." + select INTEL_CAR_NEM + +endchoice + +config MEMORY_SODIMM + def_bool n + select SPD_CACHE_IN_FMAP + +config MEMORY_SOLDERDOWN + def_bool n + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select HAVE_SPD_IN_CBFS + +config HAVE_SLP_S0_GATE + def_bool n + +endif # BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ed9d82c3d0..50f4a3111a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -1,68 +1,188 @@ comment "Brya" -config BOARD_GOOGLE_BRYA0 - bool "-> Brya 0" +config BOARD_GOOGLE_AGAH + bool "-> Agah" select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_INTEL_MIPI_CAMERA - select HAVE_WWAN_POWER_SEQUENCE - select SOC_INTEL_COMMON_BLOCK_IPU - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_BRASK - bool "-> Brask" - select BOARD_GOOGLE_BASEBOARD_BRASK - select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_CRASHLOG - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_PRIMUS - bool "-> Primus" - select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - select HAVE_WWAN_POWER_SEQUENCE - -config BOARD_GOOGLE_GIMBLE - bool "-> Gimble" - select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_MAX98390 - -config BOARD_GOOGLE_REDRIX - bool "-> Redrix" - select BOARD_GOOGLE_BASEBOARD_BRYA - select CHROMEOS_DSM_CALIB if CHROMEOS - select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS - select DRIVERS_I2C_MAX98390 - select DRIVERS_INTEL_MIPI_CAMERA - select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select SOC_INTEL_COMMON_BLOCK_IPU - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVERS_GFX_GENERIC - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_KANO - bool "-> Kano" - select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_NAU8825 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - select DRIVERS_INTEL_MIPI_CAMERA - select SOC_INTEL_COMMON_BLOCK_IPU - -config BOARD_GOOGLE_TAEKO - bool "-> Taeko" - select BOARD_GOOGLE_BASEBOARD_BRYA - select DRIVERS_GENESYSLOGIC_GL9763E - -config BOARD_GOOGLE_FELWINTER - bool "-> Felwinter" - select BOARD_GOOGLE_BASEBOARD_BRYA + select PCIEXP_SUPPORT_RESIZABLE_BARS + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE config BOARD_GOOGLE_ANAHERA bool "-> Anahera" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GFX_GENERIC - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_ANAHERA4ES + bool "-> Anahera4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GFX_GENERIC + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_BRASK + bool "-> Brask" + select BOARD_GOOGLE_BASEBOARD_BRASK + select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_CRASHLOG + +config BOARD_GOOGLE_BRYA0 + bool "-> Brya 0" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_CRASHLOG + +config BOARD_GOOGLE_BRYA4ES + bool "-> Brya4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_CRASHLOG + +config BOARD_GOOGLE_FELWINTER + bool "-> Felwinter" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_GIMBLE + bool "-> Gimble" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_MAX98390 + +config BOARD_GOOGLE_GIMBLE4ES + bool "-> Gimble4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_MAX98390 + +config BOARD_GOOGLE_KANO + bool "-> Kano" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_NAU8825 + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_NIVVIKS + bool "-> Nivviks" + select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_INTEL_MIPI_CAMERA + select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_NEREID + bool "-> Nereid" + select BOARD_GOOGLE_BASEBOARD_NISSA + +config BOARD_GOOGLE_PRIMUS + bool "-> Primus" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_PRIMUS4ES + bool "-> Primus4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENESYSLOGIC_GL9755 + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_REDRIX + bool "-> Redrix" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_MAX98390 + select DRIVERS_INTEL_MIPI_CAMERA + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_REDRIX4ES + bool "-> Redrix4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS + select DRIVERS_GENESYSLOGIC_GL9755 + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_MAX98390 + select DRIVERS_INTEL_MIPI_CAMERA + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_COMMON_BLOCK_IPU + +config BOARD_GOOGLE_TAEKO + bool "-> Taeko" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E + select CHROMEOS_WIFI_SAR if CHROMEOS + +config BOARD_GOOGLE_TAEKO4ES + bool "-> Taeko4ES" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E + select CHROMEOS_WIFI_SAR if CHROMEOS + +config BOARD_GOOGLE_TANIKS + bool "-> Taniks" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENESYSLOGIC_GL9763E + +config BOARD_GOOGLE_VELL + bool "-> Vell" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_GFX_GENERIC + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU + select CHROMEOS_WIFI_SAR if CHROMEOS + +config BOARD_GOOGLE_VOLMAR + bool "-> Volmar" + select BOARD_GOOGLE_BASEBOARD_BRYA + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_NAU8825 + +config BOARD_GOOGLE_BANSHEE + bool "-> Banshee" + select BOARD_GOOGLE_BASEBOARD_BRYA + select MEMORY_SODIMM + +config BOARD_GOOGLE_CROTA + bool "-> Crota" + select BOARD_GOOGLE_BASEBOARD_BRYA + +config BOARD_GOOGLE_MOLI + bool "-> Moli" + select BOARD_GOOGLE_BASEBOARD_BRASK + +config BOARD_GOOGLE_KINOX + bool "-> Kinox" + select BOARD_GOOGLE_BASEBOARD_BRASK diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index ac0dc32da8..1815615f5e 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -2,57 +2,6 @@ #include #include -#include -#include -#include -#include -#include -#include -#include - -#define SI_DESC_REGION "SI_DESC" -#define SI_DESC_REGION_SZ 4096 -#define PMC_DESC_7_BYTE3 0xc32 - -/* It updates PMC Descriptor in the Descriptor Region */ -static void configure_pmc_descriptor(void) -{ - uint8_t si_desc_buf[SI_DESC_REGION_SZ]; - struct region_device desc_rdev; - - if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); - return; - } - - if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x40) { - si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; - - if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) - != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); - - pmc_global_reset_enable(1); - do_full_reset(); - die("Failed to trigger GLOBAL RESET\n"); - } - - printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); -} void bootblock_mainboard_early_init(void) { @@ -61,9 +10,3 @@ void bootblock_mainboard_early_init(void) pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); } - -void bootblock_mainboard_init(void) -{ - if (cpu_get_cpuid() == CPUID_ALDERLAKE_A0) - configure_pmc_descriptor(); -} diff --git a/src/mainboard/google/brya/chromeos-serger.fmd b/src/mainboard/google/brya/chromeos-serger.fmd new file mode 100644 index 0000000000..72c6429672 --- /dev/null +++ b/src/mainboard/google/brya/chromeos-serger.fmd @@ -0,0 +1,60 @@ +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1588K + CSE_DATA 512K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 3008K + } + } + SI_BIOS 27M { + RW_SECTION_A 8M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3008K + } + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for brya variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3008K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index add73464da..cb636c616a 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -29,3 +31,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index 72c6429672..e44538395a 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -3,8 +3,8 @@ FLASH 32M { SI_DESC 4K SI_ME { CSE_LAYOUT 8K - CSE_RO 1588K - CSE_DATA 512K + CSE_RO 1640K + CSE_DATA 420K # 64-KiB aligned to optimize RW erases during CSE update. CSE_RW 3008K } diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl index c60db3081c..8ca694d152 100644 --- a/src/mainboard/google/brya/mainboard.asl +++ b/src/mainboard/google/brya/mainboard.asl @@ -2,6 +2,7 @@ #include +#if CONFIG(HAVE_SLP_S0_GATE) /* * S0ix Entry/Exit Notifications * Called from \_SB.PEPD._DSM @@ -22,3 +23,4 @@ Method (MS0X, 1, Serialized) \_SB.PCI0.STXS(GPIO_SLP_S0_GATE); } } +#endif diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 6287d2ceb5..536eabc858 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include #include -#include #include static void add_fw_config_oem_string(const struct fw_config *config, void *arg) @@ -60,7 +58,6 @@ static void mainboard_dev_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; } diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index d50d6e8571..ae47167ec1 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -7,8 +7,9 @@ #include #include -void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) +void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; diff --git a/src/mainboard/google/brya/variants/agah/Makefile.inc b/src/mainboard/google/brya/variants/agah/Makefile.inc new file mode 100644 index 0000000000..139345f260 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c new file mode 100644 index 0000000000..1423be91e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), + /* A8 : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A14 : USB_OC1# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : DDPC_CTRCLK ==> PG_PP3300_GPU_X_OD */ + PAD_CFG_GPI(GPP_A22, NONE, DEEP), + + /* B3 : PROC_GP2 ==> GPU_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), + /* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */ + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), + /* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */ + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> LAN_PR_ISOLATE_ODL */ + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */ + PAD_CFG_GPI_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_OD */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), + /* E5 : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E9 : USB_OC0# ==> USB_A2_OC_ODL */ + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), + /* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */ + PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG), + /* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */ + PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> PG_PP1800_GPU_X_OD */ + PAD_CFG_GPI(GPP_E20, NONE, DEEP), + /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + + /* H6 : I2C1_SDA ==> PCH_I2C_GPU_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_GPU_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H19 : SRCCLKREQ4# ==> LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R4 : HDA_RST# ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S_PCH_SPKR_RX */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> I2S_PCH_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), + /* S6 : SNDW3_CLK ==> SDW_HP_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + /* S7 : SNDW3_DATA ==> SDW_HP_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* + * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and + * then deassert PERST# in romstage + */ + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/agah/include/variant/ec.h b/src/mainboard/google/brya/variants/agah/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/agah/include/variant/gpio.h b/src/mainboard/google/brya/variants/agah/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/agah/memory.c b/src/mainboard/google/brya/variants/agah/memory.c new file mode 100644 index 0000000000..ef5e69a064 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/memory.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 0, 1, 4, 7, 6, 5, }, /* DDR_A_DQ0 */ + .dq1 = { 12, 13, 14, 15, 9, 10, 8, 11, }, /* DDR_A_DQ1 */ + }, + .ddr1 = { + .dq0 = { 14, 8, 9, 15, 10, 12, 11, 13, }, /* DDR_A_DQ2 */ + .dq1 = { 1, 7, 6, 0, 5, 3, 4, 2, }, /* DDR_A_DQ3 */ + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 6, 5, 7, 4, }, /* DDR_A_DQ4 */ + .dq1 = { 12, 13, 14, 15, 10, 11, 9, 8, }, /* DDR_A_DQ5 */ + }, + .ddr3 = { + .dq0 = { 1, 2, 0, 3, 5, 6, 7, 4, }, /* DDR_A_DQ6 */ + .dq1 = { 15, 14, 13, 12, 10, 9, 8, 11, }, /* DDR_A_DQ7 */ + }, + .ddr4 = { + .dq0 = { 3, 2, 1, 0, 7, 6, 5, 4, }, /* DDR_B_DQ0 */ + .dq1 = { 12, 15, 13, 14, 8, 9, 10, 11, }, /* DDR_B_DQ1 */ + }, + .ddr5 = { + .dq0 = { 14, 8, 9, 15, 12, 10, 11, 13, }, /* DDR_B_DQ2 */ + .dq1 = { 1, 7, 6, 0, 5, 2, 4, 3, }, /* DDR_B_DQ3 */ + }, + .ddr6 = { + .dq0 = { 13, 12, 15, 14, 8, 10, 9, 11, }, /* DDR_B_DQ4 */ + .dq1 = { 7, 4, 6, 5, 1, 0, 3, 2, }, /* DDR_B_DQ5 */ + }, + .ddr7 = { + .dq0 = { 6, 0, 7, 5, 3, 2, 1, 4, }, /* DDR_B_DQ6 */ + .dq1 = { 10, 8, 13, 12, 9, 14, 15, 11, }, /* DDR_B_DQ7 */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} diff --git a/src/mainboard/google/brya/variants/agah/memory/Makefile.inc b/src/mainboard/google/brya/variants/agah/memory/Makefile.inc new file mode 100644 index 0000000000..af6c1e3f94 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/memory/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /home/tony/ChromeProject/chroot_tot/GOlang/go1.17.5.linux-amd64/go/bin/part_id_gen ADL lp4x /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/ /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/agah/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/agah/memory/dram_id.generated.txt new file mode 100644 index 0000000000..20511a4cd3 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/memory/dram_id.generated.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /home/tony/ChromeProject/chroot_tot/GOlang/go1.17.5.linux-amd64/go/bin/part_id_gen ADL lp4x /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/ /home/tony/ChromeProject/coreboot/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E1G32D2NP-046 WT:A 0 (0000) +H9HCNNNBKMMLXR-NEE 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +MT53E512M32D2NP-046 WT:E 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) +MT53E2G32D4NQ-046 WT:A 4 (0100) +MT53E512M32D1NP-046 WT:B 1 (0001) +MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) diff --git a/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt new file mode 100644 index 0000000000..ca83c7f11f --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/memory/mem_parts_used.txt @@ -0,0 +1,14 @@ +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +H9HCNNNFAMMLXR-NEE +MT53E2G32D4NQ-046 WT:A +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb new file mode 100644 index 0000000000..2f79831fe6 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -0,0 +1,298 @@ +chip soc/intel/alderlake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | GPU | + #| I2C2 | External graphic | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SaGv" = "SaGv_Enabled" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""Regulator"" + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 0"" + register "uid" = "0" + register "name" = ""MXW0"" + register "r0_calib_key" = ""dsm_calib_r0_0"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" + register "dsm_param_file_name" = ""dsm_param_R"" + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + device i2c 0x3a on end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 1"" + register "uid" = "1" + register "name" = ""MXW1"" + register "r0_calib_key" = ""dsm_calib_r0_1"" + register "temperature_calib_key" = ""dsm_calib_temp_1"" + register "dsm_param_file_name" = ""dsm_param_L"" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" + device i2c 0x3b on end + end + end #I2C0 + device ref i2c1 on end # GPU + device ref i2c2 on end # External GPU + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pcie_rp3 on + chip drivers/net + register "customized_leds" = "0x05af" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "wake" = "GPE0_DW0_07" + device pci 00.0 on end + end + end #RTL8111H Ethernet NIC + device ref pcie_rp4 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 2))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 2))" + device ref usb3_port2 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/anahera/Makefile.inc b/src/mainboard/google/brya/variants/anahera/Makefile.inc index f2a624c0e8..c8a67babe4 100644 --- a/src/mainboard/google/brya/variants/anahera/Makefile.inc +++ b/src/mainboard/google/brya/variants/anahera/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c - +romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index e67de78a04..9483d564ab 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -22,13 +21,13 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -36,21 +35,21 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_C4, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ PAD_CFG_GPO(GPP_E0, 1, PLTRST), @@ -58,17 +57,22 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), - /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ @@ -91,17 +95,23 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_S6, NONE), /* S7 : SNDW3_DATA ==> NC */ PAD_NC(GPP_S7, NONE), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -125,16 +135,31 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* + * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and + * then deassert PERST# in romstage + */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -146,3 +171,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/anahera/include/variant/gpio.h b/src/mainboard/google/brya/variants/anahera/include/variant/gpio.h index c4fe342621..99d09b2432 100644 --- a/src/mainboard/google/brya/variants/anahera/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/anahera/include/variant/gpio.h @@ -5,4 +5,10 @@ #include +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif diff --git a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc index 68aa2f02ca..796b56e696 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory/ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt index dcc5ba3433..fa08f4a0cd 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera/memory/ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,8 @@ H9HCNNNFAMMLXR-NEE 3 (0011) MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) +MT53E2G32D4NQ-046 WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt index 71bd5fd385..dd7ec3ffe4 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt @@ -8,3 +8,8 @@ H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 7d003b3f62..6a79a961a6 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -22,48 +22,47 @@ fw_config end end chip soc/intel/alderlake - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" + register "tcc_offset" = "3" # TCC of 97C register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port @@ -72,6 +71,8 @@ chip soc/intel/alderlake chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" @@ -199,6 +200,13 @@ chip soc/intel/alderlake end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" @@ -215,6 +223,7 @@ chip soc/intel/alderlake register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid @@ -229,6 +238,7 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end @@ -273,13 +283,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -291,13 +301,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -309,19 +321,22 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 2))" device ref usb2_port2 on end - end + end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -337,7 +352,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -350,13 +366,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 2))" device ref usb3_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/anahera4es/Makefile.inc b/src/mainboard/google/brya/variants/anahera4es/Makefile.inc new file mode 100644 index 0000000000..c8a67babe4 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/anahera4es/fw_config.c b/src/mainboard/google/brya/variants/anahera4es/fw_config.c new file mode 100644 index 0000000000..b12293f3be --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/fw_config.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0 */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682IVS_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c new file mode 100644 index 0000000000..132dbf64b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A17 : DISP_MISCC ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B3 : PROC_GP2 ==> eMMC_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), + /* B5 : ISH_I2C0_SDA ==> NC */ + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), + /* B6 : ISH_I2C0_SCL ==> NC */ + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 1, PLTRST), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> Privacy screen */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* + * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and + * then deassert PERST# in romstage + */ + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h b/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h new file mode 100644 index 0000000000..99d09b2432 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + +#endif diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc new file mode 100644 index 0000000000..91ce2664b8 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory/ src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..c16535686f --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/anahera4es/memory/ src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E1G32D2NP-046 WT:A 0 (0000) +H9HCNNNBKMMLXR-NEE 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +MT53E512M32D2NP-046 WT:E 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) +MT53E2G32D4NQ-046 WT:A 4 (0100) +MT53E512M32D1NP-046 WT:B 1 (0001) +MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) +MT53E2G32D4NQ-046 WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..dd7ec3ffe4 --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +H9HCNNNFAMMLXR-NEE +MT53E2G32D4NQ-046 WT:A +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb new file mode 100644 index 0000000000..ab432e962e --- /dev/null +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -0,0 +1,381 @@ +fw_config + field DB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9750 1 + end + field KB_BL 2 2 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682IVS_I2S 2 + end + field DB_LTE 6 7 + option LTE_ABSENT 0 + option LTE_USB 1 + end + field EPS 10 10 + option PRIVACY_SCREEN_ABSENT 0 + option PRIVACY_SCREEN 1 + end +end +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "tcc_offset" = "3" # TCC of 97C + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)" + device generic 0 on + probe EPS PRIVACY_SCREEN + end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""Regulator"" + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 off end + device ref pcie_rp7 on + # Enable PCIE eMMC bridge 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE7 EMMC + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682IVS_I2S + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 2))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/banshee/Makefile.inc b/src/mainboard/google/brya/variants/banshee/Makefile.inc new file mode 100644 index 0000000000..20c6c3c22f --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += memory.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c new file mode 100644 index 0000000000..9bf6518da0 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + /* A12 : SATAXPCIE1 ==> EN_PP3300_SSD */ + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ + /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ + /* A16 : USB_OC3# ==> USB_C3_OC_ODL */ + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + + /* B0 : SOC_VID0 */ + /* B1 : SOC_VID1 */ + /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + /* B5 : ISH_I2C0_SDA ==> NC */ + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), + /* B6 : ISH_I2C0_SCL ==> NC */ + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), + /* B9 : NC */ + /* B10 : NC */ + /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ + /* B12 : SLP_S0# ==> SLP_S0_L */ + /* B13 : PLTRST# ==> PLT_RST_L */ + /* B14 : SPKR ==> GPP_B14_STRAP */ + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ + /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ + /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ + /* B19 : NC */ + /* B20 : NC */ + /* B21 : NC */ + /* B22 : NC */ + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + + /* C0 : SMBCLK ==> DDR_SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA ==> DDR_SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ + /* C6 : SML1CLK ==> USI_REPORT_EN */ + /* C7 : SML1DATA ==> USI_INT */ + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ + /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ + /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* D18 : UART1_TXD ==> USI_RST_L */ + PAD_CFG_GPO_LOCK(GPP_D18, 0, LOCK_CONFIG), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : THC0_SPI1_IO2 ==> NC */ + PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG), + /* E2 : THC0_SPI1_IO3 ==> NC */ + PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E11 : THC0_SPI1_CLK ==> NC */ + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* E12 : THC0_SPI1_IO1 ==> NC */ + PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* E13 : THC0_SPI1_IO2 ==> NC */ + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ + /* E15 : RSVD_TP ==> PCH_WP_OD */ + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPPF7_STRAP */ + /* F8 : NC */ + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + /* F10 : GPPF10_STRAP */ + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + /* F23 : NC */ + + /* H0 : GPPH0_BOOT_STRAP1 */ + /* H1 : GPPH1_BOOT_STRAP2 */ + /* H2 : GPPH2_BOOT_STRAP3 */ + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ + /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), + /* H14 : NC */ + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : NC */ + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ + /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ + /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ + /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ + /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ + /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ + /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* A12 : SATAXPCIE1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/banshee/include/variant/ec.h b/src/mainboard/google/brya/variants/banshee/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/banshee/include/variant/gpio.h b/src/mainboard/google/brya/variants/banshee/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/banshee/memory.c b/src/mainboard/google/brya/variants/banshee/memory.c new file mode 100644 index 0000000000..7371f57a70 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/memory.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool variant_is_half_populated(void) +{ + return false; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[1].addr_dimm[0] = 0x52; +} diff --git a/src/mainboard/google/brya/variants/banshee/memory/Makefile.inc b/src/mainboard/google/brya/variants/banshee/memory/Makefile.inc new file mode 100644 index 0000000000..eace2e443e --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/banshee/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/banshee/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/banshee/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/banshee/memory/mem_parts_used.txt new file mode 100644 index 0000000000..96211370d9 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb new file mode 100644 index 0000000000..08550d2542 --- /dev/null +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -0,0 +1,335 @@ +chip soc/intel/alderlake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI port + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + TEMP_PCT(70, 50), + TEMP_PCT(65, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(50, 90), + TEMP_PCT(48, 70), + TEMP_PCT(46, 60), + TEMP_PCT(43, 40), + TEMP_PCT(40, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp3 on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 off end + device ref pcie_rp8 off end + device ref pcie_rp9 off end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port4 as dfp[1].typec_port + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port9 as usb2_port + use tcss_usb3_port4 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref tcss_usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref tcss_usb3_port4 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc index 1693d2e263..8a4b2acfaa 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 76d437c694..98dd3a5fec 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,8 +17,7 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "10" # TCC of 90 # Enable CNVi BT register "CnviBtCore" = "true" @@ -44,9 +43,9 @@ chip soc/intel/alderlake register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" @@ -62,19 +61,38 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + # HD Audio register "PchHdaDspEnable" = "1" register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" register "PchHdaIDispCodecEnable" = "1" + # FIVR RFI Spread Spectrum 1.5% + register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | #+-------------------+---------------------------+ @@ -82,9 +100,12 @@ chip soc/intel/alderlake .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[3] = { + .i2c[1] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" @@ -102,10 +123,11 @@ chip soc/intel/alderlake device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "is_untrusted" = "true" device generic 0 on end end end - device ref i2c3 on + device ref i2c1 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index d9cbdb0d1d..ed0416b022 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include @@ -18,8 +18,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_A5, NONE), /* A6 : ESPI_ALERT1# ==> TP88 */ PAD_NC(GPP_A6, NONE), - /* A7 : SRCCLK_OE7# ==> NC */ - PAD_NC(GPP_A7, NONE), + /* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE), /* A8 : SRCCLKREQ7# ==> CLKREQ_7 */ PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK ==> ESPI_CLK */ @@ -29,13 +29,13 @@ static const struct pad_config gpio_table[] = { /* A12 : SATAXPCIE1 ==> CLKREQ_9B */ PAD_NC(GPP_A12, NONE), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), /* A17 : DISP_MISCC ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : DDSP_HPDB ==> HDMI_HPD */ @@ -58,17 +58,17 @@ static const struct pad_config gpio_table[] = { /* B2 : VRALERT# ==> M2_SSD_PLA_L */ PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> NC */ + PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> NC */ + PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG), /* B9 : NC */ PAD_NC(GPP_B9, NONE), /* B10 : NC */ @@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = { /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> PWM_PP3300_BUZZER */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_B14, NONE, NF1, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> TP159 */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> NC */ - PAD_NC(GPP_B16, NONE), + PAD_NC_LOCK(GPP_B16, NONE, LOCK_CONFIG), /* B17 : I2C5_SCL ==> NC */ - PAD_NC(GPP_B17, NONE), + PAD_NC_LOCK(GPP_B17, NONE, LOCK_CONFIG), /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), /* B19 : NC */ @@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_C7, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> EN_NFC_PWR */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_D4, 1, DEEP), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ @@ -136,34 +136,34 @@ static const struct pad_config gpio_table[] = { /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), + /* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */ + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */ + PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> TP97 */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> TP93 */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI(GPP_D17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : SATAXPCIE0 ==> CLKREQ_9 */ PAD_NC(GPP_E0, NONE), /* E1 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E1, NONE), + PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> NC */ - PAD_NC(GPP_E2, NONE), + PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> TP94644 */ PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ @@ -171,29 +171,29 @@ static const struct pad_config gpio_table[] = { /* E5 : SATA_DEVSLP1 ==> NC */ PAD_NC(GPP_E5, NONE), /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC(GPP_E6, NONE), + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), /* E7 : PROC_GP1 ==> TP94643 */ PAD_NC(GPP_E7, NONE), /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : THC0_SPI1_CLK ==> NC */ - PAD_NC(GPP_E11, NONE), + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> NC */ - PAD_NC(GPP_E12, NONE), + PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> NC */ - PAD_NC(GPP_E13, NONE), + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> SOC_DP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> CLKREQ_8 */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> TP102 */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_TX */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_RX_STRAP */ @@ -202,10 +202,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_RX_STRAP */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* E22 : DDPA_CTRLCLK ==> DDIA_DP_CTRLCLK */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - /* E23 : DDPA_CTRLDATA ==> DDIA_DP_CTRLDATA */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), @@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = { /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* F14 : GSXDIN ==> NC */ - PAD_NC(GPP_F14, NONE), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> TP94669 */ @@ -263,15 +263,15 @@ static const struct pad_config gpio_table[] = { /* H2 : GPPH2_BOOT_STRAP3 */ PAD_NC(GPP_H2, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H3, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : I2C1_SDA ==> NC */ - PAD_NC(GPP_H6, NONE), - /* H7 : I2C1_SCL ==> NC */ - PAD_NC(GPP_H7, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ @@ -281,9 +281,9 @@ static const struct pad_config gpio_table[] = { /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H14 : NC */ PAD_NC(GPP_H14, NONE), /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ @@ -318,9 +318,9 @@ static const struct pad_config gpio_table[] = { /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> NC */ PAD_NC(GPP_S0, NONE), @@ -371,10 +371,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -386,10 +382,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h index 43bf9513a6..2ea04eeccf 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h @@ -32,6 +32,8 @@ /* * ACPI related definitions for ASL code. */ +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c new file mode 100644 index 0000000000..9628b447b0 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/brask/ramstage.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +WEAK_DEV_PTR(dptf_policy); + +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) + +static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, + size_t *intel_idx, size_t *brask_idx) +{ + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (mchid == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) { + *intel_idx = cpuid_to_adl[i].limits; + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_adl)) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + for (i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + *brask_idx = i; + break; + } + } + + if (i == num_entries) { + printk(BIOS_ERR, "Cannot find correct brask sku index.\n"); + return false; + } + + return true; +} + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + const struct device *policy_dev; + size_t intel_idx, brask_idx; + struct drivers_intel_dptf_config *config; + struct dptf_power_limits *settings; + config_t *conf; + struct soc_power_limits_config *soc_config; + + if (!num_entries) + return; + + policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) + return; + + config = policy_dev->chip_info; + settings = &config->controls.power_limits; + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + settings->pl1.min_power = limits[brask_idx].pl1_min_power; + settings->pl1.max_power = limits[brask_idx].pl1_max_power; + settings->pl2.min_power = limits[brask_idx].pl2_min_power; + settings->pl2.max_power = limits[brask_idx].pl2_max_power; + + if (soc_config->tdp_pl2_override != 0) { + settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + settings->pl2.min_power = settings->pl2.max_power; + } + + if (soc_config->tdp_pl4 == 0) + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brask_idx].pl4_power, + MILLIWATTS_TO_WATTS); + + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4 (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); +} + +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config_psys) +{ + struct soc_power_limits_config *soc_config; + const struct device *policy_dev; + size_t intel_idx, brask_idx; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psyspl2, pl2; + u32 pl2_default; + config_t *conf; + u32 watts; + int rv; + + if (!num_entries) + return; + + policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &brask_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + soc_config->tdp_pl4 = 0; + + pl2_default = DIV_ROUND_UP(limits[brask_idx].pl2_max_power, MILLIWATTS_TO_WATTS); + rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts); + + /* Limit PL2 if the adapter is with lower capability */ + pl2 = (psyspl2 > pl2_default) ? pl2_default : psyspl2; + + soc_config->tdp_pl4 = psyspl2; + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + psyspl2 = sys_limits[brask_idx].psys_pl2_power; + pl2 = pl2_default; + } + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->PsysPmax = soc_config->psys_pmax; + + soc_config->tdp_pl2_override = pl2; + soc_config->tdp_psyspl2 = psyspl2; + + printk(BIOS_INFO, "Overriding PL2 (%u) PsysPL2 (%u) Psys_Pmax (%u)\n", + soc_config->tdp_pl2_override, + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +} diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 154f69799f..6ac796af1f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" - # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" @@ -21,9 +19,6 @@ chip soc/intel/alderlake register "tcc_offset" = "10" # TCC of 90 - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" @@ -74,6 +69,19 @@ chip soc/intel/alderlake register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" register "PchHdaIDispCodecEnable" = "1" + # FIVR RFI Spread Spectrum 1.5% + register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + + # This disables autonomous GPIO power management, otherwise old cr50 FW + # only supports short pulses and they can be missed by the PCH. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -135,30 +143,32 @@ chip soc/intel/alderlake device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" + register "is_untrusted" = "true" device generic 0 on end end end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end + device ref i2c3 on end device ref heci1 on end device ref sata on end device ref pcie_rp6 on # Enable WWAN PCIE 6 using clk 5 chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" register "srcclk_pin" = "5" - device generic 0 on end + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on end end register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, .clk_req = 5, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip drivers/pcie/generic + register "is_untrusted" = "1" + device pci 0 on end + end end #PCIE6 WWAN device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 73fad72480..b8d1761fde 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include @@ -29,13 +29,13 @@ static const struct pad_config gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_A17, 1, DEEP), /* A18 : DDSP_HPDB ==> HDMI_HPD */ @@ -56,19 +56,19 @@ static const struct pad_config gpio_table[] = { /* B1 : SOC_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), + PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG), /* B3 : PROC_GP2 ==> SAR2_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B9 : NC */ PAD_NC(GPP_B9, NONE), /* B10 : NC */ @@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = { /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), + PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */ - PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), /* B19 : NC */ @@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> WCAM_RST_L */ - PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_D4, 1, DEEP), /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ @@ -136,33 +136,33 @@ static const struct pad_config gpio_table[] = { /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */ - PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, EDGE_BOTH), + PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */ - PAD_CFG_GPI(GPP_D14, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI(GPP_D17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : see end of E group */ /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> HPS_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ @@ -170,29 +170,29 @@ static const struct pad_config gpio_table[] = { /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ PAD_CFG_GPO(GPP_E5, 1, DEEP), /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ - PAD_NC(GPP_E6, NONE), + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), /* E7 : PROC_GP1 ==> EN_HPS_PWR */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ - PAD_CFG_GPI(GPP_E10, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E11, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ - PAD_CFG_GPI(GPP_E17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ @@ -234,21 +234,21 @@ static const struct pad_config gpio_table[] = { /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ PAD_CFG_GPO(GPP_F19, 1, PLTRST), /* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */ @@ -267,7 +267,7 @@ static const struct pad_config gpio_table[] = { /* H2 : GPPH2_BOOT_STRAP3 */ PAD_NC(GPP_H2, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H3, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ @@ -285,9 +285,9 @@ static const struct pad_config gpio_table[] = { /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), + PAD_NC_LOCK(GPP_H13, UP_20K, LOCK_CONFIG), /* H14 : NC */ PAD_NC(GPP_H14, NONE), /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ @@ -387,7 +387,7 @@ static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -413,7 +413,7 @@ static const struct pad_config early_gpio_table[] = { */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h index b3465305d0..3c7fde5f54 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h @@ -43,10 +43,10 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS \ (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c index f04c97e608..bcad9b4be9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/memory.c @@ -18,48 +18,48 @@ static const struct mb_cfg baseboard_memcfg = { /* DQ byte map */ .lpx_dq_map = { .ddr0 = { - .dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, - .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, + .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, }, .ddr1 = { - .dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, - .dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, + .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, }, .ddr2 = { - .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, - .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, + .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, }, .ddr3 = { - .dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, - .dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, + .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, + .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, }, .ddr4 = { - .dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, - .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, + .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, + .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, }, .ddr5 = { - .dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, - .dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, + .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, + .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, }, .ddr6 = { - .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, - .dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, + .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, + .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, }, .ddr7 = { - .dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, - .dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, + .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, + .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, }, }, /* DQS CPU<>DRAM map */ .lpx_dqs_map = { - .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 3e0fd05105..b3a10e0a64 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -37,8 +37,40 @@ struct cpu_power_limits { unsigned int pl4_power; }; +struct system_power_limits { + uint16_t mchid; + u8 cpu_tdp; + /* PsysPL2 in Watts */ + unsigned int psys_pl2_power; +}; + +struct psys_config { + /* + * The efficiency of type-c chargers + * For example, 'efficiency = 97' means setting 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ + unsigned int efficiency; + + /* The maximum current maps to the Psys signal */ + unsigned int psys_imax_ma; + + /* The voltage of barrel jack */ + unsigned int bj_volts_mv; +}; + /* Modify Power Limit devictree settings during ramstage */ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries); + +/* + * Modify Power Limit and PsysPL devictree settings during ramstage. + * Note, this function must be called in front of calling variant_update_power_limits. + */ +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc new file mode 100644 index 0000000000..1693d2e263 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c + +romstage-y += memory.c +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb new file mode 100644 index 0000000000..91c633a3fa --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -0,0 +1,151 @@ +chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_H" + register "pmc_gpe0_dw2" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # S0ix enable + register "s0ix_enable" = "1" + + # Enable CNVi BT + register "CnviBtCore" = "true" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref heci1 on end + device ref emmc on end + device ref pcie_rp7 on + # Enable SD Card PCIE 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE7 SD card + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end + end +end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c new file mode 100644 index 0000000000..8a3ea0ee62 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A0 thru A4, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */ + /* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */ + /* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */ + /* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */ + /* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_SOC_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */ + /* A11 : GPP_A11 ==> EN_SPK_PA */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> NC */ + PAD_NC(GPP_A16, NONE), + /* A17 : NC */ + PAD_NC(GPP_A17, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> EC_SOC_HDMI_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* A23 : GPP_A23 ==> HP_INT_ODL */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), + + /* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : Not available */ + PAD_NC(GPP_B9, NONE), + /* B10 : Not available */ + PAD_NC(GPP_B10, NONE), + /* B11 : PMCALERT# ==> EN_PP3300_WLAN_X */ + PAD_CFG_GPO(GPP_B11, 1, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : NC */ + PAD_NC(GPP_B15, NONE), + /* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : GPP_B18 ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : Not available */ + PAD_NC(GPP_B19, NONE), + /* B20 : Not available */ + PAD_NC(GPP_B20, NONE), + /* B21 : Not available */ + PAD_NC(GPP_B21, NONE), + /* B22 : Not available */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> EN_PP3300_UCAM_X */ + PAD_CFG_GPO(GPP_C3, 1, DEEP), + /* C4 : NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> GPP_C5_STRAP */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), + /* C7 : SML1DATA ==> TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + + /* D0 : NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ + PAD_NC(GPP_D10, NONE), + /* D11 : NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D13 : NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + /* D17 : NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : NC */ + PAD_NC(GPP_D18, NONE), + /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : PROC_GP0 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E4 : NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : NC */ + PAD_NC(GPP_E9, NONE), + /* E10 : NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : NC */ + PAD_NC(GPP_E11, NONE), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E13 : NC */ + PAD_NC(GPP_E13, NONE), + /* E14 : DDSP_HPDA ==> EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WLAN_WWAN_COEX_3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPP_F7 ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : Not available */ + PAD_NC(GPP_F8, NONE), + /* F9 : Not available */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> GPP_F10_STRAP */ + PAD_NC(GPP_F10, NONE), + /* F11 : NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), + /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI(GPP_F15, NONE, DEEP, EDGE_SINGLE, NONE), + /* F16 : NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ + PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F19 : Not available */ + PAD_NC(GPP_F19, NONE), + /* F20 : Not available */ + PAD_NC(GPP_F20, NONE), + /* F21 : Not available */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPP_H0_STRAP */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPP_H1_STRAP */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPP_H2_STRAP */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : CNV_MFUART2_RXD ==> WLAN_WWAN_COEX_1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : CNV_MFUART2_TXD ==> WLAN_WWAN_COEX_2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : Not available */ + PAD_NC(GPP_H14, NONE), + /* H15 : NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : Not available */ + PAD_NC(GPP_H16, NONE), + /* H17 : NC */ + PAD_NC(GPP_H17, NONE), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : SRCCLKREQ4# ==> SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : I2S0_SCLK ==> I2S_HP_BCLK_R */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S0_SFRM ==> I2S_HP_LRCK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S0_TXD ==> I2S_HP_AUDIO_STRAP */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* R3 : I2S0_RXD ==> I2S_HP_MIC */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : DMIC_CLK_A_0A ==> DMIC_UCAM_CLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : DMIC_DATA_0A ==> DMIC_UCAM_DATA */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : I2S1_SCLK ==> I2S_SPK_BCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : I2S1_SFRM ==> I2S_SPK_LRCK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : I2S1_TXD ==> I2S_SPK_AUDIO_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : I2S1_RXD ==> NC */ + PAD_NC(GPP_S3, NONE), + /* S4 : NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : NC */ + PAD_NC(GPP_S7, NONE), + + /* I5 : NC */ + PAD_NC(GPP_I5, NONE), + /* I7 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* I8 : EMMC_DATA0 ==> EMMC_D0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* I9 : EMMC_DATA1 ==> EMMC_D1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* I10 : EMMC_DATA2 ==> EMMC_D2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* I11 : EMMC_DATA3 ==> EMMC_D3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* I12 : EMMC_DATA4 ==> EMMC_D4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* I13 : EMMC_DATA5 ==> EMMC_D5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* I14 : EMMC_DATA6 ==> EMMC_D6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* I15 : EMMC_DATA7 ==> EMMC_D7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* I16 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* I17 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* I18 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* GPD0 : BATLOW# ==> SOC_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1 : ACPRESENT ==> SOC_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2 : EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT), + /* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4 : SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5 : SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6 : SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD7 : GPD7_STRAP */ + PAD_NC(GPD7, NONE), + /* GPD8 : SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9 : NC */ + PAD_NC(GPD9, NONE), + /* GPD10 : SLP_S5# ==> NC */ + PAD_NC(GPD10, NONE), + /* GPD11 : NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *__weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + +const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h new file mode 100644 index 0000000000..fa5af03754 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. AC Connect/Disconnect + * 4. Key press + * 5. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable Keyboard Backlight */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h new file mode 100644 index 0000000000..068aaa4835 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */ +#define GPE_EC_WAKE GPE0_DW2_17 +/* WP signal to PCH */ +#define GPIO_PCH_WP GPP_E12 +/* EC in RW or RO */ +#define GPIO_EC_IN_RW GPP_F18 +/* GPIO IRQ for tight timestamps */ +#define EC_SYNC_IRQ GPD2_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/memory.c b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c new file mode 100644 index 0000000000..b74d3345ff --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/memory.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc index d38141ca24..c15531e21d 100644 --- a/src/mainboard/google/brya/variants/brask/Makefile.inc +++ b/src/mainboard/google/brya/variants/brask/Makefile.inc @@ -4,3 +4,7 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/brask/fw_config.c b/src/mainboard/google/brya/variants/brask/fw_config.c new file mode 100644 index 0000000000..5302923cd2 --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/fw_config.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable BT offload audio related GPIO pins.\n"); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) { + printk(BIOS_INFO, "BT offload enabled over I2S with NAU88L25B\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } + +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c index a23135bc90..c99115e524 100644 --- a/src/mainboard/google/brya/variants/brask/gpio.c +++ b/src/mainboard/google/brya/variants/brask/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { @@ -12,10 +11,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -27,12 +22,16 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ @@ -41,26 +40,26 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_H13, 1, DEEP), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666cd5..17c9e86a3e 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO 0 2 + option AUDIO_UNKNOWN 0 + option NAU88L25B_I2S 1 + end +end + chip soc/intel/alderlake device domain 0 on device ref dtt on @@ -79,11 +86,22 @@ chip soc/intel/alderlake device generic 0 alias dptf_policy on end end end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tcss_dma0 on @@ -161,18 +179,18 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c new file mode 100644 index 0000000000..c2a5ec3818 --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/ramstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 55000, 55000, 123000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_10, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 135 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_4, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 230 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 230 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in brask, the serial shunt resistor is 0.005ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 13.52A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v = (0.005ohm x 13.52A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.47 = 15K / (15K + 16.9K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 13.52A = 202.8W + * For Type-C 20V, the Psys_pmax should be 20v x 13.52A = 270.4W + * For a barrel jack, the Psys_pmax should be 19.5v x 13.52A = 263.6W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 270.4W. Then IMVP9.1 can calculate the current system + * power = 270.4W * 5A / 13.52A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 13520, + .bj_volts_mv = 19500 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brya/variants/brask/variant.c b/src/mainboard/google/brya/variants/brask/variant.c new file mode 100644 index 0000000000..8e3578c84b --- /dev/null +++ b/src/mainboard/google/brya/variants/brask/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S)); +} diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index c3cfc0c3d4..4cf99df49f 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -2,13 +2,15 @@ #include #include -#include #include -#include static const struct pad_config board_id0_1_overrides[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ PAD_NC(GPP_B15, NONE), /* C3 : SML0CLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index f3b7925dd7..9f3e0285a6 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -43,6 +43,11 @@ chip soc/intel/alderlake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + # Enable CNVi DDR RFIM + register "CnviDdrRfim" = "1" + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ @@ -187,6 +192,17 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end device ref tcss_dma0 on chip drivers/intel/usb4/retimer @@ -320,7 +336,7 @@ chip soc/intel/alderlake register "nvm_size" = "0x2800" register "nvm_pagesize" = "0x01" register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" + register "nvm_width" = "0x10" device i2c 58 on end end @@ -520,18 +536,19 @@ chip soc/intel/alderlake end end chip drivers/intel/mipi_camera - register "acpi_hid" = ""INT3499"" + register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID"" register "acpi_uid" = "1" register "acpi_name" = ""NVM1"" register "chip_name" = ""GT24C16S"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" - register "nvm_size" = "0x2800" + register "nvm_size" = "0x800" register "nvm_pagesize" = "0x01" register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" + register "nvm_width" = "0x08" device i2c 50 on probe UFC UFC_MIPI_IMX208 @@ -551,7 +568,13 @@ chip soc/intel/alderlake end end end - device ref i2c3 on end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -617,18 +640,18 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn2 on end end end @@ -640,19 +663,22 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -664,19 +690,22 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -691,16 +720,11 @@ chip soc/intel/alderlake probe UFC UFC_USB end end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb2_port8 on end - end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -713,15 +737,10 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb3_port2 on end - end chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" diff --git a/src/mainboard/google/brya/variants/brya4es/Makefile.inc b/src/mainboard/google/brya/variants/brya4es/Makefile.inc new file mode 100644 index 0000000000..52d03980da --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/brya4es/fw_config.c b/src/mainboard/google/brya/variants/brya4es/fw_config.c new file mode 100644 index 0000000000..17d284aa29 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/fw_config.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +static const struct pad_config sndw_enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), /* SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */ +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), +}; + +static const struct pad_config i2s0_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ +}; + +static const struct pad_config i2s2_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s0_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), +}; + +static const struct pad_config i2s2_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void enable_i2s(void) +{ + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); +} + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) { + printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } else { + printk(BIOS_INFO, "BT offload disabled\n"); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); + enable_i2s(); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_NAU88L25B_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n"); + enable_i2s(); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya4es/gpio.c b/src/mainboard/google/brya/variants/brya4es/gpio.c new file mode 100644 index 0000000000..4cf99df49f --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/gpio.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct pad_config board_id0_1_overrides[] = { + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), + /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), + /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_F19, UP_20K, DEEP), + /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ + PAD_NC(GPP_F21, NONE), + /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), + /* GPD2: LAN_WAKE# ==> NC */ + PAD_NC(GPD2, NONE), +}; + +/* Early pad configuration in bootblock for board id < 2 */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), +}; + +/* Early pad configuration in bootblock for board id 2 */ +static const struct pad_config early_gpio_table_id2[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + const uint32_t id = board_id(); + if (id == BOARD_ID_UNKNOWN || id < 2) { + *num = ARRAY_SIZE(board_id0_1_overrides); + return board_id0_1_overrides; + } + + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + const uint32_t id = board_id(); + if (id == BOARD_ID_UNKNOWN || id < 2) { + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; + } + + *num = ARRAY_SIZE(early_gpio_table_id2); + return early_gpio_table_id2; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h b/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h new file mode 100644 index 0000000000..23338de2d8 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc new file mode 100644 index 0000000000..70c8d17adb --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/memory/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/brya0/memory src/mainboard/google/brya/variants/brya0/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 3(0b0011) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..bfc1ead13f --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/brya0/memory src/mainboard/google/brya/variants/brya0/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:F 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +MT53E2G32D4NQ-046 WT:A 2 (0010) +H9HCNNNCPMMLXR-NEE 3 (0011) +MT53E1G32D2NP-046 WT:B 3 (0011) diff --git a/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..c8a24ccd6d --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:F +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +MT53E2G32D4NQ-046 WT:A +H9HCNNNCPMMLXR-NEE +MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb new file mode 100644 index 0000000000..13d028ea69 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -0,0 +1,749 @@ +fw_config + field DB_USB 0 3 + option USB_ABSENT 0 + option USB3_PS8815 1 + end + field DB_SD 4 5 + option SD_ABSENT 0 + option SD_GL9755S 1 + end + field KB_BL 7 7 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 8 10 + option AUDIO_UNKNOWN 0 + option MAX98357_ALC5682I_I2S 1 + option MAX98373_ALC5682_SNDW 2 + option MAX98373_NAU88L25B_I2S 3 + option ALC1019_NAU88L25B_I2S 4 + end + field DB_LTE 11 12 + option LTE_ABSENT 0 + option LTE_USB 1 + option LTE_PCIE 2 + end + field UFC 13 14 + option UFC_USB 0 + option UFC_MIPI_IMX208 1 + end + # Bits 15 and 16 were intended for WFC but never declared here + field HPS 17 17 + option HPS_ABSENT 0 + option HPS_PRESENT 1 + end +end + +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + + register "PsysPmax" = "145" + + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + TEMP_PCT(70, 50), + TEMP_PCT(65, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(50, 90), + TEMP_PCT(48, 70), + TEMP_PCT(46, 60), + TEMP_PCT(43, 40), + TEMP_PCT(40, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on + # MIPI lanes are split between UFC and WFC depending on + # whether the UFC is USB or MIPI hence probing UFC_USB + probe UFC UFC_USB + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 1 on + probe UFC UFC_MIPI_IMX208 + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on + probe AUDIO ALC1019_NAU88L25B_I2S + end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 1 on + probe AUDIO ALC1019_NAU88L25B_I2S + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x10" + + device i2c 58 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR1 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on end + end + chip drivers/i2c/sx9324 + register "desc" = ""SAR2 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "2" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 2C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3478"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""imx 208 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "2" + register "link_freq[0]" = "384 * MHz" # 384 MHz + register "link_freq[1]" = "96 * MHz" # 96 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset + register "gpio_panel.gpio[3].gpio_num" = "GPP_H21" #CLK_EN + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(3, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(3, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on + probe UFC UFC_MIPI_IMX208 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""ACPI_DT_NAMESPACE_HID"" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM1"" + register "chip_name" = ""GT24C16S"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x08" + + device i2c 50 on + probe UFC UFC_MIPI_IMX208 + end + end + chip drivers/i2c/generic + register "hid" = ""GOOG0020"" + register "desc" = ""Chrome OS HPS"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL + # HPS uses I2C addresses 0x30 and 0x51. + # The address we provide here is not significant because + # neither coreboot nor Linux have a driver for HPS, + # it's only used from userspace. + device i2c 30 on + probe HPS HPS_PRESENT + end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 2.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 2.7 on end + end + end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + probe UFC UFC_USB + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/brya4es/ramstage.c b/src/mainboard/google/brya/variants/brya4es/ramstage.c new file mode 100644 index 0000000000..06040e485f --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/ramstage.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brya/variants/brya4es/variant.c b/src/mainboard/google/brya/variants/brya4es/variant.c new file mode 100644 index 0000000000..8d4471ba2e --- /dev/null +++ b/src/mainboard/google/brya/variants/brya4es/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); +} diff --git a/src/mainboard/google/brya/variants/crota/include/variant/ec.h b/src/mainboard/google/brya/variants/crota/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/crota/include/variant/gpio.h b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/crota/memory/Makefile.inc b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc new file mode 100644 index 0000000000..68c56c9c2a --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/crota/memory src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt new file mode 100644 index 0000000000..a61fae8a39 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/crota/memory src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +H9JCNNNCP3MLYR-N6E 0 (0000) +K3LKBKB0BM-MGCP 2 (0010) diff --git a/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt new file mode 100644 index 0000000000..d51ce0eaef --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory/mem_parts_used.txt @@ -0,0 +1,16 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +H9JCNNNCP3MLYR-N6E +K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/felwinter/gpio.c b/src/mainboard/google/brya/variants/felwinter/gpio.c index d30dd21f4f..26af4abd8f 100644 --- a/src/mainboard/google/brya/variants/felwinter/gpio.c +++ b/src/mainboard/google/brya/variants/felwinter/gpio.c @@ -4,40 +4,39 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { /* A7 : SRCCLK_OE7# ==> PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, NONE, DEEP), /* A8 : SRCCLKREQ7# ==> PEN_DET_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_A8, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI_HIGH(GPP_A8, NONE, DEEP, EDGE_SINGLE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* B6 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> EN_PP5000_PEN */ PAD_CFG_GPO(GPP_C4, 1, DEEP), /* D0 : ISH_GP0 ==> NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : ISH_GP1 ==> NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : ISH_GP2 ==> NC */ - PAD_NC(GPP_D2, NONE), + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E3 : PROC_GP0 ==> NC */ @@ -45,13 +44,13 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E9 : USB_OC0# ==> NC */ - PAD_NC(GPP_E9, NONE), + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> NC */ PAD_NC(GPP_E18, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ @@ -61,19 +60,23 @@ static const struct pad_config override_gpio_table[] = { /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), /* F11 : THC1_SPI2_CLK ==> NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> NC */ - PAD_NC(GPP_F12, NONE), + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13 : GSXDOUT ==> NC */ - PAD_NC(GPP_F13, NONE), + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F15 : GSXSRESET# ==> NC */ - PAD_NC(GPP_F15, NONE), + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), /* F16 : GSXCLK ==> NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ @@ -115,10 +118,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ diff --git a/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc index 22436b612a..56c4f4f4c9 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/felwinter/memory/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +# util/spd_tools/src/part_id_gen/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt index abfd12d7a0..927bd60bae 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/felwinter/memory/dram_id.generated.txt @@ -1,10 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +# util/spd_tools/src/part_id_gen/part_id_gen ADL lp4x src/mainboard/google/brya/variants/felwinter/memory src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt index 89792ed712..7aadba9dbd 100644 --- a/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/felwinter/memory/mem_parts_used.txt @@ -2,3 +2,4 @@ K4U6E3S4AA-MGCR K4UBE3D4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A +MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 0fa2e616d9..d1842764f3 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -4,10 +4,19 @@ fw_config option USB3_PS8815 1 option USB4_KB8001 2 end + field STYLUS 5 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end + field AUDIO_AMP 7 9 + option UNPROVISIONED 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682VS_I2S_2WAY 2 + end end chip soc/intel/alderlake - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. @@ -15,6 +24,7 @@ chip soc/intel/alderlake .configure_ext_fivr = 1, }" + register "usb2_ports[0]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_EMPTY" @@ -34,9 +44,146 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 550, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on - device ref dtt on end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(44, 76), + TEMP_PCT(40, 65), + TEMP_PCT(36, 53), + TEMP_PCT(32, 41), + TEMP_PCT(28, 29), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(44, 76), + TEMP_PCT(40, 65), + TEMP_PCT(36, 53), + TEMP_PCT(32, 41), + TEMP_PCT(28, 29), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 13000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_KB8001 + end + device ref tbt_pcie_rp2 on + probe DB_USB USB4_KB8001 + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -44,6 +191,7 @@ chip soc/intel/alderlake end end device ref tcss_dma0 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port2 as dfp[0].typec_port @@ -51,14 +199,14 @@ chip soc/intel/alderlake end end device ref tcss_dma1 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on - probe DB_USB USB4_KB8001 - end + device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" @@ -78,12 +226,35 @@ chip soc/intel/alderlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_AMP MAX98360_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_AMP MAX98360_ALC5682VS_I2S_2WAY + end end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C1 + device ref i2c3 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN9050"" + register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" @@ -98,11 +269,25 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end - end - device ref i2c3 on end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)" + register "key.wake_gpe" = "GPE0_DW0_08" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end + end #I2C3 device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -112,7 +297,7 @@ chip soc/intel/alderlake register "probed" = "1" device i2c 15 on end end - end + end #I2C5 device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98360A"" @@ -123,10 +308,9 @@ chip soc/intel/alderlake end end device ref pch_espi on - #TBD, felwinter remove typeC port0 chip ec/google/chromeec use conn1 as mux_conn[1] - use conn2 as mux_conn[2] + use conn2 as mux_conn[0] device pnp 0c09.0 on end end end @@ -134,14 +318,14 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" - device generic 1 alias conn1 on end + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" - device generic 2 alias conn2 on end + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end end end end @@ -152,13 +336,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -170,13 +356,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -187,7 +375,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -200,7 +389,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index 9234019952..8b270de04e 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -3,11 +3,18 @@ #include #include #include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) { config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19; config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20; + config->TcssAuxOri = 0x10; } } diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index 505a9a613e..12c2df561c 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -28,11 +27,11 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> NC */ - PAD_NC(GPP_B5, NONE), + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> NC */ - PAD_NC(GPP_B6, NONE), + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -40,17 +39,17 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_C4, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), /* D9 : ISH_SPI_CS# ==> NC */ - PAD_NC(GPP_D9, NONE), + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -61,11 +60,11 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> NC */ PAD_NC(GPP_E18, NONE), /* E20 : DDP2_CTRLCLK ==> NC */ @@ -80,10 +79,16 @@ static const struct pad_config override_gpio_table[] = { /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H15 : DDPB_CTRLCLK ==> NC */ PAD_NC(GPP_H15, NONE), /* H17 : DDPB_CTRLDATA ==> NC*/ @@ -117,10 +122,10 @@ static const struct pad_config early_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA_P2 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL_P2 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -150,12 +155,14 @@ static const struct pad_config early_gpio_table[] = { /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_NC(GPP_H13, UP_20K), + PAD_CFG_GPO(GPP_H13, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc index 187d4c9697..9db94849fc 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/gimble/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt index 02c1019fe7..c3a1347f74 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt @@ -10,3 +10,5 @@ H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt index 7cb0e233af..568e7246a4 100644 --- a/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt @@ -4,3 +4,5 @@ H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4U6E3S4AA-MGCR K4UBE3D4AA-MGCR +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 8448594c1e..0d8b49b47e 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -21,24 +21,54 @@ fw_config end end chip soc/intel/alderlake - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "143" register "TcssAuxOri" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio and WFC | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | SAR0 | + #| I2C3 | Touchscreen | + #| | | + #| | | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -62,7 +92,7 @@ chip soc/intel/alderlake }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, + .min_power = 12000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, @@ -92,6 +122,7 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" @@ -135,7 +166,7 @@ chip soc/intel/alderlake register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_R"" register "vmon_slot_no" = "0" register "imon_slot_no" = "1" device i2c 0x38 on @@ -147,7 +178,7 @@ chip soc/intel/alderlake register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_L"" register "vmon_slot_no" = "1" register "imon_slot_no" = "0" device i2c 0x3c on @@ -155,6 +186,13 @@ chip soc/intel/alderlake end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -162,7 +200,7 @@ chip soc/intel/alderlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" @@ -171,6 +209,7 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x15 on end end @@ -207,13 +246,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "3" + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -225,13 +264,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -243,13 +284,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi @@ -261,7 +304,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi @@ -274,7 +318,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port2 on end end end diff --git a/src/mainboard/google/brya/variants/gimble4es/Makefile.inc b/src/mainboard/google/brya/variants/gimble4es/Makefile.inc new file mode 100644 index 0000000000..446d113a80 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/gimble4es/fw_config.c b/src/mainboard/google/brya/variants/gimble4es/fw_config.c new file mode 100644 index 0000000000..e9d87b33d8 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/fw_config.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_SSP1))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/gimble4es/gpio.c b/src/mainboard/google/brya/variants/gimble4es/gpio.c new file mode 100644 index 0000000000..a4ed7fb60b --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/gpio.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + /* B5 : ISH_I2C0_SDA ==> NC */ + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), + /* B6 : ISH_I2C0_SCL ==> NC */ + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC*/ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc new file mode 100644 index 0000000000..9db94849fc --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/memory/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..c3a1347f74 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/memory/dram_id.generated.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/gimble/memory src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNCPMMLXR-NEE 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +K4U6E3S4AA-MGCR 0 (0000) +K4UBE3D4AA-MGCR 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..568e7246a4 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/memory/mem_parts_used.txt @@ -0,0 +1,8 @@ +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4U6E3S4AA-MGCR +K4UBE3D4AA-MGCR +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb new file mode 100644 index 0000000000..1ab9a7e6be --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb @@ -0,0 +1,297 @@ +fw_config + field DB_USB 0 3 + option USB_ABSENT 0 + option USB3_PS8815 1 + end + field DB_SD 4 5 + option SD_ABSENT 0 + option SD_GL9750H 1 + end + field KB_BL 7 7 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 8 10 + option AUDIO_UNKNOWN 0 + option MAX98390_ALC5682I_I2S 1 + option MAX98390_ALC5682I_I2S_SSP1 2 + end + field DB_LTE 11 12 + option LTE_ABSENT 0 + end +end +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "143" + register "TcssAuxOri" = "1" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Fan"" + register "options.tsr[2].desc" = ""Charger"" + # TODO: below values are initial reference values only + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 12000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 alias dptf_policy on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98390_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98390_ALC5682I_I2S_SSP1 + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 0"" + register "uid" = "0" + register "name" = ""MXW0"" + register "r0_calib_key" = ""dsm_calib_r0_0"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" + register "dsm_param_file_name" = ""dsm_param_R"" + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + device i2c 0x38 on + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 1"" + register "uid" = "1" + register "name" = ""MXW1"" + register "r0_calib_key" = ""dsm_calib_r0_1"" + register "temperature_calib_key" = ""dsm_calib_temp_1"" + register "dsm_param_file_name" = ""dsm_param_L"" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" + device i2c 0x3c on + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 0x15 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port2 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/gimble4es/variant.c b/src/mainboard/google/brya/variants/gimble4es/variant.c new file mode 100644 index 0000000000..96ccf88ae7 --- /dev/null +++ b/src/mainboard/google/brya/variants/gimble4es/variant.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98390_ALC5682I_I2S_SSP1)); +} diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index 9ea19ded56..66dcf7e1ac 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -6,3 +6,4 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index 55a6fad7c6..631a908a9b 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -8,8 +8,8 @@ static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ }; static const struct pad_config dmic_disable_pads[] = { @@ -24,10 +24,10 @@ static const struct pad_config i2s_enable_pads[] = { PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ }; static const struct pad_config i2s_disable_pads[] = { diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index 6f40da1fc5..8ef3c39a0f 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -28,15 +27,21 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), + /* D16 : ISH_UART0_CTS# ==> PEN_PWR_EN */ + PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG), + /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> NC */ - PAD_NC(GPP_D18, NONE), + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -45,9 +50,9 @@ static const struct pad_config override_gpio_table[] = { /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ @@ -58,14 +63,18 @@ static const struct pad_config override_gpio_table[] = { /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H12 : I2C7_SDA ==> NC */ - PAD_NC(GPP_H12, NONE), + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : I2C7_SCL ==> NC */ - PAD_NC(GPP_H13, NONE), + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H20 : IMGCLKOUT1 ==> NC */ @@ -82,18 +91,18 @@ static const struct pad_config override_gpio_table[] = { /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), @@ -105,10 +114,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -130,32 +135,36 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* CPU PCIe VGPIO for PEG60 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index e650042549..05c688acf5 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -11,20 +11,21 @@ fw_config option UFC_USB 0 option UFC_MIPI_OVTI2740 1 end + field STYLUS 6 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - # This disabled autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_D" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN # FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. @@ -38,20 +39,37 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | SAR0 | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | SAR0 | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = 390000, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" # TODO: below values are initial reference values only ## Active Policy @@ -60,37 +78,55 @@ chip soc/intel/alderlake .target = DPTF_CPU, .thresholds = { TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), } } }" ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 15000, + .min_power = 18000, + .max_power = 28000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, @@ -146,6 +182,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref tcss_dma0 on @@ -215,24 +252,10 @@ chip soc/intel/alderlake end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN90FC"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end end device ref i2c2 on @@ -345,6 +368,7 @@ chip soc/intel/alderlake register "num_freq_entries" = "1" register "link_freq[0]" = "360 * MHz" register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" #Controls register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" @@ -377,8 +401,6 @@ chip soc/intel/alderlake register "chip_name" = ""AT24 EEPROM"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" @@ -390,7 +412,43 @@ chip soc/intel/alderlake end end end - device ref i2c3 on end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + # GPP_D6 is the IRQ source, and GPP_D17 is the wake source + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)" + register "key.wake_gpe" = "GPE0_DW1_17" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end + end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -435,13 +493,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -453,13 +511,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -471,13 +531,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -490,7 +552,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -503,7 +566,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c new file mode 100644 index 0000000000..9b26cbb0f2 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brya/variants/kinox/include/variant/ec.h b/src/mainboard/google/brya/variants/kinox/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/kinox/include/variant/gpio.h b/src/mainboard/google/brya/variants/kinox/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/moli/include/variant/ec.h b/src/mainboard/google/brya/variants/moli/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/moli/include/variant/gpio.h b/src/mainboard/google/brya/variants/moli/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc new file mode 100644 index 0000000000..defb592f2f --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nereid/gpio.c b/src/mainboard/google/brya/variants/nereid/gpio.c new file mode 100644 index 0000000000..0f68ecf3b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/gpio.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + + /* B5 : SOC_I2C_SUB_SDA */ + PAD_NC(GPP_B5, NONE), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_NC(GPP_B6, NONE), + + /* D3 : WCAM_RST_L */ + PAD_NC(GPP_D3, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* D15 : EN_PP2800_WCAM_X */ + PAD_NC(GPP_D15, NONE), + /* D16 : EN_PP1800_PP1200_WCAM_X */ + PAD_NC(GPP_D16, NONE), + + /* F12 : WWAN_RST_L */ + PAD_NC(GPP_F12, NONE), + + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H22 : WCAM_MCLK_R */ + PAD_NC(GPP_H22, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/nereid/include/variant/ec.h b/src/mainboard/google/brya/variants/nereid/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h b/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/nereid/memory.c b/src/mainboard/google/brya/variants/nereid/memory.c new file mode 100644 index 0000000000..0453cf1748 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) + return 0; + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc new file mode 100644 index 0000000000..05d428a04e --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt new file mode 100644 index 0000000000..ad17e8d829 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nereid/memory src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3LKBKB0BM-MGCP 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) diff --git a/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt new file mode 100644 index 0000000000..49183d72b3 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/memory/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +K3LKBKB0BM-MGCP +H9JCNNNBK3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb new file mode 100644 index 0000000000..add5e213f4 --- /dev/null +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -0,0 +1,186 @@ +fw_config + field DB_USB 0 1 + option DB_NONE 0 + option DB_1C_1A 1 + option DB_1A_HDMI 3 + end +end + +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC + + device domain 0 on + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/nivviks/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/Makefile.inc new file mode 100644 index 0000000000..4e128435f7 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nivviks/fw_config.c b/src/mainboard/google/brya/variants/nivviks/fw_config.c new file mode 100644 index 0000000000..c475ca3fe2 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/fw_config.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC(GPP_F12, NONE), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n"); + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c new file mode 100644 index 0000000000..e12356754b --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> I2S_SPK_AUDIO_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + /* S0 : NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC_CKL_A_0 ==> DMIC_UCAM_CLK_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : DMIC_DATA_0 ==> DMIC_UCAM_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S6 : DMIC_CLK_A_1 ==> DMIC_WCAM_CLK_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : DMIC_DATA_1 ==> DMIC_WCAM_DATA */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h b/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h new file mode 100644 index 0000000000..c96b01fc15 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + +#endif diff --git a/src/mainboard/google/brya/variants/nivviks/memory.c b/src/mainboard/google/brya/variants/nivviks/memory.c new file mode 100644 index 0000000000..0453cf1748 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +int variant_memory_sku(void) +{ + /* + * The memory straps in the P0 build don't match those generated by + * spd_tools, so override the memory ID to 0. + */ + if (board_id() == 0) + return 0; + + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E3 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc new file mode 100644 index 0000000000..3fb4d48a68 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt new file mode 100644 index 0000000000..9a239f86f2 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/nivviks/memory src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt new file mode 100644 index 0000000000..3769843357 --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/memory/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb new file mode 100644 index 0000000000..194b26fa3e --- /dev/null +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -0,0 +1,330 @@ +fw_config + field DB_USB 0 1 + option DB_NONE 0 + option DB_1C_1A 1 + option DB_1C_LTE 2 + end +end + +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + device domain 0 on + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x12" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + device i2c 28 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "20" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port2 on + probe DB_USB DB_1C_1A + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/primus/Makefile.inc b/src/mainboard/google/brya/variants/primus/Makefile.inc index 129a2938e3..725b883fba 100644 --- a/src/mainboard/google/brya/variants/primus/Makefile.inc +++ b/src/mainboard/google/brya/variants/primus/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/primus/fw_config.c b/src/mainboard/google/brya/variants/primus/fw_config.c index 0beedc7941..c9b4a38be5 100644 --- a/src/mainboard/google/brya/variants/primus/fw_config.c +++ b/src/mainboard/google/brya/variants/primus/fw_config.c @@ -80,5 +80,12 @@ static void fw_config_handle(void *unused) gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I-VS.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index ba423fc73c..4b6b40e8c3 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -21,39 +20,47 @@ static const struct pad_config override_gpio_table[] = { /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ PAD_NC(GPP_C4, NONE), - /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ - PAD_CFG_GPO(GPP_D3, 1, PLTRST), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D6 : SRCCLKREQ1# ==> NC */ PAD_NC(GPP_D6, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ - PAD_CFG_GPO(GPP_D14, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ - PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H21 : IMGCLKOUT2 ==> NC */ @@ -81,10 +88,12 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -108,6 +117,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ PAD_CFG_GPO(GPP_F21, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ @@ -118,16 +129,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), - /* B4 : PROC_GP3 ==> SSD_PERST_L - * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the - * power rails take some time to come up. - */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ PAD_CFG_GPO(GPP_F21, 1, DEEP), }; diff --git a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc index d2fae296db..aea043ecbb 100644 --- a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267 SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9HCNNNFAMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR, H54G56CYRBX247 diff --git a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt index cdaaac01c6..9e6b4d9185 100644 --- a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt @@ -11,3 +11,5 @@ K4U6E3S4AA-MGCR 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) MT53E1G32D2NP-046 WT:B 2 (0010) K4UBE3D4AA-MGCR 2 (0010) +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 2 (0010) diff --git a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt index bb14464356..3c57865c0c 100644 --- a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt @@ -5,3 +5,5 @@ K4U6E3S4AA-MGCR MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B K4UBE3D4AA-MGCR +H54G46CYRBX267 +H54G56CYRBX247 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c4debb49da..36fee91a3d 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -14,6 +14,7 @@ fw_config field AUDIO 8 10 option AUDIO_UNKNOWN 0 option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682I_VS_I2S 2 end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -22,9 +23,14 @@ fw_config end chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -32,11 +38,11 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -44,14 +50,20 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, }, .i2c[1] = { + .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, .i2c[3] = { - .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, @@ -68,21 +80,32 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""SSD"" + register "options.tsr[2].desc" = ""CHARGER"" + register "options.tsr[3].desc" = ""MEMORY"" + register "options.tsr[4].desc" = ""TYPEC"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), + [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), + }" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), }" register "controls.power_limits" = "{ @@ -91,7 +114,7 @@ chip soc/intel/alderlake .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, + .granularity = 250, }, .pl2 = { .min_power = 55000, @@ -119,6 +142,11 @@ chip soc/intel/alderlake end end device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "srcclk_pin" = "6" + device generic 0 alias emmc_rtd3 on end + end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 6, @@ -168,12 +196,20 @@ chip soc/intel/alderlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on + device i2c 1a alias audio_codec on probe AUDIO MAX98360_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_VS_I2S end end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -190,6 +226,7 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x10 on end end @@ -205,6 +242,7 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 0x40 on end end @@ -236,6 +274,7 @@ chip soc/intel/alderlake register "sdmode_delay" = "5" device generic 0 on probe AUDIO MAX98360_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_VS_I2S end end end @@ -261,13 +300,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -279,13 +318,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -297,13 +338,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -319,13 +362,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -338,13 +383,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c new file mode 100644 index 0000000000..90999ec223 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/variant.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void devtree_update_emmc_rtd3(uint32_t board_ver) +{ + struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3); + if (board_ver > 1) + return; + + emmc_rtd3->enabled = 0; +} + +static void devtree_update_audio_codec(void) +{ + struct device *audio_codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config = audio_codec->chip_info; + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) + config->hid = "RTL5682"; +} + +static const struct pad_config nvme_disable_pads[] = { + PAD_NC(GPP_B2, NONE), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B4, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_NC(GPP_D3, NONE), /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ + PAD_NC(GPP_D5, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_NC(GPP_D11, NONE), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ +}; + +static const struct pad_config emmc_disable_pads[] = { + PAD_NC(GPP_B3, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ + PAD_NC(GPP_E20, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_NC(GPP_F19, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ +}; + +static void disable_unused_gpios(void) +{ + int emmc_detected = gpio_get(GPP_T2); + + if (emmc_detected == 1) + gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); + else + gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); +} + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + disable_unused_gpios(); + devtree_update_emmc_rtd3(board_ver); + devtree_update_audio_codec(); +} diff --git a/src/mainboard/google/brya/variants/primus4es/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/Makefile.inc new file mode 100644 index 0000000000..725b883fba --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/primus4es/fw_config.c b/src/mainboard/google/brya/variants/primus4es/fw_config.c new file mode 100644 index 0000000000..c9b4a38be5 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/fw_config.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I-VS.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c new file mode 100644 index 0000000000..c5b6708c60 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> eMMC_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), + + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* T2 : GPP_T2 ==> eMMC_CFG */ + PAD_CFG_GPI(GPP_T2, NONE, DEEP), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, PLTRST), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h new file mode 100644 index 0000000000..7309098359 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +/* Enable PS/2 Mouse */ +#define SIO_EC_ENABLE_PS2M + +#endif diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h new file mode 100644 index 0000000000..cbf6040265 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + +#endif diff --git a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc new file mode 100644 index 0000000000..d2fae296db --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..cdaaac01c6 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +H9HCNNNFAMMLXR-NEE 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4U6E3S4AA-MGCR 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..bb14464356 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt @@ -0,0 +1,7 @@ +H9HCNNNBKMMLXR-NEE +H9HCNNNFAMMLXR-NEE +H9HCNNNCPMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb new file mode 100644 index 0000000000..77218b09d5 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -0,0 +1,400 @@ +fw_config + field DB_USB 0 3 + option USB_ABSENT 0 + option USB3_PS8811 1 + end + field DB_SD 4 5 + option SD_ABSENT 0 + option SD_GL9755S 1 + end + field KB_BL 7 7 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 8 10 + option AUDIO_UNKNOWN 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682I_VS_I2S 2 + end + field DB_LTE 11 12 + option LTE_ABSENT 0 + option LTE_USB 1 + end +end + +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + register "MaxDramSpeed" = "3733" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""SSD"" + register "options.tsr[2].desc" = ""CHARGER"" + register "options.tsr[3].desc" = ""MEMORY"" + register "options.tsr[4].desc" = ""TYPEC"" + # TODO: below values are initial reference values only + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), + [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), + + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 250, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 alias dptf_policy on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "srcclk_pin" = "6" + device generic 0 alias emmc_rtd3 on end + end + # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 BH799BB + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp6 off end #PCIE6 WWAN + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a alias audio_codec on + probe AUDIO MAX98360_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_VS_I2S + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x40 on end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98360_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_VS_I2S + end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/primus4es/variant.c b/src/mainboard/google/brya/variants/primus4es/variant.c new file mode 100644 index 0000000000..90999ec223 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus4es/variant.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +static void devtree_update_emmc_rtd3(uint32_t board_ver) +{ + struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3); + if (board_ver > 1) + return; + + emmc_rtd3->enabled = 0; +} + +static void devtree_update_audio_codec(void) +{ + struct device *audio_codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config = audio_codec->chip_info; + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) + config->hid = "RTL5682"; +} + +static const struct pad_config nvme_disable_pads[] = { + PAD_NC(GPP_B2, NONE), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B4, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_NC(GPP_D3, NONE), /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ + PAD_NC(GPP_D5, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_NC(GPP_D11, NONE), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ +}; + +static const struct pad_config emmc_disable_pads[] = { + PAD_NC(GPP_B3, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ + PAD_NC(GPP_E20, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_NC(GPP_F19, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ +}; + +static void disable_unused_gpios(void) +{ + int emmc_detected = gpio_get(GPP_T2); + + if (emmc_detected == 1) + gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); + else + gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); +} + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + disable_unused_gpios(); + devtree_update_emmc_rtd3(board_ver); + devtree_update_audio_codec(); +} diff --git a/src/mainboard/google/brya/variants/redrix/Makefile.inc b/src/mainboard/google/brya/variants/redrix/Makefile.inc index acf9bada81..446d113a80 100644 --- a/src/mainboard/google/brya/variants/redrix/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/redrix/gpio.c b/src/mainboard/google/brya/variants/redrix/gpio.c index 83d4a2fdba..c89d58c3fa 100644 --- a/src/mainboard/google/brya/variants/redrix/gpio.c +++ b/src/mainboard/google/brya/variants/redrix/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -20,9 +19,9 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_A22, NONE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -32,24 +31,29 @@ static const struct pad_config override_gpio_table[] = { /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : DDP2_CTRLCLK ==> NC */ PAD_NC(GPP_E20, NONE), /* E22 : DDPA_CTRLCLK ==> NC */ PAD_NC(GPP_E22, NONE), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), - /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> NC */ - PAD_NC(GPP_H3, NONE), + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H20 : IMGCLKOUT1 ==> NC */ PAD_NC(GPP_H20, NONE), /* H21 : IMGCLKOUT2 ==> Privacy screen */ @@ -68,17 +72,23 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_S6, NONE), /* S7 : SNDW3_DATA ==> NC */ PAD_NC(GPP_S7, NONE), - + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -92,23 +102,25 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* E0 : SATAXPCIE0 ==> NC */ - PAD_NC(GPP_E0, NONE), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L */ + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and - * then deassert PERST# in ramstage + * then deassert PERST# in romstage */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), @@ -116,6 +128,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_B4, 0, DEEP), }; +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -127,3 +146,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h index 6f104d5da4..ea8fb54830 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/ec.h @@ -5,6 +5,21 @@ #include +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h index c4fe342621..99d09b2432 100644 --- a/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/redrix/include/variant/gpio.h @@ -5,4 +5,10 @@ #include +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + #endif diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc index 8590598885..97f879582a 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory/ src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt index 296634a290..c9834058a0 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix/memory/ src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E1G32D2NP-046 WT:A 0 (0000) @@ -14,3 +14,8 @@ H9HCNNNFAMMLXR-NEE 3 (0011) MT53E2G32D4NQ-046 WT:A 4 (0100) MT53E512M32D1NP-046 WT:B 1 (0001) MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) +MT53E2G32D4NQ-046 WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt index 71bd5fd385..dd7ec3ffe4 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -8,3 +8,8 @@ H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 0ed6c529e3..62a24eda68 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -32,8 +32,19 @@ fw_config end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" - register "CnviBtAudioOffload" = "true" + # FIVR RFI Spread Spectrum 6% + register "FivrSpreadSpectrum" = "FIVR_SS_6" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ @@ -41,36 +52,53 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C3 | TouchScreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[1] = { + .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[3] = { - .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" + register "tcc_offset" = "3" # TCC of 97C device domain 0 on device ref igpu on chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" # Internal panel on the first port of the graphics chip register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" @@ -84,13 +112,18 @@ chip soc/intel/alderlake chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""SOC"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 55, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 45, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 51, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 51, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 51, 5000), }" register "controls.power_limits" = "{ .pl1 = { @@ -139,6 +172,16 @@ chip soc/intel/alderlake end device ref pcie_rp6 on probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end end device ref tcss_dma0 on chip drivers/intel/usb4/retimer @@ -183,7 +226,7 @@ chip soc/intel/alderlake register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_R"" register "vmon_slot_no" = "0" register "imon_slot_no" = "1" device i2c 0x3a on @@ -196,7 +239,7 @@ chip soc/intel/alderlake register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_L"" register "vmon_slot_no" = "1" register "imon_slot_no" = "0" device i2c 0x3b on @@ -209,7 +252,7 @@ chip soc/intel/alderlake register "name" = ""MXW2"" register "r0_calib_key" = ""dsm_calib_r0_2"" register "temperature_calib_key" = ""dsm_calib_temp_2"" - register "dsm_param_file_name" = ""dsm_param_tt"" + register "dsm_param_file_name" = ""dsm_param_tt_R"" register "vmon_slot_no" = "2" register "imon_slot_no" = "3" device i2c 0x38 on @@ -222,7 +265,7 @@ chip soc/intel/alderlake register "name" = ""MXW3"" register "r0_calib_key" = ""dsm_calib_r0_3"" register "temperature_calib_key" = ""dsm_calib_temp_3"" - register "dsm_param_file_name" = ""dsm_param_tt"" + register "dsm_param_file_name" = ""dsm_param_tt_L"" register "vmon_slot_no" = "3" register "imon_slot_no" = "2" device i2c 0x39 on @@ -231,24 +274,10 @@ chip soc/intel/alderlake end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN2513"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x15 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end end device ref i2c2 on @@ -264,6 +293,7 @@ chip soc/intel/alderlake register "num_freq_entries" = "1" register "link_freq[0]" = "DEFAULT_LINK_FREQ" register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "1" #Controls @@ -299,6 +329,7 @@ chip soc/intel/alderlake register "acpi_name" = ""CAM0"" register "chip_name" = ""Hi-556 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" @@ -339,8 +370,19 @@ chip soc/intel/alderlake register "acpi_name" = ""NVM0"" register "chip_name" = ""M24C64X"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_UCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" @@ -351,6 +393,28 @@ chip soc/intel/alderlake end end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on end + end + end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -396,13 +460,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end @@ -414,13 +478,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -432,13 +498,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -454,7 +522,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -467,7 +536,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/redrix4es/Makefile.inc b/src/mainboard/google/brya/variants/redrix4es/Makefile.inc new file mode 100644 index 0000000000..446d113a80 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/redrix4es/fw_config.c b/src/mainboard/google/brya/variants/redrix4es/fw_config.c new file mode 100644 index 0000000000..ac31d99c44 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/fw_config.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98390_ALC5682I_I2S_4SPK))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98390 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "BT offload enabled\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/redrix4es/gpio.c b/src/mainboard/google/brya/variants/redrix4es/gpio.c new file mode 100644 index 0000000000..ee784723e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/gpio.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A17 : DISP_MISCC ==> NC */ + PAD_NC(GPP_A17, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + + /* H3 : SX_EXIT_HOLDOFF# ==> NC */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> Privacy screen */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* R6 : I2S_PCH_TX_SPKR_RX ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_PCH_RX_SPKR_TX ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + /* + * E0 : SATAXPCIE0 ==> WWAN_PERST_L + * Drive high here, so that PERST_L is sequenced after RST_L + */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* + * enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and + * then deassert PERST# in romstage + */ + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h new file mode 100644 index 0000000000..fa210e45d1 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#undef MAINBOARD_EC_SCI_EVENTS +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. AC Connect/Disconnect + * 3. Power button + * 4. Key press + * 5. Mode change + * 6. Host Device + */ +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h new file mode 100644 index 0000000000..99d09b2432 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_E16 +#define WWAN_PERST GPP_E0 +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 + +#endif diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc new file mode 100644 index 0000000000..423d086a6f --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory/ src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..24fac288ae --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/redrix4es/memory/ src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E1G32D2NP-046 WT:A 0 (0000) +H9HCNNNBKMMLXR-NEE 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +MT53E512M32D2NP-046 WT:E 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) +MT53E2G32D4NQ-046 WT:A 4 (0100) +MT53E512M32D1NP-046 WT:B 1 (0001) +MT53E1G32D2NP-046 WT:B 2 (0010) +H54G46CYRBX267 1 (0001) +K4U6E3S4AB-MGCL 1 (0001) +H54G56CYRBX247 2 (0010) +K4UBE3D4AB-MGCL 2 (0010) +MT53E2G32D4NQ-046 WT:C 4 (0100) diff --git a/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..dd7ec3ffe4 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt @@ -0,0 +1,15 @@ +MT53E1G32D2NP-046 WT:A +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +H9HCNNNFAMMLXR-NEE +MT53E2G32D4NQ-046 WT:A +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +K4U6E3S4AB-MGCL +H54G56CYRBX247 +K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb new file mode 100644 index 0000000000..5cb105df65 --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -0,0 +1,538 @@ +fw_config + field DB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9755S 1 + end + field KB_BL 2 2 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option MAX98390_ALC5682I_I2S_4SPK 1 + end + field DB_LTE 6 7 + option LTE_ABSENT 0 + option LTE_USB 1 + option LTE_PCIE 2 + end + field EPS 10 10 + option PRIVACY_SCREEN_ABSENT 0 + option PRIVACY_SCREEN 1 + end + field CAMERA_UFC 38 39 + option CAMERA_NONE 0 + option CAMERA_OV5675 1 + option CAMERA_HI556 2 + end + field TP_SOURCE 40 41 + option ELAN0000 0 + option ELAN2703 1 + end +end +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + register "CnviBtAudioOffload" = "true" + # FIVR RFI Spread Spectrum 6% + register "FivrSpreadSpectrum" = "FIVR_SS_6" + + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "tcc_offset" = "3" # TCC of 97C + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)" + device generic 0 on + probe EPS PRIVACY_SCREEN + end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""SOC"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 55, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 45, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 51, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 51, 5000), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 13000, + .max_power = 15000, + .time_window_min = 42 * MSECS_PER_SEC, + .time_window_max = 42 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 42 * MSECS_PER_SEC, + .time_window_max = 42 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 alias dptf_policy on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)" + use rp6_rtd3 as rtd3dev + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98390_ALC5682I_I2S_4SPK + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 0"" + register "uid" = "0" + register "name" = ""MXW0"" + register "r0_calib_key" = ""dsm_calib_r0_0"" + register "temperature_calib_key" = ""dsm_calib_temp_0"" + register "dsm_param_file_name" = ""dsm_param_R"" + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + device i2c 0x3a on + probe AUDIO MAX98390_ALC5682I_I2S_4SPK + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 1"" + register "uid" = "1" + register "name" = ""MXW1"" + register "r0_calib_key" = ""dsm_calib_r0_1"" + register "temperature_calib_key" = ""dsm_calib_temp_1"" + register "dsm_param_file_name" = ""dsm_param_L"" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" + device i2c 0x3b on + probe AUDIO MAX98390_ALC5682I_I2S_4SPK + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 2"" + register "uid" = "2" + register "name" = ""MXW2"" + register "r0_calib_key" = ""dsm_calib_r0_2"" + register "temperature_calib_key" = ""dsm_calib_temp_2"" + register "dsm_param_file_name" = ""dsm_param_tt_R"" + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + device i2c 0x38 on + probe AUDIO MAX98390_ALC5682I_I2S_4SPK + end + end + chip drivers/i2c/max98390 + register "desc" = ""MAX98390 Speaker Amp 3"" + register "uid" = "3" + register "name" = ""MXW3"" + register "r0_calib_key" = ""dsm_calib_r0_3"" + register "temperature_calib_key" = ""dsm_calib_temp_3"" + register "dsm_param_file_name" = ""dsm_param_tt_L"" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" + device i2c 0x39 on + probe AUDIO MAX98390_ALC5682I_I2S_4SPK + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x15 on end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 36 on + probe CAMERA_UFC CAMERA_NONE + probe CAMERA_UFC CAMERA_OV5675 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3537"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Hi-556 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "437000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #EN_UCAM_LED_PWR + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #EN_UCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 20 on + probe CAMERA_UFC CAMERA_HI556 + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""M24C64X"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_UCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c64"" + device i2c 50 on end + end + + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on + probe TP_SOURCE ELAN0000 + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2703"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on + probe TP_SOURCE ELAN2703 + end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/redrix4es/variant.c b/src/mainboard/google/brya/variants/redrix4es/variant.c new file mode 100644 index 0000000000..6a79780f6e --- /dev/null +++ b/src/mainboard/google/brya/variants/redrix4es/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc index 478f362638..396e5be222 100644 --- a/src/mainboard/google/brya/variants/taeko/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -1,7 +1,11 @@ bootblock-y += gpio.c +romstage-y += gpio.c + romstage-y += memory.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c index b67cc49e41..2005760266 100644 --- a/src/mainboard/google/brya/variants/taeko/gpio.c +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -4,7 +4,6 @@ #include #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -34,9 +33,9 @@ static const struct pad_config override_gpio_table[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* C3 : SML0CLK ==> NC */ PAD_NC(GPP_C3, NONE), @@ -46,23 +45,23 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_C6, NONE), /* D3 : ISH_GP3 ==> NC */ - PAD_NC(GPP_D3, NONE), - /* D5 : SRCCLKREQ0# ==> NC */ - PAD_NC(GPP_D5, NONE), + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> NC */ - PAD_NC(GPP_D9, NONE), + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> NC */ - PAD_NC(GPP_D10, NONE), + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_NC(GPP_D15, NONE), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_NC(GPP_D16, NONE), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -71,11 +70,11 @@ static const struct pad_config override_gpio_table[] = { /* E5 : SATA_DEVSLP1 ==> NC */ PAD_NC(GPP_E5, NONE), /* E10 : THC0_SPI1_CS# ==> NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> NC */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> NC */ PAD_NC(GPP_E18, NONE), /* E19 : DDP1_CTRLDATA ==> NC */ @@ -98,12 +97,16 @@ static const struct pad_config override_gpio_table[] = { /* F23 : BP105_CTRL ==> PP1050_CTRL */ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), /* H8 : I2C4_SDA ==> NC */ PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H15 : DDPB_CTRLCLK ==> NC */ PAD_NC(GPP_H15, NONE), /* H17 : DDPB_CTRLDATA ==> NC */ @@ -141,10 +144,8 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* * D1 : ISH_GP1 ==> FP_RST_ODL * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. @@ -164,12 +165,40 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { /* * B4 : PROC_GP3 ==> SSD_PERST_L * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. @@ -188,3 +217,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 4398fa5e74..760ffa6e3f 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -2,12 +2,11 @@ fw_config field DB_USB 0 1 option DB_USB_ABSENT 0 option DB_USB3_NO_A 1 + option DB_USB3_1C_1A 2 end field DB_SD 2 3 option DB_SD_ABSENT 0 option DB_SD_OZ711LV2LN 1 - option DB_SD_GL9750 2 - option DB_SD_RTS5232S 3 end field KB_BL 4 option KB_BL_ABSENT 0 @@ -41,6 +40,25 @@ fw_config end end chip soc/intel/alderlake + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "SaGv" = "SaGv_Enabled" @@ -48,6 +66,9 @@ chip soc/intel/alderlake register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # DB Type-A Port A1 + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A1 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN # Intel Common SoC Config @@ -56,11 +77,11 @@ chip soc/intel/alderlake #+-------------------+---------------------------+ #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | HPS | - #| I2C3 | cr50 TPM. Early init is | + #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | + #| I2C2 | HPS | + #| I2C3 | Touchscreen | #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -68,7 +89,11 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, }, .i2c[1] = { + .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -78,7 +103,15 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, }, .i2c[5] = { - .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 500, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 70, + .sda_hold = 40, + } }, }" # I2C Port Config @@ -115,31 +148,31 @@ chip soc/intel/alderlake [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [2] = { .target = DPTF_TEMP_SENSOR_2, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } }, [3] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(51, 74), - TEMP_PCT(47, 60), - TEMP_PCT(45, 45), + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), TEMP_PCT(42, 45), - TEMP_PCT(37, 35), + TEMP_PCT(39, 39), } } }" @@ -165,7 +198,7 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 3000, - .max_power = 12000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, @@ -192,11 +225,11 @@ chip soc/intel/alderlake [0] = { 100, 6000, 220, 2200, }, [1] = { 92, 5500, 180, 1800, }, [2] = { 85, 5000, 145, 1450, }, - [3] = { 74, 4620, 115, 1150, }, - [4] = { 60, 4290, 90, 900, }, - [5] = { 45, 3980, 55, 550, }, - [6] = { 35, 3170, 30, 300, }, - [7] = { 30, 2640, 15, 150, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, [8] = { 10, 800, 10, 100, }, [9] = { 0, 0, 0, 50, } }" @@ -208,6 +241,15 @@ chip soc/intel/alderlake device generic 0 alias dptf_policy on end end end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED + end device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end @@ -242,6 +284,28 @@ chip soc/intel/alderlake end end device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c2 on + chip drivers/i2c/generic + register "hid" = ""GOOG0020"" + register "desc" = ""Chrome OS HPS"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL + # HPS uses I2C addresses 0x30 and 0x51. + # The address we provide here is not significant because + # neither coreboot nor Linux have a driver for HPS, + # it's only used from userspace. + device i2c 30 on + probe HPS HPS_PRESENT + end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" @@ -262,6 +326,7 @@ chip soc/intel/alderlake # Parameter T4 >= 1ms register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -277,30 +342,16 @@ chip soc/intel/alderlake "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end - device ref i2c2 on - chip drivers/i2c/generic - register "hid" = ""GOOG0020"" - register "desc" = ""Chrome OS HPS"" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL - # HPS uses I2C addresses 0x30 and 0x51. - # The address we provide here is not significant because - # neither coreboot nor Linux have a driver for HPS, - # it's only used from userspace. - device i2c 30 on - probe HPS HPS_PRESENT - end - end - end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "wake" = "GPE0_DW2_15" + register "wake" = "GPE0_DW2_14" register "probed" = "1" device i2c 15 on end end @@ -308,7 +359,7 @@ chip soc/intel/alderlake register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "generic.wake" = "GPE0_DW2_15" + register "generic.wake" = "GPE0_DW2_14" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end @@ -347,18 +398,25 @@ chip soc/intel/alderlake register "srcclk_pin" = "3" device generic 0 on probe DB_SD DB_SD_OZ711LV2LN - probe DB_SD DB_SD_GL9750 - probe DB_SD DB_SD_RTS5232S end end end device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" - register "srcclk_pin" = "1" - device generic 0 on end + register "srcclk_pin" = "0" + device generic 0 on + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end end + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED end device ref gspi1 on chip drivers/spi/acpi @@ -382,13 +440,13 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port device generic 2 alias conn1 on end end end @@ -400,15 +458,18 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A + probe DB_USB DB_USB3_1C_1A end end end @@ -420,15 +481,18 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A + probe DB_USB DB_USB3_1C_1A end end chip drivers/usb/acpi @@ -437,10 +501,21 @@ chip soc/intel/alderlake device ref usb2_port6 on end end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port7 on + probe DB_USB DB_USB3_1C_1A + end + end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -453,9 +528,19 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on + probe DB_USB DB_USB3_1C_1A + end + end end end end diff --git a/src/mainboard/google/brya/variants/taeko/variant.c b/src/mainboard/google/brya/variants/taeko/variant.c new file mode 100644 index 0000000000..6a79780f6e --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} diff --git a/src/mainboard/google/brya/variants/taeko4es/Makefile.inc b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc new file mode 100644 index 0000000000..396e5be222 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/Makefile.inc @@ -0,0 +1,11 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/taeko4es/fw_config.c b/src/mainboard/google/brya/variants/taeko4es/fw_config.c new file mode 100644 index 0000000000..5068f84581 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/fw_config.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_NC(GPP_R7, NONE), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_VS_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I-VS.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/taeko4es/gpio.c b/src/mainboard/google/brya/variants/taeko4es/gpio.c new file mode 100644 index 0000000000..f87452a87d --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/gpio.c @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/taeko4es/memory.c b/src/mainboard/google/brya/variants/taeko4es/memory.c new file mode 100644 index 0000000000..9a7ef5c237 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/memory.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, + .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + }, + .ddr1 = { + .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, + .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + }, + .ddr3 = { + .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, + .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, + .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + }, + .ddr5 = { + .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, + .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + }, + .ddr6 = { + .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, + .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + }, + .ddr7 = { + .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, + .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc new file mode 100644 index 0000000000..2ac3e321b5 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fda303c037 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt new file mode 100644 index 0000000000..dd80fc82cb --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb new file mode 100644 index 0000000000..11d572f96f --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -0,0 +1,509 @@ +fw_config + field DB_USB 0 1 + option DB_USB_ABSENT 0 + option DB_USB3_NO_A 1 + end + field DB_SD 2 3 + option DB_SD_ABSENT 0 + option DB_SD_OZ711LV2LN 1 + end + field KB_BL 4 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_MAX98357_ALC5682I_I2S 1 + option AUDIO_MAX98357_ALC5682I_VS_I2S 2 + end + field KB_LAYOUT 8 9 + option KB_LAYOUT_DEFAULT 0 + end + field WIFI_SAR_ID 10 11 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + option WIFI_SAR_ID_2 2 + option WIFI_SAR_ID_3 3 + end + field BOOT_NVME_MASK 12 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 13 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end + field HPS 17 + option HPS_ABSENT 0 + option HPS_PRESENT 1 + end +end +chip soc/intel/alderlake + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "SaGv" = "SaGv_Enabled" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | HPS | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 500, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 70, + .sda_hold = 40, + } + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), + TEMP_PCT(42, 45), + TEMP_PCT(39, 39), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), + TEMP_PCT(42, 45), + TEMP_PCT(39, 39), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(50, 70), + TEMP_PCT(47, 58), + TEMP_PCT(45, 47), + TEMP_PCT(42, 45), + TEMP_PCT(39, 39), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + end + device ref i2c2 on + chip drivers/i2c/generic + register "hid" = ""GOOG0020"" + register "desc" = ""Chrome OS HPS"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL + # HPS uses I2C addresses 0x30 and 0x51. + # The address we provide here is not significant because + # neither coreboot nor Linux have a driver for HPS, + # it's only used from userspace. + device i2c 30 on + probe HPS HPS_PRESENT + end + end + end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S + probe AUDIO AUDIO_MAX98357_ALC5682I_VS_I2S + end + end + end + device ref pcie_rp5 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD DB_SD_OZ711LV2LN + end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on + probe DB_USB DB_USB3_NO_A + end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on + probe DB_USB DB_USB3_NO_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/taeko4es/variant.c b/src/mainboard/google/brya/variants/taeko4es/variant.c new file mode 100644 index 0000000000..6a79780f6e --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko4es/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.inc b/src/mainboard/google/brya/variants/taniks/Makefile.inc new file mode 100644 index 0000000000..6947beb6dd --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/taniks/fw_config.c b/src/mainboard/google/brya/variants/taniks/fw_config.c new file mode 100644 index 0000000000..f79110391c --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/fw_config.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_NC(GPP_R7, NONE), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98357_ALC5682I_I2S_2WAY))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I with 4 speakers.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/taniks/gpio.c b/src/mainboard/google/brya/variants/taniks/gpio.c new file mode 100644 index 0000000000..0d36fc2c16 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* + * B4 : PROC_GP3 ==> SSD_PERST_L + * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. + */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/taniks/include/variant/ec.h b/src/mainboard/google/brya/variants/taniks/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/taniks/include/variant/gpio.h b/src/mainboard/google/brya/variants/taniks/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/taniks/memory.c b/src/mainboard/google/brya/variants/taniks/memory.c new file mode 100644 index 0000000000..e7cba57c30 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/memory.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 30, 30, 30, 30 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, + .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + }, + .ddr1 = { + .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, + .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + }, + .ddr3 = { + .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, + .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, + .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + }, + .ddr5 = { + .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, + .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + }, + .ddr6 = { + .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, + .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + }, + .ddr7 = { + .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, + .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} diff --git a/src/mainboard/google/brya/variants/taniks/memory/Makefile.inc b/src/mainboard/google/brya/variants/taniks/memory/Makefile.inc new file mode 100644 index 0000000000..e79c23e2ba --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taniks/memory src/mainboard/google/brya/variants/taniks/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/brya/variants/taniks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/taniks/memory/dram_id.generated.txt new file mode 100644 index 0000000000..9dd8bb836d --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taniks/memory src/mainboard/google/brya/variants/taniks/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/brya/variants/taniks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/taniks/memory/mem_parts_used.txt new file mode 100644 index 0000000000..dd80fc82cb --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb new file mode 100644 index 0000000000..f80f5d67fc --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -0,0 +1,483 @@ +fw_config + field DB_USB 0 1 + option DB_USB_ABSENT 0 + option DB_USB3_WITH_A 1 + end + field DB_SD 2 3 + option DB_SD_ABSENT 0 + option DB_SD_OZ711LV2LN 1 + option DB_SD_GL9750 2 + option DB_SD_RTS5232S 3 + end + field KB_BL 4 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_MAX98357_ALC5682I_I2S_2WAY 1 + end + field KB_LAYOUT 8 9 + option KB_LAYOUT_DEFAULT 0 + end + field WIFI_SAR_ID 10 11 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + option WIFI_SAR_ID_2 2 + option WIFI_SAR_ID_3 3 + end + field BOOT_NVME_MASK 12 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 13 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end +end +chip soc/intel/alderlake + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "SaGv" = "SaGv_Enabled" + + register "PsysPmax" = "145" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" #DB Type-A Port A1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # USB3/2 Type A port A1 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""WWAN"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 74), + TEMP_PCT(75, 74), + TEMP_PCT(70, 74), + TEMP_PCT(65, 74), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(57, 40), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(57, 70), + TEMP_PCT(54, 60), + TEMP_PCT(48, 60), + TEMP_PCT(45, 45), + TEMP_PCT(42, 39), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 60, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 39, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S_2WAY + end + end + end + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO AUDIO_MAX98357_ALC5682I_I2S_2WAY + end + end + end + device ref pcie_rp5 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on + probe DB_SD DB_SD_OZ711LV2LN + probe DB_SD DB_SD_GL9750 + probe DB_SD DB_SD_RTS5232S + end + end + end + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end + end + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on + probe DB_USB DB_USB3_WITH_A + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on + probe DB_USB DB_USB3_WITH_A + end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/vell/Makefile.inc b/src/mainboard/google/brya/variants/vell/Makefile.inc new file mode 100644 index 0000000000..7fb0167253 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c +romstage-y += memory.c +romstage-y += gpio.c +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c new file mode 100644 index 0000000000..e6588b9f85 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A11 : PMC_I2C_SDA ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B2 : VRALERT# ==> RGB_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + + /* D3 : ISH_GP3 ==> EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG), + /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */ + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX_STRAP */ + PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG), + + /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E10 : THC0_SPI1_CS# ==> UWB_GSPI0_CS */ + PAD_CFG_NF_LOCK(GPP_E10, NONE, NF2, LOCK_CONFIG), + /* E11 : THC0_SPI1_CLK ==> UWB_CLK */ + PAD_CFG_NF_LOCK(GPP_E11, NONE, NF2, LOCK_CONFIG), + /* E12 : THC0_SPI1_IO1 ==> UWB_GSPI0_DI */ + PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG), + /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */ + PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG), + /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_E22, NONE, DEEP), + /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F19 : NC */ + PAD_NC(GPP_F19, NONE), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), + /* H12 : I2C7_SDA ==> UWB_SDA */ + PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> UWB_SCL */ + PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6), + /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF6), + /* H21 : IMGCLKOUT2 ==> UCAM_MCLK_R */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + + /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : IC1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : ISH_GP3 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D3, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4), + + /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E3, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E5, NONE, DEEP), + /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /*Add virtual GPIOs for CPU PCIe RP*/ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/vell/include/variant/ec.h b/src/mainboard/google/brya/variants/vell/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/vell/include/variant/gpio.h b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c new file mode 100644 index 0000000000..fd36c5dda3 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 4, 0, 1, 3, 7, 5, 6, 2, }, + .dq1 = { 9, 13, 12, 8, 15, 10, 14, 11, }, + }, + .ddr1 = { + .dq1 = { 0, 2, 1, 3, 7, 5, 6, 4, }, + .dq0 = { 10, 8, 11, 9, 13, 15, 14, 12, }, + }, + .ddr2 = { + .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, }, + .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, }, + }, + .ddr3 = { + .dq1 = { 7, 6, 4, 5, 0, 3, 1, 2, }, + .dq0 = { 9, 13, 8, 12, 15, 10, 14, 11, }, + }, + .ddr4 = { + .dq1 = { 7, 5, 4, 6, 2, 0, 1, 3, }, + .dq0 = { 15, 14, 12, 13, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq1 = { 3, 7, 2, 6, 0, 4, 5, 1, }, + .dq0 = { 9, 10, 11, 8, 12, 15, 13, 14, }, + }, + .ddr6 = { + .dq1 = { 1, 0, 3, 2, 7, 5, 4, 6, }, + .dq0 = { 11, 8, 10, 9, 12, 14, 13, 15, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, }, + .dq1 = { 8, 9, 10, 12, 14, 11, 13, 15, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_ULT_ULX_T4, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E3 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E7 + */ + gpio_t spd_gpios[] = { + GPP_E3, + GPP_E2, + GPP_E1, + GPP_E7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E5 */ + return gpio_get(GPP_E5); +} diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc new file mode 100644 index 0000000000..05f46893b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt new file mode 100644 index 0000000000..2e3eb01723 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/vell/memory src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) +H9JCNNNCP3MLYR-N6E 1 (0001) diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f81efc59a2 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt @@ -0,0 +1,14 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F512M32D2DR-031 WT:B +MT62F1G32D4DR-031 WT:B +H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb new file mode 100644 index 0000000000..690e2669db --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -0,0 +1,444 @@ +fw_config + field DB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9750 1 + end + field KB_BL 2 2 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98360_ALC5682IVS_I2S 2 + end + field DB_LTE 6 7 + option LTE_ABSENT 0 + option LTE_USB 1 + end + field EPS 10 10 + option PRIVACY_SCREEN_ABSENT 0 + option PRIVACY_SCREEN 1 + end +end +chip soc/intel/alderlake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 + register "SaGv" = "SaGv_Enabled" + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)" + device generic 0 on + probe EPS PRIVACY_SCREEN + end + end + end # Integrated Graphics Device + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""Regulator"" + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 on end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" + register "cio2_prt[0]" = "1" + device generic 0 on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 1 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 1, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp8 off end + device ref pcie_rp9 off end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682IVS_I2S + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + register "stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end + device ref i2c2 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360000000" + register "link_freq[1]" = "180000000" + register "remote_name" = ""IPU0"" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_F20" #reset + register "gpio_panel.gpio[1].gpio_num" = "GPP_C4" #power + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x10" + + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2703"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + use conn3 as mux_conn[3] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port4 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MlB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref tcss_usb3_port4 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C3 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/vell/variant.c b/src/mainboard/google/brya/variants/vell/variant.c new file mode 100644 index 0000000000..76f0f524a8 --- /dev/null +++ b/src/mainboard/google/brya/variants/vell/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} diff --git a/src/mainboard/google/brya/variants/volmar/Makefile.inc b/src/mainboard/google/brya/variants/volmar/Makefile.inc new file mode 100644 index 0000000000..9ea19ded56 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/volmar/fw_config.c b/src/mainboard/google/brya/variants/volmar/fw_config.c new file mode 100644 index 0000000000..375dca2e2a --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/fw_config.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), +}; + +static const struct pad_config bt_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + PAD_NC(GPP_VGPIO_30, NONE), + PAD_NC(GPP_VGPIO_31, NONE), + PAD_NC(GPP_VGPIO_32, NONE), + PAD_NC(GPP_VGPIO_33, NONE), + PAD_NC(GPP_VGPIO_34, NONE), + PAD_NC(GPP_VGPIO_35, NONE), + PAD_NC(GPP_VGPIO_36, NONE), + PAD_NC(GPP_VGPIO_37, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98373 NAU88L25B.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + printk(BIOS_INFO, "Enabling BT offload\n"); + gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); + } else { + printk(BIOS_INFO, "Disabling BT offload\n"); + gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/volmar/gpio.c b/src/mainboard/google/brya/variants/volmar/gpio.c new file mode 100644 index 0000000000..147e6c23f7 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/gpio.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B3 : PROC_GP2 ==> NC */ + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */ + PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), + /* D18 : UART1_TXD ==> NC */ + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H19 : SRCCLKREQ4# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/volmar/include/variant/ec.h b/src/mainboard/google/brya/variants/volmar/include/variant/ec.h new file mode 100644 index 0000000000..6f104d5da4 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h b/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc new file mode 100644 index 0000000000..e91dd92bd1 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/volmar/memory/ src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt new file mode 100644 index 0000000000..ca0069fc77 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/volmar/memory/ src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 1 (0001) +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt new file mode 100644 index 0000000000..a188982f16 --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +H54G56CYRBX247 +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb new file mode 100644 index 0000000000..f54753b7af --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -0,0 +1,412 @@ +fw_config + field DB_USB 0 3 + option USB_ABSENT 0 + option USB3_PS8815 1 + end + field KB_BL 4 4 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option MAX98373_NAU88L25B_I2S 1 + end + field BOOT_NVME_MASK 8 + option BOOT_NVME_DISABLED 0 + option BOOT_NVME_ENABLED 1 + end + field BOOT_EMMC_MASK 9 + option BOOT_EMMC_DISABLED 0 + option BOOT_EMMC_ENABLED 1 + end +end +chip soc/intel/alderlake + register "SaGv" = "SaGv_Enabled" + + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN + + # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(75, 80), + TEMP_PCT(68, 70), + TEMP_PCT(62, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(40, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 90), + TEMP_PCT(55, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40), + TEMP_PCT(36, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 18000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 40000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe BOOT_NVME_MASK BOOT_NVME_ENABLED + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/nau8825 + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" + register "jkdet_pull_up" = "0" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0C" + register "sar_threshold[1]" = "0x1C" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "6" + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on + probe AUDIO MAX98373_NAU88L25B_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_NAU88L25B_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_NAU88L25B_I2S + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "4" + device generic 0 alias emmc_rtd3 on end + end + # Enable PCIe-to-eMMC bridge PCIE 3 using clk 4 + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED + end #PCIE3 BH799BB + device ref pcie_rp6 off end # PCIE6 WWAN + device ref pcie_rp8 off end # PCIE8 SD card + device ref pcie_rp9 off end # PCIE9-12 SSD + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/volmar/variant.c b/src/mainboard/google/brya/variants/volmar/variant.c new file mode 100644 index 0000000000..fef03f2b3e --- /dev/null +++ b/src/mainboard/google/brya/variants/volmar/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + config->CnviBtAudioOffload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S)); +} diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl index d9bb5e7944..f19a5ef4e9 100644 --- a/src/mainboard/google/brya/wwan_power.asl +++ b/src/mainboard/google/brya/wwan_power.asl @@ -4,8 +4,10 @@ Method (MPTS, 1) { +#if CONFIG(HAVE_PCIE_WWAN) \_SB.PCI0.CTXS(WWAN_PERST); Sleep(T1_OFF_MS) +#endif \_SB.PCI0.CTXS(WWAN_RST); Sleep(T2_OFF_MS) \_SB.PCI0.CTXS(WWAN_FCPO); diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 4eb151efc1..ebb5233d81 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -1,26 +1,29 @@ if BOARD_GOOGLE_BUTTERFLY +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT + select EC_QUANTA_ENE_KB3940Q + select GFX_GMA_PANEL_1_ON_LVDS select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select INTEL_INT15 - select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1. + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT select HAVE_IFD_BIN select HAVE_ME_BIN - select GFX_GMA_PANEL_1_ON_LVDS + select HAVE_OPTION_TABLE + select INTEL_INT15 + select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE + select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1. + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 356e97b7b5..a7d56aee4a 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -8,12 +7,10 @@ #include #include #include +#include #include #include "ec.h" - -#define WP_GPIO 6 -#define DEVMODE_GPIO 54 -#define FORCE_RECOVERY_MODE 0 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -42,23 +39,13 @@ int get_lid_switch(void) return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; } +/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ int get_recovery_mode_switch(void) { - int ec_rec_mode = 0; + if (ENV_RAMSTAGE) + return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); - if (FORCE_RECOVERY_MODE) { - printk(BIOS_DEBUG, "FORCING RECOVERY MODE.\n"); - return 1; - } - - if (ENV_RAMSTAGE) { - if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) - ec_rec_mode = 1; - - printk(BIOS_DEBUG, "RECOVERY MODE FROM EC: %x\n", ec_rec_mode); - } - - return ec_rec_mode; + return 0; } static const struct cros_gpio cros_gpios[] = { @@ -77,3 +64,10 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 725cbd1700..c79526e3c9 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00040381" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index ba30016492..073e7992f1 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include #include #include @@ -79,11 +79,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 6145dc73d4..f428e69e0e 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -7,14 +7,12 @@ #include #include #include -#include #include #include "onboard.h" #include "ec.h" #include #include #include -#include static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -258,7 +256,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index b8da862d12..f799d04083 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -16,4 +16,8 @@ /* 0x00: White LINK LED and Amber ACTIVE LED */ #define BUTTERFLY_NIC_LED_MODE 0x00 + +/* SPI write protect, active low */ +#define WP_GPIO 6 + #endif diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 71572679f2..e45b259333 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -36,6 +36,7 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "Cherry" if BOARD_GOOGLE_CHERRY + default "Dojo" if BOARD_GOOGLE_DOJO default "Tomato" if BOARD_GOOGLE_TOMATO config DRIVER_TPM_I2C_BUS @@ -62,6 +63,5 @@ config CHERRY_USE_RT1011 config CHERRY_USE_RT1019 bool - default y if BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_TOMATO - default n + default y endif diff --git a/src/mainboard/google/cherry/Kconfig.name b/src/mainboard/google/cherry/Kconfig.name index 7a65ada34b..9c58e518e6 100644 --- a/src/mainboard/google/cherry/Kconfig.name +++ b/src/mainboard/google/cherry/Kconfig.name @@ -4,6 +4,10 @@ config BOARD_GOOGLE_CHERRY bool "-> Cherry" select BOARD_GOOGLE_CHERRY_COMMON +config BOARD_GOOGLE_DOJO + bool "-> Dojo" + select BOARD_GOOGLE_CHERRY_COMMON + config BOARD_GOOGLE_TOMATO bool "-> Tomato" select BOARD_GOOGLE_CHERRY_COMMON diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 748e06e28d..13b673cf07 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -59,3 +59,9 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(GPIO_GSC_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index a09705019e..92d8ee1dbe 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -15,9 +15,7 @@ #include #include #include -#include #include -#include #include #include @@ -31,28 +29,6 @@ #define GPIO_EDP_HPD_1V8 GPIO(GPIO_07) #define GPIO_EN_PP3300_DISP_X GPIO(I2SO1_D2) -DEFINE_BITFIELD(MSDC0_DRV, 29, 0) -DEFINE_BITFIELD(MSDC1_DRV, 17, 0) -DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) -DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) -DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) - -#define MSDC0_BASE 0x11230000 -#define MSDC0_TOP_BASE 0x11f50000 - -#define MSDC0_DRV_VALUE 0x1b6db6db -#define MSDC1_DRV_VALUE 0x1b6db -#define MSDC1_GPIO_MODE0_VALUE 0x1 -#define MSDC1_GPIO_MODE1_VALUE 0x1 - -enum { - MSDC1_GPIO_MODE0_BASE = 0x100053d0, - MSDC1_GPIO_MODE1_BASE = 0x100053e0, -}; - static void register_reset_to_bl31(void) { static struct bl_aux_param_gpio param_reset = { @@ -64,82 +40,6 @@ static void register_reset_to_bl31(void) register_bl31_aux_param(¶m_reset.h); } -static void configure_emmc(void) -{ - void *gpio_base = (void *)IOCFG_TL_BASE; - int i; - - const gpio_t emmc_pu_pin[] = { - GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), - GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), - GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), - GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), - GPIO(EMMC_CMD), GPIO(EMMC_RSTB), - }; - - const gpio_t emmc_pd_pin[] = { - GPIO(EMMC_DSL), GPIO(EMMC_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) - gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) - gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ - SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); - - mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); -} - -static void configure_sdcard(void) -{ - void *gpio_base = (void *)IOCFG_RB_BASE; - void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; - void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; - int i; - - const gpio_t sdcard_pu_pin[] = { - GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), - GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), - GPIO(MSDC1_CMD), - }; - - const gpio_t sdcard_pd_pin[] = { - GPIO(MSDC1_CLK), - }; - - for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) - gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); - - for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) - gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - - /* set sdcard cmd/dat/clk pins driving to 8mA */ - SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); - - /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ - SET32_BITFIELDS(gpio_mode0_base, - MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, - MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); - - /* set sdcard dat1 pin to msdc1 mode */ - SET32_BITFIELDS(gpio_mode1_base, - MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, - MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); - - mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST); - - if (CONFIG(BOARD_GOOGLE_CHERRY)) - mt6360_init(I2C7); - - mainboard_enable_regulator(MTK_REGULATOR_VCCQ, 1); - mainboard_enable_regulator(MTK_REGULATOR_VCC, 1); -} - /* Set up backlight control pins as output pin and power-off by default */ static void configure_panel_backlight(void) { @@ -199,8 +99,8 @@ static void mainboard_init(struct device *dev) else printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); - configure_emmc(); - configure_sdcard(); + mtk_msdc_configure_emmc(true); + mtk_msdc_configure_sdcard(); setup_usb_host(); /* for audio usage */ diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig new file mode 100644 index 0000000000..7bf557fd2c --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig @@ -0,0 +1,68 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_CORSOLA_COMMON + def_bool n + +config BOARD_GOOGLE_KINGLER_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + +config BOARD_GOOGLE_KRABBY_COMMON + def_bool n + select BOARD_GOOGLE_CORSOLA_COMMON + +if BOARD_GOOGLE_CORSOLA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8186 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 + select DRIVER_PARADE_PS8640 + +config MAINBOARD_DIR + string + default "google/corsola" + +config MAINBOARD_PART_NUMBER + string + default "Kingler" if BOARD_GOOGLE_KINGLER + default "Krabby" if BOARD_GOOGLE_KRABBY + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 + +config SDCARD_INIT + bool + default y if BOARD_GOOGLE_KINGLER_COMMON + default n if BOARD_GOOGLE_KRABBY_COMMON + +config DRIVER_TPM_SPI_BUS + hex + default 0x2 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 +endif diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name new file mode 100644 index 0000000000..85cb41ef41 --- /dev/null +++ b/src/mainboard/google/corsola/Kconfig.name @@ -0,0 +1,11 @@ +comment "Kingler" + +config BOARD_GOOGLE_KINGLER + bool "-> Kingler" + select BOARD_GOOGLE_KINGLER_COMMON + +comment "Krabby" + +config BOARD_GOOGLE_KRABBY + bool "-> Krabby" + select BOARD_GOOGLE_KRABBY_COMMON diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc new file mode 100644 index 0000000000..30ee6c156f --- /dev/null +++ b/src/mainboard/google/corsola/Makefile.inc @@ -0,0 +1,22 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c +bootblock-y += chromeos.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += regulator.c +romstage-y += romstage.c +romstage-y += sdram_configs.c + +ramstage-y += memlayout.ld +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += display.c +ramstage-y += mainboard.c +ramstage-y += regulator.c +ramstage-y += reset.c diff --git a/src/mainboard/google/corsola/board_info.txt b/src/mainboard/google/corsola/board_info.txt new file mode 100644 index 0000000000..3c37bdfd3f --- /dev/null +++ b/src/mainboard/google/corsola/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Corsola MediaTek MT8186 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c new file mode 100644 index 0000000000..96031ef408 --- /dev/null +++ b/src/mainboard/google/corsola/boardid.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* board_id is provided by ec/google/chromeec/ec_boardid.c */ + +#define ADC_LEVELS 12 + +enum { + /* RAM IDs */ + RAM_ID_LOW_CHANNEL = 2, + RAM_ID_HIGH_CHANNEL = 3, + /* SKU IDs */ + SKU_ID_LOW_CHANNEL = 4, + SKU_ID_HIGH_CHANNEL = 5, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_LOW_CHANNEL] = ram_voltages, + [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [SKU_ID_LOW_CHANNEL] = ram_voltages, + [SKU_ID_HIGH_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t cached_sku_code = BOARD_ID_INIT; + + if (cached_sku_code == BOARD_ID_INIT) { + cached_sku_code = google_chromeec_get_board_sku(); + + if (cached_sku_code == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Failed to get SKU code from EC\n"); + cached_sku_code = (get_adc_index(SKU_ID_HIGH_CHANNEL) << 4 | + get_adc_index(SKU_ID_LOW_CHANNEL)); + } + printk(BIOS_DEBUG, "SKU Code: %#02x\n", cached_sku_code); + } + + return cached_sku_code; +} + +uint32_t ram_code(void) +{ + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } + + return cached_ram_code; +} diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c new file mode 100644 index 0000000000..87b972d59c --- /dev/null +++ b/src/mainboard/google/corsola/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gpio.h" + +static void usb3_hub_reset(void) +{ + gpio_output(GPIO_USB3_HUB_RST_L, 1); +} + +void bootblock_mainboard_init(void) +{ + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_snfc_init(SPI_NOR_GPIO_SET1); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING); + usb3_hub_reset(); +} diff --git a/src/mainboard/google/corsola/chromeos.c b/src/mainboard/google/corsola/chromeos.c new file mode 100644 index 0000000000..56959c3e2e --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + /* Set up open-drain pins */ + gpio_input(GPIO_SAR_INT_ODL); + gpio_input(GPIO_BT_WAKE_AP_ODL); + gpio_input(GPIO_WIFI_INT_ODL); + gpio_input(GPIO_DPBRDG_INT_ODL); + gpio_input(GPIO_EDPBRDG_INT_ODL); + gpio_input(GPIO_EC_AP_HPD_OD); + gpio_input(GPIO_TCHPAD_INT_ODL); + gpio_input(GPIO_TCHSCR_INT_1V8_ODL); + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_EC_IN_RW_ODL); + gpio_input(GPIO_GSC_AP_INT_ODL); + gpio_input(GPIO_AP_WP_ODL); + gpio_input(GPIO_HP_INT_ODL); + gpio_input(GPIO_PEN_EJECT_OD); + gpio_input(GPIO_UCAM_DET_ODL); + + /* Set up GPIOs */ + gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_XHCI_DONE, 0); + gpio_output(GPIO_EN_SPK, 0); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_EC_IN_RW_ODL.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW_ODL); +} + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT_ODL); +} diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd new file mode 100644 index 0000000000..7194632e36 --- /dev/null +++ b/src/mainboard/google/corsola/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb new file mode 100644 index 0000000000..0c4bcb57c0 --- /dev/null +++ b/src/mainboard/google/corsola/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8186 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c new file mode 100644 index 0000000000..fd269eca35 --- /dev/null +++ b/src/mainboard/google/corsola/display.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "display.h" +#include "gpio.h" + +/* Bridge functions */ +static void bridge_ps8640_power_on(void) +{ + /* Set VRF12 to 1.2V and VCN33 to 3.3V */ + mainboard_set_regulator_vol(MTK_REGULATOR_VRF12, 1200000); + mainboard_set_regulator_vol(MTK_REGULATOR_VCN33, 3300000); + udelay(200); + + /* Turn on bridge */ + gpio_output(GPIO_EDPBRDG_PWREN, 1); + gpio_output(GPIO_EDPBRDG_RST_L, 0); + mdelay(2); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} + +static int bridge_ps8640_get_edid(u8 i2c_bus, struct edid *edid) +{ + const u8 chip = 0x8; + + if (ps8640_init(i2c_bus, chip) < 0) { + printk(BIOS_ERR, "%s: Can't init PS8640 bridge\n", __func__); + return -1; + } + if (ps8640_get_edid(i2c_bus, chip, edid) < 0) { + printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); + return -1; + } + return 0; +} + +static int bridge_ps8640_post_power_on(u8 i2c_bus, struct edid *edid) +{ + /* Do nothing */ + return 0; +} + +static void bridge_anx7625_power_on(void) +{ + /* Turn on bridge */ + gpio_output(GPIO_EDPBRDG_RST_L, 0); + gpio_output(GPIO_EN_PP1000_EDPBRDG, 1); + gpio_output(GPIO_EN_PP1800_EDPBRDG, 1); + gpio_output(GPIO_EN_PP3300_EDPBRDG, 1); + mdelay(14); + gpio_output(GPIO_EDPBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_EDPBRDG_RST_L, 1); +} + +static int bridge_anx7625_get_edid(u8 i2c_bus, struct edid *edid) +{ + if (anx7625_init(i2c_bus) < 0) { + printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); + return -1; + } + if (anx7625_dp_get_edid(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); + return -1; + } + return 0; +} + +static int bridge_anx7625_post_power_on(u8 i2c_bus, struct edid *edid) +{ + return anx7625_dp_start(i2c_bus, edid); +} + +/* Display function */ +static void backlight_control(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); + gpio_output(GPIO_EN_PP3300_DISP_X, 1); +} + +static const struct edp_bridge anx7625_bridge = { + .power_on = bridge_anx7625_power_on, + .get_edid = bridge_anx7625_get_edid, + .post_power_on = bridge_anx7625_post_power_on, +}; + +static const struct edp_bridge ps8640_bridge = { + .power_on = bridge_ps8640_power_on, + .get_edid = bridge_ps8640_get_edid, + .post_power_on = bridge_ps8640_post_power_on, +}; + +_Static_assert(CONFIG(BOARD_GOOGLE_KINGLER_COMMON) + CONFIG(BOARD_GOOGLE_KRABBY_COMMON) == 1, + "Exactly one of KINGLER and KRABBY must be set"); + +int configure_display(void) +{ + struct edid edid; + const u8 i2c_bus = I2C0; + const struct edp_bridge *bridge; + + if (CONFIG(BOARD_GOOGLE_KINGLER_COMMON)) + bridge = &anx7625_bridge; + else /* BOARD_GOOGLE_KRABBY_COMMON */ + bridge = &ps8640_bridge; + + printk(BIOS_INFO, "%s: Starting display init\n", __func__); + + mtk_i2c_bus_init(i2c_bus, I2C_SPEED_FAST); + + /* Set up backlight control pins as output pin and power-off by default */ + backlight_control(); + + assert(bridge->power_on); + bridge->power_on(); + + assert(bridge->get_edid); + if (bridge->get_edid(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to get edid\n", __func__); + return -1; + } + + const char *name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET); + + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, NULL) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); + return -1; + } + + if (bridge->post_power_on(i2c_bus, &edid) < 0) { + printk(BIOS_ERR, "%s: Failed to post power on bridge\n", __func__); + return -1; + } + + mtk_ddp_mode_set(&edid); + fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + + return 0; +} diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/display.h new file mode 100644 index 0000000000..4e883f2b88 --- /dev/null +++ b/src/mainboard/google/corsola/display.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ + +#include + +struct edp_bridge { + void (*power_on)(void); + int (*get_edid)(u8 i2c_bus, struct edid *edid); + int (*post_power_on)(u8 i2c_bus, struct edid *edid); +}; + +int configure_display(void); + +#endif diff --git a/src/mainboard/google/corsola/gpio.h b/src/mainboard/google/corsola/gpio.h new file mode 100644 index 0000000000..d42a5ef0f8 --- /dev/null +++ b/src/mainboard/google/corsola/gpio.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_GPIO_H__ + +#include + +#define GPIO_SAR_INT_ODL GPIO(EINT5) +#define GPIO_BT_WAKE_AP_ODL GPIO(EINT6) +#define GPIO_WIFI_INT_ODL GPIO(EINT7) +#define GPIO_DPBRDG_INT_ODL GPIO(EINT8) +#define GPIO_EC_AP_HPD_OD GPIO(EINT10) +#define GPIO_TCHPAD_INT_ODL GPIO(EINT11) +#define GPIO_TCHSCR_INT_1V8_ODL GPIO(EINT12) +#define GPIO_EC_AP_INT_ODL GPIO(EINT13) +#define GPIO_EC_IN_RW_ODL GPIO(EINT14) +#define GPIO_GSC_AP_INT_ODL GPIO(EINT15) +#define GPIO_AP_WP_ODL GPIO(EINT16) +#define GPIO_HP_INT_ODL GPIO(EINT17) +#define GPIO_PEN_EJECT_OD GPIO(EINT18) +#define GPIO_UCAM_DET_ODL GPIO(CAM_CLK2) + +#define GPIO_RESET GPIO(PERIPHERAL_EN0) +#define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) +#define GPIO_USB3_HUB_RST_L GPIO(PERIPHERAL_EN2) +#define GPIO_EN_SPK GPIO(PERIPHERAL_EN3) +#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN4) + +/* GPIOs for SD card */ +#define GPIO_EN_PP3300_SDBRDG_X GPIO(PERIPHERAL_EN7) + +/* GPIOs for display */ +#define GPIO_AP_EDP_BKLTEN GPIO(PERIPHERAL_EN5) +#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) +#define GPIO_EN_PP3300_DISP_X GPIO(PERIPHERAL_EN6) +#define GPIO_EDPBRDG_RST_L GPIO(LCM_RST) +#define GPIO_EN_PP1000_EDPBRDG GPIO(ANT_SEL0) +#define GPIO_EN_PP1800_EDPBRDG GPIO(ANT_SEL1) +#define GPIO_EN_PP3300_EDPBRDG GPIO(ANT_SEL2) +#define GPIO_EDPBRDG_INT_ODL GPIO(EINT9) +#define GPIO_EDPBRDG_PWREN GPIO(DSI_TE) + +void setup_chromeos_gpios(void); + +#endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c new file mode 100644 index 0000000000..c0a6449b39 --- /dev/null +++ b/src/mainboard/google/corsola/mainboard.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "display.h" +#include "gpio.h" + +#include + +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(¶m_reset.h); +} + +static void configure_audio(void) +{ + mtcmos_audio_power_on(); + + /* Set up I2S */ + gpio_set_mode(GPIO(I2S2_MCK), PAD_I2S2_MCK_FUNC_I2S2_MCK); + gpio_set_mode(GPIO(I2S2_BCK), PAD_I2S2_BCK_FUNC_I2S2_BCK); + gpio_set_mode(GPIO(I2S2_LRCK), PAD_I2S2_LRCK_FUNC_I2S2_LRCK); + gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_I2S3_DO); +} + +static void mainboard_init(struct device *dev) +{ + mtk_msdc_configure_emmc(true); + + if (CONFIG(SDCARD_INIT)) { + printk(BIOS_INFO, "SD card init\n"); + + /* External SD Card connected via USB */ + gpio_output(GPIO_EN_PP3300_SDBRDG_X, 1); + } + + setup_usb_host(); + + configure_audio(); + + if (spm_init()) + printk(BIOS_ERR, "spm init failed, system suspend may not work\n"); + + register_reset_to_bl31(); + + if (display_init_required()) { + if (configure_display() < 0) + printk(BIOS_ERR, "%s: Failed to init display\n", __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init\n", __func__); + } +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl b/src/mainboard/google/corsola/memlayout.ld similarity index 56% rename from src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl rename to src/mainboard/google/corsola/memlayout.ld index fd3b5cfb4e..0f1fcec9a0 100644 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/corsola/memlayout.ld @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include diff --git a/src/mainboard/google/corsola/regulator.c b/src/mainboard/google/corsola/regulator.c new file mode 100644 index 0000000000..d607497a4f --- /dev/null +++ b/src/mainboard/google/corsola/regulator.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define REGULATOR_NOT_SUPPORT -1 + +static const int regulator_id[] = { + [MTK_REGULATOR_VDD1] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDD2] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDDQ] = MT6366_VDDQ, + [MTK_REGULATOR_VMDDR] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VCORE] = MT6366_VCORE, + [MTK_REGULATOR_VCC] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VCCQ] = REGULATOR_NOT_SUPPORT, + [MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1, + [MTK_REGULATOR_VMCH] = MT6366_VMCH, + [MTK_REGULATOR_VMC] = MT6366_VMC, + [MTK_REGULATOR_VPROC12] = MT6366_VPROC12, + [MTK_REGULATOR_VSRAM_PROC12] = MT6366_VSRAM_PROC12, + [MTK_REGULATOR_VRF12] = MT6366_VRF12, + [MTK_REGULATOR_VCN33] = MT6366_VCN33, +}; + +_Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error"); + +void mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + assert(regulator < MTK_REGULATOR_NUM); + + if (regulator_id[regulator] < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return; + } + mt6366_set_voltage(regulator_id[regulator], voltage_uv); +} + +uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + assert(regulator < MTK_REGULATOR_NUM); + + if (regulator_id[regulator] < 0) { + printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator); + return 0; + } + return mt6366_get_voltage(regulator_id[regulator]); +} diff --git a/src/mainboard/google/corsola/reset.c b/src/mainboard/google/corsola/reset.c new file mode 100644 index 0000000000..91ee7c074d --- /dev/null +++ b/src/mainboard/google/corsola/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +void do_board_reset(void) +{ + gpio_output(GPIO_RESET, 1); +} diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c new file mode 100644 index 0000000000..8d03b5b54c --- /dev/null +++ b/src/mainboard/google/corsola/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void raise_little_cpu_freq(void) +{ + mainboard_set_regulator_vol(MTK_REGULATOR_VPROC12, 1031250); + mainboard_set_regulator_vol(MTK_REGULATOR_VSRAM_PROC12, 1118750); + udelay(200); + mt_pll_raise_little_cpu_freq(2000 * MHz); + mt_pll_raise_cci_freq(1385 * MHz); + + printk(BIOS_INFO, "Check CPU freq: %u KHz, cci: %u KHz\n", + mt_fmeter_get_freq_khz(FMETER_ABIST, 9), + mt_fmeter_get_freq_khz(FMETER_ABIST, 7)); +} + +void platform_romstage_main(void) +{ + mt6366_init(); + raise_little_cpu_freq(); + rtc_boot(); + mtk_dram_init(); +} diff --git a/src/mainboard/google/corsola/sdram_configs.c b/src/mainboard/google/corsola/sdram_configs.c new file mode 100644 index 0000000000..f565f53f82 --- /dev/null +++ b/src/mainboard/google/corsola/sdram_configs.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct sdram_info *get_sdram_config(void) +{ + /* + * The MT8186 platform supports "dram adaptive" feature to + * automatically detect dram information, including channel, rank, die size..., + * and can automatically configure EMI settings. + * So we will be passing a placeholder param blob. + */ + static struct sdram_info params; + return ¶ms; +} diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 9640489253..5feecf6046 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,25 +2,61 @@ config BOARD_GOOGLE_BASEBOARD_CYAN def_bool n select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select SOC_INTEL_BRASWELL - select HAVE_ACPI_RESUME select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN + select SOC_INTEL_BRASWELL select SYSTEM_TYPE_LAPTOP select USE_GOOGLE_FSP - select HAVE_SPD_IN_CBFS + +config BOARD_GOOGLE_BANON + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_CELES + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_CYAN + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_EDGAR + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_KEFKA + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_REKS + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_RELM + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_SETZER + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_TERRA + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_ULTIMA + select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_WIZPIG + select BOARD_GOOGLE_BASEBOARD_CYAN if BOARD_GOOGLE_BASEBOARD_CYAN +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index 1ab8ed4fa9..19adc080b2 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -2,44 +2,33 @@ comment "Cyan" config BOARD_GOOGLE_BANON bool "-> Banon (Acer Chromebook 15 (CB3-532))" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_CELES bool "-> Celes (Samsung Chromebook 3)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_CYAN bool "-> Cyan (Acer Chromebook R11 (C738T))" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_EDGAR bool "-> Edgar (Acer Chromebook 14 (CB3-431))" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_KEFKA bool "-> Kefka (Dell Chromebook 11 3180/3189)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_REKS bool "-> Reks (Lenovo N22/N42 Chromebook)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_RELM bool "-> Relm" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_SETZER bool "-> Setzer (HP Chromebook 11 G5)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_TERRA bool "-> Terra (ASUS Chromebook C202SA/C300SA/C301SA)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_ULTIMA bool "-> Ultima (Lenovo Yoga 11e G3)" - select BOARD_GOOGLE_BASEBOARD_CYAN config BOARD_GOOGLE_WIZPIG bool "-> Wizpig" - select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 8a7d7b1030..3a5d04e6c9 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -20,7 +20,7 @@ Scope (\_SB.PCI0.I2C1) AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, SharedAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } } ) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index eddf808fe0..e972056510 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -20,7 +20,7 @@ Scope (\_SB.PCI0.I2C1) AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, SharedAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index 8ab5923c29..a944db6113 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -63,7 +63,7 @@ Scope (\_SB.PCI0.I2C1) AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, SharedAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index b34680c5d1..91678de8b8 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -19,7 +19,7 @@ Scope (\_SB.PCI0.I2C6) AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C6", // ResourceSource ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, SharedAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index 175bdaf845..aa268b1b5d 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -18,7 +18,7 @@ Scope (\_SB.PCI0.I2C6) AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C6", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, SharedAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index b88862ca59..a11b6f9f63 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include +#include #include /* The WP status pin lives on MF_ISH_GPIO_4 */ @@ -62,3 +64,10 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index fa23e9faa9..41ef91e497 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -4,7 +4,6 @@ #include #include #include "ec.h" -#include void mainboard_ec_init(void) { diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index b8266b31dc..1e0006ce01 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include "ec.h" static void mainboard_init(struct device *dev) @@ -16,7 +15,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index b2d1cbe355..4e91db48e9 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index b385ad7c8d..71e209e4ef 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -51,12 +51,11 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, + GPI(trig_edge_both, L1, P_20K_H, maskable, en_edge_detect, NA, NA), /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr assumed gpio number */ @@ -92,8 +91,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 9491c25d99..5723acf262 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -51,8 +51,8 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPI(trig_edge_both, L0, NA, 0, en_edge_detect, NA, NA), + /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +90,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ GPIO_NC, /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ @@ -124,8 +123,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { assert it low. */ GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + GPIO_NC, /* 95 RTK_AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ GPIO_END diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index c1b43b88ec..d285c045a3 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 4e4b01a5c1..23fe4e1abf 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index ece6c8058d..13cc6398bf 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 5a0c13a6a3..2d308f5ec7 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index cdf57a447b..c57d28cbbf 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 11071eb560..d2e79f1046 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl index d2a72088f3..88523450e7 100644 --- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl @@ -173,7 +173,7 @@ Device (DPTF) Method (_OSC, 4, Serialized) { /* Check for Passive Policy UUID */ - If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + If (LEqual (DeRefOf (IDSP[0]), Arg0)) { /* Initialize Thermal Devices */ ^TINI () @@ -206,7 +206,7 @@ Device (DPTF) Multiply (Arg0, 10, Local0) /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index cef45aa609..ede6229a9b 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU20K(2), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index 6e993305bb..3bb3931c50 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -51,8 +51,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { GPIO_NC, /* 69 MMC1_RCLK */ Native_M1, /* 75 GPO USB_OC1_B */ Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA), - /* GPIO_ALERT 77 */ + GPIO_NC, /* GPIO_ALERT 77 */ Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ @@ -90,8 +89,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* 34 MF_HDA_DOCKRSTB */ GPIO_NC, /* 35 MF_HDA_SYNC */ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 7599295f1f..c32c3b0f1e 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -37,3 +38,9 @@ int get_write_protect_state(void) { return !gpio_get_value(GPIO_D16); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get_value(GPIO_D17); +} diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 64fca47600..07b7bf13e1 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9360 select DRIVERS_INTEL_DPTF select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI @@ -46,6 +47,9 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 if BOARD_GOOGLE_BASEBOARD_DEDEDE +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BASEBOARD_DEDEDE_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP @@ -111,6 +115,7 @@ config MAINBOARD_PART_NUMBER default "Corori" if BOARD_GOOGLE_CORORI default "Driblee" if BOARD_GOOGLE_DRIBLEE default "Gooey" if BOARD_GOOGLE_GOOEY + default "Beadrix" if BOARD_GOOGLE_BEADRIX config MAX_CPUS int @@ -148,6 +153,7 @@ config VARIANT_DIR default "corori" if BOARD_GOOGLE_CORORI default "driblee" if BOARD_GOOGLE_DRIBLEE default "gooey" if BOARD_GOOGLE_GOOEY + default "beadrix" if BOARD_GOOGLE_BEADRIX endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index ea6f35c6ae..b92f1374c0 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -1,7 +1,7 @@ comment "Dedede" config BOARD_GOOGLE_BOTEN - bool "-> Boten" + bool "-> Boten (Lenovo 500e Chromebook Gen 3)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -20,6 +20,11 @@ config BOARD_GOOGLE_DRAWCIA select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + help + The Drawcia board supports the following devices: + - HP Chromebook x360 11 G4 EE (Drawcia) + - HP Chromebook 11 G9 EE (Drawlat) + - HP Chromebook 14 G7 (Drawman) config BOARD_GOOGLE_HABOKI bool "-> HABOKI" @@ -88,7 +93,7 @@ config BOARD_GOOGLE_GALTIC select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_SASUKE - bool "-> Sasuke" + bool "-> Sasuke (Samsung Galaxy Chromebook Go)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A @@ -96,7 +101,7 @@ config BOARD_GOOGLE_SASUKE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_STORO - bool "-> Storo" + bool "-> Storo (Asus Chromebook CR1100)" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA @@ -120,6 +125,7 @@ config BOARD_GOOGLE_BLIPPER bool "-> Blipper" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_CRET bool "-> Cret" @@ -145,6 +151,7 @@ config BOARD_GOOGLE_BUGZZY select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_CORORI bool "-> Corori" @@ -163,3 +170,9 @@ config BOARD_GOOGLE_GOOEY select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + +config BOARD_GOOGLE_BEADRIX + bool "-> Beadrix" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index fb904cca83..ad37b204bb 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -30,3 +32,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/dedede/fw_config.c b/src/mainboard/google/dedede/fw_config.c index 895f4891f5..7e5d8fa2e2 100644 --- a/src/mainboard/google/dedede/fw_config.c +++ b/src/mainboard/google/dedede/fw_config.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index dba4795293..700b3e368a 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -9,7 +9,6 @@ #include #include #include -#include static void mainboard_update_soc_chip_config(void) { @@ -68,7 +67,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_dev_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fa1ad8d1e8..1349f69dab 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -10,6 +10,10 @@ fw_config option DB_PORTS_1C 7 option DB_PORTS_1A_HDMI_LTE 8 end + field STYLUS 4 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end field TABLETMODE 10 option TABLETMODE_DISABLED 0 option TABLETMODE_ENABLED 1 @@ -199,9 +203,6 @@ chip soc/intel/jasperlake # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s - # Enable HECI - register "HeciEnabled" = "1" - # Set xHCI LFPS period sampling off time, the default is 9ms. register "xhci_lfps_sampling_offtime_ms" = "9" diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 9b3bd7062d..e1b920ab07 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -2,10 +2,10 @@ #include #include -#include +#include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ /* A0 : ESPI_IO0 */ @@ -423,6 +423,9 @@ static const struct pad_config early_gpio_table[] = { /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), + /* C14 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C20 : UART2 RX */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2 TX */ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc similarity index 60% rename from src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc rename to src/mainboard/google/dedede/variants/beadrix/Makefile.inc index cc5cdc1ace..11510200a5 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/Makefile.inc @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c new file mode 100644 index 0000000000..0732355657 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + /* A11 : TOUCH_RPT_EN ==> NC */ + PAD_NC(GPP_A11, NONE), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_B7, 1, DEEP), + + /* C18 : AP_I2C_EMR_SDA ==> NC */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL ==> NC */ + PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N ==> NC */ + PAD_NC(GPP_C22, NONE), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP2800_CAMERA ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> TP */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> TP */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 ==> TP */ + PAD_NC(GPP_D21, NONE), + + /* E1 : EMR_RESET_L ==> NC */ + PAD_NC(GPP_E1, NONE), + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E5 : AP_SUB_IO_2 ==> TP */ + PAD_NC(GPP_E5, NONE), + /* E10 : GPP_E10/SML_DATA0 ==> NC */ + PAD_NC(GPP_E10, NONE), + + /* G0 : SD_CMD ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK ==> NC */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), + + /* H1 : EN_PP3300_SD_U ==> NC */ + PAD_NC(GPP_H1, NONE), + /* H17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h b/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h b/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/beadrix/memory.c b/src/mainboard/google/dedede/variants/beadrix/memory.c new file mode 100644 index 0000000000..bfef45bf36 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg board_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x00, 0x0}, + {0x00, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on SoC + * the value = pin number on LPDDR4 part + */ + .dqs_map[DDR_CH0] = {0, 3, 2, 1, 7, 5, 4, 6}, + .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 7, 6, 5}, + + /* Disable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &board_memcfg_cfg; +} diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc new file mode 100644 index 0000000000..4fceb1a39d --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt new file mode 100644 index 0000000000..b44c6f79bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt new file mode 100644 index 0000000000..9e8cf19fe4 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -0,0 +1,13 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name +MT53E512M32D1NP-046 WT:B +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb new file mode 100644 index 0000000000..9c6d931f22 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -0,0 +1,97 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 05.0 off end # IPU - MIPI Camera + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""UFCamera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 3.3 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2635"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 0 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/beadrix/variant.c b/src/mainboard/google/dedede/variants/beadrix/variant.c new file mode 100644 index 0000000000..22caa069d3 --- /dev/null +++ b/src/mainboard/google/dedede/variants/beadrix/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} diff --git a/src/mainboard/google/dedede/variants/blipper/gpio.c b/src/mainboard/google/dedede/variants/blipper/gpio.c index 2244557010..8b754ee621 100644 --- a/src/mainboard/google/dedede/variants/blipper/gpio.c +++ b/src/mainboard/google/dedede/variants/blipper/gpio.c @@ -3,9 +3,8 @@ #include #include #include -#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C18 : AP_I2C_EMR_SDA */ PAD_NC(GPP_C18, NONE), diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index 6046acb94f..5085917b27 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -3,9 +3,8 @@ #include #include #include -#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c index 584ddb6d09..432c950190 100644 --- a/src/mainboard/google/dedede/variants/boten/variant.c +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -7,7 +7,14 @@ #include #include -#define SKU_ID_BOTENFLEX 0x90000 +enum { + SKU_ID_BOTEN_MIN = 0x60000, + SKU_ID_BOTEN_MAX = 0x6ffff, + SKU_ID_BOTENFLEX_MIN = 0x90000, + SKU_ID_BOTENFLEX_MAX = 0x9ffff, + SKU_ID_BOOKEM_MIN = 0x290000, + SKU_ID_BOOKEM_MAX = 0x29ffff, +}; static void power_off_lte_module(void) { @@ -30,8 +37,12 @@ const char *get_wifi_sar_cbfs_filename(void) { uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id >= SKU_ID_BOTENFLEX) + if (sku_id >= SKU_ID_BOTEN_MIN && sku_id <= SKU_ID_BOTEN_MAX) + return "wifi_sar-boten.hex"; + if (sku_id >= SKU_ID_BOTENFLEX_MIN && sku_id <= SKU_ID_BOTENFLEX_MAX) return "wifi_sar-botenflex.hex"; + if (sku_id >= SKU_ID_BOOKEM_MIN && sku_id <= SKU_ID_BOOKEM_MAX) + return "wifi_sar-bookem.hex"; - return "wifi_sar-boten.hex"; + return WIFI_SAR_CBFS_DEFAULT_FILENAME; } diff --git a/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc b/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc index fd60a18b69..74121943dd 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc +++ b/src/mainboard/google/dedede/variants/bugzzy/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/bugzzy/gpio.c b/src/mainboard/google/dedede/variants/bugzzy/gpio.c index a218c5ee5a..6d94cece96 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/gpio.c +++ b/src/mainboard/google/dedede/variants/bugzzy/gpio.c @@ -5,7 +5,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), @@ -46,6 +46,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E0, NONE), /* E1 : EMR_RESET_L */ PAD_CFG_GPO(GPP_E1, 0, DEEP), + /* E10 : LTE_SAR_SENSOR_INT */ + PAD_CFG_GPI_APIC(GPP_E10, NONE, PLTRST, LEVEL, NONE), /* E13 : DDI0_DDC_SCL */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* E14 : DDI0_DDC_SDA */ diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index 453d8c3f52..30e5e454dc 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,6 +2,15 @@ chip soc/intel/jasperlake # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + # Disable PCIe Root Port 8 (index 7) register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) @@ -45,7 +54,7 @@ chip soc/intel/jasperlake #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | Digitizer, P-sensor(LTE) | #| I2C2 | Touchscreen | #| I2C3 | Camera | #| I2C4 | Audio | @@ -63,12 +72,18 @@ chip soc/intel/jasperlake }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 133, + .fall_time_ns = 29, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 227, + .fall_time_ns = 9, }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 91, + .fall_time_ns = 2, }, .i2c[4] = { .speed = I2C_SPEED_FAST, @@ -114,10 +129,10 @@ chip soc/intel/jasperlake } }" register "controls.charger_perf" = "{ - [0] = { 55, 3500 }, - [1] = { 47, 3000 }, - [2] = { 39, 2500 }, - [3] = { 31, 2000 }, + [0] = { 255, 2800 }, + [1] = { 39, 2500 }, + [2] = { 31, 2000 }, + [3] = { 23, 1500 }, }" device generic 0 on end end @@ -194,6 +209,17 @@ chip soc/intel/jasperlake register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end end + chip drivers/i2c/sx9360 + register "desc" = ""SAR Proximity Sensor - LTE"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E10_IRQ)" + register "uid" = "1" + register "proxraw_strength" = "1" + register "avg_pos_strength" = "256" + register "resolution" = "1024" + device i2c 28 on + probe DB_PORTS DB_PORTS_1C_1A_LTE + end + end end # I2C #1 device pci 15.2 on chip drivers/i2c/hid @@ -202,7 +228,7 @@ chip soc/intel/jasperlake register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "200" register "generic.reset_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" diff --git a/src/mainboard/google/dedede/variants/bugzzy/ramstage.c b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c new file mode 100644 index 0000000000..7844b6e360 --- /dev/null +++ b/src/mainboard/google/dedede/variants/bugzzy/ramstage.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void panel_power_on(uintptr_t igd_bar) +{ + setbits32((void *)(igd_bar + PCH_PP_CONTROL), PANEL_POWER_ON); +} + +static void panel_reset_assert(uintptr_t igd_bar) +{ + clrsetbits32((void *)(igd_bar + PCH_GPIOB), + GPIO_CLOCK_VAL_OUT, + GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK); +} + +static void panel_reset_deassert(uintptr_t igd_bar) +{ + const uint32_t data32 = GPIO_CLOCK_VAL_OUT | + GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_VAL_MASK; + setbits32((void *)(igd_bar + PCH_GPIOB), data32); +} + +/* + * Bugzzy uses panel-built-in touch screen, it needs to set panel power and + * reset signal to high for touch screen to work. + * On user mode, coreboot doesn't initialize graphics since there is no screen + * display before OS. We would add this WA to initialize required signals on + * user mode. + */ +static void wa_init_display_signal(void *unused) +{ + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + uintptr_t igd_bar; + + if (display_init_required() || !igd_dev) + return; + + igd_bar = find_resource(igd_dev, PCI_BASE_ADDRESS_0)->base; + if (!igd_bar) + return; + + panel_power_on(igd_bar); + mdelay(20); + panel_reset_deassert(igd_bar); + mdelay(2); + panel_reset_assert(igd_bar); + mdelay(2); + panel_reset_deassert(igd_bar); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, wa_init_display_signal, NULL); diff --git a/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc b/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc index 31d1f7cb34..5bd1974076 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/cret/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/cret/memory src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt index ae467ecca2..fc789d367b 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/cret/memory/dram_id.generated.txt @@ -8,3 +8,5 @@ H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D2NP-046 WT:F 0 (0000) K4U6E3S4AA-MGCR 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt index c1e9e0c925..d16388475c 100644 --- a/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt @@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:F K4U6E3S4AA-MGCR MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 9786547462..fa4d4d57c5 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -7,14 +7,14 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config not_board6or8_gpio_table[] = { /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), }; -/* bid6: Pad configuration for board version 6 or 8 in ramstage*/ +/* bid6: Pad configuration for board version 6 or 8 in ramstage */ static const struct pad_config board6or8_gpio_table[] = { /* A10 : WWAN_EN */ diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc index 96284d1923..f975bfb463 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/memory/Makefile.inc @@ -4,4 +4,4 @@ # ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/drawcia/memory src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL, K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt index 78cc95d723..8a3c5c8703 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ K4U6E3S4AA-MGCR 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) H54G46CYRBX267 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt index f195c2526e..4a3e217521 100644 --- a/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/drawcia/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ K4U6E3S4AA-MGCR MT53E512M32D1NP-046 WT:B H54G46CYRBX267 K4U6E3S4AB-MGCL +K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index cb3ff48979..2b32e9b111 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -314,12 +314,13 @@ chip soc/intel/jasperlake register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset #_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "6" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[5]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" #_OFF register "off_seq.ops_cnt" = "4" @@ -342,12 +343,16 @@ chip soc/intel/jasperlake register "low_power_probe" = "1" register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D12" #reset #_ON - register "on_seq.ops_cnt" = "1" + register "on_seq.ops_cnt" = "2" register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" #_OFF - register "off_seq.ops_cnt" = "1" + register "off_seq.ops_cnt" = "2" register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + device i2c 0C on end end chip drivers/intel/mipi_camera diff --git a/src/mainboard/google/dedede/variants/galtic/gpio.c b/src/mainboard/google/dedede/variants/galtic/gpio.c index 79646b5e2e..e2e66692df 100644 --- a/src/mainboard/google/dedede/variants/galtic/gpio.c +++ b/src/mainboard/google/dedede/variants/galtic/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc index 016e8ea290..7b9f433b2d 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt index 9d92cf1f97..8d15cd91ab 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -6,5 +6,6 @@ DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D2NP-046 WT:E 0 (0000) +K4UBE3D4AA-MGCR 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index b92e5f1cb9..03c8be07f5 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -1,4 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E +K4UBE3D4AA-MGCR MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 150bfe3331..8004736d31 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -67,6 +67,9 @@ chip soc/intel/jasperlake register "tcc_offset" = "8" # TCC of 97C + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on # Default DPTF Policy for all Dedede boards if not overridden diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c index 72d91ee81f..558cba6251 100644 --- a/src/mainboard/google/dedede/variants/galtic/variant.c +++ b/src/mainboard/google/dedede/variants/galtic/variant.c @@ -1,9 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +enum { + GALTIC_SKU_START = 0x120000, + GALTIC_SKU_END = 0x12ffff, + GALITH_SKU_START = 0x130000, + GALITH_SKU_END = 0x13ffff, + GALLOP_SKU_START = 0x150000, + GALLOP_SKU_END = 0x15ffff, + GALTIC360_SKU_START = 0x260000, + GALTIC360_SKU_END = 0x26ffff, + GALITH360_SKU_START = 0x270000, + GALITH360_SKU_END = 0x27ffff, +}; const char *get_wifi_sar_cbfs_filename(void) { - return "wifi_sar-galtic.hex"; + uint32_t sku_id = google_chromeec_get_board_sku(); + + if (sku_id >= GALTIC_SKU_START && sku_id <= GALTIC_SKU_END) + return "wifi_sar-galtic.hex"; + if (sku_id >= GALTIC360_SKU_START && sku_id <= GALTIC360_SKU_END) + return "wifi_sar-galtic360.hex"; + if (sku_id >= GALITH360_SKU_START && sku_id <= GALITH360_SKU_END) + return "wifi_sar-galith360.hex"; + + return WIFI_SAR_CBFS_DEFAULT_FILENAME; } diff --git a/src/mainboard/google/dedede/variants/gooey/gpio.c b/src/mainboard/google/dedede/variants/gooey/gpio.c index 6046acb94f..5085917b27 100644 --- a/src/mainboard/google/dedede/variants/gooey/gpio.c +++ b/src/mainboard/google/dedede/variants/gooey/gpio.c @@ -3,9 +3,8 @@ #include #include #include -#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/haboki/gpio.c b/src/mainboard/google/dedede/variants/haboki/gpio.c index 03b9a45d7e..12286c6756 100644 --- a/src/mainboard/google/dedede/variants/haboki/gpio.c +++ b/src/mainboard/google/dedede/variants/haboki/gpio.c @@ -6,7 +6,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), diff --git a/src/mainboard/google/dedede/variants/kracko/gpio.c b/src/mainboard/google/dedede/variants/kracko/gpio.c index b4c00bdd3a..e8422fd618 100644 --- a/src/mainboard/google/dedede/variants/kracko/gpio.c +++ b/src/mainboard/google/dedede/variants/kracko/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index b9d6f72af7..3a9910b927 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 40 42 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/jasperlake # USB Port Configuration @@ -217,7 +224,23 @@ chip soc/intel/jasperlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end end #I2C 4 device pci 1f.3 on diff --git a/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc index 36d713ae2f..05cb4ed4c6 100644 --- a/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/madoo/memory/Makefile.inc @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/madoo/memory src/mainboard/google/dedede/variants/madoo/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 diff --git a/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt index e7b8668d01..14cf74e2fb 100644 --- a/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/madoo/memory/dram_id.generated.txt @@ -7,3 +7,6 @@ DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D2NP-046 WT:E 0 (0000) K4U6E3S4AA-MGCR 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/dedede/variants/madoo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/madoo/memory/mem_parts_used.txt index 2b339b6e07..17188e3f05 100644 --- a/src/mainboard/google/dedede/variants/madoo/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/madoo/memory/mem_parts_used.txt @@ -1,3 +1,6 @@ H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR +MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +H54G46CYRBX267 diff --git a/src/mainboard/google/dedede/variants/magolor/Makefile.inc b/src/mainboard/google/dedede/variants/magolor/Makefile.inc index 24c75d1d9a..33333832e8 100644 --- a/src/mainboard/google/dedede/variants/magolor/Makefile.inc +++ b/src/mainboard/google/dedede/variants/magolor/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/magolor/gpio.c b/src/mainboard/google/dedede/variants/magolor/gpio.c new file mode 100644 index 0000000000..ae890851d5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magolor/gpio.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/* Pad configuration of stylus */ +static const struct pad_config stylus_det_pads[] = { + /* C12 : AP_PEN_DET_ODL (external pull-high) */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_PRESENT))) + gpio_configure_pads(stylus_det_pads, ARRAY_SIZE(stylus_det_pads)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index de82a8a817..e0af22dd49 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -19,11 +19,13 @@ fw_config option TS_RAYD_0001 4 option TS_WDHT0002 5 option TS_GTCH7503 6 + option TS_ELAN_9004 7 end field AUDIO_CODEC_SOURCE 49 51 option AUDIO_CODEC_UNPROVISIONED 0 option AUDIO_CODEC_DA7219 1 option AUDIO_CODEC_RT5682 2 + option AUDIO_CODEC_ALC5682I_VS 3 end end @@ -106,6 +108,9 @@ chip soc/intel/jasperlake register "SlowSlewRate" = "SlewRateFastBy8" register "FastPkgCRampDisable" = "1" + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf @@ -186,6 +191,19 @@ chip soc/intel/jasperlake end end # I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on + probe STYLUS STYLUS_PRESENT + end + end chip drivers/i2c/hid register "generic.hid" = ""ELAN6915"" register "generic.desc" = ""ELAN Touchscreen"" @@ -227,6 +245,26 @@ chip soc/intel/jasperlake probe TS_SOURCE TS_ELAN_6918 end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TS_SOURCE TS_ELAN_9004 + end + end chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" @@ -450,20 +488,46 @@ chip soc/intel/jasperlake probe AUDIO_CODEC_SOURCE AUDIO_CODEC_DA7219 end end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end chip drivers/i2c/generic register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" - device i2c 28 on end + device i2c 28 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP R"" register "uid" = "1" - device i2c 29 on end + device i2c 29 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end end - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/generic/alc1015 + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on + probe AUDIO_AMP RT1015P_AUTO + end + end + end # Intel HDA device pci 1c.7 on chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" diff --git a/src/mainboard/google/dedede/variants/magolor/variant.c b/src/mainboard/google/dedede/variants/magolor/variant.c index 39a197a678..33c428c39b 100644 --- a/src/mainboard/google/dedede/variants/magolor/variant.c +++ b/src/mainboard/google/dedede/variants/magolor/variant.c @@ -14,6 +14,8 @@ enum { MAGISTER_SKU_END = 0xcffff, MAGMA_SKU_START = 0xd0000, MAGMA_SKU_END = 0xdffff, + MAGNETO_SKU_START = 0x110000, + MAGNETO_SKU_END = 0x11ffff, }; const char *get_wifi_sar_cbfs_filename(void) @@ -26,6 +28,8 @@ const char *get_wifi_sar_cbfs_filename(void) return "wifi_sar-magister.hex"; if (sku_id >= MAGMA_SKU_START && sku_id <= MAGMA_SKU_END) return "wifi_sar-magma.hex"; + if (sku_id >= MAGNETO_SKU_START && sku_id <= MAGNETO_SKU_END) + return "wifi_sar-magneto.hex"; return WIFI_SAR_CBFS_DEFAULT_FILENAME; } diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c index 2645e26d8a..072ea7b1c6 100644 --- a/src/mainboard/google/dedede/variants/metaknight/gpio.c +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -3,9 +3,8 @@ #include #include #include -#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 725750b654..06da2d48c3 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -69,6 +69,9 @@ chip soc/intel/jasperlake .tdp_pl2_override = 12, }" + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf @@ -243,15 +246,28 @@ chip soc/intel/jasperlake register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" - device i2c 28 on end + device i2c 28 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP R"" register "uid" = "1" - device i2c 29 on end + device i2c 29 on + probe AUDIO_AMP UNPROVISIONED + probe AUDIO_AMP RT1015_I2C + end end end - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/generic/alc1015 + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on + probe AUDIO_AMP RT1015P_AUTO + end + end + end # Intel HDA end end diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c index 79646b5e2e..e2e66692df 100644 --- a/src/mainboard/google/dedede/variants/pirika/gpio.c +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A11 : TOUCH_RPT_EN */ diff --git a/src/mainboard/google/dedede/variants/sasuke/gpio.c b/src/mainboard/google/dedede/variants/sasuke/gpio.c index f10121501a..8aa9f292e3 100644 --- a/src/mainboard/google/dedede/variants/sasuke/gpio.c +++ b/src/mainboard/google/dedede/variants/sasuke/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/sasukette/gpio.c b/src/mainboard/google/dedede/variants/sasukette/gpio.c index d9b1307928..78d72c750d 100644 --- a/src/mainboard/google/dedede/variants/sasukette/gpio.c +++ b/src/mainboard/google/dedede/variants/sasukette/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index a73caf5fc0..73b3c2a0c4 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), diff --git a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc index 49e92636b1..2f5ba21af9 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/storo/memory src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt index f450b73bd2..e627949af8 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt @@ -8,3 +8,4 @@ MT53E512M32D2NP-046 WT:E 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt index 0d11f123b1..901ff7bc72 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt @@ -13,3 +13,4 @@ MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE +K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/waddledee/gpio.c b/src/mainboard/google/dedede/variants/waddledee/gpio.c index 0905e8f217..dbb12dc788 100644 --- a/src/mainboard/google/dedede/variants/waddledee/gpio.c +++ b/src/mainboard/google/dedede/variants/waddledee/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* E5 : AP_SUB_IO_2 */ PAD_CFG_GPO(GPP_E5, 0, PLTRST), diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig index 644e4885aa..492bcbb698 100644 --- a/src/mainboard/google/deltaur/Kconfig +++ b/src/mainboard/google/deltaur/Kconfig @@ -14,18 +14,27 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TIGERLAKE select SYSTEM_TYPE_LAPTOP - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN - select SOC_INTEL_COMMON_BLOCK_HDA_VERB + +config BOARD_GOOGLE_DELTAN + select BOARD_GOOGLE_BASEBOARD_DELTAUR + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_GOOGLE_DELTAUR + select BOARD_GOOGLE_BASEBOARD_DELTAUR if BOARD_GOOGLE_BASEBOARD_DELTAUR +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config CHROMEOS select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_FORCE_DEV_SWITCH_ON - select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_ALTFW + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_SWITCH_ON config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/google/deltaur/Kconfig.name b/src/mainboard/google/deltaur/Kconfig.name index 5c4c12b479..2e04d6790d 100644 --- a/src/mainboard/google/deltaur/Kconfig.name +++ b/src/mainboard/google/deltaur/Kconfig.name @@ -2,8 +2,6 @@ comment "Deltaur" config BOARD_GOOGLE_DELTAN bool "-> Deltan" - select BOARD_GOOGLE_BASEBOARD_DELTAUR config BOARD_GOOGLE_DELTAUR bool "-> Deltaur" - select BOARD_GOOGLE_BASEBOARD_DELTAUR diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c index 9d3929e1df..778eccb0ea 100644 --- a/src/mainboard/google/deltaur/chromeos.c +++ b/src/mainboard/google/deltaur/chromeos.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include +#include #include #include #include #include +#include #include #include #include @@ -31,24 +32,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPIO_PCH_WP); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_REC_MODE); } void mainboard_chromeos_acpi_generate(void) @@ -61,11 +52,6 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -91,7 +77,7 @@ int get_recovery_mode_switch(void) state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ @@ -111,3 +97,10 @@ void mainboard_prepare_cr50_reset(void) if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c index e1cdb96959..7cca72a9de 100644 --- a/src/mainboard/google/deltaur/mainboard.c +++ b/src/mainboard/google/deltaur/mainboard.c @@ -1,17 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include -#include #include -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; @@ -26,5 +19,4 @@ static void mainboard_chip_init(void *chip_info) struct chip_operations mainboard_ops = { .init = mainboard_chip_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 72ed789aec..f5dc01910d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -25,8 +25,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SataEnable" = "1" - register "SataMode" = "0" register "SataSalpSupport" = "1" # TODO: the lengths are all MID for right now. @@ -52,6 +50,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[8]" = "1" # Mark unused SRCCLKREQs as so register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" @@ -131,7 +130,7 @@ chip soc/intel/tigerlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 off end # DPTF device pci 05.0 off end # IPU device pci 06.0 off end # PEG60 device pci 07.0 on end # TBT_PCIe0 @@ -291,7 +290,7 @@ chip soc/intel/tigerlake device pci 1f.1 off end # P2SB device pci 1f.2 hidden end # PMC device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.4 off end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller device pci 1f.6 off end # GbE Controller device pci 1f.7 off end # Intel Trace Hub diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c index 0715f275f5..9f77028522 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c +++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include #include +#include static const struct pad_config gpio_table[] = { /* A0 thru A6 are ESPI, configured elsewhere */ diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index 09e0987ed9..caa99a9b01 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -4,6 +4,7 @@ #include #include #include +#include static const struct mb_cfg baseboard_memcfg = { .type = MEM_TYPE_DDR4, diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 060a75ada9..60a07eb3d6 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -1,4 +1,3 @@ - config BOARD_GOOGLE_BASEBOARD_DRALLION def_bool n select BOARD_ROMSIZE_KB_32768 @@ -12,20 +11,29 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_EC_REGION select SMBIOS_SERIAL_FROM_VPD if VPD select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE select SYSTEM_TYPE_LAPTOP - select MAINBOARD_USES_IFD_EC_REGION - select HAVE_SPD_IN_CBFS + +config BOARD_GOOGLE_DRALLION + select BOARD_GOOGLE_BASEBOARD_DRALLION if BOARD_GOOGLE_BASEBOARD_DRALLION +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB diff --git a/src/mainboard/google/drallion/Kconfig.name b/src/mainboard/google/drallion/Kconfig.name index bd5d9032d2..5870571124 100644 --- a/src/mainboard/google/drallion/Kconfig.name +++ b/src/mainboard/google/drallion/Kconfig.name @@ -2,4 +2,3 @@ comment "Drallion" config BOARD_GOOGLE_DRALLION bool "-> Drallion" - select BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index d92ebb133d..0891f87c9b 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include #include +#include #include #include #include @@ -29,24 +30,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -59,11 +50,6 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -89,7 +75,7 @@ int get_recovery_mode_switch(void) state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ @@ -110,3 +96,10 @@ void mainboard_prepare_cr50_reset(void) pmc_soc_set_afterg3_en(true); #endif } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c index d44c7b19d3..185766bdc9 100644 --- a/src/mainboard/google/drallion/ramstage.c +++ b/src/mainboard/google/drallion/ramstage.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include -#include /* mainboard silk screen shows DIMM-A and DIMM-B */ void smbios_fill_dimm_locator(const struct dimm_info *dimm, @@ -32,12 +30,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(gpio_table, num_gpios); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 105eddbb1f..fd1153c30e 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -411,7 +411,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 007cbc7287..ec861853a5 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -1,5 +1,8 @@ if BOARD_GOOGLE_EVE +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 @@ -24,6 +27,9 @@ config BOARD_SPECIFIC_OPTIONS select SYSTEM_TYPE_CONVERTIBLE select HAVE_SPD_IN_CBFS +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 11931c676d..bc458dea77 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include #include "gpio.h" @@ -34,3 +36,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 8ea6539bec..1e9ffd9255 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -37,14 +37,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 607486be4c..ad77eb5ffa 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -225,6 +225,9 @@ static const struct pad_config early_gpio_table[] = { /* Ensure UART pins are in native mode for H1 */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/eve/mainboard.c b/src/mainboard/google/eve/mainboard.c index 35c0a61953..4abb91e57f 100644 --- a/src/mainboard/google/eve/mainboard.c +++ b/src/mainboard/google/eve/mainboard.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "gpio.h" @@ -58,7 +57,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index cac3e4f225..3e2b8c171b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -1,9 +1,6 @@ - config BOARD_GOOGLE_BASEBOARD_FIZZ def_bool n select BOARD_ROMSIZE_KB_16384 - select DRIVERS_GENERIC_MAX98357A if BOARD_GOOGLE_KARMA - select DRIVERS_I2C_DA7219 if BOARD_GOOGLE_KARMA select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI @@ -11,24 +8,41 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC - select EXCLUDE_NATIVE_SD_INTERFACE if BOARD_GOOGLE_KARMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT - select NO_FADT_8042 - select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select NO_FADT_8042 + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD select RT8168_GET_MAC_FROM_VPD select RT8168_SUPPORT_LEGACY_VPD_MAC select RT8168_SET_LED_MODE - select SPD_READ_BY_WORD + +config BOARD_GOOGLE_FIZZ + select BOARD_GOOGLE_BASEBOARD_FIZZ + +config BOARD_GOOGLE_KARMA + select BOARD_GOOGLE_BASEBOARD_FIZZ + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select EXCLUDE_NATIVE_SD_INTERFACE + +config BOARD_GOOGLE_ENDEAVOUR + select BOARD_GOOGLE_BASEBOARD_FIZZ if BOARD_GOOGLE_BASEBOARD_FIZZ +config DISABLE_HECI1_AT_PRE_BOOT + default y + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name index 45cdbd9388..7c792397d2 100644 --- a/src/mainboard/google/fizz/Kconfig.name +++ b/src/mainboard/google/fizz/Kconfig.name @@ -2,12 +2,9 @@ comment "Fizz" config BOARD_GOOGLE_FIZZ bool "-> Fizz" - select BOARD_GOOGLE_BASEBOARD_FIZZ config BOARD_GOOGLE_KARMA bool "-> Karma" - select BOARD_GOOGLE_BASEBOARD_FIZZ config BOARD_GOOGLE_ENDEAVOUR bool "-> Endeavour" - select BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index a74c2f7091..d10a59f610 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include +#include #include #include @@ -34,3 +36,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 0945b9c8ce..13bc9b70ca 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include #include -#include #include @@ -222,7 +222,6 @@ static void mainboard_enable(struct device *dev) mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e79f7044fa..5ecc77bc77 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -66,7 +66,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" @@ -75,7 +74,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 2ebc51ad04..4787d2df5a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ @@ -240,6 +241,9 @@ static const struct pad_config early_gpio_table[] = { /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; const struct pad_config * __weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fizz/variants/karma/data.vbt b/src/mainboard/google/fizz/variants/karma/data.vbt index dbbf475f217e51dc4ae999081a05079e45efd2e8..460c5eeff49801df1a61aac98946e29fb233a195 100644 GIT binary patch delta 35 qcmZorX;7IU#k`EcV6r2V@J0iEMs5xk1`Y=X4h04dfz4iw+XMiP3I_=Q delta 35 kcmZorX;7IU#jM3(Fxinwc%uP7BR2~J0}O5UV%#PG0DA@o2><{9 diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 2735fed671..8b88f23640 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -245,6 +245,9 @@ static const struct pad_config early_gpio_table[] = { /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ + +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 38d12cb696..9ac4cf0168 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include void fill_lb_gpios(struct lb_gpios *gpios) { @@ -26,3 +26,10 @@ int get_write_protect_state(void) { return 0; } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index 7c34756f86..827070397e 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -12,7 +12,6 @@ #include #include -#include static const struct pad_config sdmmc1_pad[] = { /* MMC1(SDCARD) */ diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 4674581da8..54646406b9 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -9,7 +10,6 @@ #include #include #include -#include #define PP_SW 41 @@ -157,3 +157,10 @@ int get_write_protect_state(void) { return !read_gpio(get_wp_status_gpio_pin()); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index 9bdd307bc1..6dfc2307af 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -2,7 +2,7 @@ #include #include -#include +#include #define TPM_RESET_GPIO 19 diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 4b0275f641..68e4f7199d 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -12,19 +12,75 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SOC_INTEL_SKYLAKE select SYSTEM_TYPE_LAPTOP - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS - select HAVE_SPD_IN_CBFS + +config BOARD_GOOGLE_ASUKA + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select EXCLUDE_NATIVE_SD_INTERFACE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_CAROLINE + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DSAR_ENABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS + select SAR_ENABLE + select USE_SAR + +config BOARD_GOOGLE_CAVE + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_CHELL + select BOARD_GOOGLE_BASEBOARD_GLADOS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_GLADOS + select BOARD_GOOGLE_BASEBOARD_GLADOS + select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_LARS + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select EXCLUDE_NATIVE_SD_INTERFACE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_SENTRY + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select INTEL_GMA_HAVE_VBT + select MAINBOARD_NO_FSP_GOP + select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS if BOARD_GOOGLE_BASEBOARD_GLADOS +config DISABLE_HECI1_AT_PRE_BOOT + default y + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index 5b1c383ce7..11a53c5cdd 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -2,47 +2,21 @@ comment "Glados" config BOARD_GOOGLE_ASUKA bool "-> Asuka (Dell Chromebook 13 3380)" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_GENERIC_MAX98357A - select EXCLUDE_NATIVE_SD_INTERFACE - select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_CAROLINE bool "-> Caroline (Samsung Chromebook Pro)" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select DSAR_ENABLE - select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS - select SAR_ENABLE - select USE_SAR config BOARD_GOOGLE_CAVE bool "-> Cave (Asus Chromebook Flip C302SA)" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_GENERIC_MAX98357A - select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_CHELL bool "-> Chell (HP Chromebook 13 G1)" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_GLADOS bool "-> Glados Skylake Reference Board" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS - select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_LARS bool "-> Lars (Acer Chromebook 14 for Work (CP5-471))" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_GENERIC_MAX98357A - select EXCLUDE_NATIVE_SD_INTERFACE - select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_SENTRY bool "-> Sentry (Lenovo Thinkpad 13 Chromebook)" - select BOARD_GOOGLE_BASEBOARD_GLADOS - select DRIVERS_GENERIC_MAX98357A - select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS - select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS - select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 6a1f0b4358..1adaed412f 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include #include @@ -33,3 +35,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 65e1014992..9a3e619499 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -36,14 +36,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 0d6a49942e..faa80b9cbb 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "ec.h" static const char *oem_id_maxim = "INTEL"; @@ -96,7 +95,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } static void mainboard_chip_init(void *chip_info) diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 85b394f430..882aff6da9 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index 17c24a2ed7..758b7cc321 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -214,11 +214,12 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index f570006180..fe31102f64 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -231,11 +231,12 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index 45e1f67531..e96a78a379 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -223,11 +223,12 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 1c92e51df9..326047262d 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -217,13 +217,14 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index a7bcdd7435..b812fb7a13 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -220,12 +220,14 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ /* GPD11 */ }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, + DEEP), /* EC_IN_RW */ }; #endif diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index acbf157ac0..7cf56aac8f 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -208,13 +208,14 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl index 3c71e713d1..1d4405507a 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #define DPTF_CPU_PASSIVE 90 -#define DPTF_CPU_CRITICAL 98 +#define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 77 diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index a2052a3379..10291b02ec 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -216,13 +216,14 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 688c0dd27a..479ca3d85d 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -49,3 +49,9 @@ int tis_plat_irq_status(void) return gpio_irq_status(GPIO_TPM_IRQ); } #endif + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 1690fb2142..53277715a2 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -17,7 +18,6 @@ #include #include #include -#include #include "board.h" @@ -247,12 +247,12 @@ static void configure_display(void) static void usb_power_cycle(int port) { if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) - printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); + printk(BIOS_ERR, "Cannot force USB%d PD sink\n", port); mdelay(10); /* Make sure USB stick is fully depowered. */ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) - printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); + printk(BIOS_ERR, "Cannot restore USB%d PD mode\n", port); } static void setup_usb(int port) diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index c97c06d963..ecec68849a 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -5,10 +5,14 @@ config BOARD_GOOGLE_BASEBOARD_GUYBRUSH if BOARD_GOOGLE_BASEBOARD_GUYBRUSH +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select CONSOLE_CBMEM_DUMP_TO_UART if !CONSOLE_SERIAL select DISABLE_KEYBOARD_RESET_PIN select DISABLE_SPI_FLASH_ROM_SHARING select DRIVERS_ACPI_THERMAL_ZONE @@ -38,10 +42,13 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE - select PSP_DISABLE_POSTCODES + select PSP_DISABLE_POSTCODES if !VBOOT_STARTS_BEFORE_BOOTBLOCK + select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF + select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -94,6 +101,15 @@ config AMDFW_CONFIG_FILE string default "src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg" +config HAVE_SPL_FILE + bool + default y + +config SPL_TABLE_FILE + string + depends on HAVE_SPL_FILE + default "3rdparty/blobs/mainboard/google/guybrush/TypeId0x55_SplTable_Prod_CZN_Chrome.sbin" + if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 4 # Dual IO (1-2-2) @@ -123,6 +139,7 @@ config OVERRIDE_EFS_SPI_SPEED config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD hex default 0x4 if BOARD_GOOGLE_GUYBRUSH + default 0x2 if BOARD_GOOGLE_NIPPERKIN default 0xffffffff help Minimum board version starting which the Override EFS SPI Speed diff --git a/src/mainboard/google/guybrush/Kconfig.name b/src/mainboard/google/guybrush/Kconfig.name index e8b1b32a1d..a682c76079 100644 --- a/src/mainboard/google/guybrush/Kconfig.name +++ b/src/mainboard/google/guybrush/Kconfig.name @@ -7,6 +7,7 @@ config BOARD_GOOGLE_GUYBRUSH config BOARD_GOOGLE_NIPPERKIN bool "-> Nipperkin" select BOARD_GOOGLE_BASEBOARD_GUYBRUSH + select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_DEWATT bool "-> Dewatt" diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 6bc3288276..56ef2b38b2 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -3,14 +3,6 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),) -$(info APCB sources present.) -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin -else -$(info APCB sources not found. Skipping APCB.) -endif - romstage-y += port_descriptors.c romstage-y += romstage.c @@ -18,6 +10,8 @@ ramstage-y += mainboard.c ramstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += spi_speeds.c + verstage-y += verstage.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -28,3 +22,13 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include LIB_SPD_DEPS = $(SPD_SOURCES) + +APCB_SOURCES = $(obj)/APCB_CZN_D4.gen +APCB_SOURCES_RECOVERY = $(obj)/APCB_CZN_D4.gen + +$(obj)/APCB_CZN_D4.gen: $(SPD_SOURCES) \ + $(APCB_V3_EDIT_TOOL) \ + $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin + $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin \ + $(obj)/APCB_CZN_D4.gen \ + --spd_sources $(SPD_SOURCES) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 83ac43ac41..800e70a294 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include -#include #include #include #include #include -#include -#include -#include +#include #include #include @@ -30,16 +26,10 @@ void mb_set_up_early_espi(void) void bootblock_mainboard_early_init(void) { - uint32_t dword; - size_t base_num_gpios, override_num_gpios; - const struct soc_amd_gpio *base_gpios, *override_gpios; + size_t num_gpios, override_num_gpios; + const struct soc_amd_gpio *gpios, *override_gpios; - /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped - on Picasso and older compared to Renoir/Cezanne and newer */ - dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); - dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); - dword |= LPC_LDRQ0_PD_EN; - pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + espi_disable_lpc_ldrq(); /* * All LPC decodes need to be cleared before we can configure the LPC pads as secondary @@ -50,11 +40,15 @@ void bootblock_mainboard_early_init(void) if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) return; - base_gpios = variant_early_gpio_table(&base_num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); - gpio_configure_pads_with_override(base_gpios, base_num_gpios, - override_gpios, override_num_gpios); + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); /* Set a timer to make sure there's enough delay for * the Fibocom 350 PCIe init @@ -63,14 +57,7 @@ void bootblock_mainboard_early_init(void) /* Early eSPI interface configuration */ - dword = pm_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_write32(PM_SPI_PAD_PU_PD, dword); - - /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ - dword = pm_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_write32(PM_ACPI_CONF, dword); + espi_switch_to_spi2_pads(); } void bootblock_mainboard_init(void) @@ -98,8 +85,4 @@ void bootblock_mainboard_init(void) gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, override_num_gpios); - - /* FPMCU check needs to happen after EC initialization for FW_CONFIG bits */ - if (variant_has_fpmcu()) - variant_fpmcu_reset(); } diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c index df99e6434b..9875554d64 100644 --- a/src/mainboard/google/guybrush/chromeos.c +++ b/src/mainboard/google/guybrush/chromeos.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -27,10 +28,13 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } -void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +int get_ec_is_trusted(void) { - uint32_t board_ver = board_id(); - - if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) - *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; + /* Board versions 1 & 2 support H1 DB, but the EC_IN_RW signal is not + routed. So emulate EC is trusted. */ + if (CONFIG(BOARD_GOOGLE_GUYBRUSH) && + (board_id() == UNDEFINED_STRAPPING_ID || board_id() < 3)) + return 1; + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); } diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd index 38757003a7..a6dbc2c2ae 100644 --- a/src/mainboard/google/guybrush/chromeos.fmd +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -22,6 +22,7 @@ FLASH@0xFF000000 16M { RW_LEGACY(CBFS) WP_RO@8M 8M { RO_VPD(PRESERVE) 16K + RO_GSCVD 8K RO_SECTION { FMAP 2K RO_FRID 64 diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index b2d669c443..cab570672d 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -10,7 +10,6 @@ #include #include #include -#include #define BACKLIGHT_GPIO GPIO_129 #define WWAN_AUX_RST_GPIO GPIO_18 @@ -197,7 +196,6 @@ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; init_tables(); @@ -209,13 +207,7 @@ static void mainboard_enable(struct device *dev) pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); } -static void mainboard_final(void *chip_info) -{ - variant_finalize_gpios(); -} - struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, - .final = mainboard_final, }; diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index a98983b6bc..158a802322 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,6 +14,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .port_present = true, .start_logical_lane = 0, .end_logical_lane = 0, + .link_speed_capability = 3, .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_aspm = ASPM_L1, @@ -28,6 +29,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .port_present = true, .start_logical_lane = 1, .end_logical_lane = 1, + .link_speed_capability = 3, .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, @@ -43,6 +45,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .port_present = true, .start_logical_lane = 2, .end_logical_lane = 2, + .link_speed_capability = 3, .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_aspm = ASPM_L1, @@ -57,6 +60,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .port_present = true, .start_logical_lane = 4, .end_logical_lane = 7, + .link_speed_capability = 3, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_aspm = ASPM_L1, @@ -91,7 +95,7 @@ static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { }; /* TODO: verify the DDI table, since this is mostly an educated guess right now */ -static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { +static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, .aux_index = DDI_AUX1, @@ -123,6 +127,10 @@ void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptor { } +void __weak variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +{ +} + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) @@ -139,6 +147,7 @@ void mainboard_get_dxio_ddi_descriptors( guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors); + variant_update_ddi_descriptors(guybrush_czn_ddi_descriptors); *dxio_descs = guybrush_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); diff --git a/src/mainboard/google/guybrush/spi_speeds.c b/src/mainboard/google/guybrush/spi_speeds.c new file mode 100644 index 0000000000..857e02d900 --- /dev/null +++ b/src/mainboard/google/guybrush/spi_speeds.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +void mainboard_spi_fast_speed_override(uint8_t *fast_speed) +{ + uint32_t board_ver = board_id(); + + if (board_ver >= CONFIG_OVERRIDE_EFS_SPI_SPEED_MIN_BOARD) + *fast_speed = CONFIG_OVERRIDE_EFS_SPI_SPEED; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg b/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg index 911e4ae16e..fc7d1a43fb 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg +++ b/src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg @@ -29,7 +29,7 @@ DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT -PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin L2 -PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin L2 -PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin L2 -PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin L2 +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin L2 +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin L2 +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin L2 +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin L2 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 8a9543da2b..a9b0a154a1 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,33 +52,33 @@ chip soc/amd/cezanne register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" register "stt_min_limit" = "0" - register "stt_m1" = "0x0319" - register "stt_m2" = "0x01A0" + register "stt_m1" = "0x03A0" + register "stt_m2" = "0xFFC9" register "stt_m3" = "0" register "stt_m4" = "0" register "stt_m5" = "0" register "stt_m6" = "0" - register "stt_c_apu" = "0xE99F" + register "stt_c_apu" = "0x0901" register "stt_c_gpu" = "0" register "stt_c_hs2" = "0" - register "stt_alpha_apu" = "0xCCD" + register "stt_alpha_apu" = "0x199A" register "stt_alpha_gpu" = "0" register "stt_alpha_hs2" = "0" register "stt_skin_temp_apu" = "0x2D00" register "stt_skin_temp_gpu" = "0" register "stt_skin_temp_hs2" = "0" - register "stt_error_coeff" = "0xD" - register "stt_error_rate_coefficient" = "0x8F6" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" register "system_configuration" = "2" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" # I2C Pad Control RX Select Configuration - register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad - register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Touchscreen - register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR - register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # Touchscreen + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # Audio/SAR + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_REQ" @@ -316,7 +316,11 @@ chip soc/amd/cezanne chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_132)" + # TODO(rrangel): Find data sheet + register "enable_delay_ms" = "500" + register "enable_off_delay_ms" = "10" device ref usb2_port6 on end end end @@ -342,6 +346,8 @@ chip soc/amd/cezanne register "hid" = ""GOOG0005"" register "desc" = ""Cr50 TPM"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_85)" + register "power_managed_mode" = "CONFIG(PSP_S0I3_RESUME_VERSTAGE) ? + TPM_KERNEL_POWER_MANAGED : TPM_DEFAULT_POWER_MANAGED" device i2c 50 alias cr50 on end end end diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 89594faf42..fff98d2d87 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include -#include #include #include -/* GPIO configuration in ramstage*/ +/* GPIO configuration in ramstage */ /* Please make sure that *ALL* GPIOs are configured in this table */ static const struct soc_amd_gpio base_gpio_table[] = { /* PWR_BTN_L */ @@ -18,11 +16,11 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* WAKE_L */ PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), /* EN_PWR_FP */ - PAD_GPO(GPIO_3, HIGH), + PAD_GPO(GPIO_3, LOW), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ @@ -30,10 +28,10 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* EN_PWR_WWAN_X */ PAD_GPO(GPIO_8, HIGH), /* SOC_TCHPAD_INT_ODL */ - PAD_SCI(GPIO_9, PULL_NONE, EDGE_HIGH), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0A3 */ PAD_NF(GPIO_10, S0A3, PULL_NONE), - /* SOC_FP_RST_L - Brought high in finalize */ + /* SOC_FP_RST_L */ PAD_GPO(GPIO_11, LOW), /* SLP_S3_GATED */ PAD_GPO(GPIO_12, LOW), @@ -66,8 +64,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_GPO(GPIO_29, LOW), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_31, HIGH), + /* Unused */ + PAD_NC(GPIO_31), /* Unused */ PAD_NC(GPIO_32), /* GPIO_33 - GPIO_39: Not available */ @@ -81,10 +79,10 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_GPI(GPIO_67, PULL_NONE), /* EN_PP3300_TCHSCR */ PAD_GPO(GPIO_68, HIGH), - /* Unused */ - PAD_NC(GPIO_69), - /* Unused TP27 */ - PAD_NC(GPIO_70), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), + /* EN_SPKR */ + PAD_GPO(GPIO_70, HIGH), /* GPIO_71 - GPIO_73: Not available */ /* Unused TP49 */ PAD_NC(GPIO_74), @@ -117,7 +115,7 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* ESPI1_DATA1 */ PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), /* ESPI1_DATA2 */ - PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), + PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ @@ -170,16 +168,16 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { /* Assert all AUX reset lines */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, LOW), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, LOW), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, HIGH), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, LOW), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), @@ -199,30 +197,6 @@ static const struct soc_amd_gpio early_gpio_table[] = { /* WWAN_RST_L */ PAD_GPO(GPIO_24, LOW), -/* Enable ESPI, GSC Interrupt & I2C Communication */ - /* Unused */ - PAD_NC(GPIO_3), - /* I2C3_SCL */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* ESPI_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* ESPI_SOC_CLK */ - PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), - /* ESPI1_DATA0 */ - PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), - /* ESPI1_DATA1 */ - PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), - /* ESPI1_DATA2 */ - PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), - /* ESPI1_DATA3 */ - PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), - /* Enable UART 0 */ /* UART0_RXD */ PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), @@ -234,6 +208,32 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_GPI(GPIO_91, PULL_NONE), }; +static const struct soc_amd_gpio espi_gpio_table[] = { + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), + /* ESPI1_DATA0 */ + PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), + /* ESPI1_DATA1 */ + PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE), + /* ESPI1_DATA2 */ + PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE), + /* ESPI1_DATA3 */ + PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), +}; + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), +}; + /* Power-on timing requirements: * Fibocom 350-GL: * FCP0# goes high (GPIO 6) to Reset# high (GPIO 24): 20ms min @@ -275,36 +275,22 @@ static const struct soc_amd_gpio sleep_gpio_table[] = { /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio pcie_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* WWAN_AUX_RESET_L */ PAD_GPO(GPIO_18, HIGH), /* WLAN_AUX_RESET (ACTIVE HIGH) */ PAD_GPO(GPIO_29, LOW), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), - /* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ - PAD_NC(GPIO_69), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_69, HIGH), /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ PAD_NC(GPIO_70), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -static const struct soc_amd_gpio fpmcu_shutdown_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_3, LOW), -}; - -static const struct soc_amd_gpio fpmcu_disable_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_3), -}; - const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) { *size = ARRAY_SIZE(pcie_gpio_table); @@ -355,49 +341,18 @@ const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size) const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) { - if (acpi_get_sleep_type() == ACPI_S5) - return variant_fpmcu_shutdown_gpio_table(size); - *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } -const __weak struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) { - *size = ARRAY_SIZE(fpmcu_shutdown_gpio_table); - return fpmcu_shutdown_gpio_table; + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; } -const __weak struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) { - *size = ARRAY_SIZE(fpmcu_disable_gpio_table); - return fpmcu_disable_gpio_table; -} - -__weak void variant_fpmcu_reset(void) -{ - size_t size; - const struct soc_amd_gpio *gpio_table; - - if (acpi_get_sleep_type() == ACPI_S3) - return; - /* If the system is not resuming from S3, power off the FPMCU */ - gpio_table = variant_fpmcu_shutdown_gpio_table(&size); - gpio_configure_pads(gpio_table, size); -} - -__weak void variant_finalize_gpios(void) -{ - size_t size; - const struct soc_amd_gpio *gpio_table; - - if (variant_has_fpmcu()) { - if (acpi_get_sleep_type() == ACPI_S3) - return; - /* Deassert the FPMCU reset to enable the FPMCU */ - gpio_set(GPIO_11, 1); /* FPMCU_RST_L */ - } else { - gpio_table = variant_fpmcu_disable_gpio_table(&size); - gpio_configure_pads(gpio_table, size); - } + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; } diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c index 04c05bbcc1..fe30e15386 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/helpers.c +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -4,13 +4,6 @@ #include #include -WEAK_DEV_PTR(fpmcu); - -bool variant_has_fpmcu(void) -{ - return is_dev_enabled(DEV_PTR(fpmcu)); -} - bool __weak variant_has_pcie_wwan(void) { return false; @@ -18,5 +11,5 @@ bool __weak variant_has_pcie_wwan(void) uint8_t __weak variant_sd_aux_reset_gpio(void) { - return GPIO_5; + return GPIO_69; } diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 6cc96f8441..ec9dec8136 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -40,22 +40,16 @@ const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); -/* This function provides GPIO settings for fpmcu shutdown. */ -const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); -/* This function provides GPIO settings for fpmcu disable. */ -const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size); - -/* Finalize GPIOs, such as FPMCU power */ -void variant_finalize_gpios(void); - -void variant_fpmcu_reset(void); - -bool variant_has_fpmcu(void); +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); bool variant_has_pcie_wwan(void); void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); +void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors); enum dxio_port_id { WLAN, diff --git a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc index 88e75bde52..823860b4a3 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/Makefile.inc @@ -1,3 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +verstage-y += gpio.c + subdirs-y += ./memory + +romstage-y += variant.c diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c new file mode 100644 index 0000000000..94e7272d2c --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +/* This table is used by guybrush variant */ +static const struct soc_amd_gpio override_ramstage_gpio_table[] = { + /* Unused TP247*/ + PAD_NC(GPIO_3), + /* Unused TP218*/ + PAD_NC(GPIO_4), + /* Unused TP245*/ + PAD_NC(GPIO_8), + /* Unused TP244*/ + PAD_NC(GPIO_11), + /* Unused TP194*/ + PAD_NC(GPIO_17), + /* Unused TP195*/ + PAD_NC(GPIO_18), + /* Unused TP243*/ + PAD_NC(GPIO_21), + /* Unused TP196*/ + PAD_NC(GPIO_24), + /* Unused TP219*/ + PAD_NC(GPIO_42), + /* Unused TP217*/ + PAD_NC(GPIO_69), + /* Unused TP235*/ + PAD_NC(GPIO_115), + /* Unused TP205*/ + PAD_NC(GPIO_116), + /* Unused TP226*/ + PAD_NC(GPIO_140), + /* Unused TP225*/ + PAD_NC(GPIO_142), + /* Unused TP227*/ + PAD_NC(GPIO_144), + /* SOC_TCHPAD_INT_ODL */ + PAD_SCI(GPIO_9, PULL_NONE, LEVEL_LOW), +}; + +static const struct soc_amd_gpio override_early_gpio_table[] = { + /* Unused TP245*/ + PAD_NC(GPIO_8), + /* Unused TP195*/ + PAD_NC(GPIO_18), + /* Unused TP196*/ + PAD_NC(GPIO_24), + /* Unused TP217*/ + PAD_NC(GPIO_69), +}; + +/* This table is used by guybrush variant */ +static const struct soc_amd_gpio override_pcie_gpio_table[] = { + /* Unused TP195*/ + PAD_NC(GPIO_18), + /* Unused TP217*/ + PAD_NC(GPIO_69), +}; + + +static const struct soc_amd_gpio override_bootblock_gpio_table[] = { + /* Unused TP196*/ + PAD_NC(GPIO_24), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_ramstage_gpio_table); + return override_ramstage_gpio_table; +} + +const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_early_gpio_table); + return override_early_gpio_table; +} + +const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_pcie_gpio_table); + return override_pcie_gpio_table; +} + +const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(override_bootblock_gpio_table); + return override_bootblock_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 069b2eb0bf..02eafcb317 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -4,5 +4,7 @@ # util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index 5ce9e79cdc..d574a6f474 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -4,7 +4,17 @@ # util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/guybrush/variants/dewatt/memory src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt DRAM Part Name ID to assign -K4U6E3S4AB-MGCL 0 (0000) -H54G46CYRBX267 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:A 0 (0000) +MT53E512M32D2NP-046 WT:F 1 (0001) +NT6AP256T32AV-J1 2 (0010) +H9HCNNNBKMMLXR-NEE 1 (0001) +MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt index 4b6ba225ac..298e58b569 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt @@ -1,4 +1,14 @@ +MT53E1G32D2NP-046 WT:A +MT53E512M32D2NP-046 WT:F +NT6AP256T32AV-J1 +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR K4U6E3S4AB-MGCL H54G46CYRBX267 -MT53E1G32D2NP-046 WT:B MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index c182265075..6cb829349b 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -2,6 +2,176 @@ chip soc/amd/cezanne device domain 0 on - + device ref gpp_bridge_1 off end # no SD + device ref gpp_bridge_2 off end # no WWAN + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5619"" + device generic 0.0 on end + end + end # Audio + end end # domain + + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "15000" + register "thermctl_limit_degreeC" = "100" + + #Update values based on final stardust SDLE test report. + register "telemetry_vddcrvddfull_scale_current_mA" = "95359" #mA + register "telemetry_vddcrvddoffset" = "449" + register "telemetry_vddcrsocfull_scale_current_mA" = "31481" #mA + register "telemetry_vddcrsocoffset" = "193" + + #USB 2/3 phy config + register "usb_phy" = "{ + /* Left USB C0 Port */ + .Usb2PhyPort[0] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Left USB A0 Port */ + .Usb2PhyPort[1] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Right USB C1 Port */ + .Usb2PhyPort[4] = { + .compdstune = 3, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 3, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 6, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Left USB C0 Port */ + .Usb3PhyPort[0] = { + .tx_term_ctrl=3, + .rx_term_ctrl=3, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + /* Left USB A0 Port */ + .Usb3PhyPort[1] = { + .tx_term_ctrl=3, + .rx_term_ctrl=3, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + }" + + # general purpose PCIe clock output configuration + register "gpp_clk_config[1]" = "GPP_CLK_OFF" + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + + # I2C Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Speaker, Codec, P-SAR | + #| I2C3 | H1/D2 TPM | + #+-------------------+---------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "generic.wake" = "GEVENT_22" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C0 + device ref i2c_1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6918"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_89)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_121)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_120)" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_68)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C1 + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "0" + device i2c 29 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "1" + device i2c 2a on end + end + end # I2C2 end # chip soc/amd/cezanne diff --git a/src/mainboard/google/guybrush/variants/dewatt/variant.c b/src/mainboard/google/guybrush/variants/dewatt/variant.c new file mode 100644 index 0000000000..a985b05947 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/dewatt/variant.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +{ + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; +} diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 4634c5a00e..cea1f42cca 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -5,12 +5,9 @@ #include #include #include -#include /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { - /* Unused TP183 */ - PAD_NC(GPIO_31), /* EN_SPKR */ PAD_GPO(GPIO_69, HIGH), /* SD_AUX_RESET_L */ @@ -24,61 +21,45 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { /* Unused */ PAD_NC(GPIO_85), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_32, LOW), }; /* This table is used by guybrush variant with board version >= 2. */ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { /* EN_PP5000_PEN */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_32, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_31, HIGH), + /* Unused TP27 */ + PAD_NC(GPIO_70), }; static const struct soc_amd_gpio override_early_gpio_table[] = { - PAD_NC(GPIO_5), - /* BID >= 2: SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), + /* BID>=2: EN_SPKR to select RAM_ID input, BID < 2: Unused in later stages */ + PAD_GPO(GPIO_31, LOW), /* BID == 1: SD_AUX_RESET_L */ PAD_GPO(GPIO_70, LOW), - /* GSC_SOC_INT_L */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - /* Unused */ - PAD_NC(GPIO_85), }; /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { - PAD_NC(GPIO_5), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_70, HIGH), }; -/* This table is used by guybrush variant with board version < 2. */ -static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { - PAD_NC(GPIO_5), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), -}; - -static const struct soc_amd_gpio fpmcu_shutdown_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), -}; - -static const struct soc_amd_gpio fpmcu_disable_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_32), +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -115,18 +96,11 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) return bid1_pcie_gpio_table; } - *size = ARRAY_SIZE(bid2_pcie_gpio_table); - return bid2_pcie_gpio_table; + return NULL; } -const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) { - *size = ARRAY_SIZE(fpmcu_shutdown_gpio_table); - return fpmcu_shutdown_gpio_table; -} - -const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(fpmcu_disable_gpio_table); - return fpmcu_disable_gpio_table; + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; } diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc index 5af83adff1..2b86d005c4 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/Makefile.inc @@ -5,6 +5,6 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt index 02c1bf30a1..ed9ee86c11 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/dram_id.generated.txt @@ -9,3 +9,12 @@ MT53E512M32D2NP-046 WT:F 1 (0001) NT6AP256T32AV-J1 2 (0010) H9HCNNNBKMMLXR-NEE 1 (0001) MT53E1G32D2NP-046 WT:B 3 (0011) +MT53E512M32D2NP-046 WT:E 1 (0001) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNCPMMLXR-NEE 3 (0011) +K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt index b267e539f1..298e58b569 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/guybrush/memory/mem_parts_used.txt @@ -3,3 +3,12 @@ MT53E512M32D2NP-046 WT:F NT6AP256T32AV-J1 H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:B +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 92b19802d8..934fdbfcd5 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -103,6 +103,7 @@ chip soc/amd/cezanne register "generic.stop_delay_ms" = "170" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end @@ -172,6 +173,10 @@ chip soc/amd/cezanne register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" register "wake" = "GEVENT_5" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "3" device generic 0 alias fpmcu on probe FP FP_PRESENT end diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c index ded1351674..974e357cd9 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/variant.c +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include +#include bool variant_has_pcie_wwan(void) { @@ -11,5 +13,11 @@ bool variant_has_pcie_wwan(void) uint8_t variant_sd_aux_reset_gpio(void) { - return GPIO_69; + return board_id() == 1 ? GPIO_70 : GPIO_69; +} + +void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) +{ + if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2) + ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 6a12ad3a70..0b3b9b265e 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -5,7 +5,6 @@ #include #include #include -#include /* This table is used by nipperkin variant with board version < 2. */ static const struct soc_amd_gpio bid1_override_gpio_table[] = { @@ -16,14 +15,16 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_NC(GPIO_18), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_5, HIGH), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + PAD_GPO(GPIO_32, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_31, HIGH), + /* Unused TP27 */ + PAD_NC(GPIO_70), }; /* This table is used by nipperkin variant with board version >= 2. */ @@ -34,62 +35,39 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = { PAD_NC(GPIO_17), /* LCD_PRIVACY_PCH */ PAD_GPO(GPIO_18, HIGH), - /* Unused */ - PAD_NC(GPIO_69), + /* SOC_SC_PWRSV */ + PAD_GPO(GPIO_31, HIGH), }; static const struct soc_amd_gpio override_early_gpio_table[] = { - /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ + PAD_NC(GPIO_18), + /* BID==1: EN_SPKR to select RAM_ID input, BID >= 1: Unused in later stages */ + PAD_GPO(GPIO_31, LOW), +}; + +static const struct soc_amd_gpio override_pcie_gpio_table[] = { + PAD_NC(GPIO_18), +}; + + +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), - PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, LOW), -}; - -/* This table is used by nipperkin variant with board version < 2. */ -static const struct soc_amd_gpio bid1_override_pcie_gpio_table[] = { - PAD_NC(GPIO_5), - PAD_NC(GPIO_18), - /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_69, HIGH), }; /* This table is used by nipperkin variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = { - PAD_NC(GPIO_18), - PAD_NC(GPIO_69), -}; - -/* This table is used by nipperkin variant with board version < 2. */ -static const struct soc_amd_gpio bid1_fpmcu_shutdown_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), -}; - -/* This table is used by nipperkin variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_fpmcu_shutdown_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_3, LOW), -}; - -/* This table is used by nipperkin variant with board version < 2. */ -static const struct soc_amd_gpio bid1_fpmcu_disable_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_32), -}; - -/* This table is used by nipperkin variant with board version >= 2. */ -static const struct soc_amd_gpio bid2_fpmcu_disable_gpio_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_3), +static const struct soc_amd_gpio bid2_tpm_gpio_table[] = { + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_85, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -113,39 +91,19 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) { - uint32_t board_version = board_id(); - - if (board_version < 2) { - *size = ARRAY_SIZE(bid1_override_pcie_gpio_table); - return bid1_override_pcie_gpio_table; - } - - *size = ARRAY_SIZE(bid2_override_pcie_gpio_table); - return bid2_override_pcie_gpio_table; + *size = ARRAY_SIZE(override_pcie_gpio_table); + return override_pcie_gpio_table; } -const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) { uint32_t board_version = board_id(); if (board_version < 2) { - *size = ARRAY_SIZE(bid1_fpmcu_shutdown_gpio_table); - return bid1_fpmcu_shutdown_gpio_table; + *size = ARRAY_SIZE(bid1_tpm_gpio_table); + return bid1_tpm_gpio_table; } - *size = ARRAY_SIZE(bid2_fpmcu_shutdown_gpio_table); - return bid2_fpmcu_shutdown_gpio_table; -} - -const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) -{ - uint32_t board_version = board_id(); - - if (board_version < 2) { - *size = ARRAY_SIZE(bid1_fpmcu_disable_gpio_table); - return bid1_fpmcu_disable_gpio_table; - } - - *size = ARRAY_SIZE(bid2_fpmcu_disable_gpio_table); - return bid2_fpmcu_disable_gpio_table; + *size = ARRAY_SIZE(bid2_tpm_gpio_table); + return bid2_tpm_gpio_table; } diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc index b2a552c04c..9becda6ba8 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/Makefile.inc @@ -5,6 +5,6 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt index af5e9806f7..f85255dec2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/dram_id.generated.txt @@ -13,3 +13,8 @@ MT53E512M32D2NP-046 WT:E 1 (0001) K4U6E3S4AA-MGCR 1 (0001) H9HCNNNCPMMLXR-NEE 3 (0011) K4UBE3D4AA-MGCR 3 (0011) +K4U6E3S4AB-MGCL 1 (0001) +H54G46CYRBX267 1 (0001) +MT53E512M32D1NP-046 WT:B 1 (0001) +H54G56CYRBX247 3 (0011) +K4UBE3D4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt index eb702a6274..298e58b569 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/nipperkin/memory/mem_parts_used.txt @@ -7,3 +7,8 @@ MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B +H54G56CYRBX247 +K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 48b04fb673..b49c8a6ed7 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -27,6 +27,139 @@ fw_config end chip soc/amd/cezanne + + register "usb_phy_custom" = "1" + register "usb_phy" = "{ + /* Left USB C0 Port */ + .Usb2PhyPort[0] = { + .compdstune = 5, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 9, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Left USB A0 Port or WWAN */ + .Usb2PhyPort[1] = { + .compdstune = 5, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 9, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* User facing camera */ + .Usb2PhyPort[2] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + /* World facing camera */ + .Usb2PhyPort[3] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + /* Right USB C1 Port */ + .Usb2PhyPort[4] = { + .compdstune = 6, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 0xe, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* Right USB A1 Port */ + .Usb2PhyPort[5] = { + .compdstune = 5, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 1, + .txpreemppulsetune = 0, + .txrisetune = 1, + .txvreftune = 9, + .txhsxvtune = 3, + .txrestune = 1, + }, + /* WiFi / Bluetooth */ + .Usb2PhyPort[6] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + /* Smart Card */ + .Usb2PhyPort[7] = { + .compdstune = 1, + .sqrxtune = 3, + .txfslstune = 3, + .txpreempamptune = 2, + .txpreemppulsetune = 0, + .txrisetune = 2, + .txvreftune = 3, + .txhsxvtune = 3, + .txrestune = 2, + }, + /* Left USB C0 Port */ + .Usb3PhyPort[0] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + /* Left USB A0 Port or WWAN */ + .Usb3PhyPort[1] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + /* Right USB C1 Port */ + .Usb3PhyPort[2] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + /* Right USB A1 Port */ + .Usb3PhyPort[3] = { + .tx_term_ctrl=2, + .rx_term_ctrl=2, + .tx_vboost_lvl_en=1, + .tx_vboost_lvl=5, + }, + .ComboPhyStaticConfig[0] = 0, + .ComboPhyStaticConfig[1] = 0, + .BatteryChargerEnable = 0, + .PhyP3CpmP4Support = 0, + }" + device domain 0 on device ref gpp_bridge_2 on # Required so the NVMe gets placed into D3 when entering S0i3. @@ -45,6 +178,19 @@ chip soc/amd/cezanne probe STORAGE STORAGE_SSD end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on + chip drivers/gfx/generic + register "device_count" = "1" + register "device[0].name" = ""LCD"" + # Use Chrome OS privacy screen _HID + register "device[0].hid" = ""GOOG0010"" + # Internal panel on the first port of the graphics chip + register "device[0].addr" = "0x80010400" + register "device[0].privacy.enabled" = "1" + register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_5)" + device generic 0.0 on end + end + end device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""10029836"" @@ -61,10 +207,10 @@ chip soc/amd/cezanne register "sustained_power_limit_mW" = "15000" register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcrvddfull_scale_current_mA" = "73457" #mA - register "telemetry_vddcrvddoffset" = "291" - register "telemetry_vddcrsocfull_scale_current_mA" = "30761" #mA - register "telemetry_vddcrsocoffset" = "834" + register "telemetry_vddcrvddfull_scale_current_mA" = "73331" #mA + register "telemetry_vddcrvddoffset" = "1893" + register "telemetry_vddcrsocfull_scale_current_mA" = "31955" #mA + register "telemetry_vddcrsocoffset" = "852" # I2C Config #+-------------------+---------------------------+ @@ -92,6 +238,19 @@ chip soc/amd/cezanne .early_init = true, }" + register "edp_phy_override" = "1" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2, bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .tx_eq_main = 0x1f, + .tx_eq_pre = 0x0, + .tx_eq_post = 0x0, + .tx_vboost_lvl = 0x5, + }" + device ref i2c_0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -154,6 +313,10 @@ chip soc/amd/cezanne register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" register "wake" = "GEVENT_5" register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_11)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_3)" + register "enable_delay_ms" = "3" device generic 0 alias fpmcu on probe FP FP_PRESENT end @@ -162,11 +325,9 @@ chip soc/amd/cezanne chip drivers/generic/max98357a register "hid" = ""MX98360A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_31)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_70)" register "sdmode_delay" = "5" device generic 0.1 on end end - register "common_config.espi_config.alert_pin" = "ESPI_ALERT_PIN_IN_BAND" - end # chip soc/amd/cezanne diff --git a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c index 10428050f0..c2f4fbffcd 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/ramstage.c @@ -4,18 +4,36 @@ #include #include #include +#include #include -void variant_devtree_update(void) +static void cr50_devtree_update(void) { - uint32_t board_ver = board_id(); const struct device *cr50_dev = DEV_PTR(cr50); struct drivers_i2c_tpm_config *cfg; struct acpi_gpio cr50_irq_gpio = ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3); - if (board_ver > 1) - return; - cfg = config_of(cr50_dev); cfg->irq_gpio = cr50_irq_gpio; } + +static void fpmcu_devtree_update(void) +{ + const struct device *fpmcu_dev = DEV_PTR(fpmcu); + struct drivers_uart_acpi_config *cfg; + struct acpi_gpio fpmcu_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32); + + cfg = config_of(fpmcu_dev); + cfg->enable_gpio = fpmcu_enable_gpio; +} + +void variant_devtree_update(void) +{ + uint32_t board_ver = board_id(); + + if (board_ver > 1) + return; + + cr50_devtree_update(); + fpmcu_devtree_update(); +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 917857c3ac..204ec61b55 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -7,13 +7,13 @@ void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) { - dxio_descriptors[WLAN].link_aspm_L1_1 = false; - dxio_descriptors[WLAN].link_aspm_L1_2 = false; -} + uint32_t board_version = board_id(); -uint8_t variant_sd_aux_reset_gpio(void) -{ - uint32_t board_ver = board_id(); - - return (board_ver < 2) ? GPIO_69 : GPIO_5; + if (board_version >= 3) { + dxio_descriptors[WLAN].link_aspm_L1_1 = true; + dxio_descriptors[WLAN].link_aspm_L1_2 = true; + } else { + dxio_descriptors[WLAN].link_aspm_L1_1 = false; + dxio_descriptors[WLAN].link_aspm_L1_2 = false; + } } diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index e6434dfda2..35bfa0a1da 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -4,41 +4,57 @@ #include #include #include +#include #include #include -static void setup_gpio(void) +void verstage_mainboard_early_init(void) { const struct soc_amd_gpio *gpios, *override_gpios; size_t num_gpios, override_num_gpios; - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - override_gpios = variant_early_override_gpio_table(&override_num_gpios); + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; - gpio_configure_pads_with_override(gpios, num_gpios, - override_gpios, override_num_gpios); - } + gpios = variant_early_gpio_table(&num_gpios); + override_gpios = variant_early_override_gpio_table(&override_num_gpios); + gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); } -void verstage_mainboard_early_init(void) +void verstage_mainboard_espi_init(void) { - setup_gpio(); + const struct soc_amd_gpio *gpios; + size_t num_gpios; + uint32_t dword; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); /* - * TODO : Make common function in cezanne code and just call it - * when PCI access is fixed in the PSP (b/186602472). - * For now the PSP doesn't configure LPC so it should be fine. - */ - if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - uint32_t dword; - printk(BIOS_DEBUG, "Verstage configure eSPI\n"); - dword = pm_io_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_io_write32(PM_SPI_PAD_PU_PD, dword); + * TODO : Make common function in cezanne code and just call it + * when PCI access is fixed in the PSP (b/186602472). + * For now the PSP doesn't configure LPC so it should be fine. + */ + dword = pm_io_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_io_write32(PM_SPI_PAD_PU_PD, dword); - dword = pm_io_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_io_write32(PM_ACPI_CONF, dword); - } + dword = pm_io_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_io_write32(PM_ACPI_CONF, dword); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); } diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index de68d855ef..2ddc403681 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -1,20 +1,3 @@ - -config BOARD_GOOGLE_BASEBOARD_HATCH - def_bool n - select BOARD_GOOGLE_HATCH_COMMON - select SYSTEM_TYPE_LAPTOP - -config BOARD_GOOGLE_BASEBOARD_PUFF - def_bool n - select BOARD_GOOGLE_HATCH_COMMON - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE - select RT8168_GEN_ACPI_POWER_RESOURCE - select ROMSTAGE_SPD_SMBUS - select SPD_READ_BY_WORD - select SOC_INTEL_CSE_LITE_SKU - select DRIVERS_INTEL_DPTF - config BOARD_GOOGLE_HATCH_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 @@ -28,9 +11,9 @@ config BOARD_GOOGLE_HATCH_COMMON select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL + select EC_GOOGLE_CHROMEEC_SKUID select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -42,8 +25,137 @@ config BOARD_GOOGLE_HATCH_COMMON select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT +config BOARD_GOOGLE_BASEBOARD_HATCH + def_bool n + select BOARD_GOOGLE_HATCH_COMMON + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_BASEBOARD_PUFF + def_bool n + select BOARD_GOOGLE_HATCH_COMMON + select DRIVERS_INTEL_DPTF + select ROMSTAGE_SPD_SMBUS + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_CSE_LITE_SKU + select SPD_READ_BY_WORD + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + +config BOARD_GOOGLE_AKEMI + select BOARD_GOOGLE_BASEBOARD_HATCH + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_AMBASSADOR + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_DRATINI + select BOARD_GOOGLE_BASEBOARD_HATCH + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_DUFFY_LEGACY + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_DUFFY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_FAFFY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_GENESIS + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_HELIOS + select BOARD_GOOGLE_BASEBOARD_HATCH + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_I2C_RT1011 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_HELIOS_DISKSWAP + select BOARD_GOOGLE_BASEBOARD_HATCH + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_I2C_RT1011 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_JINLON + select BOARD_GOOGLE_BASEBOARD_HATCH + select DRIVERS_GFX_GENERIC + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_KAISA_LEGACY + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_KAISA + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_KINDRED + select BOARD_GOOGLE_BASEBOARD_HATCH + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_MMC_OVERRIDE + +config BOARD_GOOGLE_KOHAKU + select BOARD_GOOGLE_BASEBOARD_HATCH + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_MOONBUGGY + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_MUSHU + select BOARD_GOOGLE_BASEBOARD_HATCH + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_NIGHTFURY + select BOARD_GOOGLE_BASEBOARD_HATCH + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_I2C_MAX98390 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_NOIBAT + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_PALKIA + select BOARD_GOOGLE_BASEBOARD_HATCH + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_SCOUT + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_WYVERN + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + if BOARD_GOOGLE_HATCH_COMMON +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config DISABLE_HECI1_AT_PRE_BOOT + default y if BOARD_GOOGLE_BASEBOARD_HATCH + config CHROMEOS select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -127,7 +239,6 @@ config MAINBOARD_PART_NUMBER default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF - default "Stryke" if BOARD_GOOGLE_STRYKE default "Wyvern" if BOARD_GOOGLE_WYVERN default "Dooly" if BOARD_GOOGLE_DOOLY default "Ambassador" if BOARD_GOOGLE_AMBASSADOR @@ -162,7 +273,6 @@ config VARIANT_DIR default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF - default "stryke" if BOARD_GOOGLE_STRYKE default "wyvern" if BOARD_GOOGLE_WYVERN default "dooly" if BOARD_GOOGLE_DOOLY default "ambassador" if BOARD_GOOGLE_AMBASSADOR diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e92f584662..1307314e9a 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -1,115 +1,73 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI - bool "-> Akemi" - select BOARD_GOOGLE_BASEBOARD_HATCH - -config BOARD_GOOGLE_DRATINI - bool "-> Dratini" - select BOARD_GOOGLE_BASEBOARD_HATCH - -config BOARD_GOOGLE_DUFFY_LEGACY - bool "-> Duffy Legacy (32MB)" - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - -config BOARD_GOOGLE_DUFFY - bool "-> Duffy" - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_FAFFY - bool "-> Faffy" - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_HATCH - bool "-> Hatch" - select BOARD_GOOGLE_BASEBOARD_HATCH - select BOARD_ROMSIZE_KB_32768 - -config BOARD_GOOGLE_JINLON - bool "-> Jinlon" - select BOARD_GOOGLE_BASEBOARD_HATCH - select DRIVERS_GFX_GENERIC - -config BOARD_GOOGLE_KAISA_LEGACY - bool "-> Kaisa Legacy (32MB)" - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - -config BOARD_GOOGLE_KAISA - bool "-> Kaisa" - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_KOHAKU - bool "-> Kohaku" - select BOARD_GOOGLE_BASEBOARD_HATCH - -config BOARD_GOOGLE_KINDRED - bool "-> Kindred" - select BOARD_GOOGLE_BASEBOARD_HATCH - select SOC_INTEL_COMMON_MMC_OVERRIDE - -config BOARD_GOOGLE_HELIOS - bool "-> Helios" - select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS - select DRIVERS_I2C_RT1011 - -config BOARD_GOOGLE_MUSHU - bool "-> Mushu" - select BOARD_GOOGLE_BASEBOARD_HATCH - -config BOARD_GOOGLE_PALKIA - bool "-> Palkia" - select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS - select DRIVERS_I2C_RT1011 - -config BOARD_GOOGLE_NIGHTFURY - bool "-> Nightfury" - select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS - select DRIVERS_I2C_MAX98390 - -config BOARD_GOOGLE_NOIBAT - bool "-> Noibat" - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_PUFF - bool "-> Puff" - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - -config BOARD_GOOGLE_HELIOS_DISKSWAP - bool "-> Helios_Diskswap" - select BOARD_GOOGLE_BASEBOARD_HATCH - select CHROMEOS_DSM_CALIB if CHROMEOS - select DRIVERS_I2C_RT1011 - -config BOARD_GOOGLE_STRYKE - bool "-> Stryke" - select BOARD_GOOGLE_BASEBOARD_HATCH - -config BOARD_GOOGLE_WYVERN - bool "-> Wyvern" - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_DOOLY - bool "-> Dooly" - select BOARD_GOOGLE_BASEBOARD_PUFF + bool "-> Akemi (IdeaPad Flex 5/5i Chromebook)" config BOARD_GOOGLE_AMBASSADOR bool "-> Ambassador" - select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + bool "-> Dooly" + +config BOARD_GOOGLE_DRATINI + bool "-> Dratini (HP Pro c640 Chromebook)" + +config BOARD_GOOGLE_DUFFY_LEGACY + bool "-> Duffy Legacy (32MB)" + +config BOARD_GOOGLE_DUFFY + bool "-> Duffy (ASUS Chromebox 4)" + +config BOARD_GOOGLE_FAFFY + bool "-> Faffy (ASUS Fanless Chromebox)" config BOARD_GOOGLE_GENESIS bool "-> Genesis" - select BOARD_GOOGLE_BASEBOARD_PUFF -config BOARD_GOOGLE_SCOUT - bool "-> Scout" - select BOARD_GOOGLE_BASEBOARD_PUFF +config BOARD_GOOGLE_HATCH + bool "-> Hatch" + +config BOARD_GOOGLE_HELIOS + bool "-> Helios (ASUS Chromebook Flip C436FA)" + +config BOARD_GOOGLE_HELIOS_DISKSWAP + bool "-> Helios_Diskswap" + +config BOARD_GOOGLE_JINLON + bool "-> Jinlon (HP Elite c1030 Chromebook)" + +config BOARD_GOOGLE_KAISA_LEGACY + bool "-> Kaisa Legacy (32MB)" + +config BOARD_GOOGLE_KAISA + bool "-> Kaisa (Acer Chromebox CXI4)" + +config BOARD_GOOGLE_KINDRED + bool "-> Kindred (Acer Chromebook 712)" + +config BOARD_GOOGLE_KOHAKU + bool "-> Kohaku (Samsung Galaxy Chromebook)" config BOARD_GOOGLE_MOONBUGGY bool "-> Moonbuggy" - select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_MUSHU + bool "-> Mushu" + +config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury (Samsung Galaxy Chromebook 2)" + +config BOARD_GOOGLE_NOIBAT + bool "-> Noibat (HP Chromebox G3)" + +config BOARD_GOOGLE_PALKIA + bool "-> Palkia" + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + +config BOARD_GOOGLE_SCOUT + bool "-> Scout" + +config BOARD_GOOGLE_WYVERN + bool "-> Wyvern (CTL Chromebox CBx2)" diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index ee54ade334..bbca895340 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include #include #include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -34,3 +35,9 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index 93864b2ad1..ff466a34a8 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -1,12 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include #include #include -#include void mainboard_silicon_init_params(FSPS_UPD *supd) { @@ -36,7 +34,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; variant_mainboard_enable(dev); } diff --git a/src/mainboard/google/hatch/variants/akemi/data.vbt b/src/mainboard/google/hatch/variants/akemi/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a972fa230a70fdfa12ba3f710f28865c4de4798f GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>I0f!#vOY=ISPiL>1;cIm=yyQL}7qzmi<4GXRP z(PA)NlSX+^vJYy|p!9{PyogW6H+(T9CQ4$WPex2kP<)Zdg9cA5bEWKu1AuG#|p(zPncj+xP55PV6m`1Q5ZcqHZ+WxcoJiK_ZEtUk=}Xs@@ujwr+Y{VTq1-dV40B ziuESbJ22gYiDWjG&30^WPwm1?Pr5VNp6u;NC~P*2_|Wi?k-_~3#xN8QV+(zwiGy;N zF+Mah+>Ehe5qr!wqu5gzEsQ)@$Tus@1UUzu8Ua9XLahM;{Lup7nfKHHSdRff4-vg3 zi=}ge3XUy;gKTR&;0kb)T@bv;RReI=j@13L1E8uN&1)Im^m)<*Pz5vgHF4dWY$f>zck~fdtHbW$@LfLt7b%8 z2qppe1Raih8z3!);Hc<;m&MJ{SaTk9FGAL48BA6tg?Npm{PpEQ=T13@*5@3didHo0>Uh>LNdDTxo&X$AVRVP(B!e+Z%ypo$$4{RK|;s zsGi&kt8c@dSss0c)~v%r2ZsSjstlbFf&e676)b@qWO#n%u`lX*ZdPYPgj#;J&+EBB z4K)z>=mI0a86wLVejUX93}0i~DaJlv_$AZ6XY6N&eo0#?u_g(#l2(w|kc4kY+ItfF zNWyOt(Dm(8K0K5Lo$0_#&=}xLz#Ud<9D)lMP}DzT&`#v6t+ddy^1!j zut^0^E852j`&7Y8iuSw0L?4EI+7mw3;lqPI?L{AZ#iulC&XVJzQ1bhDe&QLC>3r&U z$Xs3(RFclxHFOi+JTcKp!8!tD6#E^EBTUyKMEaLusIgbC~ps)jlb zK`1+K1L6Jk6BoOKtBw8>b3O=V7e_E$XRGj`^GQSBbGF4W&dnjXtSm|Hb5=8w`4pY_3o!O+p33!2TEGS6b=lDnEHLT#n#;j=3Vq0x*T zfDoKzp3BJ7&Z#Qa!`tEM3*A#I^vqjJXAwl;DYR_3szJ~jjq|ywydLPbaz@h!k(MLT zovulapjZe_tRjlbL72|qQeD>Lb5WFOKavk6_h!Bx%te0dRqbdk1)km9Wb`-9&4mcH zmJjsrXYqXzHXv7mx}2)|=X{`p)bt^>H8YUeeYjBEvHMWre^9Xk{JV1POW@jep7QuJ zcKM??r_Z #include #include #include @@ -162,6 +161,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 00649c221e..cc38362f62 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -29,7 +29,6 @@ void variant_devtree_update(void) return; ssd_host->enabled = 0; cfg->SataSalpSupport = 0; - cfg->SataMode = 0; cfg->SataPortsEnable[1] = 0; cfg->SataPortsDevSlp[1] = 0; cfg->satapwroptimize = 0; diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/hatch/variants/ambassador/gpio.c index 5a911fc4f9..996edc4fc7 100644 --- a/src/mainboard/google/hatch/variants/ambassador/gpio.c +++ b/src/mainboard/google/hatch/variants/ambassador/gpio.c @@ -100,6 +100,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a84eabde5c..976d82970c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -296,7 +296,7 @@ chip soc/intel/cannonlake device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index d7684865f7..f9ffcd96ec 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -3,7 +3,8 @@ #include #include #include -#include +#include +#include static const struct pad_config gpio_table[] = { /* A0 : GPP_A0 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index d641405daa..c6c87dc647 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/dooly/data.vbt b/src/mainboard/google/hatch/variants/dooly/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..42fc269659a4bf91307882788a20c7f85f37aa6c GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>I0f!#vOY=ISPiL>1;cIm=yyQL}7qzmi<4GXRP z(PA)NlSX+^vJYs`p!9{PyogW6H+(T9CQ4$WPex2kP*esj+KJ-e!}y%)1xyHc^P4zwu`I-K!erSf)aPo}d2iCAxJpgon2cj1rl2#on} zT>;1oLcJW(^+@vYSfLo|2@`Azw-4O1%;S#nLwgD%tw=yRwZ_QC<_#MWBkNn}(IcBk)mtOc)=f_;EYT59Z_gxC zvEF2Q2c~;4k<7-j*^ce)sa=@qNp~jOlf4}Yh0TT$9~wR~GPwW17>43uY@u&7aZv6u z#)n3Rn=w`_VvpHo6nhGzg^?Eu`DTTgAm_nTBLE0as5L-<-&+7Y^PU<2>oEZ6A)>cr zv2<=w!LdbfkZp|zTmf#f3xXH9Y5>mKk-C3=094hZc`c)xK2Mqes(_}#Ye=84nys>% z(T5$p0}99$vn|q(h|r>TGZNNEbpb7fH&d-<&}lc5%(_YVr)J!AzYCEfx%m=()r^P> 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DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index b468168056..8533f024ea 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field AUDIO_CODEC_SOURCE 8 10 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end + chip soc/intel/cannonlake register "power_limits_config" = "{ @@ -346,7 +354,23 @@ chip soc/intel/cannonlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end end chip drivers/generic/gpio_keys register "name" = ""MUTE"" diff --git a/src/mainboard/google/hatch/variants/dratini/data.vbt b/src/mainboard/google/hatch/variants/dratini/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a8a028ca64a60fc40243adc4ed70f641620f4e4e GIT binary patch literal 4608 zcmeHKUu;ul6hF7Of4_Tg*WMB7D$c{7Ks(sD9Z+$Oc)NDEvO>FcEF+q%KnpAsHupz| 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struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/helios/data.vbt b/src/mainboard/google/hatch/variants/helios/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a972fa230a70fdfa12ba3f710f28865c4de4798f GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>I0f!#vOY=ISPiL>1;cIm=yyQL}7qzmi<4GXRP z(PA)NlSX+^vJYy|p!9{PyogW6H+(T9CQ4$WPex2kP<)Zdg9cA5bEWKu1AuG#|p(zPncj+xP55PV6m`1Q5ZcqHZ+WxcoJiK_ZEtUk=}Xs@@ujwr+Y{VTq1-dV40B ziuESbJ22gYiDWjG&30^WPwm1?Pr5VNp6u;NC~P*2_|Wi?k-_~3#xN8QV+(zwiGy;N zF+Mah+>Ehe5qr!wqu5gzEsQ)@$Tus@1UUzu8Ua9XLahM;{Lup7nfKHHSdRff4-vg3 zi=}ge3XUy;gKTR&;0kb)T@bv;RReI=j@13L1E8uN&1)Im^m)<*Pz5vgHF4dWY$f>zck~fdtHbW$@LfLt7b%8 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zut^0^E852j`&7Y8iuSw0L?4EI+7mw3;lqPI?L{AZ#iulC&XVJzQ1bhDe&QLC>3r&U z$Xs3(RFclxHFOi+JTcKp!8!tD6#E^EBTUyKMEaLusIgbC~ps)jlb zK`1+K1L6Jk6BoOKtBw8>b3O=V7e_E$XRGj`^GQSBbGF4W&dnjXtSm|Hb5=8w`4pY_3o!O+p33!2TEGS6b=lDnEHLT#n#;j=3Vq0x*T zfDoKzp3BJ7&Z#Qa!`tEM3*A#I^vqjJXAwl;DYR_3szJ~jjq|ywydLPbaz@h!k(MLT zovulapjZe_tRjlbL72|qQeD>Lb5WFOKavk6_h!Bx%te0dRqbdk1)km9Wb`-9&4mcH zmJjsrXYqXzHXv7mx}2)|=X{`p)bt^>H8YUeeYjBEvHMWre^9Xk{JV1POW@jep7QuJ zcKM??r_Z #include #include #include @@ -220,6 +219,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/kindred/kled-data.vbt b/src/mainboard/google/hatch/variants/kindred/kled-data.vbt new file mode 100644 index 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z0fJC+-T}e~8zwJx2iF+=C+B?-N-mCIxXxAJL&wvGzUN%CVVs{wa9Np>+~=%hB=@cC zJKGI)`nHli7v@No`29+*R5A`nn@Tf-!8$`ndoE};t4chRm5c65q6oDXXGYGgCWHnv zb^tWq zf7UL466f`W_J5$47m;HTt&hU%+sMfzW%oPj0?WaA;VmFXX8TcI%*nNgnsfn<&C!FQ XT9YyR=jFc3jpngs9ssnenabled = 0; cfg->SataSalpSupport = 0; - cfg->SataMode = 0; cfg->SataPortsEnable[1] = 0; cfg->SataPortsDevSlp[1] = 0; cfg->satapwroptimize = 0; diff --git a/src/mainboard/google/hatch/variants/kohaku/data.vbt b/src/mainboard/google/hatch/variants/kohaku/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..31fcd1e3d87b46417b5774c94e6840b5229a3ce4 GIT binary patch literal 4608 zcmeHKUu;ul6hHUg_21Wf+q=63x{CAgC(sTyZU;*;?WUkr(fl9=d=ModgV^g-fY3`jlq&)UkwRSg)3r}uo{ z`OZD}_nq_oJzX={HGt{fJ&8zfH(Hbh70%QzqjE8I#gpmbSY#kF+?7a1d+~c%29xzS zuL5K_u1O53YAAkmGM5kZ2MIQTJ4g48zW$LXK~lmk$t)G4kRFztTD8?ZPRAN(8hLp)X)|Z)s9fOW6L8Fi*-knJ5%vQ zWFVg0g~@)5#nX{=x_f6=Vh^VJlRfdS_&|3|V&yQRqhrU$M-CpE#6UEN?bJuB0cyC6 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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c index 759768b3c8..ba75fb768d 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c @@ -126,6 +126,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/mushu/data.vbt b/src/mainboard/google/hatch/variants/mushu/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..72ef31592a8080a66e9884bb408dde19db31dc3e GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>I0f!#vOY=ISPiL>1;cIm=yyQL}7qzmi<4GXRP z(PA)NlSX+^vJYy|p!9{PyogW6H+(T9CQ4$WPex2kP<)X{VhqT7=FarT66}Hj#c+1c zJ?Eae_nUL>@7Yy-?Y)@o+LelRb)Zdo(BZWIH!5$Y_GCIckcjoh2HI2Uco+Tv55buK z#$|xKAk@ndU5_LWj}?lco-o0taQo1n!D3;3qA+@JY-kuW@g&Cf?kyAxBfG~6dCc}b z6+;tKVeR9C#XRm9KeVSX(uxG6Q)`TDY~HXDF|xje9zC*&RJ}D4ZQb;^!V(?v^!7|L z73)o=cVM~)6Ul5Wo9)=%p4x?(o^)rjJ=xolP}po3@uA@(BZK=7jA1Aq#uoZU69?rk zV|-|2xEW)`BKDYVMzNGPxspbBUzyoU4%tJx~M z8GYEnJD`AEG20^jhzKoeHzQ$vR2R@vcr(>%2Ay^@$*h}%e`&@|_qq@%lIt(fSIvmH z5KIE_2|672Hb7bo!BNoxFN>R@vF1GJUWBYyg?+?Fh`(|&_?Gw*@fG50#7-B3TH<=* zmBdZNj}ga+yNGuZ4-gL$yT;*q#Zdy938IorPx6QO! zDF4kjLGxsISQan18C-B*6^_;YH#Kw2)J1;QxY7c%j|Hp#pnNa_w>JXII^kr$loq9cECgnT_1 zF<7k!jzukmKy*^H(kgNjYD|PSO0I4lh297!x3te2EzO6CoXmeR~!8&=6n#!E{%Sy__Y=d5NV_bu-` z(+v&!*0Mbp=17+L{YtJ>GY&_a%hS1FgQ2567c`qSWuC>#C3iJZgxX5e!)I3#LZcZw z03kTbJeQHDol{k;hquGi7rLib=$W^c&LW7wQ)t<6RfC{68s~FUc|Fi=<&35eA}vRv zJ6)3;L9q~=SVa_?vIn+p+Y zEg$IL&*J+cY(TCAbvae_&-p+Hsp&&%Yi1y``*5MSWA~xL|Da+8_;=;nm%z2{Jmv9c z?D9u(PM>f82YO`zITp~mD7?CroJ>-7zmqPoJggJm1af4iALYfITnngK7vR_|-5;to W88d%g?z!CHrHjlw0BD!pMfwwhiP#?i literal 0 HcmV?d00001 diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 582d68e6a2..fd56f33f89 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -64,6 +63,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc index c0a68a889d..a856f44082 100644 --- a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -11,3 +11,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += ramstage.c ramstage-y += variant.c + +$(call add_vbt_to_cbfs, vbt-nightfury-qled.bin, nightfury-qled-data.vbt) diff --git a/src/mainboard/google/hatch/variants/nightfury/data.vbt b/src/mainboard/google/hatch/variants/nightfury/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..31fcd1e3d87b46417b5774c94e6840b5229a3ce4 GIT binary patch literal 4608 zcmeHKUu;ul6hHUg_21Wf+q=63x{CAgC(sTyZU;*;?WUkr(fl9=d=ModgV^g-fY3`jlq&)UkwRSg)3r}uo{ z`OZD}_nq_oJzX={HGt{fJ&8zfH(Hbh70%QzqjE8I#gpmbSY#kF+?7a1d+~c%29xzS zuL5K_u1O53YAAkmGM5kZ2MIQTJ4g48zW$LXK~lmk$t)G4kRFztTD8?ZPRAN(8hLp)X)|Z)s9fOW6L8Fi*-knJ5%vQ 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early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/nightfury/nightfury-qled-data.vbt b/src/mainboard/google/hatch/variants/nightfury/nightfury-qled-data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..a972fa230a70fdfa12ba3f710f28865c4de4798f GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+Zdu2>I0f!#vOY=ISPiL>1;cIm=yyQL}7qzmi<4GXRP z(PA)NlSX+^vJYy|p!9{PyogW6H+(T9CQ4$WPex2kP<)Zdg9cA5bEWKu1AuG#|p(zPncj+xP55PV6m`1Q5ZcqHZ+WxcoJiK_ZEtUk=}Xs@@ujwr+Y{VTq1-dV40B ziuESbJ22gYiDWjG&30^WPwm1?Pr5VNp6u;NC~P*2_|Wi?k-_~3#xN8QV+(zwiGy;N zF+Mah+>Ehe5qr!wqu5gzEsQ)@$Tus@1UUzu8Ua9XLahM;{Lup7nfKHHSdRff4-vg3 zi=}ge3XUy;gKTR&;0kb)T@bv;RReI=j@13L1E8uN&1)Im^m)<*Pz5vgHF4dWY$f>zck~fdtHbW$@LfLt7b%8 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zckl;LK(3g+NIxP%3)^late5HnS_*elEjQ@4-6XSb65is*O%J*eDU%zo(p$}pxDZSN z@CiB`^EN_KY=R@A1KtofLvzh}(7gz0uL}E!4-k5cd%8BpxCjCU#B2jgq4PG!sMx!IpkYf?5N|f>1bV+fUkd?{75eM9h|wExECZ zrc`pf;b!UUdMK4VTg(UyLZGyTn2pqJ%LJFAn6mr*B+aoJwELx!H$z@_Se{xem6`mneEVW|r|>b^?@6DI!b(^H)A(O`cnn+-b>&;0jo&yF2EFV4?gs z?*z=9;c;2K;AU{aeN8x8_utgaF;f@$S>s9z%-$BP{-gHM2;AKWEbE4g-a-*CJ)wFs zE39W5@6Gb$3+8d}p^d`;BvpoPXo7l(!75k+8A$Q^%3~kY^TMpogb20#XrK4w0=21; zz{eLD0nQLv#^7-f_cMH(X{Q+bgyA<#`;oC<8Tut{rNmk!OiNl$Vj~j1BWWK=>@x|! zleAwX_Pc})vbI)cn`C@m)(*<-6&XK}wNGXCg^WMQ+EtldmvOnGZBW=21@|i2q{5~Z zJgsP-E9^@JFDu#~3KM-8^l8udSeFkE__Wu2>`kB2tT_vgOG3f#?eq zO;AZXYuC_8c>BbJrv+;ZkWn0TERHZ+ix3)IhE0Vf){r!Yr>#Sg=8Lxc#SyX%U_@ZG zUVk)fA=HPbMXRi$Frmgo=%C{2&ROWqaH1DRXHUT$m$SoU4k`S8B+yMx| zS>&~hJnNjPVm-VcoW0OHvqDe3x3r8P0xzLu!&MD}-fW!D%w+ZYUaMv_V-RUM65Z>X z%m;)cV5+w_Cozjn_G;*mdad+P;15D z0oUT+MbLmu0qQcU>aWB=8>tyXVryzBwfj&mzhn2o-2b3sCHQyk+SkFg?L5`-XYBT8 zv7*nn{{y|WfE){GT^QclN #include #include #include @@ -128,6 +127,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/puff/data.vbt b/src/mainboard/google/hatch/variants/puff/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..cda1c25d7d595d8e87bbfc4e731ff4b0fb6ae2a7 GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+YCSFDGhK)28`TVTan;%s+|UAnN_ZfQz1=>of8!$NC+ zv=~g+q){G}>;oD!D19L+FXEH&4c|yil*9y|jF_09_#%-P1G1jEGuh1)kht*}^EG`T$$ zPel6T$sL&N!&p2WNvFHEcP4gWsxR3c?~M0%#S~UfBRVpAcx-t8ixb!s4PqO;qlJU= zkTE(kHrk4jd>;EupKwL$_`rf)}~L04(1?!n~LPRrP3I%jl-plja0fKvUs8q}N$)t86zy zckl;LK(3g+NIxP%3)^late5HnS_*elEjQ@4-6XSb65is*O%J*eDU%zo(p$}pxDZSN z@CiB`^EN_KY=R@A1KtofLvzh}(7gz0uL}E!4-k5cd%8BpxCjCU#B2jgq4PG!sMx!IpkYf?5N|f>1bV+fUkd?{75eM9h|wExECZ zrc`pf;b!UUdMK4VTg(UyLZGyTn2pqJ%LJFAn6mr*B+aoJwELx!H$z@_Se{xem6`mneEVW|r|>b^?@6DI!b(^H)A(O`cnn+-b>&;0jo&yF2EFV4?gs z?*z=9;c;2K;AU{aeN8x8_utgaF;f@$S>s9z%-$BP{-gHM2;AKWEbE4g-a-*CJ)wFs zE39W5@6Gb$3+8d}p^d`;BvpoPXo7l(!75k+8A$Q^%3~kY^TMpogb20#XrK4w0=21; zz{eLD0nQLv#^7-f_cMH(X{Q+bgyA<#`;oC<8Tut{rNmk!OiNl$Vj~j1BWWK=>@x|! zleAwX_Pc})vbI)cn`C@m)(*<-6&XK}wNGXCg^WMQ+EtldmvOnGZBW=21@|i2q{5~Z zJgsP-E9^@JFDu#~3KM-8^l8udSeFkE__Wu2>`kB2tT_vgOG3f#?eq zO;AZXYuC_8c>BbJrv+;ZkWn0TERHZ+ix3)IhE0Vf){r!Yr>#Sg=8Lxc#SyX%U_@ZG zUVk)fA=HPbMXRi$Frmgo=%C{2&ROWqaH1DRXHUT$m$SoU4k`S8B+yMx| zS>&~hJnNjPVm-VcoW0OHvqDe3x3r8P0xzLu!&MD}-fW!D%w+ZYUaMv_V-RUM65Z>X z%m;)cV5+w_Cozjn_G;*mdad+P;15D z0oUT+MbLmu0qQcU>aWB=8>tyXVryzBwfj&mzhn2o-2b3sCHQyk+SkFg?L5`-XYBT8 zv7*nn{{y|WfE){GT^QclN -#include -#include -#include - -static const struct pad_config gpio_table[] = { - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C12 : NC */ - PAD_NC(GPP_C12, NONE), - /* C15 : WWAN_DPR_SAR_ODL - * - * TODO: Driver doesn't use this pin as of now. In case driver starts - * using this pin, expose this pin to driver. - */ - PAD_CFG_GPO(GPP_C15, 1, DEEP), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : NC */ - PAD_NC(GPP_F11, NONE), - /* F20 : NC */ - PAD_NC(GPP_F20, NONE), - /* F21 : NC */ - PAD_NC(GPP_F21, NONE), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - -const struct pad_config *override_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -/* - * GPIOs configured before ramstage - * Note: the Hatch platform's romstage will configure - * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins - * as inputs before it reads them, so they are not - * needed in this table. - */ -static const struct pad_config early_gpio_table[] = { - /* B15 : H1_SLAVE_SPI_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : H1_SLAVE_SPI_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : H1_SLAVE_SPI_MISO_R */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* C8 : UART_PCH_RX_DEBUG_TX */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), - /* C9 : UART_PCH_TX_DEBUG_RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), - /* C14 : BT_DISABLE_L */ - PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ - PAD_CFG_GPI(GPP_C20, NONE, DEEP), - /* C21 : H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), - /* C23 : WLAN_PE_RST# */ - PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), - /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, NONE, PLTRST), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h b/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h deleted file mode 100644 index ce6fbfe1a4..0000000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_EC_H -#define VARIANT_EC_H - -#include - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h b/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h deleted file mode 100644 index be96d95906..0000000000 --- a/src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - -#endif diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb deleted file mode 100644 index aa73ab6df3..0000000000 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ /dev/null @@ -1,218 +0,0 @@ -chip soc/intel/cannonlake - - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoPci, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 - register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| GSPI1 | | - #| I2C0 | Touchpad | - #| I2C1 | Touch screen | - #| I2C4 | Audio | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - - device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 2.3 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.4 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 2.5 off end - end - chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - # Unused - device usb 2.7 off end - end - chip drivers/usb/acpi - # Unused - device usb 2.8 off end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" - device usb 2.9 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""Right Type-C Port 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 3.2 on end - end - chip drivers/usb/acpi - # No Type-A Port 1 - device usb 3.3 off end - end - chip drivers/usb/acpi - # No WWAN - device usb 3.4 off end - end - chip drivers/usb/acpi - # Unused - device usb 3.5 off end - end - end - end - end # USB xHCI - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "wake" = "GPE0_DW0_21" - register "probed" = "1" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" - device i2c 49 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end - end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 19.0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Realtek RT5682"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" - register "property_count" = "1" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a on end - end - end #I2C #4 - device pci 1e.3 off end # GSPI #1 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HDA - end - -end diff --git a/src/mainboard/google/hatch/variants/wyvern/data.vbt b/src/mainboard/google/hatch/variants/wyvern/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..cda1c25d7d595d8e87bbfc4e731ff4b0fb6ae2a7 GIT binary patch literal 4608 zcmeHKU2GIp6h5=l{kt=>ot+YCSFDGhK)28`TVTan;%s+|UAnN_ZfQz1=>of8!$NC+ zv=~g+q){G}>;oD!D19L+FXEH&4c|yil*9y|jF_09_#%-P1G1jEGuh1)kht*}^EG`T$$ zPel6T$sL&N!&p2WNvFHEcP4gWsxR3c?~M0%#S~UfBRVpAcx-t8ixb!s4PqO;qlJU= zkTE(kHrk4jd>;EupKwL$_`rf)}~L04(1?!n~LPRrP3I%jl-plja0fKvUs8q}N$)t86zy zckl;LK(3g+NIxP%3)^late5HnS_*elEjQ@4-6XSb65is*O%J*eDU%zo(p$}pxDZSN z@CiB`^EN_KY=R@A1KtofLvzh}(7gz0uL}E!4-k5cd%8BpxCjCU#B2jgq4PG!sMx!IpkYf?5N|f>1bV+fUkd?{75eM9h|wExECZ zrc`pf;b!UUdMK4VTg(UyLZGyTn2pqJ%LJFAn6mr*B+aoJwELx!H$z@_Se{xem6`mneEVW|r|>b^?@6DI!b(^H)A(O`cnn+-b>&;0jo&yF2EFV4?gs z?*z=9;c;2K;AU{aeN8x8_utgaF;f@$S>s9z%-$BP{-gHM2;AKWEbE4g-a-*CJ)wFs zE39W5@6Gb$3+8d}p^d`;BvpoPXo7l(!75k+8A$Q^%3~kY^TMpogb20#XrK4w0=21; zz{eLD0nQLv#^7-f_cMH(X{Q+bgyA<#`;oC<8Tut{rNmk!OiNl$Vj~j1BWWK=>@x|! zleAwX_Pc})vbI)cn`C@m)(*<-6&XK}wNGXCg^WMQ+EtldmvOnGZBW=21@|i2q{5~Z zJgsP-E9^@JFDu#~3KM-8^l8udSeFkE__Wu2>`kB2tT_vgOG3f#?eq zO;AZXYuC_8c>BbJrv+;ZkWn0TERHZ+ix3)IhE0Vf){r!Yr>#Sg=8Lxc#SyX%U_@ZG zUVk)fA=HPbMXRi$Frmgo=%C{2&ROWqaH1DRXHUT$m$SoU4k`S8B+yMx| zS>&~hJnNjPVm-VcoW0OHvqDe3x3r8P0xzLu!&MD}-fW!D%w+ZYUaMv_V-RUM65Z>X z%m;)cV5+w_Cozjn_G;*mdad+P;15D z0oUT+MbLmu0qQcU>aWB=8>tyXVryzBwfj&mzhn2o-2b3sCHQyk+SkFg?L5`-XYBT8 zv7*nn{{y|WfE){GT^QclN Herobrine" select BOARD_GOOGLE_HEROBRINE_COMMON +config BOARD_GOOGLE_HEROBRINE_REV0 + bool "-> Herobrine_Rev0" + select BOARD_GOOGLE_HEROBRINE_COMMON + config BOARD_GOOGLE_SENOR bool "-> Senor" select BOARD_GOOGLE_HEROBRINE_COMMON @@ -18,6 +22,9 @@ config BOARD_GOOGLE_HOGLIN bool "-> Hoglin" select BOARD_GOOGLE_HEROBRINE_COMMON +config BOARD_GOOGLE_VILLAGER + bool "-> Villager" + select BOARD_GOOGLE_HEROBRINE_COMMON endif comment "(Herobrine requires 'Allow QC blobs repository')" diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h index 0e4a7607b8..d336bce0ad 100644 --- a/src/mainboard/google/herobrine/board.h +++ b/src/mainboard/google/herobrine/board.h @@ -7,17 +7,43 @@ #include #include + +#if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) +#define GPIO_EC_IN_RW GPIO(68) +#define GPIO_AP_EC_INT GPIO(142) +#define GPIO_H1_AP_INT GPIO(54) +#elif CONFIG(BOARD_GOOGLE_SENOR) +#define GPIO_EC_IN_RW dead_code_t(gpio_t) +#define GPIO_AP_EC_INT dead_code_t(gpio_t) +#define GPIO_H1_AP_INT dead_code_t(gpio_t) +#else +#define GPIO_EC_IN_RW GPIO(156) +#define GPIO_AP_EC_INT GPIO(18) +#define GPIO_H1_AP_INT GPIO(104) +#endif + #define GPIO_SD_CD_L GPIO(91) +#if CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) +#define USB_HUB_LDO_EN GPIO(24) +#else +/* For Herobrine board and all variants */ +#define USB_HUB_LDO_EN GPIO(157) +#endif + +#define GPIO_AMP_ENABLE GPIO(63) +#define GPIO_MI2S1_SCK GPIO(106) +#define GPIO_MI2S1_DATA0 GPIO(107) +#define GPIO_MI2S1_WS GPIO(108) + #define QCOM_SC7280_SKU1 0x0 #define QCOM_SC7280_SKU2 0x1 -#define QCOM_SC7280_SKU3 0x2 /* Fingerprint-specific GPIOs. Only for fingerprint-enabled devices. */ #if CONFIG(HEROBRINE_HAS_FINGERPRINT) -#define GPIO_FPMCU_BOOT0 GPIO(77) +#define GPIO_FPMCU_BOOT0 (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) ? GPIO(77) : GPIO(68)) #define GPIO_FP_RST_L GPIO(78) -#define GPIO_EN_FP_RAILS GPIO(42) +#define GPIO_EN_FP_RAILS (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0) ? GPIO(42) : GPIO(77)) #else #define GPIO_FPMCU_BOOT0 dead_code_t(gpio_t) #define GPIO_FP_RST_L dead_code_t(gpio_t) diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c index 7db3e0bc64..6449561e0e 100644 --- a/src/mainboard/google/herobrine/boardid.c +++ b/src/mainboard/google/herobrine/boardid.c @@ -10,19 +10,24 @@ uint32_t board_id(void) { static uint32_t id = UNDEFINED_STRAPPING_ID; - const gpio_t pins[] = {[2] = GPIO(50), [1] = GPIO(49), [0] = GPIO(48)}; + gpio_t pins[3] = { 0 }; + if (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)) { + pins[2] = GPIO(75); + pins[1] = GPIO(74); + pins[0] = GPIO(73); + } else { + pins[2] = GPIO(50); + pins[1] = GPIO(49); + pins[0] = GPIO(48); + } if (id == UNDEFINED_STRAPPING_ID) id = gpio_base3_value(pins, ARRAY_SIZE(pins)); - if ((id == QCOM_SC7280_SKU1) || (id == QCOM_SC7280_SKU2) || - (id == QCOM_SC7280_SKU3)) - printk(BIOS_INFO, "BoardID :%d - " + printk(BIOS_INFO, "BoardID :%d - " "Machine model: " "Qualcomm Technologies, Inc. " - "sc7280 IDP SKU%d platform\n", id, (id+1)); - else - printk(BIOS_ERR, "Invalid BoardId : %d\n", id); + "sc7280 platform\n", id); return id; } diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c index 05e53a64bb..50ca0aa4e0 100644 --- a/src/mainboard/google/herobrine/bootblock.c +++ b/src/mainboard/google/herobrine/bootblock.c @@ -2,8 +2,20 @@ #include #include "board.h" +#include +#include +#include void bootblock_mainboard_init(void) { setup_chromeos_gpios(); + + if (CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)) + i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ + + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) + qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); /* H1/TPM SPI */ + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ } diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index a11667586b..b5631fc8b2 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -3,9 +3,17 @@ #include #include #include "board.h" +#include void setup_chromeos_gpios(void) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + } + if (CONFIG(MAINBOARD_HAS_TPM2)) + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_input_pullup(GPIO_SD_CD_L); if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) { @@ -13,14 +21,41 @@ void setup_chromeos_gpios(void) gpio_output(GPIO_FP_RST_L, 0); gpio_output(GPIO_EN_FP_RAILS, 0); } + gpio_output(GPIO_AMP_ENABLE, 0); } void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio chromeos_gpios[] = { + const struct lb_gpio chromeos_gpios[] = { {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), "SD card detect"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, +#if CONFIG(EC_GOOGLE_CHROMEEC) + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, +#endif +#if CONFIG(MAINBOARD_HAS_TPM2) + {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + return !!gpio_get(GPIO_EC_IN_RW); + else /* If no EC, always return true */ + return 1; +} + +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_H1_AP_INT); +} diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 48beda0d10..362dff5715 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -3,15 +3,29 @@ #include "board.h" #include #include -#include -#include #include #include -#include #include #include #include #include +#include +#include + +static struct usb_board_data usb0_board_data = { + .parameter_override_x0 = 0xe6, + .parameter_override_x1 = 0x8b, + .parameter_override_x2 = 0x16, + .parameter_override_x3 = 0x03, +}; + +static void setup_usb(void) +{ + /* Assert EN_PP3300_HUB for those board variants that use it. */ + gpio_output(USB_HUB_LDO_EN, 1); + + setup_usb_host0(&usb0_board_data); +} static void configure_sdhci(void) { @@ -21,6 +35,18 @@ static void configure_sdhci(void) write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4); } +static void qi2s_configure_gpios(void) +{ + gpio_configure(GPIO_MI2S1_SCK, GPIO106_FUNC_MI2S1_SCK, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); + + gpio_configure(GPIO_MI2S1_WS, GPIO108_FUNC_MI2S1_WS, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); + + gpio_configure(GPIO_MI2S1_DATA0, GPIO107_FUNC_MI2S1_DATA0, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ @@ -42,7 +68,7 @@ static void mainboard_init(struct device *dev) qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Touch I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_UART, FIFO); /* BT UART */ - if (CONFIG(BOARD_GOOGLE_HEROBRINE)) { + if (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)) { /* Audio I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); /* Trackpad I2C */ @@ -51,13 +77,21 @@ static void mainboard_init(struct device *dev) qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* Fingerprint SPI */ qupv3_se_fw_load_and_init(QUPV3_1_SE3, SE_PROTOCOL_SPI, MIXED); - } else if (CONFIG(BOARD_GOOGLE_PIGLIN)) { + } else if (CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || + CONFIG(BOARD_GOOGLE_HOGLIN)) { /* APPS I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, GSI); /* ESIM SPI */ qupv3_se_fw_load_and_init(QUPV3_1_SE4, SE_PROTOCOL_SPI, MIXED); + } else { + /* Trackpad I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE0, SE_PROTOCOL_I2C, MIXED); + /* SAR sensor I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, MIXED); + /* Audio I2C */ + qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* Fingerprint SPI */ - qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_SPI, MIXED); + qupv3_se_fw_load_and_init(QUPV3_1_SE1, SE_PROTOCOL_SPI, MIXED); } /* Take FPMCU out of reset. Power was already applied @@ -65,6 +99,8 @@ static void mainboard_init(struct device *dev) if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) gpio_output(GPIO_FP_RST_L, 1); + setup_usb(); + qi2s_configure_gpios(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index ad2d2a0c46..2ea78b8f91 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -1,16 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include "board.h" #include +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb0(); +} + void platform_romstage_main(void) { shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); - + prepare_usb(); /* This rail needs to be stable by the time we take the FPMCU out of reset in ramstage, so already turn it on here. This needs to happen at least 200ms after this pin was first driven low in the bootblock. */ diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 2f54be9b3b..0724466015 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,19 +1,34 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n - select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 - select SUPERIO_ITE_IT8772F + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select SOC_INTEL_BROADWELL + select SUPERIO_ITE_IT8772F + +config BOARD_GOOGLE_GUADO + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_JECHT + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_RIKKU + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_TIDUS + select BOARD_GOOGLE_BASEBOARD_JECHT if BOARD_GOOGLE_BASEBOARD_JECHT +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/jecht/Kconfig.name b/src/mainboard/google/jecht/Kconfig.name index b241ca4f8a..d28e5a1e53 100644 --- a/src/mainboard/google/jecht/Kconfig.name +++ b/src/mainboard/google/jecht/Kconfig.name @@ -2,16 +2,12 @@ comment "Jecht" config BOARD_GOOGLE_GUADO bool "-> Guado (ASUS Chromebox CN62)" - select BOARD_GOOGLE_BASEBOARD_JECHT config BOARD_GOOGLE_JECHT bool "-> Jecht" - select BOARD_GOOGLE_BASEBOARD_JECHT config BOARD_GOOGLE_RIKKU bool "-> Rikku (Acer Chromebox CXI2)" - select BOARD_GOOGLE_BASEBOARD_JECHT config BOARD_GOOGLE_TIDUS bool "-> Tidus (Lenovo ThinkCentre Chromebox)" - select BOARD_GOOGLE_BASEBOARD_JECHT diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index cf59636073..239134bc5f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include #include #include @@ -10,9 +12,6 @@ #include #include "onboard.h" -#define GPIO_SPI_WP 58 -#define GPIO_REC_MODE 12 - #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -28,6 +27,16 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -46,11 +55,11 @@ void init_bootmode_straps(void) const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); /* Developer: Virtual */ @@ -67,3 +76,10 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 08b2c957c7..e972baabaf 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -38,7 +38,7 @@ chip soc/intel/broadwell register "pcie_port_force_aspm" = "0x10" # Enable port coalescing - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP register "icc_clock_disable" = "0x01220000" diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index fd7e9e2493..3c255b7871 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include "onboard.h" static void mainboard_init(struct device *dev) @@ -15,7 +14,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index 1c37d7228d..a6ba80a7b3 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -37,4 +37,10 @@ enum { #define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) #define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0) +/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ +#define GPIO_SPI_WP 58 + +/* Recovery: GPIO12 = RECOVERY_L, active low */ +#define GPIO_REC_MODE 12 + #endif diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl index 2a16352c41..c8808dd2e5 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -27,7 +27,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -69,12 +69,12 @@ Scope (\_TZ) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If (LEqual (Local0, 255) || LEqual (Local0, 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max If (LGreaterEqual (Local1, \TMAX)) { @@ -82,7 +82,7 @@ Scope (\_TZ) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } @@ -95,8 +95,7 @@ Scope (\_TZ) Store (CTOK (\TMAX), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for SuperIO to re-poll Sleep (1000) @@ -104,8 +103,7 @@ Scope (\_TZ) // Re-read temperature from SuperIO Store (TCHK (), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) @@ -167,7 +165,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (0, \FLVL) Store (FAN0_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -194,7 +192,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (1, \FLVL) Store (FAN1_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -221,7 +219,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (2, \FLVL) Store (FAN2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -248,7 +246,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (3, \FLVL) Store (FAN3_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -275,7 +273,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (4, \FLVL) Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl index 2a16352c41..c8808dd2e5 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -27,7 +27,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -69,12 +69,12 @@ Scope (\_TZ) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If (LEqual (Local0, 255) || LEqual (Local0, 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max If (LGreaterEqual (Local1, \TMAX)) { @@ -82,7 +82,7 @@ Scope (\_TZ) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } @@ -95,8 +95,7 @@ Scope (\_TZ) Store (CTOK (\TMAX), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for SuperIO to re-poll Sleep (1000) @@ -104,8 +103,7 @@ Scope (\_TZ) // Re-read temperature from SuperIO Store (TCHK (), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) @@ -167,7 +165,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (0, \FLVL) Store (FAN0_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -194,7 +192,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (1, \FLVL) Store (FAN1_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -221,7 +219,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (2, \FLVL) Store (FAN2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -248,7 +246,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (3, \FLVL) Store (FAN3_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -275,7 +273,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (4, \FLVL) Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl index 2a16352c41..c8808dd2e5 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -27,7 +27,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -69,12 +69,12 @@ Scope (\_TZ) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If (LEqual (Local0, 255) || LEqual (Local0, 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max If (LGreaterEqual (Local1, \TMAX)) { @@ -82,7 +82,7 @@ Scope (\_TZ) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } @@ -95,8 +95,7 @@ Scope (\_TZ) Store (CTOK (\TMAX), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for SuperIO to re-poll Sleep (1000) @@ -104,8 +103,7 @@ Scope (\_TZ) // Re-read temperature from SuperIO Store (TCHK (), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) @@ -167,7 +165,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (0, \FLVL) Store (FAN0_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -194,7 +192,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (1, \FLVL) Store (FAN1_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -221,7 +219,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (2, \FLVL) Store (FAN2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -248,7 +246,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (3, \FLVL) Store (FAN3_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -275,7 +273,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (4, \FLVL) Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl index e2f267547e..2a7b3f09cb 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -42,7 +42,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -112,7 +112,7 @@ Scope (\_TZ) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If (LEqual (Local0, 255) || LEqual (Local0, 0)) { Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) } @@ -177,12 +177,12 @@ Scope (\_TZ) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If (LEqual (Local0, 255) || LEqual (Local0, 0)) { Return (CTOK (FAN0_0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max If (LGreaterEqual (Local1, \TMAX)) { @@ -190,7 +190,7 @@ Scope (\_TZ) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } @@ -203,8 +203,7 @@ Scope (\_TZ) Store (CTOK (\TMAX), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for SuperIO to re-poll Sleep (1000) @@ -212,8 +211,7 @@ Scope (\_TZ) // Re-read temperature from SuperIO Store (TCHK (), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) @@ -275,7 +273,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (0, \FLVL) Store (F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -302,7 +300,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (1, \FLVL) Store (F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -329,7 +327,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (2, \FLVL) Store (F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -356,7 +354,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (3, \FLVL) Store (F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) @@ -383,7 +381,7 @@ Scope (\_TZ) } } Method (_ON) { - If (LNot (_STA ())) { + If (! _STA ()) { Store (4, \FLVL) Store (F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 5940d1a2b6..0f536b4f9a 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -37,6 +37,9 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE if BOARD_GOOGLE_BASEBOARD_KAHLEE +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config MAINBOARD_DIR default "google/kahlee" @@ -123,6 +126,24 @@ config OEM_BIN_FILE depends on USE_OEM_BIN default "" +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 4 # Dual IO (1-2-2) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 0 # 66MHz + +config TPM_SPI_SPEED + default 0 # 66MHz + +endif + # Don't use AMD's Secure OS config USE_PSPSECUREOS def_bool n diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index d040f31df5..1fa8217b61 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -1,20 +1,25 @@ comment "Kahlee" config BOARD_GOOGLE_ALEENA - bool "-> Aleena" + bool "-> Aleena/Kasumi (Acer Chromebook 315 (CB315-2H), 311 (C721) / Spin 311 (R721T))" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_CAREENA - bool "-> Careena" + bool "-> Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6)" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_GRUNT bool "-> Grunt" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_LIARA - bool "-> Liara" + bool "-> Liara (Lenovo 14e Chromebook, Chromebook S345-14)" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_NUWANI bool "-> Nuwani" select BOARD_GOOGLE_BASEBOARD_KAHLEE + config BOARD_GOOGLE_TREEYA - bool "-> Treeya" + bool "-> Treeya (Lenovo 100e/300e Gen2 AMD)" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 349fe34068..5ccd1816a6 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include @@ -67,7 +67,7 @@ void set_board_env_params(GNB_ENV_CONFIGURATION *params) const struct soc_amd_stoneyridge_config *cfg; const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n"); + printk(BIOS_WARNING, "Cannot find SoC devicetree config\n"); return; } cfg = dev->chip_info; diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 9b456c8ed5..0ee9b58110 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -25,32 +25,6 @@ void bootblock_mainboard_early_init(void) void bootblock_mainboard_init(void) { - if (CONFIG(EM100)) { - /* - * We should be able to rely on defaults, but it seems safer - * to explicitly set up these registers. - */ - sb_read_mode(SPI_READ_MODE_NOM); - sb_set_spi100(SPI_SPEED_16M, /* Normal */ - SPI_SPEED_16M, /* Fast */ - SPI_SPEED_16M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ - } else { - /* - * W25Q128FW Setup - * Normal Read 40MHz - * Fast Read 104MHz - * Dual Read IO (1-2-2) - */ - sb_read_mode(SPI_READ_MODE_DUAL122); - - /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_66M, /* Fast */ - SPI_SPEED_66M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ - } - /* Setup TPM decode before verstage */ lpc_tpm_decode_spi(); } diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index b85f976890..690a9e3af3 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include @@ -32,3 +34,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 51e0e7f63a..66a933561c 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -39,7 +39,7 @@ static void early_ec_init(void) ec_ioport_base, ec_ioport_size); status = lpc_set_wideio_range(ec_ioport_base, ec_ioport_size); if (status == WIDEIO_RANGE_ERROR) - printk(BIOS_WARNING, "ERROR: Failed to assign a range\n"); + printk(BIOS_ERR, "Failed to assign a range\n"); else printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status); } diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ffec6a5396..2cd88b87f8 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -11,12 +11,12 @@ #include #include #include +#include #include #include #include #include #include -#include /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -146,7 +146,6 @@ static void mainboard_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } int mainboard_get_xhci_oc_map(uint16_t *map) diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index bf71f4147c..c4d6f01e51 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 79fd4784af..a3dfa15e93 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include static const PCIe_PORT_DESCRIPTOR PortList[] = { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl index d151e1d14d..7aaf4782cb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -30,8 +30,8 @@ Method (_PTS, 1) /* Clear wake status structure. */ Store (0, PEWD) - Store (0, Index(WKST,0)) - Store (0, Index(WKST,1)) + Store (0, WKST[0]) + Store (0, WKST[1]) Store (7, UPWS) } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl index 32a6549d83..2930def1f8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -24,7 +24,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -56,8 +56,7 @@ Scope (\_TZ) Store (CTOK (\TCRT), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) /* Wait 1 second for EC to re-poll */ Sleep (1000) @@ -65,8 +64,7 @@ Scope (\_TZ) /* Re-read temperature from EC */ Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 4b60a9cfc3..91101872f4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -29,12 +29,12 @@ int __weak variant_mainboard_read_spd(uint8_t spdAddress, void *spd = (void *)spd_cbfs_map(spd_index); if (!spd) { - printk(BIOS_ERR, "Error: spd.bin not found\n"); + printk(BIOS_ERR, "spd.bin not found\n"); return -1; } if (len != CONFIG_DIMM_SPD_SIZE) { - printk(BIOS_ERR, "Error: spd.bin is not the correct size\n"); + printk(BIOS_ERR, "spd.bin is not the correct size\n"); return -1; } diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 4c44c565ca..a1614ed2aa 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -92,6 +92,7 @@ config BOARD_SDRAM_TABLE_OFFSET default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO + default 0x40 if BOARD_GOOGLE_KAPPA default 0x0 config BOARD_OVERRIDE_LCM_ID diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 3d5f309232..d4d3a65c83 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -5,11 +5,11 @@ config BOARD_GOOGLE_KUKUI select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KRANE - bool "-> Krane" + bool "-> Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)" select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KODAMA - bool "-> Kodama" + bool "-> Kodama (Lenovo 10e Chromebook Tablet)" select BOARD_GOOGLE_KUKUI_COMMON config BOARD_GOOGLE_KAKADU @@ -31,7 +31,7 @@ config BOARD_GOOGLE_JACUZZI select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_JUNIPER - bool "-> Juniper" + bool "-> Juniper (Acer Chromebook Spin 311 (CP311-3H))" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_KAPPA @@ -39,7 +39,7 @@ config BOARD_GOOGLE_KAPPA select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_DAMU - bool "-> Damu" + bool "-> Damu (ASUS Chromebook Flip CM3 (CM3200))" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_CERISE @@ -55,11 +55,11 @@ config BOARD_GOOGLE_WILLOW select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_ESCHE - bool "-> Esche" + bool "-> Esche (HP Chromebook 11MK G9 EE)" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_BURNET - bool "-> Burnet" + bool "-> Burnet (HP Chromebook x360 11MK G3 EE)" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_FENNEL diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 3f15a3fb91..4c4a8bec03 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -37,3 +37,9 @@ int tis_plat_irq_status(void) { return gpio_eint_poll(CR50_IRQ); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 040810e1d8..283cf66519 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -34,6 +34,10 @@ static const char *const sdram_configs[] = { [0x15] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB", [0x16] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", [0x17] = "sdram-lpddr4x-MT53E1G32D2NP-046-4GB", + [0x18] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x19] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x1a] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x1b] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB", /* Table shared by Kakadu and its variants, offset = 0x20 */ [0x20] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", @@ -55,6 +59,19 @@ static const char *const sdram_configs[] = { [0x39] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", [0x3a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", [0x3b] = "sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB", + + /* Table shared by Kappa and its variants, offset = 0x40 */ + [0x40] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", + [0x41] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x42] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x43] = "sdram-lpddr4x-MT53E1G32D2NP-046-4GB", + [0x44] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB", + [0x45] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB", + [0x46] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x48] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB", + [0x49] = "sdram-lpddr4x-MT53E2G32D4NQ-046-8GB", + [0x4a] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB", + [0x4b] = "sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB", }; static struct sdram_params params; diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index ee68e46df9..ba38cb78fd 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -1,24 +1,27 @@ if BOARD_GOOGLE_LINK +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC - select HAVE_SPD_IN_CBFS - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_LIBGFXINIT + select HAVE_ACPI_TABLES select HAVE_IFD_BIN select HAVE_ME_BIN + select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 540803ca1a..f5441677db 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -4,7 +4,11 @@ #include #include #include +#include #include +#include "onboard.h" + +#define GPIO_EC_IN_RW 21 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -25,15 +29,21 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - return get_gpio(57); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index fda74da3b8..49c34765c8 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -56,7 +56,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00fc0901" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 088d5385ca..d3209d0490 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include -#include #include #include #include @@ -88,11 +88,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index c4b621ac7a..4fdfd14f6e 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -7,7 +7,6 @@ #if CONFIG(VGA_ROM_RUN) #include #endif -#include #include #include #include "onboard.h" @@ -16,7 +15,6 @@ #include #include #include -#include #if CONFIG(VGA_ROM_RUN) static int int15_handler(void) @@ -170,7 +168,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; #if CONFIG(VGA_ROM_RUN) /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index 7e351e41f7..efcda92ef9 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -16,4 +16,8 @@ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a #define BOARD_TOUCHSCREEN_IRQ 22 +#define GPIO_REC_MODE 9 + +#define GPIO_SPI_WP 57 + #endif diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index c827c7d13d..7ffcd57c51 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -1,8 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include void fill_lb_gpios(struct lb_gpios *gpios) { } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 7fe877bff0..9aaad2f191 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -19,3 +19,9 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 8bce1b2b04..e4e79755a1 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -13,7 +13,6 @@ #include #include #include -#include static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 7fe877bff0..9aaad2f191 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -19,3 +19,9 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 81da9128a8..0250b456b3 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -13,7 +13,6 @@ #include #include #include -#include static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 7fe877bff0..9aaad2f191 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -19,3 +19,9 @@ int get_write_protect_state(void) { return !gpio_get(GPIO(R1)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO(U4)); +} diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 4499f9cb7f..d6aa05a03d 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -13,7 +13,6 @@ #include #include #include -#include static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 9e7af27382..739df2e25b 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -34,3 +34,9 @@ int get_write_protect_state(void) { return !gpio_get(WRITE_PROTECT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index afbea9c770..55ef91aad1 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -17,7 +17,6 @@ #include #include #include -#include #include enum { diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index eb6cbc6efc..840ce8ef77 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -1,7 +1,5 @@ - config BOARD_GOOGLE_BASEBOARD_OCTOPUS def_bool n - select SOC_INTEL_GEMINILAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A @@ -14,34 +12,101 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_SKUID + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_AMPTON select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select SOC_ESPI select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 - select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_BOOTBLOCK_CONSOLE - select NO_FMAP_CACHE select NO_CBFS_MCACHE + select NO_FMAP_CACHE + select SOC_ESPI + select SOC_INTEL_GEMINILAKE + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_AMPTON + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_BLOOG + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_BOBBA + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_CASTA + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_DOOD + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_FLEEX + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_FOOB + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_GARG + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_LICK + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_MEEP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_OCTOPUS + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + +config BOARD_GOOGLE_PHASER + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_YORP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS if BOARD_GOOGLE_BASEBOARD_OCTOPUS +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config CHROMEOS_WIFI_SAR bool default y if CHROMEOS select DSAR_ENABLE + select GEO_SAR_ENABLE select SAR_ENABLE select USE_SAR - select GEO_SAR_ENABLE - -config BASEBOARD_OCTOPUS_LAPTOP - def_bool n - select SYSTEM_TYPE_LAPTOP config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 41932d71f1..3657e9ca35 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -1,84 +1,40 @@ comment "Octopus" -config BOARD_GOOGLE_OCTOPUS - bool "-> Octopus" - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select BASEBOARD_OCTOPUS_LAPTOP - -config BOARD_GOOGLE_YORP - bool "-> Yorp" - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select BASEBOARD_OCTOPUS_LAPTOP - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_PHASER - bool "-> Phaser" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_LICK - bool "-> Lick" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_FLEEX - bool "-> Fleex" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_BOBBA - bool "-> Bobba" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_MEEP - bool "-> Meep" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - config BOARD_GOOGLE_AMPTON - bool "-> Ampton" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_CASTA - bool "-> Casta" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + bool "-> Ampton (ASUS Chromebook Flip C214)" config BOARD_GOOGLE_BLOOG - bool "-> Bloog" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + bool "-> Bloog (HP Chromebook x360 12b, 14a, x360 14b)" -config BOARD_GOOGLE_GARG - bool "-> Garg" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS +config BOARD_GOOGLE_BOBBA + bool "-> Bobba (Acer Chromebook 311 / Spin 511)" + +config BOARD_GOOGLE_CASTA + bool "-> Bluebird/Casta (Samsung Chromebook 4, 4+)" config BOARD_GOOGLE_DOOD bool "-> Dood" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_FLEEX + bool "-> Fleex (Dell Chromebook 3100)" config BOARD_GOOGLE_FOOB bool "-> Foob" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_GARG + bool "-> Garg" + +config BOARD_GOOGLE_LICK + bool "-> Lick (Ideapad 3 Chromebook)" + +config BOARD_GOOGLE_MEEP + bool "-> Meep (HP Chromebook x360 11 G2 EE)" + +config BOARD_GOOGLE_OCTOPUS + bool "-> Octopus" + +config BOARD_GOOGLE_PHASER + bool "-> Phaser (Lenovo 100e/300e/500e Chromebook 2nd Gen (Intel))" + +config BOARD_GOOGLE_YORP + bool "-> Yorp" diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 03d3b4f0fa..82599aca73 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include +#include #include #include #include @@ -33,3 +35,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/octopus/default.fmd b/src/mainboard/google/octopus/default.fmd index 79b2a6a143..dec6b488c0 100644 --- a/src/mainboard/google/octopus/default.fmd +++ b/src/mainboard/google/octopus/default.fmd @@ -3,7 +3,7 @@ FLASH 16M { SI_BIOS@0x1000 0xf7e000 { IFWI@0x0 0x1ff000 # SMMSTORE requires 64k alignment - SMMSTORE@0xa5e000 0x40000 + SMMSTORE@0xa4f000 0x40000 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 9ffd633738..a614763bda 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -62,6 +61,7 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) /* For RT5682, GPIO 137 should be set as EDGE_BOTH. */ const struct pad_config rt5682_gpio_137 = PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, DISPUPD); + enum ssfc_audio_codec codec = ssfc_get_audio_codec(); if (table == NULL || num == 0) return; @@ -72,7 +72,8 @@ static void gpio_modification_by_ssfc(struct pad_config *table, size_t num) * provide override_table right now so it will be returned earlier since * table above is NULL. */ - if (ssfc_get_audio_codec() != SSFC_AUDIO_CODEC_RT5682) + if ((codec != SSFC_AUDIO_CODEC_RT5682) && + (codec != SSFC_AUDIO_CODEC_RT5682_VS)) return; while (num--) { @@ -138,7 +139,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { @@ -192,13 +192,26 @@ static void audio_codec_device_update(void) continue; } - if ((audio_dev->chip_ops == &drivers_i2c_generic_ops) && - (codec == SSFC_AUDIO_CODEC_RT5682)) { + if (audio_dev->chip_ops == &drivers_i2c_generic_ops) { struct drivers_i2c_generic_config *cfg = audio_dev->chip_info; - if (cfg != NULL && !strcmp(cfg->hid, "10EC5682")) { - printk(BIOS_INFO, "enable RT5682.\n"); + if ((cfg != NULL && !strcmp(cfg->hid, "10EC5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682)) { + printk(BIOS_INFO, "enable RT5682 VD.\n"); + continue; + } + + if ((cfg != NULL && !strcmp(cfg->hid, "10EC5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682_VS)) { + cfg->hid = "RTL5682"; + printk(BIOS_INFO, "enable RT5682 VS.\n"); + continue; + } + + if ((cfg != NULL && !strcmp(cfg->hid, "RTL5682")) && + (codec == SSFC_AUDIO_CODEC_RT5682_VS)) { + printk(BIOS_INFO, "enable RT5682 VS.\n"); continue; } } diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 8d83609fbf..47daba23dd 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -34,7 +34,7 @@ void mainboard_save_dimm_info(void) if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], ARRAY_SIZE(part_num_store)) < 0) - printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n"); + printk(BIOS_ERR, "Couldn't obtain DRAM part number from CBI\n"); else part_num = &part_num_store[0]; diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c index 488ba07cc4..8d84840848 100644 --- a/src/mainboard/google/octopus/smihandler.c +++ b/src/mainboard/google/octopus/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 6878cadf97..61e8e0d9c9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -3,7 +3,8 @@ #include #include #include -#include +#include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' @@ -343,6 +344,8 @@ static const struct pad_config early_gpio_table[] = { * stages. */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ + + PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h index cef047aa5d..cd160bad88 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h @@ -30,6 +30,7 @@ enum ssfc_audio_codec { SSFC_AUDIO_CODEC_DA7219, SSFC_AUDIO_CODEC_RT5682, SSFC_AUDIO_CODEC_CS42L42, + SSFC_AUDIO_CODEC_RT5682_VS, }; #define SSFC_AUDIO_CODEC_OFFSET 9 #define SSFC_AUDIO_CODEC_MASK 0x7 diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c index 9c9316c67a..13a40b35dd 100644 --- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c +++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c @@ -28,7 +28,9 @@ void __weak variant_nhlt_init(struct nhlt *nhlt) printk(BIOS_ERR, "Added Dialog_7219 codec.\n"); } - if (CONFIG(NHLT_RT5682) && codec == SSFC_AUDIO_CODEC_RT5682) { + if (CONFIG(NHLT_RT5682) && + (codec == SSFC_AUDIO_CODEC_RT5682 || + codec == SSFC_AUDIO_CODEC_RT5682_VS)) { /* Realtek for Headset codec */ if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2)) printk(BIOS_ERR, "Added ALC5682 codec.\n"); diff --git a/src/mainboard/google/octopus/variants/bloog/Makefile.inc b/src/mainboard/google/octopus/variants/bloog/Makefile.inc index ba865e9f82..98c1e441b0 100644 --- a/src/mainboard/google/octopus/variants/bloog/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bloog/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c + +$(call add_vbt_to_cbfs, vbt_blooguard.bin, blooguard-data.vbt) diff --git a/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt b/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..1d93571b5fc0dcee30e3d72620aa07811a1a297d GIT binary patch literal 5632 zcmeHLYitx%6h1Sv&pR{ic3Pk;wOk&;wm>^AP)e>`bYmbPdS zp<^gXqtWaSA83fy7^A^IB`Vh82tgP=gv&KEv0lpP*Kk2 z+;i@kbH97fx%bY!v&);yo9L#>+F)I<#=oVKGKzo-ug}ZCawe4r>l<4u{7wGW@|ya< z7WzHRhwbyOod<|;oL4GP)q>!z{%Du4A&1s>cXW0|^DCl#PxW{A&`=;q{oA%hyQ01A z{m}?*Y~JLj3{NKIdpf%!v~JJNj%aTQMGzIeX~DX@wd*J?+>o!X%`a37*5i|sf})c3 z8)Z^a8K|!f;h39(^>wtqfmQ??{f&*4wdFOB(NIHub+A0xR9PXDX(0r>5?!{Joe?#_lyf)Dxy9u5e_ zu+(+}Ty6@h+#YxYIgEVLPT&XR)5yOd|B8GS+36sVhP(**LF9bojmQDyTI5HO+mRi6 z;7Xj=*%Tn@oF&st2_74~oCEq1%YMYNyD#BnBN0oAmNbk>6!Eyz3D@G^WnoK?qs(CX_5!Eml1qcei1cH+}?t# zbSTS+Wh=nxw`BnafTUS_4eg3Fu_z6vjJLqyHA8onnsR3OPd@Rom&2k9{HT+_sPi&6 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zlEV^dlIUJZeo-Q?O7v4n{zf7{O7yBEr+LXDFD>`VQ7?JiE9J>{jUVTP}rJ91KK<@N7=;(%>xf-3SZ}Q zBg7Vg8iX7rbGX<<$Sgi6822+oz!_%~Y;En(bYMa`K?6oE2rr1#iz zM95>Y10aGuVcb*15&KXI>*3AZkPA>8JgG!P^c!A?_%;=CV5B6Oi5Dk0X&$b*o;{fJ}GoF&G3V2gbARn3=bnY&BY zsI6;~b0M&gAr=LG(agOsa#d*8Afw&qOJ}XjG2r_YNvy4ov_(30#k=b}cEtI?(lUJn8`0>x7MR)cT5KZPN}eDW8Xv z!6s!kDk}q5QCCiNF$c@Lb`|0BXbY49{vW}9(?P>4agwx2)!a|`=b6AXj|aS2c_r1&on5`p?A^EjfacQR9r)spvzN}E zJ3B6%S$-yTI)3`l*n4B|k6j#_M43Y|`d5-p9De#+WE^*R+Rf6xdPn-7= #include #include -#include #include #include #include diff --git a/src/mainboard/google/octopus/variants/casta/data.vbt b/src/mainboard/google/octopus/variants/casta/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..fbcf46e8494c759ef00a29bbd1b59c648a398994 GIT binary patch literal 5632 zcmeHLYitx%6h1Sv&$~0*?UYAZYPmct+XC&hKqkf^_m5r3#8L~Rq)@XHcnf&>y0G5P}-&z+feTT1DIprV}3 zx#!$7=YIE|bMKvdXIHdTG}BF0b>aGOZE#B!WfTJiUY~yo%b8RWZfI(&3^oVbDry@- zTj(iR0NdwZI}Z@!IKNn^D23r&1M%)aV=k@h>Fnx`7gWakpBm`trIApW2DfdCcgOoW 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HAVE_IFD_BIN - select HAVE_ME_BIN - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE + select EC_COMPAL_ENE932 # This board also feature sandy-bridge CPU's so must have LVDS select GFX_GMA_PANEL_1_ON_LVDS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_IFD_BIN + select HAVE_ME_BIN + select HAVE_OPTION_TABLE + select INTEL_INT15 + select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 0c7120de75..8f4396eddd 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "ec.h" diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 03b0d476f3..2b361ac569 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -8,9 +7,10 @@ #include #include -#include +#include #include -#include "ec.h" + +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -19,7 +19,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) struct lb_gpio chromeos_gpios[] = { /* Lid switch GPIO active high (open). */ - {15, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {GPIO_LID, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, @@ -33,32 +33,27 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - return get_gpio(15); + return get_gpio(GPIO_LID); } int get_write_protect_state(void) { - return !get_gpio(70); + return !get_gpio(GPIO_SPI_WP); } int get_recovery_mode_switch(void) { - u8 gpio = !get_gpio(68); - /* GPIO68, active low. For Servo support - * Treat as active high and let the caller invert if needed. */ - printk(BIOS_DEBUG, "REC MODE GPIO 68: %x\n", gpio); - - return gpio; + return !get_gpio(GPIO_REC_MODE); } static int parrot_ec_running_ro(void) { - return !get_gpio(68); + return get_recovery_mode_switch(); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) @@ -68,3 +63,10 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index d748277a07..6850cf2c6d 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00040069" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index a11dc9163b..f4769a1343 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include #include #include @@ -57,11 +57,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c index f4187eb4f2..4de187e89b 100644 --- a/src/mainboard/google/parrot/ec.c +++ b/src/mainboard/google/parrot/ec.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 16695dbeb8..eeb3ce4487 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -10,7 +10,6 @@ #include #include #include -#include void mainboard_suspend_resume(void) { @@ -61,7 +60,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index 9bece67886..d564c5695c 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -9,4 +9,13 @@ #define BOARD_TRACKPAD_IRQ_PVT 20 #define BOARD_TRACKPAD_WAKE_GPIO 0x1c +#define GPIO_LID 15 + +/* GPIO68, active low. For Servo support + * Treat as active high and let the caller invert if needed. */ +#define GPIO_REC_MODE 68 + + +#define GPIO_SPI_WP 70 + #endif diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index ebbfdd3cb4..e1d8fa1a9a 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -6,6 +6,7 @@ #include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -37,3 +38,9 @@ int get_write_protect_state(void) { return !gpio_get_value(GPIO_X30); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get_value(GPIO_X23); +} diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 586180b30e..e65062803c 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -1,4 +1,3 @@ - config BOARD_GOOGLE_BASEBOARD_POPPY def_bool n select BOARD_ROMSIZE_KB_16384 @@ -10,15 +9,101 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_POPPY + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 - select HAVE_SPD_IN_CBFS + select SOC_INTEL_KABYLAKE + +config BOARD_GOOGLE_ATLAS + select BOARD_GOOGLE_BASEBOARD_POPPY + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP + select VARIANT_HAS_CAMERA_ACPI + +config BOARD_GOOGLE_POPPY + select BOARD_GOOGLE_BASEBOARD_POPPY + select DRIVERS_I2C_MAX98927 + select MAINBOARD_HAS_I2C_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_LAPTOP + select VARIANT_HAS_CAMERA_ACPI + +config BOARD_GOOGLE_NAMI + select BOARD_GOOGLE_BASEBOARD_POPPY + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_NAUTILUS + select BOARD_GOOGLE_BASEBOARD_POPPY + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_I2C_TPM_CR50 + select SYSTEM_TYPE_CONVERTIBLE + select VARIANT_HAS_CAMERA_ACPI + +config BOARD_GOOGLE_NOCTURNE + select BOARD_GOOGLE_BASEBOARD_POPPY + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_SX9310 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_SPI_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI + +config BOARD_GOOGLE_RAMMUS + select BOARD_GOOGLE_BASEBOARD_POPPY + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98927 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_SORAKA + select BOARD_GOOGLE_BASEBOARD_POPPY + select DRIVERS_I2C_MAX98927 + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_I2C_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI if BOARD_GOOGLE_BASEBOARD_POPPY +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CHROMEOS_WIFI_SAR bool depends on CHROMEOS @@ -127,81 +212,6 @@ config VARIANT_HAS_CAMERA_ACPI bool default n -config VARIANT_SPECIFIC_OPTIONS_ATLAS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_POPPY - def_bool n - select DRIVERS_I2C_MAX98927 - select MAINBOARD_HAS_I2C_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_LAPTOP - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_NAMI - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - -config VARIANT_SPECIFIC_OPTIONS_NAUTILUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select MAINBOARD_HAS_I2C_TPM_CR50 - select SYSTEM_TYPE_CONVERTIBLE - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_NOCTURNE - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_SX9310 - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - select MAINBOARD_HAS_SPI_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - -config VARIANT_SPECIFIC_OPTIONS_RAMMUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98927 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select SYSTEM_TYPE_LAPTOP - -config VARIANT_SPECIFIC_OPTIONS_SORAKA - def_bool n - select DRIVERS_I2C_MAX98927 - select MAINBOARD_HAS_I2C_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index 9ecdb44cf0..4b1fe69d83 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -2,35 +2,32 @@ comment "Poppy" config BOARD_GOOGLE_ATLAS bool "-> Atlas (Google Pixelbook Go)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_ATLAS config BOARD_GOOGLE_POPPY bool "-> Poppy" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_POPPY config BOARD_GOOGLE_NAMI bool "-> Nami" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAMI + help + The Nami board supports the following devices: + - Acer Chromebook 13 / Spin 13 (Akali) + - Lenovo Yoga Chromebook C630 (Pantheon) + - HP Chromebook x360 14 (Sona) + - HP Chromebook 15 G1 (Syndra) + - Dell Inspiron Chromebook 14 (7460) (Vayne) config BOARD_GOOGLE_NAUTILUS - bool "-> Nautilus (Samsung Chromebook Plus (V2 / LTE))" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAUTILUS + bool "-> Nautilus (Samsung Chromebook Plus V2, V2 LTE)" config BOARD_GOOGLE_NOCTURNE bool "-> Nocturne (Google Pixel Slate)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NOCTURNE config BOARD_GOOGLE_RAMMUS - bool "-> Rammus (Asus Chromebook C425, Flip C433, Flip C434)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_RAMMUS + bool "-> Rammus" + help + The Rammus board supports the following devices: + - Asus Chromebook C425 (Leona) + - Asus Chromebook Flip C433/C434 (Shyvana) config BOARD_GOOGLE_SORAKA bool "-> Soraka (HP Chromebook x2)" - select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_SORAKA diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 5dd1e9877e..3c267cad0f 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include #include #include #include +#include #include #include @@ -38,3 +39,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 0a3fe1ff0f..0e6c7b98c6 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -6,7 +6,6 @@ #include #include #include -#include #include @@ -47,7 +46,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 62dd1f5099..d26f6bd28a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -44,14 +44,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index d3ea6b537b..ffea694910 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -345,6 +345,9 @@ static const struct pad_config early_gpio_table[] = { /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ebbb12f973..db4aeebb9f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,14 +32,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index dd97d1c6c4..ea9de7aa54 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ @@ -340,6 +341,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 34163efc51..7609e004cc 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,13 +32,11 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 6dba783920..b5ec95405e 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -346,6 +346,9 @@ static const struct pad_config early_gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index a29b9f37ca..629469d48e 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -241,7 +241,7 @@ void variant_devtree_update(void) case SKU_6_SYNDRA: case SKU_7_SYNDRA: pl2_id = PL2_ID_SONA_SYNDRA; - /* fallthrough */ + __fallthrough; case SKU_0_VAYNE: case SKU_1_VAYNE: case SKU_2_VAYNE: diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 098216d3c5..b8a1812751 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -32,14 +32,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 37378f93a7..e06355a3b7 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -331,6 +331,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 0d9c5bd033..03336f2e47 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,14 +37,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nocturne/ec.c b/src/mainboard/google/poppy/variants/nocturne/ec.c index fe3ee15cf8..5c78e384c9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/ec.c +++ b/src/mainboard/google/poppy/variants/nocturne/ec.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index f5344584ba..6324d8fa47 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -352,6 +352,9 @@ static const struct pad_config early_gpio_table[] = { /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index f2dc5b6b3b..c6c2d3df60 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -44,14 +44,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 8e9e5c01c5..c67c560c70 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -349,6 +349,9 @@ static const struct pad_config early_gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 745d72ce32..5c347924df 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,14 +32,12 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 9d52773271..808ab3b504 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -342,6 +342,10 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), + + /* C6 : SM1CLK ==> EC_IN_RW_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 983ca495e4..dfd66c07dc 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -1,23 +1,100 @@ - config BOARD_GOOGLE_BASEBOARD_RAMBI def_bool n - select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select ENABLE_BUILTIN_COM1 if CONSOLE_SERIAL - select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_RAMBI + select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select SYSTEM_TYPE_LAPTOP if !BOARD_GOOGLE_NINJA && !BOARD_GOOGLE_SUMO - select HAVE_SPD_IN_CBFS + select SOC_INTEL_BAYTRAIL + +config BOARD_GOOGLE_BANJO + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_CANDY + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_CLAPPER + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_ENGUARDE + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_GLIMMER + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_GNAWTY + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_HELI + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_KIP + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_NINJA + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_ORCO + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_QUAWKS + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_SQUAWKS + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_RAMBI + select BOARD_GOOGLE_BASEBOARD_RAMBI + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_SUMO + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_SWANKY + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_WINKY + select BOARD_GOOGLE_BASEBOARD_RAMBI + select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BASEBOARD_RAMBI +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name index fe26faae9a..bae223e743 100644 --- a/src/mainboard/google/rambi/Kconfig.name +++ b/src/mainboard/google/rambi/Kconfig.name @@ -2,64 +2,48 @@ comment "Rambi" config BOARD_GOOGLE_BANJO bool "-> Banjo (Acer Chromebook 15 (CB3-531))" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_CANDY bool "-> Candy (Dell Chromebook 11 3120)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_CLAPPER bool "-> Clapper (Lenovo N20 Chromebook)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_ENGUARDE bool "-> Enguarde" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_GLIMMER bool "-> Glimmer (Lenovo ThinkPad 11e Chromebook)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_GNAWTY bool "-> Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735))" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_HELI bool "-> Heli (Haier Chromebook G2)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_KIP bool "-> Kip (HP Chromebook 11 G3 / G4 / G4 EE)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_NINJA bool "-> Ninja (AOpen Chromebox Commercial)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_ORCO bool "-> Orco (Lenovo 100S Chromebook)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_QUAWKS bool "-> Quawks (ASUS Chromebook C300)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_SQUAWKS bool "-> Squawks (ASUS Chromebook C200)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_RAMBI bool "-> Rambi" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_SUMO bool "-> Sumo (AOpen Chromebase Commercial)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_SWANKY bool "-> Swanky (Toshiba Chromebook 2)" - select BOARD_GOOGLE_BASEBOARD_RAMBI config BOARD_GOOGLE_WINKY bool "-> Winky (Samsung Chromebook 2 (XE500C12))" - select BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index f9a171820d..d76c5e4c57 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -3,11 +3,15 @@ #include #include #include +#include #include /* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ #define WP_STATUS_PAD 36 +/* The EC_IN_RW lives on SCGPIO59 */ +#define EC_IN_RW_PAD 59 + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -43,3 +47,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !score_get_gpio(EC_IN_RW_PAD); +} diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index ef1acbdc59..8f887e8d0f 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -1,14 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "ec.h" #include #include #include #include -#include static void mainboard_init(struct device *dev) { @@ -54,7 +52,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; /* Install custom int15 handler for VGA OPROM */ if (CONFIG(VGA_ROM_RUN)) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 9fee4a5ddd..0073e09706 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -1,15 +1,15 @@ - config BOARD_GOOGLE_BASEBOARD_REEF def_bool n - select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DSAR_ENABLE select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT @@ -17,16 +17,30 @@ config BOARD_GOOGLE_BASEBOARD_REEF select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select GOOGLE_SMBIOS_MAINBOARD_VERSION - select USE_SAR select SAR_ENABLE - select DSAR_ENABLE + select SOC_INTEL_APOLLOLAKE + select SYSTEM_TYPE_LAPTOP + select USE_SAR + +config BOARD_GOOGLE_REEF + select BOARD_GOOGLE_BASEBOARD_REEF + +config BOARD_GOOGLE_PYRO + select BOARD_GOOGLE_BASEBOARD_REEF + +config BOARD_GOOGLE_SAND + select BOARD_GOOGLE_BASEBOARD_REEF + +config BOARD_GOOGLE_SNAPPY + select BOARD_GOOGLE_BASEBOARD_REEF + +config BOARD_GOOGLE_CORAL + select BOARD_GOOGLE_BASEBOARD_REEF if BOARD_GOOGLE_BASEBOARD_REEF -config BASEBOARD_REEF_LAPTOP - def_bool n - select SYSTEM_TYPE_LAPTOP +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y config DRIVER_TPM_I2C_BUS hex @@ -43,7 +57,7 @@ config TPM_TIS_ACPI_INTERRUPT config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE - select VBOOT_LID_SWITCH if BASEBOARD_REEF_LAPTOP + select VBOOT_LID_SWITCH config MAINBOARD_DIR default "google/reef" @@ -53,7 +67,6 @@ config VARIANT_DIR default "pyro" if BOARD_GOOGLE_PYRO default "sand" if BOARD_GOOGLE_SAND default "snappy" if BOARD_GOOGLE_SNAPPY - default "nasher" if BOARD_GOOGLE_NASHER default "coral" if BOARD_GOOGLE_CORAL config DEVICETREE @@ -68,7 +81,6 @@ config MAINBOARD_PART_NUMBER default "Pyro" if BOARD_GOOGLE_PYRO default "Sand" if BOARD_GOOGLE_SAND default "Snappy" if BOARD_GOOGLE_SNAPPY - default "Nasher" if BOARD_GOOGLE_NASHER default "Coral" if BOARD_GOOGLE_CORAL config MAINBOARD_FAMILY @@ -94,8 +106,4 @@ config PRERAM_CBMEM_CONSOLE_SIZE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS -# Override the default behavior, since the data.vbt is the same for all variants -config INTEL_GMA_VBT_FILE - default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" - endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index d880941a53..ee6f6ca000 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,30 +2,15 @@ comment "Reef" config BOARD_GOOGLE_REEF bool "-> Reef/Electro (Acer Chromebook Spin 11 R751T)" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP config BOARD_GOOGLE_PYRO bool "-> Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP config BOARD_GOOGLE_SAND bool "-> Sand (Acer Chromebook 15 CB515-1HT/1H)" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP config BOARD_GOOGLE_SNAPPY bool "-> Snappy (HP Chromebook x360 11 G1 EE)" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP - -config BOARD_GOOGLE_NASHER - bool "-> Nasher" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP config BOARD_GOOGLE_CORAL bool "-> Coral" - select BOARD_GOOGLE_BASEBOARD_REEF - select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 94d76b99e4..1d1c990d73 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include #include #include #include @@ -33,3 +35,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/reef/default.fmd b/src/mainboard/google/reef/default.fmd index ff8f8efc92..79a7736055 100644 --- a/src/mainboard/google/reef/default.fmd +++ b/src/mainboard/google/reef/default.fmd @@ -3,7 +3,7 @@ FLASH 16M { SI_BIOS@0x1000 0xf7e000 { IFWI@0x0 0x1ff000 # SMMSTORE requires 64k alignment - SMMSTORE@0xa5e000 0x40000 + SMMSTORE@0xa4f000 0x40000 UNIFIED_MRC_CACHE 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE 0x10000 diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index e0078805ee..8cae9592d7 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -125,7 +124,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index 3ca7d10c64..35ec6035ba 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 6604a70cfe..8263459789 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' @@ -367,6 +368,8 @@ static const struct pad_config early_gpio_table[] = { /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ }; const struct pad_config * __weak diff --git a/src/mainboard/google/reef/variants/coral/Makefile.inc b/src/mainboard/google/reef/variants/coral/Makefile.inc index e52d9598a6..440ec9c545 100644 --- a/src/mainboard/google/reef/variants/coral/Makefile.inc +++ b/src/mainboard/google/reef/variants/coral/Makefile.inc @@ -4,3 +4,11 @@ ramstage-y += mainboard.c ramstage-y += gpio.c smm-y += gpio.c + +$(call add_vbt_to_cbfs, vbt-astronaut.bin, astronaut-data.vbt) +$(call add_vbt_to_cbfs, vbt-babytiger.bin, babytiger-data.vbt) +$(call add_vbt_to_cbfs, vbt-babymega.bin, babymega-data.vbt) +$(call add_vbt_to_cbfs, vbt-epaulette.bin, epaulette-data.vbt) +$(call add_vbt_to_cbfs, vbt-nasher.bin, nasher-data.vbt) +$(call add_vbt_to_cbfs, vbt-rabbid_rugged.bin, rabbid_rugged-data.vbt) +$(call add_vbt_to_cbfs, vbt-santa.bin, santa-data.vbt) diff --git a/src/mainboard/google/reef/variants/coral/astronaut-data.vbt b/src/mainboard/google/reef/variants/coral/astronaut-data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..6b4109e0781605b532392f4327019efb4380a36a GIT binary patch literal 6656 zcmeHLU2GIp6h1T4{kt=>-A=2NrIyQ&Wm}+~7FbHHcD7qe7h1a8mRh4pf7nGD3oUKY zA_8M9NfU$F2Q_Gj))=F~mnQ0yG2(+tLX`GF4NsO3lS(8Z5u*>ldhX1$+aH=P2pXhk zbM86!+;hKs@43ITtD7sEXk|lvOH=($YEcwaAld6MolBLW`o`9(KvST#vbH|BgPwbmzf+9kJdriXbX_)8dVV8#Yo}vbjjzP*kE8Z^DwYVt?7DEi$Rv z8mzAihiU^&A?$d41FZ@*1{xc;)>YO%MZ*pCHKEE-)7C1P%oswjyXR1E=d*kJsV|sM zOR$~w2CmU%8tm@vDWrj}F519+`e;L}FV_2fELtcN26P6TX&eA&gLDlzxKRS&1V{tW z0O*W%=F511-^B4)BhLx;>`5iih%RE4*dr>qoa=T0{GsjZPD`~JaI>&M=!@uJt;Bc?Mi0vE0W`bjc!{Joe zIDjld7cKO_H&{5$duWQUzV2J$lGN0Ez= zw;%_R>yV#BZb!BsgzE`jXH$TrbC%37C3w={wS3S|S@u(w-E|cw8;Mv_w4`B7AxR`0 z4!D{4J{uAV=i{sg8Y1AZxhe~(#*(#$6ojyqZ$imp)nern30E6td1GnZtCXB$3)!SZ z;(phpOxTXwTX2>S<``qy1(0}G7GMBK25vHo6lro%8iuTQ!0t7R9OaWfv*mwT;$?@! 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The order largely follows the 'GPIO Muxing' @@ -368,6 +369,8 @@ static const struct pad_config early_gpio_table[] = { /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ + + PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index 683624ca65..1e7ebba6b3 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -21,6 +21,13 @@ enum { SKU_14_EPAULETTE = 14, SKU_15_EPAULETTE = 15, SKU_16_EPAULETTE = 16, + SKU_28_RABBID_RUGGED = 28, + SKU_30_BABYTIGER = 30, + SKU_31_RABBID = 31, + SKU_32_RABBID = 32, + SKU_33_BABYTIGER = 33, + SKU_52_BABYMEGA = 52, + SKU_53_BABYMEGA = 53, SKU_61_ASTRONAUT = 61, SKU_62_ASTRONAUT = 62, SKU_160_NASHER = 160, @@ -51,6 +58,23 @@ void variant_nhlt_oem_overrides(const char **oem_id, *oem_revision = variant_board_sku(); } +#define DW_I2C_SPEED_CONFIG(speedval, lcnt, hcnt, hold) \ + { \ + .speed = I2C_SPEED_ ## speedval, \ + .scl_lcnt = (lcnt), \ + .scl_hcnt = (hcnt), \ + .sda_hold = (hold), \ + } + +static const struct dw_i2c_speed_config +rabbid_i2c_speed_config = DW_I2C_SPEED_CONFIG(FAST, 210, 107, 47); + +static const struct dw_i2c_speed_config +babymega_i2c_speed_config = DW_I2C_SPEED_CONFIG(FAST, 210, 107, 47); + +static const struct dw_i2c_speed_config +babytiger_i2c_speed_config = DW_I2C_SPEED_CONFIG(FAST, 210, 107, 47); + void mainboard_devtree_update(struct device *dev) { /* Override dev tree settings per board */ @@ -60,8 +84,8 @@ void mainboard_devtree_update(struct device *dev) sku_id = variant_board_sku(); switch (sku_id) { - case SKU_0_ASTRONAUT: - case SKU_1_ASTRONAUT: + case SKU_0_ASTRONAUT: + case SKU_1_ASTRONAUT: cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; cfg->usb2eye[1].Usb20PerPortTxiSet = 2; break; @@ -77,35 +101,53 @@ void mainboard_devtree_update(struct device *dev) cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; cfg->usb2eye[1].Usb20PerPortTxiSet = 2; break; - case SKU_61_ASTRONAUT: - case SKU_62_ASTRONAUT: + case SKU_28_RABBID_RUGGED: + case SKU_31_RABBID: + case SKU_32_RABBID: + cfg->common_soc_config.i2c[3].speed_config[0] = rabbid_i2c_speed_config; + cfg->common_soc_config.i2c[4].speed_config[0] = rabbid_i2c_speed_config; + break; + case SKU_30_BABYTIGER: + case SKU_33_BABYTIGER: + cfg->common_soc_config.i2c[3].speed_config[0] = babytiger_i2c_speed_config; + cfg->common_soc_config.i2c[4].speed_config[0] = babytiger_i2c_speed_config; + break; + case SKU_52_BABYMEGA: + case SKU_53_BABYMEGA: + cfg->common_soc_config.i2c[4].speed_config[0] = babymega_i2c_speed_config; + break; + case SKU_61_ASTRONAUT: + case SKU_62_ASTRONAUT: cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; cfg->usb2eye[1].Usb20PerPortTxiSet = 5; - break; + break; default: break; } } - const char *mainboard_vbt_filename(void) { int sku_id = variant_board_sku(); - switch (sku_id) { - case SKU_0_ASTRONAUT: - case SKU_1_ASTRONAUT: + case SKU_0_ASTRONAUT: + case SKU_1_ASTRONAUT: return "vbt-astronaut.bin"; - break; case SKU_2_SANTA: case SKU_3_SANTA: return "vbt-santa.bin"; - break; case SKU_13_EPAULETTE: case SKU_14_EPAULETTE: case SKU_15_EPAULETTE: case SKU_16_EPAULETTE: return "vbt-epaulette.bin"; - break; + case SKU_28_RABBID_RUGGED: + return "vbt-rabbid_rugged.bin"; + case SKU_30_BABYTIGER: + case SKU_33_BABYTIGER: + return "vbt-babytiger.bin"; + case SKU_52_BABYMEGA: + case SKU_53_BABYMEGA: + return "vbt-babymega.bin"; case SKU_160_NASHER: case SKU_161_NASHER: case SKU_162_NASHER: @@ -114,10 +156,8 @@ const char *mainboard_vbt_filename(void) case SKU_165_NASHER360: case SKU_166_NASHER360: return "vbt-nasher.bin"; - break; default: return "vbt.bin"; - break; } } diff --git a/src/mainboard/google/reef/variants/coral/nasher-data.vbt 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z!U)l&pamdL%^vZa2-*H2!FZn`0?s%?D97j8{G(6{;CKX7P3_H`?gLvYNYbFqn-anx zjd(qpX9fZnx7`N92StOE5pSN>dOX<&E^apvH2YWzeWokRVkC7(Dx>g~>!ZD6 zs}P}p)dD~STikf3NTasl6xPF=`J>~J;gxFmjV03v0*FkPGw|!ci6PwKnlun(6TwDP7{w(ojE3nFRZ@ejmJtUbj{DJwWT~+p*dm{QRr6(f_WsiK zTI>4cTnLbEAmAZpUwB{SYtXJkX1m9e!D^X(!1EMIs;ddNg**1ex_5N!jr|WYY*4dl z?TcXFb{gO0C$03Nkkn_||APMU9OCEDx(DD`4R$MpFZG=ehA6D#UWbc9;TXWkG~E;G z26hUt{e+8lqaTwvE+k`5%?>->Diz4=yBQzw$m7;W8>^c>w7endq{Rr_ z#}U}fb2{LIM8~hNB Arcada" - select BOARD_GOOGLE_BASEBOARD_SARIEN + bool "-> Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)" config BOARD_GOOGLE_SARIEN - bool "-> Sarien" - select BOARD_GOOGLE_BASEBOARD_SARIEN + bool "-> Sarien (Dell Latitude 5400 Chromebook Enterprise)" diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index f49b63964f..180a98ebab 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include #include #include +#include #include #include #include @@ -27,24 +28,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; + return gpio_get(GPP_E15); +} - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; +static bool raw_get_recovery_mode_switch(void) +{ + return !gpio_get(GPP_E8); } void mainboard_chromeos_acpi_generate(void) @@ -57,11 +48,6 @@ void mainboard_chromeos_acpi_generate(void) chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; @@ -87,7 +73,7 @@ int get_recovery_mode_switch(void) state = REC_MODE_REQUESTED; /* Read state from the GPIO controlled by servo. */ - if (cros_get_gpio_value(CROS_GPIO_REC)) + if (raw_get_recovery_mode_switch()) state = REC_MODE_REQUESTED; /* Store the state in case this is called again in verstage. */ @@ -107,3 +93,10 @@ void mainboard_prepare_cr50_reset(void) if (ENV_RAMSTAGE) pmc_soc_set_afterg3_en(true); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/sarien/data.vbt b/src/mainboard/google/sarien/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..f9c498e45c3e31f24dac26e43a3f8e653826ba8c GIT binary patch literal 6144 zcmeHKeQZ-z6hE)8uOGMXwXbgkx{CAg5$Gn{UIz?ZMtohnv9dzjbu3#nSqH7USlHNx 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b/src/mainboard/google/sarien/ramstage.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include #include -#include #if CONFIG(GENERATE_SMBIOS_TABLES) /* mainboard silk screen shows DIMM-A and DIMM-B */ @@ -46,12 +44,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused)); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0bbc25fab6..76f4fd3ecb 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -342,7 +342,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index a447240522..059744064d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -363,7 +363,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig new file mode 100644 index 0000000000..c5b81f79c9 --- /dev/null +++ b/src/mainboard/google/skyrim/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_SKYRIM + def_bool n + +if BOARD_GOOGLE_BASEBOARD_SKYRIM + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config AMD_FWM_POSITION_INDEX + int + default 3 + help + TODO: might need to be adapted for better placement of files in cbfs + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select AMD_SOC_CONSOLE_UART + select BOARD_ROMSIZE_KB_16384 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select FW_CONFIG + select MAINBOARD_HAS_CHROMEOS + select SOC_AMD_SABRINA + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + +config MAINBOARD_DIR + default "google/skyrim" + +config MAINBOARD_FAMILY + string + default "Google_Skyrim" + +config MAINBOARD_PART_NUMBER + default "Skyrim" if BOARD_GOOGLE_SKYRIM + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VARIANT_DIR + string + default "skyrim" if BOARD_GOOGLE_SKYRIM + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +endif # BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name new file mode 100644 index 0000000000..a36235c7be --- /dev/null +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -0,0 +1,5 @@ +comment "Skyrim" + +config BOARD_GOOGLE_SKYRIM + bool "-> Skyrim" + select BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc new file mode 100644 index 0000000000..94708acbf6 --- /dev/null +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += port_descriptors.c + +ramstage-y += mainboard.c +ramstage-y += ec.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/skyrim/board_info.txt b/src/mainboard/google/skyrim/board_info.txt new file mode 100644 index 0000000000..9588901dd3 --- /dev/null +++ b/src/mainboard/google/skyrim/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Skyrim +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c new file mode 100644 index 0000000000..d1000d30b9 --- /dev/null +++ b/src/mainboard/google/skyrim/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + /* TODO: Perform mainboard initialization */ +} + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + variant_bootblock_gpio_table(&gpios, &num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c new file mode 100644 index 0000000000..67107d1b41 --- /dev/null +++ b/src/mainboard/google/skyrim/chromeos.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd new file mode 100644 index 0000000000..a6dbc2c2ae --- /dev/null +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -0,0 +1,34 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE(PRESERVE) 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/skyrim/dsdt.asl b/src/mainboard/google/skyrim/dsdt.asl new file mode 100644 index 0000000000..3aec6baf3d --- /dev/null +++ b/src/mainboard/google/skyrim/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } + +} diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c new file mode 100644 index 0000000000..bc29833713 --- /dev/null +++ b/src/mainboard/google/skyrim/ec.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct sci_source espi_sci_sources[] = { + { + .scimap = SMITYPE_ESPI_SYS, + .gpe = GEVENT_3, + .direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */ + .level = SMI_SCI_EDG, /* enum smi_sci_dir */ + } +}; + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + + /* Configure eSPI SCI events */ + gpe_configure_sci(espi_sci_sources, ARRAY_SIZE(espi_sci_sources)); +} diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c new file mode 100644 index 0000000000..0558dbaf31 --- /dev/null +++ b/src/mainboard/google/skyrim/mainboard.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + variant_base_gpio_table(&base_gpios, &base_num_gpios); + variant_override_gpio_table(&override_gpios, &override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, + override_gpios, override_num_gpios); +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c new file mode 100644 index 0000000000..56bd9f32bf --- /dev/null +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + /* TODO: Initialize DXIO and DDI descriptors */ +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..7c092e44c2 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..c2584e6587 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/sabrina + device domain 0 on + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 alias chrome_ec on end + end + end + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref xhci_0 on + end + device ref xhci_1 on + end + end + end # domain + device ref uart_0 on end # UART0 +end # chip soc/amd/sabrina diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c new file mode 100644 index 0000000000..6e079d0380 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* GPIO configuration in ramstage*/ +static const struct soc_amd_gpio base_gpio_table[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* SOC_PEN_DETECT_ODL */ + PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3), + /* EN_PWR_FP */ + PAD_GPO(GPIO_4, HIGH), + /* EN_PP3300_TCHPAD */ + PAD_GPO(GPIO_5, HIGH), + /* SSD_AUX_RESET_L */ + PAD_GPO(GPIO_6, HIGH), + /* WLAN_AUX_RST_L */ + PAD_GPO(GPIO_7, HIGH), + /* EN_PWR_WWAN_X */ + PAD_GPO(GPIO_8, HIGH), + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_9, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_10, LOW), + /* EC_SOC_WAKE_ODL */ + PAD_SCI(GPIO_11, PULL_NONE, EDGE_LOW), + /* SOC_FP_RST_L */ + PAD_GPO(GPIO_12, LOW), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* SOC_SAR_INT_L */ + PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), + /* GSC_SOC_INT_L */ + PAD_GPI(GPIO_18, PULL_NONE), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* WLAN_DISABLE */ + PAD_GPO(GPIO_21, LOW), + /* ESPI_ALERT_D1 */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* SOC_FP_INT_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_27, HIGH), + /* GPIO_28: Not available */ + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_29, HIGH), + /* SOC_DISABLE_DISP_BL */ + PAD_GPO(GPIO_30, HIGH), + /* Unused */ + PAD_NC(GPIO_31), + /* LPC_RST_L */ + PAD_GPO(GPIO_32, LOW), + /* GPIO_33 - GPIO_39: Not available */ + /* SOC_TCHPAD_INT_ODL */ + PAD_SCI(GPIO_40, PULL_NONE, EDGE_LOW), + /* GPIO_41: Not available */ + /* WWAN_RST_L */ + PAD_GPO(GPIO_42, HIGH), + /* GPIO_43 - GPIO_66: Not available */ + /* GPIO_67 */ + PAD_GPI(GPIO_67, PULL_NONE), + /* SPI1_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* SPI1_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_74, SPI1_CS1_L, PULL_NONE), + /* TCHSCR_REPORT_EN */ + PAD_GPO(GPIO_76, LOW), + /* SPI1_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* EN_PP3300_CAM */ + PAD_GPO(GPIO_78, HIGH), + /* SPI1_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* SPI1_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* EC_SOC_INT_ODL */ + PAD_GPI(GPIO_84, PULL_NONE), + /* RAM_ID_1 / DEV_BEEP_DATA */ + PAD_GPI(GPIO_85, PULL_NONE), + /* RAM_ID_2 / DEV_BEEP_LRCLK */ + PAD_GPI(GPIO_89, PULL_NONE), + /* HP_INT_ODL */ + PAD_GPI(GPIO_90, PULL_NONE), + /* RAM_ID_3 / DEV_BEEP_BCLK */ + PAD_GPI(GPIO_91, PULL_NONE), + /* CLK_REQ0_L / SSD */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L / SD */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L / WLAN */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* SOC_FPMCU_BOOT0 */ + PAD_GPO(GPIO_130, LOW), + /* TCHSCR_INT_ODL */ + PAD_GPI(GPIO_131, PULL_NONE), + /* TCHSCR_RESET_L */ + PAD_GPO(GPIO_136, LOW), + /* SOC_BIOS_WP_L */ + PAD_GPI(GPIO_138, PULL_NONE), + /* EN_SPKR */ + PAD_GPO(GPIO_139, HIGH), + /* RAM_ID_0 / DEV_BEEP_EN */ + PAD_GPI(GPIO_144, PULL_NONE), + /* UART1_TXD / FP */ + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + /* UART0_RXD / DBG */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART1_RXD / FP*/ + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + /* UART0_TXD / DBG */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* I2C0_SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0_SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1_SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1_SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), +}; + +/* GPIO configuration for sleep */ +static const struct soc_amd_gpio sleep_gpio_table[] = { + /* TODO: Fill sleep gpio configuration */ +}; + +/* Early GPIO configuration in bootblock */ +static const struct soc_amd_gpio bootblock_gpio_table[] = { + /* TODO: Fill bootblock gpio configuration */ +}; + +__weak void variant_base_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(base_gpio_table); + *gpio = base_gpio_table; +} + +__weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = 0; + *gpio = NULL; +} + +__weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(bootblock_gpio_table); + *gpio = bootblock_gpio_table; +} + +__weak void variant_sleep_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(sleep_gpio_table); + *gpio = sleep_gpio_table; +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h new file mode 100644 index 0000000000..b94afac4bf --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/baseboard.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..d66d3cb775 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid, power button or mode change event */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Set GPI for SCI */ +#define EC_SCI_GPI GEVENT_3 /* eSPI system event -> GPE 3 */ + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GEVENT_5 /* AGPIO 11 -> GPE 5 */ + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt */ +#define EC_ENABLE_SYNC_IRQ_GPIO + +/* EC sync irq */ +#define EC_SYNC_IRQ GPIO_84 + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..dbbb85d19c --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_138 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..b83344894e --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include + +/* + * This function provides base GPIO configuration table. It is typically provided by + * baseboard using a weak implementation. If GPIO configuration for a variant differs + * significantly from the baseboard, then the variant can also provide a strong implementation + * of this function. + */ +void variant_base_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by variant_base_gpio_table(). + */ +void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +/* This function provides GPIO init in bootblock. */ +void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +/* This function provides GPIO settings before entering sleep. */ +void variant_sleep_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c new file mode 100644 index 0000000000..f5131e9461 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + + variant_sleep_gpio_table(&gpios, &num_gpios); + program_gpios(gpios, num_gpios); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/google/skyrim/variants/skyrim/include/variant/ec.h b/src/mainboard/google/skyrim/variants/skyrim/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb new file mode 100644 index 0000000000..4fb8baf086 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +fw_config + # TODO define when available +end + +chip soc/amd/sabrina + device domain 0 on + end # domain +end # chip soc/amd/sabrina diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index e8963f793a..0d0902ce9a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -1,26 +1,41 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY def_bool n - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select INTEL_LYNXPOINT_LP select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT - select INTEL_GMA_HAVE_VBT - select DRIVERS_I2C_RTD2132 if BOARD_GOOGLE_LEON - select HAVE_SPD_IN_CBFS + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config BOARD_GOOGLE_FALCO + select BOARD_GOOGLE_BASEBOARD_SLIPPY + +config BOARD_GOOGLE_LEON + select BOARD_GOOGLE_BASEBOARD_SLIPPY + select DRIVERS_I2C_RTD2132 + +config BOARD_GOOGLE_PEPPY + select BOARD_GOOGLE_BASEBOARD_SLIPPY + +config BOARD_GOOGLE_WOLF + select BOARD_GOOGLE_BASEBOARD_SLIPPY if BOARD_GOOGLE_BASEBOARD_SLIPPY +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/slippy/Kconfig.name b/src/mainboard/google/slippy/Kconfig.name index e81d0568fe..3e0f81ede6 100644 --- a/src/mainboard/google/slippy/Kconfig.name +++ b/src/mainboard/google/slippy/Kconfig.name @@ -2,16 +2,12 @@ comment "Slippy" config BOARD_GOOGLE_FALCO bool "-> Falco (HP Chromebook 14)" - select BOARD_GOOGLE_BASEBOARD_SLIPPY config BOARD_GOOGLE_LEON bool "-> Leon (Toshiba Chromebook)" - select BOARD_GOOGLE_BASEBOARD_SLIPPY config BOARD_GOOGLE_PEPPY bool "-> Peppy (Acer C720/C720P Chromebook)" - select BOARD_GOOGLE_BASEBOARD_SLIPPY config BOARD_GOOGLE_WOLF bool "-> Wolf (Dell Chromebook 11)" - select BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl index 74e73a25c0..176b08dcd2 100644 --- a/src/mainboard/google/slippy/acpi/thermal.asl +++ b/src/mainboard/google/slippy/acpi/thermal.asl @@ -38,7 +38,7 @@ Scope (\_TZ) Multiply (Arg0, 10, Local0) // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -87,7 +87,7 @@ Scope (\_TZ) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin Multiply (Local0, 10, Local0) @@ -103,8 +103,7 @@ Scope (\_TZ) Store (CTOK (\TCRT), Local1) If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("CRITICAL TEMPERATURE: %o", Local0) // Wait 1 second for EC to re-poll Sleep (1000) @@ -112,8 +111,7 @@ Scope (\_TZ) // Re-read temperature from EC Store (TCHK (), Local0) - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 1198f4150e..64bc09aa5e 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 4fffd45b35..634e5637e3 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -4,7 +4,9 @@ #include #include #include +#include #include +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -18,15 +20,21 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - return get_gpio(58); + return get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !get_gpio(14); +} diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 90f28e7ec2..47f071c2a4 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "ec.h" #include "onboard.h" @@ -66,7 +65,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h index 6b7fdb281e..a1f30fda08 100644 --- a/src/mainboard/google/slippy/onboard.h +++ b/src/mainboard/google/slippy/onboard.h @@ -23,4 +23,7 @@ #define PEPPY_BOARD_VERSION_PROTO 0 #define PEPPY_BOARD_VERSION_EVT 1 +/* Write protect is active high */ +#define GPIO_SPI_WP 58 + #endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 9ab76292fb..b391d81b31 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 6911c257b0..50a1b7305c 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index babf9a0a37..e79309059b 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -18,7 +18,7 @@ Scope (\_SB.PCI0.I2C0) AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Level, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } @@ -60,7 +60,7 @@ Scope (\_SB.PCI0.I2C0) AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow) + Interrupt (ResourceConsumer, Edge, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index efbbc7f8c7..32fdd97e94 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 4c67afefcf..7c1bff007b 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 13a69bc0ed..d74df8267e 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -19,3 +19,9 @@ int get_write_protect_state(void) { return !gpio_get(WRITE_PROTECT_L); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(EC_IN_RW); +} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 21cf94f978..4ecc228385 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -9,7 +10,6 @@ #include #include #include -#include #define DEV_SW 15 #define REC_SW 16 @@ -128,3 +128,10 @@ int get_write_protect_state(void) { return !read_gpio(WP_SW); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 69cfdcccdd..b2cd2956b3 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -1,25 +1,28 @@ if BOARD_GOOGLE_STOUT +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SOUTHBRIDGE_INTEL_C216 - select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select INTEL_INT15 - select MAINBOARD_HAS_LIBGFXINIT + select EC_QUANTA_IT8518 select GFX_GMA_PANEL_1_ON_LVDS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT select HAVE_IFD_BIN select HAVE_ME_BIN + select HAVE_OPTION_TABLE + select INTEL_INT15 + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SANDYBRIDGE_VBOOT_IN_ROMSTAGE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 07e6319897..0d5f06fd17 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include "onboard.h" diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 07fdee3281..964217e8f1 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -8,9 +8,11 @@ #include #include +#include #include #include "ec.h" #include +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -34,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - return !get_gpio(7); + return !get_gpio(GPIO_SPI_WP); } int get_lid_switch(void) @@ -75,8 +77,7 @@ int get_recovery_mode_switch(void) static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index ad700cee29..b38adaf148 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "gen3_dec" = "0x0001C1611" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 6b28e00ded..b33f57c205 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include -#include #include #include #include @@ -94,11 +94,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 05ff973a47..2584166cf2 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 7f4e29d2e8..ae68a78dcb 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "ec.h" #include "onboard.h" @@ -42,7 +41,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index a31dffd4cd..2f9b92d14b 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -11,4 +11,7 @@ #define XHCI_PREBOOT 0 // No PreOS boot support #define XHCI_STREAMS 1 // Sure, lets have streams +/* Write protect is active low */ +#define GPIO_SPI_WP 7 + #endif diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index 208cafc4da..72457433fa 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -15,7 +15,7 @@ #define GPIO_AMP_ENABLE GPIO(23) /* Display specific GPIOS */ -#define GPIO_BACKLIGHT_ENABLE ((CONFIG(TROGDOR_HAS_MIPI_PANEL)) ? GPIO(85) : GPIO(12)) +#define GPIO_BACKLIGHT_ENABLE GPIO(12) /* MIPI panel specific GPIOs. Only for mipi_panel-enabled devices (e.g. Mrbland). */ #if CONFIG(TROGDOR_HAS_MIPI_PANEL) @@ -23,6 +23,7 @@ #define GPIO_AVDD_LCD_ENABLE GPIO(88) #define GPIO_AVEE_LCD_ENABLE GPIO(21) #define GPIO_VDD_RESET_1V8 GPIO(87) +#define GPIO_TP_EN (CONFIG(BOARD_GOOGLE_QUACKINGSTICK) ? GPIO(67) : GPIO(85)) #define GPIO_EDP_BRIDGE_ENABLE dead_code_t(gpio_t) #define GPIO_EN_PP3300_DX_EDP dead_code_t(gpio_t) #define GPIO_PS8640_EDP_BRIDGE_PD_L dead_code_t(gpio_t) @@ -33,6 +34,7 @@ #define GPIO_AVDD_LCD_ENABLE dead_code_t(gpio_t) #define GPIO_AVEE_LCD_ENABLE dead_code_t(gpio_t) #define GPIO_VDD_RESET_1V8 dead_code_t(gpio_t) +#define GPIO_TP_EN dead_code_t(gpio_t) #define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) #define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : \ (CONFIG(BOARD_GOOGLE_TROGDOR) && board_id() == 1 ? GPIO(30) : \ diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 9006000191..11b38b513d 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -22,6 +22,8 @@ void setup_chromeos_gpios(void) } else { gpio_output(GPIO_EN_PP3300_DX_EDP, 0); gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0); + gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 0); + gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0); } if (CONFIG(TROGDOR_HAS_FINGERPRINT)) { @@ -55,3 +57,9 @@ int tis_plat_irq_status(void) { return gpio_irq_status(GPIO_H1_AP_INT); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. This is active low. */ + return !!gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index f007f45dd1..99c325e28a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -18,9 +18,8 @@ #include #include #include -#include -#include - +#include +#include #include "board.h" #include @@ -83,7 +82,9 @@ static bool is_ps8640_bridge(void) */ return (CONFIG(BOARD_GOOGLE_HOMESTAR) && board_id() >= 4 && board_id() != 19 && board_id() != 23) || - (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() >= 9); + (CONFIG(BOARD_GOOGLE_LAZOR) && board_id() >= 9) || + (CONFIG(BOARD_GOOGLE_KINGOFTOWN) && board_id() >= 1) || + (CONFIG(BOARD_GOOGLE_PAZQUEL) && (sku_id() & 0x4)); } static void power_on_sn65dsi86_bridge(void) @@ -105,12 +106,18 @@ static void power_on_ps8640_bridge(void) gpio_output(GPIO_EN_PP3300_DX_EDP, 1); gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 1); - gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1); - gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0); /* - * According to ps8640 app note v0.6, wait for 2ms ("t1") after - * VDD33 goes high and then deassert RST. + * According to ps8640 v1.4 spec, and the raise time of vdd33 is a bit + * long, so wait for 4ms after VDD33 goes high and then deassert PD. + */ + mdelay(4); + + gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1); + + /* + * According to ps8640 app note v0.6, wait for 2ms after VDD33 goes + * high and then deassert RST. */ mdelay(2); @@ -129,14 +136,21 @@ static void configure_mipi_panel(void) gpio_output(GPIO_VDD_RESET_1V8, 1); mdelay(15); /* - * In mrbland, BOE panel_id = 3, it needs 15ms delay and - * do reset again according to spec(See in b/197300876). + * In mrbland, BOE panel_id = 3(EVT) or 4(DVT and after), + * it needs 15ms delay and do reset again according to spec + * (See in b/197300876). */ - if (CONFIG(BOARD_GOOGLE_MRBLAND) && (panel_id == 3)) { + if (CONFIG(BOARD_GOOGLE_MRBLAND) && ((panel_id == 3) || (panel_id == 4))) { gpio_output(GPIO_VDD_RESET_1V8, 0); mdelay(5); gpio_output(GPIO_VDD_RESET_1V8, 1); } + /* + * In mipi panel, TP_EN(GPIO 85) need pull up before + * GPIO_BACKLIGHT_ENABLE(GPIO12) up. + */ + if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) + gpio_output(GPIO_TP_EN, 1); } static struct panel_serializable_data *get_mipi_panel(enum lb_fb_orientation *orientation) @@ -147,6 +161,7 @@ static struct panel_serializable_data *get_mipi_panel(enum lb_fb_orientation *or if (CONFIG(BOARD_GOOGLE_MRBLAND)) { switch (panel_id) { case 3: + case 4: cbfs_filename = "panel-BOE_TV101WUM_N53"; *orientation = LB_FB_ORIENTATION_LEFT_UP; break; diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c index e110460a1b..01bd530dd8 100644 --- a/src/mainboard/google/trogdor/romstage.c +++ b/src/mainboard/google/trogdor/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index b99df04c14..9374dc4d4a 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include -#include #include "board.h" @@ -56,3 +56,9 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_ECINRW); +} diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index b270466a1c..7d17bcc2c7 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "board.h" diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 788f3da709..35ddf85990 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "board.h" diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index a3ba7529ba..c4cd6c64c3 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include "board.h" @@ -34,3 +34,10 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 25672498d9..3df0c492aa 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "board.h" diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 5095ef93fb..bac2acbefb 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 95158bf9ee..f1eb1c3d27 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include #include "board.h" @@ -43,3 +43,10 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 9a9ce79e35..faf41fa48e 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 2c2f9d749b..acea7a095d 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "board.h" diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0c77a79d57..eb8f17653a 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -6,48 +6,135 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_SX9310 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC - select DRIVERS_INTEL_USB4_RETIMER - select DRIVERS_I2C_MAX98373 select DRIVERS_INTEL_SOUNDWIRE - select DRIVERS_SPI_ACPI + select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 + select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_SKUID select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_I2C_TPM_CR50 if BOARD_GOOGLE_VOLTEER2_TI50 + select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE - select HAVE_SPD_IN_CBFS + +config BOARD_GOOGLE_DELBIN + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_ELDRID + select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_HALVOR + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + +config BOARD_GOOGLE_LINDAR + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select CHROMEOS_DSM_CALIB if CHROMEOS + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_I2C_RT1011 + select INTEL_CAR_NEM + +config BOARD_GOOGLE_MALEFOR + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + +config BOARD_GOOGLE_TERRADOR + select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_TODOR + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + +config BOARD_GOOGLE_TRONDO + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + +config BOARD_GOOGLE_VOLTEER + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_CAR_NEM + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOLTEER2 + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVER_I2C_TPM_ACPI + select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOLTEER2_TI50 + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVER_I2C_TPM_ACPI + select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOXEL + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config BOARD_GOOGLE_ELEMI + select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOEMA + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_DROBIT + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config BOARD_GOOGLE_COPANO + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config BOARD_GOOGLE_COLLIS + select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOLET + select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_CHRONICLER + select BOARD_GOOGLE_BASEBOARD_VOLTEER if BOARD_GOOGLE_BASEBOARD_VOLTEER +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config CHROMEOS select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES - select GBB_FLAG_FORCE_DEV_SWITCH_ON - select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_ALTFW + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE - select VBOOT_LID_SWITCH select VBOOT_EARLY_EC_SYNC + select VBOOT_LID_SWITCH config CHROMEOS_WIFI_SAR bool "Enable SAR options for Chrome OS build" diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 295675a42f..d868e52578 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,104 +1,59 @@ comment "Volteer" config BOARD_GOOGLE_DELBIN - bool "-> Delbin" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select DRIVERS_GENESYSLOGIC_GL9755 + bool "-> Delbin (ASUS Chromebook Flip CX5)" config BOARD_GOOGLE_ELDRID bool "-> Eldrid" - select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_HALVOR bool "-> Halvor" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM config BOARD_GOOGLE_LINDAR bool "-> Lindar" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM - select CHROMEOS_DSM_CALIB if CHROMEOS - select DRIVERS_I2C_RT1011 - select DRIVERS_GENERIC_BAYHUB_LV2 config BOARD_GOOGLE_MALEFOR bool "-> Malefor" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM config BOARD_GOOGLE_TERRADOR bool "-> Terrador" - select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_TODOR bool "-> Todor" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM config BOARD_GOOGLE_TRONDO bool "-> Trondo" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_CAR_NEM config BOARD_GOOGLE_VOLTEER bool "-> Volteer" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA - select INTEL_CAR_NEM - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_VOLTEER2 bool "-> Volteer2" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVER_I2C_TPM_ACPI - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES # Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board config BOARD_GOOGLE_VOLTEER2_TI50 bool "-> Volteer2_Ti50" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA - select DRIVERS_GENESYSLOGIC_GL9755 - select DRIVER_I2C_TPM_ACPI - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_VOXEL - bool "-> Voxel" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + bool "-> Voxel (Acer Chromebook Spin 713 (CP713-3W))" config BOARD_GOOGLE_ELEMI - bool "-> Elemi" - select BOARD_GOOGLE_BASEBOARD_VOLTEER + bool "-> Elemi (HP Pro c640 G2 Chromebook)" config BOARD_GOOGLE_VOEMA bool "-> Voema" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select VARIANT_HAS_MIPI_CAMERA config BOARD_GOOGLE_DROBIT - bool "-> Drobit" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select DRIVERS_GENESYSLOGIC_GL9755 - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + bool "-> Drobit (ASUS Chromebook CX9400)" config BOARD_GOOGLE_COPANO - bool "-> Copano" - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + bool "-> Copano (ASUS Chromebook Flip CX5400)" config BOARD_GOOGLE_COLLIS bool "-> Collis" - select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_VOLET bool "-> Volet" - select BOARD_GOOGLE_BASEBOARD_VOLTEER config BOARD_GOOGLE_CHRONICLER bool "-> Chronicler" - select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index abd50c57ba..9b8e2f5296 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -32,3 +34,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 9f8e646ae1..95b9ce755a 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include @@ -14,7 +13,6 @@ #include #include #include -#include #include #include @@ -78,7 +76,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->get_smbios_strings = mainboard_smbios_strings; variant_ramstage_init(); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b4c4f6a41f..5e5a5863dd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -87,12 +87,8 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 @@ -121,11 +117,13 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PcieRpSlotImplemented[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "0" + register "PcieRpSlotImplemented[10]" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" @@ -139,6 +137,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[6]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" @@ -147,8 +146,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA - register "SataEnable" = "1" - register "SataMode" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" @@ -297,8 +294,6 @@ chip soc/intel/tigerlake .tdp_pl4 = 83, }" - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90 register "CnviBtCore" = "true" diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 756d870a11..05c757ce97 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ @@ -431,6 +432,9 @@ static const struct pad_config early_gpio_table[] = { /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ PAD_CFG_GPO(GPP_F11, 1, DEEP), + + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), }; const struct pad_config *__weak variant_base_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h index 5ae32faa54..6eca8bc5c2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -56,13 +56,13 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -/* Enable Tablet switch */ -#define EC_ENABLE_TBMC_DEVICE - #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ diff --git a/src/mainboard/google/volteer/variants/chronicler/gpio.c b/src/mainboard/google/volteer/variants/chronicler/gpio.c index 1ffc875333..215b760804 100644 --- a/src/mainboard/google/volteer/variants/chronicler/gpio.c +++ b/src/mainboard/google/volteer/variants/chronicler/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/google/volteer/variants/chronicler/memory.c b/src/mainboard/google/volteer/variants/chronicler/memory.c index 8ec6996d11..8c67a2d059 100644 --- a/src/mainboard/google/volteer/variants/chronicler/memory.c +++ b/src/mainboard/google/volteer/variants/chronicler/memory.c @@ -24,3 +24,9 @@ int variant_memory_sku(void) return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } + +void memcfg_variant_init(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + mem_cfg->DdrMemoryDown = 1; +} diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb index 4b9f0952a9..b69990c24a 100644 --- a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -231,6 +231,21 @@ chip soc/intel/tigerlake register "has_power_resource" = "1" device i2c 34 on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end end device ref i2c5 on chip drivers/i2c/generic @@ -264,14 +279,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/collis/Makefile.inc b/src/mainboard/google/volteer/variants/collis/Makefile.inc index 343c7dbb95..2af91aab63 100644 --- a/src/mainboard/google/volteer/variants/collis/Makefile.inc +++ b/src/mainboard/google/volteer/variants/collis/Makefile.inc @@ -5,3 +5,5 @@ romstage-y += memory.c bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/collis/gpio.c b/src/mainboard/google/volteer/variants/collis/gpio.c index 03bd91ef48..86919b90a2 100644 --- a/src/mainboard/google/volteer/variants/collis/gpio.c +++ b/src/mainboard/google/volteer/variants/collis/gpio.c @@ -204,6 +204,9 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb index 2fe5001125..02eed21e4d 100644 --- a/src/mainboard/google/volteer/variants/collis/overridetree.cb +++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake # BitMask where bits [3:0] are Controller 0 Channel [3:0] and # bits [7:4] are Controller 1 Channel [3:0]. @@ -93,7 +100,7 @@ chip soc/intel/tigerlake end device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variants.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" @@ -102,8 +109,7 @@ chip soc/intel/tigerlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on - end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" @@ -205,15 +211,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/collis/variant.c b/src/mainboard/google/volteer/variants/collis/variant.c new file mode 100644 index 0000000000..cdb165d523 --- /dev/null +++ b/src/mainboard/google/volteer/variants/collis/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) + config->hid = "RTL5682"; + else + config->hid = "10EC5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} diff --git a/src/mainboard/google/volteer/variants/copano/Makefile.inc b/src/mainboard/google/volteer/variants/copano/Makefile.inc index 343c7dbb95..2af91aab63 100644 --- a/src/mainboard/google/volteer/variants/copano/Makefile.inc +++ b/src/mainboard/google/volteer/variants/copano/Makefile.inc @@ -5,3 +5,5 @@ romstage-y += memory.c bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/copano/gpio.c b/src/mainboard/google/volteer/variants/copano/gpio.c index bec58e53e2..933aebb938 100644 --- a/src/mainboard/google/volteer/variants/copano/gpio.c +++ b/src/mainboard/google/volteer/variants/copano/gpio.c @@ -220,6 +220,9 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/copano/overridetree.cb b/src/mainboard/google/volteer/variants/copano/overridetree.cb index 6ea6fd5896..150db08367 100644 --- a/src/mainboard/google/volteer/variants/copano/overridetree.cb +++ b/src/mainboard/google/volteer/variants/copano/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake # BitMask where bits [3:0] are Controller 0 Channel [3:0] and # bits [7:4] are Controller 1 Channel [3:0]. @@ -117,7 +124,7 @@ chip soc/intel/tigerlake device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variant.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" @@ -126,8 +133,7 @@ chip soc/intel/tigerlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on - end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" @@ -230,15 +236,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/copano/variant.c b/src/mainboard/google/volteer/variants/copano/variant.c new file mode 100644 index 0000000000..cdb165d523 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) + config->hid = "RTL5682"; + else + config->hid = "10EC5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} diff --git a/src/mainboard/google/volteer/variants/delbin/Makefile.inc b/src/mainboard/google/volteer/variants/delbin/Makefile.inc index 343c7dbb95..2af91aab63 100644 --- a/src/mainboard/google/volteer/variants/delbin/Makefile.inc +++ b/src/mainboard/google/volteer/variants/delbin/Makefile.inc @@ -5,3 +5,5 @@ romstage-y += memory.c bootblock-y += gpio.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index a36ad1af9d..76de7c6171 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" @@ -129,7 +136,7 @@ chip soc/intel/tigerlake end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variant.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" @@ -138,7 +145,7 @@ chip soc/intel/tigerlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" @@ -211,15 +218,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/delbin/variant.c b/src/mainboard/google/volteer/variants/delbin/variant.c new file mode 100644 index 0000000000..cdb165d523 --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) + config->hid = "RTL5682"; + else + config->hid = "10EC5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} diff --git a/src/mainboard/google/volteer/variants/drobit/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/Makefile.inc index 3454eec965..4919fcd4e1 100644 --- a/src/mainboard/google/volteer/variants/drobit/Makefile.inc +++ b/src/mainboard/google/volteer/variants/drobit/Makefile.inc @@ -6,3 +6,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += ramstage.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 14a5ecf312..08b95f85a6 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 43 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_ALC5682 1 + option AUDIO_CODEC_ALC5682I_VS 2 + end +end chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" @@ -124,7 +131,7 @@ chip soc/intel/tigerlake device ref i2c0 on chip drivers/i2c/generic - register "hid" = ""10EC5682"" + # register "hid" is set in variant.c because of FW_CONFIG register "name" = ""RT58"" register "desc" = ""Headset Codec"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" @@ -133,7 +140,7 @@ chip soc/intel/tigerlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a alias audio_codec on end end chip drivers/i2c/max98373 register "vmon_slot_no" = "0" @@ -209,15 +216,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/drobit/variant.c b/src/mainboard/google/volteer/variants/drobit/variant.c new file mode 100644 index 0000000000..cdb165d523 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static void audio_codec_update(void) +{ + struct device *codec = DEV_PTR(audio_codec); + struct drivers_i2c_generic_config *config; + + config = codec->chip_info; + if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) + config->hid = "RTL5682"; + else + config->hid = "10EC5682"; +} +void variant_devtree_update(void) +{ + audio_codec_update(); +} diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index f357f0da6f..93544182e0 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -211,14 +211,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 9ce349b277..22230ab25d 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -281,14 +281,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 7d6725a95b..994df04452 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -233,6 +233,9 @@ static const struct pad_config early_gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 9dfd56cf40..2eb482d86c 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -289,14 +289,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follows CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index 69760c13ff..0febca898f 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -221,6 +221,9 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 53b0c42bea..6d29818469 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -158,15 +158,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c index 5611ccabae..e699027320 100644 --- a/src/mainboard/google/volteer/variants/todor/gpio.c +++ b/src/mainboard/google/volteer/variants/todor/gpio.c @@ -231,6 +231,9 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index ece746bc81..eb61053258 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -147,15 +147,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c index 70b7f52340..4f3f799cff 100644 --- a/src/mainboard/google/volteer/variants/voema/gpio.c +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -219,6 +219,9 @@ static const struct pad_config early_gpio_table[] = { /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ PAD_CFG_GPI(GPP_E12, NONE, DEEP), + + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 082dfdf160..808127f86d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -15,6 +15,7 @@ chip soc/intel/tigerlake register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieRpSlotImplemented[6]" = "1" # Disable SD Card PCIE 8 register "PcieRpEnable[7]" = "0" @@ -115,13 +116,13 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "1" + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "2" + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb index 1d11063732..f4e22555d3 100644 --- a/src/mainboard/google/volteer/variants/volet/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb @@ -152,13 +152,13 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index f3b7549e82..9375af3e94 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -221,14 +221,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 7fe38a93d4..d024835aa0 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -288,14 +288,14 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2efc3ed556..4bca103584 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -244,15 +244,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "9" - register "usb3_port_number" = "1" + use usb2_port9 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index c9db2f4892..dfc87bf5d9 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -8,6 +8,9 @@ config BOARD_GOOGLE_BASEBOARD_DALBOZ if BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_COMMON_BLOCK_USE_ESPI @@ -130,22 +133,6 @@ config DRIVER_TPM_I2C_ADDR hex default 0x50 -config PICASSO_FW_A_POSITION - hex - default 0xFF012040 - depends on VBOOT_SLOTS_RW_AB - help - Location of the AMD firmware in the RW_A region. This is the - start of the RW-A region + 64 bytes for the cbfs header. - -config PICASSO_FW_B_POSITION - hex - default 0xFF312040 - depends on VBOOT_SLOTS_RW_AB - help - Location of the AMD firmware in the RW_B region. This is the - start of the RW-A region + 64 bytes for the cbfs header. - config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS bool default y if BOARD_GOOGLE_TREMBYLE diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 8bc69ab1e2..bac7ee42e0 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -5,15 +5,15 @@ config BOARD_GOOGLE_DALBOZ select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_VILBOZ - bool "-> Vilboz" + bool "-> Vilboz (Lenovo 100e/300e Gen3 AMD)" select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_EZKINIL - bool "-> Ezkinil" + bool "-> Ezkinil (Acer Chromebook Spin 514)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_MORPHIUS - bool "-> Morphius" + bool "-> Morphius (Lenovo ThinkPad C13 Yoga Chromebook)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_TREMBYLE @@ -21,15 +21,15 @@ config BOARD_GOOGLE_TREMBYLE select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_BERKNIP - bool "-> Berknip" + bool "-> Berknip (HP Pro c645 Chromebook Enterprise)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_WOOMAX - bool "-> Woomax" + bool "-> Woomax (ASUS Chromebook Flip CM5)" select BOARD_GOOGLE_BASEBOARD_TREMBYLE config BOARD_GOOGLE_DIRINBOZ - bool "-> Dirinboz" + bool "-> Dirinboz (HP Chromebook 14a-nd0097nr)" select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_SHUBOZ @@ -37,5 +37,5 @@ config BOARD_GOOGLE_SHUBOZ select BOARD_GOOGLE_BASEBOARD_DALBOZ config BOARD_GOOGLE_GUMBOZ - bool "-> Gumboz" + bool "-> Gumboz (HP Chromebook x360 14a)" select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index ccc163c4dd..a260b0fd21 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -10,6 +10,7 @@ ramstage-y += chromeos.c ramstage-y += ec.c ramstage-y += sku_id.c +verstage-y += chromeos.c verstage-y += verstage.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c index b581b90d1a..d64919316b 100644 --- a/src/mainboard/google/zork/chromeos.c +++ b/src/mainboard/google/zork/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -31,3 +33,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index ea292f163e..54da830004 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" @@ -203,7 +202,6 @@ static void mainboard_enable(struct device *dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; } diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index bec8f09576..298b64760b 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 2764a89b08..437ba0b52c 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -1,23 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio_baseboard_common.c bootblock-y += helpers.c bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -verstage-y += gpio_baseboard_common.c verstage-y += helpers.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c verstage-y += tpm_tis.c -romstage-y += gpio_baseboard_common.c romstage-y += helpers.c romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c romstage-y += tpm_tis.c -ramstage-y += gpio_baseboard_common.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c deleted file mode 100644 index 948ce8f9d4..0000000000 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -static const struct soc_amd_gpio early_gpio_table[] = { - /* H1_FCH_INT_ODL */ - PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), - /* I2C3_SCL - H1 */ - PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), - /* I2C3_SDA - H1 */ - PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), - /* PCIE_RST0_L - Fixed timings */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* FCH_ESPI_EC_CS_L */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* ESPI_ALERT_L */ - PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), - /* UART0_RXD - DEBUG */ - PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), - /* UART0_TXD - DEBUG */ - PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), -}; - -const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) -{ - *size = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 6f8a416657..ffcfb2539a 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -5,7 +5,6 @@ #include #include #include -#include #include static const struct soc_amd_gpio gpio_set_stage_ram[] = { @@ -310,3 +309,48 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 62935a66a9..ae1252db0b 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -7,7 +7,6 @@ #include #include #include -#include #include static const struct soc_amd_gpio gpio_set_stage_ram[] = { @@ -359,3 +358,48 @@ const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } + +static const struct soc_amd_gpio espi_gpio_table[] = { + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(espi_gpio_table); + return espi_gpio_table; +} + +static const struct soc_amd_gpio tpm_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(tpm_gpio_table); + return tpm_gpio_table; +} + +static const struct soc_amd_gpio early_gpio_table[] = { + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index d6c5e4824f..7057a48382 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -55,6 +55,9 @@ enum { /* Audio AMP type */ FW_CONFIG_MASK_AUDIO_AMP = 0x1, FW_CONFIG_SHIFT_AUDIO_AMP = 35, + /* Audio codec type */ + FW_CONFIG_MASK_AUDIO_CODEC_SOURCE = 0x3, + FW_CONFIG_SHIFT_AUDIO_CODEC_SOURCE = 36, }; static int get_fw_config(uint64_t *val) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl index dec33ec5dd..5667248015 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -56,8 +56,7 @@ Scope (\_TZ) Local1 = CTOK (\TCRT) If (Local0 >= Local1) { - Debug = "CRITICAL TEMPERATURE" - Debug = Local0 + Printf ("CRITICAL TEMPERATURE: %o", Local0) /* Wait 1 second for EC to re-poll */ Sleep (1000) @@ -65,8 +64,7 @@ Scope (\_TZ) /* Re-read temperature from EC */ Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) - Debug = "RE-READ TEMPERATURE" - Debug = Local0 + Printf ("RE-READ TEMPERATURE: %o", Local0) } Return (Local0) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 3f7e5d1c34..09d5786b14 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -7,8 +7,8 @@ #include #include #include +#include #include -#include "chip.h" const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* @@ -33,6 +33,12 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_ty */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +/* This function provides GPIO settings for eSPI bus. */ +const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size); + +/* This function provides GPIO settings for TPM i2c bus. */ +const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size); + void variant_updm_update(FSP_M_CONFIG *mcfg); /* Program any required GPIOs at the finalize phase */ diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c index b4e5bcc671..6bf8678404 100644 --- a/src/mainboard/google/zork/variants/dalboz/variant.c +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -1,11 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include -#include #define DALBOZ_DB_HDMI 0x1 diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index c3cc9e6c40..32a5e76b6b 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later +fw_config + field AUDIO_CODEC_SOURCE 36 37 + option AUDIO_CODEC_ALC5682 0 + option AUDIO_CODEC_ALC5682I_VS 1 + end +end chip soc/amd/picasso @@ -51,6 +57,86 @@ chip soc/amd/picasso # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit + device ref internal_bridge_a on + device ref acp on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + end + chip drivers/amd/i2s_machine_dev + register "hid" = ""10029835"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 1.0 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end # Audio + end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682 + end + device generic 1.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_84)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS + end + end + end + end + end end # domain device ref i2c_2 on diff --git a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc index 316880625f..3875882848 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/spd/Makefile.inc @@ -8,3 +8,4 @@ SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT40A512M SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE +SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:R diff --git a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt index a38e73fe1c..a1893db547 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ MT40A512M16TB-062E:J 0 (0000) H5AN8G6NCJR-XNC 1 (0001) MT40A1G16KD-062E:E 2 (0010) K4AAG165WA-BCWE 3 (0011) +MT40A512M16TB-062E:R 4 (0100) diff --git a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt index e54791948d..b4caa40cbd 100644 --- a/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt @@ -11,3 +11,4 @@ MT40A512M16TB-062E:J, 0 H5AN8G6NCJR-XNC, 1 MT40A1G16KD-062E:E, 2 K4AAG165WA-BCWE, 3 +MT40A512M16TB-062E:R, 4 diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c index 9907c7219a..b0a6b7ea02 100644 --- a/src/mainboard/google/zork/variants/shuboz/variant.c +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include -#include "chip.h" uint32_t usb_oc_map_override[USB_PORT_COUNT] = { USB_OC_PIN_0, diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index f4d0cb446d..7853c1594f 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -13,3 +13,7 @@ SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 5(0b0101) Parts = K4AAG165W SPD_SOURCES += spd/ddr4/set-0/spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E SPD_SOURCES += spd/ddr4/set-0/spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 8(0b1000) Parts = MT40A1G16RC-062E:B +SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 9(0b1001) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 10(0b1010) Parts = MT40A512M16TB-062E:R +SPD_SOURCES += spd/ddr4/set-0/spd-1.hex # ID = 11(0b1011) Parts = 4JQA-0622AD +SPD_SOURCES += spd/ddr4/set-0/spd-9.hex # ID = 12(0b1100) Parts = K4AAG165WB-BCWE diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index 4211dab31c..f3bd888c56 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -11,3 +11,7 @@ K4AAG165WA-BCWE 5 (0101) MT40A1G16KD-062E:E 6 (0110) H5ANAG6NDMR-XNC 7 (0111) MT40A1G16RC-062E:B 8 (1000) +H5ANAG6NCJR-XNC 9 (1001) +MT40A512M16TB-062E:R 10 (1010) +4JQA-0622AD 11 (1011) +K4AAG165WB-BCWE 12 (1100) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index a4b0aaf6b7..994795347a 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -14,3 +14,7 @@ K4AAG165WA-BCWE, 5 MT40A1G16KD-062E:E, 6 H5ANAG6NDMR-XNC, 7 MT40A1G16RC-062E:B, 8 +H5ANAG6NCJR-XNC, 9 +MT40A512M16TB-062E:R, 10 +4JQA-0622AD, 11 +K4AAG165WB-BCWE, 12 diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 43ca0e51df..ddfce69aaa 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -4,7 +4,7 @@ #include #include #include -#include "chip.h" +#include static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c index e1277f4d14..06032577e2 100644 --- a/src/mainboard/google/zork/verstage.c +++ b/src/mainboard/google/zork/verstage.c @@ -2,6 +2,7 @@ #include #include +#include #include static void setup_gpio(void) @@ -19,3 +20,27 @@ void verstage_mainboard_early_init(void) { setup_gpio(); } + +void verstage_mainboard_espi_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} + +void verstage_mainboard_tpm_init(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + return; + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig index df3f626e9f..0db753d2cf 100644 --- a/src/mainboard/hp/280_g2/Kconfig +++ b/src/mainboard/hp/280_g2/Kconfig @@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select SPD_READ_BY_WORD select SUPERIO_ITE_COMMON_PRE_RAM +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "hp/280_g2" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 47df4e1026..5dc62aafc8 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -56,7 +56,6 @@ chip soc/intel/skylake device pci 16.3 off end # ME KT device pci 16.4 off end # MEI #3 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ [0] = 1, diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index acbe6601e3..8ad26c2d9d 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 76d04d6d2a..98e48efeef 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index f1df3ef1c0..fa7cba114d 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index e296ff90eb..ff760b3380 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -15,7 +15,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* USB controller PME# */ Method(_L0B) { - Debug = "USB PME" + Printf ("USB PME") /* Notify devices of wake event */ Notify(\_SB.PCI0.UOH1, 0x02) Notify(\_SB.PCI0.UOH2, 0x02) @@ -38,7 +38,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* Lid switch opened or closed */ Method(_L16) { - Debug = "Lid status changed" + Printf ("Lid status changed") /* Flip trigger polarity */ LPOL = ~LPOL /* Notify lid object of status change */ @@ -47,7 +47,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* GPIO0 or GEvent8 event */ Method(_L18) { - Debug = "PCI bridge wake event" + Printf ("PCI bridge wake event") /* Notify PCI bridges of wake event */ Notify(\_SB.PCI0.PBR4, 0x02) Notify(\_SB.PCI0.PBR5, 0x02) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index b11ad68e10..467a4f56de 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -37,7 +37,7 @@ */ Method (PNOT) { - Debug = "Received PNOT call (probably from EC)" + Printf ("Received PNOT call (probably from EC)") /* TODO: Implement this */ } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index c3471ab3d8..d85ab2e8a1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -3,7 +3,6 @@ #include "ec.h" #include -#include #include #include #include diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 3dd88258fa..2bfbacdc15 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -29,7 +29,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 5204e60133..0de9cfabef 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 05b0a09a0c..fdfe541f47 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -1,5 +1,8 @@ if BOARD_IBASE_MB899 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_M diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 2b78515776..927b8ede8e 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -1,5 +1,6 @@ config BOARD_INTEL_ADLRVP_COMMON def_bool n + select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -14,7 +15,6 @@ config BOARD_INTEL_ADLRVP_COMMON select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -23,11 +23,15 @@ config BOARD_INTEL_ADLRVP_P select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_P + select GEN3_EXTERNAL_CLOCK_BUFFER config BOARD_INTEL_ADLRVP_P_EXT_EC select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_INTEL_PMC select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_ALDERLAKE_PCH_P + select GEN3_EXTERNAL_CLOCK_BUFFER config BOARD_INTEL_ADLRVP_P_MCHP select BOARD_INTEL_ADLRVP_COMMON @@ -36,7 +40,7 @@ config BOARD_INTEL_ADLRVP_P_MCHP select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select INTEL_LPSS_UART_FOR_CONSOLE - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ALDERLAKE_PCH_P config BOARD_INTEL_ADLRVP_M select BOARD_INTEL_ADLRVP_COMMON @@ -55,8 +59,25 @@ config BOARD_INTEL_ADLRVP_M_EXT_EC select SOC_INTEL_ALDERLAKE_PCH_M select SPI_TPM +config BOARD_INTEL_ADLRVP_N + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + select SOC_INTEL_ALDERLAKE_PCH_N + +config BOARD_INTEL_ADLRVP_N_EXT_EC + select BOARD_INTEL_ADLRVP_COMMON + select DRIVERS_INTEL_PMC + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_ALDERLAKE_PCH_N + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + if BOARD_INTEL_ADLRVP_COMMON +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -74,11 +95,14 @@ config VARIANT_DIR default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP default "adlrvp_m" if BOARD_INTEL_ADLRVP_M default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC + default "adlrvp_n" if BOARD_INTEL_ADLRVP_N + default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC config GBB_HWID string depends on CHROMEOS default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + default "ADLRVPN" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "ADLRVPP" config MAINBOARD_PART_NUMBER @@ -94,6 +118,7 @@ config MAINBOARD_FAMILY config DEVICETREE default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC + default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "devicetree.cb" config OVERRIDE_DEVICETREE @@ -104,8 +129,8 @@ config DIMM_SPD_SIZE choice prompt "ON BOARD EC" - default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M - default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP + default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC help This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC @@ -139,4 +164,20 @@ config DRIVER_TPM_SPI_BUS config TPM_TIS_ACPI_INTERRUPT int default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) + +config GEN3_EXTERNAL_CLOCK_BUFFER + bool + depends on SOC_INTEL_ALDERLAKE_PCH_P + default n + help + Support external Gen-3 clock chip for ADL-P. + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer + for further distribution to platform. SRCCLKREQB[7:9] maps to internal + SRCCLKREQB[6]. If any of them asserted, SRC buffer + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled. + +config CLKSRC_FOR_EXTERNAL_BUFFER + depends on GEN3_EXTERNAL_CLOCK_BUFFER + int + default 6 # CLKSRC 6 endif diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 7ee2c13ef9..c9c56fa7dc 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -12,3 +12,9 @@ config BOARD_INTEL_ADLRVP_M config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" + +config BOARD_INTEL_ADLRVP_N + bool "Alderlake-N RVP" + +config BOARD_INTEL_ADLRVP_N_EXT_EC + bool "Alderlake-N RVP with Chrome EC" diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 04c16455e8..0b658e5caa 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -7,6 +7,9 @@ bootblock-$(CONFIG_CHROMEOS) += chromeos.c ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_M),y) bootblock-y += early_gpio_m.c ramstage-y += gpio_m.c +else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) +bootblock-y += early_gpio_n.c +ramstage-y += gpio_n.c else bootblock-y += early_gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c index 332ba1b7ae..de7a3804d9 100644 --- a/src/mainboard/intel/adlrvp/board_id.c +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include "board_id.h" diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c index 60dee1ab05..eeee406f12 100644 --- a/src/mainboard/intel/adlrvp/bootblock.c +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -1,95 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include -#include -#include -#include -#include -#include -#include - -#define SI_DESC_REGION "SI_DESC" -#define SI_DESC_REGION_SZ 4096 -#define PMC_DESC_7_BYTE3 0xc32 - -/* Flash Master 1 : HOST/BIOS */ -#define FLMSTR1 0x80 - -/* Flash signature Offset */ -#define FLASH_SIGN_OFFSET 0x10 -#define FLMSTR_WR_SHIFT_V2 20 -#define FLASH_VAL_SIGN 0xFF0A55A - -/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ -static int is_descriptor_writeable(uint8_t *desc) -{ - /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { - printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); - return 0; - } - - /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { - printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); - return 0; - } - - return 1; -} - -/* It updates PMC Descriptor in the Descriptor Region */ -static void configure_pmc_descriptor(void) -{ - uint8_t si_desc_buf[SI_DESC_REGION_SZ]; - struct region_device desc_rdev; - - if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); - return; - } - - if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (!is_descriptor_writeable(si_desc_buf)) - return; - - if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { - printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); - return; - } - - si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; - - if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) - != SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); - - pmc_global_reset_enable(true); - do_full_reset(); - die("Failed to trigger GLOBAL RESET\n"); -} void bootblock_mainboard_early_init(void) { variant_configure_early_gpio_pads(); } -void bootblock_mainboard_init(void) -{ - if (cpu_get_cpuid() == CPUID_ALDERLAKE_A0) - configure_pmc_descriptor(); -} diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c index d963c73651..d7e55a91dc 100644 --- a/src/mainboard/intel/adlrvp/chromeos.c +++ b/src/mainboard/intel/adlrvp/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -12,9 +14,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || + CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)) + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); + else + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1); } #if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) @@ -44,3 +50,12 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) ||\ + CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)) +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} +#endif diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 84adad9ba5..53469de9c2 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -15,7 +15,7 @@ FLASH 32M { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4032K + ME_RW_A(CBFS) 3520K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -39,7 +39,7 @@ FLASH 32M { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4032K + ME_RW_B(CBFS) 3520K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a00ad357d3..9bd99b18f7 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -8,9 +8,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration # Enable CNVi BT @@ -81,18 +78,21 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable CPU PCIE RP 2 using CLK 3 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_req = 3, .clk_src = 3, - }" + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" # Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_req = 4, .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" register "SataSalpSupport" = "1" @@ -187,21 +187,6 @@ chip soc/intel/alderlake }, }" - # FIVR configurations - register "ext_fivr_settings" = "{ - .configure_ext_fivr = 1, - .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, - .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, - .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, - .v1p05_voltage_mv = 1050, - .vnn_voltage_mv = 1050, - .vnn_sx_voltage_mv = 1050, - .v1p05_icc_max_ma = 500, - .vnn_icc_max_ma = 500, - }" - device domain 0 on device ref pcie5 on end device ref igpu on end diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b73ded1e10..c637ec3d54 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -18,9 +18,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 communication - register "HeciEnabled" = "1" - # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 @@ -89,6 +86,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 0, .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" # Enable EDP in PortA diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb new file mode 100644 index 0000000000..0dea803874 --- /dev/null +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -0,0 +1,292 @@ +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + + # Enable CNVi BT + register "CnviBtCore" = "true" + + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable PCH PCIE RP 7 using CLK 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + # Enable PCH PCIE RP 9 using CLK 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # TCSS USB3 + register "TcssAuxOri" = "4" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" + + register "CnviBtAudioOffload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref crashlog off end + device ref tcss_xhci on end + device ref xhci on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref sata on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref uart0 on end + device ref gspi0 on end + device ref p2sb on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end + device ref smbus on end + end +end diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c index 7576ff143d..57cadfade8 100644 --- a/src/mainboard/intel/adlrvp/early_gpio.c +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -2,7 +2,6 @@ #include #include -#include #include /* Early pad configuration in bootblock */ @@ -16,93 +15,96 @@ static const struct pad_config early_gpio_table[] = { /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* CPU PCIe VGPIO for RP0 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), /* CPU PCIe vGPIO for RP1 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), /* CPU PCIe vGPIO for RP2 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), /* CPU PCIe vGPIO for RP3 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config early_uart_gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 915240ce0c..fbc6467b46 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -2,7 +2,6 @@ #include #include -#include #include /* Early pad configuration in bootblock */ @@ -17,6 +16,9 @@ static const struct pad_config early_gpio_table[] = { /* H13 : CPU_SSD_RST# */ PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* CPU PCIe VGPIO for RP0 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/adlrvp/early_gpio_n.c b/src/mainboard/intel/adlrvp/early_gpio_n.c new file mode 100644 index 0000000000..3eb1ceae52 --- /dev/null +++ b/src/mainboard/intel/adlrvp/early_gpio_n.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* EC_IN_RW */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), +}; + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 1996683778..d553180541 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* SSD1_PWREN CPU SSD1 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), @@ -38,8 +39,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* THC1_SPI2_INTB */ PAD_CFG_GPI(GPP_E17, NONE, PLTRST), - /* EC_SMI_N */ - PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), /* EC_SLP_S0_CS_N */ PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* WIFI RF KILL */ diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index 6eb670b7af..62ae0f38c0 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -2,7 +2,6 @@ #include #include -#include /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c new file mode 100644 index 0000000000..9ba20bab17 --- /dev/null +++ b/src/mainboard/intel/adlrvp/gpio_n.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* ESPI_IO0_EC_R / ESPI_IO0_HDR */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /* ESPI_IO1_EC_R / ESPI_IO1_HDR */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + /* ESPI_IO2_EC_R / ESPI_IO2_HDR */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + /* ESPI_IO3_EC_R / ESPI_IO3_HDR */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /* ESPI_CLK_EC_R / ESPI_CLK_HDR */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* CLKREQ0_M2_SSD_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* M2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* M2_SSD_DEVSLP */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), + + /* TYPEA_CONN23_USB2_P8_OC1_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* CRD1_PWREN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* TCP1_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), + /* TCP1_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), + /* TCP0_DISP_AUX_P_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + /* TCP0_DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + + /* EDP1_HPD_MIPI_PNL_RST */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* X1_SLOT_PWREN */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), + /* SML0_CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* SML0_DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* CLKREQ3_X1PCIE_SLOT_N */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* X1_PCIE_SLOT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT), + /* X1_Slot_RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* CLKREQ1_WWAN_N */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPPC_D15_M.2_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_PWREN */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* WWAN WAKE N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI + /* SRCCLK_OEB6 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3), + /* GPPC_F6_CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_F14, 1, PLTRST), + /* WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_F15, 1, PLTRST), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + /* CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* CODEC_INT_N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* SNDW0_CLK_HDR */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW0_DATA_HDR */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW1_CLK_DMIC_CLK_A_0 */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW1_DATA_DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW2_CLK_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + /* SNDW2_DATA_R */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* SOC_DMIC0_SNDW3_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SOC_DMIC0_SNDW3_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* DDIB_DP_HDMI_ALS_HDP */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* 8 : M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* 9 : GPD_9_SLP_WLAN_N */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + + /* GPIO pin for PCIE SRCCLKREQB_2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* H2 : WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* CAM_PRIVACY_LED */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* B16 : I2C5 SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : I2C5 SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* D13 : WIFI_WAKE_N */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* F0 : CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2 : CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4 : CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h index c01829936d..6a5c72ceeb 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -33,11 +33,13 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* - * EC can wake from S3 with lid or power button or key press or + * EC can wake from S3 with lid or power button or key press or AC connect/disconnect or * mode change event. */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index de0adf6cff..9a1c5851c0 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,4 +12,6 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +#define GPIO_EC_IN_RW GPP_E7 + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9ab05f6bb1..143679ac56 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -24,6 +24,8 @@ enum adl_boardid { /* ADL-M LP4 and LP5 RVPs */ ADL_M_LP4 = 0x1, ADL_M_LP5 = 0x2, + /* ADL-N LP5 RVP */ + ADL_N_LP5 = 0x7, }; /* The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index a113683e0e..8882671bfa 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -37,7 +36,7 @@ void __weak variant_devtree_update(void) /* Override dev tree settings per board */ } -#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) +#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) static void add_fw_config_oem_string(const struct fw_config *config, void *arg) { struct smbios_type11 *t; @@ -57,9 +56,7 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; - -#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) +#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) dev->ops->get_smbios_strings = mainboard_smbios_strings; #endif } @@ -71,17 +68,21 @@ struct chip_operations mainboard_ops = { const char *mainboard_vbt_filename(void) { + if (!CONFIG(CHROMEOS)) + return "vbt.bin"; + uint8_t sku_id = get_board_id(); switch (sku_id) { case ADL_P_LP5_1: case ADL_P_LP5_2: - case ADL_M_LP5: return "vbt_adlrvp_lp5.bin"; + case ADL_M_LP5: + return "vbt_adlrvp_m_lp5.bin"; case ADL_P_DDR5_1: case ADL_P_DDR5_2: return "vbt_adlrvp_ddr5.bin"; case ADL_M_LP4: - return "vbt_adlrvp_lp4.bin"; + return "vbt_adlrvp_m_lp4.bin"; default: return "vbt.bin"; } diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index f93b361267..b917d98e10 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include "board_id.h" @@ -226,7 +227,7 @@ static const struct mb_cfg adlm_lp4_mem_config = { .LpDdrDqDqsReTraining = 1, - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, }; static const struct mb_cfg adlm_lp5_mem_config = { @@ -282,8 +283,70 @@ static const struct mb_cfg adlm_lp5_mem_config = { .ect = false, /* Early Command Training */ + .UserBd = BOARD_TYPE_ULT_ULX_T4, + + .lp5x_config = { + .ccc_config = 0xff, + }, +}; + +static const struct mb_cfg adln_lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_ULT_ULX, + .LpDdrDqDqsReTraining = 1, + .lp5x_config = { .ccc_config = 0xff, }, @@ -310,6 +373,8 @@ const struct mb_cfg *variant_memory_params(void) return &adlm_lp4_mem_config; case ADL_M_LP5: return &adlm_lp5_mem_config; + case ADL_N_LP5: + return &adln_lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 136fa455df..22902bd48b 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "board_id.h" #include diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 34fc04e6cb..a0453efd5f 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -24,8 +24,27 @@ static size_t get_spd_index(void) return spd_index; } -void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) +/* + * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's + * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are + * connected on the platform, an external differential buffer chip needs to be placed at + * the platform level. + * + * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for + * ADL-M/N RVP) + * + * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete + * buffer for further distribution to platform. + */ +static void configure_external_clksrc(FSP_M_CONFIG *m_cfg) { + for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++) + m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER; +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); int board_id = get_board_id(); const bool half_populated = false; @@ -62,10 +81,14 @@ void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: + case ADL_N_LP5: memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); break; } + + if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER)) + configure_external_clksrc(m_cfg); } diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 4cb0f98da1..96869f4870 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -7,4 +7,4 @@ SPD_SOURCES += adlrvp_lp5 # 0b003 SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 SPD_SOURCES += adlrvp_ddr5_mr # 0b006 -SPD_SOURCES += adlrvp_lp5 # 0b007 +SPD_SOURCES += adlrvp_n_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex new file mode 100644 index 0000000000..88a1f1f473 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_n_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A B5 08 00 40 00 00 0A 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 133a737f66..a3860c6f76 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -14,15 +14,15 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb new file mode 100644 index 0000000000..5ed3065eb7 --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb @@ -0,0 +1,89 @@ +fw_config + field AUDIO 8 10 + option NONE 0 + option ADL_MAX98373_ALC5682I_I2S 1 + end +end + +chip soc/intel/alderlake + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO ADL_MAX98373_ALC5682I_I2S + end + end + end + + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TypeC Port 1"" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""TypeC Port 2"" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index e78d00fa7f..de5471cf65 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -34,22 +34,22 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "3" - register "usb3_port_number" = "3" + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 2 alias conn2 on end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb index a23db8c0f9..91073f7661 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_mchp/overridetree.cb @@ -14,15 +14,15 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "1" - register "usb3_port_number" = "1" + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 6d7bc8cf93..a22c33927b 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_BASKING_RIDGE +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select NORTHBRIDGE_INTEL_HASWELL diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2b140142b8..d4408f4d06 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -5,13 +5,15 @@ #include #include #include +#include #include +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ - {69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -31,18 +33,18 @@ int get_recovery_mode_switch(void) * Recovery: GPIO69, Connected to J8E3, however the silkscreen says * J8E2. The jump is active high. */ - return get_gpio(69); + return get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(22); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 04803fa37b..73fa9aa65c 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -5,7 +5,6 @@ #include #include #include -#include void mainboard_suspend_resume(void) { @@ -18,7 +17,6 @@ void mainboard_suspend_resume(void) static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h new file mode 100644 index 0000000000..66812a55f0 --- /dev/null +++ b/src/mainboard/intel/baskingridge/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASKINGRIDGE_ONBOARD_H +#define BASKINGRIDGE_ONBOARD_H + +/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */ +#define GPIO_REC_MODE 69 + +/* Write protect is active low */ +#define GPIO_SPI_WP 22 + +#endif diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 07a0083ae3..936703bce7 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index e51752b371..ae8212a8dd 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -21,7 +21,7 @@ void bootblock_mainboard_early_init(void) pcr_write32(PID_DMI, 0x2774, 1); /* Decode for SuperIO (0x2e) and COM1 (0x3f8) */ - pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); + pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16)); const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 5fb79221de..5c5003b7a9 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -2,9 +2,11 @@ #include #include +#include #include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index aa073bcc8c..eb9a316a34 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -6,7 +6,6 @@ #include #include #include -#include static void mainboard_init(void *chip_info) { @@ -45,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device, static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index f9eba5c580..9e5f2436ad 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include #if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index ebc172b6b0..c5e5afde28 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_DCP847SKE +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index df8112cdbb..0232486403 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #if CONFIG(USE_NATIVE_RAMINIT) @@ -17,11 +18,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/intel/dg41wv/Kconfig b/src/mainboard/intel/dg41wv/Kconfig index bb201bc76d..8c5a5d6111 100644 --- a/src/mainboard/intel/dg41wv/Kconfig +++ b/src/mainboard/intel/dg41wv/Kconfig @@ -2,6 +2,9 @@ if BOARD_INTEL_DG41WV +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_LGA775 diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index c3c853cdeb..55b5cd08f0 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -2,6 +2,9 @@ if BOARD_INTEL_DG43GT +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_LGA775 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 18005418ef..0fdc88a7a8 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,9 +12,6 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c index 9d17c80d3f..b2e2eeca22 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /*BT_RF_KILL_N*/ PAD_CFG_GPO(GPP_E11, 1, DEEP), diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 86fe98a803..0220d73c22 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_EMERALDLAKE2 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index e0f5fafbb0..2d0e2e1f44 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -5,13 +5,15 @@ #include #include #include +#include #include +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, @@ -28,18 +30,18 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_recovery_mode_switch(void) { /* Recovery: GPIO22, active low */ - return !get_gpio(22); + return !get_gpio(GPIO_REC_MODE); } int get_write_protect_state(void) { /* Write protect is active low, so invert it here */ - return !get_gpio(48); + return !get_gpio(GPIO_SPI_WP); } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index aa481dc780..11b3121b6c 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -54,11 +55,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 6291d60993..3b6727b057 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -4,14 +4,12 @@ #include #include #include -#include // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h new file mode 100644 index 0000000000..658ad83e19 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/onboard.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EMERALDLAKE2_ONBOARD_H +#define EMERALDLAKE2_ONBOARD_H + +/* Recovery: GPIO22, active low */ +#define GPIO_REC_MODE 22 + +/* Write protect is active low */ +#define GPIO_SPI_WP 48 + +#endif diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 9b4df3dd88..c6d5240043 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -18,8 +18,7 @@ static uint64_t reg_read(struct reg_script_context *ctx) step = ctx->step; switch (step->id) { default: - printk(BIOS_ERR, - "ERROR - Unknown register set (0x%08x)!\n", + printk(BIOS_ERR, "Unknown register set (0x%08x)!\n", step->id); ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; break; @@ -48,8 +47,7 @@ static void reg_write(struct reg_script_context *ctx) step = ctx->step; switch (step->id) { default: - printk(BIOS_ERR, - "ERROR - Unknown register set (0x%08x)!\n", + printk(BIOS_ERR, "Unknown register set (0x%08x)!\n", step->id); ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; break; diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index b5e61d926e..a7a262fa00 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -1,4 +1,3 @@ - config BOARD_INTEL_BASEBOARD_GLKRVP def_bool n select SOC_INTEL_GEMINILAKE @@ -16,6 +15,9 @@ config BOARD_INTEL_BASEBOARD_GLKRVP if BOARD_INTEL_BASEBOARD_GLKRVP +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BASEBOARD_GLKRVP_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 594440618e..7a14c86bd2 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include +#include #include #include #include @@ -37,3 +39,10 @@ int __weak get_lid_switch(void) { return -1; } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c index cfbaf0d6c8..1cfa4e06d5 100644 --- a/src/mainboard/intel/glkrvp/mainboard.c +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include @@ -55,7 +54,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 9a8188ba5d..0b2c6801af 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl deleted file mode 100644 index 7425afb7b8..0000000000 --- a/src/mainboard/intel/harcuvar/acpi/thermal.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - // Thermal Zone - -Scope (\_TZ) -{ -} diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index e8dcb787a3..9eae08e0f1 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -15,9 +15,6 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal Handler - #include "acpi/thermal.asl" - // global NVS and variables #include diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 027c56ef52..44551a2edf 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -88,7 +88,7 @@ void mainboard_config_gpios(void) } if ((!table) || (!num)) { - printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n"); + printk(BIOS_ERR, "No valid GPIO table found!\n"); return; } diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index c98c4f8318..6df26afced 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -3,8 +3,10 @@ #include #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/icelake_rvp/mainboard.c b/src/mainboard/intel/icelake_rvp/mainboard.c index c8e9e411ea..2440651499 100644 --- a/src/mainboard/intel/icelake_rvp/mainboard.c +++ b/src/mainboard/intel/icelake_rvp/mainboard.c @@ -5,7 +5,6 @@ #include #include #include -#include static void mainboard_init(void *chip_info) { @@ -16,12 +15,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(pads, num); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c index 30e249c22e..94a6a7970f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c index 30e249c22e..94a6a7970f 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* I2S2_SCLK */ PAD_CFG_GPI(GPP_A7, NONE, PLTRST), diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index a5b5c39fd4..6ae35661bf 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -33,6 +33,12 @@ config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC if BOARD_INTEL_JASPERLAKE_RVP_COMMON +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "intel/jasperlake_rvp" diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index c59fac8001..bf9a7bf8b9 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/intel/jasperlake_rvp/mainboard.c b/src/mainboard/intel/jasperlake_rvp/mainboard.c index 315d47d2b0..efba386cf9 100644 --- a/src/mainboard/intel/jasperlake_rvp/mainboard.c +++ b/src/mainboard/intel/jasperlake_rvp/mainboard.c @@ -7,7 +7,6 @@ #include #include #include -#include #define SERIAL_IO_PCR_GPPRVRW4 0x60C @@ -23,11 +22,6 @@ static void mainboard_init(void *chip_info) pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - const char *smbios_system_sku(void) { static const char *sku_str = "sku2147483647"; /* sku{0-1} */ @@ -36,5 +30,4 @@ const char *smbios_system_sku(void) struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index c44ce52990..27395db402 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* WWAN_WAKE_N */ diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf8329f6..11d1319976 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -31,6 +31,12 @@ config BOARD_INTEL_KBLRVP11 if BOARD_INTEL_KBLRVP_COMMON +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index 270c84d44f..afc27cd6d5 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include #include #include "gpio.h" @@ -62,3 +64,10 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index e502d84632..2b09df4596 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "ec.h" #include @@ -21,7 +20,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b71f3..bae6198118 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "HeciEnabled" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h index fe8c2e210c..fb47e6f71b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -257,7 +257,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h index e0292cfa86..11a6b82b41 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index a60850545f..9c252e2651 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h index 5b588a10c3..1c112dfb9b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h @@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = { }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 85f9e54d82..dc456b6858 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_KUNIMITSU +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 @@ -21,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_SKYLAKE select HAVE_SPD_IN_CBFS +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 3b8725f954..87a0e01b41 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include #include #include "gpio.h" @@ -33,3 +35,9 @@ void mainboard_chromeos_acpi_generate(void) { chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ba4835eb25..deb9f38c7a 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 2cd0196137..c4628f2ed2 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -217,11 +217,12 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_NC(GPD11, NONE), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), }; #endif diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 4136c368fd..b7c61f5058 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -5,7 +5,6 @@ #include #include #include -#include #include "ec.h" #include "gpio.h" @@ -82,7 +81,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index decbb9688a..5d16d22875 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "intel/saddlebrook" diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h index f60515b8ec..da9c27e599 100644 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ b/src/mainboard/intel/saddlebrook/gpio.h @@ -245,7 +245,7 @@ static const struct pad_config gpio_table[] = { /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -/* Early pad configuration in romstage. */ +/* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 553906a39c..f6d8a581ea 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_SHADOWMOUNTAIN +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 @@ -23,7 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG - select SOC_INTEL_ALDERLAKE + select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_CSE_LITE_SKU select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c index 35a54a8aca..0858754436 100644 --- a/src/mainboard/intel/shadowmountain/chromeos.c +++ b/src/mainboard/intel/shadowmountain/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -32,3 +34,9 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c index 2783b4d2ce..f035aa9b53 100644 --- a/src/mainboard/intel/shadowmountain/mainboard.c +++ b/src/mainboard/intel/shadowmountain/mainboard.c @@ -5,7 +5,6 @@ #include #include #include -#include static void mainboard_init(void *chip_info) { @@ -21,12 +20,6 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 3aacf38a03..48c20db1ab 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -1,16 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include -#include #include #include #include -#include #include #include -#include -void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) +void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); const bool half_populated = false; diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 6cf83d2707..63d3da423b 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ chip soc/intel/alderlake register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi Bluetooth register "CnviBtCore" = "true" @@ -279,15 +276,15 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "1" + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "4" - register "usb3_port_number" = "2" + use usb2_port4 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c index 80a42646fc..ea05b89275 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c @@ -2,7 +2,6 @@ #include #include -#include /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { @@ -13,6 +12,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* A7 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* A17 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), /* A19 : MEM_STRAP_2 */ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c index 8d7778c9c1..f416e09004 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c @@ -2,7 +2,8 @@ #include #include -#include +#include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 64d5dfc842..725ee9f0e2 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_STRAGO +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 21ae380e4b..004a6a248e 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,11 +2,11 @@ bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += ec.c +ramstage-y += gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index f01f7f1d68..91ce9aed27 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include #include -#define WP_GPIO GP_E_22 - -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 +#include "onboard.h" void fill_lb_gpios(struct lb_gpios *gpios) { @@ -22,14 +21,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { /* - * The vboot loader queries this function in romstage. The GPIOs have + * This function might get queried early in romstage. The GPIOs have * not been set up yet as that configuration is done in ramstage. * Configuring this GPIO as input so that there isn't any ambiguity * in the reading. */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO); /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index 55424c2a0f..e34ea7f258 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -4,7 +4,6 @@ #include #include #include "ec.h" -#include void mainboard_ec_init(void) { diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 82f46294cb..447ae31355 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include "ec.h" static void mainboard_init(struct device *dev) @@ -17,7 +16,6 @@ static void mainboard_init(struct device *dev) static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index bc2e7a278a..d8af569733 100644 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -29,6 +29,9 @@ #define JACK_DETECT_GPIO_INDEX 95 /* SCI: Gpio index in N bank */ #define BOARD_SCI_GPIO_INDEX 15 + +#define WP_GPIO GP_E_22 + /* Trackpad: Gpio index in N bank */ #define BOARD_TRACKPAD_GPIO_INDEX 18 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 2c4c48a438..9e63f2c09e 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -1,5 +1,8 @@ if BOARD_INTEL_TGLRVP_UP3 || BOARD_INTEL_TGLRVP_UP4 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 7da61be1b0..dd6c666794 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -2,8 +2,10 @@ #include #include +#include #include #include +#include #include void fill_lb_gpios(struct lb_gpios *gpios) @@ -45,3 +47,10 @@ void mainboard_chromeos_acpi_generate(void) gpios = variant_cros_gpios(&num); chromeos_acpi_gpio_generate(gpios, num); } + +int get_ec_is_trusted(void) +{ + /* Do not have a Chrome EC involved in entering recovery mode; + Always return trusted. */ + return 1; +} diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index 82877ed28e..bbce9278df 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include @@ -29,12 +28,6 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, - .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b84fddc397..2c9a548ae0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -8,12 +8,8 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" @@ -45,6 +41,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable RP LTR register "PcieRpLtrEnable[2]" = "1" @@ -120,9 +120,6 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 15, @@ -323,15 +320,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "3" + use usb2_port6 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "7" - register "usb3_port_number" = "4" + use usb2_port7 as usb2_port + use tcss_usb3_port4 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 448aa41ecc..b9fdac8617 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fcadcee990..d19747a5c0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -8,12 +8,8 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" @@ -46,6 +42,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable PR LTR register "PcieRpLtrEnable[2]" = "1" @@ -124,9 +124,6 @@ chip soc/intel/tigerlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 9, @@ -327,15 +324,15 @@ chip soc/intel/tigerlake chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "6" - register "usb3_port_number" = "3" + use usb2_port6 as usb2_port + use tcss_usb3_port3 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "5" - register "usb3_port_number" = "2" + use usb2_port5 as usb2_port + use tcss_usb3_port2 as usb3_port # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 18dab082a2..1c007d7bd7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -2,9 +2,10 @@ #include #include -#include +#include +#include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ PAD_CFG_GPO(GPP_B16, 1, DEEP), diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 996eee2f3c..5e01910e48 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -5,6 +5,7 @@ #include #include #include +#include #include /* Compile-time settings for recovery mode. */ diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e9583acbfc..d17645ff03 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -2,14 +2,12 @@ #include #include -#include // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 25263eacb2..53cb8c3e60 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index e8407de732..dc07949da0 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -1,5 +1,8 @@ if BOARD_KONTRON_986LCD_M +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_SOCKET_M diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index e4e29e0bf1..782f560744 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -15,19 +15,20 @@ config BOARD_KONTRON_BSL6_COMMON select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y -config BOARD_KONTRON_BSL6_OPTIONS - bool +config BOARD_KONTRON_BSL6 select BOARD_KONTRON_BSL6_COMMON select HAVE_ACPI_RESUME -config BOARD_KONTRON_BOXER26_OPTIONS - bool +config BOARD_SIEMENS_BOXER26 select BOARD_KONTRON_BSL6_COMMON select DRIVERS_I2C_LM96000 select SECUNET_DMI if BOARD_KONTRON_BSL6_COMMON +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "kontron/bsl6" diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name index 90bf1c474f..0f0577e5db 100644 --- a/src/mainboard/kontron/bsl6/Kconfig.name +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -1,7 +1,5 @@ config BOARD_KONTRON_BSL6 bool "COMe-bSL6" - select BOARD_KONTRON_BSL6_OPTIONS config BOARD_SIEMENS_BOXER26 bool "COMe-bSL6 on Siemens/Boxer26" - select BOARD_KONTRON_BOXER26_OPTIONS diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a878019e8f..31bee5d21f 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/intel/sandybridge #register "gen4_dec" = "0x00000000" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 55902db0ed..521695b9ba 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -59,11 +60,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 21a0941ccd..80daf19afe 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -182,15 +182,14 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) * data from the table. Otherwise, it will use its default conservative settings */ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), - MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - - PSO_END + PSO_END }; void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) diff --git a/src/mainboard/lenovo/g505s/acpi/ec.asl b/src/mainboard/lenovo/g505s/acpi/ec.asl index 59868a9882..cde03fac2c 100644 --- a/src/mainboard/lenovo/g505s/acpi/ec.asl +++ b/src/mainboard/lenovo/g505s/acpi/ec.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* Defines EC bits specific to the mainboard, needed by EC ASL */ -#include "mainboard.h" +#include "../mainboard.h" /* ACPI code for EC functions */ #include diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index f137606974..74b4c4807b 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -15,7 +15,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* USB controller PME# */ Method(_L0B) { - Debug = "USB PME" + Printf ("USB PME") /* Notify devices of wake event */ Notify(\_SB.PCI0.UOH1, 0x02) Notify(\_SB.PCI0.UOH2, 0x02) @@ -37,7 +37,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* Lid switch opened or closed */ Method(_L16) { - Debug = "Lid status changed" + Printf ("Lid status changed") /* Flip trigger polarity */ LPOL = ~LPOL /* Notify lid object of status change */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* GPIO0 or GEvent8 event */ Method(_L18) { - Debug = "PCI bridge wake event" + Printf ("PCI bridge wake event") /* Notify PCI bridges of wake event */ Notify(\_SB.PCI0.PBR4, 0x02) Notify(\_SB.PCI0.PBR5, 0x02) diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index b11ad68e10..36f82a3335 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) Field(GP0B, ByteAcc, NoLock, Preserve) { @@ -37,7 +36,7 @@ */ Method (PNOT) { - Debug = "Received PNOT call (probably from EC)" + Printf ("Received PNOT call (probably from EC)") /* TODO: Implement this */ } diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index 1a81182e55..c1ed48652c 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -3,7 +3,6 @@ #include "ec.h" #include -#include #include #include #include @@ -27,7 +26,6 @@ static const u8 mainboard_intr_data[0x54] = { 0x10, 0x11, 0x12, 0x13 }; - static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 86205f8f84..6c2dabeabb 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -38,7 +38,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3b" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 3c1fc9e073..14d849def9 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi7_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x5" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index e42e519f87..c934f5fe06 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -55,13 +55,13 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ab98ca0bd0..1d6adaf3a8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -57,13 +57,13 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 112dfe71e7..141faa930c 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,7 +35,7 @@ chip northbridge/intel/sandybridge register "gpi13_routing" = "2" register "gpi1_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x17" register "superspeed_capable_ports" = "0x0000000f" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 75a65f9000..942f029989 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a1e24d525b..9c75231efc 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ffa0b93e53..5cfa207564 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -52,7 +52,7 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x0c06a1" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index abe40b19dc..ee8a2e083a 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x00000c03" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 30260b0c13..cbf1141aec 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 53eb23a1bd..923c88bc31 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -55,12 +55,12 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 07a5dbdf93..7a9163dc29 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -15,11 +16,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1f81311685..30a79162d4 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 0cf8abef65..39c2e33a28 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" @@ -47,7 +46,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl index 7472ffed71..5968ff3294 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl @@ -37,7 +37,6 @@ /* GPIO0 or GEvent8 event */ Method(_L18) { - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index e35a70b8ae..5f834fc348 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -13,203 +13,12 @@ DefinitionBlock ( { /* Start of ASL file */ #include + #include - /* - * Processor Object - * - */ - Scope (\_SB) { /* define processor scope */ - Device (C000) { - Name (_HID, "ACPI0007") - Name (_UID, 0) - } - Device (C001) { - Name (_HID, "ACPI0007") - Name (_UID, 1) - } - Device (C002) { - Name (_HID, "ACPI0007") - Name (_UID, 2) - } - Device (C003) { - Name (_HID, "ACPI0007") - Name (_UID, 3) - } - } /* End _SB scope */ - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - , 1, /* MiscControl */ - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } + #include #include "acpi/routing.asl" - #include - /* Contains the supported sleep states for this chipset */ #include @@ -227,10 +36,9 @@ DefinitionBlock ( /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ Device(PCI0) { - External (TOM1) - External (TOM2) - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + + /* Describe the AMD Northbridge */ + #include /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -262,122 +70,28 @@ DefinitionBlock ( Return (PR0) /* PIC Mode */ } /* end _PRT */ - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } - } /* end AGPB */ - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ + /* Describe the Southbridge devices */ - /* Dev3 is also an external GFX bridge, not used in Herring */ + #include - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ + #include - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ + #include - /* GPP */ - Device(PBR9) { - Name(_ADR, 0x00090000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR9 */ + #include - Device(PBRa) { - Name(_ADR, 0x000A0000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ - } /* end PBRa */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PICM){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* PCI slot 1, 2, 3 */ + /* PCI bridge */ Device(PIBR) { Name(_ADR, 0x00140004) Name(_PRW, Package() {0x18, 4}) @@ -385,141 +99,6 @@ DefinitionBlock ( Method(_PRT, 0) { Return (PCIB) } - } - - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - } /* end AZHD */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - #include "acpi/superio.asl" - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) } /* end HostPciBr */ Device(ACAD) { diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c index b2a96a236f..393408237f 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c @@ -38,7 +38,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP case VOLT1_25: // board is not able to provide this MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry printk(BIOS_INFO, "can't provide 1.25 V, using "); - // fall through + __fallthrough; default: // AGESA.h says in mixed case 1.5V DIMMs get excluded case VOLT1_35: FCH_GPIO(184) = 0x08; // = output, disable PU, set to 0 diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c index 3302556113..8fa897e25e 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c index 4861809ba6..f15db2f8cb 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c @@ -39,7 +39,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP case VOLT1_25: // board is not able to provide this MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry printk(BIOS_INFO, "can't provide 1.25 V, using "); - // fall through + __fallthrough; default: // AGESA.h says in mixed case 1.5V DIMMs get excluded case VOLT1_35: FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0 diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c index 09695d4b85..6492f56fa1 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index 5a8f479431..f4db2644be 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 6c97e1f6c7..8e5df5863d 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 2d1de391e0..37bce31c80 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/ocp/deltalake/uartio_vpd.c b/src/mainboard/ocp/deltalake/uartio_vpd.c index d2e052f93a..4c2d876c7d 100644 --- a/src/mainboard/ocp/deltalake/uartio_vpd.c +++ b/src/mainboard/ocp/deltalake/uartio_vpd.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include -#include #include "vpd.h" diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index b5c2aa1567..6bcbfcc473 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -30,7 +30,7 @@ static void enable_espi_lpc_io_windows(void) pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ - pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + pci_s_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); } diff --git a/src/mainboard/portwell/m107/Kconfig b/src/mainboard/portwell/m107/Kconfig index e2cd98886f..1c8e754a82 100644 --- a/src/mainboard/portwell/m107/Kconfig +++ b/src/mainboard/portwell/m107/Kconfig @@ -2,6 +2,9 @@ if BOARD_PORTWELL_M107 +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig new file mode 100644 index 0000000000..2faefe5efb --- /dev/null +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -0,0 +1,32 @@ +config BOARD_PRODRIVE_ATLAS_BASEBOARD + def_bool n + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_ALDERLAKE_PCH_P + +if BOARD_PRODRIVE_ATLAS_BASEBOARD + +config MAINBOARD_FAMILY + string + default "PRODRIVE_ATLAS_SERIES" + +config MAINBOARD_PART_NUMBER + default "Atlas ADL-P" + +config MAINBOARD_DIR + default "prodrive/atlas" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Prodrive Technologies B.V." + +config DIMM_SPD_SIZE + default 512 + +config UART_FOR_CONSOLE + int + default 0 + +endif #BOARD_PRODRIVE_ATLAS_BASEBOARD diff --git a/src/mainboard/prodrive/atlas/Kconfig.name b/src/mainboard/prodrive/atlas/Kconfig.name new file mode 100644 index 0000000000..f4304a0542 --- /dev/null +++ b/src/mainboard/prodrive/atlas/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PRODRIVE_ATLAS + bool "Atlas" + select BOARD_PRODRIVE_ATLAS_BASEBOARD diff --git a/src/mainboard/prodrive/atlas/Makefile.inc b/src/mainboard/prodrive/atlas/Makefile.inc new file mode 100644 index 0000000000..1446e54c25 --- /dev/null +++ b/src/mainboard/prodrive/atlas/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt b/src/mainboard/prodrive/atlas/board_info.txt similarity index 59% rename from src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt rename to src/mainboard/prodrive/atlas/board_info.txt index 80dba9546d..4a86d0e76d 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt +++ b/src/mainboard/prodrive/atlas/board_info.txt @@ -1,7 +1,6 @@ -Category: server Vendor name: Prodrive -Board name: Hermes -Board URL: TBD +Board name: Atlas +Category: misc ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/prodrive/atlas/bootblock.c b/src/mainboard/prodrive/atlas/bootblock.c new file mode 100644 index 0000000000..5b1643b742 --- /dev/null +++ b/src/mainboard/prodrive/atlas/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + configure_early_gpio_pads(); +} diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb new file mode 100644 index 0000000000..7b094e4fc0 --- /dev/null +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -0,0 +1,100 @@ +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80) + # Clock source is shared hence marked as free running. + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" + + # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) + # Clock source is shared hence marked as free running. + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + + device domain 0 on + device ref pcie5 on end + device ref igpu on end + device ref dtt on end + device ref pcie4_0 on end + device ref pcie4_1 on end + device ref crashlog off end + device ref xhci on end + device ref heci1 on end + device ref sata on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref uart0 on end + device ref uart1 on end + device ref p2sb on end + device ref hda on end + device ref smbus on end + end +end diff --git a/src/mainboard/prodrive/atlas/dsdt.asl b/src/mainboard/prodrive/atlas/dsdt.asl new file mode 100644 index 0000000000..d39f2ef211 --- /dev/null +++ b/src/mainboard/prodrive/atlas/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + #include + + /* global NVS and variables */ + #include + + #include + + Device (\_SB.PCI0) { + #include + #include + #include + } + + #include +} diff --git a/src/mainboard/prodrive/atlas/early_gpio.c b/src/mainboard/prodrive/atlas/early_gpio.c new file mode 100644 index 0000000000..b79375218c --- /dev/null +++ b/src/mainboard/prodrive/atlas/early_gpio.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "gpio.h" + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* PCH HSID */ + PAD_CFG_GPI(GPP_A8, NONE, DEEP), + PAD_CFG_GPI(GPP_F19, NONE, DEEP), + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + PAD_CFG_GPI(GPP_H23, NONE, DEEP), + + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* UART1 RX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* UART1 TX */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +}; + +void configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/prodrive/atlas/gpio.c b/src/mainboard/prodrive/atlas/gpio.c new file mode 100644 index 0000000000..0f92889ab4 --- /dev/null +++ b/src/mainboard/prodrive/atlas/gpio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "gpio.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB_2_3_OC_N */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB_4_5_OC_N */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB_6_7_OC_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DP1_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DP2_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* DP3_HPD */ + PAD_NC(GPP_A23, NONE), /* ESPI_CS1 */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* AUX_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* AUX_VID1 */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SATA_SPKR_N */ + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B23, NONE), /* SML1_ALERT */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_NC(GPP_C5, NONE), /* SML0_ALERT */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_CLK */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_DATA */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* TPM INT (todo: check) */ + PAD_CFG_GPI(GPP_E6, NONE, DEEP), + PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), /* PERST_CB_RESET_N */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_0_1_OC_N */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP0_HPD (VGA_RED) */ + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DP3_DDC_CTRLCLK */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DP3_DDC_CTRLDATA */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DP2_DDC_CTRLCLK */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DP2_DDC_CTRLDATA */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* DP0_DDC_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DP0_DDC_CTRLDATA */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_CFG_GPI(GPP_F2, NONE, DEEP), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F5, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), /* EC_SLP_S0_CS_N */ + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_CFG_GPO(GPP_F22, 1, DEEP), /* PERST_PHY0_N */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), /* HDA_SDI1 */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD8, NONE), /* SUSCLK */ +}; + +void configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/prodrive/atlas/gpio.h b/src/mainboard/prodrive/atlas/gpio.h new file mode 100644 index 0000000000..8244206adf --- /dev/null +++ b/src/mainboard/prodrive/atlas/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +void configure_gpio_pads(void); +void configure_early_gpio_pads(void); + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/prodrive/atlas/mainboard.c b/src/mainboard/prodrive/atlas/mainboard.c new file mode 100644 index 0000000000..036208a0a6 --- /dev/null +++ b/src/mainboard/prodrive/atlas/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +static void mainboard_init(void *chip_info) +{ + configure_gpio_pads(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c new file mode 100644 index 0000000000..837a528422 --- /dev/null +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 50, 30, 30, 30, 27 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + } +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + const struct mb_cfg *mem_config = &ddr5_mem_config; + const bool half_populated = false; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, + }; + + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 2fecc06f6d..ae7b5f1269 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -14,6 +14,7 @@ config BOARD_PRODRIVE_HERMES_BASEBOARD select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_HDA_VERB select ONBOARD_VGA_IS_PRIMARY + select SMBIOS_TYPE41_PROVIDED_BY_DEVTREE select HAVE_ACPI_RESUME if !HERMES_USES_SPS_FIRMWARE select DISABLE_ACPI_HIBERNATE if HERMES_USES_SPS_FIRMWARE @@ -44,9 +45,6 @@ config PCIEXP_CLK_PM bool default n -config VARIANT_DIR - default "baseboard" if BOARD_PRODRIVE_HERMES_BASEBOARD - config MAX_CPUS int default 16 diff --git a/src/mainboard/prodrive/hermes/Makefile.inc b/src/mainboard/prodrive/hermes/Makefile.inc index d13b50aff7..63be66c655 100644 --- a/src/mainboard/prodrive/hermes/Makefile.inc +++ b/src/mainboard/prodrive/hermes/Makefile.inc @@ -1,16 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/prodrive/hermes/variants/$(VARIANT_DIR)/include - bootblock-y += bootblock.c -romstage-y += memory.c +bootblock-y += gpio.c + romstage-y += eeprom.c +ramstage-y += gpio.c ramstage-y += ramstage.c ramstage-y += mainboard.c ramstage-y += eeprom.c ramstage-y += smbios.c -ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += variants/baseboard/hda_verb.c -ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += variants/r04/hda_verb.c +$(call add_vbt_to_cbfs, vbt-avalanche.bin, avalanche-data.vbt) diff --git a/src/mainboard/prodrive/hermes/avalanche-data.vbt b/src/mainboard/prodrive/hermes/avalanche-data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..c3513310bbabe8fc182566ad1b0913e39447dd8f GIT binary patch literal 4608 zcmeHKU2GIp6h5=FzjtP~vr{7NiuLdl*e$fo7N}TDob7J0OBZ(AEzJ^5y1)+Du+Z8c zEe7M7G|GdLKA=H^(ifr<6Y62m5^NfGj_eyQ=^K;!_@RlBQOqV%7~j8NFX>}@C-frb2A_$e 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zhWdgmhpPIJ-ku%G?meQHcI`c^{|_>@gLg{TzXskN7wH~)o~a5V2CYE?NnK2HyZY7fTT&&z$6o9O4;{3*{bame3k&eZVj EFYt=Y9{>OV literal 0 HcmV?d00001 diff --git a/src/mainboard/prodrive/hermes/board_info.txt b/src/mainboard/prodrive/hermes/board_info.txt index 72bcfa956f..3a5aff454c 100644 --- a/src/mainboard/prodrive/hermes/board_info.txt +++ b/src/mainboard/prodrive/hermes/board_info.txt @@ -1,5 +1,7 @@ Category: server Vendor name: Prodrive +Board name: Hermes +Board URL: https://prodrive-technologies.com/products/embedded-computing-systems/motherboards/hermes-8th-9th-gen-series/ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/prodrive/hermes/bootblock.c b/src/mainboard/prodrive/hermes/bootblock.c index 40fd0b48a3..9db1fa8306 100644 --- a/src/mainboard/prodrive/hermes/bootblock.c +++ b/src/mainboard/prodrive/hermes/bootblock.c @@ -2,8 +2,9 @@ #include #include +#include #include -#include + #include "gpio.h" void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt b/src/mainboard/prodrive/hermes/data.vbt similarity index 100% rename from src/mainboard/prodrive/hermes/variants/baseboard/data.vbt rename to src/mainboard/prodrive/hermes/data.vbt diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 8faf016e7c..db573821cf 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -1,7 +1,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SataMode" = "0" # AHCI register "SataSalpSupport" = "0" register "satapwroptimize" = "1" register "SataPortsDevSlp[1]" = "1" # PCH_M2_SATA_DEVSLP1 @@ -199,18 +198,30 @@ chip soc/intel/cannonlake device pci 1c.4 on # PCIe root port 5 (PHY 3) register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" + device pci 00.0 on + smbios_dev_info 3 + end end device pci 1c.5 on # PCIe root port 6 (PHY 4) register "PcieRpEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1" + device pci 00.0 on + smbios_dev_info 4 + end end device pci 1c.6 on # PCIe root port 7 (PHY 2) register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" + device pci 00.0 on + smbios_dev_info 2 + end end device pci 1c.7 on # PCIe root port 8 (PHY 1) register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + device pci 00.0 on + smbios_dev_info 1 + end end device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" @@ -221,6 +232,9 @@ chip soc/intel/cannonlake device pci 1d.5 on # PCIe root port 14 (PHY 0) register "PcieRpEnable[13]" = "1" register "PcieRpLtrEnable[13]" = "1" + device pci 00.0 on + smbios_dev_info 0 + end end device pci 1d.6 on # PCIe root port 15 (BMC) device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 97bee96406..9d62f408c6 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -7,22 +7,19 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision + 0x20110725 ) { #include #include - - // global NVS and variables #include Scope (\_SB) { Device (PCI0) { - #include - #include + #include + #include } } #include - } diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index cdea67d6d3..5385a4a5e7 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include +#include +#include #include #include #include -#include "variants/baseboard/include/eeprom.h" +#include "eeprom.h" #define I2C_ADDR_EEPROM 0x57 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h similarity index 89% rename from src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h rename to src/mainboard/prodrive/hermes/eeprom.h index 9ec4604fc2..f428a432fc 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include +#include union eeprom_dimm_layout { struct __packed { @@ -47,19 +49,22 @@ struct __packed eeprom_board_settings { uint8_t usb_powered_in_s5; uint8_t power_state_after_g3; uint8_t blue_rear_vref; - uint8_t internal_audio_connection; + uint8_t front_panel_audio; uint8_t pxe_boot_capability; + uint8_t pink_rear_vref; + uint8_t vtx_disabled; }; - uint8_t raw_settings[9]; + uint8_t raw_settings[11]; }; }; -_Static_assert(sizeof(struct eeprom_board_settings) == (9 + sizeof(uint32_t)), +_Static_assert(sizeof(struct eeprom_board_settings) == (11 + sizeof(uint32_t)), "struct eeprom_board_settings has invalid size!"); struct __packed eeprom_bmc_settings { uint8_t pcie_mux; uint8_t hsi; + uint8_t efp3_displayport; }; #define HERMES_SERIAL_NUMBER_LENGTH 32 @@ -71,7 +76,7 @@ struct __packed eeprom_layout { FSPM_UPD mupd; }; union { - uint8_t RawFSPSUPD[0xC00]; + uint8_t RawFSPSUPD[0xc00]; FSPS_UPD supd; }; union { @@ -82,7 +87,7 @@ struct __packed eeprom_layout { char board_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; uint8_t BootOrder[0x8c0]; union { - uint8_t RawBoardSetting[0xF8]; + uint8_t RawBoardSetting[0xf8]; struct eeprom_board_settings BoardSettings; }; union { @@ -92,7 +97,7 @@ struct __packed eeprom_layout { }; _Static_assert(sizeof(FSPM_UPD) <= 0x600, "FSPM_UPD too big"); -_Static_assert(sizeof(FSPS_UPD) <= 0xC00, "FSPS_UPD too big"); +_Static_assert(sizeof(FSPS_UPD) <= 0xc00, "FSPS_UPD too big"); _Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size mismatch"); bool eeprom_read_buffer(void *blob, size_t read_offset, size_t size); diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/gpio.c similarity index 99% rename from src/mainboard/prodrive/hermes/variants/baseboard/gpio.c rename to src/mainboard/prodrive/hermes/gpio.c index 7f81842e21..5cb901d8f4 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/gpio.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/variant/gpio.h" #include +#include #include -#include + +#include "gpio.h" /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -368,7 +369,7 @@ static const struct pad_config gpio_table[] = { }; -/* Early pad configuration in bootblock. */ +/* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { /* Get PCIe out of reset */ PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h b/src/mainboard/prodrive/hermes/gpio.h similarity index 100% rename from src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h rename to src/mainboard/prodrive/hermes/gpio.h diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 9780e7dcb5..7514ce9711 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -2,10 +2,160 @@ #include #include -#include -#include "variants/baseboard/include/eeprom.h" -#include "variants/baseboard/include/variant/variants.h" +#include "eeprom.h" + +const u32 cim_verb_data[] = { + 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ + 0x10ec0888, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1d336700), + + /* Pin widgets */ + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), /* SPDIF-OUT2 - disabled */ + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* digital MIC - disabled */ + AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* PORT D - rear line out */ + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), /* PORT G - disabled */ + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* PORT H - disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* PORT B - rear mic in */ + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */ + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ + AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ + AZALIA_PIN_CFG(0, 0x1f, 0x01c52170), /* SPDIF-IN */ + + /* Config for R02 and older */ + AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */ + AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* port C - internal speaker */ + AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* port E - rear line in/mic - Blue */ + AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* port A - audio hdr input */ + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xff + * Codec Vendor: 0x8086280b + */ + 0x8086280b, + 0xffffffff, + 5, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x20878101, + + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + /* Disable the third converter and third Pin (NID 08h) */ + 0x20878100, + + /* Dummy entries */ + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; + +static const u32 r04_verb_data[] = { + AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* PORT F - front mic in */ + AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* PORT C - rear line in (mic support) */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* PORT E - disabled */ + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), /* PORT A - disabled */ +}; + +static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) +{ + switch (blue_rear_vref) { + default: + case 0: + return 0x02040000; + case 1: + return 0x02041000; + case 2: + return 0x02044000; + case 3: + return 0x02045000; + case 4: + return 0x02046000; + } +} + +static u32 get_port_b_vref_cfg(uint8_t pink_rear_vref) +{ + switch (pink_rear_vref) { + default: + case 0: + return 0x411110f0; /* Disabled (Hi-Z) */ + case 1: + return 0x411111f0; /* 50% of LDO out */ + case 2: + return 0x411114f0; /* 80% of LDO out */ + case 3: + return 0x411115f0; /* 100% of LDO out */ + case 4: + return 0x411112f0; /* Ground */ + } +} + +static u32 get_front_panel_cfg(uint8_t front_panel_audio) +{ + switch (front_panel_audio) { + default: + case 0: + return AZALIA_PIN_CFG_NC(0); + case 1: + return 0x02214c40; + case 2: + return 0x0227ec40; + } +} + +static u32 get_front_mic_cfg(uint8_t front_panel_audio) +{ + return front_panel_audio == 2 ? AZALIA_PIN_CFG_NC(0) : 0x02a19c20; +} + +static void mainboard_r0x_configure_alc888(u8 *base, u32 viddid) +{ + /* Overwrite settings made by baseboard */ + azalia_program_verb_table(base, r04_verb_data, ARRAY_SIZE(r04_verb_data)); + + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + const u32 front_panel_cfg = get_front_panel_cfg(board_cfg->front_panel_audio); + + const u32 front_mic_cfg = get_front_mic_cfg(board_cfg->front_panel_audio); + + const u32 port_b_vref_cfg = get_port_b_vref_cfg(board_cfg->pink_rear_vref); + + const u32 verbs[] = { + /* + * Write port B Vref settings to unused non-volatile NID 0x12 instead of + * NID 0x18, the actual port B NID. Because per-port Vref settings don't + * persist after codec resets, a custom Realtek driver (ab)uses NID 0x12 + * to restore port B Vref after resetting the codec. + */ + AZALIA_PIN_CFG(0, 0x12, port_b_vref_cfg), + AZALIA_PIN_CFG(0, 0x19, front_mic_cfg), + AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg), + 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ + get_port_c_vref_cfg(board_cfg->blue_rear_vref), + }; + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); +} void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) { diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index a9c840839e..2f0de61843 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,19 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include +#include #include #include #include -#include #include #include +#include +#include +#include #include -#include #include -#include "variants/baseboard/include/eeprom.h" +#include +#include + +#include "eeprom.h" #include "gpio.h" +const char *mainboard_vbt_filename(void) +{ + const struct eeprom_bmc_settings *bmc_cfg = get_bmc_settings(); + + if (bmc_cfg && bmc_cfg->efp3_displayport) + return "vbt-avalanche.bin"; + else + return "vbt.bin"; /* Poseidon */ +} + /* FIXME: Example code below */ static void mb_configure_dp1_pwr(bool enable) @@ -138,7 +153,7 @@ static void mainboard_init(void *chip_info) return; /* Enable internal speaker amplifier */ - if (board_cfg->internal_audio_connection == 2) + if (board_cfg->front_panel_audio == 2) mb_hda_amp_enable(1); else mb_hda_amp_enable(0); @@ -225,6 +240,8 @@ static void mainboard_early(void *unused) /* Set Deep Sx */ config->deep_s5_enable_ac = board_cfg->deep_sx_enabled; config->deep_s5_enable_dc = board_cfg->deep_sx_enabled; + + config->disable_vmx = board_cfg->vtx_disabled; } if (check_signature(offsetof(struct eeprom_layout, supd), FSPS_UPD_SIGNATURE)) { diff --git a/src/mainboard/prodrive/hermes/memory.c b/src/mainboard/prodrive/hermes/memory.c deleted file mode 100644 index 0ff21c4754..0000000000 --- a/src/mainboard/prodrive/hermes/memory.c +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -static const struct cnl_mb_cfg baseboard_memcfg_cfg = { - /* Access memory info through SMBUS. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA0} - }, - .spd[1] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA2} - }, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA4} - }, - .spd[3] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA6} - }, - - /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = {121, 81, 100}, - - /* Baseboard Rcomp target values. */ - .rcomp_targets = {100, 40, 20, 20, 26}, - - /* Baseboard is an interleaved design */ - .dq_pins_interleaved = 1, - - /* Baseboard is using config 2 for vref_ca */ - .vref_ca_config = 2, - - /* Disable Early Command Training */ - .ect = 0, -}; - -const struct cnl_mb_cfg *variant_memcfg_config(void) -{ - return &baseboard_memcfg_cfg; -} diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 917f3b93cf..f38ee379d1 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include "variants/baseboard/include/eeprom.h" + +#include "eeprom.h" +#include "gpio.h" void mainboard_silicon_init_params(FSPS_UPD *supd) { diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index 238a7919a1..b52c52c489 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -2,14 +2,49 @@ #include #include -#include -#include "variants/baseboard/include/eeprom.h" + +#include "eeprom.h" + +static const struct cnl_mb_cfg baseboard_mem_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0} + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa2} + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4} + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa6} + }, + + /* Rcomp resistors on CFL-S are located on the CPU itself */ + .rcomp_resistor = {121, 75, 100}, + + /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */ + .rcomp_targets = {60, 26, 20, 20, 26}, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 1, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, +}; void mainboard_memory_init_params(FSPM_UPD *memupd) { memupd->FspmConfig.UserBd = BOARD_TYPE_SERVER; memupd->FspmTestConfig.SmbusSpdWriteDisable = 0; - cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); + cannonlake_memcfg_init(&memupd->FspmConfig, &baseboard_mem_cfg); /* Overwrite memupd */ if (!check_signature(offsetof(struct eeprom_layout, mupd), FSPM_UPD_SIGNATURE)) diff --git a/src/mainboard/prodrive/hermes/smbios.c b/src/mainboard/prodrive/hermes/smbios.c index af81e86c9a..c1325d4771 100644 --- a/src/mainboard/prodrive/hermes/smbios.c +++ b/src/mainboard/prodrive/hermes/smbios.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include +#include -#include "variants/baseboard/include/eeprom.h" +#include "eeprom.h" const char *smbios_system_serial_number(void) { diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c b/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c deleted file mode 100644 index d20f35d508..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -const u32 cim_verb_data[] = { - 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ - 0x10ec0888, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x1d336700), - - /* Pin widgets */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), /* SPDIF-OUT2 - disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* digital MIC - disabled */ - AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* PORT D - rear line out */ - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), /* PORT G - disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* PORT H - disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* PORT B - rear mic in */ - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */ - AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ - AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1f, 0x01C52170), /* SPDIF-IN */ - - /* Config for R02 and older */ - AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */ - AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* port C - internal speaker */ - AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* port E - rear line in/mic - Blue */ - AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* port A - audio hdr input */ - - /* - * VerbTable: CFL Display Audio Codec - * Revision ID = 0xFF - * Codec Vendor: 0x8086280B - */ - 0x8086280B, - 0xFFFFFFFF, - 5, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(2, 0x80860101), - - /* - * Display Audio Verb Table - * For GEN9, the Vendor Node ID is 08h - * Port to be exposed to the inbox driver in the vanilla mode - * PORT C - BIT[7:6] = 01b - */ - 0x20878101, - - /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ - AZALIA_PIN_CFG(2, 0x07, 0x18560030), - /* Disable the third converter and third Pin (NID 08h) */ - 0x20878100, - - /* Dummy entries */ - 0x20878100, - 0x20878100, -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h deleted file mode 100644 index 54a116143f..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* Return memory configuration structure. */ -const struct cnl_mb_cfg *variant_memcfg_config(void); - -void mainboard_r0x_configure_alc888(u8 *base, u32 viddid); diff --git a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c b/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c deleted file mode 100644 index f9a3cb33c7..0000000000 --- a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "variant/variants.h" -#include "eeprom.h" - -static const u32 r04_verb_data[] = { - AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* PORT F - front mic in */ - AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* PORT C - rear line in (mic support) */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* PORT E - disabled */ - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), /* PORT A - disabled */ -}; - -static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) -{ - switch (blue_rear_vref) { - default: - case 0: - return 0x02040000; - case 1: - return 0x02041000; - case 2: - return 0x02044000; - case 3: - return 0x02045000; - case 4: - return 0x02046000; - } -} - -static u32 get_internal_audio_cfg(uint8_t internal_audio_connection) -{ - switch (internal_audio_connection) { - default: - case 0: - return AZALIA_PIN_CFG_NC(0); - case 1: - return 0x022a4c40; - case 2: - return AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - NA, - SPEAKER, - TYPE_UNKNOWN, - COLOR_UNKNOWN, - false, - 0xf, - 0); - } -} - -void mainboard_r0x_configure_alc888(u8 *base, u32 viddid) -{ - /* Overwrite settings made by baseboard */ - azalia_program_verb_table(base, r04_verb_data, ARRAY_SIZE(r04_verb_data)); - - const struct eeprom_board_settings *const board_cfg = get_board_settings(); - - if (!board_cfg) - return; - - const u32 config = get_internal_audio_cfg(board_cfg->internal_audio_connection); - - const u32 verbs[] = { - AZALIA_PIN_CFG(0, 0x1b, config), - 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ - get_port_c_vref_cfg(board_cfg->blue_rear_vref), - }; - azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); -} diff --git a/src/mainboard/protectli/vault_bsw/Kconfig b/src/mainboard/protectli/vault_bsw/Kconfig index e169392d6a..5877f8486c 100644 --- a/src/mainboard/protectli/vault_bsw/Kconfig +++ b/src/mainboard/protectli/vault_bsw/Kconfig @@ -1,5 +1,8 @@ if BOARD_PROTECTLI_FW2B || BOARD_PROTECTLI_FW4B +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3ef4250353..feb8b9f1e3 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -29,13 +29,11 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c index bd001b507b..1b03121053 100644 --- a/src/mainboard/purism/librem_bdw/hda_verb.c +++ b/src/mainboard/purism/librem_bdw/hda_verb.c @@ -6,85 +6,20 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ 0x19910269, /* Subsystem ID */ - 0x0000000c, /* Number of jacks (NID entries) */ + 12, /* Number of jacks (NID entries) */ - 0x0017ff00, /* Function Reset */ - 0x0017ff00, /* Double Function Reset */ - 0x0017ff00, - 0x0017ff00, - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ - 0x00172069, - 0x00172102, - 0x00172291, - 0x00172319, - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) */ - 0x01271c00, - 0x01271d00, - 0x01271e00, - 0x01271f40, - - /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d01, - 0x01471e17, - 0x01471f90, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d10, - 0x01871ea1, - 0x01871f04, - - /* Pin Complex (NID 0x19) */ - 0x01971c30, - 0x01971d01, - 0x01971ea7, - 0x01971f90, - - /* Pin Complex (NID 0x1A) */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) */ - 0x01b71cf0, - 0x01b71d11, - 0x01b71e11, - 0x01b71f41, - - /* Pin Complex (NID 0x1D) */ - 0x01d71c05, - 0x01d71d9d, - 0x01d71e56, - 0x01d71f40, - - /* Pin Complex (NID 0x1E) */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) */ - 0x02171c1f, - 0x02171d10, - 0x02171e21, - 0x02171f04, + AZALIA_RESET(1), + AZALIA_SUBVENDOR(0, 0x19910269), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11020), + AZALIA_PIN_CFG(0, 0x19, 0x90a70130), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40569d05), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0421101f), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb index c8d6816958..8b5c9086b9 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb @@ -199,7 +199,6 @@ chip soc/intel/cannonlake device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on # SATA - register "SataMode" = "SATA_AHCI" register "satapwroptimize" = "1" register "SataSalpSupport" = "1" # Port 2 (M.2 / inner) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl index 611643b54a..8045aaf402 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/include/variant/acpi/gpe.asl @@ -2,7 +2,7 @@ // GPP_E15 SWI Method (_L49, 0, Serialized) { - Debug = Concatenate("GPE _L49: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + Printf ("GPE _L49: %o", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) If (\_SB.PCI0.LPCB.EC0.ECOK) { If (\_SB.PCI0.LPCB.EC0.WFNO == One) { Notify(\_SB.LID0, 0x80) diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 4c6f6a8ade..e20a002716 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -18,6 +18,9 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL if BOARD_PURISM_BASEBOARD_LIBREM_SKL +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VARIANT_DIR default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5efb1e2aed..94b79f9bc9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" @@ -53,7 +52,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -162,7 +160,7 @@ chip soc/intel/skylake device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 14.3 off end # Camera - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index d273968b3e..ae76fb3cca 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -6,52 +6,20 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ 0x19910269, /* Subsystem ID */ - 0x0000000c, /* Number of jacks (NID entries) */ + 12, /* Number of jacks (NID entries) */ - 0x0017ff00, /* Function Reset */ - 0x0017ff00, /* Double Function Reset */ - 0x0017ff00, - 0x0017ff00, - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ + AZALIA_RESET(1), AZALIA_SUBVENDOR(0, 0x19910269), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) */ AZALIA_PIN_CFG(0, 0x12, 0x40000000), - - /* Pin Complex (NID 0x14) */ AZALIA_PIN_CFG(0, 0x14, 0x90170110), - - /* Pin Complex (NID 0x15) */ AZALIA_PIN_CFG(0, 0x15, 0x04214020), - - /* Pin Complex (NID 0x17) */ AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) */ AZALIA_PIN_CFG(0, 0x18, 0x04a19040), - - /* Pin Complex (NID 0x19) */ AZALIA_PIN_CFG(0, 0x19, 0x90a70130), - - /* Pin Complex (NID 0x1A) */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), - - /* Pin Complex (NID 0x1B) */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), - - /* Pin Complex (NID 0x1D) */ - AZALIA_PIN_CFG(0, 0x1D, 0x40548505), - - /* Pin Complex (NID 0x1E) */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40548505), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 42ee0c7971..3b2343b92c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" @@ -32,7 +31,6 @@ chip soc/intel/skylake register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 9ebe4b5eac..fc1a484f0e 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -72,20 +72,20 @@ Device(EC0) Method (_Q11, 0) { - Debug = "_Q11: Fn-F8 (Sleep Button) pressed" + Printf ("_Q11: Fn-F8 (Sleep Button) pressed") Notify(SLPB, 0x80) } Method (_Q12, 0) { - Debug = "_Q12: Fn-F9 (Display Switch) pressed" + Printf ("_Q12: Fn-F9 (Display Switch) pressed") Notify (\_SB.PCI0.GFX0, 0x82) // TLST = 1 } Method (_Q30, 0) { - Debug = "_Q30: AC In/Out" + Printf ("_Q30: AC In/Out") Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery // Notify the Batteries @@ -95,13 +95,13 @@ Device(EC0) Method (_Q31, 0) { - Debug = "_Q31: LID Open/Close" + Printf ("_Q31: LID Open/Close") Notify(LID0, 0x80) } Method (_Q32, 0) { - Debug = "_Q32: Battery 1 In/Out" + Printf ("_Q32: Battery 1 In/Out") If (ECON) { Local0 = P62S If (~Local0) { @@ -112,7 +112,7 @@ Device(EC0) Method (_Q33, 0) { - Debug = "_Q33: Battery 2 In/Out" + Printf ("_Q33: Battery 2 In/Out") If (ECON) { Local0 = P63S If (~Local0) { @@ -123,33 +123,33 @@ Device(EC0) Method (_Q34, 0) { - Debug = "_Q34: LPT/FDD" + Printf ("_Q34: LPT/FDD") // PHSS(0x70) } Method (_Q35, 0) { - Debug = "_Q35: Processor is hot" + Printf ("_Q35: Processor is hot") } Method (_Q36, 0) { - Debug = "_Q36: Thermal Warning" + Printf ("_Q36: Thermal Warning") } Method (_Q37, 0) { - Debug = "_Q37: PME" + Printf ("_Q37: PME") } Method (_Q38, 0) { - Debug = "_Q38: Thermal" + Printf ("_Q38: Thermal") } Method (_Q39, 0) { - Debug = "_Q39: Thermal" + Printf ("_Q39: Thermal") } // TODO Scope _SB devices for AC power, LID, Power button diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index fbe4173cb7..44bd5d1604 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -79,98 +79,98 @@ Device(EC0) Method (_Q11, 0) { - Debug = "_Q11: Fn-F8 (Sleep Button) pressed" + Printf ("_Q11: Fn-F8 (Sleep Button) pressed") Notify(SLPB, 0x80) } Method (_Q30, 0) { - Debug = "_Q30: AC In" + Printf ("_Q30: AC In") Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery } Method (_Q31, 0) { - Debug = "_Q31: AC Out" + Printf ("_Q31: AC Out") Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery } Method (_Q32, 0) { - Debug = "_Q32: Bat1 In" + Printf ("_Q32: Bat1 In") Notify(BAT1, 0x81) } Method (_Q33, 0) { - Debug = "_Q33: Bat1 Out" + Printf ("_Q33: Bat1 Out") Notify(BAT1, 0x81) } Method (_Q34, 0) { - Debug = "_Q34: Bat2 In" + Printf ("_Q34: Bat2 In") Notify(BAT2, 0x81) } Method (_Q35, 0) { - Debug = "_Q35: Bat2 Out" + Printf ("_Q35: Bat2 Out") Notify(BAT2, 0x81) } Method (_Q36, 0) { - Debug = "_Q36: Bat1 Low Power" + Printf ("_Q36: Bat1 Low Power") Notify(BAT1, 0x80) } Method (_Q37, 0) { - Debug = "_Q37: Bat1 Full Charge" + Printf ("_Q37: Bat1 Full Charge") Notify(BAT1, 0x80) } Method (_Q38, 0) { - Debug = "_Q38: Bat2 Low Power" + Printf ("_Q38: Bat2 Low Power") Notify(BAT2, 0x80) } Method (_Q39, 0) { - Debug = "_Q39: Bat2 Full Charge" + Printf ("_Q39: Bat2 Full Charge") Notify(BAT2, 0x80) } Method (_Q40, 0) { - Debug = "_Q40: LID Open/Close" + Printf ("_Q40: LID Open/Close") Notify(LID0, 0x80) } Method (_Q41, 0) { - Debug = "_Q41: Floppy on Parallel Port: Call the Museum!" + Printf ("_Q41: Floppy on Parallel Port: Call the Museum!") } Method (_Q50, 0) { - Debug = "_Q50: Processor is hot" + Printf ("_Q50: Processor is hot") Notify(\_TZ.THRM, 0x80) } Method (_Q51, 0) { - Debug = "_Q51: Processor is boiling" + Printf ("_Q51: Processor is boiling") Notify(\_TZ.THRM, 0x80) } Method (_Q52, 0) { - Debug = "_Q52: Processor is burning" + Printf ("_Q52: Processor is burning") Notify(\_TZ.THRM, 0x80) } diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl index 5c29846891..9bf50d9cf6 100644 --- a/src/mainboard/roda/rk9/acpi/thermal.asl +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -6,7 +6,7 @@ Scope (\_TZ) { /* degree Celsius to deci-Kelvin (ACPI temperature unit) */ Method(C2dK, 1) { - Add (2732, Multiply (Arg0, 10), Local0) + Local0 = 2732 + Arg0 * 10 Return (Local0) } diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 10deb02d16..27ee7c6c06 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 8ba2697475..6cb77e3aab 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -46,7 +46,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 37de919551..9386620c53 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,11 +14,11 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 7e5555b181..2291f6141e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -51,7 +51,7 @@ chip northbridge/intel/sandybridge register "gpe0_en" = "0x00800040" # Disable root port coalescing - register "pcie_port_coalesce" = "0" + register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index c18318de1d..b3378ba428 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -43,11 +44,11 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index d0574bbbed..f9710e5519 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -1,5 +1,8 @@ if BOARD_SAMSUNG_LUMPY +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index aa96153c29..22b936c839 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -7,10 +7,9 @@ #include #include #include +#include #include - -#define GPIO_SPI_WP 24 -#define GPIO_REC_MODE 42 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 @@ -20,19 +19,15 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - u8 lid = ec_read(0x83); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"}, - {100, ACTIVE_HIGH, lid & 1, "lid"}, + {100, ACTIVE_HIGH, get_lid_switch(), "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -41,6 +36,28 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +int get_lid_switch(void) +{ + return ec_read(0x83) & 1; +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -59,10 +76,10 @@ void init_bootmode_straps(void) const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 3d4ad805ce..26c882624e 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -119,11 +120,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index d804b2b974..0605b5ffa4 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -10,7 +9,6 @@ #include "onboard.h" #include #include -#include void mainboard_suspend_resume(void) { @@ -73,7 +71,6 @@ static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index d281e2e7a6..dd570762e2 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -12,4 +12,14 @@ #define BOARD_TRACKPAD_IRQ 21 #define BOARD_TRACKPAD_WAKE_GPIO 0x1b +/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ +#define GPIO_SPI_WP 24 + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + +#ifndef __ACPI__ +int get_power_switch(void); +#endif + #endif diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 2a706b992b..13b0eacbf9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -1,5 +1,8 @@ if BOARD_SAMSUNG_STUMPY +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index c8fbf9866d..b845a9172c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -6,19 +6,15 @@ #include #include #include +#include #include - -#define GPIO_SPI_WP 68 -#define GPIO_REC_MODE 42 +#include "onboard.h" #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1 void fill_lb_gpios(struct lb_gpios *gpios) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - struct lb_gpio chromeos_gpios[] = { /* Recovery: GPIO42 = CHP3_REC_MODE# */ {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), @@ -28,7 +24,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {100, ACTIVE_HIGH, 1, "lid"}, /* Power Button */ - {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, + {101, ACTIVE_LOW, get_power_switch(), "power"}, /* Did we load the VGA Option ROM? */ /* -1 indicates that this is a pseudo GPIO */ @@ -37,6 +33,23 @@ void fill_lb_gpios(struct lb_gpios *gpios) lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + int get_write_protect_state(void) { const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); @@ -55,10 +68,11 @@ void init_bootmode_straps(void) const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (get_gpio(GPIO_SPI_WP)) + if (raw_write_protect_state()) flags |= (1 << FLAG_SPI_WP); + /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!get_gpio(GPIO_REC_MODE)) + if (raw_recovery_mode_switch()) flags |= (1 << FLAG_REC_MODE); pci_s_write_config32(dev, SATA_SP, flags); diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index d18da567ae..dfb1f4d09b 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -104,11 +105,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 6291d60993..3b6727b057 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -4,14 +4,12 @@ #include #include #include -#include // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(struct device *dev) { - dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/onboard.h b/src/mainboard/samsung/stumpy/onboard.h new file mode 100644 index 0000000000..b89c20c18c --- /dev/null +++ b/src/mainboard/samsung/stumpy/onboard.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef STUMPY_ONBOARD_H +#define STUMPY_ONBOARD_H + +/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ +#define GPIO_REC_MODE 42 + +/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ +#define GPIO_SPI_WP 68 + +int get_power_switch(void); + +#endif diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 876f9207bc..d5f6fda26b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -14,7 +14,7 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" diff --git a/src/mainboard/scaleway/tagada/acpi/thermal.asl b/src/mainboard/scaleway/tagada/acpi/thermal.asl deleted file mode 100644 index 7425afb7b8..0000000000 --- a/src/mainboard/scaleway/tagada/acpi/thermal.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - // Thermal Zone - -Scope (\_TZ) -{ -} diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index e8dcb787a3..9eae08e0f1 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -15,9 +15,6 @@ DefinitionBlock( #include "acpi/platform.asl" #include "acpi/mainboard.asl" - // Thermal Handler - #include "acpi/thermal.asl" - // global NVS and variables #include diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c index 6d5d3ff4fd..bb0a385f7e 100644 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ b/src/mainboard/scaleway/tagada/ramstage.c @@ -83,5 +83,5 @@ void mainboard_add_dimm_info( int channel, int dimm, int index) { /* Mainboard only has DDR4 DIMM slots */ - mem_info->dimm[index].mod_type = SPD_UDIMM; + mem_info->dimm[index].mod_type = DDR4_SPD_UDIMM; } diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c index f041b6f7e2..e64356ef31 100644 --- a/src/mainboard/scaleway/tagada/romstage.c +++ b/src/mainboard/scaleway/tagada/romstage.c @@ -25,7 +25,7 @@ void mainboard_config_gpios(void) num = ARRAY_SIZE(tagada_gpio_config); if ((!table) || (!num)) { - printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n"); + printk(BIOS_ERR, "No valid GPIO table found!\n"); return; } diff --git a/src/mainboard/siemens/chili/Kconfig b/src/mainboard/siemens/chili/Kconfig index a4bd180223..f6e4914ba0 100644 --- a/src/mainboard/siemens/chili/Kconfig +++ b/src/mainboard/siemens/chili/Kconfig @@ -17,13 +17,11 @@ config BOARD_SIEMENS_CHILI_COMMON select SOC_INTEL_CANNONLAKE_PCH_H select SOC_INTEL_COFFEELAKE -config BOARD_SIEMENS_CHILI_BASE_OPTIONS - bool +config BOARD_SIEMENS_CHILI_BASE select BOARD_SIEMENS_CHILI_COMMON select DRIVERS_UART_8250IO -config BOARD_SIEMENS_CHILI_CHILI_OPTIONS - bool +config BOARD_SIEMENS_CHILI_CHILI select BOARD_SIEMENS_CHILI_COMMON select DRIVERS_I2C_LM96000 select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/siemens/chili/Kconfig.name b/src/mainboard/siemens/chili/Kconfig.name index 1c8dab5f7f..ac4e31eef4 100644 --- a/src/mainboard/siemens/chili/Kconfig.name +++ b/src/mainboard/siemens/chili/Kconfig.name @@ -4,8 +4,6 @@ comment "CHILI" config BOARD_SIEMENS_CHILI_BASE bool "-> Base board" - select BOARD_SIEMENS_CHILI_BASE_OPTIONS config BOARD_SIEMENS_CHILI_CHILI bool "-> Chili (AiO)" - select BOARD_SIEMENS_CHILI_CHILI_OPTIONS diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 7ac8764b60..24e61dcf95 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -229,7 +229,7 @@ static void mainboard_final(void *chip_info) dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); if (dev) { uint32_t reg; - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 20d44bb100..0d1cc46c11 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -72,7 +72,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY register "pcie_rp_clkreq_pin[2]" = "0" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 3e062a4e42..af1a572631 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config CBFS_SIZE default 0xb4e000 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 1749636157..6c17d63298 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,7 +70,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" @@ -97,7 +99,7 @@ chip soc/intel/apollolake end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 off end # - I2C 0 + device pci 16.0 on end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 device pci 16.3 on # - I2C 3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 45cfd850f8..449230f44b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -67,7 +67,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 6cf02abe24..53729c2e4c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config UART_FOR_CONSOLE default 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 6f37848238..58791f3f10 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -51,7 +51,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 877470fd96..00d65ce2ff 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config CBFS_SIZE default 0xb4e000 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 2500e08670..c4c2e3df9a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,7 +70,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 812c4af714..af8d058ee6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e058fdeb64..f75dc1cd86 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,7 +41,9 @@ chip soc/intel/apollolake device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index 90881aac4f..ef8373ecc4 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -11,6 +11,7 @@ config BOARD_SIEMENS_BASEBOARD_MC_EHL select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM select TPM_MEASURED_BOOT + select TPM_MEASURED_BOOT_INIT_BOOTBLOCK select USE_SIEMENS_HWILIB source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig" @@ -34,4 +35,7 @@ config DEVICETREE config DIMM_SPD_SIZE default 512 +config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN + default y + endif # BOARD_SIEMENS_BASEBOARD_MC_EHL diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index e64dbda54f..5c8f5849df 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -114,6 +115,23 @@ static void wait_for_legacy_dev(void *unused) printk(BIOS_NOTICE, "done!\n"); } +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Disable CPU power states (C-states) */ + params->Cx = 0; + + /* Set maximum package C-state to PkgC0C1 */ + params->PkgCStateLimit = 0; + + /* Disable P-States */ + params->MaxRatio = 0; + + /* Disable PMC low power modes */ + params->PmcLpmS0ixSubStateEnableMask = 0; + params->PmcV1p05PhyExtFetControlEn = 0; + params->PmcV1p05IsExtFetControlEn = 0; +} + static void mainboard_init(void *chip_info) { const struct pad_config *pads; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index f93e0affe8..82e20900a8 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -33,4 +33,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) } /* Initialize variant specific configurations */ memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, false); + + /* Enable Row-Hammer prevention */ + memupd->FspmConfig.RhPrevention = 1; } diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig index fbee7b0ede..0b0ffe5c4b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 select INTEL_LPSS_UART_FOR_CONSOLE + select NC_FPGA_POST_CODE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" @@ -12,4 +13,19 @@ config UART_FOR_CONSOLE int default 2 +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + endif # BOARD_SIEMENS_MC_EHL1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc index e011999940..30363634e6 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc @@ -4,6 +4,8 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +all-$(CONFIG_NC_FPGA_POST_CODE) += post.c + SPD_SOURCES = mc_ehl1 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index be98a15700..87b455fd83 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -12,13 +12,9 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ @@ -51,39 +47,35 @@ chip soc/intel/elkhartlake register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[2]" = "true" register "PcieRpLtrDisable[3]" = "true" - register "PcieRpLtrDisable[4]" = "true" - register "PcieRpLtrDisable[5]" = "true" + register "PcieRpLtrDisable[6]" = "true" # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" @@ -120,8 +112,8 @@ chip soc/intel/elkhartlake }" register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" @@ -138,108 +130,37 @@ chip soc/intel/elkhartlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 08.0 off end # GNA - device pci 09.0 off end # CPU Intel Trace Hub - - device pci 10.0 off end # I2C6 - device pci 10.1 off end # I2C7 - device pci 10.5 on end # Integrated Error Handler - - device pci 11.0 off end # Intel PSE UART0 - device pci 11.1 off end # Intel PSE UART1 - device pci 11.2 off end # Intel PSE UART2 - device pci 11.3 off end # Intel PSE UART3 - device pci 11.4 off end # Intel PSE UART4 - device pci 11.5 off end # Intel PSE UART5 - device pci 11.6 off end # Intel PSE IS20 - device pci 11.7 off end # Intel PSE IS21 - - device pci 12.0 off end # GSPI2 - device pci 12.3 on end # Management Engine UMA Access - device pci 12.4 on end # Management Engine PTT DMA Controller - device pci 12.5 off end # UFS0 - device pci 12.7 off end # UFS1 - - device pci 13.0 off end # Intel PSE GSPI0 - device pci 13.1 off end # Intel PSE GSPI1 - device pci 13.2 off end # Intel PSE GSPI2 - device pci 13.3 off end # Intel PSE GSPI3 - device pci 13.4 off end # Intel PSE GPIO0 - device pci 13.5 off end # Intel PSE GPIO1 device pci 14.0 on end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI (OTG) device pci 15.0 off end # I2C0 device pci 15.1 on end # I2C1 - device pci 15.2 off end # I2C2 - device pci 15.3 off end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 on end # Management Engine Interface 4 + device pci 16.0 hidden end # Management Engine Interface 1 device pci 17.0 on end # SATA - device pci 18.0 off end # Intel PSE I2C7 - device pci 18.1 off end # Intel PSE CAN0 - device pci 18.2 off end # Intel PSE CAN1 - device pci 18.3 off end # Intel PSE QEP0 - device pci 18.4 off end # Intel PSE QEP1 - device pci 18.5 off end # Intel PSE QEP2 - device pci 18.6 off end # Intel PSE QEP3 - device pci 19.0 on end # I2C4 - device pci 19.1 off end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC - device pci 1a.1 off end # SD - device pci 1a.3 off end # Intel Safety Island - - device pci 1b.0 off end # Intel PSE I2C0 - device pci 1b.1 off end # Intel PSE I2C1 - device pci 1b.2 off end # Intel PSE I2C2 - device pci 1b.3 off end # Intel PSE I2C3 - device pci 1b.4 off end # Intel PSE I2C4 - device pci 1b.5 off end # Intel PSE I2C5 - device pci 1b.6 off end # Intel PSE I2C6 device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) device pci 1c.2 on end # RP3 (pcie0 single VC) device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) - device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) - device pci 1d.0 off end # Intel PSE IPC (local host to PSE) - device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 - device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 - device pci 1d.3 off end # Intel PSE DMA0 - device pci 1d.4 off end # Intel PSE DMA1 - device pci 1d.5 off end # Intel PSE DMA2 - device pci 1d.6 off end # Intel PSE PWM - device pci 1d.7 off end # Intel PSE ADC - device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.2 off end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1e.4 on end # PCH Time-Sensitive Networking GbE - device pci 1e.6 on end # HPET - device pci 1e.7 on end # IOAPIC + device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel cAVS/HDA device pci 1f.4 on # SMBus # Enable external RTC chip chip drivers/i2c/rx6110sa @@ -257,6 +178,5 @@ chip soc/intel/elkhartlake end end device pci 1f.5 on end # PCH SPI (flash & TPM) - device pci 1f.7 off end # PCH Intel Trace Hub end end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c index 91c041756f..b6c755ac5a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -3,7 +3,7 @@ #include #include -/* Pad configuration in ramstage*/ +/* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* Community 0 - GpioGroup GPP_B */ PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c new file mode 100644 index 0000000000..c34e2539bc --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_post(uint8_t value) +{ + nc_fpga_post(value); +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 451c5dd5f2..438419a233 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -12,13 +12,9 @@ chip soc/intel/elkhartlake register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ @@ -47,63 +43,47 @@ chip soc/intel/elkhartlake register "SkipCpuReplacementCheck" = "1" # PCIe root ports related UPDs - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" - register "PcieClkSrcUsage[0]" = "0x00" - register "PcieClkSrcUsage[1]" = "0x01" - register "PcieClkSrcUsage[2]" = "0x02" - register "PcieClkSrcUsage[3]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcClkReq[0]" = "0xFF" - register "PcieClkSrcClkReq[1]" = "0xFF" - register "PcieClkSrcClkReq[2]" = "0xFF" - register "PcieClkSrcClkReq[3]" = "0xFF" - register "PcieClkSrcClkReq[4]" = "0xFF" - register "PcieClkSrcClkReq[5]" = "0xFF" + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Disable all L1 substates for PCIe root ports - register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports - register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" - register "PcieRpLtrDisable[2]" = "true" - register "PcieRpLtrDisable[3]" = "true" - register "PcieRpLtrDisable[4]" = "true" - register "PcieRpLtrDisable[5]" = "true" - - # Storage (SATA/SDCARD/EMMC) related UPDs - register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" + register "PcieRpLtrDisable[6]" = "true" + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C6] = PchSerialIoDisabled, [PchSerialIoIndexI2C7] = PchSerialIoDisabled, }" @@ -111,7 +91,7 @@ chip soc/intel/elkhartlake register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoPci, - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + [PchSerialIoIndexUART2] = PchSerialIoPci, }" register "SerialIoUartDmaEnable" = "{ @@ -133,38 +113,10 @@ chip soc/intel/elkhartlake device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 08.0 off end # GNA - device pci 09.0 off end # CPU Intel Trace Hub - - device pci 10.0 off end # I2C6 - device pci 10.1 off end # I2C7 - device pci 10.5 on end # Integrated Error Handler - - device pci 11.0 off end # Intel PSE UART0 - device pci 11.1 off end # Intel PSE UART1 - device pci 11.2 off end # Intel PSE UART2 - device pci 11.3 off end # Intel PSE UART3 - device pci 11.4 off end # Intel PSE UART4 - device pci 11.5 off end # Intel PSE UART5 - device pci 11.6 off end # Intel PSE IS20 - device pci 11.7 off end # Intel PSE IS21 device pci 12.0 on end # GSPI2 - device pci 12.3 on end # Management Engine UMA Access - device pci 12.4 on end # Management Engine PTT DMA Controller - device pci 12.5 off end # UFS0 - device pci 12.7 off end # UFS1 - - device pci 13.0 off end # Intel PSE GSPI0 - device pci 13.1 off end # Intel PSE GSPI1 - device pci 13.2 off end # Intel PSE GSPI2 - device pci 13.3 off end # Intel PSE GSPI3 - device pci 13.4 off end # Intel PSE GPIO0 - device pci 13.5 off end # Intel PSE GPIO1 device pci 14.0 on end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI (OTG) device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 @@ -186,20 +138,7 @@ chip soc/intel/elkhartlake end device pci 15.3 on end # I2C3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 - device pci 16.5 on end # Management Engine Interface 4 - - device pci 17.0 on end # SATA - - device pci 18.0 off end # Intel PSE I2C7 - device pci 18.1 off end # Intel PSE CAN0 - device pci 18.2 off end # Intel PSE CAN1 - device pci 18.3 off end # Intel PSE QEP0 - device pci 18.4 off end # Intel PSE QEP1 - device pci 18.5 off end # Intel PSE QEP2 - device pci 18.6 off end # Intel PSE QEP3 + device pci 16.0 hidden end # Management Engine Interface 1 device pci 19.0 on end # I2C4 device pci 19.1 on end # I2C5 @@ -207,51 +146,25 @@ chip soc/intel/elkhartlake device pci 1a.0 on end # eMMC device pci 1a.1 on end # SD - device pci 1a.3 off end # Intel Safety Island - device pci 1b.0 off end # Intel PSE I2C0 - device pci 1b.1 off end # Intel PSE I2C1 - device pci 1b.2 off end # Intel PSE I2C2 - device pci 1b.3 off end # Intel PSE I2C3 - device pci 1b.4 off end # Intel PSE I2C4 - device pci 1b.5 off end # Intel PSE I2C5 - device pci 1b.6 off end # Intel PSE I2C6 - - device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) - device pci 1c.2 on end # RP3 (pcie0 single VC) - device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) - device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 - device pci 1d.3 off end # Intel PSE DMA0 - device pci 1d.4 off end # Intel PSE DMA1 - device pci 1d.5 off end # Intel PSE DMA2 - device pci 1d.6 off end # Intel PSE PWM - device pci 1d.7 off end # Intel PSE ADC device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.2 off end # GSPI0 - device pci 1e.3 off end # GSPI1 device pci 1e.4 on end # PCH Time-Sensitive Networking GbE - device pci 1e.6 on end # HPET - device pci 1e.7 on end # IOAPIC device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 off end # Intel cAVS/HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI (flash & TPM) - device pci 1f.7 off end # PCH Intel Trace Hub end end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c index b979380d92..0dfd2d8a5a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/starlabs/Kconfig b/src/mainboard/starlabs/Kconfig new file mode 100644 index 0000000000..4df05881d1 --- /dev/null +++ b/src/mainboard/starlabs/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_STARLABS + +choice + prompt "Mainboard model" + +source "src/mainboard/starlabs/*/Kconfig.name" + +endchoice + +source "src/mainboard/starlabs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Star Labs" + +endif # VENDOR_STARLABS diff --git a/src/mainboard/starlabs/Kconfig.name b/src/mainboard/starlabs/Kconfig.name new file mode 100644 index 0000000000..7aab0da2b9 --- /dev/null +++ b/src/mainboard/starlabs/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_STARLABS + bool "Star Labs" diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig new file mode 100644 index 0000000000..6fe3446e93 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -0,0 +1,95 @@ +config BOARD_STARLABS_LABTOP_SERIES + def_bool n + select DRIVERS_I2C_HID + select EC_STARLABS_ITE + select EC_STARLABS_FAN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SYSTEM_TYPE_LAPTOP + +config BOARD_STARLABS_STARBOOK_TGL + select BOARD_ROMSIZE_KB_16384 + select BOARD_STARLABS_LABTOP_SERIES + select DRIVERS_INTEL_USB4_RETIMER + select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_FAN + select EC_STARLABS_NEED_ITE_BIN + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_TIGERLAKE_S3 + select SPI_FLASH_WINBOND + +if BOARD_STARLABS_LABTOP_SERIES + +config DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config DRIVER_TPM_SPI_CHIP + default 2 + +config EC_GPE_SCI + default 0x6e if BOARD_STARLABS_STARBOOK_TGL + default 0x50 + +config EC_STARLABS_ADD_ITE_BIN + default y + +config EC_STARLABS_ITE_BIN_PATH + string + depends on EC_STARLABS_NEED_ITE_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" + +config EC_VARIANT_DIR + default "tgl" if !EC_STARLABS_MERLIN + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin" + +config MAINBOARD_DIR + default "starlabs/labtop" + +config MAINBOARD_FAMILY + string + default "B5" + +config MAINBOARD_PART_NUMBER + default "StarBook Mk V" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "StarBook" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin" + +config TIANOCORE_BOOTSPLASH_FILE + string + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +config UART_FOR_CONSOLE + default 2 + +config USE_PM_ACPI_TIMER + default n + +config VARIANT_DIR + default "tgl" + +endif diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name new file mode 100644 index 0000000000..b3a5742eb1 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -0,0 +1,4 @@ +comment "Star Labs LabTop Series" + +config BOARD_STARLABS_STARBOOK_TGL + bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc new file mode 100644 index 0000000000..71fc0cf282 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +subdirs-y += variants/$(VARIANT_DIR) + +bootblock-y += bootblock.c + +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += smbios.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl new file mode 100644 index 0000000000..5bdde36bb7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sleep.asl" +} + +/* + * This platform doesn't support SoundWire but there + * is a kernel bug in some 5.10.x releases. + * + * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More + * details can be found at https://bit.ly/3ttdffG but it appears to + * be triggered by missing SoundWire ACPI entries. + * + * Add the minimal set to make it work again. + */ +Scope (_SB.PCI0.HDAS) +{ + Device (SNDW) + { + Name (_ADR, 0x40000000) + + Name (_CID, Package (0x02) + { + "PRP0001", + "PNP0A05" + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0B) + } + } +} diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl new file mode 100644 index 0000000000..9dc818d04d --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (MPTS, 1, NotSerialized) +{ + If (Arg0) + { + RPTS (Arg0) + } +} + +Method (MWAK, 1, NotSerialized) +{ + RWAK (Arg0) + Return (0x00) +} diff --git a/src/mainboard/starlabs/labtop/board_info.txt b/src/mainboard/starlabs/labtop/board_info.txt new file mode 100644 index 0000000000..9e70dba3d6 --- /dev/null +++ b/src/mainboard/starlabs/labtop/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: LabTop +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/labtop/bootblock.c b/src/mainboard/starlabs/labtop/bootblock.c new file mode 100644 index 0000000000..ca48bb1ab2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default new file mode 100644 index 0000000000..589189f9dd --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -0,0 +1,22 @@ +# hardcoded +boot_option=Fallback +# console +debug_level=Debug +# cpu +hyper_threading=Enable +vtd=Enable +power_profile=Balanced +me_state=Disable +smi_handler=Enable +# Devices +wireless=Enable +webcam=Enable +microphone=Enable +legacy_8254_timer=Enable +usb_always_on=Disable +thunderbolt=Disable +# EC +kbl_timeout=30 seconds +fn_ctrl_swap=Disable +# southbridge +power_on_after_fail=Disable diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout new file mode 100644 index 0000000000..85ec47772c --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# Bank: 1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level +# coreboot config options: cpu +#400 8 r 0 reserved for century byte +408 1 e 1 hyper_threading +416 1 e 1 vtd +424 2 e 7 power_profile +432 1 e 5 me_state +440 4 h 0 me_state_counter +448 1 e 1 smi_handler + +# coreboot config options: Devices +504 1 e 1 wireless +512 1 e 1 webcam +520 1 e 1 microphone +528 1 e 1 legacy_8254_timer +536 1 e 1 usb_always_on +544 1 e 1 thunderbolt + +# coreboot config options: EC +600 3 e 4 kbl_timeout +608 1 e 1 fn_ctrl_swap +616 2 e 8 max_charge +624 2 e 9 fan_mode + +# coreboot config options: southbridge +800 2 e 6 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# Bank: 2 +# embedded controller settings (outside the checksummed area) +1024 8 h 1 fn_lock_state +1032 8 h 1 trackpad_state +1040 8 h 10 kbl_brightness +1048 8 h 1 kbl_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 30 seconds +4 1 1 minute +4 2 3 minutes +4 3 5 minutes +4 4 Never + +5 0 Enable +5 1 Disable + +6 0 Disable +6 1 Enable +6 2 Keep + +7 0 Power Saver +7 1 Balanced +7 2 Performance + +8 0 100% +8 1 80% +8 2 60% + +9 0 Normal +9 1 Aggressive +9 2 Quiet + +10 0 Off +10 1 Low +10 2 High +10 3 On + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl new file mode 100644 index 0000000000..ac6bc433de --- /dev/null +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + /* Tiger Lake */ + #include + #include + #include + + /* PS/2 Keyboard */ + #include + } + + #include + + /* Star Labs EC */ + #include + + Scope (\_SB) + { + /* HID Driver */ + #include + + /* Suspend Methods */ + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/labtop/hda_verb.c b/src/mainboard/starlabs/labtop/hda_verb.c new file mode 100644 index 0000000000..371ab5d5f7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define AZALIA_CODEC_ALC256 0x10ec0256 +#define AZALIA_CODEC_ALC269 0x10ec0269 + +static const u32 override_verb[] = { + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), +}; + +static void disable_microphone(u8 *base) +{ + azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb)); +} + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (viddid == AZALIA_CODEC_ALC256 || viddid == AZALIA_CODEC_ALC269) { + printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid); + if (get_uint_option("microphone", 1) == 0) + disable_microphone(base); + } +} diff --git a/src/mainboard/starlabs/labtop/include/variants.h b/src/mainboard/starlabs/labtop/include/variants.h new file mode 100644 index 0000000000..0dd41c062c --- /dev/null +++ b/src/mainboard/starlabs/labtop/include/variants.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include + +enum cmos_power_profile { + PP_POWER_SAVER = 0, + PP_BALANCED = 1, + PP_PERFORMANCE = 2, +}; +#define NUM_POWER_PROFILES 3 + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback); + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void devtree_update(void); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c new file mode 100644 index 0000000000..d394f2579d --- /dev/null +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback) +{ + const unsigned int power_profile = get_uint_option("power_profile", fallback); + return power_profile < NUM_POWER_PROFILES ? power_profile : fallback; +} + +static void init_mainboard(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/labtop/smbios.c b/src/mainboard/starlabs/labtop/smbios.c new file mode 100644 index 0000000000..b787986f9b --- /dev/null +++ b/src/mainboard/starlabs/labtop/smbios.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *smbios_mainboard_bios_version(void) +{ + return "8"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_sku(void) +{ + return CONFIG_MAINBOARD_FAMILY; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc new file mode 100644 index 0000000000..2a505c35c7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/tgl/board.fmd b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd new file mode 100644 index 0000000000..932739e1e4 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd @@ -0,0 +1,18 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 + } + SI_BIOS@0x500000 0xB00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x800 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/data.vbt b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..992a864623a6e92e61ab81204e437c5c4ab5ed1b GIT binary patch literal 8704 zcmeHMO-vg{6n?X7FOF-95h!tJLI)BNLj$Z0p~SM3^$!py{Md#fN2-KF?6#;*a0!WM zRViDE1L~!Fs45awtre+K#0mA>gL|ovda-hddg#H&DC&`0N!>TIYdhvAIHI(n@>{*# z*?DiidGF2a{O#Fk{}i1HjSNLceOHGlrv%85ZTlJTJINoKn4AgvrhGI0(TTuSx(UbO ztG2(M0VD`HX>-Z4D|BlynQ}%u>Dc`2Tq@ZcOy2%@aXwAMfe`iGxRFdH7p^ZR6LfNV z#77xkz14qbE|s9;cW%xm7d#X}WYngv{+_;mO5N}F%6+|V*>wRW9@l{9!o_-Pa40Y_ z77mU2ra}|rbRtTFp-JE5ZW@!St~uwVryWCfWb z+mT;|gai?={5cCqju*>eeImYR5tx?pDX68io;aaDvRE%Ii6~n1I1Y9@nZW$g)f{a)+8af+aD^HdVx|2rS7U}S+roxgeGx5Q zfyT{5wUnXOP*h7-r~%VMwG~56*LuNI-G!~sP+)jYfG`4RB#NP4eq_Xr@{5s@%~tRr z2a(5-W5~0}DdfAzD)N`eUn75q{0R9+jq8x zBP33O;)4#^u`-||I0o*Cd|n4M6F7nwC#b!>kh@?t0}Qqpcm6-5ciMd z2W``95onc%HKQ$9BsI490yL$XIDFotW#TQZicF2R!2V#;_=*Qxvl=g)UNw_mKZ6Ke ztX=>_Fl&6uwPno9Re15BGn0!fx69%C#<~p=MBvLQn<7<%Aa^Mn@#Tcg^hs_5UxZn^v2 z2z-TS!xgo}ymkJo9BI6NrVJ{{c6V=2ap?8g*nWhkIG1EHaZVnJKZO zti@!nkZHd&S)RmT6=fY2vfPpYiX;mPqO6`=w}e#;Ti zqzuSF5wo>qXBK7JH38H*UAAsIgTCv(7n#hIA&@cWNEq(Jve=H8`W~Cfm=B7y0S<_u zEWxyqb^rE?OBUs4>seefxTQyH#1mMm9GB)Gv&DhFcf+8myTZ-~U*Iog3;xK)3#2Br TMc9*F)1SG8|0 literal 0 HcmV?d00001 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb new file mode 100644 index 0000000000..66b8e86eb7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -0,0 +1,237 @@ +chip soc/intel/tigerlake +# CPU + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Graphics + # Not used but timings left for reference + # register "panel_cfg" = "{ + # .up_delay_ms = 2000, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 2000, // T9 + # .down_delay_ms = 500, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM + # }" + + # FSP Memory + register "CnviBtCore" = "true" + register "CnviBtAudioOffload" = "1" + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + register "TcssD3ColdDisable" = "1" + + # FSP Silicon + # Serial I/O + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Power + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "3" # 1s + register "PchPmSlpSusMinAssert" = "3" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + + # PM Util + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | + LPC_IOE_SUPERIO_2E_2F | + LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | + LPC_IOE_LGE_200" + + # PCIe Clock + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal Device + device pci 05.0 off end # IPU + device pci 06.0 off end # PEG60 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 off end # TBT_PCIe1 + device pci 07.2 off end # TBT_PCIe2 + device pci 07.3 off end # TBT_PCIe3 + device pci 08.0 on end # Gaussian Mixture Model + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on # USB xHCI + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + register "TcssAuxOri" = "0" + end + device pci 0d.1 off end # USB xDCI (OTG) + device pci 0d.2 on # TBT DMA0 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device pci 0d.3 off end # TBT + device pci 0e.0 off end # VMD + device pci 10.6 off end + device pci 10.7 off end + device pci 12.0 off end # Thermal Subsystem + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + ### USB 2.0 Devices + # Motherboard USB Type C + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" + # Motherboard USB 3.0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + # Daughterboard USB 3.0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + # Internal Webcam + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + # Daughterboard SD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + # Internal Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + + ### USB 3.0 Devices + # Motherboard USB Type C + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Motherboard USB 3.0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Daughterboard USB 3.0 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + ### Thunderbolt 4.0 Devices + # Motherboard Thunderbolt 4.0 + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # USB xDCI (OTG) + device pci 14.3 on # CNVi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 15.0 on # I2C0 + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + end + device pci 19.0 on end # I2C4 + device pci 19.1 off end # I2C5 + device pci 19.2 on end # UART #2 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (SSD x4) + register "HybridStorageMode" = "0" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "0x08" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x000c1641" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c0081" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x1200 + register "PchHdaAudioLinkHdaEnable" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c new file mode 100644 index 0000000000..09d26e8ecc --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_power_limits_config *soc_conf_2core = + &cfg->power_limits_config[POWER_LIMITS_U_2_CORE]; + + struct soc_power_limits_config *soc_conf_4core = + &cfg->power_limits_config[POWER_LIMITS_U_4_CORE]; + + struct device *nic_dev = pcidev_on_root(0x14, 3); + struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); + struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + + + /* Update PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + disable_turbo(); + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 15; + soc_conf_4core->tdp_pl2_override = 15; + break; + case PP_BALANCED: + soc_conf_2core->tdp_pl1_override = 15; + soc_conf_4core->tdp_pl1_override = 15; + soc_conf_2core->tdp_pl2_override = 25; + soc_conf_4core->tdp_pl2_override = 25; + break; + case PP_PERFORMANCE: + soc_conf_2core->tdp_pl1_override = 28; + soc_conf_4core->tdp_pl1_override = 28; + soc_conf_2core->tdp_pl2_override = 40; + soc_conf_4core->tdp_pl2_override = 40; + break; + } + + /* Enable/Disable Wireless based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + nic_dev->enabled = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable Thunderbolt based on CMOS settings */ + if (get_uint_option("thunderbolt", 1) == 0) { + cfg->UsbTcPortEn = 0; + cfg->TcssXhciEn = 0; + cfg->TcssD3ColdDisable = 0; + tbt_pci_dev->enabled = 0; + tbt_dma_dev->enabled = 0; + } +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c new file mode 100644 index 0000000000..1ba1b817ef --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* C20: UART2_RXD_R */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21: UART2_TXD_R */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* REFERENCE: EP PER SCHEMATIC */ + + /* GPD0: PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: AC_PRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# */ + PAD_NC(GPD2, NONE), + /* GPD3: SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: SIO_SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SIO_SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SIO_SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: PCH_TBT_PERST# */ + PAD_CFG_GPO(GPD7, 0, PLTRST), + /* GPD8: SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SIO_SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SIO_SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: PM_LANPHY_EN */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + + /* A0: ESPI_IO_0 */ + /* A1: ESPI_IO_1 */ + /* A2: ESPI_IO_2 */ + /* A3: ESPI_IO_3 */ + /* A4: ESPI_CS_L */ + /* A5: ESPI_CLK */ + /* A6: Not Connected(TP764) */ + /* A7: WLAN_PCM_CLK */ + PAD_NC(GPP_A7, NONE), + /* A8: WLAN_PCM_RST */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + /* A9: WLAN_PCM_CLKREQ0 */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + /* A10: WLAN_PCM_IN */ + PAD_NC(GPP_A10, NONE), + /* A11: M2_CPU_SSD_RST_N */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* A12: SATAGP_1 */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + /* A13: Not Connected */ + PAD_NC(GPP_A13, NONE), + /* A14: Not Connected */ + PAD_NC(GPP_A14, NONE), + /* A15 Not Connected */ + PAD_NC(GPP_A15, NONE), + /* A16: USB2_OCB_3 */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17: Not Connected */ + PAD_NC(GPP_A17, NONE), + /* A18: DDIB_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 Not Connected */ + PAD_NC(GPP_A19, NONE), + /* A20: Not Connected */ + PAD_NC(GPP_A20, NONE), + /* A21 Not Connected */ + PAD_NC(GPP_A21, NONE), + /* A22: Not Connected */ + PAD_NC(GPP_A22, NONE), + /* A23: TC_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* B0: CORE_VID_0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1: CORE_VID_1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2: VRALERT_N */ + PAD_NC(GPP_B2, NONE), + /* B3: Not Connected */ + PAD_NC(GPP_B3, NONE), + /* B4: Not Connected */ + PAD_NC(GPP_B4, NONE), + /* B5: Not Connected */ + PAD_NC(GPP_B5, NONE), + /* B6: Not Connected */ + PAD_NC(GPP_B6, NONE), + /* B7: Not Connected */ + PAD_NC(GPP_B7, NONE), + /* B8: Not Connected */ + PAD_NC(GPP_B8, NONE), + /* B9: PWR_MON_I2C_SDA_R */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10: PWR_MON_I2C_SCL_R */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: FPS_RST_N */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* B15: Not Connected */ + PAD_NC(GPP_B15, NONE), + /* B16: M2_PCH_SSD_PWREN */ + PAD_NC(GPP_B16, NONE), + /* B17: Not Connected */ + PAD_NC(GPP_B17, NONE), + /* B18: UF_CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + /* B19: GSPI1_CS0_FPS_N */ + PAD_NC(GPP_B19, NONE), + /* B20: GSPI1_CLK_FPS */ + PAD_NC(GPP_B20, NONE), + /* B21: GSPI1_MISO_FPS */ + PAD_NC(GPP_B21, NONE), + /* B22: GSPI1_MOSI_FPS */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* B23: CPU_CLKFREQ */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* C0: SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1: SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2: SMBALERT_N */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + /* C3: SML0_CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4: SML0_DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5: SML0ALERT_IN */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* C6: SML1_CLK */ + PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), + /* C7: SML1_DATA */ + PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), + /* C8: CLICK_PAD_INT_N */ + PAD_CFG_GPI_APIC_LOW(GPP_C8, NONE, PLTRST), + /* C9: Not Connected */ + PAD_NC(GPP_C9, NONE), + /* C10: Not Connected */ + PAD_NC(GPP_C10, NONE), + /* C11: Not Connected */ + PAD_NC(GPP_C11, NONE), + /* C12: Not Connected */ + PAD_NC(GPP_C12, NONE), + /* C13: Not Connected */ + PAD_NC(GPP_C13, NONE), + /* C14: TPM_IRQ */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* C15: TPM_RST */ + PAD_NC(GPP_C15, NONE), + /* C16: I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17: I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18: TOUCH_I2C_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19: TOUCH_I2C_CLK */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C22: Not Connected */ + PAD_NC(GPP_C22, NONE), + /* C23: WLAN_WAKE_N */ + PAD_NC(GPP_C23, NONE), + + /* D0: ACCEL1_INT */ + PAD_NC(GPP_D0, NONE), + /* D1: ACCEL2_INT */ + PAD_NC(GPP_D1, NONE), + /* D2: Not Connected */ + PAD_NC(GPP_D2, NONE), + /* D3: Not Connected */ + PAD_NC(GPP_D3, NONE), + /* D4: Not Connected */ + PAD_NC(GPP_D4, NONE), + /* D5: CLKREQ0_M2_SSD_N */ + PAD_NC(GPP_D5, NONE), + /* D6: CLKREQ1_WLAN_N */ + PAD_NC(GPP_D6, NONE), + /* D7: LAN_CLKREQ# */ + PAD_NC(GPP_D7, NONE), + /* D8: Not Connected */ + PAD_NC(GPP_D8, NONE), + /* D9: Not Connected */ + PAD_NC(GPP_D9, NONE), + /* D10: Not Connected */ + PAD_NC(GPP_D10, NONE), + /* D11: Not Connected */ + PAD_NC(GPP_D11, NONE), + /* D12: Not Connected */ + PAD_NC(GPP_D12, NONE), + /* D13: Not Connected */ + PAD_NC(GPP_D13, NONE), + /* D14: Not Connected */ + PAD_NC(GPP_D14, NONE), + /* D15: Not Connected */ + PAD_NC(GPP_D15, NONE), + /* D16: CPU_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* D17: Not Connected */ + PAD_NC(GPP_D17, NONE), + /* D18: Not Connected */ + PAD_NC(GPP_D18, NONE), + /* D19: GPPC_D_19_WFCAM_PD_N */ + PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), + + /* E0: SATAXPCIE_0_SATAGP_0 */ + PAD_NC(GPP_E0, NONE), + /* E1: Not Connected */ + PAD_NC(GPP_E1, NONE), + /* E2: Not Connected */ + PAD_NC(GPP_E2, NONE), + /* E3: FPS_INT */ + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + /* E4: Not Connected */ + PAD_NC(GPP_E4, NONE), + /* E5: Not Connected */ + PAD_NC(GPP_E5, NONE), + /* E6: THC0_SPI1_RST_N_TCH_PNL */ + PAD_NC(GPP_E6, NONE), + /* E7: EC_SMI_LP_N */ + PAD_NC(GPP_E7, NONE), + /* E8: EC_SLP_S0IX_N */ + PAD_NC(GPP_E8, NONE), + /* E9: USB2_TCP01_OC_N */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10: SPI1_TCH_PNL_CS_N */ + PAD_NC(GPP_E10, NONE), + /* E11: SPI1_CLK */ + PAD_NC(GPP_E11, NONE), + /* E12: Not Connected */ + PAD_NC(GPP_E12, NONE), + /* E13: Not Connected */ + PAD_NC(GPP_E13, NONE), + /* E14: EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: Not Connected */ + PAD_NC(GPP_E15, NONE), + /* E16: Not Connected */ + PAD_NC(GPP_E16, NONE), + /* E17: Not Connected */ + PAD_NC(GPP_E17, NONE), + /* E18: TBT_LSX0_TXD */ + PAD_NC(GPP_E18, NATIVE), + /* E19: TBT_LSX0_RXD */ + PAD_NC(GPP_E19, NATIVE), + /* E20: Not Connected */ + PAD_NC(GPP_E20, NONE), + /* E21: TBT_LSX1_RXD */ + PAD_NC(GPP_E21, NATIVE), + /* E22: Not Connected */ + PAD_NC(GPP_E22, NONE), + /* E23: Not Connected */ + PAD_NC(GPP_E23, NONE), + + /* F0: CNV_BRI_DT_BT_UART0_RTS_R */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1: CNV_BRI_RSP_BT_UART0_RX_R */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* F2: CNV_RGI_DT_BT_UART0_TX_R */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3: CNV_RGI_RSP_BT_UART0_CTS */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* F4: Not Connected */ + PAD_NC(GPP_F4, NONE), + /* F5: GPPC_F5_MODEM_CLKREQ */ + PAD_NC(GPP_F5, NONE), + /* F6: Not Connected */ + PAD_NC(GPP_F6, NONE), + /* F7: BIOS_REC */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* F8: Not Connected */ + PAD_NC(GPP_F8, NONE), + /* F9: Not Connected */ + PAD_NC(GPP_F9, NONE), + /* F10: GPPC_F_10 */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* F11: Not Connected */ + PAD_NC(GPP_F11, NONE), + /* F12: Not Connected */ + PAD_NC(GPP_F12, NONE), + /* F13: Not Connected */ + PAD_NC(GPP_F13, NONE), + /* F14: Not Connected */ + PAD_NC(GPP_F14, NONE), + /* F15: Not Connected */ + PAD_NC(GPP_F15, NONE), + /* F16: Not Connected */ + PAD_NC(GPP_F16, NONE), + /* F17: TOUCH_PANEL_RESET_N */ + PAD_NC(GPP_F17, NONE), + /* F18: TOUCH_PANEL_INT_N */ + PAD_NC(GPP_F18, NONE), + /* F19: Not Connected */ + PAD_NC(GPP_F19, NONE), + /* F20: Not Connected */ + PAD_NC(GPP_F20, NONE), + /* F21: Not Connected */ + PAD_NC(GPP_F21, NONE), + /* F22: Not Connected */ + PAD_NC(GPP_F22, NONE), + /* F23: Not Connected */ + PAD_NC(GPP_F23, NONE), + + /* H0: GPPC_H0_M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + /* H1: GPPC_H_1 */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + /* H2: GPPC_H_2 */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + /* H3: Not Connected */ + PAD_NC(GPP_H3, NONE), + /* H4: GSENSOR_I2C_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5: GSENSOR_I2C_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6: Not Connected */ + PAD_NC(GPP_H6, NONE), + /* H7: Not Connected */ + PAD_NC(GPP_H7, NONE), + /* H8: Not Connected */ + PAD_NC(GPP_H8, NONE), + /* H9: Not Connected */ + PAD_NC(GPP_H9, NONE), + /* H10: Not Connected */ + PAD_NC(GPP_H10, NONE), + /* H11: Not Connected */ + PAD_NC(GPP_H11, NONE), + /* H12: Not Connected */ + PAD_NC(GPP_H12, NONE), + /* H13: Not Connected */ + PAD_NC(GPP_H13, NONE), + /* H14: Not Connected */ + PAD_NC(GPP_H14, NONE), + /* H15: Not Connected */ + PAD_NC(GPP_H15, NONE), + /* H16: DDIB_DDC_SCL */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17: DDIB_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: CPU_C10_GATE_N */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19: UART_BT_WAKE_N */ + PAD_NC(GPP_H19, NONE), + /* H20: Not Connected */ + PAD_NC(GPP_H20, NONE), + /* H21: Not Connected */ + PAD_NC(GPP_H21, NONE), + /* H22: Not Connected */ + PAD_NC(GPP_H22, NONE), + /* H23: Not Connected */ + PAD_NC(GPP_H23, NONE), + + /* R0: HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1: HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* R2: HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* R3: HDA_SDI_0_SSP0_RXD */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* R4: Not Connected */ + PAD_NC(GPP_R4, NONE), + /* R5: Not Connected */ + PAD_NC(GPP_R5, NONE), + /* R6: Not Connected */ + PAD_NC(GPP_R6, NONE), + /* R7: Not Connected */ + PAD_NC(GPP_R7, NONE), + + /* S0: Not Connected */ + PAD_NC(GPP_S0, NONE), + /* S1: Not Connected */ + PAD_NC(GPP_S1, NONE), + /* S2: Not Connected */ + PAD_NC(GPP_S2, NONE), + /* S3: Not Connected */ + PAD_NC(GPP_S3, NONE), + /* S4: Not Connected */ + PAD_NC(GPP_S4, NONE), + /* S5: Not Connected */ + PAD_NC(GPP_S5, NONE), + /* S6: Not Connected */ + PAD_NC(GPP_S6, NONE), + /* S7: Not Connected */ + PAD_NC(GPP_S7, NONE), + + /* T2: Not Connected */ + PAD_NC(GPP_T2, NONE), + /* T3: Not Connected */ + PAD_NC(GPP_T3, NONE), + + /* U4: Not Connected */ + PAD_NC(GPP_U4, NONE), + /* U5: Not Connected */ + PAD_NC(GPP_U5, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c new file mode 100644 index 0000000000..7903d96259 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec1200, /* Subsystem ID */ + 38, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID: 0x10EC1200 */ + AZALIA_SUBVENDOR(0, 0x10ec1200), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x40700001), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* Reset to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* Reset Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 Default 1 */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 Default 2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Default 3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 Default 4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* Jack Detection */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + + /* Disable Microphone Security */ + 0x0205000D, + 0x0204A020, + + /* Enable ADC clock */ + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + + /* + * Equalizer: + * + * AGC + * Threshold: - 6.00 dB + * Front Boost: + 6.00 dB + * Post Boost: + 6.00 dB + * + * Low Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: + 4.00 dB + * + * Band Pass Filter 1 + * Fc: 240Hz + * BW: 400Hz + * Gain: - 4.00 dB + * + * Band Pass Filter 2 + * Fc: 16000Hz + * BW: 1000Hz + * Gain: + 12.00 dB + * + * High Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: - 4.00 dB + * + * Class D Amp + * Power: 2.5W + * Resistance: 4ohms + * + * EQ Output + * Left: + 0.00 dB + * Right: + 0.00 dB + * + * VARQ + * Q: 0.707 + */ + + 0x05350000, + 0x053404DA, + 0x0535001d, + 0x05340800, + + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341F7A, + + 0x05350004, + 0x0534FA18, + 0x0535000F, + 0x0534C295, + + 0x05350010, + 0x05341D73, + 0x05350011, + 0x0534FA18, + + 0x05350012, + 0x05341E08, + 0x05350013, + 0x05341C10, + + 0x05350014, + 0x05342FB2, + 0x0535001B, + 0x05341F2C, + + 0x0535001C, + 0x0534095C, + 0x05450000, + 0x05440000, + + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + 0x05450003, + 0x05441F7A, + 0x05450004, + 0x0544FA18, + + 0x0545000F, + 0x0544C295, + 0x05450010, + 0x05441D73, + + 0x05450011, + 0x0544FA18, + 0x05450012, + 0x05441E08, + + 0x05450013, + 0x05441C10, + 0x05450014, + 0x05442FB2, + + 0x0545001B, + 0x05441F2C, + 0x0545001C, + 0x0544095C, + + 0x05350000, + 0x0534C4DA, + 0x02050038, + 0x02044901, + + 0x02050013, + 0x0204422F, + 0x02050016, + 0x02044E50, + + 0x02050012, + 0x0204EBC4, + 0x02050020, + 0x020451FF, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c new file mode 100644 index 0000000000..1d65c61ba5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + }; + + const bool half_populated = false; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; + + const uint8_t ht = get_uint_option("hyper_threading", + mupd->FspmConfig.HyperThreading); + mupd->FspmConfig.HyperThreading = ht; + + /* Enable/Disable Thunderbolt based on CMOS settings */ + if (get_uint_option("thunderbolt", 1) == 0) { + mupd->FspmConfig.VtdItbtEnable = 0; + mupd->FspmConfig.VtdBaseAddress[3] = 0; + mupd->FspmConfig.TcssDma0En = 0; + mupd->FspmConfig.TcssItbtPcie0En = 0; + } +}; diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 28c7c1a20f..24e67c7682 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -2,6 +2,9 @@ if BOARD_SUPERMICRO_X10SLM_PLUS_F +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index f7711c05ca..01dab69989 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index eb4a65e750..10606559bd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -18,6 +18,9 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_FAMILY string default "Supermicro_X11_LGA1151_SERIES" diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index 40b42137b2..469b7916a7 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -1,5 +1,8 @@ if BOARD_SUPERMICRO_X9SCL +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 49fcff5a6d..284d8f3204 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) - register "pcie_port_coalesce" = "1" + register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 27c9c21934..941972b1a1 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 endif # NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4aed96b50e..2d9597eba6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -625,7 +625,7 @@ static void cpu_bus_scan(struct device *dev) /* There is only one node for fam14, but there may be multiple cores. */ cpu = pcidev_on_root(0x18, 0); if (!cpu) - printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0, 0x18); cores_found = (pci_read_config32(pcidev_on_root(0x18, 0x3), 0xe8) >> 12) & 3; @@ -818,13 +818,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 3b66f56fa5..5bb7cca300 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 7af65389f3..587e737846 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -13,7 +13,7 @@ static void iommu_read_resources(struct device *dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fe567362f8..bd0a5c8e86 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -737,7 +737,7 @@ static void domain_set_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -900,13 +900,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index ee02865eed..8cf919a2d5 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 21b4d69647..3d5313a333 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -750,7 +750,7 @@ static void domain_set_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -922,13 +922,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index c1fc9a882e..94abb93177 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select LEGACY_SMP_INIT if NORTHBRIDGE_AMD_PI_00730F01 @@ -10,10 +9,10 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index ef478dda15..2de53d061c 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -12,7 +12,7 @@ static void iommu_read_resources(struct device *dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); res->size = 512 * 1024; res->align = log2(res->size); @@ -21,14 +21,9 @@ static void iommu_read_resources(struct device *dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, - .set_resources = iommu_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f1c5e23657..c6614404a9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -29,8 +29,6 @@ #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6) -static unsigned int node_nums; -static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; static struct device *__f1_dev[MAX_NODE_NUMS]; static struct device *__f2_dev[MAX_NODE_NUMS]; @@ -42,6 +40,23 @@ static struct device *get_node_pci(u32 nodeid, u32 fn) return pcidev_on_root(DEV_CDB + nodeid, fn); } +static struct device *get_mc_dev(void) +{ + return pcidev_on_root(DEV_CDB, 0); +} + +static unsigned int get_node_nums(void) +{ + static unsigned int node_nums; + + if (node_nums) + return node_nums; + + node_nums = ((pci_read_config32(get_mc_dev(), 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + + return node_nums; +} + static void get_fx_devs(void) { int i; @@ -164,6 +179,9 @@ static void nb_read_resources(struct device *dev) static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; + unsigned int sblink; + + sblink = (pci_read_config32(get_mc_dev(), 0x64)>>8) & 7; // don't forget sublink1 /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ @@ -664,8 +682,8 @@ static const struct pci_driver family10_northbridge __pci_driver = { static void fam16_finalize(void *chip_info) { struct device *dev; - u32 value; dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ @@ -680,30 +698,24 @@ static void fam16_finalize(void *chip_info) /* Select GPP link core IO Link Strap Control register 0xB0 */ pci_write_config32(dev, 0xE0, 0x014000B0); - value = pci_read_config32(dev, 0xE4); /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ - value |= PCIE_CAP_AER | PCIE_CAP_ACS; - pci_write_config32(dev, 0xE4, value); + pci_or_config32(dev, 0xE4, PCIE_CAP_AER | PCIE_CAP_ACS); /* Select GPP link core Wrapper register 0x00 (undocumented) */ pci_write_config32(dev, 0xE0, 0x01300000); - value = pci_read_config32(dev, 0xE4); /* * Enable ACS capabilities straps including sub-items. From lspci it * looks like these bits enable: Source Validation and Translation * Blocking */ - value |= (BIT(24) | BIT(25) | BIT(26)); - pci_write_config32(dev, 0xE4, value); + pci_or_config32(dev, 0xE4, (BIT(24) | BIT(25) | BIT(26))); /* disable No Snoop */ dev = pcidev_on_root(1, 1); if (dev != NULL) { - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); + pci_and_config32(dev, 0x60, ~(1 << 11)); } } @@ -724,7 +736,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) int i; mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk; u32 hole; if (!get_dram_base_limit(i, &basek, &limitk)) @@ -742,7 +754,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) */ if (mem_hole.node_id == -1) { resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t base_k, limit_k; if (!get_dram_base_limit(i, &base_k, &limit_k)) continue; // no memory on this node @@ -770,7 +782,7 @@ static void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ - mmio_basek = bsp_topmem() >> 10; + mmio_basek = amd_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -788,7 +800,7 @@ static void domain_read_resources(struct device *dev) #endif idx = 0x10; - for (i = 0; i < node_nums; i++) { + for (i = 0; i < get_node_nums(); i++) { resource_t basek, limitk, sizek; // 4 1T if (!get_dram_base_limit(i, &basek, &limitk)) @@ -826,7 +838,7 @@ static void domain_read_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -856,152 +868,42 @@ static struct device_operations pci_domain_ops = { .acpi_name = domain_acpi_name, }; -static void sysconf_init(struct device *dev) // first node +static void pre_mp_init(void) { - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); } -static void cpu_bus_scan(struct device *dev) +static int get_cpu_count(void) { - struct bus *cpu_bus; - struct device *dev_mc; - int i,j; - int coreid_bits; - int core_max = 0; - unsigned int ApicIdCoreIdSize; - unsigned int core_nums; - int siblings = 0; - unsigned int family; - u32 modules = 0; - int ioapic_count = 0; + uint8_t siblings = cpuid_ecx(0x80000008) & 0xff; - /* For binaryPI there is no multiprocessor configuration, the number of - * modules will always be 1. */ - modules = 1; - ioapic_count = CONFIG_NUM_OF_IOAPICS; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - struct device *cdb_dev; - unsigned int devn; - struct bus *pbus; - - devn = DEV_CDB + i; - pbus = dev_mc->bus; - - /* Find the cpu's pci device */ - cdb_dev = pcidev_on_root(devn, 0); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = pcidev_on_root(devn, 0); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - - add_more_links(cdb_dev, 4); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 1) { //f10 - u32 dword; - cdb_dev = pcidev_on_root(devn, 3); - dword = pci_read_config32(cdb_dev, 0xe8); - siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); - } else if (family == 7) {//f16 - cdb_dev = pcidev_on_root(devn, 5); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - siblings = 0; //default one core - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - u32 lapicid_start = 0; - - /* - * APIC ID calculation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply APIC enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - if ((node_nums * core_max) + ioapic_count >= 0x10) { - lapicid_start = (ioapic_count - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); - } - u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", - i, j, apic_id); - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } + return siblings + 1; } -static void cpu_bus_init(struct device *dev) +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; + +void mp_init_cpus(struct bus *cpu_bus) { - initialize_cpus(dev->link_list); + /* TODO: Handle mp_init_with_smm failure? */ + mp_init_with_smm(cpu_bus, &mp_ops); + + /* The flash is now no longer cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); } static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, + .init = mp_cpu_bus_init, }; static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index d9cf8aff8e..c0711eeff4 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -7,7 +7,7 @@ if NORTHBRIDGE_INTEL_E7505 config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE select LEGACY_SMP_INIT diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index e3675db2f0..3f632a1a6f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -23,10 +23,10 @@ config VGA_BIOS_ID string default "8086,2a42" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index 43d73e922d..c4636beb3e 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,7 +16,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index a9a1e8eb2d..eb1aa0a277 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,17 +21,17 @@ void bootblock_early_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 6e3ea2c7a3..e9110643f4 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include "gm45.h" diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 178149d119..77bbe3f553 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -151,7 +151,7 @@ static void gma_func0_init(struct device *dev) intel_gma_init_igd_opregion(); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (gtt_res == NULL) return; mmio = res2mmio(gtt_res, 0, 0); diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index a961481188..4199f8bb1d 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -8,7 +8,7 @@ #include "gm45.h" -void init_iommu() +void init_iommu(void) { /* FIXME: proper test? */ int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d990497a46..6e505da7bc 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -32,8 +32,8 @@ void get_gmch_info(sysinfo_t *sysinfo) { sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && - (sysinfo->stepping != STEPPING_CONVERSION_A1)) - die("Unknown stepping.\n"); + (sysinfo->stepping != STEPPING_CONVERSION_A1)) + die("Unknown stepping.\n"); if (sysinfo->stepping <= STEPPING_B3) printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); else @@ -195,8 +195,7 @@ void enter_raminit_or_reset(void) if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ /* Ignore S4-assertion-width violation like original BIOS. */ - printk(BIOS_WARNING, - "WARNING: Ignoring S4-assertion-width violation.\n"); + printk(BIOS_WARNING, "Ignoring S4-assertion-width violation.\n"); /* Bit2 is R/WC, so it will clear itself below. */ } diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index b87380a076..744c92bd70 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -42,8 +41,6 @@ void mainboard_romstage_entry(void) /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); - enable_lapic(); - /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 61c201a1cb..50acb09a91 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -32,10 +32,10 @@ config VGA_BIOS_ID string default "8086,0166" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 565b2d26ec..bc43a81e87 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -99,7 +99,7 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Debug = "Set TDP Down" + Printf ("Set TDP Down") /* Set CTC */ CTCS = CTCD @@ -135,7 +135,7 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Debug = "Set TDP Nominal" + Printf ("Set TDP Nominal") /* Set PL1 */ PL1V = CTDN @@ -173,7 +173,7 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Debug = "Enable PL1 Limit" + Printf ("Enable PL1 Limit") /* Set _PPC to LFM */ Local0 = PSSS (LFM_) @@ -201,7 +201,7 @@ Scope (\_SB.PCI0.MCHC) Return (0) } - Debug = "Disable PL1 Limit" + Printf ("Disable PL1 Limit") /* Clear PL1 CLAMP bit */ PL1C = 0 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 7dfae9fa94..513e960a09 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -125,7 +125,7 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -161,7 +161,7 @@ Method (_CRS, 0, Serialized) } PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = (PMAX - PMIN) + 1 Return (MCRS) @@ -178,7 +178,7 @@ Device (PDRC) Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 1336582889..03a715fa63 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index ccabb8cfa3..212b395a78 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -178,7 +178,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) { printk(BIOS_DEBUG, "GT Power Management Init\n"); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 338b4d0c41..e1a933766a 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -234,7 +235,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) memset(mem_info, 0, sizeof(struct memory_info)); - const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; + const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < NUM_CHANNELS; ch++) { const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); @@ -246,7 +247,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_frequency; + dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); dimm->channel_num = ch; dimm->dimm_num = d_num; @@ -260,7 +261,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); - dimm->mod_type = SPD_SODIMM; + dimm->mod_type = DDR3_SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } @@ -349,9 +350,9 @@ void perform_raminit(const int s3resume) .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 1bfbfe5ca0..558f41fd43 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -51,7 +52,7 @@ static void minihd_init(struct device *dev) int codec_mask, i; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -78,8 +79,8 @@ static void minihd_init(struct device *dev) if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, sizeof(minihd_verb_table), - minihd_verb_table); + azalia_codec_init(base, i, minihd_verb_table, + sizeof(minihd_verb_table)); } } } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 23220976dd..fd5ffd9579 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -34,10 +34,6 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } -/* - * TODO: We could determine how many PCIe buses we need in the bar. - * For now, that number is hardcoded to a max of 64. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, @@ -251,7 +247,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) /* * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address, + * or TXT/Boot Guard related data. Rather than report a base address, * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 28a0c7903e..4980f9b7ec 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ void __weak mb_late_romstage_setup(void) /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { - enable_lapic(); - early_pch_init(); /* Perform some early chipset initialization required diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 0fcadce971..4b1638c95d 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -2,7 +2,7 @@ config NORTHBRIDGE_INTEL_I440BX bool - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE select LEGACY_SMP_INIT diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index ac19fccfc8..7a05d20317 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -35,10 +35,10 @@ config I945_LVDS for the LVDS port. A linear framebuffer is only supported for LVDS. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 683ad375a5..f935b716f6 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -40,7 +40,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 448d5e411a..1486a1b576 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -20,14 +20,16 @@ static uint32_t encode_pciexbar_length(void) void bootblock_early_northbridge_init(void) { /* - * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit - * config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final assumption is that - * no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * The "io" variant of the config access is explicitly used to setup the + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way + * all subsequent non-explicit config accesses use MCFG. This code also + * assumes that bootblock_northbridge_init() is the first thing called + * in the non-asm boot block code. The final assumption is that no + * assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do + * PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 0d014fbaf1..d094a6789f 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -73,7 +73,7 @@ static int gtt_setup(u8 *mmiobase) static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - u8 *mmiobase, unsigned int pgfx) + u8 *mmiobase, uintptr_t pgfx) { struct edid edid; struct edid_mode *mode; @@ -328,7 +328,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + EIR, 0xffffffff); if (gtt_setup(mmiobase)) { - printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + printk(BIOS_ERR, "GTT Setup Failed!!!\n"); return 0; } @@ -352,7 +352,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, if (temp & 1) printk(BIOS_INFO, "GTT Enabled\n"); else - printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + printk(BIOS_ERR, "GTT is still Disabled!!!\n"); if (CONFIG(LINEAR_FRAMEBUFFER)) { printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", @@ -373,15 +373,15 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, - u8 *mmiobase, unsigned int pgfx) + u8 *mmiobase, uintptr_t pgfx) { int i; u32 hactive, vactive; u16 reg16; u32 uma_size; - printk(BIOS_SPEW, "mmiobase %x addrport %x physbase %x\n", - (u32)mmiobase, piobase, pphysbase); + printk(BIOS_SPEW, "mmiobase %lx addrport %x physbase %x\n", + (uintptr_t)mmiobase, piobase, pphysbase); gtt_setup(mmiobase); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index e1e35e9b67..6c055e9ffe 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -61,7 +61,7 @@ static void mch_domain_read_resources(struct device *dev) /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - cbmem_topk = ((uint32_t)cbmem_top() / KiB); + cbmem_topk = ((uintptr_t)cbmem_top() / KiB); delta_cbmem = tomk_stolen - cbmem_topk; tomk_stolen -= delta_cbmem; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 03419ca7b7..e168f7ce94 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -70,7 +70,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command) udelay(1); } -static void ram_read32(u32 offset) +static void ram_read32(uintptr_t offset) { PRINTK_DEBUG(" RAM read: %08x\n", offset); @@ -2121,7 +2121,7 @@ static void sdram_power_management(struct sys_info *sysinfo) { u16 reg16; u32 reg32; - int integrated_graphics = 1; + bool integrated_graphics = true; int i; if (!(pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))) diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index b95170f7c5..ca54bad7f8 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -10,7 +10,8 @@ */ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo) { - u32 reg32, addr; + u32 reg32; + uintptr_t addr; int i; mchbar_setbits32(C0DRC1 + channel_offset, 1 << 6); diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index efcf0d62ba..0a61780cdc 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -30,8 +29,6 @@ void mainboard_romstage_entry(void) int s3resume = 0; u8 spd_map[4] = {}; - enable_lapic(); - mainboard_lpc_decode(); if (mchbar_read16(SSKPD) == 0xcafe) { diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index 9fb776980b..a614058efb 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -39,10 +39,10 @@ config DCACHE_BSP_STACK_SIZE The amount of anticipated stack usage in CAR by bootblock and other stages. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 256 config INTEL_GMA_BCLV_OFFSET diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 5e6ad52180..d2e5eb1036 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -119,7 +119,7 @@ Device (MCHC) Return (0) } - Debug = "Set TDP Down" + Printf ("Set TDP Down") /* Set CTC */ CTCS = CTCD @@ -155,7 +155,7 @@ Device (MCHC) Return (0) } - Debug = "Set TDP Nominal" + Printf ("Set TDP Nominal") /* Set PL1 */ PL1V = CTDN diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 098dd13ab8..b4bd8e9f52 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 241eb43021..58f49da1d3 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -10,7 +10,7 @@ static uint32_t encode_pciexbar_length(void) { /* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */ - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 6 << 1; case 64: return 7 << 1; @@ -27,7 +27,7 @@ void bootblock_early_northbridge_init(void) */ const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0); pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 1e4d0dcc10..b765417274 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -106,10 +106,6 @@ void ironlake_early_initialization(int chipset_type) early_cpu_init(); - pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* Magic for S3 resume. Must be done early. */ if (s3_resume) { mchbar_clrsetbits32(0x1e8, 1, 6); diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 7d08f3130d..a0325d12eb 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -140,7 +140,7 @@ static void gma_func0_init(struct device *dev) if (!CONFIG(NO_GFX_INIT)) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; @@ -171,7 +171,7 @@ static void gma_read_resources(struct device *dev) struct resource *res; /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); + res = probe_resource(dev, PCI_BASE_ADDRESS_2); if (res == NULL) { printk(BIOS_DEBUG, "gma: memory resource not found.\n"); return; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 3fb1c107f5..be5f11ba14 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,8 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ -#define DEFAULT_HECIBAR ((u8 *)0xfed17000) - /* * D1:F0 PEG */ @@ -21,7 +19,7 @@ #include "memmap.h" -#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1) +#define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) #include diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index b5ad824623..2137e3b419 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -48,7 +49,7 @@ static void add_fixed_resources(struct device *dev, int index) 0xff800000-0xffffffff ROM. */ resource = new_resource(dev, index++); - resource->base = (resource_t) 0xfed00000; + resource->base = (resource_t) HPET_BASE_ADDRESS; resource->size = (resource_t) 0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index e0e6f666b6..81621d2562 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include #include @@ -495,10 +497,20 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8) if (x1c04 != x1804 && x2ca8 == 0) mchbar_setbits8(0x2ca8, 1 << 0); + reg32 = 0x3000000; + if (info->revision >= 0x18 && qpi_pll_ratio <= 12) { + /* Get TDP limit in 1/8W units */ + const msr_t msr = rdmsr(MSR_TURBO_POWER_CURRENT_LIMIT); + if ((msr.lo & 0x7fff) <= 90) + reg32 = 0; + } mchbar_write32(0x18d8, 0x120000); - mchbar_write32(0x18dc, 0x30a484a); + mchbar_write32(0x18dc, reg32 | 0xa484a); + + reg32 = qpi_pll_ratio > 20 ? 8 : 16; pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0); - pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a); + pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9404a | reg32 << 7); + mchbar_write32(0x18d8, 0x40000); mchbar_write32(0x18dc, 0xb000000); pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000); @@ -522,14 +534,18 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8) if (qpi_pll_ratio <= 14) reg8 = 0x33; - else if (qpi_pll_ratio <= 26) + else if (qpi_pll_ratio <= 22) reg8 = 0x42; else reg8 = 0x51; - mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60); - mchbar_setbits32(0x18b8, 0x200); - mchbar_setbits32(0x1918, 0x300); + info->fsb_frequency = qpi_pll_ratio * 15; + mchbar_write32(0x1a10, reg8 << 24 | info->fsb_frequency); + + if (info->silicon_revision == 2 || info->silicon_revision == 3) { + mchbar_setbits32(0x18b8, 0x200); + mchbar_setbits32(0x1918, 0x300); + } if (info->revision > 0x17) mchbar_setbits32(0x18b8, 0xc00); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 72c3028df8..1f550835b0 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -35,8 +35,6 @@ #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) #define GMA PCI_DEV (0, 0x2, 0x0) -#define HECIDEV PCI_DEV(0, 0x16, 0) -#define HECIBAR 0x10 #define FOR_ALL_RANKS \ for (channel = 0; channel < NUM_CHANNELS; channel++) \ @@ -792,7 +790,7 @@ static void compute_derived_timings(struct raminfo *info) info->max_slots_used_in_channel = 2; else info->max_slots_used_in_channel = 1; - for (channel = 0; channel < 2; channel++) + for (channel = 0; channel < NUM_CHANNELS; channel++) mchbar_write32(0x244 + (channel << 10), ((info->revision < 8) ? 1 : 0x200) | ((2 - info->max_slots_used_in_channel) << 17) | @@ -917,19 +915,14 @@ static void jedec_read(struct raminfo *info, int total_rank, u8 addr3, unsigned int value) { /* Handle mirrored mapping. */ - if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) - addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | - ((addr3 >> 1) & 0x10); + if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) { + addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) & 0x10); + value = (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) << 1); + } mchbar_clrsetbits8(0x271, 0x1f << 1, addr3); mchbar_clrsetbits8(0x671, 0x1f << 1, addr3); - /* Handle mirrored mapping. */ - if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) - value = - (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) - << 1); - read32p((value << 3) | (total_rank << 28)); mchbar_clrsetbits8(0x271, 0x1f << 1, 1 << 1); @@ -1505,224 +1498,6 @@ static const struct ram_training *get_cached_training(void) NULL); } -/* FIXME: add timeout. */ -static void wait_heci_ready(void) -{ - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c - ; - - write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); -} - -/* FIXME: add timeout. */ -static void wait_heci_cb_avail(int len) -{ - union { - struct mei_csr csr; - u32 raw; - } csr; - - while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) - ; - - do { - csr.raw = read32(DEFAULT_HECIBAR + 0x4); - } while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - - csr.csr.buffer_read_ptr)); -} - -static void send_heci_packet(struct mei_header *head, u32 *payload) -{ - int len = (head->length + 3) / 4; - int i; - - wait_heci_cb_avail(len + 1); - - /* FIXME: handle leftovers correctly. */ - write32(DEFAULT_HECIBAR + 0, *(u32 *) head); - for (i = 0; i < len - 1; i++) - write32(DEFAULT_HECIBAR + 0, payload[i]); - - write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1)); - write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4); -} - -static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) -{ - struct mei_header head; - int maxlen; - - wait_heci_ready(); - maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4; - - while (len) { - int cur = len; - if (cur > maxlen) { - cur = maxlen; - head.is_complete = 0; - } else - head.is_complete = 1; - head.length = cur; - head.reserved = 0; - head.client_address = clientaddress; - head.host_address = hostaddress; - send_heci_packet(&head, (u32 *) msg); - len -= cur; - msg += cur; - } -} - -/* FIXME: Add timeout. */ -static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size) -{ - union { - struct mei_csr csr; - u32 raw; - } csr; - int i = 0; - - write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); - do { - csr.raw = read32(DEFAULT_HECIBAR + 0xc); - } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); - - *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); - if (!head->length) { - write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); - *packet_size = 0; - return 0; - } - if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { - *packet_size = 0; - return -1; - } - - do { - csr.raw = read32(DEFAULT_HECIBAR + 0xc); - } while (((head->length + 3) >> 2) > - (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)); - - for (i = 0; i < (head->length + 3) >> 2; i++) - packet[i++] = read32(DEFAULT_HECIBAR + 0x8); - *packet_size = head->length; - if (!csr.csr.ready) - *packet_size = 0; - write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4); - return 0; -} - -union uma_reply { - struct { - u8 group_id; - u8 command; - u8 reserved; - u8 result; - u8 field2; - u8 unk3[0x48 - 4 - 1]; - }; - u32 dwords[0x48 / sizeof(u32)]; -} __packed; - -/* FIXME: Add timeout. */ -static int recv_heci_message(union uma_reply *message, u32 *message_size) -{ - struct mei_header head; - int current_position; - - current_position = 0; - while (1) { - u32 current_size; - current_size = *message_size - current_position; - if (recv_heci_packet - (&head, &message->dwords[current_position / sizeof(u32)], - ¤t_size) == -1) - break; - if (!current_size) - break; - current_position += current_size; - if (head.is_complete) { - *message_size = current_position; - return 0; - } - - if (current_position >= *message_size) - break; - } - *message_size = 0; - return -1; -} - -static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) -{ - union uma_reply reply; - - struct uma_message { - u8 group_id; - u8 cmd; - u8 reserved; - u8 result; - u32 c2; - u64 heci_uma_addr; - u32 heci_uma_size; - u16 c3; - } __packed msg = { - .group_id = 0, - .cmd = MKHI_SET_UMA, - .reserved = 0, - .result = 0, - .c2 = 0x82, - .heci_uma_addr = heci_uma_addr, - .heci_uma_size = heci_uma_size, - .c3 = 0, - }; - u32 reply_size; - - send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); - - reply_size = sizeof(reply); - if (recv_heci_message(&reply, &reply_size) == -1) - return; - - if (reply.command != (MKHI_SET_UMA | (1 << 7))) - die("HECI init failed\n"); -} - -static void setup_heci_uma(struct raminfo *info) -{ - if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20)) - return; - - const u64 heci_uma_addr = - ((u64) - ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) - - info->memory_reserved_for_heci_mb)) << 20; - - pci_read_config32(NORTHBRIDGE, DMIBAR); - if (info->memory_reserved_for_heci_mb) { - dmibar_clrbits32(DMIVC0RCTL, 1 << 7); - RCBA32(0x14) &= ~0x80; - dmibar_clrbits32(DMIVC1RCTL, 1 << 7); - RCBA32(0x20) &= ~0x80; - dmibar_clrbits32(DMIVCPRCTL, 1 << 7); - RCBA32(0x30) &= ~0x80; - dmibar_clrbits32(DMIVCMRCTL, 1 << 7); - RCBA32(0x40) &= ~0x80; - - RCBA32(0x40) = 0x87000080; // OK - dmibar_write32(DMIVCMRCTL, 0x87000080); // OK - - while ((RCBA16(0x46) & 2) && dmibar_read16(DMIVCMRSTS) & VCMNP) - ; - } - - mchbar_write32(0x24, 0x10000 + info->memory_reserved_for_heci_mb); - - send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb); - - pci_write_config32(HECIDEV, 0x10, 0x0); - pci_write_config8(HECIDEV, 0x4, 0x0); -} - static int have_match_ranks(struct raminfo *info, int channel, int ranks) { int ranks_in_channel; @@ -3157,7 +2932,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) info.last_500_command[0] = 0; info.last_500_command[1] = 0; - info.fsb_frequency = 135 * 2; info.board_lane_delay[0] = 0x14; info.board_lane_delay[1] = 0x07; info.board_lane_delay[2] = 0x07; @@ -3818,7 +3592,12 @@ void raminit(const int s3resume, const u8 *spd_addrmap) mchbar_write8(0x101c, 0xb8); } - setup_heci_uma(&info); + const u64 heci_uma_addr = + ((u64) + ((((u64)pci_read_config16(NORTHBRIDGE, TOM)) << 6) - + info.memory_reserved_for_heci_mb)) << 20; + + setup_heci_uma(heci_uma_addr, info.memory_reserved_for_heci_mb); if (info.uma_enabled) { u16 ax; diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6811..242100b800 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include "ironlake.h" @@ -27,8 +26,6 @@ void mainboard_romstage_entry(void) int s3resume = 0; u8 spd_addrmap[4] = {}; - enable_lapic(); - /* TODO, make this configurable */ ironlake_early_initialization(IRONLAKE_MOBILE); diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index f85cd2e9dd..b2a0730db4 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -19,10 +19,10 @@ config VGA_BIOS_ID string default "8086,a001" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4b74469c64..4901c2195a 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -15,7 +15,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 61bd2eedcd..498d21aa5d 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -8,7 +8,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -18,6 +18,6 @@ static uint32_t encode_pciexbar_length(void) void bootblock_early_northbridge_init(void) { - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 80b46117c5..9e272235d2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -26,7 +27,7 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; resource = new_resource(dev, index++); - resource->base = (resource_t) 0xfed00000; + resource->base = (resource_t) HPET_BASE_ADDRESS; resource->size = (resource_t) 0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 5e5420cc9f..a98ae99ac8 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "raminit.h" #include "pineview.h" @@ -31,8 +30,6 @@ void mainboard_romstage_entry(void) int boot_path, cbmem_was_initted; int s3resume = 0; - enable_lapic(); - /* Do some early chipset init, necessary for RAM init to work */ i82801gx_early_init(); pineview_early_init(); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ae246900c1..3abbddf98d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -83,12 +83,12 @@ config VGA_BIOS_ID string default "8086,0106" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xf0000000 help The MRC blob requires it to be at 0xf0000000. -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 64 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 977d7a7a8d..5421725a68 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -156,7 +156,7 @@ Device (MCHC) Return (0) } - Debug = "Set TDP Down" + Printf ("Set TDP Down") /* Set CTC */ CTCS = CTCD @@ -192,7 +192,7 @@ Device (MCHC) Return (0) } - Debug = "Set TDP Nominal" + Printf ("Set TDP Nominal") /* Set PL1 */ PL1V = CTDN @@ -320,7 +320,7 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -356,7 +356,7 @@ Method (_CRS, 0, Serialized) } PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 PLEN = PMAX - PMIN + 1 Return (MCRS) diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 1eba74438c..9e3708a21f 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -9,7 +9,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to setup the - * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all + * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all * subsequent non-explicit config accesses use MCFG. This code also assumes * that bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using the - * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. + * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index 5cd49cc9a6..a8f718c184 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -9,7 +9,7 @@ enum platform_type get_platform_type(void) { const int id = get_platform_id(); if (id != 1 && id != 4) - printk(BIOS_WARNING, "WARN: Unknown platform id 0x%x\n", id); + printk(BIOS_WARNING, "Unknown platform id 0x%x\n", id); return (id == 4) ? PLATFORM_MOBILE : PLATFORM_DESKTOP_SERVER; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 38adbceae5..9d01533e71 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -308,7 +308,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init\n"); - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) return; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 7f46d6663e..f667544c68 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -10,6 +10,7 @@ #include #include #include "sandybridge.h" +#include #include #include @@ -24,12 +25,38 @@ static size_t northbridge_get_tseg_size(void) return CONFIG_SMM_TSEG_SIZE; } +union dpr_register txt_get_chipset_dpr(void) +{ + return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) }; +} + +/* + * Return the topmost memory address below 4 GiB available for general + * use, from software's view of memory. Do not confuse this with TOLUD, + * which applies to the DRAM as viewed by the memory controller itself. + */ +static uintptr_t top_of_low_usable_memory(void) +{ + /* + * Base of DPR is top of usable DRAM below 4 GiB. However, DPR + * may not always be enabled. Unlike most memory map registers, + * the DPR register stores top of DPR instead of its base address. + * Top of DPR is R/O, and mirrored from TSEG base by hardware. + */ + uintptr_t tolum = northbridge_get_tseg_base(); + + const union dpr_register dpr = txt_get_chipset_dpr(); + + /* Subtract DMA Protected Range size if enabled */ + if (dpr.epm) + tolum -= dpr.size * MiB; + + return tolum; +} + void *cbmem_top_chipset(void) { - /* If DPR is disabled, base of TSEG is top of usable DRAM */ - uintptr_t top_of_ram = northbridge_get_tseg_base(); - - return (void *)top_of_ram; + return (void *)top_of_low_usable_memory(); } void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index bd4d1078da..f04c4f5e7f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -14,6 +14,7 @@ #include "chip.h" #include "sandybridge.h" #include +#include /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -85,9 +86,11 @@ static void mc_read_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; + uint32_t dpr_base_k, dpr_size_k; uint16_t ggc; unsigned long long tomk; unsigned long index = 3; + const union dpr_register dpr = txt_get_chipset_dpr(); pci_dev_read_resources(dev); @@ -184,6 +187,15 @@ static void mc_read_resources(struct device *dev) uma_memory_size += uma_size * 1024ULL; printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); + /* Calculate DMA Protected Region if enabled */ + if (dpr.epm && dpr.size) { + dpr_size_k = dpr.size * MiB / KiB; + tomk -= dpr_size_k; + dpr_base_k = (tseg_base - dpr.size * MiB) / KiB; + reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); + printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size); + } + printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); /* Report the memory regions */ diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 36e9f26c6a..4b1bae4662 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index e337c40e01..12a3be6806 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include "raminit_native.h" diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index ee5f1c94fa..c52203a14e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include #include #include #include @@ -14,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -231,8 +235,8 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; - pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; - pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + pei_data->hpet_address = HPET_BASE_ADDRESS; pei_data->thermalbase = 0xfed08000; pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; @@ -272,7 +276,7 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data) /* MRC only supports fixed numbers of frequencies */ default: printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); - /* fallthrough */ + __fallthrough; case 400: pei_data->max_ddr3_freq = 800; break; @@ -413,23 +417,23 @@ void setup_sdram_meminfo(struct pei_data *pei_data) if (dimm_size) { dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; - dimm->ddr_type = 0x18; /* DDR3 */ + dimm->ddr_type = MEMORY_TYPE_DDR3; dimm->ddr_frequency = ddr_frequency; dimm->rank_per_dimm = 1 + ((ch_conf >> 17) & 1); dimm->channel_num = i; dimm->dimm_num = 0; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ - dimm->bus_width = 0x3; /* 64-bit */ + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + dimm->mod_type = DDR3_SPD_SODIMM; + dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } /* DIMM-B */ @@ -437,23 +441,23 @@ void setup_sdram_meminfo(struct pei_data *pei_data) if (dimm_size) { dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; - dimm->ddr_type = 0x18; /* DDR3 */ + dimm->ddr_type = MEMORY_TYPE_DDR3; dimm->ddr_frequency = ddr_frequency; dimm->rank_per_dimm = 1 + ((ch_conf >> 18) & 1); dimm->channel_num = i; dimm->dimm_num = 1; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][122], - sizeof(uint8_t) * 4); + &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], + sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][128], - sizeof(uint8_t) * 18); + &pei_data->spd_data[0][SPD_DIMM_PART_NUM], + sizeof(uint8_t) * SPD_DIMM_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][118] << 8) | - (pei_data->spd_data[0][117] & 0xFF); - dimm->mod_type = 3; /* SPD_SODIMM */ - dimm->bus_width = 0x3; /* 64-bit */ + (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + dimm->mod_type = DDR3_SPD_SODIMM; + dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } } diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d6e7ee9025..a6f626a114 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -3,13 +3,15 @@ #include #include #include -#include #include #include "sandybridge.h" #include #include #include #include +#include +#include +#include #include #include #include @@ -22,6 +24,21 @@ __weak void mainboard_late_rcba_config(void) { } +static void configure_dpr(void) +{ + union dpr_register dpr = txt_get_chipset_dpr(); + + /* + * Just need to program the size of DPR, enable and lock it. + * The dpr.top will always point to TSEG_BASE (updated by hardware). + * We do it early because it will be needed later to calculate cbmem_top. + */ + dpr.lock = 1; + dpr.epm = 1; + dpr.size = CONFIG_INTEL_TXT_DPR_SIZE; + pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); +} + static void early_pch_reset_pmcon(void) { /* Reset RTC power status */ @@ -36,8 +53,6 @@ void mainboard_romstage_entry(void) if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset(); - enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); @@ -60,6 +75,11 @@ void mainboard_romstage_entry(void) post_code(0x39); + if (CONFIG(INTEL_TXT)) { + configure_dpr(); + intel_txt_romstage_init(); + } + perform_raminit(s3resume); post_code(0x3b); diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8eda090094..5318623c05 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -21,10 +21,10 @@ config VGA_BIOS_ID string default "8086,2e32" -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 8ef0ca4eca..462cdf9661 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -13,7 +13,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index f15d181354..80375a75ff 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -10,7 +10,7 @@ static uint32_t encode_pciexbar_length(void) { - switch (CONFIG_MMCONF_BUS_NUMBER) { + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { case 256: return 0 << 1; case 128: return 1 << 1; case 64: return 2 << 1; @@ -23,6 +23,6 @@ void bootblock_early_northbridge_init(void) /* Disable LaGrande Technology (LT) */ read32((void *)TPM_BASE_ADDRESS); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index e4cc888875..870e660810 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include "raminit.h" diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index b395493a06..8db770dc23 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -75,7 +75,7 @@ void notify_stm_resource_change(void *stm_resource); */ void *get_stm_resource(void); -void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, +void setup_smm_descriptor(void *smbase, int32_t apic_id, int32_t entry32_off); /* diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c index a8da98ca09..4e56e2e574 100644 --- a/src/security/intel/stm/StmPlatformResource.c +++ b/src/security/intel/stm/StmPlatformResource.c @@ -98,8 +98,8 @@ MSR_TABLE_ENTRY msr_table[] = { static void fixup_pciex_resource(void) { // Find max bus number and PCIEX length - rsc_pcie_mmio.length = CONFIG_MMCONF_LENGTH; // 0x10000000;// 256 MB - rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS; + rsc_pcie_mmio.length = CONFIG_ECAM_MMCONF_LENGTH; // 0x10000000;// 256 MB + rsc_pcie_mmio.base = CONFIG_ECAM_MMCONF_BASE_ADDRESS; } /* @@ -167,9 +167,14 @@ static void add_msr_resources(void) /* * Add resources to BIOS resource database. */ + +extern uint8_t *m_stm_resources_ptr; + void add_resources_cmd(void) { + m_stm_resources_ptr = NULL; + add_simple_resources(); add_msr_resources(); diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index cbb111adf0..bcf935cb11 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -77,8 +77,7 @@ static void read_gdtr(struct descriptor *gdtr) __asm__ __volatile__("sgdt %0" : "=m"(*gdtr)); } -void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, - int32_t entry32_off) +void setup_smm_descriptor(void *smbase, int32_t apic_id, int32_t entry32_off) { struct descriptor gdtr; void *smbase_processor; @@ -103,7 +102,7 @@ void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, psd->smm_descriptor_ver_minor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR; psd->smm_smi_handler_rip = - (uint64_t)((uintptr_t)base_smbase + SMM_ENTRY_OFFSET + + (uint64_t)((uintptr_t)smbase + SMM_ENTRY_OFFSET + entry32_off); psd->local_apic_id = apic_id; psd->size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); @@ -123,7 +122,7 @@ void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, read_gdtr(&gdtr); gdtr.base -= (uintptr_t) smbase_processor; - gdtr.base += (uintptr_t) base_smbase; + gdtr.base += (uintptr_t) smbase; psd->smm_gdt_ptr = gdtr.base; psd->smm_gdt_size = gdtr.limit + 1; // the stm will subtract, so add @@ -156,12 +155,15 @@ void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, return; } + // This code moved here because paralled SMM set can cause + // some processor to receive a bad value + // calculate the location in SMRAM + addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; + stm_resource_heap = (uint8_t *) addr_calc; + if (cpu == 0) { // need to create the BIOS resource list once - // first calculate the location in SMRAM - addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; - stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); //setup the list @@ -183,8 +185,8 @@ void stm_setup(uintptr_t mseg, int cpu, uintptr_t smbase, cpu, MsegChk.hi, MsegChk.lo); // setup the descriptor for this cpu - setup_smm_descriptor((void *)smbase, (void *) base_smbase, - cpu, offset32); + setup_smm_descriptor((void *)smbase, cpu, offset32); + } else { printk(BIOS_DEBUG, "STM: Error in STM load, STM not enabled: %d\n", diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 36489256b9..19eecc401b 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -8,7 +8,6 @@ config INTEL_TXT select AP_IN_SIPI_WAIT select TPM_MEASURED_BOOT_INIT_BOOTBLOCK if TPM_MEASURED_BOOT depends on TPM - depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE depends on PLATFORM_HAS_DRAM_CLEAR depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) @@ -39,6 +38,18 @@ config INTEL_TXT_DPR_SIZE the MRC does not have an input to specify the size of DPR, so this field is only used to check if the programmed size is large enough. +config INTEL_TXT_BDR_VERSION + int "BIOS Data Region version" + range 2 6 + default 5 if TPM1 + default 6 if TPM2 + help + Specify the TXT heap BIOS Data Region version. Sometimes when using + an older Trusted Boot version, it may report unsupported BIOS Data + Region version and refuse to set up the measured launch environment. + Setting lower version may work around such issue. Allowed values + currently range from 2 to 6. + config INTEL_TXT_TEST_BIOS_ACM_CALLING_CODE bool "Test BIOS ACM calling code with NOP function" help diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index e3e2f5c469..14bd296cad 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -16,6 +16,9 @@ #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include #else +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_ME) +#include +#endif #include #endif @@ -24,11 +27,14 @@ #include "txt_getsec.h" /* Usual security practice: if an unexpected error happens, reboot */ -static void __noreturn txt_reset_platform(void) +void __noreturn txt_reset_platform(void) { #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) global_reset(); #else +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_ME) + set_global_reset(1); +#endif full_reset(); #endif } @@ -141,6 +147,22 @@ bool intel_txt_memory_has_secrets(void) return ret; } +bool intel_txt_chipset_is_production_fused(void) +{ + /* + * Certain chipsets report production fused information in either + * TXT.VER.FSBIF or TXT.VER.EMIF/TXT.VER.QPIIF. + * Chapter B.1.7 and B.1.9 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + uint32_t reg = read32((void *)TXT_VER_FSBIF); + + if (reg == 0 || reg == UINT32_MAX) + reg = read32((void *)TXT_VER_QPIIF); + + return (reg & TXT_VER_PRODUCTION_FUSED) ? true : false; +} + static struct acm_info_table *find_info_table(const void *ptr) { const struct acm_header_v0 *acm_header = (struct acm_header_v0 *)ptr; @@ -203,8 +225,8 @@ static int validate_acm(const void *ptr) if (memcmp(acm_uuid, info->uuid, sizeof(acm_uuid)) != 0) return ACM_E_UUID_NOT_MATCH; - if ((acm_header->flags & ACM_FORMAT_FLAGS_DEBUG) == - (read64((void *)TXT_VER_FSBIF) & TXT_VER_PRODUCTION_FUSED)) + const bool production_acm = !(acm_header->flags & ACM_FORMAT_FLAGS_DEBUG); + if (production_acm != intel_txt_chipset_is_production_fused()) return ACM_E_PLATFORM_IS_NOT_PROD; return 0; @@ -214,11 +236,11 @@ static int validate_acm(const void *ptr) * Prepare to run the BIOS ACM: mmap it from the CBFS and verify that it * can be launched. Returns pointer to ACM on success, NULL on failure. */ -static void *intel_txt_prepare_bios_acm(struct region_device *acm, size_t *acm_len) +static void *intel_txt_prepare_bios_acm(size_t *acm_len) { void *acm_data = NULL; - if (!acm || !acm_len) + if (!acm_len) return NULL; acm_data = cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, acm_len); @@ -291,10 +313,9 @@ static void *intel_txt_prepare_bios_acm(struct region_device *acm, size_t *acm_l /* Returns on failure, resets the computer on success */ void intel_txt_run_sclean(void) { - struct region_device acm; size_t acm_len; - void *acm_data = intel_txt_prepare_bios_acm(&acm, &acm_len); + void *acm_data = intel_txt_prepare_bios_acm(&acm_len); if (!acm_data) return; @@ -322,7 +343,7 @@ void intel_txt_run_sclean(void) */ printk(BIOS_CRIT, "TEE-TXT: getsec_sclean could not launch the BIOS ACM.\n"); - rdev_munmap(&acm, acm_data); + cbfs_unmap(acm_data); } /* @@ -332,10 +353,9 @@ void intel_txt_run_sclean(void) */ int intel_txt_run_bios_acm(const u8 input_params) { - struct region_device acm; size_t acm_len; - void *acm_data = intel_txt_prepare_bios_acm(&acm, &acm_len); + void *acm_data = intel_txt_prepare_bios_acm(&acm_len); if (!acm_data) return -1; @@ -343,7 +363,7 @@ int intel_txt_run_bios_acm(const u8 input_params) /* Call into assembly which invokes the referenced ACM */ getsec_enteraccs(input_params, (uintptr_t)acm_data, acm_len); - rdev_munmap(&acm, acm_data); + cbfs_unmap(acm_data); const uint64_t acm_status = read64((void *)TXT_SPAD); if (acm_status & ACMERROR_TXT_VALID) { @@ -427,6 +447,10 @@ bool intel_txt_prepare_txt_env(void) printk(BIOS_DEBUG, " SENTER available: %s\n", (eax & BIT(4)) ? "true" : "false"); printk(BIOS_DEBUG, " SEXIT available: %s\n", (eax & BIT(5)) ? "true" : "false"); printk(BIOS_DEBUG, " PARAMETERS available: %s\n", (eax & BIT(6)) ? "true" : "false"); + printk(BIOS_DEBUG, " SMCTRL available: %s\n", (eax & BIT(7)) ? "true" : "false"); + printk(BIOS_DEBUG, " WAKEUP available: %s\n", (eax & BIT(8)) ? "true" : "false"); + + txt_dump_getsec_parameters(); /* * Causes #GP if function is not supported by getsec. diff --git a/src/security/intel/txt/getsec.c b/src/security/intel/txt/getsec.c index af9b7bb471..16ffedd24c 100644 --- a/src/security/intel/txt/getsec.c +++ b/src/security/intel/txt/getsec.c @@ -24,16 +24,26 @@ static bool getsec_enabled(void) /* * Check if SMX and VMX is supported by CPU. */ - if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) + if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) { + printk(BIOS_ERR, "SMX/VMX not supported by CPU\n"); return false; - + } /* - * Check if SMX, VMX and GetSec instructions haven't been disabled. + * This requirement is not needed for ENTERACCS, but for SENTER (see SDM). + * Skip check in romstage because IA32_FEATURE_CONTROL cannot be unlocked + * even after a global reset e.g. on Sandy/IvyBridge. However the register + * gets set properly in ramstage where all CPUs are already initialized. */ - msr_t msr = rdmsr(IA32_FEATURE_CONTROL); - if ((msr.lo & 0xff06) != 0xff06) - return false; - + if (!ENV_ROMSTAGE_OR_BEFORE) { + /* + * Check if SMX, VMX and GetSec instructions haven't been disabled. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if ((msr.lo & 0xff06) != 0xff06) { + printk(BIOS_ERR, "GETSEC not enabled in IA32_FEATURE_CONTROL MSR\n"); + return false; + } + } /* * Enable SMX. Required to execute GetSec instruction. * Chapter 2.2.4.3 diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index be3a1b4f0b..cbb24b6511 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -3,6 +3,7 @@ #include #include #include +#include #include "getsec_mtrr_setup.inc" @@ -226,6 +227,10 @@ cond_clear_var_mtrrs: movd %esp, %xmm0 movd %ebp, %xmm1 + /* Backup %gs used by CPU_INFO_V2 */ + movl %gs, %eax + movd %eax, %xmm2 + /* * Get function arguments. * It's important to pass the exact ACM size as it's used by getsec to verify @@ -252,14 +257,16 @@ cond_clear_var_mtrrs: lgdt -48(%ebp) /* Set cs */ - ljmp $0x10, $1f + ljmp $RAM_CODE_SEG, $1f 1: /* Fix segment registers */ - movl $0x18, %eax + movl $RAM_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss movl %eax, %fs + /* Restore %gs used by CPU_INFO_V2 */ + movd %xmm2, %eax movl %eax, %gs /* Disable cache */ diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index b4eac3333e..46c594cb05 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -3,10 +3,10 @@ #include #include #include -#include #include #include "txt.h" +#include "txt_getsec.h" #include "txt_register.h" const char *intel_txt_processor_error_type(uint8_t type) @@ -185,7 +185,7 @@ void txt_dump_chipset_info(void) printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", - (read64((void *)TXT_VER_FSBIF) & TXT_VER_PRODUCTION_FUSED) ? "true" : "false"); + intel_txt_chipset_is_production_fused() ? "true" : "false"); } void txt_dump_regions(void) @@ -221,3 +221,43 @@ void txt_dump_regions(void) bdr->lcp_pd_base); } } + +void txt_dump_getsec_parameters(void) +{ + uint32_t version_mask; + uint32_t version_numbers_supported; + uint32_t max_size_acm_area; + uint32_t memory_type_mask; + uint32_t senter_function_disable; + uint32_t txt_feature_flags; + + if (!getsec_parameter(&version_mask, &version_numbers_supported, + &max_size_acm_area, &memory_type_mask, + &senter_function_disable, &txt_feature_flags)) { + printk(BIOS_WARNING, "Could not obtain GETSEC parameters\n"); + return; + } + printk(BIOS_DEBUG, "TEE-TXT: GETSEC[PARAMETERS] returned:\n"); + printk(BIOS_DEBUG, " ACM Version comparison mask: %08x\n", version_mask); + printk(BIOS_DEBUG, " ACM Version numbers supported: %08x\n", + version_numbers_supported); + printk(BIOS_DEBUG, " Max size of authenticated code execution area: %08x\n", + max_size_acm_area); + printk(BIOS_DEBUG, " External memory types supported during AC mode: %08x\n", + memory_type_mask); + printk(BIOS_DEBUG, " Selective SENTER functionality control: %02x\n", + (senter_function_disable >> 8) & 0x7f); + printk(BIOS_DEBUG, " Feature Extensions Flags: %08x\n", txt_feature_flags); + printk(BIOS_DEBUG, "\tS-CRTM Capability rooted in: "); + if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) { + printk(BIOS_DEBUG, "processor\n"); + } else { + printk(BIOS_DEBUG, "BIOS\n"); + } + printk(BIOS_DEBUG, "\tMachine Check Register: "); + if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_MACHINE_CHECK) { + printk(BIOS_DEBUG, "preserved\n"); + } else { + printk(BIOS_DEBUG, "must be clear\n"); + } +} diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 3ca766e51c..265f81e62d 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -200,85 +200,139 @@ static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length) } } -static void txt_initialize_heap(void) +static void txt_heap_fill_common_bdr(struct txt_biosdataregion *bdr) { - /* - * BIOS Data Format - * Chapter C.2 - * Intel TXT Software Development Guide (Document: 315168-015) - */ - struct { - struct txt_biosdataregion bdr; - struct txt_bios_spec_ver_element spec; - struct txt_heap_acm_element heap_acm; - struct txt_extended_data_element_header end; - } __packed data = {0}; - /* TPM2.0 requires version 6 of BDT */ - if (CONFIG(TPM2)) - data.bdr.version = 6; - else - data.bdr.version = 5; + bdr->version = CONFIG_INTEL_TXT_BDR_VERSION; - data.bdr.no_logical_procs = dev_count_cpu(); - - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); - data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, - sinit_base, - read64((void *)TXT_SINIT_SIZE)); - - if (data.bdr.bios_sinit_size) { - printk(BIOS_INFO, "TEE-TXT: Placing SINIT ACM in memory.\n"); - if (CONFIG(INTEL_TXT_LOGGING)) - txt_dump_acm_info(sinit_base); - } else { - printk(BIOS_ERR, "TEE-TXT: Couldn't locate SINIT ACM in CBFS.\n"); - /* Clear memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); - } + bdr->no_logical_procs = dev_count_cpu(); /* The following have been removed from BIOS Data Table in version 6 */ size_t policy_len; void *policy_data = cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_POLICY, &policy_len); if (policy_data) { /* Point to FIT Type 9 entry in flash */ - data.bdr.lcp_pd_base = (uintptr_t)policy_data; - data.bdr.lcp_pd_size = (uint64_t)policy_len; + bdr->lcp_pd_base = (uintptr_t)policy_data; + bdr->lcp_pd_size = (uint64_t)policy_len; cbfs_unmap(policy_data); } else { printk(BIOS_ERR, "TEE-TXT: Couldn't locate LCP PD Policy in CBFS.\n"); } - data.bdr.support_acpi_ppi = 0; - data.bdr.platform_type = 0; + bdr->support_acpi_ppi = 0; + bdr->platform_type = 0; +} +static void txt_heap_fill_bios_spec(struct txt_bios_spec_ver_element *spec) +{ /* Fill in the version of the used TXT BIOS Specification */ - data.spec.header.type = HEAP_EXTDATA_TYPE_BIOS_SPEC_VER; - data.spec.header.size = sizeof(data.spec); - data.spec.ver_major = 2; - data.spec.ver_minor = 1; - data.spec.ver_revision = 0; + spec->header.type = HEAP_EXTDATA_TYPE_BIOS_SPEC_VER; + spec->header.size = sizeof(*spec); + spec->ver_major = 2; + spec->ver_minor = 1; + spec->ver_revision = 0; +} + +static void txt_heap_push_bdr_for_two_acms(u8 **heap_struct) +{ + /* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + /* Structure format for two present ACMs */ + struct { + struct txt_biosdataregion bdr; + struct txt_bios_spec_ver_element spec; + struct txt_heap_acm_element2 heap_acm; + struct txt_extended_data_element_header end; + } __packed data = {0}; + + txt_heap_fill_common_bdr(&data.bdr); + txt_heap_fill_bios_spec(&data.spec); + + void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, + sinit_base, + read64((void *)TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; - data.heap_acm.header.size = sizeof(data.heap_acm); - if (data.bdr.bios_sinit_size) { - data.heap_acm.num_acms = 2; - data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; - } else { - data.heap_acm.num_acms = 1; - } + data.heap_acm.num_acms = 2; + data.heap_acm.acm_addrs[1] = (uintptr_t)sinit_base; + + printk(BIOS_INFO, "TEE-TXT: Placing SINIT ACM in memory.\n"); + if (CONFIG(INTEL_TXT_LOGGING)) + txt_dump_acm_info(sinit_base); + data.heap_acm.acm_addrs[0] = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL); + + data.heap_acm.header.size = sizeof(data.heap_acm); + /* Extended elements - End marker */ data.end.type = HEAP_EXTDATA_TYPE_END; data.end.size = sizeof(data.end); + /* BiosData */ + push_sinit_heap(heap_struct, &data, sizeof(data)); +} + +static void txt_heap_push_bdr_for_one_acm(u8 **heap_struct) +{ + /* + * BIOS Data Format + * Chapter C.2 + * Intel TXT Software Development Guide (Document: 315168-015) + */ + /* Structure format for one present ACM */ + struct { + struct txt_biosdataregion bdr; + struct txt_bios_spec_ver_element spec; + struct txt_heap_acm_element1 heap_acm; + struct txt_extended_data_element_header end; + } __packed data = {0}; + + txt_heap_fill_common_bdr(&data.bdr); + txt_heap_fill_bios_spec(&data.spec); + + void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + /* Clear SINIT ACM memory */ + memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + + /* Extended elements - ACM addresses */ + data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; + data.heap_acm.acm_addrs[0] = + (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, NULL); + data.heap_acm.num_acms = 1; + + data.heap_acm.header.size = sizeof(data.heap_acm); + + /* Extended elements - End marker */ + data.end.type = HEAP_EXTDATA_TYPE_END; + data.end.size = sizeof(data.end); + + /* BiosData */ + push_sinit_heap(heap_struct, &data, sizeof(data)); +} + +static void txt_initialize_heap(void) +{ /* Fill TXT.HEAP.BASE with 4 subregions */ u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); - /* BiosData */ - push_sinit_heap(&heap_struct, &data, sizeof(data)); + /* + * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in + * CBFS, the size of txt_heap_acm_element will be different. We cannot + * always hardcode the number of ACM addresses for two ACMs. If we + * include BIOS ACM only, the BDR parsing will fail in TBoot due to + * invalid sizeof BDR. Check if SINIT ACM is present in CBFS and push + * properly formatted BDR region onto the TXT heap. + */ + if (cbfs_file_exists(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)) + txt_heap_push_bdr_for_two_acms(&heap_struct); + else + txt_heap_push_bdr_for_one_acm(&heap_struct); /* OsMLEData */ /* FIXME: Does firmware need to write this? */ diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index ef069ef0e2..98308b7ba1 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -83,14 +84,22 @@ static void print_memory_is_locked(void) void intel_txt_romstage_init(void) { /* Bail early if the CPU doesn't support TXT */ - if (!is_txt_cpu()) + if (!is_txt_cpu()) { + printk(BIOS_ERR, "TEE-TXT: CPU not TXT capable.\n"); return; + } - /* We need to use GETSEC here, so enable it */ - enable_getsec_or_reset(); + /* + * We need to use GETSEC here, so enable it. + * CR4_SMXE is all we need to be able to call GETSEC[CAPABILITIES] + * or GETSEC[ENTERACCS] for SCLEAN. + */ + write_cr4(read_cr4() | CR4_SMXE); - if (!is_txt_chipset()) + if (!is_txt_chipset()) { + printk(BIOS_ERR, "TEE-TXT: Chipset not TXT capable.\n"); return; + } const uint8_t txt_ests = read8((void *)TXT_ESTS); @@ -108,8 +117,8 @@ void intel_txt_romstage_init(void) printk(BIOS_ERR, "TEE-TXT: Secrets remain in memory. SCLEAN is required.\n"); if (txt_ests & TXT_ESTS_TXT_RESET_STS) { - printk(BIOS_ERR, "TEE-TXT: TXT_RESET bit set, doing full reset!\n"); - full_reset(); + printk(BIOS_ERR, "TEE-TXT: TXT_RESET bit set, doing global reset!\n"); + txt_reset_platform(); } /* FIXME: Clear SLP_TYP# */ diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h index e1a78af542..64e507d2b3 100644 --- a/src/security/intel/txt/txt.h +++ b/src/security/intel/txt/txt.h @@ -18,11 +18,12 @@ #define ACM_E_PLATFORM_IS_NOT_PROD 0x10 void intel_txt_romstage_init(void); - +void __noreturn txt_reset_platform(void); void intel_txt_log_bios_acm_error(void); int intel_txt_log_acm_error(const uint32_t acm_error); void intel_txt_log_spad(void); bool intel_txt_memory_has_secrets(void); +bool intel_txt_chipset_is_production_fused(void); void intel_txt_run_sclean(void); int intel_txt_run_bios_acm(const u8 input_params); bool intel_txt_prepare_txt_env(void); diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index bb735b6cfd..2137715edb 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -252,7 +252,15 @@ struct __packed txt_bios_spec_ver_element { uint16_t ver_revision; }; -struct __packed txt_heap_acm_element { +/* Used when only the BIOS ACM is included in CBFS */ +struct __packed txt_heap_acm_element1 { + struct txt_extended_data_element_header header; + uint32_t num_acms; // must greater 0, smaller than 3 + uint64_t acm_addrs[1]; +}; + +/* Used when both BIOS and SINIT ACMs are included in CBFS */ +struct __packed txt_heap_acm_element2 { struct txt_extended_data_element_header header; uint32_t num_acms; // must greater 0, smaller than 3 uint64_t acm_addrs[2]; @@ -283,5 +291,6 @@ struct __packed txt_biosdataregion { void txt_dump_regions(void); void txt_dump_chipset_info(void); void txt_dump_acm_info(const struct acm_header_v0 *acm_header); +void txt_dump_getsec_parameters(void); #endif /* SECURITY_INTEL_TXT_REGISTER_H_ */ diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index ff4cd1581b..c4f3bdd68f 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include + #include "memory.h" /** diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index ed642c33b5..7157b4d730 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -51,7 +51,7 @@ void tcpa_log_dump(void *unused); * @return TPM_SUCCESS on success. If not a tpm error is returned */ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, - uint8_t *digest, size_t digest_len, + const uint8_t *digest, size_t digest_len, const char *name); /** diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index b64bbbf6c6..8cd0793779 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -6,37 +6,6 @@ #include "crtm.h" #include -/* - * This function sets the TCPA log namespace - * for the cbfs file (region) lookup. - */ -static int create_tcpa_metadata(const struct region_device *rdev, - const char *cbfs_name, char log_string[TCPA_PCR_HASH_NAME]) -{ - int i; - struct region_device fmap; - static const char *const fmap_cbfs_names[] = { - "COREBOOT", - "FW_MAIN_A", - "FW_MAIN_B", - "RW_LEGACY" - }; - - for (i = 0; i < ARRAY_SIZE(fmap_cbfs_names); i++) { - if (fmap_locate_area_as_rdev(fmap_cbfs_names[i], &fmap) == 0) { - if (region_is_subregion(region_device_region(&fmap), - region_device_region(rdev))) { - snprintf(log_string, TCPA_PCR_HASH_NAME, - "FMAP: %s CBFS: %s", - fmap_cbfs_names[i], cbfs_name); - return 0; - } - } - } - - return -1; -} - static int tcpa_log_initialized; static inline int tcpa_log_available(void) { @@ -64,8 +33,6 @@ static inline int tcpa_log_available(void) */ static uint32_t tspi_init_crtm(void) { - struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock"); - /* Initialize TCPA PRERAM log. */ if (!tcpa_log_available()) { tcpa_preram_log_clear(); @@ -87,7 +54,6 @@ static uint32_t tspi_init_crtm(void) } /* measure bootblock from RO */ - struct cbfsf bootblock_data; struct region_device bootblock_fmap; if (fmap_locate_area_as_rdev("BOOTBLOCK", &bootblock_fmap) == 0) { if (tpm_measure_region(&bootblock_fmap, @@ -95,16 +61,16 @@ static uint32_t tspi_init_crtm(void) "FMAP: BOOTBLOCK")) return VB2_ERROR_UNKNOWN; } else { - if (cbfs_boot_locate(&bootblock_data, - prog_name(&bootblock), NULL)) { - /* - * measurement is done in - * tspi_measure_cbfs_hook() - */ + /* Mapping measures the file. We know we can safely map here because + bootblock-as-a-file is only used on x86, where we don't need cache to map. */ + enum cbfs_type type = CBFS_TYPE_BOOTBLOCK; + void *mapping = cbfs_ro_type_map("bootblock", NULL, &type); + if (!mapping) { printk(BIOS_INFO, "TSPI: Couldn't measure bootblock into CRTM!\n"); return VB2_ERROR_UNKNOWN; } + cbfs_unmap(mapping); } return VB2_SUCCESS; @@ -129,8 +95,7 @@ static bool is_runtime_data(const char *name) return !strcmp(allowlist, name); } -uint32_t tspi_measure_cbfs_hook(const struct region_device *rdev, const char *name, - uint32_t cbfs_type) +uint32_t tspi_cbfs_measurement(const char *name, uint32_t type, const struct vb2_hash *hash) { uint32_t pcr_index; char tcpa_metadata[TCPA_PCR_HASH_NAME]; @@ -144,7 +109,7 @@ uint32_t tspi_measure_cbfs_hook(const struct region_device *rdev, const char *na printk(BIOS_DEBUG, "CRTM initialized.\n"); } - switch (cbfs_type) { + switch (type) { case CBFS_TYPE_MRC_CACHE: pcr_index = TPM_RUNTIME_DATA_PCR; break; @@ -166,10 +131,10 @@ uint32_t tspi_measure_cbfs_hook(const struct region_device *rdev, const char *na break; } - if (create_tcpa_metadata(rdev, name, tcpa_metadata) < 0) - return VB2_ERROR_UNKNOWN; + snprintf(tcpa_metadata, TCPA_PCR_HASH_NAME, "CBFS: %s", name); - return tpm_measure_region(rdev, pcr_index, tcpa_metadata); + return tpm_extend_pcr(pcr_index, hash->algo, hash->raw, vb2_digest_size(hash->algo), + tcpa_metadata); } int tspi_measure_cache_to_pcr(void) diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 011fa26ad7..c4d051d988 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -3,10 +3,10 @@ #ifndef __SECURITY_TSPI_CRTM_H__ #define __SECURITY_TSPI_CRTM_H__ -#include #include #include #include +#include /* CRTM */ #define TPM_CRTM_PCR 2 @@ -16,21 +16,16 @@ */ #define TPM_RUNTIME_DATA_PCR 3 +#define TPM_MEASURE_ALGO (CONFIG(TPM1) ? VB2_HASH_SHA1 : VB2_HASH_SHA256) + /** * Measure digests cached in TCPA log entries into PCRs */ int tspi_measure_cache_to_pcr(void); -#if !ENV_SMM && CONFIG(TPM_MEASURED_BOOT) -/* - * Measures cbfs data via hook (cbfs) - * rdev covers the file data (not metadata) - * return 0 if successful, else an error +/** + * Extend a measurement hash taken for a CBFS file into the appropriate PCR. */ -uint32_t tspi_measure_cbfs_hook(const struct region_device *rdev, - const char *name, uint32_t cbfs_type); -#else -#define tspi_measure_cbfs_hook(rdev, name, cbfs_type) 0 -#endif +uint32_t tspi_cbfs_measurement(const char *name, uint32_t type, const struct vb2_hash *hash); #endif /* __SECURITY_TSPI_CRTM_H__ */ diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index b1bea4160d..563e8f0cd5 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -220,7 +219,7 @@ uint32_t tpm_clear_and_reenable(void) } uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, - uint8_t *digest, size_t digest_len, const char *name) + const uint8_t *digest, size_t digest_len, const char *name) { uint32_t result; @@ -234,16 +233,22 @@ uint32_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, return result; } - printk(BIOS_DEBUG, "TPM: Extending digest for %s into PCR %d\n", name, pcr); + printk(BIOS_DEBUG, "TPM: Extending digest for `%s` into PCR %d\n", name, pcr); result = tlcl_extend(pcr, digest, NULL); - if (result != TPM_SUCCESS) + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TPM: Extending hash for `%s` into PCR %d failed.\n", + name, pcr); return result; + } } if (CONFIG(TPM_MEASURED_BOOT)) tcpa_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); + printk(BIOS_DEBUG, "TPM: Digest of `%s` to PCR %d %s\n", + name, pcr, tspi_tpm_is_setup() ? "measured" : "logged"); + return TPM_SUCCESS; } @@ -253,23 +258,16 @@ uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, { uint8_t digest[TPM_PCR_MAX_LEN], digest_len; uint8_t buf[HASH_DATA_CHUNK_SIZE]; - uint32_t result, offset; + uint32_t offset; size_t len; struct vb2_digest_context ctx; - enum vb2_hash_algorithm hash_alg; if (!rdev || !rname) return TPM_E_INVALID_ARG; - if (CONFIG(TPM1)) { - hash_alg = VB2_HASH_SHA1; - } else { /* CONFIG_TPM2 */ - hash_alg = VB2_HASH_SHA256; - } - - digest_len = vb2_digest_size(hash_alg); + digest_len = vb2_digest_size(TPM_MEASURE_ALGO); assert(digest_len <= sizeof(digest)); - if (vb2_digest_init(&ctx, hash_alg)) { + if (vb2_digest_init(&ctx, TPM_MEASURE_ALGO)) { printk(BIOS_ERR, "TPM: Error initializing hash.\n"); return TPM_E_HASH_ERROR; } @@ -294,13 +292,6 @@ uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, printk(BIOS_ERR, "TPM: Error finalizing hash.\n"); return TPM_E_HASH_ERROR; } - result = tpm_extend_pcr(pcr, hash_alg, digest, digest_len, rname); - if (result != TPM_SUCCESS) { - printk(BIOS_ERR, "TPM: Extending hash into PCR failed.\n"); - return result; - } - printk(BIOS_DEBUG, "TPM: Digest of %s to PCR %d %s\n", - rname, pcr, tspi_tpm_is_setup() ? "measured" : "logged"); - return TPM_SUCCESS; + return tpm_extend_pcr(pcr, TPM_MEASURE_ALGO, digest, digest_len, rname); } #endif /* VBOOT_LIB */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index cfa533b880..8c9d12f7b0 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -242,6 +242,9 @@ uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) case TPM_RC_CR50_NV_UNDEFINED: return TPM_E_BADINDEX; + case TPM_RC_NV_RANGE: + return TPM_E_RANGE; + default: return TPM_E_READ_FAILURE; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 83fff5fb40..ae623043e6 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -680,7 +680,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) return NULL; } if (rc) - printk(BIOS_WARNING, "Warning: %s had one or more failures.\n", + printk(BIOS_WARNING, "%s had one or more failures.\n", __func__); /* The entire message have been parsed. */ diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index cb8b4f9f9e..c0e354d8f5 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -144,6 +144,7 @@ struct tpm_header { /* Values copied from tpm2/tpm_types.h */ #define RC_VER1 0x100 #define TPM_RC_INITIALIZE ((TPM_RC)(RC_VER1 + 0x000)) +#define TPM_RC_NV_RANGE ((TPM_RC)(RC_VER1 + 0x046)) #define TPM_RC_NV_UNINITIALIZED ((TPM_RC)(RC_VER1 + 0x04A)) /* diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index 7c4e569397..49a7405a7b 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -41,5 +41,6 @@ #define TPM_E_INVALID_ARG ((uint32_t)0x0000500c) #define TPM_E_HASH_ERROR ((uint32_t)0x0000500d) #define TPM_E_NO_SUCH_COMMAND ((uint32_t)0x0000500e) +#define TPM_E_RANGE ((uint32_t)0x0000500f) #endif /* TSS_ERRORS_H_ */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 7cbeea3e39..3e29c7e655 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -251,8 +251,8 @@ config VBOOT_ENABLE_CBFS_FALLBACK default n depends on VBOOT_SLOTS_RW_A help - When this option is enabled cbfs_boot_locate will look for a file in the RO - (COREBOOT) region if it isn't available in the active RW region. + When this option is enabled, the CBFS code will look for a file in the + RO (COREBOOT) region if it isn't available in the active RW region. config VBOOT_EARLY_EC_SYNC bool @@ -282,6 +282,14 @@ config VBOOT_X86_SHA256_ACCELERATION Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate SHA hash calculation in vboot. +config VBOOT_DEFINE_WIDEVINE_COUNTERS + bool + default n + help + Set up Widevine Secure Counters in TPM NVRAM by defining space. Enabling this + config will only define the counter space. Counters need to be incremented + separately before any read operation is performed on them. + menu "GBB configuration" config GBB_HWID diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index a208c04610..75bfcdc7c7 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -28,6 +28,11 @@ enum vb2_pcr_digest; /* 0x100d: Hash of MRC_CACHE training data for non-recovery boot */ #define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE +/* Widevine Secure Counter space */ +#define WIDEVINE_COUNTER_NV_INDEX(n) (0x3000 + (n)) +#define NUM_WIDEVINE_COUNTERS 4 +#define WIDEVINE_COUNTER_NAME "Widevine Secure Counter" +#define WIDEVINE_COUNTER_SIZE sizeof(uint64_t) /* Zero-Touch Enrollment related spaces */ #define ZTE_BOARD_ID_NV_INDEX 0x3fff00 #define ZTE_RMA_SN_BITS_INDEX 0x3fff01 diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 6c051093ea..3c50e4ef83 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -57,6 +57,16 @@ int __weak get_recovery_mode_retrain_switch(void) return 0; } +int __weak get_ec_is_trusted(void) +{ + /* + * If board doesn't override this, by default we always assume EC is in + * RW and untrusted. However, newer platforms are supposed to use cr50 + * BOOT_MODE to report this and won't need to override this anymore. + */ + return 0; +} + #if CONFIG(VBOOT_NO_BOARD_SUPPORT) /** * TODO: Create flash protection interface which implements get_write_protect_state. diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index a95e7d10a5..847a9597fb 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -58,16 +58,22 @@ uint32_t antirollback_read_space_kernel(struct vb2_context *ctx) } } - uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE; + uint8_t size = VB2_SECDATA_KERNEL_SIZE; + uint32_t ret; - RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, - size)); + /* Start with the version 1.0 size used by all modern cr50-boards. */ + ret = tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, size); + if (ret == TPM_E_RANGE) { + /* Fallback to version 0.2(minimum) size and re-read. */ + VBDEBUG("Antirollback: NV read out of range, trying min size\n"); + size = VB2_SECDATA_KERNEL_MIN_SIZE; + ret = tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, size); + } + RETURN_ON_FAILURE(ret); - if (vb2api_secdata_kernel_check(ctx, &size) - == VB2_ERROR_SECDATA_KERNEL_INCOMPLETE) + if (vb2api_secdata_kernel_check(ctx, &size) == VB2_ERROR_SECDATA_KERNEL_INCOMPLETE) /* Re-read. vboot will run the check and handle errors. */ - RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, - ctx->secdata_kernel, size)); + RETURN_ON_FAILURE(tlcl_read(KERNEL_NV_INDEX, ctx->secdata_kernel, size)); return TPM_SUCCESS; } @@ -141,6 +147,18 @@ static const TPMA_NV zte_rma_bytes_attr = { .TPMA_NV_POLICY_DELETE = 1, }; +static const TPMA_NV rw_orderly_counter_attributes = { + .TPMA_NV_COUNTER = 1, + .TPMA_NV_ORDERLY = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_AUTHWRITE = 1, + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_WRITE_STCLEAR = 1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PPWRITE = 1, + .TPMA_NV_NO_DA = 1, +}; + /* * This policy digest was obtained using TPM2_PolicyOR on 3 digests * corresponding to a sequence of @@ -324,6 +342,19 @@ static uint32_t setup_zte_spaces(void) return rv; } +static uint32_t setup_widevine_counter_spaces(void) +{ + uint32_t index, rv; + + for (index = 0; index < NUM_WIDEVINE_COUNTERS; index++) { + rv = define_space(WIDEVINE_COUNTER_NAME, WIDEVINE_COUNTER_NV_INDEX(index), + WIDEVINE_COUNTER_SIZE, rw_orderly_counter_attributes, NULL, 0); + if (rv != TPM_SUCCESS) + return rv; + } + return TPM_SUCCESS; +} + static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { RETURN_ON_FAILURE(tlcl_force_clear()); @@ -357,6 +388,11 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)))) RETURN_ON_FAILURE(setup_zte_spaces()); + /* Define widevine counter space. No need to increment/write to the secure counters + and are expected to be incremented during the first use. */ + if (CONFIG(VBOOT_DEFINE_WIDEVINE_COUNTERS)) + RETURN_ON_FAILURE(setup_widevine_counter_spaces()); + RETURN_ON_FAILURE(setup_firmware_space(ctx)); return TPM_SUCCESS; diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 87f382fb28..c557f25c14 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -60,7 +60,7 @@ void __weak vboot_platform_prepare_reboot(void) void vboot_reboot(void) { if (CONFIG(CONSOLE_CBMEM_DUMP_TO_UART)) - cbmem_dump_console(); + cbmem_dump_console_to_uart(); vboot_platform_prepare_reboot(); board_reset(); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2973934b99..91d42b2c7f 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -306,6 +306,9 @@ void verstage_main(void) if (CONFIG(TPM_CR50)) check_boot_mode(ctx); + if (get_ec_is_trusted()) + ctx->flags |= VB2_CONTEXT_EC_TRUSTED; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(ctx); diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index c2423cd5ab..81cf9748c6 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -16,13 +16,12 @@ config SOC_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select CPU_INFO_V2 select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE - select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI - select FSP_COMPRESS_FSP_M_LZMA - select FSP_COMPRESS_FSP_S_LZMA + select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB select HAVE_ACPI_TABLES select HAVE_CF9_RESET @@ -31,14 +30,13 @@ config SOC_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK - select PAYLOAD_PRELOAD select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP + select SOC_AMD_COMMON_BLOCK_ACP_GEN1 select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB @@ -51,9 +49,9 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC - select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI @@ -73,10 +71,13 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SSE2 - select TIMER_QUEUE select UDK_2017_BINDING + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS - select X86_AMD_INIT_SIPI + select X86_INIT_NEED_1_SIPI config ARCH_ALL_STAGES_X86 default n @@ -130,9 +131,15 @@ config PSP_SHAREDMEM_SIZE started. The workbuf's base depends on the address of the reset vector. -config PRERAM_CBMEM_CONSOLE_SIZE +config PRE_X86_CBMEM_CONSOLE_SIZE hex default 0x1600 + help + Size of the CBMEM console used in PSP verstage. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x2000 help Increase this value if preram cbmem console is getting truncated @@ -195,6 +202,21 @@ config VERSTAGE_SIZE Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. +config ASYNC_FILE_LOADING + bool "Loads files from SPI asynchronously" + select COOP_MULTITASKING + select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select CBFS_PRELOAD + help + When enabled, the platform will use the LPC SPI DMA controller to + asynchronously load contents from the SPI ROM. This will improve + boot time because the CPUs can be performing useful work while the + SPI contents are being preloaded. + +config CBFS_CACHE_SIZE + hex + default 0x40000 if CBFS_PRELOAD + config RAMBASE hex default 0x10000000 @@ -204,14 +226,10 @@ config RO_REGION_ONLY depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" -config CPU_ADDR_BITS - int - default 48 - -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config MAX_CPUS @@ -327,13 +345,11 @@ config PSP_DISABLE_POSTCODES help Disables the output of port80 post codes from PSP. -config PSP_POSTCODES_ON_ESPI - bool "Use eSPI bus for PSP post codes" - default y - depends on !PSP_DISABLE_POSTCODES +config PSP_INIT_ESPI + bool "Initialize eSPI in PSP Stage 2 Boot Loader" help - Select to send PSP port80 post codes on eSPI bus. - If not selected, PSP port80 codes will be sent on LPC bus. + Select to initialize the eSPI controller in the PSP Stage 2 Boot + Loader. config PSP_LOAD_MP2_FW bool @@ -364,6 +380,20 @@ config PSP_WHITELIST_FILE depends on HAVE_PSP_WHITELIST_FILE default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" +config HAVE_SPL_FILE + bool "Have a mainboard specific SPL table file" + default n + help + Have a mainboard specific SPL table file, which is created by AMD + and put to 3rdparty/blobs. + + If unsure, answer 'n' + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs/cezanne/PSP/TypeId0x55_SplTableBl_CZN.sbin" + config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" default "28 6" diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 87874418c3..302deaa4ce 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -10,6 +10,7 @@ all-y += aoac.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += reset.c @@ -39,6 +40,7 @@ ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c +ramstage-y += preload.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c @@ -53,8 +55,6 @@ CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) # ROMSIG Normally At ROMBASE + 0x20000 @@ -73,13 +73,17 @@ CEZANNE_FWM_POSITION=$(call int-add, \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# Building the cbfs image will fail if the offset isn't large enough +AMD_FW_AB_POSITION := 0x40 + CEZANNE_FW_A_POSITION=$(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - 0x40) + $(AMD_FW_AB_POSITION)) CEZANNE_FW_B_POSITION=$(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - 0x40) + $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -94,7 +98,7 @@ ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) PSP_SOFTFUSE_BITS += 7 endif -ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) +ifeq ($(CONFIG_PSP_INIT_ESPI),y) PSP_SOFTFUSE_BITS += 15 endif @@ -111,6 +115,10 @@ else PSP_SOFTFUSE_BITS += 29 endif +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 58 +endif + # Use additional Soft Fuse bits specified in Kconfig PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) @@ -119,6 +127,11 @@ ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) endif +# type = 0x55 +ifeq ($(CONFIG_HAVE_SPL_FILE),y) +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -188,6 +201,7 @@ OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), -- OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") @@ -205,6 +219,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ $(OPT_PSP_SHAREDMEM_BASE) \ $(OPT_PSP_SHAREDMEM_SIZE) \ $(OPT_EFS_SPI_READ_MODE) \ @@ -274,12 +289,14 @@ apu/amdfw-type := raw ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CEZANNE_FW_A_POSITION)) +# Ensure this ends up at the beginning of the FW_MAIN_A fmap region +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CEZANNE_FW_B_POSITION)) +# Ensure this ends up at the beginning of the FW_MAIN_B fmap region +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw endif diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index d390ca4f22..47f05b4bb2 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -320,9 +320,7 @@ void generate_cpu_entries(const struct device *device) }, }; - threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) - >> CPUID_EBX_THREADS_SHIFT) - + 1; + threads_per_core = get_threads_per_core(); pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); logical_cores = get_cpu_count(); diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl index 9e587b75f1..fa43db00b7 100644 --- a/src/soc/amd/cezanne/acpi/mmio.asl +++ b/src/soc/amd/cezanne/acpi/mmio.asl @@ -232,7 +232,11 @@ Device (I2C2) { Device (I2C3) { +#if CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) + Name (_HID, "AMDI0019") +#else Name (_HID, "AMDI0010") +#endif Name (_UID, 0x3) Method (_CRS, 0) { Local0 = ResourceTemplate() { @@ -263,7 +267,10 @@ Device (I2C3) Return (0x0F) } +/* If this device is shared with PSP, then PSP takes care of power management */ +#if !CONFIG(SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP) AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +#endif } Device (MISC) diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index f9956b68c5..7bd434a7f8 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -3,7 +3,7 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ + External(TOM1, IntObj) /* Generated by root_complex.c */ Method(_BBN, 0, NotSerialized) { Return(Zero) /* Bus number = 0 */ @@ -66,14 +66,14 @@ Device(PCI0) { /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = CONFIG_MMCONF_BASE_ADDRESS + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_MMCONF_BUS_NUMBER + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/cezanne/acpi/rtc_workaround.asl b/src/soc/amd/cezanne/acpi/rtc_workaround.asl new file mode 100644 index 0000000000..e69e974c16 --- /dev/null +++ b/src/soc/amd/cezanne/acpi/rtc_workaround.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Workaround for RTC on Cezanne. + * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839 + */ + +Scope (\_SB.PEP) { + Name (_PRW, Package () { + Package() {\_SB.GPIO, 0}, + 0x03 + }) +} + +Scope (\_SB.GPIO) { + Name (_AEI, ResourceTemplate () { + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,) + { + 44 /* int_shdwsysalarmfire */ + } + }) + + Method (_E2C, 0, Serialized) { + Notify (\_SB_.PEP, 0x02) + } +} diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index e603307c2f..bf2838a337 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -27,6 +27,8 @@ Scope(\_SB) { #include +#include "rtc_workaround.asl" + /* * Platform Wake Notify * diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index c3cb138473..c42ac0ac7c 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -4,92 +4,14 @@ #include #include #include -#include -#include -#include -#include #include -#include #include #include #include -/* - * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. - * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses - * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. - */ -static void set_caching(void) -{ - msr_t top_mem; - msr_t sys_cfg; - msr_t mtrr_def_type; - msr_t fixed_mtrr_ram; - msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; - - var_mtrr_context_init(&mtrr_ctx, NULL); - top_mem = rdmsr(TOP_MEM); - /* Enable RdDram and WrDram attributes in fixed MTRRs. */ - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - - /* Fixed MTRR constants. */ - fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); - fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = - ((MTRR_TYPE_UNCACHEABLE) << 0) | - ((MTRR_TYPE_UNCACHEABLE) << 8) | - ((MTRR_TYPE_UNCACHEABLE) << 16) | - ((MTRR_TYPE_UNCACHEABLE) << 24); - - /* Prep default MTRR type. */ - mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); - mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; - mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; - mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; - - disable_cache(); - - wrmsr(SYSCFG_MSR, sys_cfg); - - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); - /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ - wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); - wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - - wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); - - /* Enable Fixed and Variable MTRRs. */ - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; - sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; - /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once - MP init happens in coreboot proper it can be knocked down. */ - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_cache(); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - set_caching(); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 850d1bbbda..1e59153ef5 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -4,6 +4,8 @@ #define CEZANNE_CHIP_H #include +#include +#include #include #include #include @@ -14,7 +16,7 @@ struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; @@ -105,6 +107,19 @@ struct soc_amd_cezanne_config { uint8_t usb_phy_custom; struct usb_phy_config usb_phy; + + /* eDP phy tuning settings */ + uint8_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; + + struct { + uint8_t dp_vs_pemph_level; + uint8_t tx_eq_main; + uint8_t tx_eq_pre; + uint8_t tx_eq_post; + uint8_t tx_vboost_lvl; + } edp_tuningset; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/config.c b/src/soc/amd/cezanne/config.c index b5855eb40f..577f2aeb97 100644 --- a/src/soc/amd/cezanne/config.c +++ b/src/soc/amd/cezanne/config.c @@ -4,7 +4,7 @@ #include #include "chip.h" -const struct soc_amd_common_config *soc_get_common_config() +const struct soc_amd_common_config *soc_get_common_config(void) { /* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */ const struct soc_amd_cezanne_config *cfg = config_of_soc(); diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index c3d89bf513..adc99d0ba6 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -51,9 +50,9 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); @@ -62,7 +61,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index 1a0f9cb320..f62532c3e4 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -44,7 +45,7 @@ void data_fabric_set_mmio_np(void) for (i = 0; i < NUM_NB_MMIO_REGS; i++) { /* Adjust all registers that overlap */ ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (MMIO_WE | MMIO_RE))) + if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) continue; /* not enabled */ base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); @@ -66,8 +67,7 @@ void data_fabric_set_mmio_np(void) /* Although a pair could be freed later, this condition is * very unusual and deserves analysis. Flag an error and * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); + printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); continue; } data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); @@ -85,15 +85,15 @@ void data_fabric_set_mmio_np(void) reg = data_fabric_find_unused_mmio_reg(); if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + printk(BIOS_ERR, "cannot configure region as NP\n"); return; } data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE - | MMIO_RE); + (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP + | DF_MMIO_WE | DF_MMIO_RE); data_fabric_print_mmio_conf(); } diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 8cad78f4a8..8a69652e91 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/cezanne/espi_util.c b/src/soc/amd/cezanne/espi_util.c new file mode 100644 index 0000000000..ceb87243e2 --- /dev/null +++ b/src/soc/amd/cezanne/espi_util.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void espi_disable_lpc_ldrq(void) +{ + /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped + on Picasso and older compared to Renoir/Cezanne and newer */ + uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); +} + +void espi_switch_to_spi2_pads(void) +{ + /* Use SPI2 pins for eSPI */ + uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD); + dword |= PM_ESPI_CS_USE_DATA2; + pm_write32(PM_SPI_PAD_PU_PD, dword); + + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ + dword = pm_read32(PM_ACPI_CONF); + dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; + pm_write32(PM_ACPI_CONF, dword); +} diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index dd19c310bc..2c57f08d96 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -78,6 +78,8 @@ static void fch_clk_output_48Mhz(void) uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); /* Enable BP_X48M0 Clock Output */ ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; misc_write32(MISC_CLK_CNTL0, ctrl); } @@ -199,7 +201,6 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); gpp_clk_setup(); fch_clk_output_48Mhz(); diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 9f594d96ac..92debe3b08 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -70,7 +70,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); - mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); @@ -153,9 +153,19 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->usb_phy->Version_Major = 0xd; mcfg->usb_phy->Version_Minor = 0x6; mcfg->usb_phy->TableLength = 100; - } - else + } else { mcfg->usb_phy = NULL; + } + + if (config->edp_phy_override) { + mcfg->edp_phy_override = config->edp_phy_override; + mcfg->edp_physel = config->edp_physel; + mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level; + mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main; + mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre; + mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post; + mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl; + } fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 9757d7249e..ad253982ea 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -33,8 +33,8 @@ DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT -PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin -PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin -PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin -PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index 008b26190b..ae49a064e0 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -25,7 +24,7 @@ static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } @@ -33,33 +32,14 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) } #endif -__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } - void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { const struct soc_amd_cezanne_config *config = config_of_soc(); - uint32_t pad_ctrl; - int misc_reg; - if (bus >= ARRAY_SIZE(config->i2c_pad_ctrl_rx_sel)) + if (bus >= ARRAY_SIZE(config->i2c_pad)) return; - misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; - pad_ctrl = misc_read32(misc_reg); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= config->i2c_pad_ctrl_rx_sel[bus]; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - mainboard_i2c_override(bus, &pad_ctrl); - misc_write32(misc_reg, pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/cezanne/include/soc/aoac_defs.h b/src/soc/amd/cezanne/include/soc/aoac_defs.h index 5309cb08b8..25311dd3b3 100644 --- a/src/soc/amd/cezanne/include/soc/aoac_defs.h +++ b/src/soc/amd/cezanne/include/soc/aoac_defs.h @@ -1,4 +1,3 @@ - /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef AMD_CEZANNE_AOAC_DEFS_H diff --git a/src/soc/amd/cezanne/include/soc/cppc.h b/src/soc/amd/cezanne/include/soc/cppc.h index e2f4daaf49..41f668775c 100644 --- a/src/soc/amd/cezanne/include/soc/cppc.h +++ b/src/soc/amd/cezanne/include/soc/cppc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _CPU_AMD_COMMON_H -#define _CPU_AMD_COMMON_H +#ifndef AMD_CEZANNE_CPPC_H +#define AMD_CEZANNE_CPPC_H #include #include @@ -10,4 +10,4 @@ struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); void generate_cppc_entries(unsigned int core_id); -#endif +#endif /* AMD_CEZANNE_CPPC_H */ diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 5dcbdd07ce..27444befb3 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -5,6 +5,9 @@ #include +/* SoC-specific bits in D18F0_MMIO_CTRL0 */ +#define DF_MMIO_NP BIT(16) + #define IOMS0_FABRIC_ID 10 #define NUM_NB_MMIO_REGS 8 diff --git a/src/soc/amd/cezanne/include/soc/espi.h b/src/soc/amd/cezanne/include/soc/espi.h new file mode 100644 index 0000000000..67d7d5b2dd --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/espi.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_ESPI_H +#define AMD_CEZANNE_ESPI_H + +void espi_disable_lpc_ldrq(void); +void espi_switch_to_spi2_pads(void); + +#endif /* AMD_CEZANNE_ESPI_H */ diff --git a/src/soc/amd/cezanne/include/soc/gpio.h b/src/soc/amd/cezanne/include/soc/gpio.h index 904c3fcc8d..d12d66771d 100644 --- a/src/soc/amd/cezanne/include/soc/gpio.h +++ b/src/soc/amd/cezanne/include/soc/gpio.h @@ -235,8 +235,8 @@ #define GPIO_105_IOMUX_SD0_DATA1 2 #define GPIO_105_IOMUX_GPIOxx 3 #define GPIO_106_IOMUX_LAD2 0 -#define GPIO_106_IOMUX_EMMC_SPI2_WP_L_ESPI2_D2 1 -#define GPIO_106_IOMUX_EMMC_SD0_DATA2 2 +#define GPIO_106_IOMUX_SPI2_WP_L_ESPI2_D2 1 +#define GPIO_106_IOMUX_SD0_DATA2 2 #define GPIO_106_IOMUX_GPIOxx 3 #define GPIO_107_IOMUX_LAD3 0 #define GPIO_107_IOMUX_SPI2_HOLD_L_ESPI2_D3 1 diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h index 674c8e37b1..dba16db2db 100644 --- a/src/soc/amd/cezanne/include/soc/i2c.h +++ b/src/soc/amd/cezanne/include/soc/i2c.h @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include - #ifndef AMD_CEZANNE_I2C_H #define AMD_CEZANNE_I2C_H +#include +#include + #define GPIO_I2C0_SCL BIT(0) #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index a4f0f30d80..fc04b256a8 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -15,11 +15,6 @@ #define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 @@ -36,10 +31,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800 -#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) diff --git a/src/soc/amd/cezanne/include/soc/platform_descriptors.h b/src/soc/amd/cezanne/include/soc/platform_descriptors.h index 3a4bc62339..d6d65f05be 100644 --- a/src/soc/amd/cezanne/include/soc/platform_descriptors.h +++ b/src/soc/amd/cezanne/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H -#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#ifndef AMD_CEZANNE_PLATFORM_DESCRIPTORS_H +#define AMD_CEZANNE_PLATFORM_DESCRIPTORS_H #include #include @@ -14,4 +14,4 @@ void mainboard_get_dxio_ddi_descriptors( void mb_pre_fspm(void); -#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ +#endif /* AMD_CEZANNE_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/cezanne/include/soc/smi.h b/src/soc/amd/cezanne/include/soc/smi.h index dc299a5a95..aad4123083 100644 --- a/src/soc/amd/cezanne/include/soc/smi.h +++ b/src/soc/amd/cezanne/include/soc/smi.h @@ -6,8 +6,9 @@ #include #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -138,7 +139,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index addb850621..4e44b89fe4 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -44,6 +44,7 @@ #define PM_ACPI_DECODE_STD BIT(0) #define PM_ACPI_GLOBAL_EN BIT(1) #define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) #define PM_ACPI_TIMER_EN_EN BIT(4) #define PM_ACPI_MASK_ARB_DIS BIT(6) #define PM_ACPI_BIOS_RLS BIT(7) @@ -51,11 +52,26 @@ #define PM_ACPI_REDUCED_HW_EN BIT(9) #define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) #define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) #define PM_ACPI_BLOCK_PCIE_PME BIT(24) #define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) #define PM_SPI_PAD_PU_PD 0x90 #define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec @@ -94,33 +110,8 @@ #define USB_PHY_CMCLK_S0I3_DIS BIT(9) #define USB_PHY_CMCLK_S5_DIS BIT(10) #define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) void fch_pre_init(void); void fch_early_init(void); @@ -130,7 +121,4 @@ void fch_final(void *chip_info); void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); -/* Allow the board to change the default I2C pad configuration */ -void mainboard_i2c_override(int bus, uint32_t *pad_settings); - #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h index 9b99cd4b24..8affe10ce3 100644 --- a/src/soc/amd/cezanne/include/soc/uart.h +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMD_PICASSO_UART_H -#define AMD_PICASSO_UART_H +#ifndef AMD_CEZANNE_UART_H +#define AMD_CEZANNE_UART_H #include void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ -#endif /* AMD_PICASSO_UART_H */ +#endif /* AMD_CEZANNE_UART_H */ diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c new file mode 100644 index 0000000000..d8b08912ad --- /dev/null +++ b/src/soc/amd/cezanne/preload.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void start_fsps_preload(void *unused) +{ + preload_fsps(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL); diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index ea9353d444..547650dcc6 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -9,6 +9,7 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 183f1169cd..41d318e0eb 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -33,12 +33,10 @@ int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, return 0; } - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) +void platform_report_mode(int developer_mode_enabled) { - return 0; + if (developer_mode_enabled) + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); + else + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION); } diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index e04c702518..12fccc38f7 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -133,3 +133,17 @@ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); return retval; } + +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval); + return retval; +} + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval); + return retval; +} diff --git a/src/soc/amd/cezanne/psp_verstage/uart.c b/src/soc/amd/cezanne/psp_verstage/uart.c new file mode 100644 index 0000000000..2767b2eb27 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/uart.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static void *uart_bars[FCH_UART_ID_MAX]; + +uintptr_t get_uart_base(unsigned int idx) +{ + uint32_t err; + + if (idx >= ARRAY_SIZE(uart_bars)) + return 0; + + if (uart_bars[idx]) + return (uintptr_t)uart_bars[idx]; + + err = svc_map_fch_dev(FCH_IO_DEVICE_UART, idx, 0, &uart_bars[idx]); + if (err) { + svc_debug_print("Failed to map UART\n"); + return 0; + } + + return (uintptr_t)uart_bars[idx]; +} diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index f101680228..dde59d4dee 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -141,7 +141,7 @@ static void read_resources(struct device *dev) mmconf_resource(dev, MMIO_CONF_BASE); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -163,7 +163,7 @@ static void read_resources(struct device *dev) else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 7653836151..509a1d404a 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -23,6 +23,7 @@ static void fch_apmc_smi_handler(void) switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: @@ -120,7 +121,7 @@ static void fch_slp_typ_handler(void) psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 5a13d8da44..eba263e58a 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -36,90 +36,6 @@ Method (GPWR, 0x2, Serialized) TEMP = Arg1 } -Method (GPGB, 0x2) -{ - /* - * Returns the desired byte - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - */ - Local2 = Arg1 * 8 - Return ((GPRD (Arg0) >> Local2) & 0x000000FF) -} - -Method (GPSB, 0x3) -{ - /* - * Reads dword, replace byte, write back dword - * Arg0 - GPIO pin control MMIO address - * Arg1 - Desired byte (0 through 3) - * Arg2 - Value - */ - Local2 = Arg1 * 8 - Local3 = (GPRD(Arg0) >> Local2) & 0xFFFFFF00 - Local4 = ((Arg2 & 0x000000FF) | Local3) << Local2 - GPWR (Arg0, Local4) -} - -/* Read pin control byte 0 */ -Method (GPR0, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 0)) -} - -/* Read pin control byte 1 */ -Method (GPR1, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 1)) -} - -/* Read pin control byte 2 */ -Method (GPR2, 0x1) -{ - /* Arg0 - GPIO pin control MMIO address */ - Return (GPGB(Arg0, 2)) -} - -/* Read pin control byte 3 */ -Method (GPR3, 0x1) -{ - Return (GPGB(Arg0, 3)) -} - -/* Write pin control byte 0 */ -Method (GPW0, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 0, Arg1) -} - -/* Write pin control byte 1 */ -Method (GPW1, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 1, Arg1) -} - -/* Write pin control byte 2 */ -Method (GPW2, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 2, Arg1) -} - -/* Write pin control byte 3 */ -Method (GPW3, 0x2) -{ - /* Arg0 - GPIO pin control MMIO address */ - /* Arg1 - Value for control register */ - GPSB (Arg0, 3, Arg1) -} - /* * Set GPIO Output Value * Arg0 - GPIO Number @@ -159,7 +75,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - Local0 = (GPIO_INPUT_VALUE & VAL0) >> GPIO_INPUT_SHIFT + Local0 = (GPIO_PIN_STS & VAL0) >> GPIO_PIN_STS_SHIFT Return (Local0) } diff --git a/src/soc/amd/common/acpi/upep.asl b/src/soc/amd/common/acpi/upep.asl index b44ed43b23..d8ea30f09f 100644 --- a/src/soc/amd/common/acpi/upep.asl +++ b/src/soc/amd/common/acpi/upep.asl @@ -3,7 +3,7 @@ #define PEPD_DSM_UUID "e3f32452-febc-43ce-9039-932122d37721" #define PEPD_DSM_LPI_ENUM_FUNCTIONS 0 #define PEPD_DSM_LPI_ADDITIONAL_FUNCTIONS 1 -#define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1 +#define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1 #define PEPD_DSM_NOTIFICATIONS_UUID "11e00d56-ce64-47ce-837b-1f898f9aa461" #define PEPD_DSM_NOTIFICATION_ENUM_FUNCTIONS 0 diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig index ca733cd5de..df17f71057 100644 --- a/src/soc/amd/common/block/acp/Kconfig +++ b/src/soc/amd/common/block/acp/Kconfig @@ -1,4 +1,11 @@ -config SOC_AMD_COMMON_BLOCK_ACP +config SOC_AMD_COMMON_BLOCK_ACP_GEN1 bool help Select this option to perform Audio Co-Processor(ACP) configuration. + Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne) + +config SOC_AMD_COMMON_BLOCK_ACP_GEN2 + bool + help + Select this option to perform Audio Co-Processor(ACP) configuration. + Used by the ACP in AMD sabrina (family 17h) and possibly newer CPUs. diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc index cdff5bdb76..c1fa6ec408 100644 --- a/src/soc/amd/common/block/acp/Makefile.inc +++ b/src/soc/amd/common/block/acp/Makefile.inc @@ -1 +1,5 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp_gen2.c diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c index 465a44e2b6..b9dfce29ce 100644 --- a/src/soc/amd/common/block/acp/acp.c +++ b/src/soc/amd/common/block/acp/acp.c @@ -5,47 +5,15 @@ #include #include #include -#include #include -#include #include #include #include #include +#include "acp_def.h" -/* ACP registers and associated fields */ -#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ -#define PIN_CONFIG_MASK (7 << 0) -#define ACP_I2S_WAKE_EN 0x1414 -#define WAKE_EN_MASK (1 << 0) -#define ACP_PME_EN 0x1418 -#define PME_EN_MASK (1 << 0) - -static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) -{ - clrsetbits32((void *)(bar + reg), clear, set); -} - -static void init(struct device *dev) -{ - const struct soc_amd_common_config *cfg = soc_get_common_config(); - struct resource *res; - uintptr_t bar; - - res = dev->resource_list; - if (!res || !res->base) { - printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); - return; - } - - /* Set the proper I2S_PIN_CONFIG state */ - bar = (uintptr_t)res->base; - acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); - - /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ - acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); -} +_Static_assert(!(CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN1) && CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2)), + "Cannot select both ACP_GEN1 and ACP_GEN2 - check your config"); static const char *acp_acpi_name(const struct device *dev) { @@ -78,7 +46,7 @@ static struct device_operations acp_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = init, + .init = acp_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, .acpi_name = acp_acpi_name, diff --git a/src/soc/amd/common/block/acp/acp_def.h b/src/soc/amd/common/block/acp/acp_def.h new file mode 100644 index 0000000000..55af01aa02 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_def.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __AMD_ACP_DEF_H__ +#define __AMD_ACP_DEF_H__ + +/* This command needs to be implemented by the generation specific code. */ +void acp_init(struct device *dev); + +#endif /* __AMD_ACP_DEF_H__ */ diff --git a/src/soc/amd/common/block/acp/acp_gen1.c b/src/soc/amd/common/block/acp/acp_gen1.c new file mode 100644 index 0000000000..0fe37f3806 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_gen1.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "acp_def.h" + +/* ACP registers and associated fields */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ +#define PIN_CONFIG_MASK (7 << 0) +#define ACP_I2S_WAKE_EN 0x1414 +#define WAKE_EN_MASK (1 << 0) +#define ACP_PME_EN 0x1418 +#define PME_EN_MASK (1 << 0) + +static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) +{ + clrsetbits32((void *)(bar + reg), clear, set); +} + +void acp_init(struct device *dev) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + struct resource *res; + uintptr_t bar; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + /* Set the proper I2S_PIN_CONFIG state */ + bar = (uintptr_t)res->base; + acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); + + /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ + acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); +} diff --git a/src/soc/amd/common/block/acp/acp_gen2.c b/src/soc/amd/common/block/acp/acp_gen2.c new file mode 100644 index 0000000000..50de4b0bd9 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_gen2.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "acp_def.h" + +/* ACP registers and associated fields */ +#define ACP_PME_EN 0x41400 +#define PME_EN_MASK (1 << 0) +#define ACP_I2S_PIN_CONFIG 0x41440 /* HDA, Soundwire, I2S */ +#define PIN_CONFIG_MASK (0xf << 0) +#define ACP_I2S_WAKE_EN 0x4145C +#define WAKE_EN_MASK (1 << 0) + +static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) +{ + clrsetbits32((void *)(bar + reg), clear, set); +} + +void acp_init(struct device *dev) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + struct resource *res; + uintptr_t bar; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + /* Set the proper I2S_PIN_CONFIG state */ + bar = (uintptr_t)res->base; + acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); + + /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ + acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); +} diff --git a/src/soc/amd/common/block/acpi/bert.c b/src/soc/amd/common/block/acpi/bert.c index 968c9a6dc0..f20a4546b3 100644 --- a/src/soc/amd/common/block/acpi/bert.c +++ b/src/soc/amd/common/block/acpi/bert.c @@ -17,7 +17,7 @@ enum cb_err acpi_soc_get_bert_region(void **region, size_t *length) bert_errors_region(region, length); if (!*region) { - printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); + printk(BIOS_ERR, "Can't find BERT storage area\n"); return CB_ERR; } diff --git a/src/soc/amd/common/block/acpi/gpio.c b/src/soc/amd/common/block/acpi/gpio.c index b5167b8743..c4e3801545 100644 --- a/src/soc/amd/common/block/acpi/gpio.c +++ b/src/soc/amd/common/block/acpi/gpio.c @@ -7,13 +7,13 @@ static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) { if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + printk(BIOS_WARNING, "Pin %d should be smaller than" " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } if (SOC_GPIO_TOTAL_PINS >= AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER && gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d is a remote GPIO which isn't supported" + printk(BIOS_WARNING, "Pin %d is a remote GPIO which isn't supported" " yet.\n", gpio_num); return -1; } @@ -26,13 +26,13 @@ static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) { if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + printk(BIOS_WARNING, "Pin %d should be smaller than" " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } if (SOC_GPIO_TOTAL_PINS >= AMD_GPIO_FIRST_REMOTE_GPIO_NUMBER && gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d is a remote GPIO which isn't supported" + printk(BIOS_WARNING, "Pin %d is a remote GPIO which isn't supported" " yet.\n", gpio_num); return -1; } diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 7b2db3a338..c5218ea6ad 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -15,7 +15,6 @@ #include #include #include -#include #define MAX_DEV_ID 0xFFFF diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c index 3825753f84..5ff04125e3 100644 --- a/src/soc/amd/common/block/acpimmio/print_reset_status.c +++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c @@ -33,6 +33,7 @@ void fch_print_pmxc0_status(void) [3] = "ThermalTripFromTemp", [4] = "RemotePowerDownFromASF", [5] = "ShutDownFan0", + [9] = "InternalThermalTrip", [16] = "UserRst", [17] = "SoftPciRst", [18] = "DoInit", @@ -40,13 +41,15 @@ void fch_print_pmxc0_status(void) [20] = "DoFullReset", [21] = "SleepReset", [22] = "KbReset", - [23] = "LtReset", + [23] = "LtReset/ShutdownMsg", [24] = "FailBootRst", [25] = "WatchdogIssueReset", [26] = "RemoteResetFromASF", [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", + [30] = "SdpParityErr", + [31] = "SwSyncFloodFlag", }; printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c index c5f161bfcb..0afd2a1f19 100644 --- a/src/soc/amd/common/block/aoac/aoac.c +++ b/src/soc/amd/common/block/aoac/aoac.c @@ -24,8 +24,8 @@ void power_off_aoac_device(unsigned int dev) bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); - byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); - if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) + byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE); + if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE)) return true; else return false; diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc index 6e217df648..56cd5e12de 100644 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ b/src/soc/amd/common/block/apob/Makefile.inc @@ -1,4 +1,8 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y) romstage-y += apob_cache.c ramstage-y += apob_cache.c + +$(call src-to-obj,romstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h +$(call src-to-obj,ramstage,$(dir)/apob_cache.c) : $(obj)/fmap_config.h + endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index f61785dd8c..b932458ec2 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -8,18 +8,16 @@ #include #include #include -#include #include +#include #include #include #include #include -#include #include -#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" -/* PSP requires this value to be 64KiB */ -#define DEFAULT_MRC_CACHE_SIZE 0x10000 +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define DEFAULT_MRC_CACHE_SIZE FMAP_SECTION_RW_MRC_CACHE_SIZE #if !CONFIG_PSP_APOB_DRAM_ADDRESS #error Incorrect APOB configuration setting(s) @@ -69,7 +67,7 @@ static void *get_apob_dram_address(void) static int get_nv_rdev(struct region_device *r) { if (fmap_locate_area_as_rdev(DEFAULT_MRC_CACHE, r) < 0) { - printk(BIOS_ERR, "Error: No APOB NV region is found in flash\n"); + printk(BIOS_ERR, "No APOB NV region is found in flash\n"); return -1; } @@ -182,7 +180,7 @@ static void soc_update_apob_cache(void *unused) region_device_offset(&read_rdev), region_device_sz(&read_rdev)); if (fmap_locate_area_as_rdev_rw(DEFAULT_MRC_CACHE, &write_rdev) < 0) { - printk(BIOS_ERR, "Error: No RW APOB NV region is found in flash\n"); + printk(BIOS_ERR, "No RW APOB NV region is found in flash\n"); return; } @@ -190,14 +188,14 @@ static void soc_update_apob_cache(void *unused) /* write data to flash region */ if (rdev_eraseat(&write_rdev, 0, DEFAULT_MRC_CACHE_SIZE) < 0) { - printk(BIOS_ERR, "Error: APOB flash region erase failed\n"); + printk(BIOS_ERR, "APOB flash region erase failed\n"); return; } timestamp_add_now(TS_AMD_APOB_WRITE_START); if (rdev_writeat(&write_rdev, apob_src_ram, 0, apob_src_ram->size) < 0) { - printk(BIOS_ERR, "Error: APOB flash region update failed\n"); + printk(BIOS_ERR, "APOB flash region update failed\n"); return; } diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 11b6c8ccdb..7f509653b8 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -24,15 +24,10 @@ config MEMLAYOUT_LD_FILE string default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" -config PAYLOAD_PRELOAD_CACHE_SIZE +config CBFS_CACHE_SIZE hex - default 0x30000 - depends on PAYLOAD_PRELOAD help - This config sets the size of the payload_preload_cache memory region. - It is used as the destination for the raw payload. This space is only - populated during non-S3, so it doesn't need to be reserved in the - EARLY_RESERVED_DRAM region. + The size of the cbfs_cache region. endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/mca/mca_bert.c b/src/soc/amd/common/block/cpu/mca/mca_bert.c index 93d5749f54..5ec68e58f0 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mca_bert.c @@ -91,5 +91,5 @@ void build_bert_mca_error(struct mca_bank_status *mci) failed: /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); + printk(BIOS_ERR, "Not enough room in BERT region for Machine Check error\n"); } diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c index 8d864e855e..af2bee407d 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -91,5 +91,5 @@ void build_bert_mca_error(struct mca_bank_status *mci) failed: /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); + printk(BIOS_ERR, "Not enough room in BERT region for Machine Check error\n"); } diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index 808679dfea..71927961db 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -1,9 +1,11 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) +bootblock-y += early_cache.c bootblock-y += pre_c.S bootblock-y += write_resume_eip.c romstage-y += memmap.c ramstage-y += cpu.c +romstage-y += cpu.c ramstage-y += memmap.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 98926bff7e..b635cad750 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -11,6 +12,12 @@ int get_cpu_count(void) return 1 + (cpuid_ecx(0x80000008) & 0xff); } +unsigned int get_threads_per_core(void) +{ + return 1 + ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) + >> CPUID_EBX_THREADS_SHIFT); +} + void set_cstate_io_addr(void) { msr_t cst_addr; diff --git a/src/soc/amd/common/block/cpu/noncar/early_cache.c b/src/soc/amd/common/block/cpu/noncar/early_cache.c new file mode 100644 index 0000000000..b9650a96a7 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/early_cache.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* + * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. + * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses + * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. + */ +void early_cache_setup(void) +{ + msr_t top_mem; + msr_t sys_cfg; + msr_t mtrr_def_type; + msr_t fixed_mtrr_ram; + msr_t fixed_mtrr_mmio; + struct var_mtrr_context mtrr_ctx; + + var_mtrr_context_init(&mtrr_ctx, NULL); + top_mem = rdmsr(TOP_MEM); + /* Enable RdDram and WrDram attributes in fixed MTRRs. */ + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + + /* Fixed MTRR constants. */ + fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); + fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = + ((MTRR_TYPE_UNCACHEABLE) << 0) | + ((MTRR_TYPE_UNCACHEABLE) << 8) | + ((MTRR_TYPE_UNCACHEABLE) << 16) | + ((MTRR_TYPE_UNCACHEABLE) << 24); + + /* Prep default MTRR type. */ + mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); + mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; + mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; + mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + + disable_cache(); + + wrmsr(SYSCFG_MSR, sys_cfg); + + clear_all_var_mtrr(); + + var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + /* TODO: check if we should always mark 16 MByte below 4 GByte as WRPROT */ + var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ + wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); + wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); + + wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); + + /* Enable Fixed and Variable MTRRs. */ + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; + sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; + /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once + MP init happens in coreboot proper it can be knocked down. */ + wrmsr(SYSCFG_MSR, sys_cfg); + + enable_cache(); +} diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index 896512a0cd..461d3ee681 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -12,7 +12,13 @@ #endif ALIGN_COUNTER(64) - PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +#if ENV_SEPARATE_VERSTAGE + PRERAM_CBMEM_CONSOLE(., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE) +#else + REGION(cbmemc_transfer, ., CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE, 4) +#endif /* ENV_SEPARATE_VERSTAGE */ +#endif /* CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) */ TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 005bde093b..f17043bf27 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -25,6 +25,13 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | | * reserved_dram_end +--------------------------------+ * | | + * | cbfs_cache (if reqd) | + * | (CBFS_CACHE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE + * | | * | verstage (if reqd) | * | (VERSTAGE_SIZE) | * +--------------------------------+ VERSTAGE_ADDR @@ -44,11 +51,11 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ * | CBFS mcache (CBFS_MCACHE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE + 0x200 * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRE_X86_CBMEM_CONSOLE_SIZE + * | PSP Verstage CBMEM console | + * | (PRE_X86_CBMEM_CONSOLE_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE * | PSP shared (vboot workbuf) | * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | @@ -91,22 +98,19 @@ SECTIONS BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) -#if CONFIG(VBOOT_SEPARATE_VERSTAGE) +#if CONFIG(VBOOT_SEPARATE_VERSTAGE) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif - EARLY_RESERVED_DRAM_END(.) + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) -#if CONFIG(PAYLOAD_PRELOAD) - /* - * This section is outside the early_reserved_dram section. We only read - * the payload on non-S3 boots, so we don't need to reserve it from the - * OS. The 64 byte alignment is required by the SPI DMA controller. - */ +#if CONFIG_CBFS_CACHE_SIZE > 0 . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); - REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE) + CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE) #endif + EARLY_RESERVED_DRAM_END(.) + RAMSTAGE(CONFIG_RAMBASE, 8M) } diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 325e36b106..8f37f1ab42 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -47,7 +47,7 @@ void smm_region(uintptr_t *start, size_t *size) status = fsp_find_range_hob(&tseg, AMD_FSP_TSEG_HOB_GUID.b); if (status < 0) { - printk(BIOS_ERR, "Error: unable to find TSEG HOB\n"); + printk(BIOS_ERR, "unable to find TSEG HOB\n"); return; } diff --git a/src/soc/amd/common/block/cpu/smm/finalize.c b/src/soc/amd/common/block/cpu/smm/finalize.c index ec975bea27..73b21216f5 100644 --- a/src/soc/amd/common/block/cpu/smm/finalize.c +++ b/src/soc/amd/common/block/cpu/smm/finalize.c @@ -41,6 +41,8 @@ static void soc_finalize(void *unused) finalize_cores(); if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) acpi_disable_sci(); else diff --git a/src/soc/amd/common/block/cpu/smm/smm_helper.c b/src/soc/amd/common/block/cpu/smm/smm_helper.c index bf01b8b965..ce80f1613c 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_helper.c +++ b/src/soc/amd/common/block/cpu/smm/smm_helper.c @@ -19,7 +19,7 @@ void clear_tvalid(void) if (!tvalid) /* not valid but locked means still accessible */ return; - printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); + printk(BIOS_ERR, "can't clear TValid, already locked\n"); return; } diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index e6a57f5c99..33b244d192 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -10,6 +10,8 @@ #include #include +#define CPU_MICROCODE_BLOB_NAME "cpu_microcode_blob.bin" + _Static_assert(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE > 0, "SOC_AMD_COMMON_BLOCK_UCODE_SIZE is not set"); @@ -97,9 +99,10 @@ void amd_update_microcode_from_cbfs(void) /* Cache the buffer so each CPU doesn't need to read the uCode from flash */ if (!cache_valid) { timestamp_add_now(TS_READ_UCODE_START); - ucode_list = cbfs_map("cpu_microcode_blob.bin", &ucode_len); + ucode_list = cbfs_map(CPU_MICROCODE_BLOB_NAME, &ucode_len); if (!ucode_list) { - printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); + printk(BIOS_WARNING, + CPU_MICROCODE_BLOB_NAME " not found. Skipping updates.\n"); return; } @@ -120,3 +123,12 @@ void amd_update_microcode_from_cbfs(void) apply_microcode_patch(&ucode_cache); } + +void preload_microcode(void) +{ + if (!CONFIG(CBFS_PRELOAD)) + return; + + printk(BIOS_DEBUG, "Preloading microcode %s\n", CPU_MICROCODE_BLOB_NAME); + cbfs_preload(CPU_MICROCODE_BLOB_NAME); +} diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index abb4ba8c3a..0fcee3642b 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -63,7 +63,7 @@ void data_fabric_print_mmio_conf(void) void data_fabric_disable_mmio_reg(unsigned int reg) { data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT); + IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT); data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), 0); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), 0); } @@ -71,7 +71,7 @@ void data_fabric_disable_mmio_reg(unsigned int reg) static bool is_mmio_reg_disabled(unsigned int reg) { uint32_t val = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(reg)); - return !(val & (MMIO_WE | MMIO_RE)); + return !(val & (DF_MMIO_WE | DF_MMIO_RE)); } int data_fabric_find_unused_mmio_reg(void) diff --git a/src/soc/amd/common/block/gpio/gpio.c b/src/soc/amd/common/block/gpio/gpio.c index 1141846842..468d7aef70 100644 --- a/src/soc/amd/common/block/gpio/gpio.c +++ b/src/soc/amd/common/block/gpio/gpio.c @@ -85,7 +85,7 @@ static void program_smi(uint32_t flags, unsigned int gevent_num) uint8_t level; if (!is_gpio_event_level_triggered(flags)) { - printk(BIOS_ERR, "ERROR: %s - Only level trigger allowed for SMI!\n", __func__); + printk(BIOS_ERR, "%s - Only level trigger allowed for SMI!\n", __func__); BUG(); return; } @@ -125,11 +125,6 @@ static void program_sci(uint32_t flags, unsigned int gevent_num) configure_scimap(&sci); } -uintptr_t gpio_get_address(gpio_t gpio_num) -{ - return (uintptr_t)gpio_ctrl_ptr(gpio_num); -} - static void gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) { uint32_t reg; @@ -153,7 +148,7 @@ static void gpio_and32(gpio_t gpio_num, uint32_t mask) static void gpio_or32(gpio_t gpio_num, uint32_t or) { - gpio_update32(gpio_num, -1UL, or); + gpio_update32(gpio_num, 0xffffffff, or); } static void master_switch_clr(uint32_t mask) @@ -252,7 +247,7 @@ static void set_single_gpio(const struct soc_amd_gpio *g) gevent_num = get_gpio_gevent(g->gpio, gev_tbl, gev_items); if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n", + printk(BIOS_WARNING, "GPIO pin %d has no associated gevent!\n", g->gpio); return; } diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 79aeef795b..38a422c6b7 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -173,6 +173,7 @@ static const struct device_operations graphics_ops = { .set_resources = graphics_set_resources, .enable_resources = pci_dev_enable_resources, .init = graphics_dev_init, + .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = pci_rom_write_acpi_tables, .acpi_fill_ssdt = graphics_fill_ssdt, @@ -183,6 +184,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU, PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU, PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU, + PCI_DEVICE_ID_ATI_FAM17H_MODELA0H_GPU, PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE, PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_BARCELO, 0, diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 5d8498c6af..8e8ff9b148 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -2,3 +2,25 @@ config SOC_AMD_COMMON_BLOCK_I2C bool help Select this option to add FCH I2C controller functions to the build. + +config SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + bool + help + Select this option to add FCH I2C pad configuration functions to the + build. + +config SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + bool + help + Select this option to add FCH I2C/I3C pad configuration functions to + the build. + +config SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP + bool + depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE + default n + help + Enable PSP I2C arbitration if there is I2C3 controller with TPM device + connected, which is shared between x86 and PSP. This is necessary to + ensure proper communication with I2C peripherals connected to such + bus. diff --git a/src/soc/amd/common/block/i2c/Makefile.inc b/src/soc/amd/common/block/i2c/Makefile.inc index 8af77965ce..b0747fe50f 100644 --- a/src/soc/amd/common/block/i2c/Makefile.inc +++ b/src/soc/amd/common/block/i2c/Makefile.inc @@ -1 +1,3 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c diff --git a/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c new file mode 100644 index 0000000000..36211a3264 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i23c_pad_ctrl.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "i23c_pad_def.h" + +void fch_i23c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl) +{ + uint32_t pad_ctrl; + + pad_ctrl = misc_read32(MISC_I23C_PAD_CTRL(bus)); + + pad_ctrl &= ~I23C_PAD_CTRL_MODE_I3C_I2C_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_I2C; + + switch (ctrl->rx_level) { + case I2C_PAD_RX_NO_CHANGE: + /* Default is enabled and thresholds for 1.8V operation */ + break; + case I2C_PAD_RX_OFF: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_OFF; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V; + break; + case I2C_PAD_RX_1_8V: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_8V; + break; + case I2C_PAD_RX_1_1V: + pad_ctrl &= ~I23C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I23C_PAD_CTRL_RX_SEL_ON; + pad_ctrl &= ~I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK; + pad_ctrl |= I23C_PAD_CTRL_MODE_1_1V; + break; + default: + printk(BIOS_WARNING, "Invalid I2C/I3C pad RX level for bus %u\n", bus); + break; + } + + pad_ctrl &= ~I23C_PAD_CTRL_FALLSLEW_SEL_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? + I23C_PAD_CTRL_FALLSLEW_SEL_STD : I23C_PAD_CTRL_FALLSLEW_SEL_LOW; + + pad_ctrl &= I23C_PAD_CTRL_SLEW_N_MASK; + pad_ctrl |= I23C_PAD_CTRL_SLEW_N_FAST; + + misc_write32(MISC_I23C_PAD_CTRL(bus), pad_ctrl); +} diff --git a/src/soc/amd/common/block/i2c/i23c_pad_def.h b/src/soc/amd/common/block/i2c/i23c_pad_def.h new file mode 100644 index 0000000000..8973a0c633 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i23c_pad_def.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_I23C_PAD_DEF_H +#define AMD_BLOCK_I23C_PAD_DEF_H + +#include + +/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit + definitions. Which one is present depends on the SoC. */ +#define MISC_I23C0_PAD_CTRL 0xd8 +#define MISC_I23C_PAD_CTRL(bus) (MISC_I23C0_PAD_CTRL + 4 * (bus)) + +#define I23C_PAD_CTRL_OD_RP_SW_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define I23C_PAD_CTRL_OD_RP_SW_SHIFT 0 +#define I23C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) +#define I23C_PAD_CTRL_RX_SHIFT 4 +#define I23C_PAD_CTRL_RX_SEL_OFF (0 << I23C_PAD_CTRL_RX_SHIFT) +#define I23C_PAD_CTRL_RX_SEL_ON (3 << I23C_PAD_CTRL_RX_SHIFT) +#define I23C_PAD_CTRL_SLEW_N_MASK (BIT(6) | BIT(7)) +#define I23C_PAD_CTRL_SLEW_N_SHIFT 7 +#define I23C_PAD_CTRL_SLEW_N_DIS (0 << I23C_PAD_CTRL_SLEW_N_SHIFT) +#define I23C_PAD_CTRL_SLEW_N_FAST (3 << I23C_PAD_CTRL_SLEW_N_SHIFT) +#define I23C_PAD_CTRL_FALLSLEW_SEL_MASK (BIT(8) | BIT(9)) +#define I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT 8 +#define I23C_PAD_CTRL_FALLSLEW_SEL_STD (0 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT) +#define I23C_PAD_CTRL_FALLSLEW_SEL_LOW (3 << I23C_PAD_CTRL_FALLSLEW_SEL_SHIFT) +#define I23C_PAD_CTRL_SPIKE_RC_EN_MASK (BIT(10) | BIT(11)) +#define I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT 10 +#define I23C_PAD_CTRL_SPIKE_RC_DIS (0 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT) +#define I23C_PAD_CTRL_SPIKE_RC_EN (3 << I23C_PAD_CTRL_SPIKE_RC_EN_SHIFT) +#define I23C_PAD_CTRL_CAP_DOWN BIT(12) +#define I23C_PAD_CTRL_CAP_UP BIT(13) +#define I23C_PAD_CTRL_RES_DOWN BIT(14) +#define I23C_PAD_CTRL_RES_UP BIT(15) +#define I23C_PAD_CTRL_BIAS_CRT_EN_MASK (BIT(16) | BIT(17)) +#define I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT 16 +#define I23C_PAD_CTRL_BIAS_CRT_DIS (0 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT) +#define I23C_PAD_CTRL_BIAS_CRT_EN (3 << I23C_PAD_CTRL_BIAS_CRT_EN_SHIFT) +#define I23C_PAD_CTRL_SPARE0 BIT(18) +#define I23C_PAD_CTRL_SPARE1 BIT(19) +#define I23C_PAD_CTRL_COMP_SEL0 BIT(20) /* unused */ +#define I23C_PAD_CTRL_COMP_SEL1 BIT(21) /* unused */ +#define I23C_PAD_CTRL_RES_BIAS_EN_MASK (BIT(22) | BIT(23)) +#define I23C_PAD_CTRL_RES_BIAS_EN_SHIFT 22 +#define I23C_PAD_CTRL_RES_BIAS_T_COMP (0 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT) +#define I23C_PAD_CTRL_RES_BIAS_CONST_GM (3 << I23C_PAD_CTRL_RES_BIAS_EN_SHIFT) +#define I23C_PAD_CTRL_SLEW_P_MASK (BIT(24) | BIT(25)) +#define I23C_PAD_CTRL_SLEW_P_SHIFT 24 +#define I23C_PAD_CTRL_SLEW_P_DIS (0 << I23C_PAD_CTRL_SLEW_P_SHIFT) +#define I23C_PAD_CTRL_SLEW_P_EN (3 << I23C_PAD_CTRL_SLEW_P_SHIFT) +#define I23C_PAD_CTRL_MODE_I3C_I2C_MASK (BIT(26) | BIT(27)) +#define I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT 26 +#define I23C_PAD_CTRL_MODE_I2C (0 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT) +#define I23C_PAD_CTRL_MODE_I3C (3 << I23C_PAD_CTRL_MODE_I3C_I2C_SHIFT) +#define I23C_PAD_CTRL_MODE_1_8V_1_1V_MASK (BIT(28) | BIT(29)) +#define I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT 28 +#define I23C_PAD_CTRL_MODE_1_1V (0 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT) +#define I23C_PAD_CTRL_MODE_1_8V (3 << I23C_PAD_CTRL_MODE_1_8V_1_1V_SHIFT) +#define I23C_PAD_CTRL_SPIKE_C_SEL_MASK (BIT(30) | BIT(31)) +#define I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT 30 +#define I23C_PAD_CTRL_SPIKE_C_SEL_DIS (0 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT) +#define I23C_PAD_CTRL_SPIKE_C_SEL_EN (3 << I23C_PAD_CTRL_SPIKE_C_SEL_SHIFT) + +#endif /* AMD_BLOCK_I23C_PAD_DEF_H */ diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c index ff9ec90fd5..733ad88132 100644 --- a/src/soc/amd/common/block/i2c/i2c.c +++ b/src/soc/amd/common/block/i2c/i2c.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -78,11 +77,6 @@ int dw_i2c_soc_dev_to_bus(const struct device *dev) return -1; } -void __weak soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) -{ - /* Nothing by default. */ -} - static void dw_i2c_soc_init(bool is_early_init) { unsigned int bus; @@ -102,7 +96,7 @@ static void dw_i2c_soc_init(bool is_early_init) cfg->early_init != is_early_init) continue; - if (dw_i2c_init(bus, cfg)) { + if (dw_i2c_init(bus, cfg) != CB_SUCCESS) { printk(BIOS_ERR, "Failed to init i2c bus %u\n", bus); continue; } diff --git a/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c new file mode 100644 index 0000000000..cdb7900ee6 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_ctrl.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "i2c_pad_def.h" + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl) +{ + uint32_t pad_ctrl; + + pad_ctrl = misc_read32(MISC_I2C_PAD_CTRL(bus)); + + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; + + switch (ctrl->rx_level) { + case I2C_PAD_RX_NO_CHANGE: + break; + case I2C_PAD_RX_OFF: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_OFF; + break; + case I2C_PAD_RX_3_3V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; + break; + case I2C_PAD_RX_1_8V: + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_1_8V; + break; + default: + printk(BIOS_WARNING, "Invalid I2C pad RX level for bus %u\n", bus); + break; + } + + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= speed == I2C_SPEED_STANDARD ? + I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; + misc_write32(MISC_I2C_PAD_CTRL(bus), pad_ctrl); +} diff --git a/src/soc/amd/common/block/i2c/i2c_pad_def.h b/src/soc/amd/common/block/i2c/i2c_pad_def.h new file mode 100644 index 0000000000..5e699b1411 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i2c_pad_def.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_I2C_PAD_DEF_H +#define AMD_BLOCK_I2C_PAD_DEF_H + +#include + +/* MISC_I2Cx_PAD_CTRL and MISC_I23Cx_PAD_CTRL are in the same place, but have different bit + definitions. Which one is present depends on the SoC. */ +#define MISC_I2C0_PAD_CTRL 0xd8 +#define MISC_I2C_PAD_CTRL(bus) (MISC_I2C0_PAD_CTRL + 4 * (bus)) + +#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define I2C_PAD_CTRL_NG_NORMAL 0xc +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5)) +#define I2C_PAD_CTRL_RX_SHIFT 4 +#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 +#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) +#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) +#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ +#define I2C_PAD_CTRL_CAP_DOWN BIT(12) +#define I2C_PAD_CTRL_CAP_UP BIT(13) +#define I2C_PAD_CTRL_RES_DOWN BIT(14) +#define I2C_PAD_CTRL_RES_UP BIT(15) +#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_SPARE0 BIT(17) +#define I2C_PAD_CTRL_SPARE1 BIT(18) +/* The following bits are reserved in Picasso and Cezanne */ +#define I2C_PAD_CTRL_PD_EN BIT(19) +#define I2C_PAD_CTRL_COMP_SEL BIT(20) +#define I2C_PAD_CTRL_RES_BIAS_EN BIT(21) + +#endif /* AMD_BLOCK_I2C_PAD_DEF_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h index a4c926d246..04112ca272 100644 --- a/src/soc/amd/common/block/include/amdblocks/acp.h +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -3,17 +3,33 @@ #ifndef AMD_COMMON_ACP_H #define AMD_COMMON_ACP_H -#include #include struct acp_config { enum { +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2) + ACP_PINS_HDA_3SDI = 1, /* HDA 3xSDI */ + ACP_PINS_HDA_1SDI_1SW = 2, /* HDA 1xSDI, SW w/Data0 */ + ACP_PINS_4SW_1SW = 3, /* SW w/Data0-3, SW w/Data0 */ + ACP_PINS_HDA_3SDI_PDM2 = 4, /* HDA 3xSDI, PDM 2CH */ + ACP_PINS_HDA_1SDI_PDM6 = 5, /* HDA 1xSDI, PDM 6CH */ + ACP_PINS_HDA_1SDI_1SW_PDM2 = 6, /* HDA 1xSDI, SW w/Data0, PDM 2CH */ + ACP_PINS_4SW_PDM6 = 7, /* SW w/Data0-3, PDM 6CH */ + ACP_PINS_4SW_1SW_PDM2 = 8, /* SW w/Data0-3, SW w/Data0, PDM 2CH */ + ACP_PINS_I2S = 9, /* 3xI2S, Refclk, Intr */ + ACP_PINS_HDA_3SDI_PDM6_I2S = 10,/* HDA 3xSDI, PDM 6CH, I2S */ + ACP_PINS_HDA_3SDI_PDM8 = 11, /* HDA 3xSDI, PDM 8CH */ + ACP_PINS_HDA_1SDI_1SW_PDM6_I2S = 12,/* HDA 1xSDI, SW w/Data0, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM6_I2S = 13, /* SW w/Data0-3, SW w/Data0, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM8 = 14, /* SW w/Data0-3, SW w/Data0, PDM 8CH */ +#else I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ I2S_PINS_I2S_TDM = 4, I2S_PINS_UNCONF = 7, /* All pads will be input mode */ +#endif } acp_pin_cfg; /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 550b7d7619..e87fcdbe09 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -12,7 +12,7 @@ #define MMIO_ACPI_PM1_STS 0x00 #define MMIO_ACPI_PM1_EN 0x02 #define MMIO_ACPI_PM1_CNT_BLK 0x04 - /* sleep types defined in arch/x86/include/acpi/acpi.h */ + /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 #define MMIO_ACPI_CPU_CONTROL 0x0c diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ae8673045d..2d632f606a 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -198,31 +198,11 @@ static inline uint8_t pm2_read8(uint8_t reg) return read8(acpimmio_pmio2 + reg); } -static inline uint16_t pm2_read16(uint8_t reg) -{ - return read16(acpimmio_pmio2 + reg); -} - -static inline uint32_t pm2_read32(uint8_t reg) -{ - return read32(acpimmio_pmio2 + reg); -} - static inline void pm2_write8(uint8_t reg, uint8_t value) { write8(acpimmio_pmio2 + reg, value); } -static inline void pm2_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_pmio2 + reg, value); -} - -static inline void pm2_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_pmio2 + reg, value); -} - static inline uint8_t acpi_read8(uint8_t reg) { return read8(acpimmio_acpi + reg); diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index ff5d0db169..f4a00c73a7 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -24,7 +24,7 @@ /* Bit definitions for Device D3 State AOACx0000[41...7f; odd byte addresses] */ #define FCH_AOAC_PWR_RST_STATE BIT(0) -#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) +#define FCH_AOAC_REF_CLK_OK_STATE BIT(1) #define FCH_AOAC_RST_B_STATE BIT(2) #define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) #define FCH_AOAC_D3COLD BIT(4) diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 0627bc1377..de3fb84d12 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -3,7 +3,9 @@ #ifndef AMD_BLOCK_CPU_H #define AMD_BLOCK_CPU_H +void early_cache_setup(void); int get_cpu_count(void); +unsigned int get_threads_per_core(void); void set_cstate_io_addr(void); void write_resume_eip(void); diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 6df778d54c..604c24e16f 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -15,10 +15,10 @@ #define D18F0_MMIO_LIMIT0 0x204 #define D18F0_MMIO_SHIFT 16 #define D18F0_MMIO_CTRL0 0x208 -#define MMIO_NP BIT(12) -#define MMIO_DST_FABRIC_ID_SHIFT 4 -#define MMIO_WE BIT(1) -#define MMIO_RE BIT(0) +/* The MMIO_NP bit is SoC-specific */ +#define DF_MMIO_DST_FABRIC_ID_SHIFT 4 +#define DF_MMIO_WE BIT(1) +#define DF_MMIO_RE BIT(0) /* The number of data fabric MMIO registers is SoC-specific */ #define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index f9e25707d0..cfba50bd2d 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -3,8 +3,7 @@ #ifndef AMD_BLOCK_ESPI_H #define AMD_BLOCK_ESPI_H -#include -#include +#include /* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */ #define ESPI_OFFSET_FROM_BAR 0x10000 @@ -16,20 +15,20 @@ #define ESPI_DECODE_IO_0X60_0X64_EN (1 << 1) #define ESPI_DECODE_IO_0X2E_0X2F_EN (1 << 0) -#define ESPI_IO_BASE_OFFSET_REG0 0x44 -#define ESPI_IO_BASE_OFFSET_REG1 0x48 -#define ESPI_IO_RANGE_SIZE_OFFSET 0x4c -#define ESPI_MMIO_BASE_OFFSET_REG0 0x50 -#define ESPI_MMIO_BASE_OFFSET_REG1 0x54 -#define ESPI_MMIO_BASE_OFFSET_REG2 0x58 -#define ESPI_MMIO_BASE_OFFSET_REG3 0x5C -#define ESPI_MMIO_OFFSET_SIZE_REG0 0x60 -#define ESPI_MMIO_OFFSET_SIZE_REG1 0x64 +#define ESPI_IO_BASE_REG0 0x44 +#define ESPI_IO_BASE_REG1 0x48 +#define ESPI_IO_SIZE0 0x4c +#define ESPI_MMIO_BASE_REG0 0x50 +#define ESPI_MMIO_BASE_REG1 0x54 +#define ESPI_MMIO_BASE_REG2 0x58 +#define ESPI_MMIO_BASE_REG3 0x5c +#define ESPI_MMIO_SIZE_REG0 0x60 +#define ESPI_MMIO_SIZE_REG1 0x64 -#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_OFFSET_REG0 + ((range) & 3) * 2) -#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_RANGE_SIZE_OFFSET + ((range) & 3)) -#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_OFFSET_REG0 + ((range) & 3) * 4) -#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_OFFSET_SIZE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_BASE(range) (ESPI_IO_BASE_REG0 + ((range) & 3) * 2) +#define ESPI_IO_RANGE_SIZE(range) (ESPI_IO_SIZE0 + ((range) & 3)) +#define ESPI_MMIO_RANGE_BASE(range) (ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4) +#define ESPI_MMIO_RANGE_SIZE(range) (ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2) #define ESPI_GENERIC_IO_WIN_COUNT 4 #define ESPI_GENERIC_IO_MAX_WIN_SIZE 0x100 @@ -106,15 +105,13 @@ struct espi_config { /* * Open I/O window using the provided base and size. - * Return value: 0 = success, -1 = error. */ -int espi_open_io_window(uint16_t base, size_t size); +enum cb_err espi_open_io_window(uint16_t base, size_t size); /* * Open MMIO window using the provided base and size. - * Return value: 0 = success, -1 = error. */ -int espi_open_mmio_window(uint32_t base, size_t size); +enum cb_err espi_open_mmio_window(uint32_t base, size_t size); /* * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading @@ -124,9 +121,8 @@ void espi_update_static_bar(uintptr_t bar); /* * Perform eSPI connection setup to the slave. Currently, this supports slave0 only. - * Returns 0 on success and -1 on error. */ -int espi_setup(void); +enum cb_err espi_setup(void); /* Run mainboard configuration needed to set up eSPI */ void mb_set_up_early_espi(void); diff --git a/src/soc/amd/common/block/include/amdblocks/gpio.h b/src/soc/amd/common/block/include/amdblocks/gpio.h index 21b73f775b..7e6df9fb23 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio.h @@ -75,9 +75,6 @@ void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, const struct soc_amd_gpio *override_cfg, size_t override_num_pads); -/* Get the address of the control register of a particular pin */ -uintptr_t gpio_get_address(gpio_t gpio_num); - /** * @brief program a particular set of GPIO * diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h index 85450371d5..187be51332 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_defs.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_defs.h @@ -3,16 +3,15 @@ #ifndef AMD_BLOCK_GPIO_DEFS_H #define AMD_BLOCK_GPIO_DEFS_H -#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASTER_SWITCH 0xfc #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) #define GPIO_WAKE_EN BIT(31) -#define GPIO_WAKE_STAT_0 0x2F0 -#define GPIO_WAKE_STAT_1 0x2F4 - -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ +#define GPIO_WAKE_STAT_0 0x2f0 +#define GPIO_WAKE_STAT_1 0x2f4 +#define GPIO_IRQ_STAT_0 0x2f8 +#define GPIO_IRQ_STAT_1 0x2fc /* Pad trigger type - Level or Edge */ #define GPIO_TRIGGER_EDGE (0 << 8) @@ -41,22 +40,23 @@ #define GPIO_INT_ENABLE_STATUS (1 << 11) #define GPIO_INT_ENABLE_DELIVERY (1 << 12) -#define GPIO_INT_ENABLE_STATUS_DELIVERY \ - (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_INT_ENABLE_MASK (3 << 11) +#define GPIO_INT_ENABLE_STATUS_DELIVERY (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) +#define GPIO_INT_ENABLE_MASK (GPIO_INT_ENABLE_STATUS | GPIO_INT_ENABLE_DELIVERY) -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_MASK (GPIO_WAKE_S0i3 | GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) + +#define GPIO_PIN_STS_SHIFT 16 +#define GPIO_PIN_STS (1 << GPIO_PIN_STS_SHIFT) -#define GPIO_PIN_STS (1 << 16) -#define GPIO_8KPULLUP_SELECT (1 << 19) #define GPIO_PULLUP_ENABLE (1 << 20) #define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_PULL_MASK (7 << 19) - -#define GPIO_INPUT_SHIFT 16 -#define GPIO_INPUT_VALUE (1 << GPIO_INPUT_SHIFT) +#define GPIO_PULL_MASK (GPIO_PULLUP_ENABLE | GPIO_PULLDOWN_ENABLE) #define GPIO_OUTPUT_SHIFT 22 #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) @@ -65,15 +65,14 @@ #define GPIO_INT_STATUS (1 << 28) #define GPIO_WAKE_STATUS (1 << 29) -#define GPIO_STATUS_MASK (3 << 28) +#define GPIO_STATUS_MASK (GPIO_INT_STATUS | GPIO_WAKE_STATUS) -#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) -#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE +#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE -#define GPIO_PULL_PULL_UP_8K (GPIO_PULLUP_ENABLE | GPIO_8KPULLUP_SELECT) -#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE -#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE -#define GPIO_PULL_PULL_NONE 0 +#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE +#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 #define AMD_GPIO_MUX_MASK 0x03 @@ -104,18 +103,19 @@ #define GPIO_FLAG_EVENT_TRIGGER_EDGE_LOW (GPIO_FLAG_EVENT_TRIGGER_EDGE | \ GPIO_FLAG_EVENT_ACTIVE_LOW) #define DEB_GLITCH_SHIFT 5 +#define DEB_GLITCH_NO_DEBOUNCE 0 #define DEB_GLITCH_LOW 1 #define DEB_GLITCH_HIGH 2 -#define DEB_GLITCH_NONE 3 +#define DEB_GLITCH_REMOVE 3 +#define GPIO_DEB_PRESERVE_GLITCH (DEB_GLITCH_NO_DEBOUNCE << DEB_GLITCH_SHIFT) #define GPIO_DEB_PRESERVE_LOW_GLITCH (DEB_GLITCH_LOW << DEB_GLITCH_SHIFT) #define GPIO_DEB_PRESERVE_HIGH_GLITCH (DEB_GLITCH_HIGH << DEB_GLITCH_SHIFT) -#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_NONE << DEB_GLITCH_SHIFT) +#define GPIO_DEB_REMOVE_GLITCH (DEB_GLITCH_REMOVE << DEB_GLITCH_SHIFT) #define GPIO_TIMEBASE_61uS 0 #define GPIO_TIMEBASE_183uS (1 << 4) #define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | GPIO_TIMEBASE_15560uS) #define GPIO_DEB_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_60uS (1 | GPIO_TIMEBASE_61uS) #define GPIO_DEB_120uS (2 | GPIO_TIMEBASE_61uS) @@ -131,14 +131,6 @@ #define GPIO_DEB_MASK 0xff -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S3 (GPIO_WAKE_S0i3 | GPIO_WAKE_S3) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_MASK (7 << 13) - /* * Mask used to reset bits in GPIO control register when configuring pad using `program_gpios()` * Bits that are preserved/untouched: diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 6660e3779c..b02487a32a 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -56,6 +56,26 @@ struct soc_i2c_peripheral_reset_info { size_t num_pins; }; +enum i2c_pad_rx_level { + I2C_PAD_RX_NO_CHANGE, + I2C_PAD_RX_OFF, + I2C_PAD_RX_3_3V, + I2C_PAD_RX_1_8V, + I2C_PAD_RX_1_1V, +}; + +struct i2c_pad_control { + enum i2c_pad_rx_level rx_level; +}; + +void fch_i2c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl); + +void fch_i23c_pad_init(unsigned int bus, + enum i2c_speed speed, + const struct i2c_pad_control *ctrl); + /* Helper function to perform misc I2C configuration specific to SoC. */ void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg); diff --git a/src/soc/amd/common/block/include/amdblocks/ioapic.h b/src/soc/amd/common/block/include/amdblocks/ioapic.h index 4c10a84a03..bd1c363242 100644 --- a/src/soc/amd/common/block/include/amdblocks/ioapic.h +++ b/src/soc/amd/common/block/include/amdblocks/ioapic.h @@ -3,7 +3,8 @@ #ifndef AMD_BLOCK_IOAPIC_H #define AMD_BLOCK_IOAPIC_H -#define FCH_IOAPIC_ID CONFIG_MAX_CPUS -#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1) +/* Since the old APIC bus isn't used any more, the IOAPIC IDs can be < CONFIG_MAX_CPUS */ +#define FCH_IOAPIC_ID 0 +#define GNB_IOAPIC_ID 1 #endif /* AMD_BLOCK_IOAPIC_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 09eafb8b07..558b608743 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -10,6 +10,8 @@ #define LEGACY_DMA_EN BIT(2) #define VW_ROM_SHARING_EN BIT(3) #define EXT_ROM_SHARING_EN BIT(4) +#define SPI_ROM_BIOS_SEMAPHORE BIT(5) +#define SPI_ROM_EC_SEMAPHORE BIT(6) #define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) @@ -67,24 +69,12 @@ #define LPC_SELECT_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 -/* Assuming word access to higher word (register 0x4a) */ -#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a -#define LPC_WIDEIO2_ENABLE_H BIT(9) -#define LPC_WIDEIO1_ENABLE_H BIT(8) -#define DECODE_IO_PORT_ENABLE6_H BIT(7) -#define DECODE_IO_PORT_ENABLE5_H BIT(6) -#define DECODE_IO_PORT_ENABLE4_H BIT(5) -#define DECODE_IO_PORT_ENABLE3_H BIT(3) -#define DECODE_IO_PORT_ENABLE2_H BIT(2) -#define DECODE_IO_PORT_ENABLE1_H BIT(1) -#define DECODE_IO_PORT_ENABLE0_H BIT(0) - #define LPC_MEM_PORT1 0x4c #define ROM_PROTECT_RANGE0 0x50 #define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ #define ROM_RANGE_WP BIT(10) #define ROM_RANGE_RP BIT(9) -#define RANGE_UNIT BIT(8) +#define RANGE_UNIT BIT(8) /* 0: 4kiB, 1: 64kiB */ #define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ #define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) #define MAX_ROM_PROTECT_RANGES 4 @@ -142,7 +132,6 @@ * with the enable bits. */ void lpc_disable_decodes(void); void lpc_enable_port80(void); -void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); /* addr = index/data to enable: LPC_SELECT_SIO_2E2F or LPC_SELECT_SIO_4E4F */ void lpc_enable_sio_decode(const bool addr); diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 2aa000e554..c9986cae00 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -5,9 +5,6 @@ #include -/* Get the mailbox base address - specific to family of device. */ -void *soc_get_mbox_address(void); - #define SMM_TRIGGER_IO 0 #define SMM_TRIGGER_MEM 1 @@ -54,6 +51,8 @@ void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */ #define PSPSTS_INVALID_NAME 8 #define PSPSTS_INVALID_BLOB 9 +/* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when + the x86 cores are released from reset. */ int psp_notify_dram(void); int psp_notify_smm(void); diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 1a6059a1be..af44765519 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -16,7 +16,7 @@ #elif CONFIG(SOC_AMD_PICASSO) #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f -#elif CONFIG(SOC_AMD_CEZANNE) +#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_SABRINA) #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f #else @@ -29,6 +29,8 @@ struct second_gen_efs { /* todo: expand for Server products */ uint32_t reserved:31; } __attribute__((packed)); +#define EFS_SECOND_GEN 0 + /* Copied from coreboot/util/amdfwtool.h */ struct embedded_firmware { uint32_t signature; /* 0x55aa55aa */ diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 35a3782f7a..4be3739bcf 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -3,6 +3,7 @@ #ifndef AMD_BLOCK_SPI_H #define AMD_BLOCK_SPI_H +#include #include #define SPI_CNTRL0 0x00 @@ -70,8 +71,8 @@ enum spi100_speed { #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc7 -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) +#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) struct spi_config { /* @@ -93,7 +94,7 @@ struct spi_config { * Perform early SPI initialization: * 1. Sets SPI ROM base and enables SPI ROM * 2. Enables SPI ROM prefetching - * 3. Disables 4dw burst + * 3. Disables 4 DWORD burst if !SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST * 4. Configures SPI speed and read mode. * * This function expects SoC to include soc_amd_common_config in chip SoC config and uses @@ -118,4 +119,8 @@ void spi_write32(uint8_t reg, uint32_t val); void fch_spi_config_modes(void); void mainboard_spi_fast_speed_override(uint8_t *fast_speed); + +/* Ensure you hold the mutex when performing SPI transactions */ +extern struct thread_mutex spi_hw_mutex; + #endif /* AMD_BLOCK_SPI_H */ diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index b6e4ac2346..9d4f38e8d9 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -12,9 +12,9 @@ static void iommu_read_resources(struct device *dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* IOMMU MMIO registers */ res = new_resource(dev, 0x44); - res->size = 512 * 1024; + res->size = 512 * KiB; res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ @@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU, + PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB_IOMMU, 0 }; diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index e775606910..64192695c6 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -16,6 +16,20 @@ config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA help Select this option to enable SPI DMA support. +# The LPC SPI DMA controller requires the source and destination to be 64 byte +# aligned. +config CBFS_CACHE_ALIGN + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + +config FSP_ALIGNMENT_FSP_S + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + +config FSP_ALIGNMENT_FSP_M + int + default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h new file mode 100644 index 0000000000..a14f10fac6 --- /dev/null +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_ESPI_DEF_H +#define AMD_BLOCK_ESPI_DEF_H + +#define ESPI_DN_TX_HDR0 0x00 +#define ESPI_DN_TX_HDR1 0x04 +#define ESPI_DN_TX_HDR2 0x08 +#define ESPI_DN_TX_DATA 0x0c + +#define ESPI_MASTER_CAP 0x2c +#define ESPI_VW_MAX_SIZE_SHIFT 13 +#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) + +#define ESPI_GLOBAL_CONTROL_0 0x30 +#define ESPI_WAIT_CNT_SHIFT 24 +#define ESPI_WAIT_CNT_MASK (0x3f << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WDG_CNT_SHIFT 8 +#define ESPI_WDG_CNT_MASK (0xffff << ESPI_WDG_CNT_SHIFT) +#define ESPI_AL_IDLE_TIMER_SHIFT 4 +#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) +#define ESPI_AL_STOP_EN (1 << 3) +#define ESPI_PR_CLKGAT_EN (1 << 2) +#define ESPI_WAIT_CHKEN (1 << 1) +#define ESPI_WDG_EN (1 << 0) + +#define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_RGCMD_INT_MAP_SHIFT 13 +#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_SHIFT 8 +#define ESPI_ERR_INT_MAP_MASK (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1f << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_SUB_DECODE_SLV_SHIFT 3 +#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) +#define ESPI_SUB_DECODE_EN (1 << 2) +#define ESPI_BUS_MASTER_EN (1 << 1) +#define ESPI_SW_RST (1 << 0) + +#define ESPI_SLAVE0_INT_EN 0x6c +#define ESPI_SLAVE0_INT_STS 0x70 +#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) +#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) +#define ESPI_STATUS_FATAL_ERROR (1 << 5) +#define ESPI_STATUS_NO_RESPONSE (1 << 4) +#define ESPI_STATUS_CRC_ERR (1 << 2) +#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) +#define ESPI_STATUS_BUS_ERROR (1 << 0) + +#define ESPI_RXVW_POLARITY 0xac + +#endif /* AMD_BLOCK_ESPI_DEF_H */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 4eb700be19..c61c61f8df 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -10,6 +10,8 @@ #include #include +#include "espi_def.h" + static uintptr_t espi_bar; void espi_update_static_bar(uintptr_t bar) @@ -58,6 +60,36 @@ static void espi_write8(unsigned int reg, uint8_t val) write8((void *)(espi_get_bar() + reg), val); } +static inline uint32_t espi_decode_io_range_en_bit(unsigned int idx) +{ + return ESPI_DECODE_IO_RANGE_EN(idx); +} + +static inline uint32_t espi_decode_mmio_range_en_bit(unsigned int idx) +{ + return ESPI_DECODE_MMIO_RANGE_EN(idx); +} + +static inline unsigned int espi_io_range_base_reg(unsigned int idx) +{ + return ESPI_IO_RANGE_BASE(idx); +} + +static inline unsigned int espi_io_range_size_reg(unsigned int idx) +{ + return ESPI_IO_RANGE_SIZE(idx); +} + +static inline unsigned int espi_mmio_range_base_reg(unsigned int idx) +{ + return ESPI_MMIO_RANGE_BASE(idx); +} + +static inline unsigned int espi_mmio_range_size_reg(unsigned int idx) +{ + return ESPI_MMIO_RANGE_SIZE(idx); +} + static void espi_enable_decode(uint32_t decode_en) { uint32_t val; @@ -80,10 +112,10 @@ static int espi_find_io_window(uint16_t win_base) int i; for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { - if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) + if (!espi_is_decode_enabled(espi_decode_io_range_en_bit(i))) continue; - if (espi_read16(ESPI_IO_RANGE_BASE(i)) == win_base) + if (espi_read16(espi_io_range_base_reg(i)) == win_base) return i; } @@ -95,7 +127,7 @@ static int espi_get_unused_io_window(void) int i; for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { - if (!espi_is_decode_enabled(ESPI_DECODE_IO_RANGE_EN(i))) + if (!espi_is_decode_enabled(espi_decode_io_range_en_bit(i))) return i; } @@ -110,12 +142,12 @@ static void espi_clear_decodes(void) espi_write16(ESPI_DECODE, 0); for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { - espi_write16(ESPI_IO_RANGE_BASE(idx), 0); - espi_write8(ESPI_IO_RANGE_SIZE(idx), 0); + espi_write16(espi_io_range_base_reg(idx), 0); + espi_write8(espi_io_range_size_reg(idx), 0); } for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { - espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0); - espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0); + espi_write32(espi_mmio_range_base_reg(idx), 0); + espi_write16(espi_mmio_range_size_reg(idx), 0); } } @@ -147,16 +179,16 @@ static int espi_std_io_decode(uint16_t base, size_t size) static size_t espi_get_io_window_size(int idx) { - return espi_read8(ESPI_IO_RANGE_SIZE(idx)) + 1; + return espi_read8(espi_io_range_size_reg(idx)) + 1; } static void espi_write_io_window(int idx, uint16_t base, size_t size) { - espi_write16(ESPI_IO_RANGE_BASE(idx), base); - espi_write8(ESPI_IO_RANGE_SIZE(idx), size - 1); + espi_write16(espi_io_range_base_reg(idx), base); + espi_write8(espi_io_range_size_reg(idx), size - 1); } -static int espi_open_generic_io_window(uint16_t base, size_t size) +static enum cb_err espi_open_generic_io_window(uint16_t base, size_t size) { size_t win_size; int idx; @@ -185,25 +217,25 @@ static int espi_open_generic_io_window(uint16_t base, size_t size) if (idx == -1) { printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, size); - printk(BIOS_ERR, "ERROR: No more available IO windows!\n"); - return -1; + printk(BIOS_ERR, "No more available IO windows!\n"); + return CB_ERR; } espi_write_io_window(idx, base, win_size); - espi_enable_decode(ESPI_DECODE_IO_RANGE_EN(idx)); + espi_enable_decode(espi_decode_io_range_en_bit(idx)); } - return 0; + return CB_SUCCESS; } -int espi_open_io_window(uint16_t base, size_t size) +enum cb_err espi_open_io_window(uint16_t base, size_t size) { int std_io; std_io = espi_std_io_decode(base, size); if (std_io != -1) { espi_enable_decode(std_io); - return 0; + return CB_SUCCESS; } else { return espi_open_generic_io_window(base, size); } @@ -214,10 +246,10 @@ static int espi_find_mmio_window(uint32_t win_base) int i; for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { - if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) + if (!espi_is_decode_enabled(espi_decode_mmio_range_en_bit(i))) continue; - if (espi_read32(ESPI_MMIO_RANGE_BASE(i)) == win_base) + if (espi_read32(espi_mmio_range_base_reg(i)) == win_base) return i; } @@ -229,7 +261,7 @@ static int espi_get_unused_mmio_window(void) int i; for (i = 0; i < ESPI_GENERIC_MMIO_WIN_COUNT; i++) { - if (!espi_is_decode_enabled(ESPI_DECODE_MMIO_RANGE_EN(i))) + if (!espi_is_decode_enabled(espi_decode_mmio_range_en_bit(i))) return i; } @@ -239,16 +271,16 @@ static int espi_get_unused_mmio_window(void) static size_t espi_get_mmio_window_size(int idx) { - return espi_read16(ESPI_MMIO_RANGE_SIZE(idx)) + 1; + return espi_read16(espi_mmio_range_size_reg(idx)) + 1; } static void espi_write_mmio_window(int idx, uint32_t base, size_t size) { - espi_write32(ESPI_MMIO_RANGE_BASE(idx), base); - espi_write16(ESPI_MMIO_RANGE_SIZE(idx), size - 1); + espi_write32(espi_mmio_range_base_reg(idx), base); + espi_write16(espi_mmio_range_size_reg(idx), size - 1); } -int espi_open_mmio_window(uint32_t base, size_t size) +enum cb_err espi_open_mmio_window(uint32_t base, size_t size) { size_t win_size; int idx; @@ -277,15 +309,15 @@ int espi_open_mmio_window(uint32_t base, size_t size) if (idx == -1) { printk(BIOS_ERR, "Cannot open IO window base %x size %zx\n", base, size); - printk(BIOS_ERR, "ERROR: No more available MMIO windows!\n"); - return -1; + printk(BIOS_ERR, "No more available MMIO windows!\n"); + return CB_ERR; } espi_write_mmio_window(idx, base, win_size); - espi_enable_decode(ESPI_DECODE_MMIO_RANGE_EN(idx)); + espi_enable_decode(espi_decode_mmio_range_en_bit(idx)); } - return 0; + return CB_SUCCESS; } static const struct espi_config *espi_get_config(void) @@ -298,25 +330,23 @@ static const struct espi_config *espi_get_config(void) return &soc_cfg->espi_config; } -static int espi_configure_decodes(const struct espi_config *cfg) +static enum cb_err espi_configure_decodes(const struct espi_config *cfg) { - int i, ret; + int i; espi_enable_decode(cfg->std_io_decode_bitmap); for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { if (cfg->generic_io_range[i].size == 0) continue; - ret = espi_open_generic_io_window(cfg->generic_io_range[i].base, - cfg->generic_io_range[i].size); - if (ret) - return ret; + if (espi_open_generic_io_window(cfg->generic_io_range[i].base, + cfg->generic_io_range[i].size) != CB_SUCCESS) + return CB_ERR; } - return 0; + return CB_SUCCESS; } -#define ESPI_DN_TX_HDR0 0x00 enum espi_cmd_type { CMD_TYPE_SET_CONFIGURATION = 0, CMD_TYPE_GET_CONFIGURATION = 1, @@ -327,53 +357,6 @@ enum espi_cmd_type { CMD_TYPE_FLASH = 7, }; -#define ESPI_DN_TX_HDR1 0x04 -#define ESPI_DN_TX_HDR2 0x08 -#define ESPI_DN_TX_DATA 0x0c - -#define ESPI_MASTER_CAP 0x2c -#define ESPI_VW_MAX_SIZE_SHIFT 13 -#define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) - -#define ESPI_GLOBAL_CONTROL_0 0x30 -#define ESPI_WAIT_CNT_SHIFT 24 -#define ESPI_WAIT_CNT_MASK (0x3F << ESPI_WAIT_CNT_SHIFT) -#define ESPI_WDG_CNT_SHIFT 8 -#define ESPI_WDG_CNT_MASK (0xFFFF << ESPI_WDG_CNT_SHIFT) -#define ESPI_AL_IDLE_TIMER_SHIFT 4 -#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) -#define ESPI_AL_STOP_EN (1 << 3) -#define ESPI_PR_CLKGAT_EN (1 << 2) -#define ESPI_WAIT_CHKEN (1 << 1) -#define ESPI_WDG_EN (1 << 0) - -#define ESPI_GLOBAL_CONTROL_1 0x34 -#define ESPI_RGCMD_INT_MAP_SHIFT 13 -#define ESPI_RGCMD_INT_MAP_MASK (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_RGCMD_INT_SMI (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) -#define ESPI_ERR_INT_MAP_SHIFT 8 -#define ESPI_ERR_INT_MAP_MASK (0x1F << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_ERR_INT_SMI (0x1F << ESPI_ERR_INT_MAP_SHIFT) -#define ESPI_SUB_DECODE_SLV_SHIFT 3 -#define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) -#define ESPI_SUB_DECODE_EN (1 << 2) -#define ESPI_BUS_MASTER_EN (1 << 1) -#define ESPI_SW_RST (1 << 0) - -#define ESPI_SLAVE0_INT_EN 0x6C -#define ESPI_SLAVE0_INT_STS 0x70 -#define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) -#define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -#define ESPI_STATUS_FATAL_ERROR (1 << 5) -#define ESPI_STATUS_NO_RESPONSE (1 << 4) -#define ESPI_STATUS_CRC_ERR (1 << 2) -#define ESPI_STATUS_WAIT_TIMEOUT (1 << 1) -#define ESPI_STATUS_BUS_ERROR (1 << 0) - -#define ESPI_RXVW_POLARITY 0xac - #define ESPI_CMD_TIMEOUT_US 100 #define ESPI_CH_READY_TIMEOUT_US 10000 @@ -427,7 +410,7 @@ struct espi_cmd { } __packed; /* Wait up to ESPI_CMD_TIMEOUT_US for hardware to clear DNCMD_STATUS bit. */ -static int espi_wait_ready(void) +static enum cb_err espi_wait_ready(void) { struct stopwatch sw; union espi_txhdr0 hdr0; @@ -436,10 +419,10 @@ static int espi_wait_ready(void) do { hdr0.val = espi_read32(ESPI_DN_TX_HDR0); if (!hdr0.cmd_sts) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); - return -1; + return CB_ERR; } /* Clear interrupt status register */ @@ -454,7 +437,7 @@ static void espi_clear_status(void) * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a * command. */ -static int espi_poll_status(uint32_t *status) +static enum cb_err espi_poll_status(uint32_t *status) { struct stopwatch sw; @@ -462,12 +445,12 @@ static int espi_poll_status(uint32_t *status) do { *status = espi_read32(ESPI_SLAVE0_INT_STS); if (*status) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); - printk(BIOS_ERR, "Error: eSPI timed out waiting for status update.\n"); + printk(BIOS_ERR, "eSPI timed out waiting for status update.\n"); - return -1; + return CB_ERR; } static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint32_t status) @@ -477,7 +460,7 @@ static void espi_show_failure(const struct espi_cmd *cmd, const char *str, uint3 printk(BIOS_ERR, "%s (Status = 0x%x)\n", str, status); } -static int espi_send_command(const struct espi_cmd *cmd) +static enum cb_err espi_send_command(const struct espi_cmd *cmd) { uint32_t status; @@ -485,9 +468,9 @@ static int espi_send_command(const struct espi_cmd *cmd) printk(BIOS_DEBUG, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI was not ready to accept a command", 0); - return -1; + return CB_ERR; } espi_clear_status(); @@ -499,36 +482,36 @@ static int espi_send_command(const struct espi_cmd *cmd) /* Dword 0 must be last as this write triggers the transaction */ espi_write32(ESPI_DN_TX_HDR0, cmd->hdr0.val); - if (espi_wait_ready() == -1) { + if (espi_wait_ready() != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI timed out waiting for command to complete", 0); - return -1; + return CB_ERR; } - if (espi_poll_status(&status) == -1) { + if (espi_poll_status(&status) != CB_SUCCESS) { espi_show_failure(cmd, "Error: eSPI poll status failed", 0); - return -1; + return CB_ERR; } /* If command did not complete downstream, return error. */ if (!(status & ESPI_STATUS_DNCMD_COMPLETE)) { espi_show_failure(cmd, "Error: eSPI downstream command completion failure", status); - return -1; + return CB_ERR; } if (status & ~(ESPI_STATUS_DNCMD_COMPLETE | cmd->expected_status_codes)) { espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status); - return -1; + return CB_ERR; } espi_write32(ESPI_SLAVE0_INT_STS, status); - return 0; + return CB_SUCCESS; } -static int espi_send_reset(void) +static enum cb_err espi_send_reset(void) { struct espi_cmd cmd = { .hdr0 = { @@ -567,7 +550,7 @@ static int espi_send_reset(void) return espi_send_command(&cmd); } -static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) +static enum cb_err espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) { struct espi_cmd cmd = { .hdr0 = { @@ -583,7 +566,7 @@ static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) }; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; return espi_send_command(&cmd); } @@ -595,7 +578,7 @@ static int espi_send_pltrst(const struct espi_config *mb_cfg, bool assert) #define ESPI_CONFIGURATION_HDATA0(a) (((a) >> 8) & 0xff) #define ESPI_CONFIGURATION_HDATA1(a) ((a) & 0xff) -static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) +static enum cb_err espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) { struct espi_cmd cmd = { .hdr0 = { @@ -608,8 +591,8 @@ static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) *config = 0; - if (espi_send_command(&cmd)) - return -1; + if (espi_send_command(&cmd) != CB_SUCCESS) + return CB_ERR; *config = espi_read32(ESPI_DN_TX_HDR1); @@ -617,10 +600,10 @@ static int espi_get_configuration(uint16_t slave_reg_addr, uint32_t *config) printk(BIOS_DEBUG, "Get configuration for slave register(0x%x): 0x%x\n", slave_reg_addr, *config); - return 0; + return CB_SUCCESS; } -static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) +static enum cb_err espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) { struct espi_cmd cmd = { .hdr0 = { @@ -637,14 +620,13 @@ static int espi_set_configuration(uint16_t slave_reg_addr, uint32_t config) return espi_send_command(&cmd); } -static int espi_get_general_configuration(uint32_t *config) +static enum cb_err espi_get_general_configuration(uint32_t *config) { - int ret = espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config); - if (ret == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_GENERAL_CFG, config) != CB_SUCCESS) + return CB_ERR; espi_show_slave_general_configuration(*config); - return 0; + return CB_SUCCESS; } static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave_caps, @@ -657,17 +639,16 @@ static void espi_set_io_mode_config(enum espi_io_mode mb_io_mode, uint32_t slave *ctrlr_config |= ESPI_IO_MODE_QUAD; break; } - printk(BIOS_ERR, "Error: eSPI Quad I/O not supported. Dropping to dual mode.\n"); - /* Intentional fall-through */ + printk(BIOS_ERR, "eSPI Quad I/O not supported. Dropping to dual mode.\n"); + __fallthrough; case ESPI_IO_MODE_DUAL: if (espi_slave_supports_dual_io(slave_caps)) { *slave_config |= ESPI_SLAVE_IO_MODE_SEL_DUAL; *ctrlr_config |= ESPI_IO_MODE_DUAL; break; } - printk(BIOS_ERR, - "Error: eSPI Dual I/O not supported. Dropping to single mode.\n"); - /* Intentional fall-through */ + printk(BIOS_ERR, "eSPI Dual I/O not supported. Dropping to single mode.\n"); + __fallthrough; case ESPI_IO_MODE_SINGLE: /* Single I/O mode is always supported. */ *slave_config |= ESPI_SLAVE_IO_MODE_SEL_SINGLE; @@ -690,16 +671,16 @@ static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave *ctrlr_config |= ESPI_OP_FREQ_66_MHZ; break; } - printk(BIOS_ERR, "Error: eSPI 66MHz not supported. Dropping to 33MHz.\n"); - /* Intentional fall-through */ + printk(BIOS_ERR, "eSPI 66MHz not supported. Dropping to 33MHz.\n"); + __fallthrough; case ESPI_OP_FREQ_33_MHZ: if (slave_max_speed_mhz >= 33) { *slave_config |= ESPI_SLAVE_OP_FREQ_SEL_33_MHZ; *ctrlr_config |= ESPI_OP_FREQ_33_MHZ; break; } - printk(BIOS_ERR, "Error: eSPI 33MHz not supported. Dropping to 16MHz.\n"); - /* Intentional fall-through */ + printk(BIOS_ERR, "eSPI 33MHz not supported. Dropping to 16MHz.\n"); + __fallthrough; case ESPI_OP_FREQ_16_MHZ: /* * eSPI spec says the minimum frequency is 20MHz, but AMD datasheets support @@ -710,7 +691,7 @@ static void espi_set_op_freq_config(enum espi_op_freq mb_op_freq, uint32_t slave *ctrlr_config |= ESPI_OP_FREQ_16_MHZ; break; } - /* Intentional fall-through */ + __fallthrough; default: die("No supported eSPI Operating Frequency!\n"); } @@ -739,7 +720,8 @@ static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t sl } } -static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_set_general_configuration(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config = 0; uint32_t ctrlr_config = 0; @@ -759,28 +741,29 @@ static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint espi_show_slave_general_configuration(slave_config); - if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) - return -1; + if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) != CB_SUCCESS) + return CB_ERR; espi_write32(ESPI_SLAVE0_CONFIG, ctrlr_config); - return 0; + return CB_SUCCESS; } -static int espi_wait_channel_ready(uint16_t slave_reg_addr) +static enum cb_err espi_wait_channel_ready(uint16_t slave_reg_addr) { struct stopwatch sw; uint32_t config; stopwatch_init_usecs_expire(&sw, ESPI_CH_READY_TIMEOUT_US); do { - espi_get_configuration(slave_reg_addr, &config); + if (espi_get_configuration(slave_reg_addr, &config) != CB_SUCCESS) + return CB_ERR; if (espi_slave_is_channel_ready(config)) - return 0; + return CB_SUCCESS; } while (!stopwatch_expired(&sw)); - printk(BIOS_ERR, "Error: Channel is not ready after %d usec (slave addr: 0x%x)\n", + printk(BIOS_ERR, "Channel is not ready after %d usec (slave addr: 0x%x)\n", ESPI_CH_READY_TIMEOUT_US, slave_reg_addr); - return -1; + return CB_ERR; } @@ -793,23 +776,24 @@ static void espi_enable_ctrlr_channel(uint32_t channel_en) espi_write32(ESPI_SLAVE0_CONFIG, reg); } -static int espi_set_channel_configuration(uint32_t slave_config, uint32_t slave_reg_addr, - uint32_t ctrlr_enable) +static enum cb_err espi_set_channel_configuration(uint32_t slave_config, + uint32_t slave_reg_addr, + uint32_t ctrlr_enable) { - if (espi_set_configuration(slave_reg_addr, slave_config) == -1) - return -1; + if (espi_set_configuration(slave_reg_addr, slave_config) != CB_SUCCESS) + return CB_ERR; if (!(slave_config & ESPI_SLAVE_CHANNEL_ENABLE)) - return 0; + return CB_SUCCESS; - if (espi_wait_channel_ready(slave_reg_addr) == -1) - return -1; + if (espi_wait_channel_ready(slave_reg_addr) != CB_SUCCESS) + return CB_ERR; espi_enable_ctrlr_channel(ctrlr_enable); - return 0; + return CB_SUCCESS; } -static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_vw_caps; uint32_t ctrlr_vw_caps; @@ -819,15 +803,15 @@ static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slav uint32_t slave_config; if (!mb_cfg->vw_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_vw_channel(slave_caps)) { - printk(BIOS_ERR, "Error: eSPI slave doesn't support VW channel!\n"); - return -1; + printk(BIOS_ERR, "eSPI slave doesn't support VW channel!\n"); + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_VW_CFG, &slave_vw_caps) != CB_SUCCESS) + return CB_ERR; ctrlr_vw_caps = espi_read32(ESPI_MASTER_CAP); ctrlr_vw_count_supp = (ctrlr_vw_caps & ESPI_VW_MAX_SIZE_MASK) >> ESPI_VW_MAX_SIZE_SHIFT; @@ -839,15 +823,16 @@ static int espi_setup_vw_channel(const struct espi_config *mb_cfg, uint32_t slav return espi_set_channel_configuration(slave_config, ESPI_SLAVE_VW_CFG, ESPI_VW_CH_EN); } -static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_periph_channel(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config; /* Peripheral channel requires BME bit to be set when enabling the channel. */ const uint32_t slave_en_mask = ESPI_SLAVE_CHANNEL_ENABLE | ESPI_SLAVE_PERIPH_BUS_MASTER_ENABLE; - if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_PERIPH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; /* * Peripheral channel is the only one which is enabled on reset. So, if the mainboard @@ -856,8 +841,8 @@ static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t */ if (mb_cfg->periph_ch_en) { if (!espi_slave_supports_periph_channel(slave_caps)) { - printk(BIOS_ERR, "Error: eSPI slave doesn't support periph channel!\n"); - return -1; + printk(BIOS_ERR, "eSPI slave doesn't support periph channel!\n"); + return CB_ERR; } slave_config |= slave_en_mask; } else { @@ -870,20 +855,20 @@ static int espi_setup_periph_channel(const struct espi_config *mb_cfg, uint32_t ESPI_PERIPH_CH_EN); } -static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->oob_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_oob_channel(slave_caps)) { - printk(BIOS_ERR, "Error: eSPI slave doesn't support OOB channel!\n"); - return -1; + printk(BIOS_ERR, "eSPI slave doesn't support OOB channel!\n"); + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_OOB_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -891,20 +876,21 @@ static int espi_setup_oob_channel(const struct espi_config *mb_cfg, uint32_t sla ESPI_OOB_CH_EN); } -static int espi_setup_flash_channel(const struct espi_config *mb_cfg, uint32_t slave_caps) +static enum cb_err espi_setup_flash_channel(const struct espi_config *mb_cfg, + uint32_t slave_caps) { uint32_t slave_config; if (!mb_cfg->flash_ch_en) - return 0; + return CB_SUCCESS; if (!espi_slave_supports_flash_channel(slave_caps)) { - printk(BIOS_ERR, "Error: eSPI slave doesn't support flash channel!\n"); - return -1; + printk(BIOS_ERR, "eSPI slave doesn't support flash channel!\n"); + return CB_ERR; } - if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) == -1) - return -1; + if (espi_get_configuration(ESPI_SLAVE_FLASH_CFG, &slave_config) != CB_SUCCESS) + return CB_ERR; slave_config |= ESPI_SLAVE_CHANNEL_ENABLE; @@ -945,7 +931,7 @@ static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg) espi_write32(ESPI_GLOBAL_CONTROL_1, global_ctrl_reg); } -int espi_setup(void) +enum cb_err espi_setup(void) { uint32_t slave_caps; const struct espi_config *cfg = espi_get_config(); @@ -970,9 +956,9 @@ int espi_setup(void) * Send in-band reset * The resets affects both host and slave devices, so set initial config again. */ - if (espi_send_reset() == -1) { - printk(BIOS_ERR, "Error: In-band reset failed!\n"); - return -1; + if (espi_send_reset() != CB_SUCCESS) { + printk(BIOS_ERR, "In-band reset failed!\n"); + return CB_ERR; } espi_set_initial_config(cfg); @@ -980,9 +966,9 @@ int espi_setup(void) * Boot sequence: Step 3 * Get configuration of slave device. */ - if (espi_get_general_configuration(&slave_caps) == -1) { - printk(BIOS_ERR, "Error: Slave GET_CONFIGURATION failed!\n"); - return -1; + if (espi_get_general_configuration(&slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Slave GET_CONFIGURATION failed!\n"); + return CB_ERR; } /* @@ -990,9 +976,9 @@ int espi_setup(void) * Step 4: Write slave device general config * Step 5: Set host slave config */ - if (espi_set_general_configuration(cfg, slave_caps) == -1) { - printk(BIOS_ERR, "Error: Slave SET_CONFIGURATION failed!\n"); - return -1; + if (espi_set_general_configuration(cfg, slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Slave SET_CONFIGURATION failed!\n"); + return CB_ERR; } /* @@ -1006,41 +992,41 @@ int espi_setup(void) * Channel setup */ /* Set up VW first so we can deassert PLTRST#. */ - if (espi_setup_vw_channel(cfg, slave_caps) == -1) { - printk(BIOS_ERR, "Error: Setup VW channel failed!\n"); - return -1; + if (espi_setup_vw_channel(cfg, slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Setup VW channel failed!\n"); + return CB_ERR; } /* Assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, true) == -1) { - printk(BIOS_ERR, "Error: PLTRST# assertion failed!\n"); - return -1; + if (espi_send_pltrst(cfg, true) != CB_SUCCESS) { + printk(BIOS_ERR, "PLTRST# assertion failed!\n"); + return CB_ERR; } /* De-assert PLTRST# if VW channel is enabled by mainboard. */ - if (espi_send_pltrst(cfg, false) == -1) { - printk(BIOS_ERR, "Error: PLTRST# deassertion failed!\n"); - return -1; + if (espi_send_pltrst(cfg, false) != CB_SUCCESS) { + printk(BIOS_ERR, "PLTRST# deassertion failed!\n"); + return CB_ERR; } - if (espi_setup_periph_channel(cfg, slave_caps) == -1) { - printk(BIOS_ERR, "Error: Setup Periph channel failed!\n"); - return -1; + if (espi_setup_periph_channel(cfg, slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Setup Periph channel failed!\n"); + return CB_ERR; } - if (espi_setup_oob_channel(cfg, slave_caps) == -1) { - printk(BIOS_ERR, "Error: Setup OOB channel failed!\n"); - return -1; + if (espi_setup_oob_channel(cfg, slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Setup OOB channel failed!\n"); + return CB_ERR; } - if (espi_setup_flash_channel(cfg, slave_caps) == -1) { - printk(BIOS_ERR, "Error: Setup Flash channel failed!\n"); - return -1; + if (espi_setup_flash_channel(cfg, slave_caps) != CB_SUCCESS) { + printk(BIOS_ERR, "Setup Flash channel failed!\n"); + return CB_ERR; } - if (espi_configure_decodes(cfg) == -1) { - printk(BIOS_ERR, "Error: Configuring decodes failed!\n"); - return -1; + if (espi_configure_decodes(cfg) != CB_SUCCESS) { + printk(BIOS_ERR, "Configuring decodes failed!\n"); + return CB_ERR; } /* Enable subtractive decode if configured */ @@ -1051,7 +1037,7 @@ int espi_setup(void) printk(BIOS_SPEW, "Finished initializing ESPI.\n"); - return 0; + return CB_SUCCESS; } /* Setup eSPI with any mainboard specific initialization. */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 496816b0f3..ebded6b87a 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -106,7 +106,7 @@ static void lpc_read_resources(struct device *dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1, IORESOURCE_SUBTRACTIVE); res = new_resource(dev, 3); /* IOAPIC */ @@ -322,9 +322,10 @@ static struct device_operations lpc_ops = { }; static const unsigned short pci_device_ids[] = { + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_SB900_LPC, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_CZ_LPC, - PCI_DEVICE_ID_AMD_FAM17H_LPC, 0 }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index fb231dd7e9..72919598a3 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -138,20 +138,11 @@ int lpc_set_wideio_range(uint16_t start, uint16_t size) void lpc_enable_port80(void) { - u8 byte; + uint32_t tmp; - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - -void lpc_enable_pci_port80(void) -{ - u8 byte; - - byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); + tmp = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + tmp |= DECODE_IO_PORT_ENABLE4; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); } void lpc_enable_sio_decode(const bool addr) diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 5c697790c8..97ba2be244 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -122,6 +121,12 @@ static void start_spi_dma_transaction(struct spi_dma_transaction *transaction) ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */ ctrl |= LPC_ROM_DMA_CTRL_START; + /* + * Ensure we have exclusive access to the SPI controller before starting the LPC SPI DMA + * transaction. + */ + thread_mutex_lock(&spi_hw_mutex); + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, ctrl); } @@ -135,9 +140,14 @@ static bool continue_spi_dma_transaction(const struct region_device *rd, if (spi_dma_is_busy()) return true; + /* + * Unlock the SPI mutex between DMA transactions to allow other users of the SPI + * controller to interleave their transactions. + */ + thread_mutex_unlock(&spi_hw_mutex); + if (spi_dma_has_error()) { - printk(BIOS_ERR, - "ERROR: SPI DMA failure: dest: %p, source: %#zx, size: %zu\n", + printk(BIOS_ERR, "SPI DMA failure: dest: %p, source: %#zx, size: %zu\n", transaction->destination, transaction->source, transaction->transfer_size); return false; diff --git a/src/soc/amd/common/block/pci/acpi_prt.c b/src/soc/amd/common/block/pci/acpi_prt.c index c4c50f5b6e..c142f57567 100644 --- a/src/soc/amd/common/block/pci/acpi_prt.c +++ b/src/soc/amd/common/block/pci/acpi_prt.c @@ -5,7 +5,6 @@ #include #include #include -#include #include static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index cb221e2289..fb4db39ac5 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -10,7 +10,7 @@ void enable_pci_mmconf(void) msr_t mmconf; mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; wrmsr(MMIO_CONF_BASE, mmconf); } diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index 9c80ef8fa4..6c5565f268 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -97,7 +97,7 @@ void write_pci_cfg_irqs(void) idx_name = sb_get_apic_reg_association(&limit); if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments" + printk(BIOS_WARNING, "Can't write PCI IRQ assignments" " because 'mainboard_pirq_data' structure does" " not exist\n"); return; diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index a1cc3d2e84..d48d49ce82 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -63,6 +62,7 @@ static const unsigned short internal_pci_gpp_ids[] = { PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC, 0 }; @@ -86,6 +86,7 @@ static const unsigned short external_pci_gpp_ids[] = { PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_PCIE_GPP, 0 }; diff --git a/src/soc/amd/common/block/pm/pmlib.c b/src/soc/amd/common/block/pm/pmlib.c index f1b0b27d6a..5ce6b7bd0e 100644 --- a/src/soc/amd/common/block/pm/pmlib.c +++ b/src/soc/amd/common/block/pm/pmlib.c @@ -31,7 +31,7 @@ void pm_set_power_failure_state(void) pwr_fail |= PWR_FAIL_PREV; break; default: - printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", + printk(BIOS_WARNING, "Unknown power-failure state: %d\n", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pwr_fail |= PWR_FAIL_OFF; break; diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index c5ec56015b..3249174adb 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -27,3 +27,19 @@ config SOC_AMD_PSP_SELECTABLE_SMU_FW and each mainboard can choose to select an appropriate fanless or fanned set of blobs. Ask your AMD representative whether your APU is considered fanless. + +config AMD_SOC_SEPARATE_EFS_SECTION + bool + help + Use separate EFS FMAP section instead of putting EFS into CBFS. The + FMAP section must begin exactly at the location the EFS needs to be + placed in the flash. This option can be used to place the EFS right + after the 128kByte EC firmware at the beginning of the flash. + +config SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL + bool + default n + depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 + help + Enable sending of set SPL message to PSP. Enable this option if the platform + will require SPL fusing to be performed by PSP. diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 2b407a2b4c..4efaf0f2a5 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -5,6 +5,14 @@ ramstage-y += psp.c smm-y += psp.c smm-y += psp_smm.c +bootblock-y += psp_efs.c +verstage-y += psp_efs.c + +ifeq ($(CONFIG_AMD_SOC_SEPARATE_EFS_SECTION),y) +bootblock-y += efs_fmap_check.c +$(call src-to-obj,bootblock,$(dir)/efs_fmap_check.c) : $(obj)/fmap_config.h +endif # CONFIG_AMD_SOC_SEPARATE_EFS_SECTION + endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) @@ -22,7 +30,4 @@ ramstage-y += psp_gen2.c smm-y += psp_gen2.c smm-y += psp_smm_gen2.c -bootblock-y += psp_efs.c -verstage-y += psp_efs.c - endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/psp/efs_fmap_check.c b/src/soc/amd/common/block/psp/efs_fmap_check.c new file mode 100644 index 0000000000..44dfe70ee0 --- /dev/null +++ b/src/soc/amd/common/block/psp/efs_fmap_check.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +_Static_assert(FMAP_SECTION_EFS_START == (FLASH_BASE_ADDR + EFS_OFFSET), + "FMAP EFS Offset does not match EFS Offset - check your config"); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index b95545923f..66f7d59224 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -55,29 +55,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header) printk(BIOS_DEBUG, "OK\n"); } -/* - * Notify the PSP that DRAM is present. Upon receiving this command, the PSP - * will load its OS into fenced DRAM that is not accessible to the x86 cores. - */ -int psp_notify_dram(void) -{ - int cmd_status; - struct mbox_default_buffer buffer = { - .header = { - .size = sizeof(buffer) - } - }; - - printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - return cmd_status; -} - /* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 38d62066b2..11686aab22 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -8,7 +8,6 @@ #include /* x86 to PSP commands */ -#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMM_INFO 0x02 #define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 @@ -18,11 +17,18 @@ #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_SET_SPL_FUSE 0x2d +#define MBOX_BIOS_CMD_QUERY_SPL_FUSE 0x47 #define MBOX_BIOS_CMD_ABORT 0xfe -/* x86 to PSP commands, v1 */ + +/* x86 to PSP commands, v1-only */ +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 #define MBOX_BIOS_CMD_SMU_FW 0x19 #define MBOX_BIOS_CMD_SMU_FW2 0x1a +#define CORE_2_PSP_MSG_38_OFFSET 0x10998 +#define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12) + /* generic PSP interface status, v1 */ #define PSPV1_STATUS_INITIALIZED BIT(0) #define PSPV1_STATUS_ERROR BIT(1) @@ -30,10 +36,6 @@ #define PSPV1_STATUS_HALT BIT(3) #define PSPV1_STATUS_RECOVERY BIT(4) -/* generic PSP interface status, v2 */ -#define PSPV2_STATUS_ERROR BIT(30) -#define PSPV2_STATUS_RECOVERY BIT(31) - /* psp_mbox consists of hardware registers beginning at PSPx000070 * mbox_command: BIOS->PSP command, cleared by PSP when complete * mbox_status: BIOS->PSP interface status @@ -106,6 +108,11 @@ struct mbox_cmd_sx_info_buffer { u8 sleep_type; } __attribute__((packed, aligned(32))); +struct mbox_cmd_late_spl_buffer { + struct mbox_buffer_header header; + uint32_t spl_value; +} __attribute__((packed, aligned(32))); + #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ @@ -114,4 +121,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); /* This command needs to be implemented by the generation specific code. */ int send_psp_command(u32 command, void *buffer); +enum cb_err soc_read_c2p38(uint32_t *msg_38_value); + #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 076d3548e9..37257ba92e 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include +#include +#include #include #include #include @@ -8,8 +12,39 @@ #include #include #include +#include +#include #include "psp_def.h" +#define PSP_MAILBOX_OFFSET 0x70 + +static void *soc_get_mbox_address(void) +{ + uintptr_t psp_mmio; + + /* Check for presence of the PSP */ + if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { + printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", + PSP_DEV, PSP_FUNC); + return 0; + } + + /* Determine if Bar3Hide has been set, and if hidden get the base from + * the MSR instead. */ + if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { + psp_mmio = rdmsr(PSP_ADDR_MSR).lo; + if (!psp_mmio) { + printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); + return 0; + } + } else { + psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + } + + return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); +} + static u32 rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); @@ -135,3 +170,26 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name) cbfs_unmap(blob); return cmd_status; } + +/* + * Notify the PSP that DRAM is present. Upon receiving this command, the PSP + * will load its OS into fenced DRAM that is not accessible to the x86 cores. + */ +int psp_notify_dram(void) +{ + int cmd_status; + struct mbox_default_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; + + printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); + + cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + psp_print_cmd_status(cmd_status, &buffer.header); + + return cmd_status; +} diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index e2f51d8206..e5f23cd5b1 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,7 +20,7 @@ static uintptr_t soc_get_psp_base_address(void) return psp_mmio; } -void *soc_get_mbox_address(void) +static void *soc_get_mbox_address(void) { uintptr_t psp_mmio = soc_get_psp_base_address(); if (!psp_mmio) @@ -120,3 +121,44 @@ int send_psp_command(u32 command, void *buffer) return 0; } + +enum cb_err soc_read_c2p38(uint32_t *msg_38_value) +{ + uintptr_t psp_mmio = soc_get_psp_base_address(); + + if (!psp_mmio) { + printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); + return CB_ERR; + } + *msg_38_value = read32((void *)psp_mmio + CORE_2_PSP_MSG_38_OFFSET); + return CB_SUCCESS; +} + +static void psp_set_spl_fuse(void *unused) +{ + if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL)) + return; + + uint32_t msg_38_value = 0; + int cmd_status = 0; + struct mbox_cmd_late_spl_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; + + if (soc_read_c2p38(&msg_38_value) != CB_SUCCESS) { + printk(BIOS_ERR, "PSP: Failed to read psp base address.\n"); + return; + } + + if (msg_38_value & CORE_2_PSP_MSG_38_FUSE_SPL) { + printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n"); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer); + psp_print_cmd_status(cmd_status, NULL); + } else { + printk(BIOS_DEBUG, "PSP: Fuse SPL not requested\n"); + } +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, psp_set_spl_fuse, NULL); diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 79c381e6cd..9caec89998 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -6,8 +6,6 @@ #include #include -void __weak soc_enable_sata_features(struct device *dev) { } - static const char *sata_acpi_name(const struct device *dev) { return "STCR"; diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index ce66cbbb7a..ae2edc1506 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -89,5 +89,6 @@ static struct device_operations smbus_ops = { static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_AMD, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, }; diff --git a/src/soc/amd/common/block/smu/smu.c b/src/soc/amd/common/block/smu/smu.c index f48a9d5c45..d68867cae9 100644 --- a/src/soc/amd/common/block/smu/smu.c +++ b/src/soc/amd/common/block/smu/smu.c @@ -29,7 +29,7 @@ static int32_t smu_poll_response(bool print_command_duration) } } while (!stopwatch_expired(&sw)); - printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + printk(BIOS_ERR, "timeout sending SMU message\n"); return SMU_MESG_RESP_TIMEOUT; } diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index eb67597193..7a300e496a 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -6,7 +6,7 @@ config SOC_AMD_COMMON_BLOCK_SPI instead of individual SPI specific code. config SOC_AMD_COMMON_BLOCK_SPI_DEBUG - bool + bool "Enable SPI debugging" config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST bool diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index fad8cd9951..5ef900c3c5 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -74,7 +74,7 @@ static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) static void fch_spi_set_spi100(uint8_t norm, uint8_t fast, uint8_t alt, uint8_t tpm) { spi_write16(SPI100_SPEED_CONFIG, SPI_SPEED_CFG(norm, fast, alt, tpm)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); + spi_write16(SPI100_ENABLE, SPI_USE_SPI100 | spi_read16(SPI100_ENABLE)); } static void fch_spi_configure_4dw_burst(void) diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 565fdbe149..b2fe13d107 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -30,27 +30,46 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static void dump_state(const char *str, u8 phase) +enum spi_dump_state_phase { + SPI_DUMP_STATE_BEFORE_CMD, + SPI_DUMP_STATE_AFTER_CMD, +}; + +static void dump_state(enum spi_dump_state_phase phase) { u8 dump_size; - u32 addr; + uintptr_t addr; if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; - printk(BIOS_DEBUG, "SPI: %s\n", str); + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: + printk(BIOS_DEBUG, "SPI: Before execute\n"); + break; + case SPI_DUMP_STATE_AFTER_CMD: + printk(BIOS_DEBUG, "SPI: Transaction finished\n"); + break; + default: /* We shouldn't reach this */ + return; + } + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); addr = spi_get_bar() + SPI_FIFO; - if (phase == 0) { + + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - } else { + break; + case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); addr += spi_read8(SPI_TX_BYTE_COUNT); + break; } if (dump_size > 0) @@ -74,15 +93,16 @@ static int wait_for_ready(void) static int execute_command(void) { - dump_state("Before execute", 0); + dump_state(SPI_DUMP_STATE_BEFORE_CMD); spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); - if (wait_for_ready()) - printk(BIOS_ERR, - "FCH_SC Error: Timeout executing command\n"); + if (wait_for_ready()) { + printk(BIOS_ERR, "FCH SPI Error: Timeout executing command\n"); + return -1; + } - dump_state("Transaction finished", 1); + dump_state(SPI_DUMP_STATE_AFTER_CMD); return 0; } @@ -101,8 +121,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, const uint8_t *bufout = dout; if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) - printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, - bytesin); + printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout, bytesin); /* First byte is cmd which cannot be sent through FIFO */ cmd = bufout[0]; @@ -116,7 +135,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * and followed by other SPI commands. */ if (bytesout + bytesin > SPI_FIFO_DEPTH) { - printk(BIOS_WARNING, "FCH_SC: Too much to transfer, code error!\n"); + printk(BIOS_WARNING, "FCH SPI: Too much to transfer, code error!\n"); return -1; } @@ -142,7 +161,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, static int xfer_vectors(const struct spi_slave *slave, struct spi_op vectors[], size_t count) { - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + int rc; + + thread_mutex_lock(&spi_hw_mutex); + rc = spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); + thread_mutex_unlock(&spi_hw_mutex); + + return rc; } static int protect_a_range(u32 value) diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c index 5cef565baf..862962f0bd 100644 --- a/src/soc/amd/common/block/spi/fch_spi_util.c +++ b/src/soc/amd/common/block/spi/fch_spi_util.c @@ -6,6 +6,9 @@ #include #include +/* Global SPI controller mutex */ +struct thread_mutex spi_hw_mutex; + static uintptr_t spi_base; void spi_set_base(void *base) diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index 61d43f7aae..64a568556b 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -28,7 +28,7 @@ static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed) case MEMORY_TYPE_LPDDR4: return lpddr4_speed_mhz_to_reported_mts(speed); default: - printk(BIOS_ERR, "ERROR: Unknown memory type %x", ddr_type); + printk(BIOS_ERR, "Unknown memory type %x", ddr_type); return 0; } } @@ -52,10 +52,11 @@ static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); + dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->MemoryType, + dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/amd/common/fsp/fsp_reset.c b/src/soc/amd/common/fsp/fsp_reset.c index 62480bf319..0a89dc728a 100644 --- a/src/soc/amd/common/fsp/fsp_reset.c +++ b/src/soc/amd/common/fsp/fsp_reset.c @@ -8,7 +8,7 @@ void chipset_handle_reset(uint32_t status) { - printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", + printk(BIOS_ERR, "unexpected call to %s(0x%08x). Doing cold reset.\n", __func__, status); BUG(); do_cold_reset(); diff --git a/src/soc/amd/common/fsp/fsp_validate.c b/src/soc/amd/common/fsp/fsp_validate.c index 4d6a8f72bc..d9ff5026b3 100644 --- a/src/soc/amd/common/fsp/fsp_validate.c +++ b/src/soc/amd/common/fsp/fsp_validate.c @@ -4,12 +4,49 @@ #include #include +struct amd_image_revision { + uint8_t build; + uint8_t revision; + uint8_t minor; + uint8_t major; +} __packed; + /* Validate the FSP-M header in romstage */ void soc_validate_fspm_header(const struct fsp_header *hdr) { + struct amd_image_revision *rev; + + rev = (struct amd_image_revision *) &(hdr->image_revision); + /* Check if the image fits into the reserved memory region */ if (hdr->image_size > CONFIG_FSP_M_SIZE) - die("The FSP-M binary is %u bytes larger than the memory region allocated for " - "it. Increase FSP_M_SIZE to make it fit.\n", + die("The FSP-M binary is %u bytes larger than the memory region" + " allocated for it. Increase FSP_M_SIZE to make it fit.\n", hdr->image_size - CONFIG_FSP_M_SIZE); + + /* a coding bug on the AMD FSP side makes this value 1 in + older versions of the FSP.*/ + if (hdr->image_revision == 1) { + printk(BIOS_ERR, "No AMD FSP image revision information available\n"); + return; + } + + printk(BIOS_INFO, "FSP major = %d\n", rev->major); + printk(BIOS_INFO, "FSP minor = %d\n", rev->minor); + printk(BIOS_INFO, "FSP revision = %d\n", rev->revision); + printk(BIOS_INFO, "FSP build = %d\n", rev->build); + + if ((rev->major != IMAGE_REVISION_MAJOR_VERSION) || + (rev->minor != IMAGE_REVISION_MINOR_VERSION)) { + printk(BIOS_WARNING, "FSP binary and SOC FSP header file don't match.\n"); + printk(BIOS_WARNING, "include file ImageRevisionMajorVersion=%d\n", + IMAGE_REVISION_MAJOR_VERSION); + printk(BIOS_WARNING, "include file ImageRevisionMinorVersion=%d\n", + IMAGE_REVISION_MINOR_VERSION); + printk(BIOS_WARNING, "Please update FspmUpd.h based on the corresponding FSP" + " build's FspmUpd.h\n"); + } + + if (rev->major != IMAGE_REVISION_MAJOR_VERSION) + die("IMAGE_REVISION_MAJOR_VERSION mismatch, halting\nGoodbye now\n"); } diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c index 2ea8dfcdbf..5e3c368c0f 100644 --- a/src/soc/amd/common/fsp/pci/pci_routing_info.c +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c @@ -26,7 +26,7 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries) &hob_size); if (routing_hob == NULL || hob_size == 0 || routing_hob->num_of_entries == 0) { - printk(BIOS_ERR, "ERROR: Couldn't find valid PCIe interrupt routing HOB.\n"); + printk(BIOS_ERR, "Couldn't find valid PCIe interrupt routing HOB.\n"); return NULL; } diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index ca576bad99..8ee962b7b0 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -11,6 +10,7 @@ #include #include #include +#include void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {} void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -78,7 +78,7 @@ static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, status = module_dispatch(AMD_CREATE_STRUCT, &aip->StdHeader); if (status != AGESA_SUCCESS) { - printk(BIOS_ERR, "Error: AmdCreateStruct() for 0x%x returned 0x%x. " + printk(BIOS_ERR, "AmdCreateStruct() for 0x%x returned 0x%x. " "Proper system initialization may not be possible.\n", aip->AgesaFunctionName, status); } diff --git a/src/soc/amd/common/pi/amd_late_init.c b/src/soc/amd/common/pi/amd_late_init.c index 25aaea37bf..4d2250b5ce 100644 --- a/src/soc/amd/common/pi/amd_late_init.c +++ b/src/soc/amd/common/pi/amd_late_init.c @@ -36,10 +36,11 @@ static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); + dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->MemoryType, + dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c index 0d799b94d2..414de6f8ce 100644 --- a/src/soc/amd/common/pi/def_callouts.c +++ b/src/soc/amd/common/pi/def_callouts.c @@ -72,7 +72,7 @@ AGESA_STATUS GetBiosCallout(uint32_t Func, uintptr_t Data, void *ConfigPtr) } if (i >= BiosCalloutsLen) { - printk(BIOS_ERR, "ERROR: AGESA Callout Not Supported: 0x%x\n", + printk(BIOS_ERR, "AGESA Callout Not Supported: 0x%x\n", (u32)Func); return AGESA_UNSUPPORTED; } diff --git a/src/soc/amd/common/pi/refcode_loader.c b/src/soc/amd/common/pi/refcode_loader.c index d9704e0548..fb62796b13 100644 --- a/src/soc/amd/common/pi/refcode_loader.c +++ b/src/soc/amd/common/pi/refcode_loader.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/pi/s3_resume.c b/src/soc/amd/common/pi/s3_resume.c index 2094931dca..b7df396650 100644 --- a/src/soc/amd/common/pi/s3_resume.c +++ b/src/soc/amd/common/pi/s3_resume.c @@ -53,7 +53,7 @@ AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) stage_cache_get_raw(STAGE_S3_DATA, &base, &size); if (!base || !size) { - printk(BIOS_ERR, "Error: S3 volatile data not found\n"); + printk(BIOS_ERR, "S3 volatile data not found\n"); return AGESA_FATAL; } diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 834abaaa5f..45a5d22423 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -5,3 +5,19 @@ config PSP_VERSTAGE_CCP_DMA Configure PSP Verstage to use Crypto Co-processor (CCP) DMA while accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. + +config PSP_S0I3_RESUME_VERSTAGE + bool "S0i3 resume verstage" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default n + help + Select this item to enable running verstage during S0i3 resume. + +config PSP_INIT_TPM_ON_S0I3_RESUME + bool + depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE + default PSP_S0I3_RESUME_VERSTAGE + help + If the TPM is reset while in S0i3, it must be reinitialized + during s0i3 resume. This must be performed in PSP verstage since + coreboot is otherwise not involved with s0i3 resume. diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index f578bcb339..fca4c9a0af 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -152,15 +152,29 @@ uint32_t verstage_soc_early_init(void) return map_fch_devices(); } -void verstage_soc_init(void) +void verstage_soc_espi_init(void) { - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - espi_setup(); + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + return; + printk(BIOS_DEBUG, "Setting up espi\n"); + espi_setup(); +} - enable_aoac_devices(); +void verstage_soc_i2c_init(void) +{ printk(BIOS_DEBUG, "Setting up i2c\n"); i2c_soc_early_init(); - printk(BIOS_DEBUG, "i2c setup\n"); +} + +void verstage_soc_aoac_init(void) +{ + printk(BIOS_DEBUG, "Setting up aoac\n"); + enable_aoac_devices(); +} + +void verstage_soc_spi_init(void) +{ + printk(BIOS_DEBUG, "Setting up spi\n"); fch_spi_config_modes(); show_spi_speeds_and_modes(); } diff --git a/src/soc/amd/common/psp_verstage/include/arch/smp/spinlock.h b/src/soc/amd/common/psp_verstage/include/arch/smp/spinlock.h deleted file mode 100644 index 0a3a4d4676..0000000000 --- a/src/soc/amd/common/psp_verstage/include/arch/smp/spinlock.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _ARCH_SMP_SPINLOCK_H -#define _ARCH_SMP_SPINLOCK_H - -#define DECLARE_SPIN_LOCK(x) -#define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while (0) -#define spin_lock(lock) do {} while (0) -#define spin_unlock(lock) do {} while (0) - -#include -#define boot_cpu() 1 - -#endif diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 7687ac6da0..8c195781d1 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -20,6 +20,7 @@ #define POSTCODE_EARLY_INIT 0x02 #define POSTCODE_LATE_INIT 0x03 #define POSTCODE_VERSTAGE_MAIN 0x04 +#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 #define POSTCODE_SAVE_BUFFERS 0x0E #define POSTCODE_UPDATE_BOOT_REGION 0x0F @@ -35,6 +36,9 @@ #define POSTCODE_FMAP_REGION_MISSING 0xC8 #define POSTCODE_AMD_FW_MISSING 0xC9 #define POSTCODE_CMOS_RECOVERY 0xCA +#define POSTCODE_EARLY_INIT_ERROR 0xCB +#define POSTCODE_INIT_TPM_FAILED 0xCC + #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 @@ -47,14 +51,19 @@ void test_svc_calls(void); uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); -void verstage_soc_init(void); +void verstage_mainboard_espi_init(void); +void verstage_mainboard_tpm_init(void); +void verstage_soc_aoac_init(void); +void verstage_soc_espi_init(void); +void verstage_soc_i2c_init(void); +void verstage_soc_spi_init(void); uintptr_t *map_spi_rom(void); -uint32_t get_max_workbuf_size(uint32_t *size); uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset); uint32_t save_uapp_data(void *address, uint32_t size); uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table); int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, struct sha_generic_data *sha_op); +void platform_report_mode(int developer_mode_enabled); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/printk.c b/src/soc/amd/common/psp_verstage/printk.c index c56f78c298..526b8e7a09 100644 --- a/src/soc/amd/common/psp_verstage/printk.c +++ b/src/soc/amd/common/psp_verstage/printk.c @@ -4,11 +4,13 @@ #include #include #include +#include #include void console_hw_init(void) { __cbmemc_init(); + __uart_init(); } int printk(int msg_level, const char *fmt, ...) @@ -33,8 +35,13 @@ int vprintk(int msg_level, const char *fmt, va_list args) return 0; cnt = vsnprintf(buf, sizeof(buf), fmt, args); - for (i = 0; i < cnt; i++) + for (i = 0; i < cnt; i++) { __cbmemc_tx_byte(buf[i]); + + if (buf[i] == '\n') + __uart_tx_byte('\r'); + __uart_tx_byte(buf[i]); + } svc_debug_print(buf); return i; } diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index c03cf9b22e..05f0cdac39 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -10,7 +10,10 @@ #include #include #include +#include #include +#include +#include #include #include #include @@ -22,16 +25,7 @@ extern char _bss_start, _bss_end; -void __weak verstage_mainboard_early_init(void) {} void __weak verstage_mainboard_init(void) {} -uint32_t __weak get_max_workbuf_size(uint32_t *size) -{ - /* This svc only exists in picasso and deprecated for later platforms. - * Provide sane default function here for those platforms. - */ - *size = (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); - return 0; -} static void reboot_into_recovery(struct vb2_context *ctx, uint32_t subcode) { @@ -97,12 +91,12 @@ static uint32_t update_boot_region(struct vb2_context *ctx) amdfw_location = cbfs_map(fname, NULL); if (!amdfw_location) { - printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); + printk(BIOS_ERR, "AMD Firmware table not found.\n"); return POSTCODE_AMD_FW_MISSING; } ef_table = (struct embedded_firmware *)amdfw_location; if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { - printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); + printk(BIOS_ERR, "ROMSIG address is not correct.\n"); return POSTCODE_ROMSIG_MISMATCH_ERROR; } @@ -113,16 +107,22 @@ static uint32_t update_boot_region(struct vb2_context *ctx) bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + (uint32_t)boot_dev_base); if (*psp_dir_in_spi != PSP_COOKIE) { - printk(BIOS_ERR, "Error: PSP Directory address is not correct.\n"); + printk(BIOS_ERR, "PSP Directory address is not correct.\n"); return POSTCODE_PSP_COOKIE_MISMATCH_ERROR; } if (*bios_dir_in_spi != BDT1_COOKIE) { - printk(BIOS_ERR, "Error: BIOS Directory address is not correct.\n"); + printk(BIOS_ERR, "BIOS Directory address is not correct.\n"); return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR; } + /* EFS2 uses relative address and PSP isn't happy with that */ + if (ef_table->efs_gen.gen == EFS_SECOND_GEN) { + psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK); + bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK); + } + if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) { - printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n"); + printk(BIOS_ERR, "Updated BIOS Directory could not be set.\n"); return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR; } @@ -133,51 +133,21 @@ static uint32_t update_boot_region(struct vb2_context *ctx) * Save workbuf (and soon memory console and timestamps) to the bootloader to pass * back to coreboot. */ -static uint32_t save_buffers(struct vb2_context **ctx) +static uint32_t save_buffers(void) { uint32_t retval; - uint32_t buffer_size = MIN_TRANSFER_BUFFER_SIZE; - uint32_t max_buffer_size; + uint32_t buffer_size; struct transfer_info_struct buffer_info = {0}; - /* - * This should never fail on picasso, but if it does, we should still - * try to save the buffer. If that fails, then we should go to - * recovery mode. - */ - if (get_max_workbuf_size(&max_buffer_size)) { - post_code(POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE); - printk(BIOS_NOTICE, "Notice: using default transfer buffer size.\n"); - max_buffer_size = MIN_TRANSFER_BUFFER_SIZE; - } - printk(BIOS_DEBUG, "\nMaximum buffer size: %d bytes\n", max_buffer_size); + buffer_size = + (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); - /* Shrink workbuf if MP2 is in use and cannot be used to save buffer */ - if (max_buffer_size < VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) { - retval = vb2api_relocate(_vboot2_work, _vboot2_work, MIN_WORKBUF_TRANSFER_SIZE, - ctx); - if (retval != VB2_SUCCESS) { - printk(BIOS_ERR, "Error shrinking workbuf. Error code %#x\n", retval); - buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; - post_code(POSTCODE_WORKBUF_RESIZE_WARNING); - } - } else { - buffer_size = - (uint32_t)((uintptr_t)_etransfer_buffer - (uintptr_t)_transfer_buffer); - - buffer_info.console_offset = (uint32_t)((uintptr_t)_preram_cbmem_console - - (uintptr_t)_transfer_buffer); - buffer_info.timestamp_offset = (uint32_t)((uintptr_t)_timestamp - - (uintptr_t)_transfer_buffer); - buffer_info.fmap_offset = (uint32_t)((uintptr_t)_fmap_cache - - (uintptr_t)_transfer_buffer); - } - - if (buffer_size > max_buffer_size) { - printk(BIOS_ERR, "Error: Buffer is larger than max buffer size.\n"); - post_code(POSTCODE_WORKBUF_BUFFER_SIZE_ERROR); - return POSTCODE_WORKBUF_BUFFER_SIZE_ERROR; - } + buffer_info.console_offset = (uint32_t)((uintptr_t)_preram_cbmem_console - + (uintptr_t)_transfer_buffer); + buffer_info.timestamp_offset = (uint32_t)((uintptr_t)_timestamp - + (uintptr_t)_transfer_buffer); + buffer_info.fmap_offset = (uint32_t)((uintptr_t)_fmap_cache - + (uintptr_t)_transfer_buffer); buffer_info.magic_val = TRANSFER_MAGIC_VAL; buffer_info.struct_bytes = sizeof(buffer_info); @@ -189,18 +159,49 @@ static uint32_t save_buffers(struct vb2_context **ctx) retval = save_uapp_data((void *)_transfer_buffer, buffer_size); if (retval) { - printk(BIOS_ERR, "Error: Could not save workbuf. Error code 0x%08x\n", retval); + printk(BIOS_ERR, "Could not save workbuf. Error code 0x%08x\n", retval); return POSTCODE_WORKBUF_SAVE_ERROR; } return 0; } +/* + * S0i3 resume in PSP verstage is a special case. The FSDL is restoring mostly + * everything, so do the minimum necessary here. Unlike normal boot, subsequent + * coreboot stages are not run after s0i3 verstage. + * If the TPM is reset in S0i3, it must be re-initialized here. + */ +static void psp_verstage_s0i3_resume(void) +{ + uint32_t rv; + + post_code(POSTCODE_VERSTAGE_S0I3_RESUME); + + printk(BIOS_DEBUG, "Entering PSP verstage S0i3 resume\n"); + + if (!CONFIG(PSP_INIT_TPM_ON_S0I3_RESUME)) + return; + + rv = tpm_setup(true); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tpm_setup failed rv:%d\n", rv); + reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); + } + + rv = tlcl_disable_platform_hierarchy(); + if (rv != TPM_SUCCESS) { + printk(BIOS_ERR, "tlcl_disable_platform_hierarchy failed rv:%d\n", rv); + reboot_into_recovery(vboot_get_context(), POSTCODE_INIT_TPM_FAILED); + } +} + void Main(void) { uint32_t retval; struct vb2_context *ctx = NULL; void *boot_dev_base; + uint32_t bootmode; /* * Do not use printk() before console_init() @@ -217,16 +218,56 @@ void Main(void) svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); if (retval) { - svc_debug_print("verstage_soc_early_init failed\n"); - reboot_into_recovery(NULL, retval); + /* + * If verstage_soc_early_init fails, cmos is probably not + * accessible, so rebooting into recovery is not an option. + * Just reboot and hope for the best. + */ + svc_write_postcode(POSTCODE_EARLY_INIT_ERROR); + svc_debug_print("verstage_soc_early_init failed! -- rebooting\n"); + vboot_reboot(); } - svc_debug_print("calling verstage_mainboard_early_init\n"); + printk(BIOS_DEBUG, "calling verstage_mainboard_espi_init\n"); + verstage_mainboard_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); + verstage_soc_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_mainboard_tpm_init\n"); + /* mainboard_tpm_init may check board_id, so make sure espi is ready first */ + verstage_mainboard_tpm_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); + verstage_soc_aoac_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_i2c_init\n"); + verstage_soc_i2c_init(); + + /* + * S0i3 resume in PSP verstage is a special case, handle it separately. + * Make sure TPM i2c is ready first. + */ + svc_get_boot_mode(&bootmode); + if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) { + psp_verstage_s0i3_resume(); + + post_code(POSTCODE_UNMAP_FCH_DEVICES); + unmap_fch_devices(); + + post_code(POSTCODE_LEAVING_VERSTAGE); + svc_exit(0); + } + + printk(BIOS_DEBUG, "calling verstage_mainboard_early_init\n"); verstage_mainboard_early_init(); svc_write_postcode(POSTCODE_LATE_INIT); fch_io_enable_legacy_io(); - verstage_soc_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n"); + verstage_soc_spi_init(); + verstage_mainboard_init(); post_code(POSTCODE_VERSTAGE_MAIN); @@ -238,6 +279,8 @@ void Main(void) if (retval) reboot_into_recovery(ctx, retval); + platform_report_mode(vboot_developer_mode_enabled()); + post_code(POSTCODE_UPDATE_BOOT_REGION); /* @@ -254,7 +297,7 @@ void Main(void) reboot_into_recovery(ctx, retval); post_code(POSTCODE_SAVE_BUFFERS); - retval = save_buffers(&ctx); + retval = save_buffers(); if (retval) reboot_into_recovery(ctx, retval); diff --git a/src/soc/amd/common/psp_verstage/vboot_crypto.c b/src/soc/amd/common/psp_verstage/vboot_crypto.c index 581d92485f..d872678856 100644 --- a/src/soc/amd/common/psp_verstage/vboot_crypto.c +++ b/src/soc/amd/common/psp_verstage/vboot_crypto.c @@ -50,7 +50,7 @@ vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) sha_op.Data = (uint8_t *) buf; if (!sha_op_size_remaining) { - printk(BIOS_ERR, "ERROR: got more data than expected.\n"); + printk(BIOS_ERR, "got more data than expected.\n"); return VB2_ERROR_UNKNOWN; } @@ -65,7 +65,7 @@ vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) retval = svc_crypto_sha(&sha_op, SHA_GENERIC); if (retval) { - printk(BIOS_ERR, "ERROR: HW crypto failed - errorcode: %#x\n", + printk(BIOS_ERR, "HW crypto failed - errorcode: %#x\n", retval); return VB2_ERROR_UNKNOWN; } @@ -84,12 +84,12 @@ vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) { if (sha_op.Eom == 0) { - printk(BIOS_ERR, "ERROR: Got less data than expected.\n"); + printk(BIOS_ERR, "Got less data than expected.\n"); return VB2_ERROR_UNKNOWN; } if (digest_size != sha_op.DigestLen) { - printk(BIOS_ERR, "ERROR: Digest size does not match expected length.\n"); + printk(BIOS_ERR, "Digest size does not match expected length.\n"); return VB2_ERROR_UNKNOWN; } @@ -134,7 +134,7 @@ vb2_error_t vb2ex_hwcrypto_modexp(const struct vb2_public_key *key, retval = svc_modexp(&mod_exp_param); if (retval) { - printk(BIOS_ERR, "ERROR: HW crypto failed - errorcode: %#x\n", + printk(BIOS_ERR, "HW crypto failed - errorcode: %#x\n", retval); return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 06ac45ba5c..e3705d1d6a 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -12,7 +13,7 @@ static int transfer_buffer_valid(const struct transfer_info_struct *ptr) { - if (ptr->magic_val == TRANSFER_MAGIC_VAL) + if (ptr->magic_val == TRANSFER_MAGIC_VAL && ptr->struct_bytes == sizeof(*ptr)) return 1; else return 0; @@ -34,7 +35,7 @@ void verify_psp_transfer_buf(void) CMOS_RECOVERY_MAGIC_VAL) die("Error: Reboot into recovery was unsuccessful. Halting."); - printk(BIOS_ERR, "ERROR: VBOOT workbuf not valid.\n"); + printk(BIOS_ERR, "VBOOT workbuf not valid.\n"); printk(BIOS_DEBUG, "Signature: %#08x\n", *(uint32_t *)_vboot2_work); cmos_init(0); cmos_write(CMOS_RECOVERY_MAGIC_VAL, CMOS_RECOVERY_BYTE); @@ -61,6 +62,31 @@ void show_psp_transfer_info(void) } } +static void setup_cbmem_console(const struct transfer_info_struct *info) +{ + + void *cbmemc; + size_t cbmemc_size; + + if (info->console_offset < sizeof(*info)) + return; + + if (info->timestamp_offset <= info->console_offset) + return; + + cbmemc_size = info->timestamp_offset - info->console_offset; + + if (info->console_offset + cbmemc_size > info->buffer_size) + return; + + cbmemc = (void *)((uintptr_t)info + info->console_offset); + + /* We need to manually initialize cbmemc so we can fill the new buffer. cbmemc_init() + * will also be called later in console_hw_init(), but it will be a no-op. */ + cbmemc_init(); + cbmemc_copy_in(cbmemc, cbmemc_size); +} + void boot_with_psp_timestamp(uint64_t base_timestamp) { const struct transfer_info_struct *info = (const struct transfer_info_struct *) @@ -69,6 +95,8 @@ void boot_with_psp_timestamp(uint64_t base_timestamp) if (!transfer_buffer_valid(info) || info->timestamp == 0) return; + setup_cbmem_console(info); + /* * info->timestamp is PSP's timestamp (in microseconds) * when x86 processor is released. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5d1c0d4904..84af18c23d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -9,24 +9,32 @@ if SOC_AMD_PICASSO config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_SOC_NVS + select ADD_FSP_BINARIES if USE_AMD_BLOBS select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_X86 - select RESET_VECTOR_IN_RAM - select X86_AMD_FIXED_MTRRS - select X86_AMD_INIT_SIPI - select ACPI_SOC_NVS - select ADD_FSP_BINARIES if USE_AMD_BLOBS + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK select DRIVERS_I2C_DESIGNWARE select DRIVERS_USB_PCI_XHCI + select FSP_COMPRESS_FSP_M_LZMA + select FSP_COMPRESS_FSP_S_LZMA select GENERIC_GPIO_LIB - select IDT_IN_EVERY_STAGE select HAVE_ACPI_TABLES + select HAVE_CF9_RESET select HAVE_EM100_SUPPORT + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_0 + select PROVIDES_ROM_SHARING + select RESET_VECTOR_IN_RAM + select RTC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP + select SOC_AMD_COMMON_BLOCK_ACP_GEN1 select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB @@ -40,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX @@ -59,17 +68,13 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES - select PROVIDES_ROM_SHARING - select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select PARALLEL_MP_AP_WORK - select HAVE_SMI_HANDLER select SSE2 - select RTC - select PLATFORM_USES_FSP2_0 - select FSP_COMPRESS_FSP_M_LZMA - select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING - select HAVE_CF9_RESET + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select X86_AMD_FIXED_MTRRS + select X86_INIT_NEED_1_SIPI config ARCH_ALL_STAGES_X86 default n @@ -137,6 +142,12 @@ config PSP_SHAREDMEM_SIZE started. The workbuf's base depends on the address of the reset vector. +config PRE_X86_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Size of the CBMEM console used in PSP verstage. + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -200,14 +211,10 @@ config RAMBASE hex default 0x10000000 -config CPU_ADDR_BITS - int - default 48 - -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VERSTAGE_ADDR @@ -513,16 +520,6 @@ config RWB_REGION_ONLY Add a space-delimited list of filenames that should only be in the RW-B section. -config PICASSO_FW_A_POSITION - hex - help - Location of the AMD firmware in the RW_A region - -config PICASSO_FW_B_POSITION - hex - help - Location of the AMD firmware in the RW_B region - endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 45e9c80330..8eef1538cc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -54,7 +54,6 @@ endif smm-y += gpio.c smm-y += smu.c -CPPFLAGS_common += -I$(src)/soc/amd/picasso CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso @@ -78,6 +77,18 @@ PICASSO_FWM_POSITION=$(call int-add, \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# Building the cbfs image will fail if the offset isn't large enough +AMD_FW_AB_POSITION := 0x40 + +PICASSO_FW_A_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ + $(AMD_FW_AB_POSITION)) + +PICASSO_FW_B_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ + $(AMD_FW_AB_POSITION)) + # # PSP Directory Table items # @@ -249,7 +260,7 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_A_POSITION)) \ + --location $(shell printf "%#x" $(PICASSO_FW_A_POSITION)) \ --anywhere \ --output $@ @@ -260,7 +271,7 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ - --location $(shell printf "%#x" $(CONFIG_PICASSO_FW_B_POSITION)) \ + --location $(shell printf "%#x" $(PICASSO_FW_B_POSITION)) \ --anywhere \ --output $@ @@ -272,17 +283,15 @@ apu/amdfw-type := raw ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw endif -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) - cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c0808d9f2e..cd8a0a0968 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -4,7 +4,6 @@ * ACPI - create the Fixed ACPI Description Tables (FADT) */ -#include #include #include #include @@ -92,7 +91,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0x0d; + fadt->day_alrm = RTC_DATE_ALARM; fadt->mon_alrm = 0; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ @@ -106,8 +105,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_REMOTE_POWER_ON; fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; @@ -317,9 +315,7 @@ void generate_cpu_entries(const struct device *device) }, }; - threads_per_core = ((cpuid_ebx(CPUID_EBX_CORE_ID) & CPUID_EBX_THREADS_MASK) - >> CPUID_EBX_THREADS_SHIFT) - + 1; + threads_per_core = get_threads_per_core(); pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); logical_cores = get_cpu_count(); diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 292cdd8318..df21e9d9a5 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -73,14 +73,14 @@ Method(_CRS, 0) { /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = CONFIG_MMCONF_BASE_ADDRESS + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 CreateWordField(CRES, ^PSB0._MAX, BMAX) CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_MMCONF_BUS_NUMBER + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 782600754a..db95b92f5a 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -19,7 +18,6 @@ #include #include #include -#include #include static unsigned long gen_crat_hsa_entry(struct acpi_crat_header *crat, unsigned long current) @@ -82,7 +80,7 @@ static unsigned long gen_crat_memory_entries(struct acpi_crat_header *crat, if (memory_base == 0) { current = create_crat_memory_entry(0, 0ull, 0xa0000ull, current); - memory_base = (1 * 1024 * 1024); + memory_base = 1 * MiB; memory_length = memory_base; new_entries++; } diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index 7d1f01cec8..dd4ef3c12a 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -1,96 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include -#include #include #include -#include -#include -#include -#include #include -#include #include #include -#include #include -/* PSP performs the memory training and setting up DRAM map prior to x86 cores - being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, - route lower memory addresses covered by fixed MTRRs to DRAM except for - 0xa0000-0xc0000 . */ -static void set_caching(void) -{ - msr_t top_mem; - msr_t sys_cfg; - msr_t mtrr_def_type; - msr_t fixed_mtrr_ram; - msr_t fixed_mtrr_mmio; - struct var_mtrr_context mtrr_ctx; - - var_mtrr_context_init(&mtrr_ctx, NULL); - top_mem = rdmsr(TOP_MEM); - /* Enable RdDram and WrDram attributes in fixed MTRRs. */ - sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; - - /* Fixed MTRR constants. */ - fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | - ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); - fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = - ((MTRR_TYPE_UNCACHEABLE) << 0) | - ((MTRR_TYPE_UNCACHEABLE) << 8) | - ((MTRR_TYPE_UNCACHEABLE) << 16) | - ((MTRR_TYPE_UNCACHEABLE) << 24); - - /* Prep default MTRR type. */ - mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); - mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; - mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; - mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; - - disable_cache(); - - wrmsr(SYSCFG_MSR, sys_cfg); - - clear_all_var_mtrr(); - - var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); - var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ - wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); - wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); - wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); - - wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); - - /* Enable Fixed and Variable MTRRs. */ - sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; - sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; - /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once - MP init happens in coreboot proper it can be knocked down. */ - wrmsr(SYSCFG_MSR, sys_cfg); - - enable_cache(); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - set_caching(); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 4fcd3f71a3..72943cd616 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/amd/picasso/config.c b/src/soc/amd/picasso/config.c index 577d7b29a8..f1384bb5b0 100644 --- a/src/soc/amd/picasso/config.c +++ b/src/soc/amd/picasso/config.c @@ -4,7 +4,7 @@ #include #include "chip.h" -const struct soc_amd_common_config *soc_get_common_config() +const struct soc_amd_common_config *soc_get_common_config(void) { /* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */ const struct soc_amd_picasso_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 9822326afe..de6e9c035b 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -55,9 +54,9 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); @@ -66,7 +65,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void model_17_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index b5949f028c..75d72e9fe8 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -44,7 +45,7 @@ void data_fabric_set_mmio_np(void) for (i = 0; i < NUM_NB_MMIO_REGS; i++) { /* Adjust all registers that overlap */ ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (MMIO_WE | MMIO_RE))) + if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) continue; /* not enabled */ base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); @@ -66,8 +67,7 @@ void data_fabric_set_mmio_np(void) /* Although a pair could be freed later, this condition is * very unusual and deserves analysis. Flag an error and * leave the topmost part unconfigured. */ - printk(BIOS_ERR, - "Error: Not enough NB MMIO routing registers\n"); + printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); continue; } data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); @@ -85,15 +85,15 @@ void data_fabric_set_mmio_np(void) reg = data_fabric_find_unused_mmio_reg(); if (reg < 0) { - printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + printk(BIOS_ERR, "cannot configure region as NP\n"); return; } data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << MMIO_DST_FABRIC_ID_SHIFT) | MMIO_NP | MMIO_WE - | MMIO_RE); + (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP + | DF_MMIO_WE | DF_MMIO_RE); data_fabric_print_mmio_conf(); } diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 2a1b5c971a..f7435aae3d 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 44acc817ef..24565a75fe 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -225,8 +224,6 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - acpi_clear_pm_gpe_status(); - al2ahb_clock_gate(); gpp_clk_setup(); diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index 6a5c07425f..6483394294 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -19,7 +19,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); - mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index 57e51d5c02..af7de37057 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -9,7 +9,6 @@ #include #include #include "chip.h" -#include static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index 516af7bf3a..c9db4b6d59 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -29,11 +29,11 @@ PSP_MP2FW2_FILE MP2I2CFWPCO.sbin PSP_MP2CFG_FILE MP2FWConfig.sbin PSP_DRIVERS_FILE drv_sys_prod_RV.sbin # BDT -PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin -PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin -PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin -PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin -PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin -PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE_SUB0_INS4 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE_SUB1_INS1 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE_SUB1_INS4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE_SUB0_INS4 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE_SUB1_INS1 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE_SUB1_INS4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 18660f640b..afbc8bd379 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -30,7 +30,7 @@ static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } @@ -38,29 +38,15 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) } #endif -__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } - void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) { - uint32_t pad_ctrl; - int misc_reg; + /* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this + configurable. */ + const struct i2c_pad_control ctrl = { + .rx_level = I2C_PAD_RX_3_3V, + }; - misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * bus; - pad_ctrl = misc_read32(misc_reg); - - pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; - pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; - - pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; - pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; - - pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; - pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD ? - I2C_PAD_CTRL_FALLSLEW_STD : I2C_PAD_CTRL_FALLSLEW_LOW; - pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; - - mainboard_i2c_override(bus, &pad_ctrl); - misc_write32(misc_reg, pad_ctrl); + fch_i2c_pad_init(bus, cfg->speed, &ctrl); } const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 804b27cd0c..20876906c5 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -8,6 +8,9 @@ #include #include +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0d + uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 3a1f2c714a..5533433126 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -6,6 +6,10 @@ #include /* D18F0 - Fabric Configuration registers */ + +/* SoC-specific bits in D18F0_MMIO_CTRL0 */ +#define DF_MMIO_NP BIT(12) + #define IOMS0_FABRIC_ID 9 #define NUM_NB_MMIO_REGS 8 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1577568c90..853008bcbc 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -10,11 +10,6 @@ #define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - /* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 #define AL2AHB_CONTROL_CLK_OFFSET 0x10 @@ -61,10 +56,10 @@ #define APU_EMMC_BASE 0xfedd5000 #define APU_EMMC_CONFIG_BASE 0xfedd5800 -#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) - #endif /* ENV_X86 */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define ACPI_IO_BASE 0x400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index e86809eb2a..dba3bea63e 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -6,8 +6,9 @@ #include #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -140,7 +141,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 2cc1c62bb3..b8dd67b5c7 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -92,32 +92,6 @@ #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) #define MISC_CLK_CNTL1 0x40 #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ -#define MISC_I2C0_PAD_CTRL 0xd8 -#define MISC_I2C1_PAD_CTRL 0xdc -#define MISC_I2C2_PAD_CTRL 0xe0 -#define MISC_I2C3_PAD_CTRL 0xe4 -#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) -#define I2C_PAD_CTRL_NG_NORMAL 0xc -#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) -#define I2C_PAD_CTRL_RX_SHIFT 4 -#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) -#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) -#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) -#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 -#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) -#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) -#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) -#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ -#define I2C_PAD_CTRL_CAP_DOWN BIT(12) -#define I2C_PAD_CTRL_CAP_UP BIT(13) -#define I2C_PAD_CTRL_RES_DOWN BIT(14) -#define I2C_PAD_CTRL_RES_UP BIT(15) -#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) -#define I2C_PAD_CTRL_SPARE0 BIT(17) -#define I2C_PAD_CTRL_SPARE1 BIT(18) #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ @@ -128,22 +102,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -typedef struct aoac_devs { - unsigned int :7; - unsigned int ic2e:1; /* 7: I2C2 */ - unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int ic4e:1; /* 9: I2C4 */ - unsigned int :1; - unsigned int ut0e:1; /* 11: UART0 */ - unsigned int ut1e:1; /* 12: UART1 */ - unsigned int :3; - unsigned int ut2e:1; /* 16: UART2 */ - unsigned int :9; - unsigned int ut3e:1; /* 26: UART3 */ - unsigned int espi:1; /* 27: ESPI */ - unsigned int :4; -} __packed aoac_devs_t; - void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); @@ -152,7 +110,4 @@ void fch_final(void *chip_info); void enable_aoac_devices(void); void wait_for_aoac_enabled(unsigned int dev); -/* Allow the board to change the default I2C pad configuration */ -void mainboard_i2c_override(int bus, uint32_t *pad_settings); - #endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 41296c9b0c..82d8efa818 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -5,6 +5,7 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index 9577a5b632..1cfcb0a558 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -14,11 +14,6 @@ uint32_t save_uapp_data(void *address, uint32_t size) return svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, address, size); } -uint32_t get_max_workbuf_size(uint32_t *size) -{ - return svc_get_max_workbuf_size(size); -} - uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) { return ef_table->bios1_entry; @@ -38,3 +33,9 @@ int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, } return 0; } + +void platform_report_mode(int developer_mode_enabled) +{ + /* Picasso PSP doesn't support this */ + (void)developer_mode_enabled; +} diff --git a/src/soc/amd/picasso/psp_verstage/uart.c b/src/soc/amd/picasso/psp_verstage/uart.c new file mode 100644 index 0000000000..1c89f10c99 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/uart.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +uintptr_t get_uart_base(unsigned int idx) +{ + /* Mapping the UART is not supported. */ + return 0; +} diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index eee203684b..4ea8bc22c7 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -139,7 +139,7 @@ static void read_resources(struct device *dev) mmconf_resource(dev, MMIO_CONF_BASE); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -161,7 +161,7 @@ static void read_resources(struct device *dev) else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index b13c6e0be7..08f805bf76 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -23,6 +23,7 @@ static void fch_apmc_smi_handler(void) switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: @@ -123,7 +124,7 @@ static void fch_slp_typ_handler(void) psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig new file mode 100644 index 0000000000..1be53b5314 --- /dev/null +++ b/src/soc/amd/sabrina/Kconfig @@ -0,0 +1,480 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Check if this is still correct + +config SOC_AMD_SABRINA + bool + help + AMD Sabrina support + +if SOC_AMD_SABRINA + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ACPI_SOC_NVS + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_X86 + select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK + select DRIVERS_USB_ACPI + select DRIVERS_I2C_DESIGNWARE + select DRIVERS_USB_PCI_XHCI + select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING + select FSP_COMPRESS_FSP_S_LZ4 + select GENERIC_GPIO_LIB + select HAVE_ACPI_TABLES + select HAVE_CF9_RESET + select HAVE_EM100_SUPPORT + select HAVE_FSP_GOP + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select PARALLEL_MP_AP_WORK + select PLATFORM_USES_FSP2_0 + select PROVIDES_ROM_SHARING + select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK + select RESET_VECTOR_IN_RAM + select RTC + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACP_GEN2 + select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_IOMMU + select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMU + select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct + select SSE2 + select UDK_2017_BINDING + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK + select X86_AMD_FIXED_MTRRS + select X86_INIT_NEED_1_SIPI + +config ARCH_ALL_STAGES_X86 + default n + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 5568 + +config CHIPSET_DEVICETREE + string + default "soc/amd/sabrina/chipset.cb" + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x2000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x2001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_SHAREDMEM_BASE + hex + default 0x2011000 if VBOOT + default 0x0 + help + This variable defines the base address in DRAM memory where PSP copies + the vboot workbuf. This is used in the linker script to have a static + allocation for the buffer as well as for adding relevant entries in + the BIOS directory table for the PSP. + +config PSP_SHAREDMEM_SIZE + hex + default 0x8000 if VBOOT + default 0x0 + help + Sets the maximum size for the PSP to pass the vboot workbuf and + any logs or timestamps back to coreboot. This will be copied + into main memory by the PSP and will be available when the x86 is + started. The workbuf's base depends on the address of the reset + vector. + +config PRE_X86_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Size of the CBMEM console used in PSP verstage. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config CBFS_MCACHE_SIZE + hex + default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config ROMSTAGE_ADDR + hex + default 0x2040000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for romstage in linker script. + +config FSP_M_ADDR + hex + default 0x20C0000 + help + Sets the address in DRAM where FSP-M should be loaded. cbfstool + performs relocation of FSP-M to this address. + +config FSP_M_SIZE + hex + default 0xC0000 + help + Sets the size of DRAM allocation for FSP-M in linker script. + +config FSP_TEMP_RAM_SIZE + hex + default 0x40000 + help + The amount of coreboot-allocated heap and stack usage by the FSP. + +config VERSTAGE_ADDR + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x2180000 + help + Sets the address in DRAM where verstage should be loaded if running + as a separate stage on x86. + +config VERSTAGE_SIZE + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x80000 + help + Sets the size of DRAM allocation for verstage in linker script if + running as a separate stage on x86. + +config ASYNC_FILE_LOADING + bool "Loads files from SPI asynchronously" + select COOP_MULTITASKING + select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select CBFS_PRELOAD + help + When enabled, the platform will use the LPC SPI DMA controller to + asynchronously load contents from the SPI ROM. This will improve + boot time because the CPUs can be performing useful work while the + SPI contents are being preloaded. + +config CBFS_CACHE_SIZE + hex + default 0x40000 if CBFS_PRELOAD + +config RAMBASE + hex + default 0x10000000 + +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + default "apu/amdfw" + +config ECAM_MMCONF_BASE_ADDRESS + default 0xF8000000 + +config ECAM_MMCONF_BUS_NUMBER + default 64 + +config MAX_CPUS + int + default 16 + help + Maximum number of threads the platform can have. + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedce000 if UART_FOR_CONSOLE = 2 + default 0xfedcf000 if UART_FOR_CONSOLE = 3 + default 0xfedd1000 if UART_FOR_CONSOLE = 4 + +config SMM_TSEG_SIZE + hex + default 0x800000 if HAVE_SMI_HANDLER + default 0x0 + +config SMM_RESERVED_SIZE + hex + default 0x180000 + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + +config ACPI_BERT + bool "Build ACPI BERT Table" + default y + depends on HAVE_ACPI_TABLES + help + Report Machine Check errors identified in POST to the OS in an + ACPI Boot Error Record Table. + +config ACPI_BERT_SIZE + hex + default 0x4000 if ACPI_BERT + default 0x0 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 150 + +config DISABLE_SPI_FLASH_ROM_SHARING + def_bool n + help + Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin + which indicates a board level ROM transaction request. This + removes arbitration with board and assumes the chipset controls + the SPI flash bus entirely. + +config DISABLE_KEYBOARD_RESET_PIN + bool + help + Instruct the SoC to not use the state of GPIO_129 as keyboard reset + signal. When this pin is used as GPIO and the keyboard reset + functionality isn't disabled, configuring it as an output and driving + it as 0 will cause a reset. + +config ACPI_SSDT_PSD_INDEPENDENT + bool "Allow core p-state independent transitions" + default y + help + AMD recommends the ACPI _PSD object to be configured to cause + cores to transition between p-states independently. A vendor may + choose to generate _PSD object to allow cores to transition together. + +menu "PSP Configuration Options" + +config AMD_FWM_POSITION_INDEX + int "Firmware Directory Table location (0 to 5)" + range 0 5 + default 0 if BOARD_ROMSIZE_KB_512 + default 1 if BOARD_ROMSIZE_KB_1024 + default 2 if BOARD_ROMSIZE_KB_2048 + default 3 if BOARD_ROMSIZE_KB_4096 + default 4 if BOARD_ROMSIZE_KB_8192 + default 5 if BOARD_ROMSIZE_KB_16384 + help + Typically this is calculated by the ROM size, but there may + be situations where you want to put the firmware directory + table in a different location. + 0: 512 KB - 0xFFFA0000 + 1: 1 MB - 0xFFF20000 + 2: 2 MB - 0xFFE20000 + 3: 4 MB - 0xFFC20000 + 4: 8 MB - 0xFF820000 + 5: 16 MB - 0xFF020000 + +comment "AMD Firmware Directory Table set to location for 512KB ROM" + depends on AMD_FWM_POSITION_INDEX = 0 +comment "AMD Firmware Directory Table set to location for 1MB ROM" + depends on AMD_FWM_POSITION_INDEX = 1 +comment "AMD Firmware Directory Table set to location for 2MB ROM" + depends on AMD_FWM_POSITION_INDEX = 2 +comment "AMD Firmware Directory Table set to location for 4MB ROM" + depends on AMD_FWM_POSITION_INDEX = 3 +comment "AMD Firmware Directory Table set to location for 8MB ROM" + depends on AMD_FWM_POSITION_INDEX = 4 +comment "AMD Firmware Directory Table set to location for 16MB ROM" + depends on AMD_FWM_POSITION_INDEX = 5 + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/sabrina/fw.cfg" + +config PSP_DISABLE_POSTCODES + bool "Disable PSP post codes" + help + Disables the output of port80 post codes from PSP. + +config PSP_POSTCODES_ON_ESPI + bool "Use eSPI bus for PSP post codes" + default y + depends on !PSP_DISABLE_POSTCODES + help + Select to send PSP port80 post codes on eSPI bus. + If not selected, PSP port80 codes will be sent on LPC bus. + +config PSP_LOAD_MP2_FW + bool + default n + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'n' + +config PSP_UNLOCK_SECURE_DEBUG + bool "Unlock secure debug" + default y + help + Select this item to enable secure debug options in PSP. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + serial number. This feature requires a signed whitelist image + and bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file path" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" + +config PSP_SOFTFUSE_BITS + string "PSP Soft Fuse bits to enable" + default "28 6" + help + Space separated list of Soft Fuse bits to enable. + Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) + Bit 7: Disable PSP postcodes on Renoir and newer chips only + (Set by PSP_DISABLE_PORT80) + Bit 15: PSP post code destination: 0=LPC 1=eSPI + (Set by PSP_INITIALIZE_ESPI) + Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) + + See #55758 (NDA) for additional bit definitions. + +config PSP_VERSTAGE_FILE + string "Specify the PSP_verstage file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "\$(obj)/psp_verstage.bin" + help + Add psp_verstage file to the build & PSP Directory Table + +config PSP_VERSTAGE_SIGNING_TOKEN + string "Specify the PSP_verstage Signature Token file path" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default "" + help + Add psp_verstage signature token to the build & PSP Directory Table + +endmenu + +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +config VBOOT_STARTS_BEFORE_BOOTBLOCK + def_bool n + depends on VBOOT + select ARCH_VERSTAGE_ARMV7 + help + Runs verstage on the PSP. Only available on + certain Chrome OS branded parts from AMD. + +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x9000 + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Because the bulk of the time in psp_verstage to hash the RO cbfs is + spent in the overhead of doing svc calls, increasing the hash block + size significantly cuts the verstage hashing time as seen below. + + 4k takes 180ms + 16k takes 44ms + 32k takes 33.7ms + 36k takes 32.5ms + There's actually still room for an even bigger stack, but we've + reached a point of diminishing returns. + +config CMOS_RECOVERY_BYTE + hex + default 0x51 + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + help + If the workbuf is not passed from the PSP to coreboot, set the + recovery flag and reboot. The PSP will read this byte, mark the + recovery request in VBNV, and reset the system into recovery mode. + + This is the byte before the default first byte used by VBNV + (0x26 + 0x0E - 1) + +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +endif # SOC_AMD_SABRINA diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc new file mode 100644 index 0000000000..74124d25a7 --- /dev/null +++ b/src/soc/amd/sabrina/Makefile.inc @@ -0,0 +1,295 @@ +# SPDX-License-Identifier: BSD-3-Clause + +# TODO: Check if this is still correct + +ifeq ($(CONFIG_SOC_AMD_SABRINA),y) + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + +# Beware that all-y also adds the compilation unit to verstage on PSP +all-y += config.c +all-y += aoac.c + +bootblock-y += bootblock.c +bootblock-y += early_fch.c +bootblock-y += gpio.c +bootblock-y += i2c.c +bootblock-y += reset.c +bootblock-y += uart.c + +verstage-y += i2c.c +verstage_x86-y += gpio.c +verstage_x86-y += reset.c +verstage_x86-y += uart.c + +romstage-y += fsp_m_params.c +romstage-y += gpio.c +romstage-y += i2c.c +romstage-y += reset.c +romstage-y += romstage.c +romstage-y += uart.c + +ramstage-y += acpi.c +ramstage-y += agesa_acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += data_fabric.c +ramstage-y += fch.c +ramstage-y += fsp_s_params.c +ramstage-y += gpio.c +ramstage-y += i2c.c +ramstage-y += mca.c +ramstage-y += preload.c +ramstage-y += reset.c +ramstage-y += root_complex.c +ramstage-y += uart.c +ramstage-y += xhci.c + +smm-y += gpio.c +smm-y += smihandler.c +smm-y += smu.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + +CPPFLAGS_common += -I$(src)/soc/amd/sabrina/include +CPPFLAGS_common += -I$(src)/soc/amd/sabrina/acpi +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/sabrina + +MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + +# ROMSIG Normally At ROMBASE + 0x20000 +# Overridden by CONFIG_AMD_FWM_POSITION_INDEX +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA | | | | +# +-----------+---------------+----------------+------------+ +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + +$(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ + $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) + +SABRINA_FWM_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(call int-shift-left, \ + 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + +# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes +# Building the cbfs image will fail if the offset isn't large enough +AMD_FW_AB_POSITION := 0x40 + +SABRINA_FW_A_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ + $(AMD_FW_AB_POSITION)) + +SABRINA_FW_B_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ + $(AMD_FW_AB_POSITION)) +# +# PSP Directory Table items +# +# Certain ordering requirements apply, however these are ensured by amdfwtool. +# For more information see "AMD Platform Security Processor BIOS Architecture +# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). +# + +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) +PSP_SOFTFUSE_BITS += 15 +endif + +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 58 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') + +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ + $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ + $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + $(OPT_PSP_LOAD_MP2_FW) \ + --use-pspsecureos \ + --load-s0i3 \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + --soc-name "Cezanne" \ + --flashsize $(CONFIG_ROM_SIZE) + +$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ + $$(PSP_APCB_FILES) \ + $(DEP_FILES) \ + $(AMDFWTOOL) \ + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file + $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(SABRINA_FWM_POSITION)) \ + --multilevel \ + --output $@ + +$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(SABRINA_FW_A_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(SABRINA_FW_B_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + + +cbfs-files-y += apu/amdfw +apu/amdfw-file := $(obj)/amdfw.rom +apu/amdfw-position := $(SABRINA_FWM_POSITION) +apu/amdfw-type := raw + +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(AMD_FW_AB_POSITION) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(AMD_FW_AB_POSITION) +apu/amdfw_b-type := raw +endif + +cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) + +endif # ($(CONFIG_SOC_AMD_SABRINA),y) diff --git a/src/soc/amd/sabrina/acpi.c b/src/soc/amd/sabrina/acpi.c new file mode 100644 index 0000000000..b10773b7d5 --- /dev/null +++ b/src/soc/amd/sabrina/acpi.c @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +/* ACPI - create the Fixed ACPI Description Tables (FADT) */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + + /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, 0, 2, + MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); + /* SCI IRQ type override */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, + MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, + MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + current = acpi_fill_madt_irqoverride(current); + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, + ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + 1 /* 1: LINT1 connect to NMI */); + + return current; +} + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const struct soc_amd_sabrina_config *cfg = config_of_soc(); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); + + fadt->sci_int = ACPI_SCI_IRQ; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } + + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->duty_offset = 0; /* Not supported */ + fadt->duty_width = 0; /* Not supported */ + fadt->day_alrm = RTC_DATE_ALARM; + fadt->mon_alrm = 0; + fadt->century = RTC_ALT_CENTURY; + fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + if (cfg->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; +} + +static uint32_t get_pstate_core_freq(msr_t pstate_def) +{ + uint32_t core_freq, core_freq_mul, core_freq_div; + bool valid_freq_divisor; + + /* Core frequency multiplier */ + core_freq_mul = pstate_def.lo & PSTATE_DEF_LO_FREQ_MUL_MASK; + + /* Core frequency divisor ID */ + core_freq_div = + (pstate_def.lo & PSTATE_DEF_LO_FREQ_DIV_MASK) >> PSTATE_DEF_LO_FREQ_DIV_SHIFT; + + if (core_freq_div == 0) { + return 0; + } else if ((core_freq_div >= PSTATE_DEF_LO_FREQ_DIV_MIN) + && (core_freq_div <= PSTATE_DEF_LO_EIGHTH_STEP_MAX)) { + /* Allow 1/8 integer steps for this range */ + valid_freq_divisor = 1; + } else if ((core_freq_div > PSTATE_DEF_LO_EIGHTH_STEP_MAX) + && (core_freq_div <= PSTATE_DEF_LO_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { + /* Only allow 1/4 integer steps for this range */ + valid_freq_divisor = 1; + } else { + valid_freq_divisor = 0; + } + + if (valid_freq_divisor) { + /* 25 * core_freq_mul / (core_freq_div / 8) */ + core_freq = + ((PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); + } else { + printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", + core_freq_div); + core_freq = (PSTATE_DEF_LO_CORE_FREQ_BASE * core_freq_mul); + } + return core_freq; +} + +static uint32_t get_pstate_core_power(msr_t pstate_def) +{ + uint32_t voltage_in_uvolts, core_vid, current_value_amps, current_divisor, power_in_mw; + + /* Core voltage ID */ + core_vid = + (pstate_def.lo & PSTATE_DEF_LO_CORE_VID_MASK) >> PSTATE_DEF_LO_CORE_VID_SHIFT; + + /* Current value in amps */ + current_value_amps = + (pstate_def.lo & PSTATE_DEF_LO_CUR_VAL_MASK) >> PSTATE_DEF_LO_CUR_VAL_SHIFT; + + /* Current divisor */ + current_divisor = + (pstate_def.lo & PSTATE_DEF_LO_CUR_DIV_MASK) >> PSTATE_DEF_LO_CUR_DIV_SHIFT; + + /* Voltage */ + if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { + /* Voltage off for VID codes 0xF8 to 0xFF */ + voltage_in_uvolts = 0; + } else { + voltage_in_uvolts = + SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid); + } + + /* Power in mW */ + power_in_mw = (voltage_in_uvolts) / 1000 * current_value_amps; + + switch (current_divisor) { + case 0: + break; + case 1: + power_in_mw = power_in_mw / 10L; + break; + case 2: + power_in_mw = power_in_mw / 100L; + break; + case 3: + /* current_divisor is set to an undefined value.*/ + printk(BIOS_WARNING, "Undefined current_divisor set for enabled P-state .\n"); + power_in_mw = 0; + break; + } + + return power_in_mw; +} + +/* + * Populate structure describing enabled p-states and return count of enabled p-states. + */ +static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) +{ + msr_t pstate_def; + size_t pstate_count, pstate; + uint32_t pstate_enable, max_pstate; + + pstate_count = 0; + max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT; + + for (pstate = 0; pstate <= max_pstate; pstate++) { + pstate_def = rdmsr(PSTATE_0_MSR + pstate); + + pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK) + >> PSTATE_DEF_HI_ENABLE_SHIFT; + if (!pstate_enable) + continue; + + pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def); + pstate_values[pstate_count].power = get_pstate_core_power(pstate_def); + pstate_values[pstate_count].transition_latency = 0; + pstate_values[pstate_count].bus_master_latency = 0; + pstate_values[pstate_count].control_value = pstate; + pstate_values[pstate_count].status_value = pstate; + + pstate_xpss_values[pstate_count].core_freq = + (uint64_t)pstate_values[pstate_count].core_freq; + pstate_xpss_values[pstate_count].power = + (uint64_t)pstate_values[pstate_count].power; + pstate_xpss_values[pstate_count].transition_latency = 0; + pstate_xpss_values[pstate_count].bus_master_latency = 0; + pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate; + pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate; + pstate_count++; + } + + return pstate_count; +} + +void generate_cpu_entries(const struct device *device) +{ + int logical_cores; + size_t pstate_count, cpu, proc_blk_len; + struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; + struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; + uint32_t threads_per_core, proc_blk_addr; + uint32_t cstate_base_address = + rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK; + + const acpi_addr_t perf_ctrl = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_CTL_REG, + }; + const acpi_addr_t perf_sts = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_STS_REG, + }; + + const acpi_cstate_t cstate_info[] = { + [0] = { + .ctype = 1, + .latency = 1, + .power = 0, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 2, + .bit_offset = 2, + .addrl = 0, + .addrh = 0, + }, + }, + [1] = { + .ctype = 2, + .latency = 0x12, + .power = 0, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .bit_offset = 0, + .addrl = cstate_base_address + 1, + .addrh = 0, + .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, + }, + }, + [2] = { + .ctype = 3, + .latency = 350, + .power = 0, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .bit_offset = 0, + .addrl = cstate_base_address + 2, + .addrh = 0, + .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, + }, + }, + }; + + threads_per_core = get_threads_per_core(); + pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); + logical_cores = get_cpu_count(); + + for (cpu = 0; cpu < logical_cores; cpu++) { + + if (cpu == 0) { + /* BSP values for \_SB.Pxxx */ + proc_blk_len = 6; + proc_blk_addr = ACPI_GPE0_BLK; + } else { + /* AP values for \_SB.Pxxx */ + proc_blk_addr = 0; + proc_blk_len = 0; + } + + acpigen_write_processor(cpu, proc_blk_addr, proc_blk_len); + + acpigen_write_pct_package(&perf_ctrl, &perf_sts); + + acpigen_write_pss_object(pstate_values, pstate_count); + + acpigen_write_xpss_object(pstate_xpss_values, pstate_count); + + if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) + acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, + HW_ALL); + else + acpigen_write_PSD_package(0, logical_cores, SW_ALL); + + acpigen_write_PPC(0); + + acpigen_write_CST_package(cstate_info, ARRAY_SIZE(cstate_info)); + + acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, + CSD_HW_ALL, 0); + + acpigen_pop_len(); + } + + acpigen_write_processor_package("PPKG", 0, logical_cores); +} diff --git a/src/soc/amd/sabrina/acpi/globalnvs.asl b/src/soc/amd/sabrina/acpi/globalnvs.asl new file mode 100644 index 0000000000..19d58d5ec5 --- /dev/null +++ b/src/soc/amd/sabrina/acpi/globalnvs.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Check if this is still correct */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/amd/sabrina/include/soc/nvs.h !!! + */ + +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + , 8, // 0x00 - Processor Count + LIDS, 8, // 0x01 - LID State + , 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold +} diff --git a/src/soc/amd/sabrina/acpi/mmio.asl b/src/soc/amd/sabrina/acpi/mmio.asl new file mode 100644 index 0000000000..48ae1d2773 --- /dev/null +++ b/src/soc/amd/sabrina/acpi/mmio.asl @@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Shared, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IGPI + } Else { + IRQN = PGPI + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMDI0020") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA0 + } Else { + IRQN = PUA0 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0) +} + +Device (FUR1) { + Name (_HID, "AMDI0020") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA1 + } Else { + IRQN = PUA1 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0) +} + +Device (FUR2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA2 + } Else { + IRQN = PUA2 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0) +} + +Device (FUR3) { + Name (_HID, "AMDI0020") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA3 + } Else { + IRQN = PUA3 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART3, 0) +} + +Device (FUR4) { + Name (_HID, "AMDI0020") + Name (_UID, 0x4) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART4_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = IUA4 + } Else { + IRQN = PUA4 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART4_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + AOAC_DEVICE(FCH_AOAC_DEV_UART4, 0) +} + +Device (I2C0) { + Name (_HID, "AMDI0010") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0) +} + +Device (I2C1) { + Name (_HID, "AMDI0010") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0) +} + +Device (I2C2) { + Name (_HID, "AMDI0010") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0) +} + +Device (I2C3) +{ + Name (_HID, "AMDI0010") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0) +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () { "is-rv", 1 }, + }, + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/soc/amd/sabrina/acpi/pci0.asl b/src/soc/amd/sabrina/acpi/pci0.asl new file mode 100644 index 0000000000..e729ba38ff --- /dev/null +++ b/src/soc/amd/sabrina/acpi/pci0.asl @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +Device(PCI0) { + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + External(TOM1, IntObj) /* Generated by root_complex.c */ + + Method(_BBN, 0, NotSerialized) { + Return(Zero) /* Bus number = 0 */ + } + + Method(_STA, 0, NotSerialized) { + Return(0x0B) /* Status is visible */ + } + + /* Operating System Capabilities Method */ + Method(_OSC, 4) { + CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ + + /* Check for proper PCI/PCIe UUID */ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { + /* Let OS control everything */ + Return (Arg3) + } Else { + CDW1 |= 4 /* Unrecognized UUID */ + Return (Arg3) + } + } + Name(CRES, ResourceTemplate() { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00ff, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + + IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0cf7, /* range maximum */ + 0x0000, /* translation */ + 0x0cf8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0d00, /* range minimum */ + 0xffff, /* range maximum */ + 0x0000, /* translation */ + 0xf300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + + Method(_CRS, 0) { + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ + MM1B = TOM1 + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS + Local0 -= TOM1 + MM1L = Local0 + + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* 0:14.3 - LPC */ + #include + +} /* End PCI0 scope */ diff --git a/src/soc/amd/sabrina/acpi/pci_int_defs.asl b/src/soc/amd/sabrina/acpi/pci_int_defs.asl new file mode 100644 index 0000000000..fa5c88b0d6 --- /dev/null +++ b/src/soc/amd/sabrina/acpi/pci_int_defs.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} +/* + * All PIC indexes are prefixed with P. + * All IO-APIC indexes are prefixed with I. + */ +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x43), + PMMC, 0x00000008, /* Index 0x43: eMMC */ + + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PUA4, 0x00000008, /* Index 0x77: UART4 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xC3), + IMMC, 0x00000008, /* Index 0xC3: eMMC */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + IUA4, 0x00000008, /* Index 0xF7: UART4 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/sabrina/acpi/rtc_workaround.asl b/src/soc/amd/sabrina/acpi/rtc_workaround.asl new file mode 100644 index 0000000000..8bbca4e3f1 --- /dev/null +++ b/src/soc/amd/sabrina/acpi/rtc_workaround.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +/* + * Workaround for RTC on Cezanne. + * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839 + */ + +Scope (\_SB.PEP) { + Name (_PRW, Package () { + Package() {\_SB.GPIO, 0}, + 0x03 + }) +} + +Scope (\_SB.GPIO) { + Name (_AEI, ResourceTemplate () { + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,) + { + 44 /* int_shdwsysalarmfire */ + } + }) + + Method (_E2C, 0, Serialized) { + Notify (\_SB_.PEP, 0x02) + } +} diff --git a/src/soc/amd/sabrina/acpi/soc.asl b/src/soc/amd/sabrina/acpi/soc.asl new file mode 100644 index 0000000000..f5a41a17cf --- /dev/null +++ b/src/soc/amd/sabrina/acpi/soc.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include "globalnvs.asl" + +Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include + + #include + + #include + + #include "pci_int_defs.asl" + + #include + + #include "mmio.asl" + + #include "pci0.asl" +} /* End \_SB scope */ + +#include + +#include + +#include + +#include + +#include "rtc_workaround.asl" + +/* + * Platform Wake Notify + * + * This is called by soc/amd/common/acpi/platform.asl. + */ +Method (PNOT) +{ + /* Report AC/DC state to ALIB using WAL1() */ + \WAL1 () +} diff --git a/src/soc/amd/sabrina/agesa_acpi.c b/src/soc/amd/sabrina/agesa_acpi.c new file mode 100644 index 0000000000..f8193c7cc9 --- /dev/null +++ b/src/soc/amd/sabrina/agesa_acpi.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + acpi_ivrs_t *ivrs; + + /* add ALIB SSDT from HOB */ + current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + + /* IVRS */ + current = ALIGN(current, 8); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); + + return current; +} diff --git a/src/soc/amd/sabrina/aoac.c b/src/soc/amd/sabrina/aoac.c new file mode 100644 index 0000000000..ab52544189 --- /dev/null +++ b/src/soc/amd/sabrina/aoac.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ + : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \ + : CONFIG_UART_FOR_CONSOLE == 4 ? FCH_AOAC_DEV_UART4 \ + : -1) +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. The console UART is handled separately from this table. + * + * TODO: Find out which I2C controllers we really need to enable here. + */ +const static unsigned int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_ESPI, +}; + +void wait_for_aoac_enabled(unsigned int dev) +{ + while (!is_aoac_device_enabled(dev)) + udelay(100); +} + +void enable_aoac_devices(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); + + /* Wait for AOAC devices to indicate power and clock OK */ + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + wait_for_aoac_enabled(aoac_devs[i]); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} diff --git a/src/soc/amd/sabrina/bootblock.c b/src/soc/amd/sabrina/bootblock.c new file mode 100644 index 0000000000..bbf56d360a --- /dev/null +++ b/src/soc/amd/sabrina/bootblock.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + early_cache_setup(); + write_resume_eip(); + enable_pci_mmconf(); + + /* + * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz + * to get micro-seconds granularity. + */ + base_timestamp /= tsc_freq_mhz(); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + boot_with_psp_timestamp(base_timestamp); + + /* + * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or + * previous step did nothing, proceed with normal bootblock main. + */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + fch_pre_init(); +} + +void bootblock_soc_init(void) +{ + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_psp_transfer_buf(); + show_psp_transfer_info(); + } + + fch_early_init(); +} diff --git a/src/soc/amd/sabrina/chip.c b/src/soc/amd/sabrina/chip.c new file mode 100644 index 0000000000..c00f91b55d --- /dev/null +++ b/src/soc/amd/sabrina/chip.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* Supplied by i2c.c */ +extern struct device_operations soc_amd_i2c_mmio_ops; +/* Supplied by uart.c */ +extern struct device_operations sabrina_uart_mmio_ops; + +struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = mp_cpu_bus_init, + .acpi_fill_ssdt = generate_cpu_entries, +}; + +static const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n", + PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); + return NULL; +}; + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = soc_acpi_name, +}; + +static void set_mmio_dev_ops(struct device *dev) +{ + switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + case APU_I2C1_BASE: + case APU_I2C2_BASE: + case APU_I2C3_BASE: + dev->ops = &soc_amd_i2c_mmio_ops; + break; + case APU_UART0_BASE: + case APU_UART1_BASE: + case APU_UART2_BASE: + case APU_UART3_BASE: + case APU_UART4_BASE: + dev->ops = &sabrina_uart_mmio_ops; + break; + case APU_EMMC_BASE: + if (!dev->enabled) + power_off_aoac_device(FCH_AOAC_DEV_EMMC); + break; + } +} + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + switch (dev->path.type) { + case DEVICE_PATH_DOMAIN: + dev->ops = &pci_domain_ops; + break; + case DEVICE_PATH_CPU_CLUSTER: + dev->ops = &cpu_bus_ops; + break; + case DEVICE_PATH_MMIO: + set_mmio_dev_ops(dev); + break; + default: + break; + } +} + +static void soc_init(void *chip_info) +{ + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + + fsp_silicon_init(); + + data_fabric_set_mmio_np(); + + fch_init(chip_info); +} + +static void soc_final(void *chip_info) +{ + fch_final(chip_info); +} + +struct chip_operations soc_amd_sabrina_ops = { + CHIP_NAME("AMD Sabrina SoC") + .enable_dev = enable_dev, + .init = soc_init, + .final = soc_final +}; diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h new file mode 100644 index 0000000000..c272f9f2dc --- /dev/null +++ b/src/soc/amd/sabrina/chip.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef SABRINA_CHIP_H +#define SABRINA_CHIP_H + +#include +#include +#include +#include +#include +#include +#include +#include + +struct soc_amd_sabrina_config { + struct soc_amd_common_config common_config; + u8 i2c_scl_reset; + struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT]; + + /* Enable S0iX support */ + bool s0ix_enable; + + enum { + DOWNCORE_AUTO = 0, + DOWNCORE_1 = 1, /* Run with 1 physical core */ + DOWNCORE_2 = 3, /* Run with 2 physical cores */ + DOWNCORE_3 = 4, /* Run with 3 physical cores */ + DOWNCORE_4 = 6, /* Run with 4 physical cores */ + DOWNCORE_5 = 8, /* Run with 5 physical cores */ + DOWNCORE_6 = 9, /* Run with 6 physical cores */ + DOWNCORE_7 = 10, /* Run with 7 physical cores */ + } downcore_mode; + bool disable_smt; /* disable second thread on all physical cores */ + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; + + uint8_t stapm_boost; + uint32_t stapm_time_constant_s; + uint32_t apu_only_sppt_limit; + uint32_t sustained_power_limit_mW; + uint32_t fast_ppt_limit_mW; + uint32_t slow_ppt_limit_mW; + uint32_t slow_ppt_time_constant_s; + uint32_t thermctl_limit_degreeC; + + uint8_t smartshift_enable; + + uint8_t system_configuration; + + /* telemetry settings */ + uint32_t telemetry_vddcrvddfull_scale_current_mA; + uint32_t telemetry_vddcrvddoffset; + uint32_t telemetry_vddcrsocfull_scale_current_mA; + uint32_t telemetry_vddcrsocoffset; + + /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ + uint8_t dptc_enable; + + /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; + uint32_t thermctl_limit_tablet_mode_degreeC; + + /* The array index is the general purpose PCIe clock output number. Values in here + aren't the values written to the register to have the default to be always on. */ + enum { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ + } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_DISABLED = 0, + DXIO_PSPP_PERFORMANCE, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + + uint8_t usb_phy_custom; + struct usb_phy_config usb_phy; +}; + +#endif /* SABRINA_CHIP_H */ diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset.cb new file mode 100644 index 0000000000..c477a17d3d --- /dev/null +++ b/src/soc/amd/sabrina/chipset.cb @@ -0,0 +1,93 @@ +chip soc/amd/sabrina + device cpu_cluster 0 on + end + device domain 0 on + device pci 00.0 alias gnb on end + device pci 00.2 alias iommu off end + + device pci 01.0 on end # Dummy Host Bridge + + device pci 02.0 on end # Dummy Host Bridge, do not disable + device pci 02.1 alias gpp_bridge_0 off end + device pci 02.2 alias gpp_bridge_1 off end + device pci 02.3 alias gpp_bridge_2 off end + device pci 02.4 alias gpp_bridge_3 off end + device pci 02.5 alias gpp_bridge_4 off end + device pci 02.6 alias gpp_bridge_5 off end + + device pci 08.0 on end # Dummy Host Bridge, do not disable + device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 0.0 alias gfx off end # Internal GPU (GFX) + device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) + device pci 0.2 alias crypto off end # Crypto Coprocessor + device pci 0.3 alias xhci_0 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_0_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port0 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port0 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port1 off end + end + end + end + end + device pci 0.4 alias xhci_1 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port4 off end + end + end + end + end + device pci 0.5 alias acp off end # Audio Processor (ACP) + device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) + device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) + end + device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B + device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function + end + + device pci 14.0 alias smbus on end # primary FCH function + device pci 14.3 alias lpc_bridge on end + + device pci 18.0 alias data_fabric_0 on end + device pci 18.1 alias data_fabric_1 on end + device pci 18.2 alias data_fabric_2 on end + device pci 18.3 alias data_fabric_3 on end + device pci 18.4 alias data_fabric_4 on end + device pci 18.5 alias data_fabric_5 on end + device pci 18.6 alias data_fabric_6 on end + device pci 18.7 alias data_fabric_7 on end + end + + device mmio 0xfedc2000 alias i2c_0 off end + device mmio 0xfedc3000 alias i2c_1 off end + device mmio 0xfedc4000 alias i2c_2 off end + device mmio 0xfedc5000 alias i2c_3 off end + device mmio 0xfedc9000 alias uart_0 off end + device mmio 0xfedca000 alias uart_1 off end + device mmio 0xfedce000 alias uart_2 off end + device mmio 0xfedcf000 alias uart_3 off end + device mmio 0xfedd1000 alias uart_4 off end + device mmio 0xfedd5000 alias emmc off end +end diff --git a/src/soc/amd/sabrina/config.c b/src/soc/amd/sabrina/config.c new file mode 100644 index 0000000000..187f1664bc --- /dev/null +++ b/src/soc/amd/sabrina/config.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include "chip.h" + +const struct soc_amd_common_config *soc_get_common_config(void) +{ + /* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */ + const struct soc_amd_sabrina_config *cfg = config_of_soc(); + return &cfg->common_config; +} diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c new file mode 100644 index 0000000000..c355a704df --- /dev/null +++ b/src/soc/amd/sabrina/cpu.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " + "available cores, use the downcore_mode and disable_smt devicetree settings instead."); + +/* MP and SMM loading initialization */ + +/* + * Do essential initialization tasks before APs can be fired up - + * + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + x86_setup_mtrrs_with_detect_no_above_4gb(); + x86_mtrr_check(); +} + +static void post_mp_init(void) +{ + global_smi_enable(); + apm_control(APM_CNT_SMMINFO); +} + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = get_smm_info, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void mp_init_cpus(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); + + /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); +} + +static void zen_2_3_init(struct device *dev) +{ + check_mca(); + set_cstate_io_addr(); + + amd_update_microcode_from_cbfs(); +} + +static struct device_operations cpu_dev_ops = { + .init = zen_2_3_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, SABRINA_A0_CPUID}, + { 0, 0 }, +}; + +static const struct cpu_driver zen_2_3 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/amd/sabrina/data_fabric.c b/src/soc/amd/sabrina/data_fabric.c new file mode 100644 index 0000000000..8f821c3cc2 --- /dev/null +++ b/src/soc/amd/sabrina/data_fabric.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void data_fabric_set_mmio_np(void) +{ + /* + * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. + * + * AGESA has already programmed the NB MMIO routing, however nothing + * is yet marked as non-posted. + * + * If there exists an overlapping routing base/limit pair, trim its + * base or limit to avoid the new NP region. If any pair exists + * completely within HPET-LAPIC range, remove it. If any pair surrounds + * HPET-LAPIC, it must be split into two regions. + * + * TODO(b/156296146): Remove the settings from AGESA and allow coreboot + * to own everything. If not practical, consider erasing all settings + * and have coreboot reprogram them. At that time, make the source + * below more flexible. + * * Note that the code relies on the granularity of the HPET and + * LAPIC addresses being sufficiently large that the shifted limits + * +/-1 are always equivalent to the non-shifted values +/-1. + */ + + unsigned int i; + int reg; + uint32_t base, limit, ctrl; + const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; + + data_fabric_print_mmio_conf(); + + for (i = 0; i < NUM_NB_MMIO_REGS; i++) { + /* Adjust all registers that overlap */ + ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) + continue; /* not enabled */ + + base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); + limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)); + + if (base > np_top || limit < np_bot) + continue; /* no overlap at all */ + + if (base >= np_bot && limit <= np_top) { + data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ + continue; + } + + if (base < np_bot && limit > np_top) { + /* Split the configured region */ + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + /* Although a pair could be freed later, this condition is + * very unusual and deserves analysis. Flag an error and + * leave the topmost part unconfigured. */ + printk(BIOS_ERR, + "Error: Not enough NB MMIO routing registers\n"); + continue; + } + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); + continue; + } + + /* If still here, adjust only the base or limit */ + if (base <= np_bot) + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1); + else + data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1); + } + + reg = data_fabric_find_unused_mmio_reg(); + if (reg < 0) { + printk(BIOS_ERR, "Error: cannot configure region as NP\n"); + return; + } + + data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); + data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), + (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP + | DF_MMIO_WE | DF_MMIO_RE); + + data_fabric_print_mmio_conf(); +} + +static const char *data_fabric_acpi_name(const struct device *dev) +{ + switch (dev->device) { + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF0: + return "DFD0"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF1: + return "DFD1"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF2: + return "DFD2"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF3: + return "DFD3"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF4: + return "DFD4"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF5: + return "DFD5"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF6: + return "DFD6"; + case PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF7: + return "DFD7"; + default: + printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); + } + + return NULL; +} + +static struct device_operations data_fabric_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = data_fabric_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF0, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF1, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF2, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF3, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF4, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF5, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF6, + PCI_DEVICE_ID_AMD_FAM17H_MODELA0H_DF7, + 0 +}; + +static const struct pci_driver data_fabric_driver __pci_driver = { + .ops = &data_fabric_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; diff --git a/src/soc/amd/sabrina/early_fch.c b/src/soc/amd/sabrina/early_fch.c new file mode 100644 index 0000000000..45ba85c64c --- /dev/null +++ b/src/soc/amd/sabrina/early_fch.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" + +/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ +static const struct soc_i2c_scl_pin i2c_scl_pins[] = { + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), +}; + +static void reset_i2c_peripherals(void) +{ + const struct soc_amd_sabrina_config *cfg = config_of_soc(); + struct soc_i2c_peripheral_reset_info reset_info; + + reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; + reset_info.i2c_scl = i2c_scl_pins; + reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); + sb_reset_i2c_peripherals(&reset_info); +} + +/* Before console init */ +void fch_pre_init(void) +{ + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); + /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ + lpc_early_init(); + + /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI + interface hasn't already been set up in verstage on PSP */ + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) + configure_espi_with_mb_hook(); + + fch_spi_early_init(); + fch_smbus_init(); + fch_enable_cf9_io(); + fch_enable_legacy_io(); + fch_disable_legacy_dma_io(); + enable_aoac_devices(); + reset_i2c_peripherals(); + + /* + * On reset Range_0 defaults to enabled. We want to start with a clean + * slate to not have things unexpectedly enabled. + */ + clear_uart_legacy_config(); + + if (CONFIG(AMD_SOC_CONSOLE_UART)) + set_uart_config(CONFIG_UART_FOR_CONSOLE); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); +} + +/* After console init */ +void fch_early_init(void) +{ + pm_set_power_failure_state(); + fch_print_pmxc0_status(); + i2c_soc_early_init(); + show_spi_speeds_and_modes(); + + if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) + lpc_disable_spi_rom_sharing(); +} diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c new file mode 100644 index 0000000000..9be7dd8912 --- /dev/null +++ b/src/soc/amd/sabrina/fch.c @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +const static struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#/GENINT2" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_HPET_L, "HPET_L" }, + { PIRQ_HPET_H, "HPET_H" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SD, "SD" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_CIR, "CIR" }, + { PIRQ_GPIOA, "GPIOa" }, + { PIRQ_GPIOB, "GPIOb" }, + { PIRQ_GPIOC, "GPIOc" }, + { PIRQ_EMMC, "eMMC" }, + { PIRQ_GPP0, "GPP0" }, + { PIRQ_GPP1, "GPP1" }, + { PIRQ_GPP2, "GPP2" }, + { PIRQ_GPP3, "GPP3" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, + { PIRQ_I2C4, "I2C4" }, + { PIRQ_UART4, "UART4" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void fch_clk_output_48Mhz(void) +{ + uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); + /* Enable BP_X48M0 Clock Output */ + ctrl |= BP_X48M0_OUTPUT_EN; + /* Disable clock output in S0i3 */ + ctrl |= BP_X48M0_S0I3_DIS; + misc_write32(MISC_CLK_CNTL0, ctrl); +} + +static void fch_init_acpi_ports(void) +{ + u32 reg; + + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + response of the I/O write. */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + +static void fch_init_resets(void) +{ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ +static void gpp_clk_setup(void) +{ + const struct soc_amd_sabrina_config *cfg = config_of_soc(); + + /* look-up table to be able to iterate over the PCIe clock output settings */ + const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { + GPP_CLK0_REQ_SHIFT, + GPP_CLK1_REQ_SHIFT, + GPP_CLK2_REQ_SHIFT, + GPP_CLK3_REQ_SHIFT, + GPP_CLK4_REQ_SHIFT, + GPP_CLK5_REQ_SHIFT, + GPP_CLK6_REQ_SHIFT, + }; + + uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + + for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { + gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); + /* + * The remapping of values is done so that the default of the enum used for the + * devicetree settings is the clock being enabled, so that a missing devicetree + * configuration for this will result in an always active clock and not an + * inactive PCIe clock output. + */ + switch (cfg->gpp_clk_config[i]) { + case GPP_CLK_REQ: + gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_OFF: + gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); + break; + case GPP_CLK_ON: + default: + gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); + } + } + + misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); +} + +static void cgpll_clock_gate_init(void) +{ + uint32_t t; + + t = misc_read32(MISC_CLKGATEDCNTL); + t |= ALINKCLK_GATEOFFEN; + t |= BLINKCLK_GATEOFFEN; + t |= XTAL_PAD_S3_TURNOFF_EN; + t |= XTAL_PAD_S5_TURNOFF_EN; + misc_write32(MISC_CLKGATEDCNTL, t); + + t = misc_read32(MISC_CGPLL_CONFIGURATION0); + t |= USB_PHY_CMCLK_S3_DIS; + t |= USB_PHY_CMCLK_S0I3_DIS; + t |= USB_PHY_CMCLK_S5_DIS; + misc_write32(MISC_CGPLL_CONFIGURATION0, t); + + t = pm_read32(PM_ISACONTROL); + t |= ABCLKGATEEN; + pm_write32(PM_ISACONTROL, t); +} + +void fch_init(void *chip_info) +{ + fch_init_resets(); + i2c_soc_init(); + fch_init_acpi_ports(); + + acpi_pm_gpe_add_events_print_events(); + gpio_add_events(); + + gpp_clk_setup(); + fch_clk_output_48Mhz(); + cgpll_clock_gate_init(); +} + +void fch_final(void *chip_info) +{ +} + +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c new file mode 100644 index 0000000000..f069ba8f61 --- /dev/null +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +__weak void mb_pre_fspm(void) +{ +} + +static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, + const fsp_dxio_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT, + "Too many DXIO descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0])); + } +} + +static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg, + const fsp_ddi_descriptor *descs, size_t num) +{ + size_t i; + + ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT, + "Too many DDI descriptors provided."); + + for (i = 0; i < num; i++) { + memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0])); + } +} + +static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) +{ + const fsp_dxio_descriptor *fsp_dxio; + const fsp_ddi_descriptor *fsp_ddi; + size_t num_dxio; + size_t num_ddi; + + mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, + &fsp_ddi, &num_ddi); + fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio); + fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); +} + +static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + const struct soc_amd_sabrina_config *config = config_of_soc(); + + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); + + mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS; + mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; + mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); + mcfg->serial_port_baudrate = get_uart_baudrate(); + mcfg->serial_port_refclk = uart_platform_refclk(); + + /* 0 is default */ + mcfg->ccx_down_core_mode = config->downcore_mode; + mcfg->ccx_disable_smt = config->disable_smt; + + /* when stt_control isn't 1, FSP will ignore the other stt values */ + mcfg->stt_control = config->stt_control; + mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; + mcfg->stt_min_limit = config->stt_min_limit; + mcfg->stt_m1 = config->stt_m1; + mcfg->stt_m2 = config->stt_m2; + mcfg->stt_m3 = config->stt_m3; + mcfg->stt_m4 = config->stt_m4; + mcfg->stt_m5 = config->stt_m5; + mcfg->stt_m6 = config->stt_m6; + mcfg->stt_c_apu = config->stt_c_apu; + mcfg->stt_c_gpu = config->stt_c_gpu; + mcfg->stt_c_hs2 = config->stt_c_hs2; + mcfg->stt_alpha_apu = config->stt_alpha_apu; + mcfg->stt_alpha_gpu = config->stt_alpha_gpu; + mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; + mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; + mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; + mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; + mcfg->stt_error_coeff = config->stt_error_coeff; + mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; + + /* all following fields being 0 is a valid config */ + mcfg->stapm_boost = config->stapm_boost; + mcfg->stapm_time_constant = config->stapm_time_constant_s; + mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; + mcfg->sustained_power_limit = config->sustained_power_limit_mW; + mcfg->fast_ppt_limit = config->fast_ppt_limit_mW; + mcfg->slow_ppt_limit = config->slow_ppt_limit_mW; + mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s; + mcfg->thermctl_limit = config->thermctl_limit_degreeC; + + /* 0 is default */ + mcfg->smartshift_enable = config->smartshift_enable; + + /* 0 is default */ + mcfg->system_configuration = config->system_configuration; + + /* S0i3 enable */ + mcfg->s0i3_enable = config->s0ix_enable; + mcfg->iommu_support = is_devfn_enabled(IOMMU_DEVFN); + + /* voltage regulator telemetry settings */ + mcfg->telemetry_vddcrvddfull_scale_current = + config->telemetry_vddcrvddfull_scale_current_mA; + mcfg->telemetry_vddcrvddoffset = + config->telemetry_vddcrvddoffset; + mcfg->telemetry_vddcrsocfull_scale_current = + config->telemetry_vddcrsocfull_scale_current_mA; + mcfg->telemetry_vddcrsocOffset = + config->telemetry_vddcrsocoffset; + + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + + mcfg->enable_nb_azalia = is_dev_enabled(DEV_PTR(gfx_hda)); + mcfg->hda_enable = is_dev_enabled(DEV_PTR(hda)); + + if (config->usb_phy_custom) { + mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; + mcfg->usb_phy->Version_Major = 0xd; + mcfg->usb_phy->Version_Minor = 0x6; + mcfg->usb_phy->TableLength = 100; + } else { + mcfg->usb_phy = NULL; + } + + fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); + mb_pre_fspm(); +} diff --git a/src/soc/amd/sabrina/fsp_s_params.c b/src/soc/amd/sabrina/fsp_s_params.c new file mode 100644 index 0000000000..3f7aa9f854 --- /dev/null +++ b/src/soc/amd/sabrina/fsp_s_params.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include + +static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) +{ + scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + FSP_S_CONFIG *scfg = &supd->FspsConfig; + + fsp_assign_vbios_upds(scfg); + + /* + * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB + * before FSP-S was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs + * no SPI operations, we can read the APOB while FSP-S executes. + */ + start_apob_cache_read(); + /* + * We enqueue the payload to be loaded after the APOB. This might cause a bit of + * bus contention when loading uCode and OPROMs, but since those calls happen at + * different points in the boot state machine it's a little harder to sequence all the + * async loading correctly. So in order to keep the complexity down, we enqueue the + * payload preload here. The end goal will be to add uCode and OPROM preloading + * before the payload so that the sequencing is correct. + * + * While FSP-S is executing, it's not currently possible to enqueue other transactions + * because FSP-S doesn't call `thread_yield()`. So the payload will start loading + * right after FSP-S completes. + */ + if (!acpi_is_wakeup_s3()) + payload_preload(); +} diff --git a/src/soc/amd/sabrina/fw.cfg b/src/soc/amd/sabrina/fw.cfg new file mode 100644 index 0000000000..02ada24a7c --- /dev/null +++ b/src/soc/amd/sabrina/fw.cfg @@ -0,0 +1,42 @@ +# PSP fw config file + +# TODO: Check if this is still correct + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin + +# BDT +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin +PSP_PMUI_FILE_SUB0_INS2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin +PSP_PMUD_FILE_SUB0_INS2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/src/soc/amd/sabrina/gpio.c b/src/soc/amd/sabrina/gpio.c new file mode 100644 index 0000000000..74eecadcce --- /dev/null +++ b/src/soc/amd/sabrina/gpio.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */ +static const struct soc_amd_event gpio_event_table[] = { + { GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */ + { GPIO_1, GEVENT_19 }, + { GPIO_2, GEVENT_8 }, + { GPIO_3, GEVENT_2 }, + { GPIO_4, GEVENT_4 }, + { GPIO_5, GEVENT_7 }, + { GPIO_6, GEVENT_10 }, + { GPIO_7, GEVENT_11 }, + { GPIO_8, GEVENT_23 }, + { GPIO_9, GEVENT_22 }, + { GPIO_11, GEVENT_5 }, + { GPIO_16, GEVENT_12 }, + { GPIO_17, GEVENT_13 }, + { GPIO_18, GEVENT_14 }, + { GPIO_22, GEVENT_3 }, + { GPIO_23, GEVENT_16 }, + { GPIO_24, GEVENT_15 }, + { GPIO_29, GEVENT_9 }, + { GPIO_32, GEVENT_17 }, + { GPIO_40, GEVENT_20 }, + { GPIO_84, GEVENT_18 }, + { GPIO_89, GEVENT_0 }, + { GPIO_90, GEVENT_1 }, + { GPIO_91, GEVENT_6 }, +}; + +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) +{ + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); +} diff --git a/src/soc/amd/sabrina/i2c.c b/src/soc/amd/sabrina/i2c.c new file mode 100644 index 0000000000..1008f564fd --- /dev/null +++ b/src/soc/amd/sabrina/i2c.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "chip.h" + +#if ENV_X86 +static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" }, + { I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" }, + { I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" }, + { I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" } +}; +#else +static struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = { + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" }, + { I2C_MASTER_MODE, 0, "" } +}; + +void i2c_set_bar(unsigned int bus, uintptr_t bar) +{ + if (bus >= ARRAY_SIZE(i2c_ctrlr)) { + printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + return; + } + + i2c_ctrlr[bus].bar = bar; +} +#endif + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + const struct soc_amd_sabrina_config *config = config_of_soc(); + + if (bus >= ARRAY_SIZE(config->i2c_pad)) + return; + + /* The I/O pads of I2C0..2 are the new I23C pads and the I/O pads of I2C3 still are the + same I2C pads as in Picasso and Cezanne. */ + if (bus <= 2) + fch_i23c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); + else + fch_i2c_pad_init(bus, cfg->speed, &config->i2c_pad[bus]); +} + +const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i2c_ctrlr); + return i2c_ctrlr; +} + +const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) +{ + const struct soc_amd_sabrina_config *config = config_of_soc(); + + *num_buses = ARRAY_SIZE(config->i2c); + return config->i2c; +} diff --git a/src/soc/amd/sabrina/include/soc/acpi.h b/src/soc/amd/sabrina/include/soc/acpi.h new file mode 100644 index 0000000000..802d443c17 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/acpi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_ACPI_H +#define AMD_SABRINA_ACPI_H + +#include +#include +#include +#include + +#define ACPI_SCI_IRQ 9 + +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0d +#define RTC_ALT_CENTURY 0x32 +#define RTC_CENTURY 0x48 + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + +#endif /* AMD_SABRINA_ACPI_H */ diff --git a/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h new file mode 100644 index 0000000000..424b2245d3 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_AMD_PCI_INT_DEFS_H +#define AMD_SABRINA_AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */ +#define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ +#define PIRQ_ASF 0x12 /* ASF */ +/* 0x13-0x15 reserved */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_SD 0x17 /* SD */ +/* 0x18-0x19 reserved */ +#define PIRQ_SDIO 0x1a /* SDIO */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x4f reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x61 reserved */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_UART4 0x77 /* UART4 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ + +#endif /* AMD_SABRINA_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/sabrina/include/soc/aoac_defs.h b/src/soc/amd/sabrina/include/soc/aoac_defs.h new file mode 100644 index 0000000000..4b2b4fe580 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/aoac_defs.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_AOAC_DEFS_H +#define AMD_SABRINA_AOAC_DEFS_H + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_I2C5 10 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_UART3 26 +#define FCH_AOAC_DEV_ESPI 27 +#define FCH_AOAC_DEV_EMMC 28 + +#endif /* AMD_SABRINA_AOAC_DEFS_H */ diff --git a/src/soc/amd/sabrina/include/soc/cpu.h b/src/soc/amd/sabrina/include/soc/cpu.h new file mode 100644 index 0000000000..b7578139de --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_CPU_H +#define AMD_SABRINA_CPU_H + +#define SABRINA_A0_CPUID 0x008a0f00 + +#endif /* AMD_SABRINA_CPU_H */ diff --git a/src/soc/amd/sabrina/include/soc/data_fabric.h b/src/soc/amd/sabrina/include/soc/data_fabric.h new file mode 100644 index 0000000000..fbae1c6591 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/data_fabric.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_DATA_FABRIC_H +#define AMD_SABRINA_DATA_FABRIC_H + +#include + +/* SoC-specific bits in D18F0_MMIO_CTRL0 */ +#define DF_MMIO_NP BIT(16) + +#define IOMS0_FABRIC_ID 9 + +#define NUM_NB_MMIO_REGS 8 + +void data_fabric_set_mmio_np(void); + +#endif /* AMD_SABRINA_DATA_FABRIC_H */ diff --git a/src/soc/amd/sabrina/include/soc/gpio.h b/src/soc/amd/sabrina/include/soc/gpio.h new file mode 100644 index 0000000000..fbb19cd923 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/gpio.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_GPIO_H +#define AMD_SABRINA_GPIO_H + +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ +#include +#include +#endif /* !__ACPI__ */ + +#include + +/* The following sections describe only the GPIOs defined for this SOC */ + +#define SOC_GPIO_TOTAL_PINS 158 + +/* Bank 0: GPIO_0 - GPIO_63 */ +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_42 42 + +/* Bank 1: GPIO_64 - GPIO_127 */ +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_77 77 +#define GPIO_78 78 +#define GPIO_79 79 +#define GPIO_80 80 +#define GPIO_81 81 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_104 104 +#define GPIO_105 105 +#define GPIO_106 106 +#define GPIO_107 107 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 + +/* Bank 2: GPIO_128 - GPIO_191 */ +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 +#define GPIO_153 153 +#define GPIO_154 154 +#define GPIO_155 155 +#define GPIO_156 156 +#define GPIO_157 157 + +/* IOMUX function names and values */ +#define GPIO_0_IOMUX_PWR_BTN_L 0 +#define GPIO_0_IOMUX_GPIOxx 1 +#define GPIO_1_IOMUX_SYS_RESET_L 0 +#define GPIO_1_IOMUX_GPIOxx 1 +#define GPIO_2_IOMUX_WAKE_L 0 +#define GPIO_2_IOMUX_GPIOxx 1 +#define GPIO_3_IOMUX_GPIOxx 0 +#define GPIO_4_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_GPIOxx 0 +#define GPIO_5_IOMUX_DEVSLP0 1 +#define GPIO_6_IOMUX_GPIOxx 0 +#define GPIO_6_IOMUX_DEVSLP1 1 +#define GPIO_6_IOMUX_MDIO0_SCL 2 +#define GPIO_7_IOMUX_GPIOxx 0 +#define GPIO_7_IOMUX_SVI_RST_L 1 +#define GPIO_8_IOMUX_GPIOxx 0 +#define GPIO_8_IOMUX_TMU_CLK_OUT0 1 +#define GPIO_8_IOMUX_TMU_CLK_OUT1 2 +#define GPIO_9_IOMUX_GPIOxx 0 +/* GPIO 9 IOMUX == 1 is also GPIOxx */ +#define GPIO_9_IOMUX_MDIO2_SCL 2 +#define GPIO_10_IOMUX_GPIOxx 0 +#define GPIO_10_IOMUX_S0A3_GPIO 1 +#define GPIO_11_IOMUX_GPIOxx 0 +#define GPIO_11_IOMUX_BLINK 1 +#define GPIO_11_IOMUX_MDIO3_SDA 2 +#define GPIO_12_IOMUX_LLB_L 0 +#define GPIO_12_IOMUX_GPIOxx 1 +#define GPIO_12_IOMUX_LPC_PME_L 2 +#define GPIO_13_IOMUX_USB_SBTX_0 0 +#define GPIO_13_IOMUX_GPIOxx 1 +#define GPIO_14_IOMUX_USB_SBTX_1 0 +#define GPIO_14_IOMUX_GPIOxx 1 +#define GPIO_16_IOMUX_USB_OC0_L 0 +#define GPIO_16_IOMUX_GPIOxx 1 +#define GPIO_17_IOMUX_USB_OC1_L 0 +#define GPIO_17_IOMUX_GPIOxx 1 +#define GPIO_18_IOMUX_USB_OC2_L 0 +#define GPIO_18_IOMUX_GPIOxx 1 +#define GPIO_19_IOMUX_SMBUS1_SCL 0 +#define GPIO_19_IOMUX_I2C3_SCL 1 +/* GPIO 19 IOMUX == 2 is also I2C3_SCL */ +#define GPIO_19_IOMUX_GPIOxx 3 +#define GPIO_20_IOMUX_SMBUS1_SDA 0 +#define GPIO_20_IOMUX_I2C3_SDA 1 +/* GPIO 19 IOMUX == 2 is also I2C3_SDA */ +#define GPIO_20_IOMUX_GPIOxx 3 +#define GPIO_21_IOMUX_ESPI_RESET_L 0 +#define GPIO_21_IOMUX_KBRST_L 1 +#define GPIO_21_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_LDRQ0_L 0 +#define GPIO_22_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_22_IOMUX_GPIOxx 2 +#define GPIO_22_IOMUX_SD0_CMD 3 +#define GPIO_23_IOMUX_AC_PRES 0 +#define GPIO_23_IOMUX_GPIOxx 1 +#define GPIO_23_IOMUX_MDIO2_SDA 2 +#define GPIO_24_IOMUX_USB_OC3_L 0 +#define GPIO_24_IOMUX_GPIOxx 1 +#define GPIO_26_IOMUX_PCIE_RST0_L 0 +#define GPIO_26_IOMUX_GPIOxx 1 +#define GPIO_27_IOMUX_GPIOxx 0 +#define GPIO_27_IOMUX_PCIE_RST1_L 1 +#define GPIO_29_IOMUX_SPI_TPM_CS_L 0 +#define GPIO_29_IOMUX_GPIOxx 1 +#define GPIO_30_IOMUX_SPI_CS2_L 0 +#define GPIO_30_IOMUX_ESPI_CS_L 1 +#define GPIO_30_IOMUX_GPIOxx 2 +#define GPIO_31_IOMUX_SPI_CS3_L 0 +#define GPIO_31_IOMUX_GPIOxx 1 +#define GPIO_32_IOMUX_GPIOxx 0 +#define GPIO_32_IOMUX_LPC_RST_L 1 +#define GPIO_32_IOMUX_MDIO3_SCL 2 +#define GPIO_38_IOMUX_CLK_REQ5_L 0 +#define GPIO_38_IOMUX_GPIOxx 1 +#define GPIO_38_IOMUX_MDIO1_SDA 2 +#define GPIO_39_IOMUX_CLK_REQ6_L 0 +#define GPIO_39_IOMUX_GPIOxx 1 +#define GPIO_39_IOMUX_MDIO1_SCL 2 +#define GPIO_40_IOMUX_GPIOxx 0 +/* GPIO 40 IOMUX == 1 is also GPIOxx */ +#define GPIO_40_IOMUX_MDIO0_SDA 2 +#define GPIO_42_IOMUX_GPIOxx 0 +#define GPIO_67_IOMUX_SPI_ROM_REQ 0 +#define GPIO_67_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_SPI1_DAT2 0 +#define GPIO_68_IOMUX_GPIOxx 1 +#define GPIO_68_IOMUX_SERIRQ 2 +#define GPIO_68_IOMUX_SD0_DATA3 3 +#define GPIO_69_IOMUX_SPI1_DAT3 0 +#define GPIO_69_IOMUX_GPIOxx 1 +#define GPIO_69_IOMUX_SD0_CLK 2 +#define GPIO_70_IOMUX_SPI2_CLK 0 +#define GPIO_70_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_SPI1_CS1_L 0 +#define GPIO_74_IOMUX_GPIOxx 1 +#define GPIO_74_IOMUX_GFX10_CAC_IPIO0 2 +#define GPIO_75_IOMUX_SPI2_CS1_L 0 +#define GPIO_75_IOMUX_LPCCLK1 1 +#define GPIO_75_IOMUX_GPIOxx 2 +#define GPIO_76_IOMUX_SPI_ROM_GNT 0 +#define GPIO_76_IOMUX_GPIOxx 1 +#define GPIO_77_IOMUX_SPI1_CLK 0 +#define GPIO_77_IOMUX_GPIOxx 1 +/* GPIO 77 IOMUX == 2 is also GPIOxx */ +#define GPIO_77_IOMUX_SD0_DATA0 3 +#define GPIO_78_IOMUX_SPI1_CS2_L 0 +#define GPIO_78_IOMUX_GPIOxx 1 +#define GPIO_78_IOMUX_GFX10_CAC_IPIO1 2 +#define GPIO_78_IOMUX_SD0_DATA1 3 +#define GPIO_79_IOMUX_SPI1_CS3_L 0 +#define GPIO_79_IOMUX_GPIOxx 1 +#define GPIO_79_IOMUX_LPC_CLKRUN_L 2 +#define GPIO_80_IOMUX_SPI1_DAT1 0 +#define GPIO_80_IOMUX_GPIOxx 1 +/* GPIO 80 IOMUX == 2 is also GPIOxx */ +#define GPIO_80_IOMUX_SD0_DATA2 3 +#define GPIO_81_IOMUX_SPI1_DAT0 0 +#define GPIO_81_IOMUX_GPIOxx 1 +#define GPIO_84_IOMUX_FANIN0 0 +#define GPIO_84_IOMUX_GPIOxx 1 +#define GPIO_85_IOMUX_FANOUT0 0 +#define GPIO_85_IOMUX_GPIOxx 1 +#define GPIO_86_IOMUX_GPIOxx 0 +#define GPIO_86_IOMUX_LPC_SMI_L 1 +#define GPIO_89_IOMUX_GENINT1_L 0 +#define GPIO_89_IOMUX_PSP_INTR0 1 +#define GPIO_89_IOMUX_GPIOxx 2 +#define GPIO_90_IOMUX_GENINT2_L 0 +#define GPIO_90_IOMUX_PSP_INTR1 1 +#define GPIO_90_IOMUX_GPIOxx 2 +#define GPIO_91_IOMUX_SPKR 0 +#define GPIO_91_IOMUX_GPIOxx 1 +#define GPIO_92_IOMUX_CLK_REQ0_L 0 +#define GPIO_92_IOMUX_SATA_IS0_L 1 +#define GPIO_92_IOMUX_SATA_ZP0_L 2 +#define GPIO_92_IOMUX_GPIOxx 3 +#define GPIO_104_IOMUX_SPI2_DAT0 0 +#define GPIO_104_IOMUX_GPIOxx 1 +#define GPIO_105_IOMUX_SPI2_DAT1 0 +#define GPIO_105_IOMUX_GPIOxx 1 +#define GPIO_106_IOMUX_SPI2_DAT2 0 +#define GPIO_106_IOMUX_GPIOxx 1 +#define GPIO_107_IOMUX_SPI2_DAT3 0 +#define GPIO_107_IOMUX_GPIOxx 1 +#define GPIO_113_IOMUX_SMBUS0_SCL 0 +#define GPIO_113_IOMUX_I2C2_SCL 1 +#define GPIO_113_IOMUX_I3C2_SCL 2 +#define GPIO_113_IOMUX_GPIOxx 3 +#define GPIO_114_IOMUX_SMBUS0_SDA 0 +#define GPIO_114_IOMUX_I2C2_SDA 1 +#define GPIO_114_IOMUX_I3C2_SDA 2 +#define GPIO_114_IOMUX_GPIOxx 3 +#define GPIO_115_IOMUX_CLK_REQ1_L 0 +#define GPIO_115_IOMUX_GPIOxx 1 +#define GPIO_116_IOMUX_CLK_REQ2_L 0 +#define GPIO_116_IOMUX_GPIOxx 1 +#define GPIO_130_IOMUX_SATA_ACT_L 0 +#define GPIO_130_IOMUX_GPIOxx 1 +#define GPIO_131_IOMUX_CLK_REQ3_L 0 +#define GPIO_131_IOMUX_SATA_IS1_L 1 +#define GPIO_131_IOMUX_SATA_ZP1_L 2 +#define GPIO_131_IOMUX_GPIOxx 3 +#define GPIO_132_IOMUX_CLK_REQ4_L 0 +#define GPIO_132_IOMUX_OSCIN 1 +#define GPIO_132_IOMUX_GPIOxx 2 +#define GPIO_135_IOMUX_GPIOxx 0 +#define GPIO_135_IOMUX_UART2_CTS_L 1 +#define GPIO_135_IOMUX_UART3_TXD 2 +#define GPIO_136_IOMUX_GPIOxx 0 +#define GPIO_136_IOMUX_UART2_RXD 1 +#define GPIO_137_IOMUX_GPIOxx 0 +#define GPIO_137_IOMUX_UART2_RTS_L 1 +#define GPIO_137_IOMUX_UART3_RXD 2 +#define GPIO_138_IOMUX_GPIOxx 0 +#define GPIO_138_IOMUX_UART2_TXD 1 +#define GPIO_139_IOMUX_GPIOxx 0 +#define GPIO_139_IOMUX_UART2_INTR 1 +#define GPIO_140_IOMUX_GPIOxx 0 +#define GPIO_140_IOMUX_UART0_CTS_L 1 +#define GPIO_140_IOMUX_UART1_TXD 2 +#define GPIO_141_IOMUX_GPIOxx 0 +#define GPIO_141_IOMUX_UART0_RXD 1 +#define GPIO_142_IOMUX_GPIOxx 0 +#define GPIO_142_IOMUX_UART0_RTS_L 1 +#define GPIO_142_IOMUX_UART1_RXD 2 +#define GPIO_143_IOMUX_GPIOxx 0 +#define GPIO_143_IOMUX_UART0_TXD 1 +#define GPIO_144_IOMUX_GPIOxx 0 +#define GPIO_144_IOMUX_SHUTDOWN_L 1 +#define GPIO_144_IOMUX_UART0_INTR 2 +#define GPIO_145_IOMUX_I2C0_SCL 0 +#define GPIO_145_IOMUX_I3C0_SCL 1 +#define GPIO_145_IOMUX_GPIOxx 2 +#define GPIO_146_IOMUX_I2C0_SDA 0 +#define GPIO_146_IOMUX_I3C0_SDA 1 +#define GPIO_146_IOMUX_GPIOxx 2 +#define GPIO_147_IOMUX_I2C1_SCL 0 +#define GPIO_147_IOMUX_I3C1_SCL 1 +#define GPIO_147_IOMUX_GPIOxx 2 +#define GPIO_148_IOMUX_I2C1_SDA 0 +#define GPIO_148_IOMUX_I3C1_SDA 1 +#define GPIO_148_IOMUX_GPIOxx 2 +#define GPIO_153_IOMUX_GPIOxx 0 +#define GPIO_153_IOMUX_UART4_CTS_L 1 +#define GPIO_154_IOMUX_GPIOxx 0 +#define GPIO_154_IOMUX_UART4_RTS_L 1 +#define GPIO_155_IOMUX_GPIOxx 0 +#define GPIO_155_IOMUX_UART4_RXD 1 +#define GPIO_156_IOMUX_GPIOxx 0 +#define GPIO_156_IOMUX_UART4_TXD 1 +#define GPIO_157_IOMUX_GPIOxx 0 +#define GPIO_157_IOMUX_UART4_INTR 1 + +#endif /* AMD_SABRINA_GPIO_H */ diff --git a/src/soc/amd/sabrina/include/soc/i2c.h b/src/soc/amd/sabrina/include/soc/i2c.h new file mode 100644 index 0000000000..023bb34ac7 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/i2c.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_I2C_H +#define AMD_SABRINA_I2C_H + +#include +#include + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_113 +#define I2C3_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void i2c_set_bar(unsigned int bus, uintptr_t bar); + +#endif /* AMD_SABRINA_I2C_H */ diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h new file mode 100644 index 0000000000..7f9746b97f --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/iomap.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_IOMAP_H +#define AMD_SABRINA_IOMAP_H + +#define I2C_MASTER_DEV_COUNT 4 +#define I2C_MASTER_START_INDEX 0 +#define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + +#if ENV_X86 + +/* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 +#define SPI_BASE_ADDRESS 0xfec10000 + +/* FCH AL2AHB Registers */ +#define ALINK_AHB_ADDRESS 0xfedc0000 + +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 + +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_DMAC4_BASE 0xfedd0000 +#define APU_UART4_BASE 0xfedd1000 + +#define APU_EMMC_BASE 0xfedd5000 +#define APU_EMMC_CONFIG_BASE 0xfedd5800 + +#endif /* ENV_X86 */ + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define ACPI_IO_BASE 0x0400 +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) +#define SMB_BASE_ADDR 0x0b00 + +#endif /* AMD_SABRINA_IOMAP_H */ diff --git a/src/soc/amd/sabrina/include/soc/lpc.h b/src/soc/amd/sabrina/include/soc/lpc.h new file mode 100644 index 0000000000..d5e5712a5c --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/lpc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_LPC_H +#define AMD_SABRINA_LPC_H + +/* LPC_MISC_CONTROL_BITS at D14F3x078 */ +/* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne + and newer, so we need to keep those in a SoC-specific header file. */ +#define LPC_LDRQ0_PU_EN BIT(10) +#define LPC_LDRQ0_PD_EN BIT(9) + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_SABRINA_LPC_H */ diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h new file mode 100644 index 0000000000..bdc7a14c40 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/msr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_MSR_H +#define AMD_SABRINA_MSR_H + +/* MSRC001_00[6B:64] P-state [7:0] bit definitions */ +#define PSTATE_DEF_HI_ENABLE_SHIFT 31 +#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) +#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 +#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) +#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 +#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT) +#define PSTATE_DEF_LO_CORE_VID_SHIFT 14 +#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8 +#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT) +#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8 +#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A +#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E +#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0 +#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) +#define PSTATE_DEF_LO_CORE_FREQ_BASE 25 + +#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 +#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 + +#endif /* AMD_SABRINA_MSR_H */ diff --git a/src/soc/amd/sabrina/include/soc/nvs.h b/src/soc/amd/sabrina/include/soc/nvs.h new file mode 100644 index 0000000000..95b7392b61 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/nvs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Check if this is still correct */ + +/* + * NOTE: The layout of the global_nvs structure below must match the layout + * in soc/soc/amd/sabrina/acpi/globalnvs.asl !!! + * + */ + +#ifndef AMD_SABRINA_NVS_H +#define AMD_SABRINA_NVS_H + +#include + +struct __packed global_nvs { + /* Miscellaneous */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ + uint8_t lids; /* 0x01 - LID State */ + uint8_t unused_was_pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ +}; + +#endif /* AMD_SABRINA_NVS_H */ diff --git a/src/soc/amd/sabrina/include/soc/pci_devs.h b/src/soc/amd/sabrina/include/soc/pci_devs.h new file mode 100644 index 0000000000..52ecbd624b --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/pci_devs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_PCI_DEVS_H +#define AMD_SABRINA_PCI_DEVS_H + +#include +#include + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) +#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) + +/* PCIe GFX/GPP Bridge device 1 with no ports */ +#define PCIE_GPP_BRIDGE_1_DEV 0x1 + +/* PCIe GPP Bridge device 2 with up to 6 ports */ +#define PCIE_GPP_BRIDGE_2_DEV 0x2 + +#define PCIE_GPP_2_0_FUNC 1 +#define PCIE_GPP_2_0_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) +#define SOC_GPP_2_0_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_0_FUNC) + +#define PCIE_GPP_2_1_FUNC 2 +#define PCIE_GPP_2_1_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) +#define SOC_GPP_2_1_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_1_FUNC) + +#define PCIE_GPP_2_2_FUNC 3 +#define PCIE_GPP_2_2_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) +#define SOC_GPP_2_2_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_2_FUNC) + +#define PCIE_GPP_2_3_FUNC 4 +#define PCIE_GPP_2_3_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) +#define SOC_GPP_2_3_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_3_FUNC) + +#define PCIE_GPP_2_4_FUNC 5 +#define PCIE_GPP_2_4_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) +#define SOC_GPP_2_4_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_4_FUNC) + +#define PCIE_GPP_2_5_FUNC 6 +#define PCIE_GPP_2_5_DEVFN PCI_DEVFN(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) +#define SOC_GPP_2_5_DEV _SOC_DEV(PCIE_GPP_BRIDGE_2_DEV, PCIE_GPP_2_5_FUNC) + +/* PCIe Bridges to Bus A, Bus B and Bus C devices */ +#define PCIE_ABC_BRIDGE_DEV 0x8 + +#define PCIE_ABC_A_FUNC 1 +#define PCIE_ABC_A_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) +#define SOC_PCIE_ABC_A_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_A_FUNC) + +#define GFX_DEV 0x0 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +#define GFX_HDA_DEV 0x0 +#define GFX_HDA_FUNC 1 +#define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC) + +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) + +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) + +#define AUDIO_DEV 0x0 +#define AUDIO_FUNC 5 +#define AUDIO_DEVFN PCI_DEVFN(AUDIO_DEV, AUDIO_FUNC) + +#define HD_AUDIO_DEV 0x0 +#define HD_AUDIO_FUNC 6 +#define HD_AUDIO_DEVFN PCI_DEVFN(HD_AUDIO_DEV, HD_AUDIO_FUNC) + +#define PCIE_ABC_B_FUNC 2 +#define PCIE_GPP_B_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) +#define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) + +#define PCIE_ABC_C_FUNC 3 +#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif /* AMD_SABRINA_PCI_DEVS_H */ diff --git a/src/soc/amd/sabrina/include/soc/platform_descriptors.h b/src/soc/amd/sabrina/include/soc/platform_descriptors.h new file mode 100644 index 0000000000..c8e0fd0486 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/platform_descriptors.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_PLATFORM_DESCRIPTORS_H +#define AMD_SABRINA_PLATFORM_DESCRIPTORS_H + +#include +#include +#include + +/* Mainboard callback to obtain DXI/PCIe and DDI descriptors. */ +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); + +void mb_pre_fspm(void); + +#endif /* AMD_SABRINA_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/sabrina/include/soc/psp_transfer.h b/src/soc/amd/sabrina/include/soc/psp_transfer.h new file mode 100644 index 0000000000..60555991ca --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/psp_transfer.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_PSP_TRANSFER_H +#define AMD_SABRINA_PSP_TRANSFER_H + +# if (CONFIG_CMOS_RECOVERY_BYTE != 0) +# define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE +# elif CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) +# error "Must set CONFIG_CMOS_RECOVERY_BYTE" +# endif + +#define CMOS_RECOVERY_MAGIC_VAL 0x96 + +#define TRANSFER_INFO_SIZE 64 +#define TIMESTAMP_BUFFER_SIZE 0x200 + +#define TRANSFER_MAGIC_VAL 0x50544953 + +/* Bit definitions for the psp_info field in the PSP transfer_info_struct */ +#define PSP_INFO_PRODUCTION_MODE 0x00000001UL +#define PSP_INFO_PRODUCTION_SILICON 0x00000002UL +#define PSP_INFO_VALID 0x80000000UL + +/* Area for things that would cause errors in a linker script */ +#if !defined(__ASSEMBLER__) +#include + +struct transfer_info_struct { + uint32_t magic_val; /* Identifier */ + uint32_t struct_bytes; /* Size of this structure */ + uint32_t buffer_size; /* Size of the transfer buffer area */ + + /* Offsets from start of transfer buffer */ + uint32_t workbuf_offset; + uint32_t console_offset; + uint32_t timestamp_offset; + uint32_t fmap_offset; + + uint32_t unused1[5]; + + /* Fields reserved for the PSP */ + uint64_t timestamp; /* Offset 0x30 */ + uint32_t psp_unused; /* Offset 0x38 */ + uint32_t psp_info; /* Offset 0x3C */ +}; + +_Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE, + "TRANSFER_INFO_SIZE is incorrect"); + +/* Make sure the PSP transferred information over to x86 side. */ +void verify_psp_transfer_buf(void); +/* Display the transfer block's PSP_info data */ +void show_psp_transfer_info(void); +/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ +void boot_with_psp_timestamp(uint64_t base_timestamp); + +#endif +#endif /* AMD_SABRINA_PSP_TRANSFER_H */ diff --git a/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h new file mode 100644 index 0000000000..6636ea15e0 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/psp_verstage_addr.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_PSP_VERSTAGE_ADDR_H +#define AMD_SABRINA_PSP_VERSTAGE_ADDR_H + +/* + * Start of available space is 0x36000 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 0x14000 bytes + */ +#define PSP_SRAM_START 0x26000 +#define PSP_SRAM_SIZE (148K) +#define VERSTAGE_START PSP_SRAM_START + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ + +#define PSP_VERSTAGE_STACK_START 0x41000 +#define PSP_VERSTAGE_STACK_SIZE (40K) + +#endif /* AMD_SABRINA_PSP_VERSTAGE_ADDR_H */ diff --git a/src/soc/amd/sabrina/include/soc/smi.h b/src/soc/amd/sabrina/include/soc/smi.h new file mode 100644 index 0000000000..1642c06151 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/smi.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_SABRINA_SMI_H +#define AMD_SABRINA_SMI_H + +#include + +#define SMI_GEVENTS 24 +#define SCIMAPS 64 /* 0..63 */ +#define SCI_GPES 32 +#define NUMBER_SMITYPES 160 + +#define SMI_EVENT_STATUS 0x0 +#define SMI_EVENT_ENABLE 0x04 +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +/* SMI source and status */ +#define SMITYPE_G_GENINT1_L 0 +#define SMITYPE_G_GENINT2_L 1 +#define SMITYPE_G_AGPIO3 2 +#define SMITYPE_G_ESPI_ALERT_L 3 +#define SMITYPE_G_AGPIO4 4 +#define SMITYPE_G_BLINK 5 +#define SMITYPE_G_SPKR 6 +#define SMITYPE_G_AGPIO5 7 +#define SMITYPE_G_WAKE_L 8 +#define SMITYPE_G_SPI_TPM_CS_L 9 +#define SMITYPE_G_AGPIO6 10 +#define SMITYPE_G_AGPIO7 11 +#define SMITYPE_G_USBOC0_L 12 +#define SMITYPE_G_USBOC1_L 13 +#define SMITYPE_G_USBOC2_L 14 +#define SMITYPE_G_USBOC3_L 15 +#define SMITYPE_G_AGPIO23 16 +#define SMITYPE_G_AGPIO32 17 +#define SMITYPE_G_FANIN0 18 +#define SMITYPE_G_SYSRESET_L 19 +#define SMITYPE_G_AGPIO40 20 +#define SMITYPE_G_PWR_BTN_L 21 +#define SMITYPE_G_AGPIO9 22 +#define SMITYPE_G_AGPIO8 23 +#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ + | (1 << SMITYPE_G_GENINT2_L) \ + | (1 << SMITYPE_G_AGPIO3) \ + | (1 << SMITYPE_G_ESPI_ALERT_L) \ + | (1 << SMITYPE_G_AGPIO4) \ + | (1 << SMITYPE_G_BLINK) \ + | (1 << SMITYPE_G_SPKR) \ + | (1 << SMITYPE_G_AGPIO5) \ + | (1 << SMITYPE_G_WAKE_L) \ + | (1 << SMITYPE_G_SPI_TPM_CS_L) \ + | (1 << SMITYPE_G_AGPIO6) \ + | (1 << SMITYPE_G_AGPIO7) \ + | (1 << SMITYPE_G_USBOC0_L) \ + | (1 << SMITYPE_G_USBOC1_L) \ + | (1 << SMITYPE_G_USBOC2_L) \ + | (1 << SMITYPE_G_USBOC3_L) \ + | (1 << SMITYPE_G_AGPIO23) \ + | (1 << SMITYPE_G_AGPIO32) \ + | (1 << SMITYPE_G_FANIN0) \ + | (1 << SMITYPE_G_SYSRESET_L) \ + | (1 << SMITYPE_G_AGPIO40) \ + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPIO9) \ + | (1 << SMITYPE_G_AGPIO8)) +#define SMITYPE_MP2_WAKE 24 +#define SMITYPE_MP2_GPIO0 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +#define SMITYPE_MP2_GPIO1 28 +#define SMITYPE_GPP_PME 29 +#define SMITYPE_NB_GPP_HOT_PLUG 30 +/* 31 Reserved */ +#define SMITYPE_WAKE_L2 32 +#define SMITYPE_PSP 33 +/* 34,35 Reserved */ +#define SMITYPE_ESPI_SCI_B 36 +#define SMITYPE_CIO_FCH_PME_S5_0 37 +#define SMITYPE_CIO_FCH_PME_S5_1 38 +#define SMITYPE_AZPME 39 +#define SMITYPE_USB_PD_I2C4 40 +#define SMITYPE_GPIO_CTL 41 +#define SMITYPE_XHC2_PME 42 +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +#define SMITYPE_XHC1_PME 57 +#define SMITYPE_ACDC_TIMER 58 +/* 59-60 Reserved */ +#define SMITYPE_XHC3_PME 61 +#define SMITYPE_XHC4_PME 62 +#define SMITYPE_CUR_TEMP_STATUS_5 63 +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +/* 67 Reserved */ +#define SMITYPE_NB_GPP_PME_PULSE 68 +#define SMITYPE_NB_GPP_HP_PULSE 69 +#define SMITYPE_USB_PD_I2C4_INTR2 70 +/* 71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +/* 79-80 Reserved */ +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +/* 85-89 Reserved */ +#define SMITYPE_EMUL60_64 90 +/* 91-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-140 Reserved */ +#define SMITYPE_CF9_WRITE 141 +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +#define SMITYPE_ANY_RESET 145 +#define SMITYPE_ESPI_SMI 146 +/* 147 Reserved */ +#define SMITYPE_IOTRAP0 148 +#define SMITYPE_IOTRAP1 149 +#define SMITYPE_IOTRAP2 150 +#define SMITYPE_IOTRAP3 151 +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ + +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRIG0_PSP (1 << 25) +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 + +#define SMI_MODE_MASK 0x03 + +#endif /* AMD_SABRINA_SMI_H */ diff --git a/src/soc/amd/sabrina/include/soc/smu.h b/src/soc/amd/sabrina/include/soc/smu.h new file mode 100644 index 0000000000..d4990c0c3a --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/smu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_SMU_H +#define AMD_SABRINA_SMU_H + +/* SMU mailbox register offsets in SMN */ +#define SMN_SMU_MESG_ID 0x3b10528 +#define SMN_SMU_MESG_RESP 0x3b10578 +#define SMN_SMU_MESG_ARGS_BASE 0x3b10998 + +#define SMU_NUM_ARGS 6 + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0x0b, +}; + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn gets set by the SMU. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* AMD_SABRINA_SMU_H */ diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h new file mode 100644 index 0000000000..e755d5019c --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef AMD_SABRINA_SOUTHBRIDGE_H +#define AMD_SABRINA_SOUTHBRIDGE_H + +#include + +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_ISACONTROL 0x04 +#define ABCLKGATEEN BIT(16) +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define PM_SERIRQ_CONF 0x54 +#define PM_SERIRQ_NUM_BITS_17 0x0000 +#define PM_SERIRQ_NUM_BITS_18 0x0004 +#define PM_SERIRQ_NUM_BITS_19 0x0008 +#define PM_SERIRQ_NUM_BITS_20 0x000c +#define PM_SERIRQ_NUM_BITS_21 0x0010 +#define PM_SERIRQ_NUM_BITS_22 0x0014 +#define PM_SERIRQ_NUM_BITS_23 0x0018 +#define PM_SERIRQ_NUM_BITS_24 0x001c +#define PM_SERIRQ_MODE BIT(6) +#define PM_SERIRQ_ENABLE BIT(7) +#define PM_EVT_BLK 0x60 +#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ +#define PCIEXPWAK_STS BIT(14) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TIMER_STS BIT(0) +#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TIMER_STS BIT(0) +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) +#define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) +#define PM_SPI_PAD_PU_PD 0x90 +#define PM_LPC_GATING 0xec +#define PM_LPC_AB_NO_BYPASS_EN BIT(2) +#define PM_LPC_A20_EN BIT(1) +#define PM_LPC_ENABLE BIT(0) + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ + +/* FCH MISC Registers 0xfed80e00 */ +#define GPP_CLK_CNTRL 0x00 +#define GPP_CLK0_REQ_SHIFT 0 +#define GPP_CLK1_REQ_SHIFT 2 +#define GPP_CLK4_REQ_SHIFT 4 +#define GPP_CLK2_REQ_SHIFT 6 +#define GPP_CLK3_REQ_SHIFT 8 +#define GPP_CLK5_REQ_SHIFT 10 +#define GPP_CLK6_REQ_SHIFT 12 +#define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) +#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) +#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) + +#define MISC_CLKGATEDCNTL 0x2c +#define ALINKCLK_GATEOFFEN BIT(16) +#define BLINKCLK_GATEOFFEN BIT(17) +#define XTAL_PAD_S3_TURNOFF_EN BIT(20) +#define XTAL_PAD_S5_TURNOFF_EN BIT(21) +#define MISC_CGPLL_CONFIGURATION0 0x30 +#define USB_PHY_CMCLK_S3_DIS BIT(8) +#define USB_PHY_CMCLK_S0I3_DIS BIT(9) +#define USB_PHY_CMCLK_S5_DIS BIT(10) +#define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */ +#define BP_X48M0_S0I3_DIS BIT(4) +#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ + +void fch_pre_init(void); +void fch_early_init(void); +void fch_init(void *chip_info); +void fch_final(void *chip_info); + +void enable_aoac_devices(void); +void wait_for_aoac_enabled(unsigned int dev); + +#endif /* AMD_SABRINA_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/sabrina/include/soc/uart.h b/src/soc/amd/sabrina/include/soc/uart.h new file mode 100644 index 0000000000..27e6248de5 --- /dev/null +++ b/src/soc/amd/sabrina/include/soc/uart.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_SABRINA_UART_H +#define AMD_SABRINA_UART_H + +#include + +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ +void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ + +#endif /* AMD_SABRINA_UART_H */ diff --git a/src/soc/amd/sabrina/mca.c b/src/soc/amd/sabrina/mca.c new file mode 100644 index 0000000000..b2f5e96f8b --- /dev/null +++ b/src/soc/amd/sabrina/mca.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include + +static const char *const mca_bank_name[] = { + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "L2 cache unit", + [3] = "Decode unit", + [4] = "", + [5] = "Execution unit", + [6] = "Floating point unit", + [7] = "L3 cache unit", + [8] = "L3 cache unit", + [9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "", + [16] = "", + [17] = "UMC", + [18] = "UMC", + [19] = "CS", + [20] = "CS", + [21] = "", + [22] = "", + [23] = "", + [24] = "", + [25] = "", + [26] = "", + [27] = "PIE", +}; + +bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + +bool mca_is_valid_bank(unsigned int bank) +{ + return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); +} + +const char *mca_get_bank_name(unsigned int bank) +{ + if (mca_is_valid_bank(bank)) + return mca_bank_name[bank]; + else + return ""; +} diff --git a/src/soc/amd/sabrina/preload.c b/src/soc/amd/sabrina/preload.c new file mode 100644 index 0000000000..ae3723741a --- /dev/null +++ b/src/soc/amd/sabrina/preload.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include + +static void start_fsps_preload(void *unused) +{ + preload_fsps(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL); diff --git a/src/soc/amd/sabrina/psp_verstage/Makefile.inc b/src/soc/amd/sabrina/psp_verstage/Makefile.inc new file mode 100644 index 0000000000..2338bf5e47 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/Makefile.inc @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Check if this is still correct + +verstage-generic-ccopts += -I$(src)/soc/amd/sabrina/psp_verstage/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/sabrina/include + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-y += svc.c +verstage-y += chipset.c +verstage-y += uart.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/sabrina/psp_verstage/chipset.c b/src/soc/amd/sabrina/psp_verstage/chipset.c new file mode 100644 index 0000000000..e82a132830 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/chipset.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include + +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(address, size); +} + +uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) +{ + return ef_table->bios3_entry; +} + +int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, + struct sha_generic_data *sha_op) +{ + if (hash_alg == VB2_HASH_SHA256) { + sha_op->SHAType = SHA_TYPE_256; + sha_op->DigestLen = 32; + } else if (hash_alg == VB2_HASH_SHA384) { + sha_op->SHAType = SHA_TYPE_384; + sha_op->DigestLen = 48; + } else { + return -1; + } + return 0; +} + + +/* Functions below are stub functions for not-yet-implemented PSP features. + * These functions should be replaced with proper implementations later. + */ + +uint32_t svc_write_postcode(uint32_t postcode) +{ + return 0; +} diff --git a/src/soc/amd/sabrina/psp_verstage/svc.c b/src/soc/amd/sabrina/psp_verstage/svc.c new file mode 100644 index 0000000000..bf1a106239 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/svc.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include "svc.h" + +#include +#include +#include +#include + +void svc_exit(uint32_t status) +{ + uint32_t unused = 0; + SVC_CALL0(SVC_EXIT, unused); +} + +void svc_debug_print(const char *string) +{ + uint32_t unused = 0; + SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused); +} + +void svc_debug_print_ex(uint32_t dword0, + uint32_t dword1, uint32_t dword2, uint32_t dword3) +{ + uint32_t unused = 0; + SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused); +} + +uint32_t svc_get_boot_mode(uint32_t *boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval); + return retval; +} + +void svc_delay_in_usec(uint32_t delay) +{ + uint32_t unused = 0; + SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); +} + +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); + return retval; +} + +uint32_t svc_map_fch_dev(enum fch_io_device io_device, + uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_map_spi_rom(void *spi_rom_addr, + uint32_t size, void **spi_rom_axi_addr) +{ + uint32_t retval = 0; + SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size, + (uint32_t)spi_rom_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_spi_rom(void *spi_rom_addr) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval); + return retval; +} + +uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, + uint32_t *bios_dir_offset) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset, + (uint32_t)bios_dir_offset, retval); + return retval; +} + +uint32_t svc_save_uapp_data(void *address, uint32_t size) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); + return retval; +} + +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) +{ + unsigned int retval = 0; + assert(type < PSP_TIMER_TYPE_MAX); + SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval); + return retval; +} + +uint32_t svc_reset_system(enum reset_type reset_type) +{ + unsigned int retval = 0; + assert(reset_type < RESET_TYPE_MAX); + SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval); + return retval; +} + +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval); + return retval; +} + +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); + return retval; +} + +uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) +{ + uint32_t retval = 0; + SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); + return retval; +} diff --git a/src/soc/amd/sabrina/psp_verstage/svc.h b/src/soc/amd/sabrina/psp_verstage/svc.h new file mode 100644 index 0000000000..86e533a88d --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/svc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#ifndef PSP_VERSTAGE_SVC_H +#define PSP_VERSTAGE_SVC_H + +#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "mov r3, %[reg3]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2), \ + [reg3] "r" (R3) /* input(s) */ \ + : "r0", "r1", "r2", "r3", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2) \ + : "r0", "r1", "r2", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL2(SVC_ID, R0, R1, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1)/* input(s) */ \ + : "r0", "r1", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL1(SVC_ID, R0, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0) /* input(s) */ \ + : "r0", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL0(SVC_ID, Ret) \ + __asm__ __volatile__ ( \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "I" (SVC_ID) /* input(s) */ \ + : "memory", "cc" /* list of clobbered registers */) + +#endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/soc/amd/sabrina/psp_verstage/uart.c b/src/soc/amd/sabrina/psp_verstage/uart.c new file mode 100644 index 0000000000..1c89f10c99 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/uart.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +uintptr_t get_uart_base(unsigned int idx) +{ + /* Mapping the UART is not supported. */ + return 0; +} diff --git a/src/soc/amd/sabrina/reset.c b/src/soc/amd/sabrina/reset.c new file mode 100644 index 0000000000..90fedda904 --- /dev/null +++ b/src/soc/amd/sabrina/reset.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include + +void do_cold_reset(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + /* Warm resets are not supported and must be executed as cold */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + do_cold_reset(); +} diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c new file mode 100644 index 0000000000..91f80ef4fd --- /dev/null +++ b/src/soc/amd/sabrina/romstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void car_stage_entry(void) +{ + timestamp_add_now(TS_START_ROMSTAGE); + + post_code(0x40); + + console_init(); + + post_code(0x41); + + /* Snapshot chipset state prior to any FSP call */ + fill_chipset_state(); + + fsp_memory_init(acpi_is_wakeup_s3()); + + /* Fixup settings FSP-M should not be changing */ + fch_disable_legacy_dma_io(); + + memmap_stash_early_dram_usage(); + + run_ramstage(); +} diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c new file mode 100644 index 0000000000..e73c30e040 --- /dev/null +++ b/src/soc/amd/sabrina/root_complex.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define DPTC_TOTAL_UPDATE_PARAMS 4 + +struct dptc_input { + uint16_t size; + struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; +} __packed; + +#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + }, \ + } + +/* + * + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +static void read_resources(struct device *dev) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + unsigned int idx = 0; + const struct hob_header *hob = fsp_get_hob_list(); + const struct hob_resource *res; + struct resource *gnb_apic; + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_resource(dev, idx++, 0, 0xa0000 / KiB); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_resource(dev, idx++, (1 * MiB) / KiB, + (early_reserved_dram_start - (1 * MiB)) / KiB); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, + (early_reserved_dram_end - early_reserved_dram_start) / KiB); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_resource(dev, idx++, early_reserved_dram_end / KiB, + (mem_usable - early_reserved_dram_end) / KiB); + + mmconf_resource(dev, MMIO_CONF_BASE); + + if (!hob) { + printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + __func__); + return; + } + + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = fsp_hob_header_to_resource(hob); + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) + continue; /* 0 through low usable was set above */ + if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) + continue; /* Done separately */ + + if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) + ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) + reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); + else + printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + res->type); + } + + /* GNB IOAPIC resource */ + gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic->base = GNB_IO_APIC_ADDR; + gnb_apic->size = 0x00001000; + gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); +} + +static void acipgen_dptci(void) +{ + const struct soc_amd_sabrina_config *config = config_of_soc(); + + if (!config->dptc_enable) + return; + + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); + struct dptc_input tablet_mode_input = DPTC_INPUTS( + config->thermctl_limit_tablet_mode_degreeC, + config->sustained_power_limit_tablet_mode_mW, + config->fast_ppt_limit_tablet_mode_mW, + config->slow_ppt_limit_tablet_mode_mW); + + acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), + (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); +} + +static void root_complex_fill_ssdt(const struct device *device) +{ + acpi_fill_root_complex_tom(device); + acipgen_dptci(); +} + +static const char *gnb_acpi_name(const struct device *dev) +{ + return "GNB"; +} + +static struct device_operations root_complex_operations = { + .read_resources = read_resources, + .set_resources = noop_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, + .acpi_name = gnb_acpi_name, + .acpi_fill_ssdt = root_complex_fill_ssdt, +}; + +static const struct pci_driver family17_root_complex __pci_driver = { + .ops = &root_complex_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_17H_MODEL_A0AF_NB, +}; diff --git a/src/soc/amd/sabrina/smihandler.c b/src/soc/amd/sabrina/smihandler.c new file mode 100644 index 0000000000..9fda2f9c1a --- /dev/null +++ b/src/soc/amd/sabrina/smihandler.c @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void fch_apmc_smi_handler(void) +{ + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); + + switch (cmd) { + case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); + acpi_enable_sci(); + break; + case APM_CNT_ACPI_DISABLE: + acpi_disable_sci(); + break; + case APM_CNT_ELOG_GSMI: + if (CONFIG(ELOG_GSMI)) + handle_smi_gsmi(); + break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + handle_smi_store(); + break; + case APM_CNT_SMMINFO: + psp_notify_smm(); + break; + } + + mainboard_smi_apmc(cmd); +} + +static void fch_slp_typ_handler(void) +{ + uint32_t pci_ctrl, reg32; + uint16_t pm1cnt, reg16; + uint8_t slp_typ, rst_ctrl; + + /* Figure out SLP_TYP */ + pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); + slp_typ = acpi_sleep_from_pm1(pm1cnt); + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ); + + switch (slp_typ) { + case ACPI_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case ACPI_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + break; + case ACPI_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case ACPI_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + if (slp_typ >= ACPI_S3) { + wbinvd(); + + clear_all_smi_status(); + + /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ + pci_ctrl = pm_read32(PM_PCI_CTRL); + pci_ctrl &= ~FORCE_SLPSTATE_RETRY; + pm_write32(PM_PCI_CTRL, pci_ctrl); + + /* Enable SlpTyp */ + rst_ctrl = pm_read8(PM_RST_CTRL1); + rst_ctrl |= SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, rst_ctrl); + + /* + * Before the final command, check if there's pending wake + * event. Read enable first, so that reading the actual status + * is as close as possible to entering S3. The idea is to + * minimize the opportunity for a wake event to happen before + * actually entering S3. If there's a pending wake event, log + * it and continue normal path. S3 will fail and the wake event + * becomes a SCI. + */ + if (CONFIG(ELOG_GSMI)) { + reg16 = acpi_read16(MMIO_ACPI_PM1_EN); + reg16 &= acpi_read16(MMIO_ACPI_PM1_STS); + if (reg16) + elog_add_extended_event( + ELOG_SLEEP_PENDING_PM1_WAKE, + (u32)reg16); + + reg32 = acpi_read32(MMIO_ACPI_GPE0_EN); + reg32 &= acpi_read32(MMIO_ACPI_GPE0_STS); + if (reg32) + elog_add_extended_event( + ELOG_SLEEP_PENDING_GPE0_WAKE, + reg32); + } /* if (CONFIG(ELOG_GSMI)) */ + + if (slp_typ == ACPI_S3) + psp_notify_sx_info(ACPI_S3); + + smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ + printk(BIOS_ERR, "Error: System did not go to sleep\n"); + hlt(); + } +} + +int southbridge_io_trap_handler(int smif) +{ + return 0; +} + +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in fch.c is unrelated to this list. + */ +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +}; + +void *get_smi_source_handler(int source) +{ + size_t i; + + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + + return NULL; +} diff --git a/src/soc/amd/sabrina/smu.c b/src/soc/amd/sabrina/smu.c new file mode 100644 index 0000000000..1496957117 --- /dev/null +++ b/src/soc/amd/sabrina/smu.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn gets set by the SMU. Function does not return if successful. + */ +void smu_sx_entry(void) +{ + struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ + + printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); + send_smu_message(SMC_MSG_S3ENTRY, &msg); +} diff --git a/src/soc/amd/sabrina/uart.c b/src/soc/amd/sabrina/uart.c new file mode 100644 index 0000000000..0ffdacf792 --- /dev/null +++ b/src/soc/amd/sabrina/uart.c @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct { + uintptr_t base; + struct soc_amd_gpio mux[2]; +} uart_info[] = { + [0] = { APU_UART0_BASE, { + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, { + PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), + PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), + } }, + [2] = { APU_UART2_BASE, { + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + } }, + [3] = { APU_UART3_BASE, { + PAD_NF(GPIO_135, UART3_TXD, PULL_NONE), + PAD_NF(GPIO_137, UART3_RXD, PULL_NONE), + } }, + [4] = { APU_UART4_BASE, { + PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), + PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), + } }, +}; + +uintptr_t get_uart_base(unsigned int idx) +{ + if (idx >= ARRAY_SIZE(uart_info)) + return 0; + + return uart_info[idx].base; +} + +void clear_uart_legacy_config(void) +{ + write16((void *)FCH_LEGACY_UART_DECODE, 0); +} + +void set_uart_config(unsigned int idx) +{ + if (idx >= ARRAY_SIZE(uart_info)) + return; + + gpio_configure_pads(uart_info[idx].mux, 2); +} + +static const char *uart_acpi_name(const struct device *dev) +{ + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + return "FUR0"; + case APU_UART1_BASE: + return "FUR1"; + case APU_UART2_BASE: + return "FUR2"; + case APU_UART3_BASE: + return "FUR3"; + case APU_UART4_BASE: + return "FUR4"; + default: + return NULL; + } +} + +/* Even though this is called enable, it gets called for both enabled and disabled devices. */ +static void uart_enable(struct device *dev) +{ + unsigned int dev_id; + + switch (dev->path.mmio.addr) { + case APU_UART0_BASE: + dev_id = FCH_AOAC_DEV_UART0; + break; + case APU_UART1_BASE: + dev_id = FCH_AOAC_DEV_UART1; + break; + case APU_UART2_BASE: + dev_id = FCH_AOAC_DEV_UART2; + break; + case APU_UART3_BASE: + dev_id = FCH_AOAC_DEV_UART3; + break; + case APU_UART4_BASE: + dev_id = FCH_AOAC_DEV_UART4; + break; + default: + printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); + return; + } + + if (dev->enabled) { + power_on_aoac_device(dev_id); + wait_for_aoac_enabled(dev_id); + } else { + power_off_aoac_device(dev_id); + } +} + +static void uart_read_resources(struct device *dev) +{ + mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); +} + +struct device_operations sabrina_uart_mmio_ops = { + .read_resources = uart_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .enable = uart_enable, + .acpi_name = uart_acpi_name, + .acpi_fill_ssdt = uart_inject_ssdt, +}; diff --git a/src/soc/amd/sabrina/xhci.c b/src/soc/amd/sabrina/xhci.c new file mode 100644 index 0000000000..c95b5f91e3 --- /dev/null +++ b/src/soc/amd/sabrina/xhci.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Check if this is still correct */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct sci_source xhci_sci_sources[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = GEVENT_31, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + +enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe) +{ + if (dev->bus->dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN) + return CB_ERR_ARG; + + if (dev->path.type != DEVICE_PATH_PCI) + return CB_ERR_ARG; + + if (dev->path.pci.devfn == XHCI0_DEVFN) + *gpe = xhci_sci_sources[0].gpe; + else if (dev->path.pci.devfn == XHCI1_DEVFN) + *gpe = xhci_sci_sources[1].gpe; + else + return CB_ERR_ARG; + + return CB_SUCCESS; +} + +static void configure_xhci_sci(void *unused) +{ + gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources)); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL); diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 36eecb122f..769a61533b 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_AOAC @@ -108,10 +109,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config CPU_ADDR_BITS - int - default 48 - config BOTTOMIO_POSITION hex "Bottom of 32-bit IO space" default 0xD0000000 @@ -124,10 +121,10 @@ config BOTTOMIO_POSITION option is useful when PCI peripherals requesting large address ranges are present. -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER default 64 config VGA_BIOS_ID diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index fd3ebf7a66..b2ac43f40b 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -4,27 +4,28 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ +bootblock-y += aoac.c bootblock-y += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock.c +bootblock-y += early_fch.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += tsc_freq.c -bootblock-y += southbridge.c romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c romstage-y += enable_usbdebug.c +romstage-y += fch_agesa.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-y += uart.c romstage-y += tsc_freq.c -romstage-y += southbridge.c romstage-y += psp.c verstage-y += gpio.c @@ -46,9 +47,10 @@ ramstage-y += cpu.c ramstage-y += mca.c ramstage-y += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += fch.c +ramstage-y += fch_agesa.c ramstage-y += gpio.c ramstage-y += monotonic_timer.c -ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += sata.c ramstage-y += memmap.c @@ -66,7 +68,6 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c -CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/acpi @@ -123,6 +124,7 @@ endif ifeq ($(FIRMWARE_TYPE),ST) OPT_COMBOCAPABLE=--combo-capable +OPT_SOCNAME=--soc-name "Stoneyridge" endif ifeq ($(CONFIG_USE_PSPSECUREOS),y) @@ -131,6 +133,9 @@ endif OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -146,7 +151,10 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ $(OPT_COMBOCAPABLE)\ $(OPT_PSP_USE_PSPSECUREOS) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ + $(OPT_SOCNAME) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ --output $@ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index b2de89e016..4c3b6254fd 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -4,7 +4,6 @@ * ACPI - create the Fixed ACPI Description Tables (FADT) */ -#include #include #include #include @@ -84,7 +83,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0x0d; + fadt->day_alrm = RTC_DATE_ALARM; fadt->mon_alrm = 0; /* Not supported */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ @@ -98,8 +97,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; @@ -157,103 +155,3 @@ void generate_cpu_entries(const struct device *device) acpigen_write_name_integer("PCNT", cores); acpigen_pop_len(); } - -static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) -{ - /* - * Store (\_SB.GPR2 (addr), Local5) - * \_SB.GPR2 is used to read control byte 2 from control register. - * / It is defined in gpio_lib.asl. - */ - acpigen_write_store(); - acpigen_emit_namestring("\\_SB.GPR2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); -} - -static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - acpigen_soc_get_gpio_in_local5(addr); - - /* If (And (Local5, mask)) */ - acpigen_write_if_and(LOCAL5_OP, mask); - - /* Store (One, Local0) */ - acpigen_write_store_ops(ONE_OP, LOCAL0_OP); - - /* Else */ - acpigen_write_else(); - - /* Store (Zero, Local0) */ - acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); - - acpigen_pop_len(); /* Else */ - - return 0; -} - -static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ - acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); - acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * \_SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 1); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 0); -} diff --git a/src/soc/amd/stoneyridge/aoac.c b/src/soc/amd/stoneyridge/aoac.c new file mode 100644 index 0000000000..7c1d12ddc1 --- /dev/null +++ b/src/soc/amd/stoneyridge/aoac.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* + * Table of devices that need their AOAC registers enabled and waited + * upon (usually about .55 milliseconds). Instead of individual delays + * waiting for each device to become available, a single delay will be + * executed. + */ +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, +}; + +void enable_aoac_devices(void) +{ + bool status; + int i; + + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + power_on_aoac_device(aoac_devs[i]); + + /* Wait for AOAC devices to indicate power and clock OK */ + do { + udelay(100); + status = true; + for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) + status &= is_aoac_device_enabled(aoac_devs[i]); + } while (!status); +} diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 5cc52b6926..666deda7d4 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -131,7 +131,6 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { fch_init(chip_info); - setup_bsp_ramtop(); } static void soc_final(void *chip_info) diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index b870baeb88..bee82af4ce 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 99b40a6131..3cd3a9580a 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -39,8 +38,7 @@ static void pre_mp_init(void) static int get_cpu_count(void) { - return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) - + 1; + return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; } static const struct mp_ops mp_ops = { @@ -53,9 +51,9 @@ static const struct mp_ops mp_ops = { void mp_init_cpus(struct bus *cpu_bus) { - /* Clear for take-off */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &mp_ops); + if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) + die_with_post_code(POST_HW_INIT_FAILURE, + "mp_init_with_smm failed. Halting.\n"); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); @@ -66,7 +64,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void model_15_init(struct device *dev) { check_mca(); - setup_lapic(); /* * Per AMD, sync an undocumented MSR with the PSP base address. diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c new file mode 100644 index 0000000000..1f038f61f1 --- /dev/null +++ b/src/soc/amd/stoneyridge/early_fch.c @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void sb_enable_lpc(void) +{ + u8 byte; + + /* Enable LPC controller */ + byte = pm_io_read8(PM_LPC_GATING); + byte |= PM_LPC_ENABLE; + pm_io_write8(PM_LPC_GATING, byte); +} + +static void sb_lpc_decode(void) +{ + u32 tmp = 0; + + /* Enable I/O decode to LPC bus */ + tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 + | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 + | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 + | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 + | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 + | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 + | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 + | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 + | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT + | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT + | DECODE_ENABLE_ADLIB_PORT; + + /* Decode SIOs at 2E/2F and 4E/4F */ + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; + + lpc_enable_decode(tmp); +} + +static void setup_spread_spectrum(int *reboot) +{ + uint16_t rstcfg = pm_read16(PWR_RESET_CFG); + + rstcfg &= ~TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); + + if (cntl1 & CG1PLL_FBDIV_TEST) { + printk(BIOS_DEBUG, "Spread spectrum is ready\n"); + misc_write32(MISC_CGPLL_CONFIG1, + misc_read32(MISC_CGPLL_CONFIG1) | + CG1PLL_SPREAD_SPECTRUM_ENABLE); + + return; + } + + printk(BIOS_DEBUG, "Setting up spread spectrum\n"); + + uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); + cfg6 &= ~CG1PLL_LF_MODE_MASK; + cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; + misc_write32(MISC_CGPLL_CONFIG6, cfg6); + + uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); + cfg3 &= ~CG1PLL_REFDIV_MASK; + cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; + cfg3 &= ~CG1PLL_FBDIV_MASK; + cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; + misc_write32(MISC_CGPLL_CONFIG3, cfg3); + + uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); + cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; + misc_write32(MISC_CGPLL_CONFIG5, cfg5); + + uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); + cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) + & SS_STEP_SIZE_DSFRAC_MASK; + misc_write32(MISC_CGPLL_CONFIG4, cfg4); + + rstcfg |= TOGGLE_ALL_PWR_GOOD; + pm_write16(PWR_RESET_CFG, rstcfg); + + cntl1 |= CG1PLL_FBDIV_TEST; + misc_write32(MISC_CLK_CNTL1, cntl1); + + *reboot = 1; +} + +static void setup_misc(int *reboot) +{ + /* Undocumented register */ + uint32_t reg = misc_read32(0x50); + if (!(reg & BIT(16))) { + reg |= BIT(16); + + misc_write32(0x50, reg); + *reboot = 1; + } +} + +/* Before console init */ +void bootblock_fch_early_init(void) +{ + int reboot = 0; + + /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access + the GPIO registers. */ + enable_acpimmio_decode_pm04(); + lpc_enable_rom(); + sb_enable_lpc(); + lpc_enable_port80(); + sb_lpc_decode(); + /* Make sure the base address is predictable */ + lpc_set_spibase(SPI_BASE_ADDRESS); + fch_spi_early_init(); + fch_smbus_init(); + fch_enable_cf9_io(); + setup_spread_spectrum(&reboot); + setup_misc(&reboot); + + if (reboot) + warm_reset(); + + fch_enable_legacy_io(); + enable_aoac_devices(); + + /* disable the keyboard reset function before mainboard GPIO setup */ + if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) + fch_disable_kb_rst(); +} + +/* After console init */ +void bootblock_fch_init(void) +{ + pm_set_power_failure_state(); + fch_print_pmxc0_status(); + show_spi_speeds_and_modes(); +} + +void fch_clk_output_48Mhz(u32 osc) +{ + u32 ctrl; + + /* + * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) + * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. + */ + ctrl = misc_read32(MISC_CLK_CNTL1); + + switch (osc) { + case 1: + ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; + break; + case 2: + ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; + break; + default: + return; /* do nothing if invalid */ + } + misc_write32(MISC_CLK_CNTL1, ctrl); +} diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c new file mode 100644 index 0000000000..e793e1b380 --- /dev/null +++ b/src/soc/amd/stoneyridge/fch.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +static const struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_MISC1, "Misc1" }, + { PIRQ_MISC2, "Misc2" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_HDA, "HDA" }, + { PIRQ_FC, "FC" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SD, "SD" }, + { PIRQ_SDIO, "SDIOt" }, + { PIRQ_EHCI, "EHCI" }, + { PIRQ_XHCI, "XHCI" }, + { PIRQ_SATA, "SATA" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void fch_init_acpi_ports(void) +{ + u32 reg; + + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_SB.CP00, 6 bytes */ + pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* APMC - SMI Command Port */ + pm_write16(PM_ACPI_SMI_CMD, APM_CNT); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); + + /* SMI on SlpTyp requires sending SMI before completion + * response of the I/O write. The BKDG also specifies + * clearing ForceStpClkRetry for SMI trapping. + */ + reg = pm_read32(PM_PCI_CTRL); + reg |= FORCE_SLPSTATE_RETRY; + reg &= ~FORCE_STPCLK_RETRY; + pm_write32(PM_PCI_CTRL, reg); + + /* Disable SlpTyp feature */ + reg = pm_read8(PM_RST_CTRL1); + reg &= ~SLPTYPE_CONTROL_EN; + pm_write8(PM_RST_CTRL1, reg); + + configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* Decode ACPI registers and enable standard features */ + pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | + PM_ACPI_GLOBAL_EN | + PM_ACPI_RTC_EN_EN | + PM_ACPI_TIMER_EN_EN); +} + +void fch_init(void *chip_info) +{ + fch_init_acpi_ports(); +} + +static void set_sb_aoac(struct aoac_devs *aoac) +{ + const struct device *sd, *sata; + + aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); + + /* Rely on these being in sync with devicetree */ + sd = pcidev_path_on_root(SD_DEVFN); + aoac->sd_e = sd && sd->enabled ? 1 : 0; + sata = pcidev_path_on_root(SATA_DEVFN); + aoac->st_e = sata && sata->enabled ? 1 : 0; + aoac->espi = 1; +} + +static void set_sb_gnvs(struct global_nvs *gnvs) +{ + uintptr_t amdfw_rom; + uintptr_t xhci_fw; + uintptr_t fwaddr; + size_t fwsize; + + amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); + xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + + fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + + XHCI_FW_BOOTRAM_SIZE)); + gnvs->fw00 = 0; + gnvs->fw01 = ((32 * KiB) << 16) + 0; + gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; + gnvs->fw03 = fwsize << 16; + + /* TODO: This might break if the OS decides to re-allocate the PCI BARs. */ + gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) + & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + +void fch_final(void *chip_info) +{ + /* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */ + struct global_nvs *gnvs = acpi_get_gnvs(); + if (gnvs) { + set_sb_aoac(&gnvs->aoac); + set_sb_gnvs(gnvs); + } +} + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/stoneyridge/fch_agesa.c b/src/soc/amd/stoneyridge/fch_agesa.c new file mode 100644 index 0000000000..ee6ab91c6d --- /dev/null +++ b/src/soc/amd/stoneyridge/fch_agesa.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static int is_sata_config(void) +{ + return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) + || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); +} + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); +} + +void SetFchResetParams(FCH_RESET_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); + if (dev && dev->enabled) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } +} + +void SetFchEnvParams(FCH_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->AzaliaController = AzEnable; + params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + if (dev && dev->enabled) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } +} + +void SetFchMidParams(FCH_INTERFACE *params) +{ + SetFchEnvParams(params); +} diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 6a6d7760fc..e589b04f78 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -5,6 +5,7 @@ #include #include #include "chip.h" +#include static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" }, @@ -26,3 +27,8 @@ const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses) *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) +{ + /* Do nothing. */ +} diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index f0c35c070c..21ffd5fbdc 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -12,6 +12,9 @@ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) #endif +/* RTC Registers */ +#define RTC_DATE_ALARM 0x0d + const char *soc_acpi_name(const struct device *dev); #endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 93e218df97..76e6e778e2 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -16,11 +16,6 @@ #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 6af657feb3..4e5c8fc07c 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -6,17 +6,15 @@ #include #include -/* GNB Root Complex */ +/* GNB Root Complex: GNB_DEVID 0x1576 */ #define GNB_DEV 0x0 #define GNB_FUNC 0 -#define GNB_DEVID 0x1576 #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) #define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) -/* IOMMU */ +/* IOMMU: IOMMU_DEVID 0x1577 */ #define IOMMU_DEV 0x0 #define IOMMU_FUNC 2 -#define IOMMU_DEVID 0x1577 #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) @@ -41,59 +39,51 @@ #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* Host Bridge */ +/* Host Bridge: HOST_DEVID 0x157b */ #define HOST_DEV 0x2 #define HOST_FUNC 0 -#define HOST_DEVID 0x157b #define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) #define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) -/* PCIe GPP Bridge 0 */ +/* PCIe GPP Bridge 0: PCIE0_DEVID 0x157c */ #define PCIE0_DEV 0x2 #define PCIE0_FUNC 1 -#define PCIE0_DEVID 0x157c #define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) #define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) -/* PCIe GPP Bridge 1 */ +/* PCIe GPP Bridge 1: PCIE1_DEVID 0x157c */ #define PCIE1_DEV 0x2 #define PCIE1_FUNC 2 -#define PCIE1_DEVID 0x157c #define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) #define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) -/* PCIe GPP Bridge 2 */ +/* PCIe GPP Bridge 2: PCIE2_DEVID 0x157c */ #define PCIE2_DEV 0x2 #define PCIE2_FUNC 3 -#define PCIE2_DEVID 0x157c #define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) #define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) -/* PCIe GPP Bridge 3 */ +/* PCIe GPP Bridge 3: PCIE3_DEVID 0x157c */ #define PCIE3_DEV 0x2 #define PCIE3_FUNC 4 -#define PCIE3_DEVID 0x157c #define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) #define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) -/* PCIe GPP Bridge 4 */ +/* PCIe GPP Bridge 4: PCIE4_DEVID 0x157c */ #define PCIE4_DEV 0x2 #define PCIE4_FUNC 5 -#define PCIE4_DEVID 0x157c #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) #define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) -/* Platform Security Processor */ +/* Platform Security Processor: PSP_DEVID 0x1578 */ #define PSP_DEV 0x8 #define PSP_FUNC 0 -#define PSP_DEVID 0x1578 #define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) #define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) -/* HD Audio 1 */ +/* HD Audio 1: HDA1_DEVID 0x157a */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) @@ -157,47 +147,44 @@ #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) -/* XHCI */ +/* XHCI: XHCI_DEVID 0x7914 */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x7914 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) #define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) -/* SATA */ +/* + * SATA: + * SATA_IDE_IDEVID 0x7900 + * AHCI_DEVID_MS 0x7901 + * AHCI_DEVID_AMD 0x7904 + */ #define SATA_DEV 0x11 #define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) -/* EHCI */ +/* EHCI: EHCI_DEVID 0x7908 */ #define EHCI_DEV 0x12 #define EHCI_FUNC 0 -#define EHCI_DEVID 0x7908 #define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) #define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) -/* SMBUS */ +/* SMBUS: SMBUS_DEVID 0x790b */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x790b #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) -/* LPC BUS */ +/* LPC BUS: LPC_DEVID 0x790e */ #define PCU_DEV 0x14 #define LPC_FUNC 3 -#define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -/* SD Controller */ +/* SD Controller: SD_DEVID 0x7906 */ #define SD_DEV 0x14 #define SD_FUNC 7 -#define SD_DEVID 0x7906 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 61624755c5..3ce41df40c 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -4,8 +4,9 @@ #define AMD_STONEYRIDGE_SMI_H #define SMI_GEVENTS 24 -#define SCIMAPS 58 +#define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 +#define NUMBER_SMITYPES 160 #define SMI_EVENT_STATUS 0x0 #define SMI_EVENT_ENABLE 0x04 @@ -138,7 +139,7 @@ /* 153-155 Reserved */ #define SMITYPE_CFGTRAP0 156 /* 157-159 Reserved */ -#define NUMBER_SMITYPES 160 + #define TYPE_TO_MASK(X) (1 << (X) % 32) #define SMI_REG_SMISTS0 0x80 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 97eb806682..e00bf8ef3e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -7,7 +7,6 @@ #include #include #include -#include "chip.h" /* * AcpiMmio Region @@ -142,46 +141,10 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -#define SPI_CNTRL0 0x00 -#define SPI_BUSY BIT(31) -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -/* Nominal is 16.7MHz on older devices, 33MHz on newer */ -#define SPI_READ_MODE_NOM 0x00000000 -#define SPI_READ_MODE_DUAL112 ( BIT(29) ) -#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) -#define SPI_READ_MODE_DUAL122 (BIT(30) ) -#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) -#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) -#define SPI_ACCESS_MAC_ROM_EN BIT(22) -#define SPI_FIFO_PTR_CLR BIT(20) -#define SPI_ARB_ENABLE BIT(19) -#define EXEC_OPCODE BIT(16) - -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI100_SPEED_CONFIG 0x22 -#define SPI_SPEED_66M (0x0) -#define SPI_SPEED_33M ( BIT(0)) -#define SPI_SPEED_22M ( BIT(1) ) -#define SPI_SPEED_16M ( BIT(1) | BIT(0)) -#define SPI_SPEED_100M (BIT(2) ) -#define SPI_SPEED_800K (BIT(2) | BIT(0)) -#define SPI_NORM_SPEED_NEW_SH 12 -#define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 -#define SPI_TPM_SPEED_NEW_SH 0 - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - /* Platform Security Processor D8F0 */ void soc_enable_psp_early(void); #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ #define PSP_BAR_ENABLES 0x48 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ @@ -220,8 +183,6 @@ void fch_final(void *chip_info); void enable_aoac_devices(void); void fch_clk_output_48Mhz(u32 osc); -void sb_read_mode(u32 mode); -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); /* * Call the mainboard to get the USB Over Current Map. The mainboard diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 9da3e6522c..06f80de666 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d5231ad5d5..04472dc3b5 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -332,7 +333,7 @@ static const struct pci_driver family15_northbridge __pci_driver = { */ void amd_initcpuio(void) { - uintptr_t topmem = bsp_topmem(); + uintptr_t topmem = amd_topmem(); uintptr_t base, limit; /* Enable legacy video routing: D18F1xF4 VGA Enable */ diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index 8d6290f619..0941b0e543 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include -#include -#include #include #include #include @@ -30,30 +28,3 @@ void soc_enable_psp_early(void) cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); }; - -void *soc_get_mbox_address(void) -{ - uintptr_t psp_mmio; - - /* Check for presence of the PSP */ - if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { - printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", - PSP_DEV, PSP_FUNC); - return 0; - } - - /* Determine if Bar3Hide has been set, and if hidden get the base from - * the MSR instead. */ - if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { - psp_mmio = rdmsr(PSP_ADDR_MSR).lo; - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); - return 0; - } - } else { - psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & - ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - } - - return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); -} diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index e316d2166a..8ac2eb5a04 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -151,7 +151,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams) const struct device *dev = pcidev_path_on_root(GNB_DEVFN); if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); + printk(BIOS_ERR, "Cannot find SoC devicetree config\n"); /* In case of a BIOS error, only attempt to set UMA. */ PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; @@ -189,7 +189,7 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) struct _PLATFORM_CONFIGURATION *platform; if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" + printk(BIOS_WARNING, "Cannot find SoC devicetree" " config, STAPM unchanged\n"); return; } @@ -214,6 +214,5 @@ static void migrate_power_state(int is_recovery) acpi_fill_pm_gpe_state(&state->gpe_state); acpi_pm_gpe_add_events_print_events(); } - acpi_clear_pm_gpe_status(); } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index f9c4a5450a..50a5111461 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -21,6 +21,7 @@ static void fch_apmc_smi_handler(void) switch (cmd) { case APM_CNT_ACPI_ENABLE: + acpi_clear_pm_gpe_status(); acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c deleted file mode 100644 index de27ac540a..0000000000 --- a/src/soc/amd/stoneyridge/southbridge.c +++ /dev/null @@ -1,486 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Table of devices that need their AOAC registers enabled and waited - * upon (usually about .55 milliseconds). Instead of individual delays - * waiting for each device to become available, a single delay will be - * executed. - */ -static const unsigned int aoac_devs[] = { - FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, - FCH_AOAC_DEV_AMBA, - FCH_AOAC_DEV_I2C0, - FCH_AOAC_DEV_I2C1, - FCH_AOAC_DEV_I2C2, - FCH_AOAC_DEV_I2C3, -}; - -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) - || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || - (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - -/* - * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME - * provides a visible association with the index, therefore helping - * maintainability of table. If a new index/name is defined in - * amd_pci_int_defs.h, just add the pair at the end of this table. - * Order is not important. - */ -static const struct irq_idx_name irq_association[] = { - { PIRQ_A, "INTA#" }, - { PIRQ_B, "INTB#" }, - { PIRQ_C, "INTC#" }, - { PIRQ_D, "INTD#" }, - { PIRQ_E, "INTE#" }, - { PIRQ_F, "INTF#" }, - { PIRQ_G, "INTG#" }, - { PIRQ_H, "INTH#" }, - { PIRQ_MISC, "Misc" }, - { PIRQ_MISC0, "Misc0" }, - { PIRQ_MISC1, "Misc1" }, - { PIRQ_MISC2, "Misc2" }, - { PIRQ_SIRQA, "Ser IRQ INTA" }, - { PIRQ_SIRQB, "Ser IRQ INTB" }, - { PIRQ_SIRQC, "Ser IRQ INTC" }, - { PIRQ_SIRQD, "Ser IRQ INTD" }, - { PIRQ_SCI, "SCI" }, - { PIRQ_SMBUS, "SMBUS" }, - { PIRQ_ASF, "ASF" }, - { PIRQ_HDA, "HDA" }, - { PIRQ_FC, "FC" }, - { PIRQ_PMON, "PerMon" }, - { PIRQ_SD, "SD" }, - { PIRQ_SDIO, "SDIOt" }, - { PIRQ_EHCI, "EHCI" }, - { PIRQ_XHCI, "XHCI" }, - { PIRQ_SATA, "SATA" }, - { PIRQ_GPIO, "GPIO" }, - { PIRQ_I2C0, "I2C0" }, - { PIRQ_I2C1, "I2C1" }, - { PIRQ_I2C2, "I2C2" }, - { PIRQ_I2C3, "I2C3" }, - { PIRQ_UART0, "UART0" }, - { PIRQ_UART1, "UART1" }, -}; - -const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) -{ - *size = ARRAY_SIZE(irq_association); - return irq_association; -} - -void enable_aoac_devices(void) -{ - bool status; - int i; - - for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i]); - - /* Wait for AOAC devices to indicate power and clock OK */ - do { - udelay(100); - status = true; - for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i]); - } while (!status); -} - -static void sb_enable_lpc(void) -{ - u8 byte; - - /* Enable LPC controller */ - byte = pm_io_read8(PM_LPC_GATING); - byte |= PM_LPC_ENABLE; - pm_io_write8(PM_LPC_GATING, byte); -} - -static void sb_lpc_decode(void) -{ - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; - - /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(STONEYRIDGE_LEGACY_FREE)) - tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - - lpc_enable_decode(tmp); -} - -void fch_clk_output_48Mhz(u32 osc) -{ - u32 ctrl; - - /* - * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) - * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. - */ - ctrl = misc_read32(MISC_CLK_CNTL1); - - switch (osc) { - case 1: - ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; - break; - case 2: - ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; - break; - default: - return; /* do nothing if invalid */ - } - misc_write32(MISC_CLK_CNTL1, ctrl); -} - -static void sb_init_spi_base(void) -{ - /* Make sure the base address is predictable */ - if (ENV_X86) - lpc_set_spibase(SPI_BASE_ADDRESS); - lpc_enable_spi_rom(SPI_ROM_ENABLE); -} - -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) -{ - spi_write16(SPI100_SPEED_CONFIG, - (norm << SPI_NORM_SPEED_NEW_SH) | - (fast << SPI_FAST_SPEED_NEW_SH) | - (alt << SPI_ALT_SPEED_NEW_SH) | - (tpm << SPI_TPM_SPEED_NEW_SH)); - spi_write16(SPI100_ENABLE, SPI_USE_SPI100); -} - -static void sb_disable_4dw_burst(void) -{ - spi_write16(SPI100_HOST_PREF_CONFIG, - spi_read16(SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); -} - -void sb_read_mode(u32 mode) -{ - spi_write32(SPI_CNTRL0, - (spi_read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); -} - -static void setup_spread_spectrum(int *reboot) -{ - uint16_t rstcfg = pm_read16(PWR_RESET_CFG); - - rstcfg &= ~TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); - - if (cntl1 & CG1PLL_FBDIV_TEST) { - printk(BIOS_DEBUG, "Spread spectrum is ready\n"); - misc_write32(MISC_CGPLL_CONFIG1, - misc_read32(MISC_CGPLL_CONFIG1) | - CG1PLL_SPREAD_SPECTRUM_ENABLE); - - return; - } - - printk(BIOS_DEBUG, "Setting up spread spectrum\n"); - - uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); - cfg6 &= ~CG1PLL_LF_MODE_MASK; - cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; - misc_write32(MISC_CGPLL_CONFIG6, cfg6); - - uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); - cfg3 &= ~CG1PLL_REFDIV_MASK; - cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; - cfg3 &= ~CG1PLL_FBDIV_MASK; - cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; - misc_write32(MISC_CGPLL_CONFIG3, cfg3); - - uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; - misc_write32(MISC_CGPLL_CONFIG5, cfg5); - - uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) - & SS_STEP_SIZE_DSFRAC_MASK; - misc_write32(MISC_CGPLL_CONFIG4, cfg4); - - rstcfg |= TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - cntl1 |= CG1PLL_FBDIV_TEST; - misc_write32(MISC_CLK_CNTL1, cntl1); - - *reboot = 1; -} - -static void setup_misc(int *reboot) -{ - /* Undocumented register */ - uint32_t reg = misc_read32(0x50); - if (!(reg & BIT(16))) { - reg |= BIT(16); - - misc_write32(0x50, reg); - *reboot = 1; - } -} - -/* Before console init */ -void bootblock_fch_early_init(void) -{ - int reboot = 0; - - /* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access - the GPIO registers. */ - enable_acpimmio_decode_pm04(); - lpc_enable_rom(); - sb_enable_lpc(); - lpc_enable_port80(); - sb_lpc_decode(); - lpc_enable_spi_prefetch(); - sb_init_spi_base(); - sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ - fch_smbus_init(); - fch_enable_cf9_io(); - setup_spread_spectrum(&reboot); - setup_misc(&reboot); - - if (reboot) - warm_reset(); - - fch_enable_legacy_io(); - enable_aoac_devices(); - - /* disable the keyboard reset function before mainboard GPIO setup */ - if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) - fch_disable_kb_rst(); -} - -/* After console init */ -void bootblock_fch_init(void) -{ - pm_set_power_failure_state(); - fch_print_pmxc0_status(); - show_spi_speeds_and_modes(); -} - -static void fch_init_acpi_ports(void) -{ - u32 reg; - - /* We use some of these ports in SMM regardless of whether or not - * ACPI tables are generated. Enable these ports indiscriminately. - */ - - pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); - pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); - pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); - pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_SB.CP00, 6 bytes */ - pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - - if (CONFIG(HAVE_SMI_HANDLER)) { - /* APMC - SMI Command Port */ - pm_write16(PM_ACPI_SMI_CMD, APM_CNT); - configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); - - /* SMI on SlpTyp requires sending SMI before completion - * response of the I/O write. The BKDG also specifies - * clearing ForceStpClkRetry for SMI trapping. - */ - reg = pm_read32(PM_PCI_CTRL); - reg |= FORCE_SLPSTATE_RETRY; - reg &= ~FORCE_STPCLK_RETRY; - pm_write32(PM_PCI_CTRL, reg); - - /* Disable SlpTyp feature */ - reg = pm_read8(PM_RST_CTRL1); - reg &= ~SLPTYPE_CONTROL_EN; - pm_write8(PM_RST_CTRL1, reg); - - configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); - } else { - pm_write16(PM_ACPI_SMI_CMD, 0); - } - - /* Decode ACPI registers and enable standard features */ - pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | - PM_ACPI_GLOBAL_EN | - PM_ACPI_RTC_EN_EN | - PM_ACPI_TIMER_EN_EN); -} - -void fch_init(void *chip_info) -{ - fch_init_acpi_ports(); -} - -static void set_sb_aoac(struct aoac_devs *aoac) -{ - const struct device *sd, *sata; - - aoac->ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); - aoac->ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); - aoac->ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); - aoac->ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); - aoac->ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); - aoac->ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - aoac->ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); - aoac->xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); - - /* Rely on these being in sync with devicetree */ - sd = pcidev_path_on_root(SD_DEVFN); - aoac->sd_e = sd && sd->enabled ? 1 : 0; - sata = pcidev_path_on_root(SATA_DEVFN); - aoac->st_e = sata && sata->enabled ? 1 : 0; - aoac->espi = 1; -} - -static void set_sb_gnvs(struct global_nvs *gnvs) -{ - uintptr_t amdfw_rom; - uintptr_t xhci_fw; - uintptr_t fwaddr; - size_t fwsize; - - amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); - - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET - + XHCI_FW_BOOTRAM_SIZE)); - gnvs->fw00 = 0; - gnvs->fw01 = ((32 * KiB) << 16) + 0; - gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; - gnvs->fw03 = fwsize << 16; - - gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) - & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; -} - -void fch_final(void *chip_info) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs) { - set_sb_aoac(&gnvs->aoac); - set_sb_gnvs(gnvs); - } -} - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 87edf45cde..368581f8f1 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -9,7 +9,7 @@ config SOC_CAVIUM_CN81XX select UART_OVERRIDE_REFCLK select SOC_CAVIUM_COMMON select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS - select MMCONF_SUPPORT + select ECAM_MMCONF_SUPPORT select PCI if SOC_CAVIUM_CN81XX @@ -36,7 +36,7 @@ config HEAP_SIZE config STACK_SIZE default 0x2000 -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0x848000000000 endif diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 0dd6ce4dc4..bb85029783 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -97,7 +97,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) } while (!stopwatch_expired(&sw) && (pending & coremask)); if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, "ERROR: Timeout waiting for reset " + printk(BIOS_ERR, "Timeout waiting for reset " "pending to clear."); return 1; } @@ -113,7 +113,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) dmb(); if (!read64(&secondary_booted)) { - printk(BIOS_ERR, "ERROR: Core %zu failed to start.\n", cpu); + printk(BIOS_ERR, "Core %zu failed to start.\n", cpu); return 1; } diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index 943e1c9ed6..e789fd8db1 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -163,7 +163,7 @@ static size_t ecam0_pci_enable_msix(struct device *dev, } nr_entries = pci_msix_table_size(dev); if (nvec > nr_entries) { - printk(BIOS_ERR, "ERROR: %s: Specified to many table entries\n", + printk(BIOS_ERR, "%s: Specified to many table entries\n", dev_path(dev)); return nr_entries; } @@ -177,13 +177,13 @@ static size_t ecam0_pci_enable_msix(struct device *dev, offset = 0; bar_idx = 0; if (pci_msix_table_bar(dev, &offset, &bar_idx)) { - printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X entry\n", + printk(BIOS_ERR, "%s: Failed to find MSI-X entry\n", dev_path(dev)); return -1; } bar = ecam0_get_bar_val(dev, bar_idx); if (!bar) { - printk(BIOS_ERR, "ERROR: %s: Failed to find MSI-X bar\n", + printk(BIOS_ERR, "%s: Failed to find MSI-X bar\n", dev_path(dev)); return -1; } diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig index 660bf369e7..d1767523dd 100644 --- a/src/soc/example/min86/Kconfig +++ b/src/soc/example/min86/Kconfig @@ -16,7 +16,7 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ARCH_X86 select NO_MONOTONIC_TIMER - select NO_MMCONF_SUPPORT + select NO_ECAM_MMCONF_SUPPORT select UNKNOWN_TSC_RATE config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld diff --git a/src/soc/intel/alderlake/acpi/scs.asl b/src/soc/intel/alderlake/acpi/scs.asl new file mode 100644 index 0000000000..aac78e8fcc --- /dev/null +++ b/src/soc/intel/alderlake/acpi/scs.asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define PMCR_D0_MASK 0xFFFC +#define PMCR_D3_MASK 0x0003 + +Scope (\_SB.PCI0) { + + /* + * Clear register 0x1C20/0x4820 + * Arg0 - PCR Port ID + */ + Method(SCSC, 1, Serialized) + { + PCRA (Arg0, 0x1C20, 0x0) + PCRA (Arg0, 0x4820, 0x0) + } + + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + Name (_DDN, "eMMC Controller") + Name(TEMP, 0) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset (0x84), /* PMECTRLSTATUS */ + PMCR, 16, + Offset (0xA2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method(_INI) { + /* + * Clear eMMC timeout registers. _PS0 is not called by kernel when + * boot source is not eMMC, but OS still initializes eMMC. So disable + * timeout registers when boot source is not eMMC. Ported from CB:25290. + */ + SCSC (PID_EMMC) + } + + Method(_PS0, 0, Serialized) { + Stall (50) /* Sleep 50 us */ + + PGEN = 0 /* Disable PG */ + + /* Clear register 0x1C20/0x4820 */ + SCSC (PID_EMMC) + + /* Set Power State to D0 */ + PMCR &= PMCR_D0_MASK + /* Additional config read to eMMC controller. Ported from CB:23312 */ + TEMP = PMCR + } + + Method(_PS3, 0, Serialized) { + PGEN = 1 /* Enable PG */ + + /* Set Power State to D3 */ + PMCR |= PMCR_D3_MASK + /* Additional config read to eMMC controller. Ported from CB:23312 */ + TEMP = PMCR + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } +} diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c new file mode 100644 index 0000000000..4e8095750a --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SI_DESC_REGION "SI_DESC" +#define SI_DESC_REGION_SZ 4096 +#define PMC_DESC_7_BYTE3 0xc32 + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 + +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A + +/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ +static int is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); + return 0; + } + + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + + return 1; +} + +/* It updates PMC Descriptor in the Descriptor Region */ +void configure_pmc_descriptor(void) +{ + uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + struct region_device desc_rdev; + + if (cpu_get_cpuid() != CPUID_ALDERLAKE_A0) + return; + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + if (!is_descriptor_writeable(si_desc_buf)) + return; + + if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { + printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); + return; + } + + si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) + != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + return; + } + + printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); + + pmc_global_reset_enable(true); + do_full_reset(); + die("Failed to trigger GLOBAL RESET\n"); +} diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c new file mode 100644 index 0000000000..09bf112160 --- /dev/null +++ b/src/soc/intel/alderlake/retimer.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +int retimer_get_index_for_typec(uint8_t typec_port) +{ + int ec_port = 0; + + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port1), + DEV_PTR(tcss_usb3_port2), + DEV_PTR(tcss_usb3_port3), + DEV_PTR(tcss_usb3_port4), + }; + + for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (i == typec_port) { + printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, + ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + // Code should not come here if typec_port input is correct + return -1; +} diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c new file mode 100644 index 0000000000..4335a468d2 --- /dev/null +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPPC_NOM_FREQ_IDX 22 +#define CPPC_NOM_PERF_IDX 3 + +enum cpu_perf_eff_type { + CPU_TYPE_SMALL, + CPU_TYPE_BIG, +}; + +DECLARE_SPIN_LOCK(cpu_lock); +static u8 global_cpu_type[CONFIG_MAX_CPUS]; + +static bool is_big_core(void) +{ + return get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE; +} + +static u32 get_cpu_index(void) +{ + u32 cpu_index = 0; + struct device *dev; + u32 my_apic_id = lapicid(); + + for (dev = dev_find_lapic(0); dev; dev = dev->next) { + if (my_apic_id > dev->path.apic.apic_id) + cpu_index++; + } + + return cpu_index; +} + +/* + * This function determines the type (big or small) of the CPU that is executing + * it and stores the information (in a thread-safe manner) in an global_cpu_type + * array. + * It requires the SoC to implement a function `get_soc_cpu_type()` which will be + * called in a critical section to determine the type of the executing CPU. + */ +static void set_cpu_type(void *unused) +{ + spin_lock(&cpu_lock); + u8 cpu_index = get_cpu_index(); + + if (is_big_core()) + global_cpu_type[cpu_index] = CPU_TYPE_BIG; + + spin_unlock(&cpu_lock); +} + +static void run_set_cpu_type(void *unused) +{ + if (mp_run_on_all_cpus(set_cpu_type, NULL) != CB_SUCCESS) { + printk(BIOS_ERR, "cpu_hybrid: Failed to set global_cpu_type with CPU type info\n"); + return; + } +} + +static void acpi_get_cpu_nomi_perf(u16 *small_core_nom_perf, u16 *big_core_nom_perf) +{ + u16 big_core_scal_factor, small_core_scal_factor; + u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + + soc_get_scaling_factor(&big_core_scal_factor, &small_core_scal_factor); + + *big_core_nom_perf = (u16)((max_non_turbo_ratio * big_core_scal_factor) / 100); + + *small_core_nom_perf = (u16)((max_non_turbo_ratio * small_core_scal_factor) / 100); +} + +static u16 acpi_get_cpu_nominal_freq(void) +{ + return cpu_get_max_non_turbo_ratio() * cpu_get_bus_frequency(); +} + +/* Updates Nominal Frequency and Nominal Performance */ +static void acpigen_cppc_update_nominal_freq_perf(const char *pkg_path, s32 core_id) +{ + u16 small_core_nom_perf, big_core_nom_perf; + + if (!soc_is_nominal_freq_supported()) + return; + + acpi_get_cpu_nomi_perf(&small_core_nom_perf, &big_core_nom_perf); + + if (global_cpu_type[core_id] == CPU_TYPE_BIG) + acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, big_core_nom_perf); + else + acpigen_set_package_element_int(pkg_path, CPPC_NOM_PERF_IDX, + small_core_nom_perf); + + /* Update CPU's nominal frequency */ + acpigen_set_package_element_int(pkg_path, CPPC_NOM_FREQ_IDX, + acpi_get_cpu_nominal_freq()); +} + +void acpigen_write_CPPC_hybrid_method(s32 core_id) +{ + char pkg_path[16]; + + if (core_id == 0) + snprintf(pkg_path, sizeof(pkg_path), CPPC_PACKAGE_NAME, 0); + else + snprintf(pkg_path, sizeof(pkg_path), + CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + + acpigen_write_method("_CPC", 0); + + /* Update nominal performance and nominal frequency */ + acpigen_cppc_update_nominal_freq_perf(pkg_path, core_id); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(pkg_path); + acpigen_pop_len(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, run_set_cpu_type, NULL); diff --git a/src/soc/intel/common/block/acpi/sgx.c b/src/soc/intel/common/block/acpi/sgx.c new file mode 100644 index 0000000000..7d9073d9ab --- /dev/null +++ b/src/soc/intel/common/block/acpi/sgx.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define SGX_RESOURCE_ENUM_CPUID_LEAF 0x12 +#define SGX_RESOURCE_ENUM_CPUID_SUBLEAF 0x2 +#define SGX_RESOURCE_ENUM_BIT 0x1 +#define SGX_RESOURCE_MASK_LO 0xfffff000UL +#define SGX_RESOURCE_MASK_HI 0xfffffUL + +static inline uint64_t sgx_resource(uint32_t low, uint32_t high) +{ + uint64_t val; + val = (uint64_t)(high & SGX_RESOURCE_MASK_HI) << 32; + val |= low & SGX_RESOURCE_MASK_LO; + return val; +} + +void sgx_fill_ssdt(void) +{ + bool epcs = false; + struct cpuid_result cpuid_regs; + uint64_t emna = 0, elng = 0; + + if (is_sgx_supported()) { + /* + * Get EPC base and size. + * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or + * higher for enumeration of SGX resources + */ + cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF, + SGX_RESOURCE_ENUM_CPUID_SUBLEAF); + + if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) { + /* EPC section enumerated */ + epcs = true; + emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx); + elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx); + } + + printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n", + epcs, emna, elng); + } else { + printk(BIOS_DEBUG, "SGX: not supported.\n"); + } + + acpigen_write_scope("\\_SB.EPC"); + { + acpigen_write_name_byte("EPCS", epcs); + acpigen_write_name_qword("EMNA", emna); + acpigen_write_name_qword("ELNG", elng); + } + acpigen_pop_len(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse_layout.h b/src/soc/intel/common/block/include/intelblocks/cse_layout.h new file mode 100644 index 0000000000..4c88cc52d3 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_layout.h @@ -0,0 +1,105 @@ +/* BPDT version 1.7 support */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +enum bpdt_entry_type { + SMIP = 0, + CSE_RBE = 1, + CSE_BUP = 2, + UCODE = 3, + IBB = 4, + S_BPDT = 5, + OBB = 6, + CSE_MAIN = 7, + ISH = 8, + CSE_IDLM = 9, + IFP_OVERRIDE = 10, + UTOK = 11, + UFS_PHY = 12, + UFS_GPP = 13, + PMC = 14, + IUNIT = 15, + NVM_CFG = 16, + UEP = 17, + OEM_KM = 20, + PAVP = 22, + IOM_FW = 23, + NPHY_FW = 24, + TBT_FW = 25, + ICC = 32, + + MAX_SUBPARTS, +}; + +struct bpdt_header { + uint32_t signature; /* BPDT_SIGNATURE */ + uint16_t descriptor_count; + uint8_t version; /* Layout 1.7 = 2 */ + uint8_t flags; + uint32_t checksum; + uint32_t ifwi_version; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } fit_tool_version; +} __packed; + +struct cse_layout { + uint8_t rom_bypass[16]; + uint16_t size; + uint16_t redundancy; + uint32_t checksum; + uint32_t data_offset; + uint32_t data_size; + uint32_t bp1_offset; + uint32_t bp1_size; + uint32_t bp2_offset; + uint32_t bp2_size; + uint32_t bp3_offset; + uint32_t bp3_size; + uint32_t bp4_offset; + uint32_t bp4_size; + uint32_t bp5_offset; + uint32_t bp5_size; + uint32_t temp_base_addr; + uint32_t temp_base_size; + uint32_t flog_offset; + uint32_t flog_size; +} __packed; + +struct bpdt_entry { + uint32_t type; + uint32_t offset; + uint32_t size; +} __packed; + +struct subpart_hdr { + uint32_t signature; /* SUBPART_SIGNATURE */ + uint32_t count; + uint8_t hdr_version; /* Header version = 2 */ + uint8_t entry_version; /* Entry version = 1 */ + uint8_t length; + uint8_t reserved; + uint8_t name[4]; + uint32_t checksum; +} __packed; + +struct subpart_entry { + uint8_t name[12]; + uint32_t offset_bytes; + uint32_t length; + uint32_t rsvd2; +} __packed; + +struct subpart_entry_manifest_header { + uint8_t reserved[36]; + struct { + uint16_t major; + uint16_t minor; + uint16_t build; + uint16_t hotfix; + } binary_version; +} __packed; diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h new file mode 100644 index 0000000000..7df528d20d --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_P2SBLIB_H +#define SOC_INTEL_COMMON_BLOCK_P2SBLIB_H + +#include +#include + +/* P2SB generic configuration register */ +#define P2SBC 0xe0 +#define P2SBC_HIDE_BIT (1 << 0) + +bool p2sb_dev_is_hidden(pci_devfn_t dev); +void p2sb_dev_unhide(pci_devfn_t dev); +void p2sb_dev_hide(pci_devfn_t dev); +uint32_t p2sb_dev_sbi_read(pci_devfn_t dev, uint8_t pid, uint16_t reg); +void p2sb_dev_sbi_write(pci_devfn_t dev, uint8_t pid, uint16_t reg, uint32_t val); + +#endif /* SOC_INTEL_COMMON_BLOCK_P2SBLIB_H */ diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c new file mode 100644 index 0000000000..d00606dd89 --- /dev/null +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include + +bool p2sb_dev_is_hidden(pci_devfn_t dev) +{ + const uint16_t pci_vid = pci_read_config16(dev, PCI_VENDOR_ID); + + if (pci_vid == 0xffff) + return true; + if (pci_vid == PCI_VENDOR_ID_INTEL) + return false; + printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n"); + return true; +} + +static void p2sb_dev_set_hide_bit(pci_devfn_t dev, int hide) +{ + const uint16_t reg = P2SBC + 1; + const uint8_t mask = P2SBC_HIDE_BIT; + uint8_t val; + + val = pci_read_config8(dev, reg); + val &= ~mask; + if (hide) + val |= mask; + pci_write_config8(dev, reg, val); +} + +void p2sb_dev_unhide(pci_devfn_t dev) +{ + p2sb_dev_set_hide_bit(dev, 0); + + if (p2sb_dev_is_hidden(dev)) + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide the P2SB device!\n"); +} + +void p2sb_dev_hide(pci_devfn_t dev) +{ + p2sb_dev_set_hide_bit(dev, 1); + + if (!p2sb_dev_is_hidden(dev)) + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide the P2SB device!\n"); +} + +static void p2sb_execute_sideband_access(pci_devfn_t dev, uint8_t cmd, uint8_t pid, + uint16_t reg, uint32_t *data) +{ + struct pcr_sbi_msg msg = { + .pid = pid, + .offset = reg, + .opcode = cmd, + .is_posted = false, + .fast_byte_enable = 0xF, + .bar = 0, + .fid = 0 + }; + uint8_t response; + int status; + + /* Unhide the P2SB device */ + p2sb_dev_unhide(dev); + + status = pcr_execute_sideband_msg(dev, &msg, data, &response); + if (status || response) + printk(BIOS_ERR, "Fail to execute p2sb sideband access\n"); + + /* Hide the P2SB device */ + p2sb_dev_hide(dev); +} + +uint32_t p2sb_dev_sbi_read(pci_devfn_t dev, uint8_t pid, uint16_t reg) +{ + uint32_t val = 0; + p2sb_execute_sideband_access(dev, PCR_READ, pid, reg, &val); + return val; +} + +void p2sb_dev_sbi_write(pci_devfn_t dev, uint8_t pid, uint16_t reg, uint32_t val) +{ + p2sb_execute_sideband_access(dev, PCR_WRITE, pid, reg, &val); +} diff --git a/src/soc/intel/common/block/thermal/thermal_common.c b/src/soc/intel/common/block/thermal/thermal_common.c new file mode 100644 index 0000000000..ba1ab062a6 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_common.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->pch_thermal_trip; +} + +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void) +{ + uint8_t thermal_config; + + thermal_config = get_thermal_trip_temp(); + if (!thermal_config) + thermal_config = DEFAULT_TRIP_TEMP; + + if (thermal_config > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + return GET_LTT_VALUE(thermal_config); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pci.c b/src/soc/intel/common/block/thermal/thermal_pci.c new file mode 100644 index 0000000000..04203fe136 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_pci.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c +#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uintptr_t thermalbar; + uintptr_t thermalbar_pm; + const struct device *dev; + struct resource *res; + + dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + if (!dev) { + printk(BIOS_ERR, "PCH_DEVFN_THERMAL device not found!\n"); + return; + } + + res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "PCH thermal device not found!\n"); + return; + } + + /* Get the base address of the resource */ + thermalbar = res->base; + + /* Get the required thermal address to write the register value */ + thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT; + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value()); +} diff --git a/src/soc/intel/common/block/thermal/thermal_pmc.c b/src/soc/intel/common/block/thermal/thermal_pmc.c new file mode 100644 index 0000000000..3525b47ecb --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_pmc.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + * Thermal configuration has evolved over time. With older platform the + * thermal device is sitting over PCI and allow to configure its configuration + * register by accessing the PCI configuration space or MMIO space. + * + * Since Tiger Lake, thermal registers are being moved behind the PMC PCI device + * hence, accessing thermal configuration registers would need making access + * to PWRMBASE. In this case SoC Kconfig to select + * SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to allow thermal configuration. + */ +void pch_thermal_configuration(void) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + + struct pmc_thermal_config { + uint16_t offset; + uint32_t mask; + uint32_t value; + } config[] = { + { + .offset = PMC_PWRM_THERMAL_CTEN, + .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, + }, + { + .offset = PMC_PWRM_THERMAL_ECRPTEN, + .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT + | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, + }, + { + .offset = PMC_PWRM_THERMAL_TL, + .mask = ~0, + .value = pch_get_ltt_value() | PMC_PWRM_THERMAL_TL_TTEN + | PMC_PWRM_THERMAL_TL_TLLOCK, + }, + { + .offset = PMC_PWRM_THERMAL_PHLC, + .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, + }, + { + .offset = PMC_PWRM_THERMAL_TLEN, + .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, + }, + }; + + for (int i = 0; i < ARRAY_SIZE(config); i++) + clrsetbits32((void *)(pmc_bar + config[i].offset), config[i].mask, + config[i].value); +} diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c new file mode 100644 index 0000000000..57a5cf29dc --- /dev/null +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define CPU_CPIE_VW_IDX_BASE 24 + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group cpu_rp_groups[] = { + { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3, .lcap_port_base = 1 }, + { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1, .lcap_port_base = 1 }, + { 0 } +}; + +static bool is_part_of_group(const struct device *dev, + const struct pcie_rp_group *groups) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return false; + + const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn); + const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn); + const struct pcie_rp_group *group; + unsigned int i; + unsigned int fn; + + for (group = groups; group->count; ++group) { + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + if (slot_to_find == group->slot && fn_to_find == fn) + return true; + } + } + + return false; +} + +const struct pcie_rp_group *soc_get_pch_rp_groups(void) +{ + if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)) + return pch_h_rp_groups; + else + return pch_lp_rp_groups; +} + +enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) +{ + const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups(); + + if (is_part_of_group(dev, pch_rp_groups)) + return PCIE_RP_PCH; + + if (is_part_of_group(dev, cpu_rp_groups)) + return PCIE_RP_CPU; + + return PCIE_RP_UNKNOWN; +} + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_PEG1: + return CPU_CPIE_VW_IDX_BASE + 2; + case SA_DEVFN_PEG2: + return CPU_CPIE_VW_IDX_BASE + 1; + case SA_DEVFN_PEG3: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE: + return CPU_CPIE_VW_IDX_BASE + 3; + default: + return -1; + } +} diff --git a/src/soc/intel/tigerlake/retimer.c b/src/soc/intel/tigerlake/retimer.c new file mode 100644 index 0000000000..09bf112160 --- /dev/null +++ b/src/soc/intel/tigerlake/retimer.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +int retimer_get_index_for_typec(uint8_t typec_port) +{ + int ec_port = 0; + + const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port1), + DEV_PTR(tcss_usb3_port2), + DEV_PTR(tcss_usb3_port3), + DEV_PTR(tcss_usb3_port4), + }; + + for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (i == typec_port) { + printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, + ec_port); + return ec_port; + } + + if (is_dev_enabled(tcss_port_arr[i])) + ec_port++; + } + + // Code should not come here if typec_port input is correct + return -1; +} diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 754c0da580..27f6cec125 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -22,6 +22,13 @@ config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT This options limit DRAM frequency calibration count from total 7 to 3, other frequency will directly use the low frequency shu result. +config MEDIATEK_BLOB_FAST_INIT + bool "Enable running fast calibration by blob" + default n + help + This option allows performing fast calibration through different + open-source policy. + config MEMORY_TEST bool default y @@ -29,11 +36,6 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. -config CLEAR_WDT_MODE_REG - bool - help - Enable this option to clear WTD mode register explicitly. - config DPM_FOUR_CHANNEL bool default n @@ -41,9 +43,10 @@ config DPM_FOUR_CHANNEL This option enables four channel configuration for DPM. config MTK_DFD - bool - default n + bool "Enable MediaTek DFD (Design For Debug) settings" help - This option enables DFD (Design for Debug) settings. + DFD (Design for Debug) is a debugging tool, which scans flip-flops + and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM + to store logs of DFD. endif diff --git a/src/soc/mediatek/common/dram_init.c b/src/soc/mediatek/common/dram_init.c index 252ff8c802..cfcf84bda1 100644 --- a/src/soc/mediatek/common/dram_init.c +++ b/src/soc/mediatek/common/dram_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index a4556f5200..f16d8f2480 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -377,7 +377,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing); mtk_dsi_clk_hs_mode_enable(); - mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq); + if (init_commands) + mipi_panel_parse_init_commands(init_commands, mtk_dsi_cmdq); mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); diff --git a/src/soc/mediatek/common/flash_controller.c b/src/soc/mediatek/common/flash_controller.c index cdda056b9f..3fe17f8612 100644 --- a/src/soc/mediatek/common/flash_controller.c +++ b/src/soc/mediatek/common/flash_controller.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 1e713dbea6..c47e08e8aa 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include const struct i2c_spec_values standard_mode_spec = { @@ -31,7 +32,15 @@ const struct i2c_spec_values fast_mode_plus_spec = { .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, }; -__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { /* do nothing */ } +__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + /* do nothing */ +} + +__weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + /* do nothing */ +} const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed) { @@ -97,10 +106,10 @@ static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs) mtk_i2c_dump_more_info(regs); } -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes mode) +static int mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes mode) { - uint32_t ret_code = I2C_OK; + int ret = I2C_OK; uint16_t status; uint16_t dma_sync = 0; uint32_t time_out_val = 0; @@ -236,23 +245,23 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, while (1) { status = read32(®s->intr_stat); if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + ret = I2C_TRANSFER_FAIL_HS_NACKERR; printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); mtk_i2c_dump_info(regs); break; } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; + ret = I2C_TRANSFER_FAIL_ACKERR; printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); mtk_i2c_dump_info(regs); break; } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; + ret = I2C_OK; memcpy(read_buffer, _dma_coherent, read_len); break; } if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + ret = I2C_TRANSFER_FAIL_TIMEOUT; printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, time_out_val); mtk_i2c_dump_info(regs); @@ -270,7 +279,7 @@ static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, /* reset the i2c controller for next i2c transfer. */ i2c_hw_reset(bus); - return ret_code; + return ret; } static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) @@ -281,10 +290,18 @@ static bool mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) seg[0].slave == seg[1].slave); } +static int mtk_i2c_max_step_cnt(uint32_t target_speed) +{ + if (target_speed > I2C_SPEED_FAST_PLUS) + return MAX_HS_STEP_CNT_DIV; + else + return MAX_STEP_CNT_DIV; +} + int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { - int ret = 0; + int ret; int i; int mode; @@ -297,13 +314,239 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, } ret = mtk_i2c_transfer(bus, &segments[i], mode); - - if (ret) - break; + if (ret < 0) + return ret; if (mode == I2C_WRITE_READ_MODE) i++; } - return ret; + return 0; +} + +/* + * Check and calculate i2c ac-timing. + * + * Hardware design: + * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src + * xxx_cnt_div = spec->min_xxx_ns / sample_ns + * + * The calculation of sample_ns is rounded down; + * otherwise xxx_cnt_div would be greater than the smallest spec. + * The sda_timing is chosen as the middle value between + * the largest and smallest. + */ +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt) +{ + const struct i2c_spec_values *spec; + uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; + uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; + uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; + struct mtk_i2c_ac_timing *ac_timing; + + spec = mtk_i2c_get_spec(check_speed); + + clk_ns = NSECS_PER_SEC / clk_src; + + su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); + if (su_sta_cnt > max_sta_cnt) + return -1; + + low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); + max_step_cnt = mtk_i2c_max_step_cnt(check_speed); + if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { + if (low_cnt > step_cnt) { + high_cnt = 2 * step_cnt - low_cnt; + } else { + high_cnt = step_cnt; + low_cnt = step_cnt; + } + } else { + return -2; + } + + sda_max = spec->max_hd_dat_ns / sample_ns; + if (sda_max > low_cnt) + sda_max = 0; + + sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); + if (sda_min < low_cnt) + sda_min = 0; + + if (sda_min > sda_max) + return -3; + + ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; + if (check_speed > I2C_SPEED_FAST_PLUS) { + ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); + ac_timing->ltiming &= ~GENMASK(15, 9); + ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); + ac_timing->ext &= ~GENMASK(7, 1); + ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); + } else { + ac_timing->htiming = (sample_cnt << 8) | (high_cnt); + ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); + ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); + } + + return 0; +} + +/* + * Calculate i2c port speed. + * + * Hardware design: + * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) + * clock_div: fixed in hardware, but may be various in different SoCs + * + * To calculate sample_cnt and step_cnt, we pick the highest bus frequency + * that is still no larger than i2c->speed_hz. + */ +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt) +{ + uint32_t step_cnt; + uint32_t sample_cnt; + uint32_t max_step_cnt; + uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; + uint32_t base_step_cnt; + uint32_t opt_div; + uint32_t best_mul; + uint32_t cnt_mul; + uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; + int32_t clock_div_constraint = 0; + int success = 0; + + if (target_speed > I2C_SPEED_HIGH) + target_speed = I2C_SPEED_HIGH; + + max_step_cnt = mtk_i2c_max_step_cnt(target_speed); + base_step_cnt = max_step_cnt; + + /* Find the best combination */ + opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); + best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; + + /* Search for the best pair (sample_cnt, step_cnt) with + * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV + * 0 < step_cnt < max_step_cnt + * sample_cnt * step_cnt >= opt_div + * optimizing for sample_cnt * step_cnt being minimal + */ + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { + if (sample_cnt == 1) { + if (clk_div != 0) + clock_div_constraint = 1; + else + clock_div_constraint = 0; + } else { + if (clk_div > 1) + clock_div_constraint = 1; + else if (clk_div == 0) + clock_div_constraint = -1; + else + clock_div_constraint = 0; + } + + step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); + if (step_cnt > max_step_cnt) + continue; + + cnt_mul = step_cnt * sample_cnt; + if (cnt_mul >= best_mul) + continue; + + if (mtk_i2c_check_ac_timing(bus, clk_src, + target_speed, step_cnt - 1, + sample_cnt - 1)) + continue; + + success = 1; + best_mul = cnt_mul; + base_sample_cnt = sample_cnt; + base_step_cnt = step_cnt; + if (best_mul == opt_div + clock_div_constraint) + break; + + } + + if (!success) + return -1; + + sample_cnt = base_sample_cnt; + step_cnt = base_step_cnt; + + if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > + target_speed) + return -1; + + *timing_step_cnt = step_cnt - 1; + *timing_sample_cnt = sample_cnt - 1; + + return 0; +} + +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) +{ + uint32_t max_clk_div = MAX_CLOCK_DIV; + uint32_t clk_src, clk_div, step_cnt, sample_cnt; + uint32_t l_step_cnt, l_sample_cnt; + uint32_t timing_reg_value, ltiming_reg_value; + struct mtk_i2c *bus_ctrl; + + if (bus >= I2C_BUS_NUMBER) { + printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); + return; + } + + bus_ctrl = &mtk_i2c_bus_controller[bus]; + + for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { + clk_src = I2C_CLK_HZ / clk_div; + bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; + + if (speed > I2C_SPEED_FAST_PLUS) { + /* Set master code speed register */ + if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Set the high speed mode register */ + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &step_cnt, &sample_cnt)) + continue; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | + (sample_cnt << 12) | (step_cnt << 9); + bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); + } else { + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Disable the high speed transaction */ + bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; + } + + break; + } + + if (clk_div > max_clk_div) { + printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); + return; + } + + /* Init i2c bus timing register. */ + mtk_i2c_config_timing(bus_ctrl->i2c_regs, bus_ctrl); } diff --git a/src/soc/mediatek/common/include/soc/devapc_common.h b/src/soc/mediatek/common/include/soc/devapc_common.h new file mode 100644 index 0000000000..666fc70b5e --- /dev/null +++ b/src/soc/mediatek/common/include/soc/devapc_common.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_DEVAPC_H +#define SOC_MEDIATEK_COMMON_DEVAPC_H + +#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ + (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, + +#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3) \ + DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) + +#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ + PERM_ATTR2, PERM_ATTR3, \ + PERM_ATTR4, PERM_ATTR5, \ + PERM_ATTR6, PERM_ATTR7) \ + DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ + PERM_ATTR10, PERM_ATTR11, \ + PERM_ATTR12, PERM_ATTR13, \ + PERM_ATTR14, PERM_ATTR15) + +#define FORBIDDEN2 FORBIDDEN, FORBIDDEN +#define FORBIDDEN3 FORBIDDEN2, FORBIDDEN +#define FORBIDDEN4 FORBIDDEN3, FORBIDDEN +#define FORBIDDEN5 FORBIDDEN4, FORBIDDEN +#define FORBIDDEN6 FORBIDDEN5, FORBIDDEN +#define FORBIDDEN7 FORBIDDEN6, FORBIDDEN +#define FORBIDDEN10 FORBIDDEN3, FORBIDDEN7 +#define FORBIDDEN11 FORBIDDEN10, FORBIDDEN +#define FORBIDDEN12 FORBIDDEN11, FORBIDDEN +#define FORBIDDEN13 FORBIDDEN12, FORBIDDEN +#define FORBIDDEN14 FORBIDDEN13, FORBIDDEN +#define FORBIDDEN15 FORBIDDEN14, FORBIDDEN + +#define NO_PROTECTION2 NO_PROTECTION, NO_PROTECTION +#define NO_PROTECTION3 NO_PROTECTION2, NO_PROTECTION +#define NO_PROTECTION4 NO_PROTECTION3, NO_PROTECTION + +#endif diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h index 8c110aaaf1..e72b6a1f3d 100644 --- a/src/soc/mediatek/common/include/soc/dpm.h +++ b/src/soc/mediatek/common/include/soc/dpm.h @@ -5,7 +5,6 @@ #include #include -#include #include struct dpm_regs { diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h new file mode 100644 index 0000000000..09b89cbe62 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_DRAMC_PARAM_COMMON_H__ +#define __SOC_MEDIATEK_DRAMC_PARAM_COMMON_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, + DRAMC_ERR_INIT_DRAM, + DRAMC_ERR_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, + DRAMC_ERR_FAST_CALIBRATION, +}; + +enum DRAMC_PARAM_FLAG { + DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, +}; + +enum DRAMC_PARAM_CONFIG { + DRAMC_CONFIG_EMCP = 0x0001, + DRAMC_CONFIG_DVFS = 0x0002, + DRAMC_CONFIG_FAST_K = 0x0004, +}; + +struct dramc_param_header { + u16 version; /* DRAMC_PARAM_HEADER_VERSION, set in coreboot */ + u16 size; /* size of whole dramc_param, set in coreboot */ + u16 status; /* DRAMC_PARAM_STATUS_CODES, set in dram blob */ + u16 flags; /* DRAMC_PARAM_FLAG, set in dram blob */ + u16 config; /* DRAMC_PARAM_CONFIG, set in coreboot */ +}; + +enum SDRAM_DDR_TYPE { + DDR_TYPE_DISCRETE, + DDR_TYPE_EMCP, +}; + +enum SDRAM_DDR_GEOMETRY_TYPE { + DDR_TYPE_2CH_2RK_4GB_2_2, + DDR_TYPE_2CH_2RK_6GB_3_3, + DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, + DDR_TYPE_2CH_1RK_4GB_4_0, + DDR_TYPE_2CH_2RK_6GB_2_4, + DDR_TYPE_2CH_2RK_8GB_4_4, +}; + +struct sdram_info { + u32 ddr_type; /* SDRAM_DDR_TYPE */ + u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ +}; + +struct emi_mdl { + u32 cona_val; + u32 conh_val; + u32 conf_val; + u32 chn_cona_val; +}; + +struct ddr_mrr_info { + u16 mr5_vendor_id; + u16 mr6_revision_id; + u16 mr7_revision_id; + u64 mr8_density[RANK_MAX]; + u32 rank_nums; + u8 die_num[RANK_MAX]; +}; + +enum SDRAM_DVFS_FLAG { + DRAMC_DISABLE_DVFS, + DRAMC_ENABLE_DVFS, +}; + +enum SDRAM_VOLTAGE_TYPE { + SDRAM_VOLTAGE_NVCORE_NVDRAM, + SDRAM_VOLTAGE_HVCORE_HVDRAM, + SDRAM_VOLTAGE_LVCORE_LVDRAM, +}; + +struct ddr_base_info { + u32 config_dvfs; /* SDRAM_DVFS_FLAG */ + struct sdram_info sdram; + u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u32 support_ranks; + u64 rank_size[RANK_MAX]; + struct emi_mdl emi_config; + DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; + struct ddr_mrr_info mrr_info; + u32 data_rate; +}; + +#endif diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h index 994d35a8ec..60206d8ae7 100644 --- a/src/soc/mediatek/common/include/soc/emi.h +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_EMI_H -#define SOC_MEDIATEK_EMI_H +#ifndef SOC_MEDIATEK_COMMON_EMI_H +#define SOC_MEDIATEK_COMMON_EMI_H #include @@ -16,4 +16,4 @@ u32 get_ddr_geometry(void); u32 get_ddr_type(void); void init_dram_by_params(struct dramc_param *dparam); -#endif /* SOC_MEDIATEK_MT8192_EMI_H */ +#endif /* SOC_MEDIATEK_COMMON_EMI_H */ diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 72ec46a093..4f4449ce78 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -88,12 +88,12 @@ enum { /* I2C Status Code */ enum { I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 + I2C_SET_SPEED_FAIL_OVER_SPEED = -0xA001, + I2C_TRANSFER_INVALID_LENGTH = -0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = -0xA003, + I2C_TRANSFER_FAIL_ACKERR = -0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = -0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = -0xA006, }; struct mtk_i2c_ac_timing { @@ -143,4 +143,15 @@ extern struct mtk_i2c mtk_i2c_bus_controller[]; const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed); void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs); +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt); +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt); +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed); +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl); + #endif diff --git a/src/soc/mediatek/common/include/soc/msdc.h b/src/soc/mediatek/common/include/soc/msdc.h index 6208b72f6e..798b0f61fe 100644 --- a/src/soc/mediatek/common/include/soc/msdc.h +++ b/src/soc/mediatek/common/include/soc/msdc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __MSDC_H_ -#define __MSDC_H_ +#ifndef SOC_MEDIATEK_COMMON_MSDC_H +#define SOC_MEDIATEK_COMMON_MSDC_H #include @@ -162,8 +162,10 @@ struct msdc_ctrlr { #define msdc_debug(format...) printk(BIOS_DEBUG, format) #define msdc_trace(format...) printk(BIOS_DEBUG, format) -#define msdc_error(format...) printk(BIOS_ERR, "ERROR: " format) +#define msdc_error(format...) printk(BIOS_ERR, format) int mtk_emmc_early_init(void *base, void *top_base); +void mtk_msdc_configure_emmc(bool is_early_init); +void mtk_msdc_configure_sdcard(void); -#endif // MTK_MMC_H_ +#endif /* SOC_MEDIATEK_COMMON_MSDC_H */ diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index 61efaec42c..afd00d59aa 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -81,8 +81,13 @@ enum { RDATA_WACS_FSM_SHIFT = 16, RDATA_WACS_REQ_SHIFT = 19, RDATA_SYNC_IDLE_SHIFT, - RDATA_INIT_DONE_SHIFT, - RDATA_SYS_IDLE_SHIFT, + RDATA_INIT_DONE_V1_SHIFT, + RDATA_SYS_IDLE_V1_SHIFT, +}; + +enum { + RDATA_INIT_DONE_V2_SHIFT = 22, /* 8186 */ + RDATA_SYS_IDLE_V2_SHIFT = 23, /* 8186 */ }; enum { diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 0cd0f1e8b7..84bb364afd 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -13,12 +13,19 @@ enum mtk_regulator { MTK_REGULATOR_VCORE, MTK_REGULATOR_VCC, MTK_REGULATOR_VCCQ, + MTK_REGULATOR_VDRAM1, + MTK_REGULATOR_VMCH, + MTK_REGULATOR_VMC, + MTK_REGULATOR_VPROC12, + MTK_REGULATOR_VSRAM_PROC12, + MTK_REGULATOR_VRF12, + MTK_REGULATOR_VCN33, + MTK_REGULATOR_NUM, }; void mainboard_set_regulator_vol(enum mtk_regulator regulator, uint32_t voltage_uv); uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator); - int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable); uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator); diff --git a/src/soc/mediatek/common/include/soc/timer_v2.h b/src/soc/mediatek/common/include/soc/timer_v2.h index 507814b233..23059284ce 100644 --- a/src/soc/mediatek/common/include/soc/timer_v2.h +++ b/src/soc/mediatek/common/include/soc/timer_v2.h @@ -9,6 +9,19 @@ #define GPT_MHZ 13 +enum { + TIE_0_EN = 1 << 3, + COMP_15_EN = 1 << 10, + COMP_20_EN = 1 << 11, + COMP_25_EN = 1 << 12, + + COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, + + COMP_15_MASK = COMP_15_EN, + COMP_20_MASK = COMP_20_EN | TIE_0_EN, + COMP_25_MASK = COMP_20_EN | COMP_25_EN, +}; + struct mtk_gpt_regs { u32 reserved1[40]; u32 gpt6_con; diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h index a68d329a25..02694579e1 100644 --- a/src/soc/mediatek/common/include/soc/tracker_common.h +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -1,25 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_COMMON_TRACKER_H -#define SOC_MEDIATEK_COMMON_TRACKER_H +#ifndef SOC_MEDIATEK_TRACKER_COMMON_H +#define SOC_MEDIATEK_TRACKER_COMMON_H -#define BUS_DBG_CON 0x000 -#define BUS_DBG_TIMER_CON0 0x004 -#define BUS_DBG_TIMER_CON1 0x008 -#define BUS_TRACE_CON_1 0x900 -#define BUS_TRACE_CON_AO_1 0x9FC -#define BUS_TRACE_CON_2 0xA00 -#define BUS_TRACE_CON_AO_2 0xAFC -#define BUS_TRACE_EN 16 - -#define SYS_TRACK_ENTRY 64 -#define INFRA_ENTRY_NUM 32 -#define PERI_ENTRY_NUM 16 - -#define AR_TRACK_OFFSET 0x0100 -#define AW_TRACK_OFFSET 0x0300 - -#define BUSTRACKER_TIMEOUT 0x300 +#include #define BUS_DBG_CON_IRQ_AR_STA0 0x00000100 #define BUS_DBG_CON_IRQ_AW_STA0 0x00000200 @@ -28,13 +12,17 @@ #define BUS_DBG_CON_TIMEOUT (BUS_DBG_CON_IRQ_AR_STA0 | BUS_DBG_CON_IRQ_AW_STA0 | \ BUS_DBG_CON_IRQ_AR_STA1 | BUS_DBG_CON_IRQ_AW_STA1) -enum { - TRACKER_SYSTRACKER = 0, - TRACKER_INFRATRACKER, - TRACKER_PERISYSTRACKER, - TRACKER_NUM, +struct tracker { + uintptr_t base_addr; + u32 timeout; + u32 entry; + u32 offset[2]; + const char *str; }; +extern struct tracker tracker_data[]; + +void tracker_setup(void); void bustracker_init(void); #endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v1.h b/src/soc/mediatek/common/include/soc/tracker_v1.h new file mode 100644 index 0000000000..e2a4b67159 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V1_H +#define SOC_MEDIATEK_TRACKER_V1_H + +#define SYS_TRACK_ENTRY 8 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0200 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/include/soc/tracker_v2.h b/src/soc/mediatek/common/include/soc/tracker_v2.h new file mode 100644 index 0000000000..e7bf8df865 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tracker_v2.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_TRACKER_V2_H +#define SOC_MEDIATEK_TRACKER_V2_H + +#define BUS_DBG_CON 0x000 +#define BUS_DBG_TIMER_CON0 0x004 +#define BUS_DBG_TIMER_CON1 0x008 +#define BUS_TRACE_CON_1 0x900 +#define BUS_TRACE_CON_AO_1 0x9FC +#define BUS_TRACE_CON_2 0xA00 +#define BUS_TRACE_CON_AO_2 0xAFC +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define PERI_ENTRY_NUM 16 + +#define AR_TRACK_OFFSET 0x0100 +#define AW_TRACK_OFFSET 0x0300 + +#define BUSTRACKER_TIMEOUT 0x300 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_PERISYSTRACKER, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index 6fa050dcdf..d390b70ffa 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -130,9 +130,13 @@ struct sif_u2_phy_com { check_member(sif_u2_phy_com, u2phydtm0, 0x68); struct sif_u3phyd { - u32 reserved0[23]; + u32 reserved0[4]; + u32 phyd_cal0; + u32 phyd_cal1; + u32 reserved1[15]; + u32 phyd_reserved; u32 phyd_cdr1; - u32 reserved1[40]; + u32 reserved2[41]; }; struct sif_u3phya { @@ -155,6 +159,7 @@ struct sif_u3phya_da { * SOCs will not need it. */ void mtk_usb_prepare(void); +void mtk_usb_adjust_phy_shift(void); void setup_usb_host(void); diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 5847d4953f..cd43134078 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,7 +21,6 @@ struct mtk_wdt_regs { /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, - MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, @@ -40,5 +39,6 @@ enum { static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; int mtk_wdt_init(void); +void mtk_wdt_clr_status(void); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 93856d51e6..3ca36117e9 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -95,31 +96,11 @@ const char *get_dram_type_str(u32 ddr_type) return s; } -static int dram_run_fast_calibration(struct dramc_param *dparam) -{ - const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; - if (dparam->dramc_datas.ddr_info.config_dvfs != config) { - printk(BIOS_WARNING, - "DRAM-K: Incompatible config for calibration data from flash " - "(expected: %#x, saved: %#x)\n", - config, dparam->dramc_datas.ddr_info.config_dvfs); - return -1; - } - - printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); - init_dram_by_params(dparam); - if (mt_mem_test(&dparam->dramc_datas) == 0) - return 0; - - return DRAMC_ERR_FAST_CALIBRATION; -} - -static int dram_run_full_calibration(struct dramc_param *dparam) +static int run_dram_blob(struct dramc_param *dparam) { /* Load and run the provided blob for full-calibration if available */ struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); - initialize_dramc_param(dparam); dump_param_header(dparam); if (cbfs_prog_stage_load(&dram)) { @@ -132,12 +113,13 @@ static int dram_run_full_calibration(struct dramc_param *dparam) prog_set_entry(&dram, prog_entry(&dram), dparam); prog_run(&dram); if (dparam->header.status != DRAMC_SUCCESS) { - printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", + printk(BIOS_ERR, "DRAM-K: calibration failed: status = %d\n", dparam->header.status); return -3; } - if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + if (!(dparam->header.config & DRAMC_CONFIG_FAST_K) + && !(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { printk(BIOS_ERR, "DRAM-K: Full calibration executed without saving parameters. " "Please ensure the blob is built properly.\n"); @@ -147,6 +129,49 @@ static int dram_run_full_calibration(struct dramc_param *dparam) return 0; } +static int dram_run_fast_calibration(struct dramc_param *dparam) +{ + const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; + + if (dparam->dramc_datas.ddr_info.config_dvfs != config) { + printk(BIOS_WARNING, + "DRAM-K: Incompatible config for calibration data from flash " + "(expected: %#x, saved: %#x)\n", + config, dparam->dramc_datas.ddr_info.config_dvfs); + return -1; + } + + printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); + + if (CONFIG(MEDIATEK_BLOB_FAST_INIT)) { + printk(BIOS_INFO, "DRAM-K: Run fast calibration run in blob mode\n"); + + /* + * The loaded config should not contain FAST_K (done in full calibration), + * so we have to set that now to indicate the blob taking the config instead + * of generating a new config. + */ + dparam->header.config |= DRAMC_CONFIG_FAST_K; + + if (run_dram_blob(dparam) < 0) + return -3; + } else { + init_dram_by_params(dparam); + } + + if (mt_mem_test(&dparam->dramc_datas) < 0) + return -4; + + return 0; +} + +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + initialize_dramc_param(dparam); + + return run_dram_blob(dparam); +} + static void mem_init_set_default_config(struct dramc_param *dparam, const struct sdram_info *dram_info) { @@ -172,17 +197,15 @@ static void mem_init_set_default_config(struct dramc_param *dparam, static void mt_mem_init_run(struct dramc_param *dparam, const struct sdram_info *dram_info) { - const ssize_t mrc_cache_size = sizeof(dparam->dramc_datas); + const ssize_t mrc_cache_size = sizeof(*dparam); ssize_t data_size; struct stopwatch sw; int ret; /* Load calibration params from flash and run fast calibration */ - mem_init_set_default_config(dparam, dram_info); data_size = mrc_cache_load_current(MRC_TRAINING_DATA, DRAMC_PARAM_HEADER_VERSION, - &dparam->dramc_datas, - mrc_cache_size); + dparam, mrc_cache_size); if (data_size == mrc_cache_size) { printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); stopwatch_init(&sw); @@ -194,11 +217,10 @@ static void mt_mem_init_run(struct dramc_param *dparam, stopwatch_duration_msecs(&sw), ret); /* Erase flash data after fast calibration failed */ - memset(&dparam->dramc_datas, 0xa5, mrc_cache_size); + memset(dparam, 0xa5, mrc_cache_size); mrc_cache_stash_data(MRC_TRAINING_DATA, DRAMC_PARAM_HEADER_VERSION, - &dparam->dramc_datas, - mrc_cache_size); + dparam, mrc_cache_size); } else { printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", stopwatch_duration_msecs(&sw)); @@ -220,7 +242,7 @@ static void mt_mem_init_run(struct dramc_param *dparam, stopwatch_duration_msecs(&sw)); mrc_cache_stash_data(MRC_TRAINING_DATA, DRAMC_PARAM_HEADER_VERSION, - &dparam->dramc_datas, mrc_cache_size); + dparam, mrc_cache_size); } else { printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", stopwatch_duration_msecs(&sw)); diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/common/mmu_cmops.c similarity index 88% rename from src/soc/mediatek/mt8192/mmu_operations.c rename to src/soc/mediatek/common/mmu_cmops.c index e3bc62282d..4b81a276b6 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_cmops.c @@ -12,7 +12,7 @@ void mtk_soc_disable_l2c_sram(void) { unsigned long v; - SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); dsb(); @@ -25,7 +25,7 @@ void mtk_soc_disable_l2c_sram(void) __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); } while (((v >> 0x4) & 0xf) != 0xf); - SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0, MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 4e044a1412..d732994e4b 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -103,12 +103,17 @@ s32 pwrap_wacs2(u32 write, u16 addr, u16 wdata, u16 *rdata, u32 init_check) u32 wacs_addr = 0; u32 wacs_cmd = 0; u32 wait_result = 0; + u32 shift; if (init_check) { reg_rdata = read32(&mtk_pwrap->wacs2_rdata); /* Prevent someone to use pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + if (CONFIG(SOC_MEDIATEK_MT8186)) + shift = RDATA_INIT_DONE_V2_SHIFT; + else + shift = RDATA_INIT_DONE_V1_SHIFT; + + if (((reg_rdata >> shift) & RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { pwrap_err("Pwrap initialization isn't finished\n"); return E_PWR_NOT_INIT_DONE; } diff --git a/src/soc/mediatek/common/pmif_spi.c b/src/soc/mediatek/common/pmif_spi.c index 1d0af071d4..0ed44a041f 100644 --- a/src/soc/mediatek/common/pmif_spi.c +++ b/src/soc/mediatek/common/pmif_spi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index 48f75fe661..a17fba5c9d 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -6,7 +6,6 @@ #include #include #include -#include #define SPMFW_HEADER_SIZE 16 @@ -51,5 +50,7 @@ void spm_parse_firmware(struct mtk_mcu *mcu) /* Version */ offset += copy_size; assert(offset < file_size); - printk(BIOS_INFO, "SPM: spmfw (version %s)\n", (u8 *)mcu->load_buffer + offset); + printk(BIOS_INFO, "SPM: spmfw (version %.*s)\n", + (int)(file_size - offset), + (u8 *)mcu->load_buffer + offset); } diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 6d4e6b2f05..3485449b6b 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -1,79 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include +#include #include -static struct tracker { - uintptr_t base_addr; - u32 timeout; - u32 entry; - u32 offset[2]; - const char *str; -} tracker_data[TRACKER_NUM] = { - [TRACKER_SYSTRACKER] = { - .base_addr = DBG_TRACKER_BASE, - .timeout = BUS_DBG_CON_TIMEOUT, - .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "systracker", - }, - [TRACKER_INFRATRACKER] = { - .base_addr = INFRA_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = INFRA_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "infra_tracker", - }, - [TRACKER_PERISYSTRACKER] = { - .base_addr = PERI_TRACKER_BASE, - .timeout = BUSTRACKER_TIMEOUT, - .entry = PERI_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, - .str = "peri_tracker", - }, -}; - -static void setup_init(void) +__weak void tracker_setup(void) { - u32 val; - /* - * Set infra/peri tracker timeout. - * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms - * - * timeout: 200ms - * infra tracker clock: 156MHz - * peri tracker clock: 78MHz - */ - val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); - - /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); - - /* - * Enable infra/peri tracker. - * bit[0] - BUS_DBG_EN - * bit[1] - TIMEOUT_EN - * bit[2] - SLV_ERR_EN - * bit[13] - HALT_ON_TIMEOUT_EN - * bit[14] - BUS_OT_WEN_CTRL - */ - val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); - + /* do nothing. */ } static void tracker_dump_data(void) @@ -91,19 +26,6 @@ static void tracker_dump_data(void) printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); for (k = 0; k < 2; k++) { - /* - * for systracker: - * offset[0] dump from offset 0x100 ~ 0x2F8. - * offset[1] dump from offset 0x300 ~ 0x4FC - * - * for infra tracker: - * offset[0] dump from offset 0x100 ~ 0x1F8 - * offset[1] dump from offset 0x300 ~ 0x3FC - * - * for perisys tracker: - * offset[0] dump from offset 0x100 ~ 0x2F8 - * offset[1] dump from offset 0x300 ~ 0x4FC - */ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offset[k] + i * 4; @@ -121,5 +43,5 @@ static void tracker_dump_data(void) void bustracker_init(void) { tracker_dump_data(); - setup_init(); + tracker_setup(); } diff --git a/src/soc/mediatek/common/tracker_v1.c b/src/soc/mediatek/common/tracker_v1.c new file mode 100644 index 0000000000..746951b8de --- /dev/null +++ b/src/soc/mediatek/common/tracker_v1.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x13C. + * offset[1] dump from offset 0x200 ~ 0x23C. + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, +}; diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c new file mode 100644 index 0000000000..fecde161fd --- /dev/null +++ b/src/soc/mediatek/common/tracker_v2.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8. + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for perisys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = DBG_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "infra_tracker", + }, + [TRACKER_PERISYSTRACKER] = { + .base_addr = PERI_TRACKER_BASE, + .timeout = BUSTRACKER_TIMEOUT, + .entry = PERI_ENTRY_NUM, + .offset[0] = AR_TRACK_OFFSET, + .offset[1] = AW_TRACK_OFFSET, + .str = "peri_tracker", + }, +}; + +void tracker_setup(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz * 1000 / 16 * timeout_in_ms + * + * timeout: 200ms + * infra tracker clock: 156MHz + * peri tracker clock: 78MHz + */ + val = 156 * 1000 / 16 * 200; + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + val = 78 * 1000 / 16 * 200; + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + + /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); +} diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 52daaac117..b9fe83529d 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -140,7 +140,15 @@ static inline void ssusb_soft_reset(void) clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } -__weak void mtk_usb_prepare(void) { /* do nothing */ } +__weak void mtk_usb_prepare(void) +{ + /* do nothing */ +} + +__weak void mtk_usb_adjust_phy_shift(void) +{ + /* do nothing */ +} void setup_usb_host(void) { @@ -153,5 +161,6 @@ void setup_usb_host(void) return; } u3phy_power_on(); + mtk_usb_adjust_phy_shift(); u3p_msg("phy power-on done.\n"); } diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 05bd27d277..4f8eff282e 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include +__weak void mtk_wdt_clr_status(void) { /* do nothing */ } + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -12,8 +15,9 @@ int mtk_wdt_init(void) /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); - if (CONFIG(CLEAR_WDT_MODE_REG)) - write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + mtk_wdt_clr_status(); + + printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta); printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { @@ -24,8 +28,11 @@ int mtk_wdt_init(void) * We trigger secondary reset by triggering WDT hardware to send signal to EC. * We do not use do_board_reset() to send signal to EC * which is controlled by software driver. + * Before triggering secondary reset, clean the data cache so the logs in cbmem + * console (either in SRAM or DRAM) can be flushed. */ - write32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + dcache_clean_all(); + setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); diff --git a/src/soc/mediatek/mt8173/da9212.c b/src/soc/mediatek/mt8173/da9212.c index e44a76f592..5028f18792 100644 --- a/src/soc/mediatek/mt8173/da9212.c +++ b/src/soc/mediatek/mt8173/da9212.c @@ -46,7 +46,7 @@ static void da9212_hw_init(uint8_t i2c_num, unsigned char variant_id) DA9212_BUCK_MODE_MASK, DA9212_BUCK_MODE_SHIFT); if (ret) - printk(BIOS_ERR, "ERROR: %s failed\n", __func__); + printk(BIOS_ERR, "%s failed\n", __func__); } @@ -74,7 +74,7 @@ void da9212_probe(uint8_t i2c_num) /* Check device ID is DA9212 */ if (device_id != DA9212_ID || ret) { - printk(BIOS_ERR, "ERROR: unknown DA9212 device_id\n"); + printk(BIOS_ERR, "unknown DA9212 device_id\n"); return; } diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 23a9403acf..10d03e0c8e 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -828,7 +828,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { - if ((testaudpat == 1) || (testaudpat == 2)) { + if ((testaudpat == 1) || (testaudpat == 2)) { /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 0145c4e9ce..fc5c58c0c6 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -591,7 +591,7 @@ u8 dramk_calcu_best_dly(u8 bit, struct dqs_perbit_dly *p, u8 *p_max_byte) if (hold == 0) { /* like this: (mean this bit is error) */ /* xxxxxxxxxxxxxxxxxxxxx|xxxxxxxxxxxxxxxxxxxxxxxxx */ - printk(BIOS_ERR, "ERROR, error bit %d, " + printk(BIOS_ERR, "Error at bit %d, " "setup_time = hold_time = 0!!\n", bit); fail = 1; } diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index ff803c3d3b..dd4629d909 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -6,9 +6,6 @@ #include #include #include -#include - -#define I2C_CLK_HZ (AXI_HZ / 16) struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ @@ -52,6 +49,9 @@ struct mtk_i2c mtk_i2c_bus_controller[7] = { } }; +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + #define I2CTAG "[I2C][PL] " #if CONFIG(DEBUG_I2C) diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index e6f0140367..02a21817d9 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8173_I2C_H #include +#include /* I2C Register */ struct mt_i2c_regs { @@ -35,6 +36,10 @@ struct mt_i2c_regs { uint32_t transfer_aux_len; }; +#define I2C_CLK_HZ (AXI_HZ / 16) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, debug_stat, 0x64); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8173/mt6311.c b/src/soc/mediatek/mt8173/mt6311.c index 3e61f8c399..05149dc46c 100644 --- a/src/soc/mediatek/mt8173/mt6311.c +++ b/src/soc/mediatek/mt8173/mt6311.c @@ -97,7 +97,7 @@ static void mt6311_hw_init(uint8_t i2c_num) MT6311_LDO_CON3, 0, 0x1, 0); if (ret) - printk(BIOS_ERR, "ERROR: %s failed\n", __func__); + printk(BIOS_ERR, "%s failed\n", __func__); } void mt6311_probe(uint8_t i2c_num) @@ -109,7 +109,7 @@ void mt6311_probe(uint8_t i2c_num) printk(BIOS_INFO, "%s: device ID = %#x\n", __func__, val); if (val < MT6311_E1_CID_CODE) { - printk(BIOS_ERR, "ERROR: unknown MT6311 device_id\n"); + printk(BIOS_ERR, "unknown MT6311 device_id\n"); return; } diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 3e53a72c5e..193f4b912b 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -2,12 +2,9 @@ #include #include -#include #include #include -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) - struct mtk_i2c mtk_i2c_bus_controller[] = { /* i2c0 setting */ { @@ -52,7 +49,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = { }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -103,7 +101,7 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus) } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -132,7 +130,7 @@ static void mtk_i2c_speed_init(uint8_t bus) void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h index e70cf47958..ebe75facce 100644 --- a/src/soc/mediatek/mt8183/include/soc/i2c.h +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_I2C_H #include +#include /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ struct mt_i2c_regs { uint32_t rollback; }; +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig new file mode 100644 index 0000000000..654baf20d0 --- /dev/null +++ b/src/soc/mediatek/mt8186/Kconfig @@ -0,0 +1,41 @@ +config SOC_MEDIATEK_MT8186 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE + select CACHE_MRC_SETTINGS + select HAVE_UART_SPECIAL + select SOC_MEDIATEK_COMMON + select MEDIATEK_BLOB_FAST_INIT + +if SOC_MEDIATEK_MT8186 + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + +config SPM_FIRMWARE + string + default "spm_firmware.bin" + help + The file name of the MediaTek SPM firmware. + +config SSPM_FIRMWARE + string + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + +config FLASH_DUAL_READ + bool + default y + help + When this option is enabled, the flash controller provides the ability + to dual IO read mode. + +endif diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc new file mode 100644 index 0000000000..0d56f15009 --- /dev/null +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -0,0 +1,99 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) + +bootblock-y += ../common/auxadc.c +bootblock-y += bootblock.c +bootblock-y += ../common/eint_event.c +bootblock-y += ../common/flash_controller.c +bootblock-y += gic.c +bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c +bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +bootblock-y += ../common/timer.c timer.c +bootblock-y += ../common/tracker.c ../common/tracker_v1.c +bootblock-y += ../common/uart.c +bootblock-y += ../common/wdt.c wdt.c + +verstage-y += ../common/auxadc.c +verstage-y += ../common/flash_controller.c +verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +verstage-y += ../common/timer.c timer.c +verstage-y += ../common/uart.c +verstage-y += ../common/wdt.c wdt.c + +romstage-y += ../common/auxadc.c +romstage-y += ../common/cbmem.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += emi.c +romstage-y += ../common/flash_controller.c +romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/memory.c +romstage-y += ../common/memory_test.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pll.c pll.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/timer.c timer.c +romstage-y += ../common/uart.c +romstage-y += ../common/wdt.c wdt.c +romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c + +ramstage-y += ../common/auxadc.c +ramstage-y += ../common/ddp.c ddp.c +ramstage-y += devapc.c +ramstage-y += ../common/dfd.c +ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c +ramstage-y += emi.c +ramstage-y += ../common/flash_controller.c +ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/mcu.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += soc.c +ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/sspm.c +ramstage-y += ../common/timer.c timer.c +ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/wdt.c wdt.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c + +BL31_MAKEARGS += PLAT=mt8186 + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +MT8186_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8186 + +mcu-firmware-files := \ + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_SPM_FIRMWARE) + +$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ + $(eval $(fw)-file := $(MT8186_BLOB_DIR)/$(fw)) \ + $(eval $(fw)-type := raw) \ + $(eval $(fw)-compression := LZ4) \ + $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \ +) + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8186_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c new file mode 100644 index 0000000000..e5d1e73047 --- /dev/null +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); + bustracker_init(); + mtk_wdt_init(); + mt_pll_init(); + unmask_eint_event_mask(); + mtk_gic_preinit(); +} diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c new file mode 100644 index 0000000000..6706ed7d00 --- /dev/null +++ b/src/soc/mediatek/mt8186/ddp.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#include +#include +#include +#include + +static void disp_config_main_path_connection(void) +{ + /* + * Main path: + * OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0->DITHER->DSI0 + */ + SET32_BITFIELDS(&mmsys_cfg->disp_ovl0_mout_en, + DISP_OVL0_MOUT_EN, DISP_OVL0_MOUT_TO_RDMA0); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sel_in, + DISP_RDMA0_SEL_IN, DISP_RDMA0_FROM_OVL0); + SET32_BITFIELDS(&mmsys_cfg->mmsys_ovl_con, + DISP_MMSYS_OVL0_CON, DISP_OVL0_GO_BLEND); + SET32_BITFIELDS(&mmsys_cfg->disp_rdma0_sout_sel, + DISP_RDMA0_SOUT_SEL, DISP_RDMA0_SOUT_TO_COLOR0); + SET32_BITFIELDS(&mmsys_cfg->disp_dither0_mout_en, + DISP_DITHER0_MOUT_EN, DISP_DITHER0_MOUT_TO_DSI0); + SET32_BITFIELDS(&mmsys_cfg->disp_dsi0_sel_in, + DISP_DSI0_SEL_IN, DISP_DSI0_FROM_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + SET32_BITFIELDS(&disp_ovl[idx]->datapath_con, + SMI_ID_EN, SMI_ID_EN_VAL); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + + write32(®s->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, 0); + SET32_BITFIELDS(®s->cfg, PQ_CFG_ENGINE_EN, PQ_ENGINE_EN); + + write32(®s->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + + write32(®s->size, width << 16 | height); + write32(®s->output_size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + SET32_BITFIELDS(®s->cfg, PQ_CFG_ENGINE_EN, 0); + + write32(®s->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + + write32(®s->size, width << 16 | height); + + /* Disable relay mode */ + SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, 0); + + write32(®s->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + + write32(®s->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(®s->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + + write32(®s->size, width << 16 | height); + + /* Enable relay mode */ + SET32_BITFIELDS(®s->cfg, PQ_CFG_RELAY_MODE, PQ_RELAY_MODE); + + write32(®s->en, PQ_EN); +} + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 pixel_clk = width * height * vrefresh; + + /* One ovl in main path */ + ovl_set_roi(0, width, height, 0xff0000ff); + ovl_layer_smi_id_en(0); + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + + /* Turn off M4U port */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s: display resolution: %ux%u@%u bpp %u\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s: invalid vrefresh; setting to %u\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); +} diff --git a/src/soc/mediatek/mt8186/devapc.c b/src/soc/mediatek/mt8186/devapc.c new file mode 100644 index 0000000000..541234fc04 --- /dev/null +++ b/src/soc/mediatek/mt8186/devapc.c @@ -0,0 +1,1325 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is created based on MT8169_DEVICE_APC_REG_DEVAPC_external.docx */ + +#include +#include +#include + +static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = { + /* 0 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPCKGEN", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_INFRASYS_CONFIG_REGS", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("IO_CFG_REG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ PERICFG", + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_EFUSAO_DEBUG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_GPIO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SLEEP_CONTROLLER", + NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOPRGU", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APXGPT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 10 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SEJ", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AP_CIRQ_EINT", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_APMIXEDSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIC_WRAP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_INFRA_PERI", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MM", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_KEYPAD", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_TOP_MISC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_ DVFS_CTRL_PROC", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_IFNRA_TOP_MBIST_CTRL", + NO_PROTECTION, FORBIDDEN7), + + /* 20 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DPMAIF_AO_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PMIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_AES_TOP_0", + FORBIDDEN, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SYS_TIMER", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MDEM_TEMP_SHARE", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_DEVICAPC_AO_MD", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SECURITY_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPMI_MST_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + + /* 30 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SPM", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_AP_DMA", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SYS_CIRQ", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICAPC", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBG_TRACKER", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + + /* 40 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF0_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF1_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_INFRA_PDN_REGISTER", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_TRNG", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DX_CC", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CQ_DMA", + NO_PROTECTION, FORBIDDEN7), + + /* 50 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF4_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, + NO_PROTECTION, FORBIDDEN4), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_SRAMROM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DEVICMPU_LOW", + SEC_RW_ONLY, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_EMI_MPU_REG", + SEC_RW_NS_R, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + + /* 60 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DPMAIF_TOP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH0_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + + /* 70 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_GCE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP0", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP1", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP2", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP4", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DRAMC_CH1_TOP6", + NO_PROTECTION, FORBIDDEN4, + NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_AP", + NO_PROTECTION, SEC_RW_NS_R, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF2_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + + /* 80 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_AP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_CCIF3_MD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_1", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_2", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_1_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_2", + SEC_RW_NS_R, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_3", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_4", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_5", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_6", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + + /* 90 */ + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_7", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_PWRMCU_8", + FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_SCP", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRA_AO_MCUCFG(*)", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("INFRASYS_DBUGSYS", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUXADC", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART0", + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C7", + NO_PROTECTION, FORBIDDEN7), + + /* 100 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C8", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PWM", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_PTP", + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN, + FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_BTIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C6", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_DISP_PWM", + NO_PROTECTION, FORBIDDEN7), + + /* 110 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI4", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_SPI5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C5", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_IMP_IIC_WRAP", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UART2", + NO_PROTECTION, FORBIDDEN7), + + /* 120 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_I2C9", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN5, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SUB", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC2", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MSDC3", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_UFS", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISUS_USB3.0_SIF2", + NO_PROTECTION, FORBIDDEN7), + + /* 130 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_USB_2.0_SIF(**)", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIO", + NO_PROTECTION, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("EAST_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ CSI_TOP_AO", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("EAST_ RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("SOUTH_RESERVE", + NO_PROTECTION, FORBIDDEN7), + + /* 140 */ + DAPC_INFRA_AO_SYS0_ATTR("WEST_MIPI_TX_CONFIG", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_MSDC1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("WEST_USB20_PHY", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN6), + DAPC_INFRA_AO_SYS0_ATTR("WEST_EFUSE", + NO_PROTECTION, SEC_RW_NS_R, NO_PROTECTION, FORBIDDEN5), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_UFS_MPHY", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_MSDC0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV0", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("NORTH_RESERV1", + NO_PROTECTION, FORBIDDEN7), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_CONN", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, + FORBIDDEN3, NO_PROTECTION), + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_MD1", + NO_PROTECTION, FORBIDDEN7), + + /* 150 */ + DAPC_INFRA_AO_SYS0_ATTR("PERISYS_AUDIODSP", + NO_PROTECTION, FORBIDDEN7), +}; + +/* module, AP permission, N/A, SSPM permission, N/A */ +static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = { + + /* 0 */ + DAPC_MM_AO_SYS0_ATTR("IP", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DFD", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D Secure Reg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D TestBench", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("G3D_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MMSYS_CONFIG", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_MUTEX0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 10 */ + DAPC_MM_AO_SYS0_ATTR("SMI_COMMON", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("SMI_LARB1", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_OVL0_2L", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_RSZ0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_COLOR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_CCORR0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 20 */ + DAPC_MM_AO_SYS0_ATTR("DISP_AAL0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_GAMMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_POSTMASK0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DITHER0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_DSC_WRAP0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DSI0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_WDMA0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 30 */ + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("MM_IOMMU_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("DISP_SMI_2X1_SUB_COMMON_U1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("IMG1_SMI_2X1_SUB_COMMON", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 40 */ + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mfb_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (wpe_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (mss_a)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 50 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys1_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 60 */ + DAPC_MM_AO_SYS0_ATTR("dip_a2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a10", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("dip_a11", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 70 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb9", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mfb_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("wpe_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mss_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 80 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("imgsys2_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 90 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b0)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_a8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b1)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b2)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b3)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b4)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b5)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b6)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b7)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b8)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 100 */ + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b9)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b10)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved (dip_b11)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb11", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved (smi_larb12)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 110 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 120 */ + DAPC_MM_AO_SYS0_ATTR("vdec_core0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_larb", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("vdec_core0_gcon", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("vdec_mini_mdp_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_global_con", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb7", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("venc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("jpgenc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 130 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("venc_mbist_ctrl", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb13", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb14", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_a", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_b", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_c", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 140 */ + DAPC_MM_AO_SYS0_ATTR("seninf_d", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_e", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_f", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_g", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("seninf_h", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_3x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_smi_4x1_sub_common_u0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb_16", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("smi_larb_17", + NO_PROTECTION4), + + /* 150 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 160 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 170 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 180 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 190 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_a_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 200 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_a_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 210 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_a_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 220 */ + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_ip_group_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_dma_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_0_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ltm_curve_b_1_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 230 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 240 */ + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_set_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("cam_raw_b_clr_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsys_b_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 250 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 260 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 270 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 280 */ + DAPC_MM_AO_SYS0_ATTR("camsv_3", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_5", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_2_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_3_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_4_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 290 */ + DAPC_MM_AO_SYS0_ATTR("camsv_5_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_6_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("camsv_7_inner", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("asg", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 300 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 310 */ + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("RESERVED", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdpsys_config", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 320 */ + DAPC_MM_AO_SYS0_ATTR("mdp_mutex0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb0", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("mdp_rdma0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_aal0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_hdr0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_rsz1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_wrot0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 330 */ + DAPC_MM_AO_SYS0_ATTR("mdp_wrot1", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("mdp_tdshp0", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipesys_top", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("fdvt", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("Reserved (fe)", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("rsc", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 340 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("ipe_smi_2x1_sub_common", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 350 */ + DAPC_MM_AO_SYS0_ATTR("smi_larb20", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("depth", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + + /* 360 */ + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION), + DAPC_MM_AO_SYS0_ATTR("smi_larb19", + NO_PROTECTION4), + DAPC_MM_AO_SYS0_ATTR("reserved", + NO_PROTECTION, NO_PROTECTION, FORBIDDEN, NO_PROTECTION) +}; + +static const enum domain_id domain_map[] = { + DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, + DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, + DOMAIN_8, DOMAIN_9, DOMAIN_10, DOMAIN_11, + DOMAIN_12, DOMAIN_13, DOMAIN_14, DOMAIN_15, +}; + +static inline void *getreg_domain(uintptr_t base, unsigned int offset, + enum domain_id domain_id, unsigned int index) +{ + return (void *)(base + offset + domain_id * 0x100 + index * 0x4); +} + +static inline void *getreg(uintptr_t base, unsigned int offset) +{ + return getreg_domain(base, offset, 0, 0); +} + +static void set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id, + enum devapc_perm_type perm) +{ + uint32_t apc_register_index; + uint32_t apc_set_index; + + apc_register_index = module / MOD_NO_IN_1_DEVAPC; + apc_set_index = module % MOD_NO_IN_1_DEVAPC; + + clrsetbits32(getreg_domain(base, 0, domain_id, apc_register_index), + 0x3 << (apc_set_index * 2), + perm << (apc_set_index * 2)); +} + +static void set_infra_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(infra_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(infra_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + infra_ao_sys0_devices[i].d_permission[j]); + + /* + * Extra apc setting. + * Block debugsys to avoid privilege escalation. + */ + if (!CONFIG(CONSOLE_SERIAL)) + set_module_apc(base + SYS0_D0_APC_0, DEVAPC_DEBUGSYS_INDEX, + DOMAIN_0, SEC_RW_NS_R); +} + +static void set_mm_ao_apc(uintptr_t base) +{ + int i, j; + + for (i = 0; i < ARRAY_SIZE(mm_ao_sys0_devices); i++) + for (j = 0; j < ARRAY_SIZE(mm_ao_sys0_devices[i].d_permission); j++) + set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j], + mm_ao_sys0_devices[i].d_permission[j]); +} + +static void dump_infra_ao_apc(uintptr_t base) +{ + int reg_max; + unsigned int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(infra_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void dump_mm_ao_apc(uintptr_t base) +{ + int reg_max; + unsigned int d, i; + + reg_max = DIV_ROUND_UP(ARRAY_SIZE(mm_ao_sys0_devices), MOD_NO_IN_1_DEVAPC); + for (d = 0; d < DOM_NUM_MM_AO_SYS0; d++) + for (i = 0; i < reg_max; i++) + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO_SYS0)D%d_APC_%d: %#x\n", d, i, + read32(getreg_domain(base, SYS0_D0_APC_0, d, i))); + + printk(BIOS_DEBUG, "[DEVAPC] (MM_AO)MAS_SEC_0: %#x\n", + read32(getreg(base, MAS_SEC_0))); +} + +static void infra_init(uintptr_t base) +{ + /* Side band */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS); + + /* Default APC Setting */ + set_infra_ao_apc(base); +} + +static void mm_init(uintptr_t base) +{ + /* Default APC Setting */ + set_mm_ao_apc(base); +} + +struct devapc_init_ops { + uintptr_t base; + void (*init)(uintptr_t base); + void (*dump)(uintptr_t base); +} devapc_init[] = { + { DEVAPC_AO_INFRA_PERI_BASE, infra_init, dump_infra_ao_apc }, + { DEVAPC_AO_MM_BASE, mm_init, dump_mm_ao_apc }, +}; + +void dapc_init(void) +{ + unsigned int i; + uintptr_t devapc_ao_base; + + for (i = 0; i < ARRAY_SIZE(devapc_init); i++) { + devapc_ao_base = devapc_init[i].base; + + /* Init dapc */ + write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); + + /* Initialization */ + if (devapc_init[i].init) + devapc_init[i].init(devapc_ao_base); + + /* Dump Setting */ + if (devapc_init[i].dump) + devapc_init[i].dump(devapc_ao_base); + } +} diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c new file mode 100644 index 0000000000..48a7b3ef07 --- /dev/null +++ b/src/soc/mediatek/mt8186/emi.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.8 + */ + +#include + +size_t sdram_size(void) +{ + return (size_t)4 * GiB; +} + +void mt_set_emi(struct dramc_param *dparam) +{ + /* Do nothing */ +} diff --git a/src/soc/mediatek/mt8186/gic.c b/src/soc/mediatek/mt8186/gic.c new file mode 100644 index 0000000000..ac077647af --- /dev/null +++ b/src/soc/mediatek/mt8186/gic.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.3 + */ + +#include +#include +#include + +void mtk_gic_preinit(void) +{ + int i; + + for (i = 3; i < 15; i++) { + write32((void *)((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); + write32((void *)((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); + } +} diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c new file mode 100644 index 0000000000..bd3ab6596c --- /dev/null +++ b/src/soc/mediatek/mt8186/gpio.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#include +#include + +static void *gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + switch (gpio.base & 0x0f) { + case 1: + reg_addr = (void *)IOCFG_LT_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_LB_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_BL_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_RB_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_RT_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, BIT(bit)); + else + clrbits32(reg1, BIT(bit)); + } + + if (enable == GPIO_PULL_ENABLE) { + setbits32(reg2, 1 << bit); + } else { + clrbits32(reg2, 1 << bit); + clrbits32(reg2 + 0x010, BIT(bit)); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, BIT(bit)); + setbits32(reg2, BIT(bit)); + } else { + clrbits32(reg2, BIT(bit)); + setbits32(reg1, BIT(bit)); + } + } else { + clrbits32(reg1, BIT(bit)); + clrbits32(reg2, BIT(bit)); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c new file mode 100644 index 0000000000..8345637008 --- /dev/null +++ b/src/soc/mediatek/mt8186/i2c.c @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#include +#include +#include +#include +#include +#include + +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C0_BASE), + .i2c_dma_regs = (void *)(I2C0_DMA_BASE), + }, + [1] = { + .i2c_regs = (void *)(I2C1_BASE), + .i2c_dma_regs = (void *)(I2C1_DMA_BASE), + }, + [2] = { + .i2c_regs = (void *)(I2C2_BASE), + .i2c_dma_regs = (void *)(I2C2_DMA_BASE), + }, + [3] = { + .i2c_regs = (void *)(I2C3_BASE), + .i2c_dma_regs = (void *)(I2C3_DMA_BASE), + }, + [4] = { + .i2c_regs = (void *)(I2C4_BASE), + .i2c_dma_regs = (void *)(I2C4_DMA_BASE), + }, + [5] = { + .i2c_regs = (void *)(I2C5_BASE), + .i2c_dma_regs = (void *)(I2C5_DMA_BASE), + }, + [6] = { + .i2c_regs = (void *)(I2C6_BASE), + .i2c_dma_regs = (void *)(I2C6_DMA_BASE), + }, + [7] = { + .i2c_regs = (void *)(I2C7_BASE), + .i2c_dma_regs = (void *)(I2C7_DMA_BASE), + }, + [8] = { + .i2c_regs = (void *)(I2C8_BASE), + .i2c_dma_regs = (void *)(I2C8_DMA_BASE), + }, + [9] = { + .i2c_regs = (void *)(I2C9_BASE), + .i2c_dma_regs = (void *)(I2C9_DMA_BASE), + }, +}; + +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + [6] = { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + [7] = { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + [8] = { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + [9] = { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) +{ + mtk_i2c_speed_init(bus, speed); + mtk_i2c_set_gpio_pinmux(bus); +} + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n", + read32(®s->ltiming), + read32(®s->clock_div)); +} + +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + write32(®s->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(®s->timing, bus_ctrl->ac_timing.htiming); + write32(®s->ltiming, bus_ctrl->ac_timing.ltiming); + write32(®s->hs, bus_ctrl->ac_timing.hs); + write32(®s->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h new file mode 100644 index 0000000000..c90e0cda79 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ +#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__ + +enum { + MCUSYS_BASE = 0x0C530000, + IO_PHYS = 0x10000000, +}; + +enum { + MCUCFG_BASE = MCUSYS_BASE + 0x00008000, +}; + +enum { + CKSYS_BASE = IO_PHYS + 0x00000000, + INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + IOCFG_LT_BASE = IO_PHYS + 0x00002000, + IOCFG_LM_BASE = IO_PHYS + 0x00002200, + IOCFG_LB_BASE = IO_PHYS + 0x00002400, + IOCFG_BL_BASE = IO_PHYS + 0x00002600, + IOCFG_RB_BASE = IO_PHYS + 0x00002A00, + IOCFG_RT_BASE = IO_PHYS + 0x00002C00, + GPIO_BASE = IO_PHYS + 0x00005000, + SPM_BASE = IO_PHYS + 0x00006000, + RGU_BASE = IO_PHYS + 0x00007000, + GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, + APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, + DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, + DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, + SYSTIMER_BASE = IO_PHYS + 0x00017000, + I2C0_DMA_BASE = IO_PHYS + 0x00200100, + I2C1_DMA_BASE = IO_PHYS + 0x00200200, + I2C2_DMA_BASE = IO_PHYS + 0x00200300, + I2C3_DMA_BASE = IO_PHYS + 0x00200480, + I2C4_DMA_BASE = IO_PHYS + 0x00200580, + I2C5_DMA_BASE = IO_PHYS + 0x00200700, + I2C6_DMA_BASE = IO_PHYS + 0x00200800, + I2C7_DMA_BASE = IO_PHYS + 0x00200900, + I2C8_DMA_BASE = IO_PHYS + 0x00200A80, + I2C9_DMA_BASE = IO_PHYS + 0x00200C00, + DEVAPC_BASE = IO_PHYS + 0x00207000, + DBG_TRACKER_BASE = IO_PHYS + 0x00208000, + EMI0_BASE = IO_PHYS + 0x00219000, + EMI0_MPU_BASE = IO_PHYS + 0x0021B000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, + SFLASH_REG_BASE = IO_PHYS + 0x01000000, + AUXADC_BASE = IO_PHYS + 0x01001000, + UART0_BASE = IO_PHYS + 0x01002000, + I2C7_BASE = IO_PHYS + 0x01004000, + I2C8_BASE = IO_PHYS + 0x01005000, + I2C0_BASE = IO_PHYS + 0x01007000, + I2C1_BASE = IO_PHYS + 0x01008000, + I2C2_BASE = IO_PHYS + 0x01009000, + SPI0_BASE = IO_PHYS + 0x0100A000, + I2C6_BASE = IO_PHYS + 0x0100D000, + I2C3_BASE = IO_PHYS + 0x0100F000, + SPI1_BASE = IO_PHYS + 0x01010000, + I2C4_BASE = IO_PHYS + 0x01011000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01014000, + SPI5_BASE = IO_PHYS + 0x01015000, + I2C5_BASE = IO_PHYS + 0x01016000, + I2C9_BASE = IO_PHYS + 0x01019000, + /* Corsola uses USB2 port1 instead of USB2 port0. */ + SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, + MSDC0_BASE = IO_PHYS + 0x01230000, + /* Corsola uses USB2 port1 instead of USB2 port0. */ + SSUSB_SIF_BASE = IO_PHYS + 0x01C80300, + EFUSEC_BASE = IO_PHYS + 0x01CB0000, + MIPITX_BASE = IO_PHYS + 0x01CC0000, + MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, + SMI_BASE = IO_PHYS + 0x04002000, + SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, + DISP_OVL1_BASE = IO_PHYS + 0x04006000, + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400B000, + DISP_AAL0_BASE = IO_PHYS + 0x0400C000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400D000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400E000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400F000, + DSI0_BASE = IO_PHYS + 0x04013000, +}; +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/auxadc.h b/src/soc/mediatek/mt8186/include/soc/auxadc.h new file mode 100644 index 0000000000..13a52e3f9d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/auxadc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_AUXADC_H +#define SOC_MEDIATEK_MT8186_AUXADC_H + +#include +#include +#include + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8186_infracfg_ao_regs *const mtk_infracfg = mt8186_infracfg_ao; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h new file mode 100644 index 0000000000..e66563d9a0 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/ddp.h @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_DDP_H +#define SOC_MEDIATEK_MT8186_DDP_H + +#include +#include +#include +#include + +#define SMI_LARB_PORT_L0_OVL_RDMA0 0x388 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10c; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11c[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1ac[853]; /* 0x1AC */ + u32 reserved_0xf00; /* 0xF00 */ + u32 mmsys_ovl_con; /* 0xF04 */ + u32 reserved_0xf08; /* 0xF08 */ + u32 disp_rdma0_sout_sel; /* 0xF0C */ + u32 reserved_0xf10; /* 0xF10 */ + u32 disp_ovl0_2l_mout_en; /* 0xF14 */ + u32 disp_ovl0_mout_en; /* 0xF18 */ + u32 reserved_0xf1c; /* 0xF1C */ + u32 disp_dither0_mout_en; /* 0xF20 */ + u32 reserved_0xf24; /* 0xF24 */ + u32 disp_rdma0_sel_in; /* 0xF28 */ + u32 reserved_0xf2c; /* 0xF2C */ + u32 disp_dsi0_sel_in; /* 0xF30 */ + u32 reserved_0xf34[2]; /* 0xF34 */ + u32 disp_rdma1_mout_en; /* 0xF3C */ + u32 disp_rdma1_sel_in; /* 0xF40 */ + u32 disp_dpi0_sel_in; /* 0xF44 */ +}; +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_con, 0xF04); +check_member(mmsys_cfg_regs, disp_rdma0_sout_sel, 0xF0C); +check_member(mmsys_cfg_regs, disp_ovl0_mout_en, 0xF18); +check_member(mmsys_cfg_regs, disp_dither0_mout_en, 0xF20); +check_member(mmsys_cfg_regs, disp_rdma0_sel_in, 0xF28); +check_member(mmsys_cfg_regs, disp_dsi0_sel_in, 0xF30); + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[16]; +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 disp_dither_0; +}; +check_member(disp_dither_regs, disp_dither_0, 0x100); + +/* + * DISP_REG_CONFIG_MMSYS_CG_CON0 + * Configures free-run clock gating 0 + * 0: Enable clock + * 1: Clock gating + */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_APB_MM_BUS = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_WDMA0 = BIT(5), + CG_CON0_DISP_RSZ0 = BIT(7), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_COLOR0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(13), + CG_CON0_DISP_POSTMASK0 = BIT(14), + CG_CON0_DISP_DITHER0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + CG_CON0_DISP_DSI0 = BIT(19), + CG_CON0_DISP_FAKE_ENG0 = BIT(20), + CG_CON0_DISP_FAKE_ENG1 = BIT(21), + CG_CON0_SMI_GALS = BIT(22), + CG_CON0_SMI_IOMMU = BIT(24), + CG_CON0_DISP_ALL = CG_CON0_DISP_MUTEX0 | + CG_CON0_APB_MM_BUS | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_SMI_INFRA | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_SMI_COMMON | + CG_CON0_DISP_DSI0 | + CG_CON0_SMI_GALS | + CG_CON0_SMI_IOMMU, + CG_CON0_ALL = 0xFFFFFFFF, +}; + +enum { + CG_CON2_DSI0_DSI_CK_DOMAIN = BIT(0), + CG_CON2_DISP_26M = BIT(10), + CG_CON2_DISP_ALL = CG_CON2_DSI0_DSI_CK_DOMAIN | + CG_CON2_DISP_26M, + CG_CON2_ALL = 0xFFFFFFFF, +}; + +DEFINE_BITFIELD(DISP_OVL0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_RDMA0_SEL_IN, 3, 0) +DEFINE_BITFIELD(DISP_MMSYS_OVL0_CON, 1, 0) +DEFINE_BITFIELD(DISP_RDMA0_SOUT_SEL, 3, 0) +DEFINE_BITFIELD(DISP_DITHER0_MOUT_EN, 3, 0) +DEFINE_BITFIELD(DISP_DSI0_SEL_IN, 3, 0) + +DEFINE_BIT(SMI_ID_EN, 0) +DEFINE_BIT(PQ_CFG_RELAY_MODE, 0) +DEFINE_BIT(PQ_CFG_ENGINE_EN, 1) + +#define DISP_OVL0_MOUT_TO_RDMA0 BIT(0) +#define DISP_RDMA0_FROM_OVL0 0 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_RDMA0_SOUT_TO_COLOR0 1 +#define DISP_DITHER0_MOUT_TO_DSI0 BIT(0) +#define DISP_DSI0_FROM_DITHER0 1 + +#define SMI_ID_EN_VAL BIT(0) + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(7), + MUTEX_MOD_DISP_GAMMA0 = BIT(8), + MUTEX_MOD_DISP_POSTMASK0 = BIT(9), + MUTEX_MOD_DISP_DITHER0 = BIT(10), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +#define PQ_EN BIT(0) +#define PQ_RELAY_MODE BIT(0) +#define PQ_ENGINE_EN BIT(1) + +static struct mmsys_cfg_regs *const mmsys_cfg = (void *)MMSYS_BASE; +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/devapc.h b/src/soc/mediatek/mt8186/include/soc/devapc.h new file mode 100644 index 0000000000..0a77e37f03 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/devapc.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is created based on MT8169_DEVICE_APC_REG_DEVAPC_external.docx */ + +#ifndef SOC_MEDIATEK_MT8186_DEVAPC_H +#define SOC_MEDIATEK_MT8186_DEVAPC_H + +#include +#include + +void dapc_init(void); + +enum devapc_ao_offset { + SYS0_D0_APC_0 = 0x0, + DOM_REMAP_0_0 = 0xD00, + DOM_REMAP_1_0 = 0xD04, + MAS_DOM_0 = 0x0A00, + MAS_SEC_0 = 0x0B00, + AO_APC_CON = 0x0F00, +}; + +/****************************************************************************** + * STRUCTURE DEFINITION + ******************************************************************************/ +/* Common */ +enum trans_type { + NON_SECURE_TRANS = 0, + SECURE_TRANS, +}; + +enum devapc_perm_type { + NO_PROTECTION = 0, + SEC_RW_ONLY, + SEC_RW_NS_R, + FORBIDDEN, + PERM_NUM, +}; + +enum domain_id { + DOMAIN_0 = 0, + DOMAIN_1, + DOMAIN_2, + DOMAIN_3, + DOMAIN_4, + DOMAIN_5, + DOMAIN_6, + DOMAIN_7, + DOMAIN_8, + DOMAIN_9, + DOMAIN_10, + DOMAIN_11, + DOMAIN_12, + DOMAIN_13, + DOMAIN_14, + DOMAIN_15, +}; + +struct apc_infra_peri_dom_16 { + unsigned char d_permission[16]; +}; + +struct apc_infra_peri_dom_8 { + unsigned char d_permission[8]; +}; + +struct apc_infra_peri_dom_4 { + unsigned char d_permission[4]; +}; + +enum devapc_sys_dom_num { + DOM_NUM_INFRA_AO_SYS0 = 8, + DOM_NUM_MM_AO_SYS0 = 4, +}; + +enum devapc_cfg_index { + DEVAPC_DEBUGSYS_INDEX = 94, +}; + +/* PERM_ATTR MACRO */ +#define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_8(__VA_ARGS__) } } +#define DAPC_MM_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } + +/****************************************************************************** + * Variable DEFINITION + ******************************************************************************/ +#define MOD_NO_IN_1_DEVAPC 16 + +/****************************************************************************** + * Bit Field DEFINITION + ******************************************************************************/ +DEFINE_BIT(SCP_SSPM_SEC, 21) + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/dfd.h b/src/soc/mediatek/mt8186/include/soc/dfd.h new file mode 100644 index 0000000000..b2f1388693 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dfd.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_DFD_H +#define SOC_MEDIATEK_MT8186_DFD_H + +#include + +/* DFD dump address and size need to be the same as defined in Kernel DTS. */ +#define DFD_DUMP_ADDRESS 0x6A000000 +#define DFD_DUMP_SIZE (1 * MiB) + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h new file mode 100644 index 0000000000..2d6212b169 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include +#include +#include +#include + +#define DRAMC_PARAM_HEADER_VERSION 1 + +struct sdram_params { + /* Sometimes, we may need to compare params member + * between coreboot and blob for analysis. Here, + * add member size using xxxB. + */ + /* 4 + 4 = 8B */ + u32 rank_num; + u16 num_dlycell_perT; + u16 delay_cell_timex100; + + /* duty 16B */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* CBT 48B */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; + + /* write leveling 8B */ + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* Gating 32B */ + u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* TX perbit 164B */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat 4B */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit 88B */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* TX OE 16B */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +const struct sdram_info *get_sdram_config(void); +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int initialize_dramc_param(void *blob); + +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h new file mode 100644 index 0000000000..5602e144cb --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +typedef enum { + RANK_SINGLE = 1, + RANK_DUAL, +} DRAM_RANK_NUMBER_T; + +/* DRAM SHUFFLE RG type */ +typedef enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_4, + DRAM_DFS_SHUFFLE_5, + DRAM_DFS_SHUFFLE_6, + DRAM_DFS_SHUFFLE_7, + DRAM_DFS_SHUFFLE_8, + DRAM_DFS_SHUFFLE_9, + DRAM_DFS_SHUFFLE_10, + DRAM_DFS_SHUFFLE_MAX, +} DRAM_DFS_SHUFFLE_TYPE_T; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +typedef enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1, +} DRAM_CBT_MODE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX + +#define DQS_NUMBER_LP4 2 +#define DQS_BIT_NUMBER 8 +#define DQ_DATA_WIDTH_LP4 16 + +#endif /* __SOC_MEDIATEK_MT8186_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h new file mode 100644 index 0000000000..2cb9159350 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/dsi.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 6.9 + */ + +#ifndef SOC_MEDIATEK_MT8186_DSI_H +#define SOC_MEDIATEK_MT8186_DSI_H + +#include + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/efuse.h b/src/soc/mediatek/mt8186/include/soc/efuse.h new file mode 100644 index 0000000000..fe3dfff9aa --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_EFUSE_H +#define SOC_MEDIATEK_MT8186_EFUSE_H + +#include +#include + +struct efuse_regs { + uint32_t reserved[130]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x208); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gic.h b/src/soc/mediatek/mt8186/include/soc/gic.h new file mode 100644 index 0000000000..7e11107717 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gic.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.3 + */ + +#ifndef SOC_MEDIATEK_MT8186_GIC_H +#define SOC_MEDIATEK_MT8186_GIC_H + +void mtk_gic_preinit(void); + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h new file mode 100644 index 0000000000..a47d27c96d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -0,0 +1,626 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_GPIO_H +#define SOC_MEDIATEK_MT8186_GPIO_H + +#include +#include +#include + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +#define PIN(id, name, flag, bit, base, offset, \ + func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FLAG = flag, \ + PAD_##name##_BIT = bit, \ + PAD_##name##_BASE = base, \ + PAD_##name##_OFFSET = offset, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +#define GPIO(name) ((gpio_t){ \ + .id = PAD_##name##_ID, \ + .flag = PAD_##name##_FLAG, \ + .bit = PAD_##name##_BIT, \ + .base = PAD_##name##_BASE, \ + .offset = PAD_##name##_OFFSET \ + }) + +enum { + PIN(0, EINT0, 0, 13, 0x16, 0x50, + I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0, + SCP_SPI0_CK, TP_GPIO0_AO, dbg_mon_a0), + PIN(1, EINT1, 0, 14, 0x16, 0x50, + I2S0_BCK, SPI0_CSB_B, I2S2_BCK, CMFLASH1, + SCP_SPI0_CS, TP_GPIO1_AO, RES7), + PIN(2, EINT2, 0, 17, 0x16, 0x50, + I2S0_LRCK, SPI0_MO_B, I2S2_LRCK, CMFLASH2, + SCP_SPI0_MO, TP_GPIO2_AO, RES7), + PIN(3, EINT3, 0, 18, 0x16, 0x50, + I2S0_DI, SPI0_MI_B, I2S2_DI, SRCLKENAI1, + SCP_SPI0_MI, TP_GPIO3_AO, RES7), + PIN(4, EINT4, 0, 19, 0x16, 0x50, + I2S3_DO, RES2, I2S1_DO, RES4, + RES5, TP_GPIO4_AO, RES7), + PIN(5, EINT5, 0, 20, 0x16, 0x50, + EXT_FRAME_SYNC, RES2, RES3, RES4, + RES5, TP_GPIO5_AO, RES7), + PIN(6, EINT6, 0, 19, 0x24, 0x60, + I2S3_MCK, SPI1_CLK_B, I2S1_MCK, DPI_DATA22, + RES5, TP_GPIO6_AO, RES7), + PIN(7, EINT7, 0, 20, 0x24, 0x60, + I2S3_BCK, SPI1_CSB_B, I2S1_BCK, DPI_DATA23, + RES5, TP_GPIO7_AO, RES7), + PIN(8, EINT8, 0, 21, 0x24, 0x60, + I2S3_LRCK, SPI1_MO_B, I2S1_LRCK, CONN_UART0_RXD, + SSPM_URXD_AO, ADSP_UART_RX, CONN_MCU_DBGACK_N), + PIN(9, EINT9, 0, 22, 0x24, 0x60, + I2S3_DO, SPI1_MI_B, I2S1_DO, CONN_UART0_TXD, + SSPM_UTXD_AO, ADSP_UART_TX, CONN_MCU_DBGI_N), + PIN(10, EINT10, 0, 16, 0x24, 0x60, + I2S0_MCK, SPI4_CLK_A, I2S2_MCK, SPM_JTAG_TDI, + SCP_JTAG_TDI, ADSP_JTAG_TDI, CONN_MCU_TDI), + PIN(11, EINT11, 0, 17, 0x24, 0x60, + I2S0_BCK, SPI4_CSB_A, I2S2_BCK, SPM_JTAG_TRSTN, + SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, CONN_MCU_TRST_B), + PIN(12, EINT12, 0, 18, 0x24, 0x60, + I2S0_LRCK, SPI4_MO_A, I2S2_LRCK, SPM_JTAG_TCK, + SCP_JTAG_TCK, ADSP_JTAG_TCK, CONN_MCU_TCK), + PIN(13, EINT13, 0, 0, 0x23, 0x80, + I2S0_DI, SPI4_MI_A, I2S2_DI, SPM_JTAG_TDO, + SCP_JTAG_TDO, ADSP_JTAG_TDO, CONN_MCU_TDO), + PIN(14, EINT14, 0, 1, 0x23, 0x80, + RES1, RES2, CLKM0, SPM_JTAG_TMS, + SCP_JTAG_TMS, ADSP_JTAG_TMS, CONN_MCU_TMS), + PIN(15, EINT15, 0, 15, 0x16, 0x50, + EXT_FRAME_SYNC, SRCLKENAI1, CLKM1, PWM0, + RES5, RES6, RES7), + PIN(16, EINT16, 0, 16, 0x16, 0x50, + CONN_WIFI_TXD, SRCLKENAI0, CLKM2, PWM1, + RES5, RES6, RES7), + PIN(17, EINT17, 0, 9, 0x25, 0x90, + RES1, RES2, CLKM3, PWM2, + RES5, RES6, dbg_mon_a32), + PIN(18, EINT18, 0, 10, 0x25, 0x90, + RES1, CMVREF0, RES3, RES4, + RES5, SPI2_CLK_B, dbg_mon_a26), + PIN(19, CAM_PDN0, 0, 3, 0x25, 0x90, + RES1, CMVREF1, RES3, RES4, + ANT_SEL3, SPI2_CSB_B, dbg_mon_a2), + PIN(20, CAM_RST0, 0, 6, 0x25, 0x90, + RES1, CMVREF2, RES3, RES4, + ANT_SEL4, SPI2_MO_B, dbg_mon_a3), + PIN(21, CAM_PDN1, 0, 4, 0x25, 0x90, + I2S0_MCK, I2S1_MCK, I2S3_MCK, RES4, + ANT_SEL5, SPI2_MI_B, dbg_mon_a4), + PIN(22, CAM_RST1, 0, 7, 0x25, 0x90, + I2S0_BCK, I2S1_BCK, I2S3_BCK, TDM_RX_LRCK, + ANT_SEL6, RES6, dbg_mon_a5), + PIN(23, CAM_PDN2, 0, 5, 0x25, 0x90, + I2S0_LRCK, I2S1_LRCK, I2S3_LRCK, TDM_RX_BCK, + ANT_SEL7, RES6, dbg_mon_a6), + PIN(24, CAM_RST2, 0, 8, 0x25, 0x90, + I2S0_DI, I2S1_DO, I2S3_DO, TDM_RX_MCK, + RES5, RES6, dbg_mon_a7), + PIN(25, I2S2_MCK, 0, 18, 0x25, 0x90, + I2S2_MCK, PCM_CLK, SPI4_CLK_B, TDM_RX_DATA0, + RES5, RES6, dbg_mon_a8), + PIN(26, I2S2_BCK, 0, 15, 0x25, 0x90, + I2S2_BCK, PCM_SYNC, SPI4_CSB_B, TDM_RX_DATA1, + RES5, RES6, dbg_mon_a9), + PIN(27, I2S2_LRCK, 0, 17, 0x25, 0x90, + I2S2_LRCK, PCM_DI, SPI4_MO_B, TDM_RX_DATA2, + RES5, RES6, dbg_mon_a10), + PIN(28, I2S2_DI, 0, 16, 0x25, 0x90, + I2S2_DI, PCM_DO, SPI4_MI_B, TDM_RX_DATA3, + RES5, RES6, RES7), + PIN(29, ANT_SEL0, 0, 0, 0x16, 0x50, + ANT_SEL0, GPS_L1_ELNA_EN, RES3, RES4, + RES5, RES6, RES7), + PIN(30, ANT_SEL1, 0, 1, 0x16, 0x50, + ANT_SEL1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(31, ANT_SEL2, 0, 2, 0x16, 0x50, + ANT_SEL2, EXT_FRAME_SYNC, SRCLKENAI1, RES4, + RES5, RES6, RES7), + PIN(32, URXD0, 0, 25, 0x12, 0x60, + URXD0, UTXD0, ADSP_UART_RX, TP_URXD1_AO, + RES5, RES6, RES7), + PIN(33, UTXD0, 0, 27, 0x12, 0x60, + UTXD0, URXD0, ADSP_UART_TX, TP_UTXD1_AO, + RES5, RES6, RES7), + PIN(34, URXD1, 0, 26, 0x12, 0x60, + URXD1, TP_URXD2_AO, SSPM_URXD_AO, ADSP_UART_RX, + CONN_UART0_RXD, RES6, RES7), + PIN(35, UTXD1, 0, 28, 0x12, 0x60, + UTXD1, TP_UTXD2_AO, SSPM_UTXD_AO, ADSP_UART_TX, + CONN_UART0_TXD, CONN_WIFI_TXD, RES7), + PIN(36, SPI0_CLK, 0, 9, 0x12, 0x60, + SPI0_CLK_A, CLKM0, RES3, SCP_SPI0_CK, + SPINOR_CK, RES6, dbg_mon_a11), + PIN(37, SPI0_CSB, 0, 10, 0x12, 0x60, + SPI0_CSB_A, CLKM1, PWM0, SCP_SPI0_CS, + SPINOR_CS, RES6, dbg_mon_a12), + PIN(38, SPI0_MO, 0, 12, 0x12, 0x60, + SPI0_MO_A, CLKM2, PWM1, SCP_SPI0_MO, + SPINOR_IO0, RES6, dbg_mon_a13), + PIN(39, SPI0_MI, 0, 11, 0x12, 0x60, + SPI0_MI_A, CLKM3, PWM2, SCP_SPI0_MI, + SPINOR_IO1, RES6, dbg_mon_a14), + PIN(40, SPI1_CLK, 0, 13, 0x12, 0x60, + SPI1_CLK_A, SCP_SPI1_CK, RES3, UCTS0, + SPINOR_IO2, TP_UCTS1_AO, dbg_mon_a15), + PIN(41, SPI1_CSB, 0, 14, 0x12, 0x60, + SPI1_CSB_A, SCP_SPI1_CS, PWM0, URTS0, + SPINOR_IO3, TP_URTS1_AO, dbg_mon_a16), + PIN(42, SPI1_MO, 0, 16, 0x12, 0x60, + SPI1_MO_A, SCP_SPI1_MO, PWM1, UCTS1, + RES5, TP_UCTS2_AO, dbg_mon_a17), + PIN(43, SPI1_MI, 0, 15, 0x12, 0x60, + SPI1_MI_A, SCP_SPI1_MI, PWM2, URTS1, + RES5, TP_URTS2_AO, dbg_mon_a18), + PIN(44, SPI2_CK, 0, 28, 0x25, 0x90, + SPI2_CLK_A, SCP_SPI0_CK, RES3, RES4, + RES5, RES6, dbg_mon_a19), + PIN(45, SPI2_CSB, 0, 29, 0x25, 0x90, + SPI2_CSB_A, SCP_SPI0_CS, RES3, RES4, + RES5, RES6, dbg_mon_a20), + PIN(46, SPI2_MO, 0, 31, 0x25, 0x90, + SPI2_MO_A, SCP_SPI0_MO, RES3, RES4, + RES5, RES6, dbg_mon_a21), + PIN(47, SPI2_MI, 0, 30, 0x25, 0x90, + SPI2_MI_A, SCP_SPI0_MI, RES3, RES4, + RES5, RES6, dbg_mon_a22), + PIN(48, SPI3_CLK, 0, 17, 0x12, 0x60, + SPI3_CLK, TP_URXD1_AO, TP_URXD2_AO, URXD1, + I2S2_MCK, SCP_SPI0_CK, RES7), + PIN(49, SPI3_CSB, 0, 18, 0x12, 0x60, + SPI3_CSB, TP_UTXD1_AO, TP_UTXD2_AO, UTXD1, + I2S2_BCK, SCP_SPI0_CS, RES7), + PIN(50, SPI3_MO, 0, 20, 0x12, 0x60, + SPI3_MO, RES2, RES3, RES4, + I2S2_LRCK, SCP_SPI0_MO, RES7), + PIN(51, SPI3_MI, 0, 19, 0x12, 0x60, + SPI3_MI, RES2, RES3, RES4, + I2S2_DI, SCP_SPI0_MI, RES7), + PIN(52, SPI5_CLK, 0, 12, 0x23, 0x80, + SPI5_CLK, I2S2_MCK, I2S1_MCK, SCP_SPI1_CK, + LVTS_26M, DFD_TCK_XI, dbg_mon_b30), + PIN(53, SPI5_CSB, 0, 13, 0x23, 0x80, + SPI5_CSB, I2S2_BCK, I2S1_BCK, SCP_SPI1_CS, + LVTS_FOUT, DFD_TDI, dbg_mon_b31), + PIN(54, SPI5_MO, 0, 15, 0x23, 0x80, + SPI5_MO, I2S2_LRCK, I2S1_LRCK, SCP_SPI1_MO, + LVTS_SCK, DFD_TDO, dbg_mon_a1), + PIN(55, SPI5_MI, 0, 14, 0x23, 0x80, + SPI5_MI, I2S2_DI, I2S1_DO, SCP_SPI1_MI, + LVTS_SDO, DFD_TMS, dbg_mon_b32), + PIN(56, I2S1_DO, 0, 12, 0x25, 0x90, + I2S1_DO, I2S3_DO, RES3, RES4, + RES5, RES6, dbg_mon_a23), + PIN(57, I2S1_BCK, 0, 11, 0x25, 0x90, + I2S1_BCK, I2S3_BCK, RES3, RES4, + RES5, RES6, dbg_mon_a24), + PIN(58, I2S1_LRCK, 0, 13, 0x25, 0x90, + I2S1_LRCK, I2S3_LRCK, RES3, RES4, + RES5, RES6, dbg_mon_a25), + PIN(59, I2S1_MCK, 0, 14, 0x25, 0x90, + I2S1_MCK, I2S3_MCK, RES3, RES4, + RES5, RES6, dbg_mon_a27), + PIN(60, TDM_RX_LRCK, 0, 21, 0x23, 0x80, + TDM_RX_LRCK, ANT_SEL3, RES3, RES4, + CONN_MCU_DBGACK_N, RES6, RES7), + PIN(61, TDM_RX_BCK, 0, 16, 0x23, 0x80, + TDM_RX_BCK, ANT_SEL4, RES3, SPINOR_CK, + CONN_MCU_DBGI_N, RES6, RES7), + PIN(62, TDM_RX_MCLK, 0, 22, 0x23, 0x80, + TDM_RX_MCK, ANT_SEL5, RES3, SPINOR_CS, + CONN_MCU_TDI, RES6, RES7), + PIN(63, TDM_RX_DATA0, 0, 17, 0x23, 0x80, + TDM_RX_DATA0, ANT_SEL6, RES3, SPINOR_IO0, + CONN_MCU_TRST_B, RES6, RES7), + PIN(64, TDM_RX_DATA1, 0, 18, 0x23, 0x80, + TDM_RX_DATA1, ANT_SEL7, PWM0, SPINOR_IO1, + CONN_MCU_TCK, RES6, RES7), + PIN(65, TDM_RX_DATA2, 0, 19, 0x23, 0x80, + TDM_RX_DATA2, UCTS0, PWM1, SPINOR_IO2, + CONN_MCU_TDO, TP_UCTS1_AO, TP_UCTS2_AO), + PIN(66, TDM_RX_DATA3, 0, 20, 0x23, 0x80, + TDM_RX_DATA3, URTS0, PWM2, SPINOR_IO3, + CONN_MCU_TMS, TP_URTS1_AO, TP_URTS2_AO), + PIN(67, MSDC0_DSL, 1, 10, 0x21, 0x70, + MSDC0_DSL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(68, MSDC0_CLK, 1, 0, 0x21, 0x70, + MSDC0_CLK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(69, MSDC0_CMD, 1, 1, 0x21, 0x70, + MSDC0_CMD, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(70, MSDC0_RSTB, 1, 11, 0x21, 0x70, + MSDC0_RSTB, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(71, MSDC0_DAT0, 1, 2, 0x21, 0x70, + MSDC0_DAT0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(72, MSDC0_DAT1, 1, 3, 0x21, 0x70, + MSDC0_DAT1, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(73, MSDC0_DAT2, 1, 4, 0x21, 0x70, + MSDC0_DAT2, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(74, MSDC0_DAT3, 1, 5, 0x21, 0x70, + MSDC0_DAT3, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(75, MSDC0_DAT4, 1, 6, 0x21, 0x70, + MSDC0_DAT4, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(76, MSDC0_DAT5, 1, 7, 0x21, 0x70, + MSDC0_DAT5, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(77, MSDC0_DAT6, 1, 8, 0x21, 0x70, + MSDC0_DAT6, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(78, MSDC0_DAT7, 1, 9, 0x21, 0x70, + MSDC0_DAT7, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(79, KPCOL0, 1, 0, 0x25, 0x80, + KPCOL0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(80, KPCOL1, 1, 1, 0x25, 0x80, + KPCOL1, GPS_L1_ELNA_EN, PWM0, CLKM0, + RES5, RES6, RES7), + PIN(81, KPROW0, 1, 2, 0x25, 0x80, + KPROW0, RES2, PWM1, CLKM1, + RES5, RES6, RES7), + PIN(82, KPROW1, 1, 3, 0x25, 0x80, + KPROW1, RES2, PWM2, CLKM2, + RES5, RES6, RES7), + PIN(83, AP_GOOD, 0, 3, 0x16, 0x50, + AP_GOOD, GPS_PPS, RES3, EXT_FRAME_SYNC, + RES5, RES6, dbg_mon_a28), + PIN(84, MSDC1_CLK, 1, 0, 0x23, 0x70, + MSDC1_CLK, ADSP_JTAG_TCK, RES3, UDI_TCK, + CONN_DSP_JCK, SSPM_JTAG_TCK, DFD_TCK_XI), + PIN(85, MSDC1_CMD, 1, 1, 0x23, 0x70, + MSDC1_CMD, ADSP_JTAG_TMS, CONN_MCU_AICE_TMSC, UDI_TMS, + CONN_DSP_JMS, SSPM_JTAG_TMS, DFD_TMS), + PIN(86, MSDC1_DAT0, 1, 2, 0x23, 0x70, + MSDC1_DAT0, ADSP_JTAG_TDI, RES3, UDI_TDI, + CONN_DSP_JDI, SSPM_JTAG_TDI, DFD_TDI), + PIN(87, MSDC1_DAT1, 1, 3, 0x23, 0x70, + MSDC1_DAT1, ADSP_JTAG_TDO, RES3, UDI_TDO, + CONN_DSP_JDO, SSPM_JTAG_TDO, DFD_TDO), + PIN(88, MSDC1_DAT2, 1, 4, 0x23, 0x70, + MSDC1_DAT2, ADSP_JTAG_TRSTN, CONN_MCU_AICE_TCKC, UDI_NTRST, + CONN_WIFI_TXD, SSPM_JTAG_TRSTN, RES7), + PIN(89, MSDC1_DAT3, 1, 5, 0x23, 0x70, + MSDC1_DAT3, RES2, RES3, RES4, + CONN_DSP_JINTP, RES6, RES7), + PIN(90, IDDIG_P0, 0, 2, 0x23, 0x80, + IDDIG_P0, RES2, RES3, PGD_HV_HSC_PWR4, + GDU_SUM_TROOP2_2, RES6, RES7), + PIN(91, USB_DRVVBUS_P0, 0, 23, 0x23, 0x80, + USB_DRVVBUS_P0, RES2, RES3, PGD_HV_HSC_PWR5, + GDU_TROOPS_DET0, RES6, RES7), + PIN(92, VBUS_VALID_P0, 0, 25, 0x23, 0x80, + VBUS_VALID_P0, RES2, RES3, PGD_DA_EFUSE_RDY, + GDU_TROOPS_DET1, RES6, RES7), + PIN(93, IDDIG_P1, 0, 3, 0x23, 0x80, + IDDIG_P1, PWM0, CLKM0, PGD_DA_EFUSE_RDY_PRE, + GDU_TROOPS_DET2, RES6, RES7), + PIN(94, USB_DRVVBUS_P1, 0, 24, 0x23, 0x80, + USB_DRVVBUS_P1, PWM1, CLKM1, PGD_DA_PWRGD_RESET, + RES5, RES6, RES7), + PIN(95, VBUS_VALID_P1, 0, 26, 0x23, 0x80, + VBUS_VALID_P1, PWM2, CLKM2, PGD_DA_PWRGD_ENB, + RES5, RES6, RES7), + PIN(96, DSI_TE, 0, 1, 0x12, 0x60, + DSI_TE, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a29), + PIN(97, DISP_PWM, 0, 0, 0x12, 0x60, + DISP_PWM, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a30), + PIN(98, LCM_RST, 0, 2, 0x12, 0x60, + LCM_RST, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(99, DPI_PCLK, 0, 14, 0x24, 0x60, + DPI_PCLK, GPS_L1_ELNA_EN, SSPM_JTAG_TCK, RES4, + ANT_SEL0, TP_GPIO0_AO, PGD_LV_LSC_PWR0), + PIN(100, DPI_VSYNC, 0, 15, 0x24, 0x60, + DPI_VSYNC, KPCOL2, SSPM_JTAG_TMS, RES4, + ANT_SEL1, TP_GPIO1_AO, PGD_LV_LSC_PWR1), + PIN(101, DPI_HSYNC, 0, 13, 0x24, 0x60, + DPI_HSYNC, KPROW2, SSPM_JTAG_TDI, RES4, + ANT_SEL2, TP_GPIO2_AO, PGD_LV_LSC_PWR2), + PIN(102, DPI_DE, 0, 12, 0x24, 0x60, + DPI_DE, RES2, SSPM_JTAG_TDO, RES4, + ANT_SEL3, TP_GPIO3_AO, PGD_LV_LSC_PWR3), + PIN(103, DPI_DATA0, 0, 0, 0x24, 0x60, + DPI_DATA0, RES2, SSPM_JTAG_TRSTN, CLKM0, + ANT_SEL4, TP_GPIO4_AO, PGD_LV_LSC_PWR4), + PIN(104, DPI_DATA1, 0, 1, 0x24, 0x60, + DPI_DATA1, GPS_PPS, UCTS2, CLKM1, + ANT_SEL5, TP_GPIO5_AO, PGD_LV_LSC_PWR5), + PIN(105, DPI_DATA2, 0, 4, 0x24, 0x60, + DPI_DATA2, CONN_TCXOENA_REQ, URTS2, CLKM2, + ANT_SEL6, TP_GPIO6_AO, PGD_LV_HSC_PWR0), + PIN(106, DPI_DATA3, 0, 5, 0x24, 0x60, + DPI_DATA3, TP_UTXD1_AO, UTXD2, PWM0, + ANT_SEL7, TP_GPIO7_AO, PGD_LV_HSC_PWR1), + PIN(107, DPI_DATA4, 0, 6, 0x24, 0x60, + DPI_DATA4, TP_URXD1_AO, URXD2, PWM1, + RES5, GDU_SUM_TROOP0_0, PGD_LV_HSC_PWR2), + PIN(108, DPI_DATA5, 0, 7, 0x24, 0x60, + DPI_DATA5, TP_UCTS1_AO, UCTS0, PWM2, + RES5, GDU_SUM_TROOP0_1, PGD_LV_HSC_PWR3), + PIN(109, DPI_DATA6, 0, 8, 0x24, 0x60, + DPI_DATA6, TP_URTS1_AO, URTS0, I2S0_DI, + I2S2_DI, GDU_SUM_TROOP0_2, PGD_LV_HSC_PWR4), + PIN(110, DPI_DATA7, 0, 9, 0x24, 0x60, + DPI_DATA7, TP_UCTS2_AO, UCTS1, I2S3_BCK, + I2S1_BCK, GDU_SUM_TROOP1_0, PGD_LV_HSC_PWR5), + PIN(111, DPI_DATA8, 0, 10, 0x24, 0x60, + DPI_DATA8, TP_URTS2_AO, URTS1, I2S3_MCK, + I2S1_MCK, GDU_SUM_TROOP1_1, PGD_HV_HSC_PWR0), + PIN(112, DPI_DATA9, 0, 11, 0x24, 0x60, + DPI_DATA9, TP_URXD2_AO, URXD1, I2S3_LRCK, + I2S1_LRCK, GDU_SUM_TROOP1_2, PGD_HV_HSC_PWR1), + PIN(113, DPI_DATA10, 0, 2, 0x24, 0x60, + DPI_DATA10, TP_UTXD2_AO, UTXD1, I2S3_DO, + I2S1_DO, GDU_SUM_TROOP2_0, PGD_HV_HSC_PWR2), + PIN(114, DPI_DATA11, 0, 3, 0x24, 0x60, + DPI_DATA11, RES2, RES3, RES4, + RES5, GDU_SUM_TROOP2_1, PGD_HV_HSC_PWR3), + PIN(115, PCM_CLK, 0, 4, 0x23, 0x80, + PCM_CLK, I2S0_BCK, I2S2_BCK, RES4, + RES5, RES6, RES7), + PIN(116, PCM_SYNC, 0, 7, 0x23, 0x80, + PCM_SYNC, I2S0_LRCK, I2S2_LRCK, RES4, + RES5, RES6, RES7), + PIN(117, PCM_DI, 0, 5, 0x23, 0x80, + PCM_DI, I2S0_DI, I2S2_DI, RES4, + RES5, RES6, RES7), + PIN(118, PCM_DO, 0, 6, 0x23, 0x80, + PCM_DO, I2S0_MCK, I2S2_MCK, I2S3_DO, + I2S1_DO, RES6, RES7), + PIN(119, JTMS_SEL1, 0, 22, 0x25, 0x90, + JTMS_SEL1, UDI_TMS, DFD_TMS, SPM_JTAG_TMS, + SCP_JTAG_TMS, ADSP_JTAG_TMS, RES7), + PIN(120, JTCK_SEL1, 0, 19, 0x25, 0x90, + JTCK_SEL1, UDI_TCK, DFD_TCK_XI, SPM_JTAG_TCK, + SCP_JTAG_TCK, ADSP_JTAG_TCK, RES7), + PIN(121, JTDI_SEL1, 0, 20, 0x25, 0x90, + JTDI_SEL1, UDI_TDI, DFD_TDI, SPM_JTAG_TDI, + SCP_JTAG_TDI, ADSP_JTAG_TDI, RES7), + PIN(122, JTDO_SEL1, 0, 21, 0x25, 0x90, + JTDO_SEL1, UDI_TDO, DFD_TDO, SPM_JTAG_TDO, + SCP_JTAG_TDO, ADSP_JTAG_TDO, RES7), + PIN(123, JTRSTN_SEL1, 0, 23, 0x25, 0x90, + JTRSTN_SEL1, UDI_NTRST, RES3, SPM_JTAG_TRSTN, + SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, RES7), + PIN(124, CAM_CLK0, 0, 0, 0x25, 0x90, + CMMCLK0, CLKM0, PWM0, RES4, + RES5, RES6, RES7), + PIN(125, CAM_CLK1, 0, 1, 0x25, 0x90, + CMMCLK1, CLKM1, PWM1, RES4, + RES5, RES6, dbg_mon_b0), + PIN(126, CAM_CLK2, 0, 2, 0x25, 0x90, + CMMCLK2, CLKM2, PWM2, RES4, + RES5, RES6, dbg_mon_b1), + PIN(127, SCL0, 0, 8, 0x23, 0x80, + SCL0, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, RES7), + PIN(128, SDA0, 0, 10, 0x23, 0x80, + SDA0, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(129, SCL1, 0, 24, 0x25, 0x90, + SCL1, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b4), + PIN(130, SDA1, 0, 26, 0x25, 0x90, + SDA1, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b5), + PIN(131, SCL2, 0, 25, 0x25, 0x90, + SCL2, SSPM_UTXD_AO, CONN_UART0_TXD, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b6), + PIN(132, SDA2, 0, 27, 0x25, 0x90, + SDA2, SSPM_URXD_AO, CONN_UART0_RXD, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b7), + PIN(133, SCL3, 0, 9, 0x21, 0x80, + SCL3, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b8), + PIN(134, SDA3, 0, 12, 0x21, 0x80, + SDA3, RES2, GPS_PPS, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b9), + PIN(135, SCL4, 0, 21, 0x16, 0x50, + SCL4, TP_UTXD1_AO, UTXD1, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b10), + PIN(136, SDA4, 0, 24, 0x16, 0x50, + SDA4, TP_URXD1_AO, URXD1, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b11), + PIN(137, SCL5, 0, 10, 0x21, 0x80, + SCL5, UTXD2, UCTS1, SCP_SCL0, + SCP_SCL1, RES6, RES7), + PIN(138, SDA5, 0, 13, 0x21, 0x80, + SDA5, URXD2, URTS1, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(139, SCL6, 0, 7, 0x12, 0x60, + SCL6, UTXD1, TP_UTXD1_AO, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b12), + PIN(140, SDA6, 0, 8, 0x12, 0x60, + SDA6, URXD1, TP_URXD1_AO, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b13), + PIN(141, SCL7, 0, 9, 0x23, 0x80, + SCL7, URTS0, TP_URTS1_AO, SCP_SCL0, + SCP_SCL1, UDI_TCK, dbg_mon_b14), + PIN(142, SDA7, 0, 11, 0x23, 0x80, + SDA7, UCTS0, TP_UCTS1_AO, SCP_SDA0, + SCP_SDA1, RES6, RES7), + PIN(143, SCL8, 0, 22, 0x16, 0x50, + SCL8, RES2, RES3, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b16), + PIN(144, SDA8, 0, 25, 0x16, 0x50, + SDA8, RES2, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b17), + PIN(145, SCL9, 0, 23, 0x16, 0x50, + SCL9, CMVREF1, GPS_PPS, SCP_SCL0, + SCP_SCL1, RES6, dbg_mon_b18), + PIN(146, SDA9, 0, 26, 0x16, 0x50, + SDA9, CMVREF0, RES3, SCP_SDA0, + SCP_SDA1, RES6, dbg_mon_b19), + PIN(147, PERIPHERAL_EN0, 0, 23, 0x24, 0x60, + CMFLASH0, LVTS_SDI, DPI_DATA12, TP_GPIO0_AO, + ANT_SEL3, DFD_TCK_XI, dbg_mon_b20), + PIN(148, PERIPHERAL_EN1, 0, 24, 0x24, 0x60, + CMFLASH1, LVTS_SCF, DPI_DATA13, TP_GPIO1_AO, + ANT_SEL4, DFD_TMS, dbg_mon_b21), + PIN(149, PERIPHERAL_EN2, 0, 25, 0x24, 0x60, + CMFLASH2, CLKM0, DPI_DATA14, TP_GPIO2_AO, + ANT_SEL5, DFD_TDI, dbg_mon_b22), + PIN(150, PERIPHERAL_EN3, 0, 26, 0x24, 0x60, + RES1, CLKM1, DPI_DATA15, TP_GPIO3_AO, + ANT_SEL6, DFD_TDO, dbg_mon_b23), + PIN(151, PERIPHERAL_EN4, 0, 27, 0x24, 0x60, + GPS_L1_ELNA_EN, CLKM2, DPI_DATA16, TP_GPIO4_AO, + ANT_SEL7, UDI_TMS, dbg_mon_b24), + PIN(152, PERIPHERAL_EN5, 0, 28, 0x24, 0x60, + RES1, CLKM3, DPI_DATA17, TP_GPIO5_AO, + RES5, RES6, RES7), + PIN(153, PERIPHERAL_EN6, 0, 29, 0x24, 0x60, + CONN_TCXOENA_REQ, RES2, DPI_DATA18, TP_GPIO6_AO, + RES5, UDI_TDI, dbg_mon_b26), + PIN(154, PERIPHERAL_EN7, 0, 30, 0x24, 0x60, + PWM0, CMVREF2, DPI_DATA19, TP_GPIO7_AO, + RES5, UDI_TDO, dbg_mon_b27), + PIN(155, PERIPHERAL_EN8, 0, 31, 0x24, 0x60, + PWM1, CMVREF1, DPI_DATA20, RES4, + RES5, UDI_NTRST, dbg_mon_b28), + PIN(156, PERIPHERAL_EN9, 0, 0, 0x24, 0x70, + PWM2, CMVREF0, DPI_DATA21, RES4, + RES5, RES6, RES7), + PIN(157, PWRAP_SPI0_CSN, 0, 4, 0x12, 0x60, + PWRAP_SPI0_CSN, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(158, PWRAP_SPI0_CK, 0, 3, 0x12, 0x60, + PWRAP_SPI0_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(159, PWRAP_SPI0_MO, 0, 6, 0x12, 0x60, + PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4, + RES5, RES6, RES7), + PIN(160, PWRAP_SPI0_MI, 0, 5, 0x12, 0x60, + PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4, + RES5, RES6, RES7), + PIN(161, SRCLKENA0, 0, 23, 0x12, 0x60, + SRCLKENA0, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(162, SRCLKENA1, 0, 24, 0x12, 0x60, + SRCLKENA1, RES2, RES3, RES4, + RES5, RES6, dbg_mon_a31), + PIN(163, SCP_VREQ_VAO, 0, 11, 0x21, 0x80, + SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4, + RES5, RES6, RES7), + PIN(164, RTC32K_CK, 0, 8, 0x21, 0x80, + RTC32K_CK, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(165, WATCHDOG, 0, 16, 0x21, 0x80, + WATCHDOG, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(166, AUD_CLK_MOSI, 0, 1, 0x21, 0x80, + AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4, + RES5, RES6, RES7), + PIN(167, AUD_SYNC_MOSI, 0, 7, 0x21, 0x80, + AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4, + RES5, RES6, RES7), + PIN(168, AUD_DAT_MOSI0, 0, 4, 0x21, 0x80, + AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4, + RES5, RES6, RES7), + PIN(169, AUD_DAT_MOSI1, 0, 5, 0x21, 0x80, + AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4, + RES5, RES6, RES7), + PIN(170, AUD_CLK_MISO, 0, 0, 0x21, 0x80, + AUD_CLK_MISO, AUD_CLK_MOSI, I2S2_MCK, RES4, + RES5, RES6, RES7), + PIN(171, AUD_SYNC_MISO, 0, 6, 0x21, 0x80, + AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S2_BCK, RES4, + RES5, RES6, RES7), + PIN(172, AUD_DAT_MISO0, 0, 2, 0x21, 0x80, + AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S2_LRCK, VOW_DAT_MISO, + RES5, RES6, RES7), + PIN(173, AUD_DAT_MISO1, 0, 3, 0x21, 0x80, + AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S2_DI, VOW_CLK_MISO, + RES5, RES6, RES7), + PIN(174, CONN_TOP_CLK, 0, 7, 0x16, 0x50, + CONN_TOP_CLK, AUXIF_CLK, DFD_TCK_XI, RES4, + RES5, RES6, dbg_mon_b3), + PIN(175, CONN_TOP_DATA, 0, 8, 0x16, 0x50, + CONN_TOP_DATA, AUXIF_ST, DFD_TMS, RES4, + RES5, RES6, dbg_mon_b15), + PIN(176, CONN_BT_CLK, 0, 4, 0x16, 0x50, + CONN_BT_CLK, RES2, DFD_TDI, RES4, + RES5, RES6, dbg_mon_b2), + PIN(177, CONN_BT_DATA, 0, 5, 0x16, 0x50, + CONN_BT_DATA, RES2, DFD_TDO, RES4, + RES5, RES6, RES7), + PIN(178, CONN_HRST_B, 0, 6, 0x16, 0x50, + CONN_HRST_B, RES2, UDI_TMS, RES4, + RES5, RES6, dbg_mon_b25), + PIN(179, CONN_WB_PTA, 0, 9, 0x16, 0x50, + CONN_WB_PTA, RES2, UDI_TCK, RES4, + RES5, RES6, dbg_mon_b29), + PIN(180, CONN_WF_CTRL0, 0, 10, 0x16, 0x50, + CONN_WF_CTRL0, RES2, UDI_TDI, RES4, + RES5, RES6, RES7), + PIN(181, CONN_WF_CTRL1, 0, 11, 0x16, 0x50, + CONN_WF_CTRL1, RES2, UDI_TDO, RES4, + RES5, RES6, RES7), + PIN(182, CONN_WF_CTRL2, 0, 12, 0x16, 0x50, + CONN_WF_CTRL2, RES2, UDI_NTRST, RES4, + RES5, RES6, RES7), + PIN(183, SPMI_SCL, 0, 21, 0x12, 0x60, + SPMI_SCL, RES2, RES3, RES4, + RES5, RES6, RES7), + PIN(184, SPMI_SDA, 0, 22, 0x12, 0x60, + SPMI_SDA, RES2, RES3, RES4, + RES5, RES6, RES7), +}; + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +struct gpio_regs { + struct val_regs dir[7]; + uint8_t rsv00[144]; + struct val_regs dout[7]; + uint8_t rsv01[144]; + struct val_regs din[7]; + uint8_t rsv02[144]; + struct val_regs mode[28]; + uint8_t rsv03[560]; + uint32_t dram_pinmux_trapping; +}; + +check_member(gpio_regs, mode[27].val, 0x4b0); +check_member(gpio_regs, dram_pinmux_trapping, 0x6f0); + +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/gpio_base.h b/src/soc/mediatek/mt8186/include/soc/gpio_base.h new file mode 100644 index 0000000000..7f6480a0f1 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/gpio_base.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_GPIO_BASE_H +#define SOC_MEDIATEK_MT8186_GPIO_BASE_H + +#include + +typedef union { + u32 raw; + struct { + u32 id : 8; + u32 flag : 3; + u32 bit : 5; + u32 base : 8; + u32 offset : 8; + }; +} gpio_t; + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h new file mode 100644 index 0000000000..4024e7de6b --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/i2c.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#ifndef SOC_MEDIATEK_MT8186_I2C_H +#define SOC_MEDIATEK_MT8186_I2C_H + +#include +#include + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, + I2C8, + I2C9, +}; + +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIV2PLL_HZ / 20) + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8186_I2C_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/infracfg.h b/src/soc/mediatek/mt8186/include/soc/infracfg.h new file mode 100644 index 0000000000..00400e0bc3 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/infracfg.h @@ -0,0 +1,547 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_INFRACFG_H +#define SOC_MEDIATEK_MT8186_INFRACFG_H + +#include +#include + +struct mt8186_infracfg_ao_regs { + u32 reserved1[20]; + u32 infra_globalcon_dcmctl; + u32 reserved2[7]; + u32 infra_bus_dcm_ctrl; + u32 peri_bus_dcm_ctrl; + u32 mem_dcm_ctrl; + u32 dfs_mem_dcm_ctrl; + u32 module_sw_cg_0_set; + u32 module_sw_cg_0_clr; + u32 module_sw_cg_1_set; + u32 module_sw_cg_1_clr; + u32 module_sw_cg_0_sta; + u32 module_sw_cg_1_sta; + u32 module_clk_sel; + u32 mem_cg_ctrl; + u32 p2p_rx_clk_on; + u32 module_sw_cg_2_set; + u32 module_sw_cg_2_clr; + u32 module_sw_cg_2_sta; + u32 reserved3[1]; + u32 dramc_wbr; + u32 ddr_en_mask; + u32 reserved4[1]; + u32 module_sw_cg_3_set; + u32 module_sw_cg_3_clr; + u32 module_sw_cg_3_sta; + u32 reserved5[13]; + u32 i2c_dbtool_misc; + u32 md_sleep_ctrl_mask; + u32 pmicw_clock_ctrl; + u32 reserved6[5]; + u32 infra_globalcon_rst0_set; + u32 infra_globalcon_rst0_clr; + u32 infra_globalcon_rst0_sta; + u32 reserved7[1]; + u32 infra_globalcon_rst1_set; + u32 infra_globalcon_rst1_clr; + u32 infra_globalcon_rst1_sta; + u32 reserved8[1]; + u32 infra_globalcon_rst2_set; + u32 infra_globalcon_rst2_clr; + u32 infra_globalcon_rst2_sta; + u32 reserved9[1]; + u32 infra_globalcon_rst3_set; + u32 infra_globalcon_rst3_clr; + u32 infra_globalcon_rst3_sta; + u32 reserved10[41]; + u32 infra_topaxi_si0_ctl; + u32 infra_topaxi_si1_ctl; + u32 infra_topaxi_mdbus_ctl; + u32 infra_mci_si0_ctl; + u32 infra_mci_si1_ctl; + u32 infra_mci_si2_ctl; + u32 infra_mci_async_ctl; + u32 infra_mci_cg_mfg_sec_sta; + u32 infra_topaxi_protecten; + u32 infra_topaxi_protecten_sta0; + u32 infra_topaxi_protecten_sta1; + u32 infra_axi_aslice_ctrl; + u32 infra_apb_async_sta; + u32 infra_topaxi_si2_ctl; + u32 reserved11[1]; + u32 infra_topaxi_trans_limiter_1; + u32 infra_mci_trans_con_read; + u32 infra_mci_trans_con_write; + u32 infra_mci_id_remap_con; + u32 infra_mci_emi_trans_con; + u32 infra_topaxi_protecten_1; + u32 infra_topaxi_protecten_sta0_1; + u32 infra_topaxi_protecten_sta1_1; + u32 reserved12[1]; + u32 infra_topaxi_aslice_ctrl; + u32 infra_topaxi_protecten_2; + u32 infra_topaxi_protecten_sta0_2; + u32 infra_topaxi_protecten_sta1_2; + u32 infra_topaxi_mi_ctrl; + u32 infra_topaxi_cbip_aslice_ctrl; + u32 infra_topaxi_cbip_slice_ctrl; + u32 infra_top_master_sideband; + u32 reserved13[1]; + u32 infra_topaxi_trans_limiter; + u32 infra_topaxi_emi_gmc_l2c_ctrl; + u32 infra_topaxi_cbip_slice_ctrl_1; + u32 infra_mfg_slave_gals_ctrl; + u32 infra_mfg_master_m0_gals_ctrl; + u32 infra_mfg_master_m1_gals_ctrl; + u32 infra_top_master_sideband_1; + u32 infra_topaxi_protecten_set; + u32 infra_topaxi_protecten_clr; + u32 infra_topaxi_protecten_1_set; + u32 infra_topaxi_protecten_1_clr; + u32 infra_topaxi_protecten_2_set; + u32 infra_topaxi_protecten_2_clr; + u32 infra_topaxi_protecten_3_set; + u32 infra_topaxi_protecten_3_clr; + u32 infra_topaxi_protecten_3; + u32 infra_topaxi_protecten_sta0_3; + u32 infra_topaxi_protecten_sta1_3; + u32 reserved14[12]; + u32 infra_topaxi_bus_dbg_con_a0; + u32 md1_bank0_map0; + u32 md1_bank0_map1; + u32 md1_bank0_map2; + u32 md1_bank0_map3; + u32 md1_bank1_map0; + u32 md1_bank1_map1; + u32 md1_bank1_map2; + u32 md1_bank1_map3; + u32 md1_bank4_map0; + u32 md1_bank4_map1; + u32 md1_bank4_map2; + u32 md1_bank4_map3; + u32 md2_bank0_map0; + u32 md2_bank0_map1; + u32 md2_bank0_map2; + u32 md2_bank0_map3; + u32 reserved15[4]; + u32 md2_bank4_map0; + u32 md2_bank4_map1; + u32 md2_bank4_map2; + u32 md2_bank4_map3; + u32 c2k_config; + u32 c2k_status; + u32 c2k_spm_ctrl; + u32 reserved16[1]; + u32 ap2md_dummy; + u32 reserved17[3]; + u32 conn_map0; + u32 cldma_map0; + u32 conn_map1; + u32 conn_bus_con; + u32 mcusys_dfd_map; + u32 reserved18[1]; + u32 conn_map3; + u32 conn_map4; + u32 reserved19[24]; + u32 peri_cci_sideband_con; + u32 mfg_cci_sideband_con; + u32 reserved20[2]; + u32 infra_pwm_cksw_ctrl; + u32 reserved21[59]; + u32 infra_ao_dbg_con0; + u32 infra_ao_dbg_con1; + u32 infra_ao_dbg_con2; + u32 infra_ao_dbg_con3; + u32 md_dbg_ck_con; + u32 reserved22[59]; + u32 mfg_misc_con; + u32 reserved23[62]; + u32 infra_msdc_con; + u32 infra_rsvd0; + u32 infra_rsvd1; + u32 infra_rsvd2; + u32 infra_rsvd3; + u32 infra_rsvd4; + u32 infra_rsvd5; + u32 infra_iommu_en; + u32 reserved24[89]; + u32 md1_sbc_key0; + u32 md1_sbc_key1; + u32 md1_sbc_key2; + u32 md1_sbc_key3; + u32 md1_sbc_key4; + u32 md1_sbc_key5; + u32 md1_sbc_key6; + u32 md1_sbc_key7; + u32 md1_sbc_key_lock; + u32 reserved25[1]; + u32 md1_misc_lock; + u32 md1_misc; + u32 c2k_sbc_key0; + u32 c2k_sbc_key1; + u32 c2k_sbc_key2; + u32 c2k_sbc_key3; + u32 c2k_sbc_key4; + u32 c2k_sbc_key5; + u32 c2k_sbc_key6; + u32 c2k_sbc_key7; + u32 c2k_sbc_key_lock; + u32 reserved26[11]; + u32 infra_bonding; + u32 subsys_pdn_nohang_dis0; + u32 subsys_pdn_nohang_dis1; + u32 reserved27[61]; + u32 infra_ao_scpsys_apb_async_sta; + u32 infra_ao_md32_tx_apb_async_sta; + u32 infra_ao_md32_rx_apb_async_sta; + u32 infra_ao_cksys_apb_async_sta; + u32 infra_ao_pmic_wrap_tx_apb_async_sta; + u32 infra_ao_pmif_spmi_tx_apb_async_sta; + u32 infra_ao_spmi_mst_tx_apb_async_sta; + u32 infra_ao_infra0_iommu_apb_async_sta; + u32 infra_ao_infra1_iommu_apb_async_sta; + u32 reserved28[6]; + u32 infra_ao_mcu_pwr_mask; + u32 reserved29[48]; + u32 pll_ulposc_con0; + u32 pll_ulposc_con1; + u32 reserved30[2]; + u32 pll_auxadc_con0; + u32 scp_infra_irq_set; + u32 scp_infra_irq_clr; + u32 scp_infra_ctrl; + u32 conn2infra_gals_dbg; + u32 infra_infra2adsp_axi_gals_debug; + u32 infra_adsp2infra_axi_gals_debug; + u32 infra_adsp2emi_axi_gals_debug; + u32 nna0_1_emi_axi_gals_debug; + u32 nna2_emi_axi_gals_debug; + u32 nn2infra_axi_gals_debug; + u32 infra2nna_axi_gals_debug; + u32 reserved31[48]; + u32 cldma_ctrl; + u32 reserved32[3]; + u32 rg_ccif4_md_pwr_flag; + u32 rg_ccif4_con_pwr_flag; + u32 rd_ccif4_cpu_pwr_flag; + u32 reserved33[1]; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0; + u32 infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0; + u32 reserved34[1]; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0; + u32 infra_ipsys_s_bus_u_si0_ctrl_0; + u32 infra_ipsys_s_bus_u_si0_ctrl_1; + u32 infra_ipsys_s_bus_u_si0_ctrl_2; + u32 infra_ipsys_s_bus_u_si0_ctrl_3; + u32 infra_ipsys_s_bus_u_si0_ctrl_4; + u32 infra_ipsys_s_bus_u_si0_ctrl_5; + u32 reserved35[40]; + u32 infrabus_dbg0; + u32 infrabus_dbg1; + u32 infrabus_dbg2; + u32 infrabus_dbg3; + u32 infrabus_dbg4; + u32 infrabus_dbg5; + u32 infrabus_dbg6; + u32 infrabus_dbg7; + u32 infrabus_dbg8; + u32 infrabus_dbg9; + u32 infrabus_dbg10; + u32 infrabus_dbg11; + u32 infrabus_dbg12; + u32 infrabus_dbg13; + u32 infrabus_dbg14; + u32 infrabus_dbg15; + u32 infrabus_dbg16; + u32 reserved36[111]; + u32 infra_misc; + u32 infra_acp; + u32 misc_config; + u32 infra_misc2; + u32 mdsys_misc_con; + u32 reserved37[12]; + u32 nna_infra_gals_ctrl; + u32 nna_emi_gals_ctrl; + u32 infra_adsp_infra_gals_ctrl; + u32 infra_adsp_emi_gals_ctrl; + u32 reserved38[11]; + u32 infra_ao_sec_con; + u32 infra_ao_sec_cg_con0; + u32 infra_ao_sec_cg_con1; + u32 infra_ao_sec_rst_con0; + u32 infra_ao_sec_rst_con1; + u32 infra_ao_sec_rst_con2; + u32 dxcc_dcu_en_lock; + u32 infra_ao_sec_cg_con2; + u32 infra_ao_sec_rst_con3; + u32 infra_ao_sec_cg_con3; + u32 reserved39[2]; + u32 infra_ao_sec_hyp; + u32 infra_mcu2emi_slice; + u32 infra_ao_sec_mfg_hyp; +}; + +check_member(mt8186_infracfg_ao_regs, infra_globalcon_dcmctl, 0x50); +check_member(mt8186_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x70); +check_member(mt8186_infracfg_ao_regs, peri_bus_dcm_ctrl, 0x74); +check_member(mt8186_infracfg_ao_regs, mem_dcm_ctrl, 0x78); +check_member(mt8186_infracfg_ao_regs, dfs_mem_dcm_ctrl, 0x7c); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_set, 0x80); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_clr, 0x84); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_set, 0x88); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_clr, 0x8c); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_0_sta, 0x90); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_1_sta, 0x94); +check_member(mt8186_infracfg_ao_regs, module_clk_sel, 0x98); +check_member(mt8186_infracfg_ao_regs, mem_cg_ctrl, 0x9c); +check_member(mt8186_infracfg_ao_regs, p2p_rx_clk_on, 0xa0); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_set, 0xa4); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_clr, 0xa8); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_2_sta, 0xac); +check_member(mt8186_infracfg_ao_regs, dramc_wbr, 0xb4); +check_member(mt8186_infracfg_ao_regs, ddr_en_mask, 0xb8); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_set, 0xc0); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_clr, 0xc4); +check_member(mt8186_infracfg_ao_regs, module_sw_cg_3_sta, 0xc8); +check_member(mt8186_infracfg_ao_regs, i2c_dbtool_misc, 0x100); +check_member(mt8186_infracfg_ao_regs, md_sleep_ctrl_mask, 0x104); +check_member(mt8186_infracfg_ao_regs, pmicw_clock_ctrl, 0x108); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_set, 0x120); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_clr, 0x124); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst0_sta, 0x128); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_set, 0x130); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_clr, 0x134); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst1_sta, 0x138); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_set, 0x140); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_clr, 0x144); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst2_sta, 0x148); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_set, 0x150); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_clr, 0x154); +check_member(mt8186_infracfg_ao_regs, infra_globalcon_rst3_sta, 0x158); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si0_ctl, 0x200); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si1_ctl, 0x204); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_mdbus_ctl, 0x208); +check_member(mt8186_infracfg_ao_regs, infra_mci_si0_ctl, 0x20c); +check_member(mt8186_infracfg_ao_regs, infra_mci_si1_ctl, 0x210); +check_member(mt8186_infracfg_ao_regs, infra_mci_si2_ctl, 0x214); +check_member(mt8186_infracfg_ao_regs, infra_mci_async_ctl, 0x218); +check_member(mt8186_infracfg_ao_regs, infra_mci_cg_mfg_sec_sta, 0x21c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten, 0x220); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0, 0x224); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1, 0x228); +check_member(mt8186_infracfg_ao_regs, infra_axi_aslice_ctrl, 0x22c); +check_member(mt8186_infracfg_ao_regs, infra_apb_async_sta, 0x230); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_si2_ctl, 0x234); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter_1, 0x23c); +check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_read, 0x240); +check_member(mt8186_infracfg_ao_regs, infra_mci_trans_con_write, 0x244); +check_member(mt8186_infracfg_ao_regs, infra_mci_id_remap_con, 0x248); +check_member(mt8186_infracfg_ao_regs, infra_mci_emi_trans_con, 0x24c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1, 0x250); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_1, 0x254); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_1, 0x258); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_aslice_ctrl, 0x260); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2, 0x264); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_2, 0x268); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_2, 0x26c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_mi_ctrl, 0x270); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_aslice_ctrl, 0x274); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl, 0x278); +check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband, 0x27c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_trans_limiter, 0x284); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_emi_gmc_l2c_ctrl, 0x288); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_cbip_slice_ctrl_1, 0x28c); +check_member(mt8186_infracfg_ao_regs, infra_mfg_slave_gals_ctrl, 0x290); +check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m0_gals_ctrl, 0x294); +check_member(mt8186_infracfg_ao_regs, infra_mfg_master_m1_gals_ctrl, 0x298); +check_member(mt8186_infracfg_ao_regs, infra_top_master_sideband_1, 0x29c); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_set, 0x2a0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_clr, 0x2a4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_set, 0x2a8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_1_clr, 0x2ac); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_set, 0x2b0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_2_clr, 0x2b4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_set, 0x2b8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3_clr, 0x2bc); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_3, 0x2c0); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta0_3, 0x2c4); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_protecten_sta1_3, 0x2c8); +check_member(mt8186_infracfg_ao_regs, infra_topaxi_bus_dbg_con_a0, 0x2fc); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map0, 0x300); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map1, 0x304); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map2, 0x308); +check_member(mt8186_infracfg_ao_regs, md1_bank0_map3, 0x30c); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map0, 0x310); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map1, 0x314); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map2, 0x318); +check_member(mt8186_infracfg_ao_regs, md1_bank1_map3, 0x31c); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map0, 0x320); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map1, 0x324); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map2, 0x328); +check_member(mt8186_infracfg_ao_regs, md1_bank4_map3, 0x32c); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map0, 0x330); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map1, 0x334); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map2, 0x338); +check_member(mt8186_infracfg_ao_regs, md2_bank0_map3, 0x33c); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map0, 0x350); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map1, 0x354); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map2, 0x358); +check_member(mt8186_infracfg_ao_regs, md2_bank4_map3, 0x35c); +check_member(mt8186_infracfg_ao_regs, c2k_config, 0x360); +check_member(mt8186_infracfg_ao_regs, c2k_status, 0x364); +check_member(mt8186_infracfg_ao_regs, c2k_spm_ctrl, 0x368); +check_member(mt8186_infracfg_ao_regs, ap2md_dummy, 0x370); +check_member(mt8186_infracfg_ao_regs, conn_map0, 0x380); +check_member(mt8186_infracfg_ao_regs, cldma_map0, 0x384); +check_member(mt8186_infracfg_ao_regs, conn_map1, 0x388); +check_member(mt8186_infracfg_ao_regs, conn_bus_con, 0x38c); +check_member(mt8186_infracfg_ao_regs, mcusys_dfd_map, 0x390); +check_member(mt8186_infracfg_ao_regs, conn_map3, 0x398); +check_member(mt8186_infracfg_ao_regs, conn_map4, 0x39c); +check_member(mt8186_infracfg_ao_regs, peri_cci_sideband_con, 0x400); +check_member(mt8186_infracfg_ao_regs, mfg_cci_sideband_con, 0x404); +check_member(mt8186_infracfg_ao_regs, infra_pwm_cksw_ctrl, 0x410); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con0, 0x500); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con1, 0x504); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con2, 0x508); +check_member(mt8186_infracfg_ao_regs, infra_ao_dbg_con3, 0x50c); +check_member(mt8186_infracfg_ao_regs, md_dbg_ck_con, 0x510); +check_member(mt8186_infracfg_ao_regs, mfg_misc_con, 0x600); +check_member(mt8186_infracfg_ao_regs, infra_msdc_con, 0x6fc); +check_member(mt8186_infracfg_ao_regs, infra_rsvd0, 0x700); +check_member(mt8186_infracfg_ao_regs, infra_rsvd1, 0x704); +check_member(mt8186_infracfg_ao_regs, infra_rsvd2, 0x708); +check_member(mt8186_infracfg_ao_regs, infra_rsvd3, 0x70c); +check_member(mt8186_infracfg_ao_regs, infra_rsvd4, 0x710); +check_member(mt8186_infracfg_ao_regs, infra_rsvd5, 0x714); +check_member(mt8186_infracfg_ao_regs, infra_iommu_en, 0x718); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key0, 0x880); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key1, 0x884); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key2, 0x888); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key3, 0x88c); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key4, 0x890); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key5, 0x894); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key6, 0x898); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key7, 0x89c); +check_member(mt8186_infracfg_ao_regs, md1_sbc_key_lock, 0x8a0); +check_member(mt8186_infracfg_ao_regs, md1_misc_lock, 0x8a8); +check_member(mt8186_infracfg_ao_regs, md1_misc, 0x8ac); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key0, 0x8b0); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key1, 0x8b4); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key2, 0x8b8); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key3, 0x8bc); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key4, 0x8c0); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key5, 0x8c4); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key6, 0x8c8); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key7, 0x8cc); +check_member(mt8186_infracfg_ao_regs, c2k_sbc_key_lock, 0x8d0); +check_member(mt8186_infracfg_ao_regs, infra_bonding, 0x900); +check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis0, 0x904); +check_member(mt8186_infracfg_ao_regs, subsys_pdn_nohang_dis1, 0x908); +check_member(mt8186_infracfg_ao_regs, infra_ao_scpsys_apb_async_sta, 0xa00); +check_member(mt8186_infracfg_ao_regs, infra_ao_md32_tx_apb_async_sta, 0xa04); +check_member(mt8186_infracfg_ao_regs, infra_ao_md32_rx_apb_async_sta, 0xa08); +check_member(mt8186_infracfg_ao_regs, infra_ao_cksys_apb_async_sta, 0xa0c); +check_member(mt8186_infracfg_ao_regs, infra_ao_pmic_wrap_tx_apb_async_sta, 0xa10); +check_member(mt8186_infracfg_ao_regs, infra_ao_pmif_spmi_tx_apb_async_sta, 0xa14); +check_member(mt8186_infracfg_ao_regs, infra_ao_spmi_mst_tx_apb_async_sta, 0xa18); +check_member(mt8186_infracfg_ao_regs, infra_ao_infra0_iommu_apb_async_sta, 0xa1c); +check_member(mt8186_infracfg_ao_regs, infra_ao_infra1_iommu_apb_async_sta, 0xa20); +check_member(mt8186_infracfg_ao_regs, infra_ao_mcu_pwr_mask, 0xa3c); +check_member(mt8186_infracfg_ao_regs, pll_ulposc_con0, 0xb00); +check_member(mt8186_infracfg_ao_regs, pll_ulposc_con1, 0xb04); +check_member(mt8186_infracfg_ao_regs, pll_auxadc_con0, 0xb10); +check_member(mt8186_infracfg_ao_regs, scp_infra_irq_set, 0xb14); +check_member(mt8186_infracfg_ao_regs, scp_infra_irq_clr, 0xb18); +check_member(mt8186_infracfg_ao_regs, scp_infra_ctrl, 0xb1c); +check_member(mt8186_infracfg_ao_regs, conn2infra_gals_dbg, 0xb20); +check_member(mt8186_infracfg_ao_regs, infra_infra2adsp_axi_gals_debug, 0xb24); +check_member(mt8186_infracfg_ao_regs, infra_adsp2infra_axi_gals_debug, 0xb28); +check_member(mt8186_infracfg_ao_regs, infra_adsp2emi_axi_gals_debug, 0xb2c); +check_member(mt8186_infracfg_ao_regs, nna0_1_emi_axi_gals_debug, 0xb30); +check_member(mt8186_infracfg_ao_regs, nna2_emi_axi_gals_debug, 0xb34); +check_member(mt8186_infracfg_ao_regs, nn2infra_axi_gals_debug, 0xb38); +check_member(mt8186_infracfg_ao_regs, infra2nna_axi_gals_debug, 0xb3c); +check_member(mt8186_infracfg_ao_regs, cldma_ctrl, 0xc00); +check_member(mt8186_infracfg_ao_regs, rg_ccif4_md_pwr_flag, 0xc10); +check_member(mt8186_infracfg_ao_regs, rg_ccif4_con_pwr_flag, 0xc14); +check_member(mt8186_infracfg_ao_regs, rd_ccif4_cpu_pwr_flag, 0xc18); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_set_ctrl_0, 0xc20); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_clr_ctrl_0, 0xc24); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_rw_ctrl_0, 0xc28); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_bcrm_extended_bus_protect_ro_ctrl_0, 0xc2c); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi_pwr_prot_ctrl_0, 0xc30); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_ipcfg_s_axi2sbus_ctrl_0, 0xc34); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip0sys_bus_asl7_axi_pwr_prot_ctrl_0, 0xc38); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip1sys_bus_asl8_axi_pwr_prot_ctrl_0, 0xc40); +check_member(mt8186_infracfg_ao_regs, + infra_ipsys_s_bus_u_lnk_si0_to_infra_ip2sys_bus_asl9_axi_pwr_prot_ctrl_0, 0xc44); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_0, 0xc48); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_1, 0xc4c); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_2, 0xc50); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_3, 0xc54); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_4, 0xc58); +check_member(mt8186_infracfg_ao_regs, infra_ipsys_s_bus_u_si0_ctrl_5, 0xc5c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg0, 0xd00); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg1, 0xd04); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg2, 0xd08); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg3, 0xd0c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg4, 0xd10); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg5, 0xd14); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg6, 0xd18); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg7, 0xd1c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg8, 0xd20); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg9, 0xd24); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg10, 0xd28); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg11, 0xd2c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg12, 0xd30); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg13, 0xd34); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg14, 0xd38); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg15, 0xd3c); +check_member(mt8186_infracfg_ao_regs, infrabus_dbg16, 0xd40); +check_member(mt8186_infracfg_ao_regs, infra_misc, 0xf00); +check_member(mt8186_infracfg_ao_regs, infra_acp, 0xf04); +check_member(mt8186_infracfg_ao_regs, misc_config, 0xf08); +check_member(mt8186_infracfg_ao_regs, infra_misc2, 0xf0c); +check_member(mt8186_infracfg_ao_regs, mdsys_misc_con, 0xf10); +check_member(mt8186_infracfg_ao_regs, nna_infra_gals_ctrl, 0xf44); +check_member(mt8186_infracfg_ao_regs, nna_emi_gals_ctrl, 0xf48); +check_member(mt8186_infracfg_ao_regs, infra_adsp_infra_gals_ctrl, 0xf4c); +check_member(mt8186_infracfg_ao_regs, infra_adsp_emi_gals_ctrl, 0xf50); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_con, 0xf80); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con0, 0xf84); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con1, 0xf88); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con0, 0xf8c); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con1, 0xf90); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con2, 0xf94); +check_member(mt8186_infracfg_ao_regs, dxcc_dcu_en_lock, 0xf98); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con2, 0xf9c); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_rst_con3, 0xfa0); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_cg_con3, 0xfa4); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_hyp, 0xfb0); +check_member(mt8186_infracfg_ao_regs, infra_mcu2emi_slice, 0xfb4); +check_member(mt8186_infracfg_ao_regs, infra_ao_sec_mfg_hyp, 0xfb8); + +static struct mt8186_infracfg_ao_regs *const mt8186_infracfg_ao = + (void *)INFRACFG_AO_BASE; + +#endif /* SOC_MEDIATEK_MT8186_INFRACFG_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/mcucfg.h b/src/soc/mediatek/mt8186/include/soc/mcucfg.h new file mode 100644 index 0000000000..48ca33dd51 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/mcucfg.h @@ -0,0 +1,947 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 4.1 + */ + +#ifndef SOC_MEDIATEK_MT8186_MCUCFG_H +#define SOC_MEDIATEK_MT8186_MCUCFG_H + +#include +#include + +struct mt8186_mcucfg_regs { + u32 reserved1[2]; + u32 mbista_mcsi_sf1_con; + u32 mbista_mcsi_sf1_result; + u32 mbista_mcsi_sf2_con; + u32 mbista_mcsi_sf2_result; + u32 mbista_etb_con; + u32 mbista_etb_result; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved2[2]; + u32 mbist_trigger_mux_ctl; + u32 reserved3[3]; + u32 dfd_ctrl; + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 reserved4[5]; + u32 mp_top_dbg_mon_sel; + u32 mp_top_dbg_mon; + u32 mp0_dbg_mon_sel; + u32 mp0_dbg_mon; + u32 reserved5[8]; + u32 l2_parity_clr; + u32 l2_parity_info1_cpu0; + u32 l2_parity_info2_cpu0; + u32 l2_parity_info1_cpu1; + u32 l2_parity_info2_cpu1; + u32 l2_parity_info1_cpu2; + u32 l2_parity_info2_cpu2; + u32 l2_parity_info1_cpu3; + u32 l2_parity_info2_cpu3; + u32 l2_parity_info1_cpu4; + u32 l2_parity_info2_cpu4; + u32 l2_parity_info1_cpu5; + u32 l2_parity_info2_cpu5; + u32 l2_parity_info1_cpu6; + u32 l2_parity_info2_cpu6; + u32 l2_parity_info1_cpu7; + u32 l2_parity_info2_cpu7; + u32 reserved6[10]; + u32 apmcu2emi_early_cke_ctl; + u32 cci_tra_cfg0; + u32 reserved7[4]; + u32 cci_tra_cfg5; + u32 cci_tra_cfg6; + u32 cci_tra_cfg7; + u32 cci_tra_cfg8; + u32 cci_tra_cfg9; + u32 cci_tra_cfg10; + u32 cci_tra_cfg11; + u32 cci_tra_cfg12; + u32 reserved8[51]; + u32 cci_m0_tra; + u32 cci_m1_tra; + u32 cci_m2_tra; + u32 reserved9[5]; + u32 cci_s1_tra; + u32 cci_s2_tra; + u32 cci_s3_tra; + u32 cci_s4_tra; + u32 reserved10[4]; + u32 cci_m0_tra_latch; + u32 cci_m1_tra_latch; + u32 cci_m2_tra_latch; + u32 reserved11[5]; + u32 cci_s1_tra_latch; + u32 cci_s2_tra_latch; + u32 cci_s3_tra_latch; + u32 cci_s4_tra_latch; + u32 reserved12[20]; + u32 cci_m0_if; + u32 cci_m1_if; + u32 cci_m2_if; + u32 reserved13[5]; + u32 cci_s1_if; + u32 cci_s2_if; + u32 cci_s3_if; + u32 cci_s4_if; + u32 reserved14[4]; + u32 cci_top_if; + u32 reserved15[7]; + u32 cci_m0_if_latch; + u32 cci_m1_if_latch; + u32 cci_m2_if_latch; + u32 reserved16[5]; + u32 cci_s1_if_latch; + u32 cci_s2_if_latch; + u32 cci_s3_if_latch; + u32 cci_s4_if_latch; + u32 reserved17[4]; + u32 cci_top_if_latch; + u32 reserved18[39]; + u32 l3c_share_status0; + u32 l3c_share_status1; + u32 l3c_share_status2; + u32 reserved19[1]; + u32 mp0_cpu0_dc_age; + u32 mp0_cpu1_dc_age; + u32 mp0_cpu2_dc_age; + u32 mp0_cpu3_dc_age; + u32 mp0_cpu4_dc_age; + u32 mp0_cpu5_dc_age; + u32 mp0_cpu6_dc_age; + u32 mp0_cpu7_dc_age; + u32 reserved20[52]; + u32 mp0_cpu0_nonwfx_ctrl; + u32 mp0_cpu0_nonwfx_cnt; + u32 mp0_cpu1_nonwfx_ctrl; + u32 mp0_cpu1_nonwfx_cnt; + u32 mp0_cpu2_nonwfx_ctrl; + u32 mp0_cpu2_nonwfx_cnt; + u32 mp0_cpu3_nonwfx_ctrl; + u32 mp0_cpu3_nonwfx_cnt; + u32 mp0_cpu4_nonwfx_ctrl; + u32 mp0_cpu4_nonwfx_cnt; + u32 mp0_cpu5_nonwfx_ctrl; + u32 mp0_cpu5_nonwfx_cnt; + u32 mp0_cpu6_nonwfx_ctrl; + u32 mp0_cpu6_nonwfx_cnt; + u32 mp0_cpu7_nonwfx_ctrl; + u32 mp0_cpu7_nonwfx_cnt; + u32 reserved21[48]; + u32 mp0_ses_apb_trig; + u32 reserved22[3]; + u32 wfx_ret_met_dbc_sel; + u32 reserved23[3]; + u32 adb_bist_cfg1; + u32 adb_bist_cfg2_md; + u32 adb_bist_cfg3_go; + u32 adb_bist_done; + u32 adb_bist_pass; + u32 reserved24[1667]; + u32 dfd_internal_ctl; + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_internal_chain_length_1; + u32 dfd_internal_chain_length_2; + u32 dfd_internal_chain_length_3; + u32 dfd_internal_test_so_0; + u32 dfd_internal_test_so_1; + u32 dfd_internal_num_of_test_so_gp; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsi; + u32 dfd_internal_mcsi_sel_status; + u32 dfd_v30_ctl; + u32 dfd_v30_base_addr; + u32 dfd_power_ctl; + u32 dfd_reset_on; + u32 dfd_test_si_0; + u32 dfd_test_si_1; + u32 dfd_status_clean; + u32 dfd_status_return; + u32 reserved25[21]; + u32 dfd_hw_trigger_mask; + u32 reserved26[64]; + u32 mcusys_par_wrap_dbg_mon_sel; + u32 mcusys_par_wrap_dbg_mon; + u32 mcusys_pinmux; + u32 reserved27[1]; + u32 l3c_share_cfg0; + u32 l3c_share_cfg1; + u32 l3c_share_cfg2; + u32 reserved28[1]; + u32 udi_cfg0; + u32 udi_cfg1; + u32 reserved29[2]; + u32 mcusys_core_status; + u32 reserved30[11]; + u32 mcusys_base; + u32 l3c_sram_base; + u32 gic_periph_base; + u32 cci_periph_base; + u32 cci_periph_infra_base; + u32 dfd_sram_base; + u32 l3c_mm_sram_base; + u32 reserved31[9]; + u32 cpu_plldiv_cfg0; + u32 cpu_plldiv_cfg1; + u32 cpu_plldiv_cfg2; + u32 reserved32[13]; + u32 bus_plldiv_cfg; + u32 reserved33[3]; + u32 plldiv_ctl0; + u32 reserved34[3]; + u32 mcsi_ram_delsel0; + u32 mcsi_ram_delsel1; + u32 reserved35[6]; + u32 etb_ram_delsel0; + u32 reserved36[23]; + u32 etb_cfg0; + u32 reserved37[31]; + u32 cci_rgu; + u32 reserved38[3]; + u32 mcsi_cfg0; + u32 mcsi_cfg1; + u32 mcsi_cfg2; + u32 mcsi_cfg3; + u32 mcsi_cfg4; + u32 reserved39[7]; + u32 mcsic_dcm0; + u32 mcsic_dcm1; + u32 reserved40[46]; + u32 mp_adb_dcm_cfg0; + u32 reserved41[1]; + u32 mp_adb_dcm_cfg2; + u32 reserved42[1]; + u32 mp_adb_dcm_cfg4; + u32 reserved43[1]; + u32 mp_misc_dcm_cfg0; + u32 reserved44[9]; + u32 etb_ck_ctl; + u32 reserved45[15]; + u32 dcc_cpu_con0; + u32 dcc_cpu_con1; + u32 dcc_cpu_con2; + u32 reserved46[5]; + u32 dcc_bus_con0; + u32 reserved47[7]; + u32 mcusys_dcm_cfg0; + u32 reserved48[15]; + u32 sec_pol_ctl_en0; + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 sec_pol_ctl_en19; + u32 int_pol_ctl0; + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 int_pol_ctl19; + u32 int_msk_ctl0; + u32 int_msk_ctl1; + u32 int_msk_ctl2; + u32 int_msk_ctl3; + u32 int_msk_ctl4; + u32 int_msk_ctl5; + u32 int_msk_ctl6; + u32 int_msk_ctl7; + u32 int_msk_ctl8; + u32 int_msk_ctl9; + u32 int_msk_ctl10; + u32 int_msk_ctl11; + u32 int_msk_ctl12; + u32 int_msk_ctl13; + u32 int_msk_ctl14; + u32 int_msk_ctl15; + u32 int_msk_ctl16; + u32 int_msk_ctl17; + u32 int_msk_ctl18; + u32 int_msk_ctl19; + u32 reserved49[1]; + u32 int_msk_ctl_all; + u32 int_cfg_indirect_access; + u32 int_cfg_direct_access_en; + u32 fcm_spmc_sw_cfg1; + u32 fcm_spmc_sw_cfg2; + u32 fcm_spmc_wait_cfg; + u32 fcm_spmc_sw_pchannel; + u32 fcm_spmc_pwr_status; + u32 fcm_spmc_off_thres; + u32 fcm_spmc_wdt_latch_info; + u32 reserved50[9]; + u32 mcusys_spmc_sw_cfg; + u32 mcusys_spmc_wait_cfg; + u32 mcusys_spmc_pwr_status; + u32 reserved51[45]; + u32 cpc_pllbuck_req_ctrl; + u32 mcusys_pwr_ctrl; + u32 cpusys_pwr_ctrl; + u32 sw_gic_wakeup_req; + u32 cpc_pllbuck_arb_weight; + u32 cpc_flow_ctrl_cfg; + u32 cpc_last_core_req; + u32 cpc_cpusys_last_core_resp; + u32 reserved52[1]; + u32 cpc_mcusys_last_core_resp; + u32 cpc_pwr_on_mask; + u32 reserved53[5]; + u32 cpc_spmc_pwr_status; + u32 cpc_core_cur_fsm; + u32 cpc_cpusys_mcusys_cur_fsm; + u32 cpc_wakeup_req; + u32 reserved54[3]; + u32 cpc_turbo_ctrl; + u32 cpc_turbo_gp0_ctrl; + u32 cpc_turbo_gp1_ctrl; + u32 cpc_turbo_gp2_ctrl; + u32 cpc_turbo_pwr_on_mask; + u32 cpc_turbo_gp0_req; + u32 cpc_turbo_gp1_req; + u32 cpc_turbo_gp2_req; + u32 reserved55[1]; + u32 cpc_turbo_gp0_resp; + u32 cpc_turbo_gp1_resp; + u32 cpc_turbo_gp2_resp; + u32 cpc_coh_block_thres; + u32 cpc_int_status; + u32 cpc_int_enable; + u32 pllbuck_group_func; + u32 cpc_dcm_enable; + u32 cpc_pllbuck_state; + u32 cpc_cpu_on_sw_hint; + u32 cpc_cpu_on_sw_hint_set; + u32 cpc_cpu_on_sw_hint_clear; + u32 reserved56[20]; + u32 emi_wfifo; + u32 axi1to4_cfg; + u32 reserved57[1]; + u32 emi_adb_edge_sel; + u32 reserved58[4]; + u32 sclk_cfg_slow_down_ck; + u32 reserved59[27]; + u32 mcusys_dbg_mon_sel; + u32 mcusys_dbg_mon; + u32 reserved60[58]; + u32 gic_acao_ctl0; + u32 gic_acao_ctl1; + u32 gic_acao_ctl2; + u32 reserved61[29]; + u32 spmc_dbg_setting; + u32 kernel_base_l; + u32 kernel_base_h; + u32 systime_base_l; + u32 systime_base_h; + u32 trace_data_selection; + u32 reserved62[2]; + u32 trace_data_entry0_l; + u32 trace_data_entry0_h; + u32 trace_data_entry1_l; + u32 trace_data_entry1_h; + u32 trace_data_entry2_l; + u32 trace_data_entry2_h; + u32 trace_data_entry3_l; + u32 trace_data_entry3_h; + u32 cpu0_on_off_latency; + u32 cpu1_on_off_latency; + u32 cpu2_on_off_latency; + u32 cpu3_on_off_latency; + u32 cpu4_on_off_latency; + u32 cpu5_on_off_latency; + u32 cpu6_on_off_latency; + u32 cpu7_on_off_latency; + u32 cluster_off_latency; + u32 cluster_on_latency; + u32 mcusys_on_off_latency; + u32 reserved63[1]; + u32 cluster_off_dormant_counter; + u32 cluster_off_dormant_counter_clear; + u32 reserved64[2]; + u32 cpc_wdt_latch_info1; + u32 cpc_wdt_latch_info2; + u32 cpc_wdt_latch_info3; + u32 cpc_wdt_latch_info4; + u32 cpc_wdt_latch_info5; + u32 cpc_pmu_ctrl; + u32 cpc_pmu_cnt_clr; + u32 cpc_pmu_cnt0; + u32 reserved65[88]; + u32 ildo_vproc2_en; + u32 reserved66[63]; + u32 pikachu_event; + u32 pikachu_status; + u32 reserved67[126]; + u32 cpu0_drcc_ao_config; + u32 reserved68[125]; + u32 cpu0_resereved_reg; + u32 cpu0_resereved_reg_rd; + u32 cpu1_drcc_ao_config; + u32 reserved69[125]; + u32 cpu1_resereved_reg; + u32 cpu1_resereved_reg_rd; + u32 cpu2_drcc_ao_config; + u32 reserved70[125]; + u32 cpu2_resereved_reg; + u32 cpu2_resereved_reg_rd; + u32 cpu3_drcc_ao_config; + u32 reserved71[125]; + u32 cpu3_resereved_reg; + u32 cpu3_resereved_reg_rd; + u32 cpu4_drcc_ao_config; + u32 reserved72[125]; + u32 cpu4_resereved_reg; + u32 cpu4_resereved_reg_rd; + u32 cpu5_drcc_ao_config; + u32 reserved73[125]; + u32 cpu5_resereved_reg; + u32 cpu5_resereved_reg_rd; + u32 cpu6_drcc_ao_config; + u32 reserved74[125]; + u32 cpu6_resereved_reg; + u32 cpu6_resereved_reg_rd; + u32 cpu7_drcc_ao_config; + u32 reserved75[125]; + u32 cpu7_resereved_reg; + u32 cpu7_resereved_reg_rd; + u32 reserved76[528]; + u32 mp0_l3_data_ram_delsel; + u32 mp0_l3_tag_ram_delsel; + u32 mp0_l3_victim_ram_delsel; + u32 mp0_l3_scu_sf_ram_delsel; + u32 reserved77[12]; + u32 mp0_dcm_cfg0; + u32 mp0_dcm_cfg1; + u32 mp0_dcm_cfg2; + u32 mp0_dcm_cfg3; + u32 mp0_dcm_cfg4; + u32 mp0_dcm_cfg5; + u32 mp0_dcm_cfg6; + u32 mp0_dcm_cfg7; + u32 mp0_dcm_cfg8; + u32 reserved78[7]; + u32 mp0_l3_cache_parity1; + u32 mp0_l3_cache_parity2; + u32 mp0_l3_cache_parity3; + u32 reserved79[1]; + u32 mp0_cluster_cfg0; + u32 reserved80[3]; + u32 mp0_cluster_cfg4; + u32 mp0_cluster_cfg5; + u32 mp0_cluster_cfg6; + u32 mp0_cluster_cfg7; + u32 reserved81[4]; + u32 mp0_cluster_cfg8; + u32 mp0_cluster_cfg9; + u32 mp0_cluster_cfg10; + u32 mp0_cluster_cfg11; + u32 mp0_cluster_cfg12; + u32 mp0_cluster_cfg13; + u32 mp0_cluster_cfg14; + u32 mp0_cluster_cfg15; + u32 mp0_cluster_cfg16; + u32 mp0_cluster_cfg17; + u32 mp0_cluster_cfg18; + u32 mp0_cluster_cfg19; + u32 mp0_cluster_cfg20; + u32 mp0_cluster_cfg21; + u32 mp0_cluster_cfg22; + u32 mp0_cluster_cfg23; + u32 reserved82[1]; + u32 mp0_victim_rd_mask; + u32 reserved83[174]; + u32 cpu_type0_spmc0_cfg; + u32 reserved84[7]; + u32 cpu_type0_ram_delsel0_cfg; + u32 cpu_type0_ram_delsel1_cfg; + u32 cpu_type0_ram_delsel2_cfg; + u32 reserved85[53]; + u32 cpu_type1_spmc0_cfg; + u32 reserved86[3]; + u32 cpu_type1_mpmmen; + u32 reserved87[3]; + u32 cpu_type1_ram_delsel0_cfg; + u32 cpu_type1_ram_delsel1_cfg; + u32 cpu_type1_ram_delsel2_cfg; + u32 reserved88[53]; + u32 plldiv_turbo; + u32 plldiv_percore_dfs_1; + u32 plldiv_percore_dfs_2; + u32 plldiv_imax_cg; + u32 plldiv_imax_int; + u32 plldiv_imax_detector; + u32 plldiv_little_reserved; + u32 plldiv_big_reserved; + u32 plldiv_bus_reserved; + u32 reserved89[3183]; + u32 mcusys_reserved_reg0; + u32 mcusys_reserved_reg1; + u32 mcusys_reserved_reg2; + u32 mcusys_reserved_reg3; + u32 mcusys_reserved_reg0_rd; + u32 mcusys_reserved_reg1_rd; + u32 mcusys_reserved_reg2_rd; + u32 mcusys_reserved_reg3_rd; +}; + +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_con, 0x8); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf1_result, 0xc); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_con, 0x10); +check_member(mt8186_mcucfg_regs, mbista_mcsi_sf2_result, 0x14); +check_member(mt8186_mcucfg_regs, mbista_etb_con, 0x18); +check_member(mt8186_mcucfg_regs, mbista_etb_result, 0x1c); +check_member(mt8186_mcucfg_regs, mbista_rstb, 0x20); +check_member(mt8186_mcucfg_regs, mbista_all_result, 0x24); +check_member(mt8186_mcucfg_regs, mbist_trigger_mux_ctl, 0x30); +check_member(mt8186_mcucfg_regs, dfd_ctrl, 0x40); +check_member(mt8186_mcucfg_regs, dfd_cnt_l, 0x44); +check_member(mt8186_mcucfg_regs, dfd_cnt_h, 0x48); +check_member(mt8186_mcucfg_regs, mp_top_dbg_mon_sel, 0x60); +check_member(mt8186_mcucfg_regs, mp_top_dbg_mon, 0x64); +check_member(mt8186_mcucfg_regs, mp0_dbg_mon_sel, 0x68); +check_member(mt8186_mcucfg_regs, mp0_dbg_mon, 0x6c); +check_member(mt8186_mcucfg_regs, l2_parity_clr, 0x90); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu0, 0x94); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu0, 0x98); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu1, 0x9c); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu1, 0xa0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu2, 0xa4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu2, 0xa8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu3, 0xac); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu3, 0xb0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu4, 0xb4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu4, 0xb8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu5, 0xbc); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu5, 0xc0); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu6, 0xc4); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu6, 0xc8); +check_member(mt8186_mcucfg_regs, l2_parity_info1_cpu7, 0xcc); +check_member(mt8186_mcucfg_regs, l2_parity_info2_cpu7, 0xd0); +check_member(mt8186_mcucfg_regs, apmcu2emi_early_cke_ctl, 0xfc); +check_member(mt8186_mcucfg_regs, cci_tra_cfg0, 0x100); +check_member(mt8186_mcucfg_regs, cci_tra_cfg5, 0x114); +check_member(mt8186_mcucfg_regs, cci_tra_cfg6, 0x118); +check_member(mt8186_mcucfg_regs, cci_tra_cfg7, 0x11c); +check_member(mt8186_mcucfg_regs, cci_tra_cfg8, 0x120); +check_member(mt8186_mcucfg_regs, cci_tra_cfg9, 0x124); +check_member(mt8186_mcucfg_regs, cci_tra_cfg10, 0x128); +check_member(mt8186_mcucfg_regs, cci_tra_cfg11, 0x12c); +check_member(mt8186_mcucfg_regs, cci_tra_cfg12, 0x130); +check_member(mt8186_mcucfg_regs, cci_m0_tra, 0x200); +check_member(mt8186_mcucfg_regs, cci_m1_tra, 0x204); +check_member(mt8186_mcucfg_regs, cci_m2_tra, 0x208); +check_member(mt8186_mcucfg_regs, cci_s1_tra, 0x220); +check_member(mt8186_mcucfg_regs, cci_s2_tra, 0x224); +check_member(mt8186_mcucfg_regs, cci_s3_tra, 0x228); +check_member(mt8186_mcucfg_regs, cci_s4_tra, 0x22c); +check_member(mt8186_mcucfg_regs, cci_m0_tra_latch, 0x240); +check_member(mt8186_mcucfg_regs, cci_m1_tra_latch, 0x244); +check_member(mt8186_mcucfg_regs, cci_m2_tra_latch, 0x248); +check_member(mt8186_mcucfg_regs, cci_s1_tra_latch, 0x260); +check_member(mt8186_mcucfg_regs, cci_s2_tra_latch, 0x264); +check_member(mt8186_mcucfg_regs, cci_s3_tra_latch, 0x268); +check_member(mt8186_mcucfg_regs, cci_s4_tra_latch, 0x26c); +check_member(mt8186_mcucfg_regs, cci_m0_if, 0x2c0); +check_member(mt8186_mcucfg_regs, cci_m1_if, 0x2c4); +check_member(mt8186_mcucfg_regs, cci_m2_if, 0x2c8); +check_member(mt8186_mcucfg_regs, cci_s1_if, 0x2e0); +check_member(mt8186_mcucfg_regs, cci_s2_if, 0x2e4); +check_member(mt8186_mcucfg_regs, cci_s3_if, 0x2e8); +check_member(mt8186_mcucfg_regs, cci_s4_if, 0x2ec); +check_member(mt8186_mcucfg_regs, cci_top_if, 0x300); +check_member(mt8186_mcucfg_regs, cci_m0_if_latch, 0x320); +check_member(mt8186_mcucfg_regs, cci_m1_if_latch, 0x324); +check_member(mt8186_mcucfg_regs, cci_m2_if_latch, 0x328); +check_member(mt8186_mcucfg_regs, cci_s1_if_latch, 0x340); +check_member(mt8186_mcucfg_regs, cci_s2_if_latch, 0x344); +check_member(mt8186_mcucfg_regs, cci_s3_if_latch, 0x348); +check_member(mt8186_mcucfg_regs, cci_s4_if_latch, 0x34c); +check_member(mt8186_mcucfg_regs, cci_top_if_latch, 0x360); +check_member(mt8186_mcucfg_regs, l3c_share_status0, 0x400); +check_member(mt8186_mcucfg_regs, l3c_share_status1, 0x404); +check_member(mt8186_mcucfg_regs, l3c_share_status2, 0x408); +check_member(mt8186_mcucfg_regs, mp0_cpu0_dc_age, 0x410); +check_member(mt8186_mcucfg_regs, mp0_cpu1_dc_age, 0x414); +check_member(mt8186_mcucfg_regs, mp0_cpu2_dc_age, 0x418); +check_member(mt8186_mcucfg_regs, mp0_cpu3_dc_age, 0x41c); +check_member(mt8186_mcucfg_regs, mp0_cpu4_dc_age, 0x420); +check_member(mt8186_mcucfg_regs, mp0_cpu5_dc_age, 0x424); +check_member(mt8186_mcucfg_regs, mp0_cpu6_dc_age, 0x428); +check_member(mt8186_mcucfg_regs, mp0_cpu7_dc_age, 0x42c); +check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_ctrl, 0x500); +check_member(mt8186_mcucfg_regs, mp0_cpu0_nonwfx_cnt, 0x504); +check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_ctrl, 0x508); +check_member(mt8186_mcucfg_regs, mp0_cpu1_nonwfx_cnt, 0x50c); +check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_ctrl, 0x510); +check_member(mt8186_mcucfg_regs, mp0_cpu2_nonwfx_cnt, 0x514); +check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_ctrl, 0x518); +check_member(mt8186_mcucfg_regs, mp0_cpu3_nonwfx_cnt, 0x51c); +check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_ctrl, 0x520); +check_member(mt8186_mcucfg_regs, mp0_cpu4_nonwfx_cnt, 0x524); +check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_ctrl, 0x528); +check_member(mt8186_mcucfg_regs, mp0_cpu5_nonwfx_cnt, 0x52c); +check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_ctrl, 0x530); +check_member(mt8186_mcucfg_regs, mp0_cpu6_nonwfx_cnt, 0x534); +check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_ctrl, 0x538); +check_member(mt8186_mcucfg_regs, mp0_cpu7_nonwfx_cnt, 0x53c); +check_member(mt8186_mcucfg_regs, mp0_ses_apb_trig, 0x600); +check_member(mt8186_mcucfg_regs, wfx_ret_met_dbc_sel, 0x610); +check_member(mt8186_mcucfg_regs, adb_bist_cfg1, 0x620); +check_member(mt8186_mcucfg_regs, adb_bist_cfg2_md, 0x624); +check_member(mt8186_mcucfg_regs, adb_bist_cfg3_go, 0x628); +check_member(mt8186_mcucfg_regs, adb_bist_done, 0x62c); +check_member(mt8186_mcucfg_regs, adb_bist_pass, 0x630); +check_member(mt8186_mcucfg_regs, dfd_internal_ctl, 0x2040); +check_member(mt8186_mcucfg_regs, dfd_internal_counter, 0x2044); +check_member(mt8186_mcucfg_regs, dfd_internal_pwr_on, 0x2048); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_legth_0, 0x204c); +check_member(mt8186_mcucfg_regs, dfd_internal_shift_clk_ratio, 0x2050); +check_member(mt8186_mcucfg_regs, dfd_internal_counter_return, 0x2054); +check_member(mt8186_mcucfg_regs, dfd_internal_sram_access, 0x2058); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_1, 0x205c); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_2, 0x2060); +check_member(mt8186_mcucfg_regs, dfd_internal_chain_length_3, 0x2064); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_0, 0x2068); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_1, 0x206c); +check_member(mt8186_mcucfg_regs, dfd_internal_num_of_test_so_gp, 0x2070); +check_member(mt8186_mcucfg_regs, dfd_internal_test_so_over_64, 0x2074); +check_member(mt8186_mcucfg_regs, dfd_internal_mask_out, 0x2078); +check_member(mt8186_mcucfg_regs, dfd_internal_sw_ns_trigger, 0x207c); +check_member(mt8186_mcucfg_regs, dfd_internal_mcsi, 0x2080); +check_member(mt8186_mcucfg_regs, dfd_internal_mcsi_sel_status, 0x2084); +check_member(mt8186_mcucfg_regs, dfd_v30_ctl, 0x2088); +check_member(mt8186_mcucfg_regs, dfd_v30_base_addr, 0x208c); +check_member(mt8186_mcucfg_regs, dfd_power_ctl, 0x2090); +check_member(mt8186_mcucfg_regs, dfd_reset_on, 0x2094); +check_member(mt8186_mcucfg_regs, dfd_test_si_0, 0x2098); +check_member(mt8186_mcucfg_regs, dfd_test_si_1, 0x209c); +check_member(mt8186_mcucfg_regs, dfd_status_clean, 0x20a0); +check_member(mt8186_mcucfg_regs, dfd_status_return, 0x20a4); +check_member(mt8186_mcucfg_regs, dfd_hw_trigger_mask, 0x20fc); +check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon_sel, 0x2200); +check_member(mt8186_mcucfg_regs, mcusys_par_wrap_dbg_mon, 0x2204); +check_member(mt8186_mcucfg_regs, mcusys_pinmux, 0x2208); +check_member(mt8186_mcucfg_regs, l3c_share_cfg0, 0x2210); +check_member(mt8186_mcucfg_regs, l3c_share_cfg1, 0x2214); +check_member(mt8186_mcucfg_regs, l3c_share_cfg2, 0x2218); +check_member(mt8186_mcucfg_regs, udi_cfg0, 0x2220); +check_member(mt8186_mcucfg_regs, udi_cfg1, 0x2224); +check_member(mt8186_mcucfg_regs, mcusys_core_status, 0x2230); +check_member(mt8186_mcucfg_regs, mcusys_base, 0x2260); +check_member(mt8186_mcucfg_regs, l3c_sram_base, 0x2264); +check_member(mt8186_mcucfg_regs, gic_periph_base, 0x2268); +check_member(mt8186_mcucfg_regs, cci_periph_base, 0x226c); +check_member(mt8186_mcucfg_regs, cci_periph_infra_base, 0x2270); +check_member(mt8186_mcucfg_regs, dfd_sram_base, 0x2274); +check_member(mt8186_mcucfg_regs, l3c_mm_sram_base, 0x2278); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg1, 0x22a4); +check_member(mt8186_mcucfg_regs, cpu_plldiv_cfg2, 0x22a8); +check_member(mt8186_mcucfg_regs, bus_plldiv_cfg, 0x22e0); +check_member(mt8186_mcucfg_regs, plldiv_ctl0, 0x22f0); +check_member(mt8186_mcucfg_regs, mcsi_ram_delsel0, 0x2300); +check_member(mt8186_mcucfg_regs, mcsi_ram_delsel1, 0x2304); +check_member(mt8186_mcucfg_regs, etb_ram_delsel0, 0x2320); +check_member(mt8186_mcucfg_regs, etb_cfg0, 0x2380); +check_member(mt8186_mcucfg_regs, cci_rgu, 0x2400); +check_member(mt8186_mcucfg_regs, mcsi_cfg0, 0x2410); +check_member(mt8186_mcucfg_regs, mcsi_cfg1, 0x2414); +check_member(mt8186_mcucfg_regs, mcsi_cfg2, 0x2418); +check_member(mt8186_mcucfg_regs, mcsi_cfg3, 0x241c); +check_member(mt8186_mcucfg_regs, mcsi_cfg4, 0x2420); +check_member(mt8186_mcucfg_regs, mcsic_dcm0, 0x2440); +check_member(mt8186_mcucfg_regs, mcsic_dcm1, 0x2444); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg0, 0x2500); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg2, 0x2508); +check_member(mt8186_mcucfg_regs, mp_adb_dcm_cfg4, 0x2510); +check_member(mt8186_mcucfg_regs, mp_misc_dcm_cfg0, 0x2518); +check_member(mt8186_mcucfg_regs, etb_ck_ctl, 0x2540); +check_member(mt8186_mcucfg_regs, dcc_cpu_con0, 0x2580); +check_member(mt8186_mcucfg_regs, dcc_cpu_con1, 0x2584); +check_member(mt8186_mcucfg_regs, dcc_cpu_con2, 0x2588); +check_member(mt8186_mcucfg_regs, dcc_bus_con0, 0x25a0); +check_member(mt8186_mcucfg_regs, mcusys_dcm_cfg0, 0x25c0); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en0, 0x2600); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en1, 0x2604); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en2, 0x2608); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en3, 0x260c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en4, 0x2610); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en5, 0x2614); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en6, 0x2618); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en7, 0x261c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en8, 0x2620); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en9, 0x2624); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en10, 0x2628); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en11, 0x262c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en12, 0x2630); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en13, 0x2634); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en14, 0x2638); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en15, 0x263c); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en16, 0x2640); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en17, 0x2644); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en18, 0x2648); +check_member(mt8186_mcucfg_regs, sec_pol_ctl_en19, 0x264c); +check_member(mt8186_mcucfg_regs, int_pol_ctl0, 0x2650); +check_member(mt8186_mcucfg_regs, int_pol_ctl1, 0x2654); +check_member(mt8186_mcucfg_regs, int_pol_ctl2, 0x2658); +check_member(mt8186_mcucfg_regs, int_pol_ctl3, 0x265c); +check_member(mt8186_mcucfg_regs, int_pol_ctl4, 0x2660); +check_member(mt8186_mcucfg_regs, int_pol_ctl5, 0x2664); +check_member(mt8186_mcucfg_regs, int_pol_ctl6, 0x2668); +check_member(mt8186_mcucfg_regs, int_pol_ctl7, 0x266c); +check_member(mt8186_mcucfg_regs, int_pol_ctl8, 0x2670); +check_member(mt8186_mcucfg_regs, int_pol_ctl9, 0x2674); +check_member(mt8186_mcucfg_regs, int_pol_ctl10, 0x2678); +check_member(mt8186_mcucfg_regs, int_pol_ctl11, 0x267c); +check_member(mt8186_mcucfg_regs, int_pol_ctl12, 0x2680); +check_member(mt8186_mcucfg_regs, int_pol_ctl13, 0x2684); +check_member(mt8186_mcucfg_regs, int_pol_ctl14, 0x2688); +check_member(mt8186_mcucfg_regs, int_pol_ctl15, 0x268c); +check_member(mt8186_mcucfg_regs, int_pol_ctl16, 0x2690); +check_member(mt8186_mcucfg_regs, int_pol_ctl17, 0x2694); +check_member(mt8186_mcucfg_regs, int_pol_ctl18, 0x2698); +check_member(mt8186_mcucfg_regs, int_pol_ctl19, 0x269c); +check_member(mt8186_mcucfg_regs, int_msk_ctl0, 0x26a0); +check_member(mt8186_mcucfg_regs, int_msk_ctl1, 0x26a4); +check_member(mt8186_mcucfg_regs, int_msk_ctl2, 0x26a8); +check_member(mt8186_mcucfg_regs, int_msk_ctl3, 0x26ac); +check_member(mt8186_mcucfg_regs, int_msk_ctl4, 0x26b0); +check_member(mt8186_mcucfg_regs, int_msk_ctl5, 0x26b4); +check_member(mt8186_mcucfg_regs, int_msk_ctl6, 0x26b8); +check_member(mt8186_mcucfg_regs, int_msk_ctl7, 0x26bc); +check_member(mt8186_mcucfg_regs, int_msk_ctl8, 0x26c0); +check_member(mt8186_mcucfg_regs, int_msk_ctl9, 0x26c4); +check_member(mt8186_mcucfg_regs, int_msk_ctl10, 0x26c8); +check_member(mt8186_mcucfg_regs, int_msk_ctl11, 0x26cc); +check_member(mt8186_mcucfg_regs, int_msk_ctl12, 0x26d0); +check_member(mt8186_mcucfg_regs, int_msk_ctl13, 0x26d4); +check_member(mt8186_mcucfg_regs, int_msk_ctl14, 0x26d8); +check_member(mt8186_mcucfg_regs, int_msk_ctl15, 0x26dc); +check_member(mt8186_mcucfg_regs, int_msk_ctl16, 0x26e0); +check_member(mt8186_mcucfg_regs, int_msk_ctl17, 0x26e4); +check_member(mt8186_mcucfg_regs, int_msk_ctl18, 0x26e8); +check_member(mt8186_mcucfg_regs, int_msk_ctl19, 0x26ec); +check_member(mt8186_mcucfg_regs, int_msk_ctl_all, 0x26f4); +check_member(mt8186_mcucfg_regs, int_cfg_indirect_access, 0x26f8); +check_member(mt8186_mcucfg_regs, int_cfg_direct_access_en, 0x26fc); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg1, 0x2700); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_cfg2, 0x2704); +check_member(mt8186_mcucfg_regs, fcm_spmc_wait_cfg, 0x2708); +check_member(mt8186_mcucfg_regs, fcm_spmc_sw_pchannel, 0x270c); +check_member(mt8186_mcucfg_regs, fcm_spmc_pwr_status, 0x2710); +check_member(mt8186_mcucfg_regs, fcm_spmc_off_thres, 0x2714); +check_member(mt8186_mcucfg_regs, fcm_spmc_wdt_latch_info, 0x2718); +check_member(mt8186_mcucfg_regs, mcusys_spmc_sw_cfg, 0x2740); +check_member(mt8186_mcucfg_regs, mcusys_spmc_wait_cfg, 0x2744); +check_member(mt8186_mcucfg_regs, mcusys_spmc_pwr_status, 0x2748); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_req_ctrl, 0x2800); +check_member(mt8186_mcucfg_regs, mcusys_pwr_ctrl, 0x2804); +check_member(mt8186_mcucfg_regs, cpusys_pwr_ctrl, 0x2808); +check_member(mt8186_mcucfg_regs, sw_gic_wakeup_req, 0x280c); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_arb_weight, 0x2810); +check_member(mt8186_mcucfg_regs, cpc_flow_ctrl_cfg, 0x2814); +check_member(mt8186_mcucfg_regs, cpc_last_core_req, 0x2818); +check_member(mt8186_mcucfg_regs, cpc_cpusys_last_core_resp, 0x281c); +check_member(mt8186_mcucfg_regs, cpc_mcusys_last_core_resp, 0x2824); +check_member(mt8186_mcucfg_regs, cpc_pwr_on_mask, 0x2828); +check_member(mt8186_mcucfg_regs, cpc_spmc_pwr_status, 0x2840); +check_member(mt8186_mcucfg_regs, cpc_core_cur_fsm, 0x2844); +check_member(mt8186_mcucfg_regs, cpc_cpusys_mcusys_cur_fsm, 0x2848); +check_member(mt8186_mcucfg_regs, cpc_wakeup_req, 0x284c); +check_member(mt8186_mcucfg_regs, cpc_turbo_ctrl, 0x285c); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_ctrl, 0x2860); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_ctrl, 0x2864); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_ctrl, 0x2868); +check_member(mt8186_mcucfg_regs, cpc_turbo_pwr_on_mask, 0x286c); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_req, 0x2870); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_req, 0x2874); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_req, 0x2878); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp0_resp, 0x2880); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp1_resp, 0x2884); +check_member(mt8186_mcucfg_regs, cpc_turbo_gp2_resp, 0x2888); +check_member(mt8186_mcucfg_regs, cpc_coh_block_thres, 0x288c); +check_member(mt8186_mcucfg_regs, cpc_int_status, 0x2890); +check_member(mt8186_mcucfg_regs, cpc_int_enable, 0x2894); +check_member(mt8186_mcucfg_regs, pllbuck_group_func, 0x2898); +check_member(mt8186_mcucfg_regs, cpc_dcm_enable, 0x289c); +check_member(mt8186_mcucfg_regs, cpc_pllbuck_state, 0x28a0); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint, 0x28a4); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_set, 0x28a8); +check_member(mt8186_mcucfg_regs, cpc_cpu_on_sw_hint_clear, 0x28ac); +check_member(mt8186_mcucfg_regs, emi_wfifo, 0x2900); +check_member(mt8186_mcucfg_regs, axi1to4_cfg, 0x2904); +check_member(mt8186_mcucfg_regs, emi_adb_edge_sel, 0x290c); +check_member(mt8186_mcucfg_regs, sclk_cfg_slow_down_ck, 0x2920); +check_member(mt8186_mcucfg_regs, mcusys_dbg_mon_sel, 0x2990); +check_member(mt8186_mcucfg_regs, mcusys_dbg_mon, 0x2994); +check_member(mt8186_mcucfg_regs, gic_acao_ctl0, 0x2a80); +check_member(mt8186_mcucfg_regs, gic_acao_ctl1, 0x2a84); +check_member(mt8186_mcucfg_regs, gic_acao_ctl2, 0x2a88); +check_member(mt8186_mcucfg_regs, spmc_dbg_setting, 0x2b00); +check_member(mt8186_mcucfg_regs, kernel_base_l, 0x2b04); +check_member(mt8186_mcucfg_regs, kernel_base_h, 0x2b08); +check_member(mt8186_mcucfg_regs, systime_base_l, 0x2b0c); +check_member(mt8186_mcucfg_regs, systime_base_h, 0x2b10); +check_member(mt8186_mcucfg_regs, trace_data_selection, 0x2b14); +check_member(mt8186_mcucfg_regs, trace_data_entry0_l, 0x2b20); +check_member(mt8186_mcucfg_regs, trace_data_entry0_h, 0x2b24); +check_member(mt8186_mcucfg_regs, trace_data_entry1_l, 0x2b28); +check_member(mt8186_mcucfg_regs, trace_data_entry1_h, 0x2b2c); +check_member(mt8186_mcucfg_regs, trace_data_entry2_l, 0x2b30); +check_member(mt8186_mcucfg_regs, trace_data_entry2_h, 0x2b34); +check_member(mt8186_mcucfg_regs, trace_data_entry3_l, 0x2b38); +check_member(mt8186_mcucfg_regs, trace_data_entry3_h, 0x2b3c); +check_member(mt8186_mcucfg_regs, cpu0_on_off_latency, 0x2b40); +check_member(mt8186_mcucfg_regs, cpu1_on_off_latency, 0x2b44); +check_member(mt8186_mcucfg_regs, cpu2_on_off_latency, 0x2b48); +check_member(mt8186_mcucfg_regs, cpu3_on_off_latency, 0x2b4c); +check_member(mt8186_mcucfg_regs, cpu4_on_off_latency, 0x2b50); +check_member(mt8186_mcucfg_regs, cpu5_on_off_latency, 0x2b54); +check_member(mt8186_mcucfg_regs, cpu6_on_off_latency, 0x2b58); +check_member(mt8186_mcucfg_regs, cpu7_on_off_latency, 0x2b5c); +check_member(mt8186_mcucfg_regs, cluster_off_latency, 0x2b60); +check_member(mt8186_mcucfg_regs, cluster_on_latency, 0x2b64); +check_member(mt8186_mcucfg_regs, mcusys_on_off_latency, 0x2b68); +check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter, 0x2b70); +check_member(mt8186_mcucfg_regs, cluster_off_dormant_counter_clear, 0x2b74); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info1, 0x2b80); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info2, 0x2b84); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info3, 0x2b88); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info4, 0x2b8c); +check_member(mt8186_mcucfg_regs, cpc_wdt_latch_info5, 0x2b90); +check_member(mt8186_mcucfg_regs, cpc_pmu_ctrl, 0x2b94); +check_member(mt8186_mcucfg_regs, cpc_pmu_cnt_clr, 0x2b98); +check_member(mt8186_mcucfg_regs, cpc_pmu_cnt0, 0x2b9c); +check_member(mt8186_mcucfg_regs, ildo_vproc2_en, 0x2d00); +check_member(mt8186_mcucfg_regs, pikachu_event, 0x2e00); +check_member(mt8186_mcucfg_regs, pikachu_status, 0x2e04); +check_member(mt8186_mcucfg_regs, cpu0_drcc_ao_config, 0x3000); +check_member(mt8186_mcucfg_regs, cpu0_resereved_reg, 0x31f8); +check_member(mt8186_mcucfg_regs, cpu0_resereved_reg_rd, 0x31fc); +check_member(mt8186_mcucfg_regs, cpu1_drcc_ao_config, 0x3200); +check_member(mt8186_mcucfg_regs, cpu1_resereved_reg, 0x33f8); +check_member(mt8186_mcucfg_regs, cpu1_resereved_reg_rd, 0x33fc); +check_member(mt8186_mcucfg_regs, cpu2_drcc_ao_config, 0x3400); +check_member(mt8186_mcucfg_regs, cpu2_resereved_reg, 0x35f8); +check_member(mt8186_mcucfg_regs, cpu2_resereved_reg_rd, 0x35fc); +check_member(mt8186_mcucfg_regs, cpu3_drcc_ao_config, 0x3600); +check_member(mt8186_mcucfg_regs, cpu3_resereved_reg, 0x37f8); +check_member(mt8186_mcucfg_regs, cpu3_resereved_reg_rd, 0x37fc); +check_member(mt8186_mcucfg_regs, cpu4_drcc_ao_config, 0x3800); +check_member(mt8186_mcucfg_regs, cpu4_resereved_reg, 0x39f8); +check_member(mt8186_mcucfg_regs, cpu4_resereved_reg_rd, 0x39fc); +check_member(mt8186_mcucfg_regs, cpu5_drcc_ao_config, 0x3a00); +check_member(mt8186_mcucfg_regs, cpu5_resereved_reg, 0x3bf8); +check_member(mt8186_mcucfg_regs, cpu5_resereved_reg_rd, 0x3bfc); +check_member(mt8186_mcucfg_regs, cpu6_drcc_ao_config, 0x3c00); +check_member(mt8186_mcucfg_regs, cpu6_resereved_reg, 0x3df8); +check_member(mt8186_mcucfg_regs, cpu6_resereved_reg_rd, 0x3dfc); +check_member(mt8186_mcucfg_regs, cpu7_drcc_ao_config, 0x3e00); +check_member(mt8186_mcucfg_regs, cpu7_resereved_reg, 0x3ff8); +check_member(mt8186_mcucfg_regs, cpu7_resereved_reg_rd, 0x3ffc); +check_member(mt8186_mcucfg_regs, mp0_l3_data_ram_delsel, 0x4840); +check_member(mt8186_mcucfg_regs, mp0_l3_tag_ram_delsel, 0x4844); +check_member(mt8186_mcucfg_regs, mp0_l3_victim_ram_delsel, 0x4848); +check_member(mt8186_mcucfg_regs, mp0_l3_scu_sf_ram_delsel, 0x484c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg0, 0x4880); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg1, 0x4884); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg2, 0x4888); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg3, 0x488c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg4, 0x4890); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg5, 0x4894); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg6, 0x4898); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg7, 0x489c); +check_member(mt8186_mcucfg_regs, mp0_dcm_cfg8, 0x48a0); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity1, 0x48c0); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity2, 0x48c4); +check_member(mt8186_mcucfg_regs, mp0_l3_cache_parity3, 0x48c8); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg0, 0x48d0); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg4, 0x48e0); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg5, 0x48e4); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg6, 0x48e8); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg7, 0x48ec); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg8, 0x4900); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg9, 0x4904); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg10, 0x4908); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg11, 0x490c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg12, 0x4910); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg13, 0x4914); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg14, 0x4918); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg15, 0x491c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg16, 0x4920); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg17, 0x4924); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg18, 0x4928); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg19, 0x492c); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg20, 0x4930); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg21, 0x4934); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg22, 0x4938); +check_member(mt8186_mcucfg_regs, mp0_cluster_cfg23, 0x493c); +check_member(mt8186_mcucfg_regs, mp0_victim_rd_mask, 0x4944); +check_member(mt8186_mcucfg_regs, cpu_type0_spmc0_cfg, 0x4c00); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel0_cfg, 0x4c20); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel1_cfg, 0x4c24); +check_member(mt8186_mcucfg_regs, cpu_type0_ram_delsel2_cfg, 0x4c28); +check_member(mt8186_mcucfg_regs, cpu_type1_spmc0_cfg, 0x4d00); +check_member(mt8186_mcucfg_regs, cpu_type1_mpmmen, 0x4d10); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel0_cfg, 0x4d20); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel1_cfg, 0x4d24); +check_member(mt8186_mcucfg_regs, cpu_type1_ram_delsel2_cfg, 0x4d28); +check_member(mt8186_mcucfg_regs, plldiv_turbo, 0x4e00); +check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_1, 0x4e04); +check_member(mt8186_mcucfg_regs, plldiv_percore_dfs_2, 0x4e08); +check_member(mt8186_mcucfg_regs, plldiv_imax_cg, 0x4e0c); +check_member(mt8186_mcucfg_regs, plldiv_imax_int, 0x4e10); +check_member(mt8186_mcucfg_regs, plldiv_imax_detector, 0x4e14); +check_member(mt8186_mcucfg_regs, plldiv_little_reserved, 0x4e18); +check_member(mt8186_mcucfg_regs, plldiv_big_reserved, 0x4e1c); +check_member(mt8186_mcucfg_regs, plldiv_bus_reserved, 0x4e20); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1, 0x7fe4); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2, 0x7fe8); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3, 0x7fec); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg0_rd, 0x7ff0); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg1_rd, 0x7ff4); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg2_rd, 0x7ff8); +check_member(mt8186_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); + +static struct mt8186_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8186_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld new file mode 100644 index 0000000000..942c919f45 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr) +#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr) +#define DRAM_INIT_CODE(addr, size) \ + REGION(dram_init_code, addr, size, 64K) + +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + +SECTIONS +{ + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + TTB(0x00103000, 28K) + DMA_COHERENT(0x0010A000, 4K) + TPM_TCPA_LOG(0x0010B000, 2K) + FMAP_CACHE(0x0010B800, 2K) + WATCHDOG_TOMBSTONE(0x0010C000, 4) + CBFS_MCACHE(0x0010C004, 8K - 4) + STACK(0x0010E000, 7K) + TIMESTAMP(0x0010FC00, 1K) + /* MT8186 has 64KB SRAM. */ + SRAM_END(0x00110000) + + /* + * The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM + * has configured only half of L2/L3 cache as SRAM and the rest for cache + * so we can't use them unless if we disable L2C and reconfigure (be aware + * we can't configure whole L3 to SRAM without any cache). + */ + SRAM_L2C_START(0x00200000) + /* 4K reserved for BOOTROM until BOOTBLOCK is started */ + BOOTBLOCK(0x00201000, 60K) + /* + * The needed size can be obtained by: + * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz + */ + DRAM_INIT_CODE(0x00210000, 196K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00241000, 140K) + PRERAM_CBFS_CACHE(0x00264000, 48K) + PRERAM_CBMEM_CONSOLE(0x00270000, 64K) + SRAM_L2C_END(0x00280000) + + DRAM_START(0x40000000) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 256K) + + BL31(0x54600000, 0x60000) +} diff --git a/src/soc/mediatek/mt8186/include/soc/mt6366.h b/src/soc/mediatek/mt8186/include/soc/mt6366.h new file mode 100644 index 0000000000..2315a24a76 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/mt6366.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef __SOC_MEDIATEK_MT6366_H__ +#define __SOC_MEDIATEK_MT6366_H__ + +#include + +enum { + PMIC_SWCID = 0x000a, + PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, + PMIC_TOP_RST_MISC = 0x014c, + PMIC_TOP_RST_MISC_SET = 0x014e, + PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, + PMIC_TOP_TMA_KEY = 0x03a8, + PMIC_PWRHOLD = 0x0a08, + PMIC_CPSDSA4 = 0x0a2e, + PMIC_VPROC12_OP_EN = 0x1410, + PMIC_VPROC12_DBG0 = 0x141e, + PMIC_VPROC12_VOSEL = 0x1426, + PMIC_VCORE_OP_EN = 0x1490, + PMIC_VCORE_DBG0 = 0x149e, + PMIC_VCORE_VOSEL = 0x14aa, + PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, + PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDDQ_OP_EN = 0x1b16, + PMIC_VSRAM_PROC12_OP_EN = 0x1b90, + PMIC_VSRAM_PROC12_DBG0 = 0x1ba2, + PMIC_VSRAM_PROC12_VOSEL = 0x1bf0, + PMIC_LDO_VRF12_CON0 = 0x1c30, + PMIC_LDO_VRF12_OP_EN = 0x1c32, + PMIC_LDO_VMC_CON0 = 0x1cc4, + PMIC_LDO_VMC_OP_EN = 0x1cc6, + PMIC_LDO_VMCH_CON0 = 0x1cd8, + PMIC_LDO_VMCH_OP_EN = 0x1cda, + PMIC_LDO_VCN33_CON0_0 = 0x1d1c, + PMIC_VCN33_ANA_CON0 = 0x1e28, + PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VMCH_ANA_CON0 = 0x1e48, + PMIC_VMC_ANA_CON0 = 0x1e4c, + PMIC_VDDQ_ELR_0 = 0x1ec4, +}; + +enum mt6366_regulator_id { + MT6366_VCORE = 0, + MT6366_VDRAM1, + MT6366_VDDQ, + MT6366_VMCH, + MT6366_VMC, + MT6366_VPROC12, + MT6366_VSRAM_PROC12, + MT6366_VRF12, + MT6366_VCN33, + MT6366_REGULATOR_NUM, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +void mt6366_init(void); +void mt6366_set_power_hold(bool enable); +void mt6366_set_vsim2_cali_mv(u32 vsim2_mv); +void mt6366_init_scp_voltage(void); +void mt6366_set_voltage(enum mt6366_regulator_id id, u32 vcore_uv); +u32 mt6366_get_voltage(enum mt6366_regulator_id id); + +#endif /* __SOC_MEDIATEK_MT6366_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h new file mode 100644 index 0000000000..c2dace3220 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -0,0 +1,525 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.2 + */ + +#ifndef SOC_MEDIATEK_MT8186_PLL_H +#define SOC_MEDIATEK_MT8186_PLL_H + +#include +#include +#include + +struct mtk_topckgen_regs { + u32 clk_mode; + u32 clk_cfg_update; + u32 clk_cfg_update1; + u32 reserved1[13]; + u32 clk_cfg_0; + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved2[1]; + u32 clk_cfg_1; + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved3[1]; + u32 clk_cfg_2; + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved4[1]; + u32 clk_cfg_3; + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved5[1]; + u32 clk_cfg_4; + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved6[1]; + u32 clk_cfg_5; + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved7[1]; + u32 clk_cfg_6; + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved8[1]; + u32 clk_cfg_7; + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved9[1]; + u32 clk_cfg_8; + u32 clk_cfg_8_set; + u32 clk_cfg_8_clr; + u32 reserved10[1]; + u32 clk_cfg_9; + u32 clk_cfg_9_set; + u32 clk_cfg_9_clr; + u32 reserved11[1]; + u32 clk_cfg_10; + u32 clk_cfg_10_set; + u32 clk_cfg_10_clr; + u32 clk_cfg_11; + u32 clk_cfg_11_set; + u32 clk_cfg_11_clr; + u32 reserved12[2]; + u32 clk_cfg_12; + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved13[1]; + u32 clk_cfg_13; + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved14[1]; + u32 clk_cfg_14; + u32 clk_cfg_14_set; + u32 clk_cfg_14_clr; + u32 reserved15[1]; + u32 clk_cfg_20; + u32 clk_cfg_20_set; + u32 clk_cfg_20_clr; + u32 reserved16[1]; + u32 clk_misc_cfg_0; + u32 reserved17[3]; + u32 clk_misc_cfg_1; + u32 reserved18[10]; + u32 clk_dbg_cfg; + u32 clk_cfg_15; + u32 clk_cfg_15_set; + u32 clk_cfg_15_clr; + u32 reserved19[29]; + u32 clk_scp_cfg_0; + u32 reserved20[3]; + u32 clk_scp_cfg_1; + u32 reserved21[3]; + u32 clk26cali_0; + u32 clk26cali_1; + u32 reserved22[2]; + u32 cksta_reg; + u32 cksta_reg1; + u32 reserved23[50]; + u32 clkmon_clk_sel_reg; + u32 clkmon_k1_reg; + u32 reserved24[6]; + u32 clk_auddiv_0; + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 aud_top_cfg; + u32 aud_top_mon; + u32 clk_auddiv_3; + u32 reserved25[1]; + u32 usb_top_cfg; + u32 reserved26[112]; + u32 clk_extck_reg; +}; + +check_member(mtk_topckgen_regs, clk_mode, 0x0); +check_member(mtk_topckgen_regs, clk_cfg_update, 0x4); +check_member(mtk_topckgen_regs, clk_cfg_update1, 0x8); +check_member(mtk_topckgen_regs, clk_cfg_0, 0x40); +check_member(mtk_topckgen_regs, clk_cfg_0_set, 0x44); +check_member(mtk_topckgen_regs, clk_cfg_0_clr, 0x48); +check_member(mtk_topckgen_regs, clk_cfg_1, 0x50); +check_member(mtk_topckgen_regs, clk_cfg_1_set, 0x54); +check_member(mtk_topckgen_regs, clk_cfg_1_clr, 0x58); +check_member(mtk_topckgen_regs, clk_cfg_2, 0x60); +check_member(mtk_topckgen_regs, clk_cfg_2_set, 0x64); +check_member(mtk_topckgen_regs, clk_cfg_2_clr, 0x68); +check_member(mtk_topckgen_regs, clk_cfg_3, 0x70); +check_member(mtk_topckgen_regs, clk_cfg_3_set, 0x74); +check_member(mtk_topckgen_regs, clk_cfg_3_clr, 0x78); +check_member(mtk_topckgen_regs, clk_cfg_4, 0x80); +check_member(mtk_topckgen_regs, clk_cfg_4_set, 0x84); +check_member(mtk_topckgen_regs, clk_cfg_4_clr, 0x88); +check_member(mtk_topckgen_regs, clk_cfg_5, 0x90); +check_member(mtk_topckgen_regs, clk_cfg_5_set, 0x94); +check_member(mtk_topckgen_regs, clk_cfg_5_clr, 0x98); +check_member(mtk_topckgen_regs, clk_cfg_6, 0xa0); +check_member(mtk_topckgen_regs, clk_cfg_6_set, 0xa4); +check_member(mtk_topckgen_regs, clk_cfg_6_clr, 0xa8); +check_member(mtk_topckgen_regs, clk_cfg_7, 0xb0); +check_member(mtk_topckgen_regs, clk_cfg_7_set, 0xb4); +check_member(mtk_topckgen_regs, clk_cfg_7_clr, 0xb8); +check_member(mtk_topckgen_regs, clk_cfg_8, 0xc0); +check_member(mtk_topckgen_regs, clk_cfg_8_set, 0xc4); +check_member(mtk_topckgen_regs, clk_cfg_8_clr, 0xc8); +check_member(mtk_topckgen_regs, clk_cfg_9, 0xd0); +check_member(mtk_topckgen_regs, clk_cfg_9_set, 0xd4); +check_member(mtk_topckgen_regs, clk_cfg_9_clr, 0xd8); +check_member(mtk_topckgen_regs, clk_cfg_10, 0xe0); +check_member(mtk_topckgen_regs, clk_cfg_10_set, 0xe4); +check_member(mtk_topckgen_regs, clk_cfg_10_clr, 0xe8); +check_member(mtk_topckgen_regs, clk_cfg_11, 0xec); +check_member(mtk_topckgen_regs, clk_cfg_11_set, 0xf0); +check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0xf4); +check_member(mtk_topckgen_regs, clk_cfg_12, 0x100); +check_member(mtk_topckgen_regs, clk_cfg_12_set, 0x104); +check_member(mtk_topckgen_regs, clk_cfg_12_clr, 0x108); +check_member(mtk_topckgen_regs, clk_cfg_13, 0x110); +check_member(mtk_topckgen_regs, clk_cfg_13_set, 0x114); +check_member(mtk_topckgen_regs, clk_cfg_13_clr, 0x118); +check_member(mtk_topckgen_regs, clk_cfg_14, 0x120); +check_member(mtk_topckgen_regs, clk_cfg_14_set, 0x124); +check_member(mtk_topckgen_regs, clk_cfg_14_clr, 0x128); +check_member(mtk_topckgen_regs, clk_cfg_20, 0x130); +check_member(mtk_topckgen_regs, clk_cfg_20_set, 0x134); +check_member(mtk_topckgen_regs, clk_cfg_20_clr, 0x138); +check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x140); +check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x150); +check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x17c); +check_member(mtk_topckgen_regs, clk_cfg_15, 0x180); +check_member(mtk_topckgen_regs, clk_cfg_15_set, 0x184); +check_member(mtk_topckgen_regs, clk_cfg_15_clr, 0x188); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200); +check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x210); +check_member(mtk_topckgen_regs, clk26cali_0, 0x220); +check_member(mtk_topckgen_regs, clk26cali_1, 0x224); +check_member(mtk_topckgen_regs, cksta_reg, 0x230); +check_member(mtk_topckgen_regs, cksta_reg1, 0x234); +check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x300); +check_member(mtk_topckgen_regs, clkmon_k1_reg, 0x304); +check_member(mtk_topckgen_regs, clk_auddiv_0, 0x320); +check_member(mtk_topckgen_regs, clk_auddiv_1, 0x324); +check_member(mtk_topckgen_regs, clk_auddiv_2, 0x328); +check_member(mtk_topckgen_regs, aud_top_cfg, 0x32c); +check_member(mtk_topckgen_regs, aud_top_mon, 0x330); +check_member(mtk_topckgen_regs, clk_auddiv_3, 0x334); +check_member(mtk_topckgen_regs, usb_top_cfg, 0x33c); +check_member(mtk_topckgen_regs, clk_extck_reg, 0x500); + +struct mtk_apmixed_regs { + u32 ap_pll_con0; + u32 ap_pll_con1; + u32 ap_pll_con2; + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; + u32 apll1_tuner_con0; + u32 apll2_tuner_con0; + u32 reserved1[2]; + u32 pllon_con0; + u32 pllon_con1; + u32 reserved2[106]; + u32 ap_pllgp1_con0; + u32 armpll_ll_con0; + u32 armpll_ll_con1; + u32 armpll_ll_con2; + u32 armpll_ll_con3; + u32 armpll_bl_con0; + u32 armpll_bl_con1; + u32 armpll_bl_con2; + u32 armpll_bl_con3; + u32 ccipll_con0; + u32 ccipll_con1; + u32 ccipll_con2; + u32 ccipll_con3; + u32 apupll_con0; + u32 apupll_con1; + u32 apupll_con2; + u32 apupll_con3; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_con3; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_con3; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_con3; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_con3; + u32 reserved3[31]; + u32 ap_pllgp2_con0; + u32 adsppll_con0; + u32 adsppll_con1; + u32 adsppll_con2; + u32 adsppll_con3; + u32 mfgpll_con0; + u32 mfgpll_con1; + u32 mfgpll_con2; + u32 mfgpll_con3; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_con3; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_con4; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_con4; + u32 nnapll_con0; + u32 nnapll_con1; + u32 nnapll_con2; + u32 nnapll_con3; + u32 nna2pll_con0; + u32 nna2pll_con1; + u32 nna2pll_con2; + u32 nna2pll_con3; + u32 mdbrppll_con0; + u32 mdbrppll_con1; + u32 mdbrppll_con2; + u32 mdbrppll_con3; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_con3; + u32 mdbpipll_con0; + u32 mdbpipll_con1; + u32 mdbpipll_con2; + u32 mdbpipll_con3; + u32 reserved4[21]; + u32 ap_auxadc_con0; + u32 ap_auxadc_con1; + u32 reserved5[30]; + u32 ap_tsense_con0; + u32 ap_tsense_con1; + u32 ap_tsense_con2; + u32 reserved6[29]; + u32 ulposc_con0; + u32 ulposc_con1; + u32 reserved7[30]; + u32 ulposc2_con0; + u32 ulposc2_con1; + u32 reserved8[158]; + u32 ap_abist_mon_con0; + u32 ap_abist_mon_con1; + u32 ap_abist_mon_con2; + u32 ap_abist_mon_con3; + u32 occscan_con0; + u32 clkdiv_con0; + u32 occscan_con1; + u32 occscan_con2; + u32 occscan_con3; + u32 mcu_occscan_con0; + u32 occscan_con4; + u32 occscan_con5; + u32 reserved9[52]; + u32 rsv_rw0_con0; + u32 rsv_rw1_con0; + u32 rsv_ro_con0; +}; +check_member(mtk_apmixed_regs, ap_pll_con0, 0x0); +check_member(mtk_apmixed_regs, ap_pll_con1, 0x4); +check_member(mtk_apmixed_regs, ap_pll_con2, 0x8); +check_member(mtk_apmixed_regs, ap_pll_con3, 0xc); +check_member(mtk_apmixed_regs, ap_pll_con4, 0x10); +check_member(mtk_apmixed_regs, ap_pll_con5, 0x14); +check_member(mtk_apmixed_regs, clksq_stb_con0, 0x18); +check_member(mtk_apmixed_regs, pll_pwr_con0, 0x1c); +check_member(mtk_apmixed_regs, pll_pwr_con1, 0x20); +check_member(mtk_apmixed_regs, pll_iso_con0, 0x24); +check_member(mtk_apmixed_regs, pll_iso_con1, 0x28); +check_member(mtk_apmixed_regs, pll_stb_con0, 0x2c); +check_member(mtk_apmixed_regs, div_stb_con0, 0x30); +check_member(mtk_apmixed_regs, pll_chg_con0, 0x34); +check_member(mtk_apmixed_regs, pll_test_con0, 0x38); +check_member(mtk_apmixed_regs, pll_test_con1, 0x3c); +check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x40); +check_member(mtk_apmixed_regs, apll2_tuner_con0, 0x44); +check_member(mtk_apmixed_regs, pllon_con0, 0x50); +check_member(mtk_apmixed_regs, pllon_con1, 0x54); +check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x200); +check_member(mtk_apmixed_regs, armpll_ll_con0, 0x204); +check_member(mtk_apmixed_regs, armpll_ll_con1, 0x208); +check_member(mtk_apmixed_regs, armpll_ll_con2, 0x20c); +check_member(mtk_apmixed_regs, armpll_ll_con3, 0x210); +check_member(mtk_apmixed_regs, armpll_bl_con0, 0x214); +check_member(mtk_apmixed_regs, armpll_bl_con1, 0x218); +check_member(mtk_apmixed_regs, armpll_bl_con2, 0x21c); +check_member(mtk_apmixed_regs, armpll_bl_con3, 0x220); +check_member(mtk_apmixed_regs, ccipll_con0, 0x224); +check_member(mtk_apmixed_regs, ccipll_con1, 0x228); +check_member(mtk_apmixed_regs, ccipll_con2, 0x22c); +check_member(mtk_apmixed_regs, ccipll_con3, 0x230); +check_member(mtk_apmixed_regs, apupll_con0, 0x234); +check_member(mtk_apmixed_regs, apupll_con1, 0x238); +check_member(mtk_apmixed_regs, apupll_con2, 0x23c); +check_member(mtk_apmixed_regs, apupll_con3, 0x240); +check_member(mtk_apmixed_regs, mainpll_con0, 0x244); +check_member(mtk_apmixed_regs, mainpll_con1, 0x248); +check_member(mtk_apmixed_regs, mainpll_con2, 0x24c); +check_member(mtk_apmixed_regs, mainpll_con3, 0x250); +check_member(mtk_apmixed_regs, mmpll_con0, 0x254); +check_member(mtk_apmixed_regs, mmpll_con1, 0x258); +check_member(mtk_apmixed_regs, mmpll_con2, 0x25c); +check_member(mtk_apmixed_regs, mmpll_con3, 0x260); +check_member(mtk_apmixed_regs, tvdpll_con0, 0x264); +check_member(mtk_apmixed_regs, tvdpll_con1, 0x268); +check_member(mtk_apmixed_regs, tvdpll_con2, 0x26c); +check_member(mtk_apmixed_regs, tvdpll_con3, 0x270); +check_member(mtk_apmixed_regs, mpll_con0, 0x274); +check_member(mtk_apmixed_regs, mpll_con1, 0x278); +check_member(mtk_apmixed_regs, mpll_con2, 0x27c); +check_member(mtk_apmixed_regs, mpll_con3, 0x280); +check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x300); +check_member(mtk_apmixed_regs, adsppll_con0, 0x304); +check_member(mtk_apmixed_regs, adsppll_con1, 0x308); +check_member(mtk_apmixed_regs, adsppll_con2, 0x30c); +check_member(mtk_apmixed_regs, adsppll_con3, 0x310); +check_member(mtk_apmixed_regs, mfgpll_con0, 0x314); +check_member(mtk_apmixed_regs, mfgpll_con1, 0x318); +check_member(mtk_apmixed_regs, mfgpll_con2, 0x31c); +check_member(mtk_apmixed_regs, mfgpll_con3, 0x320); +check_member(mtk_apmixed_regs, univpll_con0, 0x324); +check_member(mtk_apmixed_regs, univpll_con1, 0x328); +check_member(mtk_apmixed_regs, univpll_con2, 0x32c); +check_member(mtk_apmixed_regs, univpll_con3, 0x330); +check_member(mtk_apmixed_regs, apll1_con0, 0x334); +check_member(mtk_apmixed_regs, apll1_con1, 0x338); +check_member(mtk_apmixed_regs, apll1_con2, 0x33c); +check_member(mtk_apmixed_regs, apll1_con3, 0x340); +check_member(mtk_apmixed_regs, apll1_con4, 0x344); +check_member(mtk_apmixed_regs, apll2_con0, 0x348); +check_member(mtk_apmixed_regs, apll2_con1, 0x34c); +check_member(mtk_apmixed_regs, apll2_con2, 0x350); +check_member(mtk_apmixed_regs, apll2_con3, 0x354); +check_member(mtk_apmixed_regs, apll2_con4, 0x358); +check_member(mtk_apmixed_regs, nnapll_con0, 0x35c); +check_member(mtk_apmixed_regs, nnapll_con1, 0x360); +check_member(mtk_apmixed_regs, nnapll_con2, 0x364); +check_member(mtk_apmixed_regs, nnapll_con3, 0x368); +check_member(mtk_apmixed_regs, nna2pll_con0, 0x36c); +check_member(mtk_apmixed_regs, nna2pll_con1, 0x370); +check_member(mtk_apmixed_regs, nna2pll_con2, 0x374); +check_member(mtk_apmixed_regs, nna2pll_con3, 0x378); +check_member(mtk_apmixed_regs, mdbrppll_con0, 0x37c); +check_member(mtk_apmixed_regs, mdbrppll_con1, 0x380); +check_member(mtk_apmixed_regs, mdbrppll_con2, 0x384); +check_member(mtk_apmixed_regs, mdbrppll_con3, 0x388); +check_member(mtk_apmixed_regs, msdcpll_con0, 0x38c); +check_member(mtk_apmixed_regs, msdcpll_con1, 0x390); +check_member(mtk_apmixed_regs, msdcpll_con2, 0x394); +check_member(mtk_apmixed_regs, msdcpll_con3, 0x398); +check_member(mtk_apmixed_regs, mdbpipll_con0, 0x39c); +check_member(mtk_apmixed_regs, mdbpipll_con1, 0x3a0); +check_member(mtk_apmixed_regs, mdbpipll_con2, 0x3a4); +check_member(mtk_apmixed_regs, mdbpipll_con3, 0x3a8); +check_member(mtk_apmixed_regs, ap_auxadc_con0, 0x400); +check_member(mtk_apmixed_regs, ap_auxadc_con1, 0x404); +check_member(mtk_apmixed_regs, ap_tsense_con0, 0x480); +check_member(mtk_apmixed_regs, ap_tsense_con1, 0x484); +check_member(mtk_apmixed_regs, ap_tsense_con2, 0x488); +check_member(mtk_apmixed_regs, ulposc_con0, 0x500); +check_member(mtk_apmixed_regs, ulposc_con1, 0x504); +check_member(mtk_apmixed_regs, ulposc2_con0, 0x580); +check_member(mtk_apmixed_regs, ulposc2_con1, 0x584); +check_member(mtk_apmixed_regs, ap_abist_mon_con0, 0x800); +check_member(mtk_apmixed_regs, ap_abist_mon_con1, 0x804); +check_member(mtk_apmixed_regs, ap_abist_mon_con2, 0x808); +check_member(mtk_apmixed_regs, ap_abist_mon_con3, 0x80c); +check_member(mtk_apmixed_regs, occscan_con0, 0x810); +check_member(mtk_apmixed_regs, clkdiv_con0, 0x814); +check_member(mtk_apmixed_regs, occscan_con1, 0x818); +check_member(mtk_apmixed_regs, occscan_con2, 0x81c); +check_member(mtk_apmixed_regs, occscan_con3, 0x820); +check_member(mtk_apmixed_regs, mcu_occscan_con0, 0x824); +check_member(mtk_apmixed_regs, occscan_con4, 0x828); +check_member(mtk_apmixed_regs, occscan_con5, 0x82c); +check_member(mtk_apmixed_regs, rsv_rw0_con0, 0x900); +check_member(mtk_apmixed_regs, rsv_rw1_con0, 0x904); +check_member(mtk_apmixed_regs, rsv_ro_con0, 0x908); + +enum { + PLL_CKSQ_ON_DELAY = 100, + PLL_PWR_ON_DELAY = 30, + PLL_ISO_DELAY = 1, + PLL_EN_DELAY = 20, +}; + +enum { + PCW_INTEGER_BITS = 8, +}; + +enum { + MT8186_PLL_EN = 0x1 << 0, + GLITCH_FREE_EN = 0x1 << 4, + PLL_DIV_EN = 0xff << 24, +}; + +enum { + ARMPLL_DIVIDER_PLL1_EN = 0x1 << 4, + ARMPLL_DIVIDER_PLL2_EN = 0x1 << 5, +}; + +enum { + MCU_DIV_MASK = 0x1f << 17, + MCU_DIV_1 = 0x8 << 17, + + MCU_MUX_MASK = 0x3 << 9, + MCU_MUX_SRC_PLL = 0x1 << 9, + MCU_MUX_SRC_26M = 0x0 << 9, +}; + +/* PLL rate */ +enum { + ARMPLL_LL_HZ = 1280 * MHz, + ARMPLL_BL_HZ = 1085 * MHz, + CCIPLL_HZ = 800 * MHz, + MAINPLL_HZ = 1092 * MHz, + UNIV2PLL_HZ = 2496UL * MHz, + MSDCPLL_HZ = 384 * MHz, + MMPLL_HZ = 560 * MHz, + NNAPLL_HZ = 800 * MHz, + NNA2PLL_HZ = 800 * MHz, + ADSPPLL_HZ = 800 * MHz, + MFGPLL_HZ = 250 * MHz, + TVDPLL_HZ = 297 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, +}; + +/* top_div rate */ +enum { + CLK26M_HZ = 26 * MHz, + MAINPLL_D5_HZ = MAINPLL_HZ / 5, +}; + +/* top_mux rate */ +enum { + SPI_HZ = MAINPLL_D5_HZ, + UART_HZ = CLK26M_HZ, +}; + +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) + +DEFINE_BIT(INFRACFG_AO_AUDIO_BUS_REG0, 29) +DEFINE_BIT(INFRACFG_AO_ICUSB_BUS_REG0, 28) + +DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_0, 14, 0) +DEFINE_BITFIELD(INFRACFG_AO_INFRA_BUS_REG0_1, 23, 20) +DEFINE_BIT(INFRACFG_AO_INFRA_BUS_REG0_2, 30) + +DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0) +DEFINE_BIT(INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 5) + +DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_0, 1, 0) +DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_1, 27, 3) +DEFINE_BIT(INFRACFG_AO_PERI_BUS_REG0_2, 31) + +#endif /* SOC_MEDIATEK_MT8186_PLL_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h new file mode 100644 index 0000000000..ccee79cf64 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h @@ -0,0 +1,440 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#ifndef __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ + +#include +#include +#include + +struct mt8186_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 si_sample_ctrl; + u32 si_sample_ctrl_1; + u32 si_sample_ctrl_2; + u32 si_sample_ctrl_3; + u32 si_sample_ctrl_ulposc; + u32 rddmy; + u32 cshext_write; + u32 cshext_read; + u32 cslext_write; + u32 cslext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 staupd_ctrl; + u32 staupd_grpen; + u32 eint_sta0_adr; + u32 eint_sta1_adr; + u32 eint_sta; + u32 eint_clr; + u32 eint_ctrl; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hiprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 harb_sta2; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs1_en; + u32 init_done1; + u32 wacs2_en; + u32 init_done2; + u32 wacs3_en; + u32 init_done3; + u32 wacs_p2p_en; + u32 init_done_p2p; + u32 wacs_md32_en; + u32 init_done_md32; + u32 int0_en; + u32 int0_flg_raw; + u32 int0_flg; + u32 int0_clr; + u32 int1_en; + u32 int1_flg_raw; + u32 int1_flg; + u32 int1_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_ctrl; + u32 timer_sta; + u32 wdt_ctrl; + u32 wdt_src_en_0; + u32 wdt_src_en_1; + u32 wdt_flg_0; + u32 wdt_flg_1; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 dvfs_adr8; + u32 dvfs_wdata8; + u32 dvfs_adr9; + u32 dvfs_wdata9; + u32 dvfs_adr10; + u32 dvfs_wdata10; + u32 dvfs_adr11; + u32 dvfs_wdata11; + u32 dvfs_adr12; + u32 dvfs_wdata12; + u32 dvfs_adr13; + u32 dvfs_wdata13; + u32 dvfs_adr14; + u32 dvfs_wdata14; + u32 dvfs_adr15; + u32 dvfs_wdata15; + u32 dcxo_enable; + u32 dcxo_conn_adr0; + u32 dcxo_conn_wdata0; + u32 dcxo_conn_adr1; + u32 dcxo_conn_wdata1; + u32 dcxo_nfc_adr0; + u32 dcxo_nfc_wdata0; + u32 dcxo_nfc_adr1; + u32 dcxo_nfc_wdata1; + u32 spminf_sta_0; + u32 spminf_sta_1; + u32 spminf_backup_sta; + u32 scpinf_sta; + u32 srclken_rcinf_sta_0; + u32 srclken_rcinf_sta_1; + u32 mcu_pminf_sta_0; + u32 mcu_pminf_sta_1; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_dbc_prd; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 ext_gps_auxadc_rdata_addr; + u32 gpsinf_0_sta; + u32 gpsinf_1_sta; + u32 md_adcinf_ctrl; + u32 md_auxadc_rdata_latest_addr; + u32 md_auxadc_rdata_wp_addr; + u32 md_auxadc_rdata[32]; + u32 md_adcinf_0_sta_0; + u32 md_adcinf_0_sta_1; + u32 md_adcinf_1_sta_0; + u32 md_adcinf_1_sta_1; + u32 swrst; + u32 sleep_protection_ctrl; + u32 spm_sleep_gating_ctrl; + u32 scp_sleep_gating_ctrl; + u32 busy_sta; + u32 busy_sta_latched_wdt; + u32 priority_user_sel_0; + u32 priority_user_sel_1; + u32 priority_user_sel_2; + u32 priority_user_sel_3; + u32 priority_user_sel_4; + u32 arbiter_out_sel_0; + u32 arbiter_out_sel_1; + u32 arbiter_out_sel_2; + u32 arbiter_out_sel_3; + u32 arbiter_out_sel_4; + u32 starv_counter_0; + u32 starv_counter_1; + u32 starv_counter_2; + u32 starv_counter_3; + u32 starv_counter_4; + u32 starv_counter_5; + u32 starv_counter_6; + u32 starv_counter_7; + u32 starv_counter_8; + u32 starv_counter_9; + u32 starv_counter_10; + u32 starv_counter_11; + u32 starv_counter_12; + u32 starv_counter_13; + u32 starv_counter_14; + u32 starv_counter_15; + u32 starv_counter_16; + u32 starv_int_en; + u32 starv_counter_0_status; + u32 starv_counter_1_status; + u32 starv_counter_2_status; + u32 starv_counter_3_status; + u32 starv_counter_4_status; + u32 starv_counter_5_status; + u32 starv_counter_6_status; + u32 starv_counter_7_status; + u32 starv_counter_8_status; + u32 starv_counter_9_status; + u32 starv_counter_10_status; + u32 starv_counter_11_status; + u32 starv_counter_12_status; + u32 starv_counter_13_status; + u32 starv_counter_14_status; + u32 starv_counter_15_status; + u32 starv_counter_16_status; + u32 starv_counter_clr; + u32 starv_prio_status; + u32 monitor_ctrl; + u32 monitor_target_channel_0; + u32 monitor_target_channel_1; + u32 monitor_target_channel_2; + u32 monitor_target_channel_3; + u32 monitor_target_channel_4; + u32 monitor_target_channel_5; + u32 monitor_target_channel_6; + u32 monitor_target_channel_7; + u32 monitor_target_write; + u32 monitor_target_adr_0; + u32 monitor_target_adr_1; + u32 monitor_target_adr_2; + u32 monitor_target_adr_3; + u32 monitor_target_adr_4; + u32 monitor_target_adr_5; + u32 monitor_target_adr_6; + u32 monitor_target_adr_7; + u32 monitor_target_wdata_0; + u32 monitor_target_wdata_1; + u32 monitor_target_wdata_2; + u32 monitor_target_wdata_3; + u32 monitor_target_wdata_4; + u32 monitor_target_wdata_5; + u32 monitor_target_wdata_6; + u32 monitor_target_wdata_7; + u32 channel_sequence_0; + u32 channel_sequence_1; + u32 channel_sequence_2; + u32 channel_sequence_3; + u32 channel_sequence_4; + u32 channel_sequence_5; + u32 channel_sequence_6; + u32 channel_sequence_7; + u32 write_sequence; + u32 adr_sequence_0; + u32 adr_sequence_1; + u32 adr_sequence_2; + u32 adr_sequence_3; + u32 adr_sequence_4; + u32 adr_sequence_5; + u32 adr_sequence_6; + u32 adr_sequence_7; + u32 adr_sequence_8; + u32 adr_sequence_9; + u32 adr_sequence_10; + u32 adr_sequence_11; + u32 adr_sequence_12; + u32 adr_sequence_13; + u32 adr_sequence_14; + u32 adr_sequence_15; + u32 wdata_sequence_0; + u32 wdata_sequence_1; + u32 wdata_sequence_2; + u32 wdata_sequence_3; + u32 wdata_sequence_4; + u32 wdata_sequence_5; + u32 wdata_sequence_6; + u32 wdata_sequence_7; + u32 wdata_sequence_8; + u32 wdata_sequence_9; + u32 wdata_sequence_10; + u32 wdata_sequence_11; + u32 wdata_sequence_12; + u32 wdata_sequence_13; + u32 wdata_sequence_14; + u32 wdata_sequence_15; + u32 bwc_options; + u32 reserved1[477]; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 reserved2; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 reserved3; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 reserved4; + u32 wacs3_cmd; + u32 wacs3_rdata; + u32 wacs3_vldclr; +}; + +check_member(mt8186_pwrap_regs, bwc_options, 0x488); +check_member(mt8186_pwrap_regs, wacs3_vldclr, 0xC38); + +static struct mt8186_pwrap_regs * const mtk_pwrap = (void *)PWRAP_BASE; + +enum { + WACS2 = 1 << 2 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0030, + PMIC_DRV_CON1 = PMIC_BASE + 0x0038, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0040, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_RG_SPI_RECORD0 = PMIC_BASE + 0x040A, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040C, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040E, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0426, + PMIC_CPU_INT_STA = PMIC_BASE + 0x042E, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0432, + PMIC_RG_SPI_CON3 = PMIC_BASE + 0x0434, + PMIC_RG_SPI_CON4 = PMIC_BASE + 0x0436, + PMIC_RG_SPI_CON5 = PMIC_BASE + 0x0438, + PMIC_RG_SPI_CON6 = PMIC_BASE + 0x043A, + PMIC_RG_SPI_CON7 = PMIC_BASE + 0x043C, + PMIC_RG_SPI_CON8 = PMIC_BASE + 0x043E, + PMIC_RG_SPI_CON13 = PMIC_BASE + 0x0448, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044A, + PMIC_PPCCTL0 = PMIC_BASE + 0x0A08, + PMIC_AUXADC_ADC17 = PMIC_BASE + 0x10AA, + PMIC_AUXADC_ADC31 = PMIC_BASE + 0x10C6, + PMIC_AUXADC_ADC32 = PMIC_BASE + 0x10C8, + PMIC_AUXADC_ADC35 = PMIC_BASE + 0x10CE, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, + PMIC_AUXADC_RQST1 = PMIC_BASE + 0x110A, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING, +}; + +enum { + GPS_MAIN = 0x40, + GPS_SUBSYS = 0x80, +}; + +enum { + SIG_PMIC_0 = 0x1 << 0, + INT_STA_PMIC_0 = 0x1 << 2, + MD_ADC_DATA0 = 0x1 << 4, + MD_ADC_DATA1 = 0x1 << 5, + GPS_ADC_DATA0 = 0x1 << 6, + GPS_ADC_DATA1 = 0x1 << 7, +}; + +enum { + MD = 1, + MD_DVFS = 2, + POWER_HW = 4, + POWER_HW_BACKUP = 8, + ARB_PRIORITY = MD | MD_DVFS | POWER_HW | POWER_HW_BACKUP, +}; + +enum { + ARB_WACS0 = BIT(0), + ARB_WACS1 = BIT(1), + ARB_WACS2 = BIT(2), + ARB_WACS3 = BIT(3), + ARB_WACS_P2P = BIT(4), + ARB_WACS_MD32 = BIT(5), + ARB_MDINF = BIT(6), + ARB_C2KINF = BIT(7), + ARB_MD_DVFSINF = BIT(8), + ARB_SPMINF = BIT(9), + ARB_SPMINF_BACKUP = BIT(10), + ARB_SRCLKEN_RCINF = BIT(11), + ARB_DCXO_CONNINF = BIT(12), + ARB_DCXO_NFCINF = BIT(13), + ARB_MCU_PMINF = BIT(14), + ARB_MD_ADCINF_0 = BIT(15), + ARB_MD_ADCINF_1 = BIT(16), + ARB_GPSINF_0 = BIT(17), + ARB_GPSINF_1 = BIT(18), + ARB_STAUPD = BIT(19), + ARB_USER_EN = ARB_WACS0 | ARB_WACS1 | ARB_WACS2 | ARB_WACS3 | + ARB_WACS_P2P | ARB_WACS_MD32 | ARB_MDINF | + ARB_MD_DVFSINF | ARB_SPMINF | + ARB_DCXO_CONNINF | ARB_DCXO_NFCINF | ARB_MD_ADCINF_0 | + ARB_MD_ADCINF_1 | ARB_GPSINF_0 | ARB_GPSINF_1 | ARB_STAUPD, +}; + +enum { + STA_PD_98_5_US = 0x5, +}; + +enum { + WATCHDOG_TIMER_7_5_MS = 0xF, +}; + +enum { + WDT_MONITOR_ALL = 0xFFFF, +}; + +enum { + MONITOR_LATCH_MATCHED_TRANS = 0x1 << 28, + STARV_15 = 0x1 << 24, + DCXO = 0x1 << 19, + MONITOR_ALL_INT = 0xFFFFFFFF, + INT0_MONITOR = MONITOR_ALL_INT, + INT1_MONITOR = MONITOR_ALL_INT & + ~MONITOR_LATCH_MATCHED_TRANS & ~STARV_15 & ~DCXO, +}; + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO), + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = (IO_4_MA << SPI_CLK_SHIFT | IO_4_MA << SPI_CSN_SHIFT | + IO_4_MA << SPI_MOSI_SHIFT | IO_4_MA << SPI_MISO_SHIFT), +}; + +enum { + DUMMY_READ_CYCLES = 0x8, +}; +#endif /* __SOC_MEDIATEK_MT8186_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h new file mode 100644 index 0000000000..3a0c7cd100 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/rtc.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8186_RTC_H +#define SOC_MEDIATEK_MT8186_RTC_H + +#include +#include +#include + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E, +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E, +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590, +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2, +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2, +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0, +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_CLR = 1U << 1, + RTC_BBPU_INIT = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + + RTC_CBUSY_TIMEOUT_US = 8000, +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15, +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_REG_XOSC32_ENB = 1U << 15, +}; + +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_SCK_TOP_CON0 = 0x050C, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C, +}; + +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11, +}; + +/* PMIC DCXO Register Definition */ +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_CLR = 0x078C, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW07 = 0x079A, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW11 = 0x07A2, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW16 = 0x07B0, + PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, + PMIC_RG_DCXO_ELR0 = 0x07C4, +}; + +enum { + PMIC_RG_TOP_TMA_KEY = 0x03A8, +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013E, + PMIC_RG_FQMTR_CON0 = 0x0514, + PMIC_RG_FQMTR_WINSET = 0x0516, + PMIC_RG_FQMTR_DATA = 0x0518, + + FQMTR_TIMEOUT_US = 8000, +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0, +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8 +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15, +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2, +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f, +}; + +/* external API */ +void rtc_bbpu_power_on(void); +int rtc_init(int recover); +bool rtc_gpio_init(void); +void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); + +static inline s32 rtc_read(u16 addr, u16 *rdata) +{ + s32 ret; + + ret = pwrap_read(addr, rdata); + if (ret) + rtc_info("pwrap_read failed: ret=%d\n", ret); + + return ret; +} + +static inline s32 rtc_write(u16 addr, u16 wdata) +{ + s32 ret; + + ret = pwrap_write(addr, wdata); + if (ret) + rtc_info("pwrap_write failed: ret=%d\n", ret); + + return ret; +} + +#endif /* SOC_MEDIATEK_MT8186_RTC_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h new file mode 100644 index 0000000000..15e7b9182f --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.6 + */ + +#ifndef MTK_MT8186_SPI_H +#define MTK_MT8186_SPI_H + +#include + +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) + +enum { + SPI_NOR_GPIO_SET0 = 0, + SPI_NOR_GPIO_SET1, + SPI_NOR_GPIO_SET_NUM, +}; + +void mtk_snfc_init(int gpio_set); + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h new file mode 100644 index 0000000000..18a97445fa --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -0,0 +1,874 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_SPM_H +#define SOC_MEDIATEK_MT8186_SPM_H + +#include +#include +#include +#include + +#define SPM_INIT_DONE_US 20 + +#define CLK_SCP_CFG_0 (IO_PHYS + 0x200) +#define CLK_SCP_CFG_1 (IO_PHYS + 0x210) +#define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8) + +#define AP_PLL_CON3 (APMIXED_BASE + 0xC) +#define AP_PLL_CON4 (APMIXED_BASE + 0x10) + +/* MD32PCM ADDR for SPM code fetch */ +#define MD32PCM_BASE (SPM_BASE + 0x0A00) +#define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) +#define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) +#define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) +#define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) +#define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) +#define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) +#define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) +#define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) +#define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) +#define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) + +#define MD32PCM_CFGREG_SW_RSTN_RUN 1 +#define MD32PCM_DMA0_CON_VAL 0x0003820E +#define MD32PCM_DMA0_START_VAL 0x00008000 + +/* SPM */ +#define BCLK_CG_EN_LSB BIT(0) +#define PCM_CK_EN_LSB BIT(2) +#define PCM_SW_RESET_LSB BIT(15) +#define RG_AHBMIF_APBEN_LSB BIT(3) +#define REG_MD32_APB_INTERNAL_EN_LSB BIT(14) +#define PCM_RF_SYNC_R7 BIT(23) +#define REG_DDREN_DBC_EN_LSB BIT(16) + +DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) +DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28) +DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4) +DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8) +DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 9) +DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 10) +DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 18) +DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 15) +DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2) +DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4) +DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0) + +#define SPM_PROJECT_CODE 0xB16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) +#define POWER_ON_VAL1_DEF 0x80015860 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF +#define DDREN_DBC_EN_VAL 0x154 +#define ARMPLL_CLK_SEL_DEF 0x3FF +#define SPM_RESOURCE_ACK_CON0_DEF 0x00000000 +#define SPM_RESOURCE_ACK_CON1_DEF 0x00000000 +#define SPM_RESOURCE_ACK_CON2_DEF 0xCCCC4E4E +#define SPM_RESOURCE_ACK_CON3_DEF 0x00000000 +#define APMIX_CON3_DEF 0xFFFF7770 +#define APMIX_CON4_DEF 0xFFFAA007 +#define SCP_CFG0_DEF 0x3FF +#define SCP_CFG1_DEF 0x3 +#define SPM_DVFS_LEVEL_DEF 0x00000001 +#define SPM_DVS_DFS_LEVEL_DEF 0x00010001 +#define SPM_ACK_CHK_3_SEL_HW_S1 0x0035009F +#define SPM_ACK_CHK_3_HW_S1_CNT 1 +#define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 1 +#define RG_PCM_TIMER_EN_LSB BIT(5) +#define RG_PCM_WDT_WAKE_LSB BIT(9) +#define PCM_RF_SYNC_R0 BIT(16) +#define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(6) +#define R12_CSYSPWREQ_B BIT(24) +#define SPM_BUS_PROTECT_MASK_B_DEF 0xFFFFFFFF +#define SPM_BUS_PROTECT2_MASK_B_DEF 0xFFFFFFFF + +#define SPM_FLAG_DISABLE_VCORE_DVS BIT(3) +#define SPM_FLAG_DISABLE_VCORE_DFS BIT(4) +#define SPM_FLAG_RUN_COMMON_SCENARIO BIT(10) + +/* PCM_WDT_VAL */ +#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ +/* PCM_TIMER_VAL */ +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/* SPM_IRQ_MASK */ +#define ISRM_TWAM BIT(2) +#define ISRM_PCM_RETURN BIT(3) +#define ISRM_RET_IRQ0 BIT(8) +#define ISRM_RET_IRQ1 BIT(9) +#define ISRM_RET_IRQ2 BIT(10) +#define ISRM_RET_IRQ3 BIT(11) +#define ISRM_RET_IRQ4 BIT(12) +#define ISRM_RET_IRQ5 BIT(13) +#define ISRM_RET_IRQ6 BIT(14) +#define ISRM_RET_IRQ7 BIT(15) +#define ISRM_RET_IRQ8 BIT(16) +#define ISRM_RET_IRQ9 BIT(17) +#define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | ISRM_RET_IRQ7 | \ + ISRM_RET_IRQ6 | ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ + ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | ISRM_RET_IRQ1) +#define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM BIT(2) +#define ISRS_PCM_RETURN BIT(3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_SWINT */ +#define PCM_SW_INT0 BIT(0) +#define PCM_SW_INT1 BIT(1) +#define PCM_SW_INT2 BIT(2) +#define PCM_SW_INT3 BIT(3) +#define PCM_SW_INT4 BIT(4) +#define PCM_SW_INT5 BIT(5) +#define PCM_SW_INT6 BIT(6) +#define PCM_SW_INT7 BIT(7) +#define PCM_SW_INT8 BIT(8) +#define PCM_SW_INT9 BIT(9) +#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ + PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ + PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ + PCM_SW_INT0) + +struct mtk_spm_regs { + uint32_t poweron_config_set; + uint32_t spm_power_on_val0; + uint32_t spm_power_on_val1; + uint32_t spm_clk_con; + uint32_t spm_clk_settle; + uint32_t spm_ap_standby_con; + uint32_t pcm_con0; + uint32_t pcm_con1; + uint32_t spm_power_on_val2; + uint32_t spm_power_on_val3; + uint32_t pcm_reg_data_ini; + uint32_t pcm_pwr_io_en; + uint32_t pcm_timer_val; + uint32_t pcm_wdt_val; + uint8_t reserved0[8]; + uint32_t spm_sw_rst_con; + uint32_t spm_sw_rst_con_set; + uint32_t spm_sw_rst_con_clr; + uint32_t spm_src6_mask; + uint8_t reserved1[52]; + uint32_t md32_clk_con; + uint32_t spm_sram_rsv_con; + uint32_t spm_swint; + uint32_t spm_swint_set; + uint32_t spm_swint_clr; + uint32_t spm_scp_mailbox; + uint32_t scp_spm_mailbox; + uint32_t spm_wakeup_event_sens; + uint32_t spm_wakeup_event_clear; + uint8_t reserved2[4]; + uint32_t spm_scp_irq; + uint32_t spm_cpu_wakeup_event; + uint32_t spm_irq_mask; + uint32_t spm_src_req; + uint32_t spm_src_mask; + uint32_t spm_src2_mask; + uint32_t spm_src3_mask; + uint32_t spm_src4_mask; + uint32_t spm_src5_mask; + uint32_t spm_wakeup_event_mask; + uint32_t spm_wakeup_event_ext_mask; + uint32_t spm_src7_mask; + uint32_t scp_clk_con; + uint32_t pcm_debug_con; + uint8_t reserved3[4]; + uint32_t ddren_dbc_con; + uint32_t spm_resource_ack_con4; + uint32_t spm_resource_ack_con0; + uint32_t spm_resource_ack_con1; + uint32_t spm_resource_ack_con2; + uint32_t spm_resource_ack_con3; + uint32_t pcm_reg0_data; + uint32_t pcm_reg2_data; + uint32_t pcm_reg6_data; + uint32_t pcm_reg7_data; + uint32_t pcm_reg13_data; + uint32_t src_req_sta_0; + uint32_t src_req_sta_1; + uint32_t src_req_sta_2; + uint32_t pcm_timer_out; + uint32_t pcm_wdt_out; + uint32_t spm_irq_sta; + uint32_t src_req_sta_4; + uint32_t md32pcm_wakeup_sta; + uint32_t md32pcm_event_sta; + uint32_t spm_wakeup_sta; + uint32_t spm_wakeup_ext_sta; + uint32_t spm_wakeup_misc; + uint32_t mm_dvfs_halt; + uint8_t reserved4[8]; + uint32_t bus_protect_rdy; + uint32_t bus_protect1_rdy; + uint32_t bus_protect2_rdy; + uint32_t bus_protect3_rdy; + uint32_t subsys_idle_sta; + uint32_t pcm_sta; + uint32_t src_req_sta_3; + uint32_t pwr_status; + uint32_t pwr_status_2nd; + uint32_t cpu_pwr_status; + uint32_t other_pwr_status; + uint32_t spm_vtcxo_event_count_sta; + uint32_t spm_infra_event_count_sta; + uint32_t spm_vrf18_event_count_sta; + uint32_t spm_apsrc_event_count_sta; + uint32_t spm_ddren_event_count_sta; + uint32_t md32pcm_sta; + uint32_t md32pcm_pc; + uint8_t reserved5[12]; + uint32_t dvfsrc_event_sta; + uint32_t bus_protect4_rdy; + uint32_t bus_protect5_rdy; + uint32_t bus_protect6_rdy; + uint32_t bus_protect7_rdy; + uint32_t bus_protect8_rdy; + uint8_t reserved6[20]; + uint32_t spm_twam_last_sta0; + uint32_t spm_twam_last_sta1; + uint32_t spm_twam_last_sta2; + uint32_t spm_twam_last_sta3; + uint32_t spm_twam_curr_sta0; + uint32_t spm_twam_curr_sta1; + uint32_t spm_twam_curr_sta2; + uint32_t spm_twam_curr_sta3; + uint32_t spm_twam_timer_out; + uint32_t spm_cg_check_sta; + uint32_t spm_dvfs_sta; + uint32_t spm_dvfs_opp_sta; + uint32_t spm_mcusys_pwr_con; + uint32_t spm_cputop_pwr_con; + uint32_t spm_cpu0_pwr_con; + uint32_t spm_cpu1_pwr_con; + uint32_t spm_cpu2_pwr_con; + uint32_t spm_cpu3_pwr_con; + uint32_t spm_cpu4_pwr_con; + uint32_t spm_cpu5_pwr_con; + uint32_t spm_cpu6_pwr_con; + uint32_t spm_cpu7_pwr_con; + uint8_t reserved7[4]; + uint32_t armpll_clk_con; + uint32_t mcusys_idle_sta; + uint32_t gic_wakeup_sta; + uint32_t cpu_spare_con; + uint32_t cpu_spare_con_set; + uint32_t cpu_spare_con_clr; + uint32_t armpll_clk_sel; + uint32_t ext_int_wakeup_req; + uint32_t ext_int_wakeup_req_set; + uint32_t ext_int_wakeup_req_clr; + uint8_t reserved8[12]; + uint32_t cpu_irq_mask; + uint32_t cpu_irq_mask_set; + uint32_t cpu_irq_mask_clr; + uint8_t reserved9[20]; + uint32_t cpu_wfi_en; + uint32_t cpu_wfi_en_set; + uint32_t cpu_wfi_en_clr; + uint8_t reserved10[20]; + uint32_t root_cputop_addr; + uint32_t root_core_addr; + uint8_t reserved11[40]; + uint32_t spm2sw_mailbox_0; + uint32_t spm2sw_mailbox_1; + uint32_t spm2sw_mailbox_2; + uint32_t spm2sw_mailbox_3; + uint32_t sw2spm_wakeup; + uint32_t sw2spm_wakeup_set; + uint32_t sw2spm_wakeup_clr; + uint32_t sw2spm_mailbox_0; + uint32_t sw2spm_mailbox_1; + uint32_t sw2spm_mailbox_2; + uint32_t sw2spm_mailbox_3; + uint32_t sw2spm_cfg; + uint32_t md1_pwr_con; + uint32_t conn_pwr_con; + uint32_t mfg0_pwr_con; + uint32_t mfg1_pwr_con; + uint32_t mfg2_pwr_con; + uint32_t mfg3_pwr_con; + uint32_t mfg4_pwr_con; + uint32_t mfg5_pwr_con; + uint32_t mfg6_pwr_con; + uint32_t ifr_pwr_con; + uint32_t ifr_sub_pwr_con; + uint32_t dpy_pwr_con; + uint32_t dramc_md32_pwr_con; + uint32_t isp_pwr_con; + uint32_t isp2_pwr_con; + uint32_t ipe_pwr_con; + uint32_t vde_pwr_con; + uint32_t vde2_pwr_con; + uint32_t ven_pwr_con; + uint32_t ven_core1_pwr_con; + uint32_t mdp_pwr_con; + uint32_t dis_pwr_con; + uint32_t audio_pwr_con; + uint32_t cam_pwr_con; + uint32_t cam_rawa_pwr_con; + uint32_t cam_rawb_pwr_con; + uint32_t cam_rawc_pwr_con; + uint32_t sysram_con; + uint32_t sysrom_con; + uint32_t sspm_sram_con; + uint32_t scp_sram_con; + uint32_t dpy_shu_sram_con; + uint32_t ufs_sram_con; + uint32_t devapc_ifr_sram_con; + uint32_t devapc_subifr_sram_con; + uint32_t devapc_acp_sram_con; + uint32_t usb_sram_con; + uint32_t dummy_sram_con; + uint32_t md_ext_buck_iso_con; + uint32_t ext_buck_iso; + uint32_t dxcc_sram_con; + uint32_t msdc_pwr_con; + uint32_t debugtop_sram_con; + uint32_t dp_tx_pwr_con; + uint32_t dpmaif_sram_con; + uint32_t dpy_shu2_sram_con; + uint32_t dramc_mcu2_sram_con; + uint32_t dramc_mcu_sram_con; + uint32_t mcupm_pwr_con; + uint32_t dpy2_pwr_con; + uint32_t spm_sram_con; + uint8_t reserved12[4]; + uint32_t peri_pwr_con; + uint32_t nna0_pwr_con; + uint32_t nna1_pwr_con; + uint32_t nna2_pwr_con; + uint32_t nna_pwr_con; + uint32_t adsp_pwr_con; + uint32_t dpy_sram_con; + uint32_t nna3_pwr_con; + uint8_t reserved13[8]; + uint32_t wpe_pwr_con; + uint8_t reserved14[4]; + uint32_t spm_mem_ck_sel; + uint32_t spm_bus_protect_mask_b; + uint32_t spm_bus_protect1_mask_b; + uint32_t spm_bus_protect2_mask_b; + uint32_t spm_bus_protect3_mask_b; + uint32_t spm_bus_protect4_mask_b; + uint32_t spm_emi_bw_mode; + uint32_t ap2md_peer_wakeup; + uint32_t ulposc_con; + uint32_t spm2mm_con; + uint32_t spm_bus_protect5_mask_b; + uint32_t spm2mcupm_con; + uint32_t ap_mdsrc_req; + uint32_t spm2emi_enter_ulpm; + uint32_t spm2md_dvfs_con; + uint32_t md2spm_dvfs_con; + uint32_t spm_bus_protect6_mask_b; + uint32_t spm_bus_protect7_mask_b; + uint32_t spm_bus_protect8_mask_b; + uint32_t spm_pll_con; + uint32_t rc_spm_ctrl; + uint32_t spm_dram_mcu_sw_con_0; + uint32_t spm_dram_mcu_sw_con_1; + uint32_t spm_dram_mcu_sw_con_2; + uint32_t spm_dram_mcu_sw_con_3; + uint32_t spm_dram_mcu_sw_con_4; + uint32_t spm_dram_mcu_sta_0; + uint32_t spm_dram_mcu_sta_1; + uint32_t spm_dram_mcu_sta_2; + uint32_t spm_dram_mcu_sw_sel_0; + uint32_t relay_dvfs_level; + uint8_t reserved15[4]; + uint32_t dramc_dpy_clk_sw_con_0; + uint32_t dramc_dpy_clk_sw_con_1; + uint32_t dramc_dpy_clk_sw_con_2; + uint32_t dramc_dpy_clk_sw_con_3; + uint32_t dramc_dpy_clk_sw_sel_0; + uint32_t dramc_dpy_clk_sw_sel_1; + uint32_t dramc_dpy_clk_sw_sel_2; + uint32_t dramc_dpy_clk_sw_sel_3; + uint32_t dramc_dpy_clk_spm_con; + uint32_t spm_dvfs_level; + uint32_t spm_cirq_con; + uint32_t spm_dvfs_misc; + uint8_t reserved16[4]; + uint32_t rg_module_sw_cg_0_mask_req_0; + uint32_t rg_module_sw_cg_0_mask_req_1; + uint32_t rg_module_sw_cg_0_mask_req_2; + uint32_t rg_module_sw_cg_1_mask_req_0; + uint32_t rg_module_sw_cg_1_mask_req_1; + uint32_t rg_module_sw_cg_1_mask_req_2; + uint32_t rg_module_sw_cg_2_mask_req_0; + uint32_t rg_module_sw_cg_2_mask_req_1; + uint32_t rg_module_sw_cg_2_mask_req_2; + uint32_t rg_module_sw_cg_3_mask_req_0; + uint32_t rg_module_sw_cg_3_mask_req_1; + uint32_t rg_module_sw_cg_3_mask_req_2; + uint32_t pwr_status_mask_req_0; + uint32_t pwr_status_mask_req_1; + uint32_t pwr_status_mask_req_2; + uint32_t spm_cg_check_con; + uint32_t spm_src_rdy_sta; + uint32_t spm_dvs_dfs_level; + uint32_t spm_force_dvfs; + uint8_t reserved17[256]; + uint32_t spm_sw_flag_0; + uint32_t spm_sw_debug_0; + uint32_t spm_sw_flag_1; + uint32_t spm_sw_debug_1; + uint32_t spm_sw_rsv_0; + uint32_t spm_sw_rsv_1; + uint32_t spm_sw_rsv_2; + uint32_t spm_sw_rsv_3; + uint32_t spm_sw_rsv_4; + uint32_t spm_sw_rsv_5; + uint32_t spm_sw_rsv_6; + uint32_t spm_sw_rsv_7; + uint32_t spm_sw_rsv_8; + uint32_t spm_bk_wake_event; + uint32_t spm_bk_vtcxo_dur; + uint32_t spm_bk_wake_misc; + uint32_t spm_bk_pcm_timer; + uint8_t reserved18[12]; + uint32_t spm_rsv_con_0; + uint32_t spm_rsv_con_1; + uint32_t spm_rsv_sta_0; + uint32_t spm_rsv_sta_1; + uint32_t spm_spare_con; + uint32_t spm_spare_con_set; + uint32_t spm_spare_con_clr; + uint32_t spm_cross_wake_m00_req; + uint32_t spm_cross_wake_m01_req; + uint32_t spm_cross_wake_m02_req; + uint32_t spm_cross_wake_m03_req; + uint32_t scp_vcore_level; + uint32_t sc_mm_ck_sel_con; + uint32_t spare_ack_mask; + uint32_t spm_spare_function; + uint32_t spm_dv_con_0; + uint32_t spm_dv_con_1; + uint32_t spm_dv_sta; + uint32_t conn_xowcn_debug_en; + uint32_t spm_sema_m0; + uint32_t spm_sema_m1; + uint32_t spm_sema_m2; + uint32_t spm_sema_m3; + uint32_t spm_sema_m4; + uint32_t spm_sema_m5; + uint32_t spm_sema_m6; + uint32_t spm_sema_m7; + uint32_t spm2adsp_mailbox; + uint32_t adsp2spm_mailbox; + uint32_t spm_adsp_irq; + uint32_t spm_md32_irq; + uint32_t spm2pmcu_mailbox_0; + uint32_t spm2pmcu_mailbox_1; + uint32_t spm2pmcu_mailbox_2; + uint32_t spm2pmcu_mailbox_3; + uint32_t pmcu2spm_mailbox_0; + uint32_t pmcu2spm_mailbox_1; + uint32_t pmcu2spm_mailbox_2; + uint32_t pmcu2spm_mailbox_3; + uint32_t ufs_psri_sw; + uint32_t ufs_psri_sw_set; + uint32_t ufs_psri_sw_clr; + uint32_t spm_ap_sema; + uint32_t spm_spm_sema; + uint32_t spm_dvfs_con; + uint32_t spm_dvfs_con_sta; + uint32_t spm_pmic_spmi_con; + uint8_t reserved19[4]; + uint32_t spm_dvfs_cmd0; + uint32_t spm_dvfs_cmd1; + uint32_t spm_dvfs_cmd2; + uint32_t spm_dvfs_cmd3; + uint32_t spm_dvfs_cmd4; + uint32_t spm_dvfs_cmd5; + uint32_t spm_dvfs_cmd6; + uint32_t spm_dvfs_cmd7; + uint32_t spm_dvfs_cmd8; + uint32_t spm_dvfs_cmd9; + uint32_t spm_dvfs_cmd10; + uint32_t spm_dvfs_cmd11; + uint32_t spm_dvfs_cmd12; + uint32_t spm_dvfs_cmd13; + uint32_t spm_dvfs_cmd14; + uint32_t spm_dvfs_cmd15; + uint32_t spm_dvfs_cmd16; + uint32_t spm_dvfs_cmd17; + uint32_t spm_dvfs_cmd18; + uint32_t spm_dvfs_cmd19; + uint32_t spm_dvfs_cmd20; + uint32_t spm_dvfs_cmd21; + uint32_t spm_dvfs_cmd22; + uint32_t spm_dvfs_cmd23; + uint32_t sys_timer_value_l; + uint32_t sys_timer_value_h; + uint32_t sys_timer_start_l; + uint32_t sys_timer_start_h; + uint32_t sys_timer_latch_l_00; + uint32_t sys_timer_latch_h_00; + uint32_t sys_timer_latch_l_01; + uint32_t sys_timer_latch_h_01; + uint32_t sys_timer_latch_l_02; + uint32_t sys_timer_latch_h_02; + uint32_t sys_timer_latch_l_03; + uint32_t sys_timer_latch_h_03; + uint32_t sys_timer_latch_l_04; + uint32_t sys_timer_latch_h_04; + uint32_t sys_timer_latch_l_05; + uint32_t sys_timer_latch_h_05; + uint32_t sys_timer_latch_l_06; + uint32_t sys_timer_latch_h_06; + uint32_t sys_timer_latch_l_07; + uint32_t sys_timer_latch_h_07; + uint32_t sys_timer_latch_l_08; + uint32_t sys_timer_latch_h_08; + uint32_t sys_timer_latch_l_09; + uint32_t sys_timer_latch_h_09; + uint32_t sys_timer_latch_l_10; + uint32_t sys_timer_latch_h_10; + uint32_t sys_timer_latch_l_11; + uint32_t sys_timer_latch_h_11; + uint32_t sys_timer_latch_l_12; + uint32_t sys_timer_latch_h_12; + uint32_t sys_timer_latch_l_13; + uint32_t sys_timer_latch_h_13; + uint32_t sys_timer_latch_l_14; + uint32_t sys_timer_latch_h_14; + uint32_t sys_timer_latch_l_15; + uint32_t sys_timer_latch_h_15; + uint32_t pcm_wdt_latch_0; + uint32_t pcm_wdt_latch_1; + uint32_t pcm_wdt_latch_2; + uint32_t pcm_wdt_latch_3; + uint32_t pcm_wdt_latch_4; + uint32_t pcm_wdt_latch_5; + uint32_t pcm_wdt_latch_6; + uint32_t pcm_wdt_latch_7; + uint32_t pcm_wdt_latch_8; + uint32_t pcm_wdt_latch_9; + uint32_t pcm_wdt_latch_10; + uint32_t pcm_wdt_latch_11; + uint32_t pcm_wdt_latch_12; + uint32_t pcm_wdt_latch_13; + uint32_t pcm_wdt_latch_14; + uint32_t pcm_wdt_latch_15; + uint32_t pcm_wdt_latch_16; + uint32_t pcm_wdt_latch_17; + uint32_t pcm_wdt_latch_18; + uint32_t pcm_wdt_latch_spare_0; + uint32_t pcm_wdt_latch_spare_1; + uint32_t pcm_wdt_latch_spare_2; + uint8_t reserved20[24]; + uint32_t pcm_wdt_latch_conn_0; + uint32_t pcm_wdt_latch_conn_1; + uint32_t pcm_wdt_latch_conn_2; + uint8_t reserved21[36]; + uint32_t dramc_gating_err_latch_ch0_0; + uint32_t dramc_gating_err_latch_ch0_1; + uint32_t dramc_gating_err_latch_ch0_2; + uint32_t dramc_gating_err_latch_ch0_3; + uint32_t dramc_gating_err_latch_ch0_4; + uint32_t dramc_gating_err_latch_ch0_5; + uint32_t dramc_gating_err_latch_ch0_6; + uint8_t reserved22[56]; + uint32_t dramc_gating_err_latch_spare_0; + uint8_t reserved23[8]; + uint32_t spm_ack_chk_con_0; + uint32_t spm_ack_chk_pc_0; + uint32_t spm_ack_chk_sel_0; + uint32_t spm_ack_chk_timer_0; + uint32_t spm_ack_chk_sta_0; + uint32_t spm_ack_chk_swint_0; + uint32_t spm_ack_chk_con_1; + uint32_t spm_ack_chk_pc_1; + uint32_t spm_ack_chk_sel_1; + uint32_t spm_ack_chk_timer_1; + uint32_t spm_ack_chk_sta_1; + uint32_t spm_ack_chk_swint_1; + uint32_t spm_ack_chk_con_2; + uint32_t spm_ack_chk_pc_2; + uint32_t spm_ack_chk_sel_2; + uint32_t spm_ack_chk_timer_2; + uint32_t spm_ack_chk_sta_2; + uint32_t spm_ack_chk_swint_2; + uint32_t spm_ack_chk_con_3; + uint32_t spm_ack_chk_pc_3; + uint32_t spm_ack_chk_sel_3; + uint32_t spm_ack_chk_timer_3; + uint32_t spm_ack_chk_sta_3; + uint32_t spm_ack_chk_swint_3; + uint32_t spm_counter_0; + uint32_t spm_counter_1; + uint32_t spm_counter_2; + uint32_t sys_timer_con; + uint32_t spm_twam_con; + uint32_t spm_twam_window_len; + uint32_t spm_twam_idle_sel; + uint32_t spm_twam_event_clear; + uint32_t opp0_table; + uint32_t opp1_table; + uint32_t opp2_table; + uint32_t opp3_table; + uint32_t opp4_table; + uint32_t opp5_table; + uint32_t opp6_table; + uint32_t opp7_table; + uint32_t opp8_table; + uint32_t opp9_table; + uint32_t opp10_table; + uint32_t opp11_table; + uint32_t opp12_table; + uint32_t opp13_table; + uint32_t opp14_table; + uint32_t opp15_table; + uint32_t opp16_table; + uint32_t opp17_table; + uint32_t shu0_array; + uint32_t shu1_array; + uint32_t shu2_array; + uint32_t shu3_array; + uint32_t shu4_array; + uint32_t shu5_array; + uint32_t shu6_array; + uint32_t shu7_array; + uint32_t shu8_array; + uint32_t shu9_array; + uint32_t ssusb_top_pwr_con; + uint32_t ssusb_top_p1_pwr_con; + uint32_t adsp_infra_pwr_con; + uint32_t adsp_ao_pwr_con; +}; + +struct pwr_ctrl { + /* For SPM */ + uint32_t pcm_flags; + uint32_t pcm_flags_cust; + uint32_t pcm_flags_cust_set; + uint32_t pcm_flags_cust_clr; + uint32_t pcm_flags1; + uint32_t pcm_flags1_cust; + uint32_t pcm_flags1_cust_set; + uint32_t pcm_flags1_cust_clr; + uint32_t timer_val; + uint32_t timer_val_cust; + uint32_t timer_val_ramp_en; + uint32_t timer_val_ramp_en_sec; + uint32_t wake_src; + uint32_t wake_src_cust; + uint32_t wakelock_timer_val; + uint8_t wdt_disable; + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + uint8_t reg_wfi_op; + uint8_t reg_wfi_type; + uint8_t reg_mp0_cputop_idle_mask; + uint8_t reg_mp1_cputop_idle_mask; + uint8_t reg_mcusys_idle_mask; + uint8_t reg_md_apsrc_1_sel; + uint8_t reg_md_apsrc_0_sel; + uint8_t reg_conn_apsrc_sel; + + /* SPM_SRC6_MASK */ + uint32_t reg_ccif_event_infra_req_mask_b; + uint32_t reg_ccif_event_apsrc_req_mask_b; + + /* SPM_SRC_REQ */ + uint8_t reg_spm_apsrc_req; + uint8_t reg_spm_f26m_req; + uint8_t reg_spm_infra_req; + uint8_t reg_spm_vrf18_req; + uint8_t reg_spm_ddren_req; + uint8_t reg_spm_dvfs_req; + uint8_t reg_spm_sw_mailbox_req; + uint8_t reg_spm_sspm_mailbox_req; + uint8_t reg_spm_adsp_mailbox_req; + uint8_t reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + uint8_t reg_md_0_srcclkena_mask_b; + uint8_t reg_md_0_infra_req_mask_b; + uint8_t reg_md_0_apsrc_req_mask_b; + uint8_t reg_md_0_vrf18_req_mask_b; + uint8_t reg_md_0_ddren_req_mask_b; + uint8_t reg_md_1_srcclkena_mask_b; + uint8_t reg_md_1_infra_req_mask_b; + uint8_t reg_md_1_apsrc_req_mask_b; + uint8_t reg_md_1_vrf18_req_mask_b; + uint8_t reg_md_1_ddren_req_mask_b; + uint8_t reg_conn_srcclkena_mask_b; + uint8_t reg_conn_srcclkenb_mask_b; + uint8_t reg_conn_infra_req_mask_b; + uint8_t reg_conn_apsrc_req_mask_b; + uint8_t reg_conn_vrf18_req_mask_b; + uint8_t reg_conn_ddren_req_mask_b; + uint8_t reg_conn_vfe28_mask_b; + uint8_t reg_srcclkeni_srcclkena_mask_b; + uint8_t reg_srcclkeni_infra_req_mask_b; + uint8_t reg_infrasys_apsrc_req_mask_b; + uint8_t reg_infrasys_ddren_req_mask_b; + uint8_t reg_sspm_srcclkena_mask_b; + uint8_t reg_sspm_infra_req_mask_b; + uint8_t reg_sspm_apsrc_req_mask_b; + uint8_t reg_sspm_vrf18_req_mask_b; + uint8_t reg_sspm_ddren_req_mask_b; + + /* SPM_SRC2_MASK */ + uint8_t reg_scp_srcclkena_mask_b; + uint8_t reg_scp_infra_req_mask_b; + uint8_t reg_scp_apsrc_req_mask_b; + uint8_t reg_scp_vrf18_req_mask_b; + uint8_t reg_scp_ddren_req_mask_b; + uint8_t reg_audio_dsp_srcclkena_mask_b; + uint8_t reg_audio_dsp_infra_req_mask_b; + uint8_t reg_audio_dsp_apsrc_req_mask_b; + uint8_t reg_audio_dsp_vrf18_req_mask_b; + uint8_t reg_audio_dsp_ddren_req_mask_b; + uint8_t reg_ufs_srcclkena_mask_b; + uint8_t reg_ufs_infra_req_mask_b; + uint8_t reg_ufs_apsrc_req_mask_b; + uint8_t reg_ufs_vrf18_req_mask_b; + uint8_t reg_ufs_ddren_req_mask_b; + uint8_t reg_disp0_apsrc_req_mask_b; + uint8_t reg_disp0_ddren_req_mask_b; + uint8_t reg_disp1_apsrc_req_mask_b; + uint8_t reg_disp1_ddren_req_mask_b; + uint8_t reg_gce_infra_req_mask_b; + uint8_t reg_gce_apsrc_req_mask_b; + uint8_t reg_gce_vrf18_req_mask_b; + uint8_t reg_gce_ddren_req_mask_b; + uint8_t reg_apu_srcclkena_mask_b; + uint8_t reg_apu_infra_req_mask_b; + uint8_t reg_apu_apsrc_req_mask_b; + uint8_t reg_apu_vrf18_req_mask_b; + uint8_t reg_apu_ddren_req_mask_b; + uint8_t reg_cg_check_srcclkena_mask_b; + uint8_t reg_cg_check_apsrc_req_mask_b; + uint8_t reg_cg_check_vrf18_req_mask_b; + uint8_t reg_cg_check_ddren_req_mask_b; + + /* SPM_SRC3_MASK */ + uint8_t reg_dvfsrc_event_trigger_mask_b; + uint8_t reg_sw2spm_wakeup_mask_b; + uint8_t reg_adsp2spm_wakeup_mask_b; + uint8_t reg_sspm2spm_wakeup_mask_b; + uint8_t reg_scp2spm_wakeup_mask_b; + uint8_t reg_csyspwrup_ack_mask; + uint8_t reg_spm_reserved_srcclkena_mask_b; + uint8_t reg_spm_reserved_infra_req_mask_b; + uint8_t reg_spm_reserved_apsrc_req_mask_b; + uint8_t reg_spm_reserved_vrf18_req_mask_b; + uint8_t reg_spm_reserved_ddren_req_mask_b; + uint8_t reg_mcupm_srcclkena_mask_b; + uint8_t reg_mcupm_infra_req_mask_b; + uint8_t reg_mcupm_apsrc_req_mask_b; + uint8_t reg_mcupm_vrf18_req_mask_b; + uint8_t reg_mcupm_ddren_req_mask_b; + uint8_t reg_msdc0_srcclkena_mask_b; + uint8_t reg_msdc0_infra_req_mask_b; + uint8_t reg_msdc0_apsrc_req_mask_b; + uint8_t reg_msdc0_vrf18_req_mask_b; + uint8_t reg_msdc0_ddren_req_mask_b; + uint8_t reg_msdc1_srcclkena_mask_b; + uint8_t reg_msdc1_infra_req_mask_b; + uint8_t reg_msdc1_apsrc_req_mask_b; + uint8_t reg_msdc1_vrf18_req_mask_b; + uint8_t reg_msdc1_ddren_req_mask_b; + + /* SPM_SRC4_MASK */ + uint32_t reg_ccif_event_srcclkena_mask_b; + uint8_t reg_bak_psri_srcclkena_mask_b; + uint8_t reg_bak_psri_infra_req_mask_b; + uint8_t reg_bak_psri_apsrc_req_mask_b; + uint8_t reg_bak_psri_vrf18_req_mask_b; + uint8_t reg_bak_psri_ddren_req_mask_b; + uint8_t reg_dramc_md32_infra_req_mask_b; + uint8_t reg_dramc_md32_vrf18_req_mask_b; + uint8_t reg_conn_srcclkenb2pwrap_mask_b; + uint8_t reg_dramc_md32_apsrc_req_mask_b; + + /* SPM_SRC5_MASK */ + uint32_t reg_mcusys_merge_apsrc_req_mask_b; + uint32_t reg_mcusys_merge_ddren_req_mask_b; + uint8_t reg_afe_srcclkena_mask_b; + uint8_t reg_afe_infra_req_mask_b; + uint8_t reg_afe_apsrc_req_mask_b; + uint8_t reg_afe_vrf18_req_mask_b; + uint8_t reg_afe_ddren_req_mask_b; + uint8_t reg_msdc2_srcclkena_mask_b; + uint8_t reg_msdc2_infra_req_mask_b; + uint8_t reg_msdc2_apsrc_req_mask_b; + uint8_t reg_msdc2_vrf18_req_mask_b; + uint8_t reg_msdc2_ddren_req_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + uint32_t reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + uint32_t reg_ext_wakeup_event_mask; + + /* SPM_SRC7_MASK */ + uint8_t reg_pcie_srcclkena_mask_b; + uint8_t reg_pcie_infra_req_mask_b; + uint8_t reg_pcie_apsrc_req_mask_b; + uint8_t reg_pcie_vrf18_req_mask_b; + uint8_t reg_pcie_ddren_req_mask_b; + uint8_t reg_dpmaif_srcclkena_mask_b; + uint8_t reg_dpmaif_infra_req_mask_b; + uint8_t reg_dpmaif_apsrc_req_mask_b; + uint8_t reg_dpmaif_vrf18_req_mask_b; + uint8_t reg_dpmaif_ddren_req_mask_b; + + /* Auto-gen End */ +}; + +check_member(mtk_spm_regs, poweron_config_set, 0x0); +check_member(mtk_spm_regs, dis_pwr_con, 0x354); +check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); +check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); +check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); +check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); +check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); + +struct pcm_desc { + uint32_t pmem_words; + uint32_t total_words; + uint32_t pmem_start; + uint32_t dmem_start; +}; + +struct dyna_load_pcm { + u8 *buf; /* binary array */ + struct pcm_desc desc; +}; + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +static const struct power_domain_data disp[] = { + { + .pwr_con = &mtk_spm->dis_pwr_con, + .pwr_sta_mask = 0x1 << 21, + .sram_pdn_mask = 0x1 << 8, + .sram_ack_mask = 0x1 << 12, + }, +}; + +/* without audio mtcmos control in MT8186 */ +static const struct power_domain_data audio[] = { +}; + +int spm_init(void); + +#endif /* SOC_MEDIATEK_MT8186_SPM_H */ diff --git a/src/soc/mediatek/mt8186/include/soc/symbols.h b/src/soc/mediatek/mt8186/include/soc/symbols.h new file mode 100644 index 0000000000..7610224d5b --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/symbols.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8186_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8186_SYMBOLS_H_ + +#include + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8186_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8186/include/soc/timer.h b/src/soc/mediatek/mt8186/include/soc/timer.h new file mode 100644 index 0000000000..24d85295ce --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/timer.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#ifndef SOC_MEDIATEK_MT8186_TIMER_H +#define SOC_MEDIATEK_MT8186_TIMER_H + +#include + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/tracker.h b/src/soc/mediatek/mt8186/include/soc/tracker.h new file mode 100644 index 0000000000..9c671c9e38 --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8186_TRACKER_H +#define SOC_MEDIATEK_MT8186_TRACKER_H + +#include + +#endif diff --git a/src/soc/mediatek/mt8186/include/soc/usb.h b/src/soc/mediatek/mt8186/include/soc/usb.h new file mode 100644 index 0000000000..297c8f186d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/usb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.5 + */ + +#ifndef SOC_MEDIATEK_MT8186_USB_H +#define SOC_MEDIATEK_MT8186_USB_H + +#include + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64 * 5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 1 + +#endif diff --git a/src/soc/mediatek/mt8186/msdc.c b/src/soc/mediatek/mt8186/msdc.c new file mode 100644 index 0000000000..cfdb0f2cfb --- /dev/null +++ b/src/soc/mediatek/mt8186/msdc.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.7 + */ + +#include +#include +#include +#include +#include + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 23, 6) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 18, 16) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 22, 20) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_2, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_3, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) + +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11cd0000 + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053a0, + MSDC1_GPIO_MODE1_BASE = 0x100053b0, +}; + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + void *gpio_base = (void *)IOCFG_LT_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_LB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_2, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_3, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE); + + /* enable SDCard power */ + mainboard_set_regulator_vol(MTK_REGULATOR_VMCH, 3300000); + mainboard_set_regulator_vol(MTK_REGULATOR_VMC, 3300000); +} diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c new file mode 100644 index 0000000000..b993a9256a --- /dev/null +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -0,0 +1,959 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct pmic_setting init_setting[] = { + {0x1E, 0xA, 0xA, 0}, + {0x22, 0x1F00, 0x1F00, 0}, + {0x2E, 0x1, 0x1, 0}, + {0x30, 0x1, 0x1, 0}, + {0x36, 0x8888, 0xFFFF, 0}, + {0x3A, 0x8888, 0xFFFF, 0}, + {0x3C, 0x8888, 0xFFFF, 0}, + {0x3E, 0x888, 0xFFF, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x18, 0x18, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x12A, 0x100, 0x180, 0}, + {0x134, 0x80, 0x2890, 0}, + {0x14C, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x790, 0x280, 0x780, 0}, + {0x7AC, 0x0, 0x2000, 0}, + {0x98A, 0x1840, 0x1E40, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA24, 0x1E00, 0x1F00, 0}, + {0xA38, 0x0, 0x100, 0}, + {0xA3C, 0x81E0, 0x81E0, 0}, + {0xA44, 0xFFFF, 0xFFFF, 0}, + {0xA46, 0xFC00, 0xFC00, 0}, + {0xC8A, 0x4, 0xC, 0}, + {0xF8C, 0xAAA, 0xAAA, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11A2, 0x0, 0x3000, 0}, + {0x11B0, 0x4000, 0x4000, 0}, + {0x11B4, 0x0, 0x100, 0}, + {0x123A, 0x8040, 0x83FF, 0}, + {0x123E, 0x4, 0x4, 0}, + {0x1242, 0x1, 0x1, 0}, + {0x1260, 0x0, 0x154, 0}, + {0x1312, 0x8, 0x8, 0}, + {0x1334, 0x0, 0x100, 0}, + {0x138A, 0x10, 0x7F, 0}, + {0x138C, 0x15, 0x7F, 0}, + {0x138E, 0x1030, 0x3030, 0}, + {0x140A, 0x10, 0x7F, 0}, + {0x140C, 0x15, 0x7F, 0}, + {0x140E, 0x1030, 0x3030, 0}, + {0x148A, 0x10, 0x7F, 0}, + {0x148E, 0x1030, 0x3030, 0}, + {0x14A2, 0x20, 0x20, 0}, + {0x150A, 0x10, 0x7F, 0}, + {0x150E, 0x1030, 0x3030, 0}, + {0x158A, 0x8, 0x7F, 0}, + {0x158C, 0x90C, 0x7F7F, 0}, + {0x158E, 0x1030, 0x3030, 0}, + {0x159C, 0x8, 0xC, 0}, + {0x15A2, 0x20, 0x20, 0}, + {0x168A, 0x50, 0x7F, 0}, + {0x168C, 0x1964, 0x7F7F, 0}, + {0x168E, 0x2020, 0x3030, 0}, + {0x16A2, 0x20, 0x20, 0}, + {0x16AA, 0x50, 0x7F, 0}, + {0x170C, 0x1964, 0x7F7F, 0}, + {0x170E, 0x2020, 0x3030, 0}, + {0x172A, 0x44, 0x7F, 0}, + {0x178C, 0x202, 0x7F7F, 0}, + {0x178E, 0x70, 0x73, 0}, + {0x1790, 0xC, 0xC, 0}, + {0x1798, 0x2810, 0x3F3F, 0}, + {0x179A, 0x800, 0x3F00, 0}, + {0x179E, 0x1, 0x1, 0}, + {0x1808, 0x2000, 0x3000, 0}, + {0x180C, 0x60, 0x60, 0}, + {0x1814, 0x3FF0, 0x7FFF, 0}, + {0x1816, 0x3, 0x7, 0}, + {0x181A, 0x6081, 0xFFBF, 0}, + {0x181C, 0x503, 0x787, 0}, + {0x181E, 0xA462, 0xFFFF, 0}, + {0x1820, 0xA662, 0xFFFF, 0}, + {0x1824, 0xDB6, 0xFFF, 0}, + {0x1828, 0x160, 0x160, 0}, + {0x1830, 0x3FF0, 0x7FFF, 0}, + {0x1832, 0x3, 0x7, 0}, + {0x1836, 0x6081, 0xFFBF, 0}, + {0x1838, 0x503, 0x787, 0}, + {0x183A, 0xA262, 0xFFFF, 0}, + {0x183C, 0xA262, 0xFFFF, 0}, + {0x1840, 0xDB6, 0xFFF, 0}, + {0x1888, 0x420, 0xE7C, 0}, + {0x188A, 0x801, 0x3C07, 0}, + {0x188C, 0x1F, 0x3F, 0}, + {0x188E, 0x129A, 0xFFFF, 0}, + {0x1894, 0x58, 0x1F8, 0}, + {0x1896, 0x1C, 0x7C, 0}, + {0x1898, 0x1805, 0x3C07, 0}, + {0x189A, 0xF, 0xF, 0}, + {0x189C, 0x221A, 0xFFFF, 0}, + {0x18A0, 0x2E, 0x3F, 0}, + {0x18A2, 0x0, 0x40, 0}, + {0x18A4, 0x2C06, 0x3C07, 0}, + {0x18A6, 0xF, 0xF, 0}, + {0x18A8, 0x221A, 0xFFFF, 0}, + {0x18AC, 0x2E, 0x3F, 0}, + {0x18AE, 0x0, 0x40, 0}, + {0x18B0, 0x1805, 0x3C07, 0}, + {0x18B2, 0xF, 0xF, 0}, + {0x18B4, 0x221A, 0xFFFF, 0}, + {0x18B8, 0x2E, 0x3F, 0}, + {0x18BC, 0x50, 0x4F0, 0}, + {0x18BE, 0x3C, 0xFC, 0}, + {0x18C0, 0x0, 0x300, 0}, + {0x18C2, 0x8886, 0xFFFF, 0}, + {0x1A0E, 0x3, 0x3, 0}, + {0x1A10, 0x1, 0x1, 0}, + {0x1A12, 0x0, 0x1, 0}, + {0x1A14, 0x0, 0x1, 0}, + {0x1A16, 0x0, 0x1, 0}, + {0x1A18, 0x0, 0x1, 0}, + {0x1A1A, 0x0, 0x1, 0}, + {0x1A1C, 0x0, 0x1, 0}, + {0x1A1E, 0x0, 0x1, 0}, + {0x1A20, 0x0, 0x1, 0}, + {0x1A22, 0x0, 0x1, 0}, + {0x1A24, 0x0, 0x1, 0}, + {0x1A26, 0x0, 0x1, 0}, + {0x1A2C, 0x0, 0x1, 0}, + {0x1A2E, 0x0, 0x1, 0}, + {0x1A30, 0x0, 0x1, 0}, + {0x1A32, 0x0, 0x1, 0}, + {0x1A34, 0x0, 0x1, 0}, + {0x1A36, 0x0, 0x1, 0}, + {0x1A38, 0x0, 0x1, 0}, + {0x1A3A, 0x0, 0x1, 0}, + {0x1A3C, 0x0, 0x1, 0}, + {0x1A3E, 0x0, 0x1, 0}, + {0x1A40, 0x0, 0x1, 0}, + {0x1A42, 0x0, 0x1, 0}, + {0x1A44, 0x0, 0x1, 0}, + {0x1A46, 0x0, 0x1, 0}, + {0x1A48, 0x0, 0x1, 0}, + {0x1A4A, 0x0, 0x1, 0}, + {0x1A4C, 0x0, 0x1, 0}, + {0x1A4E, 0x0, 0x1, 0}, + {0x1A50, 0xE7FF, 0xE7FF, 0}, + {0x1A56, 0x7FFF, 0x7FFF, 0}, + {0x1B48, 0x10, 0x7F, 0}, + {0x1B4A, 0xF15, 0x7F7F, 0}, + {0x1B8A, 0x10, 0x7F, 0}, + {0x1B8C, 0xF15, 0x7F7F, 0}, + {0x1BA8, 0x10, 0x7F, 0}, + {0x1BAA, 0xF15, 0x7F7F, 0}, + {0x1BAC, 0x0, 0x3, 0}, + {0x1BCA, 0x10, 0x7F, 0}, + {0x1BCC, 0x70F, 0x7F7F, 0}, + {0x1C9E, 0x38, 0x7F, 0}, + {0x1CA0, 0x70F, 0x7F7F, 0}, + /* VSRAM_CORE: set SW mode */ + {0x1CA4, 0x1, 0xFFFF, 0}, + /* VSRAM_CORE: SW set OFF */ + {0x1C9C, 0x0, 0xFFFF, 0}, + {0x1EA2, 0x1B, 0x1F, 0}, + {0x1EA4, 0xC00, 0x1C00, 0}, + {0x1EA6, 0xC00, 0x1C00, 0}, + {0x1EA8, 0xC00, 0x1C00, 0}, +}; + +static struct pmic_setting lp_setting[] = { + /* Suspend */ + /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ + {0x1390, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ + {0x1490, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ + {0x1510, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ + {0x1590, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ + {0x1690, 0x1, 0x1, 0}, + /* [1:1]: RG_BUCK_VS2_HW0_OP_EN */ + {0x1710, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VS2_HW0_OP_CFG */ + {0x1716, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_EN */ + {0x1610, 0x1, 0x1, 1}, + /* [1:1]: RG_BUCK_VDRAM1_HW0_OP_CFG */ + {0x1616, 0x1, 0x1, 1}, + /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ + {0x1410, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ + {0x1BD0, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_EN */ + {0x1BAE, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_HW0_OP_CFG */ + {0x1BB4, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ + {0x1B4E, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VXO22_HW0_OP_EN */ + {0x1A8A, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VXO22_HW0_OP_CFG */ + {0x1A90, 0x1, 0x1, 1}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ + {0x1C1E, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ + {0x1C24, 0x0, 0x1, 2}, + /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ + {0x1C46, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ + {0x1D8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ + {0x1C5A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ + {0x1C6E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ + {0x1C9E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ + {0x1C8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ + {0x1B90, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ + {0x1CB2, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VA12_HW0_OP_EN */ + {0x1A9E, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VA12_HW0_OP_CFG */ + {0x1AA4, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUX18_HW0_OP_EN */ + {0x1AB2, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUX18_HW0_OP_CFG */ + {0x1AB8, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUD28_HW0_OP_EN */ + {0x1AC6, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VAUD28_HW0_OP_CFG */ + {0x1ACC, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ + {0x1ADA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ + {0x1AEE, 0x1, 0x1, 0}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ + {0x1C0A, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ + {0x1C10, 0x0, 0x1, 2}, + /* [1:1]: RG_LDO_VDRAM2_HW0_OP_EN */ + {0x1B0A, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VDRAM2_HW0_OP_CFG */ + {0x1B10, 0x1, 0x1, 1}, + /* [0:0]: RG_LDO_VMC_SW_OP_EN */ + {0x1CC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ + {0x1CDA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ + {0x1B1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ + {0x1D4A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ + {0x1D5E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ + {0x1D0A, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ + {0x1B32, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ + {0x1B38, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_EN */ + {0x1B32, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VUSB_HW0_OP_CFG */ + {0x1B38, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VBIF28_HW0_OP_EN */ + {0x1DA0, 0x1, 0x1, 1}, + /* [1:1]: RG_LDO_VBIF28_HW0_OP_CFG */ + {0x1DA6, 0x0, 0x1, 1}, + + /* Deep idle setting */ + /* [0:0]: RG_BUCK_VPROC11_SW_OP_EN */ + {0x1390, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VCORE_SW_OP_EN */ + {0x1490, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VGPU_SW_OP_EN */ + {0x1510, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VMODEM_SW_OP_EN */ + {0x1590, 0x1, 0x1, 0}, + /* [0:0]: RG_BUCK_VS1_SW_OP_EN */ + {0x1690, 0x1, 0x1, 0}, + /* [3:3]: RG_BUCK_VS2_HW2_OP_EN */ + {0x1710, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VS2_HW2_OP_CFG */ + {0x1716, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_EN */ + {0x1610, 0x1, 0x1, 3}, + /* [3:3]: RG_BUCK_VDRAM1_HW2_OP_CFG */ + {0x1616, 0x1, 0x1, 3}, + /* [0:0]: RG_BUCK_VPROC12_SW_OP_EN */ + {0x1410, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_GPU_SW_OP_EN */ + {0x1BD0, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_EN */ + {0x1BAE, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VSRAM_OTHERS_HW2_OP_CFG */ + {0x1BB4, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VSRAM_PROC11_SW_OP_EN */ + {0x1B4E, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VXO22_HW2_OP_EN */ + {0x1A8A, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VXO22_HW2_OP_CFG */ + {0x1A90, 0x1, 0x1, 3}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_EN */ + {0x1C1E, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ + {0x1C24, 0x0, 0x1, 2}, + /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ + {0x1C46, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ + {0x1D1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN28_SW_OP_EN */ + {0x1D8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCN18_SW_OP_EN */ + {0x1C5A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA1_SW_OP_EN */ + {0x1C6E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMD_SW_OP_EN */ + {0x1C9E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMA2_SW_OP_EN */ + {0x1C8A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSRAM_PROC12_SW_OP_EN */ + {0x1B90, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VCAMIO_SW_OP_EN */ + {0x1CB2, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VLDO28_SW_OP_EN */ + {0x1D34, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VA12_HW2_OP_EN */ + {0x1A9E, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VA12_HW2_OP_CFG */ + {0x1AA4, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VAUX18_HW2_OP_EN */ + {0x1AB2, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VAUX18_HW2_OP_CFG */ + {0x1AB8, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VAUD28_SW_OP_EN */ + {0x1AC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO28_SW_OP_EN */ + {0x1ADA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIO18_SW_OP_EN */ + {0x1AEE, 0x1, 0x1, 0}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_EN */ + {0x1C0A, 0x1, 0x1, 2}, + /* [2:2]: RG_LDO_VFE28_HW1_OP_CFG */ + {0x1C10, 0x0, 0x1, 2}, + /* [3:3]: RG_LDO_VDRAM2_HW2_OP_EN */ + {0x1B0A, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VDRAM2_HW2_OP_CFG */ + {0x1B10, 0x1, 0x1, 3}, + /* [0:0]: RG_LDO_VMC_SW_OP_EN */ + {0x1CC6, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VMCH_SW_OP_EN */ + {0x1CDA, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VEMC_SW_OP_EN */ + {0x1B1E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM1_SW_OP_EN */ + {0x1D4A, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VSIM2_SW_OP_EN */ + {0x1D5E, 0x1, 0x1, 0}, + /* [0:0]: RG_LDO_VIBR_SW_OP_EN */ + {0x1D0A, 0x1, 0x1, 0}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ + {0x1B32, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ + {0x1B38, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_EN */ + {0x1B32, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VUSB_HW2_OP_CFG */ + {0x1B38, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VBIF28_HW2_OP_EN */ + {0x1DA0, 0x1, 0x1, 3}, + /* [3:3]: RG_LDO_VBIF28_HW2_OP_CFG */ + {0x1DA6, 0x0, 0x1, 3}, +}; + +static struct pmic_setting scp_setting[] = { + /* scp voltage initialization */ + /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */ + {0x14A6, 0x20, 0x7F, 0}, + /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */ + {0x14A6, 0x20, 0x7F, 8}, + /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */ + {0x14A4, 0x1, 0x1, 0}, + /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */ + {0x14A4, 0x0, 0x1, 1}, + /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */ + {0x1BC6, 0x40, 0x7F, 0}, + /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */ + {0x1BC6, 0x40, 0x7F, 8}, + /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */ + {0x1BC4, 0x1, 0x1, 0}, + /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */ + {0x1BC4, 0x0, 0x1, 1}, + /* [4:4]: RG_SRCVOLTEN_LP_EN */ + {0x134, 0x1, 0x1, 4}, +}; + +static const int vddq_votrim[] = { + 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, + 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static void mt6366_protect_control(bool en_protect) +{ + /* Write a magic number 0x9CA7 to disable protection */ + pwrap_write_field(PMIC_TOP_TMA_KEY, en_protect ? 0 : 0x9CA7, 0xFFFF, 0); +} + +static u32 pmic_read_efuse(int i) +{ + u32 efuse_data = 0; + + /* 1. Enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + /* 7. Disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + +static int pmic_get_efuse_votrim(void) +{ + const u32 cali_efuse = pmic_read_efuse(106) & 0xF; + assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); + return vddq_votrim[cali_efuse]; +} + +static u32 pmic_get_vcore_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vcore_vol(u32 vcore_uv) +{ + u16 vol_reg; + + assert(vcore_uv >= 500000); + assert(vcore_uv <= 1100000); + + vol_reg = (vcore_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vproc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VPROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vproc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VPROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VPROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vsram_proc12_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VSRAM_PROC12_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +static void pmic_set_vsram_proc12_vol(u32 v_uv) +{ + u16 vol_reg; + + assert(v_uv >= 500000); + assert(v_uv <= 1293750); + + vol_reg = (v_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VSRAM_PROC12_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VSRAM_PROC12_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vdram1_vol(void) +{ + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return 500000 + vol_reg * 12500; +} + +static void pmic_set_vdram1_vol(u32 vdram_uv) +{ + u16 vol_reg; + + assert(vdram_uv >= 500000); + assert(vdram_uv <= 1300000); + + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); + udelay(1); +} + +static u32 pmic_get_vddq_vol(void) +{ + int efuse_votrim; + u16 cali_trim; + + if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) + return 0; + + efuse_votrim = pmic_get_efuse_votrim(); + cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; +} + +static void pmic_set_vddq_vol(u32 vddq_uv) +{ + int target_mv, dram2_ori_mv, cali_offset_uv; + u16 cali_trim; + + assert(vddq_uv >= 530000); + assert(vddq_uv <= 680000); + + /* Round down to multiple of 10 */ + target_mv = (vddq_uv / 1000) / 10 * 10; + + dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; + cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); + + if (cali_offset_uv >= 80000) + cali_trim = 8; + else if (cali_offset_uv <= -70000) + cali_trim = 7; + else { + cali_trim = 0; + while (cali_trim < ARRAY_SIZE(vddq_votrim) && + vddq_votrim[cali_trim] != cali_offset_uv) + ++cali_trim; + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); + } + + mt6366_protect_control(false); + pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); + mt6366_protect_control(true); + udelay(1); +} + +static u32 pmic_get_vmch_vol(void) +{ + u32 ret; + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VMCH_ANA_CON0, 0x7, 8); + + switch (vol_reg) { + case 2: + ret = 2900000; + break; + case 3: + ret = 3000000; + break; + case 5: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMCH read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmch_vol(u32 vmch_uv) +{ + u16 val = 0; + + switch (vmch_uv) { + case 2900000: + val = 2; + break; + case 3000000: + val = 3; + break; + case 3300000: + val = 5; + break; + default: + die("ERROR[%s]: VMCH voltage %u is not support.\n", __func__, vmch_uv); + return; + } + + pwrap_write_field(PMIC_VMCH_ANA_CON0, val, 0x7, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMCH_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMCH_CON0, 1, 0xFF, 0); +} + +static u32 pmic_get_vmc_vol(void) +{ + u32 ret; + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VMC_ANA_CON0, 0xF, 8); + + switch (vol_reg) { + case 0x4: + ret = 1800000; + break; + case 0xA: + ret = 2900000; + break; + case 0xB: + ret = 3000000; + break; + case 0xD: + ret = 3300000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VMC read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vmc_vol(u32 vmc_uv) +{ + u16 val = 0; + + switch (vmc_uv) { + case 1800000: + val = 0x4; + break; + case 2900000: + val = 0xA; + break; + case 3000000: + val = 0xB; + break; + case 3300000: + val = 0xD; + break; + default: + die("ERROR[%s]: VMC voltage %u is not support.\n", __func__, vmc_uv); + return; + } + + pwrap_write_field(PMIC_VMC_ANA_CON0, val, 0xF, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VMC_OP_EN, 1, 0xFF, 0); + pwrap_write_field(PMIC_LDO_VMC_CON0, 1, 0xFF, 0); +} + +static u32 pmic_get_vrf12_vol(void) +{ + return (pwrap_read_field(PMIC_LDO_VRF12_CON0, 0x3, 0) & + pwrap_read_field(PMIC_LDO_VRF12_OP_EN, 0x3, 0)) ? 1200000 : 0; +} + +static void pmic_enable_vrf12(void) +{ + pwrap_write_field(PMIC_LDO_VRF12_CON0, 1, 0x3, 0); + pwrap_write_field(PMIC_LDO_VRF12_OP_EN, 1, 0x3, 0); +} + +static u32 pmic_get_vcn33_vol(void) +{ + u32 ret; + u16 vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCN33_ANA_CON0, 0x3, 8); + + switch (vol_reg) { + case 0x1: + ret = 3300000; + break; + case 0x2: + ret = 3400000; + break; + case 0x3: + ret = 3500000; + break; + default: + printk(BIOS_ERR, "ERROR[%s] VCN33 read fail: %d\n", __func__, vol_reg); + ret = 0; + break; + } + return ret; +} + +static void pmic_set_vcn33_vol(u32 vcn33_uv) +{ + u16 val = 0; + + switch (vcn33_uv) { + case 3300000: + val = 0x1; + break; + case 3400000: + val = 0x2; + break; + case 3500000: + val = 0x3; + break; + default: + die("ERROR[%s]: VCN33 voltage %u is not support.\n", __func__, vcn33_uv); + return; + } + + pwrap_write_field(PMIC_VCN33_ANA_CON0, val, 0x3, 8); + + /* Force SW to turn on */ + pwrap_write_field(PMIC_LDO_VCN33_CON0_0, 1, 0x1, 0); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + pwrap_write_field(PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + pwrap_write_field(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); +} + +static void mt6366_init_setting(void) +{ + mt6366_protect_control(false); + for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) + pwrap_write_field( + init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); + mt6366_protect_control(true); +} + +static void wk_sleep_voltage_by_ddr(void) +{ + if (pwrap_read_field(PMIC_VM_MODE, 0x3, 0) == 0x2) + pwrap_write_field(PMIC_VDRAM1_VOSEL_SLEEP, 0x3A, 0x7F, 0); +} + +static void wk_power_down_seq(void) +{ + mt6366_protect_control(false); + /* Set VPROC12 sequence to VA12 */ + pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0); + mt6366_protect_control(true); +} + +static void mt6366_lp_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) + pwrap_write_field( + lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +static void pmic_check_hwcid(void) +{ + printk(BIOS_WARNING, "%s: ID = %#x\n", __func__, + pwrap_read_field(0x8, 0xFFFF, 0)); +} + +void mt6366_set_power_hold(bool enable) +{ + pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); +} + +void mt6366_init_scp_voltage(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++) + pwrap_write_field( + scp_setting[i].addr, scp_setting[i].val, + scp_setting[i].mask, scp_setting[i].shift); +} + +void mt6366_set_vsim2_cali_mv(u32 vsim2_mv) +{ + u16 vsim2_reg, cali_mv; + + cali_mv = vsim2_mv % 100; + assert(cali_mv % 10 == 0); + + switch (vsim2_mv - cali_mv) { + case 1700: + vsim2_reg = 0x3; + break; + case 1800: + vsim2_reg = 0x4; + break; + case 2700: + vsim2_reg = 0x8; + break; + case 3000: + vsim2_reg = 0xb; + break; + case 3100: + vsim2_reg = 0xc; + break; + default: + printk(BIOS_ERR, "%s: voltage %d is not supported\n", __func__, vsim2_mv); + return; + }; + + /* [11:8]=0x8, RG_VSIM2_VOSEL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, vsim2_reg, 0xF, 8); + + /* [3:0], RG_VSIM2_VOCAL */ + pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); +} + +void mt6366_set_voltage(enum mt6366_regulator_id id, u32 voltage_uv) +{ + switch (id) { + case MT6366_VCORE: + pmic_set_vcore_vol(voltage_uv); + break; + case MT6366_VDRAM1: + pmic_set_vdram1_vol(voltage_uv); + break; + case MT6366_VDDQ: + pmic_set_vddq_vol(voltage_uv); + break; + case MT6366_VMCH: + pmic_set_vmch_vol(voltage_uv); + break; + case MT6366_VMC: + pmic_set_vmc_vol(voltage_uv); + break; + case MT6366_VPROC12: + pmic_set_vproc12_vol(voltage_uv); + break; + case MT6366_VSRAM_PROC12: + pmic_set_vsram_proc12_vol(voltage_uv); + break; + case MT6366_VRF12: + /* VRF12 only provides 1.2V, so we just need to enable it */ + pmic_enable_vrf12(); + break; + case MT6366_VCN33: + pmic_set_vcn33_vol(voltage_uv); + break; + default: + printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); + break; + } +} + +u32 mt6366_get_voltage(enum mt6366_regulator_id id) +{ + switch (id) { + case MT6366_VCORE: + return pmic_get_vcore_vol(); + case MT6366_VDRAM1: + return pmic_get_vdram1_vol(); + case MT6366_VDDQ: + return pmic_get_vddq_vol(); + case MT6366_VMCH: + return pmic_get_vmch_vol(); + case MT6366_VMC: + return pmic_get_vmc_vol(); + case MT6366_VPROC12: + return pmic_get_vproc12_vol(); + case MT6366_VSRAM_PROC12: + return pmic_get_vsram_proc12_vol(); + case MT6366_VRF12: + return pmic_get_vrf12_vol(); + case MT6366_VCN33: + return pmic_get_vcn33_vol(); + default: + printk(BIOS_ERR, "%s: PMIC %d is not supported\n", __func__, id); + break; + } + return 0; +} + +void mt6366_init(void) +{ + struct stopwatch voltage_settled; + + if (pwrap_init()) + die("ERROR - Failed to initialize pmic wrap!"); + + pmic_check_hwcid(); + mt6366_set_power_hold(true); + pmic_wdt_set(); + mt6366_init_setting(); + stopwatch_init_usecs_expire(&voltage_settled, 200); + wk_sleep_voltage_by_ddr(); + wk_power_down_seq(); + mt6366_lp_setting(); + + while (!stopwatch_expired(&voltage_settled)) + /* wait for voltages to settle */; +} diff --git a/src/soc/mediatek/mt8186/mtcmos.c b/src/soc/mediatek/mt8186/mtcmos.c new file mode 100644 index 0000000000..314edd536e --- /dev/null +++ b/src/soc/mediatek/mt8186/mtcmos.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +enum { + DISP_PROT_STEP_2_MASK = 0x00000C06, + DISP_PROT_STEP_1_MASK = 0x00001800, +}; + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8186_infracfg_ao->infra_topaxi_protecten_clr, + DISP_PROT_STEP_2_MASK); + write32(&mt8186_infracfg_ao->infra_topaxi_protecten_1_clr, + DISP_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + /* No need to do protection since MT8186 doesn't have audio mtcmos. */ +} diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c new file mode 100644 index 0000000000..9fe6a5147f --- /dev/null +++ b/src/soc/mediatek/mt8186/pll.c @@ -0,0 +1,574 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.2 + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +enum mux_id { + TOP_AXI_SEL, + TOP_SCP_SEL, + TOP_MFG_SEL, + TOP_CAMTG_SEL, + TOP_CAMTG1_SEL, + TOP_CAMTG2_SEL, + TOP_CAMTG3_SEL, + TOP_CAMTG4_SEL, + TOP_CAMTG5_SEL, + TOP_CAMTG6_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_MSDC50_0_HCLK_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_AUD_ENGEN1_SEL, + TOP_AUD_ENGEN2_SEL, + TOP_DISP_PWM_SEL, + TOP_SSPM_SEL, + TOP_DXCC_SEL, + TOP_USB_TOP_SEL, + TOP_SRCK_SEL, + TOP_SPM_SEL, + TOP_I2C_SEL, + TOP_PWM_SEL, + TOP_SENINF_SEL, + TOP_SENINF1_SEL, + TOP_SENINF2_SEL, + TOP_SENINF3_SEL, + TOP_AES_MSDCFDE_SEL, + TOP_PWRAP_ULPOSC_SEL, + TOP_CAMTM_SEL, + TOP_VENC_SEL, + TOP_CAM_SEL, + TOP_IMG1_SEL, + TOP_IPE_SEL, + TOP_DPMAIF_SEL, + TOP_VDEC_SEL, + TOP_DISP_SEL, + TOP_MDP_SEL, + TOP_AUDIO_H_SEL, + TOP_UFS_SEL, + TOP_AES_FDE_SEL, + TOP_AUDIODSP_SEL, + TOP_DVFSRC_SEL, + TOP_DSI_OCC_SEL, + TOP_SPMI_MST_SEL, + TOP_SPINOR_SEL, + TOP_NNA_SEL, + TOP_NNA1_SEL, + TOP_NNA2_SEL, + TOP_SSUSB_XHCI_SEL, + TOP_SSUSB_TOP_1P_SEL, + TOP_SSUSB_XHCI_1P_SEL, + TOP_WPE_SEL, + TOP_MEM_SEL, + TOP_DPI_SEL, + TOP_U3_OCC_250M_SEL, + TOP_U3_OCC_500M_SEL, + TOP_ADSP_BUS_SEL, + TOP_NR_MUX +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ + [_id] = { \ + .reg = &mtk_topckgen->_reg, \ + .set_reg = &mtk_topckgen->_reg##_set, \ + .clr_reg = &mtk_topckgen->_reg##_clr, \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + .upd_reg = &mtk_topckgen->_upd_reg, \ + .upd_shift = _upd_shift, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 2, clk_cfg_update, 0), + MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 8, 3, clk_cfg_update, 1), + MUX_UPD(TOP_MFG_SEL, clk_cfg_0, 16, 2, clk_cfg_update, 2), + MUX_UPD(TOP_CAMTG_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3), + /* CLK_CFG_1 */ + MUX_UPD(TOP_CAMTG1_SEL, clk_cfg_1, 0, 3, clk_cfg_update, 4), + MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_1, 8, 3, clk_cfg_update, 5), + MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_1, 16, 3, clk_cfg_update, 6), + MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_1, 24, 3, clk_cfg_update, 7), + /* CLK_CFG_2 */ + MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_2, 0, 3, clk_cfg_update, 8), + MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9), + MUX_UPD(TOP_UART_SEL, clk_cfg_2, 16, 1, clk_cfg_update, 10), + MUX_UPD(TOP_SPI_SEL, clk_cfg_2, 24, 3, clk_cfg_update, 11), + /* CLK_CFG_3 */ + MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_3, 0, 2, clk_cfg_update, 12), + MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_3, 8, 3, clk_cfg_update, 13), + MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_3, 16, 3, clk_cfg_update, 14), + MUX_UPD(TOP_AUDIO_SEL, clk_cfg_3, 24, 2, clk_cfg_update, 15), + /* CLK_CFG_4 */ + MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_4, 0, 2, clk_cfg_update, 16), + MUX_UPD(TOP_AUD_1_SEL, clk_cfg_4, 8, 1, clk_cfg_update, 17), + MUX_UPD(TOP_AUD_2_SEL, clk_cfg_4, 16, 1, clk_cfg_update, 18), + MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_4, 24, 2, clk_cfg_update, 19), + /* CLK_CFG_5 */ + MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_5, 0, 2, clk_cfg_update, 20), + MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21), + MUX_UPD(TOP_SSPM_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22), + MUX_UPD(TOP_DXCC_SEL, clk_cfg_5, 24, 2, clk_cfg_update, 23), + /* CLK_CFG_6 */ + MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_6, 0, 2, clk_cfg_update, 24), + MUX_UPD(TOP_SRCK_SEL, clk_cfg_6, 8, 2, clk_cfg_update, 25), + MUX_UPD(TOP_SPM_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26), + MUX_UPD(TOP_I2C_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27), + /* CLK_CFG_7 */ + MUX_UPD(TOP_PWM_SEL, clk_cfg_7, 0, 2, clk_cfg_update, 28), + MUX_UPD(TOP_SENINF_SEL, clk_cfg_7, 8, 2, clk_cfg_update, 29), + MUX_UPD(TOP_SENINF1_SEL, clk_cfg_7, 16, 2, clk_cfg_update, 30), + MUX_UPD(TOP_SENINF2_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0), + /* CLK_CFG_8 */ + MUX_UPD(TOP_SENINF3_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1), + MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2), + MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 16, 3, clk_cfg_update1, 3), + MUX_UPD(TOP_CAMTM_SEL, clk_cfg_8, 24, 2, clk_cfg_update1, 4), + /* CLK_CFG_9 */ + MUX_UPD(TOP_VENC_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5), + MUX_UPD(TOP_CAM_SEL, clk_cfg_9, 8, 4, clk_cfg_update1, 6), + MUX_UPD(TOP_IMG1_SEL, clk_cfg_9, 16, 4, clk_cfg_update1, 7), + MUX_UPD(TOP_IPE_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 8), + /* CLK_CFG_10 */ + MUX_UPD(TOP_DPMAIF_SEL, clk_cfg_10, 0, 3, clk_cfg_update1, 9), + MUX_UPD(TOP_VDEC_SEL, clk_cfg_10, 8, 3, clk_cfg_update1, 10), + MUX_UPD(TOP_DISP_SEL, clk_cfg_10, 16, 4, clk_cfg_update1, 11), + MUX_UPD(TOP_MDP_SEL, clk_cfg_10, 24, 4, clk_cfg_update1, 12), + /* CLK_CFG_11 */ + MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_11, 0, 2, clk_cfg_update1, 13), + MUX_UPD(TOP_UFS_SEL, clk_cfg_11, 8, 2, clk_cfg_update1, 14), + MUX_UPD(TOP_AES_FDE_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15), + MUX_UPD(TOP_AUDIODSP_SEL, clk_cfg_11, 24, 3, clk_cfg_update1, 16), + /* CLK_CFG_12 */ + MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18), + MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19), + /* CLK_CFG_13 */ + MUX_UPD(TOP_SPINOR_SEL, clk_cfg_13, 0, 3, clk_cfg_update1, 20), + MUX_UPD(TOP_NNA_SEL, clk_cfg_13, 7, 4, clk_cfg_update1, 21), + MUX_UPD(TOP_NNA1_SEL, clk_cfg_13, 15, 4, clk_cfg_update1, 22), + MUX_UPD(TOP_NNA2_SEL, clk_cfg_13, 23, 4, clk_cfg_update1, 23), + /* CLK_CFG_14 */ + MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_14, 0, 2, clk_cfg_update1, 24), + MUX_UPD(TOP_SSUSB_TOP_1P_SEL, clk_cfg_14, 6, 2, clk_cfg_update1, 25), + MUX_UPD(TOP_SSUSB_XHCI_1P_SEL, clk_cfg_14, 12, 2, clk_cfg_update1, 26), + MUX_UPD(TOP_WPE_SEL, clk_cfg_14, 18, 4, clk_cfg_update1, 27), + /* CLK_CFG_15 */ + MUX_UPD(TOP_DPI_SEL, clk_cfg_15, 0, 3, clk_cfg_update1, 28), + MUX_UPD(TOP_U3_OCC_250M_SEL, clk_cfg_15, 7, 1, clk_cfg_update1, 29), + MUX_UPD(TOP_U3_OCC_500M_SEL, clk_cfg_15, 12, 1, clk_cfg_update1, 30), + MUX_UPD(TOP_ADSP_BUS_SEL, clk_cfg_15, 17, 3, clk_cfg_update1, 31), +}; + +struct mux_sel { + enum mux_id id; + u32 sel; +}; + +static const struct mux_sel mux_sels[] = { + /* CLK_CFG_0 */ + { .id = TOP_AXI_SEL, .sel = 1 }, /* 1: mainpll_d7 */ + { .id = TOP_SCP_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */ + { .id = TOP_MFG_SEL, .sel = 1 }, /* 1: mfgpll_ck */ + { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + /* CLK_CFG_1 */ + { .id = TOP_CAMTG1_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG4_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + /* CLK_CFG_2 */ + { .id = TOP_CAMTG5_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_CAMTG6_SEL, .sel = 2 }, /* 2: univpll_d3_d8 */ + { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_SPI_SEL, .sel = 7 }, /* 7: mainpll_d5 */ + /* CLK_CFG_3 */ + { .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ + { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: msdcpll_d2 */ + { .id = TOP_AUDIO_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */ + /* CLK_CFG_4 */ + { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d2_d4 */ + { .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */ + { .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */ + { .id = TOP_AUD_ENGEN1_SEL, .sel = 3 }, /* 3: apll1_d8 */ + /* CLK_CFG_5 */ + { .id = TOP_AUD_ENGEN2_SEL, .sel = 3 }, /* 3: apll2_d8 */ + { .id = TOP_DISP_PWM_SEL, .sel = 1 }, /* 1: univpll_d5_d2 */ + { .id = TOP_SSPM_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + { .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d2_d2 */ + /* CLK_CFG_6 */ + { .id = TOP_USB_TOP_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SRCK_SEL, .sel = 2 }, /* 2: ulposc1_d10 */ + { .id = TOP_SPM_SEL, .sel = 3 }, /* 3: mainpll_d7_d2 */ + { .id = TOP_I2C_SEL, .sel = 3 }, /* 3: univpll_d5_d2 */ + /* CLK_CFG_7 */ + { .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d2_d4 */ + { .id = TOP_SENINF_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_SENINF1_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_SENINF2_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + /* CLK_CFG_8 */ + { .id = TOP_SENINF3_SEL, .sel = 3 }, /* 3: univpll_d3_d2 */ + { .id = TOP_AES_MSDCFDE_SEL, .sel = 1 }, /* 1: univpll_d3 */ + { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: clk26m */ + { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d3_d2 */ + /* CLK_CFG_9 */ + { .id = TOP_VENC_SEL, .sel = 6 }, /* 6: mainpll_d3 */ + { .id = TOP_CAM_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + { .id = TOP_IMG1_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + { .id = TOP_IPE_SEL, .sel = 7 }, /* 7: univpll_d2_d2 */ + /* CLK_CFG_10 */ + { .id = TOP_DPMAIF_SEL, .sel = 1 }, /* 1: univpll_d2_d2 */ + { .id = TOP_VDEC_SEL, .sel = 6 }, /* 6: univpll_d2_d2 */ + { .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mmpll_ck */ + { .id = TOP_MDP_SEL, .sel = 8 }, /* 8: mmpll_ck */ + /* CLK_CFG_11 */ + { .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */ + { .id = TOP_UFS_SEL, .sel = 1 }, /* 1: mainpll_d7 */ + { .id = TOP_AES_FDE_SEL, .sel = 1 }, /* 1: univpll_d3 */ + { .id = TOP_AUDIODSP_SEL, .sel = 0 }, /* 0: clk26m */ + /* CLK_CFG_12 */ + { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */ + { .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */ + /* CLK_CFG_13 */ + { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */ + { .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */ + { .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */ + { .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */ + /* CLK_CFG_14 */ + { .id = TOP_SSUSB_XHCI_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SSUSB_TOP_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_SSUSB_XHCI_1P_SEL, .sel = 2 }, /* 2: univpll_d5_d2 */ + { .id = TOP_WPE_SEL, .sel = 8 }, /* 8: mmpll_ck */ + /* CLK_CFG_15 */ + { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_ck */ + { .id = TOP_U3_OCC_250M_SEL, .sel = 1 }, /* 1: univpll_d5 */ + { .id = TOP_U3_OCC_500M_SEL, .sel = 1 }, /* 1: nna2pll_d2 */ + { .id = TOP_ADSP_BUS_SEL, .sel = 3 }, /* 3: mainpll_d2_d2 */ +}; + +enum pll_id { + APMIXED_ARMPLL_LL, + APMIXED_ARMPLL_BL, + APMIXED_CCIPLL, + APMIXED_MAINPLL, + APMIXED_UNIV2PLL, + APMIXED_MSDCPLL, + APMIXED_MMPLL, + APMIXED_NNAPLL, + APMIXED_NNA2PLL, + APMIXED_ADSPPLL, + APMIXED_MFGPLL, + APMIXED_TVDPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_PLL_MAX +}; + +static const u32 pll_div_rate[] = { + 3800UL * MHz, + 1900 * MHz, + 950 * MHz, + 475 * MHz, + 237500 * KHz, + 0, +}; + +static const struct pll plls[] = { + PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, + NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3, + NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, + pll_div_rate), + PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, + NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, + 23, 22, mainpll_con1, 24, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIV2PLL, univpll_con0, univpll_con3, + 23, 22, univpll_con1, 24, univpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, + NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, + NO_RSTB_SHIFT, 22, mmpll_con1, 24, mmpll_con1, 0, + pll_div_rate), + PLL(APMIXED_NNAPLL, nnapll_con0, nnapll_con3, + NO_RSTB_SHIFT, 22, nnapll_con1, 24, nnapll_con1, 0, + pll_div_rate), + PLL(APMIXED_NNA2PLL, nna2pll_con0, nna2pll_con3, + NO_RSTB_SHIFT, 22, nna2pll_con1, 24, nna2pll_con1, 0, + pll_div_rate), + PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, + NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, + pll_div_rate), + PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, + NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3, + NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_con4, + NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_con4, + NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, + pll_div_rate), +}; + +struct rate { + enum pll_id id; + u32 rate; +}; + +static const struct rate rates[] = { + { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, + { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, + { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, + { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, + { .id = APMIXED_UNIV2PLL, .rate = UNIV2PLL_HZ }, + { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, + { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, + { .id = APMIXED_NNAPLL, .rate = NNAPLL_HZ }, + { .id = APMIXED_NNA2PLL, .rate = NNA2PLL_HZ }, + { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, + { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, + { .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ }, + { .id = APMIXED_APLL1, .rate = APLL1_HZ }, + { .id = APMIXED_APLL2, .rate = APLL2_HZ }, +}; + +void pll_set_pcw_change(const struct pll *pll) +{ + setbits32(pll->div_reg, PLL_PCW_CHG); +} + +void mt_pll_init(void) +{ + int i; + + /* enable clock square */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(0)); + + udelay(PLL_CKSQ_ON_DELAY); + + /* enable clock square1 low-pass filter */ + setbits32(&mtk_apmixed->ap_pll_con0, BIT(1)); + + /* xPLL PWR ON */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(PLL_PWR_ON_DELAY); + + /* xPLL ISO Disable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + clrbits32(plls[i].pwr_reg, PLL_ISO); + + udelay(PLL_ISO_DELAY); + + /* disable glitch free if rate < 374MHz */ + for (i = 0; i < ARRAY_SIZE(rates); i++) { + if (rates[i].rate < 374 * MHz) + clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN); + } + + /* xPLL Frequency Set */ + for (i = 0; i < ARRAY_SIZE(rates); i++) + pll_set_rate(&plls[rates[i].id], rates[i].rate); + + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + + /* xPLL Frequency Enable */ + for (i = 0; i < APMIXED_PLL_MAX; i++) + setbits32(plls[i].reg, MT8186_PLL_EN); + + /* wait for PLL stable */ + udelay(PLL_EN_DELAY); + + /* xPLL DIV Enable & RSTB */ + for (i = 0; i < APMIXED_PLL_MAX; i++) { + if (plls[i].rstb_shift != NO_RSTB_SHIFT) { + setbits32(plls[i].reg, PLL_DIV_EN); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); + } + } + + /* MCUCFG CLKMUX */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL1_EN); + setbits32(&mtk_topckgen->clk_misc_cfg_0, ARMPLL_DIVIDER_PLL2_EN); + + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + + write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603); + write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603); + + /* dcm_infracfg_ao_audio_bus and dcm_infracfg_ao_icusb_bus */ + SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_AUDIO_BUS_REG0, 0, + INFRACFG_AO_ICUSB_BUS_REG0, 0, + INFRACFG_AO_AUDIO_BUS_REG0, 1, + INFRACFG_AO_ICUSB_BUS_REG0, 1); + + /* dcm_infracfg_ao_infra_bus */ + SET32_BITFIELDS(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_REG0_0, 0, + INFRACFG_AO_INFRA_BUS_REG0_1, 0, + INFRACFG_AO_INFRA_BUS_REG0_2, 0, + INFRACFG_AO_INFRA_BUS_REG0_0, 0x603, + INFRACFG_AO_INFRA_BUS_REG0_1, 0xF, + INFRACFG_AO_INFRA_BUS_REG0_2, 1); + + /* dcm_infracfg_ao_p2p_rx_clk */ + SET32_BITFIELDS(&mt8186_infracfg_ao->p2p_rx_clk_on, + INFRACFG_AO_P2P_RX_CLK_REG0_MASK_0, 0, + INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 0, + INFRACFG_AO_P2P_RX_CLK_REG0_MASK_1, 1); + + /* dcm_infracfg_ao_peri_bus */ + SET32_BITFIELDS(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_REG0_0, 0, + INFRACFG_AO_PERI_BUS_REG0_1, 0, + INFRACFG_AO_PERI_BUS_REG0_2, 0, + INFRACFG_AO_PERI_BUS_REG0_0, 3, + INFRACFG_AO_PERI_BUS_REG0_1, 0xFF07C, + INFRACFG_AO_PERI_BUS_REG0_2, 1); + + for (i = 0; i < ARRAY_SIZE(mux_sels); i++) + mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + + /* [4] SCP_CORE_CK_CG, [5] SEJ_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030); + /* [7] DVFSRC_CG, [20] DEVICE_APC_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_1_clr, 0x00100080); + /* [15] SEJ_F13M_CK_CG, [16] AES_TOP0_BCLK_CK_CG */ + write32(&mt8186_infracfg_ao->module_sw_cg_3_clr, 0x00018000); +} + +void mt_pll_raise_little_cpu_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable armpll_ll frequency output */ + clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); + + /* raise armpll_ll frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); + + /* enable armpll_ll frequency output */ + setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8186_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to armpll_ll */ + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +void mt_pll_raise_cci_freq(u32 freq) +{ + /* switch clock source to intermediate clock */ + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + + /* disable ccipll frequency output */ + clrbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); + + /* raise ccipll frequency */ + pll_set_rate(&plls[APMIXED_CCIPLL], freq); + + /* enable ccipll frequency output */ + setbits32(plls[APMIXED_CCIPLL].reg, MT8186_PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch clock source back to ccipll */ + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); +} + +u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) +{ + u32 output, count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1; + + /* backup */ + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + clk26cali_0 = read32(&mtk_topckgen->clk26cali_0); + clk26cali_1 = read32(&mtk_topckgen->clk26cali_1); + + /* set up frequency meter */ + if (type == FMETER_ABIST) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, id, + CLK_DBG_CFG_CKGEN_CK_SEL, 0, + CLK_DBG_CFG_METER_CK_SEL, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 1); + } else if (type == FMETER_CKGEN) { + SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, + CLK_DBG_CFG_ABIST_CK_SEL, 0, + CLK_DBG_CFG_CKGEN_CK_SEL, id, + CLK_DBG_CFG_METER_CK_SEL, 1); + SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, + CLK_MISC_CFG_0_METER_DIV, 0); + } else { + die("unsupport fmeter type\n"); + } + + /* enable frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_ENABLE, 1); + + /* trigger frequency meter */ + SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); + + /* wait frequency meter until finished */ + if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { + count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; + output = (count * 26000) / 1024; /* KHz */ + } else { + output = 0; + } + + /* restore */ + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + write32(&mtk_topckgen->clk26cali_0, clk26cali_0); + write32(&mtk_topckgen->clk26cali_1, clk26cali_1); + + if (type == FMETER_ABIST) + return output * 2; + else if (type == FMETER_CKGEN) + return output; + + return 0; +} diff --git a/src/soc/mediatek/mt8186/pmic_wrap.c b/src/soc/mediatek/mt8186/pmic_wrap.c new file mode 100644 index 0000000000..62cb72dc94 --- /dev/null +++ b/src/soc/mediatek/mt8186/pmic_wrap.c @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.7 + */ + +#include +#include +#include +#include +#include + +#define PRIORITY_FIELD(x) ((x % 4) * 8) +#define PRIORITY_IN(id, priority) (id << PRIORITY_FIELD(priority)) +#define PRIORITY_OUT(id, priority) (priority << PRIORITY_FIELD(id)) + +enum { + MD_ADCINF0 = 8, + MD_ADCINF1 = 9, + STAUPD = 10, + GPSINF0 = 11, + + PRIORITY_IN_SEL_2 = PRIORITY_IN(MD_ADCINF0, 9) | + PRIORITY_IN(MD_ADCINF1, 10) | + PRIORITY_IN(STAUPD, 8) | + PRIORITY_IN(GPSINF0, 11), + + PRIORITY_OUT_SEL_2 = PRIORITY_OUT(MD_ADCINF0, 9) | + PRIORITY_OUT(MD_ADCINF1, 10) | + PRIORITY_OUT(STAUPD, 8) | + PRIORITY_OUT(GPSINF0, 11), +}; + +#define PENDING_US(x) x +enum { + STARVE_ENABLE = 0x1 << 10, + COUNTER0_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x2), + COUNTER1_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER2_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER3_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x3), + COUNTER4_PENDING_THRES = STARVE_ENABLE | PENDING_US(0xf), + COUNTER5_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x20), + COUNTER6_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x28), + COUNTER7_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x28), + COUNTER8_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x13), + COUNTER9_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x17), + COUNTER10_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x17), + COUNTER11_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x7c), + COUNTER12_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x7c), + COUNTER13_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), + COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340), +}; + +static void pwrap_soft_reset(void) +{ + write32(&mt8186_infracfg_ao->infra_globalcon_rst2_set, 0x1); + write32(&mt8186_infracfg_ao->infra_globalcon_rst2_clr, 0x1); +} + +static void pwrap_spi_clk_set(void) +{ + write32(&mt8186_infracfg_ao->module_sw_cg_0_set, 0x0000000f); + write32(&mt8186_infracfg_ao->module_sw_cg_2_set, 0x00000100); + + write32(&mtk_topckgen->clk_cfg_8_clr, 0x00970000); + write32(&mtk_topckgen->clk_cfg_8_set, 0x00040000); + write32(&mtk_topckgen->clk_cfg_update1, (0x1 << 3)); + + write32(&mt8186_infracfg_ao->pmicw_clock_ctrl, + read32(&mt8186_infracfg_ao->pmicw_clock_ctrl) & ~(0x1 << 2)); + + pwrap_soft_reset(); + + write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x0000000f); + write32(&mt8186_infracfg_ao->module_sw_cg_2_clr, 0x00000100); +} + +static s32 pwrap_init_dio(u16 dio_en) +{ + pwrap_write_nochk(PMIC_DEW_DIO_EN, dio_en); + + if (!wait_us(100, + !wait_for_idle_and_sync(read32(&mtk_pwrap->wacs2_rdata)))) + return -1; + + write32(&mtk_pwrap->dio_en, dio_en); + return 0; +} + +static void pwrap_lock_spislvreg(void) +{ + pwrap_write_nochk(PMIC_SPISLV_KEY, 0x0); +} + +static void pwrap_initstaupd(void) +{ + write32(&mtk_pwrap->staupd_grpen, + SIG_PMIC_0 | INT_STA_PMIC_0 | MD_ADC_DATA0 | + MD_ADC_DATA1 | GPS_ADC_DATA0 | GPS_ADC_DATA1); + + /* CRC */ + pwrap_write_nochk(PMIC_DEW_CRC_EN, 0x1); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_adr, PMIC_DEW_CRC_VAL); + + write32(&mtk_pwrap->eint_sta0_adr, PMIC_CPU_INT_STA); + + /* MD ADC Interface */ + write32(&mtk_pwrap->md_auxadc_rdata_latest_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + write32(&mtk_pwrap->md_auxadc_rdata_wp_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + for (size_t i = 0; i < 32; i++) + write32(&mtk_pwrap->md_auxadc_rdata[i], + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + + write32(&mtk_pwrap->int_gps_auxadc_cmd_addr, + (PMIC_AUXADC_RQST1 << 16) + PMIC_AUXADC_RQST0); + write32(&mtk_pwrap->int_gps_auxadc_cmd, (GPS_MAIN << 16) + GPS_SUBSYS); + write32(&mtk_pwrap->int_gps_auxadc_rdata_addr, + (PMIC_AUXADC_ADC32 << 16) + PMIC_AUXADC_ADC17); + + write32(&mtk_pwrap->ext_gps_auxadc_rdata_addr, PMIC_AUXADC_ADC31); +} + +static void pwrap_starve_set(void) +{ + write32(&mtk_pwrap->harb_hprio, ARB_PRIORITY); + write32(&mtk_pwrap->starv_counter_0, COUNTER0_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_1, COUNTER1_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_2, COUNTER2_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_3, COUNTER3_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_4, COUNTER4_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_5, COUNTER5_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_6, COUNTER6_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_7, COUNTER7_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_8, COUNTER8_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_9, COUNTER9_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_10, COUNTER10_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_11, COUNTER11_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_12, COUNTER12_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_13, COUNTER13_PENDING_THRES); + write32(&mtk_pwrap->starv_counter_16, COUNTER16_PENDING_THRES); +} + +static void pwrap_enable(void) +{ + write32(&mtk_pwrap->hiprio_arb_en, ARB_USER_EN); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->wacs_p2p_en, 0x1); + write32(&mtk_pwrap->wacs_md32_en, 0x1); + write32(&mtk_pwrap->staupd_ctrl, STA_PD_98_5_US); + write32(&mtk_pwrap->wdt_ctrl, WATCHDOG_TIMER_7_5_MS); + write32(&mtk_pwrap->wdt_src_en_0, WDT_MONITOR_ALL); + write32(&mtk_pwrap->wdt_src_en_1, WDT_MONITOR_ALL); + write32(&mtk_pwrap->timer_ctrl, 0x1); + write32(&mtk_pwrap->int0_en, INT0_MONITOR); + write32(&mtk_pwrap->int1_en, INT1_MONITOR); +} + +static s32 pwrap_init_sistrobe(void) +{ + u16 rdata; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pwrap->si_sample_ctrl, si_sample_ctrl << 5); + + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + /* + * Add the delay time of SPI data from PMIC to align the start boundary + * to current sampling clock edge. + */ + for (int si_dly = 0; si_dly < 10; si_dly++) { + pwrap_write_nochk(PMIC_RG_SPI_CON2, si_dly); + + int start_boundary_found = 0; + for (size_t i = 0; i < 30; i++) { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, test_data[i]); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + start_boundary_found = 1; + break; + } + } + if (start_boundary_found == 1) + break; + } + + /* + * Change the sampling clock edge to the next one which is the middle + * of SPI data window. + */ + write32(&mtk_pwrap->si_sample_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("rdata = %#x, exp = %#x\n", rdata, + DEFAULT_VALUE_READ_TEST); + return E_PWR_READ_TEST_FAIL; + } + + return 0; +} + +static void pwrap_init_spislv(void) +{ + /* Turn on IO filter function */ + pwrap_write_nochk(PMIC_FILTER_CON0, SPI_FILTER); + /* Turn on IO SMT function to improve noise immunity */ + pwrap_write_nochk(PMIC_SMT_CON1, SPI_SMT); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + /* Enable SPI R/W in suspend mode */ + pwrap_write_nochk(PMIC_RG_SPI_CON0, 0x1); + /* Set PMIC GPIO driving current to 4mA */ + pwrap_write_nochk(PMIC_DRV_CON1, SPI_DRIVING); +} + +static void pwrap_init_reg_clock(void) +{ + write32(&mtk_pwrap->ext_ck_write, 0x1); + + pwrap_write_nochk(PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + write32(&mtk_pwrap->rddmy, DUMMY_READ_CYCLES); + + write32(&mtk_pwrap->cshext_write, 0); + write32(&mtk_pwrap->cshext_read, 0); + write32(&mtk_pwrap->cslext_write, 0); + write32(&mtk_pwrap->cslext_read, 0); +} + +s32 pwrap_init(void) +{ + s32 sub_return = 0, sub_return1 = 0; + u16 rdata; + + pwrap_spi_clk_set(); + + /* Reset spislv */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("reset_spislv fail, ret=%d\n", sub_return); + return E_PWR_INIT_RESET_SPI; + } + + /* Enable WRAP */ + write32(&mtk_pwrap->wrap_en, 0x1); + + /* Enable WACS2 */ + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); /* ONLY WACS2 */ + + /* SPI Waveform Configuration */ + pwrap_init_reg_clock(); + + /* SPI Slave Configuration */ + pwrap_init_spislv(); + + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("dio test error, ret=%d\n", sub_return); + return E_PWR_INIT_DIO; + } + + /* Input data calibration flow; */ + sub_return = pwrap_init_sistrobe(); + if (sub_return != 0) { + pwrap_err("InitSiStrobe fail,ret=%d\n", sub_return); + return E_PWR_INIT_SIDLY; + } + + /* + * Write test using WACS2, + * make sure the read/write function ready. + */ + sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST, WRITE_TEST_VALUE); + sub_return1 = pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if (rdata != WRITE_TEST_VALUE || sub_return || sub_return1) { + pwrap_err("write error, rdata=%#x, return=%d, return1=%d\n", + rdata, sub_return, sub_return1); + return E_PWR_INIT_WRITE_TEST; + } + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + pwrap_initstaupd(); + + write32(&mtk_pwrap->priority_user_sel_2, PRIORITY_IN_SEL_2); + write32(&mtk_pwrap->arbiter_out_sel_2, PRIORITY_OUT_SEL_2); + + pwrap_starve_set(); + + pwrap_enable(); + + /* Initialization Done */ + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done_p2p, 0x1); + write32(&mtk_pwrap->init_done_md32, 0x1); + + /* Lock SPISLV Registers */ + pwrap_lock_spislvreg(); + + return 0; +} diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c new file mode 100644 index 0000000000..7e38742ca2 --- /dev/null +++ b/src/soc/mediatek/mt8186/rtc.c @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +/* Initialize RTC setting of using DCXO clock */ +static bool rtc_enable_dcxo(void) +{ + u16 bbpu, con, osc32con, sec; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + mdelay(1); + if (!rtc_writeif_unlock()) { + rtc_info("rtc_writeif_unlock() failed\n"); + return false; + } + + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK + | RTC_GPS_CKOUT_EN); + osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB + | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; + if (!rtc_xosc_write(osc32con)) { + rtc_info("rtc_xosc_write() failed\n"); + return false; + } + + rtc_read(RTC_CON, &con); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_read(RTC_AL_SEC, &sec); + rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec); + + return true; +} + +/* Initialize RTC related gpio */ +bool rtc_gpio_init(void) +{ + u16 con; + + /* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */ + pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3); + + /* Export 32K clock RTC_32K1V8_1 */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1); + + /* Export 32K clock RTC_32K2V8 */ + rtc_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~RTC_CON_F32KOB; + rtc_write(RTC_CON, con); + + return rtc_write_trigger(); +} + +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + struct stopwatch sw; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + rtc_read(RTC_OSC32CON, &osc32con); + if (!rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK))) { + rtc_info("rtc_xosc_write() failed\n"); + return false; + } + + /* Enable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + /* FQMTR reset */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + do { + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + /* FQMTR normal */ + pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + + /* Set frequency meter window value (0=1X32K(fixed clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* Enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* Enable 26M -> delay 100us -> enable FQMTR */ + udelay(100); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* Enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + udelay(100); + + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + if (!wait_us(FQMTR_TIMEOUT_US, + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 && + !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) { + rtc_info("get frequency time out: %#x\n", fqmtr_busy); + return false; + } + + /* Read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* Disable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* Disable FQMTR -> delay 100us -> disable 26M */ + udelay(100); + /* Disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, + fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input = %#x, output = %#x\n", val, fqmtr_data); + + /* Disable FQMTR clock */ + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + + return fqmtr_data; +} + +/* Low power detect setting */ +static bool rtc_lpd_init(void) +{ + u16 con, sec; + + /* Set RTC_LPD_OPT */ + rtc_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + rtc_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + /* Initialize XOSC32 to detect 32k clock stop */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; + if (!rtc_lpen(con)) + return false; + + /* Initialize EOSC32 to detect RTC low power */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; + if (!rtc_lpen(con)) + return false; + + rtc_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + rtc_write(RTC_CON, con); + + /* Set RTC_LPD_OPT */ + rtc_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + rtc_write(RTC_AL_SEC, sec); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + return true; +} + +static bool rtc_hw_init(void) +{ + u16 bbpu; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + udelay(500); + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + if (!rtc_write_trigger()) { + rtc_info("rtc_write_trigger() failed\n"); + return false; + } + + rtc_read(RTC_BBPU, &bbpu); + if (bbpu & RTC_BBPU_INIT) { + rtc_info("timeout\n"); + return false; + } + + return true; +} + +static void mt6366_dcxo_disable_unused(void) +{ + /* Disable clock buffer XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); +} + +/* Check RTC Initialization */ +int rtc_init(int recover) +{ + int ret; + + rtc_info("recovery: %d\n", recover); + + /* Write powerkeys to enable RTC functions */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + /* Write interface unlock need to be set after powerkey match */ + if (!rtc_writeif_unlock()) { + ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL; + goto err; + } + + rtc_osc_init(); + + /* In recovery mode, we need 20ms delay for register setting. */ + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) { + ret = -RTC_STATUS_GPIO_INIT_FAIL; + goto err; + } + + if (!rtc_hw_init()) { + ret = -RTC_STATUS_HW_INIT_FAIL; + goto err; + } + + if (!rtc_reg_init()) { + ret = -RTC_STATUS_REG_INIT_FAIL; + goto err; + } + + if (!rtc_lpd_init()) { + ret = -RTC_STATUS_LPD_INIT_FAIL; + goto err; + } + + /* + * After lpd init, powerkeys need to be written again to enable + * low power detect function. + */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + return RTC_STATUS_OK; +err: + rtc_info("init failed: ret = %d\n", ret); + return ret; +} + +/* Enable RTC bbpu */ +void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* Pull powerhold high, control by pmic */ + mt6366_set_power_hold(true); + + /* Pull PWRBB high */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN; + rtc_write(RTC_BBPU, bbpu); + ret = rtc_write_trigger(); + rtc_info("rtc_write_trigger = %d\n", ret); + + rtc_read(RTC_BBPU, &bbpu); + rtc_info("done BBPU = %#x\n", bbpu); +} + +static void dcxo_init(void) +{ + /* Buffer setting */ + rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA); + rtc_write(PMIC_RG_DCXO_CW13, 0x98E9); + rtc_write(PMIC_RG_DCXO_CW16, 0x9855); + + /* 26M enable control */ + /* Enable clock buffer XO_SOC, XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + + /* Load thermal coefficient */ + rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); + rtc_write(PMIC_RG_DCXO_CW21, 0x12A7); + rtc_write(PMIC_RG_DCXO_ELR0, 0xD004); + rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000); + + /* Adjust OSC FPM setting */ + rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE); + + /* Re-calibrate OSC current */ + rtc_write(PMIC_RG_DCXO_CW09, 0x008F); + udelay(100); + rtc_write(PMIC_RG_DCXO_CW09, 0x408F); + mdelay(5); + + mt6366_dcxo_disable_unused(); +} + +/* Initialize rtc boot flow */ +void rtc_boot(void) +{ + /* DCXO clock initialized settings */ + dcxo_init(); + + /* DCXO 32k initialized settings */ + pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); + pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + + /* Use DCXO 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() failed\n"); + + rtc_boot_common(); + rtc_bbpu_power_on(); +} diff --git a/src/soc/mediatek/mt8186/soc.c b/src/soc/mediatek/mt8186/soc.c new file mode 100644 index 0000000000..7686986e71 --- /dev/null +++ b/src/soc/mediatek/mt8186/soc.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void bootmem_platform_add_ranges(void) +{ + if (CONFIG(MTK_DFD)) + bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED); +} + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ + mtk_mmu_disable_l2c_sram(); + sspm_init(); + dapc_init(); + + if (CONFIG(MTK_DFD)) + dfd_init(); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8186_ops = { + CHIP_NAME("SOC Mediatek MT8186") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c new file mode 100644 index 0000000000..d4d3684d32 --- /dev/null +++ b/src/soc/mediatek/mt8186/spi.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.6, 5.8 + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(SPI3_CSB), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT11), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + } +}; + +struct pad_func { + gpio_t gpio; + u8 func; + enum pull_select select; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func, GPIO_PULL_DOWN} +#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0, GPIO_PULL_DOWN} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_MI_A), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_MO_A), + PAD_FUNC(SPI0_CLK, SPI0_CLK_A), + }, + { + PAD_FUNC(SPI1_MI, SPI1_MI_A), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_MO_A), + PAD_FUNC(SPI1_CLK, SPI1_CLK_A), + }, + { + PAD_FUNC(SPI2_MI, SPI2_MI_A), + PAD_FUNC_GPIO(SPI2_CSB), + PAD_FUNC(SPI2_MO, SPI2_MO_A), + PAD_FUNC(SPI2_CK, SPI2_CLK_A), + }, + { + PAD_FUNC(SPI3_MI, SPI3_MI), + PAD_FUNC_GPIO(SPI3_CSB), + PAD_FUNC(SPI3_MO, SPI3_MO), + PAD_FUNC(SPI3_CLK, SPI3_CLK), + }, + { + PAD_FUNC(EINT13, SPI4_MI_A), + PAD_FUNC_GPIO(EINT11), + PAD_FUNC(EINT12, SPI4_MO_A), + PAD_FUNC(EINT10, SPI4_CLK_A), + }, + { + PAD_FUNC(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_MO), + PAD_FUNC(SPI5_CLK, SPI5_CLK), + }, +}; + +static const struct pad_func pad1_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(EINT3, SPI0_MI_B), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT2, SPI0_MO_B), + PAD_FUNC(EINT0, SPI0_CLK_B), + }, + { + PAD_FUNC(EINT9, SPI1_MI_B), + PAD_FUNC_GPIO(EINT7), + PAD_FUNC(EINT8, SPI1_MO_B), + PAD_FUNC(EINT6, SPI1_CLK_B), + }, + { + PAD_FUNC(CAM_PDN1, SPI2_MI_B), + PAD_FUNC_GPIO(CAM_PDN0), + PAD_FUNC(CAM_RST0, SPI2_MO_B), + PAD_FUNC(EINT18, SPI2_CLK_B), + }, + { + }, + { + PAD_FUNC(I2S2_DI, SPI4_MI_B), + PAD_FUNC_GPIO(I2S2_BCK), + PAD_FUNC(I2S2_LRCK, SPI4_MO_B), + PAD_FUNC(I2S2_MCK, SPI4_CLK_B), + }, + { + }, +}; + +static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { + /* GPIO 36 ~ 39 */ + [SPI_NOR_GPIO_SET0] = { + PAD_FUNC_SEL(SPI0_CLK, SPINOR_CK, GPIO_PULL_DOWN), + PAD_FUNC_SEL(SPI0_CSB, SPINOR_CS, GPIO_PULL_UP), + PAD_FUNC_SEL(SPI0_MO, SPINOR_IO0, GPIO_PULL_DOWN), + PAD_FUNC_SEL(SPI0_MI, SPINOR_IO1, GPIO_PULL_DOWN), + }, + /* GPIO 61 ~ 64 */ + [SPI_NOR_GPIO_SET1] = { + PAD_FUNC_SEL(TDM_RX_BCK, SPINOR_CK, GPIO_PULL_DOWN), + PAD_FUNC_SEL(TDM_RX_MCLK, SPINOR_CS, GPIO_PULL_UP), + PAD_FUNC_SEL(TDM_RX_DATA0, SPINOR_IO0, GPIO_PULL_DOWN), + PAD_FUNC_SEL(TDM_RX_DATA1, SPINOR_IO1, GPIO_PULL_DOWN), + }, +}; + +void mtk_snfc_init(int gpio_set) +{ + const struct pad_func *ptr = NULL; + + assert(gpio_set < SPI_NOR_GPIO_SET_NUM); + + ptr = nor_pinmux[gpio_set]; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) { + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select); + gpio_set_mode(ptr[i].gpio, ptr[i].func); + } +} + +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + if (pad_select == SPI_PAD0_MASK) { + ptr = pad0_funcs[bus]; + } else { + assert((bus == 0 || bus == 1 || bus == 2 || bus == 4) && + pad_select == SPI_PAD1_MASK); + ptr = pad1_funcs[bus]; + } + for (int i = 0; i < 4; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { + .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c new file mode 100644 index 0000000000..a1186ca477 --- /dev/null +++ b/src/soc/mediatek/mt8186/spm.c @@ -0,0 +1,684 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.5 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + +static const struct pwr_ctrl spm_init_ctrl = { + /* For SPM, this flag is not auto-gen. */ + .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | + SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_RUN_COMMON_SCENARIO, + + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_ccif_event_infra_req_mask_b = 0xFFFF, + .reg_ccif_event_apsrc_req_mask_b = 0xFFFF, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddren_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_0_srcclkena_mask_b = 1, + .reg_md_0_infra_req_mask_b = 1, + .reg_md_0_apsrc_req_mask_b = 1, + .reg_md_0_vrf18_req_mask_b = 1, + .reg_md_0_ddren_req_mask_b = 1, + .reg_md_1_srcclkena_mask_b = 0, + .reg_md_1_infra_req_mask_b = 0, + .reg_md_1_apsrc_req_mask_b = 0, + .reg_md_1_vrf18_req_mask_b = 0, + .reg_md_1_ddren_req_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni_srcclkena_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 0, + .reg_apu_infra_req_mask_b = 0, + .reg_apu_apsrc_req_mask_b = 0, + .reg_apu_vrf18_req_mask_b = 0, + .reg_apu_ddren_req_mask_b = 0, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddren_req_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_wakeup_mask_b = 0, + .reg_adsp2spm_wakeup_mask_b = 0, + .reg_sspm2spm_wakeup_mask_b = 0, + .reg_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrup_ack_mask = 1, + .reg_spm_reserved_srcclkena_mask_b = 0, + .reg_spm_reserved_infra_req_mask_b = 0, + .reg_spm_reserved_apsrc_req_mask_b = 0, + .reg_spm_reserved_vrf18_req_mask_b = 0, + .reg_spm_reserved_ddren_req_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddren_req_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddren_req_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddren_req_mask_b = 1, + + /* SPM_SRC4_MASK */ + .reg_ccif_event_srcclkena_mask_b = 0x3FF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddren_req_mask_b = 0, + .reg_dramc_md32_infra_req_mask_b = 1, + .reg_dramc_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc_md32_apsrc_req_mask_b = 0, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x14, + .reg_mcusys_merge_ddren_req_mask_b = 0x14, + .reg_afe_srcclkena_mask_b = 0, + .reg_afe_infra_req_mask_b = 0, + .reg_afe_apsrc_req_mask_b = 0, + .reg_afe_vrf18_req_mask_b = 0, + .reg_afe_ddren_req_mask_b = 0, + .reg_msdc2_srcclkena_mask_b = 0, + .reg_msdc2_infra_req_mask_b = 0, + .reg_msdc2_apsrc_req_mask_b = 0, + .reg_msdc2_vrf18_req_mask_b = 0, + .reg_msdc2_ddren_req_mask_b = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* SPM_SRC7_MASK */ + .reg_pcie_srcclkena_mask_b = 0, + .reg_pcie_infra_req_mask_b = 0, + .reg_pcie_apsrc_req_mask_b = 0, + .reg_pcie_vrf18_req_mask_b = 0, + .reg_pcie_ddren_req_mask_b = 0, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + + /* Auto-gen End */ +}; + +static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + write32(&mtk_spm->spm_ap_standby_con, + ((pwrctrl->reg_wfi_op & 0x1) << 0) | + ((pwrctrl->reg_wfi_type & 0x1) << 1) | + ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | + ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); + + /* SPM_SRC6_MASK */ + write32(&mtk_spm->spm_src6_mask, + ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16)); + + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); + + /* SPM_SRC_MASK */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) | + ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) | + ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC2_MASK */ + write32(&mtk_spm->spm_src2_mask, + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC3_MASK */ + write32(&mtk_spm->spm_src3_mask, + ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | + ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) | + ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) | + ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) | + ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) | + ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) | + ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC4_MASK */ + write32(&mtk_spm->spm_src4_mask, + ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | + ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) | + ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) | + ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | + ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26)); + + /* SPM_SRC5_MASK */ + write32(&mtk_spm->spm_src5_mask, + ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | + ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) | + ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) | + ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_SRC7_MASK */ + write32(&mtk_spm->spm_src7_mask, + ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9)); + /* Auto-gen End */ +} + +static void spm_hw_s1_state_monitor(int en) +{ + if (en) + SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3, + SPM_ACK_CHK_3_CON_CLR_ALL, 0, + SPM_ACK_CHK_3_CON_EN_0, 1, + SPM_ACK_CHK_3_CON_EN_1, 1); + else + SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 1, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 1, + SPM_ACK_CHK_3_CON_CLR_ALL, 1, + SPM_ACK_CHK_3_CON_EN_0, 0, + SPM_ACK_CHK_3_CON_EN_1, 0); +} + +static void spm_register_init(void) +{ + /* Enable register control */ + write32(&mtk_spm->poweron_config_set, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* Init power control register */ + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | + REG_MD32_APB_INTERNAL_EN_LSB); + + /* Initial SPM CLK control register */ + SET32_BITFIELDS(&mtk_spm->spm_clk_con, + REG_SYSCLK1_SRC_MD2_SRCCLKENA, 1); + + /* Clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* Clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* DDR EN de-bounce length to 5us */ + write32(&mtk_spm->ddren_dbc_con, DDREN_DBC_EN_VAL | REG_DDREN_DBC_EN_LSB); + + /* Configure ARMPLL Control Mode for MCDI */ + write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); + + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); + write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); + write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); + write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); + + /* Enable Side-Band */ + write32((void *)AP_PLL_CON3, APMIX_CON3_DEF); + write32((void *)AP_PLL_CON4, APMIX_CON4_DEF); + write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF); + write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF); + + /* Init VCORE DVFS Status */ + SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, + SPM_DVFS_FORCE_ENABLE_LSB, 0, + SPM_DVFSRC_ENABLE_LSB, 1); + write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); + write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); + + write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); + + spm_hw_s1_state_monitor(0); +} + +static void spm_extern_initialize(void) +{ + SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, + INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1, + INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1); +} + +static void spm_set_sysclk_settle(void) +{ + write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); +} + +static void spm_code_swapping(void) +{ + u32 mask; + + mask = read32(&mtk_spm->spm_wakeup_event_mask); + write32(&mtk_spm->spm_wakeup_event_mask, + mask & ~SPM_WAKEUP_EVENT_MASK_BIT0); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, mask); +} + +static void spm_reset_and_init_pcm(void) +{ + bool first_load_fw = true; + + /* Check whether the SPM FW is running */ + if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN) + first_load_fw = false; + + if (!first_load_fw) { + spm_code_swapping(); + /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */ + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + /* Disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Disable pcm timer after leaving FW */ + clrsetbits32(&mtk_spm->pcm_con1, + RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); + + /* Reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); +} + +static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) +{ + uintptr_t ptr; + u32 dmem_words; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + + ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; + pmem_words = pcm->desc.pmem_words; + total_words = pcm->desc.total_words; + dmem_words = total_words - pmem_words; + pmem_start = pcm->desc.pmem_start; + dmem_start = pcm->desc.dmem_start; + + printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", + __func__, (long)ptr, pmem_words, dmem_words); + + /* DMA needs 16-byte aligned source data. */ + assert(ptr % 16 == 0); + + write32((void *)MD32PCM_DMA0_SRC, ptr); + write32((void *)MD32PCM_DMA0_DST, pmem_start); + write32((void *)MD32PCM_DMA0_WPPT, pmem_words); + write32((void *)MD32PCM_DMA0_WPTO, dmem_start); + write32((void *)MD32PCM_DMA0_COUNT, total_words); + write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL); + write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL); + + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + /* Init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + u32 val, mask; + + /* Toggle event counter clear */ + setbits32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB); + + /* Toggle for reset SYS TIMER start point */ + SET32_BITFIELDS(&mtk_spm->sys_timer_con, + SYS_TIMER_START_EN_LSB, 1); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + + setbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB | SPM_REGWR_CFG_KEY); + + /* Unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrup_ack_mask) + mask &= ~R12_CSYSPWREQ_B; + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* Unmask SPM ISR */ + setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); + + /* Toggle event counter clear */ + clrsetbits32(&mtk_spm->pcm_con1, REG_SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY); + + /* Toggle for reset SYS TIMER start point */ + SET32_BITFIELDS(&mtk_spm->sys_timer_con, + SYS_TIMER_START_EN_LSB, 0); +} + +static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +{ + u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; + + /* Set PCM flags and data */ + if (pwrctrl->pcm_flags_cust_clr != 0) + pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; + if (pwrctrl->pcm_flags_cust_set != 0) + pcm_flags |= pwrctrl->pcm_flags_cust_set; + if (pwrctrl->pcm_flags1_cust_clr != 0) + pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; + if (pwrctrl->pcm_flags1_cust_set != 0) + pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; + + write32(&mtk_spm->spm_sw_flag_0, pcm_flags); + write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); + write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); + write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); +} + +static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +static void reset_spm(struct mtk_mcu *mcu) +{ + struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv; + + spm_parse_firmware(mcu); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcm); + spm_init_pcm_register(); + spm_set_power_control(&spm_init_ctrl); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); +} + +static struct mtk_mcu spm = { + .firmware_name = CONFIG_SPM_FIRMWARE, + .reset = reset_spm, +}; + +int spm_init(void) +{ + struct dyna_load_pcm pcm; + struct stopwatch sw; + + stopwatch_init(&sw); + + spm_register_init(); + spm_set_power_control(&spm_init_ctrl); + spm_set_sysclk_settle(); + spm_extern_initialize(); + + spm.load_buffer = _dram_dma; + spm.buffer_size = REGION_SIZE(dram_dma); + spm.priv = (void *)&pcm; + + if (mtk_init_mcu(&spm)) { + printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__); + return -1; + } + + printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", + __func__, stopwatch_duration_msecs(&sw), + read32(&mtk_spm->md32pcm_pc)); + + return 0; +} diff --git a/src/soc/mediatek/mt8186/timer.c b/src/soc/mediatek/mt8186/timer.c new file mode 100644 index 0000000000..7a289cd115 --- /dev/null +++ b/src/soc/mediatek/mt8186/timer.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.13 + */ + +#include +#include +#include + +void timer_prepare(void) +{ + clrbits32((void *)SYSTIMER_BASE, COMP_FEATURE_MASK); + setbits32((void *)SYSTIMER_BASE, COMP_25_MASK); +} diff --git a/src/soc/mediatek/mt8186/usb.c b/src/soc/mediatek/mt8186/usb.c new file mode 100644 index 0000000000..6d83abbde1 --- /dev/null +++ b/src/soc/mediatek/mt8186/usb.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.5 + */ + +#include +#include +#include +#include + +void mtk_usb_prepare(void) +{ + gpio_output(GPIO(USB_DRVVBUS_P1), 1); +} diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c new file mode 100644 index 0000000000..fbc9bb9989 --- /dev/null +++ b/src/soc/mediatek/mt8186/wdt.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 3.4 + */ + +#include +#include +#include + +#define MTK_WDT_CLR_STATUS_VAL 0x22 + +DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24) + +void mtk_wdt_clr_status(void) +{ + SET32_BITFIELDS(&mtk_wdt->wdt_mode, + MTK_WDT_CLR_STATUS, MTK_WDT_CLR_STATUS_VAL); +} diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index e099ffdf0f..9b55295612 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -55,7 +55,7 @@ config FLASH_DUAL_READ default y help When this option is enabled, the flash controller provides the ability - to dual read mode. + to dual IO read mode. config SRCLKEN_RC_SUPPORT bool diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d713e4d4c2..aeb50a729b 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -30,7 +31,7 @@ romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/memory.c ../common/memory_test.c -romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c @@ -55,15 +56,14 @@ ramstage-y += ../common/i2c.c i2c.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c mmu_operations.c -ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c -ramstage-y += ../common/tracker.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 17fd27e53f..3adf5c17bd 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -4,11 +4,13 @@ #include #include #include +#include #include void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index a76b0394c7..5f1e3a03f3 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -2,11 +2,9 @@ #include #include -#include #include #include -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) #define I2C_FULL_DUTY 100 #define I2C_HALF_DUTY 50 #define I2C_ADJUSTED_DUTY 45 @@ -64,7 +62,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = { }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -127,7 +126,7 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus) } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -178,7 +177,7 @@ static void mtk_i2c_speed_init(uint8_t bus) void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h index 7d6efda40f..a5357c9cd2 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -10,63 +10,10 @@ #include #include +#include #include -#define DRAMC_PARAM_HEADER_VERSION 6 - -enum DRAMC_PARAM_STATUS_CODES { - DRAMC_SUCCESS = 0, - DRAMC_ERR_INVALID_VERSION, - DRAMC_ERR_INVALID_SIZE, - DRAMC_ERR_INVALID_FLAGS, - DRAMC_ERR_RECALIBRATE, - DRAMC_ERR_INIT_DRAM, - DRAMC_ERR_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_FAST_CALIBRATION, -}; - -enum DRAMC_PARAM_FLAGS { - DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, -}; - -enum SDRAM_DVFS_FLAG { - DRAMC_DISABLE_DVFS, - DRAMC_ENABLE_DVFS, -}; - -enum SDRAM_DDR_TYPE { - DDR_TYPE_DISCRETE, - DDR_TYPE_EMCP, -}; - -enum SDRAM_DDR_GEOMETRY_TYPE { - DDR_TYPE_2CH_2RK_4GB_2_2, - DDR_TYPE_2CH_2RK_6GB_3_3, - DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, - DDR_TYPE_2CH_1RK_4GB_4_0, - DDR_TYPE_2CH_2RK_6GB_2_4, - DDR_TYPE_2CH_2RK_8GB_4_4, -}; - -enum SDRAM_VOLTAGE_TYPE { - SDRAM_VOLTAGE_NVCORE_NVDRAM, - SDRAM_VOLTAGE_HVCORE_HVDRAM, - SDRAM_VOLTAGE_LVCORE_LVDRAM, -}; - -struct dramc_param_header { - u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ - u16 size; /* size of whole dramc_param, update in the coreboot */ - u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ - u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ -}; - -struct sdram_info { - u32 ddr_type; /* SDRAM_DDR_TYPE */ - u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ -}; +#define DRAMC_PARAM_HEADER_VERSION 7 struct sdram_params { u32 rank_num; @@ -115,23 +62,6 @@ struct sdram_params { u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; }; -struct emi_mdl { - u32 cona_val; - u32 conh_val; - u32 conf_val; - u32 chn_cona_val; -}; - -struct ddr_base_info { - u32 config_dvfs; /* SDRAM_DVFS_FLAG */ - struct sdram_info sdram; - u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ - u32 support_ranks; - u64 rank_size[RANK_MAX]; - struct emi_mdl emi_config; - DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; -}; - struct dramc_data { struct ddr_base_info ddr_info; struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h index 72a9af10e2..fbf41e6c48 100644 --- a/src/soc/mediatek/mt8192/include/soc/i2c.h +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_I2C_H #include +#include /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ struct mt_i2c_regs { uint32_t rollback; }; +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8192/include/soc/mcucfg.h b/src/soc/mediatek/mt8192/include/soc/mcucfg.h index 1d270ecd41..b9f1f38e73 100644 --- a/src/soc/mediatek/mt8192/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8192/include/soc/mcucfg.h @@ -1033,6 +1033,6 @@ check_member(mt8192_mcucfg_regs, mcusys_reserved_reg4, 0x7fd0); check_member(mt8192_mcucfg_regs, mcusys_reserved_reg0, 0x7fe0); check_member(mt8192_mcucfg_regs, mcusys_reserved_reg3_rd, 0x7ffc); -static struct mt8192_mcucfg_regs *const mt8192_mcucfg = (void *)MCUCFG_BASE; +static struct mt8192_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8192_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index d99ca6587b..4951f13ccb 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -5,7 +5,6 @@ #include #include -#include #include /* SPM READ/WRITE CFG */ diff --git a/src/soc/mediatek/mt8192/include/soc/tracker.h b/src/soc/mediatek/mt8192/include/soc/tracker.h new file mode 100644 index 0000000000..0b6281114f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_TRACKER_H +#define SOC_MEDIATEK_MT8192_TRACKER_H + +#include + +#endif diff --git a/src/soc/mediatek/mt8192/msdc.c b/src/soc/mediatek/mt8192/msdc.c new file mode 100644 index 0000000000..113069a27b --- /dev/null +++ b/src/soc/mediatek/mt8192/msdc.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#define MSDC0_BASE 0x11f60000 +#define MSDC0_TOP_BASE 0x11f50000 + +#define MSDC0_DRV_MASK 0x3fffffff +#define MSDC1_DRV_MASK 0x3ffff000 +#define MSDC0_DRV_VALUE 0x24924924 +#define MSDC1_DRV_VALUE 0x1b6db000 + +#define MSDC1_GPIO_MODE0_BASE 0x10005360 +#define MSDC1_GPIO_MODE0_MASK 0x77777000 +#define MSDC1_GPIO_MODE0_VALUE 0x11111000 + +#define MSDC1_GPIO_MODE1_BASE 0x10005370 +#define MSDC1_GPIO_MODE1_MASK 0x7 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1), + GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3), + GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5), + GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7), + GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(MSDC0_DSL), GPIO(MSDC0_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ + clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RM_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + uint8_t enable = 1; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); + + mainboard_enable_regulator(MTK_REGULATOR_VCC, enable); + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable); +} diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index e49e222c7c..c9e2753174 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -417,13 +417,13 @@ void mt_pll_init(void) } /* MCUCFG CLKMUX */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); @@ -481,7 +481,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq) setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); /* switch ca55 clock source to intermediate clock */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN); @@ -494,7 +494,7 @@ void mt_pll_raise_little_cpu_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch ca55 clock source back to armpll_ll */ - clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); @@ -566,7 +566,7 @@ void mt_pll_raise_cci_freq(u32 freq) setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); /* switch cci clock source to intermediate clock */ - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN); @@ -579,7 +579,7 @@ void mt_pll_raise_cci_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch cci clock source back to ccipll */ - clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* disable [4] intermediate clock armpll_divider_pll1_ck */ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 355827ac27..006a212da9 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include @@ -34,7 +33,6 @@ static void soc_init(struct device *dev) if (CONFIG(MTK_DFD)) dfd_init(); ufs_disable_refclk(); - bustracker_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 3a444dfcf3..f98f5fce35 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #define SPM_SYSTEM_BASE_OFFSET 0x40000000 diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index df1b5d8b47..d1cb09be87 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8195 select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON - select CLEAR_WDT_MODE_REG select DPM_FOUR_CHANNEL if SOC_MEDIATEK_MT8195 @@ -55,6 +54,6 @@ config FLASH_DUAL_READ default y help When this option is enabled, the flash controller provides the ability - to dual read mode. + to dual IO read mode. endif diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 5d444c7564..8ab78a80e2 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -7,11 +7,12 @@ bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c -bootblock-y += ../common/wdt.c +bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c @@ -20,8 +21,10 @@ verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c -verstage-y += ../common/wdt.c +verstage-y += ../common/wdt.c wdt.c +ramstage-y += apusys.c +ramstage-y += apusys_devapc.c romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c @@ -33,13 +36,13 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c -romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c -romstage-y += ../common/wdt.c +romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c romstage-y += ../common/pmif_spmi.c pmif_spmi.c @@ -48,7 +51,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += mt6691.c romstage-y += mt6360.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c -ramstage-y += ../common/tracker.c + ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c ramstage-y += devapc.c @@ -63,10 +66,10 @@ ramstage-y += hdmi.c ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mcu.c ramstage-y += ../common/mcupm.c -ramstage-y += ../common/mmu_operations.c mmu_operations.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += mt6360.c ramstage-y += ../common/mtcmos.c mtcmos.c -ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/pll.c pll.c ramstage-y += ../common/pmif.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c @@ -78,7 +81,7 @@ ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c -ramstage-y += ../common/wdt.c +ramstage-y += ../common/wdt.c wdt.c BL31_MAKEARGS += PLAT=mt8195 diff --git a/src/soc/mediatek/mt8195/apusys.c b/src/soc/mediatek/mt8195/apusys.c new file mode 100644 index 0000000000..fc95cab429 --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* MBOX Functional Configuration */ +DEFINE_BITFIELD(LOCK, 0, 0) +DEFINE_BITFIELD(NO_MPU, 16, 16) + +static void dump_apusys_reg(void) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) { + printk(BIOS_DEBUG, "APU_MBOX %p = %#x\n", + (void *)&mt8195_apu_mbox[i]->mbox_func_cfg, + read32(&mt8195_apu_mbox[i]->mbox_func_cfg)); + } +} + +void apusys_init(void) +{ + size_t i; + + /* Set up MBOX MPU for non secure access */ + for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) + SET32_BITFIELDS(&mt8195_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1); + + dump_apusys_reg(); +} diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c new file mode 100644 index 0000000000..3a49e380b3 --- /dev/null +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const enum domain_id domain_map[] = { + DOMAIN_0, DOMAIN_1, DOMAIN_2, DOMAIN_3, DOMAIN_4, DOMAIN_5, DOMAIN_6, DOMAIN_7, + DOMAIN_8, DOMAIN_9, DOMAIN_10, DOMAIN_11, DOMAIN_12, DOMAIN_13, DOMAIN_14, DOMAIN_15, +}; + +#define DAPC_APU_AO_SYS0_ATTR(...) \ + { \ + { \ + DAPC_PERM_ATTR_16(__VA_ARGS__) \ + } \ + } +#define DAPC_APU_NOC_AO_SYS0_ATTR(...) \ + { \ + { \ + DAPC_PERM_ATTR_16(__VA_ARGS__) \ + } \ + } + +/* NOC DAPC */ +static const struct apc_apu_dom_16 apusys_noc_dapc[] = { + /* 0 */ + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv00-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv01-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-3", NO_PROTECTION, FORBIDDEN15), + + /* 10 */ + DAPC_APU_NOC_AO_SYS0_ATTR("slv03-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_NOC_AO_SYS0_ATTR("slv04_05_06_07-3", NO_PROTECTION, FORBIDDEN15), +}; +_Static_assert(ARRAY_SIZE(apusys_noc_dapc) == APUSYS_NOC_DAPC_AO_SLAVE_NUM, + "Wrong size on apusys_noc_dapc"); + +/* AO DAPC */ +static const struct apc_apu_dom_16 apusys_ao_apc[] = { + /* 0 */ + DAPC_APU_AO_SYS0_ATTR("apusys_ao-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-5", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-6", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-8", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apusys_ao-9", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-0", NO_PROTECTION, FORBIDDEN15), + + /* 10 */ + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_apb_s-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("md32_debug_apb", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_con2_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_con1_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sctrl_reviscer", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sema_stimer", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_emi_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_edma0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_edma1", NO_PROTECTION, FORBIDDEN15), + + /* 20 */ + DAPC_APU_AO_SYS0_ATTR("apu_cpe_sensor", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_cpe_coef", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_cpe_ctrl", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sensor_wrp_dla_0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_sensor_wrp_dla_1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_dapc_ao", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_dapc", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("infra_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("infra_ao_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("noc_dapc", NO_PROTECTION, FORBIDDEN15), + + /* 30 */ + DAPC_APU_AO_SYS0_ATTR("apu_noc_bcrm", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_0", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_1", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("apu_noc_config_2", NO_PROTECTION, FORBIDDEN, FORBIDDEN, + NO_PROTECTION, FORBIDDEN12), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_config-0", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_config-1", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_config-0", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_config-1", NO_PROTECTION, FORBIDDEN, FORBIDDEN3, + NO_PROTECTION, FORBIDDEN3, FORBIDDEN7), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-1", NO_PROTECTION, FORBIDDEN15), + + /* 40 */ + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla0_apb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("mdla1_apb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r1", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r3", SEC_RW_ONLY, FORBIDDEN15), + + /* 50 */ + DAPC_APU_AO_SYS0_ATTR("apu_iommu0_r4", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r1", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r2", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r3", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_iommu1_r4", SEC_RW_ONLY, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_rsi2_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_s0_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_n0_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_acp_ssc_config", NO_PROTECTION, FORBIDDEN15), + + /* 60 */ + DAPC_APU_AO_SYS0_ATTR("apu_s1_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_n1_ssc_config", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-0", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-1", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-2", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-3", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-4", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("apu_ao_dbgapb-5", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("vpu_core0_debug_apb", NO_PROTECTION, FORBIDDEN15), + DAPC_APU_AO_SYS0_ATTR("vpu_core1_debug_apb", NO_PROTECTION, FORBIDDEN15), + + /* 70 */ + DAPC_APU_AO_SYS0_ATTR("apb_infra_dbg_ctl", NO_PROTECTION, FORBIDDEN15), +}; +_Static_assert(ARRAY_SIZE(apusys_ao_apc) == APUSYS_APC_SYS0_AO_SLAVE_NUM, + "Wrong size on apusys_ao_apc"); + +static int set_slave_noc_dapc(u32 slave, enum domain_id domain_id, enum devapc_perm_type perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_ERR, "[NOC_DAPC] permission type:%#x is not supported!\n", perm); + return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + } + + if (slave >= APUSYS_NOC_DAPC_AO_SLAVE_NUM || domain_id >= APUSYS_NOC_DAPC_AO_DOM_NUM) { + printk(BIOS_ERR, "[NOC_DAPC] %s: %s, %s:%#x, %s:%#x\n", __func__, + "out of boundary", "slave", slave, "domain_id", domain_id); + return APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + + apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM; + base = (void *)((size_t)APUSYS_NOC_DAPC_AO_BASE + domain_id * 0x40 + + apc_register_index * 4); + clrsetbits32(base, 0x3U << (apc_set_index * 2), perm << (apc_set_index * 2)); + + return APUSYS_APC_OK; +} + +static void dump_apusys_noc_dapc(void) +{ + u32 reg_num; + size_t d, i; + + reg_num = DIV_ROUND_UP(ARRAY_SIZE(apusys_noc_dapc), + APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM); + for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { + for (i = 0U; i < reg_num; i++) + printk(BIOS_DEBUG, "[NOCDAPC] D%ld_APC_%ld: %#x\n", d, i, + read32((void *)(APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); + } + printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: %#x\n", read32(APUSYS_NOC_DAPC_CON)); +} + +static int set_slave_apc(u32 slave, enum domain_id domain_id, enum devapc_perm_type perm) +{ + u32 apc_register_index; + u32 apc_set_index; + u32 *base; + + if (perm >= PERM_NUM || perm < 0) { + printk(BIOS_ERR, "[APUAPC] perm type:%#x is not supported!\n", perm); + return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED; + } + + if (slave >= APUSYS_APC_SYS0_AO_SLAVE_NUM || domain_id >= APUSYS_APC_SYS0_AO_DOM_NUM) { + printk(BIOS_ERR, "[APUAPC] %s: %s, %s:%#x, %s:%#x\n", __func__, + "out of boundary", "slave", slave, "domain_id", domain_id); + return APUSYS_APC_ERR_OUT_OF_BOUNDARY; + } + + apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM; + base = (void *)((size_t)APUSYS_APC_AO_BASE + domain_id * 0x40 + apc_register_index * 4); + + clrsetbits32(base, 0x3U << (apc_set_index * 2), perm << (apc_set_index * 2)); + + return APUSYS_APC_OK; +} + +static void dump_apusys_ao_apc(void) +{ + u32 reg_num; + size_t d, i; + + reg_num = + DIV_ROUND_UP(ARRAY_SIZE(apusys_ao_apc), APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM); + for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { + for (i = 0U; i < reg_num; i++) + printk(BIOS_DEBUG, "[APUAPC] D%ld_APC_%ld: %#x\n", d, i, + read32((void *)(APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); + } + printk(BIOS_DEBUG, "[APUAPC] APC_CON: %#x\n", read32(APUSYS_APC_CON)); +} + +static int set_apusys_noc_dapc(void) +{ + int ret = APUSYS_APC_OK; + size_t i, j; + + for (i = 0; i < ARRAY_SIZE(apusys_noc_dapc); i++) { + for (j = 0; j < ARRAY_SIZE(apusys_noc_dapc[i].d_permission); j++) { + ret = set_slave_noc_dapc(i, j, apusys_noc_dapc[i].d_permission[j]); + if (ret) + printk(BIOS_ERR, "[APUAPC] fail (%ld, %ld)(%d)!\n", i, j, ret); + } + } + + return ret; +} + +static int32_t set_apusys_ao_apc(void) +{ + int ret = APUSYS_APC_OK; + size_t i, j; + + for (i = 0; i < ARRAY_SIZE(apusys_ao_apc); i++) { + for (j = 0; j < ARRAY_SIZE(apusys_ao_apc[j].d_permission); j++) { + ret = set_slave_apc(i, domain_map[j], apusys_ao_apc[i].d_permission[j]); + if (ret) + printk(BIOS_ERR, "[APUAPC] fail (%ld, %ld)(%d)!\n", i, j, ret); + } + } + + return ret; +} + +void start_apusys_devapc(void) +{ + int ret = APUSYS_APC_OK; + + /* Check violation status */ + printk(BIOS_DEBUG, "[APUAPC] vio %d\n", read32(APUSYS_APC_CON) & 0x80000000); + + /* Initial Permission */ + ret = set_apusys_ao_apc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_ao_apc", + ret ? "FAILED" : "SUCCESS"); + + /* Lock */ + write32(APUSYS_SYS0_APC_LOCK_0, APU_SCTRL_REVISER | DEVAPC_AO_WRAPPER); + + /* Initial NoC Permission */ + ret = set_apusys_noc_dapc(); + printk(BIOS_DEBUG, "[APUAPC] %s - %s!\n", "set_apusys_noc_dapc", + ret ? "FAILED" : "SUCCESS"); + + dump_apusys_ao_apc(); + dump_apusys_noc_dapc(); + + printk(BIOS_DEBUG, "[APUAPC] %s done\n", __func__); +} diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 17fd27e53f..3adf5c17bd 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -4,11 +4,13 @@ #include #include #include +#include #include void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index 9354353760..ac3e6db8d6 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -2,11 +2,13 @@ #include #include +#include +#include static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2", @@ -14,26 +16,26 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION3, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION2, FORBIDDEN12), DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", @@ -41,16 +43,14 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S", NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S", @@ -62,19 +62,16 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 30 */ DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", @@ -90,15 +87,14 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("SECURITY_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("SPMI_MST_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ DAPC_INFRA_AO_SYS0_ATTR("BCRM_FMEM_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S", @@ -140,13 +136,13 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("L3C_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", @@ -159,11 +155,11 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { NO_PROTECTION, FORBIDDEN15), /* 70 */ DAPC_INFRA_AO_SYS0_ATTR("NNA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("PCIE1_AXI_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB1_S", @@ -179,42 +175,42 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { /* 0 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), /* 10 */ DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", @@ -231,7 +227,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25", - NO_PROTECTION, FORBIDDEN3), + NO_PROTECTION, FORBIDDEN2, NO_PROTECTION), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26", NO_PROTECTION, FORBIDDEN3), DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27", @@ -1099,34 +1095,34 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys2_devices[] = { static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = { /* 0 */ DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), /* 10 */ DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1", @@ -1134,83 +1130,79 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = { DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), /* 20 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN2, + NO_PROTECTION, FORBIDDEN10), DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 30 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 40 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), /* 50 */ DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", @@ -1239,7 +1231,7 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = { static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = { /* 0 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2", @@ -1251,22 +1243,22 @@ static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = { DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 10 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15", @@ -1274,18 +1266,18 @@ static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = { DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16", NO_PROTECTION, FORBIDDEN7), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), /* 20 */ DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22", - NO_PROTECTION, FORBIDDEN7), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN3), }; static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { @@ -1299,7 +1291,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S", @@ -1448,8 +1440,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S", @@ -1487,10 +1478,9 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("APDMA_APB_S", @@ -1519,8 +1509,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), /* 110 */ @@ -1529,8 +1518,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION, - FORBIDDEN12), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S", @@ -1542,7 +1530,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = { DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION, FORBIDDEN3, NO_PROTECTION, FORBIDDEN11), DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S", NO_PROTECTION, FORBIDDEN15), /* 120 */ @@ -1569,9 +1557,9 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = { DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE1_AHB_S", - NO_PROTECTION, FORBIDDEN15), + NO_PROTECTION2, FORBIDDEN14), DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P1_S", NO_PROTECTION, FORBIDDEN15), /* 10 */ @@ -1582,7 +1570,7 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = { DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", @@ -1597,7 +1585,7 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = { NO_PROTECTION, FORBIDDEN15), /* 20 */ DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", @@ -1632,9 +1620,9 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = { DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S", NO_PROTECTION, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", - SEC_RW_ONLY, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", - NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN), + NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13), DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S", NO_PROTECTION, FORBIDDEN15), /* 40 */ @@ -1767,6 +1755,9 @@ static void dump_infra_ao_apc(uintptr_t base) printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n", read32(getreg(base, MAS_SEC_0))); + + printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO %#lx)DOM_REMAP_0_0: %#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); } static void dump_peri_ao_apc(uintptr_t base) @@ -1817,19 +1808,91 @@ static void dump_peri_par_ao_apc(uintptr_t base) read32(getreg(base, MAS_SEC_0))); } +static void dump_fmem_ao(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_infra2_ao_apc(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", + base, read32(getreg(base, DOM_REMAP_0_0))); +} + +static void dump_scp_master(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] SCP:%#x ADSP:%#x Lock:%#x\n", + read32(getreg(base, SCP_DOM)), + read32(getreg(base, ADSP_DOM)), + read32(getreg(base, ONETIME_LOCK))); +} + static void infra_init(uintptr_t base) { /* Side band */ SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), + SCP_SSPM_DOM, DOMAIN_2, + CPU_EB_DOM, DOMAIN_2); + /* Default APC Setting */ set_infra_ao_apc(base); + + /* + * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1, 2, 4, 5 to domain 1 (forbidden for all) + * 3. From domain 3 to domain 3 + * 4. others from XXX to domain 0 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_2_0), + TWO_BIT_DOM_REMAP_0, DOMAIN_0, + TWO_BIT_DOM_REMAP_1, DOMAIN_1, + TWO_BIT_DOM_REMAP_2, DOMAIN_1, + TWO_BIT_DOM_REMAP_3, DOMAIN_3, + TWO_BIT_DOM_REMAP_4, DOMAIN_1, + TWO_BIT_DOM_REMAP_5, DOMAIN_1); + /* + * Domain Remap: TINYSYS (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); } static void peri_init(uintptr_t base) { /* Default APC Setting */ set_peri_ao_apc(base); + + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, DOMAIN_2); + + /* + * Domain Remap: TINYSYS slave domain remap (4-bit to 3-bit) + * 1. From domain 0 to domain 0 (no protection for all) + * 2. From domain 1 ~ 5 to domain 1 ~ 5 + * 3. others from XXX to domain 0 (no protection for all) + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + THREE_BIT_DOM_REMAP_0, DOMAIN_0, + THREE_BIT_DOM_REMAP_1, DOMAIN_1, + THREE_BIT_DOM_REMAP_2, DOMAIN_2, + THREE_BIT_DOM_REMAP_3, DOMAIN_3, + THREE_BIT_DOM_REMAP_4, DOMAIN_4, + THREE_BIT_DOM_REMAP_5, DOMAIN_5); } static void peri2_init(uintptr_t base) @@ -1849,10 +1912,56 @@ static void peri_par_init(uintptr_t base) SSUSB_P2_SEC, SECURE_TRANS, SSUSB_P3_SEC, SECURE_TRANS); + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_4), + PCIE0_DOM, DOMAIN_1, + PCIE1_DOM, DOMAIN_1); + /* Default APC Setting */ set_peri_par_ao_apc(base); } +static void fmem_master_init(uintptr_t base) +{ + /* + * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) + * 1. SCP from 3 to 3 + * 2. DSP from 4 to 4 + * 3. others from XXX to 15 + */ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void infra2_init(uintptr_t base) +{ + SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0), + FOUR_BIT_DOM_REMAP_0, DOMAIN_15, + FOUR_BIT_DOM_REMAP_1, DOMAIN_15, + FOUR_BIT_DOM_REMAP_2, DOMAIN_15, + FOUR_BIT_DOM_REMAP_3, DOMAIN_3, + FOUR_BIT_DOM_REMAP_4, DOMAIN_4, + FOUR_BIT_DOM_REMAP_5, DOMAIN_15, + FOUR_BIT_DOM_REMAP_6, DOMAIN_15, + FOUR_BIT_DOM_REMAP_7, DOMAIN_15); +} + +static void scp_master_init(uintptr_t base) +{ + write32(getreg(base, SCP_DOM), DOMAIN_3); + write32(getreg(base, ADSP_DOM), DOMAIN_4); + + /* Let SCP_DOM and ADSP_DOM registers be read-only for security */ + write32(getreg(base, ONETIME_LOCK), 0x5); +} + struct devapc_init_ops { uintptr_t base; void (*init)(uintptr_t base); @@ -1862,6 +1971,9 @@ struct devapc_init_ops { { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, { DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc }, { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, + { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, + { DEVAPC_INFRA2_AO_BASE, infra2_init, dump_infra2_ao_apc }, + { SCP_CFG_BASE, scp_master_init, dump_scp_master }, }; void dapc_init(void) @@ -1884,4 +1996,7 @@ void dapc_init(void) if (devapc_init[i].dump) devapc_init[i].dump(devapc_ao_base); } + + /* Set up APUSYS Permission */ + start_apusys_devapc(); } diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c index 668376739d..aba7d7865c 100644 --- a/src/soc/mediatek/mt8195/dp_intf.c +++ b/src/soc/mediatek/mt8195/dp_intf.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -10,8 +9,6 @@ #include #include #include -#include -#include static void mtk_dpintf_mask(struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask) { diff --git a/src/soc/mediatek/mt8195/dpm_4ch.c b/src/soc/mediatek/mt8195/dpm_4ch.c index 78895c8466..f13337d8b7 100644 --- a/src/soc/mediatek/mt8195/dpm_4ch.c +++ b/src/soc/mediatek/mt8195/dpm_4ch.c @@ -28,7 +28,7 @@ static int wake_dpm_sram_up(void) } if (loop == 0) { - printk(BIOS_ERR, "ERROR: failed to wake DPM up.\n"); + printk(BIOS_ERR, "failed to wake DPM up.\n"); return -1; } diff --git a/src/soc/mediatek/mt8195/dptx.c b/src/soc/mediatek/mt8195/dptx.c index 8d557ba910..f2c0905cc4 100644 --- a/src/soc/mediatek/mt8195/dptx.c +++ b/src/soc/mediatek/mt8195/dptx.c @@ -11,7 +11,6 @@ #include #include #include -#include #define ONE_BLOCK_SIZE 128 @@ -432,7 +431,7 @@ static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp) 0x08 : 0x00; if (pixclk_mhz > mtk_dp->train_info.linkrate * 27) { count = 0x8; - printk(BIOS_ERR, "ERROR: Pixclk > LinkRateChange\n"); + printk(BIOS_ERR, "Pixclk > LinkRateChange\n"); } else { count = 0x10 + offset; } diff --git a/src/soc/mediatek/mt8195/dptx_hal.c b/src/soc/mediatek/mt8195/dptx_hal.c index cc96cc85c3..b246c20119 100644 --- a/src/soc/mediatek/mt8195/dptx_hal.c +++ b/src/soc/mediatek/mt8195/dptx_hal.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #define REG_OFFSET_LIMIT 0x8000 @@ -721,7 +719,7 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, int value) mtk_dp_write_byte(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2)); } else { - printk(BIOS_ERR, "ERROR: [%s]value << 2 > 0xff\n", __func__); + printk(BIOS_ERR, "[%s]value << 2 > 0xff\n", __func__); } } @@ -744,7 +742,7 @@ void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value) mtk_dp_write(mtk_dp, 0x103C, 0x3); break; default: - printk(BIOS_ERR, "ERROR: Link rate not support(%d)\n", value); + printk(BIOS_ERR, "Link rate not support(%d)\n", value); break; } diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c index 1a10eefe49..ac8b8e5b39 100644 --- a/src/soc/mediatek/mt8195/i2c.c +++ b/src/soc/mediatek/mt8195/i2c.c @@ -4,12 +4,8 @@ #include #include #include -#include #include #include -#include - -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) struct mtk_i2c mtk_i2c_bus_controller[] = { [0] = { @@ -54,7 +50,8 @@ struct mtk_i2c mtk_i2c_bus_controller[] = { }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -111,245 +108,6 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus) } } -static int mtk_i2c_max_step_cnt(uint32_t target_speed) -{ - if (target_speed > I2C_SPEED_FAST_PLUS) - return MAX_HS_STEP_CNT_DIV; - else - return MAX_STEP_CNT_DIV; -} - -/* - * Check and calculate i2c ac-timing. - * - * Hardware design: - * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src - * xxx_cnt_div = spec->min_xxx_ns / sample_ns - * - * The calculation of sample_ns is rounded down; - * otherwise xxx_cnt_div would be greater than the smallest spec. - * The sda_timing is chosen as the middle value between - * the largest and smallest. - */ -static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, - uint32_t check_speed, - uint32_t step_cnt, - uint32_t sample_cnt) -{ - const struct i2c_spec_values *spec; - uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; - uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; - uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; - struct mtk_i2c_ac_timing *ac_timing; - - spec = mtk_i2c_get_spec(check_speed); - - clk_ns = NSECS_PER_SEC / clk_src; - - su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); - if (su_sta_cnt > max_sta_cnt) - return -1; - - low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); - max_step_cnt = mtk_i2c_max_step_cnt(check_speed); - if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { - if (low_cnt > step_cnt) { - high_cnt = 2 * step_cnt - low_cnt; - } else { - high_cnt = step_cnt; - low_cnt = step_cnt; - } - } else { - return -2; - } - - sda_max = spec->max_hd_dat_ns / sample_ns; - if (sda_max > low_cnt) - sda_max = 0; - - sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); - if (sda_min < low_cnt) - sda_min = 0; - - if (sda_min > sda_max) - return -3; - - ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; - if (check_speed > I2C_SPEED_FAST_PLUS) { - ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); - ac_timing->ltiming &= ~GENMASK(15, 9); - ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); - ac_timing->ext &= ~GENMASK(7, 1); - ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); - } else { - ac_timing->htiming = (sample_cnt << 8) | (high_cnt); - ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); - ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); - } - - return 0; -} - -/* - * Calculate i2c port speed. - * - * Hardware design: - * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) - * clock_div: fixed in hardware, but may be various in different SoCs - * - * To calculate sample_cnt and step_cnt, we pick the highest bus frequency - * that is still no larger than i2c->speed_hz. - */ -static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, - uint32_t target_speed, - uint32_t *timing_step_cnt, - uint32_t *timing_sample_cnt) -{ - uint32_t step_cnt; - uint32_t sample_cnt; - uint32_t max_step_cnt; - uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; - uint32_t base_step_cnt; - uint32_t opt_div; - uint32_t best_mul; - uint32_t cnt_mul; - uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; - int32_t clock_div_constraint = 0; - int success = 0; - - if (target_speed > I2C_SPEED_HIGH) - target_speed = I2C_SPEED_HIGH; - - max_step_cnt = mtk_i2c_max_step_cnt(target_speed); - base_step_cnt = max_step_cnt; - - /* Find the best combination */ - opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); - best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; - - /* Search for the best pair (sample_cnt, step_cnt) with - * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV - * 0 < step_cnt < max_step_cnt - * sample_cnt * step_cnt >= opt_div - * optimizing for sample_cnt * step_cnt being minimal - */ - for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { - if (sample_cnt == 1) { - if (clk_div != 0) - clock_div_constraint = 1; - else - clock_div_constraint = 0; - } else { - if (clk_div > 1) - clock_div_constraint = 1; - else if (clk_div == 0) - clock_div_constraint = -1; - else - clock_div_constraint = 0; - } - - step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); - if (step_cnt > max_step_cnt) - continue; - - cnt_mul = step_cnt * sample_cnt; - if (cnt_mul >= best_mul) - continue; - - if (mtk_i2c_check_ac_timing(bus, clk_src, - target_speed, step_cnt - 1, - sample_cnt - 1)) - continue; - - success = 1; - best_mul = cnt_mul; - base_sample_cnt = sample_cnt; - base_step_cnt = step_cnt; - if (best_mul == opt_div + clock_div_constraint) - break; - - } - - if (!success) - return -1; - - sample_cnt = base_sample_cnt; - step_cnt = base_step_cnt; - - if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > - target_speed) - return -1; - - *timing_step_cnt = step_cnt - 1; - *timing_sample_cnt = sample_cnt - 1; - - return 0; -} - -static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) -{ - uint32_t max_clk_div = MAX_CLOCK_DIV; - uint32_t clk_src, clk_div, step_cnt, sample_cnt; - uint32_t l_step_cnt, l_sample_cnt; - uint32_t timing_reg_value, ltiming_reg_value; - struct mtk_i2c *bus_ctrl; - - if (bus >= I2C_BUS_NUMBER) { - printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); - return; - } - - bus_ctrl = &mtk_i2c_bus_controller[bus]; - - for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { - clk_src = I2C_CLK_HZ / clk_div; - bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; - - if (speed > I2C_SPEED_FAST_PLUS) { - /* Set master code speed register */ - if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Set the high speed mode register */ - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &step_cnt, &sample_cnt)) - continue; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | - (sample_cnt << 12) | (step_cnt << 9); - bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); - } else { - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Disable the high speed transaction */ - bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; - } - - break; - } - - if (clk_div > max_clk_div) { - printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); - return; - } - - /* Init i2c bus timing register */ - write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); - write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming); - write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming); - write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs); - write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext); -} - void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) { mtk_i2c_speed_init(bus, speed); @@ -362,3 +120,12 @@ void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) read32(®s->ltiming), read32(®s->clock_div)); } + +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + write32(®s->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(®s->timing, bus_ctrl->ac_timing.htiming); + write32(®s->ltiming, bus_ctrl->ac_timing.ltiming); + write32(®s->hs, bus_ctrl->ac_timing.hs); + write32(®s->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index 88b545a97e..f2714dab3a 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -27,7 +27,7 @@ enum { APMIXED_BASE = IO_PHYS + 0x0000C000, SYSTIMER_BASE = IO_PHYS + 0x00017000, INFRACFG_AO_BCRM_BASE = IO_PHYS + 0x00022000, - PMIF_SPI_BASE = IO_PHYS + 0x00024000, + PMIF_SPI_BASE = IO_PHYS + 0x00024000, PMICSPI_MST_BASE = IO_PHYS + 0x00025000, PMIF_SPMI_BASE = IO_PHYS + 0x00027000, SPMI_MST_BASE = IO_PHYS + 0x00029000, @@ -43,6 +43,7 @@ enum { I2C_DMA_BASE = IO_PHYS + 0x00220080, EMI1_SUB_BASE = IO_PHYS + 0x00225000, EMI0_MPU_BASE = IO_PHYS + 0x00226000, + DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, @@ -80,6 +81,9 @@ enum { IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, + APU_MBOX_BASE = IO_PHYS + 0x09000000, + APUSYS_APC_AO_BASE = IO_PHYS + 0x090F8000, + APUSYS_NOC_DAPC_AO_BASE = IO_PHYS + 0x090FC000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/include/soc/apusys.h b/src/soc/mediatek/mt8195/include/soc/apusys.h new file mode 100644 index 0000000000..287e0f8ee0 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_APUSYS_H +#define SOC_MEDIATEK_MT8195_APUSYS_H + +#include +#include + +struct mt8195_apu_mbox_regs { + u32 mbox_in[8]; + u32 mbox_out[8]; + u32 mbox_reserved1[28]; + u32 mbox_func_cfg; + u32 mbox0_reserved2[19]; +}; + +check_member(mt8195_apu_mbox_regs, mbox_func_cfg, 0x0b0); + +static struct mt8195_apu_mbox_regs * const mt8195_apu_mbox[] = { + (void *)APU_MBOX_BASE, + (void *)(APU_MBOX_BASE + 0x100), + (void *)(APU_MBOX_BASE + 0x200), + (void *)(APU_MBOX_BASE + 0x300), + (void *)(APU_MBOX_BASE + 0x400), + (void *)(APU_MBOX_BASE + 0x500), + (void *)(APU_MBOX_BASE + 0x600), + (void *)(APU_MBOX_BASE + 0x700), +}; + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8195_APUSYS_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h new file mode 100644 index 0000000000..4b9e75fe60 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/apusys_devapc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef APUSYS_DEVAPC_H +#define APUSYS_DEVAPC_H + +enum apusys_apc_error { + APUSYS_APC_OK = 0, + APUSYS_APC_ERR_GENERIC, + APUSYS_APC_ERR_INVALID_CMD, + APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED, + APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED, + APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED, + APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED, + APUSYS_APC_ERR_OUT_OF_BOUNDARY, + APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED, +}; + +struct apc_apu_dom_16 { + unsigned char d_permission[16]; +}; + +#define APUSYS_APC_CON ((void *)(APUSYS_APC_AO_BASE + 0x00F00)) +#define APUSYS_SYS0_APC_LOCK_0 ((void *)(APUSYS_APC_AO_BASE + 0x00700)) +#define APUSYS_NOC_DAPC_CON ((void *)(APUSYS_NOC_DAPC_AO_BASE + 0x00F00)) + +#define APU_SCTRL_REVISER BIT(15) +#define DEVAPC_AO_WRAPPER BIT(8) + +#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_APC_SYS0_AO_DOM_NUM 16U +#define APUSYS_APC_SYS0_AO_SLAVE_NUM 71U + +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U +#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U +#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 15U + +void start_apusys_devapc(void); + +#endif /* APUSYS_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/devapc.h b/src/soc/mediatek/mt8195/include/soc/devapc.h index df8197214a..a355fdf042 100644 --- a/src/soc/mediatek/mt8195/include/soc/devapc.h +++ b/src/soc/mediatek/mt8195/include/soc/devapc.h @@ -17,10 +17,17 @@ enum devapc_ao_offset { DOM_REMAP_1_1 = 0x814, DOM_REMAP_2_0 = 0x820, MAS_DOM_0 = 0x0900, + MAS_DOM_4 = 0x0910, MAS_SEC_0 = 0x0A00, AO_APC_CON = 0x0F00, }; +enum scp_offset { + SCP_DOM = 0xA5080, + ADSP_DOM = 0xA5088, + ONETIME_LOCK = 0xA5104, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -69,46 +76,6 @@ struct apc_infra_peri_dom_4 { unsigned char d_permission[4]; }; -#define DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - (unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \ - (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, - -#define DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3) \ - DAPC_PERM_ATTR_4(DEV_NAME, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) - -#define DAPC_PERM_ATTR_16(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \ - PERM_ATTR2, PERM_ATTR3, \ - PERM_ATTR4, PERM_ATTR5, \ - PERM_ATTR6, PERM_ATTR7) \ - DAPC_PERM_ATTR_8(DEV_NAME, PERM_ATTR8, PERM_ATTR9, \ - PERM_ATTR10, PERM_ATTR11, \ - PERM_ATTR12, PERM_ATTR13, \ - PERM_ATTR14, PERM_ATTR15) - -#define FORBIDDEN3 FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN7 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN12 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN -#define FORBIDDEN13 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN -#define FORBIDDEN15 FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, \ - FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN - enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 16, DOM_NUM_INFRA_AO_SYS1 = 4, @@ -144,6 +111,10 @@ enum devapc_cfg_index { DEFINE_BIT(CPU_EB_SEC, 1) DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 1 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 19, 16) /* 2 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 11, 8) /* 1 */ /* PERI_PAR */ DEFINE_BIT(SSUSB_SEC, 21) @@ -153,6 +124,9 @@ DEFINE_BIT(SSUSB_P1_1_SEC, 2) DEFINE_BIT(SSUSB_P2_SEC, 3) DEFINE_BIT(SSUSB_P3_SEC, 4) +DEFINE_BITFIELD(PCIE0_DOM, 11, 8) /* 17 */ +DEFINE_BITFIELD(PCIE1_DOM, 19, 16) /* 18 */ + /* Domain Remap */ DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_0, 3, 0) DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_1, 7, 4) @@ -168,11 +142,13 @@ DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_1, 5, 3) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_2, 8, 6) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_3, 11, 9) DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_4, 14, 12) +DEFINE_BITFIELD(THREE_BIT_DOM_REMAP_5, 17, 15) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) -DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_4, 9, 8) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_5, 11, 10) #endif /* SOC_MEDIATEK_MT8195_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h index 0e1b62c9ea..11efbe1475 100644 --- a/src/soc/mediatek/mt8195/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h @@ -10,63 +10,10 @@ #include #include +#include #include -#define DRAMC_PARAM_HEADER_VERSION 7 - -enum DRAMC_PARAM_STATUS_CODES { - DRAMC_SUCCESS = 0, - DRAMC_ERR_INVALID_VERSION, - DRAMC_ERR_INVALID_SIZE, - DRAMC_ERR_INVALID_FLAGS, - DRAMC_ERR_RECALIBRATE, - DRAMC_ERR_INIT_DRAM, - DRAMC_ERR_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_FAST_CALIBRATION, -}; - -enum DRAMC_PARAM_FLAGS { - DRAMC_FLAG_HAS_SAVED_DATA = 0x0001, -}; - -enum SDRAM_DVFS_FLAG { - DRAMC_DISABLE_DVFS, - DRAMC_ENABLE_DVFS, -}; - -enum SDRAM_DDR_TYPE { - DDR_TYPE_DISCRETE, - DDR_TYPE_EMCP, -}; - -enum SDRAM_DDR_GEOMETRY_TYPE { - DDR_TYPE_2CH_2RK_4GB_2_2, - DDR_TYPE_2CH_2RK_6GB_3_3, - DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, - DDR_TYPE_2CH_1RK_4GB_4_0, - DDR_TYPE_2CH_2RK_6GB_2_4, - DDR_TYPE_2CH_2RK_8GB_4_4, -}; - -enum SDRAM_VOLTAGE_TYPE { - SDRAM_VOLTAGE_NVCORE_NVDRAM, - SDRAM_VOLTAGE_HVCORE_HVDRAM, - SDRAM_VOLTAGE_LVCORE_LVDRAM, -}; - -struct dramc_param_header { - u16 version; /* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */ - u16 size; /* size of whole dramc_param, update in the coreboot */ - u16 status; /* DRAMC_PARAM_STATUS_CODES, update in the dram blob */ - u16 flags; /* DRAMC_PARAM_FLAGS, update in the dram blob */ -}; - -struct sdram_info { - u32 ddr_type; /* SDRAM_DDR_TYPE */ - u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ -}; +#define DRAMC_PARAM_HEADER_VERSION 8 struct sdram_params { u32 rank_num; @@ -115,23 +62,6 @@ struct sdram_params { u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; }; -struct emi_mdl { - u32 cona_val; - u32 conh_val; - u32 conf_val; - u32 chn_cona_val; -}; - -struct ddr_base_info { - u32 config_dvfs; /* SDRAM_DVFS_FLAG */ - struct sdram_info sdram; - u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ - u32 support_ranks; - u64 rank_size[RANK_MAX]; - struct emi_mdl emi_config; - DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; -}; - struct dramc_data { struct ddr_base_info ddr_info; struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h index 743faa1e53..bbdc9e88b5 100644 --- a/src/soc/mediatek/mt8195/include/soc/i2c.h +++ b/src/soc/mediatek/mt8195/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8195_I2C_H #include +#include /* I2C Register */ struct mt_i2c_regs { @@ -52,7 +53,10 @@ enum { I2C7, }; +#define I2C_BUS_NUMBER 8 #define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); diff --git a/src/soc/mediatek/mt8195/include/soc/mcucfg.h b/src/soc/mediatek/mt8195/include/soc/mcucfg.h index bb39096636..3e99e00c91 100644 --- a/src/soc/mediatek/mt8195/include/soc/mcucfg.h +++ b/src/soc/mediatek/mt8195/include/soc/mcucfg.h @@ -964,6 +964,6 @@ struct mt8195_mcucfg_regs { check_member(mt8195_mcucfg_regs, cpu_plldiv_cfg0, 0x22a0); check_member(mt8195_mcucfg_regs, bus_plldiv_cfg, 0x22e0); -static struct mt8195_mcucfg_regs *const mt8195_mcucfg = (void *)MCUCFG_BASE; +static struct mt8195_mcucfg_regs *const mtk_mcucfg = (void *)MCUCFG_BASE; #endif /* SOC_MEDIATEK_MT8195_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index fb7d17fb54..945852a560 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -6,7 +6,6 @@ #include #include #include -#include #include /* SPM READ/WRITE CFG */ diff --git a/src/soc/mediatek/mt8195/include/soc/timer.h b/src/soc/mediatek/mt8195/include/soc/timer.h index da073e1b7a..d2959bf874 100644 --- a/src/soc/mediatek/mt8195/include/soc/timer.h +++ b/src/soc/mediatek/mt8195/include/soc/timer.h @@ -5,16 +5,4 @@ #include -enum { - TIE_0_EN = 1 << 3, - COMP_15_EN = 1 << 10, - COMP_20_EN = 1 << 11, - COMP_25_EN = 1 << 12, - - COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN, - - COMP_15_MASK = COMP_15_EN, - COMP_20_MASK = COMP_20_EN | TIE_0_EN, - COMP_25_MASK = COMP_20_EN | COMP_25_EN, -}; #endif diff --git a/src/soc/mediatek/mt8195/include/soc/tracker.h b/src/soc/mediatek/mt8195/include/soc/tracker.h new file mode 100644 index 0000000000..293ce3ca7f --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/tracker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_TRACKER_H +#define SOC_MEDIATEK_MT8195_TRACKER_H + +#include + +#endif diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h index e39ec3841d..c3b3c586f6 100644 --- a/src/soc/mediatek/mt8195/include/soc/usb.h +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya, 0x800); check_member(ssusb_sif_port, u3phya_da, 0x900); check_member(ssusb_sif_port, reserved2, 0xa00); -#define USB_PORT_NUMBER 1 +DEFINE_BIT(AUTO_LOAD_DIS, 12) +DEFINE_BITFIELD(TX_IMP_CAL, 28, 24) +DEFINE_BIT(TX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(RX_IMP_CAL, 28, 24) +DEFINE_BIT(RX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(INTR_CAL, 15, 10) + +#define TX_IMP_MASK 0x1F +#define TX_IMP_SHIFT 0 +#define RX_IMP_MASK 0x3E0 +#define RX_IMP_SHIFT 5 +#define INTR_CAL_MASK 0xFC00 +#define INTR_CAL_SHIFT 10 + +#define USB_PHY_SETTING_REG 0x11C10184 +#define USB_PORT_NUMBER 1 #endif diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c deleted file mode 100644 index de6e8bcdf9..0000000000 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) -DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) - -void mtk_soc_disable_l2c_sram(void) -{ - unsigned long v; - - SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); - dsb(); - - __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); - v |= (0xf << 4); - __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); - dsb(); - - do { - __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); - } while (((v >> 0x4) & 0xf) != 0xf); - - SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, - MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); - dsb(); -} - -/* mtk_soc_after_dram is called in romstage */ -void mtk_soc_after_dram(void) -{ - mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), - NONSECURE_UNCACHED_MEM); -} diff --git a/src/soc/mediatek/mt8195/msdc.c b/src/soc/mediatek/mt8195/msdc.c new file mode 100644 index 0000000000..bbfeaa6c81 --- /dev/null +++ b/src/soc/mediatek/mt8195/msdc.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 17, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) + +#define MSDC0_BASE 0x11230000 +#define MSDC0_TOP_BASE 0x11f50000 + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053d0, + MSDC1_GPIO_MODE1_BASE = 0x100053e0, +}; + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), + GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), + GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), + GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), + GPIO(EMMC_CMD), GPIO(EMMC_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(EMMC_DSL), GPIO(EMMC_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +} + +void mtk_msdc_configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); + + mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST); + + if (CONFIG(BOARD_GOOGLE_CHERRY)) + mt6360_init(I2C7); + + mainboard_enable_regulator(MTK_REGULATOR_VCCQ, 1); + mainboard_enable_regulator(MTK_REGULATOR_VCC, 1); +} diff --git a/src/soc/mediatek/mt8195/mt6360.c b/src/soc/mediatek/mt8195/mt6360.c index 142e244e74..729478e521 100644 --- a/src/soc/mediatek/mt8195/mt6360.c +++ b/src/soc/mediatek/mt8195/mt6360.c @@ -4,7 +4,6 @@ #include #include #include -#include static struct mt6360_i2c_data i2c_data[] = { [MT6360_INDEX_LDO] = { diff --git a/src/soc/mediatek/mt8195/mt6691.c b/src/soc/mediatek/mt8195/mt6691.c index 3f224215ef..3b3ccf1623 100644 --- a/src/soc/mediatek/mt8195/mt6691.c +++ b/src/soc/mediatek/mt8195/mt6691.c @@ -65,7 +65,7 @@ void mt6691_probe(uint8_t i2c_num) { /* Check device ID is MT6691 */ if (!get_mt6691_chip_id(i2c_num)) { - printk(BIOS_ERR, "ERROR: unknown MT6691 chip_id\n"); + printk(BIOS_ERR, "unknown MT6691 chip_id\n"); return; } /* Slew rate 12mV */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 8fd424dc49..df4ae3039d 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -707,13 +707,13 @@ void mt_pll_init(void) } /* MCUCFG CLKMUX */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); /* enable infrasys DCM */ setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21); @@ -765,7 +765,7 @@ void mt_pll_init(void) void mt_pll_raise_little_cpu_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable armpll_ll frequency output */ clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8195_PLL_EN); @@ -778,13 +778,13 @@ void mt_pll_raise_little_cpu_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to armpll_ll */ - clrsetbits32(&mt8195_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_raise_cci_freq(u32 freq) { /* switch clock source to intermediate clock */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); /* disable ccipll frequency output */ clrbits32(plls[APMIXED_CCIPLL].reg, MT8195_PLL_EN); @@ -797,7 +797,7 @@ void mt_pll_raise_cci_freq(u32 freq) udelay(PLL_EN_DELAY); /* switch clock source back to ccipll */ - clrsetbits32(&mt8195_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); + clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); } void mt_pll_set_tvd_pll1_freq(u32 freq) diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 20bd226cc9..d28f668579 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -9,7 +10,6 @@ #include #include #include -#include #include #include @@ -28,6 +28,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); dapc_init(); + apusys_init(); mcupm_init(); sspm_init(); @@ -36,7 +37,6 @@ static void soc_init(struct device *dev) ufs_disable_refclk(); hdmi_low_power_setting(); - bustracker_init(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8195/spm.c b/src/soc/mediatek/mt8195/spm.c index 018063ce73..52b0fd38f2 100644 --- a/src/soc/mediatek/mt8195/spm.c +++ b/src/soc/mediatek/mt8195/spm.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #define SPM_SYSTEM_BASE_OFFSET 0x40000000 diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 7b6347e605..b3f00a97cc 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -10,3 +10,31 @@ void mtk_usb_prepare(void) setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); } + +void mtk_usb_adjust_phy_shift(void) +{ + u32 phy_set_val, write_val; + struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE); + + SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, + AUTO_LOAD_DIS, 1); + + phy_set_val = read32((void *)USB_PHY_SETTING_REG); + + /* TX imp */ + write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal0, + TX_IMP_CAL, write_val, + TX_IMP_CAL_EN, 1); + + /* RX imp */ + write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal1, + RX_IMP_CAL, write_val, + RX_IMP_CAL_EN, 1); + + /* Intr_cal */ + write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT; + SET32_BITFIELDS(&phy->u3phya.phya_reg0, + INTR_CAL, write_val); +} diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c new file mode 100644 index 0000000000..fcee3db21a --- /dev/null +++ b/src/soc/mediatek/mt8195/wdt.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define MTK_WDT_CLR_STATUS 0x230001FF + +void mtk_wdt_clr_status(void) +{ + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); +} diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index ac61c54688..9f10b388fc 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -115,7 +115,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t /* wait for HC to reset */; if (!timeout) { - printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb); + printk(BIOS_ERR, "EHCI(%p) reset timeout", usb); return; } diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 2cf16b068b..9d3422786a 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -220,10 +220,10 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, case 4: reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + __fallthrough; case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + __fallthrough; case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; @@ -581,8 +581,6 @@ static void dump_sor_reg(struct tegra_dc_sor_data *sor) DUMP_REG(NV_SOR_DP_SPARE(0)); DUMP_REG(NV_SOR_DP_SPARE(1)); DUMP_REG(NV_SOR_DP_TPG); - - return; } #endif @@ -893,10 +891,10 @@ void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) case 4: val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + __fallthrough; case 2: val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + __fallthrough; case 1: val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index f5fdb8d197..62bdbdadf9 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -5,10 +5,10 @@ #include #include #include +#include #include #include #include -#include static void enable_cache(void) { diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index a2b06b160e..f3bc208128 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -1575,7 +1575,7 @@ void dp_display_startup(struct device *dev) __func__, disp_ctrl); if (disp_ctrl == NULL) { - printk(BIOS_ERR, "Error: No dc is assigned by dt.\n"); + printk(BIOS_ERR, "No dc is assigned by dt.\n"); return; } diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index 5026ef4b58..b9bbea3756 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -963,7 +963,7 @@ void dsi_display_startup(struct device *dev) __func__, disp_ctrl); if (disp_ctrl == NULL) { - printk(BIOS_ERR, "Error: No dc is assigned by dt.\n"); + printk(BIOS_ERR, "No dc is assigned by dt.\n"); return; } diff --git a/src/soc/nvidia/tegra210/funitcfg.c b/src/soc/nvidia/tegra210/funitcfg.c index 0ca43cd06d..ba6408f702 100644 --- a/src/soc/nvidia/tegra210/funitcfg.c +++ b/src/soc/nvidia/tegra210/funitcfg.c @@ -140,7 +140,7 @@ void soc_configure_funits(const struct funit_cfg * const entries, size_t num) int funit_usb = is_usb(entry->funit_index); if (entry->funit_index >= FUNIT_INDEX_MAX) { - printk(BIOS_ERR, "Error: Index out of bounds\n"); + printk(BIOS_ERR, "Index out of bounds\n"); continue; } diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h deleted file mode 100644 index 5bc3da054f..0000000000 --- a/src/soc/nvidia/tegra210/include/soc/verstage.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ -#define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ - -#include - -#endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 9b50d93996..3b0c128d49 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -222,9 +222,10 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor, case 4: reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + fallthrough; case 2: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; + fallthrough; case 1: reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; @@ -579,8 +580,6 @@ static void dump_sor_reg(struct tegra_dc_sor_data *sor) DUMP_REG(NV_SOR_DP_SPARE(0)); DUMP_REG(NV_SOR_DP_SPARE(1)); DUMP_REG(NV_SOR_DP_TPG); - - return; } #endif @@ -891,10 +890,10 @@ void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor) case 4: val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO | NV_SOR_DP_PADCTL_PD_TXD_2_NO); - /* fall through */ + fallthrough; case 2: val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO; - /* fall through */ + fallthrough; case 1: val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO; break; diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index 09cd95c88a..e06a954f3c 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -27,7 +27,7 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, return CB_SUCCESS; udelay(1); } - printk(BIOS_ERR, "ERROR: Failed to enable clock, register val: 0x%x\n", + printk(BIOS_ERR, "Failed to enable clock, register val: 0x%x\n", read32(cbcr_addr)); return CB_ERR; } @@ -45,7 +45,7 @@ enum cb_err clock_enable(void *cbcr_addr) return CB_SUCCESS; udelay(1); } - printk(BIOS_ERR, "ERROR: Failed to enable clock, register val: 0x%x\n", + printk(BIOS_ERR, "Failed to enable clock, register val: 0x%x\n", read32(cbcr_addr)); return CB_ERR; } @@ -207,7 +207,7 @@ enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, /* Wait for Lock Detection */ if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: PLL did not lock!\n"); + printk(BIOS_ERR, "PLL did not lock!\n"); return CB_ERR; } } @@ -227,7 +227,7 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg) setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } @@ -249,7 +249,7 @@ enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) setbits32(cfg->reg_opmode, PLL_RUN_MODE); if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + printk(BIOS_ERR, "CPU PLL did not lock!\n"); return CB_ERR; } diff --git a/src/soc/qualcomm/common/gpio.c b/src/soc/qualcomm/common/gpio.c index 1ed8e8a04b..5053f3ba5f 100644 --- a/src/soc/qualcomm/common/gpio.c +++ b/src/soc/qualcomm/common/gpio.c @@ -16,7 +16,9 @@ void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) | ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | - ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT) | + ((read32(®s->cfg) & GPIO_CFG_EGPIO_BMSK) + << GPIO_CFG_EGPIO_SHFT); write32(®s->cfg, reg_val); } diff --git a/src/soc/qualcomm/common/include/soc/gpio_common.h b/src/soc/qualcomm/common/include/soc/gpio_common.h index 20f947a326..18cd040269 100644 --- a/src/soc/qualcomm/common/include/soc/gpio_common.h +++ b/src/soc/qualcomm/common/include/soc/gpio_common.h @@ -21,6 +21,7 @@ enum gpio_tlmm_bmsk { GPIO_CFG_PULL_BMSK = 0x3, GPIO_CFG_FUNC_BMSK = 0xF, GPIO_CFG_DRV_BMSK = 0x7, + GPIO_CFG_EGPIO_BMSK = 0x800, }; /* GPIO TLMM INTR: Shift */ @@ -35,6 +36,7 @@ enum gpio_tlmm_shft { GPIO_CFG_FUNC_SHFT = 2, GPIO_CFG_DRV_SHFT = 6, GPIO_CFG_OE_SHFT = 9, + GPIO_CFG_EGPIO_SHFT = 1, }; /* GPIO IO: Shift */ diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 953acc2657..75602665ce 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -24,5 +24,7 @@ DECLARE_REGION(dram_modem_extra) DECLARE_REGION(dram_wlan) DECLARE_REGION(dram_wpss) DECLARE_REGION(shrm) +DECLARE_REGION(dram_cpucp) +DECLARE_REGION(dram_modem) #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h new file mode 100644 index 0000000000..fc1721afa9 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +struct ss_usb_phy_reg { + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; +}; + +void ss_qmp_phy_init(void); diff --git a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h new file mode 100644 index 0000000000..dd4a736bd0 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + + +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 + +#define HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +struct hs_usb_phy_reg { + struct usb_qusb_phy_pll *phy_pll; + struct usb_qusb_phy_dig *phy_dig; + struct usb_board_data *board_data; + u32 efuse_offset; +}; diff --git a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h new file mode 100644 index 0000000000..de0b385c0b --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +struct usb_board_data { + /*Register values going to override from the boardfile*/ + u8 parameter_override_x0; + u8 parameter_override_x1; + u8 parameter_override_x2; + u8 parameter_override_x3; +}; + +struct hs_usb_phy_reg { + u8 rsvd1[60]; + u32 utmi_ctrl0; + u32 utmi_ctrl1; + u8 rsvd2[12]; + u32 utmi_ctrl5; + u32 hs_phy_ctrl_common0; + u32 hs_phy_ctrl_common1; + u32 hs_phy_ctrl_common2; + u32 hs_phy_ctrl1; + u32 hs_phy_ctrl2; + u8 rsvd3[4]; + u32 hs_phy_override_x0; + u32 hs_phy_override_x1; + u32 hs_phy_override_x2; + u32 hs_phy_override_x3; + u8 rsvd4[24]; + u32 cfg0; + u8 rsvd5[8]; + u32 refclk_ctrl; +}; +check_member(hs_usb_phy_reg, utmi_ctrl0, 0x03c); +check_member(hs_usb_phy_reg, utmi_ctrl1, 0x040); +check_member(hs_usb_phy_reg, utmi_ctrl5, 0x050); +check_member(hs_usb_phy_reg, hs_phy_ctrl2, 0x064); +check_member(hs_usb_phy_reg, hs_phy_override_x0, 0x06c); +check_member(hs_usb_phy_reg, hs_phy_override_x3, 0x078); +check_member(hs_usb_phy_reg, cfg0, 0x094); +check_member(hs_usb_phy_reg, refclk_ctrl, 0x0a0); diff --git a/src/soc/qualcomm/common/include/soc/usb/usb_common.h b/src/soc/qualcomm/common/include/soc/usb/usb_common.h new file mode 100644 index 0000000000..662d4889a6 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/usb_common.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "qmp_usb_phy.h" + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +void hs_usb_phy_init(void *board_data); +void setup_usb_host0(void *board_data); + +/* Call reset_ before setup_ */ +void reset_usb0(void); diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c similarity index 63% rename from src/soc/qualcomm/sc7180/usb.c rename to src/soc/qualcomm/common/usb/qmpv3_usb_phy.c index 370fa66911..c1782be790 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/common/usb/qmpv3_usb_phy.c @@ -1,54 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include -#include -#include -#include -#include #include - -struct usb_qusb_phy_dig { - u8 rsvd1[16]; - u32 pwr_ctrl1; - u32 pwr_ctrl2; - u8 rsvd2[8]; - u32 imp_ctrl1; - u32 imp_ctrl2; - u8 rsvd3[20]; - u32 chg_ctrl2; - u32 tune1; - u32 tune2; - u32 tune3; - u32 tune4; - u32 tune5; - u8 rsvd4[44]; - u32 debug_ctrl2; - u8 rsvd5[28]; - u32 debug_stat5; -}; -check_member(usb_qusb_phy_dig, tune5, 0x50); -check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); -check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); - -struct usb_qusb_phy_pll { - u8 rsvd0[4]; - u32 analog_controls_two; - u8 rsvd1[36]; - u32 cmode; - u8 rsvd2[132]; - u32 dig_tim; - u8 rsvd3[204]; - u32 lock_delay; - u8 rsvd4[4]; - u32 clock_inverters; - u8 rsvd5[4]; - u32 bias_ctrl_1; - u32 bias_ctrl_2; -}; -check_member(usb_qusb_phy_pll, cmode, 0x2C); -check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); -check_member(usb_qusb_phy_pll, dig_tim, 0xB4); +#include +#include /* Only for QMP V3 PHY - QSERDES COM registers */ struct usb3_phy_qserdes_com_reg_layout { @@ -290,41 +244,6 @@ static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = (void *)QMP_PHY_PCS_REG_BASE; -struct usb_dwc3 { - u32 sbuscfg0; - u32 sbuscfg1; - u32 txthrcfg; - u32 rxthrcfg; - u32 ctl; - u32 pmsts; - u32 sts; - u32 uctl1; - u32 snpsid; - u32 gpio; - u32 uid; - u32 uctl; - u64 buserraddr; - u64 prtbimap; - u8 reserved1[32]; - u32 dbgfifospace; - u32 dbgltssm; - u32 dbglnmcc; - u32 dbgbmu; - u32 dbglspmux; - u32 dbglsp; - u32 dbgepinfo0; - u32 dbgepinfo1; - u64 prtbimap_hs; - u64 prtbimap_fs; - u8 reserved2[112]; - u32 usb2phycfg; - u8 reserved3[124]; - u32 usb2phyacc; - u8 reserved4[60]; - u32 usb3pipectl; - u8 reserved5[60]; -}; -check_member(usb_dwc3, usb3pipectl, 0x1c0); static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, @@ -434,33 +353,7 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, }; -struct usb_dwc3_cfg { - struct usb_dwc3 *usb_host_dwc3; - struct usb_qusb_phy_pll *qusb_phy_pll; - struct usb_qusb_phy_dig *qusb_phy_dig; - /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; - struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; - - u32 *usb3_bcr; - u32 *qusb2phy_bcr; - u32 *gcc_usb3phy_bcr_reg; - u32 *gcc_qmpphy_bcr_reg; - struct usb_board_data *board_data; - u32 efuse_offset; -}; - -static struct usb_dwc3_cfg usb_port0 = { - .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, - .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, - .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, +struct ss_usb_phy_reg qmp_v3_usb_phy = { .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), .tx_tbl = qmp_v3_usb3_tx_tbl, @@ -470,155 +363,8 @@ static struct usb_dwc3_cfg usb_port0 = { .pcs_tbl = qmp_v3_usb3_pcs_tbl, .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, - .usb3_bcr = &gcc->usb30_prim_bcr, - .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, - .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, - .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, - .efuse_offset = 25, }; -static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; - -static void reset_usb(struct usb_dwc3_cfg *dwc3) -{ - /* Assert Core reset */ - clock_reset_bcr(dwc3->usb3_bcr, 1); - - /* Assert QUSB PHY reset */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 1); - - /* Assert QMP PHY reset */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); -} - -void reset_usb0(void) -{ - /* Before Resetting PHY, put Core in Reset */ - printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); - - reset_usb(&usb_port0); -} - -/* - * Update board specific PHY tuning override values that specified from - * board file. - */ -static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) -{ - /* Override preemphasis value */ - write32(&dwc3->qusb_phy_dig->tune1, - dwc3->board_data->port_tune1); - - /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - dwc3->board_data->pll_bias_control_2); - - /* Override IMP_RES_OFFSET value */ - write32(&dwc3->qusb_phy_dig->imp_ctrl1, - dwc3->board_data->imp_ctrl1); -} - -/* - * Fetches HS Tx tuning value from efuse register and sets the - * QUSB2PHY_PORT_TUNE1/2 register. - * For error case, skip setting the value and use the default value. - */ -static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) -{ - /* - * Efuse registers 3 bit value specifies tuning for HSTX - * output current in TUNE1 Register. Hence Extract 3 bits from - * EFUSE at correct position. - */ - - const int efuse_bits = 3; - int bit_pos = dwc3->efuse_offset; - - u32 bit_mask = (1 << efuse_bits) - 1; - u32 tune_val = - (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) - & bit_mask; - /* - * if efuse reg is updated (i.e non-zero) then use it to program - * tune parameters. - */ - if (tune_val) - clrsetbits32(&dwc3->qusb_phy_dig->tune1, - PORT_TUNE1_MASK, tune_val << 4); -} - -static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) -{ - write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); - /* IMP_CTRL1: Control the impedance reduction */ - write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); - /* IMP_CTRL2: Impedance offset/mapping slope */ - write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); - write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); - /* - * TUNE1: Sets HS Impedance to approx 45 ohms - * then override with efuse value. - */ - write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); - /* TUNE2: Tuning for HS Disconnect Level */ - write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); - /* TUNE3: Tune squelch range */ - write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); - /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ - write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); - write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); - - if (dwc3->board_data) { - /* Override board specific PHY tuning values */ - qusb2_phy_override_phy_params(dwc3); - - /* Set efuse value for tuning the PHY */ - qusb2_phy_set_tune_param(dwc3); - } -} - -static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) -{ - /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_pll->analog_controls_two, - QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); - write32(&dwc3->qusb_phy_pll->clock_inverters, - QUSB2PHY_PLL_CLOCK_INVERTERS); - write32(&dwc3->qusb_phy_pll->cmode, - QUSB2PHY_PLL_CMODE); - write32(&dwc3->qusb_phy_pll->lock_delay, - QUSB2PHY_PLL_LOCK_DELAY); - write32(&dwc3->qusb_phy_pll->dig_tim, - QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); - write32(&dwc3->qusb_phy_pll->bias_ctrl_1, - QUSB2PHY_PLL_BIAS_CONTROL_1); - write32(&dwc3->qusb_phy_pll->bias_ctrl_2, - QUSB2PHY_PLL_BIAS_CONTROL_2); - - tune_phy(dwc3, dwc3->qusb_phy_dig); - - /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); - - write32(&dwc3->qusb_phy_dig->debug_ctrl2, - DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); - - /* - * DEBUG_STAT5: wait for 160uS for PLL lock; - * vstatus[0] changes from 0 to 1. - */ - long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & - VSTATUS_PLL_LOCK_STATUS_MASK); - if (!lock_us) - printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); - else - printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", - lock_us); -} - static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], int num) { @@ -632,96 +378,38 @@ static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], write32(t->address, t->val); } -static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +void ss_qmp_phy_init(void) { + struct ss_usb_phy_reg *ss_phy_reg; + + ss_phy_reg = &qmp_v3_usb_phy; /* power up USB3 PHY */ - write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); /* Serdes configuration */ - qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, + ss_phy_reg->serdes_tbl_num); /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); - qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); - qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); /* perform software reset of PCS/Serdes */ - write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); /* start PCS/Serdes to operation mode */ - write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); /* * Wait for PHY initialization to be done * PCS_STATUS: wait for 1ms for PHY STATUS; * SW can continuously check for PHYSTATUS = 1.b0. */ - long lock_us = wait_us(1000, - !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + long lock_us = wait_us(10000, + !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & USB3_PCS_PHYSTATUS)); if (!lock_us) - printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + printk(BIOS_ERR, "QMP PHY PLL LOCK fails:\n"); else printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", lock_us); } - -static void setup_dwc3(struct usb_dwc3 *dwc3) -{ - /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits32(&dwc3->usb3pipectl, - DWC3_GUSB3PIPECTL_DELAYP1TRANS, - DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - - /* - * Configure USB phy interface of DWC3 core. - * 1. Select UTMI+ PHY with 16-bit interface. - * 2. Set USBTRDTIM to the corresponding value - * according to the UTMI+ PHY interface. - */ - clrsetbits32(&dwc3->usb2phycfg, - (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | - DWC3_GUSB2PHYCFG_PHYIF_MASK), - (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | - DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | - DWC3_GCTL_DISSCRAMBLE), - DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); - - /* configure controller in Host mode */ - clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), - DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); - printk(BIOS_SPEW, "Configure USB in Host mode\n"); -} - -/* Initialization of DWC3 Core and PHY */ -static void setup_usb_host(struct usb_dwc3_cfg *dwc3, - struct usb_board_data *board_data) -{ - dwc3->board_data = board_data; - - /* Clear core reset. */ - clock_reset_bcr(dwc3->usb3_bcr, 0); - - /* Clear QUSB PHY reset. */ - clock_reset_bcr(dwc3->qusb2phy_bcr, 0); - - /* Initialize QUSB PHY */ - hs_qusb_phy_init(dwc3); - - /* Clear QMP PHY resets. */ - clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); - clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); - - /* Initialize QMP PHY */ - ss_qmp_phy_init(dwc3); - - setup_dwc3(dwc3->usb_host_dwc3); - - printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); -} - -void setup_usb_host0(struct usb_board_data *board_data) -{ - printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); - setup_usb_host(&usb_port0, board_data); -} diff --git a/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c new file mode 100644 index 0000000000..23ab75ad2a --- /dev/null +++ b/src/soc/qualcomm/common/usb/qmpv4_usb_phy.c @@ -0,0 +1,411 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + + +/* Only for QMP V4 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1_mode0; + u32 com_ssc_step_size2_mode0; + u32 com_ssc_step_size3_mode0; + u32 com_ssc_step_size1_mode1; + u32 com_ssc_step_size2_mode1; + u32 com_ssc_step_size3_mode1; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[4]; + u32 com_cmn_iptrim; + u8 _reserved4[16]; + u32 com_cp_ctrl_mode0; + u32 com_cp_ctrl_mode1; + u32 com_pll_rctrl_mode0; + u32 com_pll_rctrl_mode1; + u32 com_pll_cctrl_mode0; + u32 com_pll_cctrl_mode1; + u8 _reserved6[8]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp1_mode1; + u32 com_lock_cmp2_mode1; + u32 com_dec_start_mode0; + u8 _reserved8[4]; + u32 com_dec_start_mode1; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u32 com_div_frac_start1_mode1; + u32 com_div_frac_start2_mode1; + u32 com_div_frac_start3_mode1; + u8 _reserved10[8]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[24]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u32 com_vco_tune1_mode1; + u32 com_vco_tune2_mode1; + u8 _reserved12[52]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[12]; + u32 com_coreclk_div_mode0; + u32 com_coreclk_div_mode1; + u8 _reserved14[4]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; + u8 _reserved15[36]; + u32 com_bin_vcocal_cmp_code1_mode0; + u32 com_bin_vcocal_cmp_code2_mode0; + u32 com_bin_vcocal_cmp_code1_mode1; + u32 com_bin_vcocal_cmp_code2_mode1; + u32 com_bin_vcocal_hsclk_sel; +}; + +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x044); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x058); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x074); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x094); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x0a0); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0bc); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0cc); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0ec); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x010c); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x168); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x174); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x184); +check_member(usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_hsclk_sel, 0x1bc); + +/* Only for QMP V4 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[52]; + u32 tx_res_code_lane_tx; + u32 tx_res_code_lane_rx; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[64]; + u32 tx_lane_mode_1; + u8 _reserved3[20]; + u32 tx_rcv_detect_lvl_2; + u8 _reserved4[100]; + u32 tx_pi_qec_ctrl; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x03c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x040); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x09c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x104); + +/* Only for QMP V4 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[20]; + u32 rx_ucdr_so_gain; + u8 _reserved2[24]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturation_and_enable; + u8 _reserved3[4]; + u32 rx_ucdr_fastlock_count_low; + u32 rx_ucdr_fastlock_count_high; + u32 rx_ucdr_pi_controls; + u8 _reserved4[4]; + u32 rx_ucdr_sb2_thresh1; + u32 rx_ucdr_sb2_thresh2; + u32 rx_ucdr_sb2_gain1; + u32 rx_ucdr_sb2_gain2; + u8 _reserved12[4]; + u32 rx_aux_data_tcoarse_tfine; + u8 _reserved5[112]; + u32 rx_vga_cal_cntrl1; + u32 rx_vga_cal_cntrl2; + u32 rx_gm_cal; + u8 _reserved6[12]; + u32 rx_rx_equ_adaptor_cntrl2; + u32 rx_rx_equ_adaptor_cntrl3; + u32 rx_rx_equ_adaptor_cntrl4; + u32 rx_rx_idac_tsettle_low; + u32 rx_rx_idac_tsettle_high; + u8 _reserved7[16]; + u32 rx_rx_eq_offset_adaptor_cntrl1; + u8 _reserved8[8]; + u32 rx_sigdet_cntrl; + u8 _reserved9[4]; + u32 rx_sigdet_deglitch_cntrl; + u8 _reserved10[72]; + u32 rx_rx_mode_00_low; + u32 rx_rx_mode_00_high; + u32 rx_rx_mode_00_high2; + u32 rx_rx_mode_00_high3; + u32 rx_rx_mode_00_high4; + u32 rx_rx_mode_01_low; + u32 rx_rx_mode_01_high; + u32 rx_rx_mode_01_high2; + u32 rx_rx_mode_01_high3; + u32 rx_rx_mode_01_high4; + u8 _reserved11[28]; + u32 rx_dfe_en_timer; + u32 rx_dfe_ctle_post_cal_offset; + u32 rx_dcc_ctrl1; + u8 _reserved13[4]; + u32 rx_vth_code; +}; + +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1bc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1c4); + +/* Only for QMP V4 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u8 _reserved0[16]; + u32 pcs_ready_status; + u8 _reserved1[40]; + u32 pcs_power_down_control; + u32 pcs_start_control; + u8 _reserved2[124]; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u8 _reserved3[8]; + u32 pcs_lock_detect_config6; + u32 pcs_refgen_req_config1; + u8 _reserved4[168]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved5[36]; + u32 pcs_cdr_reset_time; + u8 _reserved6[12]; + u32 pcs_align_detect_config1; + u32 pcs_align_detect_config2; + u8 _reserved7[8]; + u32 pcs_pcs_tx_rx_config; + u8 _reserved8[8]; + u32 pcs_eq_config1; + u8 _reserved9[12]; + u32 pcs_eq_config5; + u8 _reserved10[296]; + u32 pcs_usb3_lfps_det_high_count_val; + u8 _reserved11[28]; + u32 pcs_usb3_rxeqtraining_dfe_time_s2; +}; + +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x0c8); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0); +check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x318); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x338); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; +static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode0, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode0, 0x07}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode1, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode1, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_cmn_iptrim, 0x20}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode1, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode1, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode1, 0x36}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x1a}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x14}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode1, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode1, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode1, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode1, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode1, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode1, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune1_mode1, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune2_mode1, 0x02}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x01}, + {&qserdes_com_reg_layout->com_coreclk_div_mode1, 0x08}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode0, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode0, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode1, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode1, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_hsclk_sel, 0x11}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_res_code_lane_tx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_rx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x11}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x02}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0xd5}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_pi_qec_ctrl, 0x40}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_so_gain, 0x06}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x2f}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturation_and_enable, 0x7f}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_low, 0xff}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_high, 0x0f}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_controls, 0x99}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh1, 0x04}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh2, 0x08}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain1, 0x05}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain2, 0x05}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl1, 0x54}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl2, 0x0c}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl3, 0x4a}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl4, 0x0a}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_low, 0xc0}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_high, 0x00}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adaptor_cntrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_sigdet_cntrl, 0x04}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_cntrl, 0x0e}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high2, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high3, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high4, 0x97}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_low, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high2, 0x5c}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high3, 0x7b}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high4, 0xb4}, + {&qserdes_rx_reg_layout->rx_dfe_en_timer, 0x04}, + {&qserdes_rx_reg_layout->rx_dfe_ctle_post_cal_offset, 0x38}, + {&qserdes_rx_reg_layout->rx_aux_data_tcoarse_tfine, 0xa0}, + {&qserdes_rx_reg_layout->rx_dcc_ctrl1, 0x0c}, + {&qserdes_rx_reg_layout->rx_gm_cal, 0x1f}, + {&qserdes_rx_reg_layout->rx_vth_code, 0x10}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[] = { + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd0}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x07}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x20}, + {&pcs_reg_layout->pcs_lock_detect_config6, 0x13}, + {&pcs_reg_layout->pcs_refgen_req_config1, 0x21}, + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xa9}, + {&pcs_reg_layout->pcs_cdr_reset_time, 0x0a}, + {&pcs_reg_layout->pcs_align_detect_config1, 0x88}, + {&pcs_reg_layout->pcs_align_detect_config2, 0x13}, + {&pcs_reg_layout->pcs_pcs_tx_rx_config, 0x0c}, + {&pcs_reg_layout->pcs_eq_config1, 0x4b}, + {&pcs_reg_layout->pcs_eq_config5, 0x10}, + {&pcs_reg_layout->pcs_usb3_lfps_det_high_count_val, 0xf8}, + {&pcs_reg_layout->pcs_usb3_rxeqtraining_dfe_time_s2, 0x07}, +}; + +struct ss_usb_phy_reg qmp_v4_usb_phy = { + .serdes_tbl = qmp_v4_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl), + .tx_tbl = qmp_v4_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl), + .rx_tbl = qmp_v4_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl), + .pcs_tbl = qmp_v4_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, +}; + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +void ss_qmp_phy_init(void) +{ + struct ss_usb_phy_reg *ss_phy_reg; + + ss_phy_reg = &qmp_v4_usb_phy; + + /* power up USB3 PHY */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, + ss_phy_reg->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(10000, + !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c new file mode 100644 index 0000000000..494f7cd3b3 --- /dev/null +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +struct hs_usb_phy_reg qusb_phy = { + .phy_pll = (void *)QUSB_PRIM_PHY_BASE, + + .phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + + .efuse_offset = 25, +}; + +static void qusb2_phy_override_phy_params(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* Override preemphasis value */ + write32(&hs_phy_reg->phy_dig->tune1, + hs_phy_reg->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + hs_phy_reg->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, + hs_phy_reg->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ + +static void qusb2_phy_set_tune_param(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = hs_phy_reg->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits32(&hs_phy_reg->phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct hs_usb_phy_reg *hs_phy_reg) +{ + write32(&hs_phy_reg->phy_dig->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&hs_phy_reg->phy_dig->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&hs_phy_reg->phy_dig->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&hs_phy_reg->phy_dig->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&hs_phy_reg->phy_dig->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&hs_phy_reg->phy_dig->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&hs_phy_reg->phy_dig->tune4, QUSB2PHY_PORT_TUNE4); + write32(&hs_phy_reg->phy_dig->tune5, QUSB2PHY_PORT_TUNE5); + + if (hs_phy_reg->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(hs_phy_reg); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(hs_phy_reg); + } +} + +void hs_usb_phy_init(void *board_data) +{ + struct hs_usb_phy_reg *hs_phy_reg; + + hs_phy_reg = &qusb_phy; + + hs_phy_reg->board_data = (struct usb_board_data *) board_data; + + /* PWR_CTRL: set the power down bit to disable the PHY */ + + setbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&hs_phy_reg->phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&hs_phy_reg->phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&hs_phy_reg->phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&hs_phy_reg->phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&hs_phy_reg->phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(hs_phy_reg); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&hs_phy_reg->phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c new file mode 100644 index 0000000000..1b2d869bc4 --- /dev/null +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define SLEEPM BIT(0) + +#define TERMSEL BIT(5) + +#define POR BIT(1) + +#define FSEL_MASK GENMASK(7, 5) +#define FSEL_DEFAULT (0x3 << 4) + +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define VREGBYPASS BIT(0) + +#define VBUSVLDEXT0 BIT(0) + +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +#define PARAM_OVRD_MASK 0xFF + +struct hs_usb_phy_reg *hs_phy_reg = (void *)HS_USB_PRIM_PHY_BASE; + +void hs_usb_phy_init(void *board_data) +{ + struct usb_board_data *override_data = + (struct usb_board_data *) board_data; + + clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + + clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, POR); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common0, FSEL_MASK, 0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, PLLBTUNE, PLLBTUNE); + + clrsetbits32(&hs_phy_reg->refclk_ctrl, REFCLK_SEL_MASK, + REFCLK_SEL_DEFAULT); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common1, VBUSVLDEXTSEL0, + VBUSVLDEXTSEL0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl1, VBUSVLDEXT0, VBUSVLDEXT0); + + if (board_data) { + clrsetbits32(&hs_phy_reg->hs_phy_override_x0, + PARAM_OVRD_MASK, override_data->parameter_override_x0); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x1, + PARAM_OVRD_MASK, override_data->parameter_override_x1); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x2, + PARAM_OVRD_MASK, override_data->parameter_override_x2); + + clrsetbits32(&hs_phy_reg->hs_phy_override_x3, + PARAM_OVRD_MASK, override_data->parameter_override_x3); + } + clrsetbits32(&hs_phy_reg->hs_phy_ctrl_common2, VREGBYPASS, VREGBYPASS); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + clrsetbits32(&hs_phy_reg->utmi_ctrl0, SLEEPM, SLEEPM); + + clrsetbits32(&hs_phy_reg->utmi_ctrl5, POR, 0); + + clrsetbits32(&hs_phy_reg->hs_phy_ctrl2, USB2_SUSPEND_N_SEL, 0); + + clrsetbits32(&hs_phy_reg->cfg0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + printk(BIOS_DEBUG, "USB HS PHY initialized\n"); +} diff --git a/src/soc/qualcomm/common/usb/usb.c b/src/soc/qualcomm/common/usb/usb.c new file mode 100644 index 0000000000..3a0c00327b --- /dev/null +++ b/src/soc/qualcomm/common/usb/usb.c @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb2phycfg, 0x100); +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, +}; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert HS PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ + +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + void *board_data) +{ + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize HS PHY */ + hs_usb_phy_init(board_data); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} +void setup_usb_host0(void *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} diff --git a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h b/src/soc/qualcomm/ipq40xx/include/soc/verstage.h deleted file mode 100644 index 779a90e5f5..0000000000 --- a/src/soc/qualcomm/ipq40xx/include/soc/verstage.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ -#define __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ - -#include - -#endif /* __SOC_QUALCOMM_IPQ40XX_INCLUDE_SOC_VERSTAGE_H__ */ diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 31677e460f..0893dfc687 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -298,7 +298,6 @@ static void write_force_cs(const struct spi_slave *slave, int assert) clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); - return; } /* @@ -372,7 +371,6 @@ static void enable_io_config(struct ipq_spi_slave *ds, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } - return; } /* diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index df565b4c0e..cbdc5b3251 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -29,7 +29,7 @@ romstage-y += watchdog.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c -romstage-y += usb.c +romstage-y += ../common/usb/usb.c romstage-y += carve_out.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c @@ -37,8 +37,10 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ramstage-y += soc.c ramstage-y += carve_out.c ramstage-y += ../common/aop_load_reset.c -ramstage-y += usb.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += ../common/usb/usb.c +ramstage-y += ../common/usb/qusb_phy.c +ramstage-y += ../common/usb/qmpv3_usb_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 4497b9c663..5741c54bce 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c index 15d36ed0b8..48dc2b395d 100644 --- a/src/soc/qualcomm/sc7180/display/dsi.c +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -100,7 +100,6 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) { uint16_t dst_format; uint8_t lane_en = 15; /* Enable 4 lanes by default */ - uint16_t hfp, hbp, vfp, vbp; switch (bpp) { case 16: @@ -115,23 +114,17 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) break; } - hfp = edid->mode.hso; - hbp = edid->mode.hbl - edid->mode.hso; - vfp = edid->mode.vso; - vbp = edid->mode.vbl - edid->mode.vso; - write32(&dsi0->video_mode_active_h, - ((edid->mode.ha + hbp) << 16) | - hbp); + ((edid->mode.ha + edid->mode.hbl - edid->mode.hso) << 16) | + (edid->mode.hbl - edid->mode.hso)); write32(&dsi0->video_mode_active_v, - ((edid->mode.va + vbp) << 16) | (vbp)); + ((edid->mode.va + edid->mode.vbl - edid->mode.vso) << 16) | + (edid->mode.vbl - edid->mode.vso)); write32(&dsi0->video_mode_active_total, - ((edid->mode.va + vfp + - vbp - 1) << 16) | - (edid->mode.ha + hfp + - hbp - 1)); + ((edid->mode.va + edid->mode.vbl - 1) << 16) | + (edid->mode.ha + edid->mode.hbl - 1)); write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16)); write32(&dsi0->video_mode_active_vsync, 0x0); diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c index 0e7f387c84..1fcfb79839 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c index ce46e8e880..95697603cc 100644 --- a/src/soc/qualcomm/sc7180/display/mdss.c +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h index 57a30220bf..112cac67fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h +++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h @@ -4,7 +4,6 @@ #define _SOC_DISPLAY_MDSS_REG_H_ #include -#include struct dsi_regs { uint32_t hw_version; diff --git a/src/soc/qualcomm/sc7180/include/soc/usb.h b/src/soc/qualcomm/sc7180/include/soc/usb.h deleted file mode 100644 index f3bc89ad9b..0000000000 --- a/src/soc/qualcomm/sc7180/include/soc/usb.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#include - -#ifndef _SC7180_USB_H_ -#define _SC7180_USB_H_ - -/* QSCRATCH_GENERAL_CFG register bit offset */ -#define PIPE_UTMI_CLK_SEL BIT(0) -#define PIPE3_PHYSTATUS_SW BIT(3) -#define PIPE_UTMI_CLK_DIS BIT(8) - -/* Global USB3 Control Registers */ -#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) -#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) -#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) -#define DWC3_GCTL_PRTCAP_OTG 3 -#define DWC3_GCTL_PRTCAP_HOST 1 - -/* Global USB2 PHY Configuration Register */ -#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) -#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) -#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) -#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) -#define USBTRDTIM_UTMI_8_BIT 9 -#define UTMI_PHYIF_8_BIT 0 - -#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) -#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) -#define DWC3_GCTL_DISSCRAMBLE (1 << 3) -#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) - -#define PORT_TUNE1_MASK 0xf0 - -/* QUSB2PHY_PWR_CTRL1 register related bits */ -#define POWER_DOWN BIT(0) - -/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ -#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 - -/* STAT5 register bits */ -#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) - -/* QUSB PHY register values */ -#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 -#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c -#define QUSB2PHY_PLL_CMODE 0x80 -#define QUSB2PHY_PLL_LOCK_DELAY 0x0a -#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 -#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 -#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 -#define QUSB2PHY_PWR_CTRL2 0x21 -#define QUSB2PHY_IMP_CTRL1 0x08 -#define QUSB2PHY_IMP_CTRL2 0x58 -#define QUSB2PHY_PORT_TUNE1 0xc5 -#define QUSB2PHY_PORT_TUNE2 0x29 -#define QUSB2PHY_PORT_TUNE3 0xca -#define QUSB2PHY_PORT_TUNE4 0x04 -#define QUSB2PHY_PORT_TUNE5 0x03 -#define QUSB2PHY_CHG_CTRL2 0x30 - -/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ -#define USB3_PCS_PHYSTATUS BIT(6) - -struct usb_board_data { - /* Register values going to override from the boardfile */ - u32 pll_bias_control_2; - u32 imp_ctrl1; - u32 port_tune1; -}; - -struct qmp_phy_init_tbl { - u32 *address; - u32 val; -}; - -void setup_usb_host0(struct usb_board_data *data); - -/* Call reset_ before setup_ */ -void reset_usb0(void); - -#endif /* _SC7180_USB_H_ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 1b9044f691..938f3e1e42 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -31,8 +31,9 @@ SECTIONS BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 83K, 4K) WATCHDOG_TOMBSTONE(0x14814FFC, 4) - BOOTBLOCK(0x14815000, 40K) - PRERAM_CBFS_CACHE(0x1481F000, 70K) + BOOTBLOCK(0x14815000, 48K) + TPM_TCPA_LOG(0x14821000, 2K) + PRERAM_CBFS_CACHE(0x14821800, 60K) PRERAM_CBMEM_CONSOLE(0x14830800, 32K) TIMESTAMP(0x14838800, 1K) TTB(0x14839000, 56K) diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index ce23a35672..8578b3813d 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include struct qup qup[12] = { diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index 24d5c207b4..68234f96c8 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -6,6 +6,7 @@ config SOC_QUALCOMM_SC7280 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 37ed21eaa3..85508e97bb 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -30,13 +30,20 @@ romstage-y += shrm_load_reset.c romstage-y += ../common/qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c +romstage-y += ../common/usb/usb.c +romstage-y += carve_out.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ ramstage-y += soc.c +ramstage-y += carve_out.c ramstage-y += cbmem.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c +ramstage-y += ../common/usb/usb.c +ramstage-y += ../common/usb/snps_usb_phy.c +ramstage-y += ../common/usb/qmpv4_usb_phy.c ramstage-y += ../common/aop_load_reset.c +ramstage-y += cpucp_load_reset.c ################################################################################ @@ -45,6 +52,26 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/common/include SC7280_BLOB := $(top)/3rdparty/qc_blobs/sc7280 +################################################################################ +BL31_MAKEARGS += PLAT=sc7280 + +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +BL31_MAKEARGS += QTI_SDI_BUILD=1 +BL31_MAKEARGS += QTISECLIB_PATH=$(SC7280_BLOB)/qtiseclib/libqtisec_dbg.a +else +BL31_MAKEARGS += QTISECLIB_PATH=$(SC7280_BLOB)/qtiseclib/libqtisec.a +endif # CONFIG_QC_SDI_ENABLE + +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SC7280_BLOB)/boot/QcSdi.elf +QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi +$(QCSDI_CBFS)-file := $(QCSDI_FILE) +$(QCSDI_CBFS)-type := stage +$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(QCSDI_CBFS) +endif + ################################################################################ QC_SEC_FILE := $(SC7280_BLOB)/qc_sec/qc_sec.mbn $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf @@ -111,6 +138,14 @@ $(AOP_CBFS)-type := payload $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(AOP_CBFS) +################################################################################ +CPUCP_FILE := $(SC7280_BLOB)/cpucp/cpucp.elf +CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp +$(CPUCP_CBFS)-file := $(CPUCP_FILE) +$(CPUCP_CBFS)-type := payload +$(CPUCP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += $(CPUCP_CBFS) + ################################################################################ SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm diff --git a/src/soc/qualcomm/sc7280/carve_out.c b/src/soc/qualcomm/sc7280/carve_out.c new file mode 100644 index 0000000000..d548235922 --- /dev/null +++ b/src/soc/qualcomm/sc7280/carve_out.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define MODEM_ONLY 0x004c5445 + +bool soc_modem_carve_out(void **start, void **end) +{ + uint32_t modem_id = read32(_modem_id); + + switch (modem_id) { + case MODEM_ONLY: + *start = _dram_modem; + *end = _edram_modem; + return true; + default: + return false; + } +} diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 07a575b952..ddc8d3d118 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c new file mode 100644 index 0000000000..d754531ed7 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void cpucp_prepare(void) +{ + /* allow NS access to EPSS memory*/ + setbits32(&epss_top->access_override, 0x1); + + /* Enable subsystem clock. Required for CPUCP PDMEM access*/ + setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); + if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1))) + printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__); +} + +void cpucp_fw_load_reset(void) +{ + struct prog cpucp_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); + + cpucp_prepare(); + + if (!selfload(&cpucp_fw_prog)) + die("SOC image: CPUCP load failed"); + + printk(BIOS_DEBUG, "SOC:CPUCP image loaded successfully.\n"); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 599d03f7b6..31f409ff4c 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -55,4 +55,17 @@ #define QUP_WRAP1_BASE 0x00AC0000 #define QUP_1_GSI_BASE 0x00A04000 +#define EPSSTOP_EPSS_TOP 0x18598000 +#define EPSSFAST_BASE_ADDR 0x18580000 + +/* + * USB BASE ADDRESSES + */ +#define HS_USB_PRIM_PHY_BASE 0x088e3000 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define USB_HOST_DWC3_BASE 0x0a60c100 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/cpucp.h b/src/soc/qualcomm/sc7280/include/soc/cpucp.h new file mode 100644 index 0000000000..37ae7d2b53 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/cpucp.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_CPUCP_H__ +#define _SOC_QUALCOMM_SC7280_CPUCP_H__ + +#include + +struct epsstop_epss_top { + uint32_t access_override; + uint32_t global_enable; + uint32_t trace_bus_ctrl; + uint32_t debug_bus_ctrl; + uint32_t muc_hang_det_ctrl; + uint32_t muc_hang_irq_sts; + uint32_t muc_hang_count_threshold; + uint32_t muc_hang_count_sts; + uint32_t muc_hang_det_sts; + uint32_t l3_voting_en; +}; + +struct epssfast_epss_fast { + uint32_t epss_muc_clk_ctrl; + uint32_t muc_rvbar; + uint32_t muc_rvbar_ctrl; + uint32_t muc_non_secure_dmem_start_addr; + uint32_t muc_non_secure_dmem_end_addr; + uint32_t reserved_1[2]; + uint32_t cpr_data_fifo[4]; + uint32_t reserved_2[4]; + uint32_t pll_data_fifo[4]; + uint32_t reserved_3[4]; + uint32_t gfmux_data_fifo_1[4]; + uint32_t cpu_pcu_spare_irq_status; + uint32_t cpu_pcu_spare_irq_clr; + uint32_t cpu_pcu_spare_wait_event; + uint32_t seq_mem[256]; +}; + +static struct epsstop_epss_top *const epss_top = (void *)EPSSTOP_EPSS_TOP; +static struct epssfast_epss_fast *const epss_fast = (void *)EPSSFAST_BASE_ADDR; + +void cpucp_fw_load_reset(void); +void cpucp_prepare(void); + +#endif // _SOC_QUALCOMM_SC7280_CPUCP_H__ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 620e5b55db..1677dc4c65 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -54,9 +54,11 @@ SECTIONS /* Various hardware/software subsystems make use of this area */ REGION(dram_aop, 0x80800000, 0x080000, 0x1000) REGION(dram_soc, 0x80900000, 0x200000, 0x1000) - BL31(0x80B00000, 1M) + REGION(dram_cpucp,0x80B00000, 0x100000, 0x1000) REGION(dram_wlan, 0x80C00000, 0xC00000, 0x1000) + REGION(dram_modem, 0x8B800000, 0xF600000, 0x1000) REGION(dram_wpss, 0x9AE00000, 0x1900000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) RAMSTAGE(0xA0800000, 16M) + BL31(0xC0000000, 1M) } diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index ff2b7cc650..98b62cc25a 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -5,24 +5,33 @@ #include #include #include +#include static void soc_read_resources(struct device *dev) { + void *start = NULL; + void *end = NULL; + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); reserved_ram_resource(dev, 2, (uintptr_t)_dram_wlan / KiB, - REGION_SIZE(dram_wlan) / KiB); + REGION_SIZE(dram_wlan) / KiB); reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB, - REGION_SIZE(dram_wpss) / KiB); + REGION_SIZE(dram_wpss) / KiB); reserved_ram_resource(dev, 4, (uintptr_t)_dram_aop / KiB, REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 5, (uintptr_t)_dram_cpucp / KiB, + REGION_SIZE(dram_cpucp) / KiB); + if (soc_modem_carve_out(&start, &end)) + reserved_ram_resource(dev, 6, (uintptr_t)start / KiB, (end - start) / KiB); } static void soc_init(struct device *dev) { aop_fw_load_reset(); + cpucp_fw_load_reset(); } static struct device_operations soc_ops = { diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index 73c2312307..022529f187 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -54,7 +54,7 @@ static void rk808_clrsetbits(uint8_t reg, uint8_t clr, uint8_t set) uint8_t value; if (rk808_read(reg, &value) || rk808_write(reg, (value & ~clr) | set)) - printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg); + printk(BIOS_ERR, "Cannot set Rk808[%#x]!\n", reg); } void rk808_configure_switch(int sw, int enabled) diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index 96a089b955..6ce6a27c95 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -94,7 +94,7 @@ vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) do { intsts = read32(&crypto->intsts); if (intsts & HRDMA_ERR) { - printk(BIOS_ERR, "ERROR: DMA error during HW crypto\n"); + printk(BIOS_ERR, "DMA error during HW crypto\n"); return VB2_ERROR_UNKNOWN; } } while (!(intsts & HRDMA_DONE)); /* wait for DMA to finish */ diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 877f53daa8..2efe19bd2c 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -739,7 +739,7 @@ static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, != PGSR_DLDONE) ; /* if at low power state, need wakeup first, then enter the config */ - /* fall through */ + __fallthrough; case ACCESS: case INIT_MEM: write32(&ddr_pctl_regs->sctl, CFG_STATE); @@ -893,7 +893,8 @@ static void move_to_access_state(u32 chnum) while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) != CONF) ; - /* fall through - enter config next to get to access state */ + /* enter config next to get to access state */ + __fallthrough; case CONF: write32(&ddr_pctl_regs->sctl, GO_STATE); while ((read32(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 1d263ef5dc..728f45d1a0 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -72,8 +72,7 @@ retry_edp: break; } if (retry_count_init == 3) { - printk(BIOS_WARNING, - "Warning: EDP initialization failed.\n"); + printk(BIOS_WARNING, "EDP initialization failed.\n"); return; } else { reset_edp(); @@ -162,6 +161,4 @@ retry_edp: } mainboard_power_on_backlight(); fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); - - return; } diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index cadc71e682..27abe19fac 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -16,7 +16,7 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } -void reset_usb_drd_dwc3() +void reset_usb_drd_dwc3(void) { printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD\n"); reset_dwc3(exynos_usb_drd_dwc3); @@ -52,7 +52,7 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) 0x1 << 12); /* port capability HOST */ } -void setup_usb_drd_dwc3() +void setup_usb_drd_dwc3(void) { setup_dwc3(exynos_usb_drd_dwc3); printk(BIOS_DEBUG, "DWC3 setup for USB DRD finished\n"); @@ -109,7 +109,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } -void setup_usb_drd_phy() +void setup_usb_drd_phy(void) { printk(BIOS_DEBUG, "Powering up USB DRD PHY\n"); setbits32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 758e09b05d..13a8feff41 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -336,8 +336,8 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, data); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP write_to_dpcd failed\n"); - return -1; + printk(BIOS_ERR, "DP write_to_dpcd failed\n"); + return -1; } @@ -467,9 +467,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); if (ret != EXYNOS_DP_SUCCESS) { - printk(BIOS_ERR, "DP read lane status failed\n"); - edp_info->lt_info.lt_status = DP_LT_FAIL; - return ret; + printk(BIOS_ERR, "DP read lane status failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; } if (lane_stat & DP_LANE_STAT_CR_DONE) { diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index b6d9e0b37f..61445442af 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -49,8 +49,6 @@ static void exynos_dp_enable_video_input(u32 enable) reg |= VIDEO_EN_MASK; lwrite32(reg, &dp_regs->video_ctl1); - - return; } void exynos_dp_disable_video_bist(void) @@ -71,8 +69,6 @@ void exynos_dp_enable_video_mute(unsigned int enable) reg |= VIDEO_MUTE_MASK; lwrite32(reg, &dp_regs->video_ctl1); - - return; } static void exynos_dp_init_analog_param(void) @@ -174,8 +170,6 @@ void exynos_dp_reset(void) exynos_dp_init_analog_param(); exynos_dp_init_interrupt(); - - return; } void exynos_dp_enable_sw_func(unsigned int enable) @@ -189,8 +183,6 @@ void exynos_dp_enable_sw_func(unsigned int enable) reg |= SW_FUNC_EN_N; lwrite32(reg, &dp_regs->func_en1); - - return; } unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) @@ -336,8 +328,6 @@ void exynos_dp_init_hpd(void) reg = lread32(&dp_regs->sys_ctl3); reg &= ~(F_HPD | HPD_CTRL); lwrite32(reg, &dp_regs->sys_ctl3); - - return; } static inline void exynos_dp_reset_aux(void) @@ -348,8 +338,6 @@ static inline void exynos_dp_reset_aux(void) reg = lread32(&dp_regs->func_en2); reg |= AUX_FUNC_EN_N; lwrite32(reg, &dp_regs->func_en2); - - return; } void exynos_dp_init_aux(void) @@ -375,8 +363,6 @@ void exynos_dp_init_aux(void) reg = lread32(&dp_regs->func_en2); reg &= ~AUX_FUNC_EN_N; lwrite32(reg, &dp_regs->func_en2); - - return; } void exynos_dp_config_interrupt(void) @@ -398,8 +384,6 @@ void exynos_dp_config_interrupt(void) reg = INT_STA_MASK; lwrite32(reg, &dp_regs->int_sta_mask); - - return; } unsigned int exynos_dp_get_plug_in_status(void) diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index ef2b18565e..352f6b5638 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -16,13 +16,13 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } -void reset_usb_drd0_dwc3() +void reset_usb_drd0_dwc3(void) { printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD0\n"); reset_dwc3(exynos_usb_drd0_dwc3); } -void reset_usb_drd1_dwc3() +void reset_usb_drd1_dwc3(void) { printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD1\n"); reset_dwc3(exynos_usb_drd1_dwc3); @@ -58,13 +58,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) 0x1 << 12); /* port capability HOST */ } -void setup_usb_drd0_dwc3() +void setup_usb_drd0_dwc3(void) { setup_dwc3(exynos_usb_drd0_dwc3); printk(BIOS_DEBUG, "DWC3 setup for USB DRD0 finished\n"); } -void setup_usb_drd1_dwc3() +void setup_usb_drd1_dwc3(void) { setup_dwc3(exynos_usb_drd1_dwc3); printk(BIOS_DEBUG, "DWC3 setup for USB DRD1 finished\n"); @@ -121,14 +121,14 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } -void setup_usb_drd0_phy() +void setup_usb_drd0_phy(void) { printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n"); setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd0_phy); } -void setup_usb_drd1_phy() +void setup_usb_drd1_phy(void) { printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n"); setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN); diff --git a/src/soc/ti/am335x/mmc.c b/src/soc/ti/am335x/mmc.c index b7b4f97c70..b65030e7d8 100644 --- a/src/soc/ti/am335x/mmc.c +++ b/src/soc/ti/am335x/mmc.c @@ -265,7 +265,7 @@ int am335x_mmc_init_storage(struct am335x_mmc_host *mmc_host) err = am335x_mmc_init(mmc_host->reg); if (err != 0) { - printk(BIOS_ERR, "ERROR: Initialising AM335X SD failed.\n"); + printk(BIOS_ERR, "Initialising AM335X SD failed.\n"); return err; } diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index c9962be894..3aac4506fb 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -62,8 +62,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index f1506bc44f..3c34e98d4d 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -79,7 +79,7 @@ void hudson_enable(struct device *dev) case PCI_DEVFN(0x12, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_12_0); - /* fall through */ + __fallthrough; case PCI_DEVFN(0x12, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_12_2); @@ -87,7 +87,7 @@ void hudson_enable(struct device *dev) case PCI_DEVFN(0x13, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_13_0); - /* fall through */ + __fallthrough; case PCI_DEVFN(0x13, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_13_2); @@ -95,7 +95,7 @@ void hudson_enable(struct device *dev) case PCI_DEVFN(0x16, 0): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_16_0); - /* fall through */ + __fallthrough; case PCI_DEVFN(0x16, 2): if (dev->enabled == 0) hudson_disable_usb(USB_EN_DEVFN_16_2); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9bf928ec56..6a31fbfbf8 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -290,10 +290,10 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev) switch (var_num) { case 3: pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ + __fallthrough; case 2: pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ + __fallthrough; case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 67c19254c6..48751a4e64 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -7,10 +7,10 @@ #include #include -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) void cf9_reset_prepare(void) { diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index c418492731..43f8ca75d3 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -10,6 +10,7 @@ static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops; + loops = SMBUS_TIMEOUT; do { u8 val; @@ -20,12 +21,14 @@ static int smbus_wait_until_ready(u32 smbus_io_base) } outb(val, smbus_io_base + SMBHSTSTAT); } while (--loops); + return -2; /* time out */ } static int smbus_wait_until_done(u32 smbus_io_base) { u32 loops; + loops = SMBUS_TIMEOUT; do { u8 val; @@ -40,6 +43,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return 0; } } while (--loops); + return -3; /* timeout */ } @@ -97,8 +101,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -128,8 +131,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -159,8 +161,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, return 0; } -void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; @@ -181,8 +182,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, outl(0, AB_INDX); } -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, - u32 mask, u32 val) +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; @@ -206,8 +206,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, - u32 mask, u32 val) +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp; diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index 6bb433893d..3dc2d8a31e 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -52,7 +52,7 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) /* SMI0 source is GEVENT0 and so on */ configure_smi(gevent, mode); - /* And set set the trigger level */ + /* And set the trigger level */ reg32 = smi_read32(SMI_REG_SMITRIG0); reg32 &= ~(1 << gevent); reg32 |= (level & 0x1) << gevent; diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 88fbf7b48c..7cf8bb8a59 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -35,16 +35,6 @@ Method(_PRT,0) { #include "pcie.asl" -/* PCI slot 1, 2, 3 */ -Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } -} - Device(STCR) { Name(_ADR, 0x00110000) #include "acpi/sata.asl" @@ -60,8 +50,14 @@ Device(SBUS) { #include "lpc.asl" -Device(HPBR) { +/* PCI bridge */ +Device(PIBR) { Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } } /* end HostPciBr */ Device(ACAD) { @@ -164,176 +160,7 @@ Method(_INI, 0) { } /* End Method(_SB._INI) */ Scope(\){ - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } + #include "misc_io.asl" - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - , 1, /* MiscControl */ - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } } diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl index 507a8b853a..dc72061be0 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -2,9 +2,6 @@ Device(LIBR) { Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ /* Real Time Clock Device */ Device(RTC0) { @@ -12,7 +9,6 @@ Device(LIBR) { Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) - /* IO(Decode16,0x0070, 0x0070, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ @@ -21,7 +17,6 @@ Device(LIBR) { Name(_CRS, ResourceTemplate() { IRQNoFlags(){0} IO(Decode16, 0x0040, 0x0040, 0, 4) - /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ @@ -38,8 +33,6 @@ Device(LIBR) { IRQNoFlags(){2} IO(Decode16,0x0020, 0x0020, 0, 2) IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl b/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl new file mode 100644 index 0000000000..b8296fb066 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +/* Client Management index/data registers */ +OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, +} + +/* GPM Port register */ +OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, +} + +/* Flash ROM program enable register */ +OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, +} + +/* PM2 index/data registers */ +OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, +} + +/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ +OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, +} +IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + , 1, /* MiscControl */ + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, +} + +/* PM1 Event Block +* First word is PM1_Status, Second word is PM1_Enable +*/ +OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, +} diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h index 05ccd08e03..b3fb37dbc8 100644 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h +++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h @@ -24,9 +24,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 8d1139dd1f..f1ac4c920c 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include /* Include this before OEM.h to have HPET_BASE_ADDRESS from arch/x86 */ #include "SBPLATFORM.h" #include "cfg.h" #include diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 25600c081e..9c280a1670 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -86,8 +86,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index bbba3fa083..f5e0a48f4d 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -280,6 +280,4 @@ if (sb_chip->imc_tempin3_enabled) { sb_config.StdHeader.Func = SB_EC_FANCONTROL; AmdSbDispatcher(&sb_config); - - return; } diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a082e0ca5a..de88d7c4ba 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -158,10 +158,10 @@ void lpc_enable_childrens_resources(struct device *dev) switch (var_num) { case 3: pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ + __fallthrough; case 2: pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ + __fallthrough; case 1: //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index aad6d2e616..b04c3e2918 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -7,7 +7,7 @@ #include #include -#define HT_INIT_CONTROL 0x6C +#define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1<<5) #define DEV_CDB 0x18 diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 7d1ffb981e..50c77cf0b0 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include "smbus.h" -#include /* printk */ +#include static int smbus_wait_until_ready(u32 smbus_io_base) { @@ -49,11 +50,11 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); /* set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); @@ -70,7 +71,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD); - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); return byte; } @@ -79,11 +80,11 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD); @@ -100,7 +101,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return -3; /* timeout or error */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); return 0; } @@ -109,11 +110,11 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -133,7 +134,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0); - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); return byte; } @@ -142,11 +143,11 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); @@ -166,7 +167,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) return -3; /* timeout or error */ } - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); return 0; } @@ -174,7 +175,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -190,14 +191,14 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); } void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -213,7 +214,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); } /* space = 0: AX_INDXC, AX_DATAC @@ -223,7 +224,7 @@ void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp; - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -242,5 +243,5 @@ void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 468ae23393..38439d0d93 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -32,7 +32,7 @@ static void execute_command(void) (read8((void *)(spibar+3)) & 0x80)); } -void spi_init() +void spi_init(void) { struct device *dev; diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index fe967d587b..cbba3ef096 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -89,7 +89,7 @@ void write_pci_cfg_irqs(void) u32 i = 0; if (pirq_data_ptr == NULL) { - printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + printk(BIOS_WARNING, "Can't write PCI IRQ assignments because" " 'mainboard_pirq_data' structure does not exist\n"); return; } diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 20597d43da..95c6d356c1 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -77,7 +77,7 @@ void hudson_lpc_decode(void) pm_write8(0xec, pm_read8(0xec) | 0x01); const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - /* Serial port numeration on Hudson: + /* Serial port enumeration on Hudson: * PORT0 - 0x3f8 * PORT1 - 0x2f8 * PORT5 - 0x2e8 @@ -215,7 +215,8 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); + write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 | + read16((void *)(base + SPI100_ENABLE))); } void hudson_disable_4dw_burst(void) diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index e2f3bbad7d..975b0faa8b 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -62,8 +62,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 77d39c5e91..05543cfe59 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -301,10 +301,10 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev) switch (var_num) { case 3: pci_write_config16(dev, 0x90, reg_var[2]); - /* fall through */ + __fallthrough; case 2: pci_write_config16(dev, 0x66, reg_var[1]); - /* fall through */ + __fallthrough; case 1: pci_write_config16(dev, 0x64, reg_var[0]); break; @@ -354,7 +354,9 @@ static struct device_operations lpc_ops = { }; static const unsigned short pci_device_ids[] = { + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_SB900_LPC, + /* PCI device ID is used on all integrated FCHs except Family 16h Models 00h-3Fh */ PCI_DEVICE_ID_AMD_CZ_LPC, 0 }; diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index 67c19254c6..48751a4e64 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -7,10 +7,10 @@ #include #include -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) void cf9_reset_prepare(void) { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 6f9e03c2d3..f6422cf37e 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -106,5 +106,6 @@ static struct device_operations smbus_ops = { static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_AMD, + /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */ .device = PCI_DEVICE_ID_AMD_SB900_SM, }; diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index c418492731..43f8ca75d3 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -10,6 +10,7 @@ static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops; + loops = SMBUS_TIMEOUT; do { u8 val; @@ -20,12 +21,14 @@ static int smbus_wait_until_ready(u32 smbus_io_base) } outb(val, smbus_io_base + SMBHSTSTAT); } while (--loops); + return -2; /* time out */ } static int smbus_wait_until_done(u32 smbus_io_base) { u32 loops; + loops = SMBUS_TIMEOUT; do { u8 val; @@ -40,6 +43,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return 0; } } while (--loops); + return -3; /* timeout */ } @@ -97,8 +101,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -128,8 +131,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -159,8 +161,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, return 0; } -void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; @@ -181,8 +182,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, outl(0, AB_INDX); } -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, - u32 mask, u32 val) +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp; @@ -206,8 +206,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, - u32 mask, u32 val) +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) { u32 tmp; diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 6bb433893d..3dc2d8a31e 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -52,7 +52,7 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) /* SMI0 source is GEVENT0 and so on */ configure_smi(gevent, mode); - /* And set set the trigger level */ + /* And set the trigger level */ reg32 = smi_read32(SMI_REG_SMITRIG0); reg32 &= ~(1 << gevent); reg32 |= (level & 0x1) << gevent; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c9e86625d2..168c18e26c 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -53,7 +53,6 @@ config SERIRQ_CONTINUOUS_MODE operated in continuous mode. config HPET_MIN_TICKS - hex default 0x80 config HIDE_MEI_ON_ERROR diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 9df8ac6c4d..98e979e2eb 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -78,7 +80,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -91,15 +93,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index 15a2f9b37b..3e2ba78db4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -149,7 +149,7 @@ Device (XHC) // Query flag clear and xHCI in auto mode If(!(CDW1 & 0x1) && (XHCI == 2 || XHCI == 3)) { - Debug = "XHCI Switch" + Printf ("XHCI Switch") Local0 = 0 Local0 = XPRT & 0x03 If(Local0 == 0 || Local0 == 1) { diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 3b07a15298..0a0b5152da 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -12,8 +12,6 @@ #include "chip.h" #include "pch.h" -typedef struct southbridge_intel_bd82x6x_config config_t; - static int codec_detect(u8 *base) { u8 reg8; @@ -39,118 +37,6 @@ no_codec: return 0; } -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 1msec timeout */ - int timeout = 1000; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 1msec timeout */ - int timeout = 1000; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } - - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } -} - static void azalia_init(struct device *dev) { u8 *base; @@ -158,7 +44,7 @@ static void azalia_init(struct device *dev) u32 codec_mask; u32 reg32; - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -224,7 +110,7 @@ static void azalia_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } /* Enable dynamic clock gating */ diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 797c93f3aa..30c2675513 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -4,7 +4,7 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #include -#include +#include struct southbridge_intel_bd82x6x_config { /** @@ -58,7 +58,7 @@ struct southbridge_intel_bd82x6x_config { uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index a47991cdf3..561bed9664 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "me.h" #include "pch.h" @@ -57,14 +56,14 @@ int intel_early_me_init(void) udelay(ME_DELAY); } if (!count) { - printk(BIOS_ERR, "ERROR: ME is not ready!\n"); + printk(BIOS_ERR, "ME is not ready!\n"); return -1; } /* Check for valid firmware */ hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { - printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); + printk(BIOS_WARNING, "ME has bad firmware\n"); return -1; } diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 9d46897fdf..88fad7c801 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -7,7 +7,7 @@ #include #include #include -#include + #include "me.h" #include "pch.h" @@ -55,14 +55,14 @@ int intel_early_me_init(void) udelay(ME_DELAY); } if (!count) { - printk(BIOS_ERR, "ERROR: ME is not ready!\n"); + printk(BIOS_ERR, "ME is not ready!\n"); return -1; } /* Check for valid firmware */ hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { - printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); + printk(BIOS_WARNING, "ME has bad firmware\n"); return -1; } @@ -114,7 +114,7 @@ int intel_early_me_init_done(u8 status) udelay(ME_DELAY); } if (!count) { - printk(BIOS_ERR, "ERROR: ME failed to respond\n"); + printk(BIOS_ERR, "ME failed to respond\n"); return -1; } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 0148905fd9..f8f3cebc71 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 6ad4cc22c0..24d11b2f0c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 177d581103..cf322ebcb9 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -336,7 +336,7 @@ int intel_mei_setup(struct device *dev) struct mei_csr host; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/bd82x6x/me_smm.c b/src/southbridge/intel/bd82x6x/me_smm.c index e1eb9001df..c7a7f45ad7 100644 --- a/src/southbridge/intel/bd82x6x/me_smm.c +++ b/src/southbridge/intel/bd82x6x/me_smm.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 82b95f69e4..d24604c513 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -319,7 +319,7 @@ static void pch_pcie_enable(struct device *dev) * or the other devices will not be enumerated by the OS. */ if (!dev->enabled) - config->pcie_port_coalesce = 1; + config->pcie_port_coalesce = true; if (config->pcie_port_coalesce) printk(BIOS_INFO, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 839b0c3df0..0ae1f4ab28 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -19,7 +19,7 @@ static void pch_smbus_init(struct device *dev) pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 8bc45f69da..2764861651 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -43,7 +43,7 @@ static void usb_ehci_init(struct device *dev) /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((void *)(uintptr_t)(res->base + 4)); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 102bcb145b..1dadc8e6db 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "acpi_pirq_gen.h" diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index b9b766c708..2de86de855 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -104,7 +104,7 @@ config USE_ME_CLEANER If unsure, say N. -comment "Please test the modified ME/TXE firmware and coreboot in two steps" +comment "Please test coreboot with the original, unmodified ME firmware before using me_cleaner" depends on USE_ME_CLEANER config ME_CLEANER_ARGS diff --git a/src/southbridge/intel/common/hpet.c b/src/southbridge/intel/common/hpet.c index c48edae59d..e9369ee540 100644 --- a/src/southbridge/intel/common/hpet.c +++ b/src/southbridge/intel/common/hpet.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include @@ -7,8 +8,7 @@ #define HPTC 0x3404 -#define HPET_BASE 0xfed00000 -#define HPET32(x) (*((volatile u32 *)(HPET_BASE + (x)))) +#define HPET32(x) (*((volatile u32 *)(HPET_BASE_ADDRESS + (x)))) void enable_hpet(void) { diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 75dad0dc45..c9f1518734 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -83,7 +83,7 @@ void intel_acpi_gen_def_acpi_pirq(const struct device *lpc) pin_irq_map[map_count].pic_pirq = pirq; /* PIRQs are mapped to GSIs starting at 16 */ pin_irq_map[map_count].apic_gsi = 16 + pirq_idx(pirq); - printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", + printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%zd\n", dev_path(dev), int_pin - PCI_INT_A, pirq_idx(pin_irq_map[map_count].pic_pirq)); map_count++; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 30f7657948..44d283c590 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -998,7 +998,7 @@ static int spi_flash_protect(const struct spi_flash *flash, } if (fpr == cntlr.fpr_max) { - printk(BIOS_ERR, "ERROR: No SPI FPR free!\n"); + printk(BIOS_ERR, "No SPI FPR free!\n"); return -1; } @@ -1017,7 +1017,7 @@ static int spi_flash_protect(const struct spi_flash *flash, protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); break; default: - printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n"); + printk(BIOS_ERR, "Seeking invalid protection!\n"); return -1; } @@ -1027,7 +1027,7 @@ static int spi_flash_protect(const struct spi_flash *flash, /* Set the FPR register and verify it is protected */ write32(&fpr_base[fpr], reg); if (reg != read32(&fpr_base[fpr])) { - printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr); + printk(BIOS_ERR, "Unable to set SPI FPR %d\n", fpr); return -1; } diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl index c55ff33d8f..f4fa928cc5 100644 --- a/src/southbridge/intel/i82371eb/acpi/intx.asl +++ b/src/southbridge/intel/i82371eb/acpi/intx.asl @@ -40,7 +40,7 @@ Device(intx) { \ /* Use lowest available IRQ */ \ FindSetRightBit(IRQM, Local0) \ if (Local0) { \ - Decrement(Local0) \ + Local0-- \ } \ Store(Local0, pinx) \ } \ diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index 176906ade4..eeab305299 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -50,7 +50,7 @@ Device(intx) { \ /* Use lowest available IRQ */ \ FindSetRightBit(IRQM, Local0) \ if (Local0) { \ - Decrement(Local0) \ + Local0-- \ } \ Store(Local0, pinx) \ } \ diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 05b2d2c487..844106dcc0 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -30,7 +30,6 @@ static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) void bootblock_early_southbridge_init(void) { u16 reg16; - pci_devfn_t dev; /* * Note: The Intel 82371AB/EB/MB ISA device can be on different @@ -39,7 +38,7 @@ void bootblock_early_southbridge_init(void) * But scanning for the PCI IDs (instead of hardcoding * bus/device/function numbers) works on all boards. */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); /* Enable access to the whole ROM, disable ROM write access. */ diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 62e790d5d4..48c761cad0 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -9,12 +9,11 @@ void enable_pm(void) { - pci_devfn_t dev; u8 reg8; u16 reg16; /* Get the SMBus/PM device of the 82371AB/EB/MB. */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); /* Set the PM I/O base. */ diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 97cf5fd7c0..1d080453e0 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -21,12 +21,11 @@ uintptr_t smbus_base(void) int smbus_enable_iobar(uintptr_t base) { - pci_devfn_t dev; u8 reg8; u16 reg16; /* Get the SMBus/PM device of the 82371AB/EB/MB. */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); /* Set the SMBus I/O base. */ diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 030f7b4be2..ff100919e6 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -11,10 +11,8 @@ ramstage-y += lpc.c ramstage-y += usb.c ramstage-y += usb2.c -ifeq ($(CONFIG_SMM_ASEG),y) -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -endif +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S smm-y += smihandler.c diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 34d93c4800..238661cd2d 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include #include @@ -8,8 +11,7 @@ #include #include #include -#include -#include +#include #include "chip.h" #include "i82801dx.h" @@ -212,7 +214,7 @@ static void enable_hpet(struct device *dev) u32 reg32, hpet, val; /* Set HPET base address and enable it */ - printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS); + printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_BASE_ADDRESS); reg32 = pci_read_config32(dev, GEN_CNTL); /* * Bit 17 is HPET enable bit. @@ -220,7 +222,7 @@ static void enable_hpet(struct device *dev) */ reg32 &= ~(3 << 15); /* Clear it */ - hpet = CONFIG_HPET_ADDRESS >> 12; + hpet = HPET_BASE_ADDRESS >> 12; hpet &= 0x3; reg32 |= (hpet << 15); @@ -233,7 +235,7 @@ static void enable_hpet(struct device *dev) val &= 0x7; if ((val & 0x4) && (hpet == (val & 0x3))) { - printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS); + printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_BASE_ADDRESS); } else { printk(BIOS_WARNING, "HPET was not enabled correctly\n"); reg32 &= ~(1 << 17); /* Clear Enable */ @@ -273,10 +275,12 @@ static void lpc_init(struct device *dev) /* Initialize the High Precision Event Timers */ enable_hpet(dev); + setup_i8259(); + /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) + if (CONFIG(SMM_LEGACY_ASEG)) aseg_smm_lock(); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 399d7e0bbb..9e7259f121 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -30,7 +30,6 @@ config EHCI_BAR default 0xfef00000 config HPET_MIN_TICKS - hex default 0x80 config INTEL_TOP_SWAP_BOOTBLOCK_SIZE diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 72e28eb362..d2e88902f9 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -60,7 +62,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -73,15 +75,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (HPAS == 1) { - HPT0 = CONFIG_HPET_ADDRESS + 0x1000 + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (HPAS == 2) { - HPT0 = CONFIG_HPET_ADDRESS + 0x2000 + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (HPAS == 3) { - HPT0 = CONFIG_HPET_ADDRESS + 0x3000 + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 0473de64de..33a0cd8387 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -37,109 +37,6 @@ no_codec: return 0; } -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - - for (i = 2; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } -} - static void azalia_init(struct device *dev) { u8 *base; @@ -186,7 +83,7 @@ static void azalia_init(struct device *dev) // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -198,7 +95,7 @@ static void azalia_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 303536fa14..09a71260ef 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H -#include +#include enum sata_mode { SATA_MODE_AHCI = 0, @@ -61,7 +61,7 @@ struct southbridge_intel_i82801gx_config { uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; int c4onc3_enable:1; int docking_supported:1; diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index c8a6117de5..4647bf1c6a 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 8650673557..b8918e8377 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -137,7 +137,7 @@ static void ich_pcie_device_set_func(int index, int pci_func) static void root_port_commit_config(struct device *dev) { int i; - int coalesce = 0; + bool coalesce = false; if (dev->chip_info != NULL) { const struct southbridge_intel_i82801gx_config *config = dev->chip_info; @@ -145,7 +145,7 @@ static void root_port_commit_config(struct device *dev) } if (!rpc.ports[0]->enabled) - coalesce = 1; + coalesce = true; for (i = 0; i < rpc.num_ports; i++) { struct device *pcie_dev; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index abb0e2e03e..d0d8b3bf33 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -130,7 +130,7 @@ static void sata_init(struct device *dev) /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); + struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) /* write AHCI GHC_PI register */ write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 39f5e83b25..0b4501627c 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -29,7 +29,6 @@ config EHCI_BAR default 0xfef00000 config HPET_MIN_TICKS - hex default 0x80 ## Some enterprise variants may require an IFD diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index dada88511d..d376622850 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -28,10 +28,8 @@ ifneq ($(CONFIG_BOARD_EMULATION_QEMU_X86_Q35),y) ramstage-y += madt.c endif -ifeq ($(CONFIG_SMM_ASEG),y) -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -endif +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += smi.c +ramstage-$(CONFIG_SMM_LEGACY_ASEG) += ../../../cpu/x86/smm/smmrelocate.S CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index f90386da6c..9227735446 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -60,7 +62,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -73,15 +75,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 90d784cd65..0179415375 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include "chip.h" #include "i82801ix.h" @@ -36,119 +35,6 @@ no_codec: return 0; } -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - - for (i = 2; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } - - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } -} - static void azalia_init(struct device *dev) { u8 *base; @@ -179,7 +65,7 @@ static void azalia_init(struct device *dev) /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -191,7 +77,7 @@ static void azalia_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 21f1faa3b7..0132ac5b89 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -378,7 +378,7 @@ static void lpc_init(struct device *dev) /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) + if (CONFIG(SMM_LEGACY_ASEG)) aseg_smm_lock(); } diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 0483447e94..e02b3965a0 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -9,7 +9,7 @@ #include -#if !CONFIG(SMM_TSEG) +#if CONFIG(SMM_LEGACY_ASEG) /* For qemu/x86-q35 to build properly. */ struct global_nvs *gnvs; #endif diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 197ed523f6..13357c7238 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -30,7 +30,6 @@ config EHCI_BAR default 0xfef00000 config HPET_MIN_TICKS - hex default 0x80 ## Some enterprise variants may require an IFD diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index f90386da6c..9227735446 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + // Intel LPC Bus Device - 0:1f.0 Device (LPCB) @@ -60,7 +62,7 @@ Device (LPCB) Name(BUF0, ResourceTemplate() { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -73,15 +75,15 @@ Device (LPCB) If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 885c332f8f..618350ea32 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include "chip.h" #include "i82801jx.h" @@ -36,119 +35,6 @@ no_codec: return 0; } -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - - for (i = 2; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } - - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } -} - static void azalia_init(struct device *dev) { u8 *base; @@ -179,7 +65,7 @@ static void azalia_init(struct device *dev) /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -191,7 +77,7 @@ static void azalia_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 70440c02c2..9c8ec231da 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 6972da7613..a79b3f73af 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -49,7 +49,6 @@ config SERIRQ_CONTINUOUS_MODE operated in continuous mode. config HPET_MIN_TICKS - hex default 0x80 config HIDE_MEI_ON_ERROR diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index c8c96a8dfa..b33252fea4 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c romstage-y += early_cir.c romstage-y += early_usb.c +romstage-y += setup_heci_uma.c CPPFLAGS_common += -I$(src)/southbridge/intel/ibexpeak/include diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 683715fd6b..d4e639ac04 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -35,130 +35,15 @@ no_codec: return 0; } -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ - -static int wait_for_ready(u8 *base) -{ - /* Use a 1msec timeout */ - int timeout = 1000; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ - -static int wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 1msec timeout */ - int timeout = 1000; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -static void codec_init(struct device *dev, u8 *base, int addr) -{ - u32 reg32; - const u32 *verb; - u32 verb_size; - int i; - - printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); - - /* 1 */ - if (wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb); - - if (!verb_size) { - printk(BIOS_DEBUG, "Azalia: No verb!\n"); - return; - } - printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); - - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, verb[i]); - - if (wait_for_valid(base) < 0) - return; - } - printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); -} - -static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) -{ - int i; - - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - codec_init(dev, base, i); - } - - for (i = 0; i < pc_beep_verbs_size; i++) { - if (wait_for_ready(base) < 0) - return; - - write32(base + HDA_IC_REG, pc_beep_verbs[i]); - - if (wait_for_valid(base) < 0) - return; - } -} - static void azalia_init(struct device *dev) { u8 *base; struct resource *res; u32 codec_mask; - u8 reg8; - u16 reg16; u32 reg32; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -174,33 +59,21 @@ static void azalia_init(struct device *dev) reg32 |= RCBA32(0x2030) & 0xfe; pci_write_config32(dev, 0x120, reg32); - reg16 = pci_read_config16(dev, 0x78); - reg16 |= (1 << 11); - pci_write_config16(dev, 0x78, reg16); + pci_or_config16(dev, 0x78, 1 << 11); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_read_config32(dev, 0x114); - reg32 &= ~0xfe; - pci_write_config32(dev, 0x114, reg32); + pci_and_config32(dev, 0x114, ~0xfe); // Set VCi enable bit - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, 1 << 31); // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + pci_or_config32(dev, 0xc4, 1 << 1); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + pci_or_config8(dev, 0x43, 1 << 6); - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); + pci_and_config32(dev, 0xd0, ~(1 << 31)); /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -216,27 +89,21 @@ static void azalia_init(struct device *dev) /* Wait 1ms */ udelay(1000); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(dev, base, codec_mask); + azalia_codecs_init(base, codec_mask); } /* Enable dynamic clock gating */ - reg8 = pci_read_config8(dev, 0x43); - reg8 &= ~0x7; - reg8 |= (1 << 2) | (1 << 0); - pci_write_config8(dev, 0x43, reg8); + pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0)); } static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 2fa4b52d23..4df47f3cf1 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -46,6 +47,11 @@ void ibexpeak_setup_bars(void) /* halt timer */ outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); + + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0, + (uintptr_t)DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } void early_pch_init(void) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 01836b1698..53fce008f5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -25,8 +25,6 @@ #define NMI_OFF 0 -typedef struct southbridge_intel_ibexpeak_config config_t; - /** * Set miscellaneous static southbridge features. * @@ -113,7 +111,7 @@ static void pch_pirq_init(struct device *dev) static void pch_gpi_routing(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; u32 reg32 = 0; /* An array would be much nicer here, or some @@ -146,7 +144,7 @@ static void pch_power_options(struct device *dev) u32 reg32; const char *state; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On @@ -446,7 +444,7 @@ static void lpc_init(struct device *dev) static void pch_lpc_read_resources(struct device *dev) { struct resource *res; - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; u8 io_index = 0; /* Get the normal PCI resources of this device. */ @@ -521,7 +519,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(const struct device *device) { struct device *dev = pcidev_on_root(0x1f, 0); - config_t *chip = dev->chip_info; + struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); intel_acpi_gen_def_acpi_pirq(dev); diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 20b8aac94a..74b386169a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -395,7 +395,7 @@ static int intel_mei_setup(struct device *dev) u16 reg16; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 4eea0af2d5..8ff5ca7fa4 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -231,6 +231,8 @@ int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); +void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size); + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6565cd11f0..83e86c266c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,6 +22,7 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#define DEFAULT_HECIBAR ((u8 *)0xfed17000) #include diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 171057ecd0..4107abbc3e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -13,8 +13,6 @@ #include "chip.h" #include "pch.h" -typedef struct southbridge_intel_ibexpeak_config config_t; - static inline u32 sir_read(struct device *dev, int idx) { pci_write_config32(dev, SATA_SIRI, idx); @@ -32,7 +30,7 @@ static void sata_init(struct device *dev) u32 reg32; u16 reg16; /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -168,7 +166,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; u16 map = 0; if (!config) @@ -190,7 +188,7 @@ static void sata_enable(struct device *dev) static void sata_fill_ssdt(const struct device *dev) { - config_t *config = dev->chip_info; + const struct southbridge_intel_ibexpeak_config *config = dev->chip_info; generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); } diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c new file mode 100644 index 0000000000..e490573812 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HECIDEV PCI_DEV(0, 0x16, 0) + +/* FIXME: add timeout. */ +static void wait_heci_ready(void) +{ + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c + ; + + write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc); +} + +/* FIXME: add timeout. */ +static void wait_heci_cb_avail(int len) +{ + union { + struct mei_csr csr; + u32 raw; + } csr; + + while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) + ; + + do { + csr.raw = read32(DEFAULT_HECIBAR + 0x4); + } while (len > csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - + csr.csr.buffer_read_ptr)); +} + +static void send_heci_packet_dword(u8 *payload, size_t length) +{ + int i; + for (i = 0; i < length; i += sizeof(uint32_t)) { + uint32_t dword = 0; + size_t bytes = MIN(length - i, sizeof(dword)); + memcpy(&dword, payload + i, bytes); + write32(DEFAULT_HECIBAR + 0, dword); + } +} + +static void send_heci_packet(struct mei_header *head, u8 *payload) +{ + wait_heci_cb_avail(DIV_ROUND_UP(sizeof(*head) + head->length, sizeof(u32))); + + send_heci_packet_dword((u8 *)head, sizeof(*head)); + send_heci_packet_dword(payload, head->length); + + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4); +} + +static void send_heci_message(u8 *msg, int len, u8 hostaddress, u8 clientaddress) +{ + struct mei_header head; + int maxlen; + + wait_heci_ready(); + maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4; + + while (len) { + int cur = len; + if (cur > maxlen) { + cur = maxlen; + head.is_complete = 0; + } else + head.is_complete = 1; + head.length = cur; + head.reserved = 0; + head.client_address = clientaddress; + head.host_address = hostaddress; + send_heci_packet(&head, msg); + len -= cur; + msg += cur; + } +} + +/* FIXME: Add timeout. */ +static int recv_heci_packet(struct mei_header *head, u32 *packet, u32 *packet_size) +{ + union { + struct mei_csr csr; + u32 raw; + } csr; + int i = 0; + + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); + do { + csr.raw = read32(DEFAULT_HECIBAR + 0xc); + } while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); + + *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8); + if (!head->length) { + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2); + *packet_size = 0; + return 0; + } + if (head->length + 4 > 4 * csr.csr.buffer_depth || head->length > *packet_size) { + *packet_size = 0; + return -1; + } + + do { + csr.raw = read32(DEFAULT_HECIBAR + 0xc); + } while (((head->length + 3) >> 2) > + (csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr)); + + for (i = 0; i < (head->length + 3) >> 2; i++) + packet[i++] = read32(DEFAULT_HECIBAR + 0x8); + *packet_size = head->length; + if (!csr.csr.ready) + *packet_size = 0; + write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4); + return 0; +} + +union uma_reply { + struct { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + u8 field2; + u8 unk3[0x48 - 4 - 1]; + }; + u32 dwords[0x48 / sizeof(u32)]; +} __packed; + +/* FIXME: Add timeout. */ +static int recv_heci_message(union uma_reply *message, u32 *message_size) +{ + struct mei_header head; + int current_position; + + current_position = 0; + while (1) { + u32 current_size; + current_size = *message_size - current_position; + if (recv_heci_packet + (&head, &message->dwords[current_position / sizeof(u32)], + ¤t_size) == -1) + break; + if (!current_size) + break; + current_position += current_size; + if (head.is_complete) { + *message_size = current_position; + return 0; + } + + if (current_position >= *message_size) + break; + } + *message_size = 0; + return -1; +} + +static void send_heci_uma_message(const u64 heci_uma_addr, const unsigned int heci_uma_size) +{ + union uma_reply reply; + + struct uma_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u32 c2; + u64 heci_uma_addr; + u32 heci_uma_size; + u16 c3; + } __packed msg = { + .group_id = 0, + .cmd = MKHI_SET_UMA, + .reserved = 0, + .result = 0, + .c2 = 0x82, + .heci_uma_addr = heci_uma_addr, + .heci_uma_size = heci_uma_size, + .c3 = 0, + }; + u32 reply_size; + + send_heci_message((u8 *) &msg, sizeof(msg), 0, 7); + + reply_size = sizeof(reply); + if (recv_heci_message(&reply, &reply_size) == -1) + return; + + if (reply.command != (MKHI_SET_UMA | (1 << 7))) + die("HECI init failed\n"); +} + +void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size) +{ + if (!heci_uma_size && !(pci_read_config32(HECIDEV, 0x40) & 0x20)) + return; + + if (heci_uma_size) { + dmibar_clrbits32(DMIVC0RCTL, 1 << 7); + RCBA32(0x14) &= ~0x80; + dmibar_clrbits32(DMIVC1RCTL, 1 << 7); + RCBA32(0x20) &= ~0x80; + dmibar_clrbits32(DMIVCPRCTL, 1 << 7); + RCBA32(0x30) &= ~0x80; + dmibar_clrbits32(DMIVCMRCTL, 1 << 7); + RCBA32(0x40) &= ~0x80; + + RCBA32(0x40) = 0x87000080; // OK + dmibar_write32(DMIVCMRCTL, 0x87000080); // OK + + while ((RCBA16(0x46) & 2) && dmibar_read16(DMIVCMRSTS) & VCMNP) + ; + } + + mchbar_write32(0x24, 0x10000 + heci_uma_size); + + send_heci_uma_message(heci_uma_addr, heci_uma_size); + + pci_write_config32(HECIDEV, 0x10, 0x0); + pci_write_config8(HECIDEV, 0x4, 0x0); +} diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 12734a0ce6..66523256b9 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -19,7 +19,7 @@ static void pch_smbus_init(struct device *dev) pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 142d3c7d6d..b96833cb54 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -14,7 +14,7 @@ static void thermal_init(struct device *dev) u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index a2adc5aab7..3de8c33652 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -36,7 +36,7 @@ static void usb_ehci_init(struct device *dev) /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((u32 *)(uintptr_t)(res->base + 4)); diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 891b06a4a5..b188251d8b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -53,7 +53,6 @@ config SERIRQ_CONTINUOUS_MODE operated in continuous mode. config HPET_MIN_TICKS - hex default 0x80 config FINALIZE_USB_ROUTE_XHCI diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 51d777ee41..1e02467a85 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + // Intel LPC Bus Device - 0:1f.0 #include @@ -66,7 +68,7 @@ Device (LPCB) Name (BUF0, ResourceTemplate () { - Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -79,15 +81,15 @@ Device (LPCB) If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) If (HPAS == 1) { - HPT0 = CONFIG_HPET_ADDRESS + 0x1000 + HPT0 = HPET_BASE_ADDRESS + 0x1000 } If (HPAS == 2) { - HPT0 = CONFIG_HPET_ADDRESS + 0x2000 + HPT0 = HPET_BASE_ADDRESS + 0x2000 } If (HPAS == 3) { - HPT0 = CONFIG_HPET_ADDRESS + 0x3000 + HPT0 = HPET_BASE_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 27ee9248a2..1bde180883 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -11,22 +11,6 @@ #include "pch.h" #include "hda_verb.h" -static void codecs_init(u8 *base, u32 codec_mask) -{ - int i; - - /* Can support up to 4 codecs */ - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - hda_codec_init(base, i, - cim_verb_data_size, - cim_verb_data); - } - - if (pc_beep_verbs_size) - hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); -} - static void azalia_pch_init(struct device *dev, u8 *base) { u8 reg8; @@ -101,7 +85,7 @@ static void azalia_init(struct device *dev) u32 codec_mask; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; @@ -117,7 +101,7 @@ static void azalia_init(struct device *dev) if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); + azalia_codecs_init(base, codec_mask); } } diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 89bbb1ce0c..12bb401f77 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -65,7 +65,7 @@ struct southbridge_intel_lynxpoint_config { uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e5ce3f52e1..947c570e16 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -5,7 +5,7 @@ #include #include #include -#include + #include "me.h" #include "pch.h" @@ -20,55 +20,39 @@ static const char *me_ack_values[] = { [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); -} - void intel_early_me_status(void) { - struct me_hfs hfs; - struct me_hfs2 hfs2; + union me_hfs hfs = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2) }; - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&hfs2, PCI_ME_HFS2); - - intel_me_status(&hfs, &hfs2); + intel_me_status(hfs, hfs2); } int intel_early_me_init(void) { int count; - struct me_uma uma; - struct me_hfs hfs; + union me_uma uma; + union me_hfs hfs; printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); } if (!count) { - printk(BIOS_ERR, "ERROR: ME is not ready!\n"); + printk(BIOS_ERR, "ME is not ready!\n"); return -1; } /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { - printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); + printk(BIOS_WARNING, "ME has bad firmware\n"); return -1; } @@ -78,9 +62,8 @@ int intel_early_me_init(void) int intel_early_me_uma_size(void) { - struct me_uma uma; + union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) }; - pci_read_dword_ptr(&uma, PCI_ME_UMA); if (uma.valid) { printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -108,8 +91,8 @@ int intel_early_me_init_done(u8 status) u8 reset; int count; u32 mebase_l, mebase_h; - struct me_hfs hfs; - struct me_did did = { + union me_hfs hfs; + union me_did did = { .init_done = ME_INIT_DONE, .status = status }; @@ -123,7 +106,7 @@ int intel_early_me_init_done(u8 status) printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " "UMA base: 0x%04x\n", status, did.uma_base); - pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw); /* * The ME firmware does not respond with an ACK when NOMEM or ERROR @@ -134,13 +117,13 @@ int intel_early_me_init_done(u8 status) /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); } if (!count) { - printk(BIOS_ERR, "ERROR: ME failed to respond\n"); + printk(BIOS_ERR, "ME failed to respond\n"); return -1; } diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 41ecac11c5..7e9f4d2c48 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "hda_verb.h" @@ -46,112 +45,3 @@ no_codec: printk(BIOS_DEBUG, "HDA: No codec!\n"); return 0; } - -/* - * Wait 50usec for the codec to indicate it is ready. - * No response would imply that the codec is non-operative. - */ -static int hda_wait_for_ready(u8 *base) -{ - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if (!(reg32 & HDA_ICII_BUSY)) - return 0; - udelay(1); - } - - return -1; -} - -/* - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. - */ -static int hda_wait_for_valid(u8 *base) -{ - u32 reg32; - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - int timeout = 50; - - /* Send the verb to the codec */ - reg32 = read32(base + HDA_ICII_REG); - reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; - write32(base + HDA_ICII_REG, reg32); - - while (timeout--) { - reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) - return 0; - udelay(1); - } - - return -1; -} - -int hda_codec_write(u8 *base, u32 size, const u32 *data) -{ - int i; - - for (i = 0; i < size; i++) { - if (hda_wait_for_ready(base) < 0) - return -1; - - write32(base + HDA_IC_REG, data[i]); - - if (hda_wait_for_valid(base) < 0) - return -1; - } - - return 0; -} - -int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) -{ - const u32 *verb; - u32 reg32, size; - int rc; - - printk(BIOS_DEBUG, "HDA: Initializing codec #%d\n", addr); - - if (!verb_size || !verb_data) { - printk(BIOS_DEBUG, "HDA: No verb list!\n"); - return -1; - } - - /* 1 */ - if (hda_wait_for_ready(base) < 0) { - printk(BIOS_DEBUG, " codec not ready.\n"); - return -1; - } - - reg32 = (addr << 28) | 0x000f0000; - write32(base + HDA_IC_REG, reg32); - - if (hda_wait_for_valid(base) < 0) { - printk(BIOS_DEBUG, " codec not valid.\n"); - return -1; - } - - /* 2 */ - reg32 = read32(base + HDA_IR_REG); - printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32); - - size = azalia_find_verb(verb_data, verb_size, reg32, &verb); - if (!size) { - printk(BIOS_DEBUG, "HDA: No verb table entry found\n"); - return -1; - } - - /* 3 */ - rc = hda_codec_write(base, size, verb); - - if (rc < 0) - printk(BIOS_DEBUG, "HDA: verb not loaded\n"); - else - printk(BIOS_DEBUG, "HDA: verb loaded.\n"); - - return rc; -} diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 07ee513c3c..1d6ef39b98 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -6,7 +6,5 @@ #include int hda_codec_detect(u8 *base); -int hda_codec_write(u8 *base, u32 size, const u32 *data); -int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data); #endif diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 886fd90e9e..ca6aff7df7 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -40,9 +40,9 @@ static const char *const me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u8 *mei_base_address; -static void mei_dump(void *ptr, int dword, int offset, const char *type) +static void mei_dump(u32 dword, int offset, const char *type) { - struct mei_csr *csr; + union mei_csr csr; if (!CONFIG(DEBUG_INTEL_ME)) return; @@ -52,16 +52,12 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) switch (offset) { case MEI_H_CSR: case MEI_ME_CSR_HA: - csr = ptr; - if (!csr) { - printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); - break; - } + csr.raw = dword; printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr.buffer_depth, + csr.buffer_read_ptr, csr.buffer_write_ptr, + csr.ready, csr.reset, csr.interrupt_generate, + csr.interrupt_status, csr.interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -77,64 +73,47 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +static inline union mei_csr read_host_csr(void) { - u32 dword = read32(mei_base_address + offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "READ"); + union mei_csr csr = { .raw = read32(mei_base_address + MEI_H_CSR) }; + mei_dump(csr.raw, MEI_H_CSR, "READ"); + return csr; } -static inline void mei_write_dword_ptr(void *ptr, int offset) +static inline void write_host_csr(union mei_csr csr) { - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); - mei_dump(ptr, dword, offset, "WRITE"); + write32(mei_base_address + MEI_H_CSR, csr.raw); + mei_dump(csr.raw, MEI_H_CSR, "WRITE"); } -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +static inline union mei_csr read_me_csr(void) { - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} - -static inline void read_host_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_H_CSR); -} - -static inline void write_host_csr(struct mei_csr *csr) -{ - mei_write_dword_ptr(csr, MEI_H_CSR); -} - -static inline void read_me_csr(struct mei_csr *csr) -{ - mei_read_dword_ptr(csr, MEI_ME_CSR_HA); + union mei_csr csr = { .raw = read32(mei_base_address + MEI_ME_CSR_HA) }; + mei_dump(csr.raw, MEI_ME_CSR_HA, "READ"); + return csr; } static inline void write_cb(u32 dword) { write32(mei_base_address + MEI_H_CB_WW, dword); - mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); + mei_dump(dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { u32 dword = read32(mei_base_address + MEI_ME_CB_RW); - mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + mei_dump(dword, MEI_ME_CB_RW, "READ"); return dword; } /* Wait for ME ready bit to be asserted */ static int mei_wait_for_me_ready(void) { - struct mei_csr me; + union mei_csr me; unsigned int try = ME_RETRY; while (try--) { - read_me_csr(&me); + me = read_me_csr(); if (me.ready) return 0; udelay(ME_DELAY); @@ -146,31 +125,31 @@ static int mei_wait_for_me_ready(void) static void mei_reset(void) { - struct mei_csr host; + union mei_csr host; if (mei_wait_for_me_ready() < 0) return; /* Reset host and ME circular buffers for next message */ - read_host_csr(&host); + host = read_host_csr(); host.reset = 1; host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); if (mei_wait_for_me_ready() < 0) return; /* Re-init and indicate host is ready */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; host.ready = 1; host.reset = 0; - write_host_csr(&host); + write_host_csr(host); } -static int mei_send_packet(struct mei_header *mei, void *req_data) +static int mei_send_packet(union mei_header *mei, void *req_data) { - struct mei_csr host; + union mei_csr host; unsigned int ndata, n; u32 *data; @@ -190,11 +169,11 @@ static int mei_send_packet(struct mei_header *mei, void *req_data) * Make sure there is still room left in the circular buffer. * Reset the buffer pointers if the requested message will not fit. */ - read_host_csr(&host); + host = read_host_csr(); if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); mei_reset(); - read_host_csr(&host); + host = read_host_csr(); } /* Ensure the requested length will fit in the circular buffer. */ @@ -205,7 +184,7 @@ static int mei_send_packet(struct mei_header *mei, void *req_data) } /* Write MEI header */ - mei_write_dword_ptr(mei, MEI_H_CB_WW); + write_cb(mei->raw); ndata--; /* Write message data */ @@ -214,9 +193,9 @@ static int mei_send_packet(struct mei_header *mei, void *req_data) write_cb(*data++); /* Generate interrupt to the ME */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); /* Make sure ME is ready after sending request data */ return mei_wait_for_me_ready(); @@ -225,11 +204,11 @@ static int mei_send_packet(struct mei_header *mei, void *req_data) static int mei_send_data(u8 me_address, u8 host_address, void *req_data, int req_bytes) { - struct mei_header header = { + union mei_header header = { .client_address = me_address, .host_address = host_address, }; - struct mei_csr host; + union mei_csr host; int current = 0; u8 *req_ptr = req_data; @@ -237,7 +216,7 @@ static int mei_send_data(u8 me_address, u8 host_address, int remain = req_bytes - current; int buf_len; - read_host_csr(&host); + host = read_host_csr(); buf_len = host.buffer_depth - host.buffer_write_ptr; if (buf_len > remain) { @@ -261,7 +240,7 @@ static int mei_send_data(u8 me_address, u8 host_address, static int mei_send_header(u8 me_address, u8 host_address, void *header, int header_len, int complete) { - struct mei_header mei = { + union mei_header mei = { .client_address = me_address, .host_address = host_address, .length = header_len, @@ -273,8 +252,8 @@ static int mei_send_header(u8 me_address, u8 host_address, static int mei_recv_msg(void *header, int header_bytes, void *rsp_data, int rsp_bytes) { - struct mei_header mei_rsp; - struct mei_csr me, host; + union mei_header mei_rsp; + union mei_csr me, host; unsigned int ndata, n; unsigned int expected; u32 *data; @@ -293,7 +272,7 @@ static int mei_recv_msg(void *header, int header_bytes, * expected number of dwords are present in the circular buffer. */ for (n = ME_RETRY; n; --n) { - read_me_csr(&me); + me = read_me_csr(); if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) break; udelay(ME_DELAY); @@ -306,7 +285,7 @@ static int mei_recv_msg(void *header, int header_bytes, } /* Read and verify MEI response header from the ME */ - mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + mei_rsp.raw = read_cb(); if (!mei_rsp.is_complete) { printk(BIOS_ERR, "ME: response is not complete\n"); return -1; @@ -341,10 +320,10 @@ static int mei_recv_msg(void *header, int header_bytes, *data++ = read_cb(); /* Tell the ME that we have consumed the response */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_status = 1; host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); return mei_wait_for_me_ready(); } @@ -417,14 +396,14 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, */ static void intel_me_mbp_give_up(struct device *dev) { - struct mei_csr csr; + union mei_csr csr; pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); - read_host_csr(&csr); + csr = read_host_csr(); csr.reset = 1; csr.interrupt_generate = 1; - write_host_csr(&csr); + write_host_csr(csr); } /* @@ -434,11 +413,11 @@ static void intel_me_mbp_give_up(struct device *dev) static void intel_me_mbp_clear(struct device *dev) { int count; - struct me_hfs2 hfs2; + union me_hfs2 hfs2; /* Wait for the mbp_cleared indicator */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + hfs2.raw = pci_read_config32(dev, PCI_ME_HFS2); if (hfs2.mbp_cleared) break; udelay(ME_DELAY); @@ -452,7 +431,7 @@ static void intel_me_mbp_clear(struct device *dev) } } -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void me_print_fw_version(struct mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -471,7 +450,7 @@ static inline void print_cap(const char *name, int state) } /* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(mbp_mefwcaps *cap) +static int mkhi_get_fwcaps(struct mbp_mefwcaps *cap) { u32 rule_id = 0; struct me_fwcaps cap_msg; @@ -491,9 +470,9 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) } /* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void me_print_fwcaps(struct mbp_mefwcaps *cap) { - mbp_mefwcaps local_caps; + struct mbp_mefwcaps local_caps; if (!cap) { cap = &local_caps; printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); @@ -539,7 +518,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(struct device *dev) { - struct me_hfs hfs; + union me_hfs hfs; u32 reg32; reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -553,8 +532,7 @@ void intel_me_finalize(struct device *dev) intel_me_mbp_clear(dev); /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(dev, PCI_ME_HFS); - memcpy(&hfs, ®32, sizeof(u32)); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); /* Abort and leave device alone if not normal mode */ if (hfs.fpt_bad || @@ -596,17 +574,14 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(struct device *dev) +static enum me_bios_path intel_me_path(struct device *dev) { - me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_hfs2 hfs2; - - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); + enum me_bios_path path = ME_DISABLE_BIOS_PATH; + union me_hfs hfs = { .raw = pci_read_config32(dev, PCI_ME_HFS) }; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; /* Check and dump status */ - intel_me_status(&hfs, &hfs2); + intel_me_status(hfs, hfs2); /* Check Current Working State */ switch (hfs.working_state) { @@ -667,10 +642,10 @@ static me_bios_path intel_me_path(struct device *dev) static int intel_mei_setup(struct device *dev) { struct resource *res; - struct mei_csr host; + union mei_csr host; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; @@ -681,11 +656,11 @@ static int intel_mei_setup(struct device *dev) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; host.ready = 1; host.reset = 0; - write_host_csr(&host); + write_host_csr(host); return 0; } @@ -693,11 +668,10 @@ static int intel_mei_setup(struct device *dev) /* Read the Extend register hash of ME firmware */ static int intel_me_extend_valid(struct device *dev) { - struct me_heres status; + union me_heres status = { .raw = pci_read_config32(dev, PCI_ME_HERES) }; u32 extend[8] = {0}; int i, count = 0; - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); if (!status.extend_feature_present) { printk(BIOS_ERR, "ME: Extend Feature not present\n"); return -1; @@ -738,8 +712,7 @@ static int intel_me_extend_valid(struct device *dev) static u32 me_to_host_words_pending(void) { - struct mei_csr me; - read_me_csr(&me); + union mei_csr me = read_me_csr(); if (!me.ready) return 0; return (me.buffer_write_ptr - me.buffer_read_ptr) & @@ -747,7 +720,7 @@ static u32 me_to_host_words_pending(void) } struct mbp_payload { - mbp_header header; + union mbp_header header; u32 data[0]; }; @@ -757,17 +730,15 @@ struct mbp_payload { * Return -1 to indicate a problem (give up) * Return 0 to indicate success (send LOCK+EOP) */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +static int intel_me_read_mbp(struct me_bios_payload *mbp_data, struct device *dev) { - mbp_header mbp_hdr; + union mbp_header mbp_hdr; u32 me2host_pending; - struct mei_csr host; - struct me_hfs2 hfs2; + union mei_csr host; + union me_hfs2 hfs2 = { .raw = pci_read_config32(dev, PCI_ME_HFS2) }; struct mbp_payload *mbp; int i; - pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); - if (!hfs2.mbp_rdy) { printk(BIOS_ERR, "ME: MBP not ready\n"); goto mbp_failure; @@ -780,7 +751,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) } /* we know for sure that at least the header is there */ - mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); + mbp_hdr.raw = read_cb(); if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || (me2host_pending < mbp_hdr.mbp_size)) { @@ -799,14 +770,14 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) i = 0; while (i != me2host_pending) { - mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); + mbp->data[i] = read_cb(); i++; } /* Signal to the ME that the host has finished reading the MBP. */ - read_host_csr(&host); + host = read_host_csr(); host.interrupt_generate = 1; - write_host_csr(&host); + write_host_csr(host); /* Dump out the MBP contents. */ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { @@ -826,7 +797,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) } /* Setup the pointers in the me_bios_payload structure. */ for (i = 0; i < mbp->header.mbp_size - 1;) { - mbp_item_header *item = (void *)&mbp->data[i]; + struct mbp_item_header *item = (void *)&mbp->data[i]; switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { case MBP_IDENT(KERNEL, FW_VER): @@ -879,8 +850,8 @@ mbp_failure: static void intel_me_init(struct device *dev) { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - me_bios_path path = intel_me_path(dev); - me_bios_payload mbp_data; + enum me_bios_path path = intel_me_path(dev); + struct me_bios_payload mbp_data; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index d908e5b745..fe8b0260c4 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -50,31 +50,37 @@ #define ME_HFS_ACK_GBL_RESET 6 #define ME_HFS_ACK_CONTINUE 7 -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; -} __packed; +union me_hfs { + struct __packed { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; + }; + u32 raw; +}; #define PCI_ME_UMA 0x44 -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; -} __packed; +union me_uma { + struct __packed { + u32 size: 6; + u32 reserved_1: 10; + u32 valid: 1; + u32 reserved_0: 14; + u32 set_to_one: 1; + }; + u32 raw; +}; #define PCI_ME_H_GS 0x4c #define ME_INIT_DONE 1 @@ -83,13 +89,16 @@ struct me_uma { #define ME_INIT_STATUS_ERROR 2 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ -struct me_did { - u32 uma_base: 16; - u32 reserved: 7; - u32 rapid_start: 1; - u32 status: 4; - u32 init_done: 4; -} __packed; +union me_did { + struct __packed { + u32 uma_base: 16; + u32 reserved: 7; + u32 rapid_start: 1; + u32 status: 4; + u32 init_done: 4; + }; + u32 raw; +}; /* * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according @@ -165,22 +174,25 @@ struct me_did { #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc -struct me_hfs2 { - u32 bist_in_progress: 1; - u32 reserved1: 2; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 mbp_rdy: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; - u32 reserved2: 4; - u32 mbp_cleared: 1; - u32 reserved3: 2; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; -} __packed; +union me_hfs2 { + struct __packed { + u32 bist_in_progress: 1; + u32 reserved1: 2; + u32 invoke_mebx: 1; + u32 cpu_replaced_sts: 1; + u32 mbp_rdy: 1; + u32 mfs_failure: 1; + u32 warm_reset_request: 1; + u32 cpu_replaced_valid: 1; + u32 reserved2: 4; + u32 mbp_cleared: 1; + u32 reserved3: 2; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; + }; + u32 raw; +}; #define PCI_ME_H_GS2 0x70 #define PCI_ME_MBP_GIVE_UP 0x01 @@ -190,12 +202,15 @@ struct me_hfs2 { #define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; -} __packed; +union me_heres { + struct __packed { + u32 extend_reg_algorithm: 4; + u32 reserved: 26; + u32 extend_feature_present: 1; + u32 extend_reg_valid: 1; + }; + u32 raw; +}; /* * Management Engine MEI registers @@ -206,17 +221,20 @@ struct me_heres { #define MEI_ME_CB_RW 0x08 #define MEI_ME_CSR_HA 0x0c -struct mei_csr { - u32 interrupt_enable: 1; - u32 interrupt_status: 1; - u32 interrupt_generate: 1; - u32 ready: 1; - u32 reset: 1; - u32 reserved: 3; - u32 buffer_read_ptr: 8; - u32 buffer_write_ptr: 8; - u32 buffer_depth: 8; -} __packed; +union mei_csr { + struct __packed { + u32 interrupt_enable: 1; + u32 interrupt_status: 1; + u32 interrupt_generate: 1; + u32 ready: 1; + u32 reset: 1; + u32 reserved: 3; + u32 buffer_read_ptr: 8; + u32 buffer_write_ptr: 8; + u32 buffer_depth: 8; + }; + u32 raw; +}; #define MEI_ADDRESS_CORE 0x01 #define MEI_ADDRESS_AMT 0x02 @@ -228,13 +246,16 @@ struct mei_csr { #define MEI_HOST_ADDRESS 0 -struct mei_header { - u32 client_address: 8; - u32 host_address: 8; - u32 length: 9; - u32 reserved: 6; - u32 is_complete: 1; -} __packed; +union mei_header { + struct __packed { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + }; + u32 raw; +}; #define MKHI_GROUP_ID_CBM 0x00 #define MKHI_GROUP_ID_FWCAPS 0x03 @@ -303,17 +324,17 @@ struct me_global_reset { u8 reset_type; } __packed; -typedef enum { +enum me_bios_path { ME_NORMAL_BIOS_PATH, ME_S3WAKE_BIOS_PATH, ME_ERROR_BIOS_PATH, ME_RECOVERY_BIOS_PATH, ME_DISABLE_BIOS_PATH, ME_FIRMWARE_UPDATE_BIOS_PATH, -} me_bios_path; +}; /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); +void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2); void intel_early_me_status(void); int intel_early_me_init(void); @@ -353,27 +374,30 @@ void intel_me_finalize(struct device *dev); #define MBP_IDENT(appid, item) \ MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) -typedef struct { - u32 mbp_size : 8; - u32 num_entries : 8; - u32 rsvd : 16; -} __packed mbp_header; +union mbp_header { + struct __packed { + u32 mbp_size : 8; + u32 num_entries : 8; + u32 rsvd : 16; + }; + u32 raw; +}; -typedef struct { +struct mbp_item_header { u32 app_id : 8; u32 item_id : 8; u32 length : 8; u32 rsvd : 8; -} __packed mbp_item_header; +} __packed; -typedef struct { +struct mbp_fw_version_name { u32 major_version : 16; u32 minor_version : 16; u32 hotfix_version : 16; u32 build_version : 16; -} __packed mbp_fw_version_name; +} __packed; -typedef struct { +struct mbp_mefwcaps { u32 full_net : 1; u32 std_net : 1; u32 manageability : 1; @@ -393,19 +417,19 @@ typedef struct { u32 reserved_4 : 1; u32 wlan : 1; u32 reserved_5 : 8; -} __packed mbp_mefwcaps; +} __packed; -typedef struct { +struct mbp_rom_bist_data { u16 device_id; u16 fuse_test_flags; u32 umchid[4]; -} __packed mbp_rom_bist_data; +} __packed; -typedef struct { +struct mbp_platform_key { u32 key[8]; -} mbp_platform_key; +}; -typedef struct { +struct mbp_me_firmware_type { u32 mobile: 1; u32 desktop: 1; u32 server: 1; @@ -417,70 +441,70 @@ typedef struct { u32 image_type: 4; u32 brand: 4; u32 rsvd1: 16; -} __packed mbp_me_firmware_type; +} __packed; -typedef struct { - mbp_me_firmware_type rule_data; - u8 available; -} mbp_plat_type; +struct mbp_plat_type { + struct mbp_me_firmware_type rule_data; + u8 available; +}; -typedef struct { +struct icc_address_mask { u16 icc_start_address; u16 mask; -} __packed icc_address_mask; +} __packed; -typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 icc_reg_bundles; - icc_address_mask icc_address_mask[0]; -} __packed mbp_icc_profile; +struct mbp_icc_profile { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 icc_reg_bundles; + struct icc_address_mask icc_address_mask[0]; +} __packed; -typedef struct { +struct tdt_state_flag { u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; -} __packed tdt_state_flag; +} __packed; -typedef struct { - u8 state; - u8 last_theft_trigger; - tdt_state_flag flags; -} __packed mbp_at_state; +struct mbp_at_state { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +} __packed; -typedef struct { +struct mbp_plat_time { u32 wake_event_mrst_time_ms; u32 mrst_pltrst_time_ms; u32 pltrst_cpurst_time_ms; -} __packed mbp_plat_time; +} __packed; -typedef struct { +struct mbp_nfc_data { u32 device_type : 2; u32 reserved : 30; -} __packed mbp_nfc_data; +} __packed; -typedef struct { - mbp_fw_version_name *fw_version_name; - mbp_mefwcaps *fw_capabilities; - mbp_rom_bist_data *rom_bist_data; - mbp_platform_key *platform_key; - mbp_plat_type *fw_plat_type; - mbp_icc_profile *icc_profile; - mbp_at_state *at_state; - u32 *mfsintegrity; - mbp_plat_time *plat_time; - mbp_nfc_data *nfc_data; -} me_bios_payload; +struct me_bios_payload { + struct mbp_fw_version_name *fw_version_name; + struct mbp_mefwcaps *fw_capabilities; + struct mbp_rom_bist_data *rom_bist_data; + struct mbp_platform_key *platform_key; + struct mbp_plat_type *fw_plat_type; + struct mbp_icc_profile *icc_profile; + struct mbp_at_state *at_state; + u32 *mfsintegrity; + struct mbp_plat_time *plat_time; + struct mbp_nfc_data *nfc_data; +}; struct me_fwcaps { u32 id; u8 length; - mbp_mefwcaps caps_sku; + struct mbp_mefwcaps caps_sku; u8 reserved[3]; } __packed; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index fb4490f867..f9e0fcbb5b 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -123,72 +123,72 @@ static const char *me_progress_policy_values[] = { [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) +void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2) { if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); + hfs.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); + hfs.ft_bup_ld_flr ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); + hfs.fw_init_complete ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); + hfs.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); + hfs.boot_options_present ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); + hfs.update_in_progress ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); + me_cws_values[hfs.working_state]); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); + me_opstate_values[hfs.operation_state]); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); + me_opmode_values[hfs.operation_mode]); printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); + me_error_values[hfs.error_code]); printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); + me_progress_values[hfs2.progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); + me_pmevent_values[hfs2.current_pmevent]); printk(BIOS_DEBUG, "ME: Progress Phase State : "); - switch (hfs2->progress_code) { + switch (hfs2.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); + me_progress_rom_values[hfs2.current_state]); break; case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) - && me_progress_bup_values[hfs2->current_state]) + if (hfs2.current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[hfs2.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); + me_progress_bup_values[hfs2.current_state]); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_POLICY: /* Policy Module Phase */ - if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) - && me_progress_policy_values[hfs2->current_state]) + if (hfs2.current_state < ARRAY_SIZE(me_progress_policy_values) + && me_progress_policy_values[hfs2.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[hfs2->current_state]); + me_progress_policy_values[hfs2.current_state]); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; case ME_HFS2_PHASE_HOST_COMM: /* Host Communication Phase */ - if (!hfs2->current_state) + if (!hfs2.current_state) printk(BIOS_DEBUG, "Host communication established"); else - printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); + printk(BIOS_DEBUG, "0x%02x", hfs2.current_state); break; default: printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", - hfs2->progress_code, hfs2->current_state); + hfs2.progress_code, hfs2.current_state); } printk(BIOS_DEBUG, "\n"); } diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1a338b14ec..8f7cdb8cc0 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 5f21e619a5..30773e63b2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -28,7 +28,7 @@ struct root_port_config { u32 b0d28f0_32c; u32 b0d28f4_32c; u32 b0d28f5_32c; - int coalesce; + bool coalesce; int gbe_port; int num_ports; struct device *ports[MAX_NUM_ROOT_PORTS]; @@ -304,7 +304,7 @@ static void root_port_commit_config(void) /* If the first root port is disabled the coalesce ports. */ if (!is_rp_enabled(1)) - rpc.coalesce = 1; + rpc.coalesce = true; /* Perform clock gating configuration. */ pcie_enable_clock_gating(); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 34f8c78c6d..0aa683d633 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -166,10 +166,10 @@ static void serialio_init(struct device *dev) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ - bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!bar0) return; - bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); + bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1); if (!bar1) return; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index d55aa6e3d0..f41e322b82 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -18,7 +18,7 @@ static void pch_smbus_init(struct device *dev) pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c index 340bc30d4d..f8c4472ce8 100644 --- a/src/superio/fintek/f71808a/f71808a_hwm.c +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -35,7 +35,7 @@ void f71808a_hwm_init(struct device *dev) { - struct resource *res = find_resource(dev, PNP_IDX_IO0); + struct resource *res = probe_resource(dev, PNP_IDX_IO0); if (!res) { printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 6333ae160a..9add2a779e 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -41,7 +41,7 @@ void f71869ad_hwm_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; - struct resource *res = find_resource(dev, PNP_IDX_IO0); + struct resource *res = probe_resource(dev, PNP_IDX_IO0); if (!res) { printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index a7ed96bb26..a82adb3472 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -38,7 +38,7 @@ void f81866d_hwm_init(struct device *dev) { - struct resource *res = find_resource(dev, PNP_IDX_IO0); + struct resource *res = probe_resource(dev, PNP_IDX_IO0); if (!res) { printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c index 7d98a7fd2f..f6ebbfcac8 100644 --- a/src/superio/fintek/f81866d/f81866d_uart.c +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -19,7 +19,7 @@ */ void f81866d_uart_init(struct device *dev) { - struct resource *res = find_resource(dev, PNP_IDX_IO0); + struct resource *res = probe_resource(dev, PNP_IDX_IO0); u8 tmp; if (!res) { diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c index 4d12457e0d..c18c3ec357 100644 --- a/src/superio/ite/it8613e/superio.c +++ b/src/superio/ite/it8613e/superio.c @@ -19,7 +19,7 @@ static void it8613e_init(struct device *dev) switch (dev->path.pnp.device) { case IT8613E_EC: - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index ca3455ae1e..15e0071db8 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -19,7 +19,7 @@ static void it8623e_init(struct device *dev) switch (dev->path.pnp.device) { case IT8623E_EC: - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index aab554fe95..1243e75fcf 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -24,7 +24,7 @@ static void init(struct device *dev) break; case IT8718F_EC: conf = dev->chip_info; - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index c63fa9ab4f..75d0be9c02 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -51,7 +51,7 @@ static void it8720f_init(struct device *dev) switch (dev->path.pnp.device) { case IT8720F_EC: conf = dev->chip_info; - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 22e6ecbf95..67ef2181fd 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -20,7 +20,7 @@ static void it8728f_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need code for FDC etc. */ case IT8728F_EC: - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 6672cdc979..82f30fa6cd 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -171,7 +171,7 @@ static void it8772f_init(struct device *dev) switch (dev->path.pnp.device) { case IT8772F_EC: - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!res) break; @@ -203,7 +203,7 @@ static void it8772f_init(struct device *dev) break; case IT8772F_GPIO: /* Set GPIO output levels */ - res = find_resource(dev, PNP_IDX_IO1); + res = probe_resource(dev, PNP_IDX_IO1); if (res) { if (conf->gpio_set1) outb(conf->gpio_set1, res->base + 0); diff --git a/src/superio/ite/it8783ef/superio.c b/src/superio/ite/it8783ef/superio.c index feb373f709..d90ae5f3b7 100644 --- a/src/superio/ite/it8783ef/superio.c +++ b/src/superio/ite/it8783ef/superio.c @@ -20,7 +20,7 @@ static void it8783ef_init(struct device *const dev) switch (dev->path.pnp.device) { case IT8783EF_EC: conf = dev->chip_info; - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c index 55fff9154d..8d9ec1477e 100644 --- a/src/superio/ite/it8786e/superio.c +++ b/src/superio/ite/it8786e/superio.c @@ -20,7 +20,7 @@ static void it8786e_init(struct device *const dev) switch (dev->path.pnp.device) { case IT8786E_EC: conf = dev->chip_info; - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 3351ad980e..cfa22280fc 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -156,7 +156,7 @@ static void disable_gpio_io_port(struct device *dev) if (!((gpio0 && gpio0->enabled) || (gpio1 && gpio1->enabled) || (gpio6 && gpio6->enabled))) { dev->enabled = 0; - printk(BIOS_WARNING, "WARNING: GPIO IO port configured," + printk(BIOS_WARNING, "GPIO IO port configured," " but no GPIO enabled. Disabling..."); } } @@ -183,7 +183,7 @@ static void nct5104d_init(struct device *dev) case NCT5104D_GPIO0: case NCT5104D_GPIO1: route_pins_to_uart(dev, false); - /* FALLTHROUGH */ + __fallthrough; case NCT5104D_GPIO6: if (conf->reset_gpios) reset_gpio_default_in(dev); diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index b0e00fbf08..7e893eee54 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "nct5572d.h" diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 9889980650..f1db50934a 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -60,7 +60,7 @@ static void npcd378_init(struct device *dev) pc_keyboard_init(PROBE_AUX_DEVICE); break; case NPCD378_HWM: - res = find_resource(dev, PNP_IDX_IO0); + res = probe_resource(dev, PNP_IDX_IO0); if (!res || !res->base) { printk(BIOS_ERR, "NPCD378: LDN%u IOBASE not set.\n", NPCD378_HWM); break; diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index 36f3b36cde..41d7860c1f 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -57,7 +57,7 @@ void try_enabling_LPC47N207_uart(void) outb(0x12, lpc_port); reg_value = inb(lpc_port + 1); if (reg_value != (lpc_port & 0xff)) - break; + break; outb(0x13, lpc_port); reg_value = inb(lpc_port + 1); diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index a716d1937d..dcaf6e760b 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -113,7 +113,7 @@ static void lpc47n217_init(struct device *dev) static void lpc47n217_pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", + printk(BIOS_ERR, "%s %02lx not allocated\n", dev_path(dev), resource->index); return; } @@ -131,7 +131,7 @@ static void lpc47n217_pnp_set_resource(struct device *dev, struct resource *reso } else if (resource->flags & IORESOURCE_IRQ) { lpc47n217_pnp_set_irq(dev, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", + printk(BIOS_ERR, "%s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 376fddb4e2..37123509a9 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -121,7 +121,7 @@ static void lpc47n227_init(struct device *dev) static void lpc47n227_pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", + printk(BIOS_ERR, "%s %02lx not allocated\n", dev_path(dev), resource->index); return; } @@ -138,7 +138,7 @@ static void lpc47n227_pnp_set_resource(struct device *dev, struct resource *reso } else if (resource->flags & IORESOURCE_IRQ) { lpc47n227_pnp_set_irq(dev, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", + printk(BIOS_ERR, "%s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } diff --git a/src/superio/smsc/sch5545/sch5545_early_init.c b/src/superio/smsc/sch5545/sch5545_early_init.c index ed4fa5337b..d77ed0d750 100644 --- a/src/superio/smsc/sch5545/sch5545_early_init.c +++ b/src/superio/smsc/sch5545/sch5545_early_init.c @@ -100,6 +100,13 @@ void sch5545_early_init(unsigned int port) sch5545_set_led(SCH5545_RUNTIME_REG_BASE, SCH5545_LED_COLOR_GREEN, SCH5545_LED_BLINK_ON); + /* + * Clear global PME status and disable PME generation to avoid + * unexpected wakeups or hangs. OS will re-enable it via ACPI. + */ + outb(0, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_EN); + outb(1, SCH5545_RUNTIME_REG_BASE + SCH5545_RR_PME_STS); + /* Configure EMI */ dev = PNP_DEV(port, SCH5545_LDN_LPC); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/sch5545/superio.c b/src/superio/smsc/sch5545/superio.c index b6e5308f3c..1ce1fd61aa 100644 --- a/src/superio/smsc/sch5545/superio.c +++ b/src/superio/smsc/sch5545/superio.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include #include #include -#include +#include #include "sch5545.h" @@ -62,6 +63,12 @@ static void sch5545_init(struct device *dev) switch (dev->path.pnp.device) { case SCH5545_LDN_KBC: + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + /* Disable PS/2 clock and data isolation */ + pnp_unset_and_set_config(dev, 0xf0, + SCH5545_KBD_ISOLATION | SCH5545_MOUSE_ISOLATION, 0); + pnp_exit_conf_mode(dev); pc_keyboard_init(NO_AUX_DEVICE); break; case SCH5545_LDN_LPC: @@ -83,7 +90,7 @@ static void sch5545_set_iobase(struct device *dev, u8 index, u16 iobase) lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); if (!lpc_if) { - printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + printk(BIOS_ERR, "%s LPC interface LDN not present." "Check the devicetree!\n", dev_path(dev)); return; } @@ -145,7 +152,7 @@ static void sch5545_set_irq(struct device *dev, u8 index, u8 irq) lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); if (!lpc_if) { - printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + printk(BIOS_ERR, "%s LPC interface LDN not present." "Check the devicetree!\n", dev_path(dev)); return; } @@ -186,7 +193,7 @@ static void sch5545_set_drq(struct device *dev, u8 index, u8 drq) struct device *lpc_if; if (drq == 4) { - printk(BIOS_ERR, "ERROR: %s %02x: Trying to set reserved DMA channel 4!\n", + printk(BIOS_ERR, "%s %02x: Trying to set reserved DMA channel 4!\n", dev_path(dev), index); printk(BIOS_ERR, "This configuration is untested. Trying to continue.\n"); } @@ -195,7 +202,7 @@ static void sch5545_set_drq(struct device *dev, u8 index, u8 drq) lpc_if = dev_find_slot_pnp(dev->path.pnp.port, SCH5545_LDN_LPC); if (!lpc_if) { - printk(BIOS_ERR, "ERROR: %s LPC interface LDN not present." + printk(BIOS_ERR, "%s LPC interface LDN not present." "Check the devicetree!\n", dev_path(dev)); return; } @@ -226,12 +233,12 @@ static void sch5545_set_resource(struct device *dev, struct resource *resource) if (resource->flags & IORESOURCE_IRQ && (resource->index != PNP_IDX_IRQ0) && (resource->index != PNP_IDX_IRQ1)) - printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " + printk(BIOS_WARNING, "%s %02lx %s size: " "0x%010llx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); else - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " + printk(BIOS_ERR, "%s %02lx %s size: 0x%010llx " "not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; @@ -245,7 +252,7 @@ static void sch5545_set_resource(struct device *dev, struct resource *resource) } else if (resource->flags & IORESOURCE_IRQ) { sch5545_set_irq(dev, resource->index, resource->base); } else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", + printk(BIOS_ERR, "%s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 20610301d6..cc4bb87d0c 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -204,7 +204,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -306,7 +306,7 @@ Device(SIO) { EXIT_CONFIG_MODE () ShiftLeft(Local1, 8, Local1) Or(Local1, Local2, Local1) - If (LNot(Local0)) { + If (!Local0) { Return (FDE) } @@ -428,7 +428,7 @@ Device(SIO) { Store (0x0D, Local0) } } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -583,7 +583,7 @@ Device(SIO) { /* DMA off */ Store (0x04, DMA0) /* IRQ */ - Subtract(FindSetLeftBit (IRQL), 1, IRQ0) + IRQ0 = FindSetLeftBit (IRQL) - 1 /* Activate */ Store (One, ACTR) EXIT_CONFIG_MODE () @@ -605,7 +605,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -701,7 +701,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - Subtract(FindSetLeftBit (IRQL), 1, Local3) + Local3 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (2) Store (Local0, IO1L) @@ -724,12 +724,12 @@ Device(SIO) { { Store (0x00, Local0) ENTER_CONFIG_MODE (3) - If (LNot(And(OPT2, 0x30))) + If (!And(OPT2, 0x30)) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -826,7 +826,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - Subtract(FindSetLeftBit (IRQL), 1, Local3) + Local3 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (3) Store (Local0, IO1L) @@ -854,7 +854,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -951,7 +951,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - Subtract(FindSetLeftBit (IRQL), 1, Local3) + Local3 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (3) Store (Local0, IO1L) @@ -978,7 +978,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } @@ -1038,7 +1038,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) - Subtract(FindSetLeftBit (IRQL), 1, Local3) + Local3 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (6) Store (Local0, IO1L) @@ -1064,7 +1064,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) + ElseIf (IO1H || IO1L || IO2H || IO2L) { #ifdef W83627HF_KBC_COMPAT Store (0x0F, Local0) @@ -1143,7 +1143,7 @@ Device(SIO) { Divide(IOA0, 256, Local0, Local1) Divide(IOA1, 256, Local2, Local3) - Subtract(FindSetLeftBit (IRQL), 1, Local4) + Local4 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (5) Store (Local0, IO1L) @@ -1166,10 +1166,10 @@ Device(SIO) { { Store (0x00, Local0) ENTER_CONFIG_MODE (5) - If (LAnd(ACTR, IRQ1) ) { + If (ACTR && IRQ1) { Store (0x0F, Local0) } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) + ElseIf (IO1H || IO1L || IO2H || IO2L) { #ifdef W83627HF_KBC_COMPAT Store (0x0F, Local0) @@ -1222,7 +1222,7 @@ Device(SIO) { }) CreateWordField (Arg0, IRQX._INT, IRQL) - Subtract(FindSetLeftBit (IRQL), 1, Local0) + Local0 = FindSetLeftBit (IRQL) - 1 ENTER_CONFIG_MODE (5) Store (Local0, IRQ1) @@ -1244,8 +1244,8 @@ Device(SIO) { Method (_STA) { Store(0, Local0) ENTER_CONFIG_MODE (7) - If (LOr(IO1L, IO1H)) { - If (LOr(ACTR, ACT1)) { + If (IO1L || IO1H) { + If (ACTR || ACT1) { Store (0x0F, Local0) } Else { @@ -1299,8 +1299,8 @@ Device(SIO) { { Store(0, Local0) ENTER_CONFIG_MODE (7) - If (LOr(IO2L, IO2H)) { - If (LOr(ACTR, ACT2)) { + If (IO2L || IO2H) { + If (ACTR || ACT2) { Store (0x0F, Local0) } Else { @@ -1377,7 +1377,7 @@ Device(SIO) { If (ACTR) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) + ElseIf (IO1H || IO1L) { Store (0x0D, Local0) } diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 0a068983a8..a5abe61818 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "w83667hg-a.h" diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index 08d63da530..eda674449a 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -299,8 +299,8 @@ Device (ECP) /* Report a second port range that is 0x400 above base port. */ CreateByteField (BUF6, 0x0B, I2HI) CreateByteField (BUF6, 0x0D, I2RH) - Add (I2HI, 0x04, I2RH) - Add (I2HI, 0x04, I2HI) + I2RH = I2HI + 4 + I2HI = I2HI + 4 EXIT_CONFIG_MODE() Return (BUF6) } diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 4103961f64..2317daf23a 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -1088,9 +1088,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index fa1bca1955..798c1cc0cd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2444,9 +2444,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 8735dac224..9f63f42d90 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -229,7 +229,7 @@ cpuF15AddingMmioMap ( MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; MmioRange[MmioPair].Modified = TRUE; - for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { + for (i = 1; ((MmioPair + i) < MMIO_REG_PAIR_NUM) && NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 2a588698b5..8896b03dc0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -1451,9 +1451,9 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_LHTC_TEMPERATURE_LIMIT (0) #endif -#define CFG_PCI_MMIO_BASE (CONFIG_MMCONF_BASE_ADDRESS) +#define CFG_PCI_MMIO_BASE (CONFIG_ECAM_MMCONF_BASE_ADDRESS) -#define CFG_PCI_MMIO_SIZE (CONFIG_MMCONF_BUS_NUMBER) +#define CFG_PCI_MMIO_SIZE (CONFIG_ECAM_MMCONF_BUS_NUMBER) #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c index 714f970d78..bf95357b7f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c @@ -225,7 +225,7 @@ cpuF16AddingMmioMap ( MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; MmioRange[MmioPair].Modified = TRUE; - for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { + for (i = 1; ((MmioPair + i) < MMIO_REG_PAIR_NUM) && NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index d81f93c370..c184c657ca 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -52,7 +52,7 @@ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + #define PCIEX_BASE_ADDRESS CONFIG_ECAM_MMCONF_BASE_ADDRESS #endif /** diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42169..38aa36cb07 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -95,7 +95,14 @@ typedef struct __packed { /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; - /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; + /** Offset 0x04DC**/ uint8_t edp_phy_override; + /** Offset 0x04DD**/ uint8_t edp_physel; + /** Offset 0x04DE**/ uint8_t dp_vs_pemph_level; + /** Offset 0x04DF**/ uint8_t tx_eq_main; + /** Offset 0x04E0**/ uint8_t tx_eq_pre; + /** Offset 0x04E1**/ uint8_t tx_eq_post; + /** Offset 0x04E2**/ uint8_t tx_vboost_lvl; + /** Offset 0x04E3**/ uint8_t UnusedUpdSpace2[285]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; @@ -107,4 +114,10 @@ typedef struct __packed { /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + + #endif diff --git a/src/vendorcode/amd/fsp/cezanne/dmi_info.h b/src/vendorcode/amd/fsp/cezanne/dmi_info.h index 304f3876ab..d2c26fad4c 100644 --- a/src/vendorcode/amd/fsp/cezanne/dmi_info.h +++ b/src/vendorcode/amd/fsp/cezanne/dmi_info.h @@ -227,6 +227,9 @@ typedef struct { OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any. OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any. OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes. + // SMBIOS 3.3 + OUT UINT32 ExtendedSpeed; ///< Extended Speed + OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed } __packed TYPE17_DMI_INFO; /// Collection of pointers to the DMI records diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index 06e9defea7..d88bfe1801 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -50,6 +50,8 @@ #define SVC_READ_TIMER_VAL 0x68 #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A +#define SVC_SET_PLATFORM_BOOT_MODE 0x6C +#define SVC_WRITE_POSTCODE 0x6D struct mod_exp_params { char *pExponent; // Exponent address @@ -86,10 +88,17 @@ enum fch_io_device { FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; +enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + enum fch_i2c_controller_id { FCH_I2C_CONTROLLER_ID_0 = 0, FCH_I2C_CONTROLLER_ID_1 = 1, @@ -135,6 +144,19 @@ struct sha_generic_data { uint32_t Eom; }; +/* + * This is state that PSP manages internally. + * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_PRODUCTION in verstage. + */ +enum chrome_platform_boot_mode +{ + NON_CHROME_BOOK_BOOT_MODE = 0x0, + CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, + CHROME_BOOK_BOOT_MODE_PRODUCTION = 0x2, + CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, + CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check +}; + /* * Exit to the main Boot Loader. This does not return back to user application. * @@ -313,6 +335,14 @@ uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); */ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); +/* + * Get the Platform boot mode from verstage. Production or developer + * + * Parameters: + * - boot mode + -----------------------------------------------------------------------------*/ +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode); + /* C entry point for the Bootloader Userspace Application */ void Main(void); diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 28b000bb13..abb61acb4c 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -79,4 +79,9 @@ typedef struct __packed { /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; } FSPM_UPD; +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x02 +#define IMAGE_REVISION_BUILD_NUMBER 0x04 + #endif diff --git a/src/vendorcode/amd/fsp/sabrina/FspGuids.h b/src/vendorcode/amd/fsp/sabrina/FspGuids.h new file mode 100644 index 0000000000..0eca78e711 --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/FspGuids.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __FSP_GUIDS__ +#define __FSP_GUIDS__ + +#include + +#define AMD_FSP_TSEG_HOB_GUID \ + GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ + 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \ + GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \ + 0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C ) + +#endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/sabrina/FspUpd.h b/src/vendorcode/amd/fsp/sabrina/FspUpd.h new file mode 100644 index 0000000000..c9202cea9c --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/FspUpd.h @@ -0,0 +1,22 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#ifdef EFI32 +# include +# include +#else +# include +#endif + +#define FSPM_UPD_SIGNATURE 0x4d5f454e415a4543 /* 'CEZANE_M' */ + +#define FSPS_UPD_SIGNATURE 0x535f454e415a4543 /* 'CEZANE_S' */ + + +#endif diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h new file mode 100644 index 0000000000..6563cacc81 --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h @@ -0,0 +1,56 @@ +#ifndef __FSPUSB_H__ +#define __FSPUSB_H__ + +#include + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 4 +#define USBC_COMBO_PHY_COUNT 2 + +struct fch_usb2_phy { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +} __packed; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +} __packed; + +#define USB0_PORT0 0 +#define USB0_PORT1 1 +#define USB0_PORT2 1 +#define USB0_PORT3 3 +#define USB1_PORT0 (0<<2) +#define USB1_PORT1 (1<<2) +#define USB1_PORT2 (1<<2) +#define USB1_PORT3 (3<<2) + +#define USB_COMBO_PHY_MODE_USB_C 0 +#define USB_COMBO_PHY_MODE_USB_ONLY 1 +#define USB_COMBO_PHY_MODE_USB_DPM 2 +#define USB_COMBO_PHY_MODE_USB_DPP 3 + +struct usb_phy_config { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +} __packed; + +#endif diff --git a/src/vendorcode/amd/fsp/sabrina/FspmUpd.h b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h new file mode 100644 index 0000000000..f42ed4365c --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h @@ -0,0 +1,115 @@ +/** @file + * + * This file is _NOT_ automatically generated in coreboot! + * + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include +#include + +#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14 +#define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5 + +/** Fsp M Configuration +**/ +typedef struct __packed { + /** Offset 0x0040**/ uint32_t bert_size; + /** Offset 0x0044**/ uint32_t tseg_size; + /** Offset 0x0048**/ uint32_t pci_express_base_addr; + /** Offset 0x004C**/ uint8_t misc_reserved[32]; + /** Offset 0x006C**/ uint32_t serial_port_base; + /** Offset 0x0070**/ uint32_t serial_port_use_mmio; + /** Offset 0x0074**/ uint32_t serial_port_baudrate; + /** Offset 0x0078**/ uint32_t serial_port_refclk; + /** Offset 0x007C**/ uint32_t serial_reserved; + /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; + /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; + /** Offset 0x0359**/ uint8_t pcie_reserved[51]; + /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; + /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; + /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; + /** Offset 0x03A7**/ uint8_t ccx_disable_smt; + /** Offset 0x03A8**/ uint8_t ccx_reserved[32]; + /** Offset 0x03C8**/ uint8_t stt_control; + /** Offset 0x03C9**/ uint8_t stt_pcb_sensor_count; + /** Offset 0x03CA**/ uint16_t stt_min_limit; + /** Offset 0x03CC**/ uint16_t stt_m1; + /** Offset 0x03CE**/ uint16_t stt_m2; + /** Offset 0x03D0**/ uint16_t stt_m3; + /** Offset 0x03D2**/ uint16_t stt_m4; + /** Offset 0x03D4**/ uint16_t stt_m5; + /** Offset 0x03D6**/ uint16_t stt_m6; + /** Offset 0x03D8**/ uint16_t stt_c_apu; + /** Offset 0x03DA**/ uint16_t stt_c_gpu; + /** Offset 0x03DC**/ uint16_t stt_c_hs2; + /** Offset 0x03DE**/ uint16_t stt_alpha_apu; + /** Offset 0x03E0**/ uint16_t stt_alpha_gpu; + /** Offset 0x03E2**/ uint16_t stt_alpha_hs2; + /** Offset 0x03E4**/ uint16_t stt_skin_temp_apu; + /** Offset 0x03E6**/ uint16_t stt_skin_temp_gpu; + /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; + /** Offset 0x03EA**/ uint16_t stt_error_coeff; + /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; + /** Offset 0x03EE**/ uint8_t smartshift_enable; + /** Offset 0x03EF**/ uint32_t apu_only_sppt_limit; + /** Offset 0x03F3**/ uint32_t sustained_power_limit; + /** Offset 0x03F7**/ uint32_t fast_ppt_limit; + /** Offset 0x03FB**/ uint32_t slow_ppt_limit; + /** Offset 0x03FF**/ uint8_t system_configuration; + /** Offset 0x0400**/ uint8_t cppc_ctrl; + /** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range; + /** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range; + /** Offset 0x0403**/ uint8_t cppc_epp_max_range; + /** Offset 0x0404**/ uint8_t cppc_epp_min_range; + /** Offset 0x0405**/ uint8_t cppc_preferred_cores; + /** Offset 0x0406**/ uint8_t stapm_boost; + /** Offset 0x0407**/ uint32_t stapm_time_constant; + /** Offset 0x040B**/ uint32_t slow_ppt_time_constant; + /** Offset 0x040F**/ uint32_t thermctl_limit; + /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9]; + /** Offset 0x041C**/ uint8_t iommu_support; + /** Offset 0x041D**/ uint8_t pspp_policy; + /** Offset 0x041E**/ uint8_t enable_nb_azalia; + /** Offset 0x041F**/ uint8_t audio_io_ctl; + /** Offset 0x0420**/ uint8_t pdm_mic_selection; + /** Offset 0x0421**/ uint8_t hda_enable; + /** Offset 0x0422**/ uint8_t nbio_reserved[31]; + /** Offset 0x0441**/ uint32_t emmc0_mode; + /** Offset 0x0445**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85]; + /** Offset 0x049F**/ uint32_t gnb_ioapic_base; + /** Offset 0x04A3**/ uint8_t gnb_ioapic_id; + /** Offset 0x04A4**/ uint8_t fch_ioapic_id; + /** Offset 0x04A5**/ uint8_t sata_enable; + /** Offset 0x04A6**/ uint8_t fch_reserved[32]; + /** Offset 0x04C6**/ uint8_t s0i3_enable; + /** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current; + /** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset; + /** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current; + /** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset; + /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; + /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; + /** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; + /** Offset 0x0600**/ uint16_t UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; + /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#define IMAGE_REVISION_MAJOR_VERSION 0x01 +#define IMAGE_REVISION_MINOR_VERSION 0x00 +#define IMAGE_REVISION_REVISION 0x05 +#define IMAGE_REVISION_BUILD_NUMBER 0x00 + +#endif diff --git a/src/vendorcode/amd/fsp/sabrina/FspsUpd.h b/src/vendorcode/amd/fsp/sabrina/FspsUpd.h new file mode 100644 index 0000000000..3ac52c097f --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/FspsUpd.h @@ -0,0 +1,26 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include + +typedef struct __packed { + /** Offset 0x0020**/ uint32_t vbios_buffer; + /** Offset 0x0024**/ uint64_t gop_reserved; + /** Offset 0x002C**/ uint32_t reserved1; + /** Offset 0x0030**/ uint16_t UpdTerminator; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig; +} FSPS_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S new file mode 100644 index 0000000000..40ea4111cd --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S @@ -0,0 +1,44 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.arm +.global LastBytes +.section PSP_FOOTER_DATA, "ad", %note +.balign 64 + +// Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte +// in size so that the binary size is multiple of 64 bytes. +// +LastBytes: + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + +.end diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc new file mode 100644 index 0000000000..35c906a445 --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.global LastBytes + +#define BL_UAPP_START_ADDRESS 0x00036000 +#define SIZE_OF_THIS_HEADER 256 +#define SIZE_OF_PSP_END 64 +#define IMAGE_SIZE LastBytes + SIZE_OF_PSP_END - BL_UAPP_START_ADDRESS - SIZE_OF_THIS_HEADER + +#define IMAGE_VERSION 0x01,0x00,0x00,0x00 +#define FW_TYPE 0x52 + + + // 256 byte binary header + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 // nonce + .byte 0x00,0x00,0x00,0x00 // header version + .word IMAGE_SIZE + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte IMAGE_VERSION + .byte 0x00,0x00,0x00,0x00 // APU Family ID + .byte 0x00,0x01,0x00,0x00 // Load Address + .byte 0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte FW_TYPE + .byte 0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S new file mode 100644 index 0000000000..f5f1e18e6c --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include +#include + + .global Main + .global _psp_vs_start + + .global PSP_VERSTAGE_STACK_END + +.arm +.text +.section "PSP_HEADER_DATA", "aw", %note + +//============================================================================== +// First 256 bytes of the binary image contain the header. +// Executable code starts from offset 0x100. +//============================================================================== +#include "bl_uapp_header.inc" + +//============================================================================== +// This is entry point to the binary which is called by main Boot Loader. +//============================================================================== + +ENTRY(_psp_vs_start) + + ldr sp, =PSP_VERSTAGE_STACK_END // stack pointer + + // Return value contains Virtual Address of mapped stack + // + ldr lr, =ShouldNotBeReached // return address + + ldr r2, =Main // pass control to verstage main function + blx r2 + +// This point should not be reached. The Main() function should return +// to main BL using Svc_Exit(). +// +ShouldNotBeReached: + mov r0, #BL_ERR_GENERIC // Returned from Main + svc #0x0 // SVC_EXIT + +ENDPROC(_psp_vs_start) +.end diff --git a/src/vendorcode/amd/fsp/sabrina/dmi_info.h b/src/vendorcode/amd/fsp/sabrina/dmi_info.h new file mode 100644 index 0000000000..d2c26fad4c --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/dmi_info.h @@ -0,0 +1,239 @@ + /***************************************************************************** + * + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * This code was copied from src/vendorcode/amd/pi/00670F00/AGESA.h + */ + +#define AMD_FSP_DMI_HOB_GUID {0x4118FC0E, 0x353D, 0x4726, { 0x97, 0xC0, 0x53, 0xCD, 0x92, 0xB6, 0x49, 0x25}} + +// Our ACPI HOB max payload, accounting for the size of the HOB header as well as the information structure +#define HOB_MAX_SIZE 0xFFF8 +#define HOB_GUID_EXTENSION_SIZE (HOB_MAX_SIZE - sizeof (EFI_HOB_GUID_TYPE)) + +#define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system +#define MAX_CHANNELS_PER_SOCKET 8 ///< Max Channels per sockets +#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) + +/// DMI Type 16 offset 04h - Location +typedef enum { + OtherLocation = 0x01, ///< Assign 01 to Other + UnknownLocation, ///< Assign 02 to Unknown + SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard + IsaAddonCard, ///< Assign 04 to ISA add-on card + EisaAddonCard, ///< Assign 05 to EISA add-on card + PciAddonCard, ///< Assign 06 to PCI add-on card + McaAddonCard, ///< Assign 07 to MCA add-on card + PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card + ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card + NuBus, ///< Assign 0A to NuBus + Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card +} DMI_T16_LOCATION; + +/// DMI Type 16 offset 05h - Memory Error Correction +typedef enum { + OtherUse = 0x01, ///< Assign 01 to Other + UnknownUse, ///< Assign 02 to Unknown + SystemMemory, ///< Assign 03 to system memory + VideoMemory, ///< Assign 04 to video memory + FlashMemory, ///< Assign 05 to flash memory + NonvolatileRam, ///< Assign 06 to non-volatile RAM + CacheMemory ///< Assign 07 to cache memory +} DMI_T16_USE; + +/// DMI Type 16 offset 07h - Maximum Capacity +typedef enum { + Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other + Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown + Dmi16NoneErrCorrection, ///< Assign 03 to None + Dmi16Parity, ///< Assign 04 to parity + Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC + Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC + Dmi16Crc ///< Assign 07 to CRC +} DMI_T16_ERROR_CORRECTION; + +/// DMI Type 16 - Physical Memory Array +typedef struct { + OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + OUT DMI_T16_USE Use; ///< Identifies the function for which the array + ///< is used. + OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available + ///< for memory devices in this array. +} TYPE16_DMI_INFO; + +/// DMI Type 17 offset 0Eh - Form Factor +typedef enum { + OtherFormFactor = 0x01, ///< Assign 01 to Other + UnknowFormFactor, ///< Assign 02 to Unknown + SimmFormFactor, ///< Assign 03 to SIMM + SipFormFactor, ///< Assign 04 to SIP + ChipFormFactor, ///< Assign 05 to Chip + DipFormFactor, ///< Assign 06 to DIP + ZipFormFactor, ///< Assign 07 to ZIP + ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card + DimmFormFactorFormFactor, ///< Assign 09 to DIMM + TsopFormFactor, ///< Assign 10 to TSOP + RowOfChipsFormFactor, ///< Assign 11 to Row of chips + RimmFormFactor, ///< Assign 12 to RIMM + SodimmFormFactor, ///< Assign 13 to SODIMM + SrimmFormFactor, ///< Assign 14 to SRIMM + FbDimmFormFactor ///< Assign 15 to FB-DIMM +} DMI_T17_FORM_FACTOR; + +/// DMI Type 17 offset 12h - Memory Type +typedef enum { + OtherMemType = 0x01, ///< Assign 01 to Other + UnknownMemType, ///< Assign 02 to Unknown + DramMemType, ///< Assign 03 to DRAM + EdramMemType, ///< Assign 04 to EDRAM + VramMemType, ///< Assign 05 to VRAM + SramMemType, ///< Assign 06 to SRAM + RamMemType, ///< Assign 07 to RAM + RomMemType, ///< Assign 08 to ROM + FlashMemType, ///< Assign 09 to Flash + EepromMemType, ///< Assign 10 to EEPROM + FepromMemType, ///< Assign 11 to FEPROM + EpromMemType, ///< Assign 12 to EPROM + CdramMemType, ///< Assign 13 to CDRAM + ThreeDramMemType, ///< Assign 14 to 3DRAM + SdramMemType, ///< Assign 15 to SDRAM + SgramMemType, ///< Assign 16 to SGRAM + RdramMemType, ///< Assign 17 to RDRAM + DdrMemType, ///< Assign 18 to DDR + Ddr2MemType, ///< Assign 19 to DDR2 + Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM + Ddr3MemType = 0x18, ///< Assign 24 to DDR3 + Fbd2MemType, ///< Assign 25 to FBD2 + Ddr4MemType, ///< Assign 26 to DDR4 + LpDdrMemType, ///< Assign 27 to LPDDR + LpDdr2MemType, ///< Assign 28 to LPDDR2 + LpDdr3MemType, ///< Assign 29 to LPDDR3 + LpDdr4MemType, ///< Assign 30 to LPDDR4 + LpDdr5MemType, ///< Assign 31 to LPDDR5 +} DMI_T17_MEMORY_TYPE; + +/// DMI Type 17 offset 13h - Type Detail +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 FastPaged:1; ///< Fast-Paged + OUT UINT16 StaticColumn:1; ///< Static column + OUT UINT16 PseudoStatic:1; ///< Pseudo-static + OUT UINT16 Rambus:1; ///< RAMBUS + OUT UINT16 Synchronous:1; ///< Synchronous + OUT UINT16 Cmos:1; ///< CMOS + OUT UINT16 Edo:1; ///< EDO + OUT UINT16 WindowDram:1; ///< Window DRAM + OUT UINT16 CacheDram:1; ///< Cache Dram + OUT UINT16 NonVolatile:1; ///< Non-volatile + OUT UINT16 Registered:1; ///< Registered (Buffered) + OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) + OUT UINT16 LRDIMM:1; ///< LRDIMM +} DMI_T17_TYPE_DETAIL; + +/// DMI Type 17 offset 28h - Memory Technology +typedef enum { + OtherType = 0x01, ///< Assign 01 to Other + UnknownType = 0x02, ///< Assign 02 to Unknown + DramType = 0x03, ///< Assign 03 to DRAM + NvDimmNType = 0x04, ///< Assign 04 to NVDIMM-N + NvDimmFType = 0x05, ///< Assign 05 to NVDIMM-F + NvDimmPType = 0x06, ///< Assign 06 to NVDIMM-P + IntelPersistentMemoryType = 0x07, ///< Assign 07 to Intel persistent memory +} DMI_T17_MEMORY_TECHNOLOGY; + +/// DMI Type 17 offset 29h - Memory Operating Mode Capability +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved, set to 0 + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 VolatileMemory:1; ///< Volatile memory + OUT UINT16 ByteAccessiblePersistentMemory:1; ///< Byte-accessible persistent memory + OUT UINT16 BlockAccessiblePersistentMemory:1; ///< Block-accessible persistent memory + OUT UINT16 Reserved2:10; ///< Reserved, set to 0 +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY; + +typedef union { + DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY AsBitmap; + UINT16 AsUint16; +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR; + +/// DMI Type 17 - Memory Device +typedef struct { + OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of + ///< Memory Devices that must be populated with all devices of + ///< the same type and size, and the set to which this device belongs. + OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT CHAR8 BankLocator[13]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. + OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT CHAR8 SerialNumber[9]; ///< Serial Number. + OUT CHAR8 PartNumber[21]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT32 ExtSize; ///< Extended Size. + OUT UINT16 ConfigSpeed; ///< Configured memory clock speed + OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts + OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts + OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts + // SMBIOS 3.2 + OUT UINT8 MemoryTechnology; ///< Memory technology type for this memory device + OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR MemoryOperatingModeCapability; ///< The operating modes supported by this memory device + OUT CHAR8 FirmwareVersion[10]; ///< String number for the firmware version of this memory device + OUT UINT16 ModuleManufacturerId; ///< The two-byte module manufacturer ID found in the SPD of this memory device; LSB first. + OUT UINT16 ModuleProductId; ///< The two-byte module product ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerManufacturerId; //< The two-byte memory subsystem controller manufacturer ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerProductId; //< The two-byte memory subsystem controller product ID found in the SPD of this memory device; LSB first + OUT UINT64 NonvolatileSize; ///< Size of the Non-volatile portion of the memory device in Bytes, if any. + OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any. + OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any. + OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes. + // SMBIOS 3.3 + OUT UINT32 ExtendedSpeed; ///< Extended Speed + OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed +} __packed TYPE17_DMI_INFO; + +/// Collection of pointers to the DMI records +typedef struct { + OUT TYPE16_DMI_INFO T16; ///< Type 16 struc + OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc +} DMI_INFO; diff --git a/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h b/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h new file mode 100644 index 0000000000..1a295f591a --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h @@ -0,0 +1,58 @@ +/** @file + * + * C99 common FSP definitions from + * Intel Firmware Support Package External Architecture Specification v2.0 + * + * These definitions come in a format that is usable outside an EFI environment. + **/ +#ifndef FSP_H_C99_H +#define FSP_H_C99_H + +#include + +enum { + FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, + FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, + FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, + FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, + FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, + FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, + FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, + FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, +}; + +typedef enum { + EnumInitPhaseAfterPciEnumeration = 0x20, + EnumInitPhaseReadyToBoot = 0x40, + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +typedef struct __packed { + uint64_t Signature; + uint8_t Revision; + uint8_t Reserved[23]; +} FSP_UPD_HEADER; + +_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + + +#if CONFIG(PLATFORM_USES_FSP2_X86_32) +typedef struct __packed { + uint8_t Revision; + uint8_t Reserved[3]; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t NvsBufferPtr; + /* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */ + uint32_t StackBase; + uint32_t StackSize; + uint32_t BootLoaderTolumSize; + uint32_t BootMode; + uint8_t Reserved1[8]; +} FSPM_ARCH_UPD; + +_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); +#else +#error You need to implement this struct for x86_64 FSP +#endif + +#endif /* FSP_H_C99_H */ diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h new file mode 100644 index 0000000000..4fa9a3371f --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h @@ -0,0 +1,37 @@ +/***************************************************************************** + * + * Copyright (c) 2020, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef BL_ERRORCODES_PUBLIC_H +#define BL_ERRORCODES_PUBLIC_H + +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code + +#endif /* BL_ERRORCODES_PUBLIC_H */ diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h new file mode 100644 index 0000000000..06e9defea7 --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h @@ -0,0 +1,319 @@ +/***************************************************************************** + * + * Copyright (c) 2020, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _BL_SYSCALL_PUBLIC_H_ +#define _BL_SYSCALL_PUBLIC_H_ + +#include + +#define SVC_EXIT 0x00 +#define SVC_ENTER 0x02 +#define SVC_DEBUG_PRINT 0x06 +#define SVC_MODEXP 0x0C +#define SVC_DEBUG_PRINT_EX 0x1A +#define SVC_GET_BOOT_MODE 0x1C +#define SVC_DELAY_IN_MICRO_SECONDS 0x2F +#define SVC_GET_SPI_INFO 0x60 +#define SVC_MAP_SPIROM_DEVICE 0x61 +#define SVC_UNMAP_SPIROM_DEVICE 0x62 +#define SVC_MAP_FCH_IO_DEVICE 0x63 +#define SVC_UNMAP_FCH_IO_DEVICE 0x64 +#define SVC_UPDATE_PSP_BIOS_DIR 0x65 +#define SVC_COPY_DATA_FROM_UAPP 0x66 +#define SVC_RESET_SYSTEM 0x67 +#define SVC_READ_TIMER_VAL 0x68 +#define SVC_SHA 0x69 +#define SVC_CCP_DMA 0x6A + +struct mod_exp_params { + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent size in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus size in bytes + char *pMessage; // Message address, same size as ModulusSize + char *pOutput; // Output address; Must be big enough to hold the + // data of ModulusSize +}; + +enum psp_boot_mode { + PSP_BOOT_MODE_S0 = 0x0, + PSP_BOOT_MODE_S0i3_RESUME = 0x1, + PSP_BOOT_MODE_S3_RESUME = 0x2, + PSP_BOOT_MODE_S4 = 0x3, + PSP_BOOT_MODE_S5_COLD = 0x4, + PSP_BOOT_MODE_S5_WARM = 0x5, +}; + +enum reset_type +{ + RESET_TYPE_COLD = 0, + RESET_TYPE_WARM = 1, + RESET_TYPE_MAX = 2, +}; + +enum fch_io_device { + FCH_IO_DEVICE_SPI, + FCH_IO_DEVICE_I2C, + FCH_IO_DEVICE_GPIO, + FCH_IO_DEVICE_ESPI, + FCH_IO_DEVICE_IOMUX, + FCH_IO_DEVICE_MISC, + FCH_IO_DEVICE_AOAC, + FCH_IO_DEVICE_IOPORT, + + FCH_IO_DEVICE_END, +}; + +enum fch_i2c_controller_id { + FCH_I2C_CONTROLLER_ID_0 = 0, + FCH_I2C_CONTROLLER_ID_1 = 1, + FCH_I2C_CONTROLLER_ID_2 = 2, + FCH_I2C_CONTROLLER_ID_3 = 3, + FCH_I2C_CONTROLLER_ID_MAX, +}; + +struct spirom_info { + void *SpiBiosSysHubBase; + void *SpiBiosSmnBase; + uint32_t SpiBiosSize; +}; + +enum psp_timer_type { + PSP_TIMER_TYPE_CHRONO = 0, + PSP_TIMER_TYPE_SECURE_RTC = 1, + PSP_TIMER_TYPE_MAX = 2, +}; + +/* SHA types same as ccp SHA type in crypto.h */ +enum sha_type { + SHA_TYPE_256, + SHA_TYPE_384 +}; + +/* All SHA operation supported */ +enum sha_operation_mode { + SHA_GENERIC +}; + +/* SHA Supported Data Structures */ +struct sha_generic_data { + enum sha_type SHAType; + uint8_t *Data; + uint32_t DataLen; + uint32_t DataMemType; + uint8_t *Digest; + uint32_t DigestLen; + uint8_t *IntermediateDigest; + uint32_t IntermediateMsgLen; + uint32_t Init; + uint32_t Eom; +}; + +/* + * Exit to the main Boot Loader. This does not return back to user application. + * + * Parameters: + * status - either Ok or error code defined by AGESA + */ +void svc_exit(uint32_t status); + +/* Print debug message into serial console. + * + * Parameters: + * string - null-terminated string + */ +void svc_debug_print(const char *string); + +/* Print 4 DWORD values in hex to serial console + * + * Parameters: + * dword0...dword3 - 32-bit DWORD to print + */ +void svc_debug_print_ex(uint32_t dword0, + uint32_t dword1, uint32_t dword2, uint32_t dword3); + +/* Description - Returns the current boot mode from the enum psp_boot_mode found in + * bl_public.h. + * + * Inputs - boot_mode - Output parameter passed in R0 + * + * Outputs - The boot mode in boot_mode. + * See Return Values. + * + * Return Values - BL_OK + * BL_ERR_NULL_PTR + * Other BL_ERRORs lofted up from called functions + */ +uint32_t svc_get_boot_mode(uint32_t *boot_mode); + +/* Add delay in micro seconds + * + * Parameters: + * delay - required delay value in microseconds + * + * Return value: NONE + */ +void svc_delay_in_usec(uint32_t delay); + +/* Get the SPI-ROM information + * + * Parameters: + * spi_rom_iInfo - SPI-ROM information + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info); + +/* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...) + * + * Parameters: + * io_device - ID for respective FCH IO controller register space to be mapped + * arg1 - Based on IODevice ID, interpretation of this argument changes. + * arg2 - Based on IODevice ID, interpretation of this argument changes. + * io_device_axi_addr - AXI address for respective FCH IO device register space + * + * Return value: BL_OK or error code + */ +uint32_t svc_map_fch_dev(enum fch_io_device io_device, + uint32_t arg1, uint32_t arg2, void **io_device_axi_addr); + +/* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice() + * + * Parameters: + * io_device - ID for respective FCH IO controller register space to be unmapped + * io_device_addr - AXI address for respective FCH IO device register space + * + * Return value: BL_OK or error code + */ +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, + void *io_device_axi_addr); + +/* Map the SPIROM FLASH device address space + * + * Parameters: + * SpiRomAddr - Address in SPIROM tobe mapped (SMN based) + * size - Size to be mapped + * pSpiRomAddrAxi - Mapped address in AXI space + * + * Return value: BL_OK or error code + */ +uint32_t svc_map_spi_rom(void *spi_rom_addr, + uint32_t size, void **spi_rom_axi_addr); + +/* Unmap the SPIROM FLASH device address space mapped earlier using Svc_MapSpiRomDevice() + * + * Parameters: + * pSpiRomAddrAxi - Address in AXI address space previously mapped + * + * Return value: BL_OK or error code + */ +uint32_t svc_unmap_spi_rom(void *spi_rom_addr); + +/* Updates the offset at which PSP or BIOS Directory can be found in the + * SPI flash + * + * Parameters: + * psp_dir_offset - [in/out] Offset at which PSP Directory can be + * found in the SPI Flash. Same pointer is used + * to return the offset in case of GET operation + * bios_dir_offset - [in/out] Offset at which BIOS Directory can be + * found in the SPI Flash. Same pointer is used + * to return the offset in case of GET operation + * + * Return value: BL_OK or error code + */ +uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, + uint32_t *bios_dir_offset); + +/* Copies the data that is shared by verstage to the PSP BL owned memory + * + * Parameters: + * address - Address in UAPP controlled/owned memory + * size - Total size of memory to copy (max 16Kbytes) + */ +uint32_t svc_save_uapp_data(void *address, uint32_t size); + +/* + * Read timer raw (currently CHRONO and RTC) value + * + * Parameters: + * type - [in] Type of timer UAPP would like to read from + * (currently CHRONO and RTC) + * counter_value - [out] return the raw counter value read from + * RTC or CHRONO_LO/HI counter register + -----------------------------------------------------------------------------*/ +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value); + +/* + * Reset the system + * + * Parameters: + * reset_type - Cold or Warm reset + */ +uint32_t svc_reset_system(enum reset_type reset_type); + +/* + * Write postcode to Port-80 + * + * Parameters: + * postcode - Postcode value to be written on port-80h + */ +uint32_t svc_write_postcode(uint32_t postcode); + +/* + * Generic SHA call for SHA, SHA_OTP, SHA_HMAC + */ +uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode); + +/* + * Calculate ModEx + * + * Parameters: + * mod_exp_param - ModExp parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_modexp(struct mod_exp_params *mod_exp_param); + +/* + * Copies the data from source to destination using ccp + * + * Parameters: + * Source Address - SPI ROM offset + * Destination Address - Address in Verstage memory + * Size - Total size to copy + * + * Return value: BL_OK or error code + */ +uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); + +/* C entry point for the Bootloader Userspace Application */ +void Main(void); + +#endif /* _BL_SYSCALL__PUBLIC_H_ */ diff --git a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h new file mode 100644 index 0000000000..ada9bbd209 --- /dev/null +++ b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H +#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H + +#define NUM_DXIO_PHY_PARAMS 6 +#define NUM_DXIO_PORT_PARAMS 6 + +/* Engine descriptor type */ +enum dxio_engine_type { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +}; + +/* PCIe link capability/speed */ +enum dxio_link_speed_cap { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +}; + +/* Upstream Auto Speed Change Allowed */ +enum dxio_upstream_auto_speed_change { + SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 + SPDC_DISABLED, + SPDC_ENABLED, + SPDC_INVALID +}; + +/* SATA ChannelType initialization */ +enum dxio_sata_channel_type { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +}; + +/* CLKREQ for PCIe type descriptors */ +enum cpm_clk_req { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4_GFX, + CLK_REQ5, + CLK_REQ6, + CLK_ENABLE = 0xff, +}; + +/* PCIe link ASPM initialization */ +enum dxio_aspm_type { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +}; + +enum dxio_port_param_type { + PP_DEVICE = 1, + PP_FUNCTION, + PP_PORT_PRESENT, + PP_LINK_SPEED_CAP, + PP_LINK_ASPM, + PP_HOTPLUG_TYPE, + PP_CLKREQ, + PP_ASPM_L1_1, + PP_ASPM_L1_2, + PP_COMPLIANCE, + PP_SAFE_MODE, + PP_CHIPSET_LINK, + PP_CLOCK_PM, + PP_CHANNELTYPE, + PP_TURN_OFF_UNUSED_LANES, + PP_APIC_GROUPMAP, + PP_APIC_SWIZZLE, + PP_APIC_BRIDGEINT, + PP_MASTER_PLL, + PP_SLOT_NUM, + PP_PHY_PARAM, + PP_ESM, + PP_CCIX, + PP_GEN3_DS_TX_PRESET, + PP_GEN3_DS_RX_PRESET_HINT, + PP_GEN3_US_TX_PRESET, + PP_GEN3_US_RX_PRESET_HINT, + PP_GEN4_DS_TX_PRESET, + PP_GEN4_US_TX_PRESET, + PP_GEN3_FIXED_PRESET, + PP_GEN4_FIXED_PRESET, + PP_PSPP_DC, + PP_PSPP_AC, + PP_GEN2_DEEMPHASIS, + PP_INVERT_POLARITY, + PP_TARGET_LINK_SPEED, + PP_GEN4_DLF_CAP_DISABLE, + PP_GEN4_DLF_EXCHG_DISABLE +}; + +/* DDI Aux channel */ +enum ddi_aux_type { + DDI_AUX1 = 0, + DDI_AUX2, + DDI_AUX3, + DDI_AUX4, + DDI_AUX5, + DDI_AUX6, + DDI_AUX_MAX // Not valid value, used to verify input +}; + +/* DDI Hdp Index */ +enum ddi_hdp_type { + DDI_HDP1 = 0, + DDI_HDP2, + DDI_HDP3, + DDI_HDP4, + DDI_HDP5, + DDI_HDP6, + DDI_HDP_MAX // Not valid value, used to verify input +}; + +/* DDI display connector type */ +enum ddi_connector_type { + DDI_DP = 0, // DP + DDI_EDP, // eDP + DDI_SINGLE_LINK_DVI, // Single Link DVI-D + DDI_DUAL_LINK_DVI, // Dual Link DVI-D + DDI_HDMI, // HDMI + DDI_DP_TO_VGA, // DP-to-VGA + DDI_DP_TO_LVDS, // DP-to-LVDS + DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I + DDI_CRT, // CRT (VGA) + DDI_LVDS, // LVDS + DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + DDI_AUTO_DETECT, // VBIOS auto detect connector type + DDI_UNUSED_TYPE, // UnusedType + DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input +}; + +/* Cezanne DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; // see ddi_connector_type + uint8_t aux_index; // see ddi_aux_type + uint8_t hdp_index; // see ddi_hdp_type + uint8_t reserved; +} fsp_ddi_descriptor; + +/* + * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, + * configure bifurcation and other settings. Beware that the lane numbers in + * here are the logical and not the physical lane numbers! + * + * Cezanne DXIO logical lane to physical PCIe lane mapping: + * + * logical | FT6 | AM4 + * --------|------------|---------------------- + * [00:03] | GPP[00:03] | GPP[00:03] + * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] + * [08:11] | GPP[08:11] | GFX[15:12] + * [12:15] | n/a | GFX[11:08] + * [16:23] | GFX[00:07] | GFX[07:0] + * + * Different ports mustn't overlap or be assigned to the same lane(s). Within + * ports with the same width the one with a higher start logical lane number + * needs to be assigned to a higher PCIe root port number; ports of the same + * size don't have to be assigned to consecutive PCIe root ports though. + * + * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 + * platform additionally supports mapping lanes 8 and 9 to a SATA controller. + * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet + * controllers. + */ +typedef struct __packed { + uint8_t engine_type; // See dxio_engine_type + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device + uint8_t gpio_group_id; // GPIO number used as reset + uint32_t port_present :1; // Should be TRUE if train link + uint32_t reserved_3 :7; + uint32_t device_number :5; // Desired root port device number + uint32_t function_number :3; // Desired root port function number + uint32_t link_speed_capability :2; // See dxio_link_speed_cap + uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint32_t eq_preset :4; // Gen3 equalization preset + uint32_t link_aspm :2; // See dxio_aspm_type + uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 + uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 + uint32_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint32_t slot_power_limit_scale :2; // Currently unused by FSP + uint32_t reserved_4 :6; + uint32_t link_compliance_mode :1; // Currently unused by FSP + uint32_t link_safe_mode :1; // Currently unused by FSP + uint32_t sb_link :1; // Currently unused by FSP + uint32_t clk_pm_support :1; // Currently unused by FSP + uint32_t channel_type :3; // See dxio_sata_channel_type + uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present + uint8_t reserved[4]; + uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2]; + uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type +} fsp_dxio_descriptor; + +#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */ diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 9158760322..aef81943a8 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -10,6 +10,11 @@ postcar-y += vboot_check.c romstage-y += vboot_check.c ramstage-y += vboot_check.c +$(call src-to-obj,bootblock,$(dir)/vboot_check.c) : $(obj)/fmap_config.h +$(call src-to-obj,postcar,$(dir)/vboot_check.c) : $(obj)/fmap_config.h +$(call src-to-obj,romstage,$(dir)/vboot_check.c) : $(obj)/fmap_config.h +$(call src-to-obj,ramstage,$(dir)/vboot_check.c) : $(obj)/fmap_config.h + ifeq ($(CONFIG_VENDORCODE_ELTAN_VBOOT),y) cbfs-files-y += oemmanifest.bin oemmanifest.bin-file := $(obj)/oemmanifest.bin diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index ed20af5076..09da5c50ad 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -36,13 +36,13 @@ int verified_boot_check_manifest(void) buffer = cbfs_map(RSA_PUBLICKEY_FILE_NAME, &size); if (!buffer || !size) { - printk(BIOS_ERR, "ERROR: Public key not found!\n"); + printk(BIOS_ERR, "Public key not found!\n"); goto fail; } if ((size != CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) || (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { - printk(BIOS_ERR, "ERROR: Illegal public key!\n"); + printk(BIOS_ERR, "Illegal public key!\n"); goto fail; } @@ -53,7 +53,7 @@ int verified_boot_check_manifest(void) if ((sd->workbuf_used + size + sizeof(struct vb2_kernel_preamble) + ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) > sizeof(wb_buffer)) { - printk(BIOS_ERR, "ERROR: Work buffer too small\n"); + printk(BIOS_ERR, "Work buffer too small\n"); goto fail; } @@ -74,7 +74,7 @@ int verified_boot_check_manifest(void) /* Fill body_signature (vb2_structure). RSA2048 key is used */ cbfs_map("oemmanifest.bin", &size); if (size != ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) { - printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); + printk(BIOS_ERR, "Incorrect manifest size!\n"); goto fail; } pre->body_signature.data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c index 500e632858..5a54d70527 100644 --- a/src/vendorcode/google/chromeos/acpi.c +++ b/src/vendorcode/google/chromeos/acpi.c @@ -33,8 +33,3 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) acpigen_pop_len(); } - -void chromeos_dsdt_generator(const struct device *dev) -{ - mainboard_chromeos_acpi_generate(); -} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 456f2d7cb3..b9f807fada 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -97,4 +97,6 @@ Device (CRHW) } } +#include + #include "ramoops.asl" diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 89e7055f89..7be45862b8 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This is the ChromeOS specific ACPI information needed by - * the mainboard's chromeos.asl + * chromeos.asl */ +External (CNVS, OpRegionObj) + Field (CNVS, ByteAcc, NoLock, Preserve) { VBT0, 32, // 0x000 - Boot Reason diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 04805f2b21..abdd6c2a77 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -5,11 +5,6 @@ #include #include -#include -#include -#include -#include -#include #include #if CONFIG(CHROMEOS) @@ -31,6 +26,7 @@ void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); void chromeos_set_ecfw_rw(void); +void chromeos_init_chromeos_acpi(void); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD @@ -50,16 +46,9 @@ struct cros_gpio; void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); /* - * Common helper function and delcarations for mainboards to use to generate - * ACPI-specific Chrome OS needs. + * Declaration for mainboards to use to generate ACPI-specific Chrome OS needs. */ void mainboard_chromeos_acpi_generate(void); -#if CONFIG(CHROMEOS) -struct device; -void chromeos_dsdt_generator(const struct device *dev); -#else -#define chromeos_dsdt_generator NULL -#endif enum { CROS_GPIO_REC = 1, /* Recovery */ diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index a8243e17e0..0a24d0f71a 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -43,8 +44,7 @@ static int cr50_is_reset_needed(void) return 1; } else if (ret != TPM_SUCCESS) { /* TPM command failed, continue booting. */ - printk(BIOS_ERR, - "ERROR: Attempt to get CR50 TPM mode failed: %x\n", ret); + printk(BIOS_ERR, "Attempt to get CR50 TPM mode failed: %x\n", ret); return 0; } @@ -84,8 +84,7 @@ static void enable_update(void *unused) ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { - printk(BIOS_ERR, - "ERROR: tlcl_lib_init() failed for CR50 update: %x\n", + printk(BIOS_ERR, "tlcl_lib_init() failed for CR50 update: %x\n", ret); return; } @@ -97,8 +96,7 @@ static void enable_update(void *unused) &num_restored_headers); if (ret != TPM_SUCCESS) { - printk(BIOS_ERR, - "ERROR: Attempt to enable CR50 update failed: %x\n", + printk(BIOS_ERR, "Attempt to enable CR50 update failed: %x\n", ret); return; } @@ -151,8 +149,7 @@ static void enable_update(void *unused) * booting but the current boot will likely end up at * the recovery screen. */ - printk(BIOS_ERR, - "ERROR: Attempt to reset CR50 failed: %x\n", + printk(BIOS_ERR, "Attempt to reset CR50 failed: %x\n", ret); return; } diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c index dff75204a5..b7f7c8d8fc 100644 --- a/src/vendorcode/google/chromeos/elog.c +++ b/src/vendorcode/google/chromeos/elog.c @@ -4,6 +4,7 @@ #include #include #include +#include #include static void elog_add_boot_reason(void *unused) @@ -20,10 +21,16 @@ static void elog_add_boot_reason(void *unused) /* Skip logging developer mode in ACPI resume path */ if (dev && !acpi_is_wakeup_s3()) { - elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE); printk(BIOS_DEBUG, "%s: Logged dev mode boot\n", __func__); } + + /* Diagnostic boot if requested */ + if (vboot_get_context()->boot_mode == VB2_BOOT_MODE_DIAGNOSTICS) { + elog_add_event_byte(ELOG_TYPE_CROS_DIAGNOSTICS, + ELOG_CROS_LAUNCH_DIAGNOSTICS); + printk(BIOS_DEBUG, "%s: Logged diagnostic boot\n", __func__); + } } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_add_boot_reason, NULL); diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 531463b273..7236662df7 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -98,7 +98,14 @@ void acpi_fill_cnvs(void) { const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi, sizeof(*chromeos_acpi)); + + if (!chromeos_acpi) + return; + acpigen_write_scope("\\"); acpigen_write_opregion(&cnvs_op); acpigen_pop_len(); + + /* Usually this creates OIPG package for GPIOs. */ + mainboard_chromeos_acpi_generate(); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index a25b2b0e24..a9f93d99cd 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -32,6 +32,4 @@ struct chromeos_acpi { u8 pad[298]; // dd6-eff } __packed; -void chromeos_init_chromeos_acpi(void); - #endif diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 895958860b..130f5fad6a 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -25,7 +25,7 @@ static uint8_t *wifi_hextostr(const char *sar_str, size_t str_len, size_t *sar_b if (!legacy_hex_format) { sar_bin = malloc(str_len); if (!sar_bin) { - printk(BIOS_ERR, "ERROR: Failed to allocate space for SAR binary!\n"); + printk(BIOS_ERR, "Failed to allocate space for SAR binary!\n"); return NULL; } @@ -35,12 +35,12 @@ static uint8_t *wifi_hextostr(const char *sar_str, size_t str_len, size_t *sar_b bin_len = ((str_len - 1) / 2); sar_bin = malloc(bin_len); if (!sar_bin) { - printk(BIOS_ERR, "ERROR: Failed to allocate space for SAR binary!\n"); + printk(BIOS_ERR, "Failed to allocate space for SAR binary!\n"); return NULL; } if (hexstrtobin(sar_str, (uint8_t *)sar_bin, bin_len) != bin_len) { - printk(BIOS_ERR, "ERROR: sar_limits contains non-hex value!\n"); + printk(BIOS_ERR, "sar_limits contains non-hex value!\n"); free(sar_bin); return NULL; } @@ -116,20 +116,20 @@ static int fill_wifi_sar_limits(union wifi_sar_limits *sar_limits, const uint8_t size_t header_size = sar_header_size(); if (sar_bin_size < header_size) { - printk(BIOS_ERR, "ERROR: Invalid SAR format!\n"); + printk(BIOS_ERR, "Invalid SAR format!\n"); return -1; } header = (struct sar_header *)sar_bin; if (header->version != SAR_FILE_REVISION) { - printk(BIOS_ERR, "ERROR: Invalid SAR file version: %d!\n", header->version); + printk(BIOS_ERR, "Invalid SAR file version: %d!\n", header->version); return -1; } for (i = 0; i < MAX_PROFILE_COUNT; i++) { if (header->offsets[i] > sar_bin_size) { - printk(BIOS_ERR, "ERROR: Offset is outside the file size!\n"); + printk(BIOS_ERR, "Offset is outside the file size!\n"); return -1; } @@ -145,7 +145,7 @@ static int fill_wifi_sar_limits(union wifi_sar_limits *sar_limits, const uint8_t expected_sar_bin_size += dsm_table_size(sar_limits->dsm); if (sar_bin_size != expected_sar_bin_size) { - printk(BIOS_ERR, "ERROR: Invalid SAR size, expected: %ld, obtained: %ld\n", + printk(BIOS_ERR, "Invalid SAR size, expected: %ld, obtained: %ld\n", expected_sar_bin_size, sar_bin_size); return -1; } @@ -164,7 +164,7 @@ static int fill_wifi_sar_limits_legacy(union wifi_sar_limits *sar_limits, new_sar_bin = malloc(size); if (!new_sar_bin) { - printk(BIOS_ERR, "ERROR: Failed to allocate space for SAR binary!\n"); + printk(BIOS_ERR, "Failed to allocate space for SAR binary!\n"); return -1; } @@ -259,13 +259,13 @@ int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) filename = get_wifi_sar_cbfs_filename(); if (filename == NULL) { - printk(BIOS_ERR, "ERROR: Filename missing for CBFS SAR file!\n"); + printk(BIOS_ERR, "Filename missing for CBFS SAR file!\n"); return ret; } sar_str = cbfs_map(filename, &sar_str_len); if (!sar_str) { - printk(BIOS_ERR, "ERROR: Failed to get the %s file size!\n", filename); + printk(BIOS_ERR, "Failed to get the %s file size!\n", filename); return ret; } @@ -274,13 +274,13 @@ int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) } else if (valid_legacy_length(sar_str_len)) { legacy_hex_format = true; } else { - printk(BIOS_ERR, "ERROR: Invalid SAR format!\n"); + printk(BIOS_ERR, "Invalid SAR format!\n"); goto error; } sar_bin = wifi_hextostr(sar_str, sar_str_len, &sar_bin_len, legacy_hex_format); if (sar_bin == NULL) { - printk(BIOS_ERR, "ERROR: Failed to parse SAR file %s\n", filename); + printk(BIOS_ERR, "Failed to parse SAR file %s\n", filename); goto error; } diff --git a/src/vendorcode/google/chromeos/vpd_calibration.c b/src/vendorcode/google/chromeos/vpd_calibration.c index ab862c808d..460d7dca3a 100644 --- a/src/vendorcode/google/chromeos/vpd_calibration.c +++ b/src/vendorcode/google/chromeos/vpd_calibration.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 6b7e49530b..b57a296e7b 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -1,18 +1,29 @@ ## SPDX-License-Identifier: GPL-2.0-only +config UDK_BASE + def_bool n + config UEFI_2_4_BINDING def_bool n + select UDK_BASE config UDK_2015_BINDING def_bool n + select UDK_BASE config UDK_2017_BINDING def_bool n + select UDK_BASE config UDK_202005_BINDING def_bool n + select UDK_BASE -if (UEFI_2_4_BINDING || UDK_2015_BINDING || UDK_2017_BINDING || UDK_202005_BINDING) +config UDK_202111_BINDING + def_bool n + select UDK_BASE + +if UDK_BASE config UDK_2013_VERSION int default 2013 @@ -29,12 +40,17 @@ config UDK_202005_VERSION int default 202005 +config UDK_202111_VERSION + int + default 202111 + config UDK_VERSION int + default UDK_202111_VERSION if UDK_202111_BINDING default UDK_202005_VERSION if UDK_202005_BINDING default UDK_2017_VERSION if UDK_2017_BINDING default UDK_2015_VERSION if UDK_2015_BINDING default UDK_2013_VERSION help UEFI Development Kit version for Platform -endif # {UEFI,UDK}_BINDING +endif # UDK_BASE diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index b49dc64240..e307400a56 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -24,4 +24,9 @@ CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Inclu CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include +else ifeq ($(CONFIG_UDK_202111_BINDING),y) +CPPFLAGS_x86_32 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32 +CPPFLAGS_x86_64 += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas.h new file mode 100644 index 0000000000..d92682906d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas.h @@ -0,0 +1,18 @@ +/** @file + Intel FSP definition from Intel Firmware Support Package External + Architecture Specification v2.0. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_EAS_H_ +#define _FSP_EAS_H_ + +#include +#include +#include +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h new file mode 100644 index 0000000000..eb9ce86124 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -0,0 +1,485 @@ +/** @file + Intel FSP API definition from Intel Firmware Support Package External + Architecture Specification v2.0 - v2.2 + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +#include + +/// +/// FSP Reset Status code +/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code +/// @{ +#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001 +#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002 +#define FSP_STATUS_RESET_REQUIRED_3 0x40000003 +#define FSP_STATUS_RESET_REQUIRED_4 0x40000004 +#define FSP_STATUS_RESET_REQUIRED_5 0x40000005 +#define FSP_STATUS_RESET_REQUIRED_6 0x40000006 +#define FSP_STATUS_RESET_REQUIRED_7 0x40000007 +#define FSP_STATUS_RESET_REQUIRED_8 0x40000008 +/// @} + +/// +/// FSP Event related definition. +/// +#define FSP_EVENT_CODE 0xF5000000 +#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000) + +/* + FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues. + These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the + status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3. + + @param[in] Type Indicates the type of event being reported. + See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE. + @param[in] Value Describes the current status of a hardware or software entity. + This includes information about the class and subclass that is used to classify the entity as well as an operation. + For progress events, the operation is the current activity. For error events, it is the exception. + For debug events, it is not defined at this time. + See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE. + @param[in] Instance The enumeration of a hardware or software entity within the system. + A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them. + An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant. + Valid instance numbers start with 1. + @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event. + This parameter may be NULL. + @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data. + For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages. + This parameter is NULL when no additional data is provided. + + @retval EFI_SUCCESS The event was handled successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_DEVICE_ERROR The event handler failed. +*/ +typedef +EFI_STATUS +(EFIAPI *FSP_EVENT_HANDLER) ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN OPTIONAL EFI_GUID *CallerId, + IN OPTIONAL EFI_STATUS_CODE_DATA *Data + ); + +/* + Handler for FSP-T debug log messages, provided by the bootloader. + + @param[in] DebugMessage A pointer to the debug message to be written to the log. + @param[in] MessageLength Number of bytes to written to the debug log. + + @retval UINT32 The return value indicates the number of bytes actually written to + the debug log. If the return value is less than MessageLength, + an error occurred. +*/ +typedef +UINT32 +(EFIAPI *FSP_DEBUG_HANDLER) ( + IN CHAR8* DebugMessage, + IN UINT32 MessageLength + ); + +#pragma pack(1) +/// +/// FSP_UPD_HEADER Configuration. +/// +typedef struct { + /// + /// UPD Region Signature. This signature will be + /// "XXXXXX_T" for FSP-T + /// "XXXXXX_M" for FSP-M + /// "XXXXXX_S" for FSP-S + /// Where XXXXXX is an unique signature + /// + UINT64 Signature; + /// + /// Revision of the Data structure. + /// For FSP spec 2.0/2.1 value is 1. + /// For FSP spec 2.2 value is 2. + /// + UINT8 Revision; + UINT8 Reserved[23]; +} FSP_UPD_HEADER; + +/// +/// FSPT_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages + /// occurring during FSP execution. + /// + FSP_DEBUG_HANDLER FspDebugHandler; + UINT8 Reserved1[20]; +} FSPT_ARCH_UPD; + +/// +/// FSPM_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + VOID *NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + VOID *StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + UINT32 StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + /// + /// Current boot mode. + /// + UINT32 BootMode; + /// + /// Optional event handler for the bootloader to be informed of events occurring during FSP execution. + /// This value is only valid if Revision is >= 2. + /// + FSP_EVENT_HANDLER *FspEventHandler; + UINT8 Reserved1[4]; +} FSPM_ARCH_UPD; + +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspEventHandler Optional event handler for the bootloader to be informed of events + /// occurring during FSP execution. + /// + FSP_EVENT_HANDLER FspEventHandler; + /// + /// A FSP binary may optionally implement multi-phase silicon initialization, + /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER + /// is non-zero. + /// To enable multi-phase silicon initialization, the bootloader must set + /// EnableMultiPhaseSiliconInit to a non-zero value. + /// + UINT8 EnableMultiPhaseSiliconInit; + UINT8 Reserved1[19]; +} FSPS_ARCH_UPD; + +/// +/// FSPT_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; +} FSPT_UPD_COMMON; + +/// +/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPT_ARCH_UPD Configuration. + /// + FSPT_ARCH_UPD FsptArchUpd; +} FSPT_UPD_COMMON_FSP22; + +/// +/// FSPM_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + /// + /// FSPM_ARCH_UPD Configuration. + /// + FSPM_ARCH_UPD FspmArchUpd; +} FSPM_UPD_COMMON; + +/// +/// FSPS_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; +} FSPS_UPD_COMMON; + +/// +/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPS_ARCH_UPD Configuration. + /// + FSPS_ARCH_UPD FspsArchUpd; +} FSPS_UPD_COMMON_FSP22; + +/// +/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. +/// +typedef enum { + /// + /// This stage is notified when the bootloader completes the + /// PCI enumeration and the resource allocation for the + /// PCI devices is complete. + /// + EnumInitPhaseAfterPciEnumeration = 0x20, + /// + /// This stage is notified just before the bootloader hand-off + /// to the OS loader. + /// + EnumInitPhaseReadyToBoot = 0x40, + /// + /// This stage is notified just before the firmware/Preboot + /// environment transfers management of all system resources + /// to the OS or next level execution environment. + /// + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +/// +/// Definition of NOTIFY_PHASE_PARAMS. +/// +typedef struct { + /// + /// Notification phase used for NotifyPhase API + /// + FSP_INIT_PHASE Phase; +} NOTIFY_PHASE_PARAMS; + +/// +/// Action definition for FspMultiPhaseSiInit API +/// +typedef enum { + EnumMultiPhaseGetNumberOfPhases = 0x0, + EnumMultiPhaseExecutePhase = 0x1 +} FSP_MULTI_PHASE_ACTION; + +/// +/// Data structure returned by FSP when bootloader calling +/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) +/// +typedef struct { + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; + +/// +/// FspMultiPhaseSiInit function parameter. +/// +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): +/// - PhaseIndex must be 0. +/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS. +/// +/// For action 1 (EnumMultiPhaseExecutePhase): +/// - PhaseIndex will be the phase that will be executed by FSP. +/// - MultiPhaseParamPtr shall be NULL. +/// +typedef struct { + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; + IN UINT32 PhaseIndex; + IN OUT VOID *MultiPhaseParamPtr; +} FSP_MULTI_PHASE_PARAMS; + +#pragma pack() + +/** + This FSP API is called soon after coming out of reset and before memory and stack is + available. This FSP API will load the microcode update, enable code caching for the + region specified by the boot loader and also setup a temporary stack to be used until + main memory is initialized. + + A hardcoded stack can be set up with the following values, and the "esp" register + initialized to point to this hardcoded stack. + 1. The return address where the FSP will return control after setting up a temporary + stack. + 2. A pointer to the input parameter structure + + However, since the stack is in ROM and not writeable, this FSP API cannot be called + using the "call" instruction, but needs to be jumped to. + + @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure. + + @retval EFI_SUCCESS Temporary RAM was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR Temp RAM initialization failed. + + If this function is successful, the FSP initializes the ECX and EDX registers to point to + a temporary but writeable memory range available to the boot loader and returns with + FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary + memory range and EDX points to the end of the range. Boot loader is free to use the + whole range described. Typically the boot loader can reload the ESP register to point + to the end of this returned range so that it can be used as a standard stack. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_INIT) ( + IN VOID *FsptUpdDataPtr + ); + +/** + This FSP API is used to notify the FSP about the different phases in the boot process. + This allows the FSP to take appropriate actions as needed during different initialization + phases. The phases will be platform dependent and will be documented with the FSP + release. The current FSP supports two notify phases: + Post PCI enumeration + Ready To Boot + + @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS + + @retval EFI_SUCCESS The notification was handled successfully. + @retval EFI_UNSUPPORTED The notification was not called in the proper order. + @retval EFI_INVALID_PARAMETER The notification code is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_NOTIFY_PHASE) ( + IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr + ); + +/** + This FSP API is called after TempRamInit and initializes the memory. + This FSP API accepts a pointer to a data structure that will be platform dependent + and defined for each FSP binary. This will be documented in Integration guide with + each FSP release. + After FspMemInit completes its execution, it passes the pointer to the HobList and + returns to the boot loader from where it was called. BootLoader is responsible to + migrate its stack and data to Memory. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure. + @param[out] HobListPtr Pointer to receive the address of the HOB list. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met. + @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MEMORY_INIT) ( + IN VOID *FspmUpdDataPtr, + OUT VOID **HobListPtr + ); + + +/** + This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary + memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure + that will be platform dependent and defined for each FSP binary. This will be + documented in Integration Guide. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + + @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure. + This structure is normally defined in the Integration Guide. + And if it is not defined in the Integration Guide, pass NULL. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_EXIT) ( + IN VOID *TempRamExitParamPtr + ); + + +/** + This FSP API is called after TempRamExit API. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the + silicon initialization. + + @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure. + If NULL, FSP will use the default parameters. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_SILICON_INIT) ( + IN VOID *FspsUpdDataPtr + ); + +/** + This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase. + This FSP API provides multi-phase silicon initialization; which brings greater modularity + beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an + extra API to FSP-S. This allows the bootloader to add board specific initialization steps + throughout the SiliconInit flow as needed. + + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases: + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain + how many phases supported by FSP. + For action - EnumMultiPhaseExecutePhase: + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL. + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr +); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspGlobalData.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspGlobalData.h new file mode 100644 index 0000000000..2ff4c0ea58 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspGlobalData.h @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_GLOBAL_DATA_H_ +#define _FSP_GLOBAL_DATA_H_ + +#include + +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 + +#pragma pack(1) + +typedef enum { + TempRamInitApiIndex, + FspInitApiIndex, + NotifyPhaseApiIndex, + FspMemoryInitApiIndex, + TempRamExitApiIndex, + FspSiliconInitApiIndex, + FspMultiPhaseSiInitApiIndex, + FspApiIndexMax +} FSP_API_INDEX; + +typedef struct { + VOID *DataPtr; + UINT32 MicrocodeRegionBase; + UINT32 MicrocodeRegionSize; + UINT32 CodeRegionBase; + UINT32 CodeRegionSize; +} FSP_PLAT_DATA; + +#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') +#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F') +#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF + +typedef struct { + UINT32 Signature; + UINT8 Version; + UINT8 Reserved1[3]; + UINT32 CoreStack; + UINT32 StatusCode; + UINT32 Reserved2[8]; + FSP_PLAT_DATA PlatformData; + FSP_INFO_HEADER *FspInfoHeader; + VOID *UpdDataPtr; + VOID *TempRamInitUpdPtr; + VOID *MemoryInitUpdPtr; + VOID *SiliconInitUpdPtr; + UINT8 ApiIdx; + /// + /// 0: FSP in API mode; 1: FSP in DISPATCH mode + /// + UINT8 FspMode; + UINT8 OnSeparateStack; + UINT8 Reserved3; + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; + /// + /// To store function parameters pointer + /// so it can be retrieved after stack switched. + /// + VOID *FunctionParameterPtr; + UINT8 Reserved4[16]; + UINT32 PerfSig; + UINT16 PerfLen; + UINT16 Reserved5; + UINT32 PerfIdx; + UINT64 PerfData[32]; +} FSP_GLOBAL_DATA; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspMeasurePointId.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspMeasurePointId.h new file mode 100644 index 0000000000..2092543f21 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspMeasurePointId.h @@ -0,0 +1,56 @@ +/** @file + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_MEASURE_POINT_ID_H_ +#define _FSP_MEASURE_POINT_ID_H_ + +// +// 0xD0 - 0xEF are reserved for FSP common measure point +// +#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0 +#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1) + +#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8 +#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1) + +#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA +#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1) + +#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0 +#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1) + +#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8 +#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1) + +#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA +#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1) + +// +// 0xF0 - 0xFF are reserved for FSP API +// +#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0 +#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2 +#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4 +#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1) + +#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6 +#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8 +#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA +#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC +#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1) + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspStatusCode.h new file mode 100644 index 0000000000..1c0954c55d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspStatusCode.h @@ -0,0 +1,40 @@ +/** @file + Intel FSP status code definition + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_STATUS_CODE_H_ +#define _FSP_STATUS_CODE_H_ + +// +// FSP API - 4 BITS +// +#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000 +#define FSP_STATUS_CODE_MEMORY_INIT 0xD000 +#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000 +#define FSP_STATUS_CODE_SILICON_INIT 0x9000 +#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000 +#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000 +#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000 + +// +// MODULE - 4 BITS +// +#define FSP_STATUS_CODE_GFX_PEIM 0x0700 +#define FSP_STATUS_CODE_COMMON_CODE 0x0800 +#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900 +#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00 +#define FSP_STATUS_CODE_PCH 0x0B00 +#define FSP_STATUS_CODE_CPU 0x0C00 +#define FSP_STATUS_CODE_MRC 0x0D00 +#define FSP_STATUS_CODE_ME_BIOS 0x0E00 +// +// Individual Codes - 1 BYTE +// +#define FSP_STATUS_CODE_API_ENTRY 0x0000 +#define FSP_STATUS_CODE_API_EXIT 0x007F + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h new file mode 100644 index 0000000000..6751af1601 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -0,0 +1,235 @@ +/** @file + Intel FSP Header File definition from Intel Firmware Support Package External + Architecture Specification v2.0 and above. + + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FSP_HEADER_FILE_H__ +#define __FSP_HEADER_FILE_H__ + +#define FSP_HEADER_REVISION_3 3 + +#define FSPE_HEADER_REVISION_1 1 +#define FSPP_HEADER_REVISION_1 1 + +/// +/// Fixed FSP header offset in the FSP image +/// +#define FSP_INFO_HEADER_OFF 0x94 + +#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x + +#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') + +#pragma pack(1) + +/// +/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1. +/// +typedef struct { + /// + /// Byte 0x00: Signature ('FSPH') for the FSP Information Header. + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the FSP Information Header. + /// + UINT32 HeaderLength; + /// + /// Byte 0x08: Reserved. + /// + UINT8 Reserved1[2]; + /// + /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format. + /// For revision v2.3 the value will be 0x23. + /// + UINT8 SpecVersion; + /// + /// Byte 0x0B: Revision of the FSP Information Header. + /// The Current value for this field is 0x6. + /// + UINT8 HeaderRevision; + /// + /// Byte 0x0C: Revision of the FSP binary. + /// Major.Minor.Revision.Build + /// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows: + /// 7 : 0 - Build Number + /// 15 : 8 - Revision + /// 23 : 16 - Minor Version + /// 31 : 24 - Major Version + /// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision + /// while ExtendedImageRevision specifies the high-order bytes of the build number and revision. + /// 7 : 0 - Low Byte of Build Number + /// 15 : 8 - Low Byte of Revision + /// 23 : 16 - Minor Version + /// 31 : 24 - Major Version + /// + UINT32 ImageRevision; + /// + /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration. + /// + CHAR8 ImageId[8]; + /// + /// Byte 0x18: Size of the entire FSP binary. + /// + UINT32 ImageSize; + /// + /// Byte 0x1C: FSP binary preferred base address. + /// + UINT32 ImageBase; + /// + /// Byte 0x20: Attribute for the FSP binary. + /// + UINT16 ImageAttribute; + /// + /// Byte 0x22: Attributes of the FSP Component. + /// + UINT16 ComponentAttribute; + /// + /// Byte 0x24: Offset of the FSP configuration region. + /// + UINT32 CfgRegionOffset; + /// + /// Byte 0x28: Size of the FSP configuration region. + /// + UINT32 CfgRegionSize; + /// + /// Byte 0x2C: Reserved2. + /// + UINT32 Reserved2; + /// + /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized. + /// + UINT32 TempRamInitEntryOffset; + /// + /// Byte 0x34: Reserved3. + /// + UINT32 Reserved3; + /// + /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process. + /// + UINT32 NotifyPhaseEntryOffset; + /// + /// Byte 0x3C: The offset for the API to initialize the memory. + /// + UINT32 FspMemoryInitEntryOffset; + /// + /// Byte 0x40: The offset for the API to tear down temporary RAM. + /// + UINT32 TempRamExitEntryOffset; + /// + /// Byte 0x44: The offset for the API to initialize the CPU and chipset. + /// + UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >= 5. + /// If the value is set to 0x00000000, then this API is not available in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; + /// + /// Byte 0x4C: Extended revision of the FSP binary. + /// This value is only valid if FSP HeaderRevision is >= 6. + /// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision. + /// 7 : 0 - High Byte of Build Number + /// 15 : 8 - High Byte of Revision + /// The FSP binary build number can be decoded as follows: + /// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0] + /// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8] + /// Minor Version = ImageRevision[23:16] + /// Major Version = ImageRevision[31:24] + /// + UINT16 ExtendedImageRevision; + /// + /// Byte 0x4E: Reserved4. + /// + UINT16 Reserved4; +} FSP_INFO_HEADER; + +/// +/// Signature of the FSP Extended Header +/// +#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E') + +/// +/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2. +/// +typedef struct { + /// + /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header. + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data. + /// + UINT32 Length; + /// + /// Byte 0x08: FSP producer defined revision of the table. + /// + UINT8 Revision; + /// + /// Byte 0x09: Reserved for future use. + /// + UINT8 Reserved; + /// + /// Byte 0x0A: FSP producer identification string + /// + CHAR8 FspProducerId[6]; + /// + /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions. + /// + UINT32 FspProducerRevision; + /// + /// Byte 0x14: Size of the FSP producer defined data (n) in bytes. + /// + UINT32 FspProducerDataSize; + /// + /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize. + /// +} FSP_INFO_EXTENDED_HEADER; + +// +// A generic table search algorithm for additional tables can be implemented with a +// signature search algorithm until a terminator signature 'FSPP' is found. +// +#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P') +#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE + +/// +/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5. +/// +typedef struct { + /// + /// Byte 0x00: FSP Patch Table Signature "FSPP". + /// + UINT32 Signature; + /// + /// Byte 0x04: Size including the PatchData. + /// + UINT16 HeaderLength; + /// + /// Byte 0x06: Revision is set to 0x01. + /// + UINT8 HeaderRevision; + /// + /// Byte 0x07: Reserved for future use. + /// + UINT8 Reserved; + /// + /// Byte 0x08: Number of entries to Patch. + /// + UINT32 PatchEntryNum; + /// + /// Byte 0x0C: Patch Data. + /// +//UINT32 PatchData[]; +} FSP_PATCH_TABLE; + +#pragma pack() + +extern EFI_GUID gFspHeaderFileGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h new file mode 100644 index 0000000000..ad4a26b4f0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspNonVolatileStorageHob2.h @@ -0,0 +1,24 @@ +/** @file + Intel FSP Non-Volatile Storage (NVS) HOB version 2 definition from + Intel Firmware Support Package External Architecture Specification v2.3. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FSP_NON_VOLATILE_STORAGE_HOB2_H__ +#define __FSP_NON_VOLATILE_STORAGE_HOB2_H__ + +/// +/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support. +/// +typedef struct { + EFI_HOB_GUID_TYPE GuidHob; + EFI_PHYSICAL_ADDRESS NvsDataPtr; + UINT64 NvsDataLength; +} FSP_NON_VOLATILE_STORAGE_HOB2; + +extern EFI_GUID gFspNonVolatileStorageHob2Guid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h new file mode 100644 index 0000000000..631eef362f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h @@ -0,0 +1,17 @@ +/** @file + Intel FSP Hob Guid definition from Intel Firmware Support Package External + Architecture Specification v2.0. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __GUID_HOB_FSP_EAS_GUID__ +#define __GUID_HOB_FSP_EAS_GUID__ + +extern EFI_GUID gFspBootLoaderTolumHobGuid; +extern EFI_GUID gFspReservedMemoryResourceHobGuid; +extern EFI_GUID gFspNonVolatileStorageHobGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h new file mode 100644 index 0000000000..c2a4e67868 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h @@ -0,0 +1,24 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CACHE_AS_RAM_LIB_H_ +#define _CACHE_AS_RAM_LIB_H_ + +/** + This function disable CAR. + + @param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD + +**/ +VOID +EFIAPI +DisableCacheAsRam ( + IN BOOLEAN DisableCar + ); + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheLib.h new file mode 100644 index 0000000000..7548b7e1af --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/CacheLib.h @@ -0,0 +1,56 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CACHE_LIB_H_ +#define _CACHE_LIB_H_ + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITECOMBINING 1 +#define EFI_CACHE_WRITETHROUGH 4 +#define EFI_CACHE_WRITEPROTECTED 5 +#define EFI_CACHE_WRITEBACK 6 + +/** + Reset all the MTRRs to a known state. + + @retval EFI_SUCCESS All MTRRs have been reset successfully. + +**/ +EFI_STATUS +EFIAPI +ResetCacheAttributes ( + VOID + ); + +/** + Given the memory range and cache type, programs the MTRRs. + + @param[in] MemoryAddress Base Address of Memory to program MTRR. + @param[in] MemoryLength Length of Memory to program MTRR. + @param[in] MemoryCacheType Cache Type. + + @retval EFI_SUCCESS Mtrr are set successfully. + @retval EFI_LOAD_ERROR No empty MTRRs to use. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. + @retval others An error occurs when setting MTTR. + +**/ +EFI_STATUS +EFIAPI +SetCacheAttributes ( + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h new file mode 100644 index 0000000000..f8611909f0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEBUG_DEVICE_LIB_H__ +#define __DEBUG_DEVICE_LIB_H__ + +/** + Returns the debug print device enable state. + + @return Debug print device enable state. + +**/ +UINT8 +EFIAPI +GetDebugPrintDeviceEnable ( + VOID + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspCommonLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspCommonLib.h new file mode 100644 index 0000000000..dfc87ae63d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspCommonLib.h @@ -0,0 +1,308 @@ +/** @file + + Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_COMMON_LIB_H_ +#define _FSP_COMMON_LIB_H_ + +#include +#include + +/** + This function sets the FSP global data pointer. + + @param[in] FspData Fsp global data pointer. + +**/ +VOID +EFIAPI +SetFspGlobalDataPointer ( + IN FSP_GLOBAL_DATA *FspData + ); + +/** + This function gets the FSP global data pointer. + +**/ +FSP_GLOBAL_DATA * +EFIAPI +GetFspGlobalDataPointer ( + VOID + ); + +/** + This function gets back the FSP API first parameter passed by the bootloader. + + @retval ApiParameter FSP API first parameter passed by the bootloader. +**/ +UINT32 +EFIAPI +GetFspApiParameter ( + VOID + ); + +/** + This function gets back the FSP API second parameter passed by the bootloader. + + @retval ApiParameter FSP API second parameter passed by the bootloader. +**/ +UINT32 +EFIAPI +GetFspApiParameter2 ( + VOID + ); + +/** + This function returns the FSP entry stack pointer from address of the first API parameter. + + @retval FSP entry stack pointer. +**/ +VOID* +EFIAPI +GetFspEntryStack ( + VOID + ); + +/** + This function sets the FSP API parameter in the stack. + + @param[in] Value New parameter value. + +**/ +VOID +EFIAPI +SetFspApiParameter ( + IN UINT32 Value + ); + +/** + This function set the API status code returned to the BootLoader. + + @param[in] ReturnStatus Status code to return. + +**/ +VOID +EFIAPI +SetFspApiReturnStatus ( + IN UINT32 ReturnStatus + ); + +/** + This function sets the context switching stack to a new stack frame. + + @param[in] NewStackTop New core stack to be set. + +**/ +VOID +EFIAPI +SetFspCoreStackPointer ( + IN VOID *NewStackTop + ); + +/** + This function sets the platform specific data pointer. + + @param[in] PlatformData Fsp platform specific data pointer. + +**/ +VOID +EFIAPI +SetFspPlatformDataPointer ( + IN VOID *PlatformData + ); + +/** + This function gets the platform specific data pointer. + + @param[in] PlatformData Fsp platform specific data pointer. + +**/ +VOID * +EFIAPI +GetFspPlatformDataPointer ( + VOID + ); + +/** + This function sets the UPD data pointer. + + @param[in] UpdDataPtr UPD data pointer. +**/ +VOID +EFIAPI +SetFspUpdDataPointer ( + IN VOID *UpdDataPtr + ); + +/** + This function gets the UPD data pointer. + + @return UpdDataPtr UPD data pointer. +**/ +VOID * +EFIAPI +GetFspUpdDataPointer ( + VOID + ); + +/** + This function sets the memory init UPD data pointer. + + @param[in] MemoryInitUpdPtr memory init UPD data pointer. +**/ +VOID +EFIAPI +SetFspMemoryInitUpdDataPointer ( + IN VOID *MemoryInitUpdPtr + ); + +/** + This function gets the memory init UPD data pointer. + + @return memory init UPD data pointer. +**/ +VOID * +EFIAPI +GetFspMemoryInitUpdDataPointer ( + VOID + ); + +/** + This function sets the silicon init UPD data pointer. + + @param[in] SiliconInitUpdPtr silicon init UPD data pointer. +**/ +VOID +EFIAPI +SetFspSiliconInitUpdDataPointer ( + IN VOID *SiliconInitUpdPtr + ); + +/** + This function gets the silicon init UPD data pointer. + + @return silicon init UPD data pointer. +**/ +VOID * +EFIAPI +GetFspSiliconInitUpdDataPointer ( + VOID + ); + +/** + Set FSP measurement point timestamp. + + @param[in] Id Measurement point ID. + + @return performance timestamp. +**/ +UINT64 +EFIAPI +SetFspMeasurePoint ( + IN UINT8 Id + ); + +/** + This function gets the FSP info header pointer. + + @retval FspInfoHeader FSP info header pointer +**/ +FSP_INFO_HEADER * +EFIAPI +GetFspInfoHeader ( + VOID + ); + +/** + This function sets the FSP info header pointer. + + @param[in] FspInfoHeader FSP info header pointer +**/ +VOID +EFIAPI +SetFspInfoHeader ( + FSP_INFO_HEADER *FspInfoHeader + ); + +/** + This function gets the FSP info header pointer from the API context. + + @retval FspInfoHeader FSP info header pointer +**/ +FSP_INFO_HEADER * +EFIAPI +GetFspInfoHeaderFromApiContext ( + VOID + ); + +/** + This function gets the CfgRegion data pointer. + + @return CfgRegion data pointer. +**/ +VOID * +EFIAPI +GetFspCfgRegionDataPointer ( + VOID + ); + +/** + This function gets FSP API calling mode. + + @retval API calling mode +**/ +UINT8 +EFIAPI +GetFspApiCallingIndex ( + VOID + ); + +/** + This function sets FSP API calling mode. + + @param[in] Index API calling index +**/ +VOID +EFIAPI +SetFspApiCallingIndex ( + UINT8 Index + ); + +/** + This function gets FSP Phase StatusCode. + + @retval StatusCode +**/ +UINT32 +EFIAPI +GetPhaseStatusCode ( + VOID + ); + + +/** + This function sets FSP Phase StatusCode. + + @param[in] Mode Phase StatusCode +**/ +VOID +EFIAPI +SetPhaseStatusCode ( + UINT32 StatusCode + ); + +/** + This function updates the return status of the FSP API with requested reset type and returns to Boot Loader. + + @param[in] FspResetType Reset type that needs to returned as API return status + +**/ +VOID +EFIAPI +FspApiReturnStatusReset ( + IN UINT32 FspResetType + ); +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspPlatformLib.h new file mode 100644 index 0000000000..680416b46e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspPlatformLib.h @@ -0,0 +1,125 @@ +/** @file + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_PLATFORM_LIB_H_ +#define _FSP_PLATFORM_LIB_H_ + +/** + Get system memory resource descriptor by owner. + + @param[in] OwnerGuid resource owner guid +**/ +EFI_HOB_RESOURCE_DESCRIPTOR * +EFIAPI +FspGetResourceDescriptorByOwner ( + IN EFI_GUID *OwnerGuid + ); + +/** + Get system memory from HOB. + + @param[in,out] LowMemoryLength less than 4G memory length + @param[in,out] HighMemoryLength greater than 4G memory length +**/ +VOID +EFIAPI +FspGetSystemMemorySize ( + IN OUT UINT64 *LowMemoryLength, + IN OUT UINT64 *HighMemoryLength + ); + + +/** + Set a new stack frame for the continuation function. + +**/ +VOID +EFIAPI +FspSetNewStackFrame ( + VOID + ); + +/** + This function transfer control back to BootLoader after FspSiliconInit. + +**/ +VOID +EFIAPI +FspSiliconInitDone ( + VOID + ); + +/** + This function returns control to BootLoader after MemoryInitApi. + + @param[in,out] HobListPtr The address of HobList pointer. +**/ +VOID +EFIAPI +FspMemoryInitDone ( + IN OUT VOID **HobListPtr + ); + +/** + This function returns control to BootLoader after TempRamExitApi. + +**/ +VOID +EFIAPI +FspTempRamExitDone ( + VOID + ); + +/** + This function handle NotifyPhase API call from the BootLoader. + It gives control back to the BootLoader after it is handled. If the + Notification code is a ReadyToBoot event, this function will return + and FSP continues the remaining execution until it reaches the DxeIpl. + +**/ +VOID +EFIAPI +FspWaitForNotify ( + VOID + ); + +/** + This function transfer control back to BootLoader after FspSiliconInit. + + @param[in] Status return status for the FspSiliconInit. +**/ +VOID +EFIAPI +FspSiliconInitDone2 ( + IN EFI_STATUS Status + ); + +/** + This function returns control to BootLoader after MemoryInitApi. + + @param[in] Status return status for the MemoryInitApi. + @param[in,out] HobListPtr The address of HobList pointer. +**/ +VOID +EFIAPI +FspMemoryInitDone2 ( + IN EFI_STATUS Status, + IN OUT VOID **HobListPtr + ); + +/** + This function returns control to BootLoader after TempRamExitApi. + + @param[in] Status return status for the TempRamExitApi. +**/ +VOID +EFIAPI +FspTempRamExitDone2 ( + IN EFI_STATUS Status + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h new file mode 100644 index 0000000000..d6ecbd47cc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -0,0 +1,96 @@ +/** @file + + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SEC_PLATFORM_LIB_H_ +#define _FSP_SEC_PLATFORM_LIB_H_ + +/** + This function performs platform level initialization. + + This function must be in ASM file, because stack is not established yet. + This function is optional. If a library instance does not provide this function, the default empty one will be used. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @retval in saved in EAX - 0 means platform initialization success. + other means platform initialization fail. +**/ +UINT32 +EFIAPI +SecPlatformInit ( + VOID + ); + +/** + This function loads Microcode. + + This function must be in ASM file, because stack is not established yet. + This function is optional. If a library instance does not provide this function, the default one will be used. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP. + + @retval in saved in EAX - 0 means Microcode is loaded successfully. + other means Microcode is not loaded successfully. +**/ +UINT32 +EFIAPI +LoadMicrocode ( + IN VOID *FsptUpdDataPtr + ); + +/** + This function initializes the CAR. + + This function must be in ASM file, because stack is not established yet. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP. + + @retval in saved in EAX - 0 means CAR initialization success. + other means CAR initialization fail. +**/ +UINT32 +EFIAPI +SecCarInit ( + IN VOID *FsptUpdDataPtr + ); + +/** + This function check the signature of UPD. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspUpdSignatureCheck ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h new file mode 100644 index 0000000000..259a57606a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h @@ -0,0 +1,55 @@ +/** @file + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SWITCH_STACK_LIB_H_ +#define _FSP_SWITCH_STACK_LIB_H_ + +/** + + This function will switch the current stack to the previous saved stack. + Before calling the previous stack has to be set in FSP_GLOBAL_DATA.CoreStack. + EIP + FLAGS 16 bit FLAGS 16 bit + EDI + ESI + EBP + ESP + EBX + EDX + ECX + EAX + DWORD IDT base1 + StackPointer: DWORD IDT base2 + + @return ReturnKey After switching to the saved stack, + this value will be saved in eax before returning. + + +**/ +UINT32 +EFIAPI +Pei2LoaderSwitchStack ( + VOID + ); + +/** + + This function is equivalent to Pei2LoaderSwitchStack () but just indicates + the stack after switched is FSP stack. + + @return ReturnKey After switching to the saved stack, + this value will be saved in eax before returning. + + +**/ +UINT32 +EFIAPI +Loader2PeiSwitchStack ( + VOID + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h new file mode 100644 index 0000000000..e3c62a9483 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h @@ -0,0 +1,47 @@ +/** @file + Header file for FSP-M Arch Config PPI for Dispatch mode + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ +#define _FSPM_ARCH_CONFIG_PPI_H_ + +#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1 + +/// +/// Global ID for the FSPM_ARCH_CONFIG_PPI. +/// +#define FSPM_ARCH_CONFIG_GUID \ + { \ + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \ + } + +/// +/// This PPI provides FSP-M Arch Config PPI. +/// +typedef struct { + /// + /// Revision of the structure + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + VOID *NvsBufferPtr; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + UINT8 Reserved1[4]; +} FSPM_ARCH_CONFIG_PPI; + +extern EFI_GUID gFspmArchConfigPpiGuid; + +#endif // _FSPM_ARCH_CONFIG_PPI_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h new file mode 100644 index 0000000000..ed3a1c1968 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h @@ -0,0 +1,52 @@ +/** @file + This file defines the Silicon Temp Ram Exit PPI which implements the + required programming steps for disabling temporary memory. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_ +#define _FSP_TEMP_RAM_EXIT_PPI_H_ + +/// +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI. +/// +#define FSP_TEMP_RAM_EXIT_GUID \ + { \ + 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \ + } + +// +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI. +// +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI; + +/** + Silicon function for disabling temporary memory. + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters structure. + This structure is normally defined in the Integration + Guide. If it is not defined in the Integration Guide, + pass NULL. + @retval EFI_SUCCESS - FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER - Input parameters are invalid. + @retval EFI_UNSUPPORTED - The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR - Temporary memory exit. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_EXIT) ( + IN VOID *TempRamExitParamPtr + ); + +/// +/// This PPI provides function to disable temporary memory. +/// +struct _FSP_TEMP_RAM_EXIT_PPI { + FSP_TEMP_RAM_EXIT TempRamExit; +}; + +extern EFI_GUID gFspTempRamExitPpiGuid; + +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/AArch64/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/AArch64/ProcessorBind.h new file mode 100644 index 0000000000..9603c32d93 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/AArch64/ProcessorBind.h @@ -0,0 +1,207 @@ +/** @file + Processor or Compiler specific defines and types for AArch64. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_AARCH64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) && !defined(__ASSEMBLER__) +#pragma pack() +#endif + +#if defined(_MSC_EXTENSIONS) + +// +// Disable some level 4 compilation warnings (same as IA32 and X64) +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompiled header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For precompiled header only. +// +#pragma warning ( disable : 4206 ) + +// +// Disable 'potentially uninitialized local variable X used' warnings +// +#pragma warning ( disable : 4701 ) + +// +// Disable 'potentially uninitialized local pointer variable X used' warnings +// +#pragma warning ( disable : 4703 ) + + // + // use Microsoft* C compiler dependent integer width types + // + typedef unsigned __int64 UINT64; + typedef __int64 INT64; + typedef unsigned __int32 UINT32; + typedef __int32 INT32; + typedef unsigned short UINT16; + typedef unsigned short CHAR16; + typedef short INT16; + typedef unsigned char BOOLEAN; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef signed char INT8; + +#else + + // + // Assume standard AARCH64 alignment. + // + typedef unsigned long long UINT64; + typedef long long INT64; + typedef unsigned int UINT32; + typedef int INT32; + typedef unsigned short UINT16; + typedef unsigned short CHAR16; + typedef short INT16; + typedef unsigned char BOOLEAN; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef signed char INT8; + +#endif + +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN; + +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN; + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL + +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal AARCH64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal AArch64 INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// Minimum legal AArch64 INTN value. +/// +#define MIN_INTN (((INTN)-9223372036854775807LL) - 1) + +/// +/// The stack alignment required for AARCH64 +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for AARCH64 +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#define EFIAPI + +// When compiling with Clang, we still use GNU as for the assembler, so we still +// need to define the GCC_ASM* macros. +#if defined(__GNUC__) || defined(__clang__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl + + #define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + + #define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On ARM CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Arm/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Arm/ProcessorBind.h new file mode 100644 index 0000000000..8794f07cf3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Arm/ProcessorBind.h @@ -0,0 +1,240 @@ +/** @file + Processor or Compiler specific defines and types for ARM. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_ARM + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) && !defined(__ASSEMBLER__) +#pragma pack() +#endif + +#if defined(_MSC_EXTENSIONS) + +// +// Disable some level 4 compilation warnings (same as IA32 and X64) +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompiled header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For precompiled header only. +// +#pragma warning ( disable : 4206 ) + +// +// Disable 'potentially uninitialized local variable X used' warnings +// +#pragma warning ( disable : 4701 ) + +// +// Disable 'potentially uninitialized local pointer variable X used' warnings +// +#pragma warning ( disable : 4703 ) + +#endif + +// +// RVCT and MSFT don't support the __builtin_unreachable() macro +// +#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS) +#define UNREACHABLE() +#endif + +#if defined(_MSC_EXTENSIONS) + // + // use Microsoft* C compiler dependent integer width types + // + typedef unsigned __int64 UINT64; + typedef __int64 INT64; + typedef unsigned __int32 UINT32; + typedef __int32 INT32; + typedef unsigned short UINT16; + typedef unsigned short CHAR16; + typedef short INT16; + typedef unsigned char BOOLEAN; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef signed char INT8; +#else + // + // Assume standard ARM alignment. + // Need to check portability of long long + // + typedef unsigned long long UINT64; + typedef long long INT64; + typedef unsigned int UINT32; + typedef int INT32; + typedef unsigned short UINT16; + typedef unsigned short CHAR16; + typedef short INT16; + typedef unsigned char BOOLEAN; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef signed char INT8; +#endif + +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT32 UINTN; + +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT32 INTN; + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x80000000 + +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC0000000 + +/// +/// Maximum legal ARM address +/// +#define MAX_ADDRESS 0xFFFFFFFF + +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + +/// +/// Maximum legal ARM INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFF) +#define MAX_UINTN ((UINTN)0xFFFFFFFF) + +/// +/// Minimum legal ARM INTN value. +/// +#define MIN_INTN (((INTN)-2147483647) - 1) + +/// +/// The stack alignment required for ARM +/// +#define CPU_STACK_ALIGNMENT sizeof(UINT64) + +/// +/// Page allocation granularity for ARM +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#define EFIAPI + +// When compiling with Clang, we still use GNU as for the assembler, so we still +// need to define the GCC_ASM* macros. +#if defined(__GNUC__) || defined(__clang__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl + + #if !defined(__APPLE__) + /// + /// ARM EABI defines that the linker should not manipulate call relocations + /// (do bl/blx conversion) unless the target symbol has function type. + /// CodeSourcery 2010.09 started requiring the .type to function properly + /// + #define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function + + #define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + + #define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + + #else + // + // .type not supported by Apple Xcode tools + // + #define INTERWORK_FUNC(func__) + + #define GCC_ASM_EXPORT(func__) \ + .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \ + + #define GCC_ASM_IMPORT(name) + + #endif +#elif defined(_MSC_EXTENSIONS) + // + // PRESERVE8 is not supported by the MSFT assembler. + // + #define PRESERVE8 +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On ARM CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h new file mode 100644 index 0000000000..1d79bf651d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h @@ -0,0 +1,1326 @@ +/** @file + Root include file for Mde Package Base type modules + + This is the include file for any module of type base. Base modules only use + types defined via this include file and can be ported easily to any + environment. There are a set of base libraries in the Mde Package that can + be used to implement base modules. + +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __BASE_H__ +#define __BASE_H__ + +// +// Include processor specific binding +// +#include + +#if defined(_MSC_EXTENSIONS) +// +// Disable warning when last field of data structure is a zero sized array. +// +#pragma warning ( disable : 4200 ) +#endif + +// +// The Microsoft* C compiler can removed references to unreferenced data items +// if the /OPT:REF linker option is used. We defined a macro as this is a +// a non standard extension +// +#if defined(_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC) + /// + /// Remove global variable from the linked image if there are no references to + /// it after all compiler and linker optimizations have been performed. + /// + /// + #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany) +#else + /// + /// Remove the global variable from the linked image if there are no references + /// to it after all compiler and linker optimizations have been performed. + /// + /// + #define GLOBAL_REMOVE_IF_UNREFERENCED +#endif + +// +// Should be used in combination with NORETURN to avoid 'noreturn' returns +// warnings. +// +#ifndef UNREACHABLE + #ifdef __GNUC__ + /// + /// Signal compilers and analyzers that this call is not reachable. It is + /// up to the compiler to remove any code past that point. + /// + #define UNREACHABLE() __builtin_unreachable () + #elif defined (__has_feature) + #if __has_builtin (__builtin_unreachable) + /// + /// Signal compilers and analyzers that this call is not reachable. It is + /// up to the compiler to remove any code past that point. + /// + #define UNREACHABLE() __builtin_unreachable () + #endif + #endif + + #ifndef UNREACHABLE + /// + /// Signal compilers and analyzers that this call is not reachable. It is + /// up to the compiler to remove any code past that point. + /// + #define UNREACHABLE() + #endif +#endif + +// +// Signaling compilers and analyzers that a certain function cannot return may +// remove all following code and thus lead to better optimization and less +// false positives. +// +#ifndef NORETURN + #if defined (__GNUC__) || defined (__clang__) + /// + /// Signal compilers and analyzers that the function cannot return. + /// It is up to the compiler to remove any code past a call to functions + /// flagged with this attribute. + /// + #define NORETURN __attribute__((noreturn)) + #elif defined(_MSC_EXTENSIONS) && !defined(MDE_CPU_EBC) + /// + /// Signal compilers and analyzers that the function cannot return. + /// It is up to the compiler to remove any code past a call to functions + /// flagged with this attribute. + /// + #define NORETURN __declspec(noreturn) + #else + /// + /// Signal compilers and analyzers that the function cannot return. + /// It is up to the compiler to remove any code past a call to functions + /// flagged with this attribute. + /// + #define NORETURN + #endif +#endif + +// +// Should be used in combination with ANALYZER_NORETURN to avoid 'noreturn' +// returns warnings. +// +#ifndef ANALYZER_UNREACHABLE + #ifdef __clang_analyzer__ + #if __has_builtin (__builtin_unreachable) + /// + /// Signal the analyzer that this call is not reachable. + /// This excludes compilers. + /// + #define ANALYZER_UNREACHABLE() __builtin_unreachable () + #endif + #endif + + #ifndef ANALYZER_UNREACHABLE + /// + /// Signal the analyzer that this call is not reachable. + /// This excludes compilers. + /// + #define ANALYZER_UNREACHABLE() + #endif +#endif + +// +// Static Analyzers may issue errors about potential NULL-dereferences when +// dereferencing a pointer, that has been checked before, outside of a +// NULL-check. This may lead to false positives, such as when using ASSERT() +// for verification. +// +#ifndef ANALYZER_NORETURN + #ifdef __has_feature + #if __has_feature (attribute_analyzer_noreturn) + /// + /// Signal analyzers that the function cannot return. + /// This excludes compilers. + /// + #define ANALYZER_NORETURN __attribute__((analyzer_noreturn)) + #endif + #endif + + #ifndef ANALYZER_NORETURN + /// + /// Signal the analyzer that the function cannot return. + /// This excludes compilers. + /// + #define ANALYZER_NORETURN + #endif +#endif + +/// +/// Tell the code optimizer that the function will return twice. +/// This prevents wrong optimizations which can cause bugs. +/// +#ifndef RETURNS_TWICE + #if defined (__GNUC__) || defined (__clang__) + /// + /// Tell the code optimizer that the function will return twice. + /// This prevents wrong optimizations which can cause bugs. + /// + #define RETURNS_TWICE __attribute__((returns_twice)) + #else + /// + /// Tell the code optimizer that the function will return twice. + /// This prevents wrong optimizations which can cause bugs. + /// + #define RETURNS_TWICE + #endif +#endif + +// +// For symbol name in assembly code, an extra "_" is sometimes necessary +// + +/// +/// Private worker functions for ASM_PFX() +/// +#define _CONCATENATE(a, b) __CONCATENATE(a, b) +#define __CONCATENATE(a, b) a ## b + +/// +/// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix +/// on symbols in assembly language. +/// +#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) + +#ifdef __APPLE__ + // + // Apple extension that is used by the linker to optimize code size + // with assembly functions. Put at the end of your .S files + // + #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols +#else + #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED +#endif + +#ifdef __CC_ARM + // + // Older RVCT ARM compilers don't fully support #pragma pack and require __packed + // as a prefix for the structure. + // + #define PACKED __packed +#else + #define PACKED +#endif + +/// +/// 128 bit buffer containing a unique identifier value. +/// Unless otherwise specified, aligned on a 64 bit boundary. +/// +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} GUID; + +/// +/// 4-byte buffer. An IPv4 internet protocol address. +/// +typedef struct { + UINT8 Addr[4]; +} IPv4_ADDRESS; + +/// +/// 16-byte buffer. An IPv6 internet protocol address. +/// +typedef struct { + UINT8 Addr[16]; +} IPv6_ADDRESS; + +// +// 8-bytes unsigned value that represents a physical system address. +// +typedef UINT64 PHYSICAL_ADDRESS; + +/// +/// LIST_ENTRY structure definition. +/// +typedef struct _LIST_ENTRY LIST_ENTRY; + +/// +/// _LIST_ENTRY structure definition. +/// +struct _LIST_ENTRY { + LIST_ENTRY *ForwardLink; + LIST_ENTRY *BackLink; +}; + +// +// Modifiers to abstract standard types to aid in debug of problems +// + +/// +/// Datum is read-only. +/// +#define CONST const + +/// +/// Datum is scoped to the current file or function. +/// +#define STATIC static + +/// +/// Undeclared type. +/// +#define VOID void + +// +// Modifiers for Data Types used to self document code. +// This concept is borrowed for UEFI specification. +// + +/// +/// Datum is passed to the function. +/// +#define IN + +/// +/// Datum is returned from the function. +/// +#define OUT + +/// +/// Passing the datum to the function is optional, and a NULL +/// is passed if the value is not supplied. +/// +#define OPTIONAL + +// +// UEFI specification claims 1 and 0. We are concerned about the +// compiler portability so we did it this way. +// + +/// +/// Boolean true value. UEFI Specification defines this value to be 1, +/// but this form is more portable. +/// +#define TRUE ((BOOLEAN)(1==1)) + +/// +/// Boolean false value. UEFI Specification defines this value to be 0, +/// but this form is more portable. +/// +#define FALSE ((BOOLEAN)(0==1)) + +/// +/// NULL pointer (VOID *) +/// +#ifndef NULL +#define NULL ((VOID *) 0) +#endif + +// +// Null character +// +#define CHAR_NULL 0x0000 + +/// +/// Maximum values for common UEFI Data Types +/// +#define MAX_INT8 ((INT8)0x7F) +#define MAX_UINT8 ((UINT8)0xFF) +#define MAX_INT16 ((INT16)0x7FFF) +#define MAX_UINT16 ((UINT16)0xFFFF) +#define MAX_INT32 ((INT32)0x7FFFFFFF) +#define MAX_UINT32 ((UINT32)0xFFFFFFFF) +#define MAX_INT64 ((INT64)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINT64 ((UINT64)0xFFFFFFFFFFFFFFFFULL) + +/// +/// Minimum values for the signed UEFI Data Types +/// +#define MIN_INT8 (((INT8) -127) - 1) +#define MIN_INT16 (((INT16) -32767) - 1) +#define MIN_INT32 (((INT32) -2147483647) - 1) +#define MIN_INT64 (((INT64) -9223372036854775807LL) - 1) + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x0000000100000000ULL +#define BIT33 0x0000000200000000ULL +#define BIT34 0x0000000400000000ULL +#define BIT35 0x0000000800000000ULL +#define BIT36 0x0000001000000000ULL +#define BIT37 0x0000002000000000ULL +#define BIT38 0x0000004000000000ULL +#define BIT39 0x0000008000000000ULL +#define BIT40 0x0000010000000000ULL +#define BIT41 0x0000020000000000ULL +#define BIT42 0x0000040000000000ULL +#define BIT43 0x0000080000000000ULL +#define BIT44 0x0000100000000000ULL +#define BIT45 0x0000200000000000ULL +#define BIT46 0x0000400000000000ULL +#define BIT47 0x0000800000000000ULL +#define BIT48 0x0001000000000000ULL +#define BIT49 0x0002000000000000ULL +#define BIT50 0x0004000000000000ULL +#define BIT51 0x0008000000000000ULL +#define BIT52 0x0010000000000000ULL +#define BIT53 0x0020000000000000ULL +#define BIT54 0x0040000000000000ULL +#define BIT55 0x0080000000000000ULL +#define BIT56 0x0100000000000000ULL +#define BIT57 0x0200000000000000ULL +#define BIT58 0x0400000000000000ULL +#define BIT59 0x0800000000000000ULL +#define BIT60 0x1000000000000000ULL +#define BIT61 0x2000000000000000ULL +#define BIT62 0x4000000000000000ULL +#define BIT63 0x8000000000000000ULL + +#define SIZE_1KB 0x00000400 +#define SIZE_2KB 0x00000800 +#define SIZE_4KB 0x00001000 +#define SIZE_8KB 0x00002000 +#define SIZE_16KB 0x00004000 +#define SIZE_32KB 0x00008000 +#define SIZE_64KB 0x00010000 +#define SIZE_128KB 0x00020000 +#define SIZE_256KB 0x00040000 +#define SIZE_512KB 0x00080000 +#define SIZE_1MB 0x00100000 +#define SIZE_2MB 0x00200000 +#define SIZE_4MB 0x00400000 +#define SIZE_8MB 0x00800000 +#define SIZE_16MB 0x01000000 +#define SIZE_32MB 0x02000000 +#define SIZE_64MB 0x04000000 +#define SIZE_128MB 0x08000000 +#define SIZE_256MB 0x10000000 +#define SIZE_512MB 0x20000000 +#define SIZE_1GB 0x40000000 +#define SIZE_2GB 0x80000000 +#define SIZE_4GB 0x0000000100000000ULL +#define SIZE_8GB 0x0000000200000000ULL +#define SIZE_16GB 0x0000000400000000ULL +#define SIZE_32GB 0x0000000800000000ULL +#define SIZE_64GB 0x0000001000000000ULL +#define SIZE_128GB 0x0000002000000000ULL +#define SIZE_256GB 0x0000004000000000ULL +#define SIZE_512GB 0x0000008000000000ULL +#define SIZE_1TB 0x0000010000000000ULL +#define SIZE_2TB 0x0000020000000000ULL +#define SIZE_4TB 0x0000040000000000ULL +#define SIZE_8TB 0x0000080000000000ULL +#define SIZE_16TB 0x0000100000000000ULL +#define SIZE_32TB 0x0000200000000000ULL +#define SIZE_64TB 0x0000400000000000ULL +#define SIZE_128TB 0x0000800000000000ULL +#define SIZE_256TB 0x0001000000000000ULL +#define SIZE_512TB 0x0002000000000000ULL +#define SIZE_1PB 0x0004000000000000ULL +#define SIZE_2PB 0x0008000000000000ULL +#define SIZE_4PB 0x0010000000000000ULL +#define SIZE_8PB 0x0020000000000000ULL +#define SIZE_16PB 0x0040000000000000ULL +#define SIZE_32PB 0x0080000000000000ULL +#define SIZE_64PB 0x0100000000000000ULL +#define SIZE_128PB 0x0200000000000000ULL +#define SIZE_256PB 0x0400000000000000ULL +#define SIZE_512PB 0x0800000000000000ULL +#define SIZE_1EB 0x1000000000000000ULL +#define SIZE_2EB 0x2000000000000000ULL +#define SIZE_4EB 0x4000000000000000ULL +#define SIZE_8EB 0x8000000000000000ULL + +#define BASE_1KB 0x00000400 +#define BASE_2KB 0x00000800 +#define BASE_4KB 0x00001000 +#define BASE_8KB 0x00002000 +#define BASE_16KB 0x00004000 +#define BASE_32KB 0x00008000 +#define BASE_64KB 0x00010000 +#define BASE_128KB 0x00020000 +#define BASE_256KB 0x00040000 +#define BASE_512KB 0x00080000 +#define BASE_1MB 0x00100000 +#define BASE_2MB 0x00200000 +#define BASE_4MB 0x00400000 +#define BASE_8MB 0x00800000 +#define BASE_16MB 0x01000000 +#define BASE_32MB 0x02000000 +#define BASE_64MB 0x04000000 +#define BASE_128MB 0x08000000 +#define BASE_256MB 0x10000000 +#define BASE_512MB 0x20000000 +#define BASE_1GB 0x40000000 +#define BASE_2GB 0x80000000 +#define BASE_4GB 0x0000000100000000ULL +#define BASE_8GB 0x0000000200000000ULL +#define BASE_16GB 0x0000000400000000ULL +#define BASE_32GB 0x0000000800000000ULL +#define BASE_64GB 0x0000001000000000ULL +#define BASE_128GB 0x0000002000000000ULL +#define BASE_256GB 0x0000004000000000ULL +#define BASE_512GB 0x0000008000000000ULL +#define BASE_1TB 0x0000010000000000ULL +#define BASE_2TB 0x0000020000000000ULL +#define BASE_4TB 0x0000040000000000ULL +#define BASE_8TB 0x0000080000000000ULL +#define BASE_16TB 0x0000100000000000ULL +#define BASE_32TB 0x0000200000000000ULL +#define BASE_64TB 0x0000400000000000ULL +#define BASE_128TB 0x0000800000000000ULL +#define BASE_256TB 0x0001000000000000ULL +#define BASE_512TB 0x0002000000000000ULL +#define BASE_1PB 0x0004000000000000ULL +#define BASE_2PB 0x0008000000000000ULL +#define BASE_4PB 0x0010000000000000ULL +#define BASE_8PB 0x0020000000000000ULL +#define BASE_16PB 0x0040000000000000ULL +#define BASE_32PB 0x0080000000000000ULL +#define BASE_64PB 0x0100000000000000ULL +#define BASE_128PB 0x0200000000000000ULL +#define BASE_256PB 0x0400000000000000ULL +#define BASE_512PB 0x0800000000000000ULL +#define BASE_1EB 0x1000000000000000ULL +#define BASE_2EB 0x2000000000000000ULL +#define BASE_4EB 0x4000000000000000ULL +#define BASE_8EB 0x8000000000000000ULL + +// +// Support for variable argument lists in freestanding edk2 modules. +// +// For modules that use the ISO C library interfaces for variable +// argument lists, refer to "StdLib/Include/stdarg.h". +// +// VA_LIST - typedef for argument list. +// VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use. +// VA_END (VA_LIST Marker) - Clear Marker +// VA_ARG (VA_LIST Marker, var arg type) - Use Marker to get an argument from +// the ... list. You must know the type and pass it in this macro. Type +// must be compatible with the type of the actual next argument (as promoted +// according to the default argument promotions.) +// VA_COPY (VA_LIST Dest, VA_LIST Start) - Initialize Dest as a copy of Start. +// +// Example: +// +// UINTN +// EFIAPI +// ExampleVarArg ( +// IN UINTN NumberOfArgs, +// ... +// ) +// { +// VA_LIST Marker; +// UINTN Index; +// UINTN Result; +// +// // +// // Initialize the Marker +// // +// VA_START (Marker, NumberOfArgs); +// for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) { +// // +// // The ... list is a series of UINTN values, so sum them up. +// // +// Result += VA_ARG (Marker, UINTN); +// } +// +// VA_END (Marker); +// return Result; +// } +// +// Notes: +// - Functions that call VA_START() / VA_END() must have a variable +// argument list and must be declared EFIAPI. +// - Functions that call VA_COPY() / VA_END() must be declared EFIAPI. +// - Functions that only use VA_LIST and VA_ARG() need not be EFIAPI. +// + +/** + Return the size of argument that has been aligned to sizeof (UINTN). + + @param n The parameter size to be aligned. + + @return The aligned size. +**/ +#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1)) + +#if defined(__CC_ARM) +// +// RVCT ARM variable argument list support. +// + +/// +/// Variable used to traverse the list of arguments. This type can vary by +/// implementation and could be an array or structure. +/// +#ifdef __APCS_ADSABI + typedef int *va_list[1]; + #define VA_LIST va_list +#else + typedef struct __va_list { void *__ap; } va_list; + #define VA_LIST va_list +#endif + +#define VA_START(Marker, Parameter) __va_start(Marker, Parameter) + +#define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE) + +#define VA_END(Marker) ((void)0) + +// For some ARM RVCT compilers, __va_copy is not defined +#ifndef __va_copy + #define __va_copy(dest, src) ((void)((dest) = (src))) +#endif + +#define VA_COPY(Dest, Start) __va_copy (Dest, Start) + +#elif defined(_M_ARM) || defined(_M_ARM64) +// +// MSFT ARM variable argument list support. +// + +typedef char* VA_LIST; + +#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter) +#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE))) +#define VA_END(Marker) (Marker = (VA_LIST) 0) +#define VA_COPY(Dest, Start) ((void)((Dest) = (Start))) + +#elif defined(__GNUC__) || defined(__clang__) + +#if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS) +// +// X64 only. Use MS ABI version of GCC built-in macros for variable argument lists. +// +/// +/// Both GCC and LLVM 3.8 for X64 support new variable argument intrinsics for Microsoft ABI +/// + +/// +/// Variable used to traverse the list of arguments. This type can vary by +/// implementation and could be an array or structure. +/// +typedef __builtin_ms_va_list VA_LIST; + +#define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter) + +#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE))) + +#define VA_END(Marker) __builtin_ms_va_end (Marker) + +#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start) + +#else +// +// Use GCC built-in macros for variable argument lists. +// + +/// +/// Variable used to traverse the list of arguments. This type can vary by +/// implementation and could be an array or structure. +/// +typedef __builtin_va_list VA_LIST; + +#define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter) + +#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE))) + +#define VA_END(Marker) __builtin_va_end (Marker) + +#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start) + +#endif + +#else +/// +/// Variable used to traverse the list of arguments. This type can vary by +/// implementation and could be an array or structure. +/// +typedef CHAR8 *VA_LIST; + +/** + Retrieves a pointer to the beginning of a variable argument list, based on + the name of the parameter that immediately precedes the variable argument list. + + This function initializes Marker to point to the beginning of the variable + argument list that immediately follows Parameter. The method for computing the + pointer to the next argument in the argument list is CPU-specific following the + EFIAPI ABI. + + @param Marker The VA_LIST used to traverse the list of arguments. + @param Parameter The name of the parameter that immediately precedes + the variable argument list. + + @return A pointer to the beginning of a variable argument list. + +**/ +#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter))) + +/** + Returns an argument of a specified type from a variable argument list and updates + the pointer to the variable argument list to point to the next argument. + + This function returns an argument of the type specified by TYPE from the beginning + of the variable argument list specified by Marker. Marker is then updated to point + to the next argument in the variable argument list. The method for computing the + pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI. + + @param Marker VA_LIST used to traverse the list of arguments. + @param TYPE The type of argument to retrieve from the beginning + of the variable argument list. + + @return An argument of the type specified by TYPE. + +**/ +#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE))) + +/** + Terminates the use of a variable argument list. + + This function initializes Marker so it can no longer be used with VA_ARG(). + After this macro is used, the only way to access the variable argument list is + by using VA_START() again. + + @param Marker VA_LIST used to traverse the list of arguments. + +**/ +#define VA_END(Marker) (Marker = (VA_LIST) 0) + +/** + Initializes a VA_LIST as a copy of an existing VA_LIST. + + This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest + followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach + the present state of Start. + + @param Dest VA_LIST used to traverse the list of arguments. + @param Start VA_LIST used to traverse the list of arguments. + +**/ +#define VA_COPY(Dest, Start) ((void)((Dest) = (Start))) + +#endif + +/// +/// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *. +/// +typedef UINTN *BASE_LIST; + +/** + Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary. + + @param TYPE The date type to determine the size of. + + @return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary. +**/ +#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN)) + +/** + Returns an argument of a specified type from a variable argument list and updates + the pointer to the variable argument list to point to the next argument. + + This function returns an argument of the type specified by TYPE from the beginning + of the variable argument list specified by Marker. Marker is then updated to point + to the next argument in the variable argument list. The method for computing the + pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI. + + @param Marker The pointer to the beginning of a variable argument list. + @param TYPE The type of argument to retrieve from the beginning + of the variable argument list. + + @return An argument of the type specified by TYPE. + +**/ +#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE))) + +/** + The macro that returns the byte offset of a field in a data structure. + + This function returns the offset, in bytes, of field specified by Field from the + beginning of the data structure specified by TYPE. If TYPE does not contain Field, + the module will not compile. + + @param TYPE The name of the data structure that contains the field specified by Field. + @param Field The name of the field in the data structure. + + @return Offset, in bytes, of field. + +**/ +#if (defined(__GNUC__) && __GNUC__ >= 4) || defined(__clang__) +#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field)) +#endif + +#ifndef OFFSET_OF +#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) +#endif + +/** + Portable definition for compile time assertions. + Equivalent to C11 static_assert macro from assert.h. + + @param Expression Boolean expression. + @param Message Raised compiler diagnostic message when expression is false. + +**/ +#ifdef MDE_CPU_EBC + #define STATIC_ASSERT(Expression, Message) +#elif defined(_MSC_EXTENSIONS) + #define STATIC_ASSERT static_assert +#else + #define STATIC_ASSERT _Static_assert +#endif + +// +// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with +// Section 2.3.1 of the UEFI 2.3 Specification. +// + +STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (INT8) == 1, "sizeof (INT8) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (UINT8) == 1, "sizeof (UINT8) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (INT16) == 2, "sizeof (INT16) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (UINT16) == 2, "sizeof (UINT16) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (INT32) == 4, "sizeof (INT32) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (UINT32) == 4, "sizeof (UINT32) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (INT64) == 8, "sizeof (INT64) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (UINT64) == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (CHAR8) == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements"); + +// +// The following three enum types are used to verify that the compiler +// configuration for enum types is compliant with Section 2.3.1 of the +// UEFI 2.3 Specification. These enum types and enum values are not +// intended to be used. A prefix of '__' is used avoid conflicts with +// other types. +// +typedef enum { + __VerifyUint8EnumValue = 0xff +} __VERIFY_UINT8_ENUM_SIZE; + +typedef enum { + __VerifyUint16EnumValue = 0xffff +} __VERIFY_UINT16_ENUM_SIZE; + +typedef enum { + __VerifyUint32EnumValue = 0xffffffff +} __VERIFY_UINT32_ENUM_SIZE; + +STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements"); +STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements"); + +/** + Macro that returns a pointer to the data structure that contains a specified field of + that data structure. This is a lightweight method to hide information by placing a + public data structure inside a larger private data structure and using a pointer to + the public data structure to retrieve a pointer to the private data structure. + + This function computes the offset, in bytes, of field specified by Field from the beginning + of the data structure specified by TYPE. This offset is subtracted from Record, and is + used to return a pointer to a data structure of the type specified by TYPE. If the data type + specified by TYPE does not contain the field specified by Field, then the module will not compile. + + @param Record Pointer to the field specified by Field within a data structure of type TYPE. + @param TYPE The name of the data structure type to return. This data structure must + contain the field specified by Field. + @param Field The name of the field in the data structure specified by TYPE to which Record points. + + @return A pointer to the structure from one of it's elements. + +**/ +#define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field))) + +/** + Rounds a value up to the next boundary using a specified alignment. + + This function rounds Value up to the next boundary using the specified Alignment. + This aligned value is returned. + + @param Value The value to round up. + @param Alignment The alignment boundary used to return the aligned value. + + @return A value up to the next boundary. + +**/ +#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1))) + +/** + Adjust a pointer by adding the minimum offset required for it to be aligned on + a specified alignment boundary. + + This function rounds the pointer specified by Pointer to the next alignment boundary + specified by Alignment. The pointer to the aligned address is returned. + + @param Pointer The pointer to round up. + @param Alignment The alignment boundary to use to return an aligned pointer. + + @return Pointer to the aligned address. + +**/ +#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment)))) + +/** + Rounds a value up to the next natural boundary for the current CPU. + This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs. + + This function rounds the value specified by Value up to the next natural boundary for the + current CPU. This rounded value is returned. + + @param Value The value to round up. + + @return Rounded value specified by Value. + +**/ +#define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN)) + + +/** + Return the maximum of two operands. + + This macro returns the maximum of two operand specified by a and b. + Both a and b must be the same numerical types, signed or unsigned. + + @param a The first operand with any numerical type. + @param b The second operand. Can be any numerical type as long as is + the same type as a. + + @return Maximum of two operands. + +**/ +#ifndef MAX +#define MAX(a, b) \ + (((a) > (b)) ? (a) : (b)) +#endif + +/** + Return the minimum of two operands. + + This macro returns the minimal of two operand specified by a and b. + Both a and b must be the same numerical types, signed or unsigned. + + @param a The first operand with any numerical type. + @param b The second operand. It should be the same any numerical type with a. + + @return Minimum of two operands. + +**/ +#ifndef MIN +#define MIN(a, b) \ + (((a) < (b)) ? (a) : (b)) +#endif + +/** + Return the absolute value of a signed operand. + + This macro returns the absolute value of the signed operand specified by a. + + @param a The signed operand. + + @return The absolute value of the signed operand. + +**/ +#ifndef ABS +#define ABS(a) \ + (((a) < 0) ? (-(a)) : (a)) +#endif + +// +// Status codes common to all execution phases +// +typedef UINTN RETURN_STATUS; + +/** + Produces a RETURN_STATUS code with the highest bit set. + + @param StatusCode The status code value to convert into a warning code. + StatusCode must be in the range 0x00000000..0x7FFFFFFF. + + @return The value specified by StatusCode with the highest bit set. + +**/ +#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode))) + +/** + Produces a RETURN_STATUS code with the highest bit clear. + + @param StatusCode The status code value to convert into a warning code. + StatusCode must be in the range 0x00000000..0x7FFFFFFF. + + @return The value specified by StatusCode with the highest bit clear. + +**/ +#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode)) + +/** + Returns TRUE if a specified RETURN_STATUS code is an error code. + + This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned. + + @param StatusCode The status code value to evaluate. + + @retval TRUE The high bit of StatusCode is set. + @retval FALSE The high bit of StatusCode is clear. + +**/ +#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0) + +/// +/// The operation completed successfully. +/// +#define RETURN_SUCCESS 0 + +/// +/// The image failed to load. +/// +#define RETURN_LOAD_ERROR ENCODE_ERROR (1) + +/// +/// The parameter was incorrect. +/// +#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2) + +/// +/// The operation is not supported. +/// +#define RETURN_UNSUPPORTED ENCODE_ERROR (3) + +/// +/// The buffer was not the proper size for the request. +/// +#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4) + +/// +/// The buffer was not large enough to hold the requested data. +/// The required buffer size is returned in the appropriate +/// parameter when this error occurs. +/// +#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5) + +/// +/// There is no data pending upon return. +/// +#define RETURN_NOT_READY ENCODE_ERROR (6) + +/// +/// The physical device reported an error while attempting the +/// operation. +/// +#define RETURN_DEVICE_ERROR ENCODE_ERROR (7) + +/// +/// The device can not be written to. +/// +#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8) + +/// +/// The resource has run out. +/// +#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9) + +/// +/// An inconsistency was detected on the file system causing the +/// operation to fail. +/// +#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10) + +/// +/// There is no more space on the file system. +/// +#define RETURN_VOLUME_FULL ENCODE_ERROR (11) + +/// +/// The device does not contain any medium to perform the +/// operation. +/// +#define RETURN_NO_MEDIA ENCODE_ERROR (12) + +/// +/// The medium in the device has changed since the last +/// access. +/// +#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13) + +/// +/// The item was not found. +/// +#define RETURN_NOT_FOUND ENCODE_ERROR (14) + +/// +/// Access was denied. +/// +#define RETURN_ACCESS_DENIED ENCODE_ERROR (15) + +/// +/// The server was not found or did not respond to the request. +/// +#define RETURN_NO_RESPONSE ENCODE_ERROR (16) + +/// +/// A mapping to the device does not exist. +/// +#define RETURN_NO_MAPPING ENCODE_ERROR (17) + +/// +/// A timeout time expired. +/// +#define RETURN_TIMEOUT ENCODE_ERROR (18) + +/// +/// The protocol has not been started. +/// +#define RETURN_NOT_STARTED ENCODE_ERROR (19) + +/// +/// The protocol has already been started. +/// +#define RETURN_ALREADY_STARTED ENCODE_ERROR (20) + +/// +/// The operation was aborted. +/// +#define RETURN_ABORTED ENCODE_ERROR (21) + +/// +/// An ICMP error occurred during the network operation. +/// +#define RETURN_ICMP_ERROR ENCODE_ERROR (22) + +/// +/// A TFTP error occurred during the network operation. +/// +#define RETURN_TFTP_ERROR ENCODE_ERROR (23) + +/// +/// A protocol error occurred during the network operation. +/// +#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24) + +/// +/// A function encountered an internal version that was +/// incompatible with a version requested by the caller. +/// +#define RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25) + +/// +/// The function was not performed due to a security violation. +/// +#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26) + +/// +/// A CRC error was detected. +/// +#define RETURN_CRC_ERROR ENCODE_ERROR (27) + +/// +/// The beginning or end of media was reached. +/// +#define RETURN_END_OF_MEDIA ENCODE_ERROR (28) + +/// +/// The end of the file was reached. +/// +#define RETURN_END_OF_FILE ENCODE_ERROR (31) + +/// +/// The language specified was invalid. +/// +#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32) + +/// +/// The security status of the data is unknown or compromised +/// and the data must be updated or replaced to restore a valid +/// security status. +/// +#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33) + +/// +/// A HTTP error occurred during the network operation. +/// +#define RETURN_HTTP_ERROR ENCODE_ERROR (35) + +/// +/// The string contained one or more characters that +/// the device could not render and were skipped. +/// +#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1) + +/// +/// The handle was closed, but the file was not deleted. +/// +#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2) + +/// +/// The handle was closed, but the data to the file was not +/// flushed properly. +/// +#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3) + +/// +/// The resulting buffer was too small, and the data was +/// truncated to the buffer size. +/// +#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4) + +/// +/// The data has not been updated within the timeframe set by +/// local policy for this type of data. +/// +#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5) + +/// +/// The resulting buffer contains UEFI-compliant file system. +/// +#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6) + + +/** + Returns a 16-bit signature built from 2 ASCII characters. + + This macro returns a 16-bit value built from the two ASCII characters specified + by A and B. + + @param A The first ASCII character. + @param B The second ASCII character. + + @return A 16-bit value built from the two ASCII characters specified by A and B. + +**/ +#define SIGNATURE_16(A, B) ((A) | (B << 8)) + +/** + Returns a 32-bit signature built from 4 ASCII characters. + + This macro returns a 32-bit value built from the four ASCII characters specified + by A, B, C, and D. + + @param A The first ASCII character. + @param B The second ASCII character. + @param C The third ASCII character. + @param D The fourth ASCII character. + + @return A 32-bit value built from the two ASCII characters specified by A, B, + C and D. + +**/ +#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16)) + +/** + Returns a 64-bit signature built from 8 ASCII characters. + + This macro returns a 64-bit value built from the eight ASCII characters specified + by A, B, C, D, E, F, G,and H. + + @param A The first ASCII character. + @param B The second ASCII character. + @param C The third ASCII character. + @param D The fourth ASCII character. + @param E The fifth ASCII character. + @param F The sixth ASCII character. + @param G The seventh ASCII character. + @param H The eighth ASCII character. + + @return A 64-bit value built from the two ASCII characters specified by A, B, + C, D, E, F, G and H. + +**/ +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) + +#if defined(_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC) + void * _ReturnAddress(void); + #pragma intrinsic(_ReturnAddress) + /** + Get the return address of the calling function. + + Based on intrinsic function _ReturnAddress that provides the address of + the instruction in the calling function that will be executed after + control returns to the caller. + + @param L Return Level. + + @return The return address of the calling function or 0 if L != 0. + + **/ + #define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0) +#elif defined (__GNUC__) || defined (__clang__) + /** + Get the return address of the calling function. + + Based on built-in Function __builtin_return_address that returns + the return address of the current function, or of one of its callers. + + @param L Return Level. + + @return The return address of the calling function. + + **/ + #define RETURN_ADDRESS(L) __builtin_return_address (L) +#else + /** + Get the return address of the calling function. + + @param L Return Level. + + @return 0 as compilers don't support this feature. + + **/ + #define RETURN_ADDRESS(L) ((VOID *) 0) +#endif + +/** + Return the number of elements in an array. + + @param Array An object of array type. Array is only used as an argument to + the sizeof operator, therefore Array is never evaluated. The + caller is responsible for ensuring that Array's type is not + incomplete; that is, Array must have known constant size. + + @return The number of elements in Array. The result has type UINTN. + +**/ +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0])) +#endif + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ebc/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ebc/ProcessorBind.h new file mode 100644 index 0000000000..f747e8da2c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ebc/ProcessorBind.h @@ -0,0 +1,156 @@ +/** @file + Processor or compiler specific defines and types for EBC. + + We currently only have one EBC compiler so there may be some Intel compiler + specific functions in this file. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_EBC + +// +// Native integer types +// + +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value. +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character. +/// +typedef char CHAR8; +/// +/// 2-byte signed value. +/// +typedef short INT16; +/// +/// 2-byte unsigned value. +/// +typedef unsigned short UINT16; +/// +/// 2-byte Character. Unless otherwise specified all strings are stored in the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. +/// +typedef unsigned short CHAR16; +/// +/// 4-byte signed value. +/// +typedef int INT32; +/// +/// 4-byte unsigned value. +/// +typedef unsigned int UINT32; +/// +/// 8-byte signed value. +/// +typedef __int64 INT64; +/// +/// 8-byte unsigned value. +/// +typedef unsigned __int64 UINT64; + +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// "long" type scales to the processor native size with EBC compiler +/// +typedef long INTN; +/// +/// The unsigned value of native width. (4 bytes on supported 32-bit processor instructions; +/// 8 bytes on supported 64-bit processor instructions) +/// "long" type scales to the processor native size with the EBC compiler. +/// +typedef unsigned long UINTN; + +/// +/// A value of native width with the highest bit set. +/// Scalable macro to set the most significant bit in a natural number. +/// +#define MAX_BIT ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1)))) +/// +/// A value of native width with the two highest bits set. +/// Scalable macro to set the most 2 significant bits in a natural number. +/// +#define MAX_2_BITS ((UINTN)(3ULL << (sizeof (INTN) * 8 - 2))) + +/// +/// Maximum legal EBC address +/// +#define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8))) + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages) +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + +/// +/// Maximum legal EBC INTN and UINTN values. +/// +#define MAX_UINTN ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8))) +#define MAX_INTN ((INTN)(~0ULL >> (65 - sizeof (INTN) * 8))) + +/// +/// Minimum legal EBC INTN value. +/// +#define MIN_INTN (((INTN)-MAX_INTN) - 1) + +/// +/// The stack alignment required for EBC +/// +#define CPU_STACK_ALIGNMENT sizeof(UINTN) + +/// +/// Page allocation granularity for EBC +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +/// +/// Modifier to ensure that all protocol member functions and EFI intrinsics +/// use the correct C calling convention. All protocol member functions and +/// EFI intrinsics are required to modify their member functions with EFIAPI. +/// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#else +#define EFIAPI +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On EBC architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Acpi.h new file mode 100644 index 0000000000..7aa5ab5a28 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Acpi.h @@ -0,0 +1,40 @@ +/** @file + GUIDs used for ACPI entries in the EFI system table + + These GUIDs point the ACPI tables as defined in the ACPI specifications. + ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the + ACPI 2.0 Table GUID and ACPI Table GUID. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.0 spec. + +**/ + +#ifndef __ACPI_GUID_H__ +#define __ACPI_GUID_H__ + +#define ACPI_TABLE_GUID \ + { \ + 0xeb9d2d30, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +#define EFI_ACPI_TABLE_GUID \ + { \ + 0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ + } + +#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID + +// +// ACPI 2.0 or newer tables should use EFI_ACPI_TABLE_GUID. +// +#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID + +extern EFI_GUID gEfiAcpiTableGuid; +extern EFI_GUID gEfiAcpi10TableGuid; +extern EFI_GUID gEfiAcpi20TableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Apriori.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Apriori.h new file mode 100644 index 0000000000..2a30fd52e2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Apriori.h @@ -0,0 +1,24 @@ +/** @file + GUID used as an FV filename for A Priori file. The A Priori file contains a + list of FV filenames that the DXE dispatcher will schedule reguardless of + the dependency grammar. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.0. + +**/ + +#ifndef __APRIORI_GUID_H__ +#define __APRIORI_GUID_H__ + +#define EFI_APRIORI_GUID \ + { \ + 0xfc510ee7, 0xffdc, 0x11d4, {0xbd, 0x41, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \ + } + +extern EFI_GUID gAprioriGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/AprioriFileName.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/AprioriFileName.h new file mode 100644 index 0000000000..ab34b17ea8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/AprioriFileName.h @@ -0,0 +1,38 @@ +/** @file + The GUID PEI_APRIORI_FILE_NAME_GUID definition is the file + name of the PEI a priori file that is stored in a firmware + volume. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_APRIORI_FILE_NAME_H__ +#define __PEI_APRIORI_FILE_NAME_H__ + +#define PEI_APRIORI_FILE_NAME_GUID \ + { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } } + + +/// +/// This file must be of type EFI_FV_FILETYPE_FREEFORM and must +/// contain a single section of type EFI_SECTION_RAW. For details on +/// firmware volumes, firmware file types, and firmware file section +/// types. +/// +typedef struct { + /// + /// An array of zero or more EFI_GUID type entries that match the file names of PEIM + /// modules in the same Firmware Volume. The maximum number of entries. + /// + EFI_GUID FileNamesWithinVolume[1]; +} PEI_APRIORI_FILE_CONTENTS; + +extern EFI_GUID gPeiAprioriFileNameGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Btt.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Btt.h new file mode 100644 index 0000000000..93a79782b5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Btt.h @@ -0,0 +1,222 @@ +/** @file + Block Translation Table (BTT) metadata layout definition. + + BTT is a layout and set of rules for doing block I/O that provide powerfail + write atomicity of a single block. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This metadata layout definition was introduced in UEFI Specification 2.7. + +**/ + +#ifndef _BTT_H_ +#define _BTT_H_ + +/// +/// The BTT layout and behavior is described by the GUID as below. +/// +#define EFI_BTT_ABSTRACTION_GUID \ + { \ + 0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 } \ + } + +// +// Alignment of all BTT structures +// +#define EFI_BTT_ALIGNMENT 4096 + +#define EFI_BTT_INFO_UNUSED_LEN 3968 + +#define EFI_BTT_INFO_BLOCK_SIG_LEN 16 + +/// +/// Indicate inconsistent metadata or lost metadata due to unrecoverable media errors. +/// +#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001 + +#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2 +#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0 + +/// +/// Block Translation Table (BTT) Info Block +/// +typedef struct _EFI_BTT_INFO_BLOCK { + /// + /// Signature of the BTT Index Block data structure. + /// Shall be "BTT_ARENA_INFO\0\0". + /// + CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN]; + + /// + /// UUID identifying this BTT instance. + /// + GUID Uuid; + + /// + /// UUID of containing namespace. + /// + GUID ParentUuid; + + /// + /// Attributes of this BTT Info Block. + /// + UINT32 Flags; + + /// + /// Major version number. Currently at version 2. + /// + UINT16 Major; + + /// + /// Minor version number. Currently at version 0. + /// + UINT16 Minor; + + /// + /// Advertised LBA size in bytes. I/O requests shall be in this size chunk. + /// + UINT32 ExternalLbaSize; + + /// + /// Advertised number of LBAs in this arena. + /// + UINT32 ExternalNLba; + + /// + /// Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512 bytes. + /// + UINT32 InternalLbaSize; + + /// + /// Number of internal blocks in the arena data area. + /// + UINT32 InternalNLba; + + /// + /// Number of free blocks maintained for writes to this arena. + /// + UINT32 NFree; + + /// + /// The size of this info block in bytes. + /// + UINT32 InfoSize; + + /// + /// Offset of next arena, relative to the beginning of this arena. + /// + UINT64 NextOff; + + /// + /// Offset of the data area for this arena, relative to the beginning of this arena. + /// + UINT64 DataOff; + + /// + /// Offset of the map for this arena, relative to the beginning of this arena. + /// + UINT64 MapOff; + + /// + /// Offset of the flog for this arena, relative to the beginning of this arena. + /// + UINT64 FlogOff; + + /// + /// Offset of the backup copy of this arena's info block, relative to the beginning of this arena. + /// + UINT64 InfoOff; + + /// + /// Shall be zero. + /// + CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN]; + + /// + /// 64-bit Fletcher64 checksum of all fields. + /// + UINT64 Checksum; +} EFI_BTT_INFO_BLOCK; + +/// +/// BTT Map entry maps an LBA that indexes into the arena, to its actual location. +/// +typedef struct _EFI_BTT_MAP_ENTRY { + /// + /// Post-map LBA number (block number in this arena's data area) + /// + UINT32 PostMapLba : 30; + + /// + /// When set and Zero is not set, reads on this block return an error. + /// When set and Zero is set, indicate a map entry in its normal, non-error state. + /// + UINT32 Error : 1; + + /// + /// When set and Error is not set, reads on this block return a full block of zeros. + /// When set and Error is set, indicate a map entry in its normal, non-error state. + /// + UINT32 Zero : 1; +} EFI_BTT_MAP_ENTRY; + +/// +/// Alignment of each flog structure +/// +#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64 + +/// +/// The BTT Flog is both a free list and a log. +/// The Flog size is determined by the EFI_BTT_INFO_BLOCK.NFree which determines how many of these flog +/// entries there are. +/// The Flog location is the highest aligned address in the arena after space for the backup info block. +/// +typedef struct _EFI_BTT_FLOG { + /// + /// Last pre-map LBA written using this flog entry. + /// + UINT32 Lba0; + + /// + /// Old post-map LBA. + /// + UINT32 OldMap0; + + /// + /// New post-map LBA. + /// + UINT32 NewMap0; + + /// + /// The Seq0 field in each flog entry is used to determine which set of fields is newer between the two sets + /// (Lba0, OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1). + /// + UINT32 Seq0; + + /// + /// Alternate lba entry. + /// + UINT32 Lba1; + + /// + /// Alternate old entry. + /// + UINT32 OldMap1; + + /// + /// Alternate new entry. + /// + UINT32 NewMap1; + + /// + /// Alternate Seq entry. + /// + UINT32 Seq1; +} EFI_BTT_FLOG; + +extern GUID gEfiBttAbstractionGuid; + +#endif //_BTT_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/CapsuleReport.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/CapsuleReport.h new file mode 100644 index 0000000000..8228f937d0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/CapsuleReport.h @@ -0,0 +1,128 @@ +/** @file + Guid & data structure used for Capsule process result variables + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.4 spec. + +**/ + + +#ifndef _CAPSULE_REPORT_GUID_H__ +#define _CAPSULE_REPORT_GUID_H__ + +// +// This is the GUID for capsule result variable. +// +#define EFI_CAPSULE_REPORT_GUID \ + { \ + 0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 } \ + } + + +typedef struct { + + /// + /// Size in bytes of the variable including any data beyond header as specified by CapsuleGuid + /// + UINT32 VariableTotalSize; + + /// + /// For alignment + /// + UINT32 Reserved; + + /// + /// Guid from EFI_CAPSULE_HEADER + /// + EFI_GUID CapsuleGuid; + + /// + /// Timestamp using system time when processing completed + /// + EFI_TIME CapsuleProcessed; + + /// + /// Result of the capsule processing. Exact interpretation of any error code may depend + /// upon type of capsule processed + /// + EFI_STATUS CapsuleStatus; +} EFI_CAPSULE_RESULT_VARIABLE_HEADER; + + +typedef struct { + + /// + /// Version of this structure, currently 0x00000001 + /// + UINT16 Version; + + /// + /// The index of the payload within the FMP capsule which was processed to generate this report + /// Starting from zero + /// + UINT8 PayloadIndex; + + /// + /// The UpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER + /// (after unsigned conversion from UINT8 to UINT16). + /// + UINT8 UpdateImageIndex; + + /// + /// The UpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER. + /// + EFI_GUID UpdateImageTypeId; + + /// + /// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed. + /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character + /// which is included in VariableTotalSize. + /// + /// CHAR16 CapsuleFileName[]; + /// + + /// + /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol + /// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped, + /// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize. + /// + /// CHAR16 CapsuleTarget[]; + /// +} EFI_CAPSULE_RESULT_VARIABLE_FMP; + +typedef struct { + + /// + /// Version of this structure, currently 0x00000001 + /// + UINT32 Version; + + /// + /// The unique identifier of the capsule whose processing result is recorded in this variable. + /// 0x00000000 - 0xEFFFFFFF - Implementation Reserved + /// 0xF0000000 - 0xFFFFFFFF - Specification Reserved + /// #define REDFISH_DEFINED_JSON_SCHEMA 0xF000000 + /// The JSON payload shall conform to a Redfish-defined JSON schema, see DMTF-Redfish + /// Specification. + /// + UINT32 CapsuleId; + + /// + /// The length of Resp in bytes. + /// + UINT32 RespLength; + + /// + /// Variable length buffer containing the replied JSON payload to the caller who delivered JSON + /// capsule to system. The definition of the JSON schema used in the replied payload is beyond + /// the scope of this specification. + /// + UINT8 Resp[]; + } EFI_CAPSULE_RESULT_VARIABLE_JSON; + +extern EFI_GUID gEfiCapsuleReportGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Cper.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Cper.h new file mode 100644 index 0000000000..06e06c4eab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Cper.h @@ -0,0 +1,1252 @@ +/** @file + GUIDs and definitions used for Common Platform Error Record. + + Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.7 Specification. + +**/ + +#ifndef __CPER_GUID_H__ +#define __CPER_GUID_H__ + +#pragma pack(1) + +#define EFI_ERROR_RECORD_SIGNATURE_START SIGNATURE_32('C', 'P', 'E', 'R') +#define EFI_ERROR_RECORD_SIGNATURE_END 0xFFFFFFFF + +#define EFI_ERROR_RECORD_REVISION 0x0101 + +/// +/// Error Severity in Error Record Header and Error Section Descriptor +///@{ +#define EFI_GENERIC_ERROR_RECOVERABLE 0x00000000 +#define EFI_GENERIC_ERROR_FATAL 0x00000001 +#define EFI_GENERIC_ERROR_CORRECTED 0x00000002 +#define EFI_GENERIC_ERROR_INFO 0x00000003 +///@} + +/// +/// The validation bit mask indicates the validity of the following fields +/// in Error Record Header. +///@{ +#define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0 +#define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1 +#define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2 +///@} + +/// +/// Timestamp is precise if this bit is set and correlates to the time of the +/// error event. +/// +#define EFI_ERROR_TIME_STAMP_PRECISE BIT0 + +/// +/// The timestamp correlates to the time when the error information was collected +/// by the system software and may not necessarily represent the time of the error +/// event. The timestamp contains the local time in BCD format. +/// +typedef struct { + UINT8 Seconds; + UINT8 Minutes; + UINT8 Hours; + UINT8 Flag; + UINT8 Day; + UINT8 Month; + UINT8 Year; + UINT8 Century; +} EFI_ERROR_TIME_STAMP; + +/// +/// GUID value indicating the record association with an error event notification type. +///@{ +#define EFI_EVENT_NOTIFICATION_TYEP_CMC_GUID \ + { \ + 0x2DCE8BB1, 0xBDD7, 0x450e, { 0xB9, 0xAD, 0x9C, 0xF4, 0xEB, 0xD4, 0xF8, 0x90 } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_CPE_GUID \ + { \ + 0x4E292F96, 0xD843, 0x4a55, { 0xA8, 0xC2, 0xD4, 0x81, 0xF2, 0x7E, 0xBE, 0xEE } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_MCE_GUID \ + { \ + 0xE8F56FFE, 0x919C, 0x4cc5, { 0xBA, 0x88, 0x65, 0xAB, 0xE1, 0x49, 0x13, 0xBB } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_PCIE_GUID \ + { \ + 0xCF93C01F, 0x1A16, 0x4dfc, { 0xB8, 0xBC, 0x9C, 0x4D, 0xAF, 0x67, 0xC1, 0x04 } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_INIT_GUID \ + { \ + 0xCC5263E8, 0x9308, 0x454a, { 0x89, 0xD0, 0x34, 0x0B, 0xD3, 0x9B, 0xC9, 0x8E } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_NMI_GUID \ + { \ + 0x5BAD89FF, 0xB7E6, 0x42c9, { 0x81, 0x4A, 0xCF, 0x24, 0x85, 0xD6, 0xE9, 0x8A } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_BOOT_GUID \ + { \ + 0x3D61A466, 0xAB40, 0x409a, { 0xA6, 0x98, 0xF3, 0x62, 0xD4, 0x64, 0xB3, 0x8F } \ + } +#define EFI_EVENT_NOTIFICATION_TYEP_DMAR_GUID \ + { \ + 0x667DD791, 0xC6B3, 0x4c27, { 0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41 } \ + } +#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEA \ + { \ + 0x9A78788A, 0xBBE8, 0x11E4, { 0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0 } \ + } +#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEI \ + { \ + 0x5C284C81, 0xB0AE, 0x4E87, { 0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23 } \ + } +#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_PEI \ + { \ + 0x09A9D5AC, 0x5204, 0x4214, { 0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD } \ + } +///@} + +/// +/// Error Record Header Flags +///@{ +#define EFI_HW_ERROR_FLAGS_RECOVERED 0x00000001 +#define EFI_HW_ERROR_FLAGS_PREVERR 0x00000002 +#define EFI_HW_ERROR_FLAGS_SIMULATED 0x00000004 +///@} + +/// +/// Common error record header +/// +typedef struct { + UINT32 SignatureStart; + UINT16 Revision; + UINT32 SignatureEnd; + UINT16 SectionCount; + UINT32 ErrorSeverity; + UINT32 ValidationBits; + UINT32 RecordLength; + EFI_ERROR_TIME_STAMP TimeStamp; + EFI_GUID PlatformID; + EFI_GUID PartitionID; + EFI_GUID CreatorID; + EFI_GUID NotificationType; + UINT64 RecordID; + UINT32 Flags; + UINT64 PersistenceInfo; + UINT8 Resv1[12]; + /// + /// An array of SectionCount descriptors for the associated + /// sections. The number of valid sections is equivalent to the + /// SectionCount. The buffer size of the record may include + /// more space to dynamically add additional Section + /// Descriptors to the error record. + /// +} EFI_COMMON_ERROR_RECORD_HEADER; + +#define EFI_ERROR_SECTION_REVISION 0x0100 + +/// +/// Validity Fields in Error Section Descriptor. +/// +#define EFI_ERROR_SECTION_FRU_ID_VALID BIT0 +#define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1 + +/// +/// Flag field contains information that describes the error section +/// in Error Section Descriptor. +/// +#define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0 +#define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1 +#define EFI_ERROR_SECTION_FLAGS_RESET BIT2 +#define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3 +#define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE BIT4 +#define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR BIT5 + +/// +/// Error Sectition Type GUIDs in Error Section Descriptor +///@{ +#define EFI_ERROR_SECTION_PROCESSOR_GENERIC_GUID \ + { \ + 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb } \ + } +#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_GUID \ + { \ + 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d } \ + } +#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_IA32X64_GUID \ + { \ + 0xdc3ea0b0, 0xa144, 0x4797, { 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d } \ + } +#define EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_ARM_GUID \ + { \ + 0xe19e3d16, 0xbc11, 0x11e4, { 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 } \ + } +#define EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID \ + { \ + 0xa5bc1114, 0x6f64, 0x4ede, { 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 } \ + } +#define EFI_ERROR_SECTION_PLATFORM_MEMORY2_GUID \ + { \ + 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 } \ + } +#define EFI_ERROR_SECTION_PCIE_GUID \ + { \ + 0xd995e954, 0xbbc1, 0x430f, { 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 } \ + } +#define EFI_ERROR_SECTION_FW_ERROR_RECORD_GUID \ + { \ + 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed } \ + } +#define EFI_ERROR_SECTION_PCI_PCIX_BUS_GUID \ + { \ + 0xc5753963, 0x3b84, 0x4095, { 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd } \ + } +#define EFI_ERROR_SECTION_PCI_DEVICE_GUID \ + { \ + 0xeb5e4685, 0xca66, 0x4769, { 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 } \ + } +#define EFI_ERROR_SECTION_DMAR_GENERIC_GUID \ + { \ + 0x5b51fef7, 0xc79d, 0x4434, { 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64 } \ + } +#define EFI_ERROR_SECTION_DIRECTED_IO_DMAR_GUID \ + { \ + 0x71761d37, 0x32b2, 0x45cd, { 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf } \ + } +#define EFI_ERROR_SECTION_IOMMU_DMAR_GUID \ + { \ + 0x036f84e1, 0x7f37, 0x428c, { 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec } \ + } +///@} + +/// +/// Error Section Descriptor +/// +typedef struct { + UINT32 SectionOffset; + UINT32 SectionLength; + UINT16 Revision; + UINT8 SecValidMask; + UINT8 Resv1; + UINT32 SectionFlags; + EFI_GUID SectionType; + EFI_GUID FruId; + UINT32 Severity; + CHAR8 FruString[20]; +} EFI_ERROR_SECTION_DESCRIPTOR; + +/// +/// The validation bit mask indicates whether or not each of the following fields are +/// valid in Proessor Generic Error section. +///@{ +#define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0 +#define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1 +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID BIT2 +#define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3 +#define EFI_GENERIC_ERROR_PROC_FLAGS_VALID BIT4 +#define EFI_GENERIC_ERROR_PROC_LEVEL_VALID BIT5 +#define EFI_GENERIC_ERROR_PROC_VERSION_VALID BIT6 +#define EFI_GENERIC_ERROR_PROC_BRAND_VALID BIT7 +#define EFI_GENERIC_ERROR_PROC_ID_VALID BIT8 +#define EFI_GENERIC_ERROR_PROC_TARGET_ADDR_VALID BIT9 +#define EFI_GENERIC_ERROR_PROC_REQUESTER_ID_VALID BIT10 +#define EFI_GENERIC_ERROR_PROC_RESPONDER_ID_VALID BIT11 +#define EFI_GENERIC_ERROR_PROC_INST_IP_VALID BIT12 +///@} + +/// +/// The type of the processor architecture in Proessor Generic Error section. +///@{ +#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00 +#define EFI_GENERIC_ERROR_PROC_TYPE_IA64 0x01 +#define EFI_GENERIC_ERROR_PROC_TYPE_ARM 0x02 +///@} + +/// +/// The type of the instruction set executing when the error occurred in Proessor +/// Generic Error section. +///@{ +#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00 +#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01 +#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02 +#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03 +#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04 +///@} + +/// +/// The type of error that occurred in Proessor Generic Error section. +///@{ +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_UNKNOWN 0x00 +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_CACHE 0x01 +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_TLB 0x02 +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_BUS 0x04 +#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_MICRO_ARCH 0x08 +///@} + +/// +/// The type of operation in Proessor Generic Error section. +///@{ +#define EFI_GENERIC_ERROR_PROC_OPERATION_GENERIC 0x00 +#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_READ 0x01 +#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_WRITE 0x02 +#define EFI_GENERIC_ERROR_PROC_OPERATION_INSTRUCTION_EXEC 0x03 +///@} + +/// +/// Flags bit mask indicates additional information about the error in Proessor Generic +/// Error section +///@{ +#define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0 +#define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1 +#define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW BIT2 +#define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3 +///@} + +/// +/// Processor Generic Error Section +/// describes processor reported hardware errors for logical processors in the system. +/// +typedef struct { + UINT64 ValidFields; + UINT8 Type; + UINT8 Isa; + UINT8 ErrorType; + UINT8 Operation; + UINT8 Flags; + UINT8 Level; + UINT16 Resv1; + UINT64 VersionInfo; + CHAR8 BrandString[128]; + UINT64 ApicId; + UINT64 TargetAddr; + UINT64 RequestorId; + UINT64 ResponderId; + UINT64 InstructionIP; +} EFI_PROCESSOR_GENERIC_ERROR_DATA; + + +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +/// +/// IA32 and x64 Specific definitions. +/// + +/// +/// GUID value indicating the type of Processor Error Information structure +/// in IA32/X64 Processor Error Information Structure. +///@{ +#define EFI_IA32_X64_ERROR_TYPE_CACHE_CHECK_GUID \ + { \ + 0xA55701F5, 0xE3EF, 0x43de, {0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C } \ + } +#define EFI_IA32_X64_ERROR_TYPE_TLB_CHECK_GUID \ + { \ + 0xFC06B535, 0x5E1F, 0x4562, {0x9F, 0x25, 0x0A, 0x3B, 0x9A, 0xDB, 0x63, 0xC3 } \ + } +#define EFI_IA32_X64_ERROR_TYPE_BUS_CHECK_GUID \ + { \ + 0x1CF3F8B3, 0xC5B1, 0x49a2, {0xAA, 0x59, 0x5E, 0xEF, 0x92, 0xFF, 0xA6, 0x3C } \ + } +#define EFI_IA32_X64_ERROR_TYPE_MS_CHECK_GUID \ + { \ + 0x48AB7F57, 0xDC34, 0x4f6c, {0xA7, 0xD3, 0xB0, 0xB5, 0xB0, 0xA7, 0x43, 0x14 } \ + } +///@} + +/// +/// The validation bit mask indicates which fields in the IA32/X64 Processor +/// Error Record structure are valid. +///@{ +#define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID BIT0 +#define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1 +///@} + +/// +/// IA32/X64 Processor Error Record +/// +typedef struct { + UINT64 ValidFields; + UINT64 ApicId; + UINT8 CpuIdInfo[48]; +} EFI_IA32_X64_PROCESSOR_ERROR_RECORD; + +/// +/// The validation bit mask indicates which fields in the Cache Check structure +/// are valid. +///@{ +#define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0 +#define EFI_CACHE_CHECK_OPERATION_VALID BIT1 +#define EFI_CACHE_CHECK_LEVEL_VALID BIT2 +#define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3 +#define EFI_CACHE_CHECK_UNCORRECTED_VALID BIT4 +#define EFI_CACHE_CHECK_PRECISE_IP_VALID BIT5 +#define EFI_CACHE_CHECK_RESTARTABLE_VALID BIT6 +#define EFI_CACHE_CHECK_OVERFLOW_VALID BIT7 +///@} + +/// +/// Type of cache error in the Cache Check structure +///@{ +#define EFI_CACHE_CHECK_ERROR_TYPE_INSTRUCTION 0 +#define EFI_CACHE_CHECK_ERROR_TYPE_DATA_ACCESS 1 +#define EFI_CACHE_CHECK_ERROR_TYPE_GENERIC 2 +///@} + +/// +/// Type of cache operation that caused the error in the Cache +/// Check structure +///@{ +#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC 0 +#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_READ 1 +#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_WRITE 2 +#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_READ 3 +#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_WRITE 4 +#define EFI_CACHE_CHECK_OPERATION_TYPE_INSTRUCTION_FETCH 5 +#define EFI_CACHE_CHECK_OPERATION_TYPE_PREFETCH 6 +#define EFI_CACHE_CHECK_OPERATION_TYPE_EVICTION 7 +#define EFI_CACHE_CHECK_OPERATION_TYPE_SNOOP 8 +///@} + +/// +/// IA32/X64 Cache Check Structure +/// +typedef struct { + UINT64 ValidFields:16; + UINT64 TransactionType:2; + UINT64 Operation:4; + UINT64 Level:3; + UINT64 ContextCorrupt:1; + UINT64 ErrorUncorrected:1; + UINT64 PreciseIp:1; + UINT64 RestartableIp:1; + UINT64 Overflow:1; + UINT64 Resv1:34; +} EFI_IA32_X64_CACHE_CHECK_INFO; + +/// +/// The validation bit mask indicates which fields in the TLB Check structure +/// are valid. +///@{ +#define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0 +#define EFI_TLB_CHECK_OPERATION_VALID BIT1 +#define EFI_TLB_CHECK_LEVEL_VALID BIT2 +#define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3 +#define EFI_TLB_CHECK_UNCORRECTED_VALID BIT4 +#define EFI_TLB_CHECK_PRECISE_IP_VALID BIT5 +#define EFI_TLB_CHECK_RESTARTABLE_VALID BIT6 +#define EFI_TLB_CHECK_OVERFLOW_VALID BIT7 +///@} + +/// +/// Type of cache error in the TLB Check structure +///@{ +#define EFI_TLB_CHECK_ERROR_TYPE_INSTRUCTION 0 +#define EFI_TLB_CHECK_ERROR_TYPE_DATA_ACCESS 1 +#define EFI_TLB_CHECK_ERROR_TYPE_GENERIC 2 +///@} + +/// +/// Type of cache operation that caused the error in the TLB +/// Check structure +///@{ +#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC 0 +#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_READ 1 +#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_WRITE 2 +#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_READ 3 +#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_WRITE 4 +#define EFI_TLB_CHECK_OPERATION_TYPE_INST_FETCH 5 +#define EFI_TLB_CHECK_OPERATION_TYPE_PREFETCH 6 +///@} + +/// +/// IA32/X64 TLB Check Structure +/// +typedef struct { + UINT64 ValidFields:16; + UINT64 TransactionType:2; + UINT64 Operation:4; + UINT64 Level:3; + UINT64 ContextCorrupt:1; + UINT64 ErrorUncorrected:1; + UINT64 PreciseIp:1; + UINT64 RestartableIp:1; + UINT64 Overflow:1; + UINT64 Resv1:34; +} EFI_IA32_X64_TLB_CHECK_INFO; + +/// +/// The validation bit mask indicates which fields in the MS Check structure +/// are valid. +///@{ +#define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0 +#define EFI_BUS_CHECK_OPERATION_VALID BIT1 +#define EFI_BUS_CHECK_LEVEL_VALID BIT2 +#define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3 +#define EFI_BUS_CHECK_UNCORRECTED_VALID BIT4 +#define EFI_BUS_CHECK_PRECISE_IP_VALID BIT5 +#define EFI_BUS_CHECK_RESTARTABLE_VALID BIT6 +#define EFI_BUS_CHECK_OVERFLOW_VALID BIT7 +#define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8 +#define EFI_BUS_CHECK_TIME_OUT_VALID BIT9 +#define EFI_BUS_CHECK_ADDRESS_SPACE_VALID BIT10 +///@} + +/// +/// Type of cache error in the Bus Check structure +///@{ +#define EFI_BUS_CHECK_ERROR_TYPE_INSTRUCTION 0 +#define EFI_BUS_CHECK_ERROR_TYPE_DATA_ACCESS 1 +#define EFI_BUS_CHECK_ERROR_TYPE_GENERIC 2 +///@} + +/// +/// Type of cache operation that caused the error in the Bus +/// Check structure +///@{ +#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC 0 +#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_READ 1 +#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_WRITE 2 +#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_READ 3 +#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_WRITE 4 +#define EFI_BUS_CHECK_OPERATION_TYPE_INST_FETCH 5 +#define EFI_BUS_CHECK_OPERATION_TYPE_PREFETCH 6 +///@} + +/// +/// Type of Participation +///@{ +#define EFI_BUS_CHECK_PARTICIPATION_TYPE_REQUEST 0 +#define EFI_BUS_CHECK_PARTICIPATION_TYPE_RESPONDED 1 +#define EFI_BUS_CHECK_PARTICIPATION_TYPE_OBSERVED 2 +#define EFI_BUS_CHECK_PARTICIPATION_TYPE_GENERIC 3 +///@} + +/// +/// Type of Address Space +///@{ +#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_MEMORY 0 +#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_RESERVED 1 +#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_IO 2 +#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_OTHER 3 +///@} + +/// +/// IA32/X64 Bus Check Structure +/// +typedef struct { + UINT64 ValidFields:16; + UINT64 TransactionType:2; + UINT64 Operation:4; + UINT64 Level:3; + UINT64 ContextCorrupt:1; + UINT64 ErrorUncorrected:1; + UINT64 PreciseIp:1; + UINT64 RestartableIp:1; + UINT64 Overflow:1; + UINT64 ParticipationType:2; + UINT64 TimeOut:1; + UINT64 AddressSpace:2; + UINT64 Resv1:29; +} EFI_IA32_X64_BUS_CHECK_INFO; + +/// +/// The validation bit mask indicates which fields in the MS Check structure +/// are valid. +///@{ +#define EFI_MS_CHECK_ERROR_TYPE_VALID BIT0 +#define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1 +#define EFI_MS_CHECK_UNCORRECTED_VALID BIT2 +#define EFI_MS_CHECK_PRECISE_IP_VALID BIT3 +#define EFI_MS_CHECK_RESTARTABLE_VALID BIT4 +#define EFI_MS_CHECK_OVERFLOW_VALID BIT5 +///@} + +/// +/// Error type identifies the operation that caused the error. +///@{ +#define EFI_MS_CHECK_ERROR_TYPE_NO 0 +#define EFI_MS_CHECK_ERROR_TYPE_UNCLASSIFIED 1 +#define EFI_MS_CHECK_ERROR_TYPE_MICROCODE_PARITY 2 +#define EFI_MS_CHECK_ERROR_TYPE_EXTERNAL 3 +#define EFI_MS_CHECK_ERROR_TYPE_FRC 4 +#define EFI_MS_CHECK_ERROR_TYPE_INTERNAL_UNCLASSIFIED 5 +///@} + +/// +/// IA32/X64 MS Check Field Description +/// +typedef struct { + UINT64 ValidFields:16; + UINT64 ErrorType:3; + UINT64 ContextCorrupt:1; + UINT64 ErrorUncorrected:1; + UINT64 PreciseIp:1; + UINT64 RestartableIp:1; + UINT64 Overflow:1; + UINT64 Resv1:40; +} EFI_IA32_X64_MS_CHECK_INFO; + +/// +/// IA32/X64 Check Information Item +/// +typedef union { + EFI_IA32_X64_CACHE_CHECK_INFO CacheCheck; + EFI_IA32_X64_TLB_CHECK_INFO TlbCheck; + EFI_IA32_X64_BUS_CHECK_INFO BusCheck; + EFI_IA32_X64_MS_CHECK_INFO MsCheck; + UINT64 Data64; +} EFI_IA32_X64_CHECK_INFO_ITEM; + +/// +/// The validation bit mask indicates which fields in the IA32/X64 Processor Error +/// Information Structure are valid. +///@{ +#define EFI_IA32_X64_ERROR_PROC_CHECK_INFO_VALID BIT0 +#define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID BIT1 +#define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2 +#define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3 +#define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID BIT4 +///@} + +/// +/// IA32/X64 Processor Error Information Structure +/// +typedef struct { + EFI_GUID ErrorType; + UINT64 ValidFields; + EFI_IA32_X64_CHECK_INFO_ITEM CheckInfo; + UINT64 TargetId; + UINT64 RequestorId; + UINT64 ResponderId; + UINT64 InstructionIP; +} EFI_IA32_X64_PROCESS_ERROR_INFO; + +/// +/// IA32/X64 Processor Context Information Structure +/// +typedef struct { + UINT16 RegisterType; + UINT16 ArraySize; + UINT32 MsrAddress; + UINT64 MmRegisterAddress; + // + // This field will provide the contents of the actual registers or raw data. + // The number of Registers or size of the raw data reported is determined + // by (Array Size / 8) or otherwise specified by the context structure type + // definition. + // +} EFI_IA32_X64_PROCESSOR_CONTEXT_INFO; + +/// +/// Register Context Type +///@{ +#define EFI_REG_CONTEXT_TYPE_UNCLASSIFIED 0x0000 +#define EFI_REG_CONTEXT_TYPE_MSR 0x0001 +#define EFI_REG_CONTEXT_TYPE_IA32 0x0002 +#define EFI_REG_CONTEXT_TYPE_X64 0x0003 +#define EFI_REG_CONTEXT_TYPE_FXSAVE 0x0004 +#define EFI_REG_CONTEXT_TYPE_DR_IA32 0x0005 +#define EFI_REG_CONTEXT_TYPE_DR_X64 0x0006 +#define EFI_REG_CONTEXT_TYPE_MEM_MAP 0x0007 +///@} + +/// +/// IA32 Register State +/// +typedef struct { + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + UINT32 Esi; + UINT32 Edi; + UINT32 Ebp; + UINT32 Esp; + UINT16 Cs; + UINT16 Ds; + UINT16 Ss; + UINT16 Es; + UINT16 Fs; + UINT16 Gs; + UINT32 Eflags; + UINT32 Eip; + UINT32 Cr0; + UINT32 Cr1; + UINT32 Cr2; + UINT32 Cr3; + UINT32 Cr4; + UINT32 Gdtr[2]; + UINT32 Idtr[2]; + UINT16 Ldtr; + UINT16 Tr; +} EFI_CONTEXT_IA32_REGISTER_STATE; + +/// +/// X64 Register State +/// +typedef struct { + UINT64 Rax; + UINT64 Rbx; + UINT64 Rcx; + UINT64 Rdx; + UINT64 Rsi; + UINT64 Rdi; + UINT64 Rbp; + UINT64 Rsp; + UINT64 R8; + UINT64 R9; + UINT64 R10; + UINT64 R11; + UINT64 R12; + UINT64 R13; + UINT64 R14; + UINT64 R15; + UINT16 Cs; + UINT16 Ds; + UINT16 Ss; + UINT16 Es; + UINT16 Fs; + UINT16 Gs; + UINT32 Resv1; + UINT64 Rflags; + UINT64 Rip; + UINT64 Cr0; + UINT64 Cr1; + UINT64 Cr2; + UINT64 Cr3; + UINT64 Cr4; + UINT64 Gdtr[2]; + UINT64 Idtr[2]; + UINT16 Ldtr; + UINT16 Tr; +} EFI_CONTEXT_X64_REGISTER_STATE; + +/// +/// The validation bit mask indicates each of the following field is in IA32/X64 +/// Processor Error Section. +/// +typedef struct { + UINT64 ApicIdValid:1; + UINT64 CpuIdInforValid:1; + UINT64 ErrorInfoNum:6; + UINT64 ContextNum:6; + UINT64 Resv1:50; +} EFI_IA32_X64_VALID_BITS; + +#endif + +/// +/// Error Status Fields +/// +typedef struct { + UINT64 Resv1:8; + UINT64 Type:8; + UINT64 AddressSignal:1; ///< Error in Address signals or in Address portion of transaction + UINT64 ControlSignal:1; ///< Error in Control signals or in Control portion of transaction + UINT64 DataSignal:1; ///< Error in Data signals or in Data portion of transaction + UINT64 DetectedByResponder:1; ///< Error detected by responder + UINT64 DetectedByRequester:1; ///< Error detected by requestor + UINT64 FirstError:1; ///< First Error in the sequence - option field + UINT64 OverflowNotLogged:1; ///< Additional errors were not logged due to lack of resources + UINT64 Resv2:41; +} EFI_GENERIC_ERROR_STATUS; + +/// +/// Error Type +/// +typedef enum { + /// + /// General Internal errors + /// + ErrorInternal = 1, + ErrorBus = 16, + /// + /// Component Internal errors + /// + ErrorMemStorage = 4, // Error in memory device + ErrorTlbStorage = 5, // TLB error in cache + ErrorCacheStorage = 6, + ErrorFunctionalUnit = 7, + ErrorSelftest = 8, + ErrorOverflow = 9, + /// + /// Bus internal errors + /// + ErrorVirtualMap = 17, + ErrorAccessInvalid = 18, // Improper access + ErrorUnimplAccess = 19, // Unimplemented memory access + ErrorLossOfLockstep = 20, + ErrorResponseInvalid= 21, // Response not associated with request + ErrorParity = 22, + ErrorProtocol = 23, + ErrorPath = 24, // Detected path error + ErrorTimeout = 25, // Bus timeout + ErrorPoisoned = 26 // Read data poisoned +} EFI_GENERIC_ERROR_STATUS_ERROR_TYPE; + +/// +/// Validation bit mask indicates which fields in the memory error record are valid +/// in Memory Error section +///@{ +#define EFI_PLATFORM_MEMORY_ERROR_STATUS_VALID BIT0 +#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID BIT1 +#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID BIT2 +#define EFI_PLATFORM_MEMORY_NODE_VALID BIT3 +#define EFI_PLATFORM_MEMORY_CARD_VALID BIT4 +#define EFI_PLATFORM_MEMORY_MODULE_VALID BIT5 +#define EFI_PLATFORM_MEMORY_BANK_VALID BIT6 +#define EFI_PLATFORM_MEMORY_DEVICE_VALID BIT7 +#define EFI_PLATFORM_MEMORY_ROW_VALID BIT8 +#define EFI_PLATFORM_MEMORY_COLUMN_VALID BIT9 +#define EFI_PLATFORM_MEMORY_BIT_POS_VALID BIT10 +#define EFI_PLATFORM_MEMORY_REQUESTOR_ID_VALID BIT11 +#define EFI_PLATFORM_MEMORY_RESPONDER_ID_VALID BIT12 +#define EFI_PLATFORM_MEMORY_TARGET_ID_VALID BIT13 +#define EFI_PLATFORM_MEMORY_ERROR_TYPE_VALID BIT14 +#define EFI_PLATFORM_MEMORY_ERROR_RANK_NUM_VALID BIT15 +#define EFI_PLATFORM_MEMORY_ERROR_CARD_HANDLE_VALID BIT16 +#define EFI_PLATFORM_MEMORY_ERROR_MODULE_HANDLE_VALID BIT17 +#define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18 +#define EFI_PLATFORM_MEMORY_ERROR_BANK_GROUP_VALID BIT19 +#define EFI_PLATFORM_MEMORY_ERROR_BANK_ADDRESS_VALID BIT20 +#define EFI_PLATFORM_MEMORY_ERROR_CHIP_IDENTIFICATION_VALID BIT21 +///@} + +/// +/// Memory Error Type identifies the type of error that occurred in Memory +/// Error section +///@{ +#define EFI_PLATFORM_MEMORY_ERROR_UNKNOWN 0x00 +#define EFI_PLATFORM_MEMORY_ERROR_NONE 0x01 +#define EFI_PLATFORM_MEMORY_ERROR_SINGLEBIT_ECC 0x02 +#define EFI_PLATFORM_MEMORY_ERROR_MLTIBIT_ECC 0x03 +#define EFI_PLATFORM_MEMORY_ERROR_SINGLESYMBOLS_CHIPKILL 0x04 +#define EFI_PLATFORM_MEMORY_ERROR_MULTISYMBOL_CHIPKILL 0x05 +#define EFI_PLATFORM_MEMORY_ERROR_MATER_ABORT 0x06 +#define EFI_PLATFORM_MEMORY_ERROR_TARGET_ABORT 0x07 +#define EFI_PLATFORM_MEMORY_ERROR_PARITY 0x08 +#define EFI_PLATFORM_MEMORY_ERROR_WDT 0x09 +#define EFI_PLATFORM_MEMORY_ERROR_INVALID_ADDRESS 0x0A +#define EFI_PLATFORM_MEMORY_ERROR_MIRROR_FAILED 0x0B +#define EFI_PLATFORM_MEMORY_ERROR_SPARING 0x0C +#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_CORRECTED 0x0D +#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_UNCORRECTED 0x0E +#define EFI_PLATFORM_MEMORY_ERROR_MEMORY_MAP_EVENT 0x0F +///@} + +/// +/// Memory Error Section +/// +typedef struct { + UINT64 ValidFields; + EFI_GENERIC_ERROR_STATUS ErrorStatus; + UINT64 PhysicalAddress; // Error physical address + UINT64 PhysicalAddressMask; // Grnaularity + UINT16 Node; // Node # + UINT16 Card; + UINT16 ModuleRank; // Module or Rank# + UINT16 Bank; + UINT16 Device; + UINT16 Row; + UINT16 Column; + UINT16 BitPosition; + UINT64 RequestorId; + UINT64 ResponderId; + UINT64 TargetId; + UINT8 ErrorType; + UINT8 Extended; + UINT16 RankNum; + UINT16 CardHandle; + UINT16 ModuleHandle; +} EFI_PLATFORM_MEMORY_ERROR_DATA; + +/// +/// Validation bit mask indicates which fields in the memory error record 2 are valid +/// in Memory Error section 2 +///@{ +#define EFI_PLATFORM_MEMORY2_ERROR_STATUS_VALID BIT0 +#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_VALID BIT1 +#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_MASK_VALID BIT2 +#define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3 +#define EFI_PLATFORM_MEMORY2_CARD_VALID BIT4 +#define EFI_PLATFORM_MEMORY2_MODULE_VALID BIT5 +#define EFI_PLATFORM_MEMORY2_BANK_VALID BIT6 +#define EFI_PLATFORM_MEMORY2_DEVICE_VALID BIT7 +#define EFI_PLATFORM_MEMORY2_ROW_VALID BIT8 +#define EFI_PLATFORM_MEMORY2_COLUMN_VALID BIT9 +#define EFI_PLATFORM_MEMORY2_RANK_VALID BIT10 +#define EFI_PLATFORM_MEMORY2_BIT_POS_VALID BIT11 +#define EFI_PLATFORM_MEMORY2_CHIP_ID_VALID BIT12 +#define EFI_PLATFORM_MEMORY2_MEMORY_ERROR_TYPE_VALID BIT13 +#define EFI_PLATFORM_MEMORY2_STATUS_VALID BIT14 +#define EFI_PLATFORM_MEMORY2_REQUESTOR_ID_VALID BIT15 +#define EFI_PLATFORM_MEMORY2_RESPONDER_ID_VALID BIT16 +#define EFI_PLATFORM_MEMORY2_TARGET_ID_VALID BIT17 +#define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID BIT18 +#define EFI_PLATFORM_MEMORY2_MODULE_HANDLE_VALID BIT19 +#define EFI_PLATFORM_MEMORY2_BANK_GROUP_VALID BIT20 +#define EFI_PLATFORM_MEMORY2_BANK_ADDRESS_VALID BIT21 +///@} + +/// +/// Memory Error Type identifies the type of error that occurred in Memory +/// Error section 2 +///@{ +#define EFI_PLATFORM_MEMORY2_ERROR_UNKNOWN 0x00 +#define EFI_PLATFORM_MEMORY2_ERROR_NONE 0x01 +#define EFI_PLATFORM_MEMORY2_ERROR_SINGLEBIT_ECC 0x02 +#define EFI_PLATFORM_MEMORY2_ERROR_MLTIBIT_ECC 0x03 +#define EFI_PLATFORM_MEMORY2_ERROR_SINGLESYMBOL_CHIPKILL 0x04 +#define EFI_PLATFORM_MEMORY2_ERROR_MULTISYMBOL_CHIPKILL 0x05 +#define EFI_PLATFORM_MEMORY2_ERROR_MASTER_ABORT 0x06 +#define EFI_PLATFORM_MEMORY2_ERROR_TARGET_ABORT 0x07 +#define EFI_PLATFORM_MEMORY2_ERROR_PARITY 0x08 +#define EFI_PLATFORM_MEMORY2_ERROR_WDT 0x09 +#define EFI_PLATFORM_MEMORY2_ERROR_INVALID_ADDRESS 0x0A +#define EFI_PLATFORM_MEMORY2_ERROR_MIRROR_BROKEN 0x0B +#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_SPARING 0x0C +#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_CORRECTED 0x0D +#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_UNCORRECTED 0x0E +#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_MAP_EVENT 0x0F +///@} + +/// +/// Memory Error Section 2 +/// +typedef struct { + UINT64 ValidFields; + EFI_GENERIC_ERROR_STATUS ErrorStatus; + UINT64 PhysicalAddress; // Error physical address + UINT64 PhysicalAddressMask; // Grnaularity + UINT16 Node; // Node # + UINT16 Card; + UINT16 Module; // Module or Rank# + UINT16 Bank; + UINT32 Device; + UINT32 Row; + UINT32 Column; + UINT32 Rank; + UINT32 BitPosition; + UINT8 ChipId; + UINT8 MemErrorType; + UINT8 Status; + UINT8 Reserved; + UINT64 RequestorId; + UINT64 ResponderId; + UINT64 TargetId; + UINT32 CardHandle; + UINT32 ModuleHandle; +} EFI_PLATFORM_MEMORY2_ERROR_DATA; + +/// +/// Validation bits mask indicates which of the following fields is valid +/// in PCI Express Error Record. +///@{ +#define EFI_PCIE_ERROR_PORT_TYPE_VALID BIT0 +#define EFI_PCIE_ERROR_VERSION_VALID BIT1 +#define EFI_PCIE_ERROR_COMMAND_STATUS_VALID BIT2 +#define EFI_PCIE_ERROR_DEVICE_ID_VALID BIT3 +#define EFI_PCIE_ERROR_SERIAL_NO_VALID BIT4 +#define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID BIT5 +#define EFI_PCIE_ERROR_CAPABILITY_INFO_VALID BIT6 +#define EFI_PCIE_ERROR_AER_INFO_VALID BIT7 +///@} + +/// +/// PCIe Device/Port Type as defined in the PCI Express capabilities register +///@{ +#define EFI_PCIE_ERROR_PORT_PCIE_ENDPOINT 0x00000000 +#define EFI_PCIE_ERROR_PORT_PCI_ENDPOINT 0x00000001 +#define EFI_PCIE_ERROR_PORT_ROOT_PORT 0x00000004 +#define EFI_PCIE_ERROR_PORT_UPSWITCH_PORT 0x00000005 +#define EFI_PCIE_ERROR_PORT_DOWNSWITCH_PORT 0x00000006 +#define EFI_PCIE_ERROR_PORT_PCIE_TO_PCI_BRIDGE 0x00000007 +#define EFI_PCIE_ERROR_PORT_PCI_TO_PCIE_BRIDGE 0x00000008 +#define EFI_PCIE_ERROR_PORT_ROOT_INT_ENDPOINT 0x00000009 +#define EFI_PCIE_ERROR_PORT_ROOT_EVENT_COLLECTOR 0x0000000A +///@} + +/// +/// PCI Slot number +/// +typedef struct { + UINT16 Resv1:3; + UINT16 Number:13; +} EFI_GENERIC_ERROR_PCI_SLOT; + +/// +/// PCIe Root Port PCI/bridge PCI compatible device number and +/// bus number information to uniquely identify the root port or +/// bridge. Default values for both the bus numbers is zero. +/// +typedef struct { + UINT16 VendorId; + UINT16 DeviceId; + UINT8 ClassCode[3]; + UINT8 Function; + UINT8 Device; + UINT16 Segment; + UINT8 PrimaryOrDeviceBus; + UINT8 SecondaryBus; + EFI_GENERIC_ERROR_PCI_SLOT Slot; + UINT8 Resv1; +} EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID; + +/// +/// PCIe Capability Structure +/// +typedef struct { + UINT8 PcieCap[60]; +} EFI_PCIE_ERROR_DATA_CAPABILITY; + +/// +/// PCIe Advanced Error Reporting Extended Capability Structure. +/// +typedef struct { + UINT8 PcieAer[96]; +} EFI_PCIE_ERROR_DATA_AER; + +/// +/// PCI Express Error Record +/// +typedef struct { + UINT64 ValidFields; + UINT32 PortType; + UINT32 Version; + UINT32 CommandStatus; + UINT32 Resv2; + EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID DevBridge; + UINT64 SerialNo; + UINT32 BridgeControlStatus; + EFI_PCIE_ERROR_DATA_CAPABILITY Capability; + EFI_PCIE_ERROR_DATA_AER AerInfo; +} EFI_PCIE_ERROR_DATA; + +/// +/// Validation bits Indicates which of the following fields is valid +/// in PCI/PCI-X Bus Error Section. +///@{ +#define EFI_PCI_PCIX_BUS_ERROR_STATUS_VALID BIT0 +#define EFI_PCI_PCIX_BUS_ERROR_TYPE_VALID BIT1 +#define EFI_PCI_PCIX_BUS_ERROR_BUS_ID_VALID BIT2 +#define EFI_PCI_PCIX_BUS_ERROR_BUS_ADDRESS_VALID BIT3 +#define EFI_PCI_PCIX_BUS_ERROR_BUS_DATA_VALID BIT4 +#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID BIT5 +#define EFI_PCI_PCIX_BUS_ERROR_REQUESTOR_ID_VALID BIT6 +#define EFI_PCI_PCIX_BUS_ERROR_COMPLETER_ID_VALID BIT7 +#define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID BIT8 +///@} + +/// +/// PCI Bus Error Type in PCI/PCI-X Bus Error Section +///@{ +#define EFI_PCI_PCIX_BUS_ERROR_UNKNOWN 0x0000 +#define EFI_PCI_PCIX_BUS_ERROR_DATA_PARITY 0x0001 +#define EFI_PCI_PCIX_BUS_ERROR_SYSTEM 0x0002 +#define EFI_PCI_PCIX_BUS_ERROR_MASTER_ABORT 0x0003 +#define EFI_PCI_PCIX_BUS_ERROR_BUS_TIMEOUT 0x0004 +#define EFI_PCI_PCIX_BUS_ERROR_MASTER_DATA_PARITY 0x0005 +#define EFI_PCI_PCIX_BUS_ERROR_ADDRESS_PARITY 0x0006 +#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_PARITY 0x0007 +///@} + +/// +/// PCI/PCI-X Bus Error Section +/// +typedef struct { + UINT64 ValidFields; + EFI_GENERIC_ERROR_STATUS ErrorStatus; + UINT16 Type; + UINT16 BusId; + UINT32 Resv2; + UINT64 BusAddress; + UINT64 BusData; + UINT64 BusCommand; + UINT64 RequestorId; + UINT64 ResponderId; + UINT64 TargetId; +} EFI_PCI_PCIX_BUS_ERROR_DATA; + +/// +/// Validation bits Indicates which of the following fields is valid +/// in PCI/PCI-X Component Error Section. +///@{ +#define EFI_PCI_PCIX_DEVICE_ERROR_STATUS_VALID BIT0 +#define EFI_PCI_PCIX_DEVICE_ERROR_ID_INFO_VALID BIT1 +#define EFI_PCI_PCIX_DEVICE_ERROR_MEM_NUM_VALID BIT2 +#define EFI_PCI_PCIX_DEVICE_ERROR_IO_NUM_VALID BIT3 +#define EFI_PCI_PCIX_DEVICE_ERROR_REG_DATA_PAIR_VALID BIT4 +///@} + +/// +/// PCI/PCI-X Device Identification Information +/// +typedef struct { + UINT16 VendorId; + UINT16 DeviceId; + UINT8 ClassCode[3]; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT8 Segment; + UINT8 Resv1; + UINT32 Resv2; +} EFI_GENERIC_ERROR_PCI_DEVICE_ID; + +/// +/// Identifies the type of firmware error record +///@{ +#define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL 0x00 +#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1 0x01 +#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2 0x02 +///@} + +/// +/// Firmware Error Record Section +/// +typedef struct { + UINT8 ErrorType; + UINT8 Revision; + UINT8 Resv1[6]; + UINT64 RecordId; + EFI_GUID RecordIdGuid; +} EFI_FIRMWARE_ERROR_DATA; + +/// +/// Fault Reason in DMAr Generic Error Section +///@{ +#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_NOT_PRESENT 0x01 +#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_INVALID 0x02 +#define EFI_DMA_FAULT_REASON_ACCESS_MAPPING_TABLE_ERROR 0x03 +#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_MAPPING_TABLE 0x04 +#define EFI_DMA_FAULT_REASON_ACCESS_ADDR_OUT_OF_SPACE 0x05 +#define EFI_DMA_FAULT_REASON_INVALID_ACCESS 0x06 +#define EFI_DMA_FAULT_REASON_INVALID_REQUEST 0x07 +#define EFI_DMA_FAULT_REASON_ACCESS_TRANSLATE_TABLE_ERROR 0x08 +#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_TRANSLATE_TABLE 0x09 +#define EFI_DMA_FAULT_REASON_INVALID_COMMAOND 0x0A +#define EFI_DMA_FAULT_REASON_ACCESS_COMMAND_BUFFER_ERROR 0x0B +///@} + +/// +/// DMA access type in DMAr Generic Error Section +///@{ +#define EFI_DMA_ACCESS_TYPE_READ 0x00 +#define EFI_DMA_ACCESS_TYPE_WRITE 0x01 +///@} + +/// +/// DMA address type in DMAr Generic Error Section +///@{ +#define EFI_DMA_ADDRESS_UNTRANSLATED 0x00 +#define EFI_DMA_ADDRESS_TRANSLATION 0x01 +///@} + +/// +/// Architecture type in DMAr Generic Error Section +///@{ +#define EFI_DMA_ARCH_TYPE_VT 0x01 +#define EFI_DMA_ARCH_TYPE_IOMMU 0x02 +///@} + +/// +/// DMAr Generic Error Section +/// +typedef struct { + UINT16 RequesterId; + UINT16 SegmentNumber; + UINT8 FaultReason; + UINT8 AccessType; + UINT8 AddressType; + UINT8 ArchType; + UINT64 DeviceAddr; + UINT8 Resv1[16]; +} EFI_DMAR_GENERIC_ERROR_DATA; + +/// +/// Intel VT for Directed I/O specific DMAr Errors +/// +typedef struct { + UINT8 Version; + UINT8 Revision; + UINT8 OemId[6]; + UINT64 Capability; + UINT64 CapabilityEx; + UINT32 GlobalCommand; + UINT32 GlobalStatus; + UINT32 FaultStatus; + UINT8 Resv1[12]; + UINT64 FaultRecord[2]; + UINT64 RootEntry[2]; + UINT64 ContextEntry[2]; + UINT64 PteL6; + UINT64 PteL5; + UINT64 PteL4; + UINT64 PteL3; + UINT64 PteL2; + UINT64 PteL1; +} EFI_DIRECTED_IO_DMAR_ERROR_DATA; + +/// +/// IOMMU specific DMAr Errors +/// +typedef struct { + UINT8 Revision; + UINT8 Resv1[7]; + UINT64 Control; + UINT64 Status; + UINT8 Resv2[8]; + UINT64 EventLogEntry[2]; + UINT8 Resv3[16]; + UINT64 DeviceTableEntry[4]; + UINT64 PteL6; + UINT64 PteL5; + UINT64 PteL4; + UINT64 PteL3; + UINT64 PteL2; + UINT64 PteL1; +} EFI_IOMMU_DMAR_ERROR_DATA; + +#pragma pack() + +extern EFI_GUID gEfiEventNotificationTypeCmcGuid; +extern EFI_GUID gEfiEventNotificationTypeCpeGuid; +extern EFI_GUID gEfiEventNotificationTypeMceGuid; +extern EFI_GUID gEfiEventNotificationTypePcieGuid; +extern EFI_GUID gEfiEventNotificationTypeInitGuid; +extern EFI_GUID gEfiEventNotificationTypeNmiGuid; +extern EFI_GUID gEfiEventNotificationTypeBootGuid; +extern EFI_GUID gEfiEventNotificationTypeDmarGuid; +extern EFI_GUID gEfiEventNotificationTypeSeaGuid; +extern EFI_GUID gEfiEventNotificationTypeSeiGuid; +extern EFI_GUID gEfiEventNotificationTypePeiGuid; + +extern EFI_GUID gEfiProcessorGenericErrorSectionGuid; +extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid; +extern EFI_GUID gEfiIa32X64ProcessorErrorSectionGuid; +extern EFI_GUID gEfiArmProcessorErrorSectionGuid ; +extern EFI_GUID gEfiPlatformMemoryErrorSectionGuid; +extern EFI_GUID gEfiPlatformMemory2ErrorSectionGuid; +extern EFI_GUID gEfiPcieErrorSectionGuid; +extern EFI_GUID gEfiFirmwareErrorSectionGuid; +extern EFI_GUID gEfiPciBusErrorSectionGuid; +extern EFI_GUID gEfiPciDevErrorSectionGuid; +extern EFI_GUID gEfiDMArGenericErrorSectionGuid; +extern EFI_GUID gEfiDirectedIoDMArErrorSectionGuid; +extern EFI_GUID gEfiIommuDMArErrorSectionGuid; + +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +/// +/// IA32 and x64 Specific definitions. +/// + +extern EFI_GUID gEfiIa32X64ErrorTypeCacheCheckGuid; +extern EFI_GUID gEfiIa32X64ErrorTypeTlbCheckGuid; +extern EFI_GUID gEfiIa32X64ErrorTypeBusCheckGuid; +extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid; + +#endif + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DebugImageInfoTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DebugImageInfoTable.h new file mode 100644 index 0000000000..7940f8d6fd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DebugImageInfoTable.h @@ -0,0 +1,74 @@ +/** @file + GUID and related data structures used with the Debug Image Info Table. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.0 spec. + +**/ + +#ifndef __DEBUG_IMAGE_INFO_GUID_H__ +#define __DEBUG_IMAGE_INFO_GUID_H__ + +#include + +/// +/// EFI_DEBUG_IMAGE_INFO_TABLE configuration table GUID declaration. +/// +#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \ + { \ + 0x49152e77, 0x1ada, 0x4764, {0xb7, 0xa2, 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b } \ + } + +#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01 +#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02 + +#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01 + +typedef struct { + UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE + EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table. + UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid. +} EFI_SYSTEM_TABLE_POINTER; + +typedef struct { + /// + /// Indicates the type of image info structure. For PE32 EFI images, + /// this is set to EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL. + /// + UINT32 ImageInfoType; + /// + /// A pointer to an instance of the loaded image protocol for the associated image. + /// + EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance; + /// + /// Indicates the image handle of the associated image. + /// + EFI_HANDLE ImageHandle; +} EFI_DEBUG_IMAGE_INFO_NORMAL; + +typedef union { + UINT32 *ImageInfoType; + EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage; +} EFI_DEBUG_IMAGE_INFO; + +typedef struct { + /// + /// UpdateStatus is used by the system to indicate the state of the debug image info table. + /// + volatile UINT32 UpdateStatus; + /// + /// The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EfiDebugImageInfoTable. + /// + UINT32 TableSize; + /// + /// A pointer to the first element of an array of EFI_DEBUG_IMAGE_INFO structures. + /// + EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable; +} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER; + +extern EFI_GUID gEfiDebugImageInfoTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DxeServices.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DxeServices.h new file mode 100644 index 0000000000..8c5f7e927b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/DxeServices.h @@ -0,0 +1,22 @@ +/** @file + GUID used to identify the DXE Services Table + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.0. + +**/ + +#ifndef __DXE_SERVICES_GUID_H__ +#define __DXE_SERVICES_GUID_H__ + +#define DXE_SERVICES_TABLE_GUID \ + { \ + 0x5ad34ba, 0x6f02, 0x4214, {0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9 } \ + } + +extern EFI_GUID gEfiDxeServicesTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventGroup.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventGroup.h new file mode 100644 index 0000000000..1614c542bf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventGroup.h @@ -0,0 +1,46 @@ +/** @file + GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EVENT_GROUP_GUID__ +#define __EVENT_GROUP_GUID__ + + +#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \ + { 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } } + +extern EFI_GUID gEfiEventExitBootServicesGuid; + + +#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \ + { 0x13fa7698, 0xc831, 0x49c7, { 0x87, 0xea, 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96 } } + +extern EFI_GUID gEfiEventVirtualAddressChangeGuid; + + +#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \ + { 0x78bee926, 0x692f, 0x48fd, { 0x9e, 0xdb, 0x1, 0x42, 0x2e, 0xf0, 0xd7, 0xab } } + +extern EFI_GUID gEfiEventMemoryMapChangeGuid; + + +#define EFI_EVENT_GROUP_READY_TO_BOOT \ + { 0x7ce88fb3, 0x4bd7, 0x4679, { 0x87, 0xa8, 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b } } + +extern EFI_GUID gEfiEventReadyToBootGuid; + +#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \ + { 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }} + +extern EFI_GUID gEfiEventDxeDispatchGuid; + +#define EFI_END_OF_DXE_EVENT_GROUP_GUID \ + { 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 } } + +extern EFI_GUID gEfiEndOfDxeEventGroupGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventLegacyBios.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventLegacyBios.h new file mode 100644 index 0000000000..038259bf20 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/EventLegacyBios.h @@ -0,0 +1,22 @@ +/** @file + GUID is the name of events used with CreateEventEx in order to be notified + when the EFI boot manager is about to boot a legacy boot option. + Events of this type are notificated just before Int19h is invoked. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.0. + +**/ + +#ifndef __EVENT_LEGACY_BIOS_GUID_H__ +#define __EVENT_LEGACY_BIOS_GUID_H__ + +#define EFI_EVENT_LEGACY_BOOT_GUID \ + { 0x2a571201, 0x4966, 0x47f6, {0x8b, 0x86, 0xf3, 0x1e, 0x41, 0xf3, 0x2f, 0x10 } } + +extern EFI_GUID gEfiEventLegacyBootGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileInfo.h new file mode 100644 index 0000000000..db359799ad --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileInfo.h @@ -0,0 +1,65 @@ +/** @file + Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.SetInfo() + and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information. + This GUID is defined in UEFI specification. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FILE_INFO_H__ +#define __FILE_INFO_H__ + +#define EFI_FILE_INFO_ID \ + { \ + 0x9576e92, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct { + /// + /// The size of the EFI_FILE_INFO structure, including the Null-terminated FileName string. + /// + UINT64 Size; + /// + /// The size of the file in bytes. + /// + UINT64 FileSize; + /// + /// PhysicalSize The amount of physical space the file consumes on the file system volume. + /// + UINT64 PhysicalSize; + /// + /// The time the file was created. + /// + EFI_TIME CreateTime; + /// + /// The time when the file was last accessed. + /// + EFI_TIME LastAccessTime; + /// + /// The time when the file's contents were last modified. + /// + EFI_TIME ModificationTime; + /// + /// The attribute bits for the file. + /// + UINT64 Attribute; + /// + /// The Null-terminated name of the file. + /// + CHAR16 FileName[1]; +} EFI_FILE_INFO; + +/// +/// The FileName field of the EFI_FILE_INFO data structure is variable length. +/// Whenever code needs to know the size of the EFI_FILE_INFO data structure, it needs to +/// be the size of the data structure without the FileName field. The following macro +/// computes this size correctly no matter how big the FileName array is declared. +/// This is required to make the EFI_FILE_INFO data structure ANSI compilant. +/// +#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName) + +extern EFI_GUID gEfiFileInfoGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemInfo.h new file mode 100644 index 0000000000..3a0aa9d66b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemInfo.h @@ -0,0 +1,57 @@ +/** @file + Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo() + or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume. + This GUID is defined in UEFI specification. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FILE_SYSTEM_INFO_H__ +#define __FILE_SYSTEM_INFO_H__ + +#define EFI_FILE_SYSTEM_INFO_ID \ + { \ + 0x9576e93, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct { + /// + /// The size of the EFI_FILE_SYSTEM_INFO structure, including the Null-terminated VolumeLabel string. + /// + UINT64 Size; + /// + /// TRUE if the volume only supports read access. + /// + BOOLEAN ReadOnly; + /// + /// The number of bytes managed by the file system. + /// + UINT64 VolumeSize; + /// + /// The number of available bytes for use by the file system. + /// + UINT64 FreeSpace; + /// + /// The nominal block size by which files are typically grown. + /// + UINT32 BlockSize; + /// + /// The Null-terminated string that is the volume's label. + /// + CHAR16 VolumeLabel[1]; +} EFI_FILE_SYSTEM_INFO; + +/// +/// The VolumeLabel field of the EFI_FILE_SYSTEM_INFO data structure is variable length. +/// Whenever code needs to know the size of the EFI_FILE_SYSTEM_INFO data structure, it needs +/// to be the size of the data structure without the VolumeLable field. The following macro +/// computes this size correctly no matter how big the VolumeLable array is declared. +/// This is required to make the EFI_FILE_SYSTEM_INFO data structure ANSI compilant. +/// +#define SIZE_OF_EFI_FILE_SYSTEM_INFO OFFSET_OF (EFI_FILE_SYSTEM_INFO, VolumeLabel) + +extern EFI_GUID gEfiFileSystemInfoGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h new file mode 100644 index 0000000000..9be7a7c33f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h @@ -0,0 +1,31 @@ +/** @file + Provides a GUID and a data structure that can be used with EFI_FILE_PROTOCOL.GetInfo() + or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label. + This GUID is defined in UEFI specification. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FILE_SYSTEM_VOLUME_LABEL_INFO_H__ +#define __FILE_SYSTEM_VOLUME_LABEL_INFO_H__ + +#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \ + { \ + 0xDB47D7D3, 0xFE81, 0x11d3, {0x9A, 0x35, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \ + } + +typedef struct { + /// + /// The Null-terminated string that is the volume's label. + /// + CHAR16 VolumeLabel[1]; +} EFI_FILE_SYSTEM_VOLUME_LABEL; + +#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \ + OFFSET_OF (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel) + +extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareContentsSigned.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareContentsSigned.h new file mode 100644 index 0000000000..1748da8f56 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareContentsSigned.h @@ -0,0 +1,20 @@ +/** @file + GUID is used to define the signed section. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.2.1. + +**/ + +#ifndef __FIRMWARE_CONTENTS_SIGNED_GUID_H__ +#define __FIRMWARE_CONTENTS_SIGNED_GUID_H__ + +#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \ + { 0xf9d89e8, 0x9259, 0x4f76, {0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } } + +extern EFI_GUID gEfiFirmwareContentsSignedGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem2.h new file mode 100644 index 0000000000..1d4cfd3cf0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem2.h @@ -0,0 +1,34 @@ +/** @file + Guid used to define the Firmware File System 2. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs introduced in PI Version 1.0. + +**/ + +#ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__ +#define __FIRMWARE_FILE_SYSTEM2_GUID_H__ + +/// +/// The firmware volume header contains a data field for +/// the file system GUID +/// +#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \ + { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } } + +/// +/// A Volume Top File (VTF) is a file that must be +/// located such that the last byte of the file is +/// also the last byte of the firmware volume +/// +#define EFI_FFS_VOLUME_TOP_FILE_GUID \ + { 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } } + + +extern EFI_GUID gEfiFirmwareFileSystem2Guid; +extern EFI_GUID gEfiFirmwareVolumeTopFileGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem3.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem3.h new file mode 100644 index 0000000000..a9c7fb9f20 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FirmwareFileSystem3.h @@ -0,0 +1,24 @@ +/** @file + Guid used to define the Firmware File System 3. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs introduced in PI Version 1.0. + +**/ + +#ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__ +#define __FIRMWARE_FILE_SYSTEM3_GUID_H__ + +/// +/// The firmware volume header contains a data field for the file system GUID +/// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A} +/// +#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \ + { 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }} + +extern EFI_GUID gEfiFirmwareFileSystem3Guid; + +#endif // __FIRMWARE_FILE_SYSTEM3_GUID_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FmpCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FmpCapsule.h new file mode 100644 index 0000000000..c19671e845 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/FmpCapsule.h @@ -0,0 +1,101 @@ +/** @file + Guid & data structure used for Delivering Capsules Containing Updates to Firmware + Management Protocol + + Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.4 spec. + +**/ + + +#ifndef _FMP_CAPSULE_GUID_H__ +#define _FMP_CAPSULE_GUID_H__ + +// +// This is the GUID of the capsule for Firmware Management Protocol. +// +#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID \ + { \ + 0x6dcbd5ed, 0xe82d, 0x4c44, {0xbd, 0xa1, 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a } \ + } + +#pragma pack(1) + +typedef struct { + UINT32 Version; + + /// + /// The number of drivers included in the capsule and the number of corresponding + /// offsets stored in ItemOffsetList array. + /// + UINT16 EmbeddedDriverCount; + + /// + /// The number of payload items included in the capsule and the number of + /// corresponding offsets stored in the ItemOffsetList array. + /// + UINT16 PayloadItemCount; + + /// + /// Variable length array of dimension [EmbeddedDriverCount + PayloadItemCount] + /// containing offsets of each of the drivers and payload items contained within the capsule + /// + // UINT64 ItemOffsetList[]; +} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER; + +typedef struct { + UINT32 Version; + + /// + /// Used to identify device firmware targeted by this update. This guid is matched by + /// system firmware against ImageTypeId field within a EFI_FIRMWARE_IMAGE_DESCRIPTOR + /// + EFI_GUID UpdateImageTypeId; + + /// + /// Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage() + /// + UINT8 UpdateImageIndex; + UINT8 reserved_bytes[3]; + + /// + /// Size of the binary update image which immediately follows this structure + /// + UINT32 UpdateImageSize; + + /// + /// Size of the VendorCode bytes which optionally immediately follow binary update image in the capsule + /// + UINT32 UpdateVendorCodeSize; + + /// + /// The HardwareInstance to target with this update. If value is zero it means match all + /// HardwareInstances. This field allows update software to target only a single device in + /// cases where there are more than one device with the same ImageTypeId GUID. + /// This header is outside the signed data of the Authentication Info structure and + /// therefore can be modified without changing the Auth data. + /// + UINT64 UpdateHardwareInstance; + + /// + /// A 64-bit bitmask that determines what sections are added to the payload. + /// #define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001 + /// #define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002 + /// + UINT64 ImageCapsuleSupport; +} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER; + +#pragma pack() + + +#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001 +#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003 +#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001 +#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002 + +extern EFI_GUID gEfiFmpCapsuleGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GlobalVariable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GlobalVariable.h new file mode 100644 index 0000000000..b1e07ff543 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GlobalVariable.h @@ -0,0 +1,186 @@ +/** @file + GUID for EFI (NVRAM) Variables. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.1 +**/ + +#ifndef __GLOBAL_VARIABLE_GUID_H__ +#define __GLOBAL_VARIABLE_GUID_H__ + +#define EFI_GLOBAL_VARIABLE \ + { \ + 0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C } \ + } + +extern EFI_GUID gEfiGlobalVariableGuid; + +// +// Follow UEFI 2.4 spec: +// To prevent name collisions with possible future globally defined variables, +// other internal firmware data variables that are not defined here must be +// saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE or +// any other GUID defined by the UEFI Specification. Implementations must +// only permit the creation of variables with a UEFI Specification-defined +// VendorGuid when these variables are documented in the UEFI Specification. +// +// Note: except the globally defined variables defined below, the spec also defines +// L"Boot####" - A boot load option. +// L"Driver####" - A driver load option. +// L"SysPrep####" - A System Prep application load option. +// L"Key####" - Describes hot key relationship with a Boot#### load option. +// The attribute for them is NV+BS+RT, #### is a printed hex value, and no 0x or h +// is included in the hex value. They can not be expressed as a #define like other globally +// defined variables, it is because we can not list the Boot0000, Boot0001, etc one by one. +// + +/// +/// The language codes that the firmware supports. This value is deprecated. +/// Its attribute is BS+RT. +/// +#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes" +/// +/// The language code that the system is configured for. This value is deprecated. +/// Its attribute is NV+BS+RT. +/// +#define EFI_LANG_VARIABLE_NAME L"Lang" +/// +/// The firmware's boot managers timeout, in seconds, before initiating the default boot selection. +/// Its attribute is NV+BS+RT. +/// +#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout" +/// +/// The language codes that the firmware supports. +/// Its attribute is BS+RT. +/// +#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes" +/// +/// The language code that the system is configured for. +/// Its attribute is NV+BS+RT. +/// +#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang" +/// +/// The device path of the default input/output/error output console. +/// Its attribute is NV+BS+RT. +/// +#define EFI_CON_IN_VARIABLE_NAME L"ConIn" +#define EFI_CON_OUT_VARIABLE_NAME L"ConOut" +#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut" +/// +/// The device path of all possible input/output/error output devices. +/// Its attribute is BS+RT. +/// +#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev" +#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev" +#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev" +/// +/// The ordered boot option load list. +/// Its attribute is NV+BS+RT. +/// +#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder" +/// +/// The boot option for the next boot only. +/// Its attribute is NV+BS+RT. +/// +#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext" +/// +/// The boot option that was selected for the current boot. +/// Its attribute is BS+RT. +/// +#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent" +/// +/// The types of boot options supported by the boot manager. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport" +/// +/// The ordered driver load option list. +/// Its attribute is NV+BS+RT. +/// +#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder" +/// +/// The ordered System Prep Application load option list. +/// Its attribute is NV+BS+RT. +/// +#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder" +/// +/// Identifies the level of hardware error record persistence +/// support implemented by the platform. This variable is +/// only modified by firmware and is read-only to the OS. +/// Its attribute is NV+BS+RT. +/// +#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport" +/// +/// Whether the system is operating in setup mode (1) or not (0). +/// All other values are reserved. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_SETUP_MODE_NAME L"SetupMode" +/// +/// The Key Exchange Key Signature Database. +/// Its attribute is NV+BS+RT+AT. +/// +#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK" +/// +/// The public Platform Key. +/// Its attribute is NV+BS+RT+AT. +/// +#define EFI_PLATFORM_KEY_NAME L"PK" +/// +/// Array of GUIDs representing the type of signatures supported +/// by the platform firmware. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport" +/// +/// Whether the platform firmware is operating in Secure boot mode (1) or not (0). +/// All other values are reserved. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot" +/// +/// The OEM's default Key Exchange Key Signature Database. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault" +/// +/// The OEM's default public Platform Key. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault" +/// +/// The OEM's default secure boot signature store. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault" +/// +/// The OEM's default secure boot blacklist signature store. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault" +/// +/// The OEM's default secure boot timestamp signature store. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault" +/// +/// Allows the firmware to indicate supported features and actions to the OS. +/// Its attribute is BS+RT. +/// +#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported" +/// +/// Allows the OS to request the firmware to enable certain features and to take certain actions. +/// Its attribute is NV+BS+RT. +/// +#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications" +/// +/// Whether the system is configured to use only vendor provided +/// keys or not. Should be treated as read-only. +/// Its attribute is BS+RT. +/// +#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys" + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Gpt.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Gpt.h new file mode 100644 index 0000000000..8c45490c86 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Gpt.h @@ -0,0 +1,37 @@ +/** @file + Guids used for the GPT (GUID Partition Table) + + GPT defines a new disk partitioning scheme and also describes + usage of the legacy Master Boot Record (MBR) partitioning scheme. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.1 spec. + +**/ + +#ifndef __GPT_GUID_H__ +#define __GPT_GUID_H__ + +#define EFI_PART_TYPE_UNUSED_GUID \ + { \ + 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } \ + } + +#define EFI_PART_TYPE_EFI_SYSTEM_PART_GUID \ + { \ + 0xc12a7328, 0xf81f, 0x11d2, {0xba, 0x4b, 0x00, 0xa0, 0xc9, 0x3e, 0xc9, 0x3b } \ + } + +#define EFI_PART_TYPE_LEGACY_MBR_GUID \ + { \ + 0x024dee41, 0x33e7, 0x11d3, {0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f } \ + } + +extern EFI_GUID gEfiPartTypeUnusedGuid; +extern EFI_GUID gEfiPartTypeSystemPartGuid; +extern EFI_GUID gEfiPartTypeLegacyMbrGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GraphicsInfoHob.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GraphicsInfoHob.h new file mode 100644 index 0000000000..cd1965c385 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/GraphicsInfoHob.h @@ -0,0 +1,45 @@ +/** @file + Hob guid for Information about the graphics mode. + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This HOB is introduced in in PI Version 1.4. + +**/ + +#ifndef _GRAPHICS_INFO_HOB_GUID_H_ +#define _GRAPHICS_INFO_HOB_GUID_H_ + +#include + +#define EFI_PEI_GRAPHICS_INFO_HOB_GUID \ + { \ + 0x39f62cce, 0x6825, 0x4669, { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \ + } + +#define EFI_PEI_GRAPHICS_DEVICE_INFO_HOB_GUID \ + { \ + 0xe5cb2ac9, 0xd35d, 0x4430, { 0x93, 0x6e, 0x1d, 0xe3, 0x32, 0x47, 0x8d, 0xe7 } \ + } + +typedef struct { + EFI_PHYSICAL_ADDRESS FrameBufferBase; + UINT32 FrameBufferSize; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode; +} EFI_PEI_GRAPHICS_INFO_HOB; + +typedef struct { + UINT16 VendorId; ///< Ignore if the value is 0xFFFF. + UINT16 DeviceId; ///< Ignore if the value is 0xFFFF. + UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF. + UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF. + UINT8 RevisionId; ///< Ignore if the value is 0xFF. + UINT8 BarIndex; ///< Ignore if the value is 0xFF. +} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB; + +extern EFI_GUID gEfiGraphicsInfoHobGuid; +extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HardwareErrorVariable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HardwareErrorVariable.h new file mode 100644 index 0000000000..4385f5f7a2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HardwareErrorVariable.h @@ -0,0 +1,22 @@ +/** @file + GUID for hardware error record variables. + + Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.1. + +**/ + +#ifndef _HARDWARE_ERROR_VARIABLE_GUID_H_ +#define _HARDWARE_ERROR_VARIABLE_GUID_H_ + +#define EFI_HARDWARE_ERROR_VARIABLE \ + { \ + 0x414E6BDD, 0xE47B, 0x47cc, {0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16} \ + } + +extern EFI_GUID gEfiHardwareErrorVariableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiFormMapMethodGuid.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiFormMapMethodGuid.h new file mode 100644 index 0000000000..6fff5b606f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiFormMapMethodGuid.h @@ -0,0 +1,19 @@ +/** @file + Guid used to identify HII FormMap configuration method. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.2 spec. +**/ + +#ifndef __EFI_HII_FORMMAP_GUID_H__ +#define __EFI_HII_FORMMAP_GUID_H__ + +#define EFI_HII_STANDARD_FORM_GUID \ + { 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } } + +extern EFI_GUID gEfiHiiStandardFormGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiKeyBoardLayout.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiKeyBoardLayout.h new file mode 100644 index 0000000000..8f584b0930 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiKeyBoardLayout.h @@ -0,0 +1,21 @@ +/** @file + + HII keyboard layout GUID as defined in UEFI2.1 specification + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.1 spec. + +**/ + +#ifndef __HII_KEYBOARD_LAYOUT_GUID_H__ +#define __HII_KEYBOARD_LAYOUT_GUID_H__ + +#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \ + { 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }} + +extern EFI_GUID gEfiHiiKeyBoardLayoutGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiPlatformSetupFormset.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiPlatformSetupFormset.h new file mode 100644 index 0000000000..e0a38a2aa8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HiiPlatformSetupFormset.h @@ -0,0 +1,33 @@ +/** @file + GUID indicates that the form set contains forms designed to be used + for platform configuration and this form set will be displayed. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.1. + +**/ + +#ifndef __HII_PLATFORM_SETUP_FORMSET_GUID_H__ +#define __HII_PLATFORM_SETUP_FORMSET_GUID_H__ + +#define EFI_HII_PLATFORM_SETUP_FORMSET_GUID \ + { 0x93039971, 0x8545, 0x4b04, { 0xb4, 0x5e, 0x32, 0xeb, 0x83, 0x26, 0x4, 0xe } } + +#define EFI_HII_DRIVER_HEALTH_FORMSET_GUID \ + { 0xf22fc20c, 0x8cf4, 0x45eb, { 0x8e, 0x6, 0xad, 0x4e, 0x50, 0xb9, 0x5d, 0xd3 } } + +#define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \ + { 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } } + +#define EFI_HII_REST_STYLE_FORMSET_GUID \ + { 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } } + +extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid; +extern EFI_GUID gEfiHiiDriverHealthFormsetGuid; +extern EFI_GUID gEfiHiiUserCredentialFormsetGuid; +extern EFI_GUID gEfiHiiRestStyleFormsetGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HobList.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HobList.h new file mode 100644 index 0000000000..e44faedc17 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/HobList.h @@ -0,0 +1,24 @@ +/** @file + GUIDs used for HOB List entries + + These GUIDs point the HOB List passed from PEI to DXE. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID introduced in PI Version 1.0. + +**/ + +#ifndef __HOB_LIST_GUID_H__ +#define __HOB_LIST_GUID_H__ + +#define HOB_LIST_GUID \ + { \ + 0x7739f24c, 0x93d7, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +extern EFI_GUID gEfiHobListGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/ImageAuthentication.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/ImageAuthentication.h new file mode 100644 index 0000000000..84b52b9695 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/ImageAuthentication.h @@ -0,0 +1,346 @@ +/** @file + Image signature database are defined for the signed image validation. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.5 spec. +**/ + +#ifndef __IMAGE_AUTHTICATION_H__ +#define __IMAGE_AUTHTICATION_H__ + +#include +#include + +#define EFI_IMAGE_SECURITY_DATABASE_GUID \ + { \ + 0xd719b2cb, 0x3d3a, 0x4596, { 0xa3, 0xbc, 0xda, 0xd0, 0xe, 0x67, 0x65, 0x6f } \ + } + +/// +/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID +/// for the authorized signature database. +/// +#define EFI_IMAGE_SECURITY_DATABASE L"db" +/// +/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID +/// for the forbidden signature database. +/// +#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx" +/// +/// Variable name with guid EFI_IMAGE_SECURITY_DATABASE_GUID +/// for the timestamp signature database. +/// +#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt" + +#define SECURE_BOOT_MODE_ENABLE 1 +#define SECURE_BOOT_MODE_DISABLE 0 + +#define SETUP_MODE 1 +#define USER_MODE 0 + +//*********************************************************************** +// Signature Database +//*********************************************************************** +/// +/// The format of a signature database. +/// +#pragma pack(1) + +typedef struct { + /// + /// An identifier which identifies the agent which added the signature to the list. + /// + EFI_GUID SignatureOwner; + /// + /// The format of the signature is defined by the SignatureType. + /// + UINT8 SignatureData[1]; +} EFI_SIGNATURE_DATA; + +typedef struct { + /// + /// Type of the signature. GUID signature types are defined in below. + /// + EFI_GUID SignatureType; + /// + /// Total size of the signature list, including this header. + /// + UINT32 SignatureListSize; + /// + /// Size of the signature header which precedes the array of signatures. + /// + UINT32 SignatureHeaderSize; + /// + /// Size of each signature. + /// + UINT32 SignatureSize; + /// + /// Header before the array of signatures. The format of this header is specified + /// by the SignatureType. + /// UINT8 SignatureHeader[SignatureHeaderSize]; + /// + /// An array of signatures. Each signature is SignatureSize bytes in length. + /// EFI_SIGNATURE_DATA Signatures[][SignatureSize]; + /// +} EFI_SIGNATURE_LIST; + +typedef struct { + /// + /// The SHA256 hash of an X.509 certificate's To-Be-Signed contents. + /// + EFI_SHA256_HASH ToBeSignedHash; + /// + /// The time that the certificate shall be considered to be revoked. + /// + EFI_TIME TimeOfRevocation; +} EFI_CERT_X509_SHA256; + +typedef struct { + /// + /// The SHA384 hash of an X.509 certificate's To-Be-Signed contents. + /// + EFI_SHA384_HASH ToBeSignedHash; + /// + /// The time that the certificate shall be considered to be revoked. + /// + EFI_TIME TimeOfRevocation; +} EFI_CERT_X509_SHA384; + +typedef struct { + /// + /// The SHA512 hash of an X.509 certificate's To-Be-Signed contents. + /// + EFI_SHA512_HASH ToBeSignedHash; + /// + /// The time that the certificate shall be considered to be revoked. + /// + EFI_TIME TimeOfRevocation; +} EFI_CERT_X509_SHA512; + +#pragma pack() + +/// +/// This identifies a signature containing a SHA-256 hash. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + +/// 32 bytes. +/// +#define EFI_CERT_SHA256_GUID \ + { \ + 0xc1c41626, 0x504c, 0x4092, {0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28} \ + } + +/// +/// This identifies a signature containing an RSA-2048 key. The key (only the modulus +/// since the public key exponent is known to be 0x10001) shall be stored in big-endian +/// order. +/// The SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size +/// of SignatureOwner component) + 256 bytes. +/// +#define EFI_CERT_RSA2048_GUID \ + { \ + 0x3c5766e8, 0x269c, 0x4e34, {0xaa, 0x14, 0xed, 0x77, 0x6e, 0x85, 0xb3, 0xb6} \ + } + +/// +/// This identifies a signature containing a RSA-2048 signature of a SHA-256 hash. The +/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of +/// SignatureOwner component) + 256 bytes. +/// +#define EFI_CERT_RSA2048_SHA256_GUID \ + { \ + 0xe2b36190, 0x879b, 0x4a3d, {0xad, 0x8d, 0xf2, 0xe7, 0xbb, 0xa3, 0x27, 0x84} \ + } + +/// +/// This identifies a signature containing a SHA-1 hash. The SignatureSize shall always +/// be 16 (size of SignatureOwner component) + 20 bytes. +/// +#define EFI_CERT_SHA1_GUID \ + { \ + 0x826ca512, 0xcf10, 0x4ac9, {0xb1, 0x87, 0xbe, 0x1, 0x49, 0x66, 0x31, 0xbd} \ + } + +/// +/// TThis identifies a signature containing a RSA-2048 signature of a SHA-1 hash. The +/// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of +/// SignatureOwner component) + 256 bytes. +/// +#define EFI_CERT_RSA2048_SHA1_GUID \ + { \ + 0x67f8444f, 0x8743, 0x48f1, {0xa3, 0x28, 0x1e, 0xaa, 0xb8, 0x73, 0x60, 0x80} \ + } + +/// +/// This identifies a signature based on an X.509 certificate. If the signature is an X.509 +/// certificate then verification of the signature of an image should validate the public +/// key certificate in the image using certificate path verification, up to this X.509 +/// certificate as a trusted root. The SignatureHeader size shall always be 0. The +/// SignatureSize may vary but shall always be 16 (size of the SignatureOwner component) + +/// the size of the certificate itself. +/// Note: This means that each certificate will normally be in a separate EFI_SIGNATURE_LIST. +/// +#define EFI_CERT_X509_GUID \ + { \ + 0xa5c059a1, 0x94e4, 0x4aa7, {0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72} \ + } + +/// +/// This identifies a signature containing a SHA-224 hash. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + +/// 28 bytes. +/// +#define EFI_CERT_SHA224_GUID \ + { \ + 0xb6e5233, 0xa65c, 0x44c9, {0x94, 0x7, 0xd9, 0xab, 0x83, 0xbf, 0xc8, 0xbd} \ + } + +/// +/// This identifies a signature containing a SHA-384 hash. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + +/// 48 bytes. +/// +#define EFI_CERT_SHA384_GUID \ + { \ + 0xff3e5307, 0x9fd0, 0x48c9, {0x85, 0xf1, 0x8a, 0xd5, 0x6c, 0x70, 0x1e, 0x1} \ + } + +/// +/// This identifies a signature containing a SHA-512 hash. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + +/// 64 bytes. +/// +#define EFI_CERT_SHA512_GUID \ + { \ + 0x93e0fae, 0xa6c4, 0x4f50, {0x9f, 0x1b, 0xd4, 0x1e, 0x2b, 0x89, 0xc1, 0x9a} \ + } + +/// +/// This identifies a signature containing the SHA256 hash of an X.509 certificate's +/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component) +/// + 48 bytes for an EFI_CERT_X509_SHA256 structure. If the TimeOfRevocation is non-zero, +/// the certificate should be considered to be revoked from that time and onwards, and +/// otherwise the certificate shall be considered to always be revoked. +/// +#define EFI_CERT_X509_SHA256_GUID \ + { \ + 0x3bd2a492, 0x96c0, 0x4079, {0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed } \ + } + +/// +/// This identifies a signature containing the SHA384 hash of an X.509 certificate's +/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component) +/// + 64 bytes for an EFI_CERT_X509_SHA384 structure. If the TimeOfRevocation is non-zero, +/// the certificate should be considered to be revoked from that time and onwards, and +/// otherwise the certificate shall be considered to always be revoked. +/// +#define EFI_CERT_X509_SHA384_GUID \ + { \ + 0x7076876e, 0x80c2, 0x4ee6, {0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b } \ + } + +/// +/// This identifies a signature containing the SHA512 hash of an X.509 certificate's +/// To-Be-Signed contents, and a time of revocation. The SignatureHeader size shall +/// always be 0. The SignatureSize shall always be 16 (size of the SignatureOwner component) +/// + 80 bytes for an EFI_CERT_X509_SHA512 structure. If the TimeOfRevocation is non-zero, +/// the certificate should be considered to be revoked from that time and onwards, and +/// otherwise the certificate shall be considered to always be revoked. +/// +#define EFI_CERT_X509_SHA512_GUID \ + { \ + 0x446dbf63, 0x2502, 0x4cda, {0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d } \ + } + +/// +/// This identifies a signature containing a DER-encoded PKCS #7 version 1.5 [RFC2315] +/// SignedData value. +/// +#define EFI_CERT_TYPE_PKCS7_GUID \ + { \ + 0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7} \ + } + +//*********************************************************************** +// Image Execution Information Table Definition +//*********************************************************************** +typedef UINT32 EFI_IMAGE_EXECUTION_ACTION; + +#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007 +#define EFI_IMAGE_EXECUTION_AUTH_UNTESTED 0x00000000 +#define EFI_IMAGE_EXECUTION_AUTH_SIG_FAILED 0x00000001 +#define EFI_IMAGE_EXECUTION_AUTH_SIG_PASSED 0x00000002 +#define EFI_IMAGE_EXECUTION_AUTH_SIG_NOT_FOUND 0x00000003 +#define EFI_IMAGE_EXECUTION_AUTH_SIG_FOUND 0x00000004 +#define EFI_IMAGE_EXECUTION_POLICY_FAILED 0x00000005 +#define EFI_IMAGE_EXECUTION_INITIALIZED 0x00000008 + +// +// EFI_IMAGE_EXECUTION_INFO is added to EFI System Configuration Table +// and assigned the GUID EFI_IMAGE_SECURITY_DATABASE_GUID. +// +typedef struct { + /// + /// Describes the action taken by the firmware regarding this image. + /// + EFI_IMAGE_EXECUTION_ACTION Action; + /// + /// Size of all of the entire structure. + /// + UINT32 InfoSize; + /// + /// If this image was a UEFI device driver (for option ROM, for example) this is the + /// null-terminated, user-friendly name for the device. If the image was for an application, + /// then this is the name of the application. If this cannot be determined, then a simple + /// NULL character should be put in this position. + /// CHAR16 Name[]; + /// + + /// + /// For device drivers, this is the device path of the device for which this device driver + /// was intended. In some cases, the driver itself may be stored as part of the system + /// firmware, but this field should record the device's path, not the firmware path. For + /// applications, this is the device path of the application. If this cannot be determined, + /// a simple end-of-path device node should be put in this position. + /// EFI_DEVICE_PATH_PROTOCOL DevicePath; + /// + + /// + /// Zero or more image signatures. If the image contained no signatures, + /// then this field is empty. + /// EFI_SIGNATURE_LIST Signature; + /// +} EFI_IMAGE_EXECUTION_INFO; + + +typedef struct { + /// + /// Number of EFI_IMAGE_EXECUTION_INFO structures. + /// + UINTN NumberOfImages; + /// + /// Number of image instances of EFI_IMAGE_EXECUTION_INFO structures. + /// + // EFI_IMAGE_EXECUTION_INFO InformationInfo[] +} EFI_IMAGE_EXECUTION_INFO_TABLE; + +extern EFI_GUID gEfiImageSecurityDatabaseGuid; +extern EFI_GUID gEfiCertSha256Guid; +extern EFI_GUID gEfiCertRsa2048Guid; +extern EFI_GUID gEfiCertRsa2048Sha256Guid; +extern EFI_GUID gEfiCertSha1Guid; +extern EFI_GUID gEfiCertRsa2048Sha1Guid; +extern EFI_GUID gEfiCertX509Guid; +extern EFI_GUID gEfiCertSha224Guid; +extern EFI_GUID gEfiCertSha384Guid; +extern EFI_GUID gEfiCertSha512Guid; +extern EFI_GUID gEfiCertX509Sha256Guid; +extern EFI_GUID gEfiCertX509Sha384Guid; +extern EFI_GUID gEfiCertX509Sha512Guid; +extern EFI_GUID gEfiCertPkcs7Guid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/JsonCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/JsonCapsule.h new file mode 100644 index 0000000000..d54c50694f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/JsonCapsule.h @@ -0,0 +1,98 @@ +/** @file +Guid & data structure for tables defined for reporting firmware configuration data to EFI +Configuration Tables and also for processing JSON payload capsule. + + +Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __JSON_CAPSULE_GUID_H__ +#define __JSON_CAPSULE_GUID_H__ + +// +// The address reported in the table entry identified by EFI_JSON_CAPSULE_DATA_TABLE_GUID will be +// referenced as physical and will not be fixed up when transition from preboot to runtime phase. The +// addresses reported in these table entries identified by EFI_JSON_CONFIG_DATA_TABLE_GUID and +// EFI_JSON_CAPSULE_RESULT_TABLE_GUID will be referenced as virtual and will be fixed up when +// transition from preboot to runtime phase. +// +#define EFI_JSON_CONFIG_DATA_TABLE_GUID \ + {0x87367f87, 0x1119, 0x41ce, \ + {0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }} +#define EFI_JSON_CAPSULE_DATA_TABLE_GUID \ + {0x35e7a725, 0x8dd2, 0x4cac, \ + {0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }} +#define EFI_JSON_CAPSULE_RESULT_TABLE_GUID \ + {0xdbc461c3, 0xb3de, 0x422a,\ + {0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }} +#define EFI_JSON_CAPSULE_ID_GUID \ + {0x67d6f4cd, 0xd6b8, 0x4573, \ + {0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }} + + +#pragma pack(1) + +typedef struct { + /// + /// Version of the structure, initially 0x00000001. + /// + UINT32 Version; + + /// + /// The unique identifier of this capsule. + /// + UINT32 CapsuleId; + + /// + /// The length of the JSON payload immediately following this header, in bytes. + /// + UINT32 PayloadLength; + + /// + /// Variable length buffer containing the JSON payload that should be parsed and applied to the system. The + /// definition of the JSON schema used in the payload is beyond the scope of this specification. + /// + UINT8 Payload[]; +} EFI_JSON_CAPSULE_HEADER; + +typedef struct { + /// + /// The length of the following ConfigData, in bytes. + /// + UINT32 ConfigDataLength; + + /// + /// Variable length buffer containing the JSON payload that describes one group of configuration data within + /// current system. The definition of the JSON schema used in this payload is beyond the scope of this specification. + /// + UINT8 ConfigData[]; +} EFI_JSON_CONFIG_DATA_ITEM; + +typedef struct { + /// + /// Version of the structure, initially 0x00000001. + /// + UINT32 Version; + + /// + ////The total length of EFI_JSON_CAPSULE_CONFIG_DATA, in bytes. + /// + UINT32 TotalLength; + + /// + /// Array of configuration data groups. + /// + EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[]; +} EFI_JSON_CAPSULE_CONFIG_DATA; + +#pragma pack() + +extern EFI_GUID gEfiJsonConfigDataTableGuid; +extern EFI_GUID gEfiJsonCapsuleDataTableGuid; +extern EFI_GUID gEfiJsonCapsuleResultTableGuid; +extern EFI_GUID gEfiJsonCapsuleIdGuid; + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h new file mode 100644 index 0000000000..db32fc9ad3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/LinuxEfiInitrdMedia.h @@ -0,0 +1,30 @@ +/** @file + GUID definition for the Linux Initrd media device path + + Linux distro boot generally relies on an initial ramdisk (initrd) which is + provided by the loader, and which contains additional kernel modules (for + storage and network, for instance), and the initial user space startup code, + i.e., the code which brings up the user space side of the entire OS. + + In order to provide a standard method to locate this initrd, the GUID defined + in this file is used to describe the device path for a LoadFile2 Protocol + instance that is responsible for loading the initrd file. + + The kernel EFI Stub will locate and use this instance to load the initrd, + therefore the firmware/loader should install an instance of this to load the + relevant initrd. + + Copyright (c) 2020, Arm, Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef LINUX_EFI_INITRD_MEDIA_GUID_H_ +#define LINUX_EFI_INITRD_MEDIA_GUID_H_ + +#define LINUX_EFI_INITRD_MEDIA_GUID \ + {0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}} + +extern EFI_GUID gLinuxEfiInitrdMediaGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MdePkgTokenSpace.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MdePkgTokenSpace.h new file mode 100644 index 0000000000..f20370e706 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MdePkgTokenSpace.h @@ -0,0 +1,19 @@ +/** @file + GUID for MdePkg PCD Token Space + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MDEPKG_TOKEN_SPACE_GUID_H_ +#define _MDEPKG_TOKEN_SPACE_GUID_H_ + +#define MDEPKG_TOKEN_SPACE_GUID \ + { \ + 0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 } \ + } + +extern EFI_GUID gEfiMdePkgTokenSpaceGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAllocationHob.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAllocationHob.h new file mode 100644 index 0000000000..1985abc049 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAllocationHob.h @@ -0,0 +1,28 @@ +/** @file + GUIDs for HOBs used in memory allcation + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs introduced in PI Version 1.0. + +**/ + +#ifndef __MEMORY_ALLOCATION_GUID_H__ +#define __MEMORY_ALLOCATION_GUID_H__ + +#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \ + {0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} }; + +#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \ + {0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} } + +#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \ + {0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} } + +extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid; +extern EFI_GUID gEfiHobMemoryAllocStackGuid; +extern EFI_GUID gEfiHobMemoryAllocModuleGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAttributesTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAttributesTable.h new file mode 100644 index 0000000000..2b4e2aa7e6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryAttributesTable.h @@ -0,0 +1,28 @@ +/** @file + GUIDs used for UEFI Memory Attributes Table in the UEFI 2.6 specification. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_MEMORY_ATTRIBUTES_TABLE_H__ +#define __UEFI_MEMORY_ATTRIBUTES_TABLE_H__ + +#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\ + 0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20} \ +} + +typedef struct { + UINT32 Version; + UINT32 NumberOfEntries; + UINT32 DescriptorSize; + UINT32 Reserved; +//EFI_MEMORY_DESCRIPTOR Entry[1]; +} EFI_MEMORY_ATTRIBUTES_TABLE; + +#define EFI_MEMORY_ATTRIBUTES_TABLE_VERSION 0x00000001 + +extern EFI_GUID gEfiMemoryAttributesTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryOverwriteControl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryOverwriteControl.h new file mode 100644 index 0000000000..9fba7eaf3a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/MemoryOverwriteControl.h @@ -0,0 +1,70 @@ +/** @file + GUID used for MemoryOverwriteRequestControl UEFI variable defined in + TCG Platform Reset Attack Mitigation Specification 1.00. + See http://trustedcomputinggroup.org for the latest specification + + The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to + indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon + a restart. The OS loader should not create the variable. Rather, the firmware is required to create it. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_ +#define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_ + +#define MEMORY_ONLY_RESET_CONTROL_GUID \ + { \ + 0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \ + } + +/// +/// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value. +/// The attributes should be: +/// EFI_VARIABLE_NON_VOLATILE | +/// EFI_VARIABLE_BOOTSERVICE_ACCESS | +/// EFI_VARIABLE_RUNTIME_ACCESS +/// +#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl" + +/// +/// 0 = Firmware MUST clear the MOR bit +/// 1 = Firmware MUST set the MOR bit +/// +#define MOR_CLEAR_MEMORY_BIT_MASK 0x01 + +/// +/// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS. +/// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS. +/// +#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10 + +/// +/// MOR field bit offset +/// +#define MOR_CLEAR_MEMORY_BIT_OFFSET 0 +#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4 + +/** + Return the ClearMemory bit value 0 or 1. + + @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit. + + @return ClearMemory bit value +**/ +#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET) + +/** + Return the DisableAutoDetect bit value 0 or 1. + + @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit. + + @return DisableAutoDetect bit value +**/ +#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET) + +extern EFI_GUID gEfiMemoryOverwriteControlDataGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Mps.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Mps.h new file mode 100644 index 0000000000..48f52b0e2b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/Mps.h @@ -0,0 +1,29 @@ +/** @file + GUIDs used for MPS entries in the UEFI 2.0 system table + ACPI is the primary means of exporting MPS information to the OS. MPS only was + included to support Itanium-based platform power on. So don't use it if you don't have too. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.0 spec. + +**/ + +#ifndef __MPS_GUID_H__ +#define __MPS_GUID_H__ + +#define EFI_MPS_TABLE_GUID \ + { \ + 0xeb9d2d2f, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +// +// GUID name defined in spec. +// +#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID + +extern EFI_GUID gEfiMpsTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/PcAnsi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/PcAnsi.h new file mode 100644 index 0000000000..312df6bd30 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/PcAnsi.h @@ -0,0 +1,52 @@ +/** @file + Terminal Device Path Vendor Guid. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.0 spec. + +**/ + +#ifndef __PC_ANSI_H__ +#define __PC_ANSI_H__ + +#define EFI_PC_ANSI_GUID \ + { \ + 0xe0c14753, 0xf9be, 0x11d2, {0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +#define EFI_VT_100_GUID \ + { \ + 0xdfa66065, 0xb419, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +#define EFI_VT_100_PLUS_GUID \ + { \ + 0x7baec70b, 0x57e0, 0x4c76, {0x8e, 0x87, 0x2f, 0x9e, 0x28, 0x08, 0x83, 0x43 } \ + } + +#define EFI_VT_UTF8_GUID \ + { \ + 0xad15a0d6, 0x8bec, 0x4acf, {0xa0, 0x73, 0xd0, 0x1d, 0xe7, 0x7e, 0x2d, 0x88 } \ + } + +#define DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL \ + { \ + 0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \ + } + +#define EFI_SAS_DEVICE_PATH_GUID \ + { \ + 0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \ + } + +extern EFI_GUID gEfiPcAnsiGuid; +extern EFI_GUID gEfiVT100Guid; +extern EFI_GUID gEfiVT100PlusGuid; +extern EFI_GUID gEfiVTUTF8Guid; +extern EFI_GUID gEfiUartDevicePathGuid; +extern EFI_GUID gEfiSasDevicePathGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/RtPropertiesTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/RtPropertiesTable.h new file mode 100644 index 0000000000..9bad51f2cf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/RtPropertiesTable.h @@ -0,0 +1,69 @@ +/** @file +Guid & data structure for EFI_RT _PROPERTIES_TABLE, designed to be published by a +platform if it no longer supports all EFI runtime services once ExitBootServices() +has been called by the OS. Introduced in UEFI 2.8a. + + +Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RT_PROPERTIES_TABLE_GUID_H__ +#define __RT_PROPERTIES_TABLE_GUID_H__ + +// +// Table, defined here, should be published by a platform if it no longer supports all EFI runtime +// services once ExitBootServices() has been called by the OS. Note that this is merely a hint +// to the OS, which it is free to ignore, and so the platform is still required to provide callable +// implementations of unsupported runtime services that simply return EFI_UNSUPPORTED. +// +#define EFI_RT_PROPERTIES_TABLE_GUID \ + { 0xeb66918a, 0x7eef, 0x402a, \ + { 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }} + + + + +#pragma pack(1) + +typedef struct { + /// + /// Version of the structure, must be 0x1. + /// + UINT16 Version; + + /// + /// Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8. + /// + UINT16 Length; + + /// + /// Bitmask of which calls are or are not supported, where a bit set to 1 indicates + /// that the call is supported, and 0 indicates that it is not. + /// + UINT32 RuntimeServicesSupported; +} EFI_RT_PROPERTIES_TABLE; + +#pragma pack() + +#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1 + +#define EFI_RT_SUPPORTED_GET_TIME 0x0001 +#define EFI_RT_SUPPORTED_SET_TIME 0x0002 +#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME 0x0004 +#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME 0x0008 +#define EFI_RT_SUPPORTED_GET_VARIABLE 0x0010 +#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME 0x0020 +#define EFI_RT_SUPPORTED_SET_VARIABLE 0x0040 +#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP 0x0080 +#define EFI_RT_SUPPORTED_CONVERT_POINTER 0x0100 +#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT 0x0200 +#define EFI_RT_SUPPORTED_RESET_SYSTEM 0x0400 +#define EFI_RT_SUPPORTED_UPDATE_CAPSULE 0x0800 +#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000 +#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000 + +extern EFI_GUID gEfiRtPropertiesTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmBios.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmBios.h new file mode 100644 index 0000000000..9040e3b5ad --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmBios.h @@ -0,0 +1,32 @@ +/** @file + GUIDs used to locate the SMBIOS tables in the UEFI 2.5 system table. + + These GUIDs in the system table are the only legal ways to search for and + locate the SMBIOS tables. Do not search the 0xF0000 segment to find SMBIOS + tables. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.5 spec. + +**/ + +#ifndef __SMBIOS_GUID_H__ +#define __SMBIOS_GUID_H__ + +#define SMBIOS_TABLE_GUID \ + { \ + 0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +#define SMBIOS3_TABLE_GUID \ + { \ + 0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 } \ + } + +extern EFI_GUID gEfiSmbiosTableGuid; +extern EFI_GUID gEfiSmbios3TableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmramMemoryReserve.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmramMemoryReserve.h new file mode 100644 index 0000000000..955b2fb0fe --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SmramMemoryReserve.h @@ -0,0 +1,45 @@ +/** @file + This is a special GUID extension Hob to describe SMRAM memory regions. + + This file defines: + * the GUID used to identify the GUID HOB for reserving SMRAM regions. + * the data structure of SMRAM descriptor to describe SMRAM candidate regions + * values of state of SMRAM candidate regions + * the GUID specific data structure of HOB for reserving SMRAM regions. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in PI SPEC version 1.5. + +**/ + +#ifndef _SMRAM_MEMORY_RESERVE_H_ +#define _SMRAM_MEMORY_RESERVE_H_ + +#define EFI_SMM_SMRAM_MEMORY_GUID \ + { \ + 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \ + } + +/** +* The GUID extension hob is to describe SMRAM memory regions supported by the platform. +**/ +typedef struct { + /// + /// Designates the number of possible regions in the system + /// that can be usable for SMRAM. + /// + UINT32 NumberOfSmmReservedRegions; + /// + /// Used throughout this protocol to describe the candidate + /// regions for SMRAM that are supported by this platform. + /// + EFI_SMRAM_DESCRIPTOR Descriptor[1]; +} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK; + +extern EFI_GUID gEfiSmmSmramMemoryGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/StatusCodeDataTypeId.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/StatusCodeDataTypeId.h new file mode 100644 index 0000000000..60114dffa4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/StatusCodeDataTypeId.h @@ -0,0 +1,803 @@ +/** @file + GUID used to identify id for the caller who is initiating the Status Code. + + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2 + Volume 3: Shared Architectural Elements + +**/ + +#ifndef __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__ +#define __PI_STATUS_CODE_DATA_TYPE_ID_GUID_H__ + +#include +#include + +/// +/// Global ID for the EFI_STATUS_CODE_STRING structure +/// +#define EFI_STATUS_CODE_DATA_TYPE_STRING_GUID \ + { 0x92D11080, 0x496F, 0x4D95, { 0xBE, 0x7E, 0x03, 0x74, 0x88, 0x38, 0x2B, 0x0A } } + +typedef enum { + /// + /// A NULL-terminated ASCII string. + /// + EfiStringAscii, + /// + /// A double NULL-terminated Unicode string. + /// + EfiStringUnicode, + /// + /// An EFI_STATUS_CODE_STRING_TOKEN representing the string. The actual + /// string can be obtained by querying the HII Database + /// + EfiStringToken +} EFI_STRING_TYPE; + +/// +/// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String. +/// +typedef struct { + /// + /// The HII package list which contains the string. Handle is a dynamic value that may + /// not be the same for different boots. Type EFI_HII_HANDLE is defined in + /// EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the UEFI Specification. + /// + EFI_HII_HANDLE Handle; + /// + /// When combined with Handle, the string token can be used to retrieve the string. + /// Type EFI_STRING_ID is defined in EFI_IFR_OP_HEADER in the UEFI Specification. + /// + EFI_STRING_ID Token; +} EFI_STATUS_CODE_STRING_TOKEN; + +typedef union { + /// + /// ASCII formatted string. + /// + CHAR8 *Ascii; + /// + /// Unicode formatted string. + /// + CHAR16 *Unicode; + /// + /// HII handle/token pair. + /// + EFI_STATUS_CODE_STRING_TOKEN Hii; +} EFI_STATUS_CODE_STRING; + +/// +/// This data type defines a string type of extended data. A string can accompany +/// any status code. The string can provide additional information about the +/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure +/// (HII) token/GUID pair. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and + /// DataHeader.Type should be + /// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// Specifies the format of the data in String. + /// + EFI_STRING_TYPE StringType; + /// + /// A pointer to the extended data. The data follows the format specified by + /// StringType. + /// + EFI_STATUS_CODE_STRING String; +} EFI_STATUS_CODE_STRING_DATA; + +extern EFI_GUID gEfiStatusCodeDataTypeStringGuid; + +/// +/// Global ID for the following structures: +/// - EFI_DEVICE_PATH_EXTENDED_DATA +/// - EFI_DEVICE_HANDLE_EXTENDED_DATA +/// - EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA +/// - EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA +/// - EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA +/// - EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA +/// - EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA +/// - EFI_MEMORY_RANGE_EXTENDED_DATA +/// - EFI_DEBUG_ASSERT_DATA +/// - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA +/// - EFI_STATUS_CODE_START_EXTENDED_DATA +/// - EFI_LEGACY_OPROM_EXTENDED_DATA +/// - EFI_RETURN_STATUS_EXTENDED_DATA +/// +#define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \ + { 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } } + +/// +/// Extended data about the device path, which is used for many errors and +/// progress codes to point to the device. +/// +/// The device path is used to point to the physical device in case there is more than one device +/// belonging to the same subclass. For example, the system may contain two USB keyboards and one +/// PS/2* keyboard. The driver that parses the status code can use the device path extended data to +/// differentiate between the three. The index field is not useful in this case because there is no standard +/// numbering convention. Device paths are preferred over using device handles because device handles +/// for a given device can change from one boot to another and do not mean anything beyond Boot +/// Services time. In certain cases, the bus driver may not create a device handle for a given device if it +/// detects a critical error. In these cases, the device path extended data can be used to refer to the +/// device, but there may not be any device handles with an instance of +/// EFI_DEVICE_PATH_PROTOCOL that matches DevicePath. The variable device path structure +/// is included in this structure to make it self sufficient. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA). DataHeader.Size should be the size + /// of variable-length DevicePath, and DataHeader.Size is zero for a virtual + /// device that does not have a device path. DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The device path to the controller or the hardware device. Note that this parameter is a + /// variable-length device path structure and not a pointer to such a structure. This structure is + /// populated only if it is a physical device. For virtual devices, the Size field in DataHeader + /// is set to zero and this field is not populated. + /// + // EFI_DEVICE_PATH_PROTOCOL DevicePath; +} EFI_DEVICE_PATH_EXTENDED_DATA; + +/// +/// Device handle Extended Data. Used for many +/// errors and progress codes to point to the device. +/// +/// The handle of the device with which the progress or error code is associated. The handle is +/// guaranteed to be accurate only at the time the status code is reported. Handles are dynamic entities +/// between boots, so handles cannot be considered to be valid if the system has reset subsequent to the +/// status code being reported. Handles may be used to determine a wide variety of useful information +/// about the source of the status code. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_DEVICE_HANDLE_EXTENDED_DATA) - HeaderSize, and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The device handle. + /// + EFI_HANDLE Handle; +} EFI_DEVICE_HANDLE_EXTENDED_DATA; + +/// +/// This structure defines extended data describing a PCI resource allocation error. +/// +/// @par Note: +/// The following structure contains variable-length fields and cannot be defined as a C-style +/// structure. +/// +/// This extended data conveys details for a PCI resource allocation failure error. See the PCI +/// specification and the ACPI specification for details on PCI resource allocations and the format for +/// resource descriptors. This error does not detail why the resource allocation failed. It may be due to a +/// bad resource request or a lack of available resources to satisfy a valid request. The variable device +/// path structure and the resource structures are included in this structure to make it self sufficient. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be sizeof + /// (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// (DevicePathSize + DevicePathSize + DevicePathSize + + /// sizeof(UINT32) + 3 * sizeof (UINT16) ), and DataHeader.Type + /// should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The PCI BAR. Applicable only for PCI devices. Ignored for all other devices. + /// + UINT32 Bar; + /// + /// DevicePathSize should be zero if it is a virtual device that is not associated with + /// a device path. Otherwise, this parameter is the length of the variable-length + /// DevicePath. + /// + UINT16 DevicePathSize; + /// + /// Represents the size the ReqRes parameter. ReqResSize should be zero if the + /// requested resources are not provided as a part of extended data. + /// + UINT16 ReqResSize; + /// + /// Represents the size the AllocRes parameter. AllocResSize should be zero if the + /// allocated resources are not provided as a part of extended data. + /// + UINT16 AllocResSize; + /// + /// The device path to the controller or the hardware device that did not get the requested + /// resources. Note that this parameter is the variable-length device path structure and not + /// a pointer to this structure. + /// + // EFI_DEVICE_PATH_PROTOCOL DevicePath; + /// + /// The requested resources in the format of an ACPI 2.0 resource descriptor. This + /// parameter is not a pointer; it is the complete resource descriptor. + /// + // UINT8 ReqRes[]; + /// + /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This + /// parameter is not a pointer; it is the complete resource descriptor. + /// + // UINT8 AllocRes[]; +} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA; + +/// +/// This structure provides a calculation for base-10 representations. +/// +/// Not consistent with PI 1.2 Specification. +/// This data type is not defined in the PI 1.2 Specification, but is +/// required by several of the other data structures in this file. +/// +typedef struct { + /// + /// The INT16 number by which to multiply the base-2 representation. + /// + INT16 Value; + /// + /// The INT16 number by which to raise the base-2 calculation. + /// + INT16 Exponent; +} EFI_EXP_BASE10_DATA; + +/// +/// This structure provides the voltage at the time of error. It also provides +/// the threshold value indicating the minimum or maximum voltage that is considered +/// an error. If the voltage is less then the threshold, the error indicates that the +/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold, +/// the error indicates that the voltage rose above the maximum acceptable value. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA) - + /// HeaderSize, and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The voltage value at the time of the error. + /// + EFI_EXP_BASE10_DATA Voltage; + /// + /// The voltage threshold. + /// + EFI_EXP_BASE10_DATA Threshold; +} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA; + +/// +/// Microcode Update Extended Error Data +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA) - + /// HeaderSize, and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The version of the microcode update from the header. + /// + UINT32 Version; +} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA; + +/// +/// This structure provides details about the computing unit timer expiration error. +/// The timer limit provides the timeout value of the timer prior to expiration. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) - + /// HeaderSize, and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The number of seconds that the computing unit timer was configured to expire. + /// + EFI_EXP_BASE10_DATA TimerLimit; +} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA; + +/// +/// Attribute bits for EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA.Attributes +/// All other attributes are reserved for future use and must be initialized to 0. +/// +///@{ +#define EFI_COMPUTING_UNIT_MISMATCH_SPEED 0x0001 +#define EFI_COMPUTING_UNIT_MISMATCH_FSB_SPEED 0x0002 +#define EFI_COMPUTING_UNIT_MISMATCH_FAMILY 0x0004 +#define EFI_COMPUTING_UNIT_MISMATCH_MODEL 0x0008 +#define EFI_COMPUTING_UNIT_MISMATCH_STEPPING 0x0010 +#define EFI_COMPUTING_UNIT_MISMATCH_CACHE_SIZE 0x0020 +#define EFI_COMPUTING_UNIT_MISMATCH_OEM1 0x1000 +#define EFI_COMPUTING_UNIT_MISMATCH_OEM2 0x2000 +#define EFI_COMPUTING_UNIT_MISMATCH_OEM3 0x4000 +#define EFI_COMPUTING_UNIT_MISMATCH_OEM4 0x8000 +///@} + +/// +/// This structure defines extended data for processor mismatch errors. +/// +/// This provides information to indicate which processors mismatch, and how they mismatch. The +/// status code contains the instance number of the processor that is in error. This structure's +/// Instance indicates the second processor that does not match. This differentiation allows the +/// consumer to determine which two processors do not match. The Attributes indicate what +/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be +/// reported with one error code. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) - + /// HeaderSize , and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The unit number of the computing unit that does not match. + /// + UINT32 Instance; + /// + /// The attributes describing the failure. + /// + UINT16 Attributes; +} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA; + +/// +/// This structure provides details about the computing unit thermal failure. +/// +/// This structure provides the temperature at the time of error. It also provides the threshold value +/// indicating the minimum temperature that is considered an error. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) - + /// HeaderSize , and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The thermal value at the time of the error. + /// + EFI_EXP_BASE10_DATA Temperature; + /// + /// The thermal threshold. + /// + EFI_EXP_BASE10_DATA Threshold; +} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA; + +/// +/// Enumeration of valid cache types +/// +typedef enum { + EfiInitCacheDataOnly, + EfiInitCacheInstrOnly, + EfiInitCacheBoth, + EfiInitCacheUnspecified +} EFI_INIT_CACHE_TYPE; + +/// +/// Embedded cache init extended data +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_CACHE_INIT_DATA) - HeaderSize , and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The cache level. Starts with 1 for level 1 cache. + /// + UINT32 Level; + /// + /// The type of cache. + /// + EFI_INIT_CACHE_TYPE Type; +} EFI_CACHE_INIT_DATA; + +/// +/// +/// +typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE; + +/// +/// The reasons that the processor is disabled. +/// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause. +/// +///@{ +#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001 +#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002 +#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004 +#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008 +#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010 +#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020 +#define EFI_CPU_CAUSE_USER_SELECTION 0x0080 +#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100 +#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000 +///@} + +/// +/// This structure provides information about the disabled computing unit. +/// +/// This structure provides details as to why and how the computing unit was disabled. The causes +/// should cover the typical reasons a processor would be disabled. How the processor was disabled is +/// important because there are distinct differences between hardware and software disabling. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA) - + /// HeaderSize, and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The reason for disabling the processor. + /// + UINT32 Cause; + /// + /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables. + /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware + /// disabled, which means it is invisible to software and will not respond to IPIs. + /// + BOOLEAN SoftwareDisabled; +} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA; + +/// +/// Memory Error Granularity Definition +/// +typedef UINT8 EFI_MEMORY_ERROR_GRANULARITY; + +/// +/// Memory Error Granularities. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Granularity. +/// +///@{ +#define EFI_MEMORY_ERROR_OTHER 0x01 +#define EFI_MEMORY_ERROR_UNKNOWN 0x02 +#define EFI_MEMORY_ERROR_DEVICE 0x03 +#define EFI_MEMORY_ERROR_PARTITION 0x04 +///@} + +/// +/// Memory Error Operation Definition +/// +typedef UINT8 EFI_MEMORY_ERROR_OPERATION; + +/// +/// Memory Error Operations. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Operation. +/// +///@{ +#define EFI_MEMORY_OPERATION_OTHER 0x01 +#define EFI_MEMORY_OPERATION_UNKNOWN 0x02 +#define EFI_MEMORY_OPERATION_READ 0x03 +#define EFI_MEMORY_OPERATION_WRITE 0x04 +#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05 +///@} + +/// +/// This structure provides specific details about the memory error that was detected. It provides +/// enough information so that consumers can identify the exact failure and provides enough +/// information to enable corrective action if necessary. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The error granularity type. + /// + EFI_MEMORY_ERROR_GRANULARITY Granularity; + /// + /// The operation that resulted in the error being detected. + /// + EFI_MEMORY_ERROR_OPERATION Operation; + /// + /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with + /// the error. If unknown, should be initialized to 0. + /// Inconsistent with specification here: + /// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged. + /// + UINTN Syndrome; + /// + /// The physical address of the error. + /// + EFI_PHYSICAL_ADDRESS Address; + /// + /// The range, in bytes, within which the error address can be determined. + /// + UINTN Resolution; +} EFI_MEMORY_EXTENDED_ERROR_DATA; + +/// +/// A definition to describe that the operation is performed on multiple devices within the array. +/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. +/// +#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe + +/// +/// A definition to describe that the operation is performed on all devices within the array. +/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. +/// +#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff + +/// +/// A definition to describe that the operation is performed on multiple arrays. +/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. +/// +#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe + +/// +/// A definition to describe that the operation is performed on all the arrays. +/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. +/// +#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff + +/// +/// This extended data provides some context that consumers can use to locate a DIMM within the +/// overall memory scheme. +/// +/// This extended data provides some context that consumers can use to locate a DIMM within the +/// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they +/// may be populated with the group definitions in "Related Definitions" below. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_STATUS_CODE_DIMM_NUMBER) - HeaderSize, and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The memory array number. + /// + UINT16 Array; + /// + /// The device number within that Array. + /// + UINT16 Device; +} EFI_STATUS_CODE_DIMM_NUMBER; + +/// +/// This structure defines extended data describing memory modules that do not match. +/// +/// This extended data may be used to convey the specifics of memory modules that do not match. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA) - + /// HeaderSize, and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The instance number of the memory module that does not match. + /// + EFI_STATUS_CODE_DIMM_NUMBER Instance; +} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA; + +/// +/// This structure defines extended data describing a memory range. +/// +/// This extended data may be used to convey the specifics of a memory range. Ranges are specified +/// with a start address and a length. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The starting address of the memory range. + /// + EFI_PHYSICAL_ADDRESS Start; + /// + /// The length in bytes of the memory range. + /// + EFI_PHYSICAL_ADDRESS Length; +} EFI_MEMORY_RANGE_EXTENDED_DATA; + +/// +/// This structure provides the assert information that is typically associated with a debug assertion failing. +/// +/// The data indicates the location of the assertion that failed in the source code. This information +/// includes the file name and line number that are necessary to find the failing assertion in source code. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The line number of the source file where the fault was generated. + /// + UINT32 LineNumber; + /// + /// The size in bytes of FileName. + /// + UINT32 FileNameSize; + /// + /// A pointer to a NULL-terminated ASCII or Unicode string that represents + /// the file name of the source file where the fault was generated. + /// + EFI_STATUS_CODE_STRING_DATA *FileName; +} EFI_DEBUG_ASSERT_DATA; + +/// +/// System Context Data EBC/IA32/IPF +/// +typedef union { + /// + /// The context of the EBC virtual machine when the exception was generated. Type + /// EFI_SYSTEM_CONTEXT_EBC is defined in EFI_DEBUG_SUPPORT_PROTOCOL + /// in the UEFI Specification. + /// + EFI_SYSTEM_CONTEXT_EBC SystemContextEbc; + /// + /// The context of the IA-32 processor when the exception was generated. Type + /// EFI_SYSTEM_CONTEXT_IA32 is defined in the + /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification. + /// + EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32; + /// + /// The context of the Itanium(R) processor when the exception was generated. Type + /// EFI_SYSTEM_CONTEXT_IPF is defined in the + /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification. + /// + EFI_SYSTEM_CONTEXT_IPF SystemContextIpf; + /// + /// The context of the X64 processor when the exception was generated. Type + /// EFI_SYSTEM_CONTEXT_X64 is defined in the + /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification. + /// + EFI_SYSTEM_CONTEXT_X64 SystemContextX64; + /// + /// The context of the ARM processor when the exception was generated. Type + /// EFI_SYSTEM_CONTEXT_ARM is defined in the + /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification. + /// + EFI_SYSTEM_CONTEXT_ARM SystemContextArm; +} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT; + +/// +/// This structure defines extended data describing a processor exception error. +/// +/// This extended data allows the processor context that is present at the time of the exception to be +/// reported with the exception. The format and contents of the context data varies depending on the +/// processor architecture. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize, + /// and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The system context. + /// + EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context; +} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA; + +/// +/// This structure defines extended data describing a call to a driver binding protocol start function. +/// +/// This extended data records information about a Start() function call. Start() is a member of +/// the UEFI Driver Binding Protocol. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize, + /// and DataHeader.Type should be + /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The controller handle. + /// + EFI_HANDLE ControllerHandle; + /// + /// The driver binding handle. + /// + EFI_HANDLE DriverBindingHandle; + /// + /// The size of the RemainingDevicePath. It is zero if the Start() function is + /// called with RemainingDevicePath = NULL. The UEFI Specification allows + /// that the Start() function of bus drivers can be called in this way. + /// + UINT16 DevicePathSize; + /// + /// Matches the RemainingDevicePath parameter being passed to the Start() function. + /// Note that this parameter is the variable-length device path and not a pointer + /// to the device path. + /// + // EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath; +} EFI_STATUS_CODE_START_EXTENDED_DATA; + +/// +/// This structure defines extended data describing a legacy option ROM (OpROM). +/// +/// The device handle and ROM image base can be used by consumers to determine which option ROM +/// failed. Due to the black-box nature of legacy option ROMs, the amount of information that can be +/// obtained may be limited. +/// +typedef struct { + /// + /// The data header identifying the data. DataHeader.HeaderSize should be + /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be + /// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The handle corresponding to the device that this legacy option ROM is being invoked. + /// + EFI_HANDLE DeviceHandle; + /// + /// The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area. + /// + EFI_PHYSICAL_ADDRESS RomImageBase; +} EFI_LEGACY_OPROM_EXTENDED_DATA; + +/// +/// This structure defines extended data describing an EFI_STATUS return value that stands for a +/// failed function call (such as a UEFI boot service). +/// +typedef struct { + /// + /// The data header identifying the data: + /// DataHeader.HeaderSize should be sizeof(EFI_STATUS_CODE_DATA), + /// DataHeader.Size should be sizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize, + /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID. + /// + EFI_STATUS_CODE_DATA DataHeader; + /// + /// The EFI_STATUS return value of the service or function whose failure triggered the + /// reporting of the status code (generally an error code or a debug code). + /// + EFI_STATUS ReturnStatus; +} EFI_RETURN_STATUS_EXTENDED_DATA; + +extern EFI_GUID gEfiStatusCodeSpecificDataGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SystemResourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SystemResourceTable.h new file mode 100644 index 0000000000..28041886d2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/SystemResourceTable.h @@ -0,0 +1,133 @@ +/** @file + Guid & data structure used for EFI System Resource Table (ESRT) + + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUIDs defined in UEFI 2.5 spec. + +**/ + + +#ifndef _SYSTEM_RESOURCE_TABLE_H__ +#define _SYSTEM_RESOURCE_TABLE_H__ + +#define EFI_SYSTEM_RESOURCE_TABLE_GUID \ + { \ + 0xb122a263, 0x3661, 0x4f68, {0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } \ + } + +/// +/// Current Entry Version +/// +#define EFI_SYSTEM_RESOURCE_TABLE_FIRMWARE_RESOURCE_VERSION 1 + +/// +/// Firmware Type Definitions +/// +#define ESRT_FW_TYPE_UNKNOWN 0x00000000 +#define ESRT_FW_TYPE_SYSTEMFIRMWARE 0x00000001 +#define ESRT_FW_TYPE_DEVICEFIRMWARE 0x00000002 +#define ESRT_FW_TYPE_UEFIDRIVER 0x00000003 + +/// +/// Last Attempt Status Values +/// +#define LAST_ATTEMPT_STATUS_SUCCESS 0x00000000 +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL 0x00000001 +#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES 0x00000002 +#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION 0x00000003 +#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT 0x00000004 +#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR 0x00000005 +#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC 0x00000006 +#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT 0x00000007 +#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES 0x00000008 + +/// +/// LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX is defined as +/// 0x4000 as of UEFI Specification 2.8B. This will be modified in the +/// future to the correct value 0x3FFF. To ensure correct implementation, +/// this change is preemptively made in the value defined below. +/// +/// When the UEFI Specification is updated, this comment block can be +/// removed. +/// +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000 +#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF + +typedef struct { + /// + /// The firmware class field contains a GUID that identifies a firmware component + /// that can be updated via UpdateCapsule(). This GUID must be unique within all + /// entries of the ESRT. + /// + EFI_GUID FwClass; + /// + /// Identifies the type of firmware resource. + /// + UINT32 FwType; + /// + /// The firmware version field represents the current version of the firmware + /// resource, value must always increase as a larger number represents a newer + /// version. + /// + UINT32 FwVersion; + /// + /// The lowest firmware resource version to which a firmware resource can be + /// rolled back for the given system/device. Generally this is used to protect + /// against known and fixed security issues. + /// + UINT32 LowestSupportedFwVersion; + /// + /// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined + /// in the EFI_CAPSULE_HEADER that will be set in the capsule header. + /// + UINT32 CapsuleFlags; + /// + /// The last attempt version field describes the last firmware version for which + /// an update was attempted (uses the same format as Firmware Version). + /// Last Attempt Version is updated each time an UpdateCapsule() is attempted for + /// an ESRT entry and is preserved across reboots (non-volatile). However, in + /// cases where the attempt version is not recorded due to limitations in the + /// update process, the field shall set to zero after a failed update. Similarly, + /// in the case of a removable device, this value is set to 0 in cases where the + /// device has not been updated since being added to the system. + /// + UINT32 LastAttemptVersion; + /// + /// The last attempt status field describes the result of the last firmware update + /// attempt for the firmware resource entry. + /// LastAttemptStatus is updated each time an UpdateCapsule() is attempted for an + /// ESRT entry and is preserved across reboots (non-volatile). + /// If a firmware update has never been attempted or is unknown, for example after + /// fresh insertion of a removable device, LastAttemptStatus must be set to Success. + /// + UINT32 LastAttemptStatus; +} EFI_SYSTEM_RESOURCE_ENTRY; + +typedef struct { + /// + /// The number of firmware resources in the table, must not be zero. + /// + UINT32 FwResourceCount; + /// + /// The maximum number of resource array entries that can be within the table + /// without reallocating the table, must not be zero. + /// + UINT32 FwResourceCountMax; + /// + /// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table. + /// This field should be set to 1. + /// + UINT64 FwResourceVersion; + /// + /// Array of EFI_SYSTEM_RESOURCE_ENTRY + /// + //EFI_SYSTEM_RESOURCE_ENTRY Entries[]; +} EFI_SYSTEM_RESOURCE_TABLE; + +extern EFI_GUID gEfiSystemResourceTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/VectorHandoffTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/VectorHandoffTable.h new file mode 100644 index 0000000000..874f9f62c7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/VectorHandoffTable.h @@ -0,0 +1,27 @@ +/** @file + GUID for system configuration table entry that points to the table + in case an entity in DXE wishes to update/change the vector table contents. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in PI 1.2.1 spec. +**/ + +#ifndef __EFI_VECTOR_HANDOFF_TABLE_H__ +#define __EFI_VECTOR_HANDOFF_TABLE_H__ + +#include + +// +// System configuration table entry that points to the table +// in case an entity in DXE wishes to update/change the vector +// table contents. +// +#define EFI_VECTOR_HANDOF_TABLE_GUID \ + { 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }} + +extern EFI_GUID gEfiVectorHandoffTableGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/WinCertificate.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/WinCertificate.h new file mode 100644 index 0000000000..c44bb388cc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Guid/WinCertificate.h @@ -0,0 +1,122 @@ +/** @file + GUID for UEFI WIN_CERTIFICATE structure. + + Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + GUID defined in UEFI 2.0 spec. +**/ + +#ifndef __EFI_WIN_CERTIFICATE_H__ +#define __EFI_WIN_CERTIFICATE_H__ + +// +// _WIN_CERTIFICATE.wCertificateType +// +#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002 +#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0 +#define WIN_CERT_TYPE_EFI_GUID 0x0EF1 + +/// +/// The WIN_CERTIFICATE structure is part of the PE/COFF specification. +/// +typedef struct { + /// + /// The length of the entire certificate, + /// including the length of the header, in bytes. + /// + UINT32 dwLength; + /// + /// The revision level of the WIN_CERTIFICATE + /// structure. The current revision level is 0x0200. + /// + UINT16 wRevision; + /// + /// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI + /// certificate types. The UEFI specification reserves the range of + /// certificate type values from 0x0EF0 to 0x0EFF. + /// + UINT16 wCertificateType; + /// + /// The following is the actual certificate. The format of + /// the certificate depends on wCertificateType. + /// + /// UINT8 bCertificate[ANYSIZE_ARRAY]; + /// +} WIN_CERTIFICATE; + +/// +/// WIN_CERTIFICATE_UEFI_GUID.CertType +/// +#define EFI_CERT_TYPE_RSA2048_SHA256_GUID \ + {0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf } } + +/// +/// WIN_CERTIFICATE_UEFI_GUID.CertData +/// +typedef struct { + EFI_GUID HashType; + UINT8 PublicKey[256]; + UINT8 Signature[256]; +} EFI_CERT_BLOCK_RSA_2048_SHA256; + + +/// +/// Certificate which encapsulates a GUID-specific digital signature +/// +typedef struct { + /// + /// This is the standard WIN_CERTIFICATE header, where + /// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID. + /// + WIN_CERTIFICATE Hdr; + /// + /// This is the unique id which determines the + /// format of the CertData. . + /// + EFI_GUID CertType; + /// + /// The following is the certificate data. The format of + /// the data is determined by the CertType. + /// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID, + /// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure. + /// + UINT8 CertData[1]; +} WIN_CERTIFICATE_UEFI_GUID; + + +/// +/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature. +/// +/// The WIN_CERTIFICATE_UEFI_PKCS1_15 structure is derived from +/// WIN_CERTIFICATE and encapsulate the information needed to +/// implement the RSASSA-PKCS1-v1_5 digital signature algorithm as +/// specified in RFC2437. +/// +typedef struct { + /// + /// This is the standard WIN_CERTIFICATE header, where + /// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15. + /// + WIN_CERTIFICATE Hdr; + /// + /// This is the hashing algorithm which was performed on the + /// UEFI executable when creating the digital signature. + /// + EFI_GUID HashAlgorithm; + /// + /// The following is the actual digital signature. The + /// size of the signature is the same size as the key + /// (1024-bit key is 128 bytes) and can be determined by + /// subtracting the length of the other parts of this header + /// from the total length of the certificate as found in + /// Hdr.dwLength. + /// + /// UINT8 Signature[]; + /// +} WIN_CERTIFICATE_EFI_PKCS1_15; + +extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/Nasm.inc b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/Nasm.inc new file mode 100644 index 0000000000..8ff5193520 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/Nasm.inc @@ -0,0 +1,72 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Abstract: +; +; This file provides macro definitions for NASM files. +; +;------------------------------------------------------------------------------ + +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_EAX 0 + DB 0x67, 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_EAX 0 + DB 0x67, 0xF3, 0x0F, 0x01, 0x28 +%endmacro + +%macro SETSSBSY 0 + DB 0xF3, 0x0F, 0x01, 0xE8 +%endmacro + +%macro READSSP_EAX 0 + DB 0xF3, 0x0F, 0x1E, 0xC8 +%endmacro + +%macro INCSSP_EAX 0 + DB 0xF3, 0x0F, 0xAE, 0xE8 +%endmacro + +; NASM provides built-in macros STRUC and ENDSTRUC for structure definition. +; For example, to define a structure called mytype containing a longword, +; a word, a byte and a string of bytes, you might code +; +; struc mytype +; +; mt_long: resd 1 +; mt_word: resw 1 +; mt_byte: resb 1 +; mt_str: resb 32 +; +; endstruc +; +; Below macros are help to map the C types and the RESB family of pseudo-instructions. +; So that the above structure definition can be coded as +; +; struc mytype +; +; mt_long: CTYPE_UINT32 1 +; mt_word: CTYPE_UINT16 1 +; mt_byte: CTYPE_UINT8 1 +; mt_str: CTYPE_CHAR8 32 +; +; endstruc +%define CTYPE_UINT64 resq +%define CTYPE_INT64 resq +%define CTYPE_UINT32 resd +%define CTYPE_INT32 resd +%define CTYPE_UINT16 resw +%define CTYPE_INT16 resw +%define CTYPE_BOOLEAN resb +%define CTYPE_UINT8 resb +%define CTYPE_CHAR8 resb +%define CTYPE_INT8 resb + +%define CTYPE_UINTN resd +%define CTYPE_INTN resd diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/ProcessorBind.h new file mode 100644 index 0000000000..b10c641efd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ia32/ProcessorBind.h @@ -0,0 +1,322 @@ +/** @file + Processor or Compiler specific defines and types for IA-32 architecture. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices. +/// +#define MDE_CPU_IA32 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +#if defined(__INTEL_COMPILER) +// +// Disable ICC's remark #869: "Parameter" was never referenced warning. +// This is legal ANSI C code so we disable the remark that is turned on with -Wall +// +#pragma warning ( disable : 869 ) + +// +// Disable ICC's remark #1418: external function definition with no prior declaration. +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 1418 ) + +// +// Disable ICC's remark #1419: external declaration in primary source file +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 1419 ) + +// +// Disable ICC's remark #593: "Variable" was set but never used. +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 593 ) + +#endif + + +#if defined(_MSC_EXTENSIONS) + +// +// Disable warning that make it impossible to compile at /W4 +// This only works for Microsoft* tools +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompiled header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For precompiled header only. +// +#pragma warning ( disable : 4206 ) + +#if defined(_MSC_VER) && _MSC_VER >= 1800 + +// +// Disable these warnings for VS2013. +// + +// +// This warning is for potentially uninitialized local variable, and it may cause false +// positive issues in VS2013 and VS2015 build +// +#pragma warning ( disable : 4701 ) + +// +// This warning is for potentially uninitialized local pointer variable, and it may cause +// false positive issues in VS2013 and VS2015 build +// +#pragma warning ( disable : 4703 ) + +#endif + +#endif + + +#if defined(_MSC_EXTENSIONS) + + // + // use Microsoft C compiler dependent integer width types + // + + /// + /// 8-byte unsigned value. + /// + typedef unsigned __int64 UINT64; + /// + /// 8-byte signed value. + /// + typedef __int64 INT64; + /// + /// 4-byte unsigned value. + /// + typedef unsigned __int32 UINT32; + /// + /// 4-byte signed value. + /// + typedef __int32 INT32; + /// + /// 2-byte unsigned value. + /// + typedef unsigned short UINT16; + /// + /// 2-byte Character. Unless otherwise specified all strings are stored in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. + /// + typedef unsigned short CHAR16; + /// + /// 2-byte signed value. + /// + typedef short INT16; + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value. + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character. + /// + typedef char CHAR8; + /// + /// 1-byte signed value. + /// + typedef signed char INT8; +#else + /// + /// 8-byte unsigned value. + /// + typedef unsigned long long UINT64; + /// + /// 8-byte signed value. + /// + typedef long long INT64; + /// + /// 4-byte unsigned value. + /// + typedef unsigned int UINT32; + /// + /// 4-byte signed value. + /// + typedef int INT32; + /// + /// 2-byte unsigned value. + /// + typedef unsigned short UINT16; + /// + /// 2-byte Character. Unless otherwise specified all strings are stored in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. + /// + typedef unsigned short CHAR16; + /// + /// 2-byte signed value. + /// + typedef short INT16; + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value. + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character + /// + typedef char CHAR8; + /// + /// 1-byte signed value + /// + typedef signed char INT8; +#endif + +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions; +/// 8 bytes on supported 64-bit processor instructions.) +/// +typedef UINT32 UINTN; +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions; +/// 8 bytes on supported 64-bit processor instructions.) +/// +typedef INT32 INTN; + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x80000000 +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC0000000 + +/// +/// Maximum legal IA-32 address. +/// +#define MAX_ADDRESS 0xFFFFFFFF + +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + +/// +/// Maximum legal IA-32 INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFF) +#define MAX_UINTN ((UINTN)0xFFFFFFFF) + +/// +/// Minimum legal IA-32 INTN value. +/// +#define MIN_INTN (((INTN)-2147483647) - 1) + +/// +/// The stack alignment required for IA-32. +/// +#define CPU_STACK_ALIGNMENT sizeof(UINTN) + +/// +/// Page allocation granularity for IA-32. +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(_MSC_EXTENSIONS) + /// + /// Microsoft* compiler specific method for EFIAPI calling convention. + /// + #define EFIAPI __cdecl +#elif defined(__GNUC__) || defined(__clang__) + /// + /// GCC specific method for EFIAPI calling convention. + /// + #define EFIAPI __attribute__((cdecl)) +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) || defined(__clang__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On IA-32 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ _ +#endif + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi.h new file mode 100644 index 0000000000..929d259c83 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi.h @@ -0,0 +1,16 @@ +/** @file + This file contains the latest ACPI definitions that are + consumed by drivers that do not care about ACPI versions. + + Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ACPI_H_ +#define _ACPI_H_ + +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi10.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi10.h new file mode 100644 index 0000000000..7a09adc2a1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi10.h @@ -0,0 +1,666 @@ +/** @file + ACPI 1.0b definitions from the ACPI Specification, revision 1.0b + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Arm Limited. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_1_0_H_ +#define _ACPI_1_0_H_ + +#include + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure. +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_COMMON_HEADER; + +#pragma pack(1) +/// +/// The common ACPI description table header. This structure prefaces most ACPI tables. +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OemId[6]; + UINT64 OemTableId; + UINT32 OemRevision; + UINT32 CreatorId; + UINT32 CreatorRevision; +} EFI_ACPI_DESCRIPTION_HEADER; +#pragma pack() + +// +// Define for Descriptor +// +#define ACPI_SMALL_ITEM_FLAG 0x00 +#define ACPI_LARGE_ITEM_FLAG 0x01 + +// +// Small Item Descriptor Name +// +#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04 +#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05 +#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06 +#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07 +#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08 +#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09 +#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E +#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F + +// +// Large Item Descriptor Name +// +#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01 +#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04 +#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05 +#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06 +#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07 +#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08 +#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09 +#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A + +// +// Small Item Descriptor Value +// +#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22 +#define ACPI_IRQ_DESCRIPTOR 0x23 +#define ACPI_DMA_DESCRIPTOR 0x2A +#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30 +#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31 +#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38 +#define ACPI_IO_PORT_DESCRIPTOR 0x47 +#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B +#define ACPI_END_TAG_DESCRIPTOR 0x79 + +// +// Large Item Descriptor Value +// +#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81 +#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85 +#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86 +#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87 +#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88 +#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89 +#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A +#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A + +// +// Resource Type +// +#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00 +#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01 +#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02 + +/// +/// Power Management Timer frequency is fixed at 3.579545MHz. +/// +#define ACPI_TIMER_FREQUENCY 3579545 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// The common definition of QWORD, DWORD, and WORD +/// Address Space Descriptors. +/// +typedef PACKED struct { + UINT8 Desc; + UINT16 Len; + UINT8 ResType; + UINT8 GenFlag; + UINT8 SpecificFlag; + UINT64 AddrSpaceGranularity; + UINT64 AddrRangeMin; + UINT64 AddrRangeMax; + UINT64 AddrTranslationOffset; + UINT64 AddrLen; +} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR; + +typedef PACKED union { + UINT8 Byte; + PACKED struct { + UINT8 Length : 3; + UINT8 Name : 4; + UINT8 Type : 1; + } Bits; +} ACPI_SMALL_RESOURCE_HEADER; + +typedef PACKED struct { + PACKED union { + UINT8 Byte; + PACKED struct { + UINT8 Name : 7; + UINT8 Type : 1; + }Bits; + } Header; + UINT16 Length; +} ACPI_LARGE_RESOURCE_HEADER; + +/// +/// IRQ Descriptor. +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT16 Mask; +} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR; + +/// +/// IRQ Descriptor. +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT16 Mask; + UINT8 Information; +} EFI_ACPI_IRQ_DESCRIPTOR; + +/// +/// DMA Descriptor. +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT8 ChannelMask; + UINT8 Information; +} EFI_ACPI_DMA_DESCRIPTOR; + +/// +/// I/O Port Descriptor +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT8 Information; + UINT16 BaseAddressMin; + UINT16 BaseAddressMax; + UINT8 Alignment; + UINT8 Length; +} EFI_ACPI_IO_PORT_DESCRIPTOR; + +/// +/// Fixed Location I/O Port Descriptor. +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT16 BaseAddress; + UINT8 Length; +} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR; + +/// +/// 24-Bit Memory Range Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 Information; + UINT16 BaseAddressMin; + UINT16 BaseAddressMax; + UINT16 Alignment; + UINT16 Length; +} EFI_ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR; + +/// +/// 32-Bit Memory Range Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 Information; + UINT32 BaseAddressMin; + UINT32 BaseAddressMax; + UINT32 Alignment; + UINT32 Length; +} EFI_ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR; + +/// +/// Fixed 32-Bit Fixed Memory Range Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 Information; + UINT32 BaseAddress; + UINT32 Length; +} EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR; + +/// +/// QWORD Address Space Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 ResType; + UINT8 GenFlag; + UINT8 SpecificFlag; + UINT64 AddrSpaceGranularity; + UINT64 AddrRangeMin; + UINT64 AddrRangeMax; + UINT64 AddrTranslationOffset; + UINT64 AddrLen; +} EFI_ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR; + +/// +/// DWORD Address Space Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 ResType; + UINT8 GenFlag; + UINT8 SpecificFlag; + UINT32 AddrSpaceGranularity; + UINT32 AddrRangeMin; + UINT32 AddrRangeMax; + UINT32 AddrTranslationOffset; + UINT32 AddrLen; +} EFI_ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR; + +/// +/// WORD Address Space Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 ResType; + UINT8 GenFlag; + UINT8 SpecificFlag; + UINT16 AddrSpaceGranularity; + UINT16 AddrRangeMin; + UINT16 AddrRangeMax; + UINT16 AddrTranslationOffset; + UINT16 AddrLen; +} EFI_ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR; + +/// +/// Extended Interrupt Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 InterruptVectorFlags; + UINT8 InterruptTableLength; + UINT32 InterruptNumber[1]; +} EFI_ACPI_EXTENDED_INTERRUPT_DESCRIPTOR; + +#pragma pack() + +/// +/// The End tag identifies an end of resource data. +/// +typedef struct { + UINT8 Desc; + UINT8 Checksum; +} EFI_ACPI_END_TAG_DESCRIPTOR; + +// +// General use definitions +// +#define EFI_ACPI_RESERVED_BYTE 0x00 +#define EFI_ACPI_RESERVED_WORD 0x0000 +#define EFI_ACPI_RESERVED_DWORD 0x00000000 +#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000 + +// +// Resource Type Specific Flags +// Ref ACPI specification 6.4.3.5.5 +// +// Bit [0] : Write Status, _RW +// +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0) +// +// Bit [2:1] : Memory Attributes, _MEM +// +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1) +// +// Bit [4:3] : Memory Attributes, _MTP +// +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3) +#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3) +// +// Bit [5] : Memory to I/O Translation, _TTP +// +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5) +#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5) + +// +// IRQ Information +// Ref ACPI specification 6.4.2.1 +// +#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10 +#define EFI_ACPI_IRQ_SHARABLE 0x10 + +#define EFI_ACPI_IRQ_POLARITY_MASK 0x08 +#define EFI_ACPI_IRQ_HIGH_TRUE 0x00 +#define EFI_ACPI_IRQ_LOW_FALSE 0x08 + +#define EFI_ACPI_IRQ_MODE 0x01 +#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00 +#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01 + +// +// DMA Information +// Ref ACPI specification 6.4.2.2 +// +#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60 +#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00 +#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20 +#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40 +#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60 + +#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04 +#define EFI_ACPI_DMA_BUS_MASTER 0x04 + +#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03 +#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00 +#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01 +#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02 + +// +// IO Information +// Ref ACPI specification 6.4.2.5 +// +#define EFI_ACPI_IO_DECODE_MASK 0x01 +#define EFI_ACPI_IO_DECODE_16_BIT 0x01 +#define EFI_ACPI_IO_DECODE_10_BIT 0x00 + +// +// Memory Information +// Ref ACPI specification 6.4.3.4 +// +#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01 +#define EFI_ACPI_MEMORY_WRITABLE 0x01 +#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00 + +// +// Interrupt Vector Flags definitions for Extended Interrupt Descriptor +// Ref ACPI specification 6.4.3.6 +// +#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0 +#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1 +#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2 +#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3 +#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4 + +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI 1.0b table structures +// + +/// +/// Root System Description Pointer Structure. +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Reserved; + UINT32 RsdtAddress; +} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 1.0b specification). +/// +#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT). +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 IntModel; + UINT8 Reserved1; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 Reserved2; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 Reserved3; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT8 Reserved4; + UINT8 Reserved5; + UINT8 Reserved6; + UINT32 Flags; +} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 1.0b specification). +/// +#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01 + +#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0 +#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_1_0_WBINVD BIT0 +#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_1_0_PROC_C1 BIT2 +#define EFI_ACPI_1_0_P_LVL2_UP BIT3 +#define EFI_ACPI_1_0_PWR_BUTTON BIT4 +#define EFI_ACPI_1_0_SLP_BUTTON BIT5 +#define EFI_ACPI_1_0_FIX_RTC BIT6 +#define EFI_ACPI_1_0_RTC_S4 BIT7 +#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_1_0_DCK_CAP BIT9 + +/// +/// Firmware ACPI Control Structure. +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT8 Reserved[40]; +} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// Firmware Control Structure Feature Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_1_0_S4BIOS_F BIT0 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform-specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 1.0b specification). +/// +#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_1_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x05 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_1_0_IO_APIC 0x01 +#define EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_1_0_LOCAL_APIC_NMI 0x04 + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 SystemVectorBase; +} EFI_ACPI_1_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterruptVector; + UINT16 Flags; +} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Non-Maskable Interrupt Source Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterruptVector; +} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicInti; +} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer. +/// +#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table. +/// +#define EFI_ACPI_1_0_APIC_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "DSDT" Differentiated System Description Table. +/// +#define EFI_ACPI_1_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "FACS" Firmware ACPI Control Structure. +/// +#define EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FACP" Fixed ACPI Description Table. +/// +#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "PSDT" Persistent System Description Table. +/// +#define EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RSDT" Root System Description Table. +/// +#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table. +/// +#define EFI_ACPI_1_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SSDT" Secondary System Description Table. +/// +#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi20.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi20.h new file mode 100644 index 0000000000..b4e19ae56e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi20.h @@ -0,0 +1,539 @@ +/** @file + ACPI 2.0 definitions from the ACPI Specification, revision 2.0 + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_2_0_H_ +#define _ACPI_2_0_H_ + +#include + +// +// Define for Descriptor +// +#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02 + +#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Generic Register Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AddressSize; + UINT64 RegisterAddress; +} EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR; + +#pragma pack() + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 2.0 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 Reserved; + UINT64 Address; +} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_2_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_2_0_SYSTEM_IO 1 +#define EFI_ACPI_2_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_2_0_SMBUS 4 +#define EFI_ACPI_2_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// ACPI 2.0 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_2_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT8 Reserved2[3]; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; +} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0 +#define EFI_ACPI_2_0_8042 BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_2_0_WBINVD BIT0 +#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_2_0_PROC_C1 BIT2 +#define EFI_ACPI_2_0_P_LVL2_UP BIT3 +#define EFI_ACPI_2_0_PWR_BUTTON BIT4 +#define EFI_ACPI_2_0_SLP_BUTTON BIT5 +#define EFI_ACPI_2_0_FIX_RTC BIT6 +#define EFI_ACPI_2_0_RTC_S4 BIT7 +#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_2_0_DCK_CAP BIT9 +#define EFI_ACPI_2_0_RESET_REG_SUP BIT10 +#define EFI_ACPI_2_0_SEALED_CASE BIT11 +#define EFI_ACPI_2_0_HEADLESS BIT12 +#define EFI_ACPI_2_0_CPU_SW_SLP BIT13 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved[31]; +} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_2_0_S4BIOS_F BIT0 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_2_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x09 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_2_0_IO_APIC 0x01 +#define EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_2_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_2_0_IO_SAPIC 0x06 +#define EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC 0x07 +#define EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES 0x08 + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_2_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; +} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 Reserved; +} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 2.0 spec.) +/// +#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "SPIC" Multiple SAPIC Description Table +/// +/// BUGBUG: Don't know where this came from except SR870BN4 uses it. +/// #define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE 0x43495053 +/// +#define EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_2_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "DBGP" MS Bebug Port Spec +/// +#define EFI_ACPI_2_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_2_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_2_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_2_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SRAT" Static Resource Affinity Table +/// +#define EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_2_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi30.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi30.h new file mode 100644 index 0000000000..4ef7bec7a5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi30.h @@ -0,0 +1,723 @@ +/** @file + ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006 + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_3_0_H_ +#define _ACPI_3_0_H_ + +#include + +// +// Define for Descriptor +// +#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B + +#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Extended Address Space Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 ResType; + UINT8 GenFlag; + UINT8 SpecificFlag; + UINT8 RevisionId; + UINT8 Reserved; + UINT64 AddrSpaceGranularity; + UINT64 AddrRangeMin; + UINT64 AddrRangeMax; + UINT64 AddrTranslationOffset; + UINT64 AddrLen; + UINT64 TypeSpecificAttribute; +} EFI_ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR; + +#pragma pack() + +// +// Memory Type Specific Flags +// +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001 +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002 +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004 +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008 +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010 +#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 3.0 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_3_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_3_0_SYSTEM_IO 1 +#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_3_0_SMBUS 4 +#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_3_0_UNDEFINED 0 +#define EFI_ACPI_3_0_BYTE 1 +#define EFI_ACPI_3_0_WORD 2 +#define EFI_ACPI_3_0_DWORD 3 +#define EFI_ACPI_3_0_QWORD 4 + +// +// ACPI 3.0 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 3.0b spec.) +/// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_3_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT8 Reserved2[3]; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; +} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0 +#define EFI_ACPI_3_0_8042 BIT1 +#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_WBINVD BIT0 +#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_3_0_PROC_C1 BIT2 +#define EFI_ACPI_3_0_P_LVL2_UP BIT3 +#define EFI_ACPI_3_0_PWR_BUTTON BIT4 +#define EFI_ACPI_3_0_SLP_BUTTON BIT5 +#define EFI_ACPI_3_0_FIX_RTC BIT6 +#define EFI_ACPI_3_0_RTC_S4 BIT7 +#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_3_0_DCK_CAP BIT9 +#define EFI_ACPI_3_0_RESET_REG_SUP BIT10 +#define EFI_ACPI_3_0_SEALED_CASE BIT11 +#define EFI_ACPI_3_0_HEADLESS BIT12 +#define EFI_ACPI_3_0_CPU_SW_SLP BIT13 +#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14 +#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved[31]; +} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_3_0_S4BIOS_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_3_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x09 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_3_0_IO_APIC 0x01 +#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_3_0_IO_SAPIC 0x06 +#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07 +#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08 + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_3_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_POLARITY (3 << 0) +#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02 + +// +// SRAT structure types. +// All other values between 0x02 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT8 Reserved[4]; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2) + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 3.0 spec.) +/// +#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_3_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WSPT" Windows Specific Properties Table +/// +#define EFI_ACPI_3_0_WINDOWS_SPECIFIC_PROPERTIES_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'P', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi40.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi40.h new file mode 100644 index 0000000000..cfd491d45d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi40.h @@ -0,0 +1,1303 @@ +/** @file + ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010 + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_4_0_H_ +#define _ACPI_4_0_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 4.0 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_4_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_4_0_SYSTEM_IO 1 +#define EFI_ACPI_4_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_4_0_SMBUS 4 +#define EFI_ACPI_4_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_4_0_UNDEFINED 0 +#define EFI_ACPI_4_0_BYTE 1 +#define EFI_ACPI_4_0_WORD 2 +#define EFI_ACPI_4_0_DWORD 3 +#define EFI_ACPI_4_0_QWORD 4 + +// +// ACPI 4.0 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 4.0b spec.) +/// +#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_4_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT8 Reserved2[3]; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; +} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_4_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_4_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_4_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_4_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_4_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_4_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_4_0_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER 7 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0 +#define EFI_ACPI_4_0_8042 BIT1 +#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_4_0_WBINVD BIT0 +#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_4_0_PROC_C1 BIT2 +#define EFI_ACPI_4_0_P_LVL2_UP BIT3 +#define EFI_ACPI_4_0_PWR_BUTTON BIT4 +#define EFI_ACPI_4_0_SLP_BUTTON BIT5 +#define EFI_ACPI_4_0_FIX_RTC BIT6 +#define EFI_ACPI_4_0_RTC_S4 BIT7 +#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_4_0_DCK_CAP BIT9 +#define EFI_ACPI_4_0_RESET_REG_SUP BIT10 +#define EFI_ACPI_4_0_SEALED_CASE BIT11 +#define EFI_ACPI_4_0_HEADLESS BIT12 +#define EFI_ACPI_4_0_CPU_SW_SLP BIT13 +#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14 +#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_4_0_S4BIOS_F BIT0 +#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_4_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0B an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_4_0_IO_APIC 0x01 +#define EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_4_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_4_0_IO_SAPIC 0x06 +#define EFI_ACPI_4_0_LOCAL_SAPIC 0x07 +#define EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_4_0_LOCAL_X2APIC_NMI 0x0A + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_4_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_4_0_POLARITY (3 << 0) +#define EFI_ACPI_4_0_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x03 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_4_0_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_4_0_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_4_0_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_4_0_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; +} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR 0x09 + +// +// Error Source structure flags. +// +#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03 +#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03 +#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_4_0_ERST_NOOP 0x04 +#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_4_0_ERST_ADD 0x08 +#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09 +#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_4_0_ERST_STALL 0x0C +#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_4_0_ERST_GOTO 0x0F +#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 4.0 spec.) +/// +#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_4_0_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_4_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_4_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_4_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_4_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_4_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_4_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_4_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_4_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_4_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_4_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_4_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_4_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_4_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Enlightenment Table +/// +#define EFI_ACPI_4_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_4_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_4_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi50.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi50.h new file mode 100644 index 0000000000..74795fcbe6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi50.h @@ -0,0 +1,2119 @@ +/** @file + ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013. + + Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_5_0_H_ +#define _ACPI_5_0_H_ + +#include + +// +// Define for Descriptor +// +#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A +#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C +#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E + +#define ACPI_FIXED_DMA_DESCRIPTOR 0x55 +#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C +#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E + +#pragma pack(1) + +/// +/// Generic DMA Descriptor. +/// +typedef PACKED struct { + ACPI_SMALL_RESOURCE_HEADER Header; + UINT16 DmaRequestLine; + UINT16 DmaChannel; + UINT8 DmaTransferWidth; +} EFI_ACPI_FIXED_DMA_DESCRIPTOR; + +/// +/// GPIO Connection Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT8 ConnectionType; + UINT16 GeneralFlags; + UINT16 InterruptFlags; + UINT8 PinConfiguration; + UINT16 OutputDriveStrength; + UINT16 DebounceTimeout; + UINT16 PinTableOffset; + UINT8 ResourceSourceIndex; + UINT16 ResourceSourceNameOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR; + +#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0 +#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1 + +/// +/// Serial Bus Resource Descriptor (Generic) +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT8 ResourceSourceIndex; + UINT8 SerialBusType; + UINT8 GeneralFlags; + UINT16 TypeSpecificFlags; + UINT8 TypeSpecificRevisionId; + UINT16 TypeDataLength; +// Type specific data +} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR; + +#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C 0x1 +#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_SPI 0x2 +#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_UART 0x3 + +/// +/// Serial Bus Resource Descriptor (I2C) +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT8 ResourceSourceIndex; + UINT8 SerialBusType; + UINT8 GeneralFlags; + UINT16 TypeSpecificFlags; + UINT8 TypeSpecificRevisionId; + UINT16 TypeDataLength; + UINT32 ConnectionSpeed; + UINT16 SlaveAddress; +} EFI_ACPI_SERIAL_BUS_RESOURCE_I2C_DESCRIPTOR; + +/// +/// Serial Bus Resource Descriptor (SPI) +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT8 ResourceSourceIndex; + UINT8 SerialBusType; + UINT8 GeneralFlags; + UINT16 TypeSpecificFlags; + UINT8 TypeSpecificRevisionId; + UINT16 TypeDataLength; + UINT32 ConnectionSpeed; + UINT8 DataBitLength; + UINT8 Phase; + UINT8 Polarity; + UINT16 DeviceSelection; +} EFI_ACPI_SERIAL_BUS_RESOURCE_SPI_DESCRIPTOR; + +/// +/// Serial Bus Resource Descriptor (UART) +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT8 ResourceSourceIndex; + UINT8 SerialBusType; + UINT8 GeneralFlags; + UINT16 TypeSpecificFlags; + UINT8 TypeSpecificRevisionId; + UINT16 TypeDataLength; + UINT32 DefaultBaudRate; + UINT16 RxFIFO; + UINT16 TxFIFO; + UINT8 Parity; + UINT8 SerialLinesEnabled; +} EFI_ACPI_SERIAL_BUS_RESOURCE_UART_DESCRIPTOR; + +#pragma pack() + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 5.0 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_5_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_5_0_SYSTEM_IO 1 +#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_5_0_SMBUS 4 +#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_5_0_UNDEFINED 0 +#define EFI_ACPI_5_0_BYTE 1 +#define EFI_ACPI_5_0_WORD 2 +#define EFI_ACPI_5_0_DWORD 3 +#define EFI_ACPI_5_0_QWORD 4 + +// +// ACPI 5.0 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_5_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT8 Reserved2[3]; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; +} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_5_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_5_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_5_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_5_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_5_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_5_0_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_5_0_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0 +#define EFI_ACPI_5_0_8042 BIT1 +#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_0_WBINVD BIT0 +#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_5_0_PROC_C1 BIT2 +#define EFI_ACPI_5_0_P_LVL2_UP BIT3 +#define EFI_ACPI_5_0_PWR_BUTTON BIT4 +#define EFI_ACPI_5_0_SLP_BUTTON BIT5 +#define EFI_ACPI_5_0_FIX_RTC BIT6 +#define EFI_ACPI_5_0_RTC_S4 BIT7 +#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_5_0_DCK_CAP BIT9 +#define EFI_ACPI_5_0_RESET_REG_SUP BIT10 +#define EFI_ACPI_5_0_SEALED_CASE BIT11 +#define EFI_ACPI_5_0_HEADLESS BIT12 +#define EFI_ACPI_5_0_CPU_SW_SLP BIT13 +#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14 +#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_0_S4BIOS_F BIT0 +#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_5_0_IO_APIC 0x01 +#define EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_5_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_5_0_IO_SAPIC 0x06 +#define EFI_ACPI_5_0_LOCAL_SAPIC 0x07 +#define EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_5_0_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_5_0_GIC 0x0B +#define EFI_ACPI_5_0_GICD 0x0C + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_5_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_0_POLARITY (3 << 0) +#define EFI_ACPI_5_0_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicId; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; +} EFI_ACPI_5_0_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_0_GIC_ENABLED BIT0 +#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT32 Reserved2; +} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x03 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_5_0_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_5_0_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_5_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01 +#define EFI_ACPI_5_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_5_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_5_0_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01 +#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED +#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior to when the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 PhysicalAddress; + UINT32 GlobalFlags; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; +} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Global Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0 +#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_5_0_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_5_0_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_5_0_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_5_0_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; +} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR 0x09 + +// +// Error Source structure flags. +// +#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03 +#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_5_0_ERST_NOOP 0x04 +#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_5_0_ERST_ADD 0x08 +#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09 +#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_5_0_ERST_STALL 0x0C +#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_5_0_ERST_GOTO 0x0F +#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_5_0_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 5.0 spec.) +/// +#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_5_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 GenerateSci:1; +} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 SciDoorbell:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_5_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_5_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_5_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_5_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_5_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_5_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_5_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_5_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_5_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_5_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_5_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_5_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_5_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_5_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_5_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') +#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_5_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_5_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_5_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi51.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi51.h new file mode 100644 index 0000000000..e2877df988 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi51.h @@ -0,0 +1,2139 @@ +/** @file + ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016. + + Copyright (c) 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_5_1_H_ +#define _ACPI_5_1_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 5.1 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_5_1_SYSTEM_MEMORY 0 +#define EFI_ACPI_5_1_SYSTEM_IO 1 +#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_5_1_SMBUS 4 +#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_5_1_UNDEFINED 0 +#define EFI_ACPI_5_1_BYTE 1 +#define EFI_ACPI_5_1_WORD 2 +#define EFI_ACPI_5_1_DWORD 3 +#define EFI_ACPI_5_1_QWORD 4 + +// +// ACPI 5.1 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_5_1_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; +} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05 +#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_5_1_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_5_1_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_5_1_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_5_1_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_5_1_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_5_1_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_5_1_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_5_1_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_5_1_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0 +#define EFI_ACPI_5_1_8042 BIT1 +#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_1_WBINVD BIT0 +#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1 +#define EFI_ACPI_5_1_PROC_C1 BIT2 +#define EFI_ACPI_5_1_P_LVL2_UP BIT3 +#define EFI_ACPI_5_1_PWR_BUTTON BIT4 +#define EFI_ACPI_5_1_SLP_BUTTON BIT5 +#define EFI_ACPI_5_1_FIX_RTC BIT6 +#define EFI_ACPI_5_1_RTC_S4 BIT7 +#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8 +#define EFI_ACPI_5_1_DCK_CAP BIT9 +#define EFI_ACPI_5_1_RESET_REG_SUP BIT10 +#define EFI_ACPI_5_1_SEALED_CASE BIT11 +#define EFI_ACPI_5_1_HEADLESS BIT12 +#define EFI_ACPI_5_1_CPU_SW_SLP BIT13 +#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14 +#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_1_S4BIOS_F BIT0 +#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_1_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_5_1_IO_APIC 0x01 +#define EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_5_1_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_5_1_IO_SAPIC 0x06 +#define EFI_ACPI_5_1_LOCAL_SAPIC 0x07 +#define EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_5_1_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_5_1_GIC 0x0B +#define EFI_ACPI_5_1_GICD 0x0C +#define EFI_ACPI_5_1_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_5_1_GICR 0x0E + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_5_1_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_5_1_POLARITY (3 << 0) +#define EFI_ACPI_5_1_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; +} EFI_ACPI_5_1_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GIC_ENABLED BIT0 +#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_5_1_GIC_V1 0x01 +#define EFI_ACPI_5_1_GIC_V2 0x02 +#define EFI_ACPI_5_1_GIC_V3 0x03 +#define EFI_ACPI_5_1_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_5_1_GICR_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x04 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_5_1_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_5_1_GICC_AFFINITY 0x03 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0) + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_5_1_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_5_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01 +#define EFI_ACPI_5_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_5_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_5_1_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_5_1_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior to when the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_5_1_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; +} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0 +#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// SBSA Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_5_1_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_5_1_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_5_1_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_5_1_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; +} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR 0x09 + +// +// Error Source structure flags. +// +#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03 +#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_5_1_ERST_NOOP 0x04 +#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_5_1_ERST_ADD 0x08 +#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09 +#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_5_1_ERST_STALL 0x0C +#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_5_1_ERST_GOTO 0x0F +#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_5_1_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 5.1 spec.) +/// +#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_5_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 GenerateSci:1; +} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 SciDoorbell:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_5_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_5_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_5_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_5_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_5_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_5_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_5_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_5_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_5_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_5_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_5_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_5_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_5_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_5_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_5_1_IO_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_5_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_5_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_5_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_5_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_5_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_5_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_5_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_5_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_5_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_5_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi60.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi60.h new file mode 100644 index 0000000000..3b05df22a9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi60.h @@ -0,0 +1,2392 @@ +/** @file + ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_6_0_H_ +#define _ACPI_6_0_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 6.0 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_6_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_6_0_SYSTEM_IO 1 +#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_6_0_SMBUS 4 +#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_6_0_UNDEFINED 0 +#define EFI_ACPI_6_0_BYTE 1 +#define EFI_ACPI_6_0_WORD 2 +#define EFI_ACPI_6_0_DWORD 3 +#define EFI_ACPI_6_0_QWORD 4 + +// +// ACPI 6.0 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; + UINT64 HypervisorVendorIdentity; +} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06 +#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x00 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_6_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_6_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_6_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_6_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_6_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_6_0_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_6_0_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_6_0_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0 +#define EFI_ACPI_6_0_8042 BIT1 +#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_0_WBINVD BIT0 +#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1 +#define EFI_ACPI_6_0_PROC_C1 BIT2 +#define EFI_ACPI_6_0_P_LVL2_UP BIT3 +#define EFI_ACPI_6_0_PWR_BUTTON BIT4 +#define EFI_ACPI_6_0_SLP_BUTTON BIT5 +#define EFI_ACPI_6_0_FIX_RTC BIT6 +#define EFI_ACPI_6_0_RTC_S4 BIT7 +#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8 +#define EFI_ACPI_6_0_DCK_CAP BIT9 +#define EFI_ACPI_6_0_RESET_REG_SUP BIT10 +#define EFI_ACPI_6_0_SEALED_CASE BIT11 +#define EFI_ACPI_6_0_HEADLESS BIT12 +#define EFI_ACPI_6_0_CPU_SW_SLP BIT13 +#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14 +#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_0_S4BIOS_F BIT0 +#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 6.0 Errata A spec.) +/// +#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_0_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_6_0_IO_APIC 0x01 +#define EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_6_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_6_0_IO_SAPIC 0x06 +#define EFI_ACPI_6_0_LOCAL_SAPIC 0x07 +#define EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_6_0_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_6_0_GIC 0x0B +#define EFI_ACPI_6_0_GICD 0x0C +#define EFI_ACPI_6_0_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_6_0_GICR 0x0E +#define EFI_ACPI_6_0_GIC_ITS 0x0F + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_6_0_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_0_POLARITY (3 << 0) +#define EFI_ACPI_6_0_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; + UINT8 Reserved2[3]; +} EFI_ACPI_6_0_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GIC_ENABLED BIT0 +#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_6_0_GIC_V1 0x01 +#define EFI_ACPI_6_0_GIC_V2 0x02 +#define EFI_ACPI_6_0_GIC_V3 0x03 +#define EFI_ACPI_6_0_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_6_0_GICR_STRUCTURE; + +/// +/// GIC Interrupt Translation Service Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicItsId; + UINT64 PhysicalBaseAddress; + UINT32 Reserved2; +} EFI_ACPI_6_0_GIC_ITS_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x04 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_6_0_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_6_0_GICC_AFFINITY 0x03 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0) + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_6_0_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_6_0_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01 +#define EFI_ACPI_6_0_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_6_0_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_6_0_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_6_0_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior to when the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_0_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; +} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0 +#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// SBSA Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +// +// NVDIMM Firmware Interface Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE; + +// +// NFIT Version (as defined in ACPI 6.0 spec.) +// +#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1 + +// +// Definition for NFIT Table Structure Types +// +#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE_TYPE 1 +#define EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE_TYPE 2 +#define EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3 +#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4 +#define EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5 +#define EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6 + +// +// Definition for NFIT Structure Header +// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER; + +// +// Definition for System Physical Address Range Structure +// +#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0 +#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1 +#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }} +#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }} +#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }} +#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }} +#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} +#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} +#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} +#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 SPARangeStructureIndex; + UINT16 Flags; + UINT32 Reserved_8; + UINT32 ProximityDomain; + GUID AddressRangeTypeGUID; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; + UINT64 AddressRangeMemoryMappingAttribute; +} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE; + +// +// Definition for Memory Device to System Physical Address Range Mapping Structure +// +typedef struct { + UINT32 DIMMNumber:4; + UINT32 MemoryChannelNumber:4; + UINT32 MemoryControllerID:4; + UINT32 SocketID:4; + UINT32 NodeControllerID:12; + UINT32 Reserved_28:4; +} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE; + +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4 +#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5 +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 MemoryDevicePhysicalID; + UINT16 MemoryDeviceRegionID; + UINT16 SPARangeStructureIndex ; + UINT16 NVDIMMControlRegionStructureIndex; + UINT64 MemoryDeviceRegionSize; + UINT64 RegionOffset; + UINT64 MemoryDevicePhysicalAddressRegionBase; + UINT16 InterleaveStructureIndex; + UINT16 InterleaveWays; + UINT16 MemoryDeviceStateFlags; + UINT16 Reserved_46; +} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE; + +// +// Definition for Interleave Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 InterleaveStructureIndex; + UINT16 Reserved_6; + UINT32 NumberOfLines; + UINT32 LineSize; +//UINT32 LineOffset[NumberOfLines]; +} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE; + +// +// Definition for SMBIOS Management Information Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT32 Reserved_4; +//UINT8 Data[]; +} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE; + +// +// Definition for NVDIMM Control Region Structure +// +#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0 +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 Reserved_18[6]; + UINT32 SerialNumber; + UINT16 RegionFormatInterfaceCode; + UINT16 NumberOfBlockControlWindows; + UINT64 SizeOfBlockControlWindow; + UINT64 CommandRegisterOffsetInBlockControlWindow; + UINT64 SizeOfCommandRegisterInBlockControlWindows; + UINT64 StatusRegisterOffsetInBlockControlWindow; + UINT64 SizeOfStatusRegisterInBlockControlWindows; + UINT16 NVDIMMControlRegionFlag; + UINT8 Reserved_74[6]; +} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE; + +// +// Definition for NVDIMM Block Data Window Region Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 NumberOfBlockDataWindows; + UINT64 BlockDataWindowStartOffset; + UINT64 SizeOfBlockDataWindow; + UINT64 BlockAccessibleMemoryCapacity; + UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory; +} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE; + +// +// Definition for Flush Hint Address Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NumberOfFlushHintAddresses; + UINT8 Reserved_10[6]; +//UINT64 FlushHintAddress[NumberOfFlushHintAddresses]; +} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_6_0_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_6_0_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_6_0_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_6_0_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; +} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0201 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR 0x09 + +// +// Error Source structure flags. +// +#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06 +#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07 + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03 +#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_0_ERST_NOOP 0x04 +#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_6_0_ERST_ADD 0x08 +#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09 +#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_6_0_ERST_STALL 0x0C +#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_6_0_ERST_GOTO 0x0F +#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_0_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 6.0 spec.) +/// +#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00 +#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01 +#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 GenerateSci:1; +} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 SciDoorbell:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0 +#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1 + +/// +/// Type 1 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 DoorbellInterrupt; + UINT8 DoorbellInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 2 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 DoorbellInterrupt; + UINT8 DoorbellInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; + EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister; + UINT64 DoorbellAckPreserve; + UINT64 DoorbellAckWrite; +} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "NFIT" NVDIMM Firmware Interface Table +/// +#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_6_0_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_6_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_6_0_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_6_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_6_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_6_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_6_0_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_6_0_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_6_0_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_6_0_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_6_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_6_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_6_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IORT" I/O Remapping Table +/// +#define EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_6_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_6_0_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_6_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_6_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_6_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "STAO" _STA Override Table +/// +#define EFI_ACPI_6_0_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_6_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_6_0_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_6_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_6_0_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_6_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_6_0_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +/// +/// "XENV" Xen Project Table +/// +#define EFI_ACPI_6_0_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi61.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi61.h new file mode 100644 index 0000000000..31ba4e728b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi61.h @@ -0,0 +1,2424 @@ +/** @file + ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_6_1_H_ +#define _ACPI_6_1_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 6.1 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_6_1_SYSTEM_MEMORY 0 +#define EFI_ACPI_6_1_SYSTEM_IO 1 +#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_6_1_SMBUS 4 +#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_6_1_UNDEFINED 0 +#define EFI_ACPI_6_1_BYTE 1 +#define EFI_ACPI_6_1_WORD 2 +#define EFI_ACPI_6_1_DWORD 3 +#define EFI_ACPI_6_1_QWORD 4 + +// +// ACPI 6.1 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_1_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; + UINT64 HypervisorVendorIdentity; +} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06 +#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_6_1_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_6_1_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_6_1_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_6_1_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_6_1_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_6_1_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_6_1_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0 +#define EFI_ACPI_6_1_8042 BIT1 +#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_1_WBINVD BIT0 +#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1 +#define EFI_ACPI_6_1_PROC_C1 BIT2 +#define EFI_ACPI_6_1_P_LVL2_UP BIT3 +#define EFI_ACPI_6_1_PWR_BUTTON BIT4 +#define EFI_ACPI_6_1_SLP_BUTTON BIT5 +#define EFI_ACPI_6_1_FIX_RTC BIT6 +#define EFI_ACPI_6_1_RTC_S4 BIT7 +#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8 +#define EFI_ACPI_6_1_DCK_CAP BIT9 +#define EFI_ACPI_6_1_RESET_REG_SUP BIT10 +#define EFI_ACPI_6_1_SEALED_CASE BIT11 +#define EFI_ACPI_6_1_HEADLESS BIT12 +#define EFI_ACPI_6_1_CPU_SW_SLP BIT13 +#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14 +#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_1_S4BIOS_F BIT0 +#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_1_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_6_1_IO_APIC 0x01 +#define EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_6_1_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_6_1_IO_SAPIC 0x06 +#define EFI_ACPI_6_1_LOCAL_SAPIC 0x07 +#define EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_6_1_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_6_1_GIC 0x0B +#define EFI_ACPI_6_1_GICD 0x0C +#define EFI_ACPI_6_1_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_6_1_GICR 0x0E +#define EFI_ACPI_6_1_GIC_ITS 0x0F + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_6_1_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_1_POLARITY (3 << 0) +#define EFI_ACPI_6_1_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; + UINT8 Reserved2[3]; +} EFI_ACPI_6_1_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GIC_ENABLED BIT0 +#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_6_1_GIC_V1 0x01 +#define EFI_ACPI_6_1_GIC_V2 0x02 +#define EFI_ACPI_6_1_GIC_V3 0x03 +#define EFI_ACPI_6_1_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_6_1_GICR_STRUCTURE; + +/// +/// GIC Interrupt Translation Service Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicItsId; + UINT64 PhysicalBaseAddress; + UINT32 Reserved2; +} EFI_ACPI_6_1_GIC_ITS_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x04 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_6_1_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_6_1_GICC_AFFINITY 0x03 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0) + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_6_1_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_6_1_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED 0x01 +#define EFI_ACPI_6_1_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPOTED_AND_EXPOSED_TO_SOFTWARE 0x02 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_6_1_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_6_1_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_6_1_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior to when the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_1_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0 +#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// SBSA Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +// +// NVDIMM Firmware Interface Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE; + +// +// NFIT Version (as defined in ACPI 6.1 spec.) +// +#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1 + +// +// Definition for NFIT Table Structure Types +// +#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1 +#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2 +#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3 +#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4 +#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5 +#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6 + +// +// Definition for NFIT Structure Header +// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER; + +// +// Definition for System Physical Address Range Structure +// +#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0 +#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1 +#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }} +#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }} +#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }} +#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }} +#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} +#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} +#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} +#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 SPARangeStructureIndex; + UINT16 Flags; + UINT32 Reserved_8; + UINT32 ProximityDomain; + GUID AddressRangeTypeGUID; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; + UINT64 AddressRangeMemoryMappingAttribute; +} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE; + +// +// Definition for Memory Device to System Physical Address Range Mapping Structure +// +typedef struct { + UINT32 DIMMNumber:4; + UINT32 MemoryChannelNumber:4; + UINT32 MemoryControllerID:4; + UINT32 SocketID:4; + UINT32 NodeControllerID:12; + UINT32 Reserved_28:4; +} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE; + +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5 +#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6 +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NVDIMMPhysicalID; + UINT16 NVDIMMRegionID; + UINT16 SPARangeStructureIndex ; + UINT16 NVDIMMControlRegionStructureIndex; + UINT64 NVDIMMRegionSize; + UINT64 RegionOffset; + UINT64 NVDIMMPhysicalAddressRegionBase; + UINT16 InterleaveStructureIndex; + UINT16 InterleaveWays; + UINT16 NVDIMMStateFlags; + UINT16 Reserved_46; +} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE; + +// +// Definition for Interleave Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 InterleaveStructureIndex; + UINT16 Reserved_6; + UINT32 NumberOfLines; + UINT32 LineSize; +//UINT32 LineOffset[NumberOfLines]; +} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE; + +// +// Definition for SMBIOS Management Information Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT32 Reserved_4; +//UINT8 Data[]; +} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE; + +// +// Definition for NVDIMM Control Region Structure +// +#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0 + +#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0 +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 ValidFields; + UINT8 ManufacturingLocation; + UINT16 ManufacturingDate; + UINT8 Reserved_22[2]; + UINT32 SerialNumber; + UINT16 RegionFormatInterfaceCode; + UINT16 NumberOfBlockControlWindows; + UINT64 SizeOfBlockControlWindow; + UINT64 CommandRegisterOffsetInBlockControlWindow; + UINT64 SizeOfCommandRegisterInBlockControlWindows; + UINT64 StatusRegisterOffsetInBlockControlWindow; + UINT64 SizeOfStatusRegisterInBlockControlWindows; + UINT16 NVDIMMControlRegionFlag; + UINT8 Reserved_74[6]; +} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE; + +// +// Definition for NVDIMM Block Data Window Region Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 NumberOfBlockDataWindows; + UINT64 BlockDataWindowStartOffset; + UINT64 SizeOfBlockDataWindow; + UINT64 BlockAccessibleMemoryCapacity; + UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory; +} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE; + +// +// Definition for Flush Hint Address Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NumberOfFlushHintAddresses; + UINT8 Reserved_10[6]; +//UINT64 FlushHintAddress[NumberOfFlushHintAddresses]; +} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_6_1_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_6_1_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_6_1_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_6_1_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; + UINT8 Timestamp[8]; +} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR 0x09 +#define EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A + +// +// Error Source structure flags. +// +#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09 +#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Hardware Error Source Version 2 Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister; + UINT64 ReadAckPreserve; + UINT64 ReadAckWrite; +} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03 +#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F +#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10 + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_1_ERST_NOOP 0x04 +#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_6_1_ERST_ADD 0x08 +#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09 +#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_6_1_ERST_STALL 0x0C +#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_6_1_ERST_GOTO 0x0F +#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_1_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 6.1 spec.) +/// +#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00 +#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01 +#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 GenerateSci:1; +} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 SciDoorbell:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0 +#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1 + +/// +/// Type 1 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 DoorbellInterrupt; + UINT8 DoorbellInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 2 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 DoorbellInterrupt; + UINT8 DoorbellInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister; + UINT64 DoorbellAckPreserve; + UINT64 DoorbellAckWrite; +} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "NFIT" NVDIMM Firmware Interface Table +/// +#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_6_1_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_6_1_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_6_1_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_6_1_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_6_1_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_6_1_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_6_1_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_6_1_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_6_1_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_6_1_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_6_1_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_6_1_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IORT" I/O Remapping Table +/// +#define EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_6_1_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_6_1_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_6_1_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_6_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_6_1_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "STAO" _STA Override Table +/// +#define EFI_ACPI_6_1_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_6_1_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_6_1_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_6_1_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_6_1_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_6_1_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_6_1_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +/// +/// "XENV" Xen Project Table +/// +#define EFI_ACPI_6_1_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi62.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi62.h new file mode 100644 index 0000000000..319586d647 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi62.h @@ -0,0 +1,2960 @@ +/** @file + ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_6_2_H_ +#define _ACPI_6_2_H_ + +#include + +// +// Large Item Descriptor Name +// +#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D +#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F +#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10 +#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11 +#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12 + +// +// Large Item Descriptor Value +// +#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D +#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F +#define ACPI_PIN_GROUP_DESCRIPTOR 0x90 +#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91 +#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92 + +#pragma pack(1) + +/// +/// Pin Function Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT16 Flags; + UINT8 PinPullConfiguration; + UINT16 FunctionNumber; + UINT16 PinTableOffset; + UINT8 ResourceSourceIndex; + UINT16 ResourceSourceNameOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR; + +/// +/// Pin Configuration Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT16 Flags; + UINT8 PinConfigurationType; + UINT32 PinConfigurationValue; + UINT16 PinTableOffset; + UINT8 ResourceSourceIndex; + UINT16 ResourceSourceNameOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR; + +/// +/// Pin Group Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT16 Flags; + UINT16 PinTableOffset; + UINT16 ResourceLabelOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_PIN_GROUP_DESCRIPTOR; + +/// +/// Pin Group Function Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT16 Flags; + UINT16 FunctionNumber; + UINT8 ResourceSourceIndex; + UINT16 ResourceSourceNameOffset; + UINT16 ResourceSourceLabelOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR; + +/// +/// Pin Group Configuration Descriptor +/// +typedef PACKED struct { + ACPI_LARGE_RESOURCE_HEADER Header; + UINT8 RevisionId; + UINT16 Flags; + UINT8 PinConfigurationType; + UINT32 PinConfigurationValue; + UINT8 ResourceSourceIndex; + UINT16 ResourceSourceNameOffset; + UINT16 ResourceSourceLabelOffset; + UINT16 VendorDataOffset; + UINT16 VendorDataLength; +} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR; + +#pragma pack() + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 6.2 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_6_2_SYSTEM_MEMORY 0 +#define EFI_ACPI_6_2_SYSTEM_IO 1 +#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_6_2_SMBUS 4 +#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_6_2_UNDEFINED 0 +#define EFI_ACPI_6_2_BYTE 1 +#define EFI_ACPI_6_2_WORD 2 +#define EFI_ACPI_6_2_DWORD 3 +#define EFI_ACPI_6_2_QWORD 4 + +// +// ACPI 6.2 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_2_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; + UINT64 HypervisorVendorIdentity; +} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06 +#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_6_2_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_6_2_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0 +#define EFI_ACPI_6_2_8042 BIT1 +#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_2_WBINVD BIT0 +#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1 +#define EFI_ACPI_6_2_PROC_C1 BIT2 +#define EFI_ACPI_6_2_P_LVL2_UP BIT3 +#define EFI_ACPI_6_2_PWR_BUTTON BIT4 +#define EFI_ACPI_6_2_SLP_BUTTON BIT5 +#define EFI_ACPI_6_2_FIX_RTC BIT6 +#define EFI_ACPI_6_2_RTC_S4 BIT7 +#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8 +#define EFI_ACPI_6_2_DCK_CAP BIT9 +#define EFI_ACPI_6_2_RESET_REG_SUP BIT10 +#define EFI_ACPI_6_2_SEALED_CASE BIT11 +#define EFI_ACPI_6_2_HEADLESS BIT12 +#define EFI_ACPI_6_2_CPU_SW_SLP BIT13 +#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14 +#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_2_S4BIOS_F BIT0 +#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_2_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_6_2_IO_APIC 0x01 +#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_6_2_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_6_2_IO_SAPIC 0x06 +#define EFI_ACPI_6_2_LOCAL_SAPIC 0x07 +#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_6_2_GIC 0x0B +#define EFI_ACPI_6_2_GICD 0x0C +#define EFI_ACPI_6_2_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_6_2_GICR 0x0E +#define EFI_ACPI_6_2_GIC_ITS 0x0F + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_6_2_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_2_POLARITY (3 << 0) +#define EFI_ACPI_6_2_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; + UINT8 Reserved2[3]; +} EFI_ACPI_6_2_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GIC_ENABLED BIT0 +#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_6_2_GIC_V1 0x01 +#define EFI_ACPI_6_2_GIC_V2 0x02 +#define EFI_ACPI_6_2_GIC_V3 0x03 +#define EFI_ACPI_6_2_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_6_2_GICR_STRUCTURE; + +/// +/// GIC Interrupt Translation Service Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicItsId; + UINT64 PhysicalBaseAddress; + UINT32 Reserved2; +} EFI_ACPI_6_2_GIC_ITS_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x05 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_6_2_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_6_2_GICC_AFFINITY 0x03 +#define EFI_ACPI_6_2_GIC_ITS_AFFINITY 0x04 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0) + +/// +/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT8 Reserved[2]; + UINT32 ItsId; +} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE; + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_6_2_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0 +#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1 +#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2 +#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3 +#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_6_2_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior to when the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; +} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0 +#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// SBSA Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +// +// NVDIMM Firmware Interface Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE; + +// +// NFIT Version (as defined in ACPI 6.2 spec.) +// +#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1 + +// +// Definition for NFIT Table Structure Types +// +#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1 +#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2 +#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3 +#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4 +#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5 +#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6 + +// +// Definition for NFIT Structure Header +// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER; + +// +// Definition for System Physical Address Range Structure +// +#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0 +#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1 +#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }} +#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }} +#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }} +#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }} +#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} +#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} +#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} +#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 SPARangeStructureIndex; + UINT16 Flags; + UINT32 Reserved_8; + UINT32 ProximityDomain; + GUID AddressRangeTypeGUID; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; + UINT64 AddressRangeMemoryMappingAttribute; +} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE; + +// +// Definition for Memory Device to System Physical Address Range Mapping Structure +// +typedef struct { + UINT32 DIMMNumber:4; + UINT32 MemoryChannelNumber:4; + UINT32 MemoryControllerID:4; + UINT32 SocketID:4; + UINT32 NodeControllerID:12; + UINT32 Reserved_28:4; +} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE; + +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5 +#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6 +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NVDIMMPhysicalID; + UINT16 NVDIMMRegionID; + UINT16 SPARangeStructureIndex ; + UINT16 NVDIMMControlRegionStructureIndex; + UINT64 NVDIMMRegionSize; + UINT64 RegionOffset; + UINT64 NVDIMMPhysicalAddressRegionBase; + UINT16 InterleaveStructureIndex; + UINT16 InterleaveWays; + UINT16 NVDIMMStateFlags; + UINT16 Reserved_46; +} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE; + +// +// Definition for Interleave Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 InterleaveStructureIndex; + UINT16 Reserved_6; + UINT32 NumberOfLines; + UINT32 LineSize; +//UINT32 LineOffset[NumberOfLines]; +} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE; + +// +// Definition for SMBIOS Management Information Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT32 Reserved_4; +//UINT8 Data[]; +} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE; + +// +// Definition for NVDIMM Control Region Structure +// +#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0 + +#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0 +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 ValidFields; + UINT8 ManufacturingLocation; + UINT16 ManufacturingDate; + UINT8 Reserved_22[2]; + UINT32 SerialNumber; + UINT16 RegionFormatInterfaceCode; + UINT16 NumberOfBlockControlWindows; + UINT64 SizeOfBlockControlWindow; + UINT64 CommandRegisterOffsetInBlockControlWindow; + UINT64 SizeOfCommandRegisterInBlockControlWindows; + UINT64 StatusRegisterOffsetInBlockControlWindow; + UINT64 SizeOfStatusRegisterInBlockControlWindows; + UINT16 NVDIMMControlRegionFlag; + UINT8 Reserved_74[6]; +} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE; + +// +// Definition for NVDIMM Block Data Window Region Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 NumberOfBlockDataWindows; + UINT64 BlockDataWindowStartOffset; + UINT64 SizeOfBlockDataWindow; + UINT64 BlockAccessibleMemoryCapacity; + UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory; +} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE; + +// +// Definition for Flush Hint Address Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NumberOfFlushHintAddresses; + UINT8 Reserved_10[6]; +//UINT64 FlushHintAddress[NumberOfFlushHintAddresses]; +} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE; + +/// +/// Secure DEVices Table (SDEV) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER; + +/// +/// SDEV Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01 + +/// +/// Secure Device types +/// +#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01 +#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00 + +/// +/// Secure Device flags +/// +#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0 + +/// +/// SDEV Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; +} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER; + +/// +/// PCIe Endpoint Device based Secure Device Structure +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; + UINT16 PciSegmentNumber; + UINT16 StartBusNumber; + UINT16 PciPathOffset; + UINT16 PciPathLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; +} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE; + +/// +/// ACPI_NAMESPACE_DEVICE based Secure Device Structure +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; + UINT16 DeviceIdentifierOffset; + UINT16 DeviceIdentifierLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; +} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_6_2_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; + UINT8 Timestamp[8]; +} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR 0x09 +#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B + +// +// Error Source structure flags. +// +#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) +#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09 +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A +#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Hardware Error Source Version 2 Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister; + UINT64 ReadAckPreserve; + UINT64 ReadAckWrite; +} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// IA-32 Architecture Deferred Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;; + +/// +/// HMAT - Heterogeneous Memory Attribute Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[4]; +} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER; + +/// +/// HMAT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01 + +/// +/// HMAT types +/// +#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00 +#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01 +#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02 + +/// +/// HMAT Structure Header +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; +} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER; + +/// +/// Memory Subsystem Address Range Structure flags +/// +typedef struct { + UINT16 ProcessorProximityDomainValid:1; + UINT16 MemoryProximityDomainValid:1; + UINT16 ReservationHint:1; + UINT16 Reserved:13; +} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS; + +/// +/// Memory Subsystem Address Range Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags; + UINT8 Reserved1[2]; + UINT32 ProcessorProximityDomain; + UINT32 MemoryProximityDomain; + UINT8 Reserved2[4]; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; +} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE; + +/// +/// System Locality Latency and Bandwidth Information Structure flags +/// +typedef struct { + UINT8 MemoryHierarchy:5; + UINT8 Reserved:3; +} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS; + +/// +/// System Locality Latency and Bandwidth Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags; + UINT8 DataType; + UINT8 Reserved1[2]; + UINT32 NumberOfInitiatorProximityDomains; + UINT32 NumberOfTargetProximityDomains; + UINT8 Reserved2[4]; + UINT64 EntryBaseUnit; +} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO; + +/// +/// Memory Side Cache Information Structure cache attributes +/// +typedef struct { + UINT32 TotalCacheLevels:4; + UINT32 CacheLevel:4; + UINT32 CacheAssociativity:4; + UINT32 WritePolicy:4; + UINT32 CacheLineSize:16; +} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES; + +/// +/// Memory Side Cache Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + UINT32 MemoryProximityDomain; + UINT8 Reserved1[4]; + UINT64 MemorySideCacheSize; + EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes; + UINT8 Reserved2[2]; + UINT16 NumberOfSmbiosHandles; +} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03 +#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F +#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10 + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_2_ERST_NOOP 0x04 +#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_6_2_ERST_ADD 0x08 +#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09 +#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_6_2_ERST_STALL 0x0C +#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_6_2_ERST_GOTO 0x0F +#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_2_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00 +#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01 +#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02 +#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03 +#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 NotifyOnCompletion:1; +} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 PlatformInterrupt:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0 +#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1 + +/// +/// Type 1 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 2 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckWrite; +} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 3 Extended PCC Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT32 AddressLength; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT32 MinimumRequestTurnaroundTime; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckSet; + UINT8 Reserved1[8]; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister; + UINT64 CommandCompleteCheckMask; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister; + UINT64 CommandCompleteUpdatePreserve; + UINT64 CommandCompleteUpdateSet; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister; + UINT64 ErrorStatusMask; +} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC; + +/// +/// Type 4 Extended PCC Subspace Structure +/// +typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC; + +#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0 + +typedef struct { + UINT32 Signature; + UINT32 Flags; + UINT32 Length; + UINT32 Command; +} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER; + +/// +/// Platform Debug Trigger Table (PDTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 TriggerCount; + UINT8 Reserved[3]; + UINT32 TriggerIdentifierArrayOffset; +} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER; + +/// +/// PDTT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00 + +/// +/// PDTT Platform Communication Channel Identifier Structure +/// +typedef struct { + UINT16 SubChannelIdentifer:8; + UINT16 Runtime:1; + UINT16 WaitForCompletion:1; + UINT16 Reserved:6; +} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER; + +/// +/// PCC Commands Codes used by Platform Debug Trigger Table +/// +#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00 +#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01 + +/// +/// PPTT Platform Communication Channel +/// +typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC; + +/// +/// Processor Properties Topology Table (PPTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER; + +/// +/// PPTT Revision (as defined in ACPI 6.2 spec.) +/// +#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// PPTT types +/// +#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00 +#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01 +#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02 + +/// +/// PPTT Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; +} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER; + +/// +/// For PPTT struct processor flags +/// +#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1 + +/// +/// Processor hierarchy node structure flags +/// +typedef struct { + UINT32 PhysicalPackage:1; + UINT32 AcpiProcessorIdValid:1; + UINT32 Reserved:30; +} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS; + +/// +/// Processor hierarchy node structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags; + UINT32 Parent; + UINT32 AcpiProcessorId; + UINT32 NumberOfPrivateResources; +} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR; + +/// +/// Cache Type Structure flags +/// +typedef struct { + UINT32 SizePropertyValid:1; + UINT32 NumberOfSetsValid:1; + UINT32 AssociativityValid:1; + UINT32 AllocationTypeValid:1; + UINT32 CacheTypeValid:1; + UINT32 WritePolicyValid:1; + UINT32 LineSizeValid:1; + UINT32 Reserved:25; +} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS; + +/// +/// For cache attributes +/// +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0 +#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1 + +/// +/// Cache Type Structure cache attributes +/// +typedef struct { + UINT8 AllocationType:2; + UINT8 CacheType:2; + UINT8 WritePolicy:1; + UINT8 Reserved:3; +} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES; + +/// +/// Cache Type Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags; + UINT32 NextLevelOfCache; + UINT32 Size; + UINT32 NumberOfSets; + UINT8 Associativity; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes; + UINT16 LineSize; +} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE; + +/// +/// ID structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 VendorId; + UINT64 Level1Id; + UINT64 Level2Id; + UINT16 MajorRev; + UINT16 MinorRev; + UINT16 SpinRev; +} EFI_ACPI_6_2_PPTT_STRUCTURE_ID; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "HMAT" Heterogeneous Memory Attribute Table +/// +#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "NFIT" NVDIMM Firmware Interface Table +/// +#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T') + +/// +/// "PDTT" Platform Debug Trigger Table +/// +#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PPTT" Processor Properties Topology Table +/// +#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SDEV" Secure DEVices Table +/// +#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DPPT" DMA Protection Policy Table +/// +#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IORT" I/O Remapping Table +/// +#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_6_2_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SDEI" Software Delegated Exceptions Interface Table +/// +#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Console Redirection Table +/// +#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "STAO" _STA Override Table +/// +#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +/// +/// "WSMT" Windows SMM Security Mitigation Table +/// +#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T') + +/// +/// "XENV" Xen Project Table +/// +#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi63.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi63.h new file mode 100644 index 0000000000..431daac15b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi63.h @@ -0,0 +1,2960 @@ +/** @file + ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_6_3_H_ +#define _ACPI_6_3_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 6.3 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_6_3_SYSTEM_MEMORY 0x00 +#define EFI_ACPI_6_3_SYSTEM_IO 0x01 +#define EFI_ACPI_6_3_PCI_CONFIGURATION_SPACE 0x02 +#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER 0x03 +#define EFI_ACPI_6_3_SMBUS 0x04 +#define EFI_ACPI_6_3_SYSTEM_CMOS 0x05 +#define EFI_ACPI_6_3_PCI_BAR_TARGET 0x06 +#define EFI_ACPI_6_3_IPMI 0x07 +#define EFI_ACPI_6_3_GENERAL_PURPOSE_IO 0x08 +#define EFI_ACPI_6_3_GENERIC_SERIAL_BUS 0x09 +#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_6_3_UNDEFINED 0 +#define EFI_ACPI_6_3_BYTE 1 +#define EFI_ACPI_6_3_WORD 2 +#define EFI_ACPI_6_3_DWORD 3 +#define EFI_ACPI_6_3_QWORD 4 + +// +// ACPI 6.3 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_3_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; + UINT64 HypervisorVendorIdentity; +} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06 +#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_6_3_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_6_3_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_6_3_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_6_3_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_6_3_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_6_3_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0 +#define EFI_ACPI_6_3_8042 BIT1 +#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_3_WBINVD BIT0 +#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1 +#define EFI_ACPI_6_3_PROC_C1 BIT2 +#define EFI_ACPI_6_3_P_LVL2_UP BIT3 +#define EFI_ACPI_6_3_PWR_BUTTON BIT4 +#define EFI_ACPI_6_3_SLP_BUTTON BIT5 +#define EFI_ACPI_6_3_FIX_RTC BIT6 +#define EFI_ACPI_6_3_RTC_S4 BIT7 +#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8 +#define EFI_ACPI_6_3_DCK_CAP BIT9 +#define EFI_ACPI_6_3_RESET_REG_SUP BIT10 +#define EFI_ACPI_6_3_SEALED_CASE BIT11 +#define EFI_ACPI_6_3_HEADLESS BIT12 +#define EFI_ACPI_6_3_CPU_SW_SLP BIT13 +#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14 +#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_3_S4BIOS_F BIT0 +#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_3_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x0D and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_6_3_IO_APIC 0x01 +#define EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_6_3_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_6_3_IO_SAPIC 0x06 +#define EFI_ACPI_6_3_LOCAL_SAPIC 0x07 +#define EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_6_3_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_6_3_GIC 0x0B +#define EFI_ACPI_6_3_GICD 0x0C +#define EFI_ACPI_6_3_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_6_3_GICR 0x0E +#define EFI_ACPI_6_3_GIC_ITS 0x0F + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_LOCAL_APIC_ENABLED BIT0 +#define EFI_ACPI_6_3_LOCAL_APIC_ONLINE_CAPABLE BIT1 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_6_3_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_3_POLARITY (3 << 0) +#define EFI_ACPI_6_3_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; + UINT8 Reserved2; + UINT16 SpeOverflowInterrupt; +} EFI_ACPI_6_3_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GIC_ENABLED BIT0 +#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_6_3_GIC_V1 0x01 +#define EFI_ACPI_6_3_GIC_V2 0x02 +#define EFI_ACPI_6_3_GIC_V3 0x03 +#define EFI_ACPI_6_3_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_6_3_GICR_STRUCTURE; + +/// +/// GIC Interrupt Translation Service Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicItsId; + UINT64 PhysicalBaseAddress; + UINT32 Reserved2; +} EFI_ACPI_6_3_GIC_ITS_STRUCTURE; + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x06 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_6_3_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_6_3_GICC_AFFINITY 0x03 +#define EFI_ACPI_6_3_GIC_ITS_AFFINITY 0x04 +#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY 0x05 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0) + +/// +/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT8 Reserved[2]; + UINT32 ItsId; +} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE; + +// +// Generic Initiator Affinity Structure Device Handle Types +// All other values between 0x02 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00 +#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01 + +/// +/// Device Handle - ACPI +/// +typedef struct { + UINT64 AcpiHid; + UINT32 AcpiUid; + UINT8 Reserved[4]; +} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI; + +/// +/// Device Handle - PCI +/// +typedef struct { + UINT16 PciSegment; + UINT16 PciBdfNumber; + UINT8 Reserved[12]; +} EFI_ACPI_6_3_DEVICE_HANDLE_PCI; + +/// +/// Generic Initiator Affinity Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1; + UINT8 DeviceHandleType; + UINT32 ProximityDomain; + + union { + EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi; + EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci; + } DeviceHandle; + + UINT32 Flags; + UINT8 Reserved2[4]; +} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE; + +/// +/// Generic Initiator Affinity Structure Flags. All other bits are reserved +/// and must be 0. +/// +#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0) + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_6_3_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_6_3_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0 +#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1 +#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2 +#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3 +#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_6_3_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01 + +/// +/// Common Memory Aggregator Device Structure. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; +} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Memory Aggregator Device Type +/// +#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2 + +/// +/// Socket Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[]; +} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// MemoryController Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT32 ReadLatency; + UINT32 WriteLatency; + UINT32 ReadBandwidth; + UINT32 WriteBandwidth; + UINT16 OptimalAccessUnit; + UINT16 OptimalAccessAlignment; + UINT16 Reserved; + UINT16 NumberOfProximityDomains; +//UINT32 ProximityDomain[NumberOfProximityDomains]; +//EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[]; +} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// DIMM Memory Aggregator Device Structure. +/// +typedef struct { + EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header; + UINT16 PhysicalComponentIdentifier; + UINT16 Reserved; + UINT32 SizeOfDimm; + UINT32 SmbiosHandle; +} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:1] = Reserved (must be zero) + /// Bit [0] = Valid. A one indicates the boot image graphic is valid. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_6_3_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_6_3_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior towhen the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; + UINT32 VirtualPL2TimerGSIV; + UINT32 VirtualPL2TimerFlags; +} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0 +#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// SBSA Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +// +// NVDIMM Firmware Interface Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE; + +// +// NFIT Version (as defined in ACPI 6.3 spec.) +// +#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1 + +// +// Definition for NFIT Table Structure Types +// +#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1 +#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2 +#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3 +#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4 +#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5 +#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6 + +// +// Definition for NFIT Structure Header +// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER; + +// +// Definition for System Physical Address Range Structure +// +#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0 +#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1 +#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }} +#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }} +#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }} +#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }} +#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} +#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} +#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} +#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 SPARangeStructureIndex; + UINT16 Flags; + UINT32 Reserved_8; + UINT32 ProximityDomain; + GUID AddressRangeTypeGUID; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; + UINT64 AddressRangeMemoryMappingAttribute; +} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE; + +// +// Definition for Memory Device to System Physical Address Range Mapping Structure +// +typedef struct { + UINT32 DIMMNumber:4; + UINT32 MemoryChannelNumber:4; + UINT32 MemoryControllerID:4; + UINT32 SocketID:4; + UINT32 NodeControllerID:12; + UINT32 Reserved_28:4; +} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE; + +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5 +#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6 +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NVDIMMPhysicalID; + UINT16 NVDIMMRegionID; + UINT16 SPARangeStructureIndex ; + UINT16 NVDIMMControlRegionStructureIndex; + UINT64 NVDIMMRegionSize; + UINT64 RegionOffset; + UINT64 NVDIMMPhysicalAddressRegionBase; + UINT16 InterleaveStructureIndex; + UINT16 InterleaveWays; + UINT16 NVDIMMStateFlags; + UINT16 Reserved_46; +} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE; + +// +// Definition for Interleave Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 InterleaveStructureIndex; + UINT16 Reserved_6; + UINT32 NumberOfLines; + UINT32 LineSize; +//UINT32 LineOffset[NumberOfLines]; +} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE; + +// +// Definition for SMBIOS Management Information Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT32 Reserved_4; +//UINT8 Data[]; +} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE; + +// +// Definition for NVDIMM Control Region Structure +// +#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0 + +#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0 +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 ValidFields; + UINT8 ManufacturingLocation; + UINT16 ManufacturingDate; + UINT8 Reserved_22[2]; + UINT32 SerialNumber; + UINT16 RegionFormatInterfaceCode; + UINT16 NumberOfBlockControlWindows; + UINT64 SizeOfBlockControlWindow; + UINT64 CommandRegisterOffsetInBlockControlWindow; + UINT64 SizeOfCommandRegisterInBlockControlWindows; + UINT64 StatusRegisterOffsetInBlockControlWindow; + UINT64 SizeOfStatusRegisterInBlockControlWindows; + UINT16 NVDIMMControlRegionFlag; + UINT8 Reserved_74[6]; +} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE; + +// +// Definition for NVDIMM Block Data Window Region Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 NumberOfBlockDataWindows; + UINT64 BlockDataWindowStartOffset; + UINT64 SizeOfBlockDataWindow; + UINT64 BlockAccessibleMemoryCapacity; + UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory; +} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE; + +// +// Definition for Flush Hint Address Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NumberOfFlushHintAddresses; + UINT8 Reserved_10[6]; +//UINT64 FlushHintAddress[NumberOfFlushHintAddresses]; +} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE; + +/// +/// Secure DEVices Table (SDEV) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER; + +/// +/// SDEV Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01 + +/// +/// Secure Devcice types +/// +#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01 +#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00 + +/// +/// Secure Devcice flags +/// +#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0 + +/// +/// SDEV Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; +} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER; + +/// +/// PCIe Endpoint Device based Secure Device Structure +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; + UINT16 PciSegmentNumber; + UINT16 StartBusNumber; + UINT16 PciPathOffset; + UINT16 PciPathLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; +} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE; + +/// +/// ACPI_NAMESPACE_DEVICE based Secure Device Structure +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; + UINT16 DeviceIdentifierOffset; + UINT16 DeviceIdentifierLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; +} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_6_3_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; + UINT8 Timestamp[8]; +} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR 0x09 +#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B + +// +// Error Source structure flags. +// +#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) +#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09 +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A +#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Hardware Error Source Version 2 Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister; + UINT64 ReadAckPreserve; + UINT64 ReadAckWrite; +} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// IA-32 Architecture Deferred Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;; + +/// +/// HMAT - Heterogeneous Memory Attribute Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[4]; +} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER; + +/// +/// HMAT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02 + +/// +/// HMAT types +/// +#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00 +#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01 +#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02 + +/// +/// HMAT Structure Header +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; +} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER; + +/// +/// Memory Proximity Domain Attributes Structure flags +/// +typedef struct { + UINT16 InitiatorProximityDomainValid:1; + UINT16 Reserved:15; +} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS; + +/// +/// Memory Proximity Domain Attributes Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags; + UINT8 Reserved1[2]; + UINT32 InitiatorProximityDomain; + UINT32 MemoryProximityDomain; + UINT8 Reserved2[20]; +} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES; + +/// +/// System Locality Latency and Bandwidth Information Structure flags +/// +typedef struct { + UINT8 MemoryHierarchy:4; + UINT8 Reserved:4; +} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS; + +/// +/// System Locality Latency and Bandwidth Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags; + UINT8 DataType; + UINT8 Reserved1[2]; + UINT32 NumberOfInitiatorProximityDomains; + UINT32 NumberOfTargetProximityDomains; + UINT8 Reserved2[4]; + UINT64 EntryBaseUnit; +} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO; + +/// +/// Memory Side Cache Information Structure cache attributes +/// +typedef struct { + UINT32 TotalCacheLevels:4; + UINT32 CacheLevel:4; + UINT32 CacheAssociativity:4; + UINT32 WritePolicy:4; + UINT32 CacheLineSize:16; +} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES; + +/// +/// Memory Side Cache Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + UINT32 MemoryProximityDomain; + UINT8 Reserved1[4]; + UINT64 MemorySideCacheSize; + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes; + UINT8 Reserved2[2]; + UINT16 NumberOfSmbiosHandles; +} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03 +#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F +#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10 + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_3_ERST_NOOP 0x04 +#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_6_3_ERST_ADD 0x08 +#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09 +#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_6_3_ERST_STALL 0x0C +#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_6_3_ERST_GOTO 0x0F +#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_3_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00 +#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01 +#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02 +#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03 +#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 NotifyOnCompletion:1; +} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 PlatformInterrupt:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0 +#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1 + +/// +/// Type 1 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 2 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckWrite; +} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 3 Extended PCC Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT32 AddressLength; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT32 MinimumRequestTurnaroundTime; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckSet; + UINT8 Reserved1[8]; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister; + UINT64 CommandCompleteCheckMask; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister; + UINT64 CommandCompleteUpdatePreserve; + UINT64 CommandCompleteUpdateSet; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister; + UINT64 ErrorStatusMask; +} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC; + +/// +/// Type 4 Extended PCC Subspace Structure +/// +typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC; + +#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0 + +typedef struct { + UINT32 Signature; + UINT32 Flags; + UINT32 Length; + UINT32 Command; +} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER; + +/// +/// Platform Debug Trigger Table (PDTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 TriggerCount; + UINT8 Reserved[3]; + UINT32 TriggerIdentifierArrayOffset; +} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER; + +/// +/// PDTT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00 + +/// +/// PDTT Platform Communication Channel Identifier Structure +/// +typedef struct { + UINT16 SubChannelIdentifer:8; + UINT16 Runtime:1; + UINT16 WaitForCompletion:1; + UINT16 TriggerOrder:1; + UINT16 Reserved:5; +} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER; + +/// +/// PCC Commands Codes used by Platform Debug Trigger Table +/// +#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00 +#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01 + +/// +/// PPTT Platform Communication Channel +/// +typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_PCC; + +/// +/// Processor Properties Topology Table (PPTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER; + +/// +/// PPTT Revision (as defined in ACPI 6.3 spec.) +/// +#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02 + +/// +/// PPTT types +/// +#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00 +#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01 +#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02 + +/// +/// PPTT Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; +} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER; + +/// +/// For PPTT struct processor flags +/// +#define EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL 0x0 +#define EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL 0x1 +#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD 0x0 +#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD 0x1 +#define EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF 0x0 +#define EFI_ACPI_6_3_PPTT_NODE_IS_LEAF 0x1 +#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0 +#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL 0x1 + +/// +/// Processor hierarchy node structure flags +/// +typedef struct { + UINT32 PhysicalPackage:1; + UINT32 AcpiProcessorIdValid:1; + UINT32 ProcessorIsAThread:1; + UINT32 NodeIsALeaf:1; + UINT32 IdenticalImplementation:1; + UINT32 Reserved:27; +} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS; + +/// +/// Processor hierarchy node structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags; + UINT32 Parent; + UINT32 AcpiProcessorId; + UINT32 NumberOfPrivateResources; +} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR; + +/// +/// For PPTT struct cache flags +/// +#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1 +#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1 + +/// +/// Cache Type Structure flags +/// +typedef struct { + UINT32 SizePropertyValid:1; + UINT32 NumberOfSetsValid:1; + UINT32 AssociativityValid:1; + UINT32 AllocationTypeValid:1; + UINT32 CacheTypeValid:1; + UINT32 WritePolicyValid:1; + UINT32 LineSizeValid:1; + UINT32 Reserved:25; +} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS; + +/// +/// For cache attributes +/// +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0 +#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1 + +/// +/// Cache Type Structure cache attributes +/// +typedef struct { + UINT8 AllocationType:2; + UINT8 CacheType:2; + UINT8 WritePolicy:1; + UINT8 Reserved:3; +} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES; + +/// +/// Cache Type Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags; + UINT32 NextLevelOfCache; + UINT32 Size; + UINT32 NumberOfSets; + UINT8 Associativity; + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes; + UINT16 LineSize; +} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE; + +/// +/// ID structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 VendorId; + UINT64 Level1Id; + UINT64 Level2Id; + UINT16 MajorRev; + UINT16 MinorRev; + UINT16 SpinRev; +} EFI_ACPI_6_3_PPTT_STRUCTURE_ID; + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CDIT" Component Distance Information Table +/// +#define EFI_ACPI_6_3_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "CRAT" Component Resource Attribute Table +/// +#define EFI_ACPI_6_3_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "HMAT" Heterogeneous Memory Attribute Table +/// +#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "NFIT" NVDIMM Firmware Interface Table +/// +#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T') + +/// +/// "PDTT" Platform Debug Trigger Table +/// +#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_6_3_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PPTT" Processor Properties Topology Table +/// +#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_6_3_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_6_3_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_6_3_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SDEV" Secure DEVices Table +/// +#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_6_3_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_6_3_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_6_3_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DPPT" DMA Protection Policy Table +/// +#define EFI_ACPI_6_3_DMA_PROTECTION_POLICY_TABLE_SIGNATURE SIGNATURE_32('D', 'P', 'P', 'T') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_6_3_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_6_3_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_6_3_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IORT" I/O Remapping Table +/// +#define EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_6_3_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_6_3_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_6_3_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_6_3_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "SDEI" Software Delegated Exceptions Interface Table +/// +#define EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_6_3_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Concole Redirection Table +/// +#define EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_6_3_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "STAO" _STA Override Table +/// +#define EFI_ACPI_6_3_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_6_3_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_6_3_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_6_3_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_6_3_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_6_3_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +/// +/// "WSMT" Windows SMM Security Mitigation Table +/// +#define EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T') + +/// +/// "XENV" Xen Project Table +/// +#define EFI_ACPI_6_3_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi64.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi64.h new file mode 100644 index 0000000000..706e795d58 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Acpi64.h @@ -0,0 +1,3148 @@ +/** @file + ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef ACPI_6_4_H_ +#define ACPI_6_4_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// ACPI 6.4 Generic Address Space definition +/// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_6_4_SYSTEM_MEMORY 0x00 +#define EFI_ACPI_6_4_SYSTEM_IO 0x01 +#define EFI_ACPI_6_4_PCI_CONFIGURATION_SPACE 0x02 +#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER 0x03 +#define EFI_ACPI_6_4_SMBUS 0x04 +#define EFI_ACPI_6_4_SYSTEM_CMOS 0x05 +#define EFI_ACPI_6_4_PCI_BAR_TARGET 0x06 +#define EFI_ACPI_6_4_IPMI 0x07 +#define EFI_ACPI_6_4_GENERAL_PURPOSE_IO 0x08 +#define EFI_ACPI_6_4_GENERIC_SERIAL_BUS 0x09 +#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL 0x0A +#define EFI_ACPI_6_4_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_6_4_UNDEFINED 0 +#define EFI_ACPI_6_4_BYTE 1 +#define EFI_ACPI_6_4_WORD 2 +#define EFI_ACPI_6_4_DWORD 3 +#define EFI_ACPI_6_4_QWORD 4 + +// +// ACPI 6.4 table structures +// + +/// +/// Root System Description Pointer Structure +/// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER; + +/// +/// RSD_PTR Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2 + +/// +/// Common table header, this prefaces all ACPI tables, including FACS, but +/// excluding the RSD PTR structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_4_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers. +// + +/// +/// RSDT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers. +// + +/// +/// XSDT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Fixed ACPI Description Table Structure (FADT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT16 ArmBootArch; + UINT8 MinorVersion; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg; + UINT64 HypervisorVendorIdentity; +} EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE; + +/// +/// FADT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06 +#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x04 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_6_4_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_6_4_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_6_4_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_6_4_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_6_4_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_6_4_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_6_4_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_6_4_PM_PROFILE_PERFORMANCE_SERVER 7 +#define EFI_ACPI_6_4_PM_PROFILE_TABLET 8 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0 +#define EFI_ACPI_6_4_8042 BIT1 +#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2 +#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3 +#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4 +#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5 + +// +// Fixed ACPI Description Table Arm Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0 +#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1 + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_4_WBINVD BIT0 +#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1 +#define EFI_ACPI_6_4_PROC_C1 BIT2 +#define EFI_ACPI_6_4_P_LVL2_UP BIT3 +#define EFI_ACPI_6_4_PWR_BUTTON BIT4 +#define EFI_ACPI_6_4_SLP_BUTTON BIT5 +#define EFI_ACPI_6_4_FIX_RTC BIT6 +#define EFI_ACPI_6_4_RTC_S4 BIT7 +#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8 +#define EFI_ACPI_6_4_DCK_CAP BIT9 +#define EFI_ACPI_6_4_RESET_REG_SUP BIT10 +#define EFI_ACPI_6_4_SEALED_CASE BIT11 +#define EFI_ACPI_6_4_HEADLESS BIT12 +#define EFI_ACPI_6_4_CPU_SW_SLP BIT13 +#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14 +#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15 +#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16 +#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17 +#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18 +#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19 +#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20 +#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21 + +/// +/// Firmware ACPI Control Structure +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved0[3]; + UINT32 OspmFlags; + UINT8 Reserved1[24]; +} EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +/// +/// FACS Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x02 + +/// +/// Firmware Control Structure Feature Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_4_S4BIOS_F BIT0 +#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1 + +/// +/// OSPM Enabled Firmware Control Structure Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0 + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header, the same with +// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block. +// +#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +/// +/// Multiple APIC Description Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +/// +/// MADT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05 + +/// +/// Multiple APIC Flags +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_4_PCAT_COMPAT BIT0 + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x10 and 0x7F are reserved and +// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM. +// +#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_6_4_IO_APIC 0x01 +#define EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_6_4_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_6_4_IO_SAPIC 0x06 +#define EFI_ACPI_6_4_LOCAL_SAPIC 0x07 +#define EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES 0x08 +#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC 0x09 +#define EFI_ACPI_6_4_LOCAL_X2APIC_NMI 0x0A +#define EFI_ACPI_6_4_GIC 0x0B +#define EFI_ACPI_6_4_GICD 0x0C +#define EFI_ACPI_6_4_GIC_MSI_FRAME 0x0D +#define EFI_ACPI_6_4_GICR 0x0E +#define EFI_ACPI_6_4_GIC_ITS 0x0F +#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP 0x10 + +// +// APIC Structure Definitions +// + +/// +/// Processor Local APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE; + +/// +/// Local APIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_LOCAL_APIC_ENABLED BIT0 +#define EFI_ACPI_6_4_LOCAL_APIC_ONLINE_CAPABLE BIT1 + +/// +/// IO APIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_6_4_IO_APIC_STRUCTURE; + +/// +/// Interrupt Source Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_6_4_POLARITY (3 << 0) +#define EFI_ACPI_6_4_TRIGGER_MODE (3 << 2) + +/// +/// Non-Maskable Interrupt Source Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +/// +/// Local APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorUid; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE; + +/// +/// Local APIC Address Override Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +/// +/// IO SAPIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_6_4_IO_SAPIC_STRUCTURE; + +/// +/// Local SAPIC Structure +/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +/// +/// Platform Interrupt Sources Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +/// +/// Platform Interrupt Source Flags. +/// All other bits are reserved and must be set to 0. +/// +#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0 + +/// +/// Processor Local x2APIC Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 AcpiProcessorUid; +} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE; + +/// +/// Local x2APIC NMI Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 AcpiProcessorUid; + UINT8 LocalX2ApicLint; + UINT8 Reserved[3]; +} EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE; + +/// +/// GIC Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 CPUInterfaceNumber; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ParkingProtocolVersion; + UINT32 PerformanceInterruptGsiv; + UINT64 ParkedAddress; + UINT64 PhysicalBaseAddress; + UINT64 GICV; + UINT64 GICH; + UINT32 VGICMaintenanceInterrupt; + UINT64 GICRBaseAddress; + UINT64 MPIDR; + UINT8 ProcessorPowerEfficiencyClass; + UINT8 Reserved2; + UINT16 SpeOverflowInterrupt; +} EFI_ACPI_6_4_GIC_STRUCTURE; + +/// +/// GIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GIC_ENABLED BIT0 +#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1 +#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2 + +/// +/// GIC Distributor Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicId; + UINT64 PhysicalBaseAddress; + UINT32 SystemVectorBase; + UINT8 GicVersion; + UINT8 Reserved2[3]; +} EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE; + +/// +/// GIC Version +/// +#define EFI_ACPI_6_4_GIC_V1 0x01 +#define EFI_ACPI_6_4_GIC_V2 0x02 +#define EFI_ACPI_6_4_GIC_V3 0x03 +#define EFI_ACPI_6_4_GIC_V4 0x04 + +/// +/// GIC MSI Frame Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved1; + UINT32 GicMsiFrameId; + UINT64 PhysicalBaseAddress; + UINT32 Flags; + UINT16 SPICount; + UINT16 SPIBase; +} EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE; + +/// +/// GIC MSI Frame Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0 + +/// +/// GICR Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 DiscoveryRangeBaseAddress; + UINT32 DiscoveryRangeLength; +} EFI_ACPI_6_4_GICR_STRUCTURE; + +/// +/// GIC Interrupt Translation Service Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT32 GicItsId; + UINT64 PhysicalBaseAddress; + UINT32 Reserved2; +} EFI_ACPI_6_4_GIC_ITS_STRUCTURE; + +/// +/// Multiprocessor Wakeup Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 MailBoxVersion; + UINT32 Reserved; + UINT64 MailBoxAddress; +} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE; + +/// +/// Multiprocessor Wakeup Mailbox Structure +/// +typedef struct { + UINT16 Command; + UINT16 Reserved; + UINT32 AcpiId; + UINT64 WakeupVector; + UINT8 ReservedForOs[2032]; + UINT8 ReservedForFirmware[2048]; +} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE; + +#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000 +#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001 + +/// +/// Smart Battery Description Table (SBST) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE; + +/// +/// SBST Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +/// +/// Embedded Controller Boot Resources Table (ECDT) +/// The table is followed by a null terminated ASCII string that contains +/// a fully qualified reference to the name space object. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +/// +/// ECDT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +/// +/// System Resource Affinity Table (SRAT). The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; ///< Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +/// +/// SRAT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x03 + +// +// SRAT structure types. +// All other values between 0x06 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_6_4_MEMORY_AFFINITY 0x01 +#define EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY 0x02 +#define EFI_ACPI_6_4_GICC_AFFINITY 0x03 +#define EFI_ACPI_6_4_GIC_ITS_AFFINITY 0x04 +#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY 0x05 + +/// +/// Processor Local APIC/SAPIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT32 ClockDomain; +} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +/// +/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +/// +/// Memory Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2) + +/// +/// Processor Local x2APIC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1[2]; + UINT32 ProximityDomain; + UINT32 X2ApicId; + UINT32 Flags; + UINT32 ClockDomain; + UINT8 Reserved2[4]; +} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE; + +/// +/// GICC Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT32 AcpiProcessorUid; + UINT32 Flags; + UINT32 ClockDomain; +} EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE; + +/// +/// GICC Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0) + +/// +/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT8 Reserved[2]; + UINT32 ItsId; +} EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE; + +// +// Generic Initiator Affinity Structure Device Handle Types +// All other values between 0x02 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00 +#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01 + +/// +/// Device Handle - ACPI +/// +typedef struct { + UINT64 AcpiHid; + UINT32 AcpiUid; + UINT8 Reserved[4]; +} EFI_ACPI_6_4_DEVICE_HANDLE_ACPI; + +/// +/// Device Handle - PCI +/// +typedef struct { + UINT16 PciSegment; + UINT16 PciBdfNumber; + UINT8 Reserved[12]; +} EFI_ACPI_6_4_DEVICE_HANDLE_PCI; + +/// +/// Device Handle +/// +typedef union { + EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi; + EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci; +} EFI_ACPI_6_4_DEVICE_HANDLE; + +/// +/// Generic Initiator Affinity Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved1; + UINT8 DeviceHandleType; + UINT32 ProximityDomain; + EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle; + UINT32 Flags; + UINT8 Reserved2[4]; +} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE; + +/// +/// Generic Initiator Affinity Structure Flags. All other bits are reserved +/// and must be 0. +/// +#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0 +#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1 + +/// +/// System Locality Distance Information Table (SLIT). +/// The rest of the table is a matrix. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +/// +/// SLIT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +/// +/// Corrected Platform Error Polling Table (CPEP) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[8]; +} EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER; + +/// +/// CPEP Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01 + +// +// CPEP processor structure types. +// +#define EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC 0x00 + +/// +/// Corrected Platform Error Polling Processor Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT32 PollingInterval; +} EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE; + +/// +/// Maximum System Characteristics Table (MSCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaximumNumberOfProximityDomains; + UINT32 MaximumNumberOfClockDomains; + UINT64 MaximumPhysicalAddress; +} EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER; + +/// +/// MSCT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 + +/// +/// Maximum Proximity Domain Information Structure Definition +/// +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProximityDomainRangeLow; + UINT32 ProximityDomainRangeHigh; + UINT32 MaximumProcessorCapacity; + UINT64 MaximumMemoryCapacity; +} EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +/// +/// ACPI RAS Feature Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier[12]; +} EFI_ACPI_6_4_RAS_FEATURE_TABLE; + +/// +/// RASF Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01 + +/// +/// ACPI RASF Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT8 RASCapabilities[16]; + UINT8 SetRASCapabilities[16]; + UINT16 NumberOfRASFParameterBlocks; + UINT32 SetRASCapabilitiesStatus; +} EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI RASF PCC command code +/// +#define EFI_ACPI_6_4_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND 0x01 + +/// +/// ACPI RASF Platform RAS Capabilities +/// +#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0 +#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1 +#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2 +#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3 +#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4 + +/// +/// ACPI RASF Parameter Block structure for PATROL_SCRUB +/// +typedef struct { + UINT16 Type; + UINT16 Version; + UINT16 Length; + UINT16 PatrolScrubCommand; + UINT64 RequestedAddressRange[2]; + UINT64 ActualAddressRange[2]; + UINT16 Flags; + UINT8 RequestedSpeed; +} EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE; + +/// +/// ACPI RASF Patrol Scrub command +/// +#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01 +#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02 +#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03 + +/// +/// Memory Power State Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 PlatformCommunicationChannelIdentifier; + UINT8 Reserved[3]; +// Memory Power Node Structure +// Memory Power State Characteristics +} EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE; + +/// +/// MPST Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01 + +/// +/// MPST Platform Communication Channel Shared Memory Region definition. +/// +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT32 MemoryPowerCommandRegister; + UINT32 MemoryPowerStatusRegister; + UINT32 PowerStateId; + UINT32 MemoryPowerNodeId; + UINT64 MemoryEnergyConsumed; + UINT64 ExpectedAveragePowerComsuned; +} EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION; + +/// +/// ACPI MPST PCC command code +/// +#define EFI_ACPI_6_4_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND 0x03 + +/// +/// ACPI MPST Memory Power command +/// +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04 + +/// +/// MPST Memory Power Node Table +/// +typedef struct { + UINT8 PowerStateValue; + UINT8 PowerStateInformationIndex; +} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE; + +typedef struct { + UINT8 Flag; + UINT8 Reserved; + UINT16 MemoryPowerNodeId; + UINT32 Length; + UINT64 AddressBase; + UINT64 AddressLength; + UINT32 NumberOfPowerStates; + UINT32 NumberOfPhysicalComponents; +//EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates]; +//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents]; +} EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE; + +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04 + +typedef struct { + UINT16 MemoryPowerNodeCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE; + +/// +/// MPST Memory Power State Characteristics Table +/// +typedef struct { + UINT8 PowerStateStructureID; + UINT8 Flag; + UINT16 Reserved; + UINT32 AveragePowerConsumedInMPS0; + UINT32 RelativePowerSavingToMPS0; + UINT64 ExitLatencyToMPS0; +} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE; + +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02 +#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04 + +typedef struct { + UINT16 MemoryPowerStateCharacteristicsCount; + UINT8 Reserved[2]; +} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE; + +/// +/// Platform Memory Topology Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 NumberOfMemoryDevices; +//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices]; +} EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE; + +/// +/// PMTT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02 + +/// +/// Common Memory Device. +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; + UINT16 Flags; + UINT16 Reserved1; + UINT32 NumberOfMemoryDevices; +//UINT8 TypeSpecificData[]; +//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices]; +} EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE; + +/// +/// Memory Device Type. +/// +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0 +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1 +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2 +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF + +/// +/// Socket Type Data. +/// +typedef struct { + EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader; + UINT16 SocketIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[]; +} EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA; + +/// +/// Memory Controller Type Data. +/// +typedef struct { + EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader; + UINT16 MemoryControllerIdentifier; + UINT16 Reserved; +//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[]; +} EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA; + +/// +/// DIMM Type Specific Data. +/// +typedef struct { + EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader; + UINT32 SmbiosHandle; +} EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA; + +/// +/// Vendor Specific Type Data. +/// +typedef struct { + EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader; + UINT8 TypeUuid[16]; +//EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[]; +//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[]; +} EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA; + +/// +/// Boot Graphics Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// 2-bytes (16 bit) version ID. This value must be 1. + /// + UINT16 Version; + /// + /// 1-byte status field indicating current status about the table. + /// Bits[7:3] = Reserved (must be zero) + /// Bits[2:1] = Orientation Offset. These bits describe the clockwise + /// degree offset from the image's default orientation. + /// [00] = 0, no offset + /// [01] = 90 + /// [10] = 180 + /// [11] = 270 + /// Bit [0] = Displayed. A one indicates the boot image graphic is + /// displayed. + /// + UINT8 Status; + /// + /// 1-byte enumerated type field indicating format of the image. + /// 0 = Bitmap + /// 1 - 255 Reserved (for future use) + /// + UINT8 ImageType; + /// + /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy + /// of the image bitmap. + /// + UINT64 ImageAddress; + /// + /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetX; + /// + /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image. + /// (X, Y) display offset of the top left corner of the boot image. + /// The top left corner of the display is at offset (0, 0). + /// + UINT32 ImageOffsetY; +} EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE; + +/// +/// BGRT Revision +/// +#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1 + +/// +/// BGRT Version +/// +#define EFI_ACPI_6_4_BGRT_VERSION 0x01 + +/// +/// BGRT Status +/// +#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00 +#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01 + +/// +/// BGRT Image Type +/// +#define EFI_ACPI_6_4_BGRT_IMAGE_TYPE_BMP 0x00 + +/// +/// FPDT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01 + +/// +/// FPDT Performance Record Types +/// +#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000 +#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001 + +/// +/// FPDT Performance Record Revision +/// +#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01 +#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01 + +/// +/// FPDT Runtime Performance Record Types +/// +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000 +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001 +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002 + +/// +/// FPDT Runtime Performance Record Revision +/// +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME 0x01 +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND 0x01 +#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT 0x02 + +/// +/// FPDT Performance Record header +/// +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; +} EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER; + +/// +/// FPDT Performance Table header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER; + +/// +/// FPDT Firmware Basic Boot Performance Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the Basic Boot Performance Table. + /// + UINT64 BootPerformanceTablePointer; +} EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT S3 Performance Table Pointer Record Structure +/// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// 64-bit processor-relative physical address of the S3 Performance Table. + /// + UINT64 S3PerformanceTablePointer; +} EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Record Structure +/// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header; + UINT32 Reserved; + /// + /// Timer value logged at the beginning of firmware image execution. + /// This may not always be zero or near zero. + /// + UINT64 ResetEnd; + /// + /// Timer value logged just prior to loading the OS boot loader into memory. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 OsLoaderLoadImageStart; + /// + /// Timer value logged just prior to launching the previously loaded OS boot loader image. + /// For non-UEFI compatible boots, the timer value logged will be just prior + /// to the INT 19h handler invocation. + /// + UINT64 OsLoaderStartImageStart; + /// + /// Timer value logged at the point when the OS loader calls the + /// ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesEntry; + /// + /// Timer value logged at the point just prior towhen the OS loader gaining + /// control back from calls the ExitBootServices function for UEFI compatible firmware. + /// For non-UEFI compatible boots, this field must be zero. + /// + UINT64 ExitBootServicesExit; +} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD; + +/// +/// FPDT Firmware Basic Boot Performance Table signature +/// +#define EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('F', 'B', 'P', 'T') + +// +// FPDT Firmware Basic Boot Performance Table +// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_TABLE; + +/// +/// FPDT "S3PT" S3 Performance Table +/// +#define EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE SIGNATURE_32('S', '3', 'P', 'T') + +// +// FPDT Firmware S3 Boot Performance Table +// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header; + // + // one or more Performance Records. + // +} EFI_ACPI_6_4_FPDT_FIRMWARE_S3_BOOT_TABLE; + +/// +/// FPDT Basic S3 Resume Performance Record +/// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// A count of the number of S3 resume cycles since the last full boot sequence. + /// + UINT32 ResumeCount; + /// + /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the + /// OS waking vector. Only the most recent resume cycle's time is retained. + /// + UINT64 FullResume; + /// + /// Average timer value of all resume cycles logged since the last full boot + /// sequence, including the most recent resume. Note that the entire log of + /// timer values does not need to be retained in order to calculate this average. + /// + UINT64 AverageResume; +} EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD; + +/// +/// FPDT Basic S3 Suspend Performance Record +/// +typedef struct { + EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header; + /// + /// Timer value recorded at the OS write to SLP_TYP upon entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendStart; + /// + /// Timer value recorded at the final firmware write to SLP_TYP (or other + /// mechanism) used to trigger hardware entry to S3. + /// Only the most recent suspend cycle's timer value is retained. + /// + UINT64 SuspendEnd; +} EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD; + +/// +/// Firmware Performance Record Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE; + +/// +/// Generic Timer Description Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 CntControlBasePhysicalAddress; + UINT32 Reserved; + UINT32 SecurePL1TimerGSIV; + UINT32 SecurePL1TimerFlags; + UINT32 NonSecurePL1TimerGSIV; + UINT32 NonSecurePL1TimerFlags; + UINT32 VirtualTimerGSIV; + UINT32 VirtualTimerFlags; + UINT32 NonSecurePL2TimerGSIV; + UINT32 NonSecurePL2TimerFlags; + UINT64 CntReadBasePhysicalAddress; + UINT32 PlatformTimerCount; + UINT32 PlatformTimerOffset; + UINT32 VirtualPL2TimerGSIV; + UINT32 VirtualPL2TimerFlags; +} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE; + +/// +/// GTDT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03 + +/// +/// Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2 + +/// +/// Platform Timer Type +/// +#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0 +#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1 + +/// +/// GT Block Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 CntCtlBase; + UINT32 GTBlockTimerCount; + UINT32 GTBlockTimerOffset; +} EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE; + +/// +/// GT Block Timer Structure +/// +typedef struct { + UINT8 GTFrameNumber; + UINT8 Reserved[3]; + UINT64 CntBaseX; + UINT64 CntEL0BaseX; + UINT32 GTxPhysicalTimerGSIV; + UINT32 GTxPhysicalTimerFlags; + UINT32 GTxVirtualTimerGSIV; + UINT32 GTxVirtualTimerFlags; + UINT32 GTxCommonFlags; +} EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE; + +/// +/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1 + +/// +/// Common Flags Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0 +#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1 + +/// +/// Arm Generic Watchdog Structure +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Reserved; + UINT64 RefreshFramePhysicalAddress; + UINT64 WatchdogControlFramePhysicalAddress; + UINT32 WatchdogTimerGSIV; + UINT32 WatchdogTimerFlags; +} EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE; + +/// +/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0. +/// +#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0 +#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1 +#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2 + +// +// NVDIMM Firmware Interface Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; +} EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE; + +// +// NFIT Version (as defined in ACPI 6.4 spec.) +// +#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1 + +// +// Definition for NFIT Table Structure Types +// +#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1 +#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2 +#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3 +#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4 +#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5 +#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6 + +// +// Definition for NFIT Structure Header +// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER; + +// +// Definition for System Physical Address Range Structure +// +#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0 +#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1 +#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2 + +#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }} +#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }} +#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }} +#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }} +#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }} +#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }} +#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }} +#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }} + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 SPARangeStructureIndex; + UINT16 Flags; + UINT32 Reserved_8; + UINT32 ProximityDomain; + GUID AddressRangeTypeGUID; + UINT64 SystemPhysicalAddressRangeBase; + UINT64 SystemPhysicalAddressRangeLength; + UINT64 AddressRangeMemoryMappingAttribute; + UINT64 SPALocationCookie; +} EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE; + +// +// Definition for Memory Device to System Physical Address Range Mapping Structure +// +typedef struct { + UINT32 DIMMNumber:4; + UINT32 MemoryChannelNumber:4; + UINT32 MemoryControllerID:4; + UINT32 SocketID:4; + UINT32 NodeControllerID:12; + UINT32 Reserved_28:4; +} EFI_ACPI_6_4_NFIT_DEVICE_HANDLE; + +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL BIT1 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL BIT2 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF BIT3 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5 +#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6 + +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NVDIMMPhysicalID; + UINT16 NVDIMMRegionID; + UINT16 SPARangeStructureIndex ; + UINT16 NVDIMMControlRegionStructureIndex; + UINT64 NVDIMMRegionSize; + UINT64 RegionOffset; + UINT64 NVDIMMPhysicalAddressRegionBase; + UINT16 InterleaveStructureIndex; + UINT16 InterleaveWays; + UINT16 NVDIMMStateFlags; + UINT16 Reserved_46; +} EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE; + +// +// Definition for Interleave Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 InterleaveStructureIndex; + UINT16 Reserved_6; + UINT32 NumberOfLines; + UINT32 LineSize; +//UINT32 LineOffset[NumberOfLines]; +} EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE; + +// +// Definition for SMBIOS Management Information Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT32 Reserved_4; +//UINT8 Data[]; +} EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE; + +// +// Definition for NVDIMM Control Region Structure +// +#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0 + +#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0 + +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 VendorID; + UINT16 DeviceID; + UINT16 RevisionID; + UINT16 SubsystemVendorID; + UINT16 SubsystemDeviceID; + UINT16 SubsystemRevisionID; + UINT8 ValidFields; + UINT8 ManufacturingLocation; + UINT16 ManufacturingDate; + UINT8 Reserved_22[2]; + UINT32 SerialNumber; + UINT16 RegionFormatInterfaceCode; + UINT16 NumberOfBlockControlWindows; + UINT64 SizeOfBlockControlWindow; + UINT64 CommandRegisterOffsetInBlockControlWindow; + UINT64 SizeOfCommandRegisterInBlockControlWindows; + UINT64 StatusRegisterOffsetInBlockControlWindow; + UINT64 SizeOfStatusRegisterInBlockControlWindows; + UINT16 NVDIMMControlRegionFlag; + UINT8 Reserved_74[6]; +} EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE; + +// +// Definition for NVDIMM Block Data Window Region Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + UINT16 NVDIMMControlRegionStructureIndex; + UINT16 NumberOfBlockDataWindows; + UINT64 BlockDataWindowStartOffset; + UINT64 SizeOfBlockDataWindow; + UINT64 BlockAccessibleMemoryCapacity; + UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory; +} EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE; + +// +// Definition for Flush Hint Address Structure +// +typedef struct { + UINT16 Type; + UINT16 Length; + EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle; + UINT16 NumberOfFlushHintAddresses; + UINT8 Reserved_10[6]; +//UINT64 FlushHintAddress[NumberOfFlushHintAddresses]; +} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE; + +/// +/// Secure DEVices Table (SDEV) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER; + +/// +/// SDEV Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01 + +/// +/// Secure Device types +/// +#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00 +#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01 + +/// +/// Secure Device flags +/// +#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0 +#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1 + +/// +/// SDEV Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Flags; + UINT16 Length; +} EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER; + +/// +/// ACPI_NAMESPACE_DEVICE based Secure Device Structure +/// +typedef struct { + EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header; + UINT16 DeviceIdentifierOffset; + UINT16 DeviceIdentifierLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; + UINT16 SecureAccessComponentsOffset; + UINT16 SecureAccessComponentsLength; +} EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE; + +/// +/// Secure Access Component Types +/// +#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00 +#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01 + +/// +/// Identification Based Secure Access Component +/// +typedef struct { + EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header; + UINT16 HardwareIdentifierOffset; + UINT16 HardwareIdentifierLength; + UINT16 SubsystemIdentifierOffset; + UINT16 SubsystemIdentifierLength; + UINT16 HardwareRevision; + UINT8 HardwareRevisionPresent; + UINT8 ClassCodePresent; + UINT8 PciCompatibleBaseClass; + UINT8 PciCompatibleSubClass; + UINT8 PciCompatibleProgrammingInterface; +} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE; + +/// +/// Memory-based Secure Access Component +/// +typedef struct { + EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header; + UINT32 Reserved; + UINT64 MemoryAddressBase; + UINT64 MemoryLength; +} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE; + +/// +/// PCIe Endpoint Device based Secure Device Structure +/// +typedef struct { + EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header; + UINT16 PciSegmentNumber; + UINT16 StartBusNumber; + UINT16 PciPathOffset; + UINT16 PciPathLength; + UINT16 VendorSpecificDataOffset; + UINT16 VendorSpecificDataLength; +} EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE; + +/// +/// Boot Error Record Table (BERT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 BootErrorRegionLength; + UINT64 BootErrorRegion; +} EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER; + +/// +/// BERT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01 + +/// +/// Boot Error Region Block Status Definition +/// +typedef struct { + UINT32 UncorrectableErrorValid:1; + UINT32 CorrectableErrorValid:1; + UINT32 MultipleUncorrectableErrors:1; + UINT32 MultipleCorrectableErrors:1; + UINT32 ErrorDataEntryCount:10; + UINT32 Reserved:18; +} EFI_ACPI_6_4_ERROR_BLOCK_STATUS; + +/// +/// Boot Error Region Definition +/// +typedef struct { + EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE; + +// +// Boot Error Severity types +// +#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTABLE 0x00 +#define EFI_ACPI_6_4_ERROR_SEVERITY_FATAL 0x01 +#define EFI_ACPI_6_4_ERROR_SEVERITY_CORRECTED 0x02 +#define EFI_ACPI_6_4_ERROR_SEVERITY_NONE 0x03 + +/// +/// Generic Error Data Entry Definition +/// +typedef struct { + UINT8 SectionType[16]; + UINT32 ErrorSeverity; + UINT16 Revision; + UINT8 ValidationBits; + UINT8 Flags; + UINT32 ErrorDataLength; + UINT8 FruId[16]; + UINT8 FruText[20]; + UINT8 Timestamp[8]; +} EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE; + +/// +/// Generic Error Data Entry Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_REVISION 0x0300 + +/// +/// HEST - Hardware Error Source Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ErrorSourceCount; +} EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER; + +/// +/// HEST Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01 + +// +// Error Source structure types. +// +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION 0x00 +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK 0x01 +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR 0x02 +#define EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER 0x06 +#define EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER 0x07 +#define EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER 0x08 +#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR 0x09 +#define EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_VERSION_2 0x0A +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK 0x0B + +// +// Error Source structure flags. +// +#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0) +#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1) +#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2) + +/// +/// IA-32 Architecture Machine Check Exception Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT64 GlobalCapabilityInitData; + UINT64 GlobalControlInitData; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[7]; +} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure Definition +/// +typedef struct { + UINT8 BankNumber; + UINT8 ClearStatusOnInitialization; + UINT8 StatusDataFormat; + UINT8 Reserved0; + UINT32 ControlRegisterMsrAddress; + UINT64 ControlInitData; + UINT32 StatusRegisterMsrAddress; + UINT32 AddressRegisterMsrAddress; + UINT32 MiscRegisterMsrAddress; +} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE; + +/// +/// IA-32 Architecture Machine Check Bank Structure MCA data format +/// +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00 +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01 +#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02 + +// +// Hardware Error Notification types. All other values are reserved +// +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09 +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A +#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B + +/// +/// Hardware Error Notification Configuration Write Enable Structure Definition +/// +typedef struct { + UINT16 Type:1; + UINT16 PollInterval:1; + UINT16 SwitchToPollingThresholdValue:1; + UINT16 SwitchToPollingThresholdWindow:1; + UINT16 ErrorThresholdValue:1; + UINT16 ErrorThresholdWindow:1; + UINT16 Reserved:10; +} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE; + +/// +/// Hardware Error Notification Structure Definition +/// +typedef struct { + UINT8 Type; + UINT8 Length; + EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; + UINT32 PollInterval; + UINT32 Vector; + UINT32 SwitchToPollingThresholdValue; + UINT32 SwitchToPollingThresholdWindow; + UINT32 ErrorThresholdValue; + UINT32 ErrorThresholdWindow; +} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE; + +/// +/// IA-32 Architecture Corrected Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE; + +/// +/// IA-32 Architecture NMI Error Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; +} EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE; + +/// +/// PCI Express Root Port AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 RootErrorCommand; +} EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE; + +/// +/// PCI Express Device AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE; + +/// +/// PCI Express Bridge AER Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 Bus; + UINT16 Device; + UINT16 Function; + UINT16 DeviceControl; + UINT8 Reserved1[2]; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 SecondaryUncorrectableErrorMask; + UINT32 SecondaryUncorrectableErrorSeverity; + UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; +} EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE; + +/// +/// Generic Hardware Error Source Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; +} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE; + +/// +/// Generic Hardware Error Source Version 2 Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT16 RelatedSourceId; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + UINT32 MaxRawDataLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; + EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT32 ErrorStatusBlockLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister; + UINT64 ReadAckPreserve; + UINT64 ReadAckWrite; +} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE; + +/// +/// Generic Error Status Definition +/// +typedef struct { + EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus; + UINT32 RawDataOffset; + UINT32 RawDataLength; + UINT32 DataLength; + UINT32 ErrorSeverity; +} EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE; + +/// +/// IA-32 Architecture Deferred Machine Check Structure Definition +/// +typedef struct { + UINT16 Type; + UINT16 SourceId; + UINT8 Reserved0[2]; + UINT8 Flags; + UINT8 Enabled; + UINT32 NumberOfRecordsToPreAllocate; + UINT32 MaxSectionsPerRecord; + EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; + UINT8 NumberOfHardwareBanks; + UINT8 Reserved1[3]; +} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;; + +/// +/// HMAT - Heterogeneous Memory Attribute Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 Reserved[4]; +} EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER; + +/// +/// HMAT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02 + +/// +/// HMAT types +/// +#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00 +#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01 +#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02 + +/// +/// HMAT Structure Header +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; +} EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER; + +/// +/// Memory Proximity Domain Attributes Structure flags +/// +typedef struct { + UINT16 InitiatorProximityDomainValid:1; + UINT16 Reserved:15; +} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS; + +/// +/// Memory Proximity Domain Attributes Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags; + UINT8 Reserved1[2]; + UINT32 InitiatorProximityDomain; + UINT32 MemoryProximityDomain; + UINT8 Reserved2[20]; +} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES; + +/// +/// System Locality Latency and Bandwidth Information Structure flags +/// +typedef struct { + UINT8 MemoryHierarchy:4; + UINT8 AccessAttributes:2; + UINT8 Reserved:2; +} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS; + +/// +/// System Locality Latency and Bandwidth Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags; + UINT8 DataType; + UINT8 MinTransferSize; + UINT8 Reserved1; + UINT32 NumberOfInitiatorProximityDomains; + UINT32 NumberOfTargetProximityDomains; + UINT8 Reserved2[4]; + UINT64 EntryBaseUnit; +} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO; + +/// +/// Memory Side Cache Information Structure cache attributes +/// +typedef struct { + UINT32 TotalCacheLevels:4; + UINT32 CacheLevel:4; + UINT32 CacheAssociativity:4; + UINT32 WritePolicy:4; + UINT32 CacheLineSize:16; +} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES; + +/// +/// Memory Side Cache Information Structure +/// +typedef struct { + UINT16 Type; + UINT8 Reserved[2]; + UINT32 Length; + UINT32 MemoryProximityDomain; + UINT8 Reserved1[4]; + UINT64 MemorySideCacheSize; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes; + UINT8 Reserved2[2]; + UINT16 NumberOfSmbiosHandles; +} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO; + +/// +/// ERST - Error Record Serialization Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 SerializationHeaderSize; + UINT8 Reserved0[4]; + UINT32 InstructionEntryCount; +} EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER; + +/// +/// ERST Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01 + +/// +/// ERST Serialization Actions +/// +#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00 +#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01 +#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02 +#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03 +#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04 +#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08 +#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09 +#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A +#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B +#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D +#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E +#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F +#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10 + +/// +/// ERST Action Command Status +/// +#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01 +#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02 +#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03 +#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04 +#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05 + +/// +/// ERST Serialization Instructions +/// +#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00 +#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_4_ERST_NOOP 0x04 +#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05 +#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06 +#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07 +#define EFI_ACPI_6_4_ERST_ADD 0x08 +#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09 +#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A +#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B +#define EFI_ACPI_6_4_ERST_STALL 0x0C +#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D +#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E +#define EFI_ACPI_6_4_ERST_GOTO 0x0F +#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10 +#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11 +#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12 + +/// +/// ERST Instruction Flags +/// +#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01 + +/// +/// ERST Serialization Instruction Entry +/// +typedef struct { + UINT8 SerializationAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY; + +/// +/// EINJ - Error Injection Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 InjectionHeaderSize; + UINT8 InjectionFlags; + UINT8 Reserved0[3]; + UINT32 InjectionEntryCount; +} EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER; + +/// +/// EINJ Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01 + +/// +/// EINJ Error Injection Actions +/// +#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00 +#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01 +#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02 +#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03 +#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04 +#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05 +#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06 +#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07 +#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF + +/// +/// EINJ Action Command Status +/// +#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00 +#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01 +#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02 + +/// +/// EINJ Error Type Definition +/// +#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0) +#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1) +#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2) +#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3) +#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4) +#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5) +#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6) +#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7) +#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8) +#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9) +#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10) +#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11) + +/// +/// EINJ Injection Instructions +/// +#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00 +#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01 +#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02 +#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03 +#define EFI_ACPI_6_4_EINJ_NOOP 0x04 + +/// +/// EINJ Instruction Flags +/// +#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01 + +/// +/// EINJ Injection Instruction Entry +/// +typedef struct { + UINT8 InjectionAction; + UINT8 Instruction; + UINT8 Flags; + UINT8 Reserved0; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT64 Value; + UINT64 Mask; +} EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY; + +/// +/// EINJ Trigger Action Table +/// +typedef struct { + UINT32 HeaderSize; + UINT32 Revision; + UINT32 TableSize; + UINT32 EntryCount; +} EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE; + +/// +/// Platform Communications Channel Table (PCCT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; + +/// +/// PCCT Version (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02 + +/// +/// PCCT Global Flags +/// +#define EFI_ACPI_6_4_PCCT_FLAGS_PLATFORM_INTERRUPT BIT0 + +// +// PCCT Subspace type +// +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05 + +/// +/// PCC Subspace Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER; + +/// +/// Generic Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC; + +/// +/// Generic Communications Channel Shared Memory Region +/// + +typedef struct { + UINT8 Command; + UINT8 Reserved:7; + UINT8 NotifyOnCompletion:1; +} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND; + +typedef struct { + UINT8 CommandComplete:1; + UINT8 PlatformInterrupt:1; + UINT8 Error:1; + UINT8 PlatformNotification:1; + UINT8 Reserved:4; + UINT8 Reserved1; +} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS; + +typedef struct { + UINT32 Signature; + EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND Command; + EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status; +} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER; + +#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0 +#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1 + +/// +/// Type 1 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 2 HW-Reduced Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckWrite; +} EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS; + +/// +/// Type 3 Extended PCC Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 PlatformInterrupt; + UINT8 PlatformInterruptFlags; + UINT8 Reserved; + UINT64 BaseAddress; + UINT32 AddressLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT32 MinimumRequestTurnaroundTime; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister; + UINT64 PlatformInterruptAckPreserve; + UINT64 PlatformInterruptAckSet; + UINT8 Reserved1[8]; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister; + UINT64 CommandCompleteCheckMask; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister; + UINT64 CommandCompleteUpdatePreserve; + UINT64 CommandCompleteUpdateSet; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister; + UINT64 ErrorStatusMask; +} EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC; + +/// +/// Type 4 Extended PCC Subspace Structure +/// +typedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBSPACE_4_EXTENDED_PCC; + +#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0 + +typedef struct { + UINT32 Signature; + UINT32 Flags; + UINT32 Length; + UINT32 Command; +} EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER; + +/// +/// Type 5 HW Registers based Communications Subspace Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Version; + UINT64 BaseAddress; + UINT64 SharedMemoryRangeLength; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister; + UINT64 CommandCompleteCheckMask; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister; + UINT64 ErrorStatusMask; + UINT32 NominalLatency; + UINT32 MinimumRequestTurnaroundTime; +} EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS; + +/// +/// Reduced PCC Subspace Shared Memory Region +/// +typedef struct { + UINT32 Signature; +//UINT8 CommunicationSubspace[]; +} EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION; + +/// +/// Platform Debug Trigger Table (PDTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 TriggerCount; + UINT8 Reserved[3]; + UINT32 TriggerIdentifierArrayOffset; +} EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER; + +/// +/// PDTT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00 + +/// +/// PDTT Platform Communication Channel Identifier Structure +/// +typedef struct { + UINT16 SubChannelIdentifer:8; + UINT16 Runtime:1; + UINT16 WaitForCompletion:1; + UINT16 TriggerOrder:1; + UINT16 Reserved:5; +} EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER; + +/// +/// PCC Commands Codes used by Platform Debug Trigger Table +/// +#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00 +#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01 + +/// +/// PDTT Platform Communication Channel +/// +typedef EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_4_PDTT_PCC; + +/// +/// Processor Properties Topology Table (PPTT) +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER; + +/// +/// PPTT Revision (as defined in ACPI 6.4 spec.) +/// +#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03 + +/// +/// PPTT types +/// +#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00 +#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01 +#define EFI_ACPI_6_4_PPTT_TYPE_ID 0x02 + +/// +/// PPTT Structure Header +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; +} EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER; + +/// +/// For PPTT struct processor flags +/// +#define EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL 0x0 +#define EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL 0x1 +#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD 0x0 +#define EFI_ACPI_6_4_PPTT_PROCESSOR_IS_THREAD 0x1 +#define EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF 0x0 +#define EFI_ACPI_6_4_PPTT_NODE_IS_LEAF 0x1 +#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_NOT_IDENTICAL 0x0 +#define EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL 0x1 + +/// +/// Processor hierarchy node structure flags +/// +typedef struct { + UINT32 PhysicalPackage:1; + UINT32 AcpiProcessorIdValid:1; + UINT32 ProcessorIsAThread:1; + UINT32 NodeIsALeaf:1; + UINT32 IdenticalImplementation:1; + UINT32 Reserved:27; +} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS; + +/// +/// Processor hierarchy node structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags; + UINT32 Parent; + UINT32 AcpiProcessorId; + UINT32 NumberOfPrivateResources; +} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR; + +/// +/// For PPTT struct cache flags +/// +#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1 +#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1 + +/// +/// Cache Type Structure flags +/// +typedef struct { + UINT32 SizePropertyValid:1; + UINT32 NumberOfSetsValid:1; + UINT32 AssociativityValid:1; + UINT32 AllocationTypeValid:1; + UINT32 CacheTypeValid:1; + UINT32 WritePolicyValid:1; + UINT32 LineSizeValid:1; + UINT32 CacheIdValid:1; + UINT32 Reserved:24; +} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS; + +/// +/// For cache attributes +/// +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0 +#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1 + +/// +/// Cache Type Structure cache attributes +/// +typedef struct { + UINT8 AllocationType:2; + UINT8 CacheType:2; + UINT8 WritePolicy:1; + UINT8 Reserved:3; +} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES; + +/// +/// Cache Type Structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags; + UINT32 NextLevelOfCache; + UINT32 Size; + UINT32 NumberOfSets; + UINT8 Associativity; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes; + UINT16 LineSize; + UINT32 CacheId; +} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE; + +/// +/// ID structure +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[2]; + UINT32 VendorId; + UINT64 Level1Id; + UINT64 Level2Id; + UINT16 MajorRev; + UINT16 MinorRev; + UINT16 SpinRev; +} EFI_ACPI_6_4_PPTT_STRUCTURE_ID; + +/// +/// Platform Health Assessment Table (PHAT) Format +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +//UINT8 PlatformTelemetryRecords[]; +} EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE; + +#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01 + +/// +/// PHAT Record Format +/// +typedef struct { + UINT16 PlatformHealthAssessmentRecordType; + UINT16 RecordLength; + UINT8 Revision; +//UINT8 Data[]; +} EFI_ACPI_6_4_PHAT_RECORD; + +/// +/// PHAT Record Type Format +/// +#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_VERSION_DATA_RECORD 0x0000 +#define EFI_ACPI_6_4_PHAT_RECORD_TYPE_FIRMWARE_HEALTH_DATA_RECORD 0x0001 + +/// +/// PHAT Version Element +/// +typedef struct { + GUID ComponentId; + UINT64 VersionValue; + UINT32 ProducerId; +} EFI_ACPI_6_4_PHAT_VERSION_ELEMENT; + +/// +/// PHAT Firmware Version Data Record +/// +typedef struct { + UINT16 PlatformRecordType; + UINT16 RecordLength; + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 RecordCount; +//UINT8 PhatVersionElement[]; +} EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD; + +#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01 + +/// +/// Firmware Health Data Record Structure +/// +typedef struct { + UINT16 PlatformRecordType; + UINT16 RecordLength; + UINT8 Revision; + UINT16 Reserved; + UINT8 AmHealthy; + GUID DeviceSignature; + UINT32 DeviceSpecificDataOffset; +//UINT8 DevicePath[]; +//UINT8 DeviceSpecificData[]; +} EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE; + +#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01 + +/// +/// Firmware Health Data Record device health state +/// +#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00 +#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01 +#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02 +#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03 + +// +// Known table signatures +// + +/// +/// "RSD PTR " Root System Description Pointer +/// +#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') + +/// +/// "APIC" Multiple APIC Description Table +/// +#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') + +/// +/// "BERT" Boot Error Record Table +/// +#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_SIGNATURE SIGNATURE_32('B', 'E', 'R', 'T') + +/// +/// "BGRT" Boot Graphics Resource Table +/// +#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('B', 'G', 'R', 'T') + +/// +/// "CDIT" Component Distance Information Table +/// +#define EFI_ACPI_6_4_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('C', 'D', 'I', 'T') + +/// +/// "CPEP" Corrected Platform Error Polling Table +/// +#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE SIGNATURE_32('C', 'P', 'E', 'P') + +/// +/// "CRAT" Component Resource Attribute Table +/// +#define EFI_ACPI_6_4_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('C', 'R', 'A', 'T') + +/// +/// "DSDT" Differentiated System Description Table +/// +#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('D', 'S', 'D', 'T') + +/// +/// "ECDT" Embedded Controller Boot Resources Table +/// +#define EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE SIGNATURE_32('E', 'C', 'D', 'T') + +/// +/// "EINJ" Error Injection Table +/// +#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_SIGNATURE SIGNATURE_32('E', 'I', 'N', 'J') + +/// +/// "ERST" Error Record Serialization Table +/// +#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE SIGNATURE_32('E', 'R', 'S', 'T') + +/// +/// "FACP" Fixed ACPI Description Table +/// +#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'P') + +/// +/// "FACS" Firmware ACPI Control Structure +/// +#define EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE SIGNATURE_32('F', 'A', 'C', 'S') + +/// +/// "FPDT" Firmware Performance Data Table +/// +#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE SIGNATURE_32('F', 'P', 'D', 'T') + +/// +/// "GTDT" Generic Timer Description Table +/// +#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('G', 'T', 'D', 'T') + +/// +/// "HEST" Hardware Error Source Table +/// +#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('H', 'E', 'S', 'T') + +/// +/// "HMAT" Heterogeneous Memory Attribute Table +/// +#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T') + +/// +/// "MPST" Memory Power State Table +/// +#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'S', 'T') + +/// +/// "MSCT" Maximum System Characteristics Table +/// +#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'C', 'T') + +/// +/// "NFIT" NVDIMM Firmware Interface Table +/// +#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('N', 'F', 'I', 'T') + +/// +/// "PDTT" Platform Debug Trigger Table +/// +#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'D', 'T', 'T') + +/// +/// "PMTT" Platform Memory Topology Table +/// +#define EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE SIGNATURE_32('P', 'M', 'T', 'T') + +/// +/// "PPTT" Processor Properties Topology Table +/// +#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('P', 'P', 'T', 'T') + +/// +/// "PSDT" Persistent System Description Table +/// +#define EFI_ACPI_6_4_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('P', 'S', 'D', 'T') + +/// +/// "RASF" ACPI RAS Feature Table +/// +#define EFI_ACPI_6_4_ACPI_RAS_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', 'F') + +/// +/// "RSDT" Root System Description Table +/// +#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('R', 'S', 'D', 'T') + +/// +/// "SBST" Smart Battery Specification Table +/// +#define EFI_ACPI_6_4_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE SIGNATURE_32('S', 'B', 'S', 'T') + +/// +/// "SDEV" Secure DEVices Table +/// +#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'V') + +/// +/// "SLIT" System Locality Information Table +/// +#define EFI_ACPI_6_4_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'T') + +/// +/// "SRAT" System Resource Affinity Table +/// +#define EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE SIGNATURE_32('S', 'R', 'A', 'T') + +/// +/// "SSDT" Secondary System Description Table +/// +#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T') + +/// +/// "XSDT" Extended System Description Table +/// +#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('X', 'S', 'D', 'T') + +/// +/// "BOOT" MS Simple Boot Spec +/// +#define EFI_ACPI_6_4_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE SIGNATURE_32('B', 'O', 'O', 'T') + +/// +/// "CSRT" MS Core System Resource Table +/// +#define EFI_ACPI_6_4_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('C', 'S', 'R', 'T') + +/// +/// "DBG2" MS Debug Port 2 Spec +/// +#define EFI_ACPI_6_4_DEBUG_PORT_2_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', '2') + +/// +/// "DBGP" MS Debug Port Spec +/// +#define EFI_ACPI_6_4_DEBUG_PORT_TABLE_SIGNATURE SIGNATURE_32('D', 'B', 'G', 'P') + +/// +/// "DMAR" DMA Remapping Table +/// +#define EFI_ACPI_6_4_DMA_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('D', 'M', 'A', 'R') + +/// +/// "DRTM" Dynamic Root of Trust for Measurement Table +/// +#define EFI_ACPI_6_4_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE SIGNATURE_32('D', 'R', 'T', 'M') + +/// +/// "ETDT" Event Timer Description Table +/// +#define EFI_ACPI_6_4_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('E', 'T', 'D', 'T') + +/// +/// "HPET" IA-PC High Precision Event Timer Table +/// +#define EFI_ACPI_6_4_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE SIGNATURE_32('H', 'P', 'E', 'T') + +/// +/// "iBFT" iSCSI Boot Firmware Table +/// +#define EFI_ACPI_6_4_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T') + +/// +/// "IORT" I/O Remapping Table +/// +#define EFI_ACPI_6_4_IO_REMAPPING_TABLE_SIGNATURE SIGNATURE_32('I', 'O', 'R', 'T') + +/// +/// "IVRS" I/O Virtualization Reporting Structure +/// +#define EFI_ACPI_6_4_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE SIGNATURE_32('I', 'V', 'R', 'S') + +/// +/// "LPIT" Low Power Idle Table +/// +#define EFI_ACPI_6_4_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE SIGNATURE_32('L', 'P', 'I', 'T') + +/// +/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +/// +#define EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G') + +/// +/// "MCHI" Management Controller Host Interface Table +/// +#define EFI_ACPI_6_4_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'H', 'I') + +/// +/// "MSDM" MS Data Management Table +/// +#define EFI_ACPI_6_4_DATA_MANAGEMENT_TABLE_SIGNATURE SIGNATURE_32('M', 'S', 'D', 'M') + +/// +/// "PCCT" Platform Communications Channel Table +/// +#define EFI_ACPI_6_4_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'C', 'T') + +/// +/// "PHAT" Platform Health Assessment Table +/// +#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T') + +/// +/// "SDEI" Software Delegated Exceptions Interface Table +/// +#define EFI_ACPI_6_4_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'D', 'E', 'I') + +/// +/// "SLIC" MS Software Licensing Table Specification +/// +#define EFI_ACPI_6_4_SOFTWARE_LICENSING_TABLE_SIGNATURE SIGNATURE_32('S', 'L', 'I', 'C') + +/// +/// "SPCR" Serial Port Concole Redirection Table +/// +#define EFI_ACPI_6_4_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'C', 'R') + +/// +/// "SPMI" Server Platform Management Interface Table +/// +#define EFI_ACPI_6_4_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE SIGNATURE_32('S', 'P', 'M', 'I') + +/// +/// "STAO" _STA Override Table +/// +#define EFI_ACPI_6_4_STA_OVERRIDE_TABLE_SIGNATURE SIGNATURE_32('S', 'T', 'A', 'O') + +/// +/// "TCPA" Trusted Computing Platform Alliance Capabilities Table +/// +#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE SIGNATURE_32('T', 'C', 'P', 'A') + +/// +/// "TPM2" Trusted Computing Platform 1 Table +/// +#define EFI_ACPI_6_4_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE SIGNATURE_32('T', 'P', 'M', '2') + +/// +/// "UEFI" UEFI ACPI Data Table +/// +#define EFI_ACPI_6_4_UEFI_ACPI_DATA_TABLE_SIGNATURE SIGNATURE_32('U', 'E', 'F', 'I') + +/// +/// "WAET" Windows ACPI Emulated Devices Table +/// +#define EFI_ACPI_6_4_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T') + +/// +/// "WDAT" Watchdog Action Table +/// +#define EFI_ACPI_6_4_WATCHDOG_ACTION_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'A', 'T') + +/// +/// "WDRT" Watchdog Resource Table +/// +#define EFI_ACPI_6_4_WATCHDOG_RESOURCE_TABLE_SIGNATURE SIGNATURE_32('W', 'D', 'R', 'T') + +/// +/// "WPBT" MS Platform Binary Table +/// +#define EFI_ACPI_6_4_PLATFORM_BINARY_TABLE_SIGNATURE SIGNATURE_32('W', 'P', 'B', 'T') + +/// +/// "WSMT" Windows SMM Security Mitigation Table +/// +#define EFI_ACPI_6_4_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T') + +/// +/// "XENV" Xen Project Table +/// +#define EFI_ACPI_6_4_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V') + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AcpiAml.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AcpiAml.h new file mode 100644 index 0000000000..7aae14b3f6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AcpiAml.h @@ -0,0 +1,184 @@ +/** @file + This file contains AML code definition in the latest ACPI spec. + + Copyright (c) 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ACPI_AML_H_ +#define _ACPI_AML_H_ + +// +// ACPI AML definition +// + +// +// Primary OpCode +// +#define AML_ZERO_OP 0x00 +#define AML_ONE_OP 0x01 +#define AML_ALIAS_OP 0x06 +#define AML_NAME_OP 0x08 +#define AML_BYTE_PREFIX 0x0a +#define AML_WORD_PREFIX 0x0b +#define AML_DWORD_PREFIX 0x0c +#define AML_STRING_PREFIX 0x0d +#define AML_QWORD_PREFIX 0x0e +#define AML_SCOPE_OP 0x10 +#define AML_BUFFER_OP 0x11 +#define AML_PACKAGE_OP 0x12 +#define AML_VAR_PACKAGE_OP 0x13 +#define AML_METHOD_OP 0x14 +#define AML_EXTERNAL_OP 0x15 +#define AML_DUAL_NAME_PREFIX 0x2e +#define AML_MULTI_NAME_PREFIX 0x2f +#define AML_NAME_CHAR_A 0x41 +#define AML_NAME_CHAR_B 0x42 +#define AML_NAME_CHAR_C 0x43 +#define AML_NAME_CHAR_D 0x44 +#define AML_NAME_CHAR_E 0x45 +#define AML_NAME_CHAR_F 0x46 +#define AML_NAME_CHAR_G 0x47 +#define AML_NAME_CHAR_H 0x48 +#define AML_NAME_CHAR_I 0x49 +#define AML_NAME_CHAR_J 0x4a +#define AML_NAME_CHAR_K 0x4b +#define AML_NAME_CHAR_L 0x4c +#define AML_NAME_CHAR_M 0x4d +#define AML_NAME_CHAR_N 0x4e +#define AML_NAME_CHAR_O 0x4f +#define AML_NAME_CHAR_P 0x50 +#define AML_NAME_CHAR_Q 0x51 +#define AML_NAME_CHAR_R 0x52 +#define AML_NAME_CHAR_S 0x53 +#define AML_NAME_CHAR_T 0x54 +#define AML_NAME_CHAR_U 0x55 +#define AML_NAME_CHAR_V 0x56 +#define AML_NAME_CHAR_W 0x57 +#define AML_NAME_CHAR_X 0x58 +#define AML_NAME_CHAR_Y 0x59 +#define AML_NAME_CHAR_Z 0x5a +#define AML_ROOT_CHAR 0x5c +#define AML_PARENT_PREFIX_CHAR 0x5e +#define AML_NAME_CHAR__ 0x5f +#define AML_LOCAL0 0x60 +#define AML_LOCAL1 0x61 +#define AML_LOCAL2 0x62 +#define AML_LOCAL3 0x63 +#define AML_LOCAL4 0x64 +#define AML_LOCAL5 0x65 +#define AML_LOCAL6 0x66 +#define AML_LOCAL7 0x67 +#define AML_ARG0 0x68 +#define AML_ARG1 0x69 +#define AML_ARG2 0x6a +#define AML_ARG3 0x6b +#define AML_ARG4 0x6c +#define AML_ARG5 0x6d +#define AML_ARG6 0x6e +#define AML_STORE_OP 0x70 +#define AML_REF_OF_OP 0x71 +#define AML_ADD_OP 0x72 +#define AML_CONCAT_OP 0x73 +#define AML_SUBTRACT_OP 0x74 +#define AML_INCREMENT_OP 0x75 +#define AML_DECREMENT_OP 0x76 +#define AML_MULTIPLY_OP 0x77 +#define AML_DIVIDE_OP 0x78 +#define AML_SHIFT_LEFT_OP 0x79 +#define AML_SHIFT_RIGHT_OP 0x7a +#define AML_AND_OP 0x7b +#define AML_NAND_OP 0x7c +#define AML_OR_OP 0x7d +#define AML_NOR_OP 0x7e +#define AML_XOR_OP 0x7f +#define AML_NOT_OP 0x80 +#define AML_FIND_SET_LEFT_BIT_OP 0x81 +#define AML_FIND_SET_RIGHT_BIT_OP 0x82 +#define AML_DEREF_OF_OP 0x83 +#define AML_CONCAT_RES_OP 0x84 +#define AML_MOD_OP 0x85 +#define AML_NOTIFY_OP 0x86 +#define AML_SIZE_OF_OP 0x87 +#define AML_INDEX_OP 0x88 +#define AML_MATCH_OP 0x89 +#define AML_CREATE_DWORD_FIELD_OP 0x8a +#define AML_CREATE_WORD_FIELD_OP 0x8b +#define AML_CREATE_BYTE_FIELD_OP 0x8c +#define AML_CREATE_BIT_FIELD_OP 0x8d +#define AML_OBJECT_TYPE_OP 0x8e +#define AML_CREATE_QWORD_FIELD_OP 0x8f +#define AML_LAND_OP 0x90 +#define AML_LOR_OP 0x91 +#define AML_LNOT_OP 0x92 +#define AML_LEQUAL_OP 0x93 +#define AML_LGREATER_OP 0x94 +#define AML_LLESS_OP 0x95 +#define AML_TO_BUFFER_OP 0x96 +#define AML_TO_DEC_STRING_OP 0x97 +#define AML_TO_HEX_STRING_OP 0x98 +#define AML_TO_INTEGER_OP 0x99 +#define AML_TO_STRING_OP 0x9c +#define AML_COPY_OBJECT_OP 0x9d +#define AML_MID_OP 0x9e +#define AML_CONTINUE_OP 0x9f +#define AML_IF_OP 0xa0 +#define AML_ELSE_OP 0xa1 +#define AML_WHILE_OP 0xa2 +#define AML_NOOP_OP 0xa3 +#define AML_RETURN_OP 0xa4 +#define AML_BREAK_OP 0xa5 +#define AML_BREAK_POINT_OP 0xcc +#define AML_ONES_OP 0xff + +// +// Extended OpCode +// +#define AML_EXT_OP 0x5b + +#define AML_EXT_MUTEX_OP 0x01 +#define AML_EXT_EVENT_OP 0x02 +#define AML_EXT_COND_REF_OF_OP 0x12 +#define AML_EXT_CREATE_FIELD_OP 0x13 +#define AML_EXT_LOAD_TABLE_OP 0x1f +#define AML_EXT_LOAD_OP 0x20 +#define AML_EXT_STALL_OP 0x21 +#define AML_EXT_SLEEP_OP 0x22 +#define AML_EXT_ACQUIRE_OP 0x23 +#define AML_EXT_SIGNAL_OP 0x24 +#define AML_EXT_WAIT_OP 0x25 +#define AML_EXT_RESET_OP 0x26 +#define AML_EXT_RELEASE_OP 0x27 +#define AML_EXT_FROM_BCD_OP 0x28 +#define AML_EXT_TO_BCD_OP 0x29 +#define AML_EXT_UNLOAD_OP 0x2a +#define AML_EXT_REVISION_OP 0x30 +#define AML_EXT_DEBUG_OP 0x31 +#define AML_EXT_FATAL_OP 0x32 +#define AML_EXT_TIMER_OP 0x33 +#define AML_EXT_REGION_OP 0x80 +#define AML_EXT_FIELD_OP 0x81 +#define AML_EXT_DEVICE_OP 0x82 +#define AML_EXT_PROCESSOR_OP 0x83 +#define AML_EXT_POWER_RES_OP 0x84 +#define AML_EXT_THERMAL_ZONE_OP 0x85 +#define AML_EXT_INDEX_FIELD_OP 0x86 +#define AML_EXT_BANK_FIELD_OP 0x87 +#define AML_EXT_DATA_REGION_OP 0x88 + +// +// FieldElement OpCode +// +#define AML_FIELD_RESERVED_OP 0x00 +#define AML_FIELD_ACCESS_OP 0x01 +#define AML_FIELD_CONNECTION_OP 0x02 +#define AML_FIELD_EXT_ACCESS_OP 0x03 + +// +// AML Name segment definitions +// +#define AML_NAME_SEG_SIZE 4 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h new file mode 100644 index 0000000000..8bb3ca6650 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h @@ -0,0 +1,140 @@ +/** @file + ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ALERT_STANDARD_FORMAT_TABLE_H_ +#define _ALERT_STANDARD_FORMAT_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack (1) + +/// +/// Information Record header that appears at the beginning of each record +/// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 RecordLength; +} EFI_ACPI_ASF_RECORD_HEADER; + +/// +/// This structure contains information that identifies the system's type +/// and configuration +/// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 MinWatchDogResetValue; + UINT8 MinPollingInterval; + UINT16 SystemID; + UINT32 IANAManufactureID; + UINT8 FeatureFlags; + UINT8 Reserved[3]; +} EFI_ACPI_ASF_INFO; + +/// +/// ASF Alert Data +/// +typedef struct { + UINT8 DeviceAddress; + UINT8 Command; + UINT8 DataMask; + UINT8 CompareValue; + UINT8 EventSenseType; + UINT8 EventType; + UINT8 EventOffset; + UINT8 EventSourceType; + UINT8 EventSeverity; + UINT8 SensorNumber; + UINT8 Entity; + UINT8 EntityInstance; +} EFI_ACPI_ASF_ALERTDATA; + +/// +/// Alert sensors definition +/// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 AssertionEventBitMask; + UINT8 DeassertionEventBitMask; + UINT8 NumberOfAlerts; + UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C + /// + /// EFI_ACPI_ASF_ALERTDATA DeviceArray[ANYSIZE_ARRAY]; + /// +} EFI_ACPI_ASF_ALRT; + +/// +/// Alert Control Data +/// +typedef struct { + UINT8 Function; + UINT8 DeviceAddress; + UINT8 Command; + UINT8 DataValue; +} EFI_ACPI_ASF_CONTROLDATA; + +/// +/// Alert Remote Control System Actions +/// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 NumberOfControls; + UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4 + UINT16 RctlReserved; + /// + /// EFI_ACPI_ASF_CONTROLDATA; DeviceArray[ANYSIZE_ARRAY]; + /// +} EFI_ACPI_ASF_RCTL; + + +/// +/// Remote Control Capabilities +/// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 RemoteControlCapabilities[7]; + UINT8 RMCPCompletionCode; + UINT32 RMCPIANA; + UINT8 RMCPSpecialCommand; + UINT8 RMCPSpecialCommandParameter[2]; + UINT8 RMCPBootOptions[2]; + UINT8 RMCPOEMParameters[2]; +} EFI_ACPI_ASF_RMCP; + +/// +/// SMBus Devices with fixed addresses +/// +typedef struct { + EFI_ACPI_ASF_RECORD_HEADER RecordHeader; + UINT8 SEEPROMAddress; + UINT8 NumberOfDevices; + /// + /// UINT8 FixedSmbusAddresses[ANYSIZE_ARRAY]; + /// +} EFI_ACPI_ASF_ADDR; + +/// +/// ASF! Description Table Header +/// +typedef EFI_ACPI_DESCRIPTION_HEADER EFI_ACPI_ASF_DESCRIPTION_HEADER; + +/// +/// The revision stored in ASF! DESCRIPTION TABLE as BCD value +/// +#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20 + +/// +/// "ASF!" ASF Description Table Signature +/// +#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32 ('A', 'S', 'F', '!') + +#pragma pack () + +#endif // _ALERT_STANDARD_FORMAT_TABLE_H diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h new file mode 100644 index 0000000000..cae9644b26 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h @@ -0,0 +1,357 @@ +/** @file + Arm Error Source Table as described in the + 'ACPI for the Armv8 RAS Extensions 1.1' Specification. + + Copyright (c) 2020 Arm Limited. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, + dated 28 September 2020. + (https://developer.arm.com/documentation/den0085/0101/) + + @par Glossary + - Ref : Reference + - Id : Identifier +**/ + +#ifndef ARM_ERROR_SOURCE_TABLE_H_ +#define ARM_ERROR_SOURCE_TABLE_H_ + +/// +/// "AEST" Arm Error Source Table +/// +#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T') + +#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1 + +#pragma pack(1) + +/// +/// Arm Error Source Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_ARM_ERROR_SOURCE_TABLE; + +/// +/// AEST Node structure. +/// +typedef struct { + /// Node type: + /// 0x00 - Processor error node + /// 0x01 - Memory error node + /// 0x02 - SMMU error node + /// 0x03 - Vendor-defined error node + /// 0x04 - GIC error node + UINT8 Type; + + /// Length of structure in bytes. + UINT16 Length; + + /// Reserved - Must be zero. + UINT8 Reserved; + + /// Offset from the start of the node to node-specific data. + UINT32 DataOffset; + + /// Offset from the start of the node to the node interface structure. + UINT32 InterfaceOffset; + + /// Offset from the start of the node to node interrupt array. + UINT32 InterruptArrayOffset; + + /// Number of entries in the interrupt array. + UINT32 InterruptArrayCount; + + // Generic node data + + /// The timestamp frequency of the counter in Hz. + UINT64 TimestampRate; + + /// Reserved - Must be zero. + UINT64 Reserved1; + + /// The rate in Hz at which the Error Generation Counter decrements. + UINT64 ErrorInjectionCountdownRate; +} EFI_ACPI_AEST_NODE_STRUCT; + +// AEST Node type definitions +#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0 +#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1 +#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2 +#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3 +#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4 + +/// +/// AEST Node Interface structure. +/// +typedef struct { + /// Interface type: + /// 0x0 - System register (SR) + /// 0x1 - Memory mapped (MMIO) + UINT8 Type; + + /// Reserved - Must be zero. + UINT8 Reserved[3]; + + /// AEST node interface flags. + UINT32 Flags; + + /// Base address of error group that contains the error node. + UINT64 BaseAddress; + + /// Zero-based index of the first standard error record that + /// belongs to this node. + UINT32 StartErrorRecordIndex; + + /// Number of error records in this node including both + /// implemented and unimplemented records. + UINT32 NumberErrorRecords; + + /// A bitmap indicating the error records within this + /// node that are implemented in the current system. + UINT64 ErrorRecordImplemented; + + /// A bitmap indicating the error records within this node that + /// support error status reporting through the ERRGSR register. + UINT64 ErrorRecordStatusReportingSupported; + + /// A bitmap indicating the addressing mode used by each error + /// record within this node to populate the ERR_ADDR register. + UINT64 AddressingMode; +} EFI_ACPI_AEST_INTERFACE_STRUCT; + +// AEST Interface node type definitions. +#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0 +#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1 + +// AEST node interface flag definitions. +#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1 + +/// +/// AEST Node Interrupt structure. +/// +typedef struct { + /// Interrupt type: + /// 0x0 - Fault Handling Interrupt + /// 0x1 - Error Recovery Interrupt + UINT8 InterruptType; + + /// Reserved - Must be zero. + UINT8 Reserved[2]; + + /// Interrupt flags + /// Bits [31:1]: Must be zero. + /// Bit 0: + /// 0b - Interrupt is edge-triggered + /// 1b - Interrupt is level-triggered + UINT8 InterruptFlags; + + /// GSIV of interrupt, if interrupt is an SPI or a PPI. + UINT32 InterruptGsiv; + + /// If MSI is supported, then this field must be set to the + /// Identifier field of the IORT ITS Group node. + UINT8 ItsGroupRefId; + + /// Reserved - must be zero. + UINT8 Reserved1[3]; +} EFI_ACPI_AEST_INTERRUPT_STRUCT; + +// AEST Interrupt node - interrupt type defintions. +#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0 +#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1 + +// AEST Interrupt node - interrupt flag defintions. +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0 +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0 + +/// +/// Cache Processor Resource structure. +/// +typedef struct { + /// Reference to the cache structure in the PPTT table. + UINT32 CacheRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT; + +/// +/// TLB Processor Resource structure. +/// +typedef struct { + /// TLB level from perspective of current processor. + UINT32 TlbRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT; + +/// +/// Processor Generic Resource structure. +/// +typedef struct { + /// Vendor-defined supplementary data. + UINT32 Data; +} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT; + +/// +/// AEST Processor Resource union. +/// +typedef union { + /// Processor Cache resource. + EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache; + + /// Processor TLB resource. + EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb; + + /// Processor Generic resource. + EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic; +} EFI_ACPI_AEST_PROCESSOR_RESOURCE; + +/// +/// AEST Processor structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Processor ID of node. + UINT32 AcpiProcessorId; + + /// Resource type of the processor node. + /// 0x0 - Cache + /// 0x1 - TLB + /// 0x2 - Generic + UINT8 ResourceType; + + /// Reserved - must be zero. + UINT8 Reserved; + + /// Processor structure flags. + UINT8 Flags; + + /// Processor structure revision. + UINT8 Revision; + + /// Processor affinity descriptor for the resource that this + /// error node pertains to. + UINT64 ProcessorAffinityLevelIndicator; + + /// Processor resource + EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_PROCESSOR_STRUCT; + +// AEST Processor resource type definitions. +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2 + +// AEST Processor flag definitions. +#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0 +#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1 + +/// +/// Memory Controller structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// SRAT proximity domain. + UINT32 ProximityDomain; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT; + +/// +/// SMMU structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Reference to the IORT table node that describes this SMMU. + UINT32 SmmuRefId; + + /// Reference to the IORT table node that is associated with the + /// sub-component within this SMMU. + UINT32 SubComponentRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_SMMU_STRUCT; + +/// +/// Vendor-Defined structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// ACPI HID of the component. + UINT32 HardwareId; + + /// The ACPI Unique identifier of the component. + UINT32 UniqueId; + + /// Vendor-specific data, for example to identify this error source. + UINT8 VendorData[16]; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT; + +/// +/// GIC structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Type of GIC interface that is associated with this error node. + /// 0x0 - GIC CPU (GICC) + /// 0x1 - GIC Distributor (GICD) + /// 0x2 - GIC Resistributor (GICR) + /// 0x3 - GIC ITS (GITS) + UINT32 InterfaceType; + + /// Identifier for the interface instance. + UINT32 GicInterfaceRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_GIC_STRUCT; + +// AEST GIC interface type definitions. +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3 + +#pragma pack() + +#endif // ARM_ERROR_SOURCE_TABLE_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Atapi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Atapi.h new file mode 100644 index 0000000000..a886f59e3c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Atapi.h @@ -0,0 +1,851 @@ +/** @file + This file contains just some basic definitions that are needed by drivers + that dealing with ATA/ATAPI interface. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ATAPI_H_ +#define _ATAPI_H_ + +#pragma pack(1) + +/// +/// ATA5_IDENTIFY_DATA is defined in ATA-5. +/// (This structure is provided mainly for backward-compatibility support. +/// Old drivers may reference fields that are marked "obsolete" in +/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.) +/// +typedef struct { + UINT16 config; ///< General Configuration. + UINT16 cylinders; ///< Number of Cylinders. + UINT16 reserved_2; + UINT16 heads; ///< Number of logical heads. + UINT16 vendor_data1; + UINT16 vendor_data2; + UINT16 sectors_per_track; + UINT16 vendor_specific_7_9[3]; + CHAR8 SerialNo[20]; ///< ASCII + UINT16 vendor_specific_20_21[2]; + UINT16 ecc_bytes_available; + CHAR8 FirmwareVer[8]; ///< ASCII + CHAR8 ModelName[40]; ///< ASCII + UINT16 multi_sector_cmd_max_sct_cnt; + UINT16 reserved_48; + UINT16 capabilities; + UINT16 reserved_50; + UINT16 pio_cycle_timing; + UINT16 reserved_52; + UINT16 field_validity; + UINT16 current_cylinders; + UINT16 current_heads; + UINT16 current_sectors; + UINT16 CurrentCapacityLsb; + UINT16 CurrentCapacityMsb; + UINT16 reserved_59; + UINT16 user_addressable_sectors_lo; + UINT16 user_addressable_sectors_hi; + UINT16 reserved_62; + UINT16 multi_word_dma_mode; + UINT16 advanced_pio_modes; + UINT16 min_multi_word_dma_cycle_time; + UINT16 rec_multi_word_dma_cycle_time; + UINT16 min_pio_cycle_time_without_flow_control; + UINT16 min_pio_cycle_time_with_flow_control; + UINT16 reserved_69_79[11]; + UINT16 major_version_no; + UINT16 minor_version_no; + UINT16 command_set_supported_82; ///< word 82 + UINT16 command_set_supported_83; ///< word 83 + UINT16 command_set_feature_extn; ///< word 84 + UINT16 command_set_feature_enb_85; ///< word 85 + UINT16 command_set_feature_enb_86; ///< word 86 + UINT16 command_set_feature_default; ///< word 87 + UINT16 ultra_dma_mode; ///< word 88 + UINT16 reserved_89_127[39]; + UINT16 security_status; + UINT16 vendor_data_129_159[31]; + UINT16 reserved_160_255[96]; +} ATA5_IDENTIFY_DATA; + +/// +/// ATA_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec +/// to define the data returned by an ATA device upon successful +/// completion of the ATA IDENTIFY_DEVICE command. +/// +typedef struct { + UINT16 config; ///< General Configuration. + UINT16 obsolete_1; + UINT16 specific_config; ///< Specific Configuration. + UINT16 obsolete_3; + UINT16 retired_4_5[2]; + UINT16 obsolete_6; + UINT16 cfa_reserved_7_8[2]; + UINT16 retired_9; + CHAR8 SerialNo[20]; ///< word 10~19 + UINT16 retired_20_21[2]; + UINT16 obsolete_22; + CHAR8 FirmwareVer[8]; ///< word 23~26 + CHAR8 ModelName[40]; ///< word 27~46 + UINT16 multi_sector_cmd_max_sct_cnt; + UINT16 trusted_computing_support; + UINT16 capabilities_49; + UINT16 capabilities_50; + UINT16 obsolete_51_52[2]; + UINT16 field_validity; + UINT16 obsolete_54_58[5]; + UINT16 multi_sector_setting; + UINT16 user_addressable_sectors_lo; + UINT16 user_addressable_sectors_hi; + UINT16 obsolete_62; + UINT16 multi_word_dma_mode; + UINT16 advanced_pio_modes; + UINT16 min_multi_word_dma_cycle_time; + UINT16 rec_multi_word_dma_cycle_time; + UINT16 min_pio_cycle_time_without_flow_control; + UINT16 min_pio_cycle_time_with_flow_control; + UINT16 additional_supported; ///< word 69 + UINT16 reserved_70; + UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd. + UINT16 queue_depth; + UINT16 serial_ata_capabilities; + UINT16 reserved_77; ///< Reserved for Serial ATA + UINT16 serial_ata_features_supported; + UINT16 serial_ata_features_enabled; + UINT16 major_version_no; + UINT16 minor_version_no; + UINT16 command_set_supported_82; ///< word 82 + UINT16 command_set_supported_83; ///< word 83 + UINT16 command_set_feature_extn; ///< word 84 + UINT16 command_set_feature_enb_85; ///< word 85 + UINT16 command_set_feature_enb_86; ///< word 86 + UINT16 command_set_feature_default; ///< word 87 + UINT16 ultra_dma_mode; ///< word 88 + UINT16 time_for_security_erase_unit; + UINT16 time_for_enhanced_security_erase_unit; + UINT16 advanced_power_management_level; + UINT16 master_password_identifier; + UINT16 hardware_configuration_test_result; + UINT16 obsolete_94; + UINT16 stream_minimum_request_size; + UINT16 streaming_transfer_time_for_dma; + UINT16 streaming_access_latency_for_dma_and_pio; + UINT16 streaming_performance_granularity[2]; ///< word 98~99 + UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103 + UINT16 streaming_transfer_time_for_pio; + UINT16 max_no_of_512byte_blocks_per_data_set_cmd; + UINT16 phy_logic_sector_support; ///< word 106 + UINT16 interseek_delay_for_iso7779; + UINT16 world_wide_name[4]; ///< word 108~111 + UINT16 reserved_for_128bit_wwn_112_115[4]; + UINT16 reserved_for_technical_report; + UINT16 logic_sector_size_lo; ///< word 117 + UINT16 logic_sector_size_hi; ///< word 118 + UINT16 features_and_command_sets_supported_ext; ///< word 119 + UINT16 features_and_command_sets_enabled_ext; ///< word 120 + UINT16 reserved_121_126[6]; + UINT16 obsolete_127; + UINT16 security_status; ///< word 128 + UINT16 vendor_specific_129_159[31]; + UINT16 cfa_power_mode; ///< word 160 + UINT16 reserved_for_compactflash_161_167[7]; + UINT16 device_nominal_form_factor; + UINT16 is_data_set_cmd_supported; + CHAR8 additional_product_identifier[8]; + UINT16 reserved_174_175[2]; + CHAR8 media_serial_number[60]; ///< word 176~205 + UINT16 sct_command_transport; ///< word 206 + UINT16 reserved_207_208[2]; + UINT16 alignment_logic_in_phy_blocks; ///< word 209 + UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211 + UINT16 verify_sector_count_mode2[2]; + UINT16 nv_cache_capabilities; + UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215 + UINT16 nv_cache_size_in_logical_block_msw; ///< word 216 + UINT16 nominal_media_rotation_rate; + UINT16 reserved_218; + UINT16 nv_cache_options; ///< word 219 + UINT16 write_read_verify_mode; ///< word 220 + UINT16 reserved_221; + UINT16 transport_major_revision_number; + UINT16 transport_minor_revision_number; + UINT16 reserved_224_229[6]; + UINT64 extended_no_of_addressable_sectors; + UINT16 min_number_per_download_microcode_mode3; ///< word 234 + UINT16 max_number_per_download_microcode_mode3; ///< word 235 + UINT16 reserved_236_254[19]; + UINT16 integrity_word; +} ATA_IDENTIFY_DATA; + +/// +/// ATAPI_IDENTIFY_DATA strictly complies with ATA/ATAPI-8 Spec +/// to define the data returned by an ATAPI device upon successful +/// completion of the ATA IDENTIFY_PACKET_DEVICE command. +/// +typedef struct { + UINT16 config; ///< General Configuration. + UINT16 reserved_1; + UINT16 specific_config; ///< Specific Configuration. + UINT16 reserved_3_9[7]; + CHAR8 SerialNo[20]; ///< word 10~19 + UINT16 reserved_20_22[3]; + CHAR8 FirmwareVer[8]; ///< word 23~26 + CHAR8 ModelName[40]; ///< word 27~46 + UINT16 reserved_47_48[2]; + UINT16 capabilities_49; + UINT16 capabilities_50; + UINT16 obsolete_51; + UINT16 reserved_52; + UINT16 field_validity; ///< word 53 + UINT16 reserved_54_61[8]; + UINT16 dma_dir; + UINT16 multi_word_dma_mode; ///< word 63 + UINT16 advanced_pio_modes; ///< word 64 + UINT16 min_multi_word_dma_cycle_time; + UINT16 rec_multi_word_dma_cycle_time; + UINT16 min_pio_cycle_time_without_flow_control; + UINT16 min_pio_cycle_time_with_flow_control; + UINT16 reserved_69_70[2]; + UINT16 obsolete_71_72[2]; + UINT16 reserved_73_74[2]; + UINT16 obsolete_75; + UINT16 serial_ata_capabilities; + UINT16 reserved_77; ///< Reserved for Serial ATA + UINT16 serial_ata_features_supported; + UINT16 serial_ata_features_enabled; + UINT16 major_version_no; ///< word 80 + UINT16 minor_version_no; ///< word 81 + UINT16 cmd_set_support_82; + UINT16 cmd_set_support_83; + UINT16 cmd_feature_support; + UINT16 cmd_feature_enable_85; + UINT16 cmd_feature_enable_86; + UINT16 cmd_feature_default; + UINT16 ultra_dma_select; + UINT16 time_required_for_sec_erase; ///< word 89 + UINT16 time_required_for_enhanced_sec_erase; ///< word 90 + UINT16 advanced_power_management_level; + UINT16 master_pwd_revison_code; + UINT16 hardware_reset_result; ///< word 93 + UINT16 obsolete_94; + UINT16 reserved_95_107[13]; + UINT16 world_wide_name[4]; ///< word 108~111 + UINT16 reserved_for_128bit_wwn_112_115[4]; + UINT16 reserved_116_118[3]; + UINT16 command_and_feature_sets_supported; ///< word 119 + UINT16 command_and_feature_sets_supported_enabled; + UINT16 reserved_121_124[4]; + UINT16 atapi_byte_count_0_behavior; ///< word 125 + UINT16 obsolete_126_127[2]; + UINT16 security_status; + UINT16 reserved_129_159[31]; + UINT16 cfa_reserved_160_175[16]; + UINT16 reserved_176_221[46]; + UINT16 transport_major_version; + UINT16 transport_minor_version; + UINT16 reserved_224_254[31]; + UINT16 integrity_word; +} ATAPI_IDENTIFY_DATA; + + +/// +/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 peripheral_type; + UINT8 RMB; + UINT8 version; + UINT8 response_data_format; + UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one. + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 reserved_7; + UINT8 vendor_info[8]; + UINT8 product_id[16]; + UINT8 product_revision_level[4]; + UINT8 vendor_specific_36_55[55 - 36 + 1]; + UINT8 reserved_56_95[95 - 56 + 1]; + /// + /// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254 + /// since allocation_length is one byte in ATAPI_INQUIRY_CMD. + /// + UINT8 vendor_specific_96_253[253 - 96 + 1]; +} ATAPI_INQUIRY_DATA; + +/// +/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 error_code : 7; + UINT8 valid : 1; + UINT8 reserved_1; + UINT8 sense_key : 4; + UINT8 reserved_2 : 1; + UINT8 Vendor_specifc_1 : 3; + UINT8 vendor_specific_3; + UINT8 vendor_specific_4; + UINT8 vendor_specific_5; + UINT8 vendor_specific_6; + UINT8 addnl_sense_length; ///< n - 7 + UINT8 vendor_specific_8; + UINT8 vendor_specific_9; + UINT8 vendor_specific_10; + UINT8 vendor_specific_11; + UINT8 addnl_sense_code; ///< mandatory + UINT8 addnl_sense_code_qualifier; ///< mandatory + UINT8 field_replaceable_unit_code; ///< optional + UINT8 sense_key_specific_15 : 7; + UINT8 SKSV : 1; + UINT8 sense_key_specific_16; + UINT8 sense_key_specific_17; +} ATAPI_REQUEST_SENSE_DATA; + +/// +/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 LastLba3; + UINT8 LastLba2; + UINT8 LastLba1; + UINT8 LastLba0; + UINT8 BlockSize3; + UINT8 BlockSize2; + UINT8 BlockSize1; + UINT8 BlockSize0; +} ATAPI_READ_CAPACITY_DATA; + +/// +/// Capacity List Header + Current/Maximum Capacity Descriptor, +/// defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 reserved_0; + UINT8 reserved_1; + UINT8 reserved_2; + UINT8 Capacity_Length; + UINT8 LastLba3; + UINT8 LastLba2; + UINT8 LastLba1; + UINT8 LastLba0; + UINT8 DesCode : 2; + UINT8 reserved_9 : 6; + UINT8 BlockSize2; + UINT8 BlockSize1; + UINT8 BlockSize0; +} ATAPI_READ_FORMAT_CAPACITY_DATA; + +/// +/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1; + UINT8 reserved_2; + UINT8 reserved_3; + UINT8 reserved_4; + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 reserved_7; + UINT8 reserved_8; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_TEST_UNIT_READY_CMD; + +/// +/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1 : 5; + UINT8 lun : 3; + UINT8 page_code; ///< defined in SFF8090i, V6 + UINT8 reserved_3; + UINT8 allocation_length; + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 reserved_7; + UINT8 reserved_8; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_INQUIRY_CMD; + +/// +/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1 : 5; + UINT8 lun : 3; + UINT8 reserved_2; + UINT8 reserved_3; + UINT8 allocation_length; + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 reserved_7; + UINT8 reserved_8; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_REQUEST_SENSE_CMD; + +/// +/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1 : 5; + UINT8 lun : 3; + UINT8 Lba0; + UINT8 Lba1; + UINT8 Lba2; + UINT8 Lba3; + UINT8 reserved_6; + UINT8 TranLen0; + UINT8 TranLen1; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_READ10_CMD; + +/// +/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1 : 5; + UINT8 lun : 3; + UINT8 reserved_2; + UINT8 reserved_3; + UINT8 reserved_4; + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 allocation_length_hi; + UINT8 allocation_length_lo; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_READ_FORMAT_CAP_CMD; + +/// +/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification). +/// +typedef struct { + UINT8 opcode; + UINT8 reserved_1 : 5; + UINT8 lun : 3; + UINT8 page_code : 6; + UINT8 page_control : 2; + UINT8 reserved_3; + UINT8 reserved_4; + UINT8 reserved_5; + UINT8 reserved_6; + UINT8 parameter_list_length_hi; + UINT8 parameter_list_length_lo; + UINT8 reserved_9; + UINT8 reserved_10; + UINT8 reserved_11; +} ATAPI_MODE_SENSE_CMD; + +/// +/// ATAPI_PACKET_COMMAND is not defined in the ATA specification. +/// We add it here for the convenience of ATA/ATAPI module writers. +/// +typedef union { + UINT16 Data16[6]; + ATAPI_TEST_UNIT_READY_CMD TestUnitReady; + ATAPI_READ10_CMD Read10; + ATAPI_REQUEST_SENSE_CMD RequestSence; + ATAPI_INQUIRY_CMD Inquiry; + ATAPI_MODE_SENSE_CMD ModeSense; + ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity; +} ATAPI_PACKET_COMMAND; + +#pragma pack() + + +#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000 +#define ATAPI_MAX_DMA_CMD_SECTORS 0x100 + +// ATA/ATAPI Signature equates +#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3 +#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3 +#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3 + +// Spin Up Configuration definitions +#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3 +#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3 +#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3 +#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3 + +// +// ATA Packet Command Code +// +#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3 +#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3 +#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3 +#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3 +#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1 +#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4 +#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices +#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices + +#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices + #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices + #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices + #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices + #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices + #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices + +#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices + #define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices + #define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices + #define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices + #define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices + + #define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices + #define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices + #define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices + #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices + #define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices + +/// +/// Start/Stop and Eject Operations +/// +///@{ +#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc +#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type +#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible +#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray) +///@} + +// +// ATA Commands Code +// + +// +// Class 1: PIO Data-In Commands +// +#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3 +#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1 +#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1 +#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6 +#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3 +#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3 +#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3 + +// +// Class 2: PIO Data-Out Commands +// +#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1 +#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1 +#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6 +#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3 +#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3 + +// +// Class 3 No Data Command +// +#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3 +#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3 +#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1 +#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1 +#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1 +#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1 +#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1 +#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1 +#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6 +#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3 +#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2 +#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1 +#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1 +#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1 +#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1 +#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4 +#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1 +#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3 +#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6 +#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6 + +// +// Set Features Sub Command +// +#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3 +#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3 +#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3 +#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3 +#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3 +#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3 +#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3 +#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3 +#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3 +#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3 +#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3 + +// +// S.M.A.R.T +// +#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3 +#define ATA_CONSTANT_C2 0xc2 ///< reserved +#define ATA_CONSTANT_4F 0x4f ///< reserved + +#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3 + +#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3 + #define ATA_AUTOSAVE_DISABLE_ATTR 0x00 + #define ATA_AUTOSAVE_ENABLE_ATTR 0xf1 + +#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3 + #define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3 + #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3 + +#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3 +#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3 +#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved +#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3 +#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3 + +#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3 +#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3 + +// SMART Log Definitions +#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3 +#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3 +#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3 +#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3 +#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3 +#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3 +#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3 +#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3 +#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3 + +// +// Class 4: DMA Command +// +#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1 +#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5 +#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6 +#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1 +#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA- +#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6 + +// +// ATA Security commands +// +#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3 +#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3 +#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3 +#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3 +#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3 +#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3 + +#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3 + +// +// ATA Device Config Overlay +// +#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6 + #define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6 + #define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6 + #define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6 + #define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6 + +// +// ATA Trusted Computing Feature Set Commands +// +#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3 +#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3 +#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3 +#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3 +#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3 + +// +// ATA Trusted Receive Fields +// +#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3 +#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3 +#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3 +#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3 + +// +// Equates used for Acoustic Flags +// +#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6 +#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6 +#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6 + +// +// Equates used for DiPM Support +// +#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions + #define ATA_DIPM_ENABLE 0x10 // defined in ACS-3 + #define ATA_DIPM_DISABLE 0x90 // defined in ACS-3 + +// +// Equates used for DevSleep Support +// +#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep + #define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec + #define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec + +#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms +#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us +#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms + +// +// Set MAX Commands +// +#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6 +#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6 + #define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6 + #define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6 + #define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6 + #define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6 + +/// +/// Default content of device control register, disable INT, +/// Bit3 is set to 1 according ATA-1 +/// +#define ATA_DEFAULT_CTL (0x0a) +/// +/// Default context of Device/Head Register, +/// Bit7 and Bit5 are set to 1 for back-compatibilities. +/// +#define ATA_DEFAULT_CMD (0xa0) + +#define ATAPI_MAX_BYTE_COUNT (0xfffe) + +#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i + +// +// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier +// defined in MultiMedia Commands (MMC, MMC-2) +// +// Sense Key +// +#define ATA_SK_NO_SENSE (0x0) +#define ATA_SK_RECOVERY_ERROR (0x1) +#define ATA_SK_NOT_READY (0x2) +#define ATA_SK_MEDIUM_ERROR (0x3) +#define ATA_SK_HARDWARE_ERROR (0x4) +#define ATA_SK_ILLEGAL_REQUEST (0x5) +#define ATA_SK_UNIT_ATTENTION (0x6) +#define ATA_SK_DATA_PROTECT (0x7) +#define ATA_SK_BLANK_CHECK (0x8) +#define ATA_SK_VENDOR_SPECIFIC (0x9) +#define ATA_SK_RESERVED_A (0xA) +#define ATA_SK_ABORT (0xB) +#define ATA_SK_RESERVED_C (0xC) +#define ATA_SK_OVERFLOW (0xD) +#define ATA_SK_MISCOMPARE (0xE) +#define ATA_SK_RESERVED_F (0xF) + +// +// Additional Sense Codes +// +#define ATA_ASC_NOT_READY (0x04) +#define ATA_ASC_MEDIA_ERR1 (0x10) +#define ATA_ASC_MEDIA_ERR2 (0x11) +#define ATA_ASC_MEDIA_ERR3 (0x14) +#define ATA_ASC_MEDIA_ERR4 (0x30) +#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06) +#define ATA_ASC_INVALID_CMD (0x20) +#define ATA_ASC_LBA_OUT_OF_RANGE (0x21) +#define ATA_ASC_INVALID_FIELD (0x24) +#define ATA_ASC_WRITE_PROTECTED (0x27) +#define ATA_ASC_MEDIA_CHANGE (0x28) +#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred. +#define ATA_ASC_ILLEGAL_FIELD (0x26) +#define ATA_ASC_NO_MEDIA (0x3A) +#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64) + +// +// Additional Sense Code Qualifier +// +#define ATA_ASCQ_IN_PROGRESS (0x01) + +// +// Error Register +// +#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2 +#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4 +#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4 +#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4 +#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4 +#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1 +#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4 +#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4 + +// +// Status Register +// +#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1 +#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1 +#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4 +#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6 +#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4 +#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1 +#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4 +#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4 +#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1 + +// +// Device Control Register +// +#define ATA_CTLREG_SRST BIT2 ///< Software Reset. +#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #. + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bluetooth.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bluetooth.h new file mode 100644 index 0000000000..96940129ff --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bluetooth.h @@ -0,0 +1,56 @@ +/** @file + This file contains the Bluetooth definitions that are consumed by drivers. + These definitions are from Bluetooth Core Specification Version 4.0 June, 2010 + + Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BLUETOOTH_H_ +#define _BLUETOOTH_H_ + +#pragma pack(1) + +/// +/// BLUETOOTH_ADDRESS +/// +typedef struct { + /// + /// 48bit Bluetooth device address. + /// + UINT8 Address[6]; +} BLUETOOTH_ADDRESS; + +/// +/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail. +/// +typedef struct { + UINT8 FormatType:2; + UINT8 MinorDeviceClass: 6; + UINT16 MajorDeviceClass: 5; + UINT16 MajorServiceClass:11; +} BLUETOOTH_CLASS_OF_DEVICE; + +/// +/// BLUETOOTH_LE_ADDRESS +/// +typedef struct { + /// + /// 48-bit Bluetooth device address + /// + UINT8 Address[6]; + /// + /// 0x00 - Public Device Address + /// 0x01 - Random Device Address + /// + UINT8 Type; +} BLUETOOTH_LE_ADDRESS; + +#pragma pack() + +#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248 + +#define BLUETOOTH_HCI_LINK_KEY_SIZE 16 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bmp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bmp.h new file mode 100644 index 0000000000..36f7194036 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Bmp.h @@ -0,0 +1,42 @@ +/** @file + This file defines BMP file header data structures. + +Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BMP_H_ +#define _BMP_H_ + +#pragma pack(1) + +typedef struct { + UINT8 Blue; + UINT8 Green; + UINT8 Red; + UINT8 Reserved; +} BMP_COLOR_MAP; + +typedef struct { + CHAR8 CharB; + CHAR8 CharM; + UINT32 Size; + UINT16 Reserved[2]; + UINT32 ImageOffset; + UINT32 HeaderSize; + UINT32 PixelWidth; + UINT32 PixelHeight; + UINT16 Planes; ///< Must be 1 + UINT16 BitPerPixel; ///< 1, 4, 8, or 24 + UINT32 CompressionType; + UINT32 ImageSize; ///< Compressed image size in bytes + UINT32 XPixelsPerMeter; + UINT32 YPixelsPerMeter; + UINT32 NumberOfColors; + UINT32 ImportantColors; +} BMP_IMAGE_HEADER; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl.h new file mode 100644 index 0000000000..f373e14680 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl.h @@ -0,0 +1,22 @@ +/** @file + Support for the latest CXL standard + + The main header to reference all versions of CXL Base specification registers + from the MDE + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL_MAIN_H_ +#define _CXL_MAIN_H_ + +#include +// +// CXL assigned new Vendor ID +// +#define CXL_DVSEC_VENDOR_ID 0x1E98 + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl11.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl11.h new file mode 100644 index 0000000000..c3d88d3816 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Cxl11.h @@ -0,0 +1,659 @@ +/** @file + CXL 1.1 Register definitions + + This file contains the register definitions based on the Compute Express Link + (CXL) Specification Revision 1.1. + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL11_H_ +#define _CXL11_H_ + +#include +// +// DVSEC Vendor ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58 +// (subject to change as per CXL assigned Vendor ID) +// +#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086 + +// +// CXL Flex Bus Device default device and function number +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 +// +#define CXL_DEV_DEV 0 +#define CXL_DEV_FUNC 0 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/** + Macro used to verify the size of a data type at compile time and trigger a + STATIC_ASSERT() with an error message if the size of the data type does not + match the expected size. + + @param TypeName Type name of data type to verify. + @param ExpectedSize The expected size, in bytes, of the data type specified + by TypeName. +**/ +#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \ + STATIC_ASSERT ( \ + sizeof (TypeName) == ExpectedSize, \ + "Size of " #TypeName \ + " does not meet CXL 1.1 Specification requirements." \ + ) + +/** + Macro used to verify the offset of a field in a data type at compile time and + trigger a STATIC_ASSERT() with an error message if the offset of the field in + the data type does not match the expected offset. + + @param TypeName Type name of data type to verify. + @param FieldName Field name in the data type specified by TypeName to + verify. + @param ExpectedOffset The expected offset, in bytes, of the field specified + by TypeName and FieldName. +**/ +#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \ + STATIC_ASSERT ( \ + OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \ + "Offset of " #TypeName "." #FieldName \ + " does not meet CXL 1.1 Specification requirements." \ + ) + +/// +/// The PCIe DVSEC for Flex Bus Device +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // bit 0 + UINT16 IoCapable : 1; // bit 1 + UINT16 MemCapable : 1; // bit 2 + UINT16 MemHwInitMode : 1; // bit 3 + UINT16 HdmCount : 2; // bit 4..5 + UINT16 Reserved1 : 8; // bit 6..13 + UINT16 ViralCapable : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + } Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CacheSfCoverage : 5; // bit 3..7 + UINT16 CacheSfGranularity : 3; // bit 8..10 + UINT16 CacheCleanEviction : 1; // bit 11 + UINT16 Reserved1 : 2; // bit 12..13 + UINT16 ViralEnable : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + } Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; + +typedef union { + struct { + UINT16 Reserved1 : 14; // bit 0..13 + UINT16 ViralStatus : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + } Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; + +typedef union { + struct { + UINT16 Reserved1 : 1; // bit 0 + UINT16 Reserved2 : 1; // bit 1 + UINT16 Reserved3 : 1; // bit 2 + UINT16 Reserved4 : 13; // bit 3..15 + } Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; + +typedef union { + struct { + UINT16 Reserved1 : 1; // bit 0 + UINT16 Reserved2 : 1; // bit 1 + UINT16 Reserved3 : 14; // bit 2..15 + } Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; + +typedef union { + struct { + UINT16 ConfigLock : 1; // bit 0 + UINT16 Reserved1 : 15; // bit 1..15 + } Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // bit 0..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // bit 0 + UINT32 MemoryActive : 1; // bit 1 + UINT32 MediaType : 3; // bit 2..4 + UINT32 MemoryClass : 3; // bit 5..7 + UINT32 DesiredInterleave : 3; // bit 8..10 + UINT32 Reserved : 17; // bit 11..27 + UINT32 MemorySizeLow : 4; // bit 28..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // bit 0..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // bit 0..27 + UINT32 MemoryBaseLow : 4; // bit 28..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; + + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // bit 0..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // bit 0 + UINT32 MemoryActive : 1; // bit 1 + UINT32 MediaType : 3; // bit 2..4 + UINT32 MemoryClass : 3; // bit 5..7 + UINT32 DesiredInterleave : 3; // bit 8..10 + UINT32 Reserved : 17; // bit 11..27 + UINT32 MemorySizeLow : 4; // bit 28..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // bit 0..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // bit 0..27 + UINT32 MemoryBaseLow : 4; // bit 28..31 + } Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; + +// +// Flex Bus Device DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58 +// +#define FLEX_BUS_DEVICE_DVSEC_ID 0 + +// +// PCIe DVSEC for Flex Bus Device +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95 +// +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 + CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10 + CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12 + CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18 + CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20 + UINT16 Reserved; // offset 22 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52 +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE; + +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34); +CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38); +///@} + +/// +/// PCIe DVSEC for FLex Bus Port +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // bit 0 + UINT16 IoCapable : 1; // bit 1 + UINT16 MemCapable : 1; // bit 2 + UINT16 Reserved : 13; // bit 3..15 + } Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CxlSyncBypassEnable : 1; // bit 3 + UINT16 DriftBufferEnable : 1; // bit 4 + UINT16 Reserved : 3; // bit 5..7 + UINT16 Retimer1Present : 1; // bit 8 + UINT16 Retimer2Present : 1; // bit 9 + UINT16 Reserved2 : 6; // bit 10..15 + } Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CxlSyncBypassEnable : 1; // bit 3 + UINT16 DriftBufferEnable : 1; // bit 4 + UINT16 Reserved : 3; // bit 5..7 + UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8 + UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9 + UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10 + UINT16 Reserved2 : 5; // bit 11..15 + } Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; + +// +// Flex Bus Port DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62 +// +#define FLEX_BUS_PORT_DVSEC_ID 7 + +// +// PCIe DVSEC for Flex Bus Port +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99 +// +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12 + CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14 +} CXL_1_1_DVSEC_FLEX_BUS_PORT; + +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C); +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E); +CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10); +///@} + +/// +/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers +/// + +/// The CXL.Cache and CXL.Memory Architectural register definitions +/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1 +///@{ + +#define CXL_CAPABILITY_HEADER_OFFSET 0 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlCacheMemVersion : 4; // bit 20..23 + UINT32 ArraySize : 8; // bit 24..31 + } Bits; + UINT32 Uint32; +} CXL_CAPABILITY_HEADER; + +#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlRasCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_RAS_CAPABILITY_HEADER; + +#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_SECURITY_CAPABILITY_HEADER; + +#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_CAPABILITY_HEADER; + +typedef union { + struct { + UINT32 CacheDataParity : 1; // bit 0..0 + UINT32 CacheAddressParity : 1; // bit 1..1 + UINT32 CacheByteEnableParity : 1; // bit 2..2 + UINT32 CacheDataEcc : 1; // bit 3..3 + UINT32 MemDataParity : 1; // bit 4..4 + UINT32 MemAddressParity : 1; // bit 5..5 + UINT32 MemByteEnableParity : 1; // bit 6..6 + UINT32 MemDataEcc : 1; // bit 7..7 + UINT32 ReInitThreshold : 1; // bit 8..8 + UINT32 RsvdEncodingViolation : 1; // bit 9..9 + UINT32 PoisonReceived : 1; // bit 10..10 + UINT32 ReceiverOverflow : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataParityMask : 1; // bit 0..0 + UINT32 CacheAddressParityMask : 1; // bit 1..1 + UINT32 CacheByteEnableParityMask : 1; // bit 2..2 + UINT32 CacheDataEccMask : 1; // bit 3..3 + UINT32 MemDataParityMask : 1; // bit 4..4 + UINT32 MemAddressParityMask : 1; // bit 5..5 + UINT32 MemByteEnableParityMask : 1; // bit 6..6 + UINT32 MemDataEccMask : 1; // bit 7..7 + UINT32 ReInitThresholdMask : 1; // bit 8..8 + UINT32 RsvdEncodingViolationMask : 1; // bit 9..9 + UINT32 PoisonReceivedMask : 1; // bit 10..10 + UINT32 ReceiverOverflowMask : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 CacheDataParitySeverity : 1; // bit 0..0 + UINT32 CacheAddressParitySeverity : 1; // bit 1..1 + UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2 + UINT32 CacheDataEccSeverity : 1; // bit 3..3 + UINT32 MemDataParitySeverity : 1; // bit 4..4 + UINT32 MemAddressParitySeverity : 1; // bit 5..5 + UINT32 MemByteEnableParitySeverity : 1; // bit 6..6 + UINT32 MemDataEccSeverity : 1; // bit 7..7 + UINT32 ReInitThresholdSeverity : 1; // bit 8..8 + UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9 + UINT32 PoisonReceivedSeverity : 1; // bit 10..10 + UINT32 ReceiverOverflowSeverity : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; + +typedef union { + struct { + UINT32 CacheDataEcc : 1; // bit 0..0 + UINT32 MemoryDataEcc : 1; // bit 1..1 + UINT32 CrcThreshold : 1; // bit 2..2 + UINT32 RetryThreshold : 1; // bit 3..3 + UINT32 CachePoisonReceived : 1; // bit 4..4 + UINT32 MemoryPoisonReceived : 1; // bit 5..5 + UINT32 PhysicalLayerError : 1; // bit 6..6 + UINT32 Reserved : 25; // bit 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataEccMask : 1; // bit 0..0 + UINT32 MemoryDataEccMask : 1; // bit 1..1 + UINT32 CrcThresholdMask : 1; // bit 2..2 + UINT32 RetryThresholdMask : 1; // bit 3..3 + UINT32 CachePoisonReceivedMask : 1; // bit 4..4 + UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5 + UINT32 PhysicalLayerErrorMask : 1; // bit 6..6 + UINT32 Reserved : 25; // bit 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 FirstErrorPointer : 4; // bit 0..3 + UINT32 Reserved1 : 5; // bit 4..8 + UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9 + UINT32 Reserved2 : 3; // bit 10..12 + UINT32 PoisonEnabled : 1; // bit 13..13 + UINT32 Reserved3 : 18; // bit 14..31 + } Bits; + UINT32 Uint32; +} CXL_ERROR_CAPABILITIES_AND_CONTROL; + +typedef struct { + CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus; + CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask; + CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity; + CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus; + CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask; + CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl; + UINT32 HeaderLog[16]; +} CXL_1_1_RAS_CAPABILITY_STRUCTURE; + +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14); +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18); +CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58); + +typedef union { + struct { + UINT32 DeviceTrustLevel : 2; // bit 0..1 + UINT32 Reserved : 30; // bit 2..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_SECURITY_POLICY; + +typedef struct { + CXL_1_1_SECURITY_POLICY SecurityPolicy; +} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; + +CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0); +CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4); + +typedef union { + struct { + UINT64 CxlLinkVersionSupported : 4; // bit 0..3 + UINT64 CxlLinkVersionReceived : 4; // bit 4..7 + UINT64 LlrWrapValueSupported : 8; // bit 8..15 + UINT64 LlrWrapValueReceived : 8; // bit 16..23 + UINT64 NumRetryReceived : 5; // bit 24..28 + UINT64 NumPhyReinitReceived : 5; // bit 29..33 + UINT64 WrPtrReceived : 8; // bit 34..41 + UINT64 EchoEseqReceived : 8; // bit 42..49 + UINT64 NumFreeBufReceived : 8; // bit 50..57 + UINT64 Reserved : 6; // bit 58..63 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_CAPABILITY; + +typedef union { + struct { + UINT16 LlReset : 1; // bit 0..0 + UINT16 LlInitStall : 1; // bit 1..1 + UINT16 LlCrdStall : 1; // bit 2..2 + UINT16 InitState : 2; // bit 3..4 + UINT16 LlRetryBufferConsumed : 8; // bit 5..12 + UINT16 Reserved : 3; // bit 13..15 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_CONTROL_AND_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_CONTROL; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_TX_CREDIT_STATUS; + +typedef union { + struct { + UINT32 AckForceThreshold : 8; // bit 0..7 + UINT32 AckFLushRetimer : 10; // bit 8..17 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_ACK_TIMER_CONTROL; + +typedef union { + struct { + UINT32 MdhDisable : 1; // bit 0..0 + UINT32 Reserved : 31; // bit 1..31 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_DEFEATURE; + +typedef struct { + CXL_LINK_LAYER_CAPABILITY LinkLayerCapability; + CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus; + CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl; + CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus; + CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus; + CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl; + CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature; +} CXL_1_1_LINK_CAPABILITY_STRUCTURE; + +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28); +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30); +CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38); + +#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 +typedef union { + struct { + UINT32 Reserved1 : 4; // bit 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 + UINT32 Reserved2 : 24; // bit 8..31 + } Bits; + UINT32 Uint32; +} CXL_IO_ARBITRATION_CONTROL; + +CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4); + +#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 +typedef union { + struct { + UINT32 Reserved1 : 4; // bit 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 + UINT32 Reserved2 : 24; // bit 8..31 + } Bits; + UINT32 Uint32; +} CXL_CACHE_MEMORY_ARBITRATION_CONTROL; + +CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4); + +///@} + +/// The CXL.RCRB base register definition +/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1 +///@{ +typedef union { + struct { + UINT64 RcrbEnable : 1; // bit 0..0 + UINT64 Reserved : 12; // bit 1..12 + UINT64 RcrbBaseAddress : 51; // bit 13..63 + } Bits; + UINT64 Uint64; +} CXL_RCRB_BASE; + +CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8); + +///@} + +#pragma pack() + +// +// CXL Downstream / Upstream Port RCRB space register offsets +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97 +// +#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010 +#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014 +#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPort2Table.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPort2Table.h new file mode 100644 index 0000000000..0ff4769537 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPort2Table.h @@ -0,0 +1,75 @@ +/** @file + ACPI debug port 2 table definition, defined at + Microsoft DebugPort2Specification. + + Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _DEBUG_PORT_2_TABLE_H_ +#define _DEBUG_PORT_2_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// Debug Device Information structure. +// +typedef struct { + UINT8 Revision; + UINT16 Length; + UINT8 NumberofGenericAddressRegisters; + UINT16 NameSpaceStringLength; + UINT16 NameSpaceStringOffset; + UINT16 OemDataLength; + UINT16 OemDataOffset; + UINT16 PortType; + UINT16 PortSubtype; + UINT8 Reserved[2]; + UINT16 BaseAddressRegisterOffset; + UINT16 AddressSizeOffset; +} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT; + +#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00 + +#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL 0x8000 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550 0x0000 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 0x0001 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART 0x0003 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_NVIDIA_16550_UART 0x0005 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART_2X 0x000d +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART 0x000e +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_DCC 0x000f +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_BCM2835_UART 0x0010 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_WITH_GAS 0x0012 +#define EFI_ACPI_DBG2_PORT_TYPE_1394 0x8001 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_1394_STANDARD 0x0000 +#define EFI_ACPI_DBG2_PORT_TYPE_USB 0x8002 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_XHCI 0x0000 +#define EFI_ACPI_DBG2_PORT_SUBTYPE_USB_EHCI 0x0001 +#define EFI_ACPI_DBG2_PORT_TYPE_NET 0x8003 + +// +// Debug Port 2 Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetDbgDeviceInfo; + UINT32 NumberDbgDeviceInfo; +} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE; + +#pragma pack() + +// +// DBG2 Revision (defined in spec) +// +#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPortTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPortTable.h new file mode 100644 index 0000000000..1aaea8ec52 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DebugPortTable.h @@ -0,0 +1,44 @@ +/** @file + ACPI debug port table definition, defined at + Microsoft DebugPortSpecification. + + Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _DEBUG_PORT_TABLE_H_ +#define _DEBUG_PORT_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// Debug Port Table definition. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 InterfaceType; + UINT8 Reserved_37[3]; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; +} EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE; + +#pragma pack() + +// +// DBGP Revision (defined in spec) +// +#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01 + +// +// Interface Type +// +#define EFI_ACPI_DBGP_INTERFACE_TYPE_FULL_16550 0 +#define EFI_ACPI_DBGP_INTERFACE_TYPE_16550_SUBSET_COMPATIBLE_WITH_MS_DBGP_SPEC 1 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Dhcp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Dhcp.h new file mode 100644 index 0000000000..f51bb93c31 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Dhcp.h @@ -0,0 +1,283 @@ +/** @file + This file contains the DHCPv4 and DHCPv6 option definitions and other configuration. + They are used to carry additional information and parameters in DHCP messages. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DHCP_H_ +#define _DHCP_H_ + +/// +/// Dynamic Host Configuration Protocol for IPv4 (DHCPv4) +/// +/// Dhcpv4 Options, definitions from RFC 2132 +/// +#define DHCP4_TAG_PAD 0 /// Pad Option +#define DHCP4_TAG_EOP 255 /// End Option +#define DHCP4_TAG_NETMASK 1 /// Subnet Mask +#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC +#define DHCP4_TAG_ROUTER 3 /// Router option, +#define DHCP4_TAG_TIME_SERVER 4 /// Time Server +#define DHCP4_TAG_NAME_SERVER 5 /// Name Server +#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server +#define DHCP4_TAG_LOG_SERVER 7 /// Log Server +#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server +#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server +#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server +#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server +#define DHCP4_TAG_HOSTNAME 12 /// Host Name +#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size +#define DHCP4_TAG_DUMP 14 /// Merit Dump File +#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name +#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server +#define DHCP4_TAG_ROOTPATH 17 /// Root path +#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path +#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable +#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable +#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter +#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size +#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live +#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout +#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table +#define DHCP4_TAG_IFMTU 26 /// Interface MTU +#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local +#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address +#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery +#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier +#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery +#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address +#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route +#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation +#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout +#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation +#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL +#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval +#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage +#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain +#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers +#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers +#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information +#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server +#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server +#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type +#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope +#define DHCP4_TAG_XFONT 48 /// X Window System Font Server +#define DHCP4_TAG_XDM 49 /// X Window System Display Manager +#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address +#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time +#define DHCP4_TAG_OVERLOAD 52 /// Option Overload +#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type +#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier +#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List +#define DHCP4_TAG_MESSAGE 56 /// Message +#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size +#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value +#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value +#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier +#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier +#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain +#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers +#define DHCP4_TAG_TFTP 66 /// TFTP server name +#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name +#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent +#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server +#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server +#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server +#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server +#define DHCP4_TAG_FINGER 73 /// Default Finger Server +#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server +#define DHCP4_TAG_STTALK 75 /// StreetTalk Server +#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server +#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier +#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578 +#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578 +#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578 +#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route + + +/// +/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6) +/// +/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315. +/// +typedef enum { + Dhcp6MsgSolicit = 1, + Dhcp6MsgAdvertise = 2, + Dhcp6MsgRequest = 3, + Dhcp6MsgConfirm = 4, + Dhcp6MsgRenew = 5, + Dhcp6MsgRebind = 6, + Dhcp6MsgReply = 7, + Dhcp6MsgRelease = 8, + Dhcp6MsgDecline = 9, + Dhcp6MsgReconfigure = 10, + Dhcp6MsgInfoRequest = 11 +} DHCP6_MSG_TYPE; + +/// +/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315. +/// +typedef enum { + Dhcp6OptClientId = 1, + Dhcp6OptServerId = 2, + Dhcp6OptIana = 3, + Dhcp6OptIata = 4, + Dhcp6OptIaAddr = 5, + Dhcp6OptRequestOption = 6, + Dhcp6OptPreference = 7, + Dhcp6OptElapsedTime = 8, + Dhcp6OptReplayMessage = 9, + Dhcp6OptAuthentication = 11, + Dhcp6OptServerUnicast = 12, + Dhcp6OptStatusCode = 13, + Dhcp6OptRapidCommit = 14, + Dhcp6OptUserClass = 15, + Dhcp6OptVendorClass = 16, + Dhcp6OptVendorInfo = 17, + Dhcp6OptInterfaceId = 18, + Dhcp6OptReconfigMessage = 19, + Dhcp6OptReconfigureAccept = 20 +} DHCP6_OPT_CODE; + +/// +/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315. +/// +typedef enum { + Dhcp6StsSuccess = 0, + Dhcp6StsUnspecFail = 1, + Dhcp6StsNoAddrsAvail = 2, + Dhcp6StsNoBinding = 3, + Dhcp6StsNotOnLink = 4, + Dhcp6StsUseMulticast = 5 +} DHCP6_STS_CODE; + +/// +/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315. +/// +typedef enum { + Dhcp6DuidTypeLlt = 1, + Dhcp6DuidTypeEn = 2, + Dhcp6DuidTypeLl = 3, + Dhcp6DuidTypeUuid = 4 +} DHCP6_DUID_TYPE; + +/// Transmission and Retransmission Parameters +/// This section presents a table of values used to describe the message +/// transmission behavior of clients and servers. +/// +/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_SOL_MAX_DELAY 1 +#define DHCP6_SOL_IRT 1 +#define DHCP6_SOL_MRC 0 +#define DHCP6_SOL_MRT 120 +#define DHCP6_SOL_MRD 0 +/// +/// Transmit parameters of request message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_REQ_IRT 1 +#define DHCP6_REQ_MRC 10 +#define DHCP6_REQ_MRT 30 +#define DHCP6_REQ_MRD 0 +/// +/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_CNF_MAX_DELAY 1 +#define DHCP6_CNF_IRT 1 +#define DHCP6_CNF_MRC 0 +#define DHCP6_CNF_MRT 4 +#define DHCP6_CNF_MRD 10 +/// +/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_REN_IRT 10 +#define DHCP6_REN_MRC 0 +#define DHCP6_REN_MRT 600 +#define DHCP6_REN_MRD 0 +/// +/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_REB_IRT 10 +#define DHCP6_REB_MRC 0 +#define DHCP6_REB_MRT 600 +#define DHCP6_REB_MRD 0 +/// +/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_INF_MAX_DELAY 1 +#define DHCP6_INF_IRT 1 +#define DHCP6_INF_MRC 0 +#define DHCP6_INF_MRT 120 +#define DHCP6_INF_MRD 0 +/// +/// Transmit parameters of release message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_REL_IRT 1 +#define DHCP6_REL_MRC 5 +#define DHCP6_REL_MRT 0 +#define DHCP6_REL_MRD 0 +/// +/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315. +/// +#define DHCP6_DEC_IRT 1 +#define DHCP6_DEC_MRC 5 +#define DHCP6_DEC_MRT 0 +#define DHCP6_DEC_MRD 0 + +//// +//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646. +//// +#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option +#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option +#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option +#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses +#define DHCP6_OPT_IAADDR 5 /// IA Address option +#define DHCP6_OPT_ORO 6 /// Request option +#define DHCP6_OPT_PREFERENCE 7 /// Preference option +#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option +#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option +#define DHCP6_OPT_AUTH 11 /// Authentication option +#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option +#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option +#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option +#define DHCP6_OPT_USER_CLASS 15 /// User Class option +#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option +#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option +#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option +#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option +#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option +#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646 +#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970 +#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970 +#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970 +#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970 + +/// +/// Processor Architecture Types +/// These identifiers are defined by IETF: +/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml +/// +#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE +#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE +#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE +#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE +#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE +#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE +#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE +#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE +#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE +#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE + +#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http +#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http +#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http +#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http +#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http +#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http +#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http +#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h new file mode 100644 index 0000000000..a36df39b07 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h @@ -0,0 +1,291 @@ +/** @file + DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R) + Virtualization Technology for Directed I/O (VT-D) Architecture Specification. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture + Specification v3.2, Dated October 2020. + https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf + + @par Glossary: + - HPET - High Precision Event Timer + - NUMA - Non-uniform Memory Access +**/ +#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_ +#define _DMA_REMAPPING_REPORTING_TABLE_H_ + +#include + +#pragma pack(1) + +/// +/// DMA-Remapping Reporting Structure definitions from section 8.1 +///@{ +#define EFI_ACPI_DMAR_REVISION 0x01 + +#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0 +#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1 +#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2 +///@} + +/// +/// Remapping Structure Types definitions from section 8.2 +///@{ +#define EFI_ACPI_DMAR_TYPE_DRHD 0x00 +#define EFI_ACPI_DMAR_TYPE_RMRR 0x01 +#define EFI_ACPI_DMAR_TYPE_ATSR 0x02 +#define EFI_ACPI_DMAR_TYPE_RHSA 0x03 +#define EFI_ACPI_DMAR_TYPE_ANDD 0x04 +#define EFI_ACPI_DMAR_TYPE_SATC 0x05 +///@} + +/// +/// DMA-Remapping Hardware Unit definitions from section 8.3 +/// +#define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0 + +/// +/// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1 +///@{ +#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01 +#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02 +#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03 +#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04 +#define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05 +///@} + +/// +/// Root Port ATS Capability Reporting Structure definitions from section 8.5 +/// +#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0 + +/// +/// Definition for DMA Remapping Structure Header +/// +typedef struct { + UINT16 Type; + UINT16 Length; +} EFI_ACPI_DMAR_STRUCTURE_HEADER; + +/// +/// Definition for DMA-Remapping PCI Path +/// +typedef struct { + UINT8 Device; + UINT8 Function; +} EFI_ACPI_DMAR_PCI_PATH; + +/// +/// Device Scope Structure is defined in section 8.3.1 +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved2; + UINT8 EnumerationId; + UINT8 StartBusNumber; +} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER; + +/** + DMA-remapping hardware unit definition (DRHD) structure is defined in + section 8.3. This uniquely represents a remapping hardware unit present + in the platform. There must be at least one instance of this structure + for each PCI segment in the platform. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + /** + - Bit[0]: INCLUDE_PCI_ALL + - If Set, this remapping hardware unit has under its scope all + PCI compatible devices in the specified Segment, except devices + reported under the scope of other remapping hardware units for + the same Segment. + - If Clear, this remapping hardware unit has under its scope only + devices in the specified Segment that are explicitly identified + through the DeviceScope field. + - Bits[7:1] Reserved. + **/ + UINT8 Flags; + UINT8 Reserved; + /// + /// The PCI Segment associated with this unit. + /// + UINT16 SegmentNumber; + /// + /// Base address of remapping hardware register-set for this unit. + /// + UINT64 RegisterBaseAddress; +} EFI_ACPI_DMAR_DRHD_HEADER; + +/** + Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4 + Reserved memory ranges that may be DMA targets may be reported through the + RMRR structures, along with the devices that requires access to the specified + reserved memory region. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + UINT8 Reserved[2]; + /// + /// PCI Segment Number associated with devices identified through + /// the Device Scope field. + /// + UINT16 SegmentNumber; + /// + /// Base address of 4KB-aligned reserved memory region + /// + UINT64 ReservedMemoryRegionBaseAddress; + /** + Last address of the reserved memory region. Value in this field must be + greater than the value in Reserved Memory Region Base Address field. + The reserved memory region size (Limit - Base + 1) must be an integer + multiple of 4KB. + **/ + UINT64 ReservedMemoryRegionLimitAddress; +} EFI_ACPI_DMAR_RMRR_HEADER; + +/** + Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5. + This structure is applicable only for platforms supporting Device-TLBs as + reported through the Extended Capability Register. For each PCI Segment in + the platform that supports Device-TLBs, BIOS provides an ATSR structure. The + ATSR structures identifies PCI-Express Root-Ports supporting Address + Translation Services (ATS) transactions. Software must enable ATS on endpoint + devices behind a Root Port only if the Root Port is reported as supporting + ATS transactions. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + /** + - Bit[0]: ALL_PORTS: + - If Set, indicates all PCI Express Root Ports in the specified + PCI Segment supports ATS transactions. + - If Clear, indicates ATS transactions are supported only on + Root Ports identified through the Device Scope field. + - Bits[7:1] Reserved. + **/ + UINT8 Flags; + UINT8 Reserved; + /// + /// The PCI Segment associated with this ATSR structure + /// + UINT16 SegmentNumber; +} EFI_ACPI_DMAR_ATSR_HEADER; + +/** + Remapping Hardware Static Affinity (RHSA) is an optional structure defined + in section 8.6. This is intended to be used only on NUMA platforms with + Remapping hardware units and memory spanned across multiple nodes. + When used, there must be a RHSA structure for each Remapping hardware unit + reported through DRHD structure. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + UINT8 Reserved[4]; + /// + /// Register Base Address of this Remap hardware unit reported in the + /// corresponding DRHD structure. + /// + UINT64 RegisterBaseAddress; + /// + /// Proximity Domain to which the Remap hardware unit identified by the + /// Register Base Address field belongs. + /// + UINT32 ProximityDomain; +} EFI_ACPI_DMAR_RHSA_HEADER; + +/** + An ACPI Name-space Device Declaration (ANDD) structure is defined in section + 8.7 and uniquely represents an ACPI name-space enumerated device capable of + issuing DMA requests in the platform. ANDD structures are used in conjunction + with Device-Scope entries of type ACPI_NAMESPACE_DEVICE. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + UINT8 Reserved[3]; + /** + Each ACPI device enumerated through an ANDD structure must have a unique + value for this field. To report an ACPI device with ACPI Device Number + value of X, under the scope of a DRHD unit, a Device-Scope entry of type + ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field. + The Start Bus Number and Path fields in the Device-Scope together + provides the 16-bit source-id allocated by platform for the ACPI device. + **/ + UINT8 AcpiDeviceNumber; +} EFI_ACPI_DMAR_ANDD_HEADER; + +/** + An SoC Integrated Address Translation Cache (SATC) reporting structure is + defined in section 8.8. +**/ +typedef struct { + EFI_ACPI_DMAR_STRUCTURE_HEADER Header; + /** + - Bit[0]: ATC_REQUIRED: + - If Set, indicates that every SoC integrated device enumerated + in this table has a functional requirement to enable its ATC + (via the ATS capability) for device operation. + - If Clear, any device enumerated in this table can operate when + its respective ATC is not enabled (albeit with reduced + performance or functionality). + - Bits[7:1] Reserved. + **/ + UINT8 Flags; + UINT8 Reserved; + /// + /// The PCI Segment associated with this SATC structure. All SoC integrated + /// devices within a PCI segment with same value for Flags field must be + /// enumerated in the same SATC structure. + /// + UINT16 SegmentNumber; +} EFI_ACPI_DMAR_SATC_HEADER; + +/** + DMA Remapping Reporting Structure Header as defined in section 8.1 + This header will be followed by list of Remapping Structures listed below + - DMA Remapping Hardware Unit Definition (DRHD) + - Reserved Memory Region Reporting (RMRR) + - Root Port ATS Capability Reporting (ATSR) + - Remapping Hardware Static Affinity (RHSA) + - ACPI Name-space Device Declaration (ANDD) + - SoC Integrated Address Translation Cache reporting (SATC) + These structure types must by reported in numerical order. + i.e., All remapping structures of type 0 (DRHD) enumerated before remapping + structures of type 1 (RMRR), and so forth. +**/ +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /** + This field indicates the maximum DMA physical addressability supported by + this platform. The system address map reported by the BIOS indicates what + portions of this addresses are populated. The Host Address Width (HAW) of + the platform is computed as (N+1), where N is the value reported in this + field. + For example, for a platform supporting 40 bits of physical addressability, + the value of 100111b is reported in this field. + **/ + UINT8 HostAddressWidth; + /** + - Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt + remapping. If Set, the platform supports interrupt remapping. + - Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform + firmware may Set this field to request system software to opt + out of enabling Extended xAPIC (X2APIC) mode. This field is + valid only when the INTR_REMAP field (bit 0) is Set. + - Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is + recommended to Set this field to report any platform initiated + DMA is restricted to only reserved memory regions (reported in + RMRR structures) when transferring control to system software + such as on ExitBootServices(). + - Bits[7:3] Reserved. + **/ + UINT8 Flags; + UINT8 Reserved[10]; +} EFI_ACPI_DMAR_HEADER; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ElTorito.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ElTorito.h new file mode 100644 index 0000000000..e9b870f778 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ElTorito.h @@ -0,0 +1,141 @@ +/** @file + ElTorito Partitions Format Definition. + This file includes some definitions from + 1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0. + 2. Volume and File Structure of CDROM for Information Interchange, + Standard ECMA-119. (IS0 9660) + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ELTORITO_H_ +#define _ELTORITO_H_ + +// +// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660 +// +#define CDVOL_TYPE_STANDARD 0x0 +#define CDVOL_TYPE_CODED 0x1 +#define CDVOL_TYPE_END 0xFF + +/// +/// CDROM_VOLUME_DESCRIPTOR.Id +/// +#define CDVOL_ID "CD001" + +/// +/// CDROM_VOLUME_DESCRIPTOR.SystemId +/// +#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION" + +// +// Indicator types +// +#define ELTORITO_ID_CATALOG 0x01 +#define ELTORITO_ID_SECTION_BOOTABLE 0x88 +#define ELTORITO_ID_SECTION_NOT_BOOTABLE 0x00 +#define ELTORITO_ID_SECTION_HEADER 0x90 +#define ELTORITO_ID_SECTION_HEADER_FINAL 0x91 + +// +// ELTORITO_CATALOG.Boot.MediaTypes +// +#define ELTORITO_NO_EMULATION 0x00 +#define ELTORITO_12_DISKETTE 0x01 +#define ELTORITO_14_DISKETTE 0x02 +#define ELTORITO_28_DISKETTE 0x03 +#define ELTORITO_HARD_DISK 0x04 + + +#pragma pack(1) + +/// +/// CD-ROM Volume Descriptor +/// +typedef union { + struct { + UINT8 Type; + CHAR8 Id[5]; ///< "CD001" + CHAR8 Reserved[82]; + } Unknown; + + /// + /// Boot Record Volume Descriptor, defined in "El Torito" Specification. + /// + struct { + UINT8 Type; ///< Must be 0 + CHAR8 Id[5]; ///< "CD001" + UINT8 Version; ///< Must be 1 + CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION" + CHAR8 Unused[32]; ///< Must be 0 + UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog + CHAR8 Unused2[13]; ///< Must be 0 + } BootRecordVolume; + + /// + /// Primary Volume Descriptor, defined in ISO 9660. + /// + struct { + UINT8 Type; + CHAR8 Id[5]; ///< "CD001" + UINT8 Version; + UINT8 Unused; ///< Must be 0 + CHAR8 SystemId[32]; + CHAR8 VolumeId[32]; + UINT8 Unused2[8]; ///< Must be 0 + UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks + } PrimaryVolume; + +} CDROM_VOLUME_DESCRIPTOR; + +/// +/// Catalog Entry +/// +typedef union { + struct { + CHAR8 Reserved[0x20]; + } Unknown; + + /// + /// Catalog validation entry (Catalog header) + /// + struct { + UINT8 Indicator; ///< Must be 01 + UINT8 PlatformId; + UINT16 Reserved; + CHAR8 ManufacId[24]; + UINT16 Checksum; + UINT16 Id55AA; + } Catalog; + + /// + /// Initial/Default Entry or Section Entry + /// + struct { + UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable + UINT8 MediaType : 4; + UINT8 Reserved1 : 4; ///< Must be 0 + UINT16 LoadSegment; + UINT8 SystemType; + UINT8 Reserved2; ///< Must be 0 + UINT16 SectorCount; + UINT32 Lba; + } Boot; + + /// + /// Section Header Entry + /// + struct { + UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header + UINT8 PlatformId; + UINT16 SectionEntries; ///< Number of section entries following this header + CHAR8 Id[28]; + } Section; + +} ELTORITO_CATALOG; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Emmc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Emmc.h new file mode 100644 index 0000000000..0987f6c498 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Emmc.h @@ -0,0 +1,291 @@ +/** @file + Header file for eMMC support. + + This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EMMC_H__ +#define __EMMC_H__ + +// +// EMMC command index +// +#define EMMC_GO_IDLE_STATE 0 +#define EMMC_SEND_OP_COND 1 +#define EMMC_ALL_SEND_CID 2 +#define EMMC_SET_RELATIVE_ADDR 3 +#define EMMC_SET_DSR 4 +#define EMMC_SLEEP_AWAKE 5 +#define EMMC_SWITCH 6 +#define EMMC_SELECT_DESELECT_CARD 7 +#define EMMC_SEND_EXT_CSD 8 +#define EMMC_SEND_CSD 9 +#define EMMC_SEND_CID 10 +#define EMMC_STOP_TRANSMISSION 12 +#define EMMC_SEND_STATUS 13 +#define EMMC_BUSTEST_R 14 +#define EMMC_GO_INACTIVE_STATE 15 +#define EMMC_SET_BLOCKLEN 16 +#define EMMC_READ_SINGLE_BLOCK 17 +#define EMMC_READ_MULTIPLE_BLOCK 18 +#define EMMC_BUSTEST_W 19 +#define EMMC_SEND_TUNING_BLOCK 21 +#define EMMC_SET_BLOCK_COUNT 23 +#define EMMC_WRITE_BLOCK 24 +#define EMMC_WRITE_MULTIPLE_BLOCK 25 +#define EMMC_PROGRAM_CID 26 +#define EMMC_PROGRAM_CSD 27 +#define EMMC_SET_WRITE_PROT 28 +#define EMMC_CLR_WRITE_PROT 29 +#define EMMC_SEND_WRITE_PROT 30 +#define EMMC_SEND_WRITE_PROT_TYPE 31 +#define EMMC_ERASE_GROUP_START 35 +#define EMMC_ERASE_GROUP_END 36 +#define EMMC_ERASE 38 +#define EMMC_FAST_IO 39 +#define EMMC_GO_IRQ_STATE 40 +#define EMMC_LOCK_UNLOCK 42 +#define EMMC_SET_TIME 49 +#define EMMC_PROTOCOL_RD 53 +#define EMMC_PROTOCOL_WR 54 +#define EMMC_APP_CMD 55 +#define EMMC_GEN_CMD 56 + +typedef enum { + EmmcPartitionUserData = 0, + EmmcPartitionBoot1 = 1, + EmmcPartitionBoot2 = 2, + EmmcPartitionRPMB = 3, + EmmcPartitionGP1 = 4, + EmmcPartitionGP2 = 5, + EmmcPartitionGP3 = 6, + EmmcPartitionGP4 = 7, + EmmcPartitionUnknown +} EMMC_PARTITION_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 NotUsed:1; // Not used [0:0] + UINT8 Crc:7; // CRC [7:1] + UINT8 ManufacturingDate; // Manufacturing date [15:8] + UINT8 ProductSerialNumber[4]; // Product serial number [47:16] + UINT8 ProductRevision; // Product revision [55:48] + UINT8 ProductName[6]; // Product name [103:56] + UINT8 OemId; // OEM/Application ID [111:104] + UINT8 DeviceType:2; // Device/BGA [113:112] + UINT8 Reserved:6; // Reserved [119:114] + UINT8 ManufacturerId; // Manufacturer ID [127:120] +} EMMC_CID; + +typedef struct { + UINT32 NotUsed:1; // Not used [0:0] + UINT32 Crc:7; // CRC [7:1] + UINT32 Ecc:2; // ECC code [9:8] + UINT32 FileFormat:2; // File format [11:10] + UINT32 TmpWriteProtect:1; // Temporary write protection [12:12] + UINT32 PermWriteProtect:1; // Permanent write protection [13:13] + UINT32 Copy:1; // Copy flag (OTP) [14:14] + UINT32 FileFormatGrp:1; // File format group [15:15] + UINT32 ContentProtApp:1; // Content protection application [16:16] + UINT32 Reserved:4; // Reserved [20:17] + UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21] + UINT32 WriteBlLen:4; // Max. write data block length [25:22] + UINT32 R2WFactor:3; // Write speed factor [28:26] + UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29] + UINT32 WpGrpEnable:1; // Write protect group enable [31:31] + + UINT32 WpGrpSize:5; // Write protect group size [36:32] + UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37] + UINT32 EraseGrpSize:5; // Erase group size [46:42] + UINT32 CSizeMult:3; // Device size multiplier [49:47] + UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50] + UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53] + UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56] + UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59] + UINT32 CSizeLow:2; // Device size low two bits [63:62] + + UINT32 CSizeHigh:10; // Device size high eight bits [73:64] + UINT32 Reserved1:2; // Reserved [75:74] + UINT32 DsrImp:1; // DSR implemented [76:76] + UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77] + UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78] + UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79] + UINT32 ReadBlLen:4; // Max. read data block length [83:80] + UINT32 Ccc:12; // Device command classes [95:84] + + UINT32 TranSpeed:8; // Max. bus clock frequency [103:96] + UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT32 Taac:8; // Data read access-time 1 [119:112] + UINT32 Reserved2:2; // Reserved [121:120] + UINT32 SpecVers:4; // System specification version [125:122] + UINT32 CsdStructure:2; // CSD structure [127:126] +} EMMC_CSD; + +typedef struct { + // + // Modes Segment + // + UINT8 Reserved[16]; // Reserved [15:0] + UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16] + UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17] + UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18] + UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22] + UINT8 FfuStatus; // FFU status R [26] + UINT8 Reserved1[2]; // Reserved [28:27] + UINT8 ModeOperationCodes; // Mode operation codes W/EP [29] + UINT8 ModeConfig; // Mode config R/W/EP [30] + UINT8 Reserved2; // Reserved [31] + UINT8 FlushCache; // Flushing of the cache W/EP [32] + UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33] + UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34] + UINT8 PackedFailureIndex; // Packed command failure index R [35] + UINT8 PackedCommandStatus; // Packed command status R [36] + UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37] + UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52] + UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54] + UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56] + UINT8 DyncapNeeded; // Number of addressed group to be Released R [58] + UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59] + UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60] + UINT8 DataSectorSize; // Sector size R [61] + UINT8 UseNativeSector; // Sector size emulation R/W [62] + UINT8 NativeSectorSize; // Native sector size R [63] + UINT8 VendorSpecificField[64]; // Vendor Specific Fields [127:64] + UINT8 Reserved3[2]; // Reserved [129:128] + UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130] + UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131] + UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132] + UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133] + UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134] + UINT8 Reserved4; // Reserved [135] + UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136] + UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140] + UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143] + UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155] + UINT8 PartitionsAttribute; // Partitions attribute R/W [156] + UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157] + UINT8 PartitioningSupport; // Partitioning Support R [160] + UINT8 HpiMgmt; // HPI management R/W/EP [161] + UINT8 RstFunction; // H/W reset function R/W [162] + UINT8 BkopsEn; // Enable background operations handshake R/W [163] + UINT8 BkopsStart; // Manually start background operations W/EP [164] + UINT8 SanitizeStart; // Start Sanitize operation W/EP [165] + UINT8 WrRelParam; // Write reliability parameter register R [166] + UINT8 WrRelSet; // Write reliability setting register R/W [167] + UINT8 RpmbSizeMult; // RPMB Size R [168] + UINT8 FwConfig; // FW configuration R/W [169] + UINT8 Reserved5; // Reserved [170] + UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171] + UINT8 Reserved6; // Reserved [172] + UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173] + UINT8 BootWpStatus; // Boot write protection status registers R [174] + UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175] + UINT8 Reserved7; // Reserved [176] + UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177] + UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178] + UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179] + UINT8 Reserved8; // Reserved [180] + UINT8 ErasedMemCont; // Erased memory content R [181] + UINT8 Reserved9; // Reserved [182] + UINT8 BusWidth; // Bus width mode W/EP [183] + UINT8 Reserved10; // Reserved [184] + UINT8 HsTiming; // High-speed interface timing R/W/EP [185] + UINT8 Reserved11; // Reserved [186] + UINT8 PowerClass; // Power class R/W/EP [187] + UINT8 Reserved12; // Reserved [188] + UINT8 CmdSetRev; // Command set revision R [189] + UINT8 Reserved13; // Reserved [190] + UINT8 CmdSet; // Command set R/W/EP [191] + // + // Properties Segment + // + UINT8 ExtCsdRev; // Extended CSD revision [192] + UINT8 Reserved14; // Reserved [193] + UINT8 CsdStructure; // CSD STRUCTURE [194] + UINT8 Reserved15; // Reserved [195] + UINT8 DeviceType; // Device type [196] + UINT8 DriverStrength; // I/O Driver Strength [197] + UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198] + UINT8 PartitionSwitchTime; // Partition switching timing [199] + UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200] + UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201] + UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202] + UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203] + UINT8 Reserved16; // Reserved [204] + UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205] + UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206] + UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207] + UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208] + UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209] + UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210] + UINT8 Reserved17; // Reserved [211] + UINT8 SecCount[4]; // Sector Count [215:212] + UINT8 SleepNotificationTime; // Sleep Notification Timeout [216] + UINT8 SATimeout; // Sleep/awake timeout [217] + UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218] + UINT8 SCVccq; // Sleep current (VCCQ) [219] + UINT8 SCVcc; // Sleep current (VCC) [220] + UINT8 HcWpGrpSize; // High-capacity write protect group size [221] + UINT8 RelWrSecC; // Reliable write sector count [222] + UINT8 EraseTimeoutMult; // High-capacity erase timeout [223] + UINT8 HcEraseGrpSize; // High-capacity erase unit size [224] + UINT8 AccSize; // Access size [225] + UINT8 BootSizeMult; // Boot partition size [226] + UINT8 Reserved18; // Reserved [227] + UINT8 BootInfo; // Boot information [228] + UINT8 SecTrimMult; // Secure TRIM Multiplier [229] + UINT8 SecEraseMult; // Secure Erase Multiplier [230] + UINT8 SecFeatureSupport; // Secure Feature support [231] + UINT8 TrimMult; // TRIM Multiplier [232] + UINT8 Reserved19; // Reserved [233] + UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234] + UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235] + UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236] + UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237] + UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238] + UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239] + UINT8 Reserved20; // Reserved [240] + UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241] + UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242] + UINT8 BkopsStatus; // Background operations status [246] + UINT8 PowerOffLongTime; // Power off notification(long) timeout [247] + UINT8 GenericCmd6Time; // Generic CMD6 timeout [248] + UINT8 CacheSize[4]; // Cache size [252:249] + UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253] + UINT8 FirmwareVersion[8]; // Firmware version [261:254] + UINT8 DeviceVersion[2]; // Device version [263:262] + UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264] + UINT8 OptimalWriteSize; // Optimal write size [265] + UINT8 OptimalReadSize; // Optimal read size [266] + UINT8 PreEolInfo; // Pre EOL information [267] + UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268] + UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269] + UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270] + UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302] + UINT8 Reserved21[181]; // Reserved [486:306] + UINT8 FfuArg[4]; // FFU Argument [490:487] + UINT8 OperationCodeTimeout; // Operation codes timeout [491] + UINT8 FfuFeatures; // FFU features [492] + UINT8 SupportedModes; // Supported modes [493] + UINT8 ExtSupport; // Extended partitions attribute support [494] + UINT8 LargeUnitSizeM1; // Large Unit size [495] + UINT8 ContextCapabilities; // Context management capabilities [496] + UINT8 TagResSize; // Tag Resources Size [497] + UINT8 TagUnitSize; // Tag Unit Size [498] + UINT8 DataTagSupport; // Data Tag Support [499] + UINT8 MaxPackedWrites; // Max packed write commands [500] + UINT8 MaxPackedReads; // Max packed read commands[501] + UINT8 BkOpsSupport; // Background operations support [502] + UINT8 HpiFeatures; // HPI features [503] + UINT8 SupportedCmdSet; // Supported Command Sets [504] + UINT8 ExtSecurityErr; // Extended Security Commands Error [505] + UINT8 Reserved22[6]; // Reserved [511:506] +} EMMC_EXT_CSD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h new file mode 100644 index 0000000000..d2bc6d57c4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h @@ -0,0 +1,62 @@ +/** @file + ACPI high precision event timer table definition, at www.intel.com + Specification name is IA-PC HPET (High Precision Event Timers) Specification. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_ +#define _HIGH_PRECISION_EVENT_TIMER_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// HPET Event Timer Block ID described in IA-PC HPET Specification, 3.2.4. +/// +typedef union { + struct { + UINT32 Revision : 8; + UINT32 NumberOfTimers : 5; + UINT32 CounterSize : 1; + UINT32 Reserved : 1; + UINT32 LegacyRoute : 1; + UINT32 VendorId : 16; + } Bits; + UINT32 Uint32; +} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID; + + +/// +/// High Precision Event Timer Table header definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 EventTimerBlockId; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit; + UINT8 HpetNumber; + UINT16 MainCounterMinimumClockTickInPeriodicMode; + UINT8 PageProtectionAndOemAttribute; +} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER; + +/// +/// HPET Revision (defined in spec) +/// +#define EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x01 + +// +// Page protection setting +// Values 3 through 15 are reserved for use by the specification +// +#define EFI_ACPI_NO_PAGE_PROTECTION 0 +#define EFI_ACPI_4KB_PAGE_PROTECTION 1 +#define EFI_ACPI_64KB_PAGE_PROTECTION 2 + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Hsti.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Hsti.h new file mode 100644 index 0000000000..6b403ccbe8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Hsti.h @@ -0,0 +1,76 @@ +/** @file + Support for HSTI 1.1a specification, defined at + Microsoft Hardware Security Testability Specification. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __HSTI_H__ +#define __HSTI_H__ + +#pragma pack(1) + +#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \ + {0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }} + +#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003 + +#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV +#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002 +#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003 +#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004 + +typedef struct { + // + // Return PLATFORM_SECURITY_VERSION_VNEXTCS + // + UINT32 Version; + // + // The role of the publisher of this interface. Reference platform designers + // such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE + // and PLATFORM_SECURITY_ROLE_PLATFORM_IBV respectively. + // If the test modules from the designers are unable to fully verify all + // security features, then the platform implementers, OEMs and ODMs, will + // need to publish this interface with a role of Implementer. + // + UINT32 Role; + // + // Human readable vendor, model, & version of this implementation. + // + CHAR16 ImplementationID[256]; + // + // The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays. + // The arrays must be the same size. + // + UINT32 SecurityFeaturesSize; + // + // IHV-defined bitfield corresponding to all security features which must be + // implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version. + // +//UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV + // + // Publisher-defined bitfield corresponding to all security features which + // have implemented programmatic tests in this module. + // +//UINT8 SecurityFeaturesImplemented[]; + // + // Publisher-defined bitfield corresponding to all security features which + // have been verified implemented by this implementation. + // +//UINT8 SecurityFeaturesVerified[]; + // + // A Null-terminated string, one failure per line (CR/LF terminated), with a + // unique identifier that the OEM/ODM can use to locate the documentation + // which will describe the steps to remediate the failure - a URL to the + // documentation is recommended. + // +//CHAR16 ErrorString[]; +} ADAPTER_INFO_PLATFORM_SECURITY; + +#pragma pack() + +extern EFI_GUID gAdapterInfoPlatformSecurityGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Http11.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Http11.h new file mode 100644 index 0000000000..79fbde66f5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Http11.h @@ -0,0 +1,252 @@ +/** @file + Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616 + + This file contains common HTTP 1.1 definitions from RFC 2616 + + (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __HTTP_11_H__ +#define __HTTP_11_H__ + +#pragma pack(1) + +/// +/// HTTP Version (currently HTTP 1.1) +/// +/// The version of an HTTP message is indicated by an HTTP-Version field +/// in the first line of the message. +/// +#define HTTP_VERSION "HTTP/1.1" + +/// +/// HTTP Request Method definitions +/// +/// The Method token indicates the method to be performed on the +/// resource identified by the Request-URI. The method is case-sensitive. +/// +#define HTTP_METHOD_OPTIONS "OPTIONS" +#define HTTP_METHOD_GET "GET" +#define HTTP_METHOD_HEAD "HEAD" +#define HTTP_METHOD_POST "POST" +#define HTTP_METHOD_PUT "PUT" +#define HTTP_METHOD_DELETE "DELETE" +#define HTTP_METHOD_TRACE "TRACE" +#define HTTP_METHOD_CONNECT "CONNECT" +#define HTTP_METHOD_PATCH "PATCH" + +/// +/// Connect method has maximum length according to EFI_HTTP_METHOD defined in +/// UEFI2.5 spec so use this. +/// +#define HTTP_METHOD_MAXIMUM_LEN sizeof (HTTP_METHOD_CONNECT) + +/// +/// Accept Request Header +/// The Accept request-header field can be used to specify certain media types which are +/// acceptable for the response. Accept headers can be used to indicate that the request +/// is specifically limited to a small set of desired types, as in the case of a request +/// for an in-line image. +/// +#define HTTP_HEADER_ACCEPT "Accept" + + +/// +/// Accept-Charset Request Header +/// The Accept-Charset request-header field can be used to indicate what character sets +/// are acceptable for the response. This field allows clients capable of understanding +/// more comprehensive or special-purpose character sets to signal that capability to a +/// server which is capable of representing documents in those character sets. +/// +#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset" + +/// +/// Accept-Language Request Header +/// The Accept-Language request-header field is similar to Accept, +/// but restricts the set of natural languages that are preferred +/// as a response to the request. +/// +#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language" + +/// +/// Accept-Ranges Request Header +/// The Accept-Ranges response-header field allows the server to +/// indicate its acceptance of range requests for a resource: +/// +#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges" + + +/// +/// Accept-Encoding Request Header +/// The Accept-Encoding request-header field is similar to Accept, +/// but restricts the content-codings that are acceptable in the response. +/// +#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding" + +/// +/// Content-Encoding Header +/// The Content-Encoding entity-header field is used as a modifier to the media-type. +/// When present, its value indicates what additional content codings have been applied +/// to the entity-body, and thus what decoding mechanisms must be applied in order to +/// obtain the media-type referenced by the Content-Type header field. Content-Encoding +/// is primarily used to allow a document to be compressed without losing the identity +/// of its underlying media type. +/// +#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding" + +/// +/// HTTP Content-Encoding Compression types +/// + +#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding. +#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952). +#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress". +#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate" + /// compression mechanism described in RFC 1951. + + +/// +/// Content-Type Header +/// The Content-Type entity-header field indicates the media type of the entity-body sent to +/// the recipient or, in the case of the HEAD method, the media type that would have been sent +/// had the request been a GET. +/// +#define HTTP_HEADER_CONTENT_TYPE "Content-Type" +// +// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml +// +#define HTTP_CONTENT_TYPE_APP_JSON "application/json" +#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream" + +#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html" +#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain" +#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css" +#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml" + +#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif" +#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg" +#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png" +#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml" + + +/// +/// Content-Length Header +/// The Content-Length entity-header field indicates the size of the entity-body, +/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD +/// method, the size of the entity-body that would have been sent had the request been a GET. +/// +#define HTTP_HEADER_CONTENT_LENGTH "Content-Length" + +/// +/// Transfer-Encoding Header +/// The Transfer-Encoding general-header field indicates what (if any) type of transformation +/// has been applied to the message body in order to safely transfer it between the sender +/// and the recipient. This differs from the content-coding in that the transfer-coding +/// is a property of the message, not of the entity. +/// +#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding" +#define HTTP_HEADER_TRANSFER_ENCODING_CHUNKED "chunked" +#define CHUNKED_TRANSFER_CODING_CR '\r' +#define CHUNKED_TRANSFER_CODING_LF '\n' +#define CHUNKED_TRANSFER_CODING_LAST_CHUNK '0' +#define CHUNKED_TRANSFER_CODING_EXTENSION_SEPARATOR ';' + +/// +/// User Agent Request Header +/// +/// The User-Agent request-header field contains information about the user agent originating +/// the request. This is for statistical purposes, the tracing of protocol violations, and +/// automated recognition of user agents for the sake of tailoring responses to avoid +/// particular user agent limitations. User agents SHOULD include this field with requests. +/// The field can contain multiple product tokens and comments identifying the agent and any +/// subproducts which form a significant part of the user agent. +/// By convention, the product tokens are listed in order of their significance for +/// identifying the application. +/// +#define HTTP_HEADER_USER_AGENT "User-Agent" + +/// +/// Host Request Header +/// +/// The Host request-header field specifies the Internet host and port number of the resource +/// being requested, as obtained from the original URI given by the user or referring resource +/// +#define HTTP_HEADER_HOST "Host" + +/// +/// Location Response Header +/// +/// The Location response-header field is used to redirect the recipient to a location other than +/// the Request-URI for completion of the request or identification of a new resource. +/// For 201 (Created) responses, the Location is that of the new resource which was created by +/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for +/// automatic redirection to the resource. The field value consists of a single absolute URI. +/// +#define HTTP_HEADER_LOCATION "Location" + +/// +/// The If-Match request-header field is used with a method to make it conditional. +/// A client that has one or more entities previously obtained from the resource +/// can verify that one of those entities is current by including a list of their +/// associated entity tags in the If-Match header field. +/// The purpose of this feature is to allow efficient updates of cached information +/// with a minimum amount of transaction overhead. It is also used, on updating requests, +/// to prevent inadvertent modification of the wrong version of a resource. +/// As a special case, the value "*" matches any current entity of the resource. +/// +#define HTTP_HEADER_IF_MATCH "If-Match" + + +/// +/// The If-None-Match request-header field is used with a method to make it conditional. +/// A client that has one or more entities previously obtained from the resource can verify +/// that none of those entities is current by including a list of their associated entity +/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient +/// updates of cached information with a minimum amount of transaction overhead. It is also used +/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the +/// client believes that the resource does not exist. +/// +#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match" + + + +/// +/// Authorization Request Header +/// The Authorization field value consists of credentials +/// containing the authentication information of the user agent for +/// the realm of the resource being requested. +/// +#define HTTP_HEADER_AUTHORIZATION "Authorization" + +/// +/// ETAG Response Header +/// The ETag response-header field provides the current value of the entity tag +/// for the requested variant. +/// +#define HTTP_HEADER_ETAG "ETag" + +/// +/// Custom header field checked by the iLO web server to +/// specify a client session key. +/// Example: X-Auth-Token: 24de6b1f8fa147ad59f6452def628798 +/// +#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token" + +/// +/// Expect Header +/// The "Expect" header field in a request indicates a certain set of +/// behaviors (expectations) that need to be supported by the server in +/// order to properly handle this request. The only such expectation +/// defined by this specification is 100-continue. +/// +#define HTTP_HEADER_EXPECT "Expect" + +/// +/// Expect Header Value +/// +#define HTTP_EXPECT_100_CONTINUE "100-continue" + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h new file mode 100644 index 0000000000..547f2cc02f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h @@ -0,0 +1,161 @@ +/** @file + The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's + iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_ +#define _ISCSI_BOOT_FIRMWARE_TABLE_H_ + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8 + +/// +/// Structure Type/ID +/// +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5 + +/// +/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN, +/// not defined in Microsoft iBFT document. +/// +typedef enum { + IpPrefixOriginOther = 0, + IpPrefixOriginManual, + IpPrefixOriginWellKnown, + IpPrefixOriginDhcp, + IpPrefixOriginRouterAdvertisement, + IpPrefixOriginUnchanged = 16 +} IP_PREFIX_VALUE; + +#pragma pack(1) + +/// +/// iBF Table Header +/// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OemId[6]; + UINT64 OemTableId; + UINT8 Reserved[24]; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER; + +/// +/// Common Header of Boot Firmware Table Structure +/// +typedef struct { + UINT8 StructureId; + UINT8 Version; + UINT16 Length; + UINT8 Index; + UINT8 Flags; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER; + +/// +/// Control Structure +/// +typedef struct { + EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header; + UINT16 Extensions; + UINT16 InitiatorOffset; + UINT16 NIC0Offset; + UINT16 Target0Offset; + UINT16 NIC1Offset; + UINT16 Target1Offset; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE; + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1 + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0 + +/// +/// Initiator Structure +/// +typedef struct { + EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header; + EFI_IPv6_ADDRESS ISnsServer; + EFI_IPv6_ADDRESS SlpServer; + EFI_IPv6_ADDRESS PrimaryRadiusServer; + EFI_IPv6_ADDRESS SecondaryRadiusServer; + UINT16 IScsiNameLength; + UINT16 IScsiNameOffset; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE; + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1 + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1 + +/// +/// NIC Structure +/// +typedef struct { + EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header; + EFI_IPv6_ADDRESS Ip; + UINT8 SubnetMaskPrefixLength; + UINT8 Origin; + EFI_IPv6_ADDRESS Gateway; + EFI_IPv6_ADDRESS PrimaryDns; + EFI_IPv6_ADDRESS SecondaryDns; + EFI_IPv6_ADDRESS DhcpServer; + UINT16 VLanTag; + UINT8 Mac[6]; + UINT16 PciLocation; + UINT16 HostNameLength; + UINT16 HostNameOffset; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE; + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1 + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2 + +/// +/// Target Structure +/// +typedef struct { + EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header; + EFI_IPv6_ADDRESS Ip; + UINT16 Port; + UINT8 BootLun[8]; + UINT8 CHAPType; + UINT8 NicIndex; + UINT16 IScsiNameLength; + UINT16 IScsiNameOffset; + UINT16 CHAPNameLength; + UINT16 CHAPNameOffset; + UINT16 CHAPSecretLength; + UINT16 CHAPSecretOffset; + UINT16 ReverseCHAPNameLength; + UINT16 ReverseCHAPNameOffset; + UINT16 ReverseCHAPSecretLength; + UINT16 ReverseCHAPSecretOffset; +} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE; + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1 + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3 + +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1 +#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2 + +#pragma pack() + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IoRemappingTable.h new file mode 100644 index 0000000000..5ecf46097d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IoRemappingTable.h @@ -0,0 +1,203 @@ +/** @file + ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D + + http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf + + Copyright (c) 2017, Linaro Limited. All rights reserved.
+ Copyright (c) 2018, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __IO_REMAPPING_TABLE_H__ +#define __IO_REMAPPING_TABLE_H__ + +#include + +#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0 + +#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0 +#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1 +#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2 +#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3 +#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4 +#define EFI_ACPI_IORT_TYPE_PMCG 0x5 + +#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0 + +#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0 +#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1 +#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2 +#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3 + +#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0 +#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1 + +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0 +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1 +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2 +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3 +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4 +#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5 + +#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0 +#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1 + +#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0 +#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1 + +#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0 +#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1 +#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3 + +#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0 +#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1 +#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2 + +#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0 +#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1 + +#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0 + +#pragma pack(1) + +/// +/// Table header +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 NumNodes; + UINT32 NodeOffset; + UINT32 Reserved; +} EFI_ACPI_6_0_IO_REMAPPING_TABLE; + +/// +/// Definition for ID mapping table shared by all node types +/// +typedef struct { + UINT32 InputBase; + UINT32 NumIds; + UINT32 OutputBase; + UINT32 OutputReference; + UINT32 Flags; +} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE; + +/// +/// Node header definition shared by all node types +/// +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 NumIdMappings; + UINT32 IdReference; +} EFI_ACPI_6_0_IO_REMAPPING_NODE; + +/// +/// Node type 0: ITS node +/// +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT32 NumItsIdentifiers; +//UINT32 ItsIdentifiers[NumItsIdentifiers]; +} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; + +/// +/// Node type 1: root complex node +/// +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT32 CacheCoherent; + UINT8 AllocationHints; + UINT16 Reserved; + UINT8 MemoryAccessFlags; + + UINT32 AtsAttribute; + UINT32 PciSegmentNumber; + UINT8 MemoryAddressSize; + UINT8 Reserved1[3]; +} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; + +/// +/// Node type 2: named component node +/// +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT32 Flags; + UINT32 CacheCoherent; + UINT8 AllocationHints; + UINT16 Reserved; + UINT8 MemoryAccessFlags; + UINT8 AddressSizeLimit; +//UINT8 ObjectName[]; +} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE; + +/// +/// Node type 3: SMMUv1 or SMMUv2 node +/// +typedef struct { + UINT32 Interrupt; + UINT32 InterruptFlags; +} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT64 Base; + UINT64 Span; + UINT32 Model; + UINT32 Flags; + UINT32 GlobalInterruptArrayRef; + UINT32 NumContextInterrupts; + UINT32 ContextInterruptArrayRef; + UINT32 NumPmuInterrupts; + UINT32 PmuInterruptArrayRef; + + UINT32 SMMU_NSgIrpt; + UINT32 SMMU_NSgIrptFlags; + UINT32 SMMU_NSgCfgIrpt; + UINT32 SMMU_NSgCfgIrptFlags; + +//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts]; +//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts]; +} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE; + +/// +/// Node type 4: SMMUv3 node +/// +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT64 Base; + UINT32 Flags; + UINT32 Reserved; + UINT64 VatosAddress; + UINT32 Model; + UINT32 Event; + UINT32 Pri; + UINT32 Gerr; + UINT32 Sync; + UINT32 ProximityDomain; + UINT32 DeviceIdMappingIndex; +} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE; + +/// +/// Node type 5: PMCG node +/// +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NODE Node; + + UINT64 Base; + UINT32 OverflowInterruptGsiv; + UINT32 NodeReference; + UINT64 Page1Base; +//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1]; +} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Ipmi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Ipmi.h new file mode 100644 index 0000000000..0be12b6590 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Ipmi.h @@ -0,0 +1,55 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + IPMI Platform Management FRU Information Storage Definition v1.0 Revision 1.3. + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_H_ +#define _IPMI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Generic Completion Codes definitions +// +#define IPMI_COMP_CODE_NORMAL 0x00 +#define IPMI_COMP_CODE_NODE_BUSY 0xC0 +#define IPMI_COMP_CODE_INVALID_COMMAND 0xC1 +#define IPMI_COMP_CODE_INVALID_FOR_GIVEN_LUN 0xC2 +#define IPMI_COMP_CODE_TIMEOUT 0xC3 +#define IPMI_COMP_CODE_OUT_OF_SPACE 0xC4 +#define IPMI_COMP_CODE_RESERVATION_CANCELED_OR_INVALID 0xC5 +#define IPMI_COMP_CODE_REQUEST_DATA_TRUNCATED 0xC6 +#define IPMI_COMP_CODE_INVALID_REQUEST_DATA_LENGTH 0xC7 +#define IPMI_COMP_CODE_REQUEST_EXCEED_LIMIT 0xC8 +#define IPMI_COMP_CODE_OUT_OF_RANGE 0xC9 +#define IPMI_COMP_CODE_CANNOT_RETURN 0xCA +#define IPMI_COMP_CODE_NOT_PRESENT 0xCB +#define IPMI_COMP_CODE_INVALID_DATA_FIELD 0xCC +#define IPMI_COMP_CODE_COMMAND_ILLEGAL 0xCD +#define IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED 0xCE +#define IPMI_COMP_CODE_FAIL_DUP_REQUEST 0xCF +#define IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE 0xD0 +#define IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE 0xD1 +#define IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS 0xD2 +#define IPMI_COMP_CODE_DEST_UNAVAILABLE 0xD3 +#define IPMI_COMP_CODE_INSUFFICIENT_PRIVILEGE 0xD4 +#define IPMI_COMP_CODE_UNSUPPORTED_IN_PRESENT_STATE 0xD5 +#define IPMI_COMP_CODE_SUBFUNCTION_DISABLED 0xD6 +#define IPMI_COMP_CODE_UNSPECIFIED 0xFF + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h new file mode 100644 index 0000000000..402b586ef1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h @@ -0,0 +1,86 @@ +/** @file + IPMI Platform Management FRU Information Storage Definitions + + This file contains the definitions for: + Common Header Format (Chapter 8) + MultiRecord Header (Section 16.1) + + Copyright (c) 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - IPMI Platform Management FRU Information Storage Definition v1.0 Revision + 1.3, Dated March 24, 2015. + https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-platform-mgt-fru-info-storage-def-v1-0-rev-1-3-spec-update.pdf +**/ + +#ifndef _IPMI_FRU_INFORMATION_STORAGE_H_ +#define _IPMI_FRU_INFORMATION_STORAGE_H_ + +#pragma pack(1) + +// +// Structure definitions for FRU Common Header +// +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT8 FormatVersionNumber:4; + UINT8 Reserved:4; + } Bits; + /// + /// All bit fields as a 8-bit value + /// + UINT8 Uint8; +} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION; + +typedef struct { + IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion; + UINT8 InternalUseStartingOffset; + UINT8 ChassisInfoStartingOffset; + UINT8 BoardAreaStartingOffset; + UINT8 ProductInfoStartingOffset; + UINT8 MultiRecInfoStartingOffset; + UINT8 Pad; + UINT8 Checksum; +} IPMI_FRU_COMMON_HEADER; + +// +// Structure definition for FRU MultiRecord Header +// +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT8 RecordFormatVersion:4; + UINT8 Reserved:3; + UINT8 EndofList:1; + } Bits; + /// + /// All bit fields as a 8-bit value + /// + UINT8 Uint8; +} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION; + +typedef struct { + UINT8 RecordTypeId; + IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion; + UINT8 RecordLength; + UINT8 RecordChecksum; + UINT8 HeaderChecksum; +} IPMI_FRU_MULTI_RECORD_HEADER; + +// +// Structure definition for System UUID Subrecord with checksum. +// +typedef struct { + UINT8 RecordCheckSum; + UINT8 SubRecordId; + EFI_GUID Uuid; +} IPMI_SYSTEM_UUID_SUB_RECORD_WITH_CHECKSUM; + +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h new file mode 100644 index 0000000000..499175f1c4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h @@ -0,0 +1,1029 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + This file contains all NetFn App commands, including: + IPM Device "Global" Commands (Chapter 20) + Firmware Firewall & Command Discovery Commands (Chapter 21) + BMC Watchdog Timer Commands (Chapter 27) + IPMI Messaging Support Commands (Chapter 22) + RMCP+ Support and Payload Commands (Chapter 24) + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_APP_H_ +#define _IPMI_NET_FN_APP_H_ + +#pragma pack(1) +// +// Net function definition for App command +// +#define IPMI_NETFN_APP 0x06 + +// +// Below is Definitions for IPM Device "Global" Commands (Chapter 20) +// + +// +// Definitions for Get Device ID command +// +#define IPMI_APP_GET_DEVICE_ID 0x1 + +// +// Constants and Structure definitions for "Get Device ID" command to follow here +// +typedef union { + struct { + UINT8 DeviceRevision : 4; + UINT8 Reserved : 3; + UINT8 DeviceSdr : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_DEVICE_ID_DEVICE_REV; + +typedef union { + struct { + UINT8 MajorFirmwareRev : 7; + UINT8 UpdateMode : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_DEVICE_ID_FIRMWARE_REV_1; + +typedef union { + struct { + UINT8 SensorDeviceSupport : 1; + UINT8 SdrRepositorySupport : 1; + UINT8 SelDeviceSupport : 1; + UINT8 FruInventorySupport : 1; + UINT8 IpmbMessageReceiver : 1; + UINT8 IpmbMessageGenerator : 1; + UINT8 BridgeSupport : 1; + UINT8 ChassisSupport : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_DEVICE_ID_DEVICE_SUPPORT; + +typedef struct { + UINT8 CompletionCode; + UINT8 DeviceId; + IPMI_GET_DEVICE_ID_DEVICE_REV DeviceRevision; + IPMI_GET_DEVICE_ID_FIRMWARE_REV_1 FirmwareRev1; + UINT8 MinorFirmwareRev; + UINT8 SpecificationVersion; + IPMI_GET_DEVICE_ID_DEVICE_SUPPORT DeviceSupport; + UINT8 ManufacturerId[3]; + UINT16 ProductId; + UINT32 AuxFirmwareRevInfo; +} IPMI_GET_DEVICE_ID_RESPONSE; + + +// +// Definitions for Cold Reset command +// +#define IPMI_APP_COLD_RESET 0x2 + +// +// Constants and Structure definitions for "Cold Reset" command to follow here +// + +// +// Definitions for Warm Reset command +// +#define IPMI_APP_WARM_RESET 0x3 + +// +// Constants and Structure definitions for "Warm Reset" command to follow here +// + +// +// Definitions for Get Self Results command +// +#define IPMI_APP_GET_SELFTEST_RESULTS 0x4 + +// +// Constants and Structure definitions for "Get Self Test Results" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT8 Result; + UINT8 Param; +} IPMI_SELF_TEST_RESULT_RESPONSE; + +#define IPMI_APP_SELFTEST_NO_ERROR 0x55 +#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56 +#define IPMI_APP_SELFTEST_ERROR 0x57 +#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58 +#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL 0x80 +#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR 0x40 +#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU 0x20 +#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL 0x10 +#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08 +#define IPMI_APP_SELFTEST_FRU_CORRUPT 0x04 +#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02 +#define IPMI_APP_SELFTEST_FW_CORRUPT 0x01 + +// +// Definitions for Manufacturing Test ON command +// +#define IPMI_APP_MANUFACTURING_TEST_ON 0x5 + +// +// Constants and Structure definitions for "Manufacturing Test ON" command to follow here +// + +// +// Definitions for Set ACPI Power State command +// +#define IPMI_APP_SET_ACPI_POWERSTATE 0x6 + +// +// Constants and Structure definitions for "Set ACPI Power State" command to follow here +// + +// +// Definitions for System Power State +// +// Working +#define IPMI_SYSTEM_POWER_STATE_S0_G0 0x0 +#define IPMI_SYSTEM_POWER_STATE_S1 0x1 +#define IPMI_SYSTEM_POWER_STATE_S2 0x2 +#define IPMI_SYSTEM_POWER_STATE_S3 0x3 +#define IPMI_SYSTEM_POWER_STATE_S4 0x4 +// Soft off +#define IPMI_SYSTEM_POWER_STATE_S5_G2 0x5 +// Sent when message source cannot differentiate between S4 and S5 +#define IPMI_SYSTEM_POWER_STATE_S4_S5 0x6 +// Mechanical off +#define IPMI_SYSTEM_POWER_STATE_G3 0x7 +// Sleeping - cannot differentiate between S1-S3 +#define IPMI_SYSTEM_POWER_STATE_SLEEPING 0x8 +// Sleeping - cannot differentiate between S1-S4 +#define IPMI_SYSTEM_POWER_STATE_G1_SLEEPING 0x9 +// S5 entered by override +#define IPMI_SYSTEM_POWER_STATE_OVERRIDE 0xA +#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON 0x20 +#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF 0x21 +#define IPMI_SYSTEM_POWER_STATE_UNKNOWN 0x2A +#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE 0x7F + +// +// Definitions for Device Power State +// +#define IPMI_DEVICE_POWER_STATE_D0 0x0 +#define IPMI_DEVICE_POWER_STATE_D1 0x1 +#define IPMI_DEVICE_POWER_STATE_D2 0x2 +#define IPMI_DEVICE_POWER_STATE_D3 0x3 +#define IPMI_DEVICE_POWER_STATE_UNKNOWN 0x2A +#define IPMI_DEVICE_POWER_STATE_NO_CHANGE 0x7F + +typedef union { + struct { + UINT8 PowerState : 7; + UINT8 StateChange : 1; + } Bits; + UINT8 Uint8; +} IPMI_ACPI_POWER_STATE; + +typedef struct { + IPMI_ACPI_POWER_STATE SystemPowerState; + IPMI_ACPI_POWER_STATE DevicePowerState; +} IPMI_SET_ACPI_POWER_STATE_REQUEST; + +// +// Definitions for Get ACPI Power State command +// +#define IPMI_APP_GET_ACPI_POWERSTATE 0x7 + +// +// Constants and Structure definitions for "Get ACPI Power State" command to follow here +// + +// +// Definitions for Get Device GUID command +// +#define IPMI_APP_GET_DEVICE_GUID 0x8 + +// +// Constants and Structure definitions for "Get Device GUID" command to follow here +// +// +// Message structure definition for "Get Device Guid" IPMI command +// +typedef struct { + UINT8 CompletionCode; + UINT8 Guid[16]; +} IPMI_GET_DEVICE_GUID_RESPONSE; + +// +// Below is Definitions for BMC Watchdog Timer Commands (Chapter 27) +// + +// +// Definitions for Reset WatchDog Timer command +// +#define IPMI_APP_RESET_WATCHDOG_TIMER 0x22 + +// +// Definitions for Set WatchDog Timer command +// +#define IPMI_APP_SET_WATCHDOG_TIMER 0x24 + +// +// Constants and Structure definitions for "Set WatchDog Timer" command to follow here +// + +// +// Definitions for watchdog timer use +// +#define IPMI_WATCHDOG_TIMER_BIOS_FRB2 0x1 +#define IPMI_WATCHDOG_TIMER_BIOS_POST 0x2 +#define IPMI_WATCHDOG_TIMER_OS_LOADER 0x3 +#define IPMI_WATCHDOG_TIMER_SMS 0x4 +#define IPMI_WATCHDOG_TIMER_OEM 0x5 + +// +// Structure definition for timer Use +// +typedef union { + struct { + UINT8 TimerUse : 3; + UINT8 Reserved : 3; + UINT8 TimerRunning : 1; + UINT8 TimerUseExpirationFlagLog : 1; + } Bits; + UINT8 Uint8; +} IPMI_WATCHDOG_TIMER_USE; + +// +// Definitions for watchdog timeout action +// +#define IPMI_WATCHDOG_TIMER_ACTION_NO_ACTION 0x0 +#define IPMI_WATCHDOG_TIMER_ACTION_HARD_RESET 0x1 +#define IPMI_WATCHDOG_TIMER_ACTION_POWER_DONW 0x2 +#define IPMI_WATCHDOG_TIMER_ACTION_POWER_CYCLE 0x3 + +// +// Definitions for watchdog pre-timeout interrupt +// +#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NONE 0x0 +#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_SMI 0x1 +#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NMI 0x2 +#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_MESSAGING 0x3 + +// +// Structure definitions for Timer Actions +// +typedef union { + struct { + UINT8 TimeoutAction : 3; + UINT8 Reserved1 : 1; + UINT8 PreTimeoutInterrupt : 3; + UINT8 Reserved2 : 1; + } Bits; + UINT8 Uint8; +} IPMI_WATCHDOG_TIMER_ACTIONS; + +// +// Bit definitions for Timer use expiration flags +// +#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_FRB2 BIT1 +#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_POST BIT2 +#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OS_LOAD BIT3 +#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_SMS_OS BIT4 +#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OEM BIT5 + +typedef struct { + IPMI_WATCHDOG_TIMER_USE TimerUse; + IPMI_WATCHDOG_TIMER_ACTIONS TimerActions; + UINT8 PretimeoutInterval; + UINT8 TimerUseExpirationFlagsClear; + UINT16 InitialCountdownValue; +} IPMI_SET_WATCHDOG_TIMER_REQUEST; + +// +// Definitions for Get WatchDog Timer command +// +#define IPMI_APP_GET_WATCHDOG_TIMER 0x25 + +// +// Constants and Structure definitions for "Get WatchDog Timer" command to follow here +// +typedef struct { + UINT8 CompletionCode; + IPMI_WATCHDOG_TIMER_USE TimerUse; + IPMI_WATCHDOG_TIMER_ACTIONS TimerActions; + UINT8 PretimeoutInterval; + UINT8 TimerUseExpirationFlagsClear; + UINT16 InitialCountdownValue; + UINT16 PresentCountdownValue; +} IPMI_GET_WATCHDOG_TIMER_RESPONSE; + +// +// Below is Definitions for IPMI Messaging Support Commands (Chapter 22) +// + +// +// Definitions for Set BMC Global Enables command +// +#define IPMI_APP_SET_BMC_GLOBAL_ENABLES 0x2E + +// +// Constants and Structure definitions for "Set BMC Global Enables " command to follow here +// +typedef union { + struct { + UINT8 ReceiveMessageQueueInterrupt : 1; + UINT8 EventMessageBufferFullInterrupt : 1; + UINT8 EventMessageBuffer : 1; + UINT8 SystemEventLogging : 1; + UINT8 Reserved : 1; + UINT8 Oem0Enable : 1; + UINT8 Oem1Enable : 1; + UINT8 Oem2Enable : 1; + } Bits; + UINT8 Uint8; +} IPMI_BMC_GLOBAL_ENABLES; + +typedef struct { + IPMI_BMC_GLOBAL_ENABLES SetEnables; +} IPMI_SET_BMC_GLOBAL_ENABLES_REQUEST; + +// +// Definitions for Get BMC Global Enables command +// +#define IPMI_APP_GET_BMC_GLOBAL_ENABLES 0x2F + +// +// Constants and Structure definitions for "Get BMC Global Enables " command to follow here +// +typedef struct { + UINT8 CompletionCode; + IPMI_BMC_GLOBAL_ENABLES GetEnables; +} IPMI_GET_BMC_GLOBAL_ENABLES_RESPONSE; + +// +// Definitions for Clear Message Flags command +// +#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30 + +// +// Constants and Structure definitions for "Clear Message Flags" command to follow here +// +typedef union { + struct { + UINT8 ReceiveMessageQueue : 1; + UINT8 EventMessageBuffer : 1; + UINT8 Reserved1 : 1; + UINT8 WatchdogPerTimeoutInterrupt : 1; + UINT8 Reserved2 : 1; + UINT8 Oem0 : 1; + UINT8 Oem1 : 1; + UINT8 Oem2 : 1; + } Bits; + UINT8 Uint8; +} IPMI_MESSAGE_FLAGS; + +typedef struct { + IPMI_MESSAGE_FLAGS ClearFlags; +} IPMI_CLEAR_MESSAGE_FLAGS_REQUEST; + +// +// Definitions for Get Message Flags command +// +#define IPMI_APP_GET_MESSAGE_FLAGS 0x31 + +// +// Constants and Structure definitions for "Get Message Flags" command to follow here +// +typedef struct { + UINT8 CompletionCode; + IPMI_MESSAGE_FLAGS GetFlags; +} IPMI_GET_MESSAGE_FLAGS_RESPONSE; + +// +// Definitions for Enable Message Channel Receive command +// +#define IPMI_APP_ENABLE_MESSAGE_CHANNEL_RECEIVE 0x32 + +// +// Constants and Structure definitions for "Enable Message Channel Receive" command to follow here +// + +// +// Definitions for Get Message command +// +#define IPMI_APP_GET_MESSAGE 0x33 + +// +// Constants and Structure definitions for "Get Message" command to follow here +// +typedef union { + struct { + UINT8 ChannelNumber : 4; + UINT8 InferredPrivilegeLevel : 4; + } Bits; + UINT8 Uint8; +} IPMI_GET_MESSAGE_CHANNEL_NUMBER; + +typedef struct { + UINT8 CompletionCode; + IPMI_GET_MESSAGE_CHANNEL_NUMBER ChannelNumber; + UINT8 MessageData[0]; +} IPMI_GET_MESSAGE_RESPONSE; + +// +// Definitions for Send Message command +// +#define IPMI_APP_SEND_MESSAGE 0x34 + +// +// Constants and Structure definitions for "Send Message" command to follow here +// +typedef union { + struct { + UINT8 ChannelNumber : 4; + UINT8 Authentication : 1; + UINT8 Encryption : 1; + UINT8 Tracking : 2; + } Bits; + UINT8 Uint8; +} IPMI_SEND_MESSAGE_CHANNEL_NUMBER; + +typedef struct { + UINT8 CompletionCode; + IPMI_SEND_MESSAGE_CHANNEL_NUMBER ChannelNumber; + UINT8 MessageData[0]; +} IPMI_SEND_MESSAGE_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 ResponseData[0]; +} IPMI_SEND_MESSAGE_RESPONSE; + +// +// Definitions for Read Event Message Buffer command +// +#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35 + +// +// Constants and Structure definitions for "Read Event Message Buffer" command to follow here +// + +// +// Definitions for Get BT Interface Capabilities command +// +#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36 + +// +// Constants and Structure definitions for "Get BT Interface Capabilities" command to follow here +// + +// +// Definitions for Get System GUID command +// +#define IPMI_APP_GET_SYSTEM_GUID 0x37 + +// +// Constants and Structure definitions for "Get System GUID" command to follow here +// + +// +// Definitions for Get Channel Authentication Capabilities command +// +#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38 + +// +// Constants and Structure definitions for "Get Channel Authentication Capabilities" command to follow here +// + +// +// Definitions for Get Session Challenge command +// +#define IPMI_APP_GET_SESSION_CHALLENGE 0x39 + +// +// Constants and Structure definitions for "Get Session Challenge" command to follow here +// + +// +// Definitions for Activate Session command +// +#define IPMI_APP_ACTIVATE_SESSION 0x3A + +// +// Constants and Structure definitions for "Activate Session" command to follow here +// + +// +// Definitions for Set Session Privelege Level command +// +#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B + +// +// Constants and Structure definitions for "Set Session Privelege Level" command to follow here +// + +// +// Definitions for Close Session command +// +#define IPMI_APP_CLOSE_SESSION 0x3C + +// +// Constants and Structure definitions for "Close Session" command to follow here +// + +// +// Definitions for Get Session Info command +// +#define IPMI_APP_GET_SESSION_INFO 0x3D + +// +// Constants and Structure definitions for "Get Session Info" command to follow here +// + +// +// Definitions for Get Auth Code command +// +#define IPMI_APP_GET_AUTHCODE 0x3F + +// +// Constants and Structure definitions for "Get AuthCode" command to follow here +// + +// +// Definitions for Set Channel Access command +// +#define IPMI_APP_SET_CHANNEL_ACCESS 0x40 + +// +// Constants and Structure definitions for "Set Channel Access" command to follow here +// + +// +// Definitions for Get Channel Access command +// +#define IPMI_APP_GET_CHANNEL_ACCESS 0x41 + +// +// Constants and Structure definitions for "Get Channel Access" command to follow here +// + +// +// Definitions for channel access memory type in Get Channel Access command request +// +#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_NON_VOLATILE 0x1 +#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_PRESENT_VOLATILE_SETTING 0x2 + +// +// Definitions for channel access modes in Get Channel Access command response +// +#define IPMI_CHANNEL_ACCESS_MODES_DISABLED 0x0 +#define IPMI_CHANNEL_ACCESS_MODES_PRE_BOOT_ONLY 0x1 +#define IPMI_CHANNEL_ACCESS_MODES_ALWAYS_AVAILABLE 0x2 +#define IPMI_CHANNEL_ACCESS_MODES_SHARED 0x3 + +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER; + +typedef union { + struct { + UINT8 Reserved : 6; + UINT8 MemoryType : 2; + } Bits; + UINT8 Uint8; +} IPMI_GET_CHANNEL_ACCESS_TYPE; + +typedef struct { + IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER ChannelNumber; + IPMI_GET_CHANNEL_ACCESS_TYPE AccessType; +} IPMI_GET_CHANNEL_ACCESS_REQUEST; + +typedef union { + struct { + UINT8 AccessMode : 3; + UINT8 UserLevelAuthEnabled : 1; + UINT8 MessageAuthEnable : 1; + UINT8 Alert : 1; + UINT8 Reserved : 2; + } Bits; + UINT8 Uint8; +} IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS; + +typedef union { + struct { + UINT8 ChannelPriviledgeLimit : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT; + +typedef struct { + UINT8 CompletionCode; + IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS ChannelAccess; + IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT PrivilegeLimit; +} IPMI_GET_CHANNEL_ACCESS_RESPONSE; + +// +// Definitions for Get Channel Info command +// +#define IPMI_APP_GET_CHANNEL_INFO 0x42 + +// +// Constants and Structure definitions for "Get Channel Info" command to follow here +// + +// +// Definitions for channel media type +// +// IPMB (I2C) +#define IPMI_CHANNEL_MEDIA_TYPE_IPMB 0x1 +// ICMB v1.0 +#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0 0x2 +// ICMB v0.9 +#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9 0x3 +// 802.3 LAN +#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN 0x4 +// Asynch. Serial/Modem (RS-232) +#define IPMI_CHANNEL_MEDIA_TYPE_RS_232 0x5 +// Other LAN +#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN 0x6 +// PCI SMBus +#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS 0x7 +// SMBus v1.0/1.1 +#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1 0x8 +// SMBus v2.0 +#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2 0x9 +// USB 1.x +#define IPMI_CHANNEL_MEDIA_TYPE_USB1 0xA +// USB 2.x +#define IPMI_CHANNEL_MEDIA_TYPE_USB2 0xB +// System Interface (KCS, SMIC, or BT) +#define IPMI_CHANNEL_MEDIA_TYPE_SYSTEM_INTERFACE 0xC +// OEM +#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START 0x60 +#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END 0x7F + +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_INFO_CHANNEL_NUMBER; + +typedef union { + struct { + UINT8 ChannelMediumType : 7; + UINT8 Reserved : 1; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_INFO_MEDIUM_TYPE; + +typedef union { + struct { + UINT8 ChannelProtocolType : 5; + UINT8 Reserved : 3; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_INFO_PROTOCOL_TYPE; + +typedef union { + struct { + UINT8 ActiveSessionCount : 6; + UINT8 SessionSupport : 2; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_INFO_SESSION_SUPPORT; + +typedef struct { + UINT8 CompletionCode; + IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber; + IPMI_CHANNEL_INFO_MEDIUM_TYPE MediumType; + IPMI_CHANNEL_INFO_PROTOCOL_TYPE ProtocolType; + IPMI_CHANNEL_INFO_SESSION_SUPPORT SessionSupport; + UINT8 VendorId[3]; + UINT16 AuxChannelInfo; +} IPMI_GET_CHANNEL_INFO_RESPONSE; + +// +// Definitions for Get Channel Info command +// +#define IPMI_APP_GET_CHANNEL_INFO 0x42 + +// +// Constants and Structure definitions for "Get Channel Info" command to follow here +// + +// +// Definitions for Set User Access command +// +#define IPMI_APP_SET_USER_ACCESS 0x43 + +// +// Constants and Structure definitions for "Set User Access" command to follow here +// + +// +// Definitions for Get User Access command +// +#define IPMI_APP_GET_USER_ACCESS 0x44 + +// +// Constants and Structure definitions for "Get User Access" command to follow here +// +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_GET_USER_ACCESS_CHANNEL_NUMBER; + +typedef union { + struct { + UINT8 UserId : 6; + UINT8 Reserved : 2; + } Bits; + UINT8 Uint8; +} IPMI_USER_ID; + +typedef struct { + IPMI_GET_USER_ACCESS_CHANNEL_NUMBER ChannelNumber; + IPMI_USER_ID UserId; +} IPMI_GET_USER_ACCESS_REQUEST; + +typedef union { + struct { + UINT8 MaxUserId : 6; + UINT8 Reserved : 2; + } Bits; + UINT8 Uint8; +} IPMI_GET_USER_ACCESS_MAX_USER_ID; + +typedef union { + struct { + UINT8 CurrentUserId : 6; + UINT8 UserIdEnableStatus : 2; + } Bits; + UINT8 Uint8; +} IPMI_GET_USER_ACCESS_CURRENT_USER; + +typedef union { + struct { + UINT8 FixedUserId : 6; + UINT8 Reserved : 2; + } Bits; + UINT8 Uint8; +} IPMI_GET_USER_ACCESS_FIXED_NAME_USER; + +typedef union { + struct { + UINT8 UserPrivilegeLimit : 4; + UINT8 EnableIpmiMessaging : 1; + UINT8 EnableUserLinkAuthetication : 1; + UINT8 UserAccessAvailable : 1; + UINT8 Reserved : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_USER_ACCESS_CHANNEL_ACCESS; + +typedef struct { + UINT8 CompletionCode; + IPMI_GET_USER_ACCESS_MAX_USER_ID MaxUserId; + IPMI_GET_USER_ACCESS_CURRENT_USER CurrentUser; + IPMI_GET_USER_ACCESS_FIXED_NAME_USER FixedNameUser; + IPMI_GET_USER_ACCESS_CHANNEL_ACCESS ChannelAccess; +} IPMI_GET_USER_ACCESS_RESPONSE; + +// +// Definitions for Set User Name command +// +#define IPMI_APP_SET_USER_NAME 0x45 + +// +// Constants and Structure definitions for "Set User Name" command to follow here +// +typedef struct { + IPMI_USER_ID UserId; + UINT8 UserName[16]; +} IPMI_SET_USER_NAME_REQUEST; + +// +// Definitions for Get User Name command +// +#define IPMI_APP_GET_USER_NAME 0x46 + +// +// Constants and Structure definitions for "Get User Name" command to follow here +// +typedef struct { + IPMI_USER_ID UserId; +} IPMI_GET_USER_NAME_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 UserName[16]; +} IPMI_GET_USER_NAME_RESPONSE; + +// +// Definitions for Set User Password command +// +#define IPMI_APP_SET_USER_PASSWORD 0x47 + +// +// Constants and Structure definitions for "Set User Password" command to follow here +// + +// +// Definitions for Set User password command operation type +// +#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_DISABLE_USER 0x0 +#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_ENABLE_USER 0x1 +#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_SET_PASSWORD 0x2 +#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_TEST_PASSWORD 0x3 + +// +// Definitions for Set user password command password size +// +#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_16 0x0 +#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_20 0x1 + +typedef union { + struct { + UINT8 UserId : 6; + UINT8 Reserved : 1; + UINT8 PasswordSize : 1; + } Bits; + UINT8 Uint8; +} IPMI_SET_USER_PASSWORD_USER_ID; + +typedef union { + struct { + UINT8 Operation : 2; + UINT8 Reserved : 6; + } Bits; + UINT8 Uint8; +} IPMI_SET_USER_PASSWORD_OPERATION; + +typedef struct { + IPMI_SET_USER_PASSWORD_USER_ID UserId; + IPMI_SET_USER_PASSWORD_OPERATION Operation; + UINT8 PasswordData[0]; // 16 or 20 bytes, depending on the 'PasswordSize' field +} IPMI_SET_USER_PASSWORD_REQUEST; + +// +// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24) +// + +// +// Definitions for Activate Payload command +// +#define IPMI_APP_ACTIVATE_PAYLOAD 0x48 + +// +// Constants and Structure definitions for "Activate Payload" command to follow here +// + +// +// Definitions for De-Activate Payload command +// +#define IPMI_APP_DEACTIVATE_PAYLOAD 0x49 + +// +// Constants and Structure definitions for "DeActivate Payload" command to follow here +// + +// +// Definitions for Get Payload activation Status command +// +#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a + +// +// Constants and Structure definitions for "Get Payload activation Status" command to follow here +// + +// +// Definitions for Get Payload Instance Info command +// +#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b + +// +// Constants and Structure definitions for "Get Payload Instance Info" command to follow here +// + +// +// Definitions for Set User Payload Access command +// +#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C + +// +// Constants and Structure definitions for "Set User Payload Access" command to follow here +// + +// +// Definitions for Get User Payload Access command +// +#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D + +// +// Constants and Structure definitions for "Get User Payload Access" command to follow here +// + +// +// Definitions for Get Channel Payload Support command +// +#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E + +// +// Constants and Structure definitions for "Get Channel Payload Support" command to follow here +// + +// +// Definitions for Get Channel Payload Version command +// +#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F + +// +// Constants and Structure definitions for "Get Channel Payload Version" command to follow here +// + +// +// Definitions for Get Channel OEM Payload Info command +// +#define IPMI_APP_GET_CHANNEL_OEM_PAYLOAD_INFO 0x50 + +// +// Constants and Structure definitions for "Get Channel OEM Payload Info" command to follow here +// + +// +// Definitions for Master Write-Read command +// +#define IPMI_APP_MASTER_WRITE_READ 0x52 + +// +// Constants and Structure definitions for "Master Write Read" command to follow here +// + +// +// Definitions for Get Channel Cipher Suites command +// +#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54 + +// +// Constants and Structure definitions for "Get Channel Cipher Suites" command to follow here +// + +// +// Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24, Section 3) +// + +// +// Definitions for Suspend-Resume Payload Encryption command +// +#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55 + +// +// Constants and Structure definitions for "Suspend-Resume Payload Encryption" command to follow here +// + +// +// Below is Definitions for IPMI Messaging Support Commands (Chapter 22, Section 25 and 9) +// + +// +// Definitions for Set Channel Security Keys command +// +#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56 + +// +// Constants and Structure definitions for "Set Channel Security Keys" command to follow here +// + +// +// Definitions for Get System Interface Capabilities command +// +#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57 + +// +// Constants and Structure definitions for "Get System Interface Capabilities" command to follow here +// + +// +// Definitions for Get System Interface Capabilities command SSIF transaction support +// +#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_SINGLE_PARTITION_RW 0x0 +#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW 0x1 +#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW_WITH_MIDDLE 0x2 + +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h new file mode 100644 index 0000000000..640a5402e3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h @@ -0,0 +1,237 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + IPMI Intelligent Chassis Management Bus Bridge Specification Version 1.0, + Revision 1.3. + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_BRIDGE_H_ +#define _IPMI_NET_FN_BRIDGE_H_ + +// +// Net function definition for Bridge command +// +#define IPMI_NETFN_BRIDGE 0x02 + +// +// Definitions for Get Bridge State command +// +#define IPMI_BRIDGE_GET_STATE 0x00 + +// +// Constants and Structure definitions for "Get Bridge State" command to follow here +// + +// +// Definitions for Set Bridge State command +// +#define IPMI_BRIDGE_SET_STATE 0x01 + +// +// Constants and Structure definitions for "Set Bridge State" command to follow here +// + +// +// Definitions for Get ICMB Address command +// +#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02 + +// +// Constants and Structure definitions for "Get ICMB Address" command to follow here +// + +// +// Definitions for Set ICMB Address command +// +#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03 + +// +// Constants and Structure definitions for "Set ICMB Address" command to follow here +// + +// +// Definitions for Set Bridge Proxy Address command +// +#define IPMI_BRIDGE_SET_PROXY_ADDRESS 0x04 + +// +// Constants and Structure definitions for "Set Bridge Proxy Address" command to follow here +// + +// +// Definitions for Get Bridge Statistics command +// +#define IPMI_BRIDGE_GET_BRIDGE_STATISTICS 0x05 + +// +// Constants and Structure definitions for "Get Bridge Statistics" command to follow here +// + +// +// Definitions for Get ICMB Capabilities command +// +#define IPMI_BRIDGE_GET_ICMB_CAPABILITIES 0x06 + +// +// Constants and Structure definitions for "Get ICMB Capabilities" command to follow here +// + +// +// Definitions for Clear Bridge Statistics command +// +#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08 + +// +// Constants and Structure definitions for "Clear Bridge Statistics" command to follow here +// + +// +// Definitions for Get Bridge Proxy Address command +// +#define IPMI_BRIDGE_GET_PROXY_ADDRESS 0x09 + +// +// Constants and Structure definitions for "Get Bridge Proxy Address" command to follow here +// + +// +// Definitions for Get ICMB Connector Info command +// +#define IPMI_BRIDGE_GET_ICMB_CONNECTOR_INFO 0x0A + +// +// Constants and Structure definitions for "Get ICMB Connector Info " command to follow here +// + +// +// Definitions for Get ICMB Connection ID command +// +#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B + +// +// Constants and Structure definitions for "Get ICMB Connection ID" command to follow here +// + +// +// Definitions for Get ICMB Connection ID command +// +#define IPMI_BRIDGE_SEND_ICMB_CONNECTION_ID 0x0C + +// +// Constants and Structure definitions for "Send ICMB Connection ID" command to follow here +// + +// +// Definitions for Prepare for Discovery command +// +#define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY 0x10 + +// +// Constants and Structure definitions for "Prepare for Discovery" command to follow here +// + +// +// Definitions for Get Addresses command +// +#define IPMI_BRIDGE_GET_ADDRESSES 0x11 + +// +// Constants and Structure definitions for "Get Addresses" command to follow here +// + +// +// Definitions for Set Discovered command +// +#define IPMI_BRIDGE_SET_DISCOVERED 0x12 + +// +// Constants and Structure definitions for "Set Discovered" command to follow here +// + +// +// Definitions for Get Chassis Device ID command +// +#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13 + +// +// Constants and Structure definitions for "Get Chassis Device ID" command to follow here +// + +// +// Definitions for Set Chassis Device ID command +// +#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14 + +// +// Constants and Structure definitions for "Set Chassis Device ID" command to follow here +// + +// +// Definitions for Bridge Request command +// +#define IPMI_BRIDGE_REQUEST 0x20 + +// +// Constants and Structure definitions for "Bridge Request" command to follow here +// + +// +// Definitions for Bridge Message command +// +#define IPMI_BRIDGE_MESSAGE 0x21 + +// +// Constants and Structure definitions for "Bridge Message" command to follow here +// + +// +// Definitions for Get Event Count command +// +#define IPMI_BRIDGE_GET_EVENT_COUNT 0x30 + +// +// Constants and Structure definitions for "Get Event Count" command to follow here +// + +// +// Definitions for Set Event Destination command +// +#define IPMI_BRIDGE_SET_EVENT_DESTINATION 0x31 + +// +// Constants and Structure definitions for "Set Event Destination" command to follow here +// + +// +// Definitions for Set Event Reception State command +// +#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32 + +// +// Constants and Structure definitions for "Set Event Reception State" command to follow here +// + +// +// Definitions for Set Event Reception State command +// +#define IPMI_BRIDGE_SET_EVENT_RECEPTION_STATE 0x32 + +// +// Constants and Structure definitions for "Set Event Reception State" command to follow here +// + +// +// Definitions for Send ICMB Event Message command +// +#define IPMI_BRIDGE_SEND_ICMB_EVENT_MESSAGE 0x33 + +// +// Constants and Structure definitions for "Send ICMB Event Message" command to follow here +// + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h new file mode 100644 index 0000000000..d1aaf485a8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h @@ -0,0 +1,462 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + This file contains all NetFn Chassis commands, including: + Chassis Commands (Chapter 28) + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_CHASSIS_H_ +#define _IPMI_NET_FN_CHASSIS_H_ + +#pragma pack (1) +// +// Net function definition for Chassis command +// +#define IPMI_NETFN_CHASSIS 0x00 + +// +// Below is Definitions for Chassis commands (Chapter 28) +// + +// +// Definitions for Get Chassis Capabilities command +// +#define IPMI_CHASSIS_GET_CAPABILITIES 0x00 + +// +// Constants and Structure definitions for "Get Chassis Capabilities" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT8 CapabilitiesFlags; + UINT8 ChassisFruInfoDeviceAddress; + UINT8 ChassisSDRDeviceAddress; + UINT8 ChassisSELDeviceAddress; + UINT8 ChassisSystemManagementDeviceAddress; + UINT8 ChassisBridgeDeviceAddress; +} IPMI_GET_CHASSIS_CAPABILITIES_RESPONSE; + +// +// Definitions for Get Chassis Status command +// +#define IPMI_CHASSIS_GET_STATUS 0x01 + +// +// Constants and Structure definitions for "Get Chassis Status" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT8 CurrentPowerState; + UINT8 LastPowerEvent; + UINT8 MiscChassisState; + UINT8 FrontPanelButtonCapabilities; +} IPMI_GET_CHASSIS_STATUS_RESPONSE; + +// +// Definitions for Chassis Control command +// +#define IPMI_CHASSIS_CONTROL 0x02 + +// +// Constants and Structure definitions for "Chassis Control" command to follow here +// +typedef union { + struct { + UINT8 ChassisControl:4; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL; + +typedef struct { + IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL ChassisControl; +} IPMI_CHASSIS_CONTROL_REQUEST; + +// +// Definitions for Chassis Reset command +// +#define IPMI_CHASSIS_RESET 0x03 + +// +// Constants and Structure definitions for "Chassis Reset" command to follow here +// + +// +// Definitions for Chassis Identify command +// +#define IPMI_CHASSIS_IDENTIFY 0x04 + +// +// Constants and Structure definitions for "Chassis Identify" command to follow here +// + +// +// Definitions for Set Chassis Capabilities command +// +#define IPMI_CHASSIS_SET_CAPABILITIES 0x05 + +// +// Constants and Structure definitions for "Set Chassis Capabilities" command to follow here +// + +// +// Definitions for Set Power Restore Policy command +// +#define IPMI_CHASSIS_SET_POWER_RESTORE_POLICY 0x06 + +// +// Constants and Structure definitions for "Set Power Restore Policy" command to follow here +// +typedef union { + struct { + UINT8 PowerRestorePolicy : 3; + UINT8 Reserved : 5; + } Bits; + UINT8 Uint8; +} IPMI_POWER_RESTORE_POLICY; + +typedef struct { + IPMI_POWER_RESTORE_POLICY PowerRestorePolicy; +} IPMI_SET_POWER_RESTORE_POLICY_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 PowerRestorePolicySupport; +} IPMI_SET_POWER_RESTORE_POLICY_RESPONSE; + +// +// Definitions for Get System Restart Cause command +// +#define IPMI_CHASSIS_GET_SYSTEM_RESTART_CAUSE 0x07 + +// +// Constants and Structure definitions for "Get System Restart Cause" command to follow here +// +#define IPMI_SYSTEM_RESTART_CAUSE_UNKNOWN 0x0 +#define IPMI_SYSTEM_RESTART_CAUSE_CHASSIS_CONTROL_COMMAND 0x1 +#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_RESET 0x2 +#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_POWERUP 0x3 +#define IPMI_SYSTEM_RESTART_CAUSE_WATCHDOG_EXPIRE 0x4 +#define IPMI_SYSTEM_RESTART_CAUSE_OEM 0x5 +#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_ALWAYS_RESTORE 0x6 +#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_RESTORE_PREV 0x7 +#define IPMI_SYSTEM_RESTART_CAUSE_PEF_RESET 0x8 +#define IPMI_SYSTEM_RESTART_CAUSE_PEF_POWERCYCLE 0x9 +#define IPMI_SYSTEM_RESTART_CAUSE_SOFT_RESET 0xA +#define IPMI_SYSTEM_RESTART_CAUSE_RTC_POWERUP 0xB + +typedef union { + struct { + UINT8 Cause:4; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_SYSTEM_RESTART_CAUSE; + +typedef struct { + UINT8 CompletionCode; + IPMI_SYSTEM_RESTART_CAUSE RestartCause; + UINT8 ChannelNumber; +} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE; + +// +// Definitions for Set System BOOT options command +// +#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08 + +// +// Constants and Structure definitions for "Set System boot options" command to follow here +// +typedef union { + struct { + UINT8 ParameterSelector:7; + UINT8 MarkParameterInvalid:1; + } Bits; + UINT8 Uint8; +} IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID; + +typedef struct { + IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid; + UINT8 ParameterData[0]; +} IPMI_SET_BOOT_OPTIONS_REQUEST; + +typedef struct { + UINT8 CompletionCode:8; +} IPMI_SET_BOOT_OPTIONS_RESPONSE; + +// +// Definitions for Get System Boot options command +// +#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09 + +// +// Constants and Structure definitions for "Get System boot options" command to follow here +// +typedef union { + struct { + UINT8 ParameterSelector:7; + UINT8 Reserved:1; + } Bits; + UINT8 Uint8; +} IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR; + +typedef struct { + IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR ParameterSelector; + UINT8 SetSelector; + UINT8 BlockSelector; +} IPMI_GET_BOOT_OPTIONS_REQUEST; + +typedef struct { + UINT8 Parameter; + UINT8 Valid; + UINT8 Data1; + UINT8 Data2; + UINT8 Data3; + UINT8 Data4; + UINT8 Data5; +} IPMI_GET_THE_SYSTEM_BOOT_OPTIONS; + +typedef struct { + UINT8 ParameterVersion; + UINT8 ParameterValid; + UINT8 ChannelNumber; + UINT32 SessionId; + UINT32 TimeStamp; + UINT8 Reserved[3]; +} IPMI_BOOT_INITIATOR; + +// +// Definitions for boot option parameter selector +// +#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SET_IN_PROGRESS 0x0 +#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SELECTOR 0x1 +#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SCAN 0x2 +#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_BMC_BOOT_FLAG 0x3 +#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INFO_ACK 0x4 +#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS 0x5 +#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_INFO 0x6 +#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_MAILBOX 0x7 +#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_BEGIN 0x60 +#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_END 0x7F + +// +// Response Parameters for IPMI Get Boot Options +// +typedef union { + struct { + UINT8 SetInProgress : 2; + UINT8 Reserved : 6; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0; + +typedef struct { + UINT8 ServicePartitionSelector; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1; + +typedef union { + struct { + UINT8 ServicePartitionDiscovered : 1; + UINT8 ServicePartitionScanRequest : 1; + UINT8 Reserved: 6; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2; + +typedef union { + struct { + UINT8 BmcBootFlagValid : 5; + UINT8 Reserved : 3; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3; + +typedef struct { + UINT8 WriteMask; + UINT8 BootInitiatorAcknowledgeData; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4; + +// +// Definitions for the 'Boot device selector' field of Boot Option Parameters #5 +// +#define IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE 0x0 +#define IPMI_BOOT_DEVICE_SELECTOR_PXE 0x1 +#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE 0x2 +#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE_SAFE_MODE 0x3 +#define IPMI_BOOT_DEVICE_SELECTOR_DIAGNOSTIC_PARTITION 0x4 +#define IPMI_BOOT_DEVICE_SELECTOR_CD_DVD 0x5 +#define IPMI_BOOT_DEVICE_SELECTOR_BIOS_SETUP 0x6 +#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_FLOPPY 0x7 +#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_CD_DVD 0x8 +#define IPMI_BOOT_DEVICE_SELECTOR_PRIMARY_REMOTE_MEDIA 0x9 +#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_HARDDRIVE 0xB +#define IPMI_BOOT_DEVICE_SELECTOR_FLOPPY 0xF + +#define BOOT_OPTION_HANDLED_BY_BIOS 0x01 + +// +// Constant definitions for the 'BIOS Mux Control Override' field of Boot Option Parameters #5 +// +#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING 0x00 +#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC 0x01 +#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM 0x02 + +typedef union { + struct { + UINT8 Reserved:5; + UINT8 BiosBootType:1; + UINT8 PersistentOptions:1; + UINT8 BootFlagValid:1; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1; + +typedef union { + struct { + UINT8 LockReset:1; + UINT8 ScreenBlank:1; + UINT8 BootDeviceSelector:4; + UINT8 LockKeyboard:1; + UINT8 CmosClear:1; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2; + +typedef union { + struct { + UINT8 ConsoleRedirection:2; + UINT8 LockSleep:1; + UINT8 UserPasswordBypass:1; + UINT8 ForceProgressEventTrap:1; + UINT8 BiosVerbosity:2; + UINT8 LockPower:1; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3; + +typedef union { + struct { + UINT8 BiosMuxControlOverride:3; + UINT8 BiosSharedModeOverride:1; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4; + +typedef union { + struct { + UINT8 DeviceInstanceSelector:5; + UINT8 Reserved:3; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5; + +typedef struct { + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1 Data1; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2 Data2; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3 Data3; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4 Data4; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5 Data5; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5; + +typedef union { + struct { + UINT8 ChannelNumber:4; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_BOOT_OPTIONS_CHANNEL_NUMBER; + +typedef struct { + IPMI_BOOT_OPTIONS_CHANNEL_NUMBER ChannelNumber; + UINT8 SessionId[4]; + UINT8 BootInfoTimeStamp[4]; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6; + +typedef struct { + UINT8 SetSelector; + UINT8 BlockData[16]; +} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7; + +typedef union { + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0 Parm0; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1 Parm1; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2 Parm2; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3 Parm3; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4 Parm4; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 Parm5; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6 Parm6; + IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7; +} IPMI_BOOT_OPTIONS_PARAMETERS; + +typedef union { + struct { + UINT8 ParameterVersion:4; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION; + +typedef union { + struct { + UINT8 ParameterSelector:7; + UINT8 ParameterValid:1; + } Bits; + UINT8 Uint8; +} IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID; + +typedef struct { + UINT8 CompletionCode; + IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION ParameterVersion; + IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid; + UINT8 ParameterData[0]; +} IPMI_GET_BOOT_OPTIONS_RESPONSE; + +// +// Definitions for Set front panel button enables command +// +#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A + +// +// Constants and Structure definitions for "Set front panel button enables" command to follow here +// +typedef union { + struct { + UINT8 DisablePoweroffButton:1; + UINT8 DisableResetButton:1; + UINT8 DisableDiagnosticInterruptButton:1; + UINT8 DisableStandbyButton:1; + UINT8 Reserved:4; + } Bits; + UINT8 Uint8; +} IPMI_FRONT_PANEL_BUTTON_ENABLES; + +typedef struct { + IPMI_FRONT_PANEL_BUTTON_ENABLES FrontPanelButtonEnables; +} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST; + +// +// Definitions for Set Power Cycle Interval command +// +#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B + +// +// Constants and Structure definitions for "Set Power Cycle Interval" command to follow here +// + +// +// Definitions for Get POH Counter command +// +#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F + +// +// Constants and Structure definitions for "Get POH Counter" command to follow here +// +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h new file mode 100644 index 0000000000..9971559ff2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h @@ -0,0 +1,38 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_FIRMWARE_H_ +#define _IPMI_NET_FN_FIRMWARE_H_ + +// +// Net function definition for Firmware command +// +#define IPMI_NETFN_FIRMWARE 0x08 + +// +// All Firmware commands and their structure definitions to follow here +// + +// ---------------------------------------------------------------------------------------- +// Definitions for Get BMC Execution Context +// ---------------------------------------------------------------------------------------- +#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23 + +// +// Constants and Structure definitions for "Get Device ID" command to follow here +// +typedef struct { + UINT8 CurrentExecutionContext; + UINT8 PartitionPointer; +} IPMI_MSG_GET_BMC_EXEC_RSP; + +// +// Current Execution Context responses +// +#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h new file mode 100644 index 0000000000..fbadfcd7f0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h @@ -0,0 +1,20 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_ +#define _IPMI_NET_FN_GROUP_EXTENSION_H_ + +// +// Net function definition for Group Extension command +// +#define IPMI_NETFN_GROUP_EXT 0x2C + +// +// All Group Extension commands and their structure definitions to follow here +// + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h new file mode 100644 index 0000000000..dd09000492 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h @@ -0,0 +1,46 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + This file contains all NetFn Sensor/Event commands, including: + Event Commands (Chapter 29) + PEF and Alerting Commands (Chapter 30) + Sensor Device Commands (Chapter 35) + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_SENSOR_EVENT_H_ +#define _IPMI_NET_FN_SENSOR_EVENT_H_ + +#pragma pack(1) +// +// Net function definition for Sensor command +// +#define IPMI_NETFN_SENSOR_EVENT 0x04 + +// +// All Sensor commands and their structure definitions to follow here +// + +// +// Definitions for Send Platform Event Message command +// +#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE 0x02 + +typedef struct { + UINT8 GeneratorId; + UINT8 EvMRevision; + UINT8 SensorType; + UINT8 SensorNumber; + UINT8 EventDirType; + UINT8 OEMEvData1; + UINT8 OEMEvData2; + UINT8 OEMEvData3; +} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST; + +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h new file mode 100644 index 0000000000..c69df8f303 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h @@ -0,0 +1,783 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + This file contains all NetFn Storage commands, including: + FRU Inventory Commands (Chapter 34) + SDR Repository (Chapter 33) + System Event Log(SEL) Commands (Chapter 31) + SEL Record Formats (Chapter 32) + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_STORAGE_H_ +#define _IPMI_NET_FN_STORAGE_H_ + +#pragma pack(1) +// +// Net function definition for Storage command +// +#define IPMI_NETFN_STORAGE 0x0A + +// +// All Storage commands and their structure definitions to follow here +// + +// +// Below is Definitions for FRU Inventory Commands (Chapter 34) +// + +// +// Definitions for Get Fru Inventory Area Info command +// +#define IPMI_STORAGE_GET_FRU_INVENTORY_AREAINFO 0x10 + +// +// Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here +// +typedef struct { + UINT8 DeviceId; +} IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT16 InventoryAreaSize; + UINT8 AccessType; +} IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE; + +// +// Definitions for Read Fru Data command +// +#define IPMI_STORAGE_READ_FRU_DATA 0x11 + +// +// Constants and Structure definitions for "Read Fru Data" command to follow here +// +typedef struct { + UINT8 FruDeviceId; + UINT16 FruOffset; +} IPMI_FRU_COMMON_DATA; + +typedef struct { + IPMI_FRU_COMMON_DATA Data; + UINT8 Count; +} IPMI_FRU_READ_COMMAND; + +typedef struct { + UINT8 DeviceId; + UINT16 InventoryOffset; + UINT8 CountToRead; +} IPMI_READ_FRU_DATA_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 CountReturned; + UINT8 Data[0]; +} IPMI_READ_FRU_DATA_RESPONSE; + +// +// Definitions for Write Fru Data command +// +#define IPMI_STORAGE_WRITE_FRU_DATA 0x12 + +// +// Constants and Structure definitions for "Write Fru Data" command to follow here +// +typedef struct { + IPMI_FRU_COMMON_DATA Data; + UINT8 FruData[16]; +} IPMI_FRU_WRITE_COMMAND; + +typedef struct { + UINT8 DeviceId; + UINT16 InventoryOffset; + UINT8 Data[0]; +} IPMI_WRITE_FRU_DATA_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 CountWritten; +} IPMI_WRITE_FRU_DATA_RESPONSE; + +// +// Below is Definitions for SDR Repository (Chapter 33) +// + +// +// Definitions for Get SDR Repository Info command +// +#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20 + +// +// Constants and Structure definitions for "Get SDR Repository Info" command to follow here +// +typedef union { + struct { + UINT8 SdrRepAllocInfoCmd : 1; + UINT8 SdrRepReserveCmd : 1; + UINT8 PartialAddSdrCmd : 1; + UINT8 DeleteSdrRepCmd : 1; + UINT8 Reserved : 1; + UINT8 SdrRepUpdateOp : 2; + UINT8 Overflow : 1; + } Bits; + UINT8 Uint8; +} IPMI_SDR_OPERATION_SUPPORT; + +typedef struct { + UINT8 CompletionCode; + UINT8 Version; + UINT16 RecordCount; + UINT16 FreeSpace; + UINT32 RecentAdditionTimeStamp; + UINT32 RecentEraseTimeStamp; + IPMI_SDR_OPERATION_SUPPORT OperationSupport; +} IPMI_GET_SDR_REPOSITORY_INFO_RESPONSE; + +// +// Definitions for Get SDR Repository Allocateion Info command +// +#define IPMI_STORAGE_GET_SDR_REPOSITORY_ALLOCATION_INFO 0x21 + +// +// Constants and Structure definitions for "Get SDR Repository Allocateion Info" command to follow here +// + +// +// Definitions for Reserve SDR Repository command +// +#define IPMI_STORAGE_RESERVE_SDR_REPOSITORY 0x22 + +// +// Constants and Structure definitions for "Reserve SDR Repository" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT8 ReservationId[2]; // Reservation ID. LS byte first. +} IPMI_RESERVE_SDR_REPOSITORY_RESPONSE; + +// +// Definitions for Get SDR command +// +#define IPMI_STORAGE_GET_SDR 0x23 + +// +// Constants and Structure definitions for "Get SDR" command to follow here +// +typedef union { + struct { + UINT8 EventScanningEnabled : 1; + UINT8 EventScanningDisabled : 1; + UINT8 InitSensorType : 1; + UINT8 InitHysteresis : 1; + UINT8 InitThresholds : 1; + UINT8 InitEvent : 1; + UINT8 InitScanning : 1; + UINT8 SettableSensor : 1; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_SENSOR_INIT; + +typedef union { + struct { + UINT8 EventMessageControl : 2; + UINT8 ThresholdAccessSupport : 2; + UINT8 HysteresisSupport : 2; + UINT8 ReArmSupport : 1; + UINT8 IgnoreSensor : 1; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_SENSOR_CAP; + +typedef union { + struct { + UINT8 Linearization : 7; + UINT8 Reserved : 1; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_LINEARIZATION; + +typedef union { + struct { + UINT8 Toleremce : 6; + UINT8 MHi : 2; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_M_TOLERANCE; + +typedef union { + struct { + UINT8 AccuracyLow : 6; + UINT8 BHi : 2; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_B_ACCURACY; + +typedef union { + struct { + UINT8 Reserved : 2; + UINT8 AccuracyExp : 2; + UINT8 AccuracyHi : 4; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR; + +typedef union { + struct { + UINT8 BExp : 4; + UINT8 RExp : 4; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_R_EXP_B_EXP; + +typedef union { + struct { + UINT8 NominalReadingSpscified : 1; + UINT8 NominalMaxSpscified : 1; + UINT8 NominalMinSpscified : 1; + UINT8 Reserved : 5; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_ANALOG_FLAGS; + +typedef struct { + UINT16 RecordId; // 1 + UINT8 Version; // 3 + UINT8 RecordType; // 4 + UINT8 RecordLength; // 5 + UINT8 OwnerId; // 6 + UINT8 OwnerLun; // 7 + UINT8 SensorNumber; // 8 + UINT8 EntityId; // 9 + UINT8 EntityInstance; // 10 + IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11 + IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12 + UINT8 SensorType; // 13 + UINT8 EventType; // 14 + UINT8 Reserved1[7]; // 15 + UINT8 UnitType; // 22 + UINT8 Reserved2; // 23 + IPMI_SDR_RECORD_LINEARIZATION Linearization; // 24 + UINT8 MLo; // 25 + IPMI_SDR_RECORD_M_TOLERANCE MHiTolerance; // 26 + UINT8 BLo; // 27 + IPMI_SDR_RECORD_B_ACCURACY BHiAccuracyLo; // 28 + IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR AccuracySensorDirection; // 29 + IPMI_SDR_RECORD_R_EXP_B_EXP RExpBExp; // 30 + IPMI_SDR_RECORD_ANALOG_FLAGS AnalogFlags; // 31 + UINT8 NominalReading; // 32 + UINT8 Reserved3[4]; // 33 + UINT8 UpperNonRecoverThreshold; // 37 + UINT8 UpperCriticalThreshold; // 38 + UINT8 UpperNonCriticalThreshold; // 39 + UINT8 LowerNonRecoverThreshold; // 40 + UINT8 LowerCriticalThreshold; // 41 + UINT8 LowerNonCriticalThreshold; // 42 + UINT8 Reserved4[5]; // 43 + UINT8 IdStringLength; // 48 + UINT8 AsciiIdString[16]; // 49 - 64 +} IPMI_SDR_RECORD_STRUCT_1; + +typedef struct { + UINT16 RecordId; // 1 + UINT8 Version; // 3 + UINT8 RecordType; // 4 + UINT8 RecordLength; // 5 + UINT8 OwnerId; // 6 + UINT8 OwnerLun; // 7 + UINT8 SensorNumber; // 8 + UINT8 EntityId; // 9 + UINT8 EntityInstance; // 10 + IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11 + IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12 + UINT8 SensorType; // 13 + UINT8 EventType; // 14 + UINT8 Reserved1[7]; // 15 + UINT8 UnitType; // 22 + UINT8 Reserved2[9]; // 23 + UINT8 IdStringLength; // 32 + UINT8 AsciiIdString[16]; // 33 - 48 +} IPMI_SDR_RECORD_STRUCT_2; + +typedef union { + struct { + UINT8 Reserved1 : 1; + UINT8 ControllerSlaveAddress : 7; + UINT8 FruDeviceId; + UINT8 BusId : 3; + UINT8 Lun : 2; + UINT8 Reserved2 : 2; + UINT8 LogicalFruDevice : 1; + UINT8 Reserved3 : 4; + UINT8 ChannelNumber : 4; + } Bits; + UINT32 Uint32; +} IPMI_FRU_DATA_INFO; + +typedef union { + struct { + UINT8 Length : 4; + UINT8 Reserved : 1; + UINT8 StringType : 3; + } Bits; + UINT8 Uint8; +} IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH; + +typedef struct { + UINT16 RecordId; // 1 + UINT8 Version; // 3 + UINT8 RecordType; // 4 + UINT8 RecordLength; // 5 + IPMI_FRU_DATA_INFO FruDeviceData; // 6 + UINT8 Reserved; // 10 + UINT8 DeviceType; // 11 + UINT8 DeviceTypeModifier; // 12 + UINT8 FruEntityId; // 13 + UINT8 FruEntityInstance; // 14 + UINT8 OemReserved; // 15 + IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH StringTypeLength; // 16 + UINT8 String[16]; // 17 +} IPMI_SDR_RECORD_STRUCT_11; + +typedef struct { + UINT16 RecordId; //1 + UINT8 Version; //3 + UINT8 RecordType; //4 + UINT8 RecordLength; //5 + UINT8 ManufacturerId[3]; //6 + UINT8 StringChars[20]; +} IPMI_SDR_RECORD_STRUCT_C0; + +typedef struct { + UINT16 RecordId; //1 + UINT8 Version; //3 + UINT8 RecordType; //4 + UINT8 RecordLength; //5 +} IPMI_SDR_RECORD_STRUCT_HEADER; + +typedef union { + IPMI_SDR_RECORD_STRUCT_1 SensorType1; + IPMI_SDR_RECORD_STRUCT_2 SensorType2; + IPMI_SDR_RECORD_STRUCT_11 SensorType11; + IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0; + IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader; +} IPMI_SENSOR_RECORD_STRUCT; + +typedef struct { + UINT16 ReservationId; + UINT16 RecordId; + UINT8 RecordOffset; + UINT8 BytesToRead; +} IPMI_GET_SDR_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT16 NextRecordId; + IPMI_SENSOR_RECORD_STRUCT RecordData; +} IPMI_GET_SDR_RESPONSE; + +// +// Definitions for Add SDR command +// +#define IPMI_STORAGE_ADD_SDR 0x24 + +// +// Constants and Structure definitions for "Add SDR" command to follow here +// + +// +// Definitions for Partial Add SDR command +// +#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25 + +// +// Constants and Structure definitions for "Partial Add SDR" command to follow here +// + +// +// Definitions for Delete SDR command +// +#define IPMI_STORAGE_DELETE_SDR 0x26 + +// +// Constants and Structure definitions for "Delete SDR" command to follow here +// + +// +// Definitions for Clear SDR Repository command +// +#define IPMI_STORAGE_CLEAR_SDR 0x27 + +// +// Constants and Structure definitions for "Clear SDR Repository" command to follow here +// + +// +// Definitions for Get SDR Repository Time command +// +#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28 + +// +// Constants and Structure definitions for "Get SDR Repository Time" command to follow here +// + +// +// Definitions for Set SDR Repository Time command +// +#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29 + +// +// Constants and Structure definitions for "Set SDR Repository Time" command to follow here +// + +// +// Definitions for Enter SDR Repository Update Mode command +// +#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A + +// +// Constants and Structure definitions for "Enter SDR Repository Update Mode" command to follow here +// + +// +// Definitions for Exit SDR Repository Update Mode command +// +#define IPMI_STORAGE_EXIT_SDR_UPDATE_MODE 0x2B + +// +// Constants and Structure definitions for "Exit SDR Repository Update Mode" command to follow here +// + +// +// Definitions for Run Initialize Agent command +// +#define IPMI_STORAGE_RUN_INIT_AGENT 0x2C + +// +// Constants and Structure definitions for "Run Initialize Agent" command to follow here +// + +// +// Below is Definitions for System Event Log(SEL) Commands (Chapter 31) +// + +// +// Definitions for Get SEL Info command +// +#define IPMI_STORAGE_GET_SEL_INFO 0x40 + +// +// Constants and Structure definitions for "Get SEL Info" command to follow here +// +#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD BIT0 +#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD BIT1 +#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD BIT2 +#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD BIT3 +#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG BIT7 + +typedef struct { + UINT8 CompletionCode; + UINT8 Version; // Version of SEL + UINT16 NoOfEntries; // No of Entries in the SEL + UINT16 FreeSpace; // Free space in Bytes + UINT32 RecentAddTimeStamp; // Most Recent Addition of Time Stamp + UINT32 RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp + UINT8 OperationSupport; // Operation Support +} IPMI_GET_SEL_INFO_RESPONSE; + +// +// Definitions for Get SEL Allocation Info command +// +#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41 + +// +// Constants and Structure definitions for "Get SEL Allocation Info" command to follow here +// + +// +// Definitions for Reserve SEL command +// +#define IPMI_STORAGE_RESERVE_SEL 0x42 + +// +// Constants and Structure definitions for "Reserve SEL" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT8 ReservationId[2]; // Reservation ID. LS byte first. +} IPMI_RESERVE_SEL_RESPONSE; + +// +// Definitions for Get SEL Entry command +// +#define IPMI_STORAGE_GET_SEL_ENTRY 0x43 + +// +// Constants and Structure definitions for "Get SEL Entry" command to follow here +// + +// +// Below is Definitions for SEL Record Formats (Chapter 32) +// +typedef struct { + UINT16 RecordId; + UINT8 RecordType; + UINT32 TimeStamp; + UINT16 GeneratorId; + UINT8 EvMRevision; + UINT8 SensorType; + UINT8 SensorNumber; + UINT8 EventDirType; + UINT8 OEMEvData1; + UINT8 OEMEvData2; + UINT8 OEMEvData3; +} IPMI_SEL_EVENT_RECORD_DATA; + +typedef struct { + UINT16 RecordId; + UINT8 RecordType; // C0h-DFh = OEM system event record + UINT32 TimeStamp; + UINT8 ManufacturerId[3]; + UINT8 OEMDefined[6]; +} IPMI_TIMESTAMPED_OEM_SEL_RECORD_DATA; + +typedef struct { + UINT16 RecordId; + UINT8 RecordType; // E0h-FFh = OEM system event record + UINT8 OEMDefined[13]; +} IPMI_NON_TIMESTAMPED_OEM_SEL_RECORD_DATA; + +typedef struct { + UINT8 ReserveId[2]; // Reservation ID, LS Byte First + UINT8 SelRecID[2]; // Sel Record ID, LS Byte First + UINT8 Offset; // Offset Into Record + UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record +} IPMI_GET_SEL_ENTRY_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT16 NextSelRecordId; // Next SEL Record ID, LS Byte first + IPMI_SEL_EVENT_RECORD_DATA RecordData; +} IPMI_GET_SEL_ENTRY_RESPONSE; + +// +// Definitions for Add SEL Entry command +// +#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44 + +// +// Constants and Structure definitions for "Add SEL Entry" command to follow here +// +typedef struct { + IPMI_SEL_EVENT_RECORD_DATA RecordData; +} IPMI_ADD_SEL_ENTRY_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT16 RecordId; // Record ID for added record, LS Byte first +} IPMI_ADD_SEL_ENTRY_RESPONSE; + +// +// Definitions for Partial Add SEL Entry command +// +#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45 + +// +// Constants and Structure definitions for "Partial Add SEL Entry" command to follow here +// +typedef struct { + UINT16 ReservationId; + UINT16 RecordId; + UINT8 OffsetIntoRecord; + UINT8 InProgress; + UINT8 RecordData[0]; +} IPMI_PARTIAL_ADD_SEL_ENTRY_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT16 RecordId; +} IPMI_PARTIAL_ADD_SEL_ENTRY_RESPONSE; + +// +// Definitions for Delete SEL Entry command +// +#define IPMI_STORAGE_DELETE_SEL_ENTRY 0x46 + +// +// Constants and Structure definitions for "Delete SEL Entry" command to follow here +// +typedef struct { + UINT8 ReserveId[2]; // Reservation ID, LS byte first + UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First +} IPMI_DELETE_SEL_ENTRY_REQUEST; + +#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED 0x80 +#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS 0x81 + +typedef struct { + UINT8 CompletionCode; + UINT16 RecordId; // Record ID added. LS byte first +} IPMI_DELETE_SEL_ENTRY_RESPONSE; + +// +// Definitions for Clear SEL command +// +#define IPMI_STORAGE_CLEAR_SEL 0x47 + +// +// Constants and Structure definitions for "Clear SEL" command to follow here +// +#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII 0x43 +#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII 0x4C +#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII 0x52 +#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE 0xAA +#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS 0x00 + +typedef struct { + UINT8 Reserve[2]; // Reserve ID, LSB first + UINT8 AscC; // Ascii for 'C' (0x43) + UINT8 AscL; // Ascii for 'L' (0x4c) + UINT8 AscR; // Ascii for 'R' (0x52) + UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status +} IPMI_CLEAR_SEL_REQUEST; + +#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS 0x00 +#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED 0x01 + +typedef struct { + UINT8 CompletionCode; + UINT8 ErasureProgress; +} IPMI_CLEAR_SEL_RESPONSE; + +// +// Definitions for Get SEL Time command +// +#define IPMI_STORAGE_GET_SEL_TIME 0x48 + +// +// Constants and Structure definitions for "Get SEL Time" command to follow here +// +typedef struct { + UINT8 CompletionCode; + UINT32 Timestamp; // Present Timestamp clock reading. LS byte first. +} IPMI_GET_SEL_TIME_RESPONSE; + +// +// Definitions for Set SEL Time command +// +#define IPMI_STORAGE_SET_SEL_TIME 0x49 + +// +// Constants and Structure definitions for "Set SEL Time" command to follow here +// +typedef struct { + UINT32 Timestamp; +} IPMI_SET_SEL_TIME_REQUEST; + +// +// Definitions for Get Auxillary Log Status command +// +#define IPMI_STORAGE_GET_AUXILLARY_LOG_STATUS 0x5A + +// +// Constants and Structure definitions for "Get Auxillary Log Status" command to follow here +// + +// +// Definitions for Set Auxillary Log Status command +// +#define IPMI_STORAGE_SET_AUXILLARY_LOG_STATUS 0x5B + +// +// Constants and Structure definitions for "Set Auxillary Log Status" command to follow here +// + +// +// Definitions for Get SEL Time UTC Offset command +// +#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET 0x5C + +// +// Constants and Structure definitions for "Get SEL Time UTC Offset" command to follow here +// +typedef struct { + UINT8 CompletionCode; + // + // 16-bit, 2s-complement signed integer for the offset in minutes from UTC to SEL Time. + // LS-byte first. (ranges from -1440 to 1440) + // + INT16 UtcOffset; +} IPMI_GET_SEL_TIME_UTC_OFFSET_RESPONSE; + +// +// Definitions for Set SEL Time UTC Offset command +// +#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET 0x5D + +// +// Constants and Structure definitions for "Set SEL Time UTC Offset" command to follow here +// + +#define IPMI_COMPLETE_SEL_RECORD 0xFF + +#define IPMI_SEL_SYSTEM_RECORD 0x02 +#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START 0xC0 +#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END 0xDF +#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START 0xE0 +#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END 0xFF + +#define IPMI_SEL_EVENT_DIR(EventDirType) (EventDirType >> 7) +#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT 0x00 +#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT 0x01 + +#define IPMI_SEL_EVENT_TYPE(EventDirType) (EventDirType & 0x7F) +// +// Event/Reading Type Code Ranges (Chapter 42) +// +#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED 0x00 +#define IPMI_SEL_EVENT_TYPE_THRESHOLD 0x01 +#define IPMI_SEL_EVENT_TYPE_GENERIC_START 0x02 +#define IPMI_SEL_EVENT_TYPE_GENERIC_END 0x0C +#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC 0x6F +#define IPMI_SEL_EVENT_TYPE_OEM_START 0x70 +#define IPMI_SEL_EVENT_TYPE_OEM_END 0x7F + +#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1) +// +// System Software IDs definitions (Section 5.5) +// +#define IPMI_SWID_BIOS_RANGE_START 0x00 +#define IPMI_SWID_BIOS_RANGE_END 0x0F +#define IPMI_SWID_SMI_HANDLER_RANGE_START 0x10 +#define IPMI_SWID_SMI_HANDLER_RANGE_END 0x1F +#define IPMI_SWID_SMS_RANGE_START 0x20 +#define IPMI_SWID_SMS_RANGE_END 0x2F +#define IPMI_SWID_OEM_RANGE_START 0x30 +#define IPMI_SWID_OEM_RANGE_END 0x3F +#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START 0x40 +#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END 0x46 +#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID 0x47 + +#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1) +#define LUN_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 8) & 0x03) +#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 12) & 0x0F) + +#define IPMI_EVM_REVISION 0x04 +#define IPMI_BIOS_ID 0x18 +#define IPMI_FORMAT_REV 0x00 +#define IPMI_FORMAT_REV1 0x01 +#define IPMI_SOFTWARE_ID 0x01 +#define IPMI_PLATFORM_VAL_ID 0x01 +#define IPMI_GENERATOR_ID(i,f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID) + +#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F + +#define IPMI_OEM_SPECIFIC_DATA 0x02 +#define IPMI_SENSOR_SPECIFIC_DATA 0x03 + +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h new file mode 100644 index 0000000000..6ede54cbea --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h @@ -0,0 +1,885 @@ +/** @file + IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1. + + This file contains all NetFn Transport commands, including: + IPM LAN Commands (Chapter 23) + IPMI Serial/Modem Commands (Chapter 25) + SOL Commands (Chapter 26) + Command Forwarding Commands (Chapter 35b) + + See IPMI specification, Appendix G, Command Assignments + and Appendix H, Sub-function Assignments. + + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPMI_NET_FN_TRANSPORT_H_ +#define _IPMI_NET_FN_TRANSPORT_H_ + +#pragma pack(1) +// +// Net function definition for Transport command +// +#define IPMI_NETFN_TRANSPORT 0x0C + +// +// Below is Definitions for IPM LAN Commands (Chapter 23) +// + +// +// Definitions for Set Lan Configuration Parameters command +// +#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01 + +// +// Constants and Structure definitions for "Set Lan Configuration Parameters" command to follow here +// + +// +// LAN Management Structure +// +typedef enum { + IpmiLanReserved1, + IpmiLanReserved2, + IpmiLanAuthType, + IpmiLanIpAddress, + IpmiLanIpAddressSource, + IpmiLanMacAddress, + IpmiLanSubnetMask, + IpmiLanIpv4HeaderParam, + IpmiLanPrimaryRcmpPort, + IpmiLanSecondaryRcmpPort, + IpmiLanBmcGeneratedArpCtrl, + IpmiLanArpInterval, + IpmiLanDefaultGateway, + IpmiLanDefaultGatewayMac, + IpmiLanBackupGateway, + IpmiLanBackupGatewayMac, + IpmiLanCommunityString, + IpmiLanReserved3, + IpmiLanDestinationType, + IpmiLanDestinationAddress, + IpmiIpv4OrIpv6Support = 0x32, + IpmiIpv4OrIpv6AddressEnable, + IpmiIpv6HdrStatTrafficClass, + IpmiIpv6HdrStatHopLimit, + IpmiIpv6HdrFlowLabel, + IpmiIpv6Status, + IpmiIpv6StaticAddress, + IpmiIpv6DhcpStaticDuidLen, + IpmiIpv6DhcpStaticDuid, + IpmiIpv6DhcpAddress, + IpmiIpv6DhcpDynamicDuidLen, + IpmiIpv6DhcpDynamicDuid, + IpmiIpv6RouterConfig = 0x40, + IpmiIpv6StaticRouter1IpAddr, + IpmiIpv6DynamicRouterIpAddr = 0x4a +} IPMI_LAN_OPTION_TYPE; + +// +// IP Address Source +// +typedef enum { + IpmiUnspecified, + IpmiStaticAddrsss, + IpmiDynamicAddressBmcDhcp, + IpmiDynamicAddressBiosDhcp, + IpmiDynamicAddressBmcNonDhcp +} IPMI_IP_ADDRESS_SRC; + +// +// Destination Type +// +typedef enum { + IpmiPetTrapDestination, + IpmiDirectedEventDestination, + IpmiReserved1, + IpmiReserved2, + IpmiReserved3, + IpmiReserved4, + IpmiReserved5, + IpmiOem1, + IpmiOem2 +} IPMI_LAN_DEST_TYPE_DEST_TYPE; + +typedef union { + struct { + UINT8 NoAuth : 1; + UINT8 MD2Auth : 1; + UINT8 MD5Auth : 1; + UINT8 Reserved1 : 1; + UINT8 StraightPswd : 1; + UINT8 OemType : 1; + UINT8 Reserved2 : 2; + } Bits; + UINT8 Uint8; +} IPMI_LAN_AUTH_TYPE; + +typedef struct { + UINT8 IpAddress[4]; +} IPMI_LAN_IP_ADDRESS; + +typedef union { + struct { + UINT8 AddressSrc : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_LAN_IP_ADDRESS_SRC; + +typedef struct { + UINT8 MacAddress[6]; +} IPMI_LAN_MAC_ADDRESS; + +typedef struct { + UINT8 IpAddress[4]; +} IPMI_LAN_SUBNET_MASK; + +typedef union { + struct { + UINT8 IpFlag : 3; + UINT8 Reserved : 5; + } Bits; + UINT8 Uint8; +} IPMI_LAN_IPV4_HDR_PARAM_DATA_2; + +typedef union { + struct { + UINT8 Precedence : 3; + UINT8 Reserved : 1; + UINT8 ServiceType : 4; + } Bits; + UINT8 Uint8; +} IPMI_LAN_IPV4_HDR_PARAM_DATA_3; + +typedef struct { + UINT8 TimeToLive; + IPMI_LAN_IPV4_HDR_PARAM_DATA_2 Data2; + IPMI_LAN_IPV4_HDR_PARAM_DATA_3 Data3; +} IPMI_LAN_IPV4_HDR_PARAM; + +typedef struct { + UINT8 RcmpPortMsb; + UINT8 RcmpPortLsb; +} IPMI_LAN_RCMP_PORT; + +typedef union { + struct { + UINT8 EnableBmcArpResponse : 1; + UINT8 EnableBmcGratuitousArp : 1; + UINT8 Reserved : 6; + } Bits; + UINT8 Uint8; +} IPMI_LAN_BMC_GENERATED_ARP_CONTROL; + +typedef struct { + UINT8 ArpInterval; +} IPMI_LAN_ARP_INTERVAL; + +typedef struct { + UINT8 Data[18]; +} IPMI_LAN_COMMUNITY_STRING; + +typedef union { + struct { + UINT8 DestinationSelector : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_LAN_SET_SELECTOR; + +typedef union { + struct { + UINT8 DestinationType : 3; + UINT8 Reserved : 4; + UINT8 AlertAcknowledged : 1; + } Bits; + UINT8 Uint8; +} IPMI_LAN_DEST_TYPE_DESTINATION_TYPE; + +typedef struct { + IPMI_LAN_SET_SELECTOR SetSelector; + IPMI_LAN_DEST_TYPE_DESTINATION_TYPE DestinationType; +} IPMI_LAN_DEST_TYPE; + +typedef union { + struct { + UINT8 AlertingIpAddressSelector : 4; + UINT8 AddressFormat : 4; + } Bits; + UINT8 Uint8; +} IPMI_LAN_ADDRESS_FORMAT; + +typedef union { + struct { + UINT8 UseDefaultGateway : 1; + UINT8 Reserved2 : 7; + } Bits; + UINT8 Uint8; +} IPMI_LAN_GATEWAY_SELECTOR; + +typedef struct { + IPMI_LAN_SET_SELECTOR SetSelector; + IPMI_LAN_ADDRESS_FORMAT AddressFormat; + IPMI_LAN_GATEWAY_SELECTOR GatewaySelector; + IPMI_LAN_IP_ADDRESS AlertingIpAddress; + IPMI_LAN_MAC_ADDRESS AlertingMacAddress; +} IPMI_LAN_DEST_ADDRESS; + +typedef union { + IPMI_LAN_AUTH_TYPE IpmiLanAuthType; + IPMI_LAN_IP_ADDRESS IpmiLanIpAddress; + IPMI_LAN_IP_ADDRESS_SRC IpmiLanIpAddressSrc; + IPMI_LAN_MAC_ADDRESS IpmiLanMacAddress; + IPMI_LAN_SUBNET_MASK IpmiLanSubnetMask; + IPMI_LAN_IPV4_HDR_PARAM IpmiLanIpv4HdrParam; + IPMI_LAN_RCMP_PORT IpmiLanPrimaryRcmpPort; + IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl; + IPMI_LAN_ARP_INTERVAL IpmiLanArpInterval; + IPMI_LAN_COMMUNITY_STRING IpmiLanCommunityString; + IPMI_LAN_DEST_TYPE IpmiLanDestType; + IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress; +} IPMI_LAN_OPTIONS; + +typedef union { + struct { + UINT8 AddressSourceType : 4; + UINT8 Reserved : 3; + UINT8 EnableStatus : 1; + } Bits; + UINT8 Uint8; +} IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE; + +typedef struct { + UINT8 SetSelector; + IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE AddressSourceType; + UINT8 Ipv6Address[16]; + UINT8 AddressPrefixLen; + UINT8 AddressStatus; +} IPMI_LAN_IPV6_STATIC_ADDRESS; + +// +// Set in progress parameter +// +typedef union { + struct { + UINT8 SetInProgress:2; + UINT8 Reserved:6; + } Bits; + UINT8 Uint8; +} IPMI_LAN_SET_IN_PROGRESS; + +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_SET_LAN_CONFIG_CHANNEL_NUM; + +typedef struct { + IPMI_SET_LAN_CONFIG_CHANNEL_NUM ChannelNumber; + UINT8 ParameterSelector; + UINT8 ParameterData[0]; +} IPMI_SET_LAN_CONFIGURATION_PARAMETERS_COMMAND_REQUEST; + +// +// Definitions for Get Lan Configuration Parameters command +// +#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02 + +// +// Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here +// +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 3; + UINT8 GetParameter : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_LAN_CONFIG_CHANNEL_NUM; + +typedef struct { + IPMI_GET_LAN_CONFIG_CHANNEL_NUM ChannelNumber; + UINT8 ParameterSelector; + UINT8 SetSelector; + UINT8 BlockSelector; +} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 ParameterRevision; + UINT8 ParameterData[0]; +} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_RESPONSE; + +// +// Definitions for Suspend BMC ARPs command +// +#define IPMI_TRANSPORT_SUSPEND_BMC_ARPS 0x03 + +// +// Constants and Structure definitions for "Suspend BMC ARPs" command to follow here +// + +// +// Definitions for Get IP-UDP-RMCP Statistics command +// +#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04 + +// +// Constants and Structure definitions for "Get IP-UDP-RMCP Statistics" command to follow here +// + +// +// Below is Definitions for IPMI Serial/Modem Commands (Chapter 25) +// + +// +// Definitions for Set Serial/Modem Configuration command +// +#define IPMI_TRANSPORT_SET_SERIAL_CONFIGURATION 0x10 + +// +// Constants and Structure definitions for "Set Serial/Modem Configuration" command to follow here +// + +// +// EMP OPTION DATA +// +typedef union { + struct { + UINT8 NoAuthentication : 1; + UINT8 MD2Authentication : 1; + UINT8 MD5Authentication : 1; + UINT8 Reserved1 : 1; + UINT8 StraightPassword : 1; + UINT8 OemProprietary : 1; + UINT8 Reservd2 : 2; + } Bits; + UINT8 Uint8; +} IPMI_EMP_AUTH_TYPE; + +typedef union { + struct { + UINT8 EnableBasicMode : 1; + UINT8 EnablePPPMode : 1; + UINT8 EnableTerminalMode : 1; + UINT8 Reserved1 : 2; + UINT8 SnoopOsPPPNegotiation : 1; + UINT8 Reserved2 : 1; + UINT8 DirectConnect : 1; + } Bits; + UINT8 Uint8; +} IPMI_EMP_CONNECTION_TYPE; + +typedef union { + struct { + UINT8 InactivityTimeout : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_EMP_INACTIVITY_TIMEOUT; + +typedef union { + struct { + UINT8 IpmiCallback : 1; + UINT8 CBCPCallback : 1; + UINT8 Reserved : 6; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE; + +typedef union { + struct { + UINT8 CbcpEnableNoCallback : 1; + UINT8 CbcpEnablePreSpecifiedNumber : 1; + UINT8 CbcpEnableUserSpecifiedNumber : 1; + UINT8 CbcpEnableCallbackFromList : 1; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_CHANNEL_CALLBACK_CONTROL_CBCP; + +typedef struct { + IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE CallbackEnable; + IPMI_CHANNEL_CALLBACK_CONTROL_CBCP CBCPNegotiation; + UINT8 CallbackDestination1; + UINT8 CallbackDestination2; + UINT8 CallbackDestination3; +} IPMI_EMP_CHANNEL_CALLBACK_CONTROL; + +typedef union { + struct { + UINT8 CloseSessionOnDCDLoss : 1; + UINT8 EnableSessionInactivityTimeout : 1; + UINT8 Reserved : 6; + } Bits; + UINT8 Uint8; +} IPMI_EMP_SESSION_TERMINATION; + +typedef union { + struct { + UINT8 Reserved1 : 5; + UINT8 EnableDtrHangup : 1; + UINT8 FlowControl : 2; + UINT8 BitRate : 4; + UINT8 Reserved2 : 4; + UINT8 SaveSetting : 1; + UINT8 SetComPort : 1; + UINT8 Reserved3 : 6; + } Bits; + UINT8 Uint8; + UINT16 Uint16; +} IPMI_EMP_MESSAGING_COM_SETTING; + +typedef union { + struct { + UINT8 RingDurationInterval : 6; + UINT8 Reserved1 : 2; + UINT8 RingDeadTime : 4; + UINT8 Reserved2 : 4; + } Bits; + UINT8 Uint8; +} IPMI_EMP_MODEM_RING_TIME; + +typedef struct { + UINT8 Reserved; + UINT8 InitString[48]; +} IPMI_EMP_MODEM_INIT_STRING; + +typedef struct { + UINT8 EscapeSequence[5]; +} IPMI_EMP_MODEM_ESC_SEQUENCE; + +typedef struct { + UINT8 HangupSequence[8]; +} IPMI_EMP_MODEM_HANGUP_SEQUENCE; + +typedef struct { + UINT8 ModelDialCommend[8]; +} IPMI_MODEM_DIALUP_COMMAND; + +typedef struct { + UINT8 PageBlackoutInterval; +} IPMI_PAGE_BLACKOUT_INTERVAL; + +typedef struct { + UINT8 CommunityString[18]; +} IPMI_EMP_COMMUNITY_STRING; + +typedef union { + struct { + UINT8 Reserved : 4; + UINT8 DialStringSelector : 4; + } Bits; + UINT8 Uint8; +} IPMI_DIAL_PAGE_DESTINATION; + +typedef union { + struct { + UINT8 TapAccountSelector : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_TAP_PAGE_DESTINATION; + +typedef struct { + UINT8 PPPAccountSetSelector; + UINT8 DialStringSelector; +} IPMI_PPP_ALERT_DESTINATION; + +typedef union { + IPMI_DIAL_PAGE_DESTINATION DialPageDestination; + IPMI_TAP_PAGE_DESTINATION TapPageDestination; + IPMI_PPP_ALERT_DESTINATION PppAlertDestination; +} IPMI_DEST_TYPE_SPECIFIC; + +typedef union { + struct { + UINT8 DestinationSelector : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_EMP_DESTINATION_SELECTOR; + +typedef union { + struct { + UINT8 DestinationType : 4; + UINT8 Reserved : 3; + UINT8 AlertAckRequired : 1; + } Bits; + UINT8 Uint8; +} IPMI_EMP_DESTINATION_TYPE; + +typedef union { + struct { + UINT8 NumRetriesCall : 3; + UINT8 Reserved1 : 1; + UINT8 NumRetryAlert : 3; + UINT8 Reserved2 : 1; + } Bits; + UINT8 Uint8; +} IPMI_EMP_RETRIES; + +typedef struct { + IPMI_EMP_DESTINATION_SELECTOR DestinationSelector; + IPMI_EMP_DESTINATION_TYPE DestinationType; + UINT8 AlertAckTimeoutSeconds; + IPMI_EMP_RETRIES Retries; + IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific; +} IPMI_EMP_DESTINATION_INFO; + +typedef union { + struct { + UINT8 Parity : 3; + UINT8 CharacterSize : 1; + UINT8 StopBit : 1; + UINT8 DtrHangup : 1; + UINT8 FlowControl : 2; + } Bits; + UINT8 Uint8; +} IPMI_EMP_DESTINATION_COM_SETTING_DATA_2; + +typedef union { + struct { + UINT8 BitRate : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_EMP_BIT_RATE; + +typedef struct { + IPMI_EMP_DESTINATION_SELECTOR DestinationSelector; + IPMI_EMP_DESTINATION_COM_SETTING_DATA_2 Data2; + IPMI_EMP_BIT_RATE BitRate; +} IPMI_EMP_DESTINATION_COM_SETTING; + +typedef union { + struct { + UINT8 DialStringSelector : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_DIAL_STRING_SELECTOR; + +typedef struct { + IPMI_DIAL_STRING_SELECTOR DestinationSelector; + UINT8 Reserved; + UINT8 DialString[48]; +} IPMI_DESTINATION_DIAL_STRING; + +typedef union { + UINT32 IpAddressLong; + UINT8 IpAddress[4]; +} IPMI_PPP_IP_ADDRESS; + +typedef union { + struct { + UINT8 IpAddressSelector : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_DESTINATION_IP_ADDRESS_SELECTOR; + +typedef struct { + IPMI_DESTINATION_IP_ADDRESS_SELECTOR DestinationSelector; + IPMI_PPP_IP_ADDRESS PppIpAddress; +} IPMI_DESTINATION_IP_ADDRESS; + +typedef union { + struct { + UINT8 TapServiceSelector : 4; + UINT8 TapDialStringSelector : 4; + } Bits; + UINT8 Uint8; +} IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR; + + +typedef struct { + UINT8 TapSelector; + IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR TapDialStringServiceSelector; +} IPMI_DESTINATION_TAP_ACCOUNT; + +typedef struct { + UINT8 TapSelector; + UINT8 PagerIdString[16]; +} IPMI_TAP_PAGER_ID_STRING; + +typedef union { + UINT8 OptionData; + IPMI_EMP_AUTH_TYPE EmpAuthType; + IPMI_EMP_CONNECTION_TYPE EmpConnectionType; + IPMI_EMP_INACTIVITY_TIMEOUT EmpInactivityTimeout; + IPMI_EMP_CHANNEL_CALLBACK_CONTROL EmpCallbackControl; + IPMI_EMP_SESSION_TERMINATION EmpSessionTermination; + IPMI_EMP_MESSAGING_COM_SETTING EmpMessagingComSetting; + IPMI_EMP_MODEM_RING_TIME EmpModemRingTime; + IPMI_EMP_MODEM_INIT_STRING EmpModemInitString; + IPMI_EMP_MODEM_ESC_SEQUENCE EmpModemEscSequence; + IPMI_EMP_MODEM_HANGUP_SEQUENCE EmpModemHangupSequence; + IPMI_MODEM_DIALUP_COMMAND EmpModemDialupCommand; + IPMI_PAGE_BLACKOUT_INTERVAL EmpPageBlackoutInterval; + IPMI_EMP_COMMUNITY_STRING EmpCommunityString; + IPMI_EMP_DESTINATION_INFO EmpDestinationInfo; + IPMI_EMP_DESTINATION_COM_SETTING EmpDestinationComSetting; + UINT8 CallRetryBusySignalInterval; + IPMI_DESTINATION_DIAL_STRING DestinationDialString; + IPMI_DESTINATION_IP_ADDRESS DestinationIpAddress; + IPMI_DESTINATION_TAP_ACCOUNT DestinationTapAccount; + IPMI_TAP_PAGER_ID_STRING TapPagerIdString; +} IPMI_EMP_OPTIONS; + +// +// Definitions for Get Serial/Modem Configuration command +// +#define IPMI_TRANSPORT_GET_SERIAL_CONFIGURATION 0x11 + +// +// Constants and Structure definitions for "Get Serial/Modem Configuration" command to follow here +// + +// +// Definitions for Set Serial/Modem Mux command +// +#define IPMI_TRANSPORT_SET_SERIAL_MUX 0x12 + +// +// Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here +// + +// +// Set Serial/Modem Mux command request return status +// +#define IPMI_MUX_SETTING_REQUEST_REJECTED 0x00 +#define IPMI_MUX_SETTING_REQUEST_ACCEPTED 0x01 + +// +// Definitions for serial multiplex settings +// +#define IPMI_MUX_SETTING_GET_MUX_SETTING 0x0 +#define IPMI_MUX_SETTING_REQUEST_MUX_TO_SYSTEM 0x1 +#define IPMI_MUX_SETTING_REQUEST_MUX_TO_BMC 0x2 +#define IPMI_MUX_SETTING_FORCE_MUX_TO_SYSTEM 0x3 +#define IPMI_MUX_SETTING_FORCE_MUX_TO_BMC 0x4 +#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_SYSTEM 0x5 +#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_SYSTEM 0x6 +#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_BMC 0x7 +#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_BMC 0x8 + +typedef union { + struct { + UINT8 ChannelNo : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_MUX_CHANNEL_NUM; + +typedef union { + struct { + UINT8 MuxSetting : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_MUX_SETTING_REQUEST; + +typedef struct { + IPMI_MUX_CHANNEL_NUM ChannelNumber; + IPMI_MUX_SETTING_REQUEST MuxSetting; +} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST; + +typedef union { + struct { + UINT8 MuxSetToBmc : 1; + UINT8 CommandStatus : 1; + UINT8 MessagingSessionActive : 1; + UINT8 AlertInProgress : 1; + UINT8 Reserved : 2; + UINT8 MuxToBmcAllowed : 1; + UINT8 MuxToSystemBlocked : 1; + } Bits; + UINT8 Uint8; +} IPMI_MUX_SETTING_PRESENT_STATE; + +typedef struct { + UINT8 CompletionCode; + IPMI_MUX_SETTING_PRESENT_STATE MuxSetting; +} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE; + +// +// Definitions for Get TAP Response Code command +// +#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13 + +// +// Constants and Structure definitions for "Get TAP Response Code" command to follow here +// + +// +// Definitions for Set PPP UDP Proxy Transmit Data command +// +#define IPMI_TRANSPORT_SET_PPP_UDP_PROXY_TXDATA 0x14 + +// +// Constants and Structure definitions for "Set PPP UDP Proxy Transmit Data" command to follow here +// + +// +// Definitions for Get PPP UDP Proxy Transmit Data command +// +#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_TXDATA 0x15 + +// +// Constants and Structure definitions for "Get PPP UDP Proxy Transmit Data" command to follow here +// + +// +// Definitions for Send PPP UDP Proxy Packet command +// +#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16 + +// +// Constants and Structure definitions for "Send PPP UDP Proxy Packet" command to follow here +// + +// +// Definitions for Get PPP UDP Proxy Receive Data command +// +#define IPMI_TRANSPORT_GET_PPP_UDP_PROXY_RX 0x17 + +// +// Constants and Structure definitions for "Get PPP UDP Proxy Receive Data" command to follow here +// + +// +// Definitions for Serial/Modem connection active command +// +#define IPMI_TRANSPORT_SERIAL_CONNECTION_ACTIVE 0x18 + +// +// Constants and Structure definitions for "Serial/Modem connection active" command to follow here +// + +// +// Definitions for Callback command +// +#define IPMI_TRANSPORT_CALLBACK 0x19 + +// +// Constants and Structure definitions for "Callback" command to follow here +// + +// +// Definitions for Set user Callback Options command +// +#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A + +// +// Constants and Structure definitions for "Set user Callback Options" command to follow here +// + +// +// Definitions for Get user Callback Options command +// +#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B + +// +// Constants and Structure definitions for "Get user Callback Options" command to follow here +// + +// +// Below is Definitions for SOL Commands (Chapter 26) +// + +// +// Definitions for SOL activating command +// +#define IPMI_TRANSPORT_SOL_ACTIVATING 0x20 + +// +// Constants and Structure definitions for "SOL activating" command to follow here +// +typedef union { + struct { + UINT8 SessionState : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_SOL_SESSION_STATE; + +typedef struct { + IPMI_SOL_SESSION_STATE SessionState; + UINT8 PayloadInstance; + UINT8 FormatVersionMajor; // 1 + UINT8 FormatVersionMinor; // 0 +} IPMI_SOL_ACTIVATING_REQUEST; + +// +// Definitions for Set SOL Configuration Parameters command +// +#define IPMI_TRANSPORT_SET_SOL_CONFIG_PARAM 0x21 + +// +// Constants and Structure definitions for "Set SOL Configuration Parameters" command to follow here +// + +// +// SOL Configuration Parameters selector +// +#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS 0 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE 1 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION 2 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM 3 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY 4 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE 5 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL 7 +#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT 8 + +typedef union { + struct { + UINT8 ChannelNumber : 4; + UINT8 Reserved : 4; + } Bits; + UINT8 Uint8; +} IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM; + +typedef struct { + IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber; + UINT8 ParameterSelector; + UINT8 ParameterData[0]; +} IPMI_SET_SOL_CONFIGURATION_PARAMETERS_REQUEST; + +// +// Definitions for Get SOL Configuration Parameters command +// +#define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM 0x22 + +// +// Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here +// +typedef union { + struct { + UINT8 ChannelNumber : 4; + UINT8 Reserved : 3; + UINT8 GetParameter : 1; + } Bits; + UINT8 Uint8; +} IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM; + +typedef struct { + IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber; + UINT8 ParameterSelector; + UINT8 SetSelector; + UINT8 BlockSelector; +} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_REQUEST; + +typedef struct { + UINT8 CompletionCode; + UINT8 ParameterRevision; + UINT8 ParameterData[0]; +} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_RESPONSE; + +#pragma pack() +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h new file mode 100644 index 0000000000..5c1f6ecfba --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h @@ -0,0 +1,288 @@ +/** @file + Defives data structures per MultiProcessor Specification Ver 1.4. + + The MultiProcessor Specification defines an enhancement to the standard + to which PC manufacturers design DOS-compatible systems. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _LEGACY_BIOS_MPTABLE_H_ +#define _LEGACY_BIOS_MPTABLE_H_ + +#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04 + +// +// Define MP table structures. All are packed. +// +#pragma pack(1) + +#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_') +typedef struct { + UINT32 Reserved1 : 6; + UINT32 MutipleClk : 1; + UINT32 Imcr : 1; + UINT32 Reserved2 : 24; +} FEATUREBYTE2_5; + +typedef struct { + UINT32 Signature; + UINT32 PhysicalAddress; + UINT8 Length; + UINT8 SpecRev; + UINT8 Checksum; + UINT8 FeatureByte1; + FEATUREBYTE2_5 FeatureByte2_5; +} EFI_LEGACY_MP_TABLE_FLOATING_POINTER; + +#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P') +typedef struct { + UINT32 Signature; + UINT16 BaseTableLength; + UINT8 SpecRev; + UINT8 Checksum; + CHAR8 OemId[8]; + CHAR8 OemProductId[12]; + UINT32 OemTablePointer; + UINT16 OemTableSize; + UINT16 EntryCount; + UINT32 LocalApicAddress; + UINT16 ExtendedTableLength; + UINT8 ExtendedChecksum; + UINT8 Reserved; +} EFI_LEGACY_MP_TABLE_HEADER; + +typedef struct { + UINT8 EntryType; +} EFI_LEGACY_MP_TABLE_ENTRY_TYPE; + +// +// Entry Type 0: Processor. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00 +typedef struct { + UINT8 Enabled : 1; + UINT8 Bsp : 1; + UINT8 Reserved : 6; +} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS; + +typedef struct { + UINT32 Stepping : 4; + UINT32 Model : 4; + UINT32 Family : 4; + UINT32 Reserved : 20; +} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE; + +typedef struct { + UINT32 Fpu : 1; + UINT32 Reserved1 : 6; + UINT32 Mce : 1; + UINT32 Cx8 : 1; + UINT32 Apic : 1; + UINT32 Reserved2 : 22; +} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES; + +typedef struct { + UINT8 EntryType; + UINT8 Id; + UINT8 Ver; + EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS Flags; + EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature; + EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES Features; + UINT32 Reserved1; + UINT32 Reserved2; +} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR; + +// +// Entry Type 1: Bus. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01 +typedef struct { + UINT8 EntryType; + UINT8 Id; + CHAR8 TypeString[6]; +} EFI_LEGACY_MP_TABLE_ENTRY_BUS; + +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc. +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus +#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus +// +// Entry Type 2: I/O APIC. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02 +typedef struct { + UINT8 Enabled : 1; + UINT8 Reserved : 7; +} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS; + +typedef struct { + UINT8 EntryType; + UINT8 Id; + UINT8 Ver; + EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags; + UINT32 Address; +} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC; + +// +// Entry Type 3: I/O Interrupt Assignment. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03 +typedef struct { + UINT16 Polarity : 2; + UINT16 Trigger : 2; + UINT16 Reserved : 12; +} EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS; + +typedef struct { + UINT8 IntNo : 2; + UINT8 Dev : 5; + UINT8 Reserved : 1; +} EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS; + +typedef union { + EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields; + UINT8 byte; +} EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ; + +typedef struct { + UINT8 EntryType; + UINT8 IntType; + EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags; + UINT8 SourceBusId; + EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq; + UINT8 DestApicId; + UINT8 DestApicIntIn; +} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT; + +typedef enum { + EfiLegacyMpTableEntryIoIntTypeInt = 0, + EfiLegacyMpTableEntryIoIntTypeNmi = 1, + EfiLegacyMpTableEntryIoIntTypeSmi = 2, + EfiLegacyMpTableEntryIoIntTypeExtInt= 3, +} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE; + +typedef enum { + EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0, + EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1, + EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2, + EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3, +} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY; + +typedef enum { + EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0, + EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1, + EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2, + EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3, +} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER; + +// +// Entry Type 4: Local Interrupt Assignment. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04 +typedef struct { + UINT8 EntryType; + UINT8 IntType; + EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags; + UINT8 SourceBusId; + EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq; + UINT8 DestApicId; + UINT8 DestApicIntIn; +} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT; + +typedef enum { + EfiLegacyMpTableEntryLocalIntTypeInt = 0, + EfiLegacyMpTableEntryLocalIntTypeNmi = 1, + EfiLegacyMpTableEntryLocalIntTypeSmi = 2, + EfiLegacyMpTableEntryLocalIntTypeExtInt = 3, +} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE; + +typedef enum { + EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0, + EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1, + EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2, + EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3, +} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY; + +typedef enum { + EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0, + EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1, + EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2, + EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3, +} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER; + +// +// Entry Type 128: System Address Space Mapping. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80 +typedef struct { + UINT8 EntryType; + UINT8 Length; + UINT8 BusId; + UINT8 AddressType; + UINT64 AddressBase; + UINT64 AddressLength; +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING; + +typedef enum { + EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0, + EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1, + EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2, +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE; + +// +// Entry Type 129: Bus Hierarchy. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81 +typedef struct { + UINT8 SubtractiveDecode : 1; + UINT8 Reserved : 7; +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO; + +typedef struct { + UINT8 EntryType; + UINT8 Length; + UINT8 BusId; + EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo; + UINT8 ParentBus; + UINT8 Reserved1; + UINT8 Reserved2; + UINT8 Reserved3; +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY; + +// +// Entry Type 130: Compatibility Bus Address Space Modifier. +// +#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82 +typedef struct { + UINT8 RangeMode : 1; + UINT8 Reserved : 7; +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE; + +typedef struct { + UINT8 EntryType; + UINT8 Length; + UINT8 BusId; + EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode; + UINT32 PredefinedRangeList; +} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h new file mode 100644 index 0000000000..8de0cbf612 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h @@ -0,0 +1,76 @@ +/** @file + ACPI Low Power Idle Table (LPIT) definitions + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014 + http://www.uefi.org/sites/default/files/resources/ACPI_Low_Power_Idle_Table.pdf + + @par Glossary: + - GAS - Generic Address Structure + - LPI - Low Power Idle +**/ +#ifndef _LOW_POWER_IDLE_TABLE_H_ +#define _LOW_POWER_IDLE_TABLE_H_ + +#include + +#pragma pack(1) + +/// +/// LPI Structure Types +/// +#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00 + +/// +/// Low Power Idle (LPI) State Flags +/// +typedef union { + struct { + UINT32 Disabled : 1; ///< If set, LPI state is not used + /** + If set, Residency counter is not available for this LPI state and + Residency Counter Frequency is invalid + **/ + UINT32 CounterUnavailable : 1; + UINT32 Reserved : 30; ///< Reserved for future use. Must be zero + } Bits; + UINT32 Data32; +} ACPI_LPI_STATE_FLAGS; + +/// +/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor +/// +typedef struct { + UINT32 Type; ///< LPI State descriptor Type 0 + UINT32 Length; ///< Length of LPI state Descriptor Structure + /// + /// Unique LPI state identifier: zero based, monotonically increasing identifier + /// + UINT16 UniqueId; + UINT8 Reserved[2]; ///< Must be Zero + ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags + /** + The LPI entry trigger, matching an existing _CST.Register object, represented as a + Generic Address Structure. All processors must request this state or deeper to trigger. + **/ + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger; + UINT32 Residency; ///< Minimum residency or break-even in uSec + UINT32 Latency; ///< Worst case exit latency in uSec + /** + [optional] Residency counter, represented as a Generic Address Structure. + If not present, Flags[1] bit should be set. + **/ + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; + /** + [optional] Residency counter frequency in cycles per second. Value 0 indicates that + counter runs at TSC frequency. Valid only if Residency Counter is present. + **/ + UINT64 ResidencyCounterFrequency; +} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Mbr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Mbr.h new file mode 100644 index 0000000000..2d8c1f1e19 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Mbr.h @@ -0,0 +1,54 @@ +/** @file + Legacy Master Boot Record Format Definition. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MBR_H_ +#define _MBR_H_ + +#define MBR_SIGNATURE 0xaa55 + +#define EXTENDED_DOS_PARTITION 0x05 +#define EXTENDED_WINDOWS_PARTITION 0x0F + +#define MAX_MBR_PARTITIONS 4 + +#define PMBR_GPT_PARTITION 0xEE +#define EFI_PARTITION 0xEF + +#define MBR_SIZE 512 + +#pragma pack(1) +/// +/// MBR Partition Entry +/// +typedef struct { + UINT8 BootIndicator; + UINT8 StartHead; + UINT8 StartSector; + UINT8 StartTrack; + UINT8 OSIndicator; + UINT8 EndHead; + UINT8 EndSector; + UINT8 EndTrack; + UINT8 StartingLBA[4]; + UINT8 SizeInLBA[4]; +} MBR_PARTITION_RECORD; + +/// +/// MBR Partition Table +/// +typedef struct { + UINT8 BootStrapCode[440]; + UINT8 UniqueMbrSignature[4]; + UINT8 Unknown[2]; + MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS]; + UINT16 Signature; +} MASTER_BOOT_RECORD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h new file mode 100644 index 0000000000..4bc163e1bf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h @@ -0,0 +1,49 @@ +/** @file + ACPI memory mapped configuration space access table definition, defined at + in the PCI Firmware Specification, version 3.0. + Specification is available at http://www.pcisig.com. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_ +#define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Memory Mapped Configuration Space Access Table (MCFG) +/// This table is a basic description table header followed by +/// a number of base address allocation structures. +/// +typedef struct { + UINT64 BaseAddress; + UINT16 PciSegmentGroupNumber; + UINT8 StartBusNumber; + UINT8 EndBusNumber; + UINT32 Reserved; +} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE; + +/// +/// MCFG Table header definition. The rest of the table +/// must be defined in a platform specific manner. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER; + +/// +/// MCFG Revision (defined in spec) +/// +#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01 + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h new file mode 100644 index 0000000000..3d5aaabf27 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h @@ -0,0 +1,37 @@ +/** @file + Support for Microsoft Secure MOR implementation, defined at + Microsoft Secure MOR implementation. + https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__ +#define __MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_H__ + +#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_GUID \ + { \ + 0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92} \ + } + +#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock" + +// +// VendorGuid: {BB983CCF-151D-40E1-A07B-4A17BE168292} +// Name: MemoryOverwriteRequestControlLock +// Attributes: NV+BS+RT +// GetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked without key); 0x2 (locked with key) +// SetVariable value in Data parameter: 0x0 (unlocked); 0x1 (locked); +// Revision 2 additionally accepts an 8-byte value that represents a shared secret key. +// + +// +// Note: Setting MemoryOverwriteRequestControlLock does not commit to flash (just changes the internal lock state). +// Getting the variable returns the internal state and never exposes the key. +// + +extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Nvme.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Nvme.h new file mode 100644 index 0000000000..4601a59ef0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Nvme.h @@ -0,0 +1,942 @@ +/** @file + Definitions based on NVMe spec. version 1.1. + + (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + NVMe Specification 1.1 + +**/ + +#ifndef __NVM_E_H__ +#define __NVM_E_H__ + +#pragma pack(1) + +// +// controller register offsets +// +#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities +#define NVME_VER_OFFSET 0x0008 // Version +#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set +#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear +#define NVME_CC_OFFSET 0x0014 // Controller Configuration +#define NVME_CSTS_OFFSET 0x001c // Controller Status +#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset +#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes +#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address +#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address +#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell +#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell + +// +// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD)) +// Get the doorbell stride bit shift value from the controller capabilities. +// +#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell +#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell + + +#pragma pack(1) + +// +// 3.1.1 Offset 00h: CAP - Controller Capabilities +// +typedef struct { + UINT16 Mqes; // Maximum Queue Entries Supported + UINT8 Cqr:1; // Contiguous Queues Required + UINT8 Ams:2; // Arbitration Mechanism Supported + UINT8 Rsvd1:5; + UINT8 To; // Timeout + UINT16 Dstrd:4; + UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS + UINT16 Css:4; // Command Sets Supported - Bit 37 + UINT16 Rsvd3:7; + UINT8 Mpsmin:4; + UINT8 Mpsmax:4; + UINT8 Rsvd4; +} NVME_CAP; + +// +// 3.1.2 Offset 08h: VS - Version +// +typedef struct { + UINT16 Mnr; // Minor version number + UINT16 Mjr; // Major version number +} NVME_VER; + +// +// 3.1.5 Offset 14h: CC - Controller Configuration +// +typedef struct { + UINT16 En:1; // Enable + UINT16 Rsvd1:3; + UINT16 Css:3; // I/O Command Set Selected + UINT16 Mps:4; // Memory Page Size + UINT16 Ams:3; // Arbitration Mechanism Selected + UINT16 Shn:2; // Shutdown Notification + UINT8 Iosqes:4; // I/O Submission Queue Entry Size + UINT8 Iocqes:4; // I/O Completion Queue Entry Size + UINT8 Rsvd2; +} NVME_CC; +#define NVME_CC_SHN_NORMAL_SHUTDOWN 1 +#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2 + +// +// 3.1.6 Offset 1Ch: CSTS - Controller Status +// +typedef struct { + UINT32 Rdy:1; // Ready + UINT32 Cfs:1; // Controller Fatal Status + UINT32 Shst:2; // Shutdown Status + UINT32 Nssro:1; // NVM Subsystem Reset Occurred + UINT32 Rsvd1:27; +} NVME_CSTS; +#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1 +#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2 +// +// 3.1.8 Offset 24h: AQA - Admin Queue Attributes +// +typedef struct { + UINT16 Asqs:12; // Submission Queue Size + UINT16 Rsvd1:4; + UINT16 Acqs:12; // Completion Queue Size + UINT16 Rsvd2:4; +} NVME_AQA; + +// +// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address +// +#define NVME_ASQ UINT64 +// +// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address +// +#define NVME_ACQ UINT64 + +// +// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell +// +typedef struct { + UINT16 Sqt; + UINT16 Rsvd1; +} NVME_SQTDBL; + +// +// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell +// +typedef struct { + UINT16 Cqh; + UINT16 Rsvd1; +} NVME_CQHDBL; + +// +// NVM command set structures +// +// Read Command +// +typedef struct { + // + // CDW 10, 11 + // + UINT64 Slba; /* Starting Sector Address */ + // + // CDW 12 + // + UINT16 Nlb; /* Number of Sectors */ + UINT16 Rsvd1:10; + UINT16 Prinfo:4; /* Protection Info Check */ + UINT16 Fua:1; /* Force Unit Access */ + UINT16 Lr:1; /* Limited Retry */ + // + // CDW 13 + // + UINT32 Af:4; /* Access Frequency */ + UINT32 Al:2; /* Access Latency */ + UINT32 Sr:1; /* Sequential Request */ + UINT32 In:1; /* Incompressible */ + UINT32 Rsvd2:24; + // + // CDW 14 + // + UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */ + // + // CDW 15 + // + UINT16 Elbat; /* Expected Logical Block Application Tag */ + UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */ +} NVME_READ; + +// +// Write Command +// +typedef struct { + // + // CDW 10, 11 + // + UINT64 Slba; /* Starting Sector Address */ + // + // CDW 12 + // + UINT16 Nlb; /* Number of Sectors */ + UINT16 Rsvd1:10; + UINT16 Prinfo:4; /* Protection Info Check */ + UINT16 Fua:1; /* Force Unit Access */ + UINT16 Lr:1; /* Limited Retry */ + // + // CDW 13 + // + UINT32 Af:4; /* Access Frequency */ + UINT32 Al:2; /* Access Latency */ + UINT32 Sr:1; /* Sequential Request */ + UINT32 In:1; /* Incompressible */ + UINT32 Rsvd2:24; + // + // CDW 14 + // + UINT32 Ilbrt; /* Initial Logical Block Reference Tag */ + // + // CDW 15 + // + UINT16 Lbat; /* Logical Block Application Tag */ + UINT16 Lbatm; /* Logical Block Application Tag Mask */ +} NVME_WRITE; + +// +// Flush +// +typedef struct { + // + // CDW 10 + // + UINT32 Flush; /* Flush */ +} NVME_FLUSH; + +// +// Write Uncorrectable command +// +typedef struct { + // + // CDW 10, 11 + // + UINT64 Slba; /* Starting LBA */ + // + // CDW 12 + // + UINT32 Nlb:16; /* Number of Logical Blocks */ + UINT32 Rsvd1:16; +} NVME_WRITE_UNCORRECTABLE; + +// +// Write Zeroes command +// +typedef struct { + // + // CDW 10, 11 + // + UINT64 Slba; /* Starting LBA */ + // + // CDW 12 + // + UINT16 Nlb; /* Number of Logical Blocks */ + UINT16 Rsvd1:10; + UINT16 Prinfo:4; /* Protection Info Check */ + UINT16 Fua:1; /* Force Unit Access */ + UINT16 Lr:1; /* Limited Retry */ + // + // CDW 13 + // + UINT32 Rsvd2; + // + // CDW 14 + // + UINT32 Ilbrt; /* Initial Logical Block Reference Tag */ + // + // CDW 15 + // + UINT16 Lbat; /* Logical Block Application Tag */ + UINT16 Lbatm; /* Logical Block Application Tag Mask */ +} NVME_WRITE_ZEROES; + +// +// Compare command +// +typedef struct { + // + // CDW 10, 11 + // + UINT64 Slba; /* Starting LBA */ + // + // CDW 12 + // + UINT16 Nlb; /* Number of Logical Blocks */ + UINT16 Rsvd1:10; + UINT16 Prinfo:4; /* Protection Info Check */ + UINT16 Fua:1; /* Force Unit Access */ + UINT16 Lr:1; /* Limited Retry */ + // + // CDW 13 + // + UINT32 Rsvd2; + // + // CDW 14 + // + UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */ + // + // CDW 15 + // + UINT16 Elbat; /* Expected Logical Block Application Tag */ + UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */ +} NVME_COMPARE; + +typedef union { + NVME_READ Read; + NVME_WRITE Write; + NVME_FLUSH Flush; + NVME_WRITE_UNCORRECTABLE WriteUncorrectable; + NVME_WRITE_ZEROES WriteZeros; + NVME_COMPARE Compare; +} NVME_CMD; + +typedef struct { + UINT16 Mp; /* Maximum Power */ + UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 Mps:1; /* Max Power Scale */ + UINT8 Nops:1; /* Non-Operational State */ + UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */ + UINT32 Enlat; /* Entry Latency */ + UINT32 Exlat; /* Exit Latency */ + UINT8 Rrt:5; /* Relative Read Throughput */ + UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 Rrl:5; /* Relative Read Latency */ + UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 Rwt:5; /* Relative Write Throughput */ + UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 Rwl:5; /* Relative Write Latency */ + UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */ +} NVME_PSDESCRIPTOR; + +// +// Identify Controller Data +// +typedef struct { + // + // Controller Capabilities and Features 0-255 + // + UINT16 Vid; /* PCI Vendor ID */ + UINT16 Ssvid; /* PCI sub-system vendor ID */ + UINT8 Sn[20]; /* Product serial number */ + + UINT8 Mn[40]; /* Product model number */ + UINT8 Fr[8]; /* Firmware Revision */ + UINT8 Rab; /* Recommended Arbitration Burst */ + UINT8 Ieee_oui[3]; /* Organization Unique Identifier */ + UINT8 Cmic; /* Multi-interface Capabilities */ + UINT8 Mdts; /* Maximum Data Transfer Size */ + UINT8 Cntlid[2]; /* Controller ID */ + UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */ + // + // Admin Command Set Attributes + // + UINT16 Oacs; /* Optional Admin Command Support */ + #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3 + #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2 + #define FORMAT_NVM_SUPPORTED BIT1 + #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0 + UINT8 Acl; /* Abort Command Limit */ + UINT8 Aerl; /* Async Event Request Limit */ + UINT8 Frmw; /* Firmware updates */ + UINT8 Lpa; /* Log Page Attributes */ + UINT8 Elpe; /* Error Log Page Entries */ + UINT8 Npss; /* Number of Power States Support */ + UINT8 Avscc; /* Admin Vendor Specific Command Configuration */ + UINT8 Apsta; /* Autonomous Power State Transition Attributes */ + // + // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec + // + UINT16 Wctemp; /* Warning Composite Temperature Threshold */ + UINT16 Cctemp; /* Critical Composite Temperature Threshold */ + UINT16 Mtfa; /* Maximum Time for Firmware Activation */ + UINT32 Hmpre; /* Host Memory Buffer Preferred Size */ + UINT32 Hmmin; /* Host Memory Buffer Minimum Size */ + UINT8 Tnvmcap[16]; /* Total NVM Capacity */ + UINT8 Rsvd2[216]; /* Reserved as of NVM Express */ + // + // NVM Command Set Attributes + // + UINT8 Sqes; /* Submission Queue Entry Size */ + UINT8 Cqes; /* Completion Queue Entry Size */ + UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */ + UINT32 Nn; /* Number of Namespaces */ + UINT16 Oncs; /* Optional NVM Command Support */ + UINT16 Fuses; /* Fused Operation Support */ + UINT8 Fna; /* Format NVM Attributes */ + UINT8 Vwc; /* Volatile Write Cache */ + UINT16 Awun; /* Atomic Write Unit Normal */ + UINT16 Awupf; /* Atomic Write Unit Power Fail */ + UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */ + UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */ + UINT16 Acwu; /* Atomic Compare & Write Unit */ + UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */ + UINT32 Sgls; /* SGL Support */ + UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */ + // + // I/O Command set Attributes + // + UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */ + // + // Power State Descriptors + // + NVME_PSDESCRIPTOR PsDescriptor[32]; + + UINT8 VendorData[1024]; /* Vendor specific data */ +} NVME_ADMIN_CONTROLLER_DATA; + +typedef struct { + UINT16 Ms; /* Metadata Size */ + UINT8 Lbads; /* LBA Data Size */ + UINT8 Rp:2; /* Relative Performance */ + #define LBAF_RP_BEST 00b + #define LBAF_RP_BETTER 01b + #define LBAF_RP_GOOD 10b + #define LBAF_RP_DEGRADED 11b + UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */ +} NVME_LBAFORMAT; + +// +// Identify Namespace Data +// +typedef struct { + // + // NVM Command Set Specific + // + UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */ + UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */ + UINT64 Nuse; /* Namespace Utilization */ + UINT8 Nsfeat; /* Namespace Features */ + UINT8 Nlbaf; /* Number of LBA Formats */ + UINT8 Flbas; /* Formatted LBA size */ + UINT8 Mc; /* Metadata Capabilities */ + UINT8 Dpc; /* End-to-end Data Protection capabilities */ + UINT8 Dps; /* End-to-end Data Protection Type Settings */ + UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */ + UINT8 Rescap; /* Reservation Capabilities */ + UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */ + UINT64 Eui64; /* IEEE Extended Unique Identifier */ + // + // LBA Format + // + NVME_LBAFORMAT LbaFormat[16]; + + UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */ + UINT8 VendorData[3712]; /* Vendor specific data */ +} NVME_ADMIN_NAMESPACE_DATA; + +// +// NvmExpress Admin Identify Cmd +// +typedef struct { + // + // CDW 10 + // + UINT32 Cns:2; + UINT32 Rsvd1:30; +} NVME_ADMIN_IDENTIFY; + +// +// NvmExpress Admin Create I/O Completion Queue +// +typedef struct { + // + // CDW 10 + // + UINT32 Qid:16; /* Queue Identifier */ + UINT32 Qsize:16; /* Queue Size */ + + // + // CDW 11 + // + UINT32 Pc:1; /* Physically Contiguous */ + UINT32 Ien:1; /* Interrupts Enabled */ + UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */ + UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/ +} NVME_ADMIN_CRIOCQ; + +// +// NvmExpress Admin Create I/O Submission Queue +// +typedef struct { + // + // CDW 10 + // + UINT32 Qid:16; /* Queue Identifier */ + UINT32 Qsize:16; /* Queue Size */ + + // + // CDW 11 + // + UINT32 Pc:1; /* Physically Contiguous */ + UINT32 Qprio:2; /* Queue Priority */ + UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */ + UINT32 Cqid:16; /* Completion Queue ID */ +} NVME_ADMIN_CRIOSQ; + +// +// NvmExpress Admin Delete I/O Completion Queue +// +typedef struct { + // + // CDW 10 + // + UINT16 Qid; + UINT16 Rsvd1; +} NVME_ADMIN_DEIOCQ; + +// +// NvmExpress Admin Delete I/O Submission Queue +// +typedef struct { + // + // CDW 10 + // + UINT16 Qid; + UINT16 Rsvd1; +} NVME_ADMIN_DEIOSQ; + +// +// NvmExpress Admin Abort Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Sqid:16; /* Submission Queue identifier */ + UINT32 Cid:16; /* Command Identifier */ +} NVME_ADMIN_ABORT; + +// +// NvmExpress Admin Firmware Activate Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Fs:3; /* Submission Queue identifier */ + UINT32 Aa:2; /* Command Identifier */ + UINT32 Rsvd1:27; +} NVME_ADMIN_FIRMWARE_ACTIVATE; + +// +// NvmExpress Admin Firmware Image Download Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Numd; /* Number of Dwords */ + // + // CDW 11 + // + UINT32 Ofst; /* Offset */ +} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD; + +// +// NvmExpress Admin Get Features Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Fid:8; /* Feature Identifier */ + UINT32 Sel:3; /* Select */ + UINT32 Rsvd1:21; +} NVME_ADMIN_GET_FEATURES; + +// +// NvmExpress Admin Get Log Page Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Lid:8; /* Log Page Identifier */ + #define LID_ERROR_INFO 0x1 + #define LID_SMART_INFO 0x2 + #define LID_FW_SLOT_INFO 0x3 + UINT32 Rsvd1:8; + UINT32 Numd:12; /* Number of Dwords */ + UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */ +} NVME_ADMIN_GET_LOG_PAGE; + +// +// NvmExpress Admin Set Features Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Fid:8; /* Feature Identifier */ + UINT32 Rsvd1:23; + UINT32 Sv:1; /* Save */ +} NVME_ADMIN_SET_FEATURES; + +// +// NvmExpress Admin Format NVM Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Lbaf:4; /* LBA Format */ + UINT32 Ms:1; /* Metadata Settings */ + UINT32 Pi:3; /* Protection Information */ + UINT32 Pil:1; /* Protection Information Location */ + UINT32 Ses:3; /* Secure Erase Settings */ + UINT32 Rsvd1:20; +} NVME_ADMIN_FORMAT_NVM; + +// +// NvmExpress Admin Security Receive Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Rsvd1:8; + UINT32 Spsp:16; /* SP Specific */ + UINT32 Secp:8; /* Security Protocol */ + // + // CDW 11 + // + UINT32 Al; /* Allocation Length */ +} NVME_ADMIN_SECURITY_RECEIVE; + +// +// NvmExpress Admin Security Send Command +// +typedef struct { + // + // CDW 10 + // + UINT32 Rsvd1:8; + UINT32 Spsp:16; /* SP Specific */ + UINT32 Secp:8; /* Security Protocol */ + // + // CDW 11 + // + UINT32 Tl; /* Transfer Length */ +} NVME_ADMIN_SECURITY_SEND; + +typedef union { + NVME_ADMIN_IDENTIFY Identify; + NVME_ADMIN_CRIOCQ CrIoCq; + NVME_ADMIN_CRIOSQ CrIoSq; + NVME_ADMIN_DEIOCQ DeIoCq; + NVME_ADMIN_DEIOSQ DeIoSq; + NVME_ADMIN_ABORT Abort; + NVME_ADMIN_FIRMWARE_ACTIVATE Activate; + NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload; + NVME_ADMIN_GET_FEATURES GetFeatures; + NVME_ADMIN_GET_LOG_PAGE GetLogPage; + NVME_ADMIN_SET_FEATURES SetFeatures; + NVME_ADMIN_FORMAT_NVM FormatNvm; + NVME_ADMIN_SECURITY_RECEIVE SecurityReceive; + NVME_ADMIN_SECURITY_SEND SecuritySend; +} NVME_ADMIN_CMD; + +typedef struct { + UINT32 Cdw10; + UINT32 Cdw11; + UINT32 Cdw12; + UINT32 Cdw13; + UINT32 Cdw14; + UINT32 Cdw15; +} NVME_RAW; + +typedef union { + NVME_ADMIN_CMD Admin; // Union of Admin commands + NVME_CMD Nvm; // Union of Nvm commands + NVME_RAW Raw; +} NVME_PAYLOAD; + +// +// Submission Queue +// +typedef struct { + // + // CDW 0, Common to all commands + // + UINT8 Opc; // Opcode + UINT8 Fuse:2; // Fused Operation + UINT8 Rsvd1:5; + UINT8 Psdt:1; // PRP or SGL for Data Transfer + UINT16 Cid; // Command Identifier + + // + // CDW 1 + // + UINT32 Nsid; // Namespace Identifier + + // + // CDW 2,3 + // + UINT64 Rsvd2; + + // + // CDW 4,5 + // + UINT64 Mptr; // Metadata Pointer + + // + // CDW 6-9 + // + UINT64 Prp[2]; // First and second PRP entries + + NVME_PAYLOAD Payload; + +} NVME_SQ; + +// +// Completion Queue +// +typedef struct { + // + // CDW 0 + // + UINT32 Dword0; + // + // CDW 1 + // + UINT32 Rsvd1; + // + // CDW 2 + // + UINT16 Sqhd; // Submission Queue Head Pointer + UINT16 Sqid; // Submission Queue Identifier + // + // CDW 3 + // + UINT16 Cid; // Command Identifier + UINT16 Pt:1; // Phase Tag + UINT16 Sc:8; // Status Code + UINT16 Sct:3; // Status Code Type + UINT16 Rsvd2:2; + UINT16 Mo:1; // More + UINT16 Dnr:1; // Do Not Retry +} NVME_CQ; + +// +// Nvm Express Admin cmd opcodes +// +#define NVME_ADMIN_DEIOSQ_CMD 0x00 +#define NVME_ADMIN_CRIOSQ_CMD 0x01 +#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02 +#define NVME_ADMIN_DEIOCQ_CMD 0x04 +#define NVME_ADMIN_CRIOCQ_CMD 0x05 +#define NVME_ADMIN_IDENTIFY_CMD 0x06 +#define NVME_ADMIN_ABORT_CMD 0x08 +#define NVME_ADMIN_SET_FEATURES_CMD 0x09 +#define NVME_ADMIN_GET_FEATURES_CMD 0x0A +#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C +#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D +#define NVME_ADMIN_FW_COMMIT_CMD 0x10 +#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11 +#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15 +#define NVME_ADMIN_FORMAT_NVM_CMD 0x80 +#define NVME_ADMIN_SECURITY_SEND_CMD 0x81 +#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82 + +#define NVME_IO_FLUSH_OPC 0 +#define NVME_IO_WRITE_OPC 1 +#define NVME_IO_READ_OPC 2 + +typedef enum { + DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD, + CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD, + GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD, + DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD, + CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD, + IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD, + AbortOpcode = NVME_ADMIN_ABORT_CMD, + SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD, + GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD, + AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD, + NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD, + FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD, + FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD, + NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD, + FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD, + SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD, + SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD +} NVME_ADMIN_COMMAND_OPCODE; + +// +// Controller or Namespace Structure (CNS) field +// (ref. spec. v1.1 figure 82). +// +typedef enum { +IdentifyNamespaceCns = 0x0, +IdentifyControllerCns = 0x1, +IdentifyActiveNsListCns = 0x2 +} NVME_ADMIN_IDENTIFY_CNS; + +// +// Commit Action +// (ref. spec. 1.1 figure 60). +// +typedef enum { + ActivateActionReplace = 0x0, + ActivateActionReplaceActivate = 0x1, + ActivateActionActivate = 0x2 +} NVME_FW_ACTIVATE_ACTION; + +// +// Firmware Slot +// (ref. spec. 1.1 Figure 60). +// +typedef enum { + FirmwareSlotCtrlChooses = 0x0, + FirmwareSlot1 = 0x1, + FirmwareSlot2 = 0x2, + FirmwareSlot3 = 0x3, + FirmwareSlot4 = 0x4, + FirmwareSlot5 = 0x5, + FirmwareSlot6 = 0x6, + FirmwareSlot7 = 0x7 +} NVME_FW_ACTIVATE_SLOT; + +// +// Get Log Page ? Log Page Identifiers +// (ref. spec. v1.1 Figure 73). +// +typedef enum { + ErrorInfoLogID = LID_ERROR_INFO, + SmartHealthInfoLogID = LID_SMART_INFO, + FirmwareSlotInfoLogID = LID_FW_SLOT_INFO +} NVME_LOG_ID; + +// +// Get Log Page ? Firmware Slot Information Log +// (ref. spec. v1.1 Figure 77). +// +typedef struct { + // + // Indicates the firmware slot from which the actively running firmware revision was loaded. + // + UINT8 ActivelyRunningFwSlot:3; + UINT8 :1; + // + // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset. + // + UINT8 NextActiveFwSlot:3; + UINT8 :1; +} NVME_ACTIVE_FW_INFO; + +// +// Get Log Page ? Firmware Slot Information Log +// (ref. spec. v1.1 Figure 77). +// +typedef struct { + // + // Specifies information about the active firmware revision. + //s + NVME_ACTIVE_FW_INFO ActiveFwInfo; + UINT8 Reserved1[7]; + // + // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned. + // + CHAR8 FwRevisionSlot[7][8]; + UINT8 Reserved2[448]; +} NVME_FW_SLOT_INFO_LOG; + +// +// SMART / Health Information (Log Identifier 02h) +// (ref. spec. v1.1 5.10.1.2) +// +typedef struct { + // + // This field indicates critical warnings for the state of the controller. + // + UINT8 CriticalWarningAvailableSpare:1; + UINT8 CriticalWarningTemperature:1; + UINT8 CriticalWarningReliability:1; + UINT8 CriticalWarningMediaReadOnly:1; + UINT8 CriticalWarningVolatileBackup:1; + UINT8 CriticalWarningReserved:3; + // + // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem. + // + UINT16 CompositeTemp; + // + // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available. + // + UINT8 AvailableSpare; + // + // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%). + // + UINT8 AvailableSpareThreshold; + // + // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state). + // + UINT8 PercentageUsed; + UINT8 Reserved1[26]; + // + // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata. + // + UINT8 DataUnitsRead[16]; + // + // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata. + // + UINT8 DataUnitsWritten[16]; + // + // Contains the number of read commands completed by the controller. + // + UINT8 HostReadCommands[16]; + // + // Contains the number of write commands completed by the controller. + // + UINT8 HostWriteCommands[16]; + // + // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes. + // + UINT8 ControllerBusyTime[16]; + // + // Contains the number of power cycles. + // + UINT8 PowerCycles[16]; + // + // Contains the number of power-on hours. + // + UINT8 PowerOnHours[16]; + // + // Contains the number of unsafe shutdowns. + // + UINT8 UnsafeShutdowns[16]; + // + // Contains the number of occurrences where the controller detected an unrecovered data integrity error. + // + UINT8 MediaAndDataIntegrityErrors[16]; + // + // Contains the number of Error Information log entries over the life of the controller. + // + UINT8 NumberErrorInformationLogEntries[16]; + // + // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90. + // + UINT32 WarningCompositeTemperatureTime; + // + // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90. + // + UINT32 CriticalCompositeTemperatureTime; + // + // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin. + // + UINT16 TemperatureSensor[8]; + UINT8 Reserved2[296]; +} NVME_SMART_HEALTH_INFO_LOG; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci.h new file mode 100644 index 0000000000..2cd95d75a2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci.h @@ -0,0 +1,15 @@ +/** @file + Support for the latest PCI standard. + +Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCI_H_ +#define _PCI_H_ + +#include +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h new file mode 100644 index 0000000000..69e15f7aa9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h @@ -0,0 +1,861 @@ +/** @file + Support for PCI 2.2 standard. + + This file includes the definitions in the following specifications, + PCI Local Bus Specification, 2.2 + PCI-to-PCI Bridge Architecture Specification, Revision 1.2 + PC Card Standard, 8.0 + PCI Power Management Interface Specification, Revision 1.2 + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCI22_H_ +#define _PCI22_H_ + +#define PCI_MAX_BUS 255 +#define PCI_MAX_DEVICE 31 +#define PCI_MAX_FUNC 7 + +#pragma pack(1) + +/// +/// Common header region in PCI Configuration Space +/// Section 6.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + UINT16 VendorId; + UINT16 DeviceId; + UINT16 Command; + UINT16 Status; + UINT8 RevisionID; + UINT8 ClassCode[3]; + UINT8 CacheLineSize; + UINT8 LatencyTimer; + UINT8 HeaderType; + UINT8 BIST; +} PCI_DEVICE_INDEPENDENT_REGION; + +/// +/// PCI Device header region in PCI Configuration Space +/// Section 6.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + UINT32 Bar[6]; + UINT32 CISPtr; + UINT16 SubsystemVendorID; + UINT16 SubsystemID; + UINT32 ExpansionRomBar; + UINT8 CapabilityPtr; + UINT8 Reserved1[3]; + UINT32 Reserved2; + UINT8 InterruptLine; + UINT8 InterruptPin; + UINT8 MinGnt; + UINT8 MaxLat; +} PCI_DEVICE_HEADER_TYPE_REGION; + +/// +/// PCI Device Configuration Space +/// Section 6.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + PCI_DEVICE_INDEPENDENT_REGION Hdr; + PCI_DEVICE_HEADER_TYPE_REGION Device; +} PCI_TYPE00; + +/// +/// PCI-PCI Bridge header region in PCI Configuration Space +/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2 +/// +typedef struct { + UINT32 Bar[2]; + UINT8 PrimaryBus; + UINT8 SecondaryBus; + UINT8 SubordinateBus; + UINT8 SecondaryLatencyTimer; + UINT8 IoBase; + UINT8 IoLimit; + UINT16 SecondaryStatus; + UINT16 MemoryBase; + UINT16 MemoryLimit; + UINT16 PrefetchableMemoryBase; + UINT16 PrefetchableMemoryLimit; + UINT32 PrefetchableBaseUpper32; + UINT32 PrefetchableLimitUpper32; + UINT16 IoBaseUpper16; + UINT16 IoLimitUpper16; + UINT8 CapabilityPtr; + UINT8 Reserved[3]; + UINT32 ExpansionRomBAR; + UINT8 InterruptLine; + UINT8 InterruptPin; + UINT16 BridgeControl; +} PCI_BRIDGE_CONTROL_REGISTER; + +/// +/// PCI-to-PCI Bridge Configuration Space +/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2 +/// +typedef struct { + PCI_DEVICE_INDEPENDENT_REGION Hdr; + PCI_BRIDGE_CONTROL_REGISTER Bridge; +} PCI_TYPE01; + +typedef union { + PCI_TYPE00 Device; + PCI_TYPE01 Bridge; +} PCI_TYPE_GENERIC; + +/// +/// CardBus Controller Configuration Space, +/// Section 4.5.1, PC Card Standard. 8.0 +/// +typedef struct { + UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base + UINT8 Cap_Ptr; + UINT8 Reserved; + UINT16 SecondaryStatus; ///< Secondary Status + UINT8 PciBusNumber; ///< PCI Bus Number + UINT8 CardBusBusNumber; ///< CardBus Bus Number + UINT8 SubordinateBusNumber; ///< Subordinate Bus Number + UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer + UINT32 MemoryBase0; ///< Memory Base Register 0 + UINT32 MemoryLimit0; ///< Memory Limit Register 0 + UINT32 MemoryBase1; + UINT32 MemoryLimit1; + UINT32 IoBase0; + UINT32 IoLimit0; ///< I/O Base Register 0 + UINT32 IoBase1; ///< I/O Limit Register 0 + UINT32 IoLimit1; + UINT8 InterruptLine; ///< Interrupt Line + UINT8 InterruptPin; ///< Interrupt Pin + UINT16 BridgeControl; ///< Bridge Control +} PCI_CARDBUS_CONTROL_REGISTER; + +// +// Definitions of PCI class bytes and manipulation macros. +// +#define PCI_CLASS_OLD 0x00 +#define PCI_CLASS_OLD_OTHER 0x00 +#define PCI_CLASS_OLD_VGA 0x01 + +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_CLASS_MASS_STORAGE_IDE 0x01 +#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_CLASS_MASS_STORAGE_IPI 0x03 +#define PCI_CLASS_MASS_STORAGE_RAID 0x04 +#define PCI_CLASS_MASS_STORAGE_OTHER 0x80 + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_TOKENRING 0x01 +#define PCI_CLASS_NETWORK_FDDI 0x02 +#define PCI_CLASS_NETWORK_ATM 0x03 +#define PCI_CLASS_NETWORK_ISDN 0x04 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x00 +#define PCI_IF_VGA_VGA 0x00 +#define PCI_IF_VGA_8514 0x01 +#define PCI_CLASS_DISPLAY_XGA 0x01 +#define PCI_CLASS_DISPLAY_3D 0x02 +#define PCI_CLASS_DISPLAY_OTHER 0x80 + +#define PCI_CLASS_MEDIA 0x04 +#define PCI_CLASS_MEDIA_VIDEO 0x00 +#define PCI_CLASS_MEDIA_AUDIO 0x01 +#define PCI_CLASS_MEDIA_TELEPHONE 0x02 +#define PCI_CLASS_MEDIA_OTHER 0x80 + +#define PCI_CLASS_MEMORY_CONTROLLER 0x05 +#define PCI_CLASS_MEMORY_RAM 0x00 +#define PCI_CLASS_MEMORY_FLASH 0x01 +#define PCI_CLASS_MEMORY_OTHER 0x80 + +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x00 +#define PCI_CLASS_BRIDGE_ISA 0x01 +#define PCI_CLASS_BRIDGE_EISA 0x02 +#define PCI_CLASS_BRIDGE_MCA 0x03 +#define PCI_CLASS_BRIDGE_P2P 0x04 +#define PCI_IF_BRIDGE_P2P 0x00 +#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01 +#define PCI_CLASS_BRIDGE_PCMCIA 0x05 +#define PCI_CLASS_BRIDGE_NUBUS 0x06 +#define PCI_CLASS_BRIDGE_CARDBUS 0x07 +#define PCI_CLASS_BRIDGE_RACEWAY 0x08 +#define PCI_CLASS_BRIDGE_OTHER 0x80 +#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80 + +#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers +#define PCI_SUBCLASS_SERIAL 0x00 +#define PCI_IF_GENERIC_XT 0x00 +#define PCI_IF_16450 0x01 +#define PCI_IF_16550 0x02 +#define PCI_IF_16650 0x03 +#define PCI_IF_16750 0x04 +#define PCI_IF_16850 0x05 +#define PCI_IF_16950 0x06 +#define PCI_SUBCLASS_PARALLEL 0x01 +#define PCI_IF_PARALLEL_PORT 0x00 +#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01 +#define PCI_IF_ECP_PARALLEL_PORT 0x02 +#define PCI_IF_1284_CONTROLLER 0x03 +#define PCI_IF_1284_DEVICE 0xFE +#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02 +#define PCI_SUBCLASS_MODEM 0x03 +#define PCI_IF_GENERIC_MODEM 0x00 +#define PCI_IF_16450_MODEM 0x01 +#define PCI_IF_16550_MODEM 0x02 +#define PCI_IF_16650_MODEM 0x03 +#define PCI_IF_16750_MODEM 0x04 +#define PCI_SUBCLASS_SCC_OTHER 0x80 + +#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08 +#define PCI_SUBCLASS_PIC 0x00 +#define PCI_IF_8259_PIC 0x00 +#define PCI_IF_ISA_PIC 0x01 +#define PCI_IF_EISA_PIC 0x02 +#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory. +#define PCI_IF_APIC_CONTROLLER2 0x20 +#define PCI_SUBCLASS_DMA 0x01 +#define PCI_IF_8237_DMA 0x00 +#define PCI_IF_ISA_DMA 0x01 +#define PCI_IF_EISA_DMA 0x02 +#define PCI_SUBCLASS_TIMER 0x02 +#define PCI_IF_8254_TIMER 0x00 +#define PCI_IF_ISA_TIMER 0x01 +#define PCI_IF_EISA_TIMER 0x02 +#define PCI_SUBCLASS_RTC 0x03 +#define PCI_IF_GENERIC_RTC 0x00 +#define PCI_IF_ISA_RTC 0x01 +#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller +#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80 + +#define PCI_CLASS_INPUT_DEVICE 0x09 +#define PCI_SUBCLASS_KEYBOARD 0x00 +#define PCI_SUBCLASS_PEN 0x01 +#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02 +#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03 +#define PCI_SUBCLASS_GAMEPORT 0x04 +#define PCI_IF_GAMEPORT 0x00 +#define PCI_IF_GAMEPORT1 0x10 +#define PCI_SUBCLASS_INPUT_OTHER 0x80 + +#define PCI_CLASS_DOCKING_STATION 0x0A +#define PCI_SUBCLASS_DOCKING_GENERIC 0x00 +#define PCI_SUBCLASS_DOCKING_OTHER 0x80 + +#define PCI_CLASS_PROCESSOR 0x0B +#define PCI_SUBCLASS_PROC_386 0x00 +#define PCI_SUBCLASS_PROC_486 0x01 +#define PCI_SUBCLASS_PROC_PENTIUM 0x02 +#define PCI_SUBCLASS_PROC_ALPHA 0x10 +#define PCI_SUBCLASS_PROC_POWERPC 0x20 +#define PCI_SUBCLASS_PROC_MIPS 0x30 +#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor + +#define PCI_CLASS_SERIAL 0x0C +#define PCI_CLASS_SERIAL_FIREWIRE 0x00 +#define PCI_IF_1394 0x00 +#define PCI_IF_1394_OPEN_HCI 0x10 +#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01 +#define PCI_CLASS_SERIAL_SSA 0x02 +#define PCI_CLASS_SERIAL_USB 0x03 +#define PCI_IF_UHCI 0x00 +#define PCI_IF_OHCI 0x10 +#define PCI_IF_USB_OTHER 0x80 +#define PCI_IF_USB_DEVICE 0xFE +#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04 +#define PCI_CLASS_SERIAL_SMB 0x05 + +#define PCI_CLASS_WIRELESS 0x0D +#define PCI_SUBCLASS_IRDA 0x00 +#define PCI_SUBCLASS_IR 0x01 +#define PCI_SUBCLASS_RF 0x10 +#define PCI_SUBCLASS_WIRELESS_OTHER 0x80 + +#define PCI_CLASS_INTELLIGENT_IO 0x0E + +#define PCI_CLASS_SATELLITE 0x0F +#define PCI_SUBCLASS_TV 0x01 +#define PCI_SUBCLASS_AUDIO 0x02 +#define PCI_SUBCLASS_VOICE 0x03 +#define PCI_SUBCLASS_DATA 0x04 + +#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller +#define PCI_SUBCLASS_NET_COMPUT 0x00 +#define PCI_SUBCLASS_ENTERTAINMENT 0x10 +#define PCI_SUBCLASS_SECURITY_OTHER 0x80 + +#define PCI_CLASS_DPIO 0x11 +#define PCI_SUBCLASS_DPIO 0x00 +#define PCI_SUBCLASS_DPIO_OTHER 0x80 + +/** + Macro that checks whether the Base Class code of device matched. + + @param _p Specified device. + @param c Base Class code needs matching. + + @retval TRUE Base Class code matches the specified device. + @retval FALSE Base Class code doesn't match the specified device. + +**/ +#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c)) +/** + Macro that checks whether the Base Class code and Sub-Class code of device matched. + + @param _p Specified device. + @param c Base Class code needs matching. + @param s Sub-Class code needs matching. + + @retval TRUE Base Class code and Sub-Class code match the specified device. + @retval FALSE Base Class code and Sub-Class code don't match the specified device. + +**/ +#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s))) +/** + Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched. + + @param _p Specified device. + @param c Base Class code needs matching. + @param s Sub-Class code needs matching. + @param p Interface code needs matching. + + @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device. + @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device. + +**/ +#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p))) + +/** + Macro that checks whether device is a display controller. + + @param _p Specified device. + + @retval TRUE Device is a display controller. + @retval FALSE Device is not a display controller. + +**/ +#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY) +/** + Macro that checks whether device is a VGA-compatible controller. + + @param _p Specified device. + + @retval TRUE Device is a VGA-compatible controller. + @retval FALSE Device is not a VGA-compatible controller. + +**/ +#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA) +/** + Macro that checks whether device is an 8514-compatible controller. + + @param _p Specified device. + + @retval TRUE Device is an 8514-compatible controller. + @retval FALSE Device is not an 8514-compatible controller. + +**/ +#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514) +/** + Macro that checks whether device is built before the Class Code field was defined. + + @param _p Specified device. + + @retval TRUE Device is an old device. + @retval FALSE Device is not an old device. + +**/ +#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD) +/** + Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined. + + @param _p Specified device. + + @retval TRUE Device is an old VGA-compatible device. + @retval FALSE Device is not an old VGA-compatible device. + +**/ +#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) +/** + Macro that checks whether device is an IDE controller. + + @param _p Specified device. + + @retval TRUE Device is an IDE controller. + @retval FALSE Device is not an IDE controller. + +**/ +#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE) +/** + Macro that checks whether device is a SCSI bus controller. + + @param _p Specified device. + + @retval TRUE Device is a SCSI bus controller. + @retval FALSE Device is not a SCSI bus controller. + +**/ +#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI) +/** + Macro that checks whether device is a RAID controller. + + @param _p Specified device. + + @retval TRUE Device is a RAID controller. + @retval FALSE Device is not a RAID controller. + +**/ +#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID) +/** + Macro that checks whether device is an ISA bridge. + + @param _p Specified device. + + @retval TRUE Device is an ISA bridge. + @retval FALSE Device is not an ISA bridge. + +**/ +#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA) +/** + Macro that checks whether device is a PCI-to-PCI bridge. + + @param _p Specified device. + + @retval TRUE Device is a PCI-to-PCI bridge. + @retval FALSE Device is not a PCI-to-PCI bridge. + +**/ +#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P) +/** + Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge. + + @param _p Specified device. + + @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge. + @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge. + +**/ +#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE) +/** + Macro that checks whether device is a 16550-compatible serial controller. + + @param _p Specified device. + + @retval TRUE Device is a 16550-compatible serial controller. + @retval FALSE Device is not a 16550-compatible serial controller. + +**/ +#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) +/** + Macro that checks whether device is a Universal Serial Bus controller. + + @param _p Specified device. + + @retval TRUE Device is a Universal Serial Bus controller. + @retval FALSE Device is not a Universal Serial Bus controller. + +**/ +#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB) + +// +// the definition of Header Type +// +#define HEADER_TYPE_DEVICE 0x00 +#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 +#define HEADER_TYPE_CARDBUS_BRIDGE 0x02 +#define HEADER_TYPE_MULTI_FUNCTION 0x80 +// +// Mask of Header type +// +#define HEADER_LAYOUT_CODE 0x7f +/** + Macro that checks whether device is a PCI-PCI bridge. + + @param _p Specified device. + + @retval TRUE Device is a PCI-PCI bridge. + @retval FALSE Device is not a PCI-PCI bridge. + +**/ +#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE)) +/** + Macro that checks whether device is a CardBus bridge. + + @param _p Specified device. + + @retval TRUE Device is a CardBus bridge. + @retval FALSE Device is not a CardBus bridge. + +**/ +#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) +/** + Macro that checks whether device is a multiple functions device. + + @param _p Specified device. + + @retval TRUE Device is a multiple functions device. + @retval FALSE Device is not a multiple functions device. + +**/ +#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) + +/// +/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification, +/// +#define PCI_BRIDGE_ROMBAR 0x38 + +#define PCI_MAX_BAR 0x0006 +#define PCI_MAX_CONFIG_OFFSET 0x0100 + +#define PCI_VENDOR_ID_OFFSET 0x00 +#define PCI_DEVICE_ID_OFFSET 0x02 +#define PCI_COMMAND_OFFSET 0x04 +#define PCI_PRIMARY_STATUS_OFFSET 0x06 +#define PCI_REVISION_ID_OFFSET 0x08 +#define PCI_CLASSCODE_OFFSET 0x09 +#define PCI_CACHELINE_SIZE_OFFSET 0x0C +#define PCI_LATENCY_TIMER_OFFSET 0x0D +#define PCI_HEADER_TYPE_OFFSET 0x0E +#define PCI_BIST_OFFSET 0x0F +#define PCI_BASE_ADDRESSREG_OFFSET 0x10 +#define PCI_CARDBUS_CIS_OFFSET 0x28 +#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id +#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C +#define PCI_SID_OFFSET 0x2E ///< SubSystem ID +#define PCI_SUBSYSTEM_ID_OFFSET 0x2E +#define PCI_EXPANSION_ROM_BASE 0x30 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 +#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register +#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register +#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register +#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register + +// +// defined in PCI-to-PCI Bridge Architecture Specification +// +#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18 +#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19 +#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a +#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b +#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E +#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E + +/// +/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system +/// +#define PCI_INT_LINE_UNKNOWN 0xFF + +/// +/// PCI Access Data Format +/// +typedef union { + struct { + UINT32 Reg : 8; + UINT32 Func : 3; + UINT32 Dev : 5; + UINT32 Bus : 8; + UINT32 Reserved : 7; + UINT32 Enable : 1; + } Bits; + UINT32 Uint32; +} PCI_CONFIG_ACCESS_CF8; + +#pragma pack() + +#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001 +#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002 +#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004 +#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008 +#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010 +#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020 +#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040 +#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080 +#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100 +#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200 + +// +// defined in PCI-to-PCI Bridge Architecture Specification +// +#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001 +#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002 +#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004 +#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008 +#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010 +#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020 +#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040 +#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080 +#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100 +#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200 +#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400 +#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800 + +// +// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard +// +#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080 +#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100 +#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200 +#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400 + +// +// Following are the PCI status control bit +// +#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010 +#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020 +#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080 +#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100 + +/// +/// defined in PC Card Standard +/// +#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14 + +#pragma pack(1) +// +// PCI Capability List IDs and records +// +#define EFI_PCI_CAPABILITY_ID_PMI 0x01 +#define EFI_PCI_CAPABILITY_ID_AGP 0x02 +#define EFI_PCI_CAPABILITY_ID_VPD 0x03 +#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04 +#define EFI_PCI_CAPABILITY_ID_MSI 0x05 +#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06 +#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C + +/// +/// Capabilities List Header +/// Section 6.7, PCI Local Bus Specification, 2.2 +/// +typedef struct { + UINT8 CapabilityID; + UINT8 NextItemPtr; +} EFI_PCI_CAPABILITY_HDR; + +/// +/// PMC - Power Management Capabilities +/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2 +/// +typedef union { + struct { + UINT16 Version : 3; + UINT16 PmeClock : 1; + UINT16 Reserved : 1; + UINT16 DeviceSpecificInitialization : 1; + UINT16 AuxCurrent : 3; + UINT16 D1Support : 1; + UINT16 D2Support : 1; + UINT16 PmeSupport : 5; + } Bits; + UINT16 Data; +} EFI_PCI_PMC; + +#define EFI_PCI_PMC_D3_COLD_MASK (BIT15) + +/// +/// PMCSR - Power Management Control/Status +/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2 +/// +typedef union { + struct { + UINT16 PowerState : 2; + UINT16 ReservedForPciExpress : 1; + UINT16 NoSoftReset : 1; + UINT16 Reserved : 4; + UINT16 PmeEnable : 1; + UINT16 DataSelect : 4; + UINT16 DataScale : 2; + UINT16 PmeStatus : 1; + } Bits; + UINT16 Data; +} EFI_PCI_PMCSR; + +#define PCI_POWER_STATE_D0 0 +#define PCI_POWER_STATE_D1 1 +#define PCI_POWER_STATE_D2 2 +#define PCI_POWER_STATE_D3_HOT 3 + +/// +/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions +/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2 +/// +typedef union { + struct { + UINT8 Reserved : 6; + UINT8 B2B3 : 1; + UINT8 BusPowerClockControl : 1; + } Bits; + UINT8 Uint8; +} EFI_PCI_PMCSR_BSE; + +/// +/// Power Management Register Block Definition +/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + EFI_PCI_PMC PMC; + EFI_PCI_PMCSR PMCSR; + EFI_PCI_PMCSR_BSE BridgeExtention; + UINT8 Data; +} EFI_PCI_CAPABILITY_PMI; + +/// +/// A.G.P Capability +/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT8 Rev; + UINT8 Reserved; + UINT32 Status; + UINT32 Command; +} EFI_PCI_CAPABILITY_AGP; + +/// +/// VPD Capability Structure +/// Appendix I, PCI Local Bus Specification, 2.2 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT16 AddrReg; + UINT32 DataReg; +} EFI_PCI_CAPABILITY_VPD; + +/// +/// Slot Numbering Capabilities Register +/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT8 ExpnsSlotReg; + UINT8 ChassisNo; +} EFI_PCI_CAPABILITY_SLOTID; + +/// +/// Message Capability Structure for 32-bit Message Address +/// Section 6.8.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT16 MsgCtrlReg; + UINT32 MsgAddrReg; + UINT16 MsgDataReg; +} EFI_PCI_CAPABILITY_MSI32; + +/// +/// Message Capability Structure for 64-bit Message Address +/// Section 6.8.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT16 MsgCtrlReg; + UINT32 MsgAddrRegLsdw; + UINT32 MsgAddrRegMsdw; + UINT16 MsgDataReg; +} EFI_PCI_CAPABILITY_MSI64; + +/// +/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, +/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + /// + /// not finished - fields need to go here + /// +} EFI_PCI_CAPABILITY_HOTPLUG; + +#define PCI_BAR_IDX0 0x00 +#define PCI_BAR_IDX1 0x01 +#define PCI_BAR_IDX2 0x02 +#define PCI_BAR_IDX3 0x03 +#define PCI_BAR_IDX4 0x04 +#define PCI_BAR_IDX5 0x05 + +/// +/// EFI PCI Option ROM definitions +/// +#define EFI_ROOT_BRIDGE_LIST 'eprb' +#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec. + +#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55 +#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R') +#define PCI_CODE_TYPE_PCAT_IMAGE 0x00 +#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec. + +/// +/// Standard PCI Expansion ROM Header +/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1 +/// +typedef struct { + UINT16 Signature; ///< 0xaa55 + UINT8 Reserved[0x16]; + UINT16 PcirOffset; +} PCI_EXPANSION_ROM_HEADER; + +/// +/// Legacy ROM Header Extensions +/// Section 6.3.3.1, PCI Local Bus Specification, 2.2 +/// +typedef struct { + UINT16 Signature; ///< 0xaa55 + UINT8 Size512; + UINT8 InitEntryPoint[3]; + UINT8 Reserved[0x12]; + UINT16 PcirOffset; +} EFI_LEGACY_EXPANSION_ROM_HEADER; + +/// +/// PCI Data Structure Format +/// Section 6.3.1.2, PCI Local Bus Specification, 2.2 +/// +typedef struct { + UINT32 Signature; ///< "PCIR" + UINT16 VendorId; + UINT16 DeviceId; + UINT16 Reserved0; + UINT16 Length; + UINT8 Revision; + UINT8 ClassCode[3]; + UINT16 ImageLength; + UINT16 CodeRevision; + UINT8 CodeType; + UINT8 Indicator; + UINT16 Reserved1; +} PCI_DATA_STRUCTURE; + +/// +/// EFI PCI Expansion ROM Header +/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1 +/// +typedef struct { + UINT16 Signature; ///< 0xaa55 + UINT16 InitializationSize; + UINT32 EfiSignature; ///< 0x0EF1 + UINT16 EfiSubsystem; + UINT16 EfiMachineType; + UINT16 CompressionType; + UINT8 Reserved[8]; + UINT16 EfiImageHeaderOffset; + UINT16 PcirOffset; +} EFI_PCI_EXPANSION_ROM_HEADER; + +typedef union { + UINT8 *Raw; + PCI_EXPANSION_ROM_HEADER *Generic; + EFI_PCI_EXPANSION_ROM_HEADER *Efi; + EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt; +} EFI_PCI_ROM_HEADER; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci23.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci23.h new file mode 100644 index 0000000000..0ce38eb867 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci23.h @@ -0,0 +1,127 @@ +/** @file + Support for PCI 2.3 standard. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCI23_H_ +#define _PCI23_H_ + +#include + +/// +/// PCI_CLASS_MASS_STORAGE, Base Class 01h. +/// +///@{ +#define PCI_CLASS_MASS_STORAGE_ATA 0x05 +#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20 +#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30 +///@} + +/// +/// PCI_CLASS_NETWORK, Base Class 02h. +/// +///@{ +#define PCI_CLASS_NETWORK_WORLDFIP 0x05 +#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06 +///@} + +/// +/// PCI_CLASS_BRIDGE, Base Class 06h. +/// +///@{ +#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09 +#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40 +#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80 +#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A +///@} + +/// +/// PCI_CLASS_SCC, Base Class 07h. +/// +///@{ +#define PCI_SUBCLASS_GPIB 0x04 +#define PCI_SUBCLASS_SMART_CARD 0x05 +///@} + +/// +/// PCI_CLASS_SERIAL, Base Class 0Ch. +/// +///@{ +#define PCI_IF_EHCI 0x20 +#define PCI_CLASS_SERIAL_IB 0x06 +#define PCI_CLASS_SERIAL_IPMI 0x07 +#define PCI_IF_IPMI_SMIC 0x00 +#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style +#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer +#define PCI_CLASS_SERIAL_SERCOS 0x08 +#define PCI_CLASS_SERIAL_CANBUS 0x09 +///@} + +/// +/// PCI_CLASS_WIRELESS, Base Class 0Dh. +/// +///@{ +#define PCI_SUBCLASS_BLUETOOTH 0x11 +#define PCI_SUBCLASS_BROADBAND 0x12 +///@} + +/// +/// PCI_CLASS_DPIO, Base Class 11h. +/// +///@{ +#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01 +#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10 +#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20 +///@} + +/// +/// defined in PCI Express Spec. +/// +#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000 + +/// +/// PCI Capability List IDs and records. +/// +#define EFI_PCI_CAPABILITY_ID_PCIX 0x07 +#define EFI_PCI_CAPABILITY_ID_VENDOR 0x09 + +#pragma pack(1) +/// +/// PCI-X Capabilities List, +/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT16 CommandReg; + UINT32 StatusReg; +} EFI_PCI_CAPABILITY_PCIX; + +/// +/// PCI-X Bridge Capabilities List, +/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT16 SecStatusReg; + UINT32 StatusReg; + UINT32 SplitTransCtrlRegUp; + UINT32 SplitTransCtrlRegDn; +} EFI_PCI_CAPABILITY_PCIX_BRDG; + +/// +/// Vendor Specific Capability Header +/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3 +/// +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + UINT8 Length; +} EFI_PCI_CAPABILITY_VENDOR_HDR; + +#pragma pack() + +#define PCI_CODE_TYPE_EFI_IMAGE 0x03 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci30.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci30.h new file mode 100644 index 0000000000..beefb1aeb4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci30.h @@ -0,0 +1,73 @@ +/** @file + Support for PCI 3.0 standard. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI30_H__ +#define __PCI30_H__ + + +#include + +/// +/// PCI_CLASS_MASS_STORAGE, Base Class 01h. +/// +///@{ +#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06 +#define PCI_IF_MASS_STORAGE_SATA 0x00 +#define PCI_IF_MASS_STORAGE_AHCI 0x01 +///@} + +/// +/// PCI_CLASS_WIRELESS, Base Class 0Dh. +/// +///@{ +#define PCI_SUBCLASS_ETHERNET_80211A 0x20 +#define PCI_SUBCLASS_ETHERNET_80211B 0x21 +///@} + +/** + Macro that checks whether device is a SATA controller. + + @param _p Specified device. + + @retval TRUE Device is a SATA controller. + @retval FALSE Device is not a SATA controller. + +**/ +#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA) + +/// +/// PCI Capability List IDs and records +/// +#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10 + +#pragma pack(1) + +/// +/// PCI Data Structure Format +/// Section 5.1.2, PCI Firmware Specification, Revision 3.0 +/// +typedef struct { + UINT32 Signature; ///< "PCIR" + UINT16 VendorId; + UINT16 DeviceId; + UINT16 DeviceListOffset; + UINT16 Length; + UINT8 Revision; + UINT8 ClassCode[3]; + UINT16 ImageLength; + UINT16 CodeRevision; + UINT8 CodeType; + UINT8 Indicator; + UINT16 MaxRuntimeImageLength; + UINT16 ConfigUtilityCodeHeaderOffset; + UINT16 DMTFCLPEntryPointOffset; +} PCI_3_0_DATA_STRUCTURE; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciCodeId.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciCodeId.h new file mode 100644 index 0000000000..e5b63c3f42 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciCodeId.h @@ -0,0 +1,94 @@ +/** @file + The file lists the PCI class codes only defined in PCI code and ID assignment specification + revision 1.3. + + Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_CODE_ID_H__ +#define __PCI_CODE_ID_H__ + + +/// +/// PCI_CLASS_MASS_STORAGE, Base Class 01h. +/// +///@{ +#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00 +#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11 +#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12 +#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13 +#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21 +#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02 +#define PCI_CLASS_MASS_STORAGE_SAS 0x07 +#define PCI_IF_MASS_STORAGE_SAS 0x00 +#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01 +#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08 +#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00 +#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01 +#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02 +///@} + +/// +/// PCI_CLASS_NETWORK, Base Class 02h. +/// +///@{ +#define PCI_CLASS_NETWORK_INFINIBAND 0x07 +///@} + +/// +/// PCI_CLASS_MEDIA, Base Class 04h. +/// +///@{ +#define PCI_CLASS_MEDIA_MIXED_MODE 0x03 +///@} + +/// +/// PCI_CLASS_BRIDGE, Base Class 06h. +/// +///@{ +#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B +#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00 +#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01 +///@} + +/// +/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h. +/// +///@{ +#define PCI_IF_HPET 0x03 +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_SUBCLASS_IOMMU 0x06 +///@} + +/// +/// PCI_CLASS_PROCESSOR, Base Class 0Bh. +/// +///@{ +#define PCI_SUBCLASS_PROC_OTHER 0x80 +///@} + +/// +/// PCI_CLASS_SERIAL, Base Class 0Ch. +/// +///@{ +#define PCI_IF_XHCI 0x30 +#define PCI_CLASS_SERIAL_OTHER 0x80 +///@} + +/// +/// PCI_CLASS_SATELLITE, Base Class 0Fh. +/// +///@{ +#define PCI_SUBCLASS_SATELLITE_OTHER 0x80 +///@} + +/// +/// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h. +/// +///@{ +#define PCI_CLASS_PROCESSING_ACCELERATOR 0x12 +///@} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress21.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress21.h new file mode 100644 index 0000000000..dbe6349dea --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -0,0 +1,715 @@ +/** @file + Support for the latest PCI standard. + + Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS21_H_ +#define _PCIEXPRESS21_H_ + +#include + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits + of Bus, Device, Function and Register are stripped prior to the generation of + the address. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..4095. + + @return The encode ECAM address. + +**/ +#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +#pragma pack(1) +/// +/// PCI Express Capability Structure +/// +typedef union { + struct { + UINT16 Version : 4; + UINT16 DevicePortType : 4; + UINT16 SlotImplemented : 1; + UINT16 InterruptMessageNumber : 5; + UINT16 Undefined : 1; + UINT16 Reserved : 1; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_CAPABILITY; + +#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0 +#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1 +#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4 +#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5 +#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6 +#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7 +#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8 +#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9 +#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10 + +typedef union { + struct { + UINT32 MaxPayloadSize : 3; + UINT32 PhantomFunctions : 2; + UINT32 ExtendedTagField : 1; + UINT32 EndpointL0sAcceptableLatency : 3; + UINT32 EndpointL1AcceptableLatency : 3; + UINT32 Undefined : 3; + UINT32 RoleBasedErrorReporting : 1; + UINT32 Reserved : 2; + UINT32 CapturedSlotPowerLimitValue : 8; + UINT32 CapturedSlotPowerLimitScale : 2; + UINT32 FunctionLevelReset : 1; + UINT32 Reserved2 : 3; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_DEVICE_CAPABILITY; + +typedef union { + struct { + UINT16 CorrectableError : 1; + UINT16 NonFatalError : 1; + UINT16 FatalError : 1; + UINT16 UnsupportedRequest : 1; + UINT16 RelaxedOrdering : 1; + UINT16 MaxPayloadSize : 3; + UINT16 ExtendedTagField : 1; + UINT16 PhantomFunctions : 1; + UINT16 AuxPower : 1; + UINT16 NoSnoop : 1; + UINT16 MaxReadRequestSize : 3; + UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_DEVICE_CONTROL; + +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 + +#define PCIE_MAX_READ_REQ_SIZE_128B 0 +#define PCIE_MAX_READ_REQ_SIZE_256B 1 +#define PCIE_MAX_READ_REQ_SIZE_512B 2 +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 + +typedef union { + struct { + UINT16 CorrectableError : 1; + UINT16 NonFatalError : 1; + UINT16 FatalError : 1; + UINT16 UnsupportedRequest : 1; + UINT16 AuxPower : 1; + UINT16 TransactionsPending : 1; + UINT16 Reserved : 10; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_DEVICE_STATUS; + +typedef union { + struct { + UINT32 MaxLinkSpeed : 4; + UINT32 MaxLinkWidth : 6; + UINT32 Aspm : 2; + UINT32 L0sExitLatency : 3; + UINT32 L1ExitLatency : 3; + UINT32 ClockPowerManagement : 1; + UINT32 SurpriseDownError : 1; + UINT32 DataLinkLayerLinkActive : 1; + UINT32 LinkBandwidthNotification : 1; + UINT32 AspmOptionalityCompliance : 1; + UINT32 Reserved : 1; + UINT32 PortNumber : 8; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_LINK_CAPABILITY; + +#define PCIE_LINK_ASPM_L0S BIT0 +#define PCIE_LINK_ASPM_L1 BIT1 + +typedef union { + struct { + UINT16 AspmControl : 2; + UINT16 Reserved : 1; + UINT16 ReadCompletionBoundary : 1; + UINT16 LinkDisable : 1; + UINT16 RetrainLink : 1; + UINT16 CommonClockConfiguration : 1; + UINT16 ExtendedSynch : 1; + UINT16 ClockPowerManagement : 1; + UINT16 HardwareAutonomousWidthDisable : 1; + UINT16 LinkBandwidthManagementInterrupt : 1; + UINT16 LinkAutonomousBandwidthInterrupt : 1; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_LINK_CONTROL; + +typedef union { + struct { + UINT16 CurrentLinkSpeed : 4; + UINT16 NegotiatedLinkWidth : 6; + UINT16 Undefined : 1; + UINT16 LinkTraining : 1; + UINT16 SlotClockConfiguration : 1; + UINT16 DataLinkLayerLinkActive : 1; + UINT16 LinkBandwidthManagement : 1; + UINT16 LinkAutonomousBandwidth : 1; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_LINK_STATUS; + +typedef union { + struct { + UINT32 AttentionButton : 1; + UINT32 PowerController : 1; + UINT32 MrlSensor : 1; + UINT32 AttentionIndicator : 1; + UINT32 PowerIndicator : 1; + UINT32 HotPlugSurprise : 1; + UINT32 HotPlugCapable : 1; + UINT32 SlotPowerLimitValue : 8; + UINT32 SlotPowerLimitScale : 2; + UINT32 ElectromechanicalInterlock : 1; + UINT32 NoCommandCompleted : 1; + UINT32 PhysicalSlotNumber : 13; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_SLOT_CAPABILITY; + +typedef union { + struct { + UINT16 AttentionButtonPressed : 1; + UINT16 PowerFaultDetected : 1; + UINT16 MrlSensorChanged : 1; + UINT16 PresenceDetectChanged : 1; + UINT16 CommandCompletedInterrupt : 1; + UINT16 HotPlugInterrupt : 1; + UINT16 AttentionIndicator : 2; + UINT16 PowerIndicator : 2; + UINT16 PowerController : 1; + UINT16 ElectromechanicalInterlock : 1; + UINT16 DataLinkLayerStateChanged : 1; + UINT16 Reserved : 3; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_SLOT_CONTROL; + +typedef union { + struct { + UINT16 AttentionButtonPressed : 1; + UINT16 PowerFaultDetected : 1; + UINT16 MrlSensorChanged : 1; + UINT16 PresenceDetectChanged : 1; + UINT16 CommandCompleted : 1; + UINT16 MrlSensor : 1; + UINT16 PresenceDetect : 1; + UINT16 ElectromechanicalInterlock : 1; + UINT16 DataLinkLayerStateChanged : 1; + UINT16 Reserved : 7; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_SLOT_STATUS; + +typedef union { + struct { + UINT16 SystemErrorOnCorrectableError : 1; + UINT16 SystemErrorOnNonFatalError : 1; + UINT16 SystemErrorOnFatalError : 1; + UINT16 PmeInterrupt : 1; + UINT16 CrsSoftwareVisibility : 1; + UINT16 Reserved : 11; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_ROOT_CONTROL; + +typedef union { + struct { + UINT16 CrsSoftwareVisibility : 1; + UINT16 Reserved : 15; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_ROOT_CAPABILITY; + +typedef union { + struct { + UINT32 PmeRequesterId : 16; + UINT32 PmeStatus : 1; + UINT32 PmePending : 1; + UINT32 Reserved : 14; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_ROOT_STATUS; + +typedef union { + struct { + UINT32 CompletionTimeoutRanges : 4; + UINT32 CompletionTimeoutDisable : 1; + UINT32 AriForwarding : 1; + UINT32 AtomicOpRouting : 1; + UINT32 AtomicOp32Completer : 1; + UINT32 AtomicOp64Completer : 1; + UINT32 Cas128Completer : 1; + UINT32 NoRoEnabledPrPrPassing : 1; + UINT32 LtrMechanism : 1; + UINT32 TphCompleter : 2; + UINT32 LnSystemCLS : 2; + UINT32 TenBitTagCompleterSupported : 1; + UINT32 TenBitTagRequesterSupported : 1; + UINT32 Obff : 2; + UINT32 ExtendedFmtField : 1; + UINT32 EndEndTlpPrefix : 1; + UINT32 MaxEndEndTlpPrefixes : 2; + UINT32 EmergencyPowerReductionSupported : 2; + UINT32 EmergencyPowerReductionInitializationRequired : 1; + UINT32 Reserved3 : 4; + UINT32 FrsSupported : 1; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_DEVICE_CAPABILITY2; + +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 + +#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 +#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 + +typedef union { + struct { + UINT16 CompletionTimeoutValue : 4; + UINT16 CompletionTimeoutDisable : 1; + UINT16 AriForwarding : 1; + UINT16 AtomicOpRequester : 1; + UINT16 AtomicOpEgressBlocking : 1; + UINT16 IdoRequest : 1; + UINT16 IdoCompletion : 1; + UINT16 LtrMechanism : 1; + UINT16 EmergencyPowerReductionRequest : 1; + UINT16 TenBitTagRequesterEnable : 1; + UINT16 Obff : 2; + UINT16 EndEndTlpPrefixBlocking : 1; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_DEVICE_CONTROL2; + +#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0 +#define PCIE_COMPLETION_TIMEOUT_50US_100US 1 +#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2 +#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5 +#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6 +#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9 +#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10 +#define PCIE_COMPLETION_TIMEOUT_4S_13S 13 +#define PCIE_COMPLETION_TIMEOUT_17S_64S 14 + +#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0 +#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1 +#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2 +#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3 + +typedef union { + struct { + UINT32 Reserved : 1; + UINT32 LinkSpeedsVector : 7; + UINT32 Crosslink : 1; + UINT32 Reserved2 : 23; + } Bits; + UINT32 Uint32; +} PCI_REG_PCIE_LINK_CAPABILITY2; + +typedef union { + struct { + UINT16 TargetLinkSpeed : 4; + UINT16 EnterCompliance : 1; + UINT16 HardwareAutonomousSpeedDisable : 1; + UINT16 SelectableDeemphasis : 1; + UINT16 TransmitMargin : 3; + UINT16 EnterModifiedCompliance : 1; + UINT16 ComplianceSos : 1; + UINT16 CompliancePresetDeemphasis : 4; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_LINK_CONTROL2; + +typedef union { + struct { + UINT16 CurrentDeemphasisLevel : 1; + UINT16 EqualizationComplete : 1; + UINT16 EqualizationPhase1Successful : 1; + UINT16 EqualizationPhase2Successful : 1; + UINT16 EqualizationPhase3Successful : 1; + UINT16 LinkEqualizationRequest : 1; + UINT16 Reserved : 10; + } Bits; + UINT16 Uint16; +} PCI_REG_PCIE_LINK_STATUS2; + +typedef struct { + EFI_PCI_CAPABILITY_HDR Hdr; + PCI_REG_PCIE_CAPABILITY Capability; + PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability; + PCI_REG_PCIE_DEVICE_CONTROL DeviceControl; + PCI_REG_PCIE_DEVICE_STATUS DeviceStatus; + PCI_REG_PCIE_LINK_CAPABILITY LinkCapability; + PCI_REG_PCIE_LINK_CONTROL LinkControl; + PCI_REG_PCIE_LINK_STATUS LinkStatus; + PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability; + PCI_REG_PCIE_SLOT_CONTROL SlotControl; + PCI_REG_PCIE_SLOT_STATUS SlotStatus; + PCI_REG_PCIE_ROOT_CONTROL RootControl; + PCI_REG_PCIE_ROOT_CAPABILITY RootCapability; + PCI_REG_PCIE_ROOT_STATUS RootStatus; + PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2; + PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2; + UINT16 DeviceStatus2; + PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2; + PCI_REG_PCIE_LINK_CONTROL2 LinkControl2; + PCI_REG_PCIE_LINK_STATUS2 LinkStatus2; + UINT32 SlotCapability2; + UINT16 SlotControl2; + UINT16 SlotStatus2; +} PCI_CAPABILITY_PCIEXP; + +#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10 +#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24 +#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20 +#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28 +#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20 + +// +// for SR-IOV +// +#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E +#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F +#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10 +#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11 + +typedef struct { + UINT32 CapabilityHeader; + UINT32 Capability; + UINT16 Control; + UINT16 Status; + UINT16 InitialVFs; + UINT16 TotalVFs; + UINT16 NumVFs; + UINT8 FunctionDependencyLink; + UINT8 Reserved0; + UINT16 FirstVFOffset; + UINT16 VFStride; + UINT16 Reserved1; + UINT16 VFDeviceID; + UINT32 SupportedPageSize; + UINT32 SystemPageSize; + UINT32 VFBar[6]; + UINT32 VFMigrationStateArrayOffset; +} SR_IOV_CAPABILITY_REGISTER; + +#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A +#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C +#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E +#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A +#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C +#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38 +#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C + +typedef struct { + UINT32 CapabilityId:16; + UINT32 CapabilityVersion:4; + UINT32 NextCapabilityOffset:12; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER; + +#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2 + +typedef union { + struct { + UINT32 Undefined : 1; + UINT32 Reserved : 3; + UINT32 DataLinkProtocolError : 1; + UINT32 SurpriseDownError : 1; + UINT32 Reserved2 : 6; + UINT32 PoisonedTlp : 1; + UINT32 FlowControlProtocolError : 1; + UINT32 CompletionTimeout : 1; + UINT32 CompleterAbort : 1; + UINT32 UnexpectedCompletion : 1; + UINT32 ReceiverOverflow : 1; + UINT32 MalformedTlp : 1; + UINT32 EcrcError : 1; + UINT32 UnsupportedRequestError : 1; + UINT32 AcsVoilation : 1; + UINT32 UncorrectableInternalError : 1; + UINT32 McBlockedTlp : 1; + UINT32 AtomicOpEgressBlocked : 1; + UINT32 TlpPrefixBlockedError : 1; + UINT32 Reserved3 : 6; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus; + PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask; + PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity; + UINT32 CorrectableErrorStatus; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 HeaderLog[4]; + UINT32 RootErrorCommand; + UINT32 RootErrorStatus; + UINT16 ErrorSourceIdentification; + UINT16 CorrectableErrorSourceIdentification; + UINT32 TlpPrefixLog[4]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1 + +typedef struct { + UINT32 VcResourceCapability:24; + UINT32 PortArbTableOffset:8; + UINT32 VcResourceControl; + UINT16 Reserved1; + UINT16 VcResourceStatus; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 ExtendedVcCount:3; + UINT32 PortVcCapability1:29; + UINT32 PortVcCapability2:24; + UINT32 VcArbTableOffset:8; + UINT16 PortVcControl; + UINT16 PortVcStatus; + PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT64 SerialNumber; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 ElementSelfDescription; + UINT32 Reserved; + UINT32 LinkEntry[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 RootComplexLinkCapabilities; + UINT16 RootComplexLinkControl; + UINT16 RootComplexLinkStatus; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 DataSelect:8; + UINT32 Reserved:24; + UINT32 Data; + UINT32 PowerBudgetCapability:1; + UINT32 Reserved2:7; + UINT32 Reserved3:24; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 AcsCapability; + UINT16 AcsControl; + UINT8 EgressControlVectorArray[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020)) +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00)) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 AssociationBitmap; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1 + +typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 VendorSpecificHeader; + UINT8 VendorSpecific[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 VendorId; + UINT16 DeviceId; + UINT32 RcrbCapabilities; + UINT32 RcrbControl; + UINT32 Reserved; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 MultiCastCapability; + UINT16 MulticastControl; + UINT64 McBaseAddress; + UINT64 McReceiveAddress; + UINT64 McBlockAll; + UINT64 McBlockUntranslated; + UINT64 McOverlayBar; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1 + +typedef union { + struct { + UINT32 Reserved:4; + UINT32 BarSizeCapability:28; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY; + + +typedef union { + struct { + UINT32 BarIndex:3; + UINT32 Reserved:2; + UINT32 ResizableBarNumber:3; + UINT32 BarSize:6; + UINT32 Reserved2:2; + UINT32 BarSizeCapability:16; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability; + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR; + +#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 AriCapability; + UINT16 AriControl; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 DpaCapability; + UINT32 DpaLatencyIndicator; + UINT16 DpaStatus; + UINT16 DpaControl; + UINT8 DpaPowerAllocationArray[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F)) + + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 MaxSnoopLatency; + UINT16 MaxNoSnoopLatency; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 TphRequesterCapability; + UINT32 TphRequesterControl; + UINT16 TphStTable[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH; + +#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16) + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress30.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress30.h new file mode 100644 index 0000000000..2e52e0782a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress30.h @@ -0,0 +1,51 @@ +/** @file + Support for the PCI Express 3.0 standard. + + This header file may not define all structures. Please extend as required. + + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS30_H_ +#define _PCIEXPRESS30_H_ + +#include + +#pragma pack(1) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1 + +typedef union { + struct { + UINT32 PerformEqualization : 1; + UINT32 LinkEqualizationRequestInterruptEnable : 1; + UINT32 Reserved : 30; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_LINK_CONTROL3; + +typedef union { + struct { + UINT16 DownstreamPortTransmitterPreset : 4; + UINT16 DownstreamPortReceiverPresetHint : 3; + UINT16 Reserved : 1; + UINT16 UpstreamPortTransmitterPreset : 4; + UINT16 UpstreamPortReceiverPresetHint : 3; + UINT16 Reserved2 : 1; + } Bits; + UINT16 Uint16; +} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3; + UINT32 LaneErrorStatus; + PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress31.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress31.h new file mode 100644 index 0000000000..2e5e097be9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress31.h @@ -0,0 +1,72 @@ +/** @file +Support for the PCI Express 3.1 standard. + +This header file may not define all structures. Please extend as required. + +Copyright (c) 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS31_H_ +#define _PCIEXPRESS31_H_ + +#include + +#pragma pack(1) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E +#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1 + +typedef union { + struct { + UINT32 PciPmL12 : 1; + UINT32 PciPmL11 : 1; + UINT32 AspmL12 : 1; + UINT32 AspmL11 : 1; + UINT32 L1PmSubstates : 1; + UINT32 Reserved : 3; + UINT32 CommonModeRestoreTime : 8; + UINT32 TPowerOnScale : 2; + UINT32 Reserved2 : 1; + UINT32 TPowerOnValue : 5; + UINT32 Reserved3 : 8; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY; + +typedef union { + struct { + UINT32 PciPmL12 : 1; + UINT32 PciPmL11 : 1; + UINT32 AspmL12 : 1; + UINT32 AspmL11 : 1; + UINT32 Reserved : 4; + UINT32 CommonModeRestoreTime : 8; + UINT32 LtrL12ThresholdValue : 10; + UINT32 Reserved2 : 3; + UINT32 LtrL12ThresholdScale : 3; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1; + +typedef union { + struct { + UINT32 TPowerOnScale : 2; + UINT32 Reserved : 1; + UINT32 TPowerOnValue : 5; + UINT32 Reserved2 : 24; + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability; + PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1; + PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress40.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress40.h new file mode 100644 index 0000000000..a76f1bd5ae --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -0,0 +1,111 @@ +/** @file +Support for the PCI Express 4.0 standard. + +This header file may not define all structures. Please extend as required. + +Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS40_H_ +#define _PCIEXPRESS40_H_ + +#include + +#pragma pack(1) + +/// The Physical Layer PCI Express Extended Capability definitions. +/// +/// Based on section 7.7.5 of PCI Express Base Specification 4.0. +///@{ +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1 + +// Register offsets from Physical Layer PCI-E Ext Cap Header +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20 + +typedef union { + struct { + UINT32 Reserved : 32; // Reserved bit 0:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES; + +typedef union { + struct { + UINT32 Reserved : 32; // Reserved bit 0:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL; + +typedef union { + struct { + UINT32 EqualizationComplete : 1; // bit 0 + UINT32 EqualizationPhase1Success : 1; // bit 1 + UINT32 EqualizationPhase2Success : 1; // bit 2 + UINT32 EqualizationPhase3Success : 1; // bit 3 + UINT32 LinkEqualizationRequest : 1; // bit 4 + UINT32 Reserved : 27; // Reserved bit 5:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS; + +typedef union { + struct { + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 + } Bits; + UINT8 Uint8; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status; + UINT32 LocalDataParityMismatchStatus; + UINT32 FirstRetimerDataParityMismatchStatus; + UINT32 SecondRetimerDataParityMismatchStatus; + UINT32 Reserved; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; +///@} + +/// The Designated Vendor Specific Capability definitions +/// Based on section 7.9.6 of PCI Express Base Specification 4.0. +///@{ +typedef union { + struct { + UINT32 DvsecVendorId : 16; //bit 0..15 + UINT32 DvsecRevision : 4; //bit 16..19 + UINT32 DvsecLength : 12; //bit 20..31 + }Bits; + UINT32 Uint32; +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1; + +typedef union { + struct { + UINT16 DvsecId : 16; //bit 0..15 + }Bits; + UINT16 Uint16; +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; + UINT8 DesignatedVendorSpecific[1]; +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC; +///@} + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress50.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress50.h new file mode 100644 index 0000000000..3765875869 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PciExpress50.h @@ -0,0 +1,136 @@ +/** @file +Support for the PCI Express 5.0 standard. + +This header file may not define all structures. Please extend as required. + +Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIEXPRESS50_H_ +#define _PCIEXPRESS50_H_ + +#include + +#pragma pack(1) + +/// The Physical Layer PCI Express Extended Capability definitions. +/// +/// Based on section 7.7.6 of PCI Express Base Specification 5.0. +///@{ +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1 + +// Register offsets from Physical Layer PCI-E Ext Cap Header +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20 + +typedef union { + struct { + UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0 + UINT32 NoEqualizationNeededSupport : 1; // bit 1 + UINT32 Reserved1 : 6; // Reserved bit 2:7 + UINT32 ModifiedTSUsageMode0Support : 1; // bit 8 + UINT32 ModifiedTSUsageMode1Support : 1; // bit 9 + UINT32 ModifiedTSUsageMode2Support : 1; // bit 10 + UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15 + UINT32 Reserved2 : 16; // Reserved bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES; + +typedef union { + struct { + UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0 + UINT32 NoEqualizationNeededDisable : 1; // bit 1 + UINT32 Reserved1 : 6; // Reserved bit 2:7 + UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10 + UINT32 Reserved2 : 21; // Reserved bit 11:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL; + +typedef union { + struct { + UINT32 EqualizationComplete : 1; // bit 0 + UINT32 EqualizationPhase1Success : 1; // bit 1 + UINT32 EqualizationPhase2Success : 1; // bit 2 + UINT32 EqualizationPhase3Success : 1; // bit 3 + UINT32 LinkEqualizationRequest : 1; // bit 4 + UINT32 ModifiedTSRcvd : 1; // bit 5 + UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7 + UINT32 TransmitterPrecodingOn : 1; // bit 8 + UINT32 TransmitterPrecodeRequest : 1; // bit 9 + UINT32 NoEqualizationNeededRcvd : 1; // bit 10 + UINT32 Reserved : 21; // Reserved bit 11:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS; + +typedef union { + struct { + UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2 + UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15 + UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1; + +typedef union { + struct { + UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23 + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 + UINT32 Reserved : 6; // Reserved bit 26:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2; + +typedef union { + struct { + UINT32 TransModifiedTSUsageMode : 3; // bit 0:2 + UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15 + UINT32 TransModifiedTSVendorId : 16; // bit 16:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1; + +typedef union { + struct { + UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23 + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 + UINT32 Reserved : 6; // Reserved bit 26:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2; + +typedef union { + struct { + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 + } Bits; + UINT8 Uint8; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data; + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0; +///@} + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PeImage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PeImage.h new file mode 100644 index 0000000000..15a713ea06 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/PeImage.h @@ -0,0 +1,762 @@ +/** @file + EFI image format for PE32, PE32+ and TE. Please note some data structures are + different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and + EFI_IMAGE_NT_HEADERS64 is for PE32+. + + This file is coded to the Visual Studio, Microsoft Portable Executable and + Common Object File Format Specification, Revision 8.3 - February 6, 2013. + This file also includes some definitions in PI Specification, Revision 1.0. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PE_IMAGE_H__ +#define __PE_IMAGE_H__ + +// +// PE32+ Subsystem type for EFI images +// +#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10 +#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 +#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 +#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13 ///< defined PI Specification, 1.0 + + +// +// PE32+ Machine type for EFI images +// +#define IMAGE_FILE_MACHINE_I386 0x014c +#define IMAGE_FILE_MACHINE_IA64 0x0200 +#define IMAGE_FILE_MACHINE_EBC 0x0EBC +#define IMAGE_FILE_MACHINE_X64 0x8664 +#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2 +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 +#define IMAGE_FILE_MACHINE_RISCV128 0x5128 + +// +// EXE file formats +// +#define EFI_IMAGE_DOS_SIGNATURE SIGNATURE_16('M', 'Z') +#define EFI_IMAGE_OS2_SIGNATURE SIGNATURE_16('N', 'E') +#define EFI_IMAGE_OS2_SIGNATURE_LE SIGNATURE_16('L', 'E') +#define EFI_IMAGE_NT_SIGNATURE SIGNATURE_32('P', 'E', '\0', '\0') + +/// +/// PE images can start with an optional DOS header, so if an image is run +/// under DOS it can print an error message. +/// +typedef struct { + UINT16 e_magic; ///< Magic number. + UINT16 e_cblp; ///< Bytes on last page of file. + UINT16 e_cp; ///< Pages in file. + UINT16 e_crlc; ///< Relocations. + UINT16 e_cparhdr; ///< Size of header in paragraphs. + UINT16 e_minalloc; ///< Minimum extra paragraphs needed. + UINT16 e_maxalloc; ///< Maximum extra paragraphs needed. + UINT16 e_ss; ///< Initial (relative) SS value. + UINT16 e_sp; ///< Initial SP value. + UINT16 e_csum; ///< Checksum. + UINT16 e_ip; ///< Initial IP value. + UINT16 e_cs; ///< Initial (relative) CS value. + UINT16 e_lfarlc; ///< File address of relocation table. + UINT16 e_ovno; ///< Overlay number. + UINT16 e_res[4]; ///< Reserved words. + UINT16 e_oemid; ///< OEM identifier (for e_oeminfo). + UINT16 e_oeminfo; ///< OEM information; e_oemid specific. + UINT16 e_res2[10]; ///< Reserved words. + UINT32 e_lfanew; ///< File address of new exe header. +} EFI_IMAGE_DOS_HEADER; + +/// +/// COFF File Header (Object and Image). +/// +typedef struct { + UINT16 Machine; + UINT16 NumberOfSections; + UINT32 TimeDateStamp; + UINT32 PointerToSymbolTable; + UINT32 NumberOfSymbols; + UINT16 SizeOfOptionalHeader; + UINT16 Characteristics; +} EFI_IMAGE_FILE_HEADER; + +/// +/// Size of EFI_IMAGE_FILE_HEADER. +/// +#define EFI_IMAGE_SIZEOF_FILE_HEADER 20 + +// +// Characteristics +// +#define EFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 ///< 0x0001 Relocation info stripped from file. +#define EFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 ///< 0x0002 File is executable (i.e. no unresolved externel references). +#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED BIT2 ///< 0x0004 Line numbers stripped from file. +#define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED BIT3 ///< 0x0008 Local symbols stripped from file. +#define EFI_IMAGE_FILE_BYTES_REVERSED_LO BIT7 ///< 0x0080 Bytes of machine word are reversed. +#define EFI_IMAGE_FILE_32BIT_MACHINE BIT8 ///< 0x0100 32 bit word machine. +#define EFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 ///< 0x0200 Debugging info stripped from file in .DBG file. +#define EFI_IMAGE_FILE_SYSTEM BIT12 ///< 0x1000 System File. +#define EFI_IMAGE_FILE_DLL BIT13 ///< 0x2000 File is a DLL. +#define EFI_IMAGE_FILE_BYTES_REVERSED_HI BIT15 ///< 0x8000 Bytes of machine word are reversed. + +/// +/// Header Data Directories. +/// +typedef struct { + UINT32 VirtualAddress; + UINT32 Size; +} EFI_IMAGE_DATA_DIRECTORY; + +// +// Directory Entries +// +#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0 +#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1 +#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2 +#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3 +#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4 +#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5 +#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6 +#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7 +#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8 +#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9 +#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10 + +#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16 + +/// +/// @attention +/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and +/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary +/// after NT additional fields. +/// +#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b + +/// +/// Optional Header Standard Fields for PE32. +/// +typedef struct { + /// + /// Standard fields. + /// + UINT16 Magic; + UINT8 MajorLinkerVersion; + UINT8 MinorLinkerVersion; + UINT32 SizeOfCode; + UINT32 SizeOfInitializedData; + UINT32 SizeOfUninitializedData; + UINT32 AddressOfEntryPoint; + UINT32 BaseOfCode; + UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+. + /// + /// Optional Header Windows-Specific Fields. + /// + UINT32 ImageBase; + UINT32 SectionAlignment; + UINT32 FileAlignment; + UINT16 MajorOperatingSystemVersion; + UINT16 MinorOperatingSystemVersion; + UINT16 MajorImageVersion; + UINT16 MinorImageVersion; + UINT16 MajorSubsystemVersion; + UINT16 MinorSubsystemVersion; + UINT32 Win32VersionValue; + UINT32 SizeOfImage; + UINT32 SizeOfHeaders; + UINT32 CheckSum; + UINT16 Subsystem; + UINT16 DllCharacteristics; + UINT32 SizeOfStackReserve; + UINT32 SizeOfStackCommit; + UINT32 SizeOfHeapReserve; + UINT32 SizeOfHeapCommit; + UINT32 LoaderFlags; + UINT32 NumberOfRvaAndSizes; + EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES]; +} EFI_IMAGE_OPTIONAL_HEADER32; + +/// +/// @attention +/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and +/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary +/// after NT additional fields. +/// +#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b + +/// +/// Optional Header Standard Fields for PE32+. +/// +typedef struct { + /// + /// Standard fields. + /// + UINT16 Magic; + UINT8 MajorLinkerVersion; + UINT8 MinorLinkerVersion; + UINT32 SizeOfCode; + UINT32 SizeOfInitializedData; + UINT32 SizeOfUninitializedData; + UINT32 AddressOfEntryPoint; + UINT32 BaseOfCode; + /// + /// Optional Header Windows-Specific Fields. + /// + UINT64 ImageBase; + UINT32 SectionAlignment; + UINT32 FileAlignment; + UINT16 MajorOperatingSystemVersion; + UINT16 MinorOperatingSystemVersion; + UINT16 MajorImageVersion; + UINT16 MinorImageVersion; + UINT16 MajorSubsystemVersion; + UINT16 MinorSubsystemVersion; + UINT32 Win32VersionValue; + UINT32 SizeOfImage; + UINT32 SizeOfHeaders; + UINT32 CheckSum; + UINT16 Subsystem; + UINT16 DllCharacteristics; + UINT64 SizeOfStackReserve; + UINT64 SizeOfStackCommit; + UINT64 SizeOfHeapReserve; + UINT64 SizeOfHeapCommit; + UINT32 LoaderFlags; + UINT32 NumberOfRvaAndSizes; + EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES]; +} EFI_IMAGE_OPTIONAL_HEADER64; + + +/// +/// @attention +/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools. +/// +typedef struct { + UINT32 Signature; + EFI_IMAGE_FILE_HEADER FileHeader; + EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader; +} EFI_IMAGE_NT_HEADERS32; + +#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32) + +/// +/// @attention +/// EFI_IMAGE_HEADERS64 is for use ONLY by tools. +/// +typedef struct { + UINT32 Signature; + EFI_IMAGE_FILE_HEADER FileHeader; + EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader; +} EFI_IMAGE_NT_HEADERS64; + +#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64) + +// +// Other Windows Subsystem Values +// +#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0 +#define EFI_IMAGE_SUBSYSTEM_NATIVE 1 +#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2 +#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3 +#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5 +#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7 + +/// +/// Length of ShortName. +/// +#define EFI_IMAGE_SIZEOF_SHORT_NAME 8 + +/// +/// Section Table. This table immediately follows the optional header. +/// +typedef struct { + UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME]; + union { + UINT32 PhysicalAddress; + UINT32 VirtualSize; + } Misc; + UINT32 VirtualAddress; + UINT32 SizeOfRawData; + UINT32 PointerToRawData; + UINT32 PointerToRelocations; + UINT32 PointerToLinenumbers; + UINT16 NumberOfRelocations; + UINT16 NumberOfLinenumbers; + UINT32 Characteristics; +} EFI_IMAGE_SECTION_HEADER; + +/// +/// Size of EFI_IMAGE_SECTION_HEADER. +/// +#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40 + +// +// Section Flags Values +// +#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved. +#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020 +#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040 +#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080 + +#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved. +#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information. +#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image. +#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000 + +#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000 +#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000 +#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000 +#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000 +#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000 +#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000 +#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000 + +#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000 +#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000 +#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000 +#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000 +#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000 +#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000 +#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000 + +/// +/// Size of a Symbol Table Record. +/// +#define EFI_IMAGE_SIZEOF_SYMBOL 18 + +// +// Symbols have a section number of the section in which they are +// defined. Otherwise, section numbers have the following meanings: +// +#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common. +#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value. +#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item. + +// +// Symbol Type (fundamental) values. +// +#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type. +#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type. +#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character. +#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer. +#define EFI_IMAGE_SYM_TYPE_INT 4 +#define EFI_IMAGE_SYM_TYPE_LONG 5 +#define EFI_IMAGE_SYM_TYPE_FLOAT 6 +#define EFI_IMAGE_SYM_TYPE_DOUBLE 7 +#define EFI_IMAGE_SYM_TYPE_STRUCT 8 +#define EFI_IMAGE_SYM_TYPE_UNION 9 +#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration. +#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration. +#define EFI_IMAGE_SYM_TYPE_BYTE 12 +#define EFI_IMAGE_SYM_TYPE_WORD 13 +#define EFI_IMAGE_SYM_TYPE_UINT 14 +#define EFI_IMAGE_SYM_TYPE_DWORD 15 + +// +// Symbol Type (derived) values. +// +#define EFI_IMAGE_SYM_DTYPE_NULL 0 ///< no derived type. +#define EFI_IMAGE_SYM_DTYPE_POINTER 1 +#define EFI_IMAGE_SYM_DTYPE_FUNCTION 2 +#define EFI_IMAGE_SYM_DTYPE_ARRAY 3 + +// +// Storage classes. +// +#define EFI_IMAGE_SYM_CLASS_END_OF_FUNCTION ((UINT8) -1) +#define EFI_IMAGE_SYM_CLASS_NULL 0 +#define EFI_IMAGE_SYM_CLASS_AUTOMATIC 1 +#define EFI_IMAGE_SYM_CLASS_EXTERNAL 2 +#define EFI_IMAGE_SYM_CLASS_STATIC 3 +#define EFI_IMAGE_SYM_CLASS_REGISTER 4 +#define EFI_IMAGE_SYM_CLASS_EXTERNAL_DEF 5 +#define EFI_IMAGE_SYM_CLASS_LABEL 6 +#define EFI_IMAGE_SYM_CLASS_UNDEFINED_LABEL 7 +#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_STRUCT 8 +#define EFI_IMAGE_SYM_CLASS_ARGUMENT 9 +#define EFI_IMAGE_SYM_CLASS_STRUCT_TAG 10 +#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_UNION 11 +#define EFI_IMAGE_SYM_CLASS_UNION_TAG 12 +#define EFI_IMAGE_SYM_CLASS_TYPE_DEFINITION 13 +#define EFI_IMAGE_SYM_CLASS_UNDEFINED_STATIC 14 +#define EFI_IMAGE_SYM_CLASS_ENUM_TAG 15 +#define EFI_IMAGE_SYM_CLASS_MEMBER_OF_ENUM 16 +#define EFI_IMAGE_SYM_CLASS_REGISTER_PARAM 17 +#define EFI_IMAGE_SYM_CLASS_BIT_FIELD 18 +#define EFI_IMAGE_SYM_CLASS_BLOCK 100 +#define EFI_IMAGE_SYM_CLASS_FUNCTION 101 +#define EFI_IMAGE_SYM_CLASS_END_OF_STRUCT 102 +#define EFI_IMAGE_SYM_CLASS_FILE 103 +#define EFI_IMAGE_SYM_CLASS_SECTION 104 +#define EFI_IMAGE_SYM_CLASS_WEAK_EXTERNAL 105 + +// +// type packing constants +// +#define EFI_IMAGE_N_BTMASK 017 +#define EFI_IMAGE_N_TMASK 060 +#define EFI_IMAGE_N_TMASK1 0300 +#define EFI_IMAGE_N_TMASK2 0360 +#define EFI_IMAGE_N_BTSHFT 4 +#define EFI_IMAGE_N_TSHIFT 2 + +// +// Communal selection types. +// +#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1 +#define EFI_IMAGE_COMDAT_SELECT_ANY 2 +#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3 +#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4 +#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5 + +// +// the following values only be referred in PeCoff, not defined in PECOFF. +// +#define EFI_IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY 1 +#define EFI_IMAGE_WEAK_EXTERN_SEARCH_LIBRARY 2 +#define EFI_IMAGE_WEAK_EXTERN_SEARCH_ALIAS 3 + +/// +/// Relocation format. +/// +typedef struct { + UINT32 VirtualAddress; + UINT32 SymbolTableIndex; + UINT16 Type; +} EFI_IMAGE_RELOCATION; + +/// +/// Size of EFI_IMAGE_RELOCATION +/// +#define EFI_IMAGE_SIZEOF_RELOCATION 10 + +// +// I386 relocation types. +// +#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary. +#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address. +#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address. +#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address. +#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included. +#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address. +#define EFI_IMAGE_REL_I386_SECTION 0x000A +#define EFI_IMAGE_REL_I386_SECREL 0x000B +#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address. + +// +// x64 processor relocation types. +// +#define IMAGE_REL_AMD64_ABSOLUTE 0x0000 +#define IMAGE_REL_AMD64_ADDR64 0x0001 +#define IMAGE_REL_AMD64_ADDR32 0x0002 +#define IMAGE_REL_AMD64_ADDR32NB 0x0003 +#define IMAGE_REL_AMD64_REL32 0x0004 +#define IMAGE_REL_AMD64_REL32_1 0x0005 +#define IMAGE_REL_AMD64_REL32_2 0x0006 +#define IMAGE_REL_AMD64_REL32_3 0x0007 +#define IMAGE_REL_AMD64_REL32_4 0x0008 +#define IMAGE_REL_AMD64_REL32_5 0x0009 +#define IMAGE_REL_AMD64_SECTION 0x000A +#define IMAGE_REL_AMD64_SECREL 0x000B +#define IMAGE_REL_AMD64_SECREL7 0x000C +#define IMAGE_REL_AMD64_TOKEN 0x000D +#define IMAGE_REL_AMD64_SREL32 0x000E +#define IMAGE_REL_AMD64_PAIR 0x000F +#define IMAGE_REL_AMD64_SSPAN32 0x0010 + +/// +/// Based relocation format. +/// +typedef struct { + UINT32 VirtualAddress; + UINT32 SizeOfBlock; +} EFI_IMAGE_BASE_RELOCATION; + +/// +/// Size of EFI_IMAGE_BASE_RELOCATION. +/// +#define EFI_IMAGE_SIZEOF_BASE_RELOCATION 8 + +// +// Based relocation types. +// +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 +#define EFI_IMAGE_REL_BASED_HIGH 1 +#define EFI_IMAGE_REL_BASED_LOW 2 +#define EFI_IMAGE_REL_BASED_HIGHLOW 3 +#define EFI_IMAGE_REL_BASED_HIGHADJ 4 +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR16 9 +#define EFI_IMAGE_REL_BASED_DIR64 10 + +/// +/// Relocation types of RISC-V processor. +/// +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 + +/// +/// Line number format. +/// +typedef struct { + union { + UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0. + UINT32 VirtualAddress; ///< Virtual address of line number. + } Type; + UINT16 Linenumber; ///< Line number. +} EFI_IMAGE_LINENUMBER; + +/// +/// Size of EFI_IMAGE_LINENUMBER. +/// +#define EFI_IMAGE_SIZEOF_LINENUMBER 6 + +// +// Archive format. +// +#define EFI_IMAGE_ARCHIVE_START_SIZE 8 +#define EFI_IMAGE_ARCHIVE_START "!\n" +#define EFI_IMAGE_ARCHIVE_END "`\n" +#define EFI_IMAGE_ARCHIVE_PAD "\n" +#define EFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ " +#define EFI_IMAGE_ARCHIVE_LONGNAMES_MEMBER "// " + +/// +/// Archive Member Headers +/// +typedef struct { + UINT8 Name[16]; ///< File member name - `/' terminated. + UINT8 Date[12]; ///< File member date - decimal. + UINT8 UserID[6]; ///< File member user id - decimal. + UINT8 GroupID[6]; ///< File member group id - decimal. + UINT8 Mode[8]; ///< File member mode - octal. + UINT8 Size[10]; ///< File member size - decimal. + UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A). +} EFI_IMAGE_ARCHIVE_MEMBER_HEADER; + +/// +/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER. +/// +#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60 + + +// +// DLL Support +// + +/// +/// Export Directory Table. +/// +typedef struct { + UINT32 Characteristics; + UINT32 TimeDateStamp; + UINT16 MajorVersion; + UINT16 MinorVersion; + UINT32 Name; + UINT32 Base; + UINT32 NumberOfFunctions; + UINT32 NumberOfNames; + UINT32 AddressOfFunctions; + UINT32 AddressOfNames; + UINT32 AddressOfNameOrdinals; +} EFI_IMAGE_EXPORT_DIRECTORY; + +/// +/// Hint/Name Table. +/// +typedef struct { + UINT16 Hint; + UINT8 Name[1]; +} EFI_IMAGE_IMPORT_BY_NAME; + +/// +/// Import Address Table RVA (Thunk Table). +/// +typedef struct { + union { + UINT32 Function; + UINT32 Ordinal; + EFI_IMAGE_IMPORT_BY_NAME *AddressOfData; + } u1; +} EFI_IMAGE_THUNK_DATA; + +#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32. +#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0) +#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff) + +/// +/// Import Directory Table +/// +typedef struct { + UINT32 Characteristics; + UINT32 TimeDateStamp; + UINT32 ForwarderChain; + UINT32 Name; + EFI_IMAGE_THUNK_DATA *FirstThunk; +} EFI_IMAGE_IMPORT_DESCRIPTOR; + + +/// +/// Debug Directory Format. +/// +typedef struct { + UINT32 Characteristics; + UINT32 TimeDateStamp; + UINT16 MajorVersion; + UINT16 MinorVersion; + UINT32 Type; + UINT32 SizeOfData; + UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base. + UINT32 FileOffset; ///< The file pointer to the debug data. +} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY; + +#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information. + +/// +/// Debug Data Structure defined in Microsoft C++. +/// +#define CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0') +typedef struct { + UINT32 Signature; ///< "NB10" + UINT32 Unknown; + UINT32 Unknown2; + UINT32 Unknown3; + // + // Filename of .PDB goes here + // +} EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY; + +/// +/// Debug Data Structure defined in Microsoft C++. +/// +#define CODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S') +typedef struct { + UINT32 Signature; ///< "RSDS". + UINT32 Unknown; + UINT32 Unknown2; + UINT32 Unknown3; + UINT32 Unknown4; + UINT32 Unknown5; + // + // Filename of .PDB goes here + // +} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY; + + +/// +/// Debug Data Structure defined by Apple Mach-O to Coff utility. +/// +#define CODEVIEW_SIGNATURE_MTOC SIGNATURE_32('M', 'T', 'O', 'C') +typedef struct { + UINT32 Signature; ///< "MTOC". + GUID MachOUuid; + // + // Filename of .DLL (Mach-O with debug info) goes here + // +} EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY; + +/// +/// Resource format. +/// +typedef struct { + UINT32 Characteristics; + UINT32 TimeDateStamp; + UINT16 MajorVersion; + UINT16 MinorVersion; + UINT16 NumberOfNamedEntries; + UINT16 NumberOfIdEntries; + // + // Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here. + // +} EFI_IMAGE_RESOURCE_DIRECTORY; + +/// +/// Resource directory entry format. +/// +typedef struct { + union { + struct { + UINT32 NameOffset:31; + UINT32 NameIsString:1; + } s; + UINT32 Id; + } u1; + union { + UINT32 OffsetToData; + struct { + UINT32 OffsetToDirectory:31; + UINT32 DataIsDirectory:1; + } s; + } u2; +} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY; + +/// +/// Resource directory entry for string. +/// +typedef struct { + UINT16 Length; + CHAR16 String[1]; +} EFI_IMAGE_RESOURCE_DIRECTORY_STRING; + +/// +/// Resource directory entry for data array. +/// +typedef struct { + UINT32 OffsetToData; + UINT32 Size; + UINT32 CodePage; + UINT32 Reserved; +} EFI_IMAGE_RESOURCE_DATA_ENTRY; + +/// +/// Header format for TE images, defined in the PI Specification, 1.0. +/// +typedef struct { + UINT16 Signature; ///< The signature for TE format = "VZ". + UINT16 Machine; ///< From the original file header. + UINT8 NumberOfSections; ///< From the original file header. + UINT8 Subsystem; ///< From original optional header. + UINT16 StrippedSize; ///< Number of bytes we removed from the header. + UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header. + UINT32 BaseOfCode; ///< From original image -- required for ITP debug. + UINT64 ImageBase; ///< From original file header. + EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory. +} EFI_TE_IMAGE_HEADER; + + +#define EFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z') + +// +// Data directory indexes in our TE image header +// +#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0 +#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1 + + +/// +/// Union of PE32, PE32+, and TE headers. +/// +typedef union { + EFI_IMAGE_NT_HEADERS32 Pe32; + EFI_IMAGE_NT_HEADERS64 Pe32Plus; + EFI_TE_IMAGE_HEADER Te; +} EFI_IMAGE_OPTIONAL_HEADER_UNION; + +typedef union { + EFI_IMAGE_NT_HEADERS32 *Pe32; + EFI_IMAGE_NT_HEADERS64 *Pe32Plus; + EFI_TE_IMAGE_HEADER *Te; + EFI_IMAGE_OPTIONAL_HEADER_UNION *Union; +} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Scsi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Scsi.h new file mode 100644 index 0000000000..f49c55b036 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Scsi.h @@ -0,0 +1,426 @@ +/** @file + Support for SCSI-2 standard + + Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SCSI_H__ +#define __SCSI_H__ + +// +// SCSI command OP Code +// +// +// Commands for all device types +// +#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40 +#define EFI_SCSI_OP_COMPARE 0x39 +#define EFI_SCSI_OP_COPY 0x18 +#define EFI_SCSI_OP_COPY_VERIFY 0x3a +#define EFI_SCSI_OP_INQUIRY 0x12 +#define EFI_SCSI_OP_LOG_SELECT 0x4c +#define EFI_SCSI_OP_LOG_SENSE 0x4d +#define EFI_SCSI_OP_MODE_SEL6 0x15 +#define EFI_SCSI_OP_MODE_SEL10 0x55 +#define EFI_SCSI_OP_MODE_SEN6 0x1a +#define EFI_SCSI_OP_MODE_SEN10 0x5a +#define EFI_SCSI_OP_READ_BUFFER 0x3c +#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c +#define EFI_SCSI_OP_REQUEST_SENSE 0x03 +#define EFI_SCSI_OP_SEND_DIAG 0x1d +#define EFI_SCSI_OP_TEST_UNIT_READY 0x00 +#define EFI_SCSI_OP_WRITE_BUFF 0x3b + +// +// Additional commands for Direct Access Devices +// +#define EFI_SCSI_OP_FORMAT 0x04 +#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36 +#define EFI_SCSI_OP_PREFETCH 0x34 +#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e +#define EFI_SCSI_OP_READ6 0x08 +#define EFI_SCSI_OP_READ10 0x28 +#define EFI_SCSI_OP_READ16 0x88 +#define EFI_SCSI_OP_READ_CAPACITY 0x25 +#define EFI_SCSI_OP_READ_CAPACITY16 0x9e +#define EFI_SCSI_OP_READ_DEFECT 0x37 +#define EFI_SCSI_OP_READ_LONG 0x3e +#define EFI_SCSI_OP_REASSIGN_BLK 0x07 +#define EFI_SCSI_OP_RELEASE 0x17 +#define EFI_SCSI_OP_REZERO 0x01 +#define EFI_SCSI_OP_SEARCH_DATA_E 0x31 +#define EFI_SCSI_OP_SEARCH_DATA_H 0x30 +#define EFI_SCSI_OP_SEARCH_DATA_L 0x32 +#define EFI_SCSI_OP_SEEK6 0x0b +#define EFI_SCSI_OP_SEEK10 0x2b +#define EFI_SCSI_OP_SEND_DIAG 0x1d +#define EFI_SCSI_OP_SET_LIMIT 0x33 +#define EFI_SCSI_OP_START_STOP_UNIT 0x1b +#define EFI_SCSI_OP_SYNC_CACHE 0x35 +#define EFI_SCSI_OP_VERIFY 0x2f +#define EFI_SCSI_OP_WRITE6 0x0a +#define EFI_SCSI_OP_WRITE10 0x2a +#define EFI_SCSI_OP_WRITE16 0x8a +#define EFI_SCSI_OP_WRITE_VERIFY 0x2e +#define EFI_SCSI_OP_WRITE_LONG 0x3f +#define EFI_SCSI_OP_WRITE_SAME 0x41 +#define EFI_SCSI_OP_UNMAP 0x42 + +// +// Additional commands for Sequential Access Devices +// +#define EFI_SCSI_OP_ERASE 0x19 +#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b +#define EFI_SCSI_OP_LOCATE 0x2b +#define EFI_SCSI_OP_READ_BLOCK_LIMIT 0x05 +#define EFI_SCSI_OP_READ_POS 0x34 +#define EFI_SCSI_OP_READ_REVERSE 0x0f +#define EFI_SCSI_OP_RECOVER_BUF_DATA 0x14 +#define EFI_SCSI_OP_RESERVE_UNIT 0x16 +#define EFI_SCSI_OP_REWIND 0x01 +#define EFI_SCSI_OP_SPACE 0x11 +#define EFI_SCSI_OP_VERIFY_TAPE 0x13 +#define EFI_SCSI_OP_WRITE_FILEMARK 0x10 + +// +// Additional commands for Printer Devices +// +#define EFI_SCSI_OP_PRINT 0x0a +#define EFI_SCSI_OP_SLEW_PRINT 0x0b +#define EFI_SCSI_OP_STOP_PRINT 0x1b +#define EFI_SCSI_OP_SYNC_BUFF 0x10 + +// +// Additional commands for Processor Devices +// +#define EFI_SCSI_OP_RECEIVE 0x08 +#define EFI_SCSI_OP_SEND 0x0a + +// +// Additional commands for Write-Once Devices +// +#define EFI_SCSI_OP_MEDIUM_SCAN 0x38 +#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31 +#define EFI_SCSI_OP_SEARCH_DAT_E12 0xb1 +#define EFI_SCSI_OP_SEARCH_DAT_H10 0x30 +#define EFI_SCSI_OP_SEARCH_DAT_H12 0xb0 +#define EFI_SCSI_OP_SEARCH_DAT_L10 0x32 +#define EFI_SCSI_OP_SEARCH_DAT_L12 0xb2 +#define EFI_SCSI_OP_SET_LIMIT10 0x33 +#define EFI_SCSI_OP_SET_LIMIT12 0xb3 +#define EFI_SCSI_OP_VERIFY10 0x2f +#define EFI_SCSI_OP_VERIFY12 0xaf +#define EFI_SCSI_OP_WRITE12 0xaa +#define EFI_SCSI_OP_WRITE_VERIFY10 0x2e +#define EFI_SCSI_OP_WRITE_VERIFY12 0xae + +// +// Additional commands for CD-ROM Devices +// +#define EFI_SCSI_OP_PLAY_AUD_10 0x45 +#define EFI_SCSI_OP_PLAY_AUD_12 0xa5 +#define EFI_SCSI_OP_PLAY_AUD_MSF 0x47 +#define EFI_SCSI_OP_PLAY_AUD_TKIN 0x48 +#define EFI_SCSI_OP_PLAY_TK_REL10 0x49 +#define EFI_SCSI_OP_PLAY_TK_REL12 0xa9 +#define EFI_SCSI_OP_READ_CD_CAPACITY 0x25 +#define EFI_SCSI_OP_READ_HEADER 0x44 +#define EFI_SCSI_OP_READ_SUB_CHANNEL 0x42 +#define EFI_SCSI_OP_READ_TOC 0x43 + +// +// Additional commands for Scanner Devices +// +#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34 +#define EFI_SCSI_OP_GET_WINDOW 0x25 +#define EFI_SCSI_OP_OBJECT_POS 0x31 +#define EFI_SCSI_OP_SCAN 0x1b +#define EFI_SCSI_OP_SET_WINDOW 0x24 + +// +// Additional commands for Optical Memory Devices +// +#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d + +// +// Additional commands for Medium Changer Devices +// +#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6 +#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07 +#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b +#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5 +#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6 + +// +// Additional commands for Communication Devices +// +#define EFI_SCSI_OP_GET_MESSAGE6 0x08 +#define EFI_SCSI_OP_GET_MESSAGE10 0x28 +#define EFI_SCSI_OP_GET_MESSAGE12 0xa8 +#define EFI_SCSI_OP_SEND_MESSAGE6 0x0a +#define EFI_SCSI_OP_SEND_MESSAGE10 0x2a +#define EFI_SCSI_OP_SEND_MESSAGE12 0xaa + +// +// Additional commands for Secure Transactions +// +#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2 +#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5 + +// +// SCSI Data Transfer Direction +// +#define EFI_SCSI_DATA_IN 0 +#define EFI_SCSI_DATA_OUT 1 + +// +// SCSI Block Command Cache Control Parameters +// +#define EFI_SCSI_BLOCK_FUA BIT3 ///< Force Unit Access +#define EFI_SCSI_BLOCK_DPO BIT4 ///< Disable Page Out + +// +// Peripheral Device Type Definitions +// +#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk) +#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape) +#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device +#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device +#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks) +#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device +#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete) +#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks) +#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes) +#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete) +#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices) +#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices) +#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID) +#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device +#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk) +#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device +#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands +#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device +#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface +#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device +#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low) +#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high) +#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit +#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type + +// +// Page Codes for INQUIRY command +// +#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00 +#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0 + +#pragma pack(1) +/// +/// Standard INQUIRY data format +/// +typedef struct { + UINT8 Peripheral_Type : 5; + UINT8 Peripheral_Qualifier : 3; + UINT8 DeviceType_Modifier : 7; + UINT8 Rmb : 1; + UINT8 Version; + UINT8 Response_Data_Format; + UINT8 Addnl_Length; + UINT8 Reserved_5_95[95 - 5 + 1]; +} EFI_SCSI_INQUIRY_DATA; + +/// +/// Supported VPD Pages VPD page +/// +typedef struct { + UINT8 Peripheral_Type : 5; + UINT8 Peripheral_Qualifier : 3; + UINT8 PageCode; + UINT8 PageLength2; + UINT8 PageLength1; + UINT8 SupportedVpdPageList[0x100]; +} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE; + +/// +/// Block Limits VPD page +/// +typedef struct { + UINT8 Peripheral_Type : 5; + UINT8 Peripheral_Qualifier : 3; + UINT8 PageCode; + UINT8 PageLength2; + UINT8 PageLength1; + UINT8 WriteSameNonZero : 1; + UINT8 Reserved_4 : 7; + UINT8 MaximumCompareAndWriteLength; + UINT8 OptimalTransferLengthGranularity2; + UINT8 OptimalTransferLengthGranularity1; + UINT8 MaximumTransferLength4; + UINT8 MaximumTransferLength3; + UINT8 MaximumTransferLength2; + UINT8 MaximumTransferLength1; + UINT8 OptimalTransferLength4; + UINT8 OptimalTransferLength3; + UINT8 OptimalTransferLength2; + UINT8 OptimalTransferLength1; + UINT8 MaximumPrefetchXdreadXdwriteTransferLength4; + UINT8 MaximumPrefetchXdreadXdwriteTransferLength3; + UINT8 MaximumPrefetchXdreadXdwriteTransferLength2; + UINT8 MaximumPrefetchXdreadXdwriteTransferLength1; + UINT8 MaximumUnmapLbaCount4; + UINT8 MaximumUnmapLbaCount3; + UINT8 MaximumUnmapLbaCount2; + UINT8 MaximumUnmapLbaCount1; + UINT8 MaximumUnmapBlockDescriptorCount4; + UINT8 MaximumUnmapBlockDescriptorCount3; + UINT8 MaximumUnmapBlockDescriptorCount2; + UINT8 MaximumUnmapBlockDescriptorCount1; + UINT8 OptimalUnmapGranularity4; + UINT8 OptimalUnmapGranularity3; + UINT8 OptimalUnmapGranularity2; + UINT8 OptimalUnmapGranularity1; + UINT8 UnmapGranularityAlignment4 : 7; + UINT8 UnmapGranularityAlignmentValid : 1; + UINT8 UnmapGranularityAlignment3; + UINT8 UnmapGranularityAlignment2; + UINT8 UnmapGranularityAlignment1; + UINT8 MaximumWriteSameLength4; + UINT8 MaximumWriteSameLength3; + UINT8 MaximumWriteSameLength2; + UINT8 MaximumWriteSameLength1; + UINT8 MaximumAtomicTransferLength4; + UINT8 MaximumAtomicTransferLength3; + UINT8 MaximumAtomicTransferLength2; + UINT8 MaximumAtomicTransferLength1; + UINT8 AtomicAlignment4; + UINT8 AtomicAlignment3; + UINT8 AtomicAlignment2; + UINT8 AtomicAlignment1; + UINT8 AtomicTransferLengthGranularity4; + UINT8 AtomicTransferLengthGranularity3; + UINT8 AtomicTransferLengthGranularity2; + UINT8 AtomicTransferLengthGranularity1; + UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4; + UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3; + UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2; + UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1; + UINT8 MaximumAtomicBoundarySize4; + UINT8 MaximumAtomicBoundarySize3; + UINT8 MaximumAtomicBoundarySize2; + UINT8 MaximumAtomicBoundarySize1; +} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE; + +/// +/// Error codes 70h and 71h sense data format +/// +typedef struct { + UINT8 Error_Code : 7; + UINT8 Valid : 1; + UINT8 Segment_Number; + UINT8 Sense_Key : 4; + UINT8 Reserved_21 : 1; + UINT8 Ili : 1; + UINT8 Reserved_22 : 2; + UINT8 Information_3_6[4]; + UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7) + UINT8 Vendor_Specific_8_11[4]; + UINT8 Addnl_Sense_Code; ///< Additional sense code + UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier + UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code + UINT8 Reserved_15_17[3]; +} EFI_SCSI_SENSE_DATA; + +/// +/// SCSI Disk READ CAPACITY Data +/// +typedef struct { + UINT8 LastLba3; + UINT8 LastLba2; + UINT8 LastLba1; + UINT8 LastLba0; + UINT8 BlockSize3; + UINT8 BlockSize2; + UINT8 BlockSize1; + UINT8 BlockSize0; +} EFI_SCSI_DISK_CAPACITY_DATA; + +typedef struct { + UINT8 LastLba7; + UINT8 LastLba6; + UINT8 LastLba5; + UINT8 LastLba4; + UINT8 LastLba3; + UINT8 LastLba2; + UINT8 LastLba1; + UINT8 LastLba0; + UINT8 BlockSize3; + UINT8 BlockSize2; + UINT8 BlockSize1; + UINT8 BlockSize0; + UINT8 Protection; + UINT8 LogicPerPhysical; + UINT8 LowestAlignLogic2; + UINT8 LowestAlignLogic1; + UINT8 Reserved[16]; +} EFI_SCSI_DISK_CAPACITY_DATA16; + +typedef struct { + UINT16 DataLen; + UINT16 BlkDespDataLen; + UINT8 Reserved[4]; +} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER; + +typedef struct { + UINT64 Lba; + UINT32 BlockNum; + UINT8 Reserved[4]; +} EFI_SCSI_DISK_UNMAP_BLOCK_DESP; + + +#pragma pack() + +// +// Sense Key +// +#define EFI_SCSI_SK_NO_SENSE (0x0) +#define EFI_SCSI_SK_RECOVERY_ERROR (0x1) +#define EFI_SCSI_SK_NOT_READY (0x2) +#define EFI_SCSI_SK_MEDIUM_ERROR (0x3) +#define EFI_SCSI_SK_HARDWARE_ERROR (0x4) +#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5) +#define EFI_SCSI_SK_UNIT_ATTENTION (0x6) +#define EFI_SCSI_SK_DATA_PROTECT (0x7) +#define EFI_SCSI_SK_BLANK_CHECK (0x8) +#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9) +#define EFI_SCSI_SK_RESERVED_A (0xA) +#define EFI_SCSI_SK_ABORT (0xB) +#define EFI_SCSI_SK_RESERVED_C (0xC) +#define EFI_SCSI_SK_OVERFLOW (0xD) +#define EFI_SCSI_SK_MISCOMPARE (0xE) +#define EFI_SCSI_SK_RESERVED_F (0xF) + +// +// Additional Sense Codes and Sense Code Qualifiers. +// Only some frequently used additional sense codes and qualifiers are +// defined here. Please refer to SCSI standard for full value definition. +// +#define EFI_SCSI_ASC_NOT_READY (0x04) +#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01) + +#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10) +#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11) +#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14) +#define EFI_SCSI_ASC_MEDIA_ERR4 (0x30) +#define EFI_SCSI_ASC_MEDIA_UPSIDE_DOWN (0x06) +#define EFI_SCSI_ASC_INVALID_CMD (0x20) +#define EFI_SCSI_ASC_LBA_OUT_OF_RANGE (0x21) +#define EFI_SCSI_ASC_INVALID_FIELD (0x24) +#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27) +#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28) +#define EFI_SCSI_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred +#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26) +#define EFI_SCSI_ASC_NO_MEDIA (0x3A) +#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64) + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Sd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Sd.h new file mode 100644 index 0000000000..415aaf893d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Sd.h @@ -0,0 +1,175 @@ +/** @file + Header file for SD memory card support. + + This header file contains some definitions defined in SD Physical Layer Simplified + Specification Version 4.10 spec. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SD_H__ +#define __SD_H__ + +// +// SD command index +// +#define SD_GO_IDLE_STATE 0 +#define SD_ALL_SEND_CID 2 +#define SD_SET_RELATIVE_ADDR 3 +#define SD_SET_DSR 4 +#define SDIO_SEND_OP_COND 5 +#define SD_SWITCH_FUNC 6 +#define SD_SELECT_DESELECT_CARD 7 +#define SD_SEND_IF_COND 8 +#define SD_SEND_CSD 9 +#define SD_SEND_CID 10 +#define SD_VOLTAGE_SWITCH 11 +#define SD_STOP_TRANSMISSION 12 +#define SD_SEND_STATUS 13 +#define SD_GO_INACTIVE_STATE 15 +#define SD_SET_BLOCKLEN 16 +#define SD_READ_SINGLE_BLOCK 17 +#define SD_READ_MULTIPLE_BLOCK 18 +#define SD_SEND_TUNING_BLOCK 19 +#define SD_SPEED_CLASS_CONTROL 20 +#define SD_SET_BLOCK_COUNT 23 +#define SD_WRITE_SINGLE_BLOCK 24 +#define SD_WRITE_MULTIPLE_BLOCK 25 +#define SD_PROGRAM_CSD 27 +#define SD_SET_WRITE_PROT 28 +#define SD_CLR_WRITE_PROT 29 +#define SD_SEND_WRITE_PROT 30 +#define SD_ERASE_WR_BLK_START 32 +#define SD_ERASE_WR_BLK_END 33 +#define SD_ERASE 38 +#define SD_LOCK_UNLOCK 42 +#define SD_READ_EXTR_SINGLE 48 +#define SD_WRITE_EXTR_SINGLE 49 +#define SDIO_RW_DIRECT 52 +#define SDIO_RW_EXTENDED 53 +#define SD_APP_CMD 55 +#define SD_GEN_CMD 56 +#define SD_READ_EXTR_MULTI 58 +#define SD_WRITE_EXTR_MULTI 59 + +#define SD_SET_BUS_WIDTH 6 // ACMD6 +#define SD_STATUS 13 // ACMD13 +#define SD_SEND_NUM_WR_BLOCKS 22 // ACMD22 +#define SD_SET_WR_BLK_ERASE_COUNT 23 // ACMD23 +#define SD_SEND_OP_COND 41 // ACMD41 +#define SD_SET_CLR_CARD_DETECT 42 // ACMD42 +#define SD_SEND_SCR 51 // ACMD51 + +#pragma pack(1) +typedef struct { + UINT8 NotUsed:1; // Not used [0:0] + UINT8 Crc:7; // CRC [7:1] + UINT16 ManufacturingDate:12; // Manufacturing date [19:8] + UINT16 Reserved:4; // Reserved [23:20] + UINT8 ProductSerialNumber[4]; // Product serial number [55:24] + UINT8 ProductRevision; // Product revision [63:56] + UINT8 ProductName[5]; // Product name [103:64] + UINT8 OemId[2]; // OEM/Application ID [119:104] + UINT8 ManufacturerId; // Manufacturer ID [127:120] +} SD_CID; + +typedef struct { + UINT32 NotUsed:1; // Not used [0:0] + UINT32 Crc:7; // CRC [7:1] + UINT32 Reserved:2; // Reserved [9:8] + UINT32 FileFormat:2; // File format [11:10] + UINT32 TmpWriteProtect:1; // Temporary write protection [12:12] + UINT32 PermWriteProtect:1; // Permanent write protection [13:13] + UINT32 Copy:1; // Copy flag (OTP) [14:14] + UINT32 FileFormatGrp:1; // File format group [15:15] + UINT32 Reserved1:5; // Reserved [20:16] + UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21] + UINT32 WriteBlLen:4; // Max. write data block length [25:22] + UINT32 R2WFactor:3; // Write speed factor [28:26] + UINT32 Reserved2:2; // Manufacturer default ECC [30:29] + UINT32 WpGrpEnable:1; // Write protect group enable [31:31] + + UINT32 WpGrpSize:7; // Write protect group size [38:32] + UINT32 SectorSize:7; // Erase sector size [45:39] + UINT32 EraseBlkEn:1; // Erase single block enable [46:46] + UINT32 CSizeMul:3; // device size multiplier [49:47] + UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50] + UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53] + UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56] + UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59] + UINT32 CSizeLow:2; // Device size low 2 bits [63:62] + + UINT32 CSizeHigh:10; // Device size high 10 bits [73:64] + UINT32 Reserved4:2; // Reserved [75:74] + UINT32 DsrImp:1; // DSR implemented [76:76] + UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77] + UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78] + UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79] + UINT32 ReadBlLen:4; // Max. read data block length [83:80] + UINT32 Ccc:12; // Card command classes [95:84] + + UINT32 TranSpeed:8; // Max. data transfer rate [103:96] + UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104] + UINT32 Taac:8; // Data read access-time [119:112] + UINT32 Reserved5:6; // Reserved [125:120] + UINT32 CsdStructure:2; // CSD structure [127:126] +} SD_CSD; + +typedef struct { + UINT32 NotUsed:1; // Not used [0:0] + UINT32 Crc:7; // CRC [7:1] + UINT32 Reserved:2; // Reserved [9:8] + UINT32 FileFormat:2; // File format [11:10] + UINT32 TmpWriteProtect:1; // Temporary write protection [12:12] + UINT32 PermWriteProtect:1; // Permanent write protection [13:13] + UINT32 Copy:1; // Copy flag (OTP) [14:14] + UINT32 FileFormatGrp:1; // File format group [15:15] + UINT32 Reserved1:5; // Reserved [20:16] + UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21] + UINT32 WriteBlLen:4; // Max. write data block length [25:22] + UINT32 R2WFactor:3; // Write speed factor [28:26] + UINT32 Reserved2:2; // Manufacturer default ECC [30:29] + UINT32 WpGrpEnable:1; // Write protect group enable [31:31] + + UINT32 WpGrpSize:7; // Write protect group size [38:32] + UINT32 SectorSize:7; // Erase sector size [45:39] + UINT32 EraseBlkEn:1; // Erase single block enable [46:46] + UINT32 Reserved3:1; // Reserved [47:47] + UINT32 CSizeLow:16; // Device size low 16 bits [63:48] + + UINT32 CSizeHigh:6; // Device size high 6 bits [69:64] + UINT32 Reserved4:6; // Reserved [75:70] + UINT32 DsrImp:1; // DSR implemented [76:76] + UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77] + UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78] + UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79] + UINT32 ReadBlLen:4; // Max. read data block length [83:80] + UINT32 Ccc:12; // Card command classes [95:84] + + UINT32 TranSpeed:8; // Max. data transfer rate [103:96] + UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104] + UINT32 Taac:8; // Data read access-time [119:112] + UINT32 Reserved5:6; // Reserved [125:120] + UINT32 CsdStructure:2; // CSD structure [127:126] +} SD_CSD2; + +typedef struct { + UINT32 Reserved; // Reserved [31:0] + + UINT32 CmdSupport:4; // Command Support bits [35:32] + UINT32 Reserved1:6; // Reserved [41:36] + UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42] + UINT32 ExSecurity:4; // Extended Security Support [46:43] + UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47] + UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48] + UINT32 SdSecurity:3; // CPRM security support [54:52] + UINT32 DataStatAfterErase:1; // Data status after erases [55] + UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56] + UINT32 ScrStructure:4; // SCR Structure [63:60] +} SD_SCR; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpd.h new file mode 100644 index 0000000000..30958588a0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpd.h @@ -0,0 +1,68 @@ +/** @file + This file contains definitions for the SPD fields on an SDRAM. + + Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SDRAM_SPD_H_ +#define _SDRAM_SPD_H_ + +#include +#include +#include + +// +// SDRAM SPD field definitions +// +#define SPD_MEMORY_TYPE 2 +#define SPD_SDRAM_ROW_ADDR 3 +#define SPD_SDRAM_COL_ADDR 4 +#define SPD_SDRAM_MODULE_ROWS 5 +#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6 +#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7 +#define SPD_SDRAM_ECC_SUPPORT 11 +#define SPD_SDRAM_REFRESH 12 +#define SPD_SDRAM_WIDTH 13 +#define SPD_SDRAM_ERROR_WIDTH 14 +#define SPD_SDRAM_BURST_LENGTH 16 +#define SPD_SDRAM_NO_OF_BANKS 17 +#define SPD_SDRAM_CAS_LATENCY 18 +#define SPD_SDRAM_MODULE_ATTR 21 + +#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency +#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency +#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency +#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency +#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency +#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency +#define SPD_SDRAM_MIN_PRECHARGE 27 +#define SPD_SDRAM_ACTIVE_MIN 28 +#define SPD_SDRAM_RAS_CAS 29 +#define SPD_SDRAM_RAS_PULSE 30 +#define SPD_SDRAM_DENSITY 31 + +// +// Memory Type Definitions +// +#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory +#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory +#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory +#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory +#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory +#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory +#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory + +// +// ECC Type Definitions +// +#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking +#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking +#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only +// +// Module Attributes (Bit positions) +// +#define SPD_BUFFERED 0x01 +#define SPD_REGISTERED 0x02 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h new file mode 100644 index 0000000000..ae4a771faf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h @@ -0,0 +1,763 @@ +/** @file + This file contains definitions for SPD DDR3. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6 + http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf +**/ + +#ifndef _SDRAM_SPD_DDR3_H_ +#define _SDRAM_SPD_DDR3_H_ + +#pragma pack (push, 1) + +typedef union { + struct { + UINT8 BytesUsed : 4; ///< Bits 3:0 + UINT8 BytesTotal : 3; ///< Bits 6:4 + UINT8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + UINT8 Minor : 4; ///< Bits 3:0 + UINT8 Major : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_REVISION_STRUCT; + +typedef union { + struct { + UINT8 Type : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 3; ///< Bits 6:4 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 ColumnAddress : 3; ///< Bits 2:0 + UINT8 RowAddress : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_50 : 1; ///< Bits 0:0 + UINT8 OperationAt1_35 : 1; ///< Bits 1:1 + UINT8 OperationAt1_25 : 1; ///< Bits 2:2 + UINT8 Reserved : 5; ///< Bits 7:3 + } Bits; + UINT8 Data; +} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 4; ///< Bits 3:0 + UINT8 Dividend : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_FINE_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT8 Dividend : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT; + +typedef struct { + SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend + SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor +} SPD3_MEDIUM_TIMEBASE; + +typedef union { + struct { + UINT8 tCKmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 Cl4 : 1; ///< Bits 0:0 + UINT16 Cl5 : 1; ///< Bits 1:1 + UINT16 Cl6 : 1; ///< Bits 2:2 + UINT16 Cl7 : 1; ///< Bits 3:3 + UINT16 Cl8 : 1; ///< Bits 4:4 + UINT16 Cl9 : 1; ///< Bits 5:5 + UINT16 Cl10 : 1; ///< Bits 6:6 + UINT16 Cl11 : 1; ///< Bits 7:7 + UINT16 Cl12 : 1; ///< Bits 8:8 + UINT16 Cl13 : 1; ///< Bits 9:9 + UINT16 Cl14 : 1; ///< Bits 10:10 + UINT16 Cl15 : 1; ///< Bits 11:11 + UINT16 Cl16 : 1; ///< Bits 12:12 + UINT16 Cl17 : 1; ///< Bits 13:13 + UINT16 Cl18 : 1; ///< Bits 14:14 + UINT16 Reserved : 1; ///< Bits 15:15 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 tAAmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TWR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRRDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRRD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASminUpper : 4; ///< Bits 3:0 + UINT8 tRCminUpper : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_TRAS_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRAS_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCmin : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD3_TRFC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWTRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TWTR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRTPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TRTP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tFAWminUpper : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_TFAW_MIN_MTB_UPPER_STRUCT; + +typedef union { + struct { + UINT8 tFAWmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_TFAW_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 Rzq6 : 1; ///< Bits 0:0 + UINT8 Rzq7 : 1; ///< Bits 1:1 + UINT8 Reserved : 5; ///< Bits 6:2 + UINT8 DllOff : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0 + UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 + UINT8 AutoSelfRefresh : 1; ///< Bits 2:2 + UINT8 OnDieThermalSensor : 1; ///< Bits 3:3 + UINT8 Reserved : 3; ///< Bits 6:4 + UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 Reserved : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_SDRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + INT8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD3_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD3_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD3_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRPminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD3_TRP_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD3_TRC_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 VendorSpecific : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_UNBUF_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 MappingRank1 : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD3_UNBUF_ADDRESS_MAPPING; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_RDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 + UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD3_MANUFACTURER_ID_CODE; + +typedef union { + struct { + UINT8 RegisterRevisionNumber; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 Bit0 : 1; ///< Bits 0:0 + UINT8 Bit1 : 1; ///< Bits 1:1 + UINT8 Bit2 : 1; ///< Bits 2:2 + UINT8 Reserved : 5; ///< Bits 7:3 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_TYPE; + +typedef union { + struct { + UINT8 Reserved : 4; ///< Bits 0:3 + UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4 + UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1 + UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2 + UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 + UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK; + +typedef union { + struct { + UINT8 Reserved0 : 4; ///< Bits 0:3 + UINT8 Reserved1 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_RDIMM_REGISTER_CONTROL_RESERVED; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0 + UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1 + UINT8 Reserved0 : 1; ///< Bits 2:2 + UINT8 Reserved1 : 1; ///< Bits 3:3 + UINT8 AddressCommandOutputs : 2; ///< Bits 5:4 + UINT8 QxCS_nOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 QxOdtOutputs : 2; ///< Bits 1:0 + UINT8 QxCkeOutputs : 2; ///< Bits 3:2 + UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4 + UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 YExtendedDelay : 2; ///< Bits 1:0 + UINT8 QxCS_n : 2; ///< Bits 3:2 + UINT8 QxOdt : 2; ///< Bits 5:4 + UINT8 QxCke : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_EXTENDED_DELAY; + +typedef union { + struct { + UINT8 DelayY : 3; ///< Bits 2:0 + UINT8 Reserved : 1; ///< Bits 3:3 + UINT8 QxCS_n : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA; + +typedef union { + struct { + UINT8 QxCS_n : 4; ///< Bits 3:0 + UINT8 QxOdt : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE; + +typedef union { + struct { + UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0 + UINT8 RC8Reserved : 1; ///< Bits 3:3 + UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4 + UINT8 RC9Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0 + UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1 + UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2 + UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3 + UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4 + UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5 + UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6 + UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL; + +typedef union { + struct { + UINT8 Driver_Impedance : 2; ///< Bits 1:0 + UINT8 Rtt_Nom : 3; ///< Bits 4:2 + UINT8 Reserved : 1; ///< Bits 5:5 + UINT8 Rtt_WR : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MR_1_2; + +typedef union { + struct { + UINT8 MinimumDelayTime : 7; ///< Bits 0:6 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD3_LRDIMM_MODULE_DELAY_TIME; + +typedef struct { + UINT8 Year; ///< Year represented in BCD (00h = 2000) + UINT8 Week; ///< Year represented in BCD (47h = week 47) +} SPD3_MANUFACTURING_DATE; + +typedef union { + UINT32 Data; + UINT16 SerialNumber16[2]; + UINT8 SerialNumber8[4]; +} SPD3_MANUFACTURER_SERIAL_NUMBER; + +typedef struct { + UINT8 Location; ///< Module Manufacturing Location +} SPD3_MANUFACTURING_LOCATION; + +typedef struct { + SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code + SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location + SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) + SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number +} SPD3_UNIQUE_MODULE_ID; + +typedef union { + UINT16 Crc[1]; + UINT8 Data8[2]; +} SPD3_CYCLIC_REDUNDANCY_CODE; + +typedef struct { + SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD + SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization + SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width + SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor + SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend + SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin) + UINT8 Reserved0; ///< 13 Reserved + SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported + SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin) + SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin) + SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) + SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin) + SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC + SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin) + SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) + SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW + SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) + SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features + SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options + SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor + SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type + SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin) + SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved + SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value + UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved +} SPD3_BASE_SECTION; + +typedef struct { + SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM + UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved +} SPD3_MODULE_UNBUFFERED; + +typedef struct { + SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes + SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution + SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code + SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number + SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address + SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved + SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved + UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved +} SPD3_MODULE_REGISTERED; + +typedef struct { + SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved +} SPD3_MODULE_CLOCKED; + +typedef struct { + SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height + SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness + SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used + SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes + UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number + SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code + SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS + SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y + SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE + SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA + SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066 + SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066 + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V + SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V + SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V + UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved + UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes +} SPD3_MODULE_LOADREDUCED; + +typedef union { + SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types + SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types + SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types + SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types +} SPD3_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number +} SPD3_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code +} SPD3_MODULE_REVISION_CODE; + +typedef struct { + UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data +} SPD3_MANUFACTURER_SPECIFIC; + +/// +/// DDR3 Serial Presence Detect structure +/// +typedef struct { + SPD3_BASE_SECTION General; ///< 0-59 General Section + SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section + SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID + SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) + SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number + SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code + SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code + SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data + UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use +} SPD_DDR3; + +#pragma pack (pop) +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h new file mode 100644 index 0000000000..2eeb95ba2a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h @@ -0,0 +1,952 @@ +/** @file + This file contains definitions for SPD DDR4. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4 + http://www.jedec.org/standards-documents/docs/spd412l-4 +**/ + +#ifndef _SDRAM_SPD_DDR4_H_ +#define _SDRAM_SPD_DDR4_H_ + +#pragma pack (push, 1) + +typedef union { + struct { + UINT8 BytesUsed : 4; ///< Bits 3:0 + UINT8 BytesTotal : 3; ///< Bits 6:4 + UINT8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + UINT8 Minor : 4; ///< Bits 3:0 + UINT8 Major : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_REVISION_STRUCT; + +typedef union { + struct { + UINT8 Type : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 HybridMedia : 3; ///< Bits 6:4 + UINT8 Hybrid : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 ColumnAddress : 3; ///< Bits 2:0 + UINT8 RowAddress : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 Reserved : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramPackageType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 5; ///< Bits 4:0 + UINT8 SoftPPR : 1; ///< Bits 5:5 + UINT8 PostPackageRepair : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 DRAMDensityRatio : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramPackageType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 Reserved : 6; ///< Bits 7:2 + } Bits; + UINT8 Data; +} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 RankMix : 1; ///< Bits 6:6 + UINT8 Reserved : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_EXTENDED_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Fine : 2; ///< Bits 1:0 + UINT8 Medium : 2; ///< Bits 3:2 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT8 tCKmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tCKmax : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TCK_MAX_MTB_STRUCT; + +typedef union { + struct { + UINT32 Cl7 : 1; ///< Bits 0:0 + UINT32 Cl8 : 1; ///< Bits 1:1 + UINT32 Cl9 : 1; ///< Bits 2:2 + UINT32 Cl10 : 1; ///< Bits 3:3 + UINT32 Cl11 : 1; ///< Bits 4:4 + UINT32 Cl12 : 1; ///< Bits 5:5 + UINT32 Cl13 : 1; ///< Bits 6:6 + UINT32 Cl14 : 1; ///< Bits 7:7 + UINT32 Cl15 : 1; ///< Bits 8:8 + UINT32 Cl16 : 1; ///< Bits 9:9 + UINT32 Cl17 : 1; ///< Bits 10:10 + UINT32 Cl18 : 1; ///< Bits 11:11 + UINT32 Cl19 : 1; ///< Bits 12:12 + UINT32 Cl20 : 1; ///< Bits 13:13 + UINT32 Cl21 : 1; ///< Bits 14:14 + UINT32 Cl22 : 1; ///< Bits 15:15 + UINT32 Cl23 : 1; ///< Bits 16:16 + UINT32 Cl24 : 1; ///< Bits 17:17 + UINT32 Cl25 : 1; ///< Bits 18:18 + UINT32 Cl26 : 1; ///< Bits 19:19 + UINT32 Cl27 : 1; ///< Bits 20:20 + UINT32 Cl28 : 1; ///< Bits 21:21 + UINT32 Cl29 : 1; ///< Bits 22:22 + UINT32 Cl30 : 1; ///< Bits 23:23 + UINT32 Cl31 : 1; ///< Bits 24:24 + UINT32 Cl32 : 1; ///< Bits 25:25 + UINT32 Cl33 : 1; ///< Bits 26:26 + UINT32 Cl34 : 1; ///< Bits 27:27 + UINT32 Cl35 : 1; ///< Bits 28:28 + UINT32 Cl36 : 1; ///< Bits 29:29 + UINT32 Reserved : 1; ///< Bits 30:30 + UINT32 ClRange : 1; ///< Bits 31:31 + } Bits; + struct { + UINT32 Cl23 : 1; ///< Bits 0:0 + UINT32 Cl24 : 1; ///< Bits 1:1 + UINT32 Cl25 : 1; ///< Bits 2:2 + UINT32 Cl26 : 1; ///< Bits 3:3 + UINT32 Cl27 : 1; ///< Bits 4:4 + UINT32 Cl28 : 1; ///< Bits 5:5 + UINT32 Cl29 : 1; ///< Bits 6:6 + UINT32 Cl30 : 1; ///< Bits 7:7 + UINT32 Cl31 : 1; ///< Bits 8:8 + UINT32 Cl32 : 1; ///< Bits 9:9 + UINT32 Cl33 : 1; ///< Bits 10:10 + UINT32 Cl34 : 1; ///< Bits 11:11 + UINT32 Cl35 : 1; ///< Bits 12:12 + UINT32 Cl36 : 1; ///< Bits 13:13 + UINT32 Cl37 : 1; ///< Bits 14:14 + UINT32 Cl38 : 1; ///< Bits 15:15 + UINT32 Cl39 : 1; ///< Bits 16:16 + UINT32 Cl40 : 1; ///< Bits 17:17 + UINT32 Cl41 : 1; ///< Bits 18:18 + UINT32 Cl42 : 1; ///< Bits 19:19 + UINT32 Cl43 : 1; ///< Bits 20:20 + UINT32 Cl44 : 1; ///< Bits 21:21 + UINT32 Cl45 : 1; ///< Bits 22:22 + UINT32 Cl46 : 1; ///< Bits 23:23 + UINT32 Cl47 : 1; ///< Bits 24:24 + UINT32 Cl48 : 1; ///< Bits 25:25 + UINT32 Cl49 : 1; ///< Bits 26:26 + UINT32 Cl50 : 1; ///< Bits 27:27 + UINT32 Cl51 : 1; ///< Bits 28:28 + UINT32 Cl52 : 1; ///< Bits 29:29 + UINT32 Reserved : 1; ///< Bits 30:30 + UINT32 ClRange : 1; ///< Bits 31:31 + } HighRangeBits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 tAAmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TRP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASminUpper : 4; ///< Bits 3:0 + UINT8 tRCminUpper : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TRAS_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TRAS_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCmin : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD4_TRFC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tFAWminUpper : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TFAW_MIN_MTB_UPPER_STRUCT; + +typedef union { + struct { + UINT8 tFAWmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TFAW_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRRDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TRRD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tCCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TCCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TWR_UPPER_NIBBLE_STRUCT; + +typedef union { + struct { + UINT8 tWRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TWR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0 + UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TWTR_UPPER_NIBBLE_STRUCT; + +typedef union { + struct { + UINT8 tWTRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TWTR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0 + UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5 + UINT8 PackageRankMap : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT; + +typedef union { + struct { + INT8 tCCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TCCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRRDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TRRD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TRC_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRPminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TRP_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tCKmaxFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TCK_MAX_FTB_STRUCT; + +typedef union { + struct { + INT8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_UNBUF_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 MappingRank1 : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD4_UNBUF_ADDRESS_MAPPING; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_RDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 + UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD4_MANUFACTURER_ID_CODE; + +typedef union { + struct { + UINT8 RegisterRevisionNumber; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REGISTER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 Rank1Mapping : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; + +typedef union { + struct { + UINT8 Cke : 2; ///< Bits 1:0 + UINT8 Odt : 2; ///< Bits 3:2 + UINT8 CommandAddress : 2; ///< Bits 5:4 + UINT8 ChipSelect : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 Y0Y2 : 2; ///< Bits 1:0 + UINT8 Y1Y3 : 2; ///< Bits 3:2 + UINT8 Reserved0 : 2; ///< Bits 5:4 + UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6 + UINT8 Reserved1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 RegisterType : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0 + UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION; + +typedef union { + struct { + UINT8 RegisterRevisionNumber; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 Rank1Mapping : 1; ///< Bits 0:0 + UINT8 Reserved : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM; + +typedef union { + struct { + UINT8 Cke : 2; ///< Bits 1:0 + UINT8 Odt : 2; ///< Bits 3:2 + UINT8 CommandAddress : 2; ///< Bits 5:4 + UINT8 ChipSelect : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS; + +typedef union { + struct { + UINT8 Y0Y2 : 2; ///< Bits 1:0 + UINT8 Y1Y3 : 2; ///< Bits 3:2 + UINT8 Reserved0 : 2; ///< Bits 5:4 + UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6 + UINT8 Reserved1 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK; + +typedef struct { + UINT8 DataBufferRevisionNumber; +} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER; + +typedef union { + struct { + UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK; + +typedef struct { + UINT8 DataBufferVrefDQforDramInterface; +} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE; + +typedef union { + struct { + UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0 + UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 DataRateLe1866 : 2; ///< Bits 1:0 + UINT8 DataRateLe2400 : 2; ///< Bits 3:2 + UINT8 DataRateLe3200 : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH; + +typedef union { + struct { + UINT8 Rtt_Nom : 3; ///< Bits 2:0 + UINT8 Rtt_WR : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 PackageRanks0_1 : 3; ///< Bits 2:0 + UINT8 PackageRanks2_3 : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE; + +typedef union { + struct { + UINT8 Rank0 : 1; ///< Bits 0:0 + UINT8 Rank1 : 1; ///< Bits 1:1 + UINT8 Rank2 : 1; ///< Bits 2:2 + UINT8 Rank3 : 1; ///< Bits 3:3 + UINT8 DataBuffer : 1; ///< Bits 4:4 + UINT8 Reserved : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE; + +typedef union { + struct { + UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0 + UINT8 DataBufferDfe : 1; ///< Bits 1:1 + UINT8 Reserved : 6; ///< Bits 7:2 + } Bits; + UINT8 Data; +} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION; + +typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE; + +typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER; + +typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_NVDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 Reserved : 4; ///< Bits 3:0 + UINT8 Extension : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_NVDIMM_MODULE_CHARACTERISTICS; + +typedef struct { + UINT8 Reserved; + UINT8 MediaType; +} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES; + +typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME; + +typedef union { + struct { + UINT16 FunctionInterface : 5; ///< Bits 4:0 + UINT16 FunctionClass : 5; ///< Bits 9:5 + UINT16 BlockOffset : 4; ///< Bits 13:10 + UINT16 Reserved : 1; ///< Bits 14:14 + UINT16 Implemented : 1; ///< Bits 15:15 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR; + +typedef struct { + UINT8 Year; ///< Year represented in BCD (00h = 2000) + UINT8 Week; ///< Year represented in BCD (47h = week 47) +} SPD4_MANUFACTURING_DATE; + +typedef union { + UINT32 Data; + UINT16 SerialNumber16[2]; + UINT8 SerialNumber8[4]; +} SPD4_MANUFACTURER_SERIAL_NUMBER; + +typedef struct { + UINT8 Location; ///< Module Manufacturing Location +} SPD4_MANUFACTURING_LOCATION; + +typedef struct { + SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code + SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location + SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) + SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number +} SPD4_UNIQUE_MODULE_ID; + +typedef union { + UINT16 Crc[1]; + UINT8 Data8[2]; +} SPD4_CYCLIC_REDUNDANCY_CODE; + +typedef struct { + SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type + SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features + SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options + SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features + SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type + SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD + SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization + SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width + SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor + SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type + UINT8 Reserved0; ///< 16 Reserved + SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases + SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) + SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) + SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported + SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) + SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin) + SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC + SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min) + SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min) + SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min) + SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW + SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin) + SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group + SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group + SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group + SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin + SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin) + SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin + SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group + SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group + UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved + SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping + UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved + SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group + SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group + SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group + SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin) + SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) + SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin) + SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) +} SPD4_BASE_SECTION; + +typedef struct { + SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM + UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved + SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_UNBUFFERED; + +typedef struct { + SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes + SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution + SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code + SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number + SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM + SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address + SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock + UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved + SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_REGISTERED; + +typedef struct { + SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes + SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution + SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code + SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number + SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM + SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address + SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock + SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2 + SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3 + SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866 + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400 + SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200 + SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866 + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400 + SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400 + SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200 + SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range + SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization + UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved + SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_LOADREDUCED; + +typedef struct { + UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved + SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier + SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code + SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier + SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code + SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used + SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics + SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types + SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time + SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors + UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved + SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_NVDIMM; + +typedef union { + SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types + SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types + SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types + SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters +} SPD4_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number +} SPD4_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data +} SPD4_MANUFACTURER_SPECIFIC; + +typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code +typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping + +typedef struct { + SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID + SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number + SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code + SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code + SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping + SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data + UINT8 Reserved[2]; ///< 382-383 Reserved +} SPD4_MANUFACTURING_DATA; + +typedef struct { + UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types +} SPD4_END_USER_SECTION; + +/// +/// DDR4 Serial Presence Detect structure +/// +typedef struct { + SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters + SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section + UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved + SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information + SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable +} SPD_DDR4; + +#pragma pack (pop) +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h new file mode 100644 index 0000000000..4cc9241afd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h @@ -0,0 +1,468 @@ +/** @file + This file contains definitions for SPD LPDDR. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2 + http://www.jedec.org/standards-documents/docs/spd412m-2 +**/ + +#ifndef _SDRAM_SPD_LPDDR_H_ +#define _SDRAM_SPD_LPDDR_H_ + +#pragma pack (push, 1) + +typedef union { + struct { + UINT8 BytesUsed : 4; ///< Bits 3:0 + UINT8 BytesTotal : 3; ///< Bits 6:4 + UINT8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + UINT8 Minor : 4; ///< Bits 3:0 + UINT8 Major : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_REVISION_STRUCT; + +typedef union { + struct { + UINT8 Type : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 HybridMedia : 3; ///< Bits 6:4 + UINT8 Hybrid : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 ColumnAddress : 3; ///< Bits 2:0 + UINT8 RowAddress : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 ChannelsPerDie : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramPackageType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 MaximumActivateCount : 4; ///< Bits 3:0 + UINT8 MaximumActivateWindow : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 5; ///< Bits 4:0 + UINT8 SoftPPR : 1; ///< Bits 5:5 + UINT8 PostPackageRepair : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 OperationAt1_10 : 1; ///< Bits 2:2 + UINT8 EndurantAt1_10 : 1; ///< Bits 3:3 + UINT8 OperationAtTBD2V : 1; ///< Bits 4:4 + UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 NumberofChannels : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Reserved : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ChipSelectLoading : 3; ///< Bits 2:0 + UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3 + UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SIGNAL_LOADING_STRUCT; + +typedef union { + struct { + UINT8 Fine : 2; ///< Bits 1:0 + UINT8 Medium : 2; ///< Bits 3:2 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT8 tCKmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tCKmax : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TCK_MAX_MTB_STRUCT; + +typedef union { + struct { + UINT32 Cl3 : 1; ///< Bits 0:0 + UINT32 Cl6 : 1; ///< Bits 1:1 + UINT32 Cl8 : 1; ///< Bits 2:2 + UINT32 Cl9 : 1; ///< Bits 3:3 + UINT32 Cl10 : 1; ///< Bits 4:4 + UINT32 Cl11 : 1; ///< Bits 5:5 + UINT32 Cl12 : 1; ///< Bits 6:6 + UINT32 Cl14 : 1; ///< Bits 7:7 + UINT32 Cl16 : 1; ///< Bits 8:8 + UINT32 Reserved0 : 1; ///< Bits 9:9 + UINT32 Cl20 : 1; ///< Bits 10:10 + UINT32 Cl22 : 1; ///< Bits 11:11 + UINT32 Cl24 : 1; ///< Bits 12:12 + UINT32 Reserved1 : 1; ///< Bits 13:13 + UINT32 Cl28 : 1; ///< Bits 14:14 + UINT32 Reserved2 : 1; ///< Bits 15:15 + UINT32 Cl32 : 1; ///< Bits 16:16 + UINT32 Reserved3 : 1; ///< Bits 17:17 + UINT32 Cl36 : 1; ///< Bits 18:18 + UINT32 Reserved4 : 1; ///< Bits 19:19 + UINT32 Cl40 : 1; ///< Bits 20:20 + UINT32 Reserved5 : 11; ///< Bits 31:21 + } Bits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 tAAmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 ReadLatencyMode : 2; ///< Bits 1:0 + UINT8 WriteLatencySet : 2; ///< Bits 3:2 + UINT8 Reserved : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT; + +typedef union { + struct { + UINT8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPab : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TRP_AB_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPpb : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TRP_PB_MTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCab : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_LPDDR_TRFC_AB_MTB_STRUCT; + +typedef union { +struct { + UINT16 tRFCpb : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_LPDDR_TRFC_PB_MTB_STRUCT; + +typedef union { + struct { + UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0 + UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5 + UINT8 PackageRankMap : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT; + +typedef union { + struct { + INT8 tRPpbFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TRP_PB_FTB_STRUCT; + +typedef union { + struct { + INT8 tRPabFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TRP_AB_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tCKmaxFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TCK_MAX_FTB_STRUCT; + +typedef union { + struct { + INT8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_LPDDR_MANUFACTURER_ID_CODE; + +typedef struct { + UINT8 Location; ///< Module Manufacturing Location +} SPD_LPDDR_MANUFACTURING_LOCATION; + +typedef struct { + UINT8 Year; ///< Year represented in BCD (00h = 2000) + UINT8 Week; ///< Year represented in BCD (47h = week 47) +} SPD_LPDDR_MANUFACTURING_DATE; + +typedef union { + UINT32 Data; + UINT16 SerialNumber16[2]; + UINT8 SerialNumber8[4]; +} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER; + +typedef struct { + SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code + SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location + SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) + SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number +} SPD_LPDDR_UNIQUE_MODULE_ID; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_REFERENCE_RAW_CARD; + +typedef union { + UINT16 Crc[1]; + UINT8 Data8[2]; +} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE; + +typedef struct { + SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision + SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type + SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type + SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks + SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing + SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type + SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features + SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options + SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features + UINT8 Reserved0; ///< 10 Reserved + SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD + SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization + SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width + SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor + SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type + SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading + SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases + SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) + SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) + SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported + SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) + SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options + SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks + SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank + SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks + SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank + UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved + SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping + UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved + SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank + SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks + SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax) + SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_BASE_SECTION; + +typedef struct { + SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height + SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness + SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used + UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved + SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_MODULE_LPDIMM; + +typedef struct { + SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types +} SPD_LPDDR_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number +} SPD_LPDDR_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data +} SPD_LPDDR_MANUFACTURER_SPECIFIC; + +typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code +typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping + +typedef struct { + SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID + SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number + SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code + SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code + SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping + SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data + UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved +} SPD_LPDDR_MANUFACTURING_DATA; + +typedef struct { + UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable +} SPD_LPDDR_END_USER_SECTION; + +/// +/// LPDDR Serial Presence Detect structure +/// +typedef struct { + SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters + SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section + UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters + SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information + SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable +} SPD_LPDDR; + +#pragma pack (pop) +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h new file mode 100644 index 0000000000..1a2ce05860 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h @@ -0,0 +1,177 @@ +/** @file + ACPI Serial Port Console Redirection Table as defined by Microsoft in + http://www.microsoft.com/whdc/system/platform/server/spcr.mspx + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_ +#define _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_ + + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// SPCR Revision (defined in spec) +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x02 + +/// +/// Serial Port Console Redirection Table Format +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 InterfaceType; + UINT8 Reserved1[3]; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + UINT8 InterruptType; + UINT8 Irq; + UINT32 GlobalSystemInterrupt; + UINT8 BaudRate; + UINT8 Parity; + UINT8 StopBits; + UINT8 FlowControl; + UINT8 TerminalType; + UINT8 Reserved2; + UINT16 PciDeviceId; + UINT16 PciVendorId; + UINT8 PciBusNumber; + UINT8 PciDeviceNumber; + UINT8 PciFunctionNumber; + UINT32 PciFlags; + UINT8 PciSegment; + UINT32 Reserved3; +} EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE; + +#pragma pack() + +// +// SPCR Definitions +// + +// +// Interface Type +// + +/// +/// Full 16550 interface +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 0 +/// +/// Full 16450 interface +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450 1 + + +// +// The Serial Port Subtypes for ARM are documented in Table 3 of the DBG2 Specification +// + +/// +/// ARM PL011 UART +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART 0x03 + +/// +/// NVIDIA 16550 UART +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_NVIDIA_16550_UART 0x05 + +/// +/// ARM SBSA Generic UART (2.x) supporting 32-bit only accesses [deprecated] +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART_2X 0x0d + +/// +/// ARM SBSA Generic UART +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART 0x0e + +/// +/// ARM DCC +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_DCC 0x0f + +/// +/// BCM2835 UART +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART 0x10 + +/// +/// 16550-compatible with parameters defined in Generic Address Structure +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550_WITH_GAS 0x12 + +// +// Interrupt Type +// + +/// +/// PC-AT-compatible dual-8259 IRQ interrupt +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259 0x1 +/// +/// I/O APIC interrupt (Global System Interrupt) +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC 0x2 +/// +/// I/O SAPIC interrupt (Global System Interrupt) +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC 0x4 +/// +/// ARMH GIC interrupt (Global System Interrupt) +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC 0x8 + +// +// Baud Rate +// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600 3 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200 4 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600 6 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200 7 + +// +// Parity +// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY 0 + +// +// Stop Bits +// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1 1 + +// +// Flow Control +// + +/// +/// DCD required for transmit +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD 0x1 +/// +/// RTS/CTS hardware flow control +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS 0x2 +/// +/// XON/XOFF software control +/// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_XON_XOFF 0x4 + +// +// Terminal Type +// +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100 0 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100_PLUS 1 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8 2 +#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI 3 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h new file mode 100644 index 0000000000..2006e12473 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h @@ -0,0 +1,98 @@ +/** @file + Service Processor Management Interface (SPMI) ACPI table definition from + Intelligent Platform Management Interface Specification Second Generation. + + Copyright (c) 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Intelligent Platform Management Interface Specification Second Generation + v2.0 Revision 1.1, Dated October 2013. + https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf +**/ +#ifndef _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_ +#define _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_ + +#include + +#pragma pack(1) + +/// +/// Definition for the device identification information used by the Service +/// Processor Management Interface Description Table +/// +typedef union { + /// + /// For PCI IPMI device + /// + struct { + UINT8 SegmentGroup; + UINT8 Bus; + UINT8 Device; + UINT8 Function; + } Pci; + /// + /// For non-PCI IPMI device, the ACPI _UID value of the device + /// + UINT32 Uid; +} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID; + + +/// +/// Definition for Service Processor Management Interface Description Table +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + /// + /// Indicates the type of IPMI interface. + /// + UINT8 InterfaceType; + /// + /// This field must always be 01h to be compatible with any software that + /// implements previous versions of this spec. + /// + UINT8 Reserved1; + /// + /// Identifies the IPMI specification revision, in BCD format. + /// + UINT16 SpecificationRevision; + /// + /// Interrupt type(s) used by the interface. + /// + UINT8 InterruptType; + /// + /// The bit assignment of the SCI interrupt within the GPEx_STS register of a + /// GPE described if the FADT that the interface triggers. + /// + UINT8 Gpe; + /// + /// Reserved, must be 00h. + /// + UINT8 Reserved2; + /// + /// PCI Device Flag. + /// + UINT8 PciDeviceFlag; + /// + /// The I/O APIC or I/O SAPIC Global System Interrupt used by the interface. + /// + UINT32 GlobalSystemInterrupt; + /// + /// The base address of the interface register set described using the + /// Generic Address Structure (GAS, See [ACPI 2.0] for the definition). + /// + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + /// + /// Device identification information. + /// + EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID DeviceId; + /// + /// This field must always be null (0x00) to be compatible with any software + /// that implements previous versions of this spec. + /// + UINT8 Reserved3; +} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBios.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBios.h new file mode 100644 index 0000000000..486e984cfe --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBios.h @@ -0,0 +1,2724 @@ +/** @file + Industry Standard Definitions of SMBIOS Table Specification v3.3.0. + +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMBIOS_STANDARD_H__ +#define __SMBIOS_STANDARD_H__ + +/// +/// Reference SMBIOS 2.6, chapter 3.1.2. +/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for +/// use by this specification. +/// +#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00 + +/// +/// Reference SMBIOS 2.7, chapter 6.1.2. +/// The UEFI Platform Initialization Specification reserves handle number FFFEh for its +/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically." +/// This number is not used for any other purpose by the SMBIOS specification. +/// +#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE + +/// +/// Reference SMBIOS 2.6, chapter 3.1.3. +/// Each text string is limited to 64 significant characters due to system MIF limitations. +/// Reference SMBIOS 2.7, chapter 6.1.3. +/// It will have no limit on the length of each individual text string. +/// +#define SMBIOS_STRING_MAX_LENGTH 64 + +// +// The length of the entire structure table (including all strings) must be reported +// in the Structure Table Length field of the SMBIOS Structure Table Entry Point, +// which is a WORD field limited to 65,535 bytes. +// +#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF + +// +// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes. +// +#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF + +// +// SMBIOS type macros which is according to SMBIOS 3.3.0 specification. +// +#define SMBIOS_TYPE_BIOS_INFORMATION 0 +#define SMBIOS_TYPE_SYSTEM_INFORMATION 1 +#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2 +#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3 +#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4 +#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5 +#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6 +#define SMBIOS_TYPE_CACHE_INFORMATION 7 +#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8 +#define SMBIOS_TYPE_SYSTEM_SLOTS 9 +#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10 +#define SMBIOS_TYPE_OEM_STRINGS 11 +#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12 +#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13 +#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14 +#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15 +#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16 +#define SMBIOS_TYPE_MEMORY_DEVICE 17 +#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18 +#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19 +#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20 +#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21 +#define SMBIOS_TYPE_PORTABLE_BATTERY 22 +#define SMBIOS_TYPE_SYSTEM_RESET 23 +#define SMBIOS_TYPE_HARDWARE_SECURITY 24 +#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25 +#define SMBIOS_TYPE_VOLTAGE_PROBE 26 +#define SMBIOS_TYPE_COOLING_DEVICE 27 +#define SMBIOS_TYPE_TEMPERATURE_PROBE 28 +#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29 +#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30 +#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31 +#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32 +#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33 +#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34 +#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35 +#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36 +#define SMBIOS_TYPE_MEMORY_CHANNEL 37 +#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38 +#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39 +#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40 +#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41 +#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42 +#define SMBIOS_TYPE_TPM_DEVICE 43 +#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44 + +/// +/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43. +/// Upper-level software that interprets the SMBIOS structure-table should bypass an +/// Inactive structure just like a structure type that the software does not recognize. +/// +#define SMBIOS_TYPE_INACTIVE 0x007E + +/// +/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44. +/// The end-of-table indicator is used in the last physical structure in a table +/// +#define SMBIOS_TYPE_END_OF_TABLE 0x007F + +#define SMBIOS_OEM_BEGIN 128 +#define SMBIOS_OEM_END 255 + +/// +/// Types 0 through 127 (7Fh) are reserved for and defined by this +/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information. +/// +typedef UINT8 SMBIOS_TYPE; + +/// +/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version +/// 2.0) or 0 to 0FEFFh (for version 2.1 and later). The handle can be used with the Get SMBIOS +/// Structure function to retrieve a specific structure; the handle numbers are not required to be +/// contiguous. For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for +/// use by this specification. +/// If the system configuration changes, a previously assigned handle might no longer exist. +/// However once a handle has been assigned by the BIOS, the BIOS cannot re-assign that handle +/// number to another structure. +/// +typedef UINT16 SMBIOS_HANDLE; + +/// +/// Smbios Table Entry Point Structure. +/// +#pragma pack(1) +typedef struct { + UINT8 AnchorString[4]; + UINT8 EntryPointStructureChecksum; + UINT8 EntryPointLength; + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT16 MaxStructureSize; + UINT8 EntryPointRevision; + UINT8 FormattedArea[5]; + UINT8 IntermediateAnchorString[5]; + UINT8 IntermediateChecksum; + UINT16 TableLength; + UINT32 TableAddress; + UINT16 NumberOfSmbiosStructures; + UINT8 SmbiosBcdRevision; +} SMBIOS_TABLE_ENTRY_POINT; + +typedef struct { + UINT8 AnchorString[5]; + UINT8 EntryPointStructureChecksum; + UINT8 EntryPointLength; + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 DocRev; + UINT8 EntryPointRevision; + UINT8 Reserved; + UINT32 TableMaximumSize; + UINT64 TableAddress; +} SMBIOS_TABLE_3_0_ENTRY_POINT; + +/// +/// The Smbios structure header. +/// +typedef struct { + SMBIOS_TYPE Type; + UINT8 Length; + SMBIOS_HANDLE Handle; +} SMBIOS_STRUCTURE; + +/// +/// Text strings associated with a given SMBIOS structure are returned in the dmiStrucBuffer, appended directly after +/// the formatted portion of the structure. This method of returning string information eliminates the need for +/// application software to deal with pointers embedded in the SMBIOS structure. Each string is terminated with a null +/// (00h) BYTE and the set of strings is terminated with an additional null (00h) BYTE. When the formatted portion of +/// a SMBIOS structure references a string, it does so by specifying a non-zero string number within the structure's +/// string-set. For example, if a string field contains 02h, it references the second string following the formatted portion +/// of the SMBIOS structure. If a string field references no string, a null (0) is placed in that string field. If the +/// formatted portion of the structure contains string-reference fields and all the string fields are set to 0 (no string +/// references), the formatted section of the structure is followed by two null (00h) BYTES. +/// +typedef UINT8 SMBIOS_TABLE_STRING; + +/// +/// BIOS Characteristics +/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. +/// +typedef struct { + UINT32 Reserved :2; ///< Bits 0-1. + UINT32 Unknown :1; + UINT32 BiosCharacteristicsNotSupported :1; + UINT32 IsaIsSupported :1; + UINT32 McaIsSupported :1; + UINT32 EisaIsSupported :1; + UINT32 PciIsSupported :1; + UINT32 PcmciaIsSupported :1; + UINT32 PlugAndPlayIsSupported :1; + UINT32 ApmIsSupported :1; + UINT32 BiosIsUpgradable :1; + UINT32 BiosShadowingAllowed :1; + UINT32 VlVesaIsSupported :1; + UINT32 EscdSupportIsAvailable :1; + UINT32 BootFromCdIsSupported :1; + UINT32 SelectableBootIsSupported :1; + UINT32 RomBiosIsSocketed :1; + UINT32 BootFromPcmciaIsSupported :1; + UINT32 EDDSpecificationIsSupported :1; + UINT32 JapaneseNecFloppyIsSupported :1; + UINT32 JapaneseToshibaFloppyIsSupported :1; + UINT32 Floppy525_360IsSupported :1; + UINT32 Floppy525_12IsSupported :1; + UINT32 Floppy35_720IsSupported :1; + UINT32 Floppy35_288IsSupported :1; + UINT32 PrintScreenIsSupported :1; + UINT32 Keyboard8042IsSupported :1; + UINT32 SerialIsSupported :1; + UINT32 PrinterIsSupported :1; + UINT32 CgaMonoIsSupported :1; + UINT32 NecPc98 :1; + UINT32 ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor + ///< and bits 48-63 reserved for System Vendor. +} MISC_BIOS_CHARACTERISTICS; + +/// +/// BIOS Characteristics Extension Byte 1. +/// This information, available for SMBIOS version 2.1 and later, appears at offset 12h +/// within the BIOS Information structure. +/// +typedef struct { + UINT8 AcpiIsSupported :1; + UINT8 UsbLegacyIsSupported :1; + UINT8 AgpIsSupported :1; + UINT8 I2OBootIsSupported :1; + UINT8 Ls120BootIsSupported :1; + UINT8 AtapiZipDriveBootIsSupported :1; + UINT8 Boot1394IsSupported :1; + UINT8 SmartBatteryIsSupported :1; +} MBCE_BIOS_RESERVED; + +/// +/// BIOS Characteristics Extension Byte 2. +/// This information, available for SMBIOS version 2.3 and later, appears at offset 13h +/// within the BIOS Information structure. +/// +typedef struct { + UINT8 BiosBootSpecIsSupported :1; + UINT8 FunctionKeyNetworkBootIsSupported :1; + UINT8 TargetContentDistributionEnabled :1; + UINT8 UefiSpecificationSupported :1; + UINT8 VirtualMachineSupported :1; + UINT8 ExtensionByte2Reserved :3; +} MBCE_SYSTEM_RESERVED; + +/// +/// BIOS Characteristics Extension Bytes. +/// +typedef struct { + MBCE_BIOS_RESERVED BiosReserved; + MBCE_SYSTEM_RESERVED SystemReserved; +} MISC_BIOS_CHARACTERISTICS_EXTENSION; + +/// +/// Extended BIOS ROM size. +/// +typedef struct { + UINT16 Size :14; + UINT16 Unit :2; +} EXTENDED_BIOS_ROM_SIZE; + +/// +/// BIOS Information (Type 0). +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Vendor; + SMBIOS_TABLE_STRING BiosVersion; + UINT16 BiosSegment; + SMBIOS_TABLE_STRING BiosReleaseDate; + UINT8 BiosSize; + MISC_BIOS_CHARACTERISTICS BiosCharacteristics; + UINT8 BIOSCharacteristicsExtensionBytes[2]; + UINT8 SystemBiosMajorRelease; + UINT8 SystemBiosMinorRelease; + UINT8 EmbeddedControllerFirmwareMajorRelease; + UINT8 EmbeddedControllerFirmwareMinorRelease; + // + // Add for smbios 3.1.0 + // + EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize; +} SMBIOS_TABLE_TYPE0; + +/// +/// System Wake-up Type. +/// +typedef enum { + SystemWakeupTypeReserved = 0x00, + SystemWakeupTypeOther = 0x01, + SystemWakeupTypeUnknown = 0x02, + SystemWakeupTypeApmTimer = 0x03, + SystemWakeupTypeModemRing = 0x04, + SystemWakeupTypeLanRemote = 0x05, + SystemWakeupTypePowerSwitch = 0x06, + SystemWakeupTypePciPme = 0x07, + SystemWakeupTypeAcPowerRestored = 0x08 +} MISC_SYSTEM_WAKEUP_TYPE; + +/// +/// System Information (Type 1). +/// +/// The information in this structure defines attributes of the overall system and is +/// intended to be associated with the Component ID group of the system's MIF. +/// An SMBIOS implementation is associated with a single system instance and contains +/// one and only one System Information (Type 1) structure. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Manufacturer; + SMBIOS_TABLE_STRING ProductName; + SMBIOS_TABLE_STRING Version; + SMBIOS_TABLE_STRING SerialNumber; + GUID Uuid; + UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE. + SMBIOS_TABLE_STRING SKUNumber; + SMBIOS_TABLE_STRING Family; +} SMBIOS_TABLE_TYPE1; + +/// +/// Base Board - Feature Flags. +/// +typedef struct { + UINT8 Motherboard :1; + UINT8 RequiresDaughterCard :1; + UINT8 Removable :1; + UINT8 Replaceable :1; + UINT8 HotSwappable :1; + UINT8 Reserved :3; +} BASE_BOARD_FEATURE_FLAGS; + +/// +/// Base Board - Board Type. +/// +typedef enum { + BaseBoardTypeUnknown = 0x1, + BaseBoardTypeOther = 0x2, + BaseBoardTypeServerBlade = 0x3, + BaseBoardTypeConnectivitySwitch = 0x4, + BaseBoardTypeSystemManagementModule = 0x5, + BaseBoardTypeProcessorModule = 0x6, + BaseBoardTypeIOModule = 0x7, + BaseBoardTypeMemoryModule = 0x8, + BaseBoardTypeDaughterBoard = 0x9, + BaseBoardTypeMotherBoard = 0xA, + BaseBoardTypeProcessorMemoryModule = 0xB, + BaseBoardTypeProcessorIOModule = 0xC, + BaseBoardTypeInterconnectBoard = 0xD +} BASE_BOARD_TYPE; + +/// +/// Base Board (or Module) Information (Type 2). +/// +/// The information in this structure defines attributes of a system baseboard - +/// for example a motherboard, planar, or server blade or other standard system module. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Manufacturer; + SMBIOS_TABLE_STRING ProductName; + SMBIOS_TABLE_STRING Version; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING AssetTag; + BASE_BOARD_FEATURE_FLAGS FeatureFlag; + SMBIOS_TABLE_STRING LocationInChassis; + UINT16 ChassisHandle; + UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE. + UINT8 NumberOfContainedObjectHandles; + UINT16 ContainedObjectHandles[1]; +} SMBIOS_TABLE_TYPE2; + +/// +/// System Enclosure or Chassis Types +/// +typedef enum { + MiscChassisTypeOther = 0x01, + MiscChassisTypeUnknown = 0x02, + MiscChassisTypeDeskTop = 0x03, + MiscChassisTypeLowProfileDesktop = 0x04, + MiscChassisTypePizzaBox = 0x05, + MiscChassisTypeMiniTower = 0x06, + MiscChassisTypeTower = 0x07, + MiscChassisTypePortable = 0x08, + MiscChassisTypeLapTop = 0x09, + MiscChassisTypeNotebook = 0x0A, + MiscChassisTypeHandHeld = 0x0B, + MiscChassisTypeDockingStation = 0x0C, + MiscChassisTypeAllInOne = 0x0D, + MiscChassisTypeSubNotebook = 0x0E, + MiscChassisTypeSpaceSaving = 0x0F, + MiscChassisTypeLunchBox = 0x10, + MiscChassisTypeMainServerChassis = 0x11, + MiscChassisTypeExpansionChassis = 0x12, + MiscChassisTypeSubChassis = 0x13, + MiscChassisTypeBusExpansionChassis = 0x14, + MiscChassisTypePeripheralChassis = 0x15, + MiscChassisTypeRaidChassis = 0x16, + MiscChassisTypeRackMountChassis = 0x17, + MiscChassisTypeSealedCasePc = 0x18, + MiscChassisMultiSystemChassis = 0x19, + MiscChassisCompactPCI = 0x1A, + MiscChassisAdvancedTCA = 0x1B, + MiscChassisBlade = 0x1C, + MiscChassisBladeEnclosure = 0x1D, + MiscChassisTablet = 0x1E, + MiscChassisConvertible = 0x1F, + MiscChassisDetachable = 0x20, + MiscChassisIoTGateway = 0x21, + MiscChassisEmbeddedPc = 0x22, + MiscChassisMiniPc = 0x23, + MiscChassisStickPc = 0x24 +} MISC_CHASSIS_TYPE; + +/// +/// System Enclosure or Chassis States . +/// +typedef enum { + ChassisStateOther = 0x01, + ChassisStateUnknown = 0x02, + ChassisStateSafe = 0x03, + ChassisStateWarning = 0x04, + ChassisStateCritical = 0x05, + ChassisStateNonRecoverable = 0x06 +} MISC_CHASSIS_STATE; + +/// +/// System Enclosure or Chassis Security Status. +/// +typedef enum { + ChassisSecurityStatusOther = 0x01, + ChassisSecurityStatusUnknown = 0x02, + ChassisSecurityStatusNone = 0x03, + ChassisSecurityStatusExternalInterfaceLockedOut = 0x04, + ChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05 +} MISC_CHASSIS_SECURITY_STATE; + +/// +/// Contained Element record +/// +typedef struct { + UINT8 ContainedElementType; + UINT8 ContainedElementMinimum; + UINT8 ContainedElementMaximum; +} CONTAINED_ELEMENT; + + +/// +/// System Enclosure or Chassis (Type 3). +/// +/// The information in this structure defines attributes of the system's mechanical enclosure(s). +/// For example, if a system included a separate enclosure for its peripheral devices, +/// two structures would be returned: one for the main, system enclosure and the second for +/// the peripheral device enclosure. The additions to this structure in v2.1 of this specification +/// support the population of the CIM_Chassis class. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Manufacturer; + UINT8 Type; + SMBIOS_TABLE_STRING Version; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING AssetTag; + UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE. + UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE. + UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE. + UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE. + UINT8 OemDefined[4]; + UINT8 Height; + UINT8 NumberofPowerCords; + UINT8 ContainedElementCount; + UINT8 ContainedElementRecordLength; + // + // Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements + // + CONTAINED_ELEMENT ContainedElements[1]; + // + // Add for smbios 2.7 + // + // Since ContainedElements has a variable number of entries, must not define SKUNumber in + // the structure. Need to reference it by starting at offset 0x15 and adding + // (ContainedElementCount * ContainedElementRecordLength) bytes. + // + // SMBIOS_TABLE_STRING SKUNumber; +} SMBIOS_TABLE_TYPE3; + +/// +/// Processor Information - Processor Type. +/// +typedef enum { + ProcessorOther = 0x01, + ProcessorUnknown = 0x02, + CentralProcessor = 0x03, + MathProcessor = 0x04, + DspProcessor = 0x05, + VideoProcessor = 0x06 +} PROCESSOR_TYPE_DATA; + +/// +/// Processor Information - Processor Family. +/// +typedef enum { + ProcessorFamilyOther = 0x01, + ProcessorFamilyUnknown = 0x02, + ProcessorFamily8086 = 0x03, + ProcessorFamily80286 = 0x04, + ProcessorFamilyIntel386 = 0x05, + ProcessorFamilyIntel486 = 0x06, + ProcessorFamily8087 = 0x07, + ProcessorFamily80287 = 0x08, + ProcessorFamily80387 = 0x09, + ProcessorFamily80487 = 0x0A, + ProcessorFamilyPentium = 0x0B, + ProcessorFamilyPentiumPro = 0x0C, + ProcessorFamilyPentiumII = 0x0D, + ProcessorFamilyPentiumMMX = 0x0E, + ProcessorFamilyCeleron = 0x0F, + ProcessorFamilyPentiumIIXeon = 0x10, + ProcessorFamilyPentiumIII = 0x11, + ProcessorFamilyM1 = 0x12, + ProcessorFamilyM2 = 0x13, + ProcessorFamilyIntelCeleronM = 0x14, + ProcessorFamilyIntelPentium4Ht = 0x15, + ProcessorFamilyAmdDuron = 0x18, + ProcessorFamilyK5 = 0x19, + ProcessorFamilyK6 = 0x1A, + ProcessorFamilyK6_2 = 0x1B, + ProcessorFamilyK6_3 = 0x1C, + ProcessorFamilyAmdAthlon = 0x1D, + ProcessorFamilyAmd29000 = 0x1E, + ProcessorFamilyK6_2Plus = 0x1F, + ProcessorFamilyPowerPC = 0x20, + ProcessorFamilyPowerPC601 = 0x21, + ProcessorFamilyPowerPC603 = 0x22, + ProcessorFamilyPowerPC603Plus = 0x23, + ProcessorFamilyPowerPC604 = 0x24, + ProcessorFamilyPowerPC620 = 0x25, + ProcessorFamilyPowerPCx704 = 0x26, + ProcessorFamilyPowerPC750 = 0x27, + ProcessorFamilyIntelCoreDuo = 0x28, + ProcessorFamilyIntelCoreDuoMobile = 0x29, + ProcessorFamilyIntelCoreSoloMobile = 0x2A, + ProcessorFamilyIntelAtom = 0x2B, + ProcessorFamilyIntelCoreM = 0x2C, + ProcessorFamilyIntelCorem3 = 0x2D, + ProcessorFamilyIntelCorem5 = 0x2E, + ProcessorFamilyIntelCorem7 = 0x2F, + ProcessorFamilyAlpha = 0x30, + ProcessorFamilyAlpha21064 = 0x31, + ProcessorFamilyAlpha21066 = 0x32, + ProcessorFamilyAlpha21164 = 0x33, + ProcessorFamilyAlpha21164PC = 0x34, + ProcessorFamilyAlpha21164a = 0x35, + ProcessorFamilyAlpha21264 = 0x36, + ProcessorFamilyAlpha21364 = 0x37, + ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38, + ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39, + ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A, + ProcessorFamilyAmdOpteron6100Series = 0x3B, + ProcessorFamilyAmdOpteron4100Series = 0x3C, + ProcessorFamilyAmdOpteron6200Series = 0x3D, + ProcessorFamilyAmdOpteron4200Series = 0x3E, + ProcessorFamilyAmdFxSeries = 0x3F, + ProcessorFamilyMips = 0x40, + ProcessorFamilyMIPSR4000 = 0x41, + ProcessorFamilyMIPSR4200 = 0x42, + ProcessorFamilyMIPSR4400 = 0x43, + ProcessorFamilyMIPSR4600 = 0x44, + ProcessorFamilyMIPSR10000 = 0x45, + ProcessorFamilyAmdCSeries = 0x46, + ProcessorFamilyAmdESeries = 0x47, + ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name + ProcessorFamilyAmdGSeries = 0x49, + ProcessorFamilyAmdZSeries = 0x4A, + ProcessorFamilyAmdRSeries = 0x4B, + ProcessorFamilyAmdOpteron4300 = 0x4C, + ProcessorFamilyAmdOpteron6300 = 0x4D, + ProcessorFamilyAmdOpteron3300 = 0x4E, + ProcessorFamilyAmdFireProSeries = 0x4F, + ProcessorFamilySparc = 0x50, + ProcessorFamilySuperSparc = 0x51, + ProcessorFamilymicroSparcII = 0x52, + ProcessorFamilymicroSparcIIep = 0x53, + ProcessorFamilyUltraSparc = 0x54, + ProcessorFamilyUltraSparcII = 0x55, + ProcessorFamilyUltraSparcIii = 0x56, + ProcessorFamilyUltraSparcIII = 0x57, + ProcessorFamilyUltraSparcIIIi = 0x58, + ProcessorFamily68040 = 0x60, + ProcessorFamily68xxx = 0x61, + ProcessorFamily68000 = 0x62, + ProcessorFamily68010 = 0x63, + ProcessorFamily68020 = 0x64, + ProcessorFamily68030 = 0x65, + ProcessorFamilyAmdAthlonX4QuadCore = 0x66, + ProcessorFamilyAmdOpteronX1000Series = 0x67, + ProcessorFamilyAmdOpteronX2000Series = 0x68, + ProcessorFamilyAmdOpteronASeries = 0x69, + ProcessorFamilyAmdOpteronX3000Series = 0x6A, + ProcessorFamilyAmdZen = 0x6B, + ProcessorFamilyHobbit = 0x70, + ProcessorFamilyCrusoeTM5000 = 0x78, + ProcessorFamilyCrusoeTM3000 = 0x79, + ProcessorFamilyEfficeonTM8000 = 0x7A, + ProcessorFamilyWeitek = 0x80, + ProcessorFamilyItanium = 0x82, + ProcessorFamilyAmdAthlon64 = 0x83, + ProcessorFamilyAmdOpteron = 0x84, + ProcessorFamilyAmdSempron = 0x85, + ProcessorFamilyAmdTurion64Mobile = 0x86, + ProcessorFamilyDualCoreAmdOpteron = 0x87, + ProcessorFamilyAmdAthlon64X2DualCore = 0x88, + ProcessorFamilyAmdTurion64X2Mobile = 0x89, + ProcessorFamilyQuadCoreAmdOpteron = 0x8A, + ProcessorFamilyThirdGenerationAmdOpteron = 0x8B, + ProcessorFamilyAmdPhenomFxQuadCore = 0x8C, + ProcessorFamilyAmdPhenomX4QuadCore = 0x8D, + ProcessorFamilyAmdPhenomX2DualCore = 0x8E, + ProcessorFamilyAmdAthlonX2DualCore = 0x8F, + ProcessorFamilyPARISC = 0x90, + ProcessorFamilyPaRisc8500 = 0x91, + ProcessorFamilyPaRisc8000 = 0x92, + ProcessorFamilyPaRisc7300LC = 0x93, + ProcessorFamilyPaRisc7200 = 0x94, + ProcessorFamilyPaRisc7100LC = 0x95, + ProcessorFamilyPaRisc7100 = 0x96, + ProcessorFamilyV30 = 0xA0, + ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1, + ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2, + ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3, + ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4, + ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5, + ProcessorFamilyDualCoreIntelXeonLV = 0xA6, + ProcessorFamilyDualCoreIntelXeonULV = 0xA7, + ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8, + ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9, + ProcessorFamilyQuadCoreIntelXeon = 0xAA, + ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB, + ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC, + ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD, + ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE, + ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF, + ProcessorFamilyPentiumIIIXeon = 0xB0, + ProcessorFamilyPentiumIIISpeedStep = 0xB1, + ProcessorFamilyPentium4 = 0xB2, + ProcessorFamilyIntelXeon = 0xB3, + ProcessorFamilyAS400 = 0xB4, + ProcessorFamilyIntelXeonMP = 0xB5, + ProcessorFamilyAMDAthlonXP = 0xB6, + ProcessorFamilyAMDAthlonMP = 0xB7, + ProcessorFamilyIntelItanium2 = 0xB8, + ProcessorFamilyIntelPentiumM = 0xB9, + ProcessorFamilyIntelCeleronD = 0xBA, + ProcessorFamilyIntelPentiumD = 0xBB, + ProcessorFamilyIntelPentiumEx = 0xBC, + ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value + ProcessorFamilyReserved = 0xBE, + ProcessorFamilyIntelCore2 = 0xBF, + ProcessorFamilyIntelCore2Solo = 0xC0, + ProcessorFamilyIntelCore2Extreme = 0xC1, + ProcessorFamilyIntelCore2Quad = 0xC2, + ProcessorFamilyIntelCore2ExtremeMobile = 0xC3, + ProcessorFamilyIntelCore2DuoMobile = 0xC4, + ProcessorFamilyIntelCore2SoloMobile = 0xC5, + ProcessorFamilyIntelCoreI7 = 0xC6, + ProcessorFamilyDualCoreIntelCeleron = 0xC7, + ProcessorFamilyIBM390 = 0xC8, + ProcessorFamilyG4 = 0xC9, + ProcessorFamilyG5 = 0xCA, + ProcessorFamilyG6 = 0xCB, + ProcessorFamilyzArchitecture = 0xCC, + ProcessorFamilyIntelCoreI5 = 0xCD, + ProcessorFamilyIntelCoreI3 = 0xCE, + ProcessorFamilyIntelCoreI9 = 0xCF, + ProcessorFamilyViaC7M = 0xD2, + ProcessorFamilyViaC7D = 0xD3, + ProcessorFamilyViaC7 = 0xD4, + ProcessorFamilyViaEden = 0xD5, + ProcessorFamilyMultiCoreIntelXeon = 0xD6, + ProcessorFamilyDualCoreIntelXeon3Series = 0xD7, + ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8, + ProcessorFamilyViaNano = 0xD9, + ProcessorFamilyDualCoreIntelXeon5Series = 0xDA, + ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB, + ProcessorFamilyDualCoreIntelXeon7Series = 0xDD, + ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE, + ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF, + ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0, + ProcessorFamilyAmdOpteron3000Series = 0xE4, + ProcessorFamilyAmdSempronII = 0xE5, + ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6, + ProcessorFamilyAmdPhenomTripleCore = 0xE7, + ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8, + ProcessorFamilyAmdTurionDualCoreMobile = 0xE9, + ProcessorFamilyAmdAthlonDualCore = 0xEA, + ProcessorFamilyAmdSempronSI = 0xEB, + ProcessorFamilyAmdPhenomII = 0xEC, + ProcessorFamilyAmdAthlonII = 0xED, + ProcessorFamilySixCoreAmdOpteron = 0xEE, + ProcessorFamilyAmdSempronM = 0xEF, + ProcessorFamilyi860 = 0xFA, + ProcessorFamilyi960 = 0xFB, + ProcessorFamilyIndicatorFamily2 = 0xFE, + ProcessorFamilyReserved1 = 0xFF +} PROCESSOR_FAMILY_DATA; + +/// +/// Processor Information2 - Processor Family2. +/// +typedef enum { + ProcessorFamilyARMv7 = 0x0100, + ProcessorFamilyARMv8 = 0x0101, + ProcessorFamilySH3 = 0x0104, + ProcessorFamilySH4 = 0x0105, + ProcessorFamilyARM = 0x0118, + ProcessorFamilyStrongARM = 0x0119, + ProcessorFamily6x86 = 0x012C, + ProcessorFamilyMediaGX = 0x012D, + ProcessorFamilyMII = 0x012E, + ProcessorFamilyWinChip = 0x0140, + ProcessorFamilyDSP = 0x015E, + ProcessorFamilyVideoProcessor = 0x01F4, + ProcessorFamilyRiscvRV32 = 0x0200, + ProcessorFamilyRiscVRV64 = 0x0201, + ProcessorFamilyRiscVRV128 = 0x0202 +} PROCESSOR_FAMILY2_DATA; + +/// +/// Processor Information - Voltage. +/// +typedef struct { + UINT8 ProcessorVoltageCapability5V :1; + UINT8 ProcessorVoltageCapability3_3V :1; + UINT8 ProcessorVoltageCapability2_9V :1; + UINT8 ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + UINT8 ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero. + UINT8 ProcessorVoltageIndicateLegacy :1; +} PROCESSOR_VOLTAGE; + +/// +/// Processor Information - Processor Upgrade. +/// +typedef enum { + ProcessorUpgradeOther = 0x01, + ProcessorUpgradeUnknown = 0x02, + ProcessorUpgradeDaughterBoard = 0x03, + ProcessorUpgradeZIFSocket = 0x04, + ProcessorUpgradePiggyBack = 0x05, ///< Replaceable. + ProcessorUpgradeNone = 0x06, + ProcessorUpgradeLIFSocket = 0x07, + ProcessorUpgradeSlot1 = 0x08, + ProcessorUpgradeSlot2 = 0x09, + ProcessorUpgrade370PinSocket = 0x0A, + ProcessorUpgradeSlotA = 0x0B, + ProcessorUpgradeSlotM = 0x0C, + ProcessorUpgradeSocket423 = 0x0D, + ProcessorUpgradeSocketA = 0x0E, ///< Socket 462. + ProcessorUpgradeSocket478 = 0x0F, + ProcessorUpgradeSocket754 = 0x10, + ProcessorUpgradeSocket940 = 0x11, + ProcessorUpgradeSocket939 = 0x12, + ProcessorUpgradeSocketmPGA604 = 0x13, + ProcessorUpgradeSocketLGA771 = 0x14, + ProcessorUpgradeSocketLGA775 = 0x15, + ProcessorUpgradeSocketS1 = 0x16, + ProcessorUpgradeAM2 = 0x17, + ProcessorUpgradeF1207 = 0x18, + ProcessorSocketLGA1366 = 0x19, + ProcessorUpgradeSocketG34 = 0x1A, + ProcessorUpgradeSocketAM3 = 0x1B, + ProcessorUpgradeSocketC32 = 0x1C, + ProcessorUpgradeSocketLGA1156 = 0x1D, + ProcessorUpgradeSocketLGA1567 = 0x1E, + ProcessorUpgradeSocketPGA988A = 0x1F, + ProcessorUpgradeSocketBGA1288 = 0x20, + ProcessorUpgradeSocketrPGA988B = 0x21, + ProcessorUpgradeSocketBGA1023 = 0x22, + ProcessorUpgradeSocketBGA1224 = 0x23, + ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name + ProcessorUpgradeSocketLGA1356 = 0x25, + ProcessorUpgradeSocketLGA2011 = 0x26, + ProcessorUpgradeSocketFS1 = 0x27, + ProcessorUpgradeSocketFS2 = 0x28, + ProcessorUpgradeSocketFM1 = 0x29, + ProcessorUpgradeSocketFM2 = 0x2A, + ProcessorUpgradeSocketLGA2011_3 = 0x2B, + ProcessorUpgradeSocketLGA1356_3 = 0x2C, + ProcessorUpgradeSocketLGA1150 = 0x2D, + ProcessorUpgradeSocketBGA1168 = 0x2E, + ProcessorUpgradeSocketBGA1234 = 0x2F, + ProcessorUpgradeSocketBGA1364 = 0x30, + ProcessorUpgradeSocketAM4 = 0x31, + ProcessorUpgradeSocketLGA1151 = 0x32, + ProcessorUpgradeSocketBGA1356 = 0x33, + ProcessorUpgradeSocketBGA1440 = 0x34, + ProcessorUpgradeSocketBGA1515 = 0x35, + ProcessorUpgradeSocketLGA3647_1 = 0x36, + ProcessorUpgradeSocketSP3 = 0x37, + ProcessorUpgradeSocketSP3r2 = 0x38, + ProcessorUpgradeSocketLGA2066 = 0x39, + ProcessorUpgradeSocketBGA1392 = 0x3A, + ProcessorUpgradeSocketBGA1510 = 0x3B, + ProcessorUpgradeSocketBGA1528 = 0x3C, + ProcessorUpgradeSocketLGA4189 = 0x3D, + ProcessorUpgradeSocketLGA1200 = 0x3E, + ProcessorUpgradeSocketLGA4677 = 0x3F +} PROCESSOR_UPGRADE; + +/// +/// Processor ID Field Description +/// +typedef struct { + UINT32 ProcessorSteppingId:4; + UINT32 ProcessorModel: 4; + UINT32 ProcessorFamily: 4; + UINT32 ProcessorType: 2; + UINT32 ProcessorReserved1: 2; + UINT32 ProcessorXModel: 4; + UINT32 ProcessorXFamily: 8; + UINT32 ProcessorReserved2: 4; +} PROCESSOR_SIGNATURE; + +typedef struct { + UINT32 ProcessorFpu :1; + UINT32 ProcessorVme :1; + UINT32 ProcessorDe :1; + UINT32 ProcessorPse :1; + UINT32 ProcessorTsc :1; + UINT32 ProcessorMsr :1; + UINT32 ProcessorPae :1; + UINT32 ProcessorMce :1; + UINT32 ProcessorCx8 :1; + UINT32 ProcessorApic :1; + UINT32 ProcessorReserved1 :1; + UINT32 ProcessorSep :1; + UINT32 ProcessorMtrr :1; + UINT32 ProcessorPge :1; + UINT32 ProcessorMca :1; + UINT32 ProcessorCmov :1; + UINT32 ProcessorPat :1; + UINT32 ProcessorPse36 :1; + UINT32 ProcessorPsn :1; + UINT32 ProcessorClfsh :1; + UINT32 ProcessorReserved2 :1; + UINT32 ProcessorDs :1; + UINT32 ProcessorAcpi :1; + UINT32 ProcessorMmx :1; + UINT32 ProcessorFxsr :1; + UINT32 ProcessorSse :1; + UINT32 ProcessorSse2 :1; + UINT32 ProcessorSs :1; + UINT32 ProcessorReserved3 :1; + UINT32 ProcessorTm :1; + UINT32 ProcessorReserved4 :2; +} PROCESSOR_FEATURE_FLAGS; + +typedef struct { + UINT16 ProcessorReserved1 :1; + UINT16 ProcessorUnknown :1; + UINT16 Processor64BitCapable :1; + UINT16 ProcessorMultiCore :1; + UINT16 ProcessorHardwareThread :1; + UINT16 ProcessorExecuteProtection :1; + UINT16 ProcessorEnhancedVirtualization :1; + UINT16 ProcessorPowerPerformanceCtrl :1; + UINT16 Processor128BitCapable :1; + UINT16 ProcessorArm64SocId :1; + UINT16 ProcessorReserved2 :6; +} PROCESSOR_CHARACTERISTIC_FLAGS; + +/// +/// Processor Information - Status +/// +typedef union { + struct { + UINT8 CpuStatus :3; ///< Indicates the status of the processor. + UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to zero. + UINT8 SocketPopulated :1; ///< Indicates if the processor socket is populated or not. + UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to zero. + } Bits; + UINT8 Data; +} PROCESSOR_STATUS_DATA; + +typedef struct { + PROCESSOR_SIGNATURE Signature; + PROCESSOR_FEATURE_FLAGS FeatureFlags; +} PROCESSOR_ID_DATA; + +/// +/// Processor Information (Type 4). +/// +/// The information in this structure defines the attributes of a single processor; +/// a separate structure instance is provided for each system processor socket/slot. +/// For example, a system with an IntelDX2 processor would have a single +/// structure instance, while a system with an IntelSX2 processor would have a structure +/// to describe the main CPU, and a second structure to describe the 80487 co-processor. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Socket; + UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA. + UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA. + SMBIOS_TABLE_STRING ProcessorManufacturer; + PROCESSOR_ID_DATA ProcessorId; + SMBIOS_TABLE_STRING ProcessorVersion; + PROCESSOR_VOLTAGE Voltage; + UINT16 ExternalClock; + UINT16 MaxSpeed; + UINT16 CurrentSpeed; + UINT8 Status; + UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE. + UINT16 L1CacheHandle; + UINT16 L2CacheHandle; + UINT16 L3CacheHandle; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING AssetTag; + SMBIOS_TABLE_STRING PartNumber; + // + // Add for smbios 2.5 + // + UINT8 CoreCount; + UINT8 EnabledCoreCount; + UINT8 ThreadCount; + UINT16 ProcessorCharacteristics; + // + // Add for smbios 2.6 + // + UINT16 ProcessorFamily2; + // + // Add for smbios 3.0 + // + UINT16 CoreCount2; + UINT16 EnabledCoreCount2; + UINT16 ThreadCount2; +} SMBIOS_TABLE_TYPE4; + +/// +/// Memory Controller Error Detecting Method. +/// +typedef enum { + ErrorDetectingMethodOther = 0x01, + ErrorDetectingMethodUnknown = 0x02, + ErrorDetectingMethodNone = 0x03, + ErrorDetectingMethodParity = 0x04, + ErrorDetectingMethod32Ecc = 0x05, + ErrorDetectingMethod64Ecc = 0x06, + ErrorDetectingMethod128Ecc = 0x07, + ErrorDetectingMethodCrc = 0x08 +} MEMORY_ERROR_DETECT_METHOD; + +/// +/// Memory Controller Error Correcting Capability. +/// +typedef struct { + UINT8 Other :1; + UINT8 Unknown :1; + UINT8 None :1; + UINT8 SingleBitErrorCorrect :1; + UINT8 DoubleBitErrorCorrect :1; + UINT8 ErrorScrubbing :1; + UINT8 Reserved :2; +} MEMORY_ERROR_CORRECT_CAPABILITY; + +/// +/// Memory Controller Information - Interleave Support. +/// +typedef enum { + MemoryInterleaveOther = 0x01, + MemoryInterleaveUnknown = 0x02, + MemoryInterleaveOneWay = 0x03, + MemoryInterleaveTwoWay = 0x04, + MemoryInterleaveFourWay = 0x05, + MemoryInterleaveEightWay = 0x06, + MemoryInterleaveSixteenWay = 0x07 +} MEMORY_SUPPORT_INTERLEAVE_TYPE; + +/// +/// Memory Controller Information - Memory Speeds. +/// +typedef struct { + UINT16 Other :1; + UINT16 Unknown :1; + UINT16 SeventyNs:1; + UINT16 SixtyNs :1; + UINT16 FiftyNs :1; + UINT16 Reserved :11; +} MEMORY_SPEED_TYPE; + +/// +/// Memory Controller Information (Type 5, Obsolete). +/// +/// The information in this structure defines the attributes of the system's memory controller(s) +/// and the supported attributes of any memory-modules present in the sockets controlled by +/// this controller. +/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete), +/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16) +/// and Memory Device (Type 17) structures should be used instead. BIOS providers might +/// choose to implement both memory description types to allow existing DMI browsers +/// to properly display the system's memory attributes. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD. + MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability; + UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE. + UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE . + UINT8 MaxMemoryModuleSize; + MEMORY_SPEED_TYPE SupportSpeed; + UINT16 SupportMemoryType; + UINT8 MemoryModuleVoltage; + UINT8 AssociatedMemorySlotNum; + UINT16 MemoryModuleConfigHandles[1]; +} SMBIOS_TABLE_TYPE5; + +/// +/// Memory Module Information - Memory Types +/// +typedef struct { + UINT16 Other :1; + UINT16 Unknown :1; + UINT16 Standard :1; + UINT16 FastPageMode:1; + UINT16 Edo :1; + UINT16 Parity :1; + UINT16 Ecc :1; + UINT16 Simm :1; + UINT16 Dimm :1; + UINT16 BurstEdo :1; + UINT16 Sdram :1; + UINT16 Reserved :5; +} MEMORY_CURRENT_TYPE; + +/// +/// Memory Module Information - Memory Size. +/// +typedef struct { + UINT8 InstalledOrEnabledSize :7; ///< Size (n), where 2**n is the size in MB. + UINT8 SingleOrDoubleBank :1; +} MEMORY_INSTALLED_ENABLED_SIZE; + +/// +/// Memory Module Information (Type 6, Obsolete) +/// +/// One Memory Module Information structure is included for each memory-module socket +/// in the system. The structure describes the speed, type, size, and error status +/// of each system memory module. The supported attributes of each module are described +/// by the "owning" Memory Controller Information structure. +/// Note: This structure, and its companion Memory Controller Information (Type 5, Obsolete), +/// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16) +/// and Memory Device (Type 17) structures should be used instead. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING SocketDesignation; + UINT8 BankConnections; + UINT8 CurrentSpeed; + MEMORY_CURRENT_TYPE CurrentMemoryType; + MEMORY_INSTALLED_ENABLED_SIZE InstalledSize; + MEMORY_INSTALLED_ENABLED_SIZE EnabledSize; + UINT8 ErrorStatus; +} SMBIOS_TABLE_TYPE6; + +/// +/// Cache Information - SRAM Type. +/// +typedef struct { + UINT16 Other :1; + UINT16 Unknown :1; + UINT16 NonBurst :1; + UINT16 Burst :1; + UINT16 PipelineBurst :1; + UINT16 Synchronous :1; + UINT16 Asynchronous :1; + UINT16 Reserved :9; +} CACHE_SRAM_TYPE_DATA; + +/// +/// Cache Information - Error Correction Type. +/// +typedef enum { + CacheErrorOther = 0x01, + CacheErrorUnknown = 0x02, + CacheErrorNone = 0x03, + CacheErrorParity = 0x04, + CacheErrorSingleBit = 0x05, ///< ECC + CacheErrorMultiBit = 0x06 ///< ECC +} CACHE_ERROR_TYPE_DATA; + +/// +/// Cache Information - System Cache Type. +/// +typedef enum { + CacheTypeOther = 0x01, + CacheTypeUnknown = 0x02, + CacheTypeInstruction = 0x03, + CacheTypeData = 0x04, + CacheTypeUnified = 0x05 +} CACHE_TYPE_DATA; + +/// +/// Cache Information - Associativity. +/// +typedef enum { + CacheAssociativityOther = 0x01, + CacheAssociativityUnknown = 0x02, + CacheAssociativityDirectMapped = 0x03, + CacheAssociativity2Way = 0x04, + CacheAssociativity4Way = 0x05, + CacheAssociativityFully = 0x06, + CacheAssociativity8Way = 0x07, + CacheAssociativity16Way = 0x08, + CacheAssociativity12Way = 0x09, + CacheAssociativity24Way = 0x0A, + CacheAssociativity32Way = 0x0B, + CacheAssociativity48Way = 0x0C, + CacheAssociativity64Way = 0x0D, + CacheAssociativity20Way = 0x0E +} CACHE_ASSOCIATIVITY_DATA; + +/// +/// Cache Information (Type 7). +/// +/// The information in this structure defines the attributes of CPU cache device in the system. +/// One structure is specified for each such device, whether the device is internal to +/// or external to the CPU module. Cache modules can be associated with a processor structure +/// in one or two ways, depending on the SMBIOS version. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING SocketDesignation; + UINT16 CacheConfiguration; + UINT16 MaximumCacheSize; + UINT16 InstalledSize; + CACHE_SRAM_TYPE_DATA SupportedSRAMType; + CACHE_SRAM_TYPE_DATA CurrentSRAMType; + UINT8 CacheSpeed; + UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA. + UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA. + UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA. + // + // Add for smbios 3.1.0 + // + UINT32 MaximumCacheSize2; + UINT32 InstalledSize2; +} SMBIOS_TABLE_TYPE7; + +/// +/// Port Connector Information - Connector Types. +/// +typedef enum { + PortConnectorTypeNone = 0x00, + PortConnectorTypeCentronics = 0x01, + PortConnectorTypeMiniCentronics = 0x02, + PortConnectorTypeProprietary = 0x03, + PortConnectorTypeDB25Male = 0x04, + PortConnectorTypeDB25Female = 0x05, + PortConnectorTypeDB15Male = 0x06, + PortConnectorTypeDB15Female = 0x07, + PortConnectorTypeDB9Male = 0x08, + PortConnectorTypeDB9Female = 0x09, + PortConnectorTypeRJ11 = 0x0A, + PortConnectorTypeRJ45 = 0x0B, + PortConnectorType50PinMiniScsi = 0x0C, + PortConnectorTypeMiniDin = 0x0D, + PortConnectorTypeMicroDin = 0x0E, + PortConnectorTypePS2 = 0x0F, + PortConnectorTypeInfrared = 0x10, + PortConnectorTypeHpHil = 0x11, + PortConnectorTypeUsb = 0x12, + PortConnectorTypeSsaScsi = 0x13, + PortConnectorTypeCircularDin8Male = 0x14, + PortConnectorTypeCircularDin8Female = 0x15, + PortConnectorTypeOnboardIde = 0x16, + PortConnectorTypeOnboardFloppy = 0x17, + PortConnectorType9PinDualInline = 0x18, + PortConnectorType25PinDualInline = 0x19, + PortConnectorType50PinDualInline = 0x1A, + PortConnectorType68PinDualInline = 0x1B, + PortConnectorTypeOnboardSoundInput = 0x1C, + PortConnectorTypeMiniCentronicsType14 = 0x1D, + PortConnectorTypeMiniCentronicsType26 = 0x1E, + PortConnectorTypeHeadPhoneMiniJack = 0x1F, + PortConnectorTypeBNC = 0x20, + PortConnectorType1394 = 0x21, + PortConnectorTypeSasSata = 0x22, + PortConnectorTypeUsbTypeC = 0x23, + PortConnectorTypePC98 = 0xA0, + PortConnectorTypePC98Hireso = 0xA1, + PortConnectorTypePCH98 = 0xA2, + PortConnectorTypePC98Note = 0xA3, + PortConnectorTypePC98Full = 0xA4, + PortConnectorTypeOther = 0xFF +} MISC_PORT_CONNECTOR_TYPE; + +/// +/// Port Connector Information - Port Types +/// +typedef enum { + PortTypeNone = 0x00, + PortTypeParallelXtAtCompatible = 0x01, + PortTypeParallelPortPs2 = 0x02, + PortTypeParallelPortEcp = 0x03, + PortTypeParallelPortEpp = 0x04, + PortTypeParallelPortEcpEpp = 0x05, + PortTypeSerialXtAtCompatible = 0x06, + PortTypeSerial16450Compatible = 0x07, + PortTypeSerial16550Compatible = 0x08, + PortTypeSerial16550ACompatible = 0x09, + PortTypeScsi = 0x0A, + PortTypeMidi = 0x0B, + PortTypeJoyStick = 0x0C, + PortTypeKeyboard = 0x0D, + PortTypeMouse = 0x0E, + PortTypeSsaScsi = 0x0F, + PortTypeUsb = 0x10, + PortTypeFireWire = 0x11, + PortTypePcmciaTypeI = 0x12, + PortTypePcmciaTypeII = 0x13, + PortTypePcmciaTypeIII = 0x14, + PortTypeCardBus = 0x15, + PortTypeAccessBusPort = 0x16, + PortTypeScsiII = 0x17, + PortTypeScsiWide = 0x18, + PortTypePC98 = 0x19, + PortTypePC98Hireso = 0x1A, + PortTypePCH98 = 0x1B, + PortTypeVideoPort = 0x1C, + PortTypeAudioPort = 0x1D, + PortTypeModemPort = 0x1E, + PortTypeNetworkPort = 0x1F, + PortTypeSata = 0x20, + PortTypeSas = 0x21, + PortTypeMfdp = 0x22, ///< Multi-Function Display Port + PortTypeThunderbolt = 0x23, + PortType8251Compatible = 0xA0, + PortType8251FifoCompatible = 0xA1, + PortTypeOther = 0xFF +} MISC_PORT_TYPE; + +/// +/// Port Connector Information (Type 8). +/// +/// The information in this structure defines the attributes of a system port connector, +/// e.g. parallel, serial, keyboard, or mouse ports. The port's type and connector information +/// are provided. One structure is present for each port provided by the system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING InternalReferenceDesignator; + UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE. + SMBIOS_TABLE_STRING ExternalReferenceDesignator; + UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE. + UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE. +} SMBIOS_TABLE_TYPE8; + +/// +/// System Slots - Slot Type +/// +typedef enum { + SlotTypeOther = 0x01, + SlotTypeUnknown = 0x02, + SlotTypeIsa = 0x03, + SlotTypeMca = 0x04, + SlotTypeEisa = 0x05, + SlotTypePci = 0x06, + SlotTypePcmcia = 0x07, + SlotTypeVlVesa = 0x08, + SlotTypeProprietary = 0x09, + SlotTypeProcessorCardSlot = 0x0A, + SlotTypeProprietaryMemoryCardSlot = 0x0B, + SlotTypeIORiserCardSlot = 0x0C, + SlotTypeNuBus = 0x0D, + SlotTypePci66MhzCapable = 0x0E, + SlotTypeAgp = 0x0F, + SlotTypeApg2X = 0x10, + SlotTypeAgp4X = 0x11, + SlotTypePciX = 0x12, + SlotTypeAgp8X = 0x13, + SlotTypeM2Socket1_DP = 0x14, + SlotTypeM2Socket1_SD = 0x15, + SlotTypeM2Socket2 = 0x16, + SlotTypeM2Socket3 = 0x17, + SlotTypeMxmTypeI = 0x18, + SlotTypeMxmTypeII = 0x19, + SlotTypeMxmTypeIIIStandard = 0x1A, + SlotTypeMxmTypeIIIHe = 0x1B, + SlotTypeMxmTypeIV = 0x1C, + SlotTypeMxm30TypeA = 0x1D, + SlotTypeMxm30TypeB = 0x1E, + SlotTypePciExpressGen2Sff_8639 = 0x1F, + SlotTypePciExpressGen3Sff_8639 = 0x20, + SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs. + SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs. + SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card. + SlotTypeCXLFlexbus10 = 0x30, + SlotTypePC98C20 = 0xA0, + SlotTypePC98C24 = 0xA1, + SlotTypePC98E = 0xA2, + SlotTypePC98LocalBus = 0xA3, + SlotTypePC98Card = 0xA4, + SlotTypePciExpress = 0xA5, + SlotTypePciExpressX1 = 0xA6, + SlotTypePciExpressX2 = 0xA7, + SlotTypePciExpressX4 = 0xA8, + SlotTypePciExpressX8 = 0xA9, + SlotTypePciExpressX16 = 0xAA, + SlotTypePciExpressGen2 = 0xAB, + SlotTypePciExpressGen2X1 = 0xAC, + SlotTypePciExpressGen2X2 = 0xAD, + SlotTypePciExpressGen2X4 = 0xAE, + SlotTypePciExpressGen2X8 = 0xAF, + SlotTypePciExpressGen2X16 = 0xB0, + SlotTypePciExpressGen3 = 0xB1, + SlotTypePciExpressGen3X1 = 0xB2, + SlotTypePciExpressGen3X2 = 0xB3, + SlotTypePciExpressGen3X4 = 0xB4, + SlotTypePciExpressGen3X8 = 0xB5, + SlotTypePciExpressGen3X16 = 0xB6, + SlotTypePciExpressGen4 = 0xB8, + SlotTypePciExpressGen4X1 = 0xB9, + SlotTypePciExpressGen4X2 = 0xBA, + SlotTypePciExpressGen4X4 = 0xBB, + SlotTypePciExpressGen4X8 = 0xBC, + SlotTypePciExpressGen4X16 = 0xBD +} MISC_SLOT_TYPE; + +/// +/// System Slots - Slot Data Bus Width. +/// +typedef enum { + SlotDataBusWidthOther = 0x01, + SlotDataBusWidthUnknown = 0x02, + SlotDataBusWidth8Bit = 0x03, + SlotDataBusWidth16Bit = 0x04, + SlotDataBusWidth32Bit = 0x05, + SlotDataBusWidth64Bit = 0x06, + SlotDataBusWidth128Bit = 0x07, + SlotDataBusWidth1X = 0x08, ///< Or X1 + SlotDataBusWidth2X = 0x09, ///< Or X2 + SlotDataBusWidth4X = 0x0A, ///< Or X4 + SlotDataBusWidth8X = 0x0B, ///< Or X8 + SlotDataBusWidth12X = 0x0C, ///< Or X12 + SlotDataBusWidth16X = 0x0D, ///< Or X16 + SlotDataBusWidth32X = 0x0E ///< Or X32 +} MISC_SLOT_DATA_BUS_WIDTH; + +/// +/// System Slots - Current Usage. +/// +typedef enum { + SlotUsageOther = 0x01, + SlotUsageUnknown = 0x02, + SlotUsageAvailable = 0x03, + SlotUsageInUse = 0x04, + SlotUsageUnavailable = 0x05 +} MISC_SLOT_USAGE; + +/// +/// System Slots - Slot Length. +/// +typedef enum { + SlotLengthOther = 0x01, + SlotLengthUnknown = 0x02, + SlotLengthShort = 0x03, + SlotLengthLong = 0x04 +} MISC_SLOT_LENGTH; + +/// +/// System Slots - Slot Characteristics 1. +/// +typedef struct { + UINT8 CharacteristicsUnknown :1; + UINT8 Provides50Volts :1; + UINT8 Provides33Volts :1; + UINT8 SharedSlot :1; + UINT8 PcCard16Supported :1; + UINT8 CardBusSupported :1; + UINT8 ZoomVideoSupported :1; + UINT8 ModemRingResumeSupported:1; +} MISC_SLOT_CHARACTERISTICS1; +/// +/// System Slots - Slot Characteristics 2. +/// +typedef struct { + UINT8 PmeSignalSupported :1; + UINT8 HotPlugDevicesSupported :1; + UINT8 SmbusSignalSupported :1; + UINT8 BifurcationSupported :1; + UINT8 AsyncSurpriseRemoval :1; + UINT8 FlexbusSlotCxl10Capable :1; + UINT8 FlexbusSlotCxl20Capable :1; + UINT8 Reserved :1; ///< Set to 0. +} MISC_SLOT_CHARACTERISTICS2; + +/// +/// System Slots - Peer Segment/Bus/Device/Function/Width Groups +/// +typedef struct { + UINT16 SegmentGroupNum; + UINT8 BusNum; + UINT8 DevFuncNum; + UINT8 DataBusWidth; +} MISC_SLOT_PEER_GROUP; + +/// +/// System Slots (Type 9) +/// +/// The information in this structure defines the attributes of a system slot. +/// One structure is provided for each slot in the system. +/// +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING SlotDesignation; + UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE. + UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH. + UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE. + UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH. + UINT16 SlotID; + MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1; + MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2; + // + // Add for smbios 2.6 + // + UINT16 SegmentGroupNum; + UINT8 BusNum; + UINT8 DevFuncNum; + // + // Add for smbios 3.2 + // + UINT8 DataBusWidth; + UINT8 PeerGroupingCount; + MISC_SLOT_PEER_GROUP PeerGroups[1]; + // + // Add for smbios 3.4 + // + UINT8 SlotInformation; + UINT8 SlotPhysicalWidth; + UINT16 SlotPitch; +} SMBIOS_TABLE_TYPE9; + +/// +/// On Board Devices Information - Device Types. +/// +typedef enum { + OnBoardDeviceTypeOther = 0x01, + OnBoardDeviceTypeUnknown = 0x02, + OnBoardDeviceTypeVideo = 0x03, + OnBoardDeviceTypeScsiController = 0x04, + OnBoardDeviceTypeEthernet = 0x05, + OnBoardDeviceTypeTokenRing = 0x06, + OnBoardDeviceTypeSound = 0x07, + OnBoardDeviceTypePATAController = 0x08, + OnBoardDeviceTypeSATAController = 0x09, + OnBoardDeviceTypeSASController = 0x0A +} MISC_ONBOARD_DEVICE_TYPE; + +/// +/// Device Item Entry +/// +typedef struct { + UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE. + ///< Bit 7 - 1 : device enabled, 0 : device disabled. + SMBIOS_TABLE_STRING DescriptionString; +} DEVICE_STRUCT; + +/// +/// On Board Devices Information (Type 10, obsolete). +/// +/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended +/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both +/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information. +/// The information in this structure defines the attributes of devices that are onboard (soldered onto) +/// a system element, usually the baseboard. In general, an entry in this table implies that the BIOS +/// has some level of control over the enabling of the associated device for use by the system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + DEVICE_STRUCT Device[1]; +} SMBIOS_TABLE_TYPE10; + +/// +/// OEM Strings (Type 11). +/// This structure contains free form strings defined by the OEM. Examples of this are: +/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 StringCount; +} SMBIOS_TABLE_TYPE11; + +/// +/// System Configuration Options (Type 12). +/// +/// This structure contains information required to configure the base board's Jumpers and Switches. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 StringCount; +} SMBIOS_TABLE_TYPE12; + + +/// +/// BIOS Language Information (Type 13). +/// +/// The information in this structure defines the installable language attributes of the BIOS. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 InstallableLanguages; + UINT8 Flags; + UINT8 Reserved[15]; + SMBIOS_TABLE_STRING CurrentLanguages; +} SMBIOS_TABLE_TYPE13; + +/// +/// Group Item Entry +/// +typedef struct { + UINT8 ItemType; + UINT16 ItemHandle; +} GROUP_STRUCT; + +/// +/// Group Associations (Type 14). +/// +/// The Group Associations structure is provided for OEMs who want to specify +/// the arrangement or hierarchy of certain components (including other Group Associations) +/// within the system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING GroupName; + GROUP_STRUCT Group[1]; +} SMBIOS_TABLE_TYPE14; + +/// +/// System Event Log - Event Log Types. +/// +typedef enum { + EventLogTypeReserved = 0x00, + EventLogTypeSingleBitECC = 0x01, + EventLogTypeMultiBitECC = 0x02, + EventLogTypeParityMemErr = 0x03, + EventLogTypeBusTimeOut = 0x04, + EventLogTypeIOChannelCheck = 0x05, + EventLogTypeSoftwareNMI = 0x06, + EventLogTypePOSTMemResize = 0x07, + EventLogTypePOSTErr = 0x08, + EventLogTypePCIParityErr = 0x09, + EventLogTypePCISystemErr = 0x0A, + EventLogTypeCPUFailure = 0x0B, + EventLogTypeEISATimeOut = 0x0C, + EventLogTypeMemLogDisabled = 0x0D, + EventLogTypeLoggingDisabled = 0x0E, + EventLogTypeSysLimitExce = 0x10, + EventLogTypeAsyncHWTimer = 0x11, + EventLogTypeSysConfigInfo = 0x12, + EventLogTypeHDInfo = 0x13, + EventLogTypeSysReconfig = 0x14, + EventLogTypeUncorrectCPUErr = 0x15, + EventLogTypeAreaResetAndClr = 0x16, + EventLogTypeSystemBoot = 0x17, + EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F + EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE + EventLogTypeEndOfLog = 0xFF +} EVENT_LOG_TYPE_DATA; + +/// +/// System Event Log - Variable Data Format Types. +/// +typedef enum { + EventLogVariableNone = 0x00, + EventLogVariableHandle = 0x01, + EventLogVariableMutilEvent = 0x02, + EventLogVariableMutilEventHandle = 0x03, + EventLogVariablePOSTResultBitmap = 0x04, + EventLogVariableSysManagementType = 0x05, + EventLogVariableMutliEventSysManagmentType = 0x06, + EventLogVariableUnused = 0x07, + EventLogVariableOEMAssigned = 0x80 +} EVENT_LOG_VARIABLE_DATA; + +/// +/// Event Log Type Descriptors +/// +typedef struct { + UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA. + UINT8 DataFormatType; +} EVENT_LOG_TYPE; + +/// +/// System Event Log (Type 15). +/// +/// The presence of this structure within the SMBIOS data returned for a system indicates +/// that the system supports an event log. An event log is a fixed-length area within a +/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header +/// record, followed by one or more variable-length log records. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT16 LogAreaLength; + UINT16 LogHeaderStartOffset; + UINT16 LogDataStartOffset; + UINT8 AccessMethod; + UINT8 LogStatus; + UINT32 LogChangeToken; + UINT32 AccessMethodAddress; + UINT8 LogHeaderFormat; + UINT8 NumberOfSupportedLogTypeDescriptors; + UINT8 LengthOfLogTypeDescriptor; + EVENT_LOG_TYPE EventLogTypeDescriptors[1]; +} SMBIOS_TABLE_TYPE15; + +/// +/// Physical Memory Array - Location. +/// +typedef enum { + MemoryArrayLocationOther = 0x01, + MemoryArrayLocationUnknown = 0x02, + MemoryArrayLocationSystemBoard = 0x03, + MemoryArrayLocationIsaAddonCard = 0x04, + MemoryArrayLocationEisaAddonCard = 0x05, + MemoryArrayLocationPciAddonCard = 0x06, + MemoryArrayLocationMcaAddonCard = 0x07, + MemoryArrayLocationPcmciaAddonCard = 0x08, + MemoryArrayLocationProprietaryAddonCard = 0x09, + MemoryArrayLocationNuBus = 0x0A, + MemoryArrayLocationPc98C20AddonCard = 0xA0, + MemoryArrayLocationPc98C24AddonCard = 0xA1, + MemoryArrayLocationPc98EAddonCard = 0xA2, + MemoryArrayLocationPc98LocalBusAddonCard = 0xA3, + MemoryArrayLocationCXLAddonCard = 0xA4 +} MEMORY_ARRAY_LOCATION; + +/// +/// Physical Memory Array - Use. +/// +typedef enum { + MemoryArrayUseOther = 0x01, + MemoryArrayUseUnknown = 0x02, + MemoryArrayUseSystemMemory = 0x03, + MemoryArrayUseVideoMemory = 0x04, + MemoryArrayUseFlashMemory = 0x05, + MemoryArrayUseNonVolatileRam = 0x06, + MemoryArrayUseCacheMemory = 0x07 +} MEMORY_ARRAY_USE; + +/// +/// Physical Memory Array - Error Correction Types. +/// +typedef enum { + MemoryErrorCorrectionOther = 0x01, + MemoryErrorCorrectionUnknown = 0x02, + MemoryErrorCorrectionNone = 0x03, + MemoryErrorCorrectionParity = 0x04, + MemoryErrorCorrectionSingleBitEcc = 0x05, + MemoryErrorCorrectionMultiBitEcc = 0x06, + MemoryErrorCorrectionCrc = 0x07 +} MEMORY_ERROR_CORRECTION; + +/// +/// Physical Memory Array (Type 16). +/// +/// This structure describes a collection of memory devices that operate +/// together to form a memory address space. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION. + UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE. + UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION. + UINT32 MaximumCapacity; + UINT16 MemoryErrorInformationHandle; + UINT16 NumberOfMemoryDevices; + // + // Add for smbios 2.7 + // + UINT64 ExtendedMaximumCapacity; +} SMBIOS_TABLE_TYPE16; + +/// +/// Memory Device - Form Factor. +/// +typedef enum { + MemoryFormFactorOther = 0x01, + MemoryFormFactorUnknown = 0x02, + MemoryFormFactorSimm = 0x03, + MemoryFormFactorSip = 0x04, + MemoryFormFactorChip = 0x05, + MemoryFormFactorDip = 0x06, + MemoryFormFactorZip = 0x07, + MemoryFormFactorProprietaryCard = 0x08, + MemoryFormFactorDimm = 0x09, + MemoryFormFactorTsop = 0x0A, + MemoryFormFactorRowOfChips = 0x0B, + MemoryFormFactorRimm = 0x0C, + MemoryFormFactorSodimm = 0x0D, + MemoryFormFactorSrimm = 0x0E, + MemoryFormFactorFbDimm = 0x0F, + MemoryFormFactorDie = 0x10 +} MEMORY_FORM_FACTOR; + +/// +/// Memory Device - Type +/// +typedef enum { + MemoryTypeOther = 0x01, + MemoryTypeUnknown = 0x02, + MemoryTypeDram = 0x03, + MemoryTypeEdram = 0x04, + MemoryTypeVram = 0x05, + MemoryTypeSram = 0x06, + MemoryTypeRam = 0x07, + MemoryTypeRom = 0x08, + MemoryTypeFlash = 0x09, + MemoryTypeEeprom = 0x0A, + MemoryTypeFeprom = 0x0B, + MemoryTypeEprom = 0x0C, + MemoryTypeCdram = 0x0D, + MemoryType3Dram = 0x0E, + MemoryTypeSdram = 0x0F, + MemoryTypeSgram = 0x10, + MemoryTypeRdram = 0x11, + MemoryTypeDdr = 0x12, + MemoryTypeDdr2 = 0x13, + MemoryTypeDdr2FbDimm = 0x14, + MemoryTypeDdr3 = 0x18, + MemoryTypeFbd2 = 0x19, + MemoryTypeDdr4 = 0x1A, + MemoryTypeLpddr = 0x1B, + MemoryTypeLpddr2 = 0x1C, + MemoryTypeLpddr3 = 0x1D, + MemoryTypeLpddr4 = 0x1E, + MemoryTypeLogicalNonVolatileDevice = 0x1F, + MemoryTypeHBM = 0x20, + MemoryTypeHBM2 = 0x21, + MemoryTypeDdr5 = 0x22, + MemoryTypeLpddr5 = 0x23 +} MEMORY_DEVICE_TYPE; + +/// +/// Memory Device - Type Detail +/// +typedef struct { + UINT16 Reserved :1; + UINT16 Other :1; + UINT16 Unknown :1; + UINT16 FastPaged :1; + UINT16 StaticColumn :1; + UINT16 PseudoStatic :1; + UINT16 Rambus :1; + UINT16 Synchronous :1; + UINT16 Cmos :1; + UINT16 Edo :1; + UINT16 WindowDram :1; + UINT16 CacheDram :1; + UINT16 Nonvolatile :1; + UINT16 Registered :1; + UINT16 Unbuffered :1; + UINT16 LrDimm :1; +} MEMORY_DEVICE_TYPE_DETAIL; + +/// +/// Memory Device - Memory Technology +/// +typedef enum { + MemoryTechnologyOther = 0x01, + MemoryTechnologyUnknown = 0x02, + MemoryTechnologyDram = 0x03, + MemoryTechnologyNvdimmN = 0x04, + MemoryTechnologyNvdimmF = 0x05, + MemoryTechnologyNvdimmP = 0x06, + // + // This definition is updated to represent Intel + // Optane DC Persistent Memory in SMBIOS spec 3.4.0 + // + MemoryTechnologyIntelOptanePersistentMemory = 0x07 + +} MEMORY_DEVICE_TECHNOLOGY; + +/// +/// Memory Device - Memory Operating Mode Capability +/// +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT16 Reserved :1; ///< Set to 0. + UINT16 Other :1; + UINT16 Unknown :1; + UINT16 VolatileMemory :1; + UINT16 ByteAccessiblePersistentMemory :1; + UINT16 BlockAccessiblePersistentMemory :1; + UINT16 Reserved2 :10; ///< Set to 0. + } Bits; + /// + /// All bit fields as a 16-bit value + /// + UINT16 Uint16; +} MEMORY_DEVICE_OPERATING_MODE_CAPABILITY; + +/// +/// Memory Device (Type 17). +/// +/// This structure describes a single memory device that is part of +/// a larger Physical Memory Array (Type 16). +/// Note: If a system includes memory-device sockets, the SMBIOS implementation +/// includes a Memory Device structure instance for each slot, whether or not the +/// socket is currently populated. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT16 MemoryArrayHandle; + UINT16 MemoryErrorInformationHandle; + UINT16 TotalWidth; + UINT16 DataWidth; + UINT16 Size; + UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR. + UINT8 DeviceSet; + SMBIOS_TABLE_STRING DeviceLocator; + SMBIOS_TABLE_STRING BankLocator; + UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE. + MEMORY_DEVICE_TYPE_DETAIL TypeDetail; + UINT16 Speed; + SMBIOS_TABLE_STRING Manufacturer; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING AssetTag; + SMBIOS_TABLE_STRING PartNumber; + // + // Add for smbios 2.6 + // + UINT8 Attributes; + // + // Add for smbios 2.7 + // + UINT32 ExtendedSize; + // + // Keep using name "ConfiguredMemoryClockSpeed" for compatibility + // although this field is renamed from "Configured Memory Clock Speed" + // to "Configured Memory Speed" in smbios 3.2.0. + // + UINT16 ConfiguredMemoryClockSpeed; + // + // Add for smbios 2.8.0 + // + UINT16 MinimumVoltage; + UINT16 MaximumVoltage; + UINT16 ConfiguredVoltage; + // + // Add for smbios 3.2.0 + // + UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY + MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability; + SMBIOS_TABLE_STRING FirmwareVersion; + UINT16 ModuleManufacturerID; + UINT16 ModuleProductID; + UINT16 MemorySubsystemControllerManufacturerID; + UINT16 MemorySubsystemControllerProductID; + UINT64 NonVolatileSize; + UINT64 VolatileSize; + UINT64 CacheSize; + UINT64 LogicalSize; + // + // Add for smbios 3.3.0 + // + UINT32 ExtendedSpeed; + UINT32 ExtendedConfiguredMemorySpeed; +} SMBIOS_TABLE_TYPE17; + +/// +/// 32-bit Memory Error Information - Error Type. +/// +typedef enum { + MemoryErrorOther = 0x01, + MemoryErrorUnknown = 0x02, + MemoryErrorOk = 0x03, + MemoryErrorBadRead = 0x04, + MemoryErrorParity = 0x05, + MemoryErrorSigleBit = 0x06, + MemoryErrorDoubleBit = 0x07, + MemoryErrorMultiBit = 0x08, + MemoryErrorNibble = 0x09, + MemoryErrorChecksum = 0x0A, + MemoryErrorCrc = 0x0B, + MemoryErrorCorrectSingleBit = 0x0C, + MemoryErrorCorrected = 0x0D, + MemoryErrorUnCorrectable = 0x0E +} MEMORY_ERROR_TYPE; + +/// +/// 32-bit Memory Error Information - Error Granularity. +/// +typedef enum { + MemoryGranularityOther = 0x01, + MemoryGranularityOtherUnknown = 0x02, + MemoryGranularityDeviceLevel = 0x03, + MemoryGranularityMemPartitionLevel = 0x04 +} MEMORY_ERROR_GRANULARITY; + +/// +/// 32-bit Memory Error Information - Error Operation. +/// +typedef enum { + MemoryErrorOperationOther = 0x01, + MemoryErrorOperationUnknown = 0x02, + MemoryErrorOperationRead = 0x03, + MemoryErrorOperationWrite = 0x04, + MemoryErrorOperationPartialWrite = 0x05 +} MEMORY_ERROR_OPERATION; + +/// +/// 32-bit Memory Error Information (Type 18). +/// +/// This structure identifies the specifics of an error that might be detected +/// within a Physical Memory Array. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE. + UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY. + UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION. + UINT32 VendorSyndrome; + UINT32 MemoryArrayErrorAddress; + UINT32 DeviceErrorAddress; + UINT32 ErrorResolution; +} SMBIOS_TABLE_TYPE18; + +/// +/// Memory Array Mapped Address (Type 19). +/// +/// This structure provides the address mapping for a Physical Memory Array. +/// One structure is present for each contiguous address range described. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT32 StartingAddress; + UINT32 EndingAddress; + UINT16 MemoryArrayHandle; + UINT8 PartitionWidth; + // + // Add for smbios 2.7 + // + UINT64 ExtendedStartingAddress; + UINT64 ExtendedEndingAddress; +} SMBIOS_TABLE_TYPE19; + +/// +/// Memory Device Mapped Address (Type 20). +/// +/// This structure maps memory address space usually to a device-level granularity. +/// One structure is present for each contiguous address range described. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT32 StartingAddress; + UINT32 EndingAddress; + UINT16 MemoryDeviceHandle; + UINT16 MemoryArrayMappedAddressHandle; + UINT8 PartitionRowPosition; + UINT8 InterleavePosition; + UINT8 InterleavedDataDepth; + // + // Add for smbios 2.7 + // + UINT64 ExtendedStartingAddress; + UINT64 ExtendedEndingAddress; +} SMBIOS_TABLE_TYPE20; + +/// +/// Built-in Pointing Device - Type +/// +typedef enum { + PointingDeviceTypeOther = 0x01, + PointingDeviceTypeUnknown = 0x02, + PointingDeviceTypeMouse = 0x03, + PointingDeviceTypeTrackBall = 0x04, + PointingDeviceTypeTrackPoint = 0x05, + PointingDeviceTypeGlidePoint = 0x06, + PointingDeviceTouchPad = 0x07, + PointingDeviceTouchScreen = 0x08, + PointingDeviceOpticalSensor = 0x09 +} BUILTIN_POINTING_DEVICE_TYPE; + +/// +/// Built-in Pointing Device - Interface. +/// +typedef enum { + PointingDeviceInterfaceOther = 0x01, + PointingDeviceInterfaceUnknown = 0x02, + PointingDeviceInterfaceSerial = 0x03, + PointingDeviceInterfacePs2 = 0x04, + PointingDeviceInterfaceInfrared = 0x05, + PointingDeviceInterfaceHpHil = 0x06, + PointingDeviceInterfaceBusMouse = 0x07, + PointingDeviceInterfaceADB = 0x08, + PointingDeviceInterfaceBusMouseDB9 = 0xA0, + PointingDeviceInterfaceBusMouseMicroDin = 0xA1, + PointingDeviceInterfaceUsb = 0xA2 +} BUILTIN_POINTING_DEVICE_INTERFACE; + +/// +/// Built-in Pointing Device (Type 21). +/// +/// This structure describes the attributes of the built-in pointing device for the +/// system. The presence of this structure does not imply that the built-in +/// pointing device is active for the system's use! +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE. + UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE. + UINT8 NumberOfButtons; +} SMBIOS_TABLE_TYPE21; + +/// +/// Portable Battery - Device Chemistry +/// +typedef enum { + PortableBatteryDeviceChemistryOther = 0x01, + PortableBatteryDeviceChemistryUnknown = 0x02, + PortableBatteryDeviceChemistryLeadAcid = 0x03, + PortableBatteryDeviceChemistryNickelCadmium = 0x04, + PortableBatteryDeviceChemistryNickelMetalHydride = 0x05, + PortableBatteryDeviceChemistryLithiumIon = 0x06, + PortableBatteryDeviceChemistryZincAir = 0x07, + PortableBatteryDeviceChemistryLithiumPolymer = 0x08 +} PORTABLE_BATTERY_DEVICE_CHEMISTRY; + +/// +/// Portable Battery (Type 22). +/// +/// This structure describes the attributes of the portable battery(s) for the system. +/// The structure contains the static attributes for the group. Each structure describes +/// a single battery pack's attributes. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Location; + SMBIOS_TABLE_STRING Manufacturer; + SMBIOS_TABLE_STRING ManufactureDate; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING DeviceName; + UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY. + UINT16 DeviceCapacity; + UINT16 DesignVoltage; + SMBIOS_TABLE_STRING SBDSVersionNumber; + UINT8 MaximumErrorInBatteryData; + UINT16 SBDSSerialNumber; + UINT16 SBDSManufactureDate; + SMBIOS_TABLE_STRING SBDSDeviceChemistry; + UINT8 DesignCapacityMultiplier; + UINT32 OEMSpecific; +} SMBIOS_TABLE_TYPE22; + +/// +/// System Reset (Type 23) +/// +/// This structure describes whether Automatic System Reset functions enabled (Status). +/// If the system has a watchdog Timer and the timer is not reset (Timer Reset) +/// before the Interval elapses, an automatic system reset will occur. The system will re-boot +/// according to the Boot Option. This function may repeat until the Limit is reached, at which time +/// the system will re-boot according to the Boot Option at Limit. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 Capabilities; + UINT16 ResetCount; + UINT16 ResetLimit; + UINT16 TimerInterval; + UINT16 Timeout; +} SMBIOS_TABLE_TYPE23; + +/// +/// Hardware Security (Type 24). +/// +/// This structure describes the system-wide hardware security settings. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 HardwareSecuritySettings; +} SMBIOS_TABLE_TYPE24; + +/// +/// System Power Controls (Type 25). +/// +/// This structure describes the attributes for controlling the main power supply to the system. +/// Software that interprets this structure uses the month, day, hour, minute, and second values +/// to determine the number of seconds until the next power-on of the system. The presence of +/// this structure implies that a timed power-on facility is available for the system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 NextScheduledPowerOnMonth; + UINT8 NextScheduledPowerOnDayOfMonth; + UINT8 NextScheduledPowerOnHour; + UINT8 NextScheduledPowerOnMinute; + UINT8 NextScheduledPowerOnSecond; +} SMBIOS_TABLE_TYPE25; + +/// +/// Voltage Probe - Location and Status. +/// +typedef struct { + UINT8 VoltageProbeSite :5; + UINT8 VoltageProbeStatus :3; +} MISC_VOLTAGE_PROBE_LOCATION; + +/// +/// Voltage Probe (Type 26) +/// +/// This describes the attributes for a voltage probe in the system. +/// Each structure describes a single voltage probe. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Description; + MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus; + UINT16 MaximumValue; + UINT16 MinimumValue; + UINT16 Resolution; + UINT16 Tolerance; + UINT16 Accuracy; + UINT32 OEMDefined; + UINT16 NominalValue; +} SMBIOS_TABLE_TYPE26; + +/// +/// Cooling Device - Device Type and Status. +/// +typedef struct { + UINT8 CoolingDevice :5; + UINT8 CoolingDeviceStatus :3; +} MISC_COOLING_DEVICE_TYPE; + +/// +/// Cooling Device (Type 27) +/// +/// This structure describes the attributes for a cooling device in the system. +/// Each structure describes a single cooling device. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT16 TemperatureProbeHandle; + MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus; + UINT8 CoolingUnitGroup; + UINT32 OEMDefined; + UINT16 NominalSpeed; + // + // Add for smbios 2.7 + // + SMBIOS_TABLE_STRING Description; +} SMBIOS_TABLE_TYPE27; + +/// +/// Temperature Probe - Location and Status. +/// +typedef struct { + UINT8 TemperatureProbeSite :5; + UINT8 TemperatureProbeStatus :3; +} MISC_TEMPERATURE_PROBE_LOCATION; + +/// +/// Temperature Probe (Type 28). +/// +/// This structure describes the attributes for a temperature probe in the system. +/// Each structure describes a single temperature probe. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Description; + MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus; + UINT16 MaximumValue; + UINT16 MinimumValue; + UINT16 Resolution; + UINT16 Tolerance; + UINT16 Accuracy; + UINT32 OEMDefined; + UINT16 NominalValue; +} SMBIOS_TABLE_TYPE28; + +/// +/// Electrical Current Probe - Location and Status. +/// +typedef struct { + UINT8 ElectricalCurrentProbeSite :5; + UINT8 ElectricalCurrentProbeStatus :3; +} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION; + +/// +/// Electrical Current Probe (Type 29). +/// +/// This structure describes the attributes for an electrical current probe in the system. +/// Each structure describes a single electrical current probe. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Description; + MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus; + UINT16 MaximumValue; + UINT16 MinimumValue; + UINT16 Resolution; + UINT16 Tolerance; + UINT16 Accuracy; + UINT32 OEMDefined; + UINT16 NominalValue; +} SMBIOS_TABLE_TYPE29; + +/// +/// Out-of-Band Remote Access (Type 30). +/// +/// This structure describes the attributes and policy settings of a hardware facility +/// that may be used to gain remote access to a hardware system when the operating system +/// is not available due to power-down status, hardware failures, or boot failures. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING ManufacturerName; + UINT8 Connections; +} SMBIOS_TABLE_TYPE30; + +/// +/// Boot Integrity Services (BIS) Entry Point (Type 31). +/// +/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS). +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 Checksum; + UINT8 Reserved1; + UINT16 Reserved2; + UINT32 BisEntry16; + UINT32 BisEntry32; + UINT64 Reserved3; + UINT32 Reserved4; +} SMBIOS_TABLE_TYPE31; + +/// +/// System Boot Information - System Boot Status. +/// +typedef enum { + BootInformationStatusNoError = 0x00, + BootInformationStatusNoBootableMedia = 0x01, + BootInformationStatusNormalOSFailedLoading = 0x02, + BootInformationStatusFirmwareDetectedFailure = 0x03, + BootInformationStatusOSDetectedFailure = 0x04, + BootInformationStatusUserRequestedBoot = 0x05, + BootInformationStatusSystemSecurityViolation = 0x06, + BootInformationStatusPreviousRequestedImage = 0x07, + BootInformationStatusWatchdogTimerExpired = 0x08, + BootInformationStatusStartReserved = 0x09, + BootInformationStatusStartOemSpecific = 0x80, + BootInformationStatusStartProductSpecific = 0xC0 +} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE; + +/// +/// System Boot Information (Type 32). +/// +/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the +/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management +/// application via this structure. When used in the PXE environment, for example, +/// this code identifies the reason the PXE was initiated and can be used by boot-image +/// software to further automate an enterprise's PXE sessions. For example, an enterprise +/// could choose to automatically download a hardware-diagnostic image to a client whose +/// reason code indicated either a firmware- or operating system-detected hardware failure. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 Reserved[6]; + UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE. +} SMBIOS_TABLE_TYPE32; + +/// +/// 64-bit Memory Error Information (Type 33). +/// +/// This structure describes an error within a Physical Memory Array, +/// when the error address is above 4G (0xFFFFFFFF). +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE. + UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY. + UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION. + UINT32 VendorSyndrome; + UINT64 MemoryArrayErrorAddress; + UINT64 DeviceErrorAddress; + UINT32 ErrorResolution; +} SMBIOS_TABLE_TYPE33; + +/// +/// Management Device - Type. +/// +typedef enum { + ManagementDeviceTypeOther = 0x01, + ManagementDeviceTypeUnknown = 0x02, + ManagementDeviceTypeLm75 = 0x03, + ManagementDeviceTypeLm78 = 0x04, + ManagementDeviceTypeLm79 = 0x05, + ManagementDeviceTypeLm80 = 0x06, + ManagementDeviceTypeLm81 = 0x07, + ManagementDeviceTypeAdm9240 = 0x08, + ManagementDeviceTypeDs1780 = 0x09, + ManagementDeviceTypeMaxim1617 = 0x0A, + ManagementDeviceTypeGl518Sm = 0x0B, + ManagementDeviceTypeW83781D = 0x0C, + ManagementDeviceTypeHt82H791 = 0x0D +} MISC_MANAGEMENT_DEVICE_TYPE; + +/// +/// Management Device - Address Type. +/// +typedef enum { + ManagementDeviceAddressTypeOther = 0x01, + ManagementDeviceAddressTypeUnknown = 0x02, + ManagementDeviceAddressTypeIOPort = 0x03, + ManagementDeviceAddressTypeMemory = 0x04, + ManagementDeviceAddressTypeSmbus = 0x05 +} MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE; + +/// +/// Management Device (Type 34). +/// +/// The information in this structure defines the attributes of a Management Device. +/// A Management Device might control one or more fans or voltage, current, or temperature +/// probes as defined by one or more Management Device Component structures. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Description; + UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE. + UINT32 Address; + UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE. +} SMBIOS_TABLE_TYPE34; + +/// +/// Management Device Component (Type 35) +/// +/// This structure associates a cooling device or environmental probe with structures +/// that define the controlling hardware device and (optionally) the component's thresholds. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING Description; + UINT16 ManagementDeviceHandle; + UINT16 ComponentHandle; + UINT16 ThresholdHandle; +} SMBIOS_TABLE_TYPE35; + +/// +/// Management Device Threshold Data (Type 36). +/// +/// The information in this structure defines threshold information for +/// a component (probe or cooling-unit) contained within a Management Device. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT16 LowerThresholdNonCritical; + UINT16 UpperThresholdNonCritical; + UINT16 LowerThresholdCritical; + UINT16 UpperThresholdCritical; + UINT16 LowerThresholdNonRecoverable; + UINT16 UpperThresholdNonRecoverable; +} SMBIOS_TABLE_TYPE36; + +/// +/// Memory Channel Entry. +/// +typedef struct { + UINT8 DeviceLoad; + UINT16 DeviceHandle; +} MEMORY_DEVICE; + +/// +/// Memory Channel - Channel Type. +/// +typedef enum { + MemoryChannelTypeOther = 0x01, + MemoryChannelTypeUnknown = 0x02, + MemoryChannelTypeRambus = 0x03, + MemoryChannelTypeSyncLink = 0x04 +} MEMORY_CHANNEL_TYPE; + +/// +/// Memory Channel (Type 37) +/// +/// The information in this structure provides the correlation between a Memory Channel +/// and its associated Memory Devices. Each device presents one or more loads to the channel. +/// The sum of all device loads cannot exceed the channel's defined maximum. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 ChannelType; + UINT8 MaximumChannelLoad; + UINT8 MemoryDeviceCount; + MEMORY_DEVICE MemoryDevice[1]; +} SMBIOS_TABLE_TYPE37; + +/// +/// IPMI Device Information - BMC Interface Type +/// +typedef enum { + IPMIDeviceInfoInterfaceTypeUnknown = 0x00, + IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style. + IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip. + IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer + IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface +} BMC_INTERFACE_TYPE; + +/// +/// IPMI Device Information (Type 38). +/// +/// The information in this structure defines the attributes of an +/// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC). +/// +/// The Type 42 structure can also be used to describe a physical management controller +/// host interface and one or more protocols that share that interface. If IPMI is not +/// shared with other protocols, either the Type 38 or Type 42 structures can be used. +/// Providing Type 38 is recommended for backward compatibility. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE. + UINT8 IPMISpecificationRevision; + UINT8 I2CSlaveAddress; + UINT8 NVStorageDeviceAddress; + UINT64 BaseAddress; + UINT8 BaseAddressModifier_InterruptInfo; + UINT8 InterruptNumber; +} SMBIOS_TABLE_TYPE38; + +/// +/// System Power Supply - Power Supply Characteristics. +/// +typedef struct { + UINT16 PowerSupplyHotReplaceable:1; + UINT16 PowerSupplyPresent :1; + UINT16 PowerSupplyUnplugged :1; + UINT16 InputVoltageRangeSwitch :4; + UINT16 PowerSupplyStatus :3; + UINT16 PowerSupplyType :4; + UINT16 Reserved :2; +} SYS_POWER_SUPPLY_CHARACTERISTICS; + +/// +/// System Power Supply (Type 39). +/// +/// This structure identifies attributes of a system power supply. One instance +/// of this record is present for each possible power supply in a system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 PowerUnitGroup; + SMBIOS_TABLE_STRING Location; + SMBIOS_TABLE_STRING DeviceName; + SMBIOS_TABLE_STRING Manufacturer; + SMBIOS_TABLE_STRING SerialNumber; + SMBIOS_TABLE_STRING AssetTagNumber; + SMBIOS_TABLE_STRING ModelPartNumber; + SMBIOS_TABLE_STRING RevisionLevel; + UINT16 MaxPowerCapacity; + SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics; + UINT16 InputVoltageProbeHandle; + UINT16 CoolingDeviceHandle; + UINT16 InputCurrentProbeHandle; +} SMBIOS_TABLE_TYPE39; + +/// +/// Additional Information Entry Format. +/// +typedef struct { + UINT8 EntryLength; + UINT16 ReferencedHandle; + UINT8 ReferencedOffset; + SMBIOS_TABLE_STRING EntryString; + UINT8 Value[1]; +} ADDITIONAL_INFORMATION_ENTRY; + +/// +/// Additional Information (Type 40). +/// +/// This structure is intended to provide additional information for handling unspecified +/// enumerated values and interim field updates in another structure. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 NumberOfAdditionalInformationEntries; + ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1]; +} SMBIOS_TABLE_TYPE40; + +/// +/// Onboard Devices Extended Information - Onboard Device Types. +/// +typedef enum{ + OnBoardDeviceExtendedTypeOther = 0x01, + OnBoardDeviceExtendedTypeUnknown = 0x02, + OnBoardDeviceExtendedTypeVideo = 0x03, + OnBoardDeviceExtendedTypeScsiController = 0x04, + OnBoardDeviceExtendedTypeEthernet = 0x05, + OnBoardDeviceExtendedTypeTokenRing = 0x06, + OnBoardDeviceExtendedTypeSound = 0x07, + OnBoardDeviceExtendedTypePATAController = 0x08, + OnBoardDeviceExtendedTypeSATAController = 0x09, + OnBoardDeviceExtendedTypeSASController = 0x0A +} ONBOARD_DEVICE_EXTENDED_INFO_TYPE; + +/// +/// Onboard Devices Extended Information (Type 41). +/// +/// The information in this structure defines the attributes of devices that +/// are onboard (soldered onto) a system element, usually the baseboard. +/// In general, an entry in this table implies that the BIOS has some level of +/// control over the enabling of the associated device for use by the system. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING ReferenceDesignation; + UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE + UINT8 DeviceTypeInstance; + UINT16 SegmentGroupNum; + UINT8 BusNum; + UINT8 DevFuncNum; +} SMBIOS_TABLE_TYPE41; + +/// +/// Management Controller Host Interface - Protocol Record Data Format. +/// +typedef struct { + UINT8 ProtocolType; + UINT8 ProtocolTypeDataLen; + UINT8 ProtocolTypeData[1]; +} MC_HOST_INTERFACE_PROTOCOL_RECORD; + +/// +/// Management Controller Host Interface - Interface Types. +/// 00h - 3Fh: MCTP Host Interfaces +/// +typedef enum{ + MCHostInterfaceTypeNetworkHostInterface = 0x40, + MCHostInterfaceTypeOemDefined = 0xF0 +} MC_HOST_INTERFACE_TYPE; + +/// +/// Management Controller Host Interface - Protocol Types. +/// +typedef enum{ + MCHostInterfaceProtocolTypeIPMI = 0x02, + MCHostInterfaceProtocolTypeMCTP = 0x03, + MCHostInterfaceProtocolTypeRedfishOverIP = 0x04, + MCHostInterfaceProtocolTypeOemDefined = 0xF0 +} MC_HOST_INTERFACE_PROTOCOL_TYPE; + +/// +/// Management Controller Host Interface (Type 42). +/// +/// The information in this structure defines the attributes of a Management +/// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms. +/// +/// Type 42 should be used for management controller host interfaces that use protocols +/// other than IPMI or that use multiple protocols on a single host interface type. +/// +/// This structure should also be provided if IPMI is shared with other protocols +/// over the same interface hardware. If IPMI is not shared with other protocols, +/// either the Type 38 or Type 42 structures can be used. Providing Type 38 is +/// recommended for backward compatibility. The structures are not required to +/// be mutually exclusive. Type 38 and Type 42 structures may be implemented +/// simultaneously to provide backward compatibility with IPMI applications or drivers +/// that do not yet recognize the Type 42 structure. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE + UINT8 InterfaceTypeSpecificDataLength; + UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes +} SMBIOS_TABLE_TYPE42; + + +/// +/// Processor Specific Block - Processor Architecture Type +/// +typedef enum{ + ProcessorSpecificBlockArchTypeReserved = 0x00, + ProcessorSpecificBlockArchTypeIa32 = 0x01, + ProcessorSpecificBlockArchTypeX64 = 0x02, + ProcessorSpecificBlockArchTypeItanium = 0x03, + ProcessorSpecificBlockArchTypeAarch32 = 0x04, + ProcessorSpecificBlockArchTypeAarch64 = 0x05, + ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06, + ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07, + ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08 +} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE; + +/// +/// Processor Specific Block is the standard container of processor-specific data. +/// +typedef struct { + UINT8 Length; + UINT8 ProcessorArchType; + /// + /// Below followed by Processor-specific data + /// + /// +} PROCESSOR_SPECIFIC_BLOCK; + +/// +/// Processor Additional Information(Type 44). +/// +/// The information in this structure defines the processor additional information in case +/// SMBIOS type 4 is not sufficient to describe processor characteristics. +/// The SMBIOS type 44 structure has a reference handle field to link back to the related +/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the +/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor, +/// SMBIOS type 44 structures describe different core-specific information. +/// +/// SMBIOS type 44 defines the standard header for the processor-specific block, while the +/// contents of processor-specific data are maintained by processor +/// architecture workgroups or vendors in separate documents. +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4 + /// + /// Below followed by Processor-specific block + /// + PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock; +} SMBIOS_TABLE_TYPE44; + +/// +/// TPM Device (Type 43). +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; + UINT8 VendorID[4]; + UINT8 MajorSpecVersion; + UINT8 MinorSpecVersion; + UINT32 FirmwareVersion1; + UINT32 FirmwareVersion2; + SMBIOS_TABLE_STRING Description; + UINT64 Characteristics; + UINT32 OemDefined; +} SMBIOS_TABLE_TYPE43; + +/// +/// Inactive (Type 126) +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; +} SMBIOS_TABLE_TYPE126; + +/// +/// End-of-Table (Type 127) +/// +typedef struct { + SMBIOS_STRUCTURE Hdr; +} SMBIOS_TABLE_TYPE127; + +/// +/// Union of all the possible SMBIOS record types. +/// +typedef union { + SMBIOS_STRUCTURE *Hdr; + SMBIOS_TABLE_TYPE0 *Type0; + SMBIOS_TABLE_TYPE1 *Type1; + SMBIOS_TABLE_TYPE2 *Type2; + SMBIOS_TABLE_TYPE3 *Type3; + SMBIOS_TABLE_TYPE4 *Type4; + SMBIOS_TABLE_TYPE5 *Type5; + SMBIOS_TABLE_TYPE6 *Type6; + SMBIOS_TABLE_TYPE7 *Type7; + SMBIOS_TABLE_TYPE8 *Type8; + SMBIOS_TABLE_TYPE9 *Type9; + SMBIOS_TABLE_TYPE10 *Type10; + SMBIOS_TABLE_TYPE11 *Type11; + SMBIOS_TABLE_TYPE12 *Type12; + SMBIOS_TABLE_TYPE13 *Type13; + SMBIOS_TABLE_TYPE14 *Type14; + SMBIOS_TABLE_TYPE15 *Type15; + SMBIOS_TABLE_TYPE16 *Type16; + SMBIOS_TABLE_TYPE17 *Type17; + SMBIOS_TABLE_TYPE18 *Type18; + SMBIOS_TABLE_TYPE19 *Type19; + SMBIOS_TABLE_TYPE20 *Type20; + SMBIOS_TABLE_TYPE21 *Type21; + SMBIOS_TABLE_TYPE22 *Type22; + SMBIOS_TABLE_TYPE23 *Type23; + SMBIOS_TABLE_TYPE24 *Type24; + SMBIOS_TABLE_TYPE25 *Type25; + SMBIOS_TABLE_TYPE26 *Type26; + SMBIOS_TABLE_TYPE27 *Type27; + SMBIOS_TABLE_TYPE28 *Type28; + SMBIOS_TABLE_TYPE29 *Type29; + SMBIOS_TABLE_TYPE30 *Type30; + SMBIOS_TABLE_TYPE31 *Type31; + SMBIOS_TABLE_TYPE32 *Type32; + SMBIOS_TABLE_TYPE33 *Type33; + SMBIOS_TABLE_TYPE34 *Type34; + SMBIOS_TABLE_TYPE35 *Type35; + SMBIOS_TABLE_TYPE36 *Type36; + SMBIOS_TABLE_TYPE37 *Type37; + SMBIOS_TABLE_TYPE38 *Type38; + SMBIOS_TABLE_TYPE39 *Type39; + SMBIOS_TABLE_TYPE40 *Type40; + SMBIOS_TABLE_TYPE41 *Type41; + SMBIOS_TABLE_TYPE42 *Type42; + SMBIOS_TABLE_TYPE43 *Type43; + SMBIOS_TABLE_TYPE44 *Type44; + SMBIOS_TABLE_TYPE126 *Type126; + SMBIOS_TABLE_TYPE127 *Type127; + UINT8 *Raw; +} SMBIOS_STRUCTURE_POINTER; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBus.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBus.h new file mode 100644 index 0000000000..43bf6f5950 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/SmBus.h @@ -0,0 +1,75 @@ +/** @file + This file declares the SMBus definitions defined in SmBus Specification V2.0 + and defined in PI1.0 specification volume 5. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMBUS_H_ +#define _SMBUS_H_ + + +/// +/// UDID of SMBUS device. +/// +typedef struct { + UINT32 VendorSpecificId; + UINT16 SubsystemDeviceId; + UINT16 SubsystemVendorId; + UINT16 Interface; + UINT16 DeviceId; + UINT16 VendorId; + UINT8 VendorRevision; + UINT8 DeviceCapabilities; +} EFI_SMBUS_UDID; + +/// +/// Smbus Device Address +/// +typedef struct { + /// + /// The SMBUS hardware address to which the SMBUS device is preassigned or allocated. + /// + UINTN SmbusDeviceAddress : 7; +} EFI_SMBUS_DEVICE_ADDRESS; + +typedef struct { + /// + /// The SMBUS hardware address to which the SMBUS device is preassigned or + /// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute(). + /// + EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress; + /// + /// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID. + /// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice(). + /// + EFI_SMBUS_UDID SmbusDeviceUdid; +} EFI_SMBUS_DEVICE_MAP; + +/// +/// Smbus Operations +/// +typedef enum _EFI_SMBUS_OPERATION { + EfiSmbusQuickRead, + EfiSmbusQuickWrite, + EfiSmbusReceiveByte, + EfiSmbusSendByte, + EfiSmbusReadByte, + EfiSmbusWriteByte, + EfiSmbusReadWord, + EfiSmbusWriteWord, + EfiSmbusReadBlock, + EfiSmbusWriteBlock, + EfiSmbusProcessCall, + EfiSmbusBWBRProcessCall +} EFI_SMBUS_OPERATION; + +/// +/// EFI_SMBUS_DEVICE_COMMAND +/// +typedef UINTN EFI_SMBUS_DEVICE_COMMAND; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Spdm.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Spdm.h new file mode 100644 index 0000000000..ff46525333 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Spdm.h @@ -0,0 +1,320 @@ +/** @file + Definitions of Security Protocol & Data Model Specification (SPDM) + version 1.0.0 in Distributed Management Task Force (DMTF). + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __SPDM_H__ +#define __SPDM_H__ + +#pragma pack(1) + +/// +/// SPDM response code +/// +#define SPDM_DIGESTS 0x01 +#define SPDM_CERTIFICATE 0x02 +#define SPDM_CHALLENGE_AUTH 0x03 +#define SPDM_VERSION 0x04 +#define SPDM_MEASUREMENTS 0x60 +#define SPDM_CAPABILITIES 0x61 +#define SPDM_SET_CERT_RESPONSE 0x62 +#define SPDM_ALGORITHMS 0x63 +#define SPDM_ERROR 0x7F +/// +/// SPDM request code +/// +#define SPDM_GET_DIGESTS 0x81 +#define SPDM_GET_CERTIFICATE 0x82 +#define SPDM_CHALLENGE 0x83 +#define SPDM_GET_VERSION 0x84 +#define SPDM_GET_MEASUREMENTS 0xE0 +#define SPDM_GET_CAPABILITIES 0xE1 +#define SPDM_NEGOTIATE_ALGORITHMS 0xE3 +#define SPDM_RESPOND_IF_READY 0xFF + +/// +/// SPDM message header +/// +typedef struct { + UINT8 SPDMVersion; + UINT8 RequestResponseCode; + UINT8 Param1; + UINT8 Param2; +} SPDM_MESSAGE_HEADER; + +#define SPDM_MESSAGE_VERSION 0x10 + +/// +/// SPDM GET_VERSION request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; +} SPDM_GET_VERSION_REQUEST; + +/// +/// SPDM GET_VERSION response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT8 Reserved; + UINT8 VersionNumberEntryCount; +//SPDM_VERSION_NUMBER VersionNumberEntry[VersionNumberEntryCount]; +} SPDM_VERSION_RESPONSE; + +/// +/// SPDM VERSION structure +/// +typedef struct { + UINT16 Alpha:4; + UINT16 UpdateVersionNumber:4; + UINT16 MinorVersion:4; + UINT16 MajorVersion:4; +} SPDM_VERSION_NUMBER; + +/// +/// SPDM GET_CAPABILITIES request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; +} SPDM_GET_CAPABILITIES_REQUEST; + +/// +/// SPDM GET_CAPABILITIES response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT8 Reserved; + UINT8 CTExponent; + UINT16 Reserved2; + UINT32 Flags; +} SPDM_CAPABILITIES_RESPONSE; + +/// +/// SPDM GET_CAPABILITIES response Flags +/// +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP BIT0 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP BIT1 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP BIT2 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4) +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG BIT3 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP BIT5 + +/// +/// SPDM NEGOTIATE_ALGORITHMS request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT16 Length; + UINT8 MeasurementSpecification; + UINT8 Reserved; + UINT32 BaseAsymAlgo; + UINT32 BaseHashAlgo; + UINT8 Reserved2[12]; + UINT8 ExtAsymCount; + UINT8 ExtHashCount; + UINT16 Reserved3; +//UINT32 ExtAsym[ExtAsymCount]; +//UINT32 ExtHash[ExtHashCount]; +} SPDM_NEGOTIATE_ALGORITHMS_REQUEST; + +/// +/// SPDM NEGOTIATE_ALGORITHMS request BaseAsymAlgo +/// +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 BIT0 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 BIT1 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 BIT2 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 BIT3 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 BIT5 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 BIT6 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 BIT7 +#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 BIT8 + +/// +/// SPDM NEGOTIATE_ALGORITHMS request BaseHashAlgo +/// +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 BIT0 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 BIT1 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 BIT2 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 BIT3 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4 +#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 BIT5 + +/// +/// SPDM NEGOTIATE_ALGORITHMS response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT16 Length; + UINT8 MeasurementSpecificationSel; + UINT8 Reserved; + UINT32 MeasurementHashAlgo; + UINT32 BaseAsymSel; + UINT32 BaseHashSel; + UINT8 Reserved2[12]; + UINT8 ExtAsymSelCount; + UINT8 ExtHashSelCount; + UINT16 Reserved3; +//UINT32 ExtAsymSel[ExtAsymSelCount]; +//UINT32 ExtHashSel[ExtHashSelCount]; +} SPDM_ALGORITHMS_RESPONSE; + +/// +/// SPDM NEGOTIATE_ALGORITHMS response MeasurementHashAlgo +/// +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 BIT1 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 BIT2 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 BIT3 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 BIT5 +#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 BIT6 + +/// +/// SPDM GET_DIGESTS request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; +} SPDM_GET_DIGESTS_REQUEST; + +/// +/// SPDM GET_DIGESTS response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; +//UINT8 Digest[DigestSize]; +} SPDM_DIGESTS_RESPONSE; + +/// +/// SPDM GET_DIGESTS request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT16 Offset; + UINT16 Length; +} SPDM_GET_CERTIFICATE_REQUEST; + +/// +/// SPDM GET_DIGESTS response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT16 PortionLength; + UINT16 RemainderLength; +//UINT8 CertChain[CertChainSize]; +} SPDM_CERTIFICATE_RESPONSE; + +/// +/// SPDM CHALLENGE request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT8 Nonce[32]; +} SPDM_CHALLENGE_REQUEST; + +/// +/// SPDM CHALLENGE response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; +//UINT8 CertChainHash[DigestSize]; +//UINT8 Nonce[32]; +//UINT8 MeasurementSummaryHash[DigestSize]; +//UINT16 OpaqueLength; +//UINT8 OpaqueData[OpaqueLength]; +//UINT8 Signature[KeySize]; +} SPDM_CHALLENGE_AUTH_RESPONSE; + +/// +/// SPDM GET_MEASUREMENTS request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT8 Nonce[32]; +} SPDM_GET_MEASUREMENTS_REQUEST; + +/// +/// SPDM MEASUREMENTS block common header +/// +typedef struct { + UINT8 Index; + UINT8 MeasurementSpecification; + UINT16 MeasurementSize; +//UINT8 Measurement[MeasurementSize]; +} SPDM_MEASUREMENT_BLOCK_COMMON_HEADER; + +#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0 + +/// +/// SPDM MEASUREMENTS block DMTF header +/// +typedef struct { + UINT8 DMTFSpecMeasurementValueType; + UINT16 DMTFSpecMeasurementValueSize; +//UINT8 DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize]; +} SPDM_MEASUREMENT_BLOCK_DMTF_HEADER; + +/// +/// SPDM MEASUREMENTS block MeasurementValueType +/// +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM 0 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE 1 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION 2 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION 3 +#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM BIT7 + +/// +/// SPDM GET_MEASUREMENTS response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + UINT8 NumberOfBlocks; + UINT8 MeasurementRecordLength[3]; +//UINT8 MeasurementRecord[MeasurementRecordLength]; +//UINT8 Nonce[32]; +//UINT16 OpaqueLength; +//UINT8 OpaqueData[OpaqueLength]; +//UINT8 Signature[KeySize]; +} SPDM_MEASUREMENTS_RESPONSE; + +/// +/// SPDM ERROR response +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + // Param1 == Error Code + // Param2 == Error Data +//UINT8 ExtendedErrorData[]; +} SPDM_ERROR_RESPONSE; + +/// +/// SPDM error code +/// +#define SPDM_ERROR_CODE_INVALID_REQUEST 0x01 +#define SPDM_ERROR_CODE_BUSY 0x03 +#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST 0x04 +#define SPDM_ERROR_CODE_UNSPECIFIED 0x05 +#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST 0x07 +#define SPDM_ERROR_CODE_MAJOR_VERSION_MISMATCH 0x41 +#define SPDM_ERROR_CODE_RESPONSE_NOT_READY 0x42 +#define SPDM_ERROR_CODE_REQUEST_RESYNCH 0x43 + +/// +/// SPDM RESPONSE_IF_READY request +/// +typedef struct { + SPDM_MESSAGE_HEADER Header; + // Param1 == RequestCode + // Param2 == Token +} SPDM_RESPONSE_IF_READY_REQUEST; + +#pragma pack() + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h new file mode 100644 index 0000000000..f35c1f51a3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h @@ -0,0 +1,123 @@ +/** @file + TCG Physical Presence definition. + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TCG_PHYSICAL_PRESENCE_H_ +#define _TCG_PHYSICAL_PRESENCE_H_ + +// +// TCG PP definition for physical presence ACPI function +// +#define TCG_ACPI_FUNCTION_GET_PHYSICAL_PRESENCE_INTERFACE_VERSION 1 +#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS 2 +#define TCG_ACPI_FUNCTION_GET_PENDING_REQUEST_BY_OS 3 +#define TCG_ACPI_FUNCTION_GET_PLATFORM_ACTION_TO_TRANSITION_TO_BIOS 4 +#define TCG_ACPI_FUNCTION_RETURN_REQUEST_RESPONSE_TO_OS 5 +#define TCG_ACPI_FUNCTION_SUBMIT_PREFERRED_USER_LANGUAGE 6 +#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS_2 7 +#define TCG_ACPI_FUNCTION_GET_USER_CONFIRMATION_STATUS_FOR_REQUEST 8 + +// +// TCG PP definition for TPM Operation Response to OS Environment +// +#define TCG_PP_OPERATION_RESPONSE_SUCCESS 0x0 +#define TCG_PP_OPERATION_RESPONSE_USER_ABORT 0xFFFFFFF0 +#define TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE 0xFFFFFFF1 + +// +// TCG PP definition of return code for Return TPM Operation Response to OS Environment +// +#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS 0 +#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_FAILURE 1 + +// +// TCG PP definition of return code for Submit TPM Request to Pre-OS Environment +// and Submit TPM Request to Pre-OS Environment 2 +// +#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS 0 +#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED 1 +#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE 2 +#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_BLOCKED_BY_BIOS_SETTINGS 3 + +// +// TCG PP definition of return code for Get User Confirmation Status for Operation +// +#define TCG_PP_GET_USER_CONFIRMATION_NOT_IMPLEMENTED 0 +#define TCG_PP_GET_USER_CONFIRMATION_BIOS_ONLY 1 +#define TCG_PP_GET_USER_CONFIRMATION_BLOCKED_BY_BIOS_CONFIGURATION 2 +#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_REQUIRED 3 +#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_NOT_REQUIRED 4 + +// +// TCG PP definition of physical presence operation actions for TPM12 +// +#define TCG_PHYSICAL_PRESENCE_NO_ACTION 0 +#define TCG_PHYSICAL_PRESENCE_ENABLE 1 +#define TCG_PHYSICAL_PRESENCE_DISABLE 2 +#define TCG_PHYSICAL_PRESENCE_ACTIVATE 3 +#define TCG_PHYSICAL_PRESENCE_DEACTIVATE 4 +#define TCG_PHYSICAL_PRESENCE_CLEAR 5 +#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE 6 +#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE 7 +#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_TRUE 8 +#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_FALSE 9 +#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_OWNER_TRUE 10 +#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE_OWNER_FALSE 11 +#define TCG_PHYSICAL_PRESENCE_DEFERRED_PP_UNOWNERED_FIELD_UPGRADE 12 +#define TCG_PHYSICAL_PRESENCE_SET_OPERATOR_AUTH 13 +#define TCG_PHYSICAL_PRESENCE_CLEAR_ENABLE_ACTIVATE 14 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_FALSE 15 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_TRUE 16 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE 17 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE 18 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_FALSE 19 +#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_TRUE 20 +#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR 21 +#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE 22 + +#define TCG_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128 + +// +// TCG PP definition of physical presence operation actions for TPM2 +// +#define TCG2_PHYSICAL_PRESENCE_NO_ACTION 0 +#define TCG2_PHYSICAL_PRESENCE_ENABLE 1 +#define TCG2_PHYSICAL_PRESENCE_DISABLE 2 +#define TCG2_PHYSICAL_PRESENCE_CLEAR 5 +#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR 14 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18 +#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_2 21 +#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_3 22 +#define TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS 23 +#define TCG2_PHYSICAL_PRESENCE_CHANGE_EPS 24 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32 +#define TCG2_PHYSICAL_PRESENCE_LOG_ALL_DIGESTS 33 +#define TCG2_PHYSICAL_PRESENCE_DISABLE_ENDORSEMENT_ENABLE_STORAGE_HIERARCHY 34 +#define TCG2_PHYSICAL_PRESENCE_NO_ACTION_MAX 34 + +// +// TCG PP definition of physical presence operation actions for storage management +// +#define TCG2_PHYSICAL_PRESENCE_STORAGE_MANAGEMENT_BEGIN 96 +#define TCG2_PHYSICAL_PRESENCE_ENABLE_BLOCK_SID 96 +#define TCG2_PHYSICAL_PRESENCE_DISABLE_BLOCK_SID 97 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_TRUE 98 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FUNC_FALSE 99 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_TRUE 100 +#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_FALSE 101 + +#define TCG2_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageCore.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageCore.h new file mode 100644 index 0000000000..a9c1332d2d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageCore.h @@ -0,0 +1,395 @@ +/** @file + TCG defined values and structures. + + (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00, + https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/) + + Check http://trustedcomputinggroup.org for latest specification updates. + +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TCG_STORAGE_CORE_H_ +#define _TCG_STORAGE_CORE_H_ + +#include + +#pragma pack(1) + +/// UID in host native byte order +typedef UINT64 TCG_UID; + +#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TCG_UID)( \ + (UINT64)(b0) | \ + ((UINT64)(b1) << 8) | \ + ((UINT64)(b2) << 16) | \ + ((UINT64)(b3) << 24) | \ + ((UINT64)(b4) << 32) | \ + ((UINT64)(b5) << 40) | \ + ((UINT64)(b6) << 48) | \ + ((UINT64)(b7) << 56)) + +typedef struct { + UINT32 ReservedBE; + UINT16 ComIDBE; + UINT16 ComIDExtensionBE; + UINT32 OutstandingDataBE; + UINT32 MinTransferBE; + UINT32 LengthBE; + UINT8 Payload[0]; +} TCG_COM_PACKET; + +typedef struct { + UINT32 TperSessionNumberBE; + UINT32 HostSessionNumberBE; + UINT32 SequenceNumberBE; + UINT16 ReservedBE; + UINT16 AckTypeBE; + UINT32 AcknowledgementBE; + UINT32 LengthBE; + UINT8 Payload[0]; +} TCG_PACKET; + +#define TCG_SUBPACKET_ALIGNMENT 4 // 4-byte alignment per spec + +typedef struct { + UINT8 ReservedBE[6]; + UINT16 KindBE; + UINT32 LengthBE; + UINT8 Payload[0]; +} TCG_SUB_PACKET; + +#define SUBPACKET_KIND_DATA 0x0000 +#define SUBPACKET_KIND_CREDIT_CONTROL 0x8001 + +#define TCG_ATOM_TYPE_INTEGER 0x0 +#define TCG_ATOM_TYPE_BYTE 0x1 +typedef struct { + UINT8 Data : 6; + UINT8 Sign : 1; + UINT8 IsZero : 1; +} TCG_TINY_ATOM_BITS; + +typedef union { + UINT8 Raw; + TCG_TINY_ATOM_BITS TinyAtomBits; +} TCG_SIMPLE_TOKEN_TINY_ATOM; + + +typedef struct { + UINT8 Length : 4; + UINT8 SignOrCont : 1; + UINT8 ByteOrInt : 1; + UINT8 IsZero : 1; + UINT8 IsOne : 1; +} TCG_SHORT_ATOM_BITS; + +typedef union { + UINT8 RawHeader; + TCG_SHORT_ATOM_BITS ShortAtomBits; +} TCG_SIMPLE_TOKEN_SHORT_ATOM; + + +#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 0x8 +#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7 + +typedef struct { + UINT8 LengthHigh : 3; + UINT8 SignOrCont : 1; + UINT8 ByteOrInt : 1; + UINT8 IsZero : 1; + UINT8 IsOne1 : 1; + UINT8 IsOne2 : 1; + UINT8 LengthLow; +} TCG_MEDIUM_ATOM_BITS; + +typedef union { + UINT16 RawHeader; + TCG_MEDIUM_ATOM_BITS MediumAtomBits; +} TCG_SIMPLE_TOKEN_MEDIUM_ATOM; + + +#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16 +#define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8 + +typedef struct { + UINT8 SignOrCont : 1; + UINT8 ByteOrInt : 1; + UINT8 Reserved : 2; + UINT8 IsZero : 1; + UINT8 IsOne1 : 1; + UINT8 IsOne2 : 1; + UINT8 IsOne3 : 1; + UINT8 LengthHigh; + UINT8 LengthMid; + UINT8 LengthLow; +} TCG_LONG_ATOM_BITS; + +typedef union { + UINT32 RawHeader; + TCG_LONG_ATOM_BITS LongAtomBits; +} TCG_SIMPLE_TOKEN_LONG_ATOM; + + +// TCG Core Spec v2 - Table 04 - Token Types +typedef enum { + TcgTokenTypeReserved, + TcgTokenTypeTinyAtom, + TcgTokenTypeShortAtom, + TcgTokenTypeMediumAtom, + TcgTokenTypeLongAtom, + TcgTokenTypeStartList, + TcgTokenTypeEndList, + TcgTokenTypeStartName, + TcgTokenTypeEndName, + TcgTokenTypeCall, + TcgTokenTypeEndOfData, + TcgTokenTypeEndOfSession, + TcgTokenTypeStartTransaction, + TcgTokenTypeEndTransaction, + TcgTokenTypeEmptyAtom, +} TCG_TOKEN_TYPE; + +#pragma pack() + +#define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F +#define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE 0x7FF +#define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE 0xFFFFFF + +#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F +#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F +#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32 + +// TOKEN TYPES +#define TCG_TOKEN_TINYATOM 0x00 +#define TCG_TOKEN_TINYSIGNEDATOM 0x40 +#define TCG_TOKEN_SHORTATOM 0x80 +#define TCG_TOKEN_SHORTSIGNEDATOM 0x90 +#define TCG_TOKEN_SHORTBYTESATOM 0xA0 +#define TCG_TOKEN_MEDIUMATOM 0xC0 +#define TCG_TOKEN_MEDIUMSIGNEDATOM 0xC8 +#define TCG_TOKEN_MEDIUMBYTESATOM 0xD0 +#define TCG_TOKEN_LONGATOM 0xE0 +#define TCG_TOKEN_LONGSIGNEDATOM 0xE1 +#define TCG_TOKEN_LONGBYTESATOM 0xE2 +#define TCG_TOKEN_STARTLIST 0xF0 +#define TCG_TOKEN_ENDLIST 0xF1 +#define TCG_TOKEN_STARTNAME 0xF2 +#define TCG_TOKEN_ENDNAME 0xF3 +// 0xF4 - 0xF7 TCG Reserved +#define TCG_TOKEN_CALL 0xF8 +#define TCG_TOKEN_ENDDATA 0xF9 +#define TCG_TOKEN_ENDSESSION 0xFA +#define TCG_TOKEN_STARTTRANSACTION 0xFB +#define TCG_TOKEN_ENDTRANSACTION 0xFC +// 0xFD - 0xFE TCG Reserved +#define TCG_TOKEN_EMPTY 0xFF + +// CELLBLOCK reserved Names +#define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00 +#define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01 +#define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02 +#define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03 +#define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04 + +// METHOD STATUS CODES +#define TCG_METHOD_STATUS_CODE_SUCCESS 0x00 +#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01 +#define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02 +#define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03 +#define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04 +#define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05 +#define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06 +#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07 +#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08 +#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09 +#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A +#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C +#define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D +#define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E +#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F +#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10 +#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11 +#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12 +#define TCG_METHOD_STATUS_CODE_FAIL 0x3F + + +// Feature Codes +#define TCG_FEATURE_INVALID (UINT16)0x0000 +#define TCG_FEATURE_TPER (UINT16)0x0001 +#define TCG_FEATURE_LOCKING (UINT16)0x0002 +#define TCG_FEATURE_GEOMETRY_REPORTING (UINT16)0x0003 +#define TCG_FEATURE_SINGLE_USER_MODE (UINT16)0x0201 +#define TCG_FEATURE_DATASTORE_TABLE (UINT16)0x0202 +#define TCG_FEATURE_OPAL_SSC_V1_0_0 (UINT16)0x0200 +#define TCG_FEATURE_OPAL_SSC_V2_0_0 (UINT16)0x0203 +#define TCG_FEATURE_OPAL_SSC_LITE (UINT16)0x0301 +#define TCG_FEATURE_PYRITE_SSC (UINT16)0x0302 +#define TCG_FEATURE_PYRITE_SSC_V2_0_0 (UINT16)0x0303 +#define TCG_FEATURE_BLOCK_SID (UINT16)0x0402 +#define TCG_FEATURE_DATA_REMOVAL (UINT16)0x0404 + +// ACE Expression values +#define TCG_ACE_EXPRESSION_AND 0x0 +#define TCG_ACE_EXPRESSION_OR 0x1 + +/**************************************************************************** +TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h) +ATA 8 Rev6a Table 68 7.57.6.2 +****************************************************************************/ +// Security Protocol IDs +#define TCG_SECURITY_PROTOCOL_INFO 0x00 +#define TCG_OPAL_SECURITY_PROTOCOL_1 0x01 +#define TCG_OPAL_SECURITY_PROTOCOL_2 0x02 +#define TCG_SECURITY_PROTOCOL_TCG3 0x03 +#define TCG_SECURITY_PROTOCOL_TCG4 0x04 +#define TCG_SECURITY_PROTOCOL_TCG5 0x05 +#define TCG_SECURITY_PROTOCOL_TCG6 0x06 +#define TCG_SECURITY_PROTOCOL_CBCS 0x07 +#define TCG_SECURITY_PROTOCOL_TAPE_DATA 0x20 +#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21 +#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40 +#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI 0x41 +#define TCG_SECURITY_PROTOCOL_JEDEC_UFS 0xEC +#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY 0xED +#define TCG_SECURITY_PROTOCOL_IEEE_1667 0xEE +#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF + +// Security Protocol Specific IDs +#define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000 +#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001 + +#define TCG_RESERVED_COMID 0x0000 + +// Defined in TCG Storage Feature Set:Block SID Authentication spec, +// ComId used for BlockSid command is hardcode 0x0005. +#define TCG_BLOCKSID_COMID 0x0005 + +#pragma pack(1) +typedef struct { + UINT8 Reserved[6]; + UINT16 ListLength_BE; // 6 - 7 + UINT8 List[504]; // 8... +} TCG_SUPPORTED_SECURITY_PROTOCOLS; + + +// Level 0 Discovery +typedef struct { + UINT32 LengthBE; // number of valid bytes in discovery response, not including length field + UINT16 VerMajorBE; + UINT16 VerMinorBE; + UINT8 Reserved[8]; + UINT8 VendorUnique[32]; +} TCG_LEVEL0_DISCOVERY_HEADER; + +typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER { + UINT16 FeatureCode_BE; + UINT8 Reserved : 4; + UINT8 Version : 4; + UINT8 Length; // length of feature dependent data in bytes +} TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER; + + +typedef struct { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT8 LockingSupported : 1; + UINT8 LockingEnabled : 1; // means the locking security provider (SP) is enabled + UINT8 Locked : 1; // means at least 1 locking range is enabled + UINT8 MediaEncryption : 1; + UINT8 MbrEnabled : 1; + UINT8 MbrDone : 1; + UINT8 Reserved : 2; + UINT8 Reserved515[11]; +} TCG_LOCKING_FEATURE_DESCRIPTOR; + +typedef struct { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT8 SIDValueState : 1; + UINT8 SIDBlockedState : 1; + UINT8 Reserved4 : 6; + UINT8 HardwareReset : 1; + UINT8 Reserved5 : 7; + UINT8 Reserved615[10]; +} TCG_BLOCK_SID_FEATURE_DESCRIPTOR; + + +typedef struct { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT8 SyncSupported : 1; + UINT8 AsyncSupported : 1; + UINT8 AckNakSupported : 1; + UINT8 BufferMgmtSupported : 1; + UINT8 StreamingSupported : 1; + UINT8 Reserved4b5 : 1; + UINT8 ComIdMgmtSupported : 1; + UINT8 Reserved4b7 : 1; + UINT8 Reserved515[11]; +} TCG_TPER_FEATURE_DESCRIPTOR; + +#pragma pack() + +// Special Purpose UIDs +#define TCG_UID_NULL TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00) +#define TCG_UID_THIS_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01) +#define TCG_UID_SMUID TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF) + +// Session Manager Method UIDS +#define TCG_UID_SM_PROPERTIES TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01) +#define TCG_UID_SM_START_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02) +#define TCG_UID_SM_SYNC_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03) +#define TCG_UID_SM_START_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04) +#define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05) +#define TCG_UID_SM_CLOSE_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06) + +// MethodID UIDs +#define TCG_UID_METHOD_DELETE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01) +#define TCG_UID_METHOD_CREATE_TABLE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02) +#define TCG_UID_METHOD_DELETE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03) +#define TCG_UID_METHOD_CREATE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04) +#define TCG_UID_METHOD_DELETE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05) +#define TCG_UID_METHOD_NEXT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08) +#define TCG_UID_METHOD_GET_FREE_SPACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09) +#define TCG_UID_METHOD_GET_FREE_ROWS TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A) +#define TCG_UID_METHOD_DELETE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B) +#define TCG_UID_METHOD_GET_ACL TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D) +#define TCG_UID_METHOD_ADD_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E) +#define TCG_UID_METHOD_REMOVE_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F) +#define TCG_UID_METHOD_GEN_KEY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10) +#define TCG_UID_METHOD_GET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12) +#define TCG_UID_METHOD_SET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13) +#define TCG_UID_METHOD_GET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16) +#define TCG_UID_METHOD_SET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17) +#define TCG_UID_METHOD_AUTHENTICATE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C) +#define TCG_UID_METHOD_ISSUE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01) +#define TCG_UID_METHOD_GET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01) +#define TCG_UID_METHOD_RESET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02) +#define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03) +#define TCG_UID_METHOD_SET_LAG_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04) +#define TCG_UID_METHOD_SET_CLOCK_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05) +#define TCG_UID_METHOD_SET_LAG_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06) +#define TCG_UID_METHOD_INCREMENT_COUNTER TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07) +#define TCG_UID_METHOD_RANDOM TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01) +#define TCG_UID_METHOD_SALT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02) +#define TCG_UID_METHOD_DECRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03) +#define TCG_UID_METHOD_DECRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04) +#define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05) +#define TCG_UID_METHOD_ENCRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06) +#define TCG_UID_METHOD_ENCRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07) +#define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08) +#define TCG_UID_METHOD_HMAC_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09) +#define TCG_UID_METHOD_HMAC TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A) +#define TCG_UID_METHOD_HMAC_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B) +#define TCG_UID_METHOD_HASH_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C) +#define TCG_UID_METHOD_HASH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D) +#define TCG_UID_METHOD_HASH_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E) +#define TCG_UID_METHOD_SIGN TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F) +#define TCG_UID_METHOD_VERIFY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10) +#define TCG_UID_METHOD_XOR TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11) +#define TCG_UID_METHOD_ADD_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01) +#define TCG_UID_METHOD_CREATE_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02) +#define TCG_UID_METHOD_CLEAR_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03) +#define TCG_UID_METHOD_FLUSH_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04) + +#endif // TCG_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageOpal.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageOpal.h new file mode 100644 index 0000000000..cd83e32b10 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcgStorageOpal.h @@ -0,0 +1,243 @@ +/** @file + Opal Specification defined values and structures. + + (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00, + https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/ + + Storage Work Group Storage Security Subsystem Class: Pyrite, Version 1.00 Final, Revision 1.00, + https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-pyrite/ + + Storage Work Group Storage Security Subsystem Class: Opal, Version 2.01 Final, Revision 1.00, + https://trustedcomputinggroup.org/storage-work-group-storage-security-subsystem-class-opal/ + + TCG Storage Security Subsystem Class: Opalite Version 1.00 Revision 1.00, + https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-opalite/) + + Check http://trustedcomputinggroup.org for latest specification updates. + +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TCG_STORAGE_OPAL_H_ +#define _TCG_STORAGE_OPAL_H_ + +#include + +#define OPAL_UID_ADMIN_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x01) +#define OPAL_UID_ADMIN_SP_C_PIN_MSID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x84, 0x02) +#define OPAL_UID_ADMIN_SP_C_PIN_SID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x01) +#define OPAL_UID_LOCKING_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02) + +// ADMIN_SP +// Authorities +#define OPAL_ADMIN_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01) +#define OPAL_ADMIN_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02) +#define OPAL_ADMIN_SP_MAKERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03) +#define OPAL_ADMIN_SP_SID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06) +#define OPAL_ADMIN_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x01) +#define OPAL_ADMIN_SP_PSID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0xFF, 0x01) + +#define OPAL_ADMIN_SP_ACTIVATE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03) +#define OPAL_ADMIN_SP_REVERT_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02) + +// ADMIN_SP +// Data Removal mechanism +#define OPAL_UID_ADMIN_SP_DATA_REMOVAL_MECHANISM TCG_TO_UID(0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x01) + +// LOCKING SP +// Authorities +#define OPAL_LOCKING_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01) +#define OPAL_LOCKING_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02) +#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01) +#define OPAL_LOCKING_SP_USERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x00) +#define OPAL_LOCKING_SP_USER1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01) + +#define OPAL_LOCKING_SP_REVERTSP_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11) + +// C_PIN Table Rows +#define OPAL_LOCKING_SP_C_PIN_ADMIN1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01 ) +#define OPAL_LOCKING_SP_C_PIN_USER1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x03, 0x00, 0x01 ) + +// Locking Table +#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01 ) +#define OPAL_LOCKING_SP_LOCKING_RANGE1 TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x03, 0x00, 0x01 ) + + +// LOCKING SP ACE Table Preconfiguration +#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_GET_ALL TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xD0, 0x00 ) +#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_RDLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE0, 0x00 ) +#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_WRLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE8, 0x00 ) + +#define OPAL_LOCKING_SP_ACE_K_AES_256_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB8, 0x00 ) +#define OPAL_LOCKING_SP_ACE_K_AES_128_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB0, 0x00 ) + + +// LOCKING SP LockingInfo Table Preconfiguration +#define OPAL_LOCKING_SP_LOCKING_INFO TCG_TO_UID( 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01 ) + +#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTREQUIRED_COL 0x7 +#define OPAL_LOCKING_SP_LOCKINGINFO_LOGICALBLOCKSIZE_COL 0x8 +#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTGRANULARITY_COL 0x9 +#define OPAL_LOCKING_SP_LOCKINGINFO_LOWESTALIGNEDLBA_COL 0xA + +// K_AES_256 Table Preconfiguration +#define OPAL_LOCKING_SP_K_AES_256_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x06, 0x00, 0x00, 0x00, 0x01 ) + +// K_AES_128 Table Preconfiguration +#define OPAL_LOCKING_SP_K_AES_128_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01 ) + +// Minimum Properties that an Opal Compliant SD Shall support +#define OPAL_MIN_MAX_COM_PACKET_SIZE 2048 +#define OPAL_MIN_MAX_REPONSE_COM_PACKET_SIZE 2048 +#define OPAL_MIN_MAX_PACKET_SIZE 2028 +#define OPAL_MIN_MAX_IND_TOKEN_SIZE 1992 +#define OPAL_MIN_MAX_PACKETS 1 +#define OPAL_MIN_MAX_SUBPACKETS 1 +#define OPAL_MIN_MAX_METHODS 1 +#define OPAL_MIN_MAX_SESSIONS 1 +#define OPAL_MIN_MAX_AUTHENTICATIONS 2 +#define OPAL_MIN_MAX_TRANSACTION_LIMIT 1 + +#define OPAL_ADMIN_SP_PIN_COL 3 +#define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5 +#define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32 + +// Data Removal Mechanism column. +#define OPAL_ADMIN_SP_ACTIVE_DATA_REMOVAL_MECHANISM_COL 1 + +// +// Supported Data Removal Mechanism. +// Detail see Pyrite SSC v2 spec. +// +typedef enum { + OverwriteDataErase = 0, + BlockErase, + CryptoErase, + Unmap, + ResetWritePointers, + VendorSpecificErase, + ResearvedMechanism +} SUPPORTED_DATA_REMOVAL_MECHANISM; + +#pragma pack(1) + +typedef struct _OPAL_GEOMETRY_REPORTING_FEATURE { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT8 Reserved[8]; + UINT32 LogicalBlockSizeBE; + UINT64 AlignmentGranularityBE; + UINT64 LowestAlignedLBABE; +} OPAL_GEOMETRY_REPORTING_FEATURE; + +typedef struct _OPAL_SINGLE_USER_MODE_FEATURE { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT32 NumLockingObjectsSupportedBE; + UINT8 Any : 1; + UINT8 All : 1; + UINT8 Policy : 1; + UINT8 Reserved : 5; + UINT8 Reserved2[7]; +} OPAL_SINGLE_USER_MODE_FEATURE; + +typedef struct _OPAL_DATASTORE_TABLE_FEATURE { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 Reserved; + UINT16 MaxNumTablesBE; + UINT32 MaxTotalSizeBE; + UINT32 SizeAlignmentBE; +} OPAL_DATASTORE_TABLE_FEATURE; + +typedef struct _OPAL_SSCV1_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 BaseComdIdBE; + UINT16 NumComIdsBE; + UINT8 RangeCrossing : 1; + UINT8 Reserved : 7; + UINT8 Future[11]; +} OPAL_SSCV1_FEATURE_DESCRIPTOR; + +typedef struct _OPAL_SSCV2_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 BaseComdIdBE; + UINT16 NumComIdsBE; + UINT8 Reserved; + UINT16 NumLockingSpAdminAuthoritiesSupportedBE; + UINT16 NumLockingSpUserAuthoritiesSupportedBE; + UINT8 InitialCPINSIDPIN; + UINT8 CPINSIDPINRevertBehavior; + UINT8 Future[5]; +} OPAL_SSCV2_FEATURE_DESCRIPTOR; + +typedef struct _OPAL_SSCLITE_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 BaseComdIdBE; + UINT16 NumComIdsBE; + UINT8 Reserved[5]; + UINT8 InitialCPINSIDPIN; + UINT8 CPINSIDPINRevertBehavior; + UINT8 Future[5]; +} OPAL_SSCLITE_FEATURE_DESCRIPTOR; + +typedef struct _PYRITE_SSC_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 BaseComdIdBE; + UINT16 NumComIdsBE; + UINT8 Reserved[5]; + UINT8 InitialCPINSIDPIN; + UINT8 CPINSIDPINRevertBehavior; + UINT8 Future[5]; +} PYRITE_SSC_FEATURE_DESCRIPTOR; + +typedef struct _PYRITE_SSCV2_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT16 BaseComdIdBE; + UINT16 NumComIdsBE; + UINT8 Reserved[5]; + UINT8 InitialCPINSIDPIN; + UINT8 CPINSIDPINRevertBehavior; + UINT8 Future[5]; +} PYRITE_SSCV2_FEATURE_DESCRIPTOR; + +typedef struct _DATA_REMOVAL_FEATURE_DESCRIPTOR { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header; + UINT8 Reserved; + UINT8 OperationProcessing : 1; + UINT8 Reserved2 : 7; + UINT8 RemovalMechanism; + UINT8 FormatBit0 : 1; // Data Removal Time Format for Bit 0 + UINT8 FormatBit1 : 1; // Data Removal Time Format for Bit 1 + UINT8 FormatBit2 : 1; // Data Removal Time Format for Bit 2 + UINT8 FormatBit3 : 1; // Data Removal Time Format for Bit 3 + UINT8 FormatBit4 : 1; // Data Removal Time Format for Bit 4 + UINT8 FormatBit5 : 1; // Data Removal Time Format for Bit 5 + UINT8 Reserved3 : 2; + UINT16 TimeBit0; // Data Removal Time for Supported Data Removal Mechanism Bit 0 + UINT16 TimeBit1; // Data Removal Time for Supported Data Removal Mechanism Bit 1 + UINT16 TimeBit2; // Data Removal Time for Supported Data Removal Mechanism Bit 2 + UINT16 TimeBit3; // Data Removal Time for Supported Data Removal Mechanism Bit 3 + UINT16 TimeBit4; // Data Removal Time for Supported Data Removal Mechanism Bit 4 + UINT16 TimeBit5; // Data Removal Time for Supported Data Removal Mechanism Bit 5 + UINT8 Future[16]; +} DATA_REMOVAL_FEATURE_DESCRIPTOR; + +typedef union { + TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER CommonHeader; + TCG_TPER_FEATURE_DESCRIPTOR Tper; + TCG_LOCKING_FEATURE_DESCRIPTOR Locking; + OPAL_GEOMETRY_REPORTING_FEATURE Geometry; + OPAL_SINGLE_USER_MODE_FEATURE SingleUser; + OPAL_DATASTORE_TABLE_FEATURE DataStore; + OPAL_SSCV1_FEATURE_DESCRIPTOR OpalSscV1; + OPAL_SSCV2_FEATURE_DESCRIPTOR OpalSscV2; + OPAL_SSCLITE_FEATURE_DESCRIPTOR OpalSscLite; + PYRITE_SSC_FEATURE_DESCRIPTOR PyriteSsc; + PYRITE_SSCV2_FEATURE_DESCRIPTOR PyriteSscV2; + TCG_BLOCK_SID_FEATURE_DESCRIPTOR BlockSid; + DATA_REMOVAL_FEATURE_DESCRIPTOR DataRemoval; +} OPAL_LEVEL0_FEATURE_DESCRIPTOR; + +#pragma pack() + +#endif // _OPAL_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcpaAcpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcpaAcpi.h new file mode 100644 index 0000000000..4b02c91587 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TcpaAcpi.h @@ -0,0 +1,52 @@ +/** @file + TCPA ACPI table definition. + +Copyright (c) 2013, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TCPA_ACPI_H_ +#define _TCPA_ACPI_H_ + +#include + +#pragma pack (1) + +typedef struct _EFI_TCG_CLIENT_ACPI_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT16 PlatformClass; + UINT32 Laml; + UINT64 Lasa; +} EFI_TCG_CLIENT_ACPI_TABLE; + +typedef struct _EFI_TCG_SERVER_ACPI_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT16 PlatformClass; + UINT16 Reserved0; + UINT64 Laml; + UINT64 Lasa; + UINT16 SpecRev; + UINT8 DeviceFlags; + UINT8 InterruptFlags; + UINT8 Gpe; + UINT8 Reserved1[3]; + UINT32 GlobalSysInt; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + UINT32 Reserved2; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ConfigAddress; + UINT8 PciSegNum; + UINT8 PciBusNum; + UINT8 PciDevNum; + UINT8 PciFuncNum; +} EFI_TCG_SERVER_ACPI_TABLE; + +// +// TCG Platform Type based on TCG ACPI Specification Version 1.00 +// +#define TCG_PLATFORM_TYPE_CLIENT 0 +#define TCG_PLATFORM_TYPE_SERVER 1 + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tls1.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tls1.h new file mode 100644 index 0000000000..9d98bbbe28 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tls1.h @@ -0,0 +1,101 @@ +/** @file + Transport Layer Security -- TLS 1.0/1.1/1.2 Standard definitions, from RFC 2246/4346/5246 + + This file contains common TLS 1.0/1.1/1.2 definitions from RFC 2246/4346/5246 + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __TLS_1_H__ +#define __TLS_1_H__ + +#pragma pack(1) + +/// +/// TLS Cipher Suite, refers to A.5 of rfc-2246, rfc-4346 and rfc-5246. +/// +#define TLS_RSA_WITH_NULL_MD5 {0x00, 0x01} +#define TLS_RSA_WITH_NULL_SHA {0x00, 0x02} +#define TLS_RSA_WITH_RC4_128_MD5 {0x00, 0x04} +#define TLS_RSA_WITH_RC4_128_SHA {0x00, 0x05} +#define TLS_RSA_WITH_IDEA_CBC_SHA {0x00, 0x07} +#define TLS_RSA_WITH_DES_CBC_SHA {0x00, 0x09} +#define TLS_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x0A} +#define TLS_DH_DSS_WITH_DES_CBC_SHA {0x00, 0x0C} +#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x0D} +#define TLS_DH_RSA_WITH_DES_CBC_SHA {0x00, 0x0F} +#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x10} +#define TLS_DHE_DSS_WITH_DES_CBC_SHA {0x00, 0x12} +#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x13} +#define TLS_DHE_RSA_WITH_DES_CBC_SHA {0x00, 0x15} +#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x16} +#define TLS_RSA_WITH_AES_128_CBC_SHA {0x00, 0x2F} +#define TLS_DH_DSS_WITH_AES_128_CBC_SHA {0x00, 0x30} +#define TLS_DH_RSA_WITH_AES_128_CBC_SHA {0x00, 0x31} +#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA {0x00, 0x32} +#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA {0x00, 0x33} +#define TLS_RSA_WITH_AES_256_CBC_SHA {0x00, 0x35} +#define TLS_DH_DSS_WITH_AES_256_CBC_SHA {0x00, 0x36} +#define TLS_DH_RSA_WITH_AES_256_CBC_SHA {0x00, 0x37} +#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA {0x00, 0x38} +#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA {0x00, 0x39} +#define TLS_RSA_WITH_NULL_SHA256 {0x00, 0x3B} +#define TLS_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3C} +#define TLS_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x3D} +#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x3E} +#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3F} +#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x40} +#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x67} +#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x68} +#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x69} +#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x6A} +#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x6B} + +/// +/// TLS Version, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246. +/// +#define TLS10_PROTOCOL_VERSION_MAJOR 0x03 +#define TLS10_PROTOCOL_VERSION_MINOR 0x01 +#define TLS11_PROTOCOL_VERSION_MAJOR 0x03 +#define TLS11_PROTOCOL_VERSION_MINOR 0x02 +#define TLS12_PROTOCOL_VERSION_MAJOR 0x03 +#define TLS12_PROTOCOL_VERSION_MINOR 0x03 + +/// +/// TLS Content Type, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246. +/// +typedef enum { + TlsContentTypeChangeCipherSpec = 20, + TlsContentTypeAlert = 21, + TlsContentTypeHandshake = 22, + TlsContentTypeApplicationData = 23, +} TLS_CONTENT_TYPE; + +/// +/// TLS Record Header, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246. +/// +typedef struct { + UINT8 ContentType; + EFI_TLS_VERSION Version; + UINT16 Length; +} TLS_RECORD_HEADER; + +#define TLS_RECORD_HEADER_LENGTH 5 + +// +// The length (in bytes) of the TLSPlaintext records payload MUST NOT exceed 2^14. +// Refers to section 6.2 of RFC5246. +// +#define TLS_PLAINTEXT_RECORD_MAX_PAYLOAD_LENGTH 16384 + +// +// The length (in bytes) of the TLSCiphertext records payload MUST NOT exceed 2^14 + 2048. +// Refers to section 6.2 of RFC5246. +// +#define TLS_CIPHERTEXT_RECORD_MAX_PAYLOAD_LENGTH 18432 + +#pragma pack() + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm12.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm12.h new file mode 100644 index 0000000000..4ac86c4c9d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm12.h @@ -0,0 +1,2167 @@ +/** @file + TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 103) + See http://trustedcomputinggroup.org for latest specification updates + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#ifndef _TPM12_H_ +#define _TPM12_H_ + +/// +/// The start of TPM return codes +/// +#define TPM_BASE 0 + +// +// All structures MUST be packed on a byte boundary. +// + +#pragma pack (1) + +// +// Part 2, section 2.2.3: Helper redefinitions +// +/// +/// Indicates the conditions where it is required that authorization be presented +/// +typedef UINT8 TPM_AUTH_DATA_USAGE; +/// +/// The information as to what the payload is in an encrypted structure +/// +typedef UINT8 TPM_PAYLOAD_TYPE; +/// +/// The version info breakdown +/// +typedef UINT8 TPM_VERSION_BYTE; +/// +/// The state of the dictionary attack mitigation logic +/// +typedef UINT8 TPM_DA_STATE; +/// +/// The request or response authorization type +/// +typedef UINT16 TPM_TAG; +/// +/// The protocol in use +/// +typedef UINT16 TPM_PROTOCOL_ID; +/// +/// Indicates the start state +/// +typedef UINT16 TPM_STARTUP_TYPE; +/// +/// The definition of the encryption scheme +/// +typedef UINT16 TPM_ENC_SCHEME; +/// +/// The definition of the signature scheme +/// +typedef UINT16 TPM_SIG_SCHEME; +/// +/// The definition of the migration scheme +/// +typedef UINT16 TPM_MIGRATE_SCHEME; +/// +/// Sets the state of the physical presence mechanism +/// +typedef UINT16 TPM_PHYSICAL_PRESENCE; +/// +/// Indicates the types of entity that are supported by the TPM +/// +typedef UINT16 TPM_ENTITY_TYPE; +/// +/// Indicates the permitted usage of the key +/// +typedef UINT16 TPM_KEY_USAGE; +/// +/// The type of asymmetric encrypted structure in use by the endorsement key +/// +typedef UINT16 TPM_EK_TYPE; +/// +/// The tag for the structure +/// +typedef UINT16 TPM_STRUCTURE_TAG; +/// +/// The platform specific spec to which the information relates to +/// +typedef UINT16 TPM_PLATFORM_SPECIFIC; +/// +/// The command ordinal +/// +typedef UINT32 TPM_COMMAND_CODE; +/// +/// Identifies a TPM capability area +/// +typedef UINT32 TPM_CAPABILITY_AREA; +/// +/// Indicates information regarding a key +/// +typedef UINT32 TPM_KEY_FLAGS; +/// +/// Indicates the type of algorithm +/// +typedef UINT32 TPM_ALGORITHM_ID; +/// +/// The locality modifier +/// +typedef UINT32 TPM_MODIFIER_INDICATOR; +/// +/// The actual number of a counter +/// +typedef UINT32 TPM_ACTUAL_COUNT; +/// +/// Attributes that define what options are in use for a transport session +/// +typedef UINT32 TPM_TRANSPORT_ATTRIBUTES; +/// +/// Handle to an authorization session +/// +typedef UINT32 TPM_AUTHHANDLE; +/// +/// Index to a DIR register +/// +typedef UINT32 TPM_DIRINDEX; +/// +/// The area where a key is held assigned by the TPM +/// +typedef UINT32 TPM_KEY_HANDLE; +/// +/// Index to a PCR register +/// +typedef UINT32 TPM_PCRINDEX; +/// +/// The return code from a function +/// +typedef UINT32 TPM_RESULT; +/// +/// The types of resources that a TPM may have using internal resources +/// +typedef UINT32 TPM_RESOURCE_TYPE; +/// +/// Allows for controlling of the key when loaded and how to handle TPM_Startup issues +/// +typedef UINT32 TPM_KEY_CONTROL; +/// +/// The index into the NV storage area +/// +typedef UINT32 TPM_NV_INDEX; +/// +/// The family ID. Family IDs are automatically assigned a sequence number by the TPM. +/// A trusted process can set the FamilyID value in an individual row to NULL, which +/// invalidates that row. The family ID resets to NULL on each change of TPM Owner. +/// +typedef UINT32 TPM_FAMILY_ID; +/// +/// IA value used as a label for the most recent verification of this family. Set to zero when not in use. +/// +typedef UINT32 TPM_FAMILY_VERIFICATION; +/// +/// How the TPM handles var +/// +typedef UINT32 TPM_STARTUP_EFFECTS; +/// +/// The mode of a symmetric encryption +/// +typedef UINT32 TPM_SYM_MODE; +/// +/// The family flags +/// +typedef UINT32 TPM_FAMILY_FLAGS; +/// +/// The index value for the delegate NV table +/// +typedef UINT32 TPM_DELEGATE_INDEX; +/// +/// The restrictions placed on delegation of CMK commands +/// +typedef UINT32 TPM_CMK_DELEGATE; +/// +/// The ID value of a monotonic counter +/// +typedef UINT32 TPM_COUNT_ID; +/// +/// A command to execute +/// +typedef UINT32 TPM_REDIT_COMMAND; +/// +/// A transport session handle +/// +typedef UINT32 TPM_TRANSHANDLE; +/// +/// A generic handle could be key, transport etc +/// +typedef UINT32 TPM_HANDLE; +/// +/// What operation is happening +/// +typedef UINT32 TPM_FAMILY_OPERATION; + +// +// Part 2, section 2.2.4: Vendor specific +// The following defines allow for the quick specification of a +// vendor specific item. +// +#define TPM_Vendor_Specific32 ((UINT32) 0x00000400) +#define TPM_Vendor_Specific8 ((UINT8) 0x80) + +// +// Part 2, section 3.1: TPM_STRUCTURE_TAG +// +#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001) +#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002) +#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003) +#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004) +#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005) +#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006) +#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007) +#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008) +#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009) +#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A) +#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B) +#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C) +#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D) +#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E) +#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F) +#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010) +#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011) +#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012) +#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013) +#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014) +#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015) +#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016) +#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017) +#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018) +#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019) +#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A) +#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B) +#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C) +#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D) +#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E) +#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F) +#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020) +#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021) +#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022) +#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023) +#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024) +#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025) +#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026) +#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027) +#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028) +#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029) +#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A) +#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B) +#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C) +#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D) +#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E) +#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F) +#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030) +#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031) +#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032) +#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033) +#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034) +#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035) +#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036) +#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037) +#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038) +#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039) + +// +// Part 2, section 4: TPM Types +// + +// +// Part 2, section 4.1: TPM_RESOURCE_TYPE +// +#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation +#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP +#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes +#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport +#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands +#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters +#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM +#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob +#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter +#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter + +// +// Part 2, section 4.2: TPM_PAYLOAD_TYPE +// +#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key +#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data +#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob +#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob +#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data +#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key +#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key +#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob +#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads + +// +// Part 2, section 4.3: TPM_ENTITY_TYPE +// +#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key +#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner +#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data +#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK +#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle +#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value +#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob +#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row +#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob +#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter +#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index +#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator +#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting. +// +// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable +// +#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR +#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits + +// +// Part 2, section 4.4.1: Reserved Key Handles +// +#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK +#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner +#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value +#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization +#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth +#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth +#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub + +// +// Part 2, section 4.5: TPM_STARTUP_TYPE +// +#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state +#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state +#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE + +// +// Part 2, section 4.6: TPM_STATUP_EFFECTS +// The table makeup is still an open issue. +// + +// +// Part 2, section 4.7: TPM_PROTOCOL_ID +// +#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol. +#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol. +#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol. +#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol. +#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM. +#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol +#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol + +// +// Part 2, section 4.8: TPM_ALGORITHM_ID +// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC, +// TPM_ALG_MGF1 +// +#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm. +#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm +#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode +#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm +#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm +#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128 +#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block +#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192 +#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256 +#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces + +// +// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE +// +#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE +#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE +#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE +#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE +#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE +#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE +#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE +#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE + +// +// Part 2, section 4.10: TPM_MIGRATE_SCHEME +// +#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode. +#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob. +#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands +#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority. +#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping + +// +// Part 2, section 4.11: TPM_EK_TYPE +// +#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE +#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH + +// +// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC +// +#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1 +#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2 +#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2 +#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2 +#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2 + +// +// Part 2, section 5: Basic Structures +// + +/// +/// Part 2, section 5.1: TPM_STRUCT_VER +/// +typedef struct tdTPM_STRUCT_VER { + UINT8 major; + UINT8 minor; + UINT8 revMajor; + UINT8 revMinor; +} TPM_STRUCT_VER; + +/// +/// Part 2, section 5.3: TPM_VERSION +/// +typedef struct tdTPM_VERSION { + TPM_VERSION_BYTE major; + TPM_VERSION_BYTE minor; + UINT8 revMajor; + UINT8 revMinor; +} TPM_VERSION; + + +#define TPM_SHA1_160_HASH_LEN 0x14 +#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN + +/// +/// Part 2, section 5.4: TPM_DIGEST +/// +typedef struct tdTPM_DIGEST{ + UINT8 digest[TPM_SHA1_160_HASH_LEN]; +} TPM_DIGEST; + +/// +/// This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity +/// +typedef TPM_DIGEST TPM_CHOSENID_HASH; +/// +/// This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to +/// +typedef TPM_DIGEST TPM_COMPOSITE_HASH; +/// +/// This SHALL be the value of a DIR register +/// +typedef TPM_DIGEST TPM_DIRVALUE; + +typedef TPM_DIGEST TPM_HMAC; +/// +/// The value inside of the PCR +/// +typedef TPM_DIGEST TPM_PCRVALUE; +/// +/// This SHALL be the value of the current internal audit state +/// +typedef TPM_DIGEST TPM_AUDITDIGEST; + +/// +/// Part 2, section 5.5: TPM_NONCE +/// +typedef struct tdTPM_NONCE{ + UINT8 nonce[20]; +} TPM_NONCE; + +/// +/// This SHALL be a random value generated by a TPM immediately after the EK is installed +/// in that TPM, whenever an EK is installed in that TPM +/// +typedef TPM_NONCE TPM_DAA_TPM_SEED; +/// +/// This SHALL be a random value +/// +typedef TPM_NONCE TPM_DAA_CONTEXT_SEED; + +// +// Part 2, section 5.6: TPM_AUTHDATA +// +/// +/// The AuthData data is the information that is saved or passed to provide proof of ownership +/// 296 of an entity +/// +typedef UINT8 tdTPM_AUTHDATA[20]; + +typedef tdTPM_AUTHDATA TPM_AUTHDATA; +/// +/// A secret plaintext value used in the authorization process +/// +typedef TPM_AUTHDATA TPM_SECRET; +/// +/// A ciphertext (encrypted) version of AuthData data. The encryption mechanism depends on the context +/// +typedef TPM_AUTHDATA TPM_ENCAUTH; + +/// +/// Part 2, section 5.7: TPM_KEY_HANDLE_LIST +/// Size of handle is loaded * sizeof(TPM_KEY_HANDLE) +/// +typedef struct tdTPM_KEY_HANDLE_LIST { + UINT16 loaded; + TPM_KEY_HANDLE handle[1]; +} TPM_KEY_HANDLE_LIST; + +// +// Part 2, section 5.8: TPM_KEY_USAGE values +// +/// +/// TPM_KEY_SIGNING SHALL indicate a signing key. The [private] key SHALL be +/// used for signing operations, only. This means that it MUST be a leaf of the +/// Protected Storage key hierarchy. +/// +#define TPM_KEY_SIGNING ((UINT16) 0x0010) +/// +/// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap +/// and unwrap other keys in the Protected Storage hierarchy +/// +#define TPM_KEY_STORAGE ((UINT16) 0x0011) +/// +/// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for +/// operations that require a TPM identity, only. +/// +#define TPM_KEY_IDENTITY ((UINT16) 0x0012) +/// +/// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during +/// the ChangeAuthAsym process, only. +/// +#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013) +/// +/// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and +/// TPM_Unbind operations only. +/// +#define TPM_KEY_BIND ((UINT16) 0x0014) +/// +/// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding +/// operations. The key MAY be used for both signing and binding operations. +/// The TPM_KEY_LEGACY key type is to allow for use by applications where both +/// signing and encryption operations occur with the same key. The use of this +/// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a +/// key in use for TPM_MigrateKey +/// +#define TPM_KEY_LEGACY ((UINT16) 0x0015) +/// +/// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey +/// +#define TPM_KEY_MIGRATE ((UINT16) 0x0016) + +// +// Part 2, section 5.8.1: Mandatory Key Usage Schemes +// + +#define TPM_ES_NONE ((TPM_ENC_SCHEME) 0x0001) +#define TPM_ES_RSAESPKCSv15 ((TPM_ENC_SCHEME) 0x0002) +#define TPM_ES_RSAESOAEP_SHA1_MGF1 ((TPM_ENC_SCHEME) 0x0003) +#define TPM_ES_SYM_CNT ((TPM_ENC_SCHEME) 0x0004) ///< rev94 defined +#define TPM_ES_SYM_CTR ((TPM_ENC_SCHEME) 0x0004) +#define TPM_ES_SYM_OFB ((TPM_ENC_SCHEME) 0x0005) + +#define TPM_SS_NONE ((TPM_SIG_SCHEME) 0x0001) +#define TPM_SS_RSASSAPKCS1v15_SHA1 ((TPM_SIG_SCHEME) 0x0002) +#define TPM_SS_RSASSAPKCS1v15_DER ((TPM_SIG_SCHEME) 0x0003) +#define TPM_SS_RSASSAPKCS1v15_INFO ((TPM_SIG_SCHEME) 0x0004) + +// +// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values +// +#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00) +#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01) +#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03) + +/// +/// Part 2, section 5.10: TPM_KEY_FLAGS +/// +typedef enum tdTPM_KEY_FLAGS { + redirection = 0x00000001, + migratable = 0x00000002, + isVolatile = 0x00000004, + pcrIgnoredOnRead = 0x00000008, + migrateAuthority = 0x00000010 +} TPM_KEY_FLAGS_BITS; + +/// +/// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE +/// +typedef struct tdTPM_CHANGEAUTH_VALIDATE { + TPM_SECRET newAuthSecret; + TPM_NONCE n1; +} TPM_CHANGEAUTH_VALIDATE; + +/// +/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH +/// declared after section 10 to catch declaration of TPM_PUBKEY +/// +/// Part 2 section 10.1: TPM_KEY_PARMS +/// [size_is(parmSize)] BYTE* parms; +/// +typedef struct tdTPM_KEY_PARMS { + TPM_ALGORITHM_ID algorithmID; + TPM_ENC_SCHEME encScheme; + TPM_SIG_SCHEME sigScheme; + UINT32 parmSize; + UINT8 *parms; +} TPM_KEY_PARMS; + +/// +/// Part 2, section 10.4: TPM_STORE_PUBKEY +/// +typedef struct tdTPM_STORE_PUBKEY { + UINT32 keyLength; + UINT8 key[1]; +} TPM_STORE_PUBKEY; + +/// +/// Part 2, section 10.5: TPM_PUBKEY +/// +typedef struct tdTPM_PUBKEY{ + TPM_KEY_PARMS algorithmParms; + TPM_STORE_PUBKEY pubKey; +} TPM_PUBKEY; + +/// +/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH +/// +typedef struct tdTPM_MIGRATIONKEYAUTH{ + TPM_PUBKEY migrationKey; + TPM_MIGRATE_SCHEME migrationScheme; + TPM_DIGEST digest; +} TPM_MIGRATIONKEYAUTH; + +/// +/// Part 2, section 5.13: TPM_COUNTER_VALUE +/// +typedef struct tdTPM_COUNTER_VALUE{ + TPM_STRUCTURE_TAG tag; + UINT8 label[4]; + TPM_ACTUAL_COUNT counter; +} TPM_COUNTER_VALUE; + +/// +/// Part 2, section 5.14: TPM_SIGN_INFO +/// Size of data indicated by dataLen +/// +typedef struct tdTPM_SIGN_INFO { + TPM_STRUCTURE_TAG tag; + UINT8 fixed[4]; + TPM_NONCE replay; + UINT32 dataLen; + UINT8 *data; +} TPM_SIGN_INFO; + +/// +/// Part 2, section 5.15: TPM_MSA_COMPOSITE +/// Number of migAuthDigest indicated by MSAlist +/// +typedef struct tdTPM_MSA_COMPOSITE { + UINT32 MSAlist; + TPM_DIGEST migAuthDigest[1]; +} TPM_MSA_COMPOSITE; + +/// +/// Part 2, section 5.16: TPM_CMK_AUTH +/// +typedef struct tdTPM_CMK_AUTH{ + TPM_DIGEST migrationAuthorityDigest; + TPM_DIGEST destinationKeyDigest; + TPM_DIGEST sourceKeyDigest; +} TPM_CMK_AUTH; + +// +// Part 2, section 5.17: TPM_CMK_DELEGATE +// +#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31) +#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30) +#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29) +#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28) +#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27) + +/// +/// Part 2, section 5.18: TPM_SELECT_SIZE +/// +typedef struct tdTPM_SELECT_SIZE { + UINT8 major; + UINT8 minor; + UINT16 reqSize; +} TPM_SELECT_SIZE; + +/// +/// Part 2, section 5,19: TPM_CMK_MIGAUTH +/// +typedef struct tdTPM_CMK_MIGAUTH{ + TPM_STRUCTURE_TAG tag; + TPM_DIGEST msaDigest; + TPM_DIGEST pubKeyDigest; +} TPM_CMK_MIGAUTH; + +/// +/// Part 2, section 5.20: TPM_CMK_SIGTICKET +/// +typedef struct tdTPM_CMK_SIGTICKET{ + TPM_STRUCTURE_TAG tag; + TPM_DIGEST verKeyDigest; + TPM_DIGEST signedData; +} TPM_CMK_SIGTICKET; + +/// +/// Part 2, section 5.21: TPM_CMK_MA_APPROVAL +/// +typedef struct tdTPM_CMK_MA_APPROVAL{ + TPM_STRUCTURE_TAG tag; + TPM_DIGEST migrationAuthorityDigest; +} TPM_CMK_MA_APPROVAL; + +// +// Part 2, section 6: Command Tags +// +#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1) +#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2) +#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3) +#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4) +#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5) +#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6) + +/// +/// Part 2, section 7.1: TPM_PERMANENT_FLAGS +/// +typedef struct tdTPM_PERMANENT_FLAGS{ + TPM_STRUCTURE_TAG tag; + BOOLEAN disable; + BOOLEAN ownership; + BOOLEAN deactivated; + BOOLEAN readPubek; + BOOLEAN disableOwnerClear; + BOOLEAN allowMaintenance; + BOOLEAN physicalPresenceLifetimeLock; + BOOLEAN physicalPresenceHWEnable; + BOOLEAN physicalPresenceCMDEnable; + BOOLEAN CEKPUsed; + BOOLEAN TPMpost; + BOOLEAN TPMpostLock; + BOOLEAN FIPS; + BOOLEAN operator; + BOOLEAN enableRevokeEK; + BOOLEAN nvLocked; + BOOLEAN readSRKPub; + BOOLEAN tpmEstablished; + BOOLEAN maintenanceDone; + BOOLEAN disableFullDALogicInfo; +} TPM_PERMANENT_FLAGS; + +// +// Part 2, section 7.1.1: Flag Restrictions (of TPM_PERMANENT_FLAGS) +// +#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1) +#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2) +#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3) +#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4) +#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5) +#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6) +#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7) +#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8) +#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9) +#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10) +#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11) +#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12) +#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13) +#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14) +#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15) +#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16) +#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17) +#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18) +#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19) +#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20) + +/// +/// Part 2, section 7.2: TPM_STCLEAR_FLAGS +/// +typedef struct tdTPM_STCLEAR_FLAGS{ + TPM_STRUCTURE_TAG tag; + BOOLEAN deactivated; + BOOLEAN disableForceClear; + BOOLEAN physicalPresence; + BOOLEAN physicalPresenceLock; + BOOLEAN bGlobalLock; +} TPM_STCLEAR_FLAGS; + +// +// Part 2, section 7.2.1: Flag Restrictions (of TPM_STCLEAR_FLAGS) +// +#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1) +#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2) +#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3) +#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4) +#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5) + +/// +/// Part 2, section 7.3: TPM_STANY_FLAGS +/// +typedef struct tdTPM_STANY_FLAGS{ + TPM_STRUCTURE_TAG tag; + BOOLEAN postInitialise; + TPM_MODIFIER_INDICATOR localityModifier; + BOOLEAN transportExclusive; + BOOLEAN TOSPresent; +} TPM_STANY_FLAGS; + +// +// Part 2, section 7.3.1: Flag Restrictions (of TPM_STANY_FLAGS) +// +#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1) +#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2) +#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3) +#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4) + +// +// All those structures defined in section 7.4, 7.5, 7.6 are not normative and +// thus no definitions here +// +// Part 2, section 7.4: TPM_PERMANENT_DATA +// +#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4 +#define TPM_DELEGATE_KEY TPM_KEY +#define TPM_NUM_PCR 16 +#define TPM_MAX_NV_WRITE_NOOWNER 64 + +// +// Part 2, section 7.4.1: PERMANENT_DATA Subcap for SetCapability +// +#define TPM_PD_REVMAJOR ((TPM_CAPABILITY_AREA) 1) +#define TPM_PD_REVMINOR ((TPM_CAPABILITY_AREA) 2) +#define TPM_PD_TPMPROOF ((TPM_CAPABILITY_AREA) 3) +#define TPM_PD_OWNERAUTH ((TPM_CAPABILITY_AREA) 4) +#define TPM_PD_OPERATORAUTH ((TPM_CAPABILITY_AREA) 5) +#define TPM_PD_MANUMAINTPUB ((TPM_CAPABILITY_AREA) 6) +#define TPM_PD_ENDORSEMENTKEY ((TPM_CAPABILITY_AREA) 7) +#define TPM_PD_SRK ((TPM_CAPABILITY_AREA) 8) +#define TPM_PD_DELEGATEKEY ((TPM_CAPABILITY_AREA) 9) +#define TPM_PD_CONTEXTKEY ((TPM_CAPABILITY_AREA) 10) +#define TPM_PD_AUDITMONOTONICCOUNTER ((TPM_CAPABILITY_AREA) 11) +#define TPM_PD_MONOTONICCOUNTER ((TPM_CAPABILITY_AREA) 12) +#define TPM_PD_PCRATTRIB ((TPM_CAPABILITY_AREA) 13) +#define TPM_PD_ORDINALAUDITSTATUS ((TPM_CAPABILITY_AREA) 14) +#define TPM_PD_AUTHDIR ((TPM_CAPABILITY_AREA) 15) +#define TPM_PD_RNGSTATE ((TPM_CAPABILITY_AREA) 16) +#define TPM_PD_FAMILYTABLE ((TPM_CAPABILITY_AREA) 17) +#define TPM_DELEGATETABLE ((TPM_CAPABILITY_AREA) 18) +#define TPM_PD_EKRESET ((TPM_CAPABILITY_AREA) 19) +#define TPM_PD_MAXNVBUFSIZE ((TPM_CAPABILITY_AREA) 20) +#define TPM_PD_LASTFAMILYID ((TPM_CAPABILITY_AREA) 21) +#define TPM_PD_NOOWNERNVWRITE ((TPM_CAPABILITY_AREA) 22) +#define TPM_PD_RESTRICTDELEGATE ((TPM_CAPABILITY_AREA) 23) +#define TPM_PD_TPMDAASEED ((TPM_CAPABILITY_AREA) 24) +#define TPM_PD_DAAPROOF ((TPM_CAPABILITY_AREA) 25) + +/// +/// Part 2, section 7.5: TPM_STCLEAR_DATA +/// available inside TPM only +/// + typedef struct tdTPM_STCLEAR_DATA{ + TPM_STRUCTURE_TAG tag; + TPM_NONCE contextNonceKey; + TPM_COUNT_ID countID; + UINT32 ownerReference; + BOOLEAN disableResetLock; + TPM_PCRVALUE PCR[TPM_NUM_PCR]; + UINT32 deferredPhysicalPresence; + }TPM_STCLEAR_DATA; + +// +// Part 2, section 7.5.1: STCLEAR_DATA Subcap for SetCapability +// +#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001) +#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002) +#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003) +#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004) +#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005) +#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006) + +// +// Part 2, section 7.6.1: STANY_DATA Subcap for SetCapability +// +#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1) +#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2) +#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3) +#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4) +#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5) +#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6) + +// +// Part 2, section 8: PCR Structures +// + +/// +/// Part 2, section 8.1: TPM_PCR_SELECTION +/// Size of pcrSelect[] indicated by sizeOfSelect +/// +typedef struct tdTPM_PCR_SELECTION { + UINT16 sizeOfSelect; + UINT8 pcrSelect[1]; +} TPM_PCR_SELECTION; + +/// +/// Part 2, section 8.2: TPM_PCR_COMPOSITE +/// Size of pcrValue[] indicated by valueSize +/// +typedef struct tdTPM_PCR_COMPOSITE { + TPM_PCR_SELECTION select; + UINT32 valueSize; + TPM_PCRVALUE pcrValue[1]; +} TPM_PCR_COMPOSITE; + +/// +/// Part 2, section 8.3: TPM_PCR_INFO +/// +typedef struct tdTPM_PCR_INFO { + TPM_PCR_SELECTION pcrSelection; + TPM_COMPOSITE_HASH digestAtRelease; + TPM_COMPOSITE_HASH digestAtCreation; +} TPM_PCR_INFO; + +/// +/// Part 2, section 8.6: TPM_LOCALITY_SELECTION +/// +typedef UINT8 TPM_LOCALITY_SELECTION; + +#define TPM_LOC_FOUR ((UINT8) 0x10) +#define TPM_LOC_THREE ((UINT8) 0x08) +#define TPM_LOC_TWO ((UINT8) 0x04) +#define TPM_LOC_ONE ((UINT8) 0x02) +#define TPM_LOC_ZERO ((UINT8) 0x01) + +/// +/// Part 2, section 8.4: TPM_PCR_INFO_LONG +/// +typedef struct tdTPM_PCR_INFO_LONG { + TPM_STRUCTURE_TAG tag; + TPM_LOCALITY_SELECTION localityAtCreation; + TPM_LOCALITY_SELECTION localityAtRelease; + TPM_PCR_SELECTION creationPCRSelection; + TPM_PCR_SELECTION releasePCRSelection; + TPM_COMPOSITE_HASH digestAtCreation; + TPM_COMPOSITE_HASH digestAtRelease; +} TPM_PCR_INFO_LONG; + +/// +/// Part 2, section 8.5: TPM_PCR_INFO_SHORT +/// +typedef struct tdTPM_PCR_INFO_SHORT{ + TPM_PCR_SELECTION pcrSelection; + TPM_LOCALITY_SELECTION localityAtRelease; + TPM_COMPOSITE_HASH digestAtRelease; +} TPM_PCR_INFO_SHORT; + +/// +/// Part 2, section 8.8: TPM_PCR_ATTRIBUTES +/// +typedef struct tdTPM_PCR_ATTRIBUTES{ + BOOLEAN pcrReset; + TPM_LOCALITY_SELECTION pcrExtendLocal; + TPM_LOCALITY_SELECTION pcrResetLocal; +} TPM_PCR_ATTRIBUTES; + +// +// Part 2, section 9: Storage Structures +// + +/// +/// Part 2, section 9.1: TPM_STORED_DATA +/// [size_is(sealInfoSize)] BYTE* sealInfo; +/// [size_is(encDataSize)] BYTE* encData; +/// +typedef struct tdTPM_STORED_DATA { + TPM_STRUCT_VER ver; + UINT32 sealInfoSize; + UINT8 *sealInfo; + UINT32 encDataSize; + UINT8 *encData; +} TPM_STORED_DATA; + +/// +/// Part 2, section 9.2: TPM_STORED_DATA12 +/// [size_is(sealInfoSize)] BYTE* sealInfo; +/// [size_is(encDataSize)] BYTE* encData; +/// +typedef struct tdTPM_STORED_DATA12 { + TPM_STRUCTURE_TAG tag; + TPM_ENTITY_TYPE et; + UINT32 sealInfoSize; + UINT8 *sealInfo; + UINT32 encDataSize; + UINT8 *encData; +} TPM_STORED_DATA12; + +/// +/// Part 2, section 9.3: TPM_SEALED_DATA +/// [size_is(dataSize)] BYTE* data; +/// +typedef struct tdTPM_SEALED_DATA { + TPM_PAYLOAD_TYPE payload; + TPM_SECRET authData; + TPM_NONCE tpmProof; + TPM_DIGEST storedDigest; + UINT32 dataSize; + UINT8 *data; +} TPM_SEALED_DATA; + +/// +/// Part 2, section 9.4: TPM_SYMMETRIC_KEY +/// [size_is(size)] BYTE* data; +/// +typedef struct tdTPM_SYMMETRIC_KEY { + TPM_ALGORITHM_ID algId; + TPM_ENC_SCHEME encScheme; + UINT16 dataSize; + UINT8 *data; +} TPM_SYMMETRIC_KEY; + +/// +/// Part 2, section 9.5: TPM_BOUND_DATA +/// +typedef struct tdTPM_BOUND_DATA { + TPM_STRUCT_VER ver; + TPM_PAYLOAD_TYPE payload; + UINT8 payloadData[1]; +} TPM_BOUND_DATA; + +// +// Part 2 section 10: TPM_KEY complex +// + +// +// Section 10.1, 10.4, and 10.5 have been defined previously +// + +/// +/// Part 2, section 10.2: TPM_KEY +/// [size_is(encDataSize)] BYTE* encData; +/// +typedef struct tdTPM_KEY{ + TPM_STRUCT_VER ver; + TPM_KEY_USAGE keyUsage; + TPM_KEY_FLAGS keyFlags; + TPM_AUTH_DATA_USAGE authDataUsage; + TPM_KEY_PARMS algorithmParms; + UINT32 PCRInfoSize; + UINT8 *PCRInfo; + TPM_STORE_PUBKEY pubKey; + UINT32 encDataSize; + UINT8 *encData; +} TPM_KEY; + +/// +/// Part 2, section 10.3: TPM_KEY12 +/// [size_is(encDataSize)] BYTE* encData; +/// +typedef struct tdTPM_KEY12{ + TPM_STRUCTURE_TAG tag; + UINT16 fill; + TPM_KEY_USAGE keyUsage; + TPM_KEY_FLAGS keyFlags; + TPM_AUTH_DATA_USAGE authDataUsage; + TPM_KEY_PARMS algorithmParms; + UINT32 PCRInfoSize; + UINT8 *PCRInfo; + TPM_STORE_PUBKEY pubKey; + UINT32 encDataSize; + UINT8 *encData; +} TPM_KEY12; + +/// +/// Part 2, section 10.7: TPM_STORE_PRIVKEY +/// [size_is(keyLength)] BYTE* key; +/// +typedef struct tdTPM_STORE_PRIVKEY { + UINT32 keyLength; + UINT8 *key; +} TPM_STORE_PRIVKEY; + +/// +/// Part 2, section 10.6: TPM_STORE_ASYMKEY +/// +typedef struct tdTPM_STORE_ASYMKEY { // pos len total + TPM_PAYLOAD_TYPE payload; // 0 1 1 + TPM_SECRET usageAuth; // 1 20 21 + TPM_SECRET migrationAuth; // 21 20 41 + TPM_DIGEST pubDataDigest; // 41 20 61 + TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214 +} TPM_STORE_ASYMKEY; + +/// +/// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY +/// [size_is(partPrivKeyLen)] BYTE* partPrivKey; +/// +typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total + TPM_PAYLOAD_TYPE payload; // 0 1 1 + TPM_SECRET usageAuth; // 1 20 21 + TPM_DIGEST pubDataDigest; // 21 20 41 + UINT32 partPrivKeyLen; // 41 4 45 + UINT8 *partPrivKey; // 45 112-127 157-172 +} TPM_MIGRATE_ASYMKEY; + +/// +/// Part 2, section 10.9: TPM_KEY_CONTROL +/// +#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001) + +// +// Part 2, section 11: Signed Structures +// + +/// +/// Part 2, section 11.1: TPM_CERTIFY_INFO Structure +/// +typedef struct tdTPM_CERTIFY_INFO { + TPM_STRUCT_VER version; + TPM_KEY_USAGE keyUsage; + TPM_KEY_FLAGS keyFlags; + TPM_AUTH_DATA_USAGE authDataUsage; + TPM_KEY_PARMS algorithmParms; + TPM_DIGEST pubkeyDigest; + TPM_NONCE data; + BOOLEAN parentPCRStatus; + UINT32 PCRInfoSize; + UINT8 *PCRInfo; +} TPM_CERTIFY_INFO; + +/// +/// Part 2, section 11.2: TPM_CERTIFY_INFO2 Structure +/// +typedef struct tdTPM_CERTIFY_INFO2 { + TPM_STRUCTURE_TAG tag; + UINT8 fill; + TPM_PAYLOAD_TYPE payloadType; + TPM_KEY_USAGE keyUsage; + TPM_KEY_FLAGS keyFlags; + TPM_AUTH_DATA_USAGE authDataUsage; + TPM_KEY_PARMS algorithmParms; + TPM_DIGEST pubkeyDigest; + TPM_NONCE data; + BOOLEAN parentPCRStatus; + UINT32 PCRInfoSize; + UINT8 *PCRInfo; + UINT32 migrationAuthoritySize; + UINT8 *migrationAuthority; +} TPM_CERTIFY_INFO2; + +/// +/// Part 2, section 11.3 TPM_QUOTE_INFO Structure +/// +typedef struct tdTPM_QUOTE_INFO { + TPM_STRUCT_VER version; + UINT8 fixed[4]; + TPM_COMPOSITE_HASH digestValue; + TPM_NONCE externalData; +} TPM_QUOTE_INFO; + +/// +/// Part 2, section 11.4 TPM_QUOTE_INFO2 Structure +/// +typedef struct tdTPM_QUOTE_INFO2 { + TPM_STRUCTURE_TAG tag; + UINT8 fixed[4]; + TPM_NONCE externalData; + TPM_PCR_INFO_SHORT infoShort; +} TPM_QUOTE_INFO2; + +// +// Part 2, section 12: Identity Structures +// + +/// +/// Part 2, section 12.1 TPM_EK_BLOB +/// +typedef struct tdTPM_EK_BLOB { + TPM_STRUCTURE_TAG tag; + TPM_EK_TYPE ekType; + UINT32 blobSize; + UINT8 *blob; +} TPM_EK_BLOB; + +/// +/// Part 2, section 12.2 TPM_EK_BLOB_ACTIVATE +/// +typedef struct tdTPM_EK_BLOB_ACTIVATE { + TPM_STRUCTURE_TAG tag; + TPM_SYMMETRIC_KEY sessionKey; + TPM_DIGEST idDigest; + TPM_PCR_INFO_SHORT pcrInfo; +} TPM_EK_BLOB_ACTIVATE; + +/// +/// Part 2, section 12.3 TPM_EK_BLOB_AUTH +/// +typedef struct tdTPM_EK_BLOB_AUTH { + TPM_STRUCTURE_TAG tag; + TPM_SECRET authValue; +} TPM_EK_BLOB_AUTH; + + +/// +/// Part 2, section 12.5 TPM_IDENTITY_CONTENTS +/// +typedef struct tdTPM_IDENTITY_CONTENTS { + TPM_STRUCT_VER ver; + UINT32 ordinal; + TPM_CHOSENID_HASH labelPrivCADigest; + TPM_PUBKEY identityPubKey; +} TPM_IDENTITY_CONTENTS; + +/// +/// Part 2, section 12.6 TPM_IDENTITY_REQ +/// +typedef struct tdTPM_IDENTITY_REQ { + UINT32 asymSize; + UINT32 symSize; + TPM_KEY_PARMS asymAlgorithm; + TPM_KEY_PARMS symAlgorithm; + UINT8 *asymBlob; + UINT8 *symBlob; +} TPM_IDENTITY_REQ; + +/// +/// Part 2, section 12.7 TPM_IDENTITY_PROOF +/// +typedef struct tdTPM_IDENTITY_PROOF { + TPM_STRUCT_VER ver; + UINT32 labelSize; + UINT32 identityBindingSize; + UINT32 endorsementSize; + UINT32 platformSize; + UINT32 conformanceSize; + TPM_PUBKEY identityKey; + UINT8 *labelArea; + UINT8 *identityBinding; + UINT8 *endorsementCredential; + UINT8 *platformCredential; + UINT8 *conformanceCredential; +} TPM_IDENTITY_PROOF; + +/// +/// Part 2, section 12.8 TPM_ASYM_CA_CONTENTS +/// +typedef struct tdTPM_ASYM_CA_CONTENTS { + TPM_SYMMETRIC_KEY sessionKey; + TPM_DIGEST idDigest; +} TPM_ASYM_CA_CONTENTS; + +/// +/// Part 2, section 12.9 TPM_SYM_CA_ATTESTATION +/// +typedef struct tdTPM_SYM_CA_ATTESTATION { + UINT32 credSize; + TPM_KEY_PARMS algorithm; + UINT8 *credential; +} TPM_SYM_CA_ATTESTATION; + +/// +/// Part 2, section 15: Tick Structures +/// Placed here out of order because definitions are used in section 13. +/// +typedef struct tdTPM_CURRENT_TICKS { + TPM_STRUCTURE_TAG tag; + UINT64 currentTicks; + UINT16 tickRate; + TPM_NONCE tickNonce; +} TPM_CURRENT_TICKS; + +/// +/// Part 2, section 13: Transport structures +/// + +/// +/// Part 2, section 13.1: TPM _TRANSPORT_PUBLIC +/// +typedef struct tdTPM_TRANSPORT_PUBLIC { + TPM_STRUCTURE_TAG tag; + TPM_TRANSPORT_ATTRIBUTES transAttributes; + TPM_ALGORITHM_ID algId; + TPM_ENC_SCHEME encScheme; +} TPM_TRANSPORT_PUBLIC; + +// +// Part 2, section 13.1.1 TPM_TRANSPORT_ATTRIBUTES Definitions +// +#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0) +#define TPM_TRANSPORT_LOG ((UINT32)BIT1) +#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2) + +/// +/// Part 2, section 13.2 TPM_TRANSPORT_INTERNAL +/// +typedef struct tdTPM_TRANSPORT_INTERNAL { + TPM_STRUCTURE_TAG tag; + TPM_AUTHDATA authData; + TPM_TRANSPORT_PUBLIC transPublic; + TPM_TRANSHANDLE transHandle; + TPM_NONCE transNonceEven; + TPM_DIGEST transDigest; +} TPM_TRANSPORT_INTERNAL; + +/// +/// Part 2, section 13.3 TPM_TRANSPORT_LOG_IN structure +/// +typedef struct tdTPM_TRANSPORT_LOG_IN { + TPM_STRUCTURE_TAG tag; + TPM_DIGEST parameters; + TPM_DIGEST pubKeyHash; +} TPM_TRANSPORT_LOG_IN; + +/// +/// Part 2, section 13.4 TPM_TRANSPORT_LOG_OUT structure +/// +typedef struct tdTPM_TRANSPORT_LOG_OUT { + TPM_STRUCTURE_TAG tag; + TPM_CURRENT_TICKS currentTicks; + TPM_DIGEST parameters; + TPM_MODIFIER_INDICATOR locality; +} TPM_TRANSPORT_LOG_OUT; + +/// +/// Part 2, section 13.5 TPM_TRANSPORT_AUTH structure +/// +typedef struct tdTPM_TRANSPORT_AUTH { + TPM_STRUCTURE_TAG tag; + TPM_AUTHDATA authData; +} TPM_TRANSPORT_AUTH; + +// +// Part 2, section 14: Audit Structures +// + +/// +/// Part 2, section 14.1 TPM_AUDIT_EVENT_IN structure +/// +typedef struct tdTPM_AUDIT_EVENT_IN { + TPM_STRUCTURE_TAG tag; + TPM_DIGEST inputParms; + TPM_COUNTER_VALUE auditCount; +} TPM_AUDIT_EVENT_IN; + +/// +/// Part 2, section 14.2 TPM_AUDIT_EVENT_OUT structure +/// +typedef struct tdTPM_AUDIT_EVENT_OUT { + TPM_STRUCTURE_TAG tag; + TPM_COMMAND_CODE ordinal; + TPM_DIGEST outputParms; + TPM_COUNTER_VALUE auditCount; + TPM_RESULT returnCode; +} TPM_AUDIT_EVENT_OUT; + +// +// Part 2, section 16: Return Codes +// + +#define TPM_VENDOR_ERROR TPM_Vendor_Specific32 +#define TPM_NON_FATAL 0x00000800 + +#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE) +#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1)) +#define TPM_BADINDEX ((TPM_RESULT) (TPM_BASE + 2)) +#define TPM_BAD_PARAMETER ((TPM_RESULT) (TPM_BASE + 3)) +#define TPM_AUDITFAILURE ((TPM_RESULT) (TPM_BASE + 4)) +#define TPM_CLEAR_DISABLED ((TPM_RESULT) (TPM_BASE + 5)) +#define TPM_DEACTIVATED ((TPM_RESULT) (TPM_BASE + 6)) +#define TPM_DISABLED ((TPM_RESULT) (TPM_BASE + 7)) +#define TPM_DISABLED_CMD ((TPM_RESULT) (TPM_BASE + 8)) +#define TPM_FAIL ((TPM_RESULT) (TPM_BASE + 9)) +#define TPM_BAD_ORDINAL ((TPM_RESULT) (TPM_BASE + 10)) +#define TPM_INSTALL_DISABLED ((TPM_RESULT) (TPM_BASE + 11)) +#define TPM_INVALID_KEYHANDLE ((TPM_RESULT) (TPM_BASE + 12)) +#define TPM_KEYNOTFOUND ((TPM_RESULT) (TPM_BASE + 13)) +#define TPM_INAPPROPRIATE_ENC ((TPM_RESULT) (TPM_BASE + 14)) +#define TPM_MIGRATEFAIL ((TPM_RESULT) (TPM_BASE + 15)) +#define TPM_INVALID_PCR_INFO ((TPM_RESULT) (TPM_BASE + 16)) +#define TPM_NOSPACE ((TPM_RESULT) (TPM_BASE + 17)) +#define TPM_NOSRK ((TPM_RESULT) (TPM_BASE + 18)) +#define TPM_NOTSEALED_BLOB ((TPM_RESULT) (TPM_BASE + 19)) +#define TPM_OWNER_SET ((TPM_RESULT) (TPM_BASE + 20)) +#define TPM_RESOURCES ((TPM_RESULT) (TPM_BASE + 21)) +#define TPM_SHORTRANDOM ((TPM_RESULT) (TPM_BASE + 22)) +#define TPM_SIZE ((TPM_RESULT) (TPM_BASE + 23)) +#define TPM_WRONGPCRVAL ((TPM_RESULT) (TPM_BASE + 24)) +#define TPM_BAD_PARAM_SIZE ((TPM_RESULT) (TPM_BASE + 25)) +#define TPM_SHA_THREAD ((TPM_RESULT) (TPM_BASE + 26)) +#define TPM_SHA_ERROR ((TPM_RESULT) (TPM_BASE + 27)) +#define TPM_FAILEDSELFTEST ((TPM_RESULT) (TPM_BASE + 28)) +#define TPM_AUTH2FAIL ((TPM_RESULT) (TPM_BASE + 29)) +#define TPM_BADTAG ((TPM_RESULT) (TPM_BASE + 30)) +#define TPM_IOERROR ((TPM_RESULT) (TPM_BASE + 31)) +#define TPM_ENCRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 32)) +#define TPM_DECRYPT_ERROR ((TPM_RESULT) (TPM_BASE + 33)) +#define TPM_INVALID_AUTHHANDLE ((TPM_RESULT) (TPM_BASE + 34)) +#define TPM_NO_ENDORSEMENT ((TPM_RESULT) (TPM_BASE + 35)) +#define TPM_INVALID_KEYUSAGE ((TPM_RESULT) (TPM_BASE + 36)) +#define TPM_WRONG_ENTITYTYPE ((TPM_RESULT) (TPM_BASE + 37)) +#define TPM_INVALID_POSTINIT ((TPM_RESULT) (TPM_BASE + 38)) +#define TPM_INAPPROPRIATE_SIG ((TPM_RESULT) (TPM_BASE + 39)) +#define TPM_BAD_KEY_PROPERTY ((TPM_RESULT) (TPM_BASE + 40)) +#define TPM_BAD_MIGRATION ((TPM_RESULT) (TPM_BASE + 41)) +#define TPM_BAD_SCHEME ((TPM_RESULT) (TPM_BASE + 42)) +#define TPM_BAD_DATASIZE ((TPM_RESULT) (TPM_BASE + 43)) +#define TPM_BAD_MODE ((TPM_RESULT) (TPM_BASE + 44)) +#define TPM_BAD_PRESENCE ((TPM_RESULT) (TPM_BASE + 45)) +#define TPM_BAD_VERSION ((TPM_RESULT) (TPM_BASE + 46)) +#define TPM_NO_WRAP_TRANSPORT ((TPM_RESULT) (TPM_BASE + 47)) +#define TPM_AUDITFAIL_UNSUCCESSFUL ((TPM_RESULT) (TPM_BASE + 48)) +#define TPM_AUDITFAIL_SUCCESSFUL ((TPM_RESULT) (TPM_BASE + 49)) +#define TPM_NOTRESETABLE ((TPM_RESULT) (TPM_BASE + 50)) +#define TPM_NOTLOCAL ((TPM_RESULT) (TPM_BASE + 51)) +#define TPM_BAD_TYPE ((TPM_RESULT) (TPM_BASE + 52)) +#define TPM_INVALID_RESOURCE ((TPM_RESULT) (TPM_BASE + 53)) +#define TPM_NOTFIPS ((TPM_RESULT) (TPM_BASE + 54)) +#define TPM_INVALID_FAMILY ((TPM_RESULT) (TPM_BASE + 55)) +#define TPM_NO_NV_PERMISSION ((TPM_RESULT) (TPM_BASE + 56)) +#define TPM_REQUIRES_SIGN ((TPM_RESULT) (TPM_BASE + 57)) +#define TPM_KEY_NOTSUPPORTED ((TPM_RESULT) (TPM_BASE + 58)) +#define TPM_AUTH_CONFLICT ((TPM_RESULT) (TPM_BASE + 59)) +#define TPM_AREA_LOCKED ((TPM_RESULT) (TPM_BASE + 60)) +#define TPM_BAD_LOCALITY ((TPM_RESULT) (TPM_BASE + 61)) +#define TPM_READ_ONLY ((TPM_RESULT) (TPM_BASE + 62)) +#define TPM_PER_NOWRITE ((TPM_RESULT) (TPM_BASE + 63)) +#define TPM_FAMILYCOUNT ((TPM_RESULT) (TPM_BASE + 64)) +#define TPM_WRITE_LOCKED ((TPM_RESULT) (TPM_BASE + 65)) +#define TPM_BAD_ATTRIBUTES ((TPM_RESULT) (TPM_BASE + 66)) +#define TPM_INVALID_STRUCTURE ((TPM_RESULT) (TPM_BASE + 67)) +#define TPM_KEY_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 68)) +#define TPM_BAD_COUNTER ((TPM_RESULT) (TPM_BASE + 69)) +#define TPM_NOT_FULLWRITE ((TPM_RESULT) (TPM_BASE + 70)) +#define TPM_CONTEXT_GAP ((TPM_RESULT) (TPM_BASE + 71)) +#define TPM_MAXNVWRITES ((TPM_RESULT) (TPM_BASE + 72)) +#define TPM_NOOPERATOR ((TPM_RESULT) (TPM_BASE + 73)) +#define TPM_RESOURCEMISSING ((TPM_RESULT) (TPM_BASE + 74)) +#define TPM_DELEGATE_LOCK ((TPM_RESULT) (TPM_BASE + 75)) +#define TPM_DELEGATE_FAMILY ((TPM_RESULT) (TPM_BASE + 76)) +#define TPM_DELEGATE_ADMIN ((TPM_RESULT) (TPM_BASE + 77)) +#define TPM_TRANSPORT_NOTEXCLUSIVE ((TPM_RESULT) (TPM_BASE + 78)) +#define TPM_OWNER_CONTROL ((TPM_RESULT) (TPM_BASE + 79)) +#define TPM_DAA_RESOURCES ((TPM_RESULT) (TPM_BASE + 80)) +#define TPM_DAA_INPUT_DATA0 ((TPM_RESULT) (TPM_BASE + 81)) +#define TPM_DAA_INPUT_DATA1 ((TPM_RESULT) (TPM_BASE + 82)) +#define TPM_DAA_ISSUER_SETTINGS ((TPM_RESULT) (TPM_BASE + 83)) +#define TPM_DAA_TPM_SETTINGS ((TPM_RESULT) (TPM_BASE + 84)) +#define TPM_DAA_STAGE ((TPM_RESULT) (TPM_BASE + 85)) +#define TPM_DAA_ISSUER_VALIDITY ((TPM_RESULT) (TPM_BASE + 86)) +#define TPM_DAA_WRONG_W ((TPM_RESULT) (TPM_BASE + 87)) +#define TPM_BAD_HANDLE ((TPM_RESULT) (TPM_BASE + 88)) +#define TPM_BAD_DELEGATE ((TPM_RESULT) (TPM_BASE + 89)) +#define TPM_BADCONTEXT ((TPM_RESULT) (TPM_BASE + 90)) +#define TPM_TOOMANYCONTEXTS ((TPM_RESULT) (TPM_BASE + 91)) +#define TPM_MA_TICKET_SIGNATURE ((TPM_RESULT) (TPM_BASE + 92)) +#define TPM_MA_DESTINATION ((TPM_RESULT) (TPM_BASE + 93)) +#define TPM_MA_SOURCE ((TPM_RESULT) (TPM_BASE + 94)) +#define TPM_MA_AUTHORITY ((TPM_RESULT) (TPM_BASE + 95)) +#define TPM_PERMANENTEK ((TPM_RESULT) (TPM_BASE + 97)) +#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98)) +#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99)) + +#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL)) +#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1)) +#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2)) +#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3)) + +// +// Part 2, section 17: Ordinals +// +// Ordinals are 32 bit values. The upper byte contains values that serve as +// flag indicators, the next byte contains values indicating what committee +// designated the ordinal, and the final two bytes contain the Command +// Ordinal Index. +// 3 2 1 +// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// |P|C|V| Reserved| Purview | Command Ordinal Index | +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// +// Where: +// +// * P is Protected/Unprotected command. When 0 the command is a Protected +// command, when 1 the command is an Unprotected command. +// +// * C is Non-Connection/Connection related command. When 0 this command +// passes through to either the protected (TPM) or unprotected (TSS) +// components. +// +// * V is TPM/Vendor command. When 0 the command is TPM defined, when 1 the +// command is vendor defined. +// +// * All reserved area bits are set to 0. +// + +#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A) +#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B) +#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032) +#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033) +#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052) +#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C) +#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F) +#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E) +#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010) +#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D) +#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024) +#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B) +#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013) +#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012) +#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C) +#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053) +#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A) +#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC) +#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078) +#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C) +#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028) +#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F) +#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F) +#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029) +#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031) +#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4) +#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5) +#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8) +#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2) +#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB) +#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1) +#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6) +#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A) +#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019) +#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E) +#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C) +#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E) +#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011) +#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6) +#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022) +#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7) +#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014) +#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA) +#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA) +#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D) +#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085) +#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086) +#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082) +#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083) +#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065) +#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066) +#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064) +#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C) +#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021) +#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046) +#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054) +#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1) +#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD) +#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097) +#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023) +#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E) +#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7) +#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9) +#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020) +#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041) +#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5) +#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D) +#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F) +#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079) +#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025) +#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC) +#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF) +#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0) +#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD) +#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE) +#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A) +#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B) +#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B) +#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081) +#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D) +#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E) +#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8) +#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015) +#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070) +#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F) +#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072) +#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016) +#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E) +#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE) +#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030) +#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C) +#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF) +#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0) +#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8) +#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A) +#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040) +#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080) +#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6) +#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8) +#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4) +#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098) +#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017) +#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D) +#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050) +#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F) +#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074) +#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D) +#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071) +#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075) +#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A) +#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073) +#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2) +#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3) +#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0) +#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1) +#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C) +#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099) +#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047) +#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D) +#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096) +#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2) +#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E) +#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018) +#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A) +#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B) + +// +// Part 2, section 18: Context structures +// + +/// +/// Part 2, section 18.1: TPM_CONTEXT_BLOB +/// +typedef struct tdTPM_CONTEXT_BLOB { + TPM_STRUCTURE_TAG tag; + TPM_RESOURCE_TYPE resourceType; + TPM_HANDLE handle; + UINT8 label[16]; + UINT32 contextCount; + TPM_DIGEST integrityDigest; + UINT32 additionalSize; + UINT8 *additionalData; + UINT32 sensitiveSize; + UINT8 *sensitiveData; +} TPM_CONTEXT_BLOB; + +/// +/// Part 2, section 18.2 TPM_CONTEXT_SENSITIVE +/// +typedef struct tdTPM_CONTEXT_SENSITIVE { + TPM_STRUCTURE_TAG tag; + TPM_NONCE contextNonce; + UINT32 internalSize; + UINT8 *internalData; +} TPM_CONTEXT_SENSITIVE; + +// +// Part 2, section 19: NV Structures +// + +// +// Part 2, section 19.1.1: Required TPM_NV_INDEX values +// +#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff) +#define TPM_NV_INDEX0 ((UINT32)0x00000000) +#define TPM_NV_INDEX_DIR ((UINT32)0x10000001) +#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000) +#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001) +#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002) +#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003) +// +// Part 2, section 19.1.2: Reserved Index values +// +#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100) +#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200) +#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300) +#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400) +#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500) +#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000) + +/// +/// Part 2, section 19.2: TPM_NV_ATTRIBUTES +/// +typedef struct tdTPM_NV_ATTRIBUTES { + TPM_STRUCTURE_TAG tag; + UINT32 attributes; +} TPM_NV_ATTRIBUTES; + +#define TPM_NV_PER_READ_STCLEAR (BIT31) +#define TPM_NV_PER_AUTHREAD (BIT18) +#define TPM_NV_PER_OWNERREAD (BIT17) +#define TPM_NV_PER_PPREAD (BIT16) +#define TPM_NV_PER_GLOBALLOCK (BIT15) +#define TPM_NV_PER_WRITE_STCLEAR (BIT14) +#define TPM_NV_PER_WRITEDEFINE (BIT13) +#define TPM_NV_PER_WRITEALL (BIT12) +#define TPM_NV_PER_AUTHWRITE (BIT2) +#define TPM_NV_PER_OWNERWRITE (BIT1) +#define TPM_NV_PER_PPWRITE (BIT0) + +/// +/// Part 2, section 19.3: TPM_NV_DATA_PUBLIC +/// +typedef struct tdTPM_NV_DATA_PUBLIC { + TPM_STRUCTURE_TAG tag; + TPM_NV_INDEX nvIndex; + TPM_PCR_INFO_SHORT pcrInfoRead; + TPM_PCR_INFO_SHORT pcrInfoWrite; + TPM_NV_ATTRIBUTES permission; + BOOLEAN bReadSTClear; + BOOLEAN bWriteSTClear; + BOOLEAN bWriteDefine; + UINT32 dataSize; +} TPM_NV_DATA_PUBLIC; + +// +// Part 2, section 20: Delegate Structures +// + +#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001) +#define TPM_DEL_KEY_BITS ((UINT32)0x00000002) +/// +/// Part 2, section 20.2: Delegate Definitions +/// +typedef struct tdTPM_DELEGATIONS { + TPM_STRUCTURE_TAG tag; + UINT32 delegateType; + UINT32 per1; + UINT32 per2; +} TPM_DELEGATIONS; + +// +// Part 2, section 20.2.1: Owner Permission Settings +// +#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30) +#define TPM_DELEGATE_DirWriteAuth (BIT29) +#define TPM_DELEGATE_CMK_ApproveMA (BIT28) +#define TPM_DELEGATE_NV_WriteValue (BIT27) +#define TPM_DELEGATE_CMK_CreateTicket (BIT26) +#define TPM_DELEGATE_NV_ReadValue (BIT25) +#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24) +#define TPM_DELEGATE_DAA_Join (BIT23) +#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22) +#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21) +#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20) +#define TPM_DELEGATE_KillMaintenanceFeature (BIT19) +#define TPM_DELEGATE_OwnerReadInteralPub (BIT18) +#define TPM_DELEGATE_ResetLockValue (BIT17) +#define TPM_DELEGATE_OwnerClear (BIT16) +#define TPM_DELEGATE_DisableOwnerClear (BIT15) +#define TPM_DELEGATE_NV_DefineSpace (BIT14) +#define TPM_DELEGATE_OwnerSetDisable (BIT13) +#define TPM_DELEGATE_SetCapability (BIT12) +#define TPM_DELEGATE_MakeIdentity (BIT11) +#define TPM_DELEGATE_ActivateIdentity (BIT10) +#define TPM_DELEGATE_OwnerReadPubek (BIT9) +#define TPM_DELEGATE_DisablePubekRead (BIT8) +#define TPM_DELEGATE_SetRedirection (BIT7) +#define TPM_DELEGATE_FieldUpgrade (BIT6) +#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5) +#define TPM_DELEGATE_CreateCounter (BIT4) +#define TPM_DELEGATE_ReleaseCounterOwner (BIT3) +#define TPM_DELEGATE_DelegateManage (BIT2) +#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1) +#define TPM_DELEGATE_DAA_Sign (BIT0) + +// +// Part 2, section 20.2.3: Key Permission settings +// +#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28) +#define TPM_KEY_DELEGATE_TickStampBlob (BIT27) +#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26) +#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25) +#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24) +#define TPM_KEY_DELEGATE_MigrateKey (BIT23) +#define TPM_KEY_DELEGATE_LoadKey2 (BIT22) +#define TPM_KEY_DELEGATE_EstablishTransport (BIT21) +#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20) +#define TPM_KEY_DELEGATE_Quote2 (BIT19) +#define TPM_KEY_DELEGATE_Sealx (BIT18) +#define TPM_KEY_DELEGATE_MakeIdentity (BIT17) +#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16) +#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15) +#define TPM_KEY_DELEGATE_Sign (BIT14) +#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13) +#define TPM_KEY_DELEGATE_CertifyKey (BIT12) +#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11) +#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10) +#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9) +#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8) +#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7) +#define TPM_KEY_DELEGATE_ChangeAuth (BIT6) +#define TPM_KEY_DELEGATE_GetPubKey (BIT5) +#define TPM_KEY_DELEGATE_UnBind (BIT4) +#define TPM_KEY_DELEGATE_Quote (BIT3) +#define TPM_KEY_DELEGATE_Unseal (BIT2) +#define TPM_KEY_DELEGATE_Seal (BIT1) +#define TPM_KEY_DELEGATE_LoadKey (BIT0) + +// +// Part 2, section 20.3: TPM_FAMILY_FLAGS +// +#define TPM_DELEGATE_ADMIN_LOCK (BIT1) +#define TPM_FAMFLAG_ENABLE (BIT0) + +/// +/// Part 2, section 20.4: TPM_FAMILY_LABEL +/// +typedef struct tdTPM_FAMILY_LABEL { + UINT8 label; +} TPM_FAMILY_LABEL; + +/// +/// Part 2, section 20.5: TPM_FAMILY_TABLE_ENTRY +/// +typedef struct tdTPM_FAMILY_TABLE_ENTRY { + TPM_STRUCTURE_TAG tag; + TPM_FAMILY_LABEL label; + TPM_FAMILY_ID familyID; + TPM_FAMILY_VERIFICATION verificationCount; + TPM_FAMILY_FLAGS flags; +} TPM_FAMILY_TABLE_ENTRY; + +// +// Part 2, section 20.6: TPM_FAMILY_TABLE +// +#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8 + +typedef struct tdTPM_FAMILY_TABLE{ + TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN]; +} TPM_FAMILY_TABLE; + +/// +/// Part 2, section 20.7: TPM_DELEGATE_LABEL +/// +typedef struct tdTPM_DELEGATE_LABEL { + UINT8 label; +} TPM_DELEGATE_LABEL; + +/// +/// Part 2, section 20.8: TPM_DELEGATE_PUBLIC +/// +typedef struct tdTPM_DELEGATE_PUBLIC { + TPM_STRUCTURE_TAG tag; + TPM_DELEGATE_LABEL label; + TPM_PCR_INFO_SHORT pcrInfo; + TPM_DELEGATIONS permissions; + TPM_FAMILY_ID familyID; + TPM_FAMILY_VERIFICATION verificationCount; +} TPM_DELEGATE_PUBLIC; + +/// +/// Part 2, section 20.9: TPM_DELEGATE_TABLE_ROW +/// +typedef struct tdTPM_DELEGATE_TABLE_ROW { + TPM_STRUCTURE_TAG tag; + TPM_DELEGATE_PUBLIC pub; + TPM_SECRET authValue; +} TPM_DELEGATE_TABLE_ROW; + +// +// Part 2, section 20.10: TPM_DELEGATE_TABLE +// +#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2 + +typedef struct tdTPM_DELEGATE_TABLE{ + TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN]; +} TPM_DELEGATE_TABLE; + +/// +/// Part 2, section 20.11: TPM_DELEGATE_SENSITIVE +/// +typedef struct tdTPM_DELEGATE_SENSITIVE { + TPM_STRUCTURE_TAG tag; + TPM_SECRET authValue; +} TPM_DELEGATE_SENSITIVE; + +/// +/// Part 2, section 20.12: TPM_DELEGATE_OWNER_BLOB +/// +typedef struct tdTPM_DELEGATE_OWNER_BLOB { + TPM_STRUCTURE_TAG tag; + TPM_DELEGATE_PUBLIC pub; + TPM_DIGEST integrityDigest; + UINT32 additionalSize; + UINT8 *additionalArea; + UINT32 sensitiveSize; + UINT8 *sensitiveArea; +} TPM_DELEGATE_OWNER_BLOB; + +/// +/// Part 2, section 20.13: TTPM_DELEGATE_KEY_BLOB +/// +typedef struct tdTPM_DELEGATE_KEY_BLOB { + TPM_STRUCTURE_TAG tag; + TPM_DELEGATE_PUBLIC pub; + TPM_DIGEST integrityDigest; + TPM_DIGEST pubKeyDigest; + UINT32 additionalSize; + UINT8 *additionalArea; + UINT32 sensitiveSize; + UINT8 *sensitiveArea; +} TPM_DELEGATE_KEY_BLOB; + +// +// Part 2, section 20.14: TPM_FAMILY_OPERATION Values +// +#define TPM_FAMILY_CREATE ((UINT32)0x00000001) +#define TPM_FAMILY_ENABLE ((UINT32)0x00000002) +#define TPM_FAMILY_ADMIN ((UINT32)0x00000003) +#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004) + +// +// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability +// +#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001) +#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002) +#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003) +#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004) +#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005) +#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006) +#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007) +#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008) +#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009) +#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C) +#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D) +#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010) +#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011) +#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012) +#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014) +#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015) +#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017) +#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018) +#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A) + +#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108) +#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109) + +// +// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability +// +#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101) +#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102) +#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103) +#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104) +#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107) +#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A) +#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B) +#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C) +#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D) +#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E) +#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F) +#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110) +#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111) +#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112) +#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113) +#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114) +#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115) +#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116) +#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117) +#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119) +#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A) +#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B) +#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C) +#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D) +#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E) +#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F) +#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120) +#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122) +#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123) +#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124) + +// +// Part 2, section 21.4: TPM_CAPABILITY_AREA for SetCapability +// +#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001) +#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002) +#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003) +#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004) +#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005) +#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006) + +/// +/// Part 2, section 21.6: TPM_CAP_VERSION_INFO +/// [size_is(vendorSpecificSize)] BYTE* vendorSpecific; +/// +typedef struct tdTPM_CAP_VERSION_INFO { + TPM_STRUCTURE_TAG tag; + TPM_VERSION version; + UINT16 specLevel; + UINT8 errataRev; + UINT8 tpmVendorID[4]; + UINT16 vendorSpecificSize; + UINT8 *vendorSpecific; +} TPM_CAP_VERSION_INFO; + +/// +/// Part 2, section 21.10: TPM_DA_ACTION_TYPE +/// +typedef struct tdTPM_DA_ACTION_TYPE { + TPM_STRUCTURE_TAG tag; + UINT32 actions; +} TPM_DA_ACTION_TYPE; + +#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3) +#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2) +#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1) +#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0) + +/// +/// Part 2, section 21.7: TPM_DA_INFO +/// +typedef struct tdTPM_DA_INFO { + TPM_STRUCTURE_TAG tag; + TPM_DA_STATE state; + UINT16 currentCount; + UINT16 thresholdCount; + TPM_DA_ACTION_TYPE actionAtThreshold; + UINT32 actionDependValue; + UINT32 vendorDataSize; + UINT8 *vendorData; +} TPM_DA_INFO; + +/// +/// Part 2, section 21.8: TPM_DA_INFO_LIMITED +/// +typedef struct tdTPM_DA_INFO_LIMITED { + TPM_STRUCTURE_TAG tag; + TPM_DA_STATE state; + TPM_DA_ACTION_TYPE actionAtThreshold; + UINT32 vendorDataSize; + UINT8 *vendorData; +} TPM_DA_INFO_LIMITED; + +// +// Part 2, section 21.9: CAP_PROPERTY Subcap values for GetCapability +// +#define TPM_DA_STATE_INACTIVE ((UINT8)0x00) +#define TPM_DA_STATE_ACTIVE ((UINT8)0x01) + +// +// Part 2, section 22: DAA Structures +// + +// +// Part 2, section 22.1: Size definitions +// +#define TPM_DAA_SIZE_r0 (43) +#define TPM_DAA_SIZE_r1 (43) +#define TPM_DAA_SIZE_r2 (128) +#define TPM_DAA_SIZE_r3 (168) +#define TPM_DAA_SIZE_r4 (219) +#define TPM_DAA_SIZE_NT (20) +#define TPM_DAA_SIZE_v0 (128) +#define TPM_DAA_SIZE_v1 (192) +#define TPM_DAA_SIZE_NE (256) +#define TPM_DAA_SIZE_w (256) +#define TPM_DAA_SIZE_issuerModulus (256) +// +// Part 2, section 22.2: Constant definitions +// +#define TPM_DAA_power0 (104) +#define TPM_DAA_power1 (1024) + +/// +/// Part 2, section 22.3: TPM_DAA_ISSUER +/// +typedef struct tdTPM_DAA_ISSUER { + TPM_STRUCTURE_TAG tag; + TPM_DIGEST DAA_digest_R0; + TPM_DIGEST DAA_digest_R1; + TPM_DIGEST DAA_digest_S0; + TPM_DIGEST DAA_digest_S1; + TPM_DIGEST DAA_digest_n; + TPM_DIGEST DAA_digest_gamma; + UINT8 DAA_generic_q[26]; +} TPM_DAA_ISSUER; + +/// +/// Part 2, section 22.4: TPM_DAA_TPM +/// +typedef struct tdTPM_DAA_TPM { + TPM_STRUCTURE_TAG tag; + TPM_DIGEST DAA_digestIssuer; + TPM_DIGEST DAA_digest_v0; + TPM_DIGEST DAA_digest_v1; + TPM_DIGEST DAA_rekey; + UINT32 DAA_count; +} TPM_DAA_TPM; + +/// +/// Part 2, section 22.5: TPM_DAA_CONTEXT +/// +typedef struct tdTPM_DAA_CONTEXT { + TPM_STRUCTURE_TAG tag; + TPM_DIGEST DAA_digestContext; + TPM_DIGEST DAA_digest; + TPM_DAA_CONTEXT_SEED DAA_contextSeed; + UINT8 DAA_scratch[256]; + UINT8 DAA_stage; +} TPM_DAA_CONTEXT; + +/// +/// Part 2, section 22.6: TPM_DAA_JOINDATA +/// +typedef struct tdTPM_DAA_JOINDATA { + UINT8 DAA_join_u0[128]; + UINT8 DAA_join_u1[138]; + TPM_DIGEST DAA_digest_n0; +} TPM_DAA_JOINDATA; + +/// +/// Part 2, section 22.8: TPM_DAA_BLOB +/// +typedef struct tdTPM_DAA_BLOB { + TPM_STRUCTURE_TAG tag; + TPM_RESOURCE_TYPE resourceType; + UINT8 label[16]; + TPM_DIGEST blobIntegrity; + UINT32 additionalSize; + UINT8 *additionalData; + UINT32 sensitiveSize; + UINT8 *sensitiveData; +} TPM_DAA_BLOB; + +/// +/// Part 2, section 22.9: TPM_DAA_SENSITIVE +/// +typedef struct tdTPM_DAA_SENSITIVE { + TPM_STRUCTURE_TAG tag; + UINT32 internalSize; + UINT8 *internalData; +} TPM_DAA_SENSITIVE; + + +// +// Part 2, section 23: Redirection +// + +/// +/// Part 2 section 23.1: TPM_REDIR_COMMAND +/// This section defines exactly one value but does not +/// give it a name. The definition of TPM_SetRedirection in Part3 +/// refers to exactly one name but does not give its value. We join +/// them here. +/// +#define TPM_REDIR_GPIO (0x00000001) + +/// +/// TPM Command Headers defined in Part 3 +/// +typedef struct tdTPM_RQU_COMMAND_HDR { + TPM_STRUCTURE_TAG tag; + UINT32 paramSize; + TPM_COMMAND_CODE ordinal; +} TPM_RQU_COMMAND_HDR; + +/// +/// TPM Response Headers defined in Part 3 +/// +typedef struct tdTPM_RSP_COMMAND_HDR { + TPM_STRUCTURE_TAG tag; + UINT32 paramSize; + TPM_RESULT returnCode; +} TPM_RSP_COMMAND_HDR; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm20.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm20.h new file mode 100644 index 0000000000..39332b15e8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm20.h @@ -0,0 +1,1814 @@ +/** @file + TPM2.0 Specification data structures + (Trusted Platform Module Library Specification, Family "2.0", Level 00, Revision 00.96, + @http://www.trustedcomputinggroup.org/resources/tpm_library_specification) + + Check http://trustedcomputinggroup.org for latest specification updates. + +Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _TPM20_H_ +#define _TPM20_H_ + +#include + +#pragma pack (1) + +// Annex A Algorithm Constants + +// Table 205 - Defines for SHA1 Hash Values +#define SHA1_DIGEST_SIZE 20 +#define SHA1_BLOCK_SIZE 64 + +// Table 206 - Defines for SHA256 Hash Values +#define SHA256_DIGEST_SIZE 32 +#define SHA256_BLOCK_SIZE 64 + +// Table 207 - Defines for SHA384 Hash Values +#define SHA384_DIGEST_SIZE 48 +#define SHA384_BLOCK_SIZE 128 + +// Table 208 - Defines for SHA512 Hash Values +#define SHA512_DIGEST_SIZE 64 +#define SHA512_BLOCK_SIZE 128 + +// Table 209 - Defines for SM3_256 Hash Values +#define SM3_256_DIGEST_SIZE 32 +#define SM3_256_BLOCK_SIZE 64 + +// Table 210 - Defines for Architectural Limits Values +#define MAX_SESSION_NUMBER 3 + +// Annex B Implementation Definitions + +// Table 211 - Defines for Logic Values +#define YES 1 +#define NO 0 +#define SET 1 +#define CLEAR 0 + +// Table 215 - Defines for RSA Algorithm Constants +#define MAX_RSA_KEY_BITS 2048 +#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8) + +// Table 216 - Defines for ECC Algorithm Constants +#define MAX_ECC_KEY_BITS 256 +#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8) + +// Table 217 - Defines for AES Algorithm Constants +#define MAX_AES_KEY_BITS 128 +#define MAX_AES_BLOCK_SIZE_BYTES 16 +#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8) + +// Table 218 - Defines for SM4 Algorithm Constants +#define MAX_SM4_KEY_BITS 128 +#define MAX_SM4_BLOCK_SIZE_BYTES 16 +#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8) + +// Table 219 - Defines for Symmetric Algorithm Constants +#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS +#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES +#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES + +// Table 220 - Defines for Implementation Values +typedef UINT16 BSIZE; +#define BUFFER_ALIGNMENT 4 +#define IMPLEMENTATION_PCR 24 +#define PLATFORM_PCR 24 +#define DRTM_PCR 17 +#define NUM_LOCALITIES 5 +#define MAX_HANDLE_NUM 3 +#define MAX_ACTIVE_SESSIONS 64 +typedef UINT16 CONTEXT_SLOT; +typedef UINT64 CONTEXT_COUNTER; +#define MAX_LOADED_SESSIONS 3 +#define MAX_SESSION_NUM 3 +#define MAX_LOADED_OBJECTS 3 +#define MIN_EVICT_OBJECTS 2 +#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8) +#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8) +#define NUM_POLICY_PCR_GROUP 1 +#define NUM_AUTHVALUE_PCR_GROUP 1 +#define MAX_CONTEXT_SIZE 4000 +#define MAX_DIGEST_BUFFER 1024 +#define MAX_NV_INDEX_SIZE 1024 +#define MAX_CAP_BUFFER 1024 +#define NV_MEMORY_SIZE 16384 +#define NUM_STATIC_PCR 16 +#define MAX_ALG_LIST_SIZE 64 +#define TIMER_PRESCALE 100000 +#define PRIMARY_SEED_SIZE 32 +#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES +#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS +#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8) +#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256 +#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE +#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE +#define NV_CLOCK_UPDATE_INTERVAL 12 +#define NUM_POLICY_PCR 1 +#define MAX_COMMAND_SIZE 4096 +#define MAX_RESPONSE_SIZE 4096 +#define ORDERLY_BITS 8 +#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1) +#define ALG_ID_FIRST TPM_ALG_FIRST +#define ALG_ID_LAST TPM_ALG_LAST +#define MAX_SYM_DATA 128 +#define MAX_RNG_ENTROPY_SIZE 64 +#define RAM_INDEX_SPACE 512 +#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001 +#define CRT_FORMAT_RSA YES +#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2)) + +// Capability related MAX_ value +#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32)) +#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY)) +#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE)) +#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC)) +#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY)) +#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT)) +#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE)) + +// +// Always set 5 here, because we want to support all hash algo in BIOS. +// +#define HASH_COUNT 5 + +// 5 Base Types + +// Table 3 - Definition of Base Types +typedef UINT8 BYTE; + +// Table 4 - Definition of Types for Documentation Clarity +// +// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue) +// +//typedef UINT32 TPM_ALGORITHM_ID; +//typedef UINT32 TPM_MODIFIER_INDICATOR; +typedef UINT32 TPM_AUTHORIZATION_SIZE; +typedef UINT32 TPM_PARAMETER_SIZE; +typedef UINT16 TPM_KEY_SIZE; +typedef UINT16 TPM_KEY_BITS; + +// 6 Constants + +// Table 6 - TPM_GENERATED Constants +typedef UINT32 TPM_GENERATED; +#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347) + +// Table 7 - TPM_ALG_ID Constants +typedef UINT16 TPM_ALG_ID; +// +// NOTE: Comment some algo which has same name as TPM1.2 (value is same, so not runtime issue) +// +#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000) +#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001) +//#define TPM_ALG_RSA (TPM_ALG_ID)(0x0001) +//#define TPM_ALG_SHA (TPM_ALG_ID)(0x0004) +#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004) +//#define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005) +#define TPM_ALG_AES (TPM_ALG_ID)(0x0006) +//#define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007) +#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008) +//#define TPM_ALG_XOR (TPM_ALG_ID)(0x000A) +#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B) +#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C) +#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D) +#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010) +#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012) +#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013) +#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014) +#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015) +#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016) +#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017) +#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018) +#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019) +#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A) +#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B) +#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C) +#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D) +#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020) +#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021) +#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022) +#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023) +#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025) +#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040) +#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041) +#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042) +#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043) +#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044) +#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044) + +// Table 8 - TPM_ECC_CURVE Constants +typedef UINT16 TPM_ECC_CURVE; +#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000) +#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001) +#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002) +#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003) +#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004) +#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005) +#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010) +#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011) +#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020) + +// Table 11 - TPM_CC Constants (Numeric Order) +typedef UINT32 TPM_CC; +#define TPM_CC_FIRST (TPM_CC)(0x0000011F) +#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F) +#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F) +#define TPM_CC_EvictControl (TPM_CC)(0x00000120) +#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121) +#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122) +#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124) +#define TPM_CC_ChangePPS (TPM_CC)(0x00000125) +#define TPM_CC_Clear (TPM_CC)(0x00000126) +#define TPM_CC_ClearControl (TPM_CC)(0x00000127) +#define TPM_CC_ClockSet (TPM_CC)(0x00000128) +#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129) +#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A) +#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B) +#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C) +#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D) +#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E) +#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F) +#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130) +#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131) +#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132) +#define TPM_CC_PP_LAST (TPM_CC)(0x00000132) +#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133) +#define TPM_CC_NV_Increment (TPM_CC)(0x00000134) +#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135) +#define TPM_CC_NV_Extend (TPM_CC)(0x00000136) +#define TPM_CC_NV_Write (TPM_CC)(0x00000137) +#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138) +#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139) +#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A) +#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B) +#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C) +#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D) +#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E) +#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F) +#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140) +#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141) +#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142) +#define TPM_CC_SelfTest (TPM_CC)(0x00000143) +#define TPM_CC_Startup (TPM_CC)(0x00000144) +#define TPM_CC_Shutdown (TPM_CC)(0x00000145) +#define TPM_CC_StirRandom (TPM_CC)(0x00000146) +#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147) +#define TPM_CC_Certify (TPM_CC)(0x00000148) +#define TPM_CC_PolicyNV (TPM_CC)(0x00000149) +#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A) +#define TPM_CC_Duplicate (TPM_CC)(0x0000014B) +#define TPM_CC_GetTime (TPM_CC)(0x0000014C) +#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D) +#define TPM_CC_NV_Read (TPM_CC)(0x0000014E) +#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F) +#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150) +#define TPM_CC_PolicySecret (TPM_CC)(0x00000151) +#define TPM_CC_Rewrap (TPM_CC)(0x00000152) +#define TPM_CC_Create (TPM_CC)(0x00000153) +#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154) +#define TPM_CC_HMAC (TPM_CC)(0x00000155) +#define TPM_CC_Import (TPM_CC)(0x00000156) +#define TPM_CC_Load (TPM_CC)(0x00000157) +#define TPM_CC_Quote (TPM_CC)(0x00000158) +#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159) +#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B) +#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C) +#define TPM_CC_Sign (TPM_CC)(0x0000015D) +#define TPM_CC_Unseal (TPM_CC)(0x0000015E) +#define TPM_CC_PolicySigned (TPM_CC)(0x00000160) +#define TPM_CC_ContextLoad (TPM_CC)(0x00000161) +#define TPM_CC_ContextSave (TPM_CC)(0x00000162) +#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163) +#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164) +#define TPM_CC_FlushContext (TPM_CC)(0x00000165) +#define TPM_CC_LoadExternal (TPM_CC)(0x00000167) +#define TPM_CC_MakeCredential (TPM_CC)(0x00000168) +#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169) +#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A) +#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B) +#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C) +#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D) +#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E) +#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F) +#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170) +#define TPM_CC_PolicyOR (TPM_CC)(0x00000171) +#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172) +#define TPM_CC_ReadPublic (TPM_CC)(0x00000173) +#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174) +#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176) +#define TPM_CC_VerifySignature (TPM_CC)(0x00000177) +#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178) +#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179) +#define TPM_CC_GetCapability (TPM_CC)(0x0000017A) +#define TPM_CC_GetRandom (TPM_CC)(0x0000017B) +#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C) +#define TPM_CC_Hash (TPM_CC)(0x0000017D) +#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E) +#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F) +#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180) +#define TPM_CC_ReadClock (TPM_CC)(0x00000181) +#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182) +#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183) +#define TPM_CC_NV_Certify (TPM_CC)(0x00000184) +#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185) +#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186) +#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187) +#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188) +#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189) +#define TPM_CC_TestParms (TPM_CC)(0x0000018A) +#define TPM_CC_Commit (TPM_CC)(0x0000018B) +#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C) +#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D) +#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E) +#define TPM_CC_LAST (TPM_CC)(0x0000018E) + +// Table 15 - TPM_RC Constants (Actions) +typedef UINT32 TPM_RC; +#define TPM_RC_SUCCESS (TPM_RC)(0x000) +#define TPM_RC_BAD_TAG (TPM_RC)(0x030) +#define RC_VER1 (TPM_RC)(0x100) +#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000) +#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001) +#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003) +#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B) +#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019) +#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020) +#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021) +#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024) +#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025) +#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026) +#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027) +#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028) +#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D) +#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E) +#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F) +#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030) +#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031) +#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042) +#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043) +#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044) +#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045) +#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046) +#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047) +#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048) +#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049) +#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A) +#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B) +#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C) +#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050) +#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051) +#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052) +#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053) +#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054) +#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055) +#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F) +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001) +#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004) +#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005) +#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007) +#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008) +#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009) +#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A) +#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B) +#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C) +#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D) +#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E) +#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F) +#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010) +#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012) +#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015) +#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016) +#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017) +#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018) +#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A) +#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B) +#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C) +#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D) +#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F) +#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020) +#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021) +#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022) +#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023) +#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 ) +#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025) +#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026) +#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027) +#define RC_WARN (TPM_RC)(0x900) +#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001) +#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002) +#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003) +#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004) +#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005) +#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006) +#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007) +#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008) +#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009) +#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A) +#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010) +#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011) +#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012) +#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013) +#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014) +#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015) +#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016) +#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018) +#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019) +#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A) +#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B) +#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C) +#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D) +#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E) +#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020) +#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021) +#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022) +#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023) +#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F) +#define TPM_RC_H (TPM_RC)(0x000) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_S (TPM_RC)(0x800) +#define TPM_RC_1 (TPM_RC)(0x100) +#define TPM_RC_2 (TPM_RC)(0x200) +#define TPM_RC_3 (TPM_RC)(0x300) +#define TPM_RC_4 (TPM_RC)(0x400) +#define TPM_RC_5 (TPM_RC)(0x500) +#define TPM_RC_6 (TPM_RC)(0x600) +#define TPM_RC_7 (TPM_RC)(0x700) +#define TPM_RC_8 (TPM_RC)(0x800) +#define TPM_RC_9 (TPM_RC)(0x900) +#define TPM_RC_A (TPM_RC)(0xA00) +#define TPM_RC_B (TPM_RC)(0xB00) +#define TPM_RC_C (TPM_RC)(0xC00) +#define TPM_RC_D (TPM_RC)(0xD00) +#define TPM_RC_E (TPM_RC)(0xE00) +#define TPM_RC_F (TPM_RC)(0xF00) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + +// Table 16 - TPM_CLOCK_ADJUST Constants +typedef INT8 TPM_CLOCK_ADJUST; +#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3) +#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2) +#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1) +#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0) +#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1) +#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2) +#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3) + +// Table 17 - TPM_EO Constants +typedef UINT16 TPM_EO; +#define TPM_EO_EQ (TPM_EO)(0x0000) +#define TPM_EO_NEQ (TPM_EO)(0x0001) +#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002) +#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003) +#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004) +#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005) +#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006) +#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007) +#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008) +#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009) +#define TPM_EO_BITSET (TPM_EO)(0x000A) +#define TPM_EO_BITCLEAR (TPM_EO)(0x000B) + +// Table 18 - TPM_ST Constants +typedef UINT16 TPM_ST; +#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4) +#define TPM_ST_NULL (TPM_ST)(0X8000) +#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) +#define TPM_ST_SESSIONS (TPM_ST)(0x8002) +#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014) +#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015) +#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016) +#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017) +#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018) +#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019) +#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A) +#define TPM_ST_CREATION (TPM_ST)(0x8021) +#define TPM_ST_VERIFIED (TPM_ST)(0x8022) +#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023) +#define TPM_ST_HASHCHECK (TPM_ST)(0x8024) +#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025) +#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029) + +// Table 19 - TPM_SU Constants +typedef UINT16 TPM_SU; +#define TPM_SU_CLEAR (TPM_SU)(0x0000) +#define TPM_SU_STATE (TPM_SU)(0x0001) + +// Table 20 - TPM_SE Constants +typedef UINT8 TPM_SE; +#define TPM_SE_HMAC (TPM_SE)(0x00) +#define TPM_SE_POLICY (TPM_SE)(0x01) +#define TPM_SE_TRIAL (TPM_SE)(0x03) + +// Table 21 - TPM_CAP Constants +typedef UINT32 TPM_CAP; +#define TPM_CAP_FIRST (TPM_CAP)(0x00000000) +#define TPM_CAP_ALGS (TPM_CAP)(0x00000000) +#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001) +#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002) +#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003) +#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004) +#define TPM_CAP_PCRS (TPM_CAP)(0x00000005) +#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006) +#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007) +#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008) +#define TPM_CAP_LAST (TPM_CAP)(0x00000008) +#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100) + +// Table 22 - TPM_PT Constants +typedef UINT32 TPM_PT; +#define TPM_PT_NONE (TPM_PT)(0x00000000) +#define PT_GROUP (TPM_PT)(0x00000100) +#define PT_FIXED (TPM_PT)(PT_GROUP * 1) +#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0) +#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1) +#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2) +#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3) +#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4) +#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5) +#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6) +#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7) +#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8) +#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9) +#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10) +#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11) +#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12) +#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13) +#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14) +#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15) +#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16) +#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17) +#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18) +#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19) +#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20) +#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22) +#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23) +#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24) +#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25) +#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26) +#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27) +#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28) +#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29) +#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30) +#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31) +#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32) +#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33) +#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34) +#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35) +#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36) +#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37) +#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38) +#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39) +#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40) +#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41) +#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42) +#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43) +#define PT_VAR (TPM_PT)(PT_GROUP * 2) +#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0) +#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1) +#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2) +#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3) +#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4) +#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5) +#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6) +#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7) +#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8) +#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9) +#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10) +#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11) +#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12) +#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13) +#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14) +#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15) +#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16) +#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17) +#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18) +#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19) +#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20) + +// Table 23 - TPM_PT_PCR Constants +typedef UINT32 TPM_PT_PCR; +#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000) +#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000) +#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001) +#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002) +#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003) +#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004) +#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005) +#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006) +#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007) +#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008) +#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009) +#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A) +#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011) +#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012) +#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013) +#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014) +#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014) + +// Table 24 - TPM_PS Constants +typedef UINT32 TPM_PS; +#define TPM_PS_MAIN (TPM_PS)(0x00000000) +#define TPM_PS_PC (TPM_PS)(0x00000001) +#define TPM_PS_PDA (TPM_PS)(0x00000002) +#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003) +#define TPM_PS_SERVER (TPM_PS)(0x00000004) +#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005) +#define TPM_PS_TSS (TPM_PS)(0x00000006) +#define TPM_PS_STORAGE (TPM_PS)(0x00000007) +#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008) +#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009) +#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A) +#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B) +#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C) +#define TPM_PS_TNC (TPM_PS)(0x0000000D) +#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E) +#define TPM_PS_TC (TPM_PS)(0x0000000F) + +// 7 Handles + +// Table 25 - Handles Types +// +// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue) +// +//typedef UINT32 TPM_HANDLE; + +// Table 26 - TPM_HT Constants +typedef UINT8 TPM_HT; +#define TPM_HT_PCR (TPM_HT)(0x00) +#define TPM_HT_NV_INDEX (TPM_HT)(0x01) +#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02) +#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02) +#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03) +#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03) +#define TPM_HT_PERMANENT (TPM_HT)(0x40) +#define TPM_HT_TRANSIENT (TPM_HT)(0x80) +#define TPM_HT_PERSISTENT (TPM_HT)(0x81) + +// Table 27 - TPM_RH Constants +typedef UINT32 TPM_RH; +#define TPM_RH_FIRST (TPM_RH)(0x40000000) +#define TPM_RH_SRK (TPM_RH)(0x40000000) +#define TPM_RH_OWNER (TPM_RH)(0x40000001) +#define TPM_RH_REVOKE (TPM_RH)(0x40000002) +#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003) +#define TPM_RH_OPERATOR (TPM_RH)(0x40000004) +#define TPM_RH_ADMIN (TPM_RH)(0x40000005) +#define TPM_RH_EK (TPM_RH)(0x40000006) +#define TPM_RH_NULL (TPM_RH)(0x40000007) +#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008) +#define TPM_RS_PW (TPM_RH)(0x40000009) +#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A) +#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B) +#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C) +#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D) +#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010) +#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F) +#define TPM_RH_LAST (TPM_RH)(0x4000010F) + +// Table 28 - TPM_HC Constants +typedef TPM_HANDLE TPM_HC; +#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF) +#define HR_RANGE_MASK (TPM_HC)(0xFF000000) +#define HR_SHIFT (TPM_HC)(24) +#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT) +#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT) +#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT) +#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT) +#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT) +#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT) +#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT) +#define PCR_FIRST (TPM_HC)(HR_PCR + 0) +#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1) +#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0) +#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1) +#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST) +#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST) +#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0) +#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1) +#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0) +#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST) +#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST) +#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1) +#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0) +#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF) +#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000) +#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0) +#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF) +#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST) +#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST) + +// 8 Attribute Structures + +// Table 29 - TPMA_ALGORITHM Bits +typedef struct { + UINT32 asymmetric : 1; + UINT32 symmetric : 1; + UINT32 hash : 1; + UINT32 object : 1; + UINT32 reserved4_7 : 4; + UINT32 signing : 1; + UINT32 encrypting : 1; + UINT32 method : 1; + UINT32 reserved11_31 : 21; +} TPMA_ALGORITHM; + +// Table 30 - TPMA_OBJECT Bits +typedef struct { + UINT32 reserved1 : 1; + UINT32 fixedTPM : 1; + UINT32 stClear : 1; + UINT32 reserved4 : 1; + UINT32 fixedParent : 1; + UINT32 sensitiveDataOrigin : 1; + UINT32 userWithAuth : 1; + UINT32 adminWithPolicy : 1; + UINT32 reserved8_9 : 2; + UINT32 noDA : 1; + UINT32 encryptedDuplication : 1; + UINT32 reserved12_15 : 4; + UINT32 restricted : 1; + UINT32 decrypt : 1; + UINT32 sign : 1; + UINT32 reserved19_31 : 13; +} TPMA_OBJECT; + +// Table 31 - TPMA_SESSION Bits +typedef struct { + UINT8 continueSession : 1; + UINT8 auditExclusive : 1; + UINT8 auditReset : 1; + UINT8 reserved3_4 : 2; + UINT8 decrypt : 1; + UINT8 encrypt : 1; + UINT8 audit : 1; +} TPMA_SESSION; + +// Table 32 - TPMA_LOCALITY Bits +// +// NOTE: Use low case here to resolve conflict +// +typedef struct { + UINT8 locZero : 1; + UINT8 locOne : 1; + UINT8 locTwo : 1; + UINT8 locThree : 1; + UINT8 locFour : 1; + UINT8 Extended : 3; +} TPMA_LOCALITY; + +// Table 33 - TPMA_PERMANENT Bits +typedef struct { + UINT32 ownerAuthSet : 1; + UINT32 endorsementAuthSet : 1; + UINT32 lockoutAuthSet : 1; + UINT32 reserved3_7 : 5; + UINT32 disableClear : 1; + UINT32 inLockout : 1; + UINT32 tpmGeneratedEPS : 1; + UINT32 reserved11_31 : 21; +} TPMA_PERMANENT; + +// Table 34 - TPMA_STARTUP_CLEAR Bits +typedef struct { + UINT32 phEnable : 1; + UINT32 shEnable : 1; + UINT32 ehEnable : 1; + UINT32 reserved3_30 : 28; + UINT32 orderly : 1; +} TPMA_STARTUP_CLEAR; + +// Table 35 - TPMA_MEMORY Bits +typedef struct { + UINT32 sharedRAM : 1; + UINT32 sharedNV : 1; + UINT32 objectCopiedToRam : 1; + UINT32 reserved3_31 : 29; +} TPMA_MEMORY; + +// Table 36 - TPMA_CC Bits +typedef struct { + UINT32 commandIndex : 16; + UINT32 reserved16_21 : 6; + UINT32 nv : 1; + UINT32 extensive : 1; + UINT32 flushed : 1; + UINT32 cHandles : 3; + UINT32 rHandle : 1; + UINT32 V : 1; + UINT32 Res : 2; +} TPMA_CC; + +// 9 Interface Types + +// Table 37 - TPMI_YES_NO Type +typedef BYTE TPMI_YES_NO; + +// Table 38 - TPMI_DH_OBJECT Type +typedef TPM_HANDLE TPMI_DH_OBJECT; + +// Table 39 - TPMI_DH_PERSISTENT Type +typedef TPM_HANDLE TPMI_DH_PERSISTENT; + +// Table 40 - TPMI_DH_ENTITY Type +typedef TPM_HANDLE TPMI_DH_ENTITY; + +// Table 41 - TPMI_DH_PCR Type +typedef TPM_HANDLE TPMI_DH_PCR; + +// Table 42 - TPMI_SH_AUTH_SESSION Type +typedef TPM_HANDLE TPMI_SH_AUTH_SESSION; + +// Table 43 - TPMI_SH_HMAC Type +typedef TPM_HANDLE TPMI_SH_HMAC; + +// Table 44 - TPMI_SH_POLICY Type +typedef TPM_HANDLE TPMI_SH_POLICY; + +// Table 45 - TPMI_DH_CONTEXT Type +typedef TPM_HANDLE TPMI_DH_CONTEXT; + +// Table 46 - TPMI_RH_HIERARCHY Type +typedef TPM_HANDLE TPMI_RH_HIERARCHY; + +// Table 47 - TPMI_RH_HIERARCHY_AUTH Type +typedef TPM_HANDLE TPMI_RH_HIERARCHY_AUTH; + +// Table 48 - TPMI_RH_PLATFORM Type +typedef TPM_HANDLE TPMI_RH_PLATFORM; + +// Table 49 - TPMI_RH_OWNER Type +typedef TPM_HANDLE TPMI_RH_OWNER; + +// Table 50 - TPMI_RH_ENDORSEMENT Type +typedef TPM_HANDLE TPMI_RH_ENDORSEMENT; + +// Table 51 - TPMI_RH_PROVISION Type +typedef TPM_HANDLE TPMI_RH_PROVISION; + +// Table 52 - TPMI_RH_CLEAR Type +typedef TPM_HANDLE TPMI_RH_CLEAR; + +// Table 53 - TPMI_RH_NV_AUTH Type +typedef TPM_HANDLE TPMI_RH_NV_AUTH; + +// Table 54 - TPMI_RH_LOCKOUT Type +typedef TPM_HANDLE TPMI_RH_LOCKOUT; + +// Table 55 - TPMI_RH_NV_INDEX Type +typedef TPM_HANDLE TPMI_RH_NV_INDEX; + +// Table 56 - TPMI_ALG_HASH Type +typedef TPM_ALG_ID TPMI_ALG_HASH; + +// Table 57 - TPMI_ALG_ASYM Type +typedef TPM_ALG_ID TPMI_ALG_ASYM; + +// Table 58 - TPMI_ALG_SYM Type +typedef TPM_ALG_ID TPMI_ALG_SYM; + +// Table 59 - TPMI_ALG_SYM_OBJECT Type +typedef TPM_ALG_ID TPMI_ALG_SYM_OBJECT; + +// Table 60 - TPMI_ALG_SYM_MODE Type +typedef TPM_ALG_ID TPMI_ALG_SYM_MODE; + +// Table 61 - TPMI_ALG_KDF Type +typedef TPM_ALG_ID TPMI_ALG_KDF; + +// Table 62 - TPMI_ALG_SIG_SCHEME Type +typedef TPM_ALG_ID TPMI_ALG_SIG_SCHEME; + +// Table 63 - TPMI_ECC_KEY_EXCHANGE Type +typedef TPM_ALG_ID TPMI_ECC_KEY_EXCHANGE; + +// Table 64 - TPMI_ST_COMMAND_TAG Type +typedef TPM_ST TPMI_ST_COMMAND_TAG; + +// 10 Structure Definitions + +// Table 65 - TPMS_ALGORITHM_DESCRIPTION Structure +typedef struct { + TPM_ALG_ID alg; + TPMA_ALGORITHM attributes; +} TPMS_ALGORITHM_DESCRIPTION; + +// Table 66 - TPMU_HA Union +typedef union { + BYTE sha1[SHA1_DIGEST_SIZE]; + BYTE sha256[SHA256_DIGEST_SIZE]; + BYTE sm3_256[SM3_256_DIGEST_SIZE]; + BYTE sha384[SHA384_DIGEST_SIZE]; + BYTE sha512[SHA512_DIGEST_SIZE]; +} TPMU_HA; + +// Table 67 - TPMT_HA Structure +typedef struct { + TPMI_ALG_HASH hashAlg; + TPMU_HA digest; +} TPMT_HA; + +// Table 68 - TPM2B_DIGEST Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(TPMU_HA)]; +} TPM2B_DIGEST; + +// Table 69 - TPM2B_DATA Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(TPMT_HA)]; +} TPM2B_DATA; + +// Table 70 - TPM2B_NONCE Types +typedef TPM2B_DIGEST TPM2B_NONCE; + +// Table 71 - TPM2B_AUTH Types +typedef TPM2B_DIGEST TPM2B_AUTH; + +// Table 72 - TPM2B_OPERAND Types +typedef TPM2B_DIGEST TPM2B_OPERAND; + +// Table 73 - TPM2B_EVENT Structure +typedef struct { + UINT16 size; + BYTE buffer[1024]; +} TPM2B_EVENT; + +// Table 74 - TPM2B_MAX_BUFFER Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_DIGEST_BUFFER]; +} TPM2B_MAX_BUFFER; + +// Table 75 - TPM2B_MAX_NV_BUFFER Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_NV_INDEX_SIZE]; +} TPM2B_MAX_NV_BUFFER; + +// Table 76 - TPM2B_TIMEOUT Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(UINT64)]; +} TPM2B_TIMEOUT; + +// Table 77 -- TPM2B_IV Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_SYM_BLOCK_SIZE]; +} TPM2B_IV; + +// Table 78 - TPMU_NAME Union +typedef union { + TPMT_HA digest; + TPM_HANDLE handle; +} TPMU_NAME; + +// Table 79 - TPM2B_NAME Structure +typedef struct { + UINT16 size; + BYTE name[sizeof(TPMU_NAME)]; +} TPM2B_NAME; + +// Table 80 - TPMS_PCR_SELECT Structure +typedef struct { + UINT8 sizeofSelect; + BYTE pcrSelect[PCR_SELECT_MAX]; +} TPMS_PCR_SELECT; + +// Table 81 - TPMS_PCR_SELECTION Structure +typedef struct { + TPMI_ALG_HASH hash; + UINT8 sizeofSelect; + BYTE pcrSelect[PCR_SELECT_MAX]; +} TPMS_PCR_SELECTION; + +// Table 84 - TPMT_TK_CREATION Structure +typedef struct { + TPM_ST tag; + TPMI_RH_HIERARCHY hierarchy; + TPM2B_DIGEST digest; +} TPMT_TK_CREATION; + +// Table 85 - TPMT_TK_VERIFIED Structure +typedef struct { + TPM_ST tag; + TPMI_RH_HIERARCHY hierarchy; + TPM2B_DIGEST digest; +} TPMT_TK_VERIFIED; + +// Table 86 - TPMT_TK_AUTH Structure +typedef struct { + TPM_ST tag; + TPMI_RH_HIERARCHY hierarchy; + TPM2B_DIGEST digest; +} TPMT_TK_AUTH; + +// Table 87 - TPMT_TK_HASHCHECK Structure +typedef struct { + TPM_ST tag; + TPMI_RH_HIERARCHY hierarchy; + TPM2B_DIGEST digest; +} TPMT_TK_HASHCHECK; + +// Table 88 - TPMS_ALG_PROPERTY Structure +typedef struct { + TPM_ALG_ID alg; + TPMA_ALGORITHM algProperties; +} TPMS_ALG_PROPERTY; + +// Table 89 - TPMS_TAGGED_PROPERTY Structure +typedef struct { + TPM_PT property; + UINT32 value; +} TPMS_TAGGED_PROPERTY; + +// Table 90 - TPMS_TAGGED_PCR_SELECT Structure +typedef struct { + TPM_PT tag; + UINT8 sizeofSelect; + BYTE pcrSelect[PCR_SELECT_MAX]; +} TPMS_TAGGED_PCR_SELECT; + +// Table 91 - TPML_CC Structure +typedef struct { + UINT32 count; + TPM_CC commandCodes[MAX_CAP_CC]; +} TPML_CC; + +// Table 92 - TPML_CCA Structure +typedef struct { + UINT32 count; + TPMA_CC commandAttributes[MAX_CAP_CC]; +} TPML_CCA; + +// Table 93 - TPML_ALG Structure +typedef struct { + UINT32 count; + TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE]; +} TPML_ALG; + +// Table 94 - TPML_HANDLE Structure +typedef struct { + UINT32 count; + TPM_HANDLE handle[MAX_CAP_HANDLES]; +} TPML_HANDLE; + +// Table 95 - TPML_DIGEST Structure +typedef struct { + UINT32 count; + TPM2B_DIGEST digests[8]; +} TPML_DIGEST; + +// Table 96 -- TPML_DIGEST_VALUES Structure +typedef struct { + UINT32 count; + TPMT_HA digests[HASH_COUNT]; +} TPML_DIGEST_VALUES; + +// Table 97 - TPM2B_DIGEST_VALUES Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(TPML_DIGEST_VALUES)]; +} TPM2B_DIGEST_VALUES; + +// Table 98 - TPML_PCR_SELECTION Structure +typedef struct { + UINT32 count; + TPMS_PCR_SELECTION pcrSelections[HASH_COUNT]; +} TPML_PCR_SELECTION; + +// Table 99 - TPML_ALG_PROPERTY Structure +typedef struct { + UINT32 count; + TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS]; +} TPML_ALG_PROPERTY; + +// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure +typedef struct { + UINT32 count; + TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; +} TPML_TAGGED_TPM_PROPERTY; + +// Table 101 - TPML_TAGGED_PCR_PROPERTY Structure +typedef struct { + UINT32 count; + TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES]; +} TPML_TAGGED_PCR_PROPERTY; + +// Table 102 - TPML_ECC_CURVE Structure +typedef struct { + UINT32 count; + TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES]; +} TPML_ECC_CURVE; + +// Table 103 - TPMU_CAPABILITIES Union +typedef union { + TPML_ALG_PROPERTY algorithms; + TPML_HANDLE handles; + TPML_CCA command; + TPML_CC ppCommands; + TPML_CC auditCommands; + TPML_PCR_SELECTION assignedPCR; + TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_TAGGED_PCR_PROPERTY pcrProperties; + TPML_ECC_CURVE eccCurves; +} TPMU_CAPABILITIES; + +// Table 104 - TPMS_CAPABILITY_DATA Structure +typedef struct { + TPM_CAP capability; + TPMU_CAPABILITIES data; +} TPMS_CAPABILITY_DATA; + +// Table 105 - TPMS_CLOCK_INFO Structure +typedef struct { + UINT64 clock; + UINT32 resetCount; + UINT32 restartCount; + TPMI_YES_NO safe; +} TPMS_CLOCK_INFO; + +// Table 106 - TPMS_TIME_INFO Structure +typedef struct { + UINT64 time; + TPMS_CLOCK_INFO clockInfo; +} TPMS_TIME_INFO; + +// Table 107 - TPMS_TIME_ATTEST_INFO Structure +typedef struct { + TPMS_TIME_INFO time; + UINT64 firmwareVersion; +} TPMS_TIME_ATTEST_INFO; + +// Table 108 - TPMS_CERTIFY_INFO Structure +typedef struct { + TPM2B_NAME name; + TPM2B_NAME qualifiedName; +} TPMS_CERTIFY_INFO; + +// Table 109 - TPMS_QUOTE_INFO Structure +typedef struct { + TPML_PCR_SELECTION pcrSelect; + TPM2B_DIGEST pcrDigest; +} TPMS_QUOTE_INFO; + +// Table 110 - TPMS_COMMAND_AUDIT_INFO Structure +typedef struct { + UINT64 auditCounter; + TPM_ALG_ID digestAlg; + TPM2B_DIGEST auditDigest; + TPM2B_DIGEST commandDigest; +} TPMS_COMMAND_AUDIT_INFO; + +// Table 111 - TPMS_SESSION_AUDIT_INFO Structure +typedef struct { + TPMI_YES_NO exclusiveSession; + TPM2B_DIGEST sessionDigest; +} TPMS_SESSION_AUDIT_INFO; + +// Table 112 - TPMS_CREATION_INFO Structure +typedef struct { + TPM2B_NAME objectName; + TPM2B_DIGEST creationHash; +} TPMS_CREATION_INFO; + +// Table 113 - TPMS_NV_CERTIFY_INFO Structure +typedef struct { + TPM2B_NAME indexName; + UINT16 offset; + TPM2B_MAX_NV_BUFFER nvContents; +} TPMS_NV_CERTIFY_INFO; + +// Table 114 - TPMI_ST_ATTEST Type +typedef TPM_ST TPMI_ST_ATTEST; + +// Table 115 - TPMU_ATTEST Union +typedef union { + TPMS_CERTIFY_INFO certify; + TPMS_CREATION_INFO creation; + TPMS_QUOTE_INFO quote; + TPMS_COMMAND_AUDIT_INFO commandAudit; + TPMS_SESSION_AUDIT_INFO sessionAudit; + TPMS_TIME_ATTEST_INFO time; + TPMS_NV_CERTIFY_INFO nv; +} TPMU_ATTEST; + +// Table 116 - TPMS_ATTEST Structure +typedef struct { + TPM_GENERATED magic; + TPMI_ST_ATTEST type; + TPM2B_NAME qualifiedSigner; + TPM2B_DATA extraData; + TPMS_CLOCK_INFO clockInfo; + UINT64 firmwareVersion; + TPMU_ATTEST attested; +} TPMS_ATTEST; + +// Table 117 - TPM2B_ATTEST Structure +typedef struct { + UINT16 size; + BYTE attestationData[sizeof(TPMS_ATTEST)]; +} TPM2B_ATTEST; + +// Table 118 - TPMS_AUTH_COMMAND Structure +typedef struct { + TPMI_SH_AUTH_SESSION sessionHandle; + TPM2B_NONCE nonce; + TPMA_SESSION sessionAttributes; + TPM2B_AUTH hmac; +} TPMS_AUTH_COMMAND; + +// Table 119 - TPMS_AUTH_RESPONSE Structure +typedef struct { + TPM2B_NONCE nonce; + TPMA_SESSION sessionAttributes; + TPM2B_AUTH hmac; +} TPMS_AUTH_RESPONSE; + +// 11 Algorithm Parameters and Structures + +// Table 120 - TPMI_AES_KEY_BITS Type +typedef TPM_KEY_BITS TPMI_AES_KEY_BITS; + +// Table 121 - TPMI_SM4_KEY_BITS Type +typedef TPM_KEY_BITS TPMI_SM4_KEY_BITS; + +// Table 122 - TPMU_SYM_KEY_BITS Union +typedef union { + TPMI_AES_KEY_BITS aes; + TPMI_SM4_KEY_BITS SM4; + TPM_KEY_BITS sym; + TPMI_ALG_HASH xor; +} TPMU_SYM_KEY_BITS; + +// Table 123 - TPMU_SYM_MODE Union +typedef union { + TPMI_ALG_SYM_MODE aes; + TPMI_ALG_SYM_MODE SM4; + TPMI_ALG_SYM_MODE sym; +} TPMU_SYM_MODE; + +// Table 125 - TPMT_SYM_DEF Structure +typedef struct { + TPMI_ALG_SYM algorithm; + TPMU_SYM_KEY_BITS keyBits; + TPMU_SYM_MODE mode; +} TPMT_SYM_DEF; + +// Table 126 - TPMT_SYM_DEF_OBJECT Structure +typedef struct { + TPMI_ALG_SYM_OBJECT algorithm; + TPMU_SYM_KEY_BITS keyBits; + TPMU_SYM_MODE mode; +} TPMT_SYM_DEF_OBJECT; + +// Table 127 - TPM2B_SYM_KEY Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_SYM_KEY_BYTES]; +} TPM2B_SYM_KEY; + +// Table 128 - TPMS_SYMCIPHER_PARMS Structure +typedef struct { + TPMT_SYM_DEF_OBJECT sym; +} TPMS_SYMCIPHER_PARMS; + +// Table 129 - TPM2B_SENSITIVE_DATA Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_SYM_DATA]; +} TPM2B_SENSITIVE_DATA; + +// Table 130 - TPMS_SENSITIVE_CREATE Structure +typedef struct { + TPM2B_AUTH userAuth; + TPM2B_SENSITIVE_DATA data; +} TPMS_SENSITIVE_CREATE; + +// Table 131 - TPM2B_SENSITIVE_CREATE Structure +typedef struct { + UINT16 size; + TPMS_SENSITIVE_CREATE sensitive; +} TPM2B_SENSITIVE_CREATE; + +// Table 132 - TPMS_SCHEME_SIGHASH Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_SIGHASH; + +// Table 133 - TPMI_ALG_KEYEDHASH_SCHEME Type +typedef TPM_ALG_ID TPMI_ALG_KEYEDHASH_SCHEME; + +// Table 134 - HMAC_SIG_SCHEME Types +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_HMAC; + +// Table 135 - TPMS_SCHEME_XOR Structure +typedef struct { + TPMI_ALG_HASH hashAlg; + TPMI_ALG_KDF kdf; +} TPMS_SCHEME_XOR; + +// Table 136 - TPMU_SCHEME_KEYEDHASH Union +typedef union { + TPMS_SCHEME_HMAC hmac; + TPMS_SCHEME_XOR xor; +} TPMU_SCHEME_KEYEDHASH; + +// Table 137 - TPMT_KEYEDHASH_SCHEME Structure +typedef struct { + TPMI_ALG_KEYEDHASH_SCHEME scheme; + TPMU_SCHEME_KEYEDHASH details; +} TPMT_KEYEDHASH_SCHEME; + +// Table 138 - RSA_SIG_SCHEMES Types +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSASSA; +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_RSAPSS; + +// Table 139 - ECC_SIG_SCHEMES Types +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECDSA; +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_SM2; +typedef TPMS_SCHEME_SIGHASH TPMS_SCHEME_ECSCHNORR; + +// Table 140 - TPMS_SCHEME_ECDAA Structure +typedef struct { + TPMI_ALG_HASH hashAlg; + UINT16 count; +} TPMS_SCHEME_ECDAA; + +// Table 141 - TPMU_SIG_SCHEME Union +typedef union { + TPMS_SCHEME_RSASSA rsassa; + TPMS_SCHEME_RSAPSS rsapss; + TPMS_SCHEME_ECDSA ecdsa; + TPMS_SCHEME_ECDAA ecdaa; + TPMS_SCHEME_ECSCHNORR ecSchnorr; + TPMS_SCHEME_HMAC hmac; + TPMS_SCHEME_SIGHASH any; +} TPMU_SIG_SCHEME; + +// Table 142 - TPMT_SIG_SCHEME Structure +typedef struct { + TPMI_ALG_SIG_SCHEME scheme; + TPMU_SIG_SCHEME details; +} TPMT_SIG_SCHEME; + +// Table 143 - TPMS_SCHEME_OAEP Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_OAEP; + +// Table 144 - TPMS_SCHEME_ECDH Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_ECDH; + +// Table 145 - TPMS_SCHEME_MGF1 Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_MGF1; + +// Table 146 - TPMS_SCHEME_KDF1_SP800_56a Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_KDF1_SP800_56a; + +// Table 147 - TPMS_SCHEME_KDF2 Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_KDF2; + +// Table 148 - TPMS_SCHEME_KDF1_SP800_108 Structure +typedef struct { + TPMI_ALG_HASH hashAlg; +} TPMS_SCHEME_KDF1_SP800_108; + +// Table 149 - TPMU_KDF_SCHEME Union +typedef union { + TPMS_SCHEME_MGF1 mgf1; + TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a; + TPMS_SCHEME_KDF2 kdf2; + TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108; +} TPMU_KDF_SCHEME; + +// Table 150 - TPMT_KDF_SCHEME Structure +typedef struct { + TPMI_ALG_KDF scheme; + TPMU_KDF_SCHEME details; +} TPMT_KDF_SCHEME; + +// Table 151 - TPMI_ALG_ASYM_SCHEME Type +typedef TPM_ALG_ID TPMI_ALG_ASYM_SCHEME; + +// Table 152 - TPMU_ASYM_SCHEME Union +typedef union { + TPMS_SCHEME_RSASSA rsassa; + TPMS_SCHEME_RSAPSS rsapss; + TPMS_SCHEME_OAEP oaep; + TPMS_SCHEME_ECDSA ecdsa; + TPMS_SCHEME_ECDAA ecdaa; + TPMS_SCHEME_ECSCHNORR ecSchnorr; + TPMS_SCHEME_SIGHASH anySig; +} TPMU_ASYM_SCHEME; + +// Table 153 - TPMT_ASYM_SCHEME Structure +typedef struct { + TPMI_ALG_ASYM_SCHEME scheme; + TPMU_ASYM_SCHEME details; +} TPMT_ASYM_SCHEME; + +// Table 154 - TPMI_ALG_RSA_SCHEME Type +typedef TPM_ALG_ID TPMI_ALG_RSA_SCHEME; + +// Table 155 - TPMT_RSA_SCHEME Structure +typedef struct { + TPMI_ALG_RSA_SCHEME scheme; + TPMU_ASYM_SCHEME details; +} TPMT_RSA_SCHEME; + +// Table 156 - TPMI_ALG_RSA_DECRYPT Type +typedef TPM_ALG_ID TPMI_ALG_RSA_DECRYPT; + +// Table 157 - TPMT_RSA_DECRYPT Structure +typedef struct { + TPMI_ALG_RSA_DECRYPT scheme; + TPMU_ASYM_SCHEME details; +} TPMT_RSA_DECRYPT; + +// Table 158 - TPM2B_PUBLIC_KEY_RSA Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_RSA_KEY_BYTES]; +} TPM2B_PUBLIC_KEY_RSA; + +// Table 159 - TPMI_RSA_KEY_BITS Type +typedef TPM_KEY_BITS TPMI_RSA_KEY_BITS; + +// Table 160 - TPM2B_PRIVATE_KEY_RSA Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_RSA_KEY_BYTES/2]; +} TPM2B_PRIVATE_KEY_RSA; + +// Table 161 - TPM2B_ECC_PARAMETER Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_ECC_KEY_BYTES]; +} TPM2B_ECC_PARAMETER; + +// Table 162 - TPMS_ECC_POINT Structure +typedef struct { + TPM2B_ECC_PARAMETER x; + TPM2B_ECC_PARAMETER y; +} TPMS_ECC_POINT; + +// Table 163 -- TPM2B_ECC_POINT Structure +typedef struct { + UINT16 size; + TPMS_ECC_POINT point; +} TPM2B_ECC_POINT; + +// Table 164 - TPMI_ALG_ECC_SCHEME Type +typedef TPM_ALG_ID TPMI_ALG_ECC_SCHEME; + +// Table 165 - TPMI_ECC_CURVE Type +typedef TPM_ECC_CURVE TPMI_ECC_CURVE; + +// Table 166 - TPMT_ECC_SCHEME Structure +typedef struct { + TPMI_ALG_ECC_SCHEME scheme; + TPMU_SIG_SCHEME details; +} TPMT_ECC_SCHEME; + +// Table 167 - TPMS_ALGORITHM_DETAIL_ECC Structure +typedef struct { + TPM_ECC_CURVE curveID; + UINT16 keySize; + TPMT_KDF_SCHEME kdf; + TPMT_ECC_SCHEME sign; + TPM2B_ECC_PARAMETER p; + TPM2B_ECC_PARAMETER a; + TPM2B_ECC_PARAMETER b; + TPM2B_ECC_PARAMETER gX; + TPM2B_ECC_PARAMETER gY; + TPM2B_ECC_PARAMETER n; + TPM2B_ECC_PARAMETER h; +} TPMS_ALGORITHM_DETAIL_ECC; + +// Table 168 - TPMS_SIGNATURE_RSASSA Structure +typedef struct { + TPMI_ALG_HASH hash; + TPM2B_PUBLIC_KEY_RSA sig; +} TPMS_SIGNATURE_RSASSA; + +// Table 169 - TPMS_SIGNATURE_RSAPSS Structure +typedef struct { + TPMI_ALG_HASH hash; + TPM2B_PUBLIC_KEY_RSA sig; +} TPMS_SIGNATURE_RSAPSS; + +// Table 170 - TPMS_SIGNATURE_ECDSA Structure +typedef struct { + TPMI_ALG_HASH hash; + TPM2B_ECC_PARAMETER signatureR; + TPM2B_ECC_PARAMETER signatureS; +} TPMS_SIGNATURE_ECDSA; + +// Table 171 - TPMU_SIGNATURE Union +typedef union { + TPMS_SIGNATURE_RSASSA rsassa; + TPMS_SIGNATURE_RSAPSS rsapss; + TPMS_SIGNATURE_ECDSA ecdsa; + TPMS_SIGNATURE_ECDSA sm2; + TPMS_SIGNATURE_ECDSA ecdaa; + TPMS_SIGNATURE_ECDSA ecschnorr; + TPMT_HA hmac; + TPMS_SCHEME_SIGHASH any; +} TPMU_SIGNATURE; + +// Table 172 - TPMT_SIGNATURE Structure +typedef struct { + TPMI_ALG_SIG_SCHEME sigAlg; + TPMU_SIGNATURE signature; +} TPMT_SIGNATURE; + +// Table 173 - TPMU_ENCRYPTED_SECRET Union +typedef union { + BYTE ecc[sizeof(TPMS_ECC_POINT)]; + BYTE rsa[MAX_RSA_KEY_BYTES]; + BYTE symmetric[sizeof(TPM2B_DIGEST)]; + BYTE keyedHash[sizeof(TPM2B_DIGEST)]; +} TPMU_ENCRYPTED_SECRET; + +// Table 174 - TPM2B_ENCRYPTED_SECRET Structure +typedef struct { + UINT16 size; + BYTE secret[sizeof(TPMU_ENCRYPTED_SECRET)]; +} TPM2B_ENCRYPTED_SECRET; + +// 12 Key/Object Complex + +// Table 175 - TPMI_ALG_PUBLIC Type +typedef TPM_ALG_ID TPMI_ALG_PUBLIC; + +// Table 176 - TPMU_PUBLIC_ID Union +typedef union { + TPM2B_DIGEST keyedHash; + TPM2B_DIGEST sym; + TPM2B_PUBLIC_KEY_RSA rsa; + TPMS_ECC_POINT ecc; +} TPMU_PUBLIC_ID; + +// Table 177 - TPMS_KEYEDHASH_PARMS Structure +typedef struct { + TPMT_KEYEDHASH_SCHEME scheme; +} TPMS_KEYEDHASH_PARMS; + +// Table 178 - TPMS_ASYM_PARMS Structure +typedef struct { + TPMT_SYM_DEF_OBJECT symmetric; + TPMT_ASYM_SCHEME scheme; +} TPMS_ASYM_PARMS; + +// Table 179 - TPMS_RSA_PARMS Structure +typedef struct { + TPMT_SYM_DEF_OBJECT symmetric; + TPMT_RSA_SCHEME scheme; + TPMI_RSA_KEY_BITS keyBits; + UINT32 exponent; +} TPMS_RSA_PARMS; + +// Table 180 - TPMS_ECC_PARMS Structure +typedef struct { + TPMT_SYM_DEF_OBJECT symmetric; + TPMT_ECC_SCHEME scheme; + TPMI_ECC_CURVE curveID; + TPMT_KDF_SCHEME kdf; +} TPMS_ECC_PARMS; + +// Table 181 - TPMU_PUBLIC_PARMS Union +typedef union { + TPMS_KEYEDHASH_PARMS keyedHashDetail; + TPMT_SYM_DEF_OBJECT symDetail; + TPMS_RSA_PARMS rsaDetail; + TPMS_ECC_PARMS eccDetail; + TPMS_ASYM_PARMS asymDetail; +} TPMU_PUBLIC_PARMS; + +// Table 182 - TPMT_PUBLIC_PARMS Structure +typedef struct { + TPMI_ALG_PUBLIC type; + TPMU_PUBLIC_PARMS parameters; +} TPMT_PUBLIC_PARMS; + +// Table 183 - TPMT_PUBLIC Structure +typedef struct { + TPMI_ALG_PUBLIC type; + TPMI_ALG_HASH nameAlg; + TPMA_OBJECT objectAttributes; + TPM2B_DIGEST authPolicy; + TPMU_PUBLIC_PARMS parameters; + TPMU_PUBLIC_ID unique; +} TPMT_PUBLIC; + +// Table 184 - TPM2B_PUBLIC Structure +typedef struct { + UINT16 size; + TPMT_PUBLIC publicArea; +} TPM2B_PUBLIC; + +// Table 185 - TPM2B_PRIVATE_VENDOR_SPECIFIC Structure +typedef struct { + UINT16 size; + BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES]; +} TPM2B_PRIVATE_VENDOR_SPECIFIC; + +// Table 186 - TPMU_SENSITIVE_COMPOSITE Union +typedef union { + TPM2B_PRIVATE_KEY_RSA rsa; + TPM2B_ECC_PARAMETER ecc; + TPM2B_SENSITIVE_DATA bits; + TPM2B_SYM_KEY sym; + TPM2B_PRIVATE_VENDOR_SPECIFIC any; +} TPMU_SENSITIVE_COMPOSITE; + +// Table 187 - TPMT_SENSITIVE Structure +typedef struct { + TPMI_ALG_PUBLIC sensitiveType; + TPM2B_AUTH authValue; + TPM2B_DIGEST seedValue; + TPMU_SENSITIVE_COMPOSITE sensitive; +} TPMT_SENSITIVE; + +// Table 188 - TPM2B_SENSITIVE Structure +typedef struct { + UINT16 size; + TPMT_SENSITIVE sensitiveArea; +} TPM2B_SENSITIVE; + +// Table 189 - _PRIVATE Structure +typedef struct { + TPM2B_DIGEST integrityOuter; + TPM2B_DIGEST integrityInner; + TPMT_SENSITIVE sensitive; +} _PRIVATE; + +// Table 190 - TPM2B_PRIVATE Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(_PRIVATE)]; +} TPM2B_PRIVATE; + +// Table 191 - _ID_OBJECT Structure +typedef struct { + TPM2B_DIGEST integrityHMAC; + TPM2B_DIGEST encIdentity; +} _ID_OBJECT; + +// Table 192 - TPM2B_ID_OBJECT Structure +typedef struct { + UINT16 size; + BYTE credential[sizeof(_ID_OBJECT)]; +} TPM2B_ID_OBJECT; + +// 13 NV Storage Structures + +// Table 193 - TPM_NV_INDEX Bits +// +// NOTE: Comment here to resolve conflict +// +//typedef struct { +// UINT32 index : 22; +// UINT32 space : 2; +// UINT32 RH_NV : 8; +//} TPM_NV_INDEX; + +// Table 195 - TPMA_NV Bits +typedef struct { + UINT32 TPMA_NV_PPWRITE : 1; + UINT32 TPMA_NV_OWNERWRITE : 1; + UINT32 TPMA_NV_AUTHWRITE : 1; + UINT32 TPMA_NV_POLICYWRITE : 1; + UINT32 TPMA_NV_COUNTER : 1; + UINT32 TPMA_NV_BITS : 1; + UINT32 TPMA_NV_EXTEND : 1; + UINT32 reserved7_9 : 3; + UINT32 TPMA_NV_POLICY_DELETE : 1; + UINT32 TPMA_NV_WRITELOCKED : 1; + UINT32 TPMA_NV_WRITEALL : 1; + UINT32 TPMA_NV_WRITEDEFINE : 1; + UINT32 TPMA_NV_WRITE_STCLEAR : 1; + UINT32 TPMA_NV_GLOBALLOCK : 1; + UINT32 TPMA_NV_PPREAD : 1; + UINT32 TPMA_NV_OWNERREAD : 1; + UINT32 TPMA_NV_AUTHREAD : 1; + UINT32 TPMA_NV_POLICYREAD : 1; + UINT32 reserved20_24 : 5; + UINT32 TPMA_NV_NO_DA : 1; + UINT32 TPMA_NV_ORDERLY : 1; + UINT32 TPMA_NV_CLEAR_STCLEAR : 1; + UINT32 TPMA_NV_READLOCKED : 1; + UINT32 TPMA_NV_WRITTEN : 1; + UINT32 TPMA_NV_PLATFORMCREATE : 1; + UINT32 TPMA_NV_READ_STCLEAR : 1; +} TPMA_NV; + +// Table 196 - TPMS_NV_PUBLIC Structure +typedef struct { + TPMI_RH_NV_INDEX nvIndex; + TPMI_ALG_HASH nameAlg; + TPMA_NV attributes; + TPM2B_DIGEST authPolicy; + UINT16 dataSize; +} TPMS_NV_PUBLIC; + +// Table 197 - TPM2B_NV_PUBLIC Structure +typedef struct { + UINT16 size; + TPMS_NV_PUBLIC nvPublic; +} TPM2B_NV_PUBLIC; + +// 14 Context Data + +// Table 198 - TPM2B_CONTEXT_SENSITIVE Structure +typedef struct { + UINT16 size; + BYTE buffer[MAX_CONTEXT_SIZE]; +} TPM2B_CONTEXT_SENSITIVE; + +// Table 199 - TPMS_CONTEXT_DATA Structure +typedef struct { + TPM2B_DIGEST integrity; + TPM2B_CONTEXT_SENSITIVE encrypted; +} TPMS_CONTEXT_DATA; + +// Table 200 - TPM2B_CONTEXT_DATA Structure +typedef struct { + UINT16 size; + BYTE buffer[sizeof(TPMS_CONTEXT_DATA)]; +} TPM2B_CONTEXT_DATA; + +// Table 201 - TPMS_CONTEXT Structure +typedef struct { + UINT64 sequence; + TPMI_DH_CONTEXT savedHandle; + TPMI_RH_HIERARCHY hierarchy; + TPM2B_CONTEXT_DATA contextBlob; +} TPMS_CONTEXT; + +// 15 Creation Data + +// Table 203 - TPMS_CREATION_DATA Structure +typedef struct { + TPML_PCR_SELECTION pcrSelect; + TPM2B_DIGEST pcrDigest; + TPMA_LOCALITY locality; + TPM_ALG_ID parentNameAlg; + TPM2B_NAME parentName; + TPM2B_NAME parentQualifiedName; + TPM2B_DATA outsideInfo; +} TPMS_CREATION_DATA; + +// Table 204 - TPM2B_CREATION_DATA Structure +typedef struct { + UINT16 size; + TPMS_CREATION_DATA creationData; +} TPM2B_CREATION_DATA; + + +// +// Command Header +// +typedef struct { + TPM_ST tag; + UINT32 paramSize; + TPM_CC commandCode; +} TPM2_COMMAND_HEADER; + +typedef struct { + TPM_ST tag; + UINT32 paramSize; + TPM_RC responseCode; +} TPM2_RESPONSE_HEADER; + +#pragma pack () + +// +// TCG Algorithm Registry +// +#define HASH_ALG_SHA1 0x00000001 +#define HASH_ALG_SHA256 0x00000002 +#define HASH_ALG_SHA384 0x00000004 +#define HASH_ALG_SHA512 0x00000008 +#define HASH_ALG_SM3_256 0x00000010 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm2Acpi.h new file mode 100644 index 0000000000..e6d0bda36a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Tpm2Acpi.h @@ -0,0 +1,66 @@ +/** @file + TPM2 ACPI table definition. + +Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TPM2_ACPI_H_ +#define _TPM2_ACPI_H_ + +#include + +#pragma pack (1) + +#define EFI_TPM2_ACPI_TABLE_REVISION_3 3 +#define EFI_TPM2_ACPI_TABLE_REVISION_4 4 +#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4 + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + // Flags field is replaced in version 4 and above + // BIT0~15: PlatformClass This field is only valid for version 4 and above + // BIT16~31: Reserved + UINT32 Flags; + UINT64 AddressOfControlArea; + UINT32 StartMethod; +//UINT8 PlatformSpecificParameters[]; // size up to 12 +//UINT32 Laml; // Optional +//UINT64 Lasa; // Optional +} EFI_TPM2_ACPI_TABLE; + +#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11 + +typedef struct { + UINT32 Reserved; + UINT32 Error; + UINT32 Cancel; + UINT32 Start; + UINT64 InterruptControl; + UINT32 CommandSize; + UINT64 Command; + UINT32 ResponseSize; + UINT64 Response; +} EFI_TPM2_ACPI_CONTROL_AREA; + +// +// Start Method Specific Parameters for ARM SMC Start Method (11) +// Refer to Table 9: Start Method Specific Parameters for ARM SMC +// +typedef struct { + UINT32 Interrupt; + UINT8 Flags; + UINT8 OperationFlags; + UINT8 Reserved[2]; + UINT32 SmcFunctionId; +} EFI_TPM2_ACPI_START_METHOD_SPECIFIC_PARAMETERS_ARM_SMC; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmPtp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmPtp.h new file mode 100644 index 0000000000..4481a0891b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmPtp.h @@ -0,0 +1,517 @@ +/** @file + Platform TPM Profile Specification definition for TPM2.0. + It covers both FIFO and CRB interface. + +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TPM_PTP_H_ +#define _TPM_PTP_H_ + +// +// PTP FIFO definition +// + +// +// Set structure alignment to 1-byte +// +#pragma pack (1) + +// +// Register set map as specified in PTP specification Chapter 5 +// +typedef struct { + /// + /// Used to gain ownership for this particular port. + /// + UINT8 Access; // 0 + UINT8 Reserved1[7]; // 1 + /// + /// Controls interrupts. + /// + UINT32 IntEnable; // 8 + /// + /// SIRQ vector to be used by the TPM. + /// + UINT8 IntVector; // 0ch + UINT8 Reserved2[3]; // 0dh + /// + /// What caused interrupt. + /// + UINT32 IntSts; // 10h + /// + /// Shows which interrupts are supported by that particular TPM. + /// + UINT32 InterfaceCapability;// 14h + /// + /// Status Register. Provides status of the TPM. + /// + UINT8 Status; // 18h + /// + /// Number of consecutive writes that can be done to the TPM. + /// + UINT16 BurstCount; // 19h + /// + /// Additional Status Register. + /// + UINT8 StatusEx; // 1Bh + UINT8 Reserved3[8]; + /// + /// Read or write FIFO, depending on transaction. + /// + UINT32 DataFifo; // 24h + UINT8 Reserved4[8]; // 28h + /// + /// Used to identify the Interface types supported by the TPM. + /// + UINT32 InterfaceId; // 30h + UINT8 Reserved5[0x4c]; // 34h + /// + /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write) + /// + UINT32 XDataFifo; // 80h + UINT8 Reserved6[0xe7c]; // 84h + /// + /// Vendor ID + /// + UINT16 Vid; // 0f00h + /// + /// Device ID + /// + UINT16 Did; // 0f02h + /// + /// Revision ID + /// + UINT8 Rid; // 0f04h + UINT8 Reserved[0xfb]; // 0f05h +} PTP_FIFO_REGISTERS; + +// +// Restore original structure alignment +// +#pragma pack () + +// +// Define pointer types used to access TIS registers on PC +// +typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR; + +// +// Define bits of FIFO Interface Identifier Register +// +typedef union { + struct { + UINT32 InterfaceType:4; + UINT32 InterfaceVersion:4; + UINT32 CapLocality:1; + UINT32 Reserved1:2; + UINT32 CapDataXferSizeSupport:2; + UINT32 CapFIFO:1; + UINT32 CapCRB:1; + UINT32 CapIFRes:2; + UINT32 InterfaceSelector:2; + UINT32 IntfSelLock:1; + UINT32 Reserved2:4; + UINT32 Reserved3:8; + } Bits; + UINT32 Uint32; +} PTP_FIFO_INTERFACE_IDENTIFIER; + +// +// Define bits of FIFO Interface Capability Register +// +typedef union { + struct { + UINT32 DataAvailIntSupport:1; + UINT32 StsValidIntSupport:1; + UINT32 LocalityChangeIntSupport:1; + UINT32 InterruptLevelHigh:1; + UINT32 InterruptLevelLow:1; + UINT32 InterruptEdgeRising:1; + UINT32 InterruptEdgeFalling:1; + UINT32 CommandReadyIntSupport:1; + UINT32 BurstCountStatic:1; + UINT32 DataTransferSizeSupport:2; + UINT32 Reserved:17; + UINT32 InterfaceVersion:3; + UINT32 Reserved2:1; + } Bits; + UINT32 Uint32; +} PTP_FIFO_INTERFACE_CAPABILITY; + +/// +/// InterfaceVersion +/// +#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0 +#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2 +#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3 + + +// +// Define bits of ACCESS and STATUS registers +// + +/// +/// This bit is a 1 to indicate that the other bits in this register are valid. +/// +#define PTP_FIFO_VALID BIT7 +/// +/// Indicate that this locality is active. +/// +#define PTP_FIFO_ACC_ACTIVE BIT5 +/// +/// Set to 1 to indicate that this locality had the TPM taken away while +/// this locality had the TIS_PC_ACC_ACTIVE bit set. +/// +#define PTP_FIFO_ACC_SEIZED BIT4 +/// +/// Set to 1 to indicate that TPM MUST reset the +/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the +/// locality that is writing this bit. +/// +#define PTP_FIFO_ACC_SEIZE BIT3 +/// +/// When this bit is 1, another locality is requesting usage of the TPM. +/// +#define PTP_FIFO_ACC_PENDIND BIT2 +/// +/// Set to 1 to indicate that this locality is requesting to use TPM. +/// +#define PTP_FIFO_ACC_RQUUSE BIT1 +/// +/// A value of 1 indicates that a T/OS has not been established on the platform +/// +#define PTP_FIFO_ACC_ESTABLISH BIT0 + +/// +/// This field indicates that STS_DATA and STS_EXPECT are valid +/// +#define PTP_FIFO_STS_VALID BIT7 +/// +/// When this bit is 1, TPM is in the Ready state, +/// indicating it is ready to receive a new command. +/// +#define PTP_FIFO_STS_READY BIT6 +/// +/// Write a 1 to this bit to cause the TPM to execute that command. +/// +#define PTP_FIFO_STS_GO BIT5 +/// +/// This bit indicates that the TPM has data available as a response. +/// +#define PTP_FIFO_STS_DATA BIT4 +/// +/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command. +/// +#define PTP_FIFO_STS_EXPECT BIT3 +/// +/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command. +/// +#define PTP_FIFO_STS_SELFTEST_DONE BIT2 +/// +/// Writes a 1 to this bit to force the TPM to re-send the response. +/// +#define PTP_FIFO_STS_RETRY BIT1 + +/// +/// TPM Family Identifier. +/// 00: TPM 1.2 Family +/// 01: TPM 2.0 Family +/// +#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) +#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2) +#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0) +#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) +/// +/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED. +/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM. +/// +#define PTP_FIFO_STS_EX_CANCEL BIT0 + + +// +// PTP CRB definition +// + +// +// Set structure alignment to 1-byte +// +#pragma pack (1) + +// +// Register set map as specified in PTP specification Chapter 5 +// +typedef struct { + /// + /// Used to determine current state of Locality of the TPM. + /// + UINT32 LocalityState; // 0 + UINT8 Reserved1[4]; // 4 + /// + /// Used to gain control of the TPM by this Locality. + /// + UINT32 LocalityControl; // 8 + /// + /// Used to determine whether Locality has been granted or Seized. + /// + UINT32 LocalityStatus; // 0ch + UINT8 Reserved2[0x20]; // 10h + /// + /// Used to identify the Interface types supported by the TPM. + /// + UINT32 InterfaceId; // 30h + /// + /// Vendor ID + /// + UINT16 Vid; // 34h + /// + /// Device ID + /// + UINT16 Did; // 36h + /// + /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability. + /// + UINT64 CrbControlExtension; // 38h + /// + /// Register used to initiate transactions for the CRB interface. + /// + UINT32 CrbControlRequest; // 40h + /// + /// Register used by the TPM to provide status of the CRB interface. + /// + UINT32 CrbControlStatus; // 44h + /// + /// Register used by software to cancel command processing. + /// + UINT32 CrbControlCancel; // 48h + /// + /// Register used to indicate presence of command or response data in the CRB buffer. + /// + UINT32 CrbControlStart; // 4Ch + /// + /// Register used to configure and respond to interrupts. + /// + UINT32 CrbInterruptEnable; // 50h + UINT32 CrbInterruptStatus; // 54h + /// + /// Size of the Command buffer. + /// + UINT32 CrbControlCommandSize; // 58h + /// + /// Command buffer start address + /// + UINT32 CrbControlCommandAddressLow; // 5Ch + UINT32 CrbControlCommandAddressHigh; // 60h + /// + /// Size of the Response buffer + /// + UINT32 CrbControlResponseSize; // 64h + /// + /// Address of the start of the Response buffer + /// + UINT64 CrbControlResponseAddrss; // 68h + UINT8 Reserved4[0x10]; // 70h + /// + /// Command/Response Data may be defined as large as 3968 (0xF80). + /// + UINT8 CrbDataBuffer[0xF80]; // 80h +} PTP_CRB_REGISTERS; + +// +// Define pointer types used to access CRB registers on PTP +// +typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR; + +// +// Define bits of CRB Interface Identifier Register +// +typedef union { + struct { + UINT32 InterfaceType:4; + UINT32 InterfaceVersion:4; + UINT32 CapLocality:1; + UINT32 CapCRBIdleBypass:1; + UINT32 Reserved1:1; + UINT32 CapDataXferSizeSupport:2; + UINT32 CapFIFO:1; + UINT32 CapCRB:1; + UINT32 CapIFRes:2; + UINT32 InterfaceSelector:2; + UINT32 IntfSelLock:1; + UINT32 Reserved2:4; + UINT32 Rid:8; + } Bits; + UINT32 Uint32; +} PTP_CRB_INTERFACE_IDENTIFIER; + +/// +/// InterfaceType +/// +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0 +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1 +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF + +/// +/// InterfaceVersion +/// +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0 +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1 + +/// +/// InterfaceSelector +/// +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0 +#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1 + +// +// Define bits of Locality State Register +// + +/// +/// This bit indicates whether all other bits of this register contain valid values, if it is a 1. +/// +#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7 + +/// +/// 000 - Locality 0 +/// 001 - Locality 1 +/// 010 - Locality 2 +/// 011 - Locality 3 +/// 100 - Locality 4 +/// +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0) +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3) +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) +#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4) + +/// +/// A 0 indicates to the host that no locality is assigned. +/// A 1 indicates a locality has been assigned. +/// +#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1 + +/// +/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End +/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1. +/// +#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0 + +// +// Define bits of Locality Control Register +// + +/// +/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4. +/// +#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3 + +/// +/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality. +/// +#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2 + +/// +/// Writes (1): The active Locality is done with the TPM. +/// +#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1 + +/// +/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm. +/// +#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0 + +// +// Define bits of Locality Status Register +// + +/// +/// 0: A higher locality has not initiated a Seize arbitration process. +/// 1: A higher locality has Seized the TPM from this locality. +/// +#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1 + +/// +/// 0: Locality has not been granted to the TPM. +/// 1: Locality has been granted access to the TPM +/// +#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0 + +// +// Define bits of CRB Control Area Request Register +// + +/// +/// Used by Software to indicate transition the TPM to and from the Idle state +/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle +/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state. +/// TPM SHALL complete this transition within TIMEOUT_C. +/// +#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1 + +/// +/// Used by Software to request the TPM transition to the Ready State. +/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command. +/// 0: Cleared to 0 by TPM to acknowledge the request. +/// TPM SHALL complete this transition within TIMEOUT_C. +/// +#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0 + +// +// Define bits of CRB Control Area Status Register +// + +/// +/// Used by TPM to indicate it is in the Idle State +/// 1: Set by TPM when in the Idle State +/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State. +/// SHALL be cleared by TIMEOUT_C. +/// +#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1 + +/// +/// Used by the TPM to indicate current status. +/// 1: Set by TPM to indicate a FATAL Error +/// 0: Indicates TPM is operational +/// +#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0 + +// +// Define bits of CRB Control Cancel Register +// + +/// +/// Used by software to cancel command processing Reads return correct value +/// Writes (0000 0001h): Cancel a command +/// Writes (0000 0000h): Clears field when command has been cancelled +/// +#define PTP_CRB_CONTROL_CANCEL BIT0 + +// +// Define bits of CRB Control Start Register +// + +/// +/// When set by software, indicates a command is ready for processing. +/// Writes (0000 0001h): TPM transitions to Command Execution +/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion +/// +#define PTP_CRB_CONTROL_START BIT0 + +// +// Restore original structure alignment +// +#pragma pack () + +// +// Default TimeOut value +// +#define PTP_TIMEOUT_A (750 * 1000) // 750ms +#define PTP_TIMEOUT_B (2000 * 1000) // 2s +#define PTP_TIMEOUT_C (200 * 1000) // 200ms +#define PTP_TIMEOUT_D (30 * 1000) // 30ms + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmTis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmTis.h new file mode 100644 index 0000000000..85c2969cc3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/TpmTis.h @@ -0,0 +1,181 @@ +/** @file + TPM Interface Specification definition. + It covers both TPM1.2 and TPM2.0. + +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TPM_TIS_H_ +#define _TPM_TIS_H_ + +// +// Set structure alignment to 1-byte +// +#pragma pack (1) + +// +// Register set map as specified in TIS specification Chapter 10 +// +typedef struct { + /// + /// Used to gain ownership for this particular port. + /// + UINT8 Access; // 0 + UINT8 Reserved1[7]; // 1 + /// + /// Controls interrupts. + /// + UINT32 IntEnable; // 8 + /// + /// SIRQ vector to be used by the TPM. + /// + UINT8 IntVector; // 0ch + UINT8 Reserved2[3]; // 0dh + /// + /// What caused interrupt. + /// + UINT32 IntSts; // 10h + /// + /// Shows which interrupts are supported by that particular TPM. + /// + UINT32 IntfCapability; // 14h + /// + /// Status Register. Provides status of the TPM. + /// + UINT8 Status; // 18h + /// + /// Number of consecutive writes that can be done to the TPM. + /// + UINT16 BurstCount; // 19h + UINT8 Reserved3[9]; + /// + /// Read or write FIFO, depending on transaction. + /// + UINT32 DataFifo; // 24h + UINT8 Reserved4[0xed8]; // 28h + /// + /// Vendor ID + /// + UINT16 Vid; // 0f00h + /// + /// Device ID + /// + UINT16 Did; // 0f02h + /// + /// Revision ID + /// + UINT8 Rid; // 0f04h + UINT8 Reserved[0x7b]; // 0f05h + /// + /// Alias to I/O legacy space. + /// + UINT32 LegacyAddress1; // 0f80h + /// + /// Additional 8 bits for I/O legacy space extension. + /// + UINT32 LegacyAddress1Ex; // 0f84h + /// + /// Alias to second I/O legacy space. + /// + UINT32 LegacyAddress2; // 0f88h + /// + /// Additional 8 bits for second I/O legacy space extension. + /// + UINT32 LegacyAddress2Ex; // 0f8ch + /// + /// Vendor-defined configuration registers. + /// + UINT8 VendorDefined[0x70];// 0f90h +} TIS_PC_REGISTERS; + +// +// Restore original structure alignment +// +#pragma pack () + +// +// Define pointer types used to access TIS registers on PC +// +typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR; + +// +// Define bits of ACCESS and STATUS registers +// + +/// +/// This bit is a 1 to indicate that the other bits in this register are valid. +/// +#define TIS_PC_VALID BIT7 +/// +/// Indicate that this locality is active. +/// +#define TIS_PC_ACC_ACTIVE BIT5 +/// +/// Set to 1 to indicate that this locality had the TPM taken away while +/// this locality had the TIS_PC_ACC_ACTIVE bit set. +/// +#define TIS_PC_ACC_SEIZED BIT4 +/// +/// Set to 1 to indicate that TPM MUST reset the +/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the +/// locality that is writing this bit. +/// +#define TIS_PC_ACC_SEIZE BIT3 +/// +/// When this bit is 1, another locality is requesting usage of the TPM. +/// +#define TIS_PC_ACC_PENDIND BIT2 +/// +/// Set to 1 to indicate that this locality is requesting to use TPM. +/// +#define TIS_PC_ACC_RQUUSE BIT1 +/// +/// A value of 1 indicates that a T/OS has not been established on the platform +/// +#define TIS_PC_ACC_ESTABLISH BIT0 + +/// +/// Write a 1 to this bit to notify TPM to cancel currently executing command +/// +#define TIS_PC_STS_CANCEL BIT24 +/// +/// This field indicates that STS_DATA and STS_EXPECT are valid +/// +#define TIS_PC_STS_VALID BIT7 +/// +/// When this bit is 1, TPM is in the Ready state, +/// indicating it is ready to receive a new command. +/// +#define TIS_PC_STS_READY BIT6 +/// +/// Write a 1 to this bit to cause the TPM to execute that command. +/// +#define TIS_PC_STS_GO BIT5 +/// +/// This bit indicates that the TPM has data available as a response. +/// +#define TIS_PC_STS_DATA BIT4 +/// +/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command. +/// +#define TIS_PC_STS_EXPECT BIT3 +/// +/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command. +/// +#define TIS_PC_STS_SELFTEST_DONE BIT2 +/// +/// Writes a 1 to this bit to force the TPM to re-send the response. +/// +#define TIS_PC_STS_RETRY BIT1 + +// +// Default TimeOut value +// +#define TIS_TIMEOUT_A (750 * 1000) // 750ms +#define TIS_TIMEOUT_B (2000 * 1000) // 2s +#define TIS_TIMEOUT_C (750 * 1000) // 750ms +#define TIS_TIMEOUT_D (750 * 1000) // 750ms + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Udf.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Udf.h new file mode 100644 index 0000000000..e299b75599 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Udf.h @@ -0,0 +1,141 @@ +/** @file + OSTA Universal Disk Format (UDF) definitions. + + Copyright (C) 2014-2017 Paulo Alcantara + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __UDF_H__ +#define __UDF_H__ + +#define UDF_BEA_IDENTIFIER "BEA01" +#define UDF_NSR2_IDENTIFIER "NSR02" +#define UDF_NSR3_IDENTIFIER "NSR03" +#define UDF_TEA_IDENTIFIER "TEA01" + +#define UDF_LOGICAL_SECTOR_SHIFT 11 +#define UDF_LOGICAL_SECTOR_SIZE ((UINT64)(1ULL << UDF_LOGICAL_SECTOR_SHIFT)) +#define UDF_VRS_START_OFFSET ((UINT64)(16ULL << UDF_LOGICAL_SECTOR_SHIFT)) + +typedef enum { + UdfPrimaryVolumeDescriptor = 1, + UdfAnchorVolumeDescriptorPointer = 2, + UdfVolumeDescriptorPointer = 3, + UdfImplemenationUseVolumeDescriptor = 4, + UdfPartitionDescriptor = 5, + UdfLogicalVolumeDescriptor = 6, + UdfUnallocatedSpaceDescriptor = 7, + UdfTerminatingDescriptor = 8, + UdfLogicalVolumeIntegrityDescriptor = 9, + UdfFileSetDescriptor = 256, + UdfFileIdentifierDescriptor = 257, + UdfAllocationExtentDescriptor = 258, + UdfFileEntry = 261, + UdfExtendedFileEntry = 266, +} UDF_VOLUME_DESCRIPTOR_ID; + +#pragma pack(1) + +typedef struct { + UINT16 TagIdentifier; + UINT16 DescriptorVersion; + UINT8 TagChecksum; + UINT8 Reserved; + UINT16 TagSerialNumber; + UINT16 DescriptorCRC; + UINT16 DescriptorCRCLength; + UINT32 TagLocation; +} UDF_DESCRIPTOR_TAG; + +typedef struct { + UINT32 ExtentLength; + UINT32 ExtentLocation; +} UDF_EXTENT_AD; + +typedef struct { + UINT8 CharacterSetType; + UINT8 CharacterSetInfo[63]; +} UDF_CHAR_SPEC; + +typedef struct { + UINT8 Flags; + UINT8 Identifier[23]; + union { + // + // Domain Entity Identifier + // + struct { + UINT16 UdfRevision; + UINT8 DomainFlags; + UINT8 Reserved[5]; + } Domain; + // + // UDF Entity Identifier + // + struct { + UINT16 UdfRevision; + UINT8 OSClass; + UINT8 OSIdentifier; + UINT8 Reserved[4]; + } Entity; + // + // Implementation Entity Identifier + // + struct { + UINT8 OSClass; + UINT8 OSIdentifier; + UINT8 ImplementationUseArea[6]; + } ImplementationEntity; + // + // Application Entity Identifier + // + struct { + UINT8 ApplicationUseArea[8]; + } ApplicationEntity; + // + // Raw Identifier Suffix + // + struct { + UINT8 Data[8]; + } Raw; + } Suffix; +} UDF_ENTITY_ID; + +typedef struct { + UINT32 LogicalBlockNumber; + UINT16 PartitionReferenceNumber; +} UDF_LB_ADDR; + +typedef struct { + UINT32 ExtentLength; + UDF_LB_ADDR ExtentLocation; + UINT8 ImplementationUse[6]; +} UDF_LONG_ALLOCATION_DESCRIPTOR; + +typedef struct { + UDF_DESCRIPTOR_TAG DescriptorTag; + UDF_EXTENT_AD MainVolumeDescriptorSequenceExtent; + UDF_EXTENT_AD ReserveVolumeDescriptorSequenceExtent; + UINT8 Reserved[480]; +} UDF_ANCHOR_VOLUME_DESCRIPTOR_POINTER; + +typedef struct { + UDF_DESCRIPTOR_TAG DescriptorTag; + UINT32 VolumeDescriptorSequenceNumber; + UDF_CHAR_SPEC DescriptorCharacterSet; + UINT8 LogicalVolumeIdentifier[128]; + UINT32 LogicalBlockSize; + UDF_ENTITY_ID DomainIdentifier; + UDF_LONG_ALLOCATION_DESCRIPTOR LogicalVolumeContentsUse; + UINT32 MapTableLength; + UINT32 NumberOfPartitionMaps; + UDF_ENTITY_ID ImplementationIdentifier; + UINT8 ImplementationUse[128]; + UDF_EXTENT_AD IntegritySequenceExtent; + UINT8 PartitionMaps[6]; +} UDF_LOGICAL_VOLUME_DESCRIPTOR; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h new file mode 100644 index 0000000000..683a479259 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h @@ -0,0 +1,500 @@ +/** @file + TCG EFI Platform Definition in TCG_EFI_Platform_1_20_Final and + TCG PC Client Platform Firmware Profile Specification, Revision 1.05 + + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_TCG_PLATFORM_H__ +#define __UEFI_TCG_PLATFORM_H__ + +#include +#include +#include + +// +// Standard event types +// +#define EV_PREBOOT_CERT ((TCG_EVENTTYPE) 0x00000000) +#define EV_POST_CODE ((TCG_EVENTTYPE) 0x00000001) +#define EV_NO_ACTION ((TCG_EVENTTYPE) 0x00000003) +#define EV_SEPARATOR ((TCG_EVENTTYPE) 0x00000004) +#define EV_ACTION ((TCG_EVENTTYPE) 0x00000005) +#define EV_EVENT_TAG ((TCG_EVENTTYPE) 0x00000006) +#define EV_S_CRTM_CONTENTS ((TCG_EVENTTYPE) 0x00000007) +#define EV_S_CRTM_VERSION ((TCG_EVENTTYPE) 0x00000008) +#define EV_CPU_MICROCODE ((TCG_EVENTTYPE) 0x00000009) +#define EV_PLATFORM_CONFIG_FLAGS ((TCG_EVENTTYPE) 0x0000000A) +#define EV_TABLE_OF_DEVICES ((TCG_EVENTTYPE) 0x0000000B) +#define EV_COMPACT_HASH ((TCG_EVENTTYPE) 0x0000000C) +#define EV_NONHOST_CODE ((TCG_EVENTTYPE) 0x0000000F) +#define EV_NONHOST_CONFIG ((TCG_EVENTTYPE) 0x00000010) +#define EV_NONHOST_INFO ((TCG_EVENTTYPE) 0x00000011) +#define EV_OMIT_BOOT_DEVICE_EVENTS ((TCG_EVENTTYPE) 0x00000012) + +// +// EFI specific event types +// +#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000) +#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1) +#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2) +#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3) +#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4) +#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5) +#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6) +#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7) +#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8) +#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9) +#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA) +#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB) +#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10) +#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0) +#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1) +#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2) + +#define EFI_CALLING_EFI_APPLICATION \ + "Calling EFI Application from Boot Option" +#define EFI_RETURNING_FROM_EFI_APPLICATION \ + "Returning from EFI Application from Boot Option" +#define EFI_EXIT_BOOT_SERVICES_INVOCATION \ + "Exit Boot Services Invocation" +#define EFI_EXIT_BOOT_SERVICES_FAILED \ + "Exit Boot Services Returned with Failure" +#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \ + "Exit Boot Services Returned with Success" + + +#define EV_POSTCODE_INFO_POST_CODE "POST CODE" +#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1) + +#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE" +#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1) + +#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA" +#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1) + +#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE" +#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1) + +#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI" +#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1) + +#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM" +#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1) + +#define EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER "Embedded UEFI Driver" +#define EMBEDDED_UEFI_DRIVER_LEN (sizeof(EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER) - 1) + +#define FIRMWARE_DEBUGGER_EVENT_STRING "UEFI Debug Mode" +#define FIRMWARE_DEBUGGER_EVENT_STRING_LEN (sizeof(FIRMWARE_DEBUGGER_EVENT_STRING) - 1) + +// +// Set structure alignment to 1-byte +// +#pragma pack (1) + +typedef UINT32 TCG_EVENTTYPE; +typedef TPM_PCRINDEX TCG_PCRINDEX; +typedef TPM_DIGEST TCG_DIGEST; +/// +/// Event Log Entry Structure Definition +/// +typedef struct tdTCG_PCR_EVENT { + TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to + TCG_EVENTTYPE EventType; ///< TCG EFI event type + TCG_DIGEST Digest; ///< Value extended into PCRIndex + UINT32 EventSize; ///< Size of the event data + UINT8 Event[1]; ///< The event data +} TCG_PCR_EVENT; + +#define TSS_EVENT_DATA_MAX_SIZE 256 + +/// +/// TCG_PCR_EVENT_HDR +/// +typedef struct tdTCG_PCR_EVENT_HDR { + TCG_PCRINDEX PCRIndex; + TCG_EVENTTYPE EventType; + TCG_DIGEST Digest; + UINT32 EventSize; +} TCG_PCR_EVENT_HDR; + +/// +/// EFI_PLATFORM_FIRMWARE_BLOB +/// +/// BlobLength should be of type UINTN but we use UINT64 here +/// because PEI is 32-bit while DXE is 64-bit on x64 platforms +/// +typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB { + EFI_PHYSICAL_ADDRESS BlobBase; + UINT64 BlobLength; +} EFI_PLATFORM_FIRMWARE_BLOB; + +/// +/// UEFI_PLATFORM_FIRMWARE_BLOB +/// +/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB +/// event to facilitate the measurement of firmware volume. +/// +typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB { + EFI_PHYSICAL_ADDRESS BlobBase; + UINT64 BlobLength; +} UEFI_PLATFORM_FIRMWARE_BLOB; + +/// +/// UEFI_PLATFORM_FIRMWARE_BLOB2 +/// +/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB2 +/// event to facilitate the measurement of firmware volume. +/// +typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 { + UINT8 BlobDescriptionSize; +//UINT8 BlobDescription[BlobDescriptionSize]; +//EFI_PHYSICAL_ADDRESS BlobBase; +//UINT64 BlobLength; +} UEFI_PLATFORM_FIRMWARE_BLOB2; + +/// +/// EFI_IMAGE_LOAD_EVENT +/// +/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION, +/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER +/// +typedef struct tdEFI_IMAGE_LOAD_EVENT { + EFI_PHYSICAL_ADDRESS ImageLocationInMemory; + UINTN ImageLengthInMemory; + UINTN ImageLinkTimeAddress; + UINTN LengthOfDevicePath; + EFI_DEVICE_PATH_PROTOCOL DevicePath[1]; +} EFI_IMAGE_LOAD_EVENT; + +/// +/// UEFI_IMAGE_LOAD_EVENT +/// +/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION, +/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER +/// +typedef struct tdUEFI_IMAGE_LOAD_EVENT { + EFI_PHYSICAL_ADDRESS ImageLocationInMemory; + UINT64 ImageLengthInMemory; + UINT64 ImageLinkTimeAddress; + UINT64 LengthOfDevicePath; + EFI_DEVICE_PATH_PROTOCOL DevicePath[1]; +} UEFI_IMAGE_LOAD_EVENT; + +/// +/// EFI_HANDOFF_TABLE_POINTERS +/// +/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate +/// the measurement of given configuration tables. +/// +typedef struct tdEFI_HANDOFF_TABLE_POINTERS { + UINTN NumberOfTables; + EFI_CONFIGURATION_TABLE TableEntry[1]; +} EFI_HANDOFF_TABLE_POINTERS; + +/// +/// UEFI_HANDOFF_TABLE_POINTERS +/// +/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate +/// the measurement of given configuration tables. +/// +typedef struct tdUEFI_HANDOFF_TABLE_POINTERS { + UINT64 NumberOfTables; + EFI_CONFIGURATION_TABLE TableEntry[1]; +} UEFI_HANDOFF_TABLE_POINTERS; + +/// +/// UEFI_HANDOFF_TABLE_POINTERS2 +/// +/// This structure is used in EV_EFI_HANDOFF_TABLES2 event to facilitate +/// the measurement of given configuration tables. +/// +typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 { + UINT8 TableDescriptionSize; +//UINT8 TableDescription[TableDescriptionSize]; +//UINT64 NumberOfTables; +//EFI_CONFIGURATION_TABLE TableEntry[1]; +} UEFI_HANDOFF_TABLE_POINTERS2; + +/// +/// EFI_VARIABLE_DATA +/// +/// This structure serves as the header for measuring variables. The name of the +/// variable (in Unicode format) should immediately follow, then the variable +/// data. +/// This is defined in TCG EFI Platform Spec for TPM1.1 or 1.2 V1.22 +/// +typedef struct tdEFI_VARIABLE_DATA { + EFI_GUID VariableName; + UINTN UnicodeNameLength; + UINTN VariableDataLength; + CHAR16 UnicodeName[1]; + INT8 VariableData[1]; ///< Driver or platform-specific data +} EFI_VARIABLE_DATA; + +/// +/// UEFI_VARIABLE_DATA +/// +/// This structure serves as the header for measuring variables. The name of the +/// variable (in Unicode format) should immediately follow, then the variable +/// data. +/// This is defined in TCG PC Client Firmware Profile Spec 00.21 +/// +typedef struct tdUEFI_VARIABLE_DATA { + EFI_GUID VariableName; + UINT64 UnicodeNameLength; + UINT64 VariableDataLength; + CHAR16 UnicodeName[1]; + INT8 VariableData[1]; ///< Driver or platform-specific data +} UEFI_VARIABLE_DATA; + +// +// For TrEE1.0 compatibility +// +typedef struct { + EFI_GUID VariableName; + UINT64 UnicodeNameLength; // The TCG Definition used UINTN + UINT64 VariableDataLength; // The TCG Definition used UINTN + CHAR16 UnicodeName[1]; + INT8 VariableData[1]; +} EFI_VARIABLE_DATA_TREE; + +typedef struct tdEFI_GPT_DATA { + EFI_PARTITION_TABLE_HEADER EfiPartitionHeader; + UINTN NumberOfPartitions; + EFI_PARTITION_ENTRY Partitions[1]; +} EFI_GPT_DATA; + +typedef struct tdUEFI_GPT_DATA { + EFI_PARTITION_TABLE_HEADER EfiPartitionHeader; + UINT64 NumberOfPartitions; + EFI_PARTITION_ENTRY Partitions[1]; +} UEFI_GPT_DATA; + +#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec" +#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1 + +#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_NULL 0 +#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_PCI 1 +#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_USB 2 + +/// +/// TCG_DEVICE_SECURITY_EVENT_DATA_HEADER +/// This is the header of TCG_DEVICE_SECURITY_EVENT_DATA, which is +/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG. +/// +typedef struct { + UINT8 Signature[16]; + UINT16 Version; + UINT16 Length; + UINT32 SpdmHashAlgo; + UINT32 DeviceType; +//SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock; +} TCG_DEVICE_SECURITY_EVENT_DATA_HEADER; + +#define TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT_VERSION 0 + +/// +/// TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT +/// This is the PCI context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is +/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG. +/// +typedef struct { + UINT16 Version; + UINT16 Length; + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevisionID; + UINT8 ClassCode[3]; + UINT16 SubsystemVendorID; + UINT16 SubsystemID; +} TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT; + +#define TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT_VERSION 0 + +/// +/// TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT +/// This is the USB context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is +/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG. +/// +typedef struct { + UINT16 Version; + UINT16 Length; +//UINT8 DeviceDescriptor[DescLen]; +//UINT8 BodDescriptor[DescLen]; +//UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration]; +} TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT; + +// +// Crypto Agile Log Entry Format +// +typedef struct tdTCG_PCR_EVENT2 { + TCG_PCRINDEX PCRIndex; + TCG_EVENTTYPE EventType; + TPML_DIGEST_VALUES Digest; + UINT32 EventSize; + UINT8 Event[1]; +} TCG_PCR_EVENT2; + +// +// TCG PCR Event2 Header +// Follow TCG EFI Protocol Spec 5.2 Crypto Agile Log Entry Format +// +typedef struct tdTCG_PCR_EVENT2_HDR{ + TCG_PCRINDEX PCRIndex; + TCG_EVENTTYPE EventType; + TPML_DIGEST_VALUES Digests; + UINT32 EventSize; +} TCG_PCR_EVENT2_HDR; + +// +// Log Header Entry Data +// +typedef struct { + // + // TCG defined hashing algorithm ID. + // + UINT16 algorithmId; + // + // The size of the digest for the respective hashing algorithm. + // + UINT16 digestSize; +} TCG_EfiSpecIdEventAlgorithmSize; + +#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02" +#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03" + +#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1 +#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2 +#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2 + +#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2 2 +#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2 0 +#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2 0 +#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2_REV_105 105 + +typedef struct { + UINT8 signature[16]; + // + // The value for the Platform Class. + // The enumeration is defined in the TCG ACPI Specification Client Common Header. + // + UINT32 platformClass; + // + // The TCG EFI Platform Specification minor version number this BIOS supports. + // Any BIOS supporting version (1.22) MUST set this value to 02h. + // Any BIOS supporting version (2.0) SHALL set this value to 0x00. + // + UINT8 specVersionMinor; + // + // The TCG EFI Platform Specification major version number this BIOS supports. + // Any BIOS supporting version (1.22) MUST set this value to 01h. + // Any BIOS supporting version (2.0) SHALL set this value to 0x02. + // + UINT8 specVersionMajor; + // + // The TCG EFI Platform Specification errata for this specification this BIOS supports. + // Any BIOS supporting version and errata (1.22) MUST set this value to 02h. + // Any BIOS supporting version and errata (2.0) SHALL set this value to 0x00. + // + UINT8 specErrata; + // + // Specifies the size of the UINTN fields used in various data structures used in this specification. + // 0x01 indicates UINT32 and 0x02 indicates UINT64. + // + UINT8 uintnSize; + // + // This field is added in "Spec ID Event03". + // The number of hashing algorithms used in this event log (except the first event). + // All events in this event log use all hashing algorithms defined here. + // +//UINT32 numberOfAlgorithms; + // + // This field is added in "Spec ID Event03". + // An array of size numberOfAlgorithms of value pairs. + // +//TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms]; + // + // Size in bytes of the VendorInfo field. + // Maximum value SHALL be FFh bytes. + // +//UINT8 vendorInfoSize; + // + // Provided for use by the BIOS implementer. + // The value might be used, for example, to provide more detailed information about the specific BIOS such as BIOS revision numbers, etc. + // The values within this field are not standardized and are implementer-specific. + // Platform-specific or -unique information SHALL NOT be provided in this field. + // +//UINT8 vendorInfo[vendorInfoSize]; +} TCG_EfiSpecIDEventStruct; + +typedef struct tdTCG_PCClientTaggedEvent { + UINT32 taggedEventID; + UINT32 taggedEventDataSize; +//UINT8 taggedEventData[taggedEventDataSize]; +} TCG_PCClientTaggedEvent; + +#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event" +#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2" + +typedef struct tdTCG_Sp800_155_PlatformId_Event2 { + UINT8 Signature[16]; + // + // Where Vendor ID is an integer defined + // at http://www.iana.org/assignments/enterprisenumbers + // + UINT32 VendorId; + // + // 16-byte identifier of a given platform's static configuration of code + // + EFI_GUID ReferenceManifestGuid; + // + // Below structure is newly added in TCG_Sp800_155_PlatformId_Event2. + // +//UINT8 PlatformManufacturerStrSize; +//UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize]; +//UINT8 PlatformModelSize; +//UINT8 PlatformModel[PlatformModelSize]; +//UINT8 PlatformVersionSize; +//UINT8 PlatformVersion[PlatformVersionSize]; +//UINT8 PlatformModelSize; +//UINT8 PlatformModel[PlatformModelSize]; +//UINT8 FirmwareManufacturerStrSize; +//UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize]; +//UINT32 FirmwareManufacturerId; +//UINT8 FirmwareVersion; +//UINT8 FirmwareVersion[FirmwareVersionSize]]; +} TCG_Sp800_155_PlatformId_Event2; + +#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality" + + +// +// The Locality Indicator which sent the TPM2_Startup command +// +#define LOCALITY_0_INDICATOR 0x00 +#define LOCALITY_3_INDICATOR 0x03 + +// +// Startup Locality Event +// +typedef struct tdTCG_EfiStartupLocalityEvent{ + UINT8 Signature[16]; + // + // The Locality Indicator which sent the TPM2_Startup command + // + UINT8 StartupLocality; +} TCG_EfiStartupLocalityEvent; + + +// +// Restore original structure alignment +// +#pragma pack () + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Usb.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Usb.h new file mode 100644 index 0000000000..e7c02e5a46 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Usb.h @@ -0,0 +1,380 @@ +/** @file + Support for USB 2.0 standard. + + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USB_H__ +#define __USB_H__ + +// +// Subset of Class and Subclass definitions from USB Specs +// + +// +// Usb mass storage class code +// +#define USB_MASS_STORE_CLASS 0x08 + +// +// Usb mass storage subclass code, specify the command set used. +// +#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands +#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device +#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device +#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device +#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device. +#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set + +// +// Usb mass storage protocol code, specify the transport protocol +// +#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt +#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt +#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport + +// +// Standard device request and request type +// USB 2.0 spec, Section 9.4 +// +#define USB_DEV_GET_STATUS 0x00 +#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device +#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface +#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint + +#define USB_DEV_CLEAR_FEATURE 0x01 +#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device +#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface +#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint + +#define USB_DEV_SET_FEATURE 0x03 +#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device +#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface +#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint + +#define USB_DEV_SET_ADDRESS 0x05 +#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00 + +#define USB_DEV_GET_DESCRIPTOR 0x06 +#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80 + +#define USB_DEV_SET_DESCRIPTOR 0x07 +#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00 + +#define USB_DEV_GET_CONFIGURATION 0x08 +#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80 + +#define USB_DEV_SET_CONFIGURATION 0x09 +#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00 + +#define USB_DEV_GET_INTERFACE 0x0A +#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81 + +#define USB_DEV_SET_INTERFACE 0x0B +#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01 + +#define USB_DEV_SYNCH_FRAME 0x0C +#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82 + + +// +// USB standard descriptors and reqeust +// +#pragma pack(1) + +/// +/// Format of Setup Data for USB Device Requests +/// USB 2.0 spec, Section 9.3 +/// +typedef struct { + UINT8 RequestType; + UINT8 Request; + UINT16 Value; + UINT16 Index; + UINT16 Length; +} USB_DEVICE_REQUEST; + +/// +/// Standard Device Descriptor +/// USB 2.0 spec, Section 9.6.1 +/// +typedef struct { + UINT8 Length; + UINT8 DescriptorType; + UINT16 BcdUSB; + UINT8 DeviceClass; + UINT8 DeviceSubClass; + UINT8 DeviceProtocol; + UINT8 MaxPacketSize0; + UINT16 IdVendor; + UINT16 IdProduct; + UINT16 BcdDevice; + UINT8 StrManufacturer; + UINT8 StrProduct; + UINT8 StrSerialNumber; + UINT8 NumConfigurations; +} USB_DEVICE_DESCRIPTOR; + +/// +/// Standard Configuration Descriptor +/// USB 2.0 spec, Section 9.6.3 +/// +typedef struct { + UINT8 Length; + UINT8 DescriptorType; + UINT16 TotalLength; + UINT8 NumInterfaces; + UINT8 ConfigurationValue; + UINT8 Configuration; + UINT8 Attributes; + UINT8 MaxPower; +} USB_CONFIG_DESCRIPTOR; + +/// +/// Standard Interface Descriptor +/// USB 2.0 spec, Section 9.6.5 +/// +typedef struct { + UINT8 Length; + UINT8 DescriptorType; + UINT8 InterfaceNumber; + UINT8 AlternateSetting; + UINT8 NumEndpoints; + UINT8 InterfaceClass; + UINT8 InterfaceSubClass; + UINT8 InterfaceProtocol; + UINT8 Interface; +} USB_INTERFACE_DESCRIPTOR; + +/// +/// Standard Endpoint Descriptor +/// USB 2.0 spec, Section 9.6.6 +/// +typedef struct { + UINT8 Length; + UINT8 DescriptorType; + UINT8 EndpointAddress; + UINT8 Attributes; + UINT16 MaxPacketSize; + UINT8 Interval; +} USB_ENDPOINT_DESCRIPTOR; + +/// +/// UNICODE String Descriptor +/// USB 2.0 spec, Section 9.6.7 +/// +typedef struct { + UINT8 Length; + UINT8 DescriptorType; + CHAR16 String[1]; +} EFI_USB_STRING_DESCRIPTOR; + +#pragma pack() + + +typedef enum { + // + // USB request type + // + USB_REQ_TYPE_STANDARD = (0x00 << 5), + USB_REQ_TYPE_CLASS = (0x01 << 5), + USB_REQ_TYPE_VENDOR = (0x02 << 5), + + // + // Standard control transfer request type, or the value + // to fill in EFI_USB_DEVICE_REQUEST.Request + // + USB_REQ_GET_STATUS = 0x00, + USB_REQ_CLEAR_FEATURE = 0x01, + USB_REQ_SET_FEATURE = 0x03, + USB_REQ_SET_ADDRESS = 0x05, + USB_REQ_GET_DESCRIPTOR = 0x06, + USB_REQ_SET_DESCRIPTOR = 0x07, + USB_REQ_GET_CONFIG = 0x08, + USB_REQ_SET_CONFIG = 0x09, + USB_REQ_GET_INTERFACE = 0x0A, + USB_REQ_SET_INTERFACE = 0x0B, + USB_REQ_SYNCH_FRAME = 0x0C, + + // + // Usb control transfer target + // + USB_TARGET_DEVICE = 0, + USB_TARGET_INTERFACE = 0x01, + USB_TARGET_ENDPOINT = 0x02, + USB_TARGET_OTHER = 0x03, + + // + // USB Descriptor types + // + USB_DESC_TYPE_DEVICE = 0x01, + USB_DESC_TYPE_CONFIG = 0x02, + USB_DESC_TYPE_STRING = 0x03, + USB_DESC_TYPE_INTERFACE = 0x04, + USB_DESC_TYPE_ENDPOINT = 0x05, + USB_DESC_TYPE_HID = 0x21, + USB_DESC_TYPE_REPORT = 0x22, + + // + // Features to be cleared by CLEAR_FEATURE requests + // + USB_FEATURE_ENDPOINT_HALT = 0, + + // + // USB endpoint types: 00: control, 01: isochronous, 10: bulk, 11: interrupt + // + USB_ENDPOINT_CONTROL = 0x00, + USB_ENDPOINT_ISO = 0x01, + USB_ENDPOINT_BULK = 0x02, + USB_ENDPOINT_INTERRUPT = 0x03, + + USB_ENDPOINT_TYPE_MASK = 0x03, + USB_ENDPOINT_DIR_IN = 0x80, + + // + //Use 200 ms to increase the error handling response time + // + EFI_USB_INTERRUPT_DELAY = 2000000 +} USB_TYPES_DEFINITION; + + +// +// HID constants definition, see Device Class Definition +// for Human Interface Devices (HID) rev1.11 +// + +// +// HID standard GET_DESCRIPTOR request. +// +#define USB_HID_GET_DESCRIPTOR_REQ_TYPE 0x81 + +// +// HID specific requests. +// +#define USB_HID_CLASS_GET_REQ_TYPE 0xa1 +#define USB_HID_CLASS_SET_REQ_TYPE 0x21 + +// +// HID report item format +// +#define HID_ITEM_FORMAT_SHORT 0 +#define HID_ITEM_FORMAT_LONG 1 + +// +// Special tag indicating long items +// +#define HID_ITEM_TAG_LONG 15 + +// +// HID report descriptor item type (prefix bit 2,3) +// +#define HID_ITEM_TYPE_MAIN 0 +#define HID_ITEM_TYPE_GLOBAL 1 +#define HID_ITEM_TYPE_LOCAL 2 +#define HID_ITEM_TYPE_RESERVED 3 + +// +// HID report descriptor main item tags +// +#define HID_MAIN_ITEM_TAG_INPUT 8 +#define HID_MAIN_ITEM_TAG_OUTPUT 9 +#define HID_MAIN_ITEM_TAG_FEATURE 11 +#define HID_MAIN_ITEM_TAG_BEGIN_COLLECTION 10 +#define HID_MAIN_ITEM_TAG_END_COLLECTION 12 + +// +// HID report descriptor main item contents +// +#define HID_MAIN_ITEM_CONSTANT 0x001 +#define HID_MAIN_ITEM_VARIABLE 0x002 +#define HID_MAIN_ITEM_RELATIVE 0x004 +#define HID_MAIN_ITEM_WRAP 0x008 +#define HID_MAIN_ITEM_NONLINEAR 0x010 +#define HID_MAIN_ITEM_NO_PREFERRED 0x020 +#define HID_MAIN_ITEM_NULL_STATE 0x040 +#define HID_MAIN_ITEM_VOLATILE 0x080 +#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100 + +// +// HID report descriptor collection item types +// +#define HID_COLLECTION_PHYSICAL 0 +#define HID_COLLECTION_APPLICATION 1 +#define HID_COLLECTION_LOGICAL 2 + +// +// HID report descriptor global item tags +// +#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM 1 +#define HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM 2 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM 3 +#define HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM 4 +#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 5 +#define HID_GLOBAL_ITEM_TAG_UNIT 6 +#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 7 +#define HID_GLOBAL_ITEM_TAG_REPORT_ID 8 +#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 9 +#define HID_GLOBAL_ITEM_TAG_PUSH 10 +#define HID_GLOBAL_ITEM_TAG_POP 11 + +// +// HID report descriptor local item tags +// +#define HID_LOCAL_ITEM_TAG_USAGE 0 +#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1 +#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4 +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5 +#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7 +#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8 +#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9 +#define HID_LOCAL_ITEM_TAG_DELIMITER 10 + +// +// HID report types +// +#define HID_INPUT_REPORT 1 +#define HID_OUTPUT_REPORT 2 +#define HID_FEATURE_REPORT 3 + +// +// HID class protocol request +// +#define EFI_USB_GET_REPORT_REQUEST 0x01 +#define EFI_USB_GET_IDLE_REQUEST 0x02 +#define EFI_USB_GET_PROTOCOL_REQUEST 0x03 +#define EFI_USB_SET_REPORT_REQUEST 0x09 +#define EFI_USB_SET_IDLE_REQUEST 0x0a +#define EFI_USB_SET_PROTOCOL_REQUEST 0x0b + +#pragma pack(1) +/// +/// Descriptor header for Report/Physical Descriptors +/// HID 1.1, section 6.2.1 +/// +typedef struct hid_class_descriptor { + UINT8 DescriptorType; + UINT16 DescriptorLength; +} EFI_USB_HID_CLASS_DESCRIPTOR; + +/// +/// The HID descriptor identifies the length and type +/// of subordinate descriptors for a device. +/// HID 1.1, section 6.2.1 +/// +typedef struct hid_descriptor { + UINT8 Length; + UINT8 DescriptorType; + UINT16 BcdHID; + UINT8 CountryCode; + UINT8 NumDescriptors; + EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1]; +} EFI_USB_HID_DESCRIPTOR; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogActionTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogActionTable.h new file mode 100644 index 0000000000..d30c461507 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogActionTable.h @@ -0,0 +1,90 @@ +/** @file + ACPI Watchdog Action Table (WADT) as defined at + Microsoft Hardware Watchdog Timers Design Specification. + + Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#ifndef _WATCHDOG_ACTION_TABLE_H_ +#define _WATCHDOG_ACTION_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) +/// +/// Watchdog Action Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WatchdogHeaderLength; + UINT16 PCISegment; + UINT8 PCIBusNumber; + UINT8 PCIDeviceNumber; + UINT8 PCIFunctionNumber; + UINT8 Reserved_45[3]; + UINT32 TimerPeriod; + UINT32 MaxCount; + UINT32 MinCount; + UINT8 WatchdogFlags; + UINT8 Reserved_61[3]; + UINT32 NumberWatchdogInstructionEntries; +} EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE; + +/// +/// Watchdog Instruction Entries +/// +typedef struct { + UINT8 WatchdogAction; + UINT8 InstructionFlags; + UINT8 Reserved_2[2]; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; + UINT32 Value; + UINT32 Mask; +} EFI_ACPI_WATCHDOG_ACTION_1_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY; + +#pragma pack() + +/// +/// WDAT Revision (defined in spec) +/// +#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION 0x01 + +// +// WDAT 1.0 Flags +// +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED 0x1 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80 + +// +// WDAT 1.0 Watchdog Actions +// +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_RESET 0x1 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD 0x5 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD 0x6 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE 0x8 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_RUNNING_STATE 0x9 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE 0xA +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_STOPPED_STATE 0xB +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_REBOOT 0x10 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_REBOOT 0x11 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_SHUTDOWN 0x12 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_SHUTDOWN 0x13 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS 0x20 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS 0x21 + +// +// WDAT 1.0 Watchdog Action Entry Instruction Flags +// +#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_VALUE 0x0 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN 0x1 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_VALUE 0x2 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN 0x3 +#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h new file mode 100644 index 0000000000..3ff87a3ea3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h @@ -0,0 +1,50 @@ +/** @file + ACPI Watchdog Resource Table (WDRT) as defined at + Microsoft Windows Hardware Developer Central. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WATCHDOG_RESOURCE_TABLE_H_ +#define _WATCHDOG_RESOURCE_TABLE_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// Watchdog Resource Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ControlRegisterAddress; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE CountRegisterAddress; + UINT16 PCIDeviceID; + UINT16 PCIVendorID; + UINT8 PCIBusNumber; + UINT8 PCIDeviceNumber; + UINT8 PCIFunctionNumber; + UINT8 PCISegment; + UINT16 MaxCount; + UINT8 Units; +} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE; + +#pragma pack() + +// +// WDRT Revision (defined in spec) +// +#define EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE_REVISION 0x01 + +// +// WDRT 1.0 Count Unit +// +#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_1_SEC_PER_COUNT 1 +#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2 +#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT 3 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h new file mode 100644 index 0000000000..4256d24f58 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h @@ -0,0 +1,33 @@ +/** @file + Defines Windows SMM Security Mitigation Table + @ https://msdn.microsoft.com/windows/hardware/drivers/bringup/acpi-system-description-tables#wsmt + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_ +#define _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_ + +#include + +#define EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T') + +#pragma pack(1) + +#define EFI_WSMT_TABLE_REVISION 1 + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 ProtectionFlags; +} EFI_ACPI_WSMT_TABLE; + +#define EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS 0x1 +#define EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION 0x2 +#define EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION 0x4 + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h new file mode 100644 index 0000000000..3434fd6c4b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h @@ -0,0 +1,41 @@ +/** @file + Defines Windows UX Capsule GUID and layout defined at Microsoft + Windows UEFI Firmware Update Platform specification + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _WINDOWS_UX_CAPSULE_GUID_H_ +#define _WINDOWS_UX_CAPSULE_GUID_H_ + +#pragma pack(1) + +typedef struct { + UINT8 Version; + UINT8 Checksum; + UINT8 ImageType; + UINT8 Reserved; + UINT32 Mode; + UINT32 OffsetX; + UINT32 OffsetY; + //UINT8 Image[]; +} DISPLAY_DISPLAY_PAYLOAD; + +typedef struct { + EFI_CAPSULE_HEADER CapsuleHeader; + DISPLAY_DISPLAY_PAYLOAD ImagePayload; +} EFI_DISPLAY_CAPSULE; + +#pragma pack() + +#define WINDOWS_UX_CAPSULE_GUID \ + { \ + 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97} \ + } + +extern EFI_GUID gWindowsUxCapsuleGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseLib.h new file mode 100644 index 0000000000..9eb6ff93ad --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseLib.h @@ -0,0 +1,7656 @@ +/** @file + Provides string functions, linked list functions, math functions, synchronization + functions, file path functions, and CPU architecture-specific functions. + +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+Copyright (c) Microsoft Corporation.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __BASE_LIB__ +#define __BASE_LIB__ + +// +// Definitions for architecture-specific types +// +#if defined (MDE_CPU_IA32) +/// +/// The IA-32 architecture context buffer used by SetJump() and LongJump(). +/// +typedef struct { + UINT32 Ebx; + UINT32 Esi; + UINT32 Edi; + UINT32 Ebp; + UINT32 Esp; + UINT32 Eip; + UINT32 Ssp; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4 + +#endif // defined (MDE_CPU_IA32) + +#if defined (MDE_CPU_X64) +/// +/// The x64 architecture context buffer used by SetJump() and LongJump(). +/// +typedef struct { + UINT64 Rbx; + UINT64 Rsp; + UINT64 Rbp; + UINT64 Rdi; + UINT64 Rsi; + UINT64 R12; + UINT64 R13; + UINT64 R14; + UINT64 R15; + UINT64 Rip; + UINT64 MxCsr; + UINT8 XmmBuffer[160]; ///< XMM6-XMM15. + UINT64 Ssp; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_X64) + +#if defined (MDE_CPU_EBC) +/// +/// The EBC context buffer used by SetJump() and LongJump(). +/// +typedef struct { + UINT64 R0; + UINT64 R1; + UINT64 R2; + UINT64 R3; + UINT64 IP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_EBC) + +#if defined (MDE_CPU_ARM) + +typedef struct { + UINT32 R3; ///< A copy of R13. + UINT32 R4; + UINT32 R5; + UINT32 R6; + UINT32 R7; + UINT32 R8; + UINT32 R9; + UINT32 R10; + UINT32 R11; + UINT32 R12; + UINT32 R14; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4 + +#endif // defined (MDE_CPU_ARM) + +#if defined (MDE_CPU_AARCH64) +typedef struct { + // GP regs + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 FP; + UINT64 LR; + UINT64 IP0; + + // FP regs + UINT64 D8; + UINT64 D9; + UINT64 D10; + UINT64 D11; + UINT64 D12; + UINT64 D13; + UINT64 D14; + UINT64 D15; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_AARCH64) + +#if defined (MDE_CPU_RISCV64) +/// +/// The RISC-V architecture context buffer used by SetJump() and LongJump(). +/// +typedef struct { + UINT64 RA; + UINT64 S0; + UINT64 S1; + UINT64 S2; + UINT64 S3; + UINT64 S4; + UINT64 S5; + UINT64 S6; + UINT64 S7; + UINT64 S8; + UINT64 S9; + UINT64 S10; + UINT64 S11; + UINT64 SP; +} BASE_LIBRARY_JUMP_BUFFER; + +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 + +#endif // defined (MDE_CPU_RISCV64) + +// +// String Services +// + + +/** + Returns the length of a Null-terminated Unicode string. + + This function is similar as strlen_s defined in C11. + + If String is not aligned on a 16-bit boundary, then ASSERT(). + + @param String A pointer to a Null-terminated Unicode string. + @param MaxSize The maximum number of Destination Unicode + char, including terminating null char. + + @retval 0 If String is NULL. + @retval MaxSize If there is no null character in the first MaxSize characters of String. + @return The number of characters that percede the terminating null character. + +**/ +UINTN +EFIAPI +StrnLenS ( + IN CONST CHAR16 *String, + IN UINTN MaxSize + ); + +/** + Returns the size of a Null-terminated Unicode string in bytes, including the + Null terminator. + + This function returns the size of the Null-terminated Unicode string + specified by String in bytes, including the Null terminator. + + If String is not aligned on a 16-bit boundary, then ASSERT(). + + @param String A pointer to a Null-terminated Unicode string. + @param MaxSize The maximum number of Destination Unicode + char, including the Null terminator. + + @retval 0 If String is NULL. + @retval (sizeof (CHAR16) * (MaxSize + 1)) + If there is no Null terminator in the first MaxSize characters of + String. + @return The size of the Null-terminated Unicode string in bytes, including + the Null terminator. + +**/ +UINTN +EFIAPI +StrnSizeS ( + IN CONST CHAR16 *String, + IN UINTN MaxSize + ); + +/** + Copies the string pointed to by Source (including the terminating null char) + to the array pointed to by Destination. + + This function is similar as strcpy_s defined in C11. + + If Destination is not aligned on a 16-bit boundary, then ASSERT(). + If Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode + char, including terminating null char. + @param Source A pointer to a Null-terminated Unicode string. + + @retval RETURN_SUCCESS String is copied. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +StrCpyS ( + OUT CHAR16 *Destination, + IN UINTN DestMax, + IN CONST CHAR16 *Source + ); + +/** + Copies not more than Length successive char from the string pointed to by + Source to the array pointed to by Destination. If no null char is copied from + Source, then Destination[Length] is always set to null. + + This function is similar as strncpy_s defined in C11. + + If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT(). + If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode + char, including terminating null char. + @param Source A pointer to a Null-terminated Unicode string. + @param Length The maximum number of Unicode characters to copy. + + @retval RETURN_SUCCESS String is copied. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than + MIN(StrLen(Source), Length). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +StrnCpyS ( + OUT CHAR16 *Destination, + IN UINTN DestMax, + IN CONST CHAR16 *Source, + IN UINTN Length + ); + +/** + Appends a copy of the string pointed to by Source (including the terminating + null char) to the end of the string pointed to by Destination. + + This function is similar as strcat_s defined in C11. + + If Destination is not aligned on a 16-bit boundary, then ASSERT(). + If Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode + char, including terminating null char. + @param Source A pointer to a Null-terminated Unicode string. + + @retval RETURN_SUCCESS String is appended. + @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than + StrLen(Destination). + @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT + greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +StrCatS ( + IN OUT CHAR16 *Destination, + IN UINTN DestMax, + IN CONST CHAR16 *Source + ); + +/** + Appends not more than Length successive char from the string pointed to by + Source to the end of the string pointed to by Destination. If no null char is + copied from Source, then Destination[StrLen(Destination) + Length] is always + set to null. + + This function is similar as strncat_s defined in C11. + + If Destination is not aligned on a 16-bit boundary, then ASSERT(). + If Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode + char, including terminating null char. + @param Source A pointer to a Null-terminated Unicode string. + @param Length The maximum number of Unicode characters to copy. + + @retval RETURN_SUCCESS String is appended. + @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than + StrLen(Destination). + @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT + greater than MIN(StrLen(Source), Length). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +StrnCatS ( + IN OUT CHAR16 *Destination, + IN UINTN DestMax, + IN CONST CHAR16 *Source, + IN UINTN Length + ); + +/** + Convert a Null-terminated Unicode decimal string to a value of type UINTN. + + This function outputs a value of type UINTN by interpreting the contents of + the Unicode string specified by String as a decimal number. The format of the + input Unicode string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before + [decimal digits]. The running zero in the beginning of [decimal digits] will + be ignored. Then, the function stops at the first character that is a not a + valid decimal character or a Null-terminator, whichever one comes first. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If String has no valid decimal digits in the above format, then 0 is stored + at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINTN, then + MAX_UINTN is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + decimal digits right after the optional pad spaces, the value of String is + stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINTN. + +**/ +RETURN_STATUS +EFIAPI +StrDecimalToUintnS ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT UINTN *Data + ); + +/** + Convert a Null-terminated Unicode decimal string to a value of type UINT64. + + This function outputs a value of type UINT64 by interpreting the contents of + the Unicode string specified by String as a decimal number. The format of the + input Unicode string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before + [decimal digits]. The running zero in the beginning of [decimal digits] will + be ignored. Then, the function stops at the first character that is a not a + valid decimal character or a Null-terminator, whichever one comes first. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If String has no valid decimal digits in the above format, then 0 is stored + at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINT64, then + MAX_UINT64 is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + decimal digits right after the optional pad spaces, the value of String is + stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINT64. + +**/ +RETURN_STATUS +EFIAPI +StrDecimalToUint64S ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT UINT64 *Data + ); + +/** + Convert a Null-terminated Unicode hexadecimal string to a value of type + UINTN. + + This function outputs a value of type UINTN by interpreting the contents of + the Unicode string specified by String as a hexadecimal number. The format of + the input Unicode string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. + If "x" appears in the input string, it must be prefixed with at least one 0. + The function will ignore the pad space, which includes spaces or tab + characters, before [zeros], [x] or [hexadecimal digit]. The running zero + before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts + after [x] or the first valid hexadecimal digit. Then, the function stops at + the first character that is a not a valid hexadecimal character or NULL, + whichever one comes first. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If String has no valid hexadecimal digits in the above format, then 0 is + stored at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINTN, then + MAX_UINTN is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + hexadecimal digits right after the optional pad spaces, the value of String + is stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINTN. + +**/ +RETURN_STATUS +EFIAPI +StrHexToUintnS ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT UINTN *Data + ); + +/** + Convert a Null-terminated Unicode hexadecimal string to a value of type + UINT64. + + This function outputs a value of type UINT64 by interpreting the contents of + the Unicode string specified by String as a hexadecimal number. The format of + the input Unicode string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. + If "x" appears in the input string, it must be prefixed with at least one 0. + The function will ignore the pad space, which includes spaces or tab + characters, before [zeros], [x] or [hexadecimal digit]. The running zero + before [x] or [hexadecimal digit] will be ignored. Then, the decoding starts + after [x] or the first valid hexadecimal digit. Then, the function stops at + the first character that is a not a valid hexadecimal character or NULL, + whichever one comes first. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If String has no valid hexadecimal digits in the above format, then 0 is + stored at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINT64, then + MAX_UINT64 is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + hexadecimal digits right after the optional pad spaces, the value of String + is stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINT64. + +**/ +RETURN_STATUS +EFIAPI +StrHexToUint64S ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT UINT64 *Data + ); + +/** + Returns the length of a Null-terminated Ascii string. + + This function is similar as strlen_s defined in C11. + + @param String A pointer to a Null-terminated Ascii string. + @param MaxSize The maximum number of Destination Ascii + char, including terminating null char. + + @retval 0 If String is NULL. + @retval MaxSize If there is no null character in the first MaxSize characters of String. + @return The number of characters that percede the terminating null character. + +**/ +UINTN +EFIAPI +AsciiStrnLenS ( + IN CONST CHAR8 *String, + IN UINTN MaxSize + ); + +/** + Returns the size of a Null-terminated Ascii string in bytes, including the + Null terminator. + + This function returns the size of the Null-terminated Ascii string specified + by String in bytes, including the Null terminator. + + @param String A pointer to a Null-terminated Ascii string. + @param MaxSize The maximum number of Destination Ascii + char, including the Null terminator. + + @retval 0 If String is NULL. + @retval (sizeof (CHAR8) * (MaxSize + 1)) + If there is no Null terminator in the first MaxSize characters of + String. + @return The size of the Null-terminated Ascii string in bytes, including the + Null terminator. + +**/ +UINTN +EFIAPI +AsciiStrnSizeS ( + IN CONST CHAR8 *String, + IN UINTN MaxSize + ); + +/** + Copies the string pointed to by Source (including the terminating null char) + to the array pointed to by Destination. + + This function is similar as strcpy_s defined in C11. + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Ascii string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + @param Source A pointer to a Null-terminated Ascii string. + + @retval RETURN_SUCCESS String is copied. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +AsciiStrCpyS ( + OUT CHAR8 *Destination, + IN UINTN DestMax, + IN CONST CHAR8 *Source + ); + +/** + Copies not more than Length successive char from the string pointed to by + Source to the array pointed to by Destination. If no null char is copied from + Source, then Destination[Length] is always set to null. + + This function is similar as strncpy_s defined in C11. + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Ascii string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + @param Source A pointer to a Null-terminated Ascii string. + @param Length The maximum number of Ascii characters to copy. + + @retval RETURN_SUCCESS String is copied. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than + MIN(StrLen(Source), Length). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +AsciiStrnCpyS ( + OUT CHAR8 *Destination, + IN UINTN DestMax, + IN CONST CHAR8 *Source, + IN UINTN Length + ); + +/** + Appends a copy of the string pointed to by Source (including the terminating + null char) to the end of the string pointed to by Destination. + + This function is similar as strcat_s defined in C11. + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Ascii string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + @param Source A pointer to a Null-terminated Ascii string. + + @retval RETURN_SUCCESS String is appended. + @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than + StrLen(Destination). + @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT + greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +AsciiStrCatS ( + IN OUT CHAR8 *Destination, + IN UINTN DestMax, + IN CONST CHAR8 *Source + ); + +/** + Appends not more than Length successive char from the string pointed to by + Source to the end of the string pointed to by Destination. If no null char is + copied from Source, then Destination[StrLen(Destination) + Length] is always + set to null. + + This function is similar as strncat_s defined in C11. + + If an error is returned, then the Destination is unmodified. + + @param Destination A pointer to a Null-terminated Ascii string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + @param Source A pointer to a Null-terminated Ascii string. + @param Length The maximum number of Ascii characters to copy. + + @retval RETURN_SUCCESS String is appended. + @retval RETURN_BAD_BUFFER_SIZE If DestMax is NOT greater than + StrLen(Destination). + @retval RETURN_BUFFER_TOO_SMALL If (DestMax - StrLen(Destination)) is NOT + greater than MIN(StrLen(Source), Length). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. +**/ +RETURN_STATUS +EFIAPI +AsciiStrnCatS ( + IN OUT CHAR8 *Destination, + IN UINTN DestMax, + IN CONST CHAR8 *Source, + IN UINTN Length + ); + +/** + Convert a Null-terminated Ascii decimal string to a value of type UINTN. + + This function outputs a value of type UINTN by interpreting the contents of + the Ascii string specified by String as a decimal number. The format of the + input Ascii string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before + [decimal digits]. The running zero in the beginning of [decimal digits] will + be ignored. Then, the function stops at the first character that is a not a + valid decimal character or a Null-terminator, whichever one comes first. + + If String has no valid decimal digits in the above format, then 0 is stored + at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINTN, then + MAX_UINTN is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + decimal digits right after the optional pad spaces, the value of String is + stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Ascii string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumAsciiStringLength is not zero, + and String contains more than + PcdMaximumAsciiStringLength Ascii + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINTN. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrDecimalToUintnS ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT UINTN *Data + ); + +/** + Convert a Null-terminated Ascii decimal string to a value of type UINT64. + + This function outputs a value of type UINT64 by interpreting the contents of + the Ascii string specified by String as a decimal number. The format of the + input Ascii string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before + [decimal digits]. The running zero in the beginning of [decimal digits] will + be ignored. Then, the function stops at the first character that is a not a + valid decimal character or a Null-terminator, whichever one comes first. + + If String has no valid decimal digits in the above format, then 0 is stored + at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINT64, then + MAX_UINT64 is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + decimal digits right after the optional pad spaces, the value of String is + stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Ascii string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumAsciiStringLength is not zero, + and String contains more than + PcdMaximumAsciiStringLength Ascii + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINT64. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrDecimalToUint64S ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT UINT64 *Data + ); + +/** + Convert a Null-terminated Ascii hexadecimal string to a value of type UINTN. + + This function outputs a value of type UINTN by interpreting the contents of + the Ascii string specified by String as a hexadecimal number. The format of + the input Ascii string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If + "x" appears in the input string, it must be prefixed with at least one 0. The + function will ignore the pad space, which includes spaces or tab characters, + before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or + [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or + the first valid hexadecimal digit. Then, the function stops at the first + character that is a not a valid hexadecimal character or Null-terminator, + whichever on comes first. + + If String has no valid hexadecimal digits in the above format, then 0 is + stored at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINTN, then + MAX_UINTN is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + hexadecimal digits right after the optional pad spaces, the value of String + is stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Ascii string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumAsciiStringLength is not zero, + and String contains more than + PcdMaximumAsciiStringLength Ascii + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINTN. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrHexToUintnS ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT UINTN *Data + ); + +/** + Convert a Null-terminated Ascii hexadecimal string to a value of type UINT64. + + This function outputs a value of type UINT64 by interpreting the contents of + the Ascii string specified by String as a hexadecimal number. The format of + the input Ascii string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If + "x" appears in the input string, it must be prefixed with at least one 0. The + function will ignore the pad space, which includes spaces or tab characters, + before [zeros], [x] or [hexadecimal digits]. The running zero before [x] or + [hexadecimal digits] will be ignored. Then, the decoding starts after [x] or + the first valid hexadecimal digit. Then, the function stops at the first + character that is a not a valid hexadecimal character or Null-terminator, + whichever on comes first. + + If String has no valid hexadecimal digits in the above format, then 0 is + stored at the location pointed to by Data. + If the number represented by String exceeds the range defined by UINT64, then + MAX_UINT64 is stored at the location pointed to by Data. + + If EndPointer is not NULL, a pointer to the character that stopped the scan + is stored at the location pointed to by EndPointer. If String has no valid + hexadecimal digits right after the optional pad spaces, the value of String + is stored at the location pointed to by EndPointer. + + @param String Pointer to a Null-terminated Ascii string. + @param EndPointer Pointer to character that stops scan. + @param Data Pointer to the converted value. + + @retval RETURN_SUCCESS Value is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If PcdMaximumAsciiStringLength is not zero, + and String contains more than + PcdMaximumAsciiStringLength Ascii + characters, not including the + Null-terminator. + @retval RETURN_UNSUPPORTED If the number represented by String exceeds + the range defined by UINT64. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrHexToUint64S ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT UINT64 *Data + ); + + +/** + Returns the length of a Null-terminated Unicode string. + + This function returns the number of Unicode characters in the Null-terminated + Unicode string specified by String. + + If String is NULL, then ASSERT(). + If String is not aligned on a 16-bit boundary, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the + Null-terminator, then ASSERT(). + + @param String Pointer to a Null-terminated Unicode string. + + @return The length of String. + +**/ +UINTN +EFIAPI +StrLen ( + IN CONST CHAR16 *String + ); + + +/** + Returns the size of a Null-terminated Unicode string in bytes, including the + Null terminator. + + This function returns the size, in bytes, of the Null-terminated Unicode string + specified by String. + + If String is NULL, then ASSERT(). + If String is not aligned on a 16-bit boundary, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the + Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + + @return The size of String. + +**/ +UINTN +EFIAPI +StrSize ( + IN CONST CHAR16 *String + ); + + +/** + Compares two Null-terminated Unicode strings, and returns the difference + between the first mismatched Unicode characters. + + This function compares the Null-terminated Unicode string FirstString to the + Null-terminated Unicode string SecondString. If FirstString is identical to + SecondString, then 0 is returned. Otherwise, the value returned is the first + mismatched Unicode character in SecondString subtracted from the first + mismatched Unicode character in FirstString. + + If FirstString is NULL, then ASSERT(). + If FirstString is not aligned on a 16-bit boundary, then ASSERT(). + If SecondString is NULL, then ASSERT(). + If SecondString is not aligned on a 16-bit boundary, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more + than PcdMaximumUnicodeStringLength Unicode characters not including the + Null-terminator, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more + than PcdMaximumUnicodeStringLength Unicode characters, not including the + Null-terminator, then ASSERT(). + + @param FirstString The pointer to a Null-terminated Unicode string. + @param SecondString The pointer to a Null-terminated Unicode string. + + @retval 0 FirstString is identical to SecondString. + @return others FirstString is not identical to SecondString. + +**/ +INTN +EFIAPI +StrCmp ( + IN CONST CHAR16 *FirstString, + IN CONST CHAR16 *SecondString + ); + + +/** + Compares up to a specified length the contents of two Null-terminated Unicode strings, + and returns the difference between the first mismatched Unicode characters. + + This function compares the Null-terminated Unicode string FirstString to the + Null-terminated Unicode string SecondString. At most, Length Unicode + characters will be compared. If Length is 0, then 0 is returned. If + FirstString is identical to SecondString, then 0 is returned. Otherwise, the + value returned is the first mismatched Unicode character in SecondString + subtracted from the first mismatched Unicode character in FirstString. + + If Length > 0 and FirstString is NULL, then ASSERT(). + If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT(). + If Length > 0 and SecondString is NULL, then ASSERT(). + If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and Length is greater than + PcdMaximumUnicodeStringLength, then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than + PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator, + then ASSERT(). + If PcdMaximumUnicodeStringLength is not zero, and SecondString contains more than + PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator, + then ASSERT(). + + @param FirstString The pointer to a Null-terminated Unicode string. + @param SecondString The pointer to a Null-terminated Unicode string. + @param Length The maximum number of Unicode characters to compare. + + @retval 0 FirstString is identical to SecondString. + @return others FirstString is not identical to SecondString. + +**/ +INTN +EFIAPI +StrnCmp ( + IN CONST CHAR16 *FirstString, + IN CONST CHAR16 *SecondString, + IN UINTN Length + ); + + +/** + Returns the first occurrence of a Null-terminated Unicode sub-string + in a Null-terminated Unicode string. + + This function scans the contents of the Null-terminated Unicode string + specified by String and returns the first occurrence of SearchString. + If SearchString is not found in String, then NULL is returned. If + the length of SearchString is zero, then String is returned. + + If String is NULL, then ASSERT(). + If String is not aligned on a 16-bit boundary, then ASSERT(). + If SearchString is NULL, then ASSERT(). + If SearchString is not aligned on a 16-bit boundary, then ASSERT(). + + If PcdMaximumUnicodeStringLength is not zero, and SearchString + or String contains more than PcdMaximumUnicodeStringLength Unicode + characters, not including the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + @param SearchString The pointer to a Null-terminated Unicode string to search for. + + @retval NULL If the SearchString does not appear in String. + @return others If there is a match. + +**/ +CHAR16 * +EFIAPI +StrStr ( + IN CONST CHAR16 *String, + IN CONST CHAR16 *SearchString + ); + +/** + Convert a Null-terminated Unicode decimal string to a value of + type UINTN. + + This function returns a value of type UINTN by interpreting the contents + of the Unicode string specified by String as a decimal number. The format + of the input Unicode string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The + function will ignore the pad space, which includes spaces or + tab characters, before [decimal digits]. The running zero in the + beginning of [decimal digits] will be ignored. Then, the function + stops at the first character that is a not a valid decimal character + or a Null-terminator, whichever one comes first. + + If String is NULL, then ASSERT(). + If String is not aligned in a 16-bit boundary, then ASSERT(). + If String has only pad spaces, then 0 is returned. + If String has no pad spaces or valid decimal digits, + then 0 is returned. + If the number represented by String overflows according + to the range defined by UINTN, then MAX_UINTN is returned. + + If PcdMaximumUnicodeStringLength is not zero, and String contains + more than PcdMaximumUnicodeStringLength Unicode characters not including + the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + + @retval Value translated from String. + +**/ +UINTN +EFIAPI +StrDecimalToUintn ( + IN CONST CHAR16 *String + ); + +/** + Convert a Null-terminated Unicode decimal string to a value of + type UINT64. + + This function returns a value of type UINT64 by interpreting the contents + of the Unicode string specified by String as a decimal number. The format + of the input Unicode string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The + function will ignore the pad space, which includes spaces or + tab characters, before [decimal digits]. The running zero in the + beginning of [decimal digits] will be ignored. Then, the function + stops at the first character that is a not a valid decimal character + or a Null-terminator, whichever one comes first. + + If String is NULL, then ASSERT(). + If String is not aligned in a 16-bit boundary, then ASSERT(). + If String has only pad spaces, then 0 is returned. + If String has no pad spaces or valid decimal digits, + then 0 is returned. + If the number represented by String overflows according + to the range defined by UINT64, then MAX_UINT64 is returned. + + If PcdMaximumUnicodeStringLength is not zero, and String contains + more than PcdMaximumUnicodeStringLength Unicode characters not including + the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + + @retval Value translated from String. + +**/ +UINT64 +EFIAPI +StrDecimalToUint64 ( + IN CONST CHAR16 *String + ); + + +/** + Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN. + + This function returns a value of type UINTN by interpreting the contents + of the Unicode string specified by String as a hexadecimal number. + The format of the input Unicode string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. + If "x" appears in the input string, it must be prefixed with at least one 0. + The function will ignore the pad space, which includes spaces or tab characters, + before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or + [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the + first valid hexadecimal digit. Then, the function stops at the first character + that is a not a valid hexadecimal character or NULL, whichever one comes first. + + If String is NULL, then ASSERT(). + If String is not aligned in a 16-bit boundary, then ASSERT(). + If String has only pad spaces, then zero is returned. + If String has no leading pad spaces, leading zeros or valid hexadecimal digits, + then zero is returned. + If the number represented by String overflows according to the range defined by + UINTN, then MAX_UINTN is returned. + + If PcdMaximumUnicodeStringLength is not zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + + @retval Value translated from String. + +**/ +UINTN +EFIAPI +StrHexToUintn ( + IN CONST CHAR16 *String + ); + + +/** + Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64. + + This function returns a value of type UINT64 by interpreting the contents + of the Unicode string specified by String as a hexadecimal number. + The format of the input Unicode string String is + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. + If "x" appears in the input string, it must be prefixed with at least one 0. + The function will ignore the pad space, which includes spaces or tab characters, + before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or + [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the + first valid hexadecimal digit. Then, the function stops at the first character that is + a not a valid hexadecimal character or NULL, whichever one comes first. + + If String is NULL, then ASSERT(). + If String is not aligned in a 16-bit boundary, then ASSERT(). + If String has only pad spaces, then zero is returned. + If String has no leading pad spaces, leading zeros or valid hexadecimal digits, + then zero is returned. + If the number represented by String overflows according to the range defined by + UINT64, then MAX_UINT64 is returned. + + If PcdMaximumUnicodeStringLength is not zero, and String contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated Unicode string. + + @retval Value translated from String. + +**/ +UINT64 +EFIAPI +StrHexToUint64 ( + IN CONST CHAR16 *String + ); + +/** + Convert a Null-terminated Unicode string to IPv6 address and prefix length. + + This function outputs a value of type IPv6_ADDRESS and may output a value + of type UINT8 by interpreting the contents of the Unicode string specified + by String. The format of the input Unicode string String is as follows: + + X:X:X:X:X:X:X:X[/P] + + X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and + [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low + memory address and high byte is stored in high memory address. P contains decimal + digit characters in the range [0-9]. The running zero in the beginning of P will + be ignored. /P is optional. + + When /P is not in the String, the function stops at the first character that is + not a valid hexadecimal digit character after eight X's are converted. + + When /P is in the String, the function stops at the first character that is not + a valid decimal digit character after P is converted. + + "::" can be used to compress one or more groups of X when X contains only 0. + The "::" can only appear once in the String. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If EndPointer is not NULL and Address is translated from String, a pointer + to the character that stopped the scan is stored at the location pointed to + by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Address Pointer to the converted IPv6 address. + @param PrefixLength Pointer to the converted IPv6 address prefix + length. MAX_UINT8 is returned when /P is + not in the String. + + @retval RETURN_SUCCESS Address is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal + digit characters. + If String contains "::" and number of X + is not less than 8. + If P starts with character that is not a + valid decimal digit character. + If the decimal number converted from P + exceeds 128. + +**/ +RETURN_STATUS +EFIAPI +StrToIpv6Address ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT IPv6_ADDRESS *Address, + OUT UINT8 *PrefixLength OPTIONAL + ); + +/** + Convert a Null-terminated Unicode string to IPv4 address and prefix length. + + This function outputs a value of type IPv4_ADDRESS and may output a value + of type UINT8 by interpreting the contents of the Unicode string specified + by String. The format of the input Unicode string String is as follows: + + D.D.D.D[/P] + + D and P are decimal digit characters in the range [0-9]. The running zero in + the beginning of D and P will be ignored. /P is optional. + + When /P is not in the String, the function stops at the first character that is + not a valid decimal digit character after four D's are converted. + + When /P is in the String, the function stops at the first character that is not + a valid decimal digit character after P is converted. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + If EndPointer is not NULL and Address is translated from String, a pointer + to the character that stopped the scan is stored at the location pointed to + by EndPointer. + + @param String Pointer to a Null-terminated Unicode string. + @param EndPointer Pointer to character that stops scan. + @param Address Pointer to the converted IPv4 address. + @param PrefixLength Pointer to the converted IPv4 address prefix + length. MAX_UINT8 is returned when /P is + not in the String. + + @retval RETURN_SUCCESS Address is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If String is not in the correct format. + If any decimal number converted from D + exceeds 255. + If the decimal number converted from P + exceeds 32. + +**/ +RETURN_STATUS +EFIAPI +StrToIpv4Address ( + IN CONST CHAR16 *String, + OUT CHAR16 **EndPointer, OPTIONAL + OUT IPv4_ADDRESS *Address, + OUT UINT8 *PrefixLength OPTIONAL + ); + +#define GUID_STRING_LENGTH 36 + +/** + Convert a Null-terminated Unicode GUID string to a value of type + EFI_GUID. + + This function outputs a GUID value by interpreting the contents of + the Unicode string specified by String. The format of the input + Unicode string String consists of 36 characters, as follows: + + aabbccdd-eeff-gghh-iijj-kkllmmnnoopp + + The pairs aa - pp are two characters in the range [0-9], [a-f] and + [A-F], with each pair representing a single byte hexadecimal value. + + The mapping between String and the EFI_GUID structure is as follows: + aa Data1[24:31] + bb Data1[16:23] + cc Data1[8:15] + dd Data1[0:7] + ee Data2[8:15] + ff Data2[0:7] + gg Data3[8:15] + hh Data3[0:7] + ii Data4[0:7] + jj Data4[8:15] + kk Data4[16:23] + ll Data4[24:31] + mm Data4[32:39] + nn Data4[40:47] + oo Data4[48:55] + pp Data4[56:63] + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + @param String Pointer to a Null-terminated Unicode string. + @param Guid Pointer to the converted GUID. + + @retval RETURN_SUCCESS Guid is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If String is not as the above format. + +**/ +RETURN_STATUS +EFIAPI +StrToGuid ( + IN CONST CHAR16 *String, + OUT GUID *Guid + ); + +/** + Convert a Null-terminated Unicode hexadecimal string to a byte array. + + This function outputs a byte array by interpreting the contents of + the Unicode string specified by String in hexadecimal format. The format of + the input Unicode string String is: + + [XX]* + + X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F]. + The function decodes every two hexadecimal digit characters as one byte. The + decoding stops after Length of characters and outputs Buffer containing + (Length / 2) bytes. + + If String is not aligned in a 16-bit boundary, then ASSERT(). + + @param String Pointer to a Null-terminated Unicode string. + @param Length The number of Unicode characters to decode. + @param Buffer Pointer to the converted bytes array. + @param MaxBufferSize The maximum size of Buffer. + + @retval RETURN_SUCCESS Buffer is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If Length is not multiple of 2. + If PcdMaximumUnicodeStringLength is not zero, + and Length is greater than + PcdMaximumUnicodeStringLength. + @retval RETURN_UNSUPPORTED If Length of characters from String contain + a character that is not valid hexadecimal + digit characters, or a Null-terminator. + @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2). +**/ +RETURN_STATUS +EFIAPI +StrHexToBytes ( + IN CONST CHAR16 *String, + IN UINTN Length, + OUT UINT8 *Buffer, + IN UINTN MaxBufferSize + ); + + +/** + Convert a Null-terminated Unicode string to a Null-terminated + ASCII string. + + This function is similar to AsciiStrCpyS. + + This function converts the content of the Unicode string Source + to the ASCII string Destination by copying the lower 8 bits of + each Unicode character. The function terminates the ASCII string + Destination by appending a Null-terminator character at the end. + + The caller is responsible to make sure Destination points to a buffer with size + equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes. + + If any Unicode characters in Source contain non-zero value in + the upper 8 bits, then ASSERT(). + + If Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Source The pointer to a Null-terminated Unicode string. + @param Destination The pointer to a Null-terminated ASCII string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + + @retval RETURN_SUCCESS String is converted. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. + +**/ +RETURN_STATUS +EFIAPI +UnicodeStrToAsciiStrS ( + IN CONST CHAR16 *Source, + OUT CHAR8 *Destination, + IN UINTN DestMax + ); + +/** + Convert not more than Length successive characters from a Null-terminated + Unicode string to a Null-terminated Ascii string. If no null char is copied + from Source, then Destination[Length] is always set to null. + + This function converts not more than Length successive characters from the + Unicode string Source to the Ascii string Destination by copying the lower 8 + bits of each Unicode character. The function terminates the Ascii string + Destination by appending a Null-terminator character at the end. + + The caller is responsible to make sure Destination points to a buffer with size + equal or greater than ((StrLen (Source) + 1) * sizeof (CHAR8)) in bytes. + + If any Unicode characters in Source contain non-zero value in the upper 8 + bits, then ASSERT(). + If Source is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Source The pointer to a Null-terminated Unicode string. + @param Length The maximum number of Unicode characters to + convert. + @param Destination The pointer to a Null-terminated Ascii string. + @param DestMax The maximum number of Destination Ascii + char, including terminating null char. + @param DestinationLength The number of Unicode characters converted. + + @retval RETURN_SUCCESS String is converted. + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If DestinationLength is NULL. + If PcdMaximumAsciiStringLength is not zero, + and Length or DestMax is greater than + PcdMaximumAsciiStringLength. + If PcdMaximumUnicodeStringLength is not + zero, and Length or DestMax is greater than + PcdMaximumUnicodeStringLength. + If DestMax is 0. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than + MIN(StrLen(Source), Length). + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. + +**/ +RETURN_STATUS +EFIAPI +UnicodeStrnToAsciiStrS ( + IN CONST CHAR16 *Source, + IN UINTN Length, + OUT CHAR8 *Destination, + IN UINTN DestMax, + OUT UINTN *DestinationLength + ); + + +/** + Returns the length of a Null-terminated ASCII string. + + This function returns the number of ASCII characters in the Null-terminated + ASCII string specified by String. + + If Length > 0 and Destination is NULL, then ASSERT(). + If Length > 0 and Source is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and String contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @return The length of String. + +**/ +UINTN +EFIAPI +AsciiStrLen ( + IN CONST CHAR8 *String + ); + + +/** + Returns the size of a Null-terminated ASCII string in bytes, including the + Null terminator. + + This function returns the size, in bytes, of the Null-terminated ASCII string + specified by String. + + If String is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and String contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @return The size of String. + +**/ +UINTN +EFIAPI +AsciiStrSize ( + IN CONST CHAR8 *String + ); + + +/** + Compares two Null-terminated ASCII strings, and returns the difference + between the first mismatched ASCII characters. + + This function compares the Null-terminated ASCII string FirstString to the + Null-terminated ASCII string SecondString. If FirstString is identical to + SecondString, then 0 is returned. Otherwise, the value returned is the first + mismatched ASCII character in SecondString subtracted from the first + mismatched ASCII character in FirstString. + + If FirstString is NULL, then ASSERT(). + If SecondString is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and FirstString contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and SecondString contains more + than PcdMaximumAsciiStringLength ASCII characters not including the + Null-terminator, then ASSERT(). + + @param FirstString The pointer to a Null-terminated ASCII string. + @param SecondString The pointer to a Null-terminated ASCII string. + + @retval ==0 FirstString is identical to SecondString. + @retval !=0 FirstString is not identical to SecondString. + +**/ +INTN +EFIAPI +AsciiStrCmp ( + IN CONST CHAR8 *FirstString, + IN CONST CHAR8 *SecondString + ); + + +/** + Performs a case insensitive comparison of two Null-terminated ASCII strings, + and returns the difference between the first mismatched ASCII characters. + + This function performs a case insensitive comparison of the Null-terminated + ASCII string FirstString to the Null-terminated ASCII string SecondString. If + FirstString is identical to SecondString, then 0 is returned. Otherwise, the + value returned is the first mismatched lower case ASCII character in + SecondString subtracted from the first mismatched lower case ASCII character + in FirstString. + + If FirstString is NULL, then ASSERT(). + If SecondString is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and FirstString contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + If PcdMaximumAsciiStringLength is not zero and SecondString contains more + than PcdMaximumAsciiStringLength ASCII characters not including the + Null-terminator, then ASSERT(). + + @param FirstString The pointer to a Null-terminated ASCII string. + @param SecondString The pointer to a Null-terminated ASCII string. + + @retval ==0 FirstString is identical to SecondString using case insensitive + comparisons. + @retval !=0 FirstString is not identical to SecondString using case + insensitive comparisons. + +**/ +INTN +EFIAPI +AsciiStriCmp ( + IN CONST CHAR8 *FirstString, + IN CONST CHAR8 *SecondString + ); + + +/** + Compares two Null-terminated ASCII strings with maximum lengths, and returns + the difference between the first mismatched ASCII characters. + + This function compares the Null-terminated ASCII string FirstString to the + Null-terminated ASCII string SecondString. At most, Length ASCII characters + will be compared. If Length is 0, then 0 is returned. If FirstString is + identical to SecondString, then 0 is returned. Otherwise, the value returned + is the first mismatched ASCII character in SecondString subtracted from the + first mismatched ASCII character in FirstString. + + If Length > 0 and FirstString is NULL, then ASSERT(). + If Length > 0 and SecondString is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, and Length is greater than + PcdMaximumAsciiStringLength, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than + PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator, + then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, and SecondString contains more than + PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator, + then ASSERT(). + + @param FirstString The pointer to a Null-terminated ASCII string. + @param SecondString The pointer to a Null-terminated ASCII string. + @param Length The maximum number of ASCII characters for compare. + + @retval ==0 FirstString is identical to SecondString. + @retval !=0 FirstString is not identical to SecondString. + +**/ +INTN +EFIAPI +AsciiStrnCmp ( + IN CONST CHAR8 *FirstString, + IN CONST CHAR8 *SecondString, + IN UINTN Length + ); + + +/** + Returns the first occurrence of a Null-terminated ASCII sub-string + in a Null-terminated ASCII string. + + This function scans the contents of the ASCII string specified by String + and returns the first occurrence of SearchString. If SearchString is not + found in String, then NULL is returned. If the length of SearchString is zero, + then String is returned. + + If String is NULL, then ASSERT(). + If SearchString is NULL, then ASSERT(). + + If PcdMaximumAsciiStringLength is not zero, and SearchString or + String contains more than PcdMaximumAsciiStringLength Unicode characters + not including the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + @param SearchString The pointer to a Null-terminated ASCII string to search for. + + @retval NULL If the SearchString does not appear in String. + @retval others If there is a match return the first occurrence of SearchingString. + If the length of SearchString is zero,return String. + +**/ +CHAR8 * +EFIAPI +AsciiStrStr ( + IN CONST CHAR8 *String, + IN CONST CHAR8 *SearchString + ); + + +/** + Convert a Null-terminated ASCII decimal string to a value of type + UINTN. + + This function returns a value of type UINTN by interpreting the contents + of the ASCII string String as a decimal number. The format of the input + ASCII string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before the digits. + The running zero in the beginning of [decimal digits] will be ignored. Then, the + function stops at the first character that is a not a valid decimal character or + Null-terminator, whichever on comes first. + + If String has only pad spaces, then 0 is returned. + If String has no pad spaces or valid decimal digits, then 0 is returned. + If the number represented by String overflows according to the range defined by + UINTN, then MAX_UINTN is returned. + If String is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, and String contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @retval The value translated from String. + +**/ +UINTN +EFIAPI +AsciiStrDecimalToUintn ( + IN CONST CHAR8 *String + ); + + +/** + Convert a Null-terminated ASCII decimal string to a value of type + UINT64. + + This function returns a value of type UINT64 by interpreting the contents + of the ASCII string String as a decimal number. The format of the input + ASCII string String is: + + [spaces] [decimal digits]. + + The valid decimal digit character is in the range [0-9]. The function will + ignore the pad space, which includes spaces or tab characters, before the digits. + The running zero in the beginning of [decimal digits] will be ignored. Then, the + function stops at the first character that is a not a valid decimal character or + Null-terminator, whichever on comes first. + + If String has only pad spaces, then 0 is returned. + If String has no pad spaces or valid decimal digits, then 0 is returned. + If the number represented by String overflows according to the range defined by + UINT64, then MAX_UINT64 is returned. + If String is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, and String contains more than + PcdMaximumAsciiStringLength ASCII characters not including the Null-terminator, + then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @retval Value translated from String. + +**/ +UINT64 +EFIAPI +AsciiStrDecimalToUint64 ( + IN CONST CHAR8 *String + ); + + +/** + Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN. + + This function returns a value of type UINTN by interpreting the contents of + the ASCII string String as a hexadecimal number. The format of the input ASCII + string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x" + appears in the input string, it must be prefixed with at least one 0. The function + will ignore the pad space, which includes spaces or tab characters, before [zeros], + [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits] + will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal + digit. Then, the function stops at the first character that is a not a valid + hexadecimal character or Null-terminator, whichever on comes first. + + If String has only pad spaces, then 0 is returned. + If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then + 0 is returned. + + If the number represented by String overflows according to the range defined by UINTN, + then MAX_UINTN is returned. + If String is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, + and String contains more than PcdMaximumAsciiStringLength ASCII characters not including + the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @retval Value translated from String. + +**/ +UINTN +EFIAPI +AsciiStrHexToUintn ( + IN CONST CHAR8 *String + ); + + +/** + Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64. + + This function returns a value of type UINT64 by interpreting the contents of + the ASCII string String as a hexadecimal number. The format of the input ASCII + string String is: + + [spaces][zeros][x][hexadecimal digits]. + + The valid hexadecimal digit character is in the range [0-9], [a-f] and [A-F]. + The prefix "0x" is optional. Both "x" and "X" is allowed in "0x" prefix. If "x" + appears in the input string, it must be prefixed with at least one 0. The function + will ignore the pad space, which includes spaces or tab characters, before [zeros], + [x] or [hexadecimal digits]. The running zero before [x] or [hexadecimal digits] + will be ignored. Then, the decoding starts after [x] or the first valid hexadecimal + digit. Then, the function stops at the first character that is a not a valid + hexadecimal character or Null-terminator, whichever on comes first. + + If String has only pad spaces, then 0 is returned. + If String has no leading pad spaces, leading zeros or valid hexadecimal digits, then + 0 is returned. + + If the number represented by String overflows according to the range defined by UINT64, + then MAX_UINT64 is returned. + If String is NULL, then ASSERT(). + If PcdMaximumAsciiStringLength is not zero, + and String contains more than PcdMaximumAsciiStringLength ASCII characters not including + the Null-terminator, then ASSERT(). + + @param String The pointer to a Null-terminated ASCII string. + + @retval Value translated from String. + +**/ +UINT64 +EFIAPI +AsciiStrHexToUint64 ( + IN CONST CHAR8 *String + ); + +/** + Convert a Null-terminated ASCII string to IPv6 address and prefix length. + + This function outputs a value of type IPv6_ADDRESS and may output a value + of type UINT8 by interpreting the contents of the ASCII string specified + by String. The format of the input ASCII string String is as follows: + + X:X:X:X:X:X:X:X[/P] + + X contains one to four hexadecimal digit characters in the range [0-9], [a-f] and + [A-F]. X is converted to a value of type UINT16, whose low byte is stored in low + memory address and high byte is stored in high memory address. P contains decimal + digit characters in the range [0-9]. The running zero in the beginning of P will + be ignored. /P is optional. + + When /P is not in the String, the function stops at the first character that is + not a valid hexadecimal digit character after eight X's are converted. + + When /P is in the String, the function stops at the first character that is not + a valid decimal digit character after P is converted. + + "::" can be used to compress one or more groups of X when X contains only 0. + The "::" can only appear once in the String. + + If EndPointer is not NULL and Address is translated from String, a pointer + to the character that stopped the scan is stored at the location pointed to + by EndPointer. + + @param String Pointer to a Null-terminated ASCII string. + @param EndPointer Pointer to character that stops scan. + @param Address Pointer to the converted IPv6 address. + @param PrefixLength Pointer to the converted IPv6 address prefix + length. MAX_UINT8 is returned when /P is + not in the String. + + @retval RETURN_SUCCESS Address is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If X contains more than four hexadecimal + digit characters. + If String contains "::" and number of X + is not less than 8. + If P starts with character that is not a + valid decimal digit character. + If the decimal number converted from P + exceeds 128. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrToIpv6Address ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT IPv6_ADDRESS *Address, + OUT UINT8 *PrefixLength OPTIONAL + ); + +/** + Convert a Null-terminated ASCII string to IPv4 address and prefix length. + + This function outputs a value of type IPv4_ADDRESS and may output a value + of type UINT8 by interpreting the contents of the ASCII string specified + by String. The format of the input ASCII string String is as follows: + + D.D.D.D[/P] + + D and P are decimal digit characters in the range [0-9]. The running zero in + the beginning of D and P will be ignored. /P is optional. + + When /P is not in the String, the function stops at the first character that is + not a valid decimal digit character after four D's are converted. + + When /P is in the String, the function stops at the first character that is not + a valid decimal digit character after P is converted. + + If EndPointer is not NULL and Address is translated from String, a pointer + to the character that stopped the scan is stored at the location pointed to + by EndPointer. + + @param String Pointer to a Null-terminated ASCII string. + @param EndPointer Pointer to character that stops scan. + @param Address Pointer to the converted IPv4 address. + @param PrefixLength Pointer to the converted IPv4 address prefix + length. MAX_UINT8 is returned when /P is + not in the String. + + @retval RETURN_SUCCESS Address is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If String is not in the correct format. + If any decimal number converted from D + exceeds 255. + If the decimal number converted from P + exceeds 32. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrToIpv4Address ( + IN CONST CHAR8 *String, + OUT CHAR8 **EndPointer, OPTIONAL + OUT IPv4_ADDRESS *Address, + OUT UINT8 *PrefixLength OPTIONAL + ); + +/** + Convert a Null-terminated ASCII GUID string to a value of type + EFI_GUID. + + This function outputs a GUID value by interpreting the contents of + the ASCII string specified by String. The format of the input + ASCII string String consists of 36 characters, as follows: + + aabbccdd-eeff-gghh-iijj-kkllmmnnoopp + + The pairs aa - pp are two characters in the range [0-9], [a-f] and + [A-F], with each pair representing a single byte hexadecimal value. + + The mapping between String and the EFI_GUID structure is as follows: + aa Data1[24:31] + bb Data1[16:23] + cc Data1[8:15] + dd Data1[0:7] + ee Data2[8:15] + ff Data2[0:7] + gg Data3[8:15] + hh Data3[0:7] + ii Data4[0:7] + jj Data4[8:15] + kk Data4[16:23] + ll Data4[24:31] + mm Data4[32:39] + nn Data4[40:47] + oo Data4[48:55] + pp Data4[56:63] + + @param String Pointer to a Null-terminated ASCII string. + @param Guid Pointer to the converted GUID. + + @retval RETURN_SUCCESS Guid is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + @retval RETURN_UNSUPPORTED If String is not as the above format. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrToGuid ( + IN CONST CHAR8 *String, + OUT GUID *Guid + ); + +/** + Convert a Null-terminated ASCII hexadecimal string to a byte array. + + This function outputs a byte array by interpreting the contents of + the ASCII string specified by String in hexadecimal format. The format of + the input ASCII string String is: + + [XX]* + + X is a hexadecimal digit character in the range [0-9], [a-f] and [A-F]. + The function decodes every two hexadecimal digit characters as one byte. The + decoding stops after Length of characters and outputs Buffer containing + (Length / 2) bytes. + + @param String Pointer to a Null-terminated ASCII string. + @param Length The number of ASCII characters to decode. + @param Buffer Pointer to the converted bytes array. + @param MaxBufferSize The maximum size of Buffer. + + @retval RETURN_SUCCESS Buffer is translated from String. + @retval RETURN_INVALID_PARAMETER If String is NULL. + If Data is NULL. + If Length is not multiple of 2. + If PcdMaximumAsciiStringLength is not zero, + and Length is greater than + PcdMaximumAsciiStringLength. + @retval RETURN_UNSUPPORTED If Length of characters from String contain + a character that is not valid hexadecimal + digit characters, or a Null-terminator. + @retval RETURN_BUFFER_TOO_SMALL If MaxBufferSize is less than (Length / 2). +**/ +RETURN_STATUS +EFIAPI +AsciiStrHexToBytes ( + IN CONST CHAR8 *String, + IN UINTN Length, + OUT UINT8 *Buffer, + IN UINTN MaxBufferSize + ); + + +/** + Convert one Null-terminated ASCII string to a Null-terminated + Unicode string. + + This function is similar to StrCpyS. + + This function converts the contents of the ASCII string Source to the Unicode + string Destination. The function terminates the Unicode string Destination by + appending a Null-terminator character at the end. + + The caller is responsible to make sure Destination points to a buffer with size + equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes. + + If Destination is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then the Destination is unmodified. + + @param Source The pointer to a Null-terminated ASCII string. + @param Destination The pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode + char, including terminating null char. + + @retval RETURN_SUCCESS String is converted. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than StrLen(Source). + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If PcdMaximumUnicodeStringLength is not zero, + and DestMax is greater than + PcdMaximumUnicodeStringLength. + If PcdMaximumAsciiStringLength is not zero, + and DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrToUnicodeStrS ( + IN CONST CHAR8 *Source, + OUT CHAR16 *Destination, + IN UINTN DestMax + ); + +/** + Convert not more than Length successive characters from a Null-terminated + Ascii string to a Null-terminated Unicode string. If no null char is copied + from Source, then Destination[Length] is always set to null. + + This function converts not more than Length successive characters from the + Ascii string Source to the Unicode string Destination. The function + terminates the Unicode string Destination by appending a Null-terminator + character at the end. + + The caller is responsible to make sure Destination points to a buffer with + size not smaller than + ((MIN(AsciiStrLen(Source), Length) + 1) * sizeof (CHAR8)) in bytes. + + If Destination is not aligned on a 16-bit boundary, then ASSERT(). + + If an error is returned, then Destination and DestinationLength are + unmodified. + + @param Source The pointer to a Null-terminated Ascii string. + @param Length The maximum number of Ascii characters to convert. + @param Destination The pointer to a Null-terminated Unicode string. + @param DestMax The maximum number of Destination Unicode char, + including terminating null char. + @param DestinationLength The number of Ascii characters converted. + + @retval RETURN_SUCCESS String is converted. + @retval RETURN_INVALID_PARAMETER If Destination is NULL. + If Source is NULL. + If DestinationLength is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and Length or DestMax is greater than + PcdMaximumUnicodeStringLength. + If PcdMaximumAsciiStringLength is not zero, + and Length or DestMax is greater than + PcdMaximumAsciiStringLength. + If DestMax is 0. + @retval RETURN_BUFFER_TOO_SMALL If DestMax is NOT greater than + MIN(AsciiStrLen(Source), Length). + @retval RETURN_ACCESS_DENIED If Source and Destination overlap. + +**/ +RETURN_STATUS +EFIAPI +AsciiStrnToUnicodeStrS ( + IN CONST CHAR8 *Source, + IN UINTN Length, + OUT CHAR16 *Destination, + IN UINTN DestMax, + OUT UINTN *DestinationLength + ); + +/** + Convert a Unicode character to upper case only if + it maps to a valid small-case ASCII character. + + This internal function only deal with Unicode character + which maps to a valid small-case ASCII character, i.e. + L'a' to L'z'. For other Unicode character, the input character + is returned directly. + + @param Char The character to convert. + + @retval LowerCharacter If the Char is with range L'a' to L'z'. + @retval Unchanged Otherwise. + +**/ +CHAR16 +EFIAPI +CharToUpper ( + IN CHAR16 Char + ); + +/** + Converts a lowercase Ascii character to upper one. + + If Chr is lowercase Ascii character, then converts it to upper one. + + If Value >= 0xA0, then ASSERT(). + If (Value & 0x0F) >= 0x0A, then ASSERT(). + + @param Chr one Ascii character + + @return The uppercase value of Ascii character + +**/ +CHAR8 +EFIAPI +AsciiCharToUpper ( + IN CHAR8 Chr + ); + +/** + Convert binary data to a Base64 encoded ascii string based on RFC4648. + + Produce a Null-terminated Ascii string in the output buffer specified by Destination and DestinationSize. + The Ascii string is produced by converting the data string specified by Source and SourceLength. + + @param Source Input UINT8 data + @param SourceLength Number of UINT8 bytes of data + @param Destination Pointer to output string buffer + @param DestinationSize Size of ascii buffer. Set to 0 to get the size needed. + Caller is responsible for passing in buffer of DestinationSize + + @retval RETURN_SUCCESS When ascii buffer is filled in. + @retval RETURN_INVALID_PARAMETER If Source is NULL or DestinationSize is NULL. + @retval RETURN_INVALID_PARAMETER If SourceLength or DestinationSize is bigger than (MAX_ADDRESS - (UINTN)Destination). + @retval RETURN_BUFFER_TOO_SMALL If SourceLength is 0 and DestinationSize is <1. + @retval RETURN_BUFFER_TOO_SMALL If Destination is NULL or DestinationSize is smaller than required buffersize. + +**/ +RETURN_STATUS +EFIAPI +Base64Encode ( + IN CONST UINT8 *Source, + IN UINTN SourceLength, + OUT CHAR8 *Destination OPTIONAL, + IN OUT UINTN *DestinationSize + ); + +/** + Decode Base64 ASCII encoded data to 8-bit binary representation, based on + RFC4648. + + Decoding occurs according to "Table 1: The Base 64 Alphabet" in RFC4648. + + Whitespace is ignored at all positions: + - 0x09 ('\t') horizontal tab + - 0x0A ('\n') new line + - 0x0B ('\v') vertical tab + - 0x0C ('\f') form feed + - 0x0D ('\r') carriage return + - 0x20 (' ') space + + The minimum amount of required padding (with ASCII 0x3D, '=') is tolerated + and enforced at the end of the Base64 ASCII encoded data, and only there. + + Other characters outside of the encoding alphabet cause the function to + reject the Base64 ASCII encoded data. + + @param[in] Source Array of CHAR8 elements containing the Base64 + ASCII encoding. May be NULL if SourceSize is + zero. + + @param[in] SourceSize Number of CHAR8 elements in Source. + + @param[out] Destination Array of UINT8 elements receiving the decoded + 8-bit binary representation. Allocated by the + caller. May be NULL if DestinationSize is + zero on input. If NULL, decoding is + performed, but the 8-bit binary + representation is not stored. If non-NULL and + the function returns an error, the contents + of Destination are indeterminate. + + @param[in,out] DestinationSize On input, the number of UINT8 elements that + the caller allocated for Destination. On + output, if the function returns + RETURN_SUCCESS or RETURN_BUFFER_TOO_SMALL, + the number of UINT8 elements that are + required for decoding the Base64 ASCII + representation. If the function returns a + value different from both RETURN_SUCCESS and + RETURN_BUFFER_TOO_SMALL, then DestinationSize + is indeterminate on output. + + @retval RETURN_SUCCESS SourceSize CHAR8 elements at Source have + been decoded to on-output DestinationSize + UINT8 elements at Destination. Note that + RETURN_SUCCESS covers the case when + DestinationSize is zero on input, and + Source decodes to zero bytes (due to + containing at most ignored whitespace). + + @retval RETURN_BUFFER_TOO_SMALL The input value of DestinationSize is not + large enough for decoding SourceSize CHAR8 + elements at Source. The required number of + UINT8 elements has been stored to + DestinationSize. + + @retval RETURN_INVALID_PARAMETER DestinationSize is NULL. + + @retval RETURN_INVALID_PARAMETER Source is NULL, but SourceSize is not zero. + + @retval RETURN_INVALID_PARAMETER Destination is NULL, but DestinationSize is + not zero on input. + + @retval RETURN_INVALID_PARAMETER Source is non-NULL, and (Source + + SourceSize) would wrap around MAX_ADDRESS. + + @retval RETURN_INVALID_PARAMETER Destination is non-NULL, and (Destination + + DestinationSize) would wrap around + MAX_ADDRESS, as specified on input. + + @retval RETURN_INVALID_PARAMETER None of Source and Destination are NULL, + and CHAR8[SourceSize] at Source overlaps + UINT8[DestinationSize] at Destination, as + specified on input. + + @retval RETURN_INVALID_PARAMETER Invalid CHAR8 element encountered in + Source. +**/ +RETURN_STATUS +EFIAPI +Base64Decode ( + IN CONST CHAR8 *Source OPTIONAL, + IN UINTN SourceSize, + OUT UINT8 *Destination OPTIONAL, + IN OUT UINTN *DestinationSize + ); + +/** + Converts an 8-bit value to an 8-bit BCD value. + + Converts the 8-bit value specified by Value to BCD. The BCD value is + returned. + + If Value >= 100, then ASSERT(). + + @param Value The 8-bit value to convert to BCD. Range 0..99. + + @return The BCD value. + +**/ +UINT8 +EFIAPI +DecimalToBcd8 ( + IN UINT8 Value + ); + + +/** + Converts an 8-bit BCD value to an 8-bit value. + + Converts the 8-bit BCD value specified by Value to an 8-bit value. The 8-bit + value is returned. + + If Value >= 0xA0, then ASSERT(). + If (Value & 0x0F) >= 0x0A, then ASSERT(). + + @param Value The 8-bit BCD value to convert to an 8-bit value. + + @return The 8-bit value is returned. + +**/ +UINT8 +EFIAPI +BcdToDecimal8 ( + IN UINT8 Value + ); + +// +// File Path Manipulation Functions +// + +/** + Removes the last directory or file entry in a path. + + @param[in, out] Path The pointer to the path to modify. + + @retval FALSE Nothing was found to remove. + @retval TRUE A directory or file was removed. +**/ +BOOLEAN +EFIAPI +PathRemoveLastItem( + IN OUT CHAR16 *Path + ); + +/** + Function to clean up paths. + - Single periods in the path are removed. + - Double periods in the path are removed along with a single parent directory. + - Forward slashes L'/' are converted to backward slashes L'\'. + + This will be done inline and the existing buffer may be larger than required + upon completion. + + @param[in] Path The pointer to the string containing the path. + + @return Returns Path, otherwise returns NULL to indicate that an error has occurred. +**/ +CHAR16* +EFIAPI +PathCleanUpDirectories( + IN CHAR16 *Path + ); + +// +// Linked List Functions and Macros +// + +/** + Initializes the head node of a doubly linked list that is declared as a + global variable in a module. + + Initializes the forward and backward links of a new linked list. After + initializing a linked list with this macro, the other linked list functions + may be used to add and remove nodes from the linked list. This macro results + in smaller executables by initializing the linked list in the data section, + instead if calling the InitializeListHead() function to perform the + equivalent operation. + + @param ListHead The head note of a list to initialize. + +**/ +#define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)} + +/** + Iterates over each node in a doubly linked list using each node's forward link. + + @param Entry A pointer to a list node used as a loop cursor during iteration + @param ListHead The head node of the doubly linked list + +**/ +#define BASE_LIST_FOR_EACH(Entry, ListHead) \ + for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink) + +/** + Iterates over each node in a doubly linked list using each node's forward link + with safety against node removal. + + This macro uses NextEntry to temporarily store the next list node so the node + pointed to by Entry may be deleted in the current loop iteration step and + iteration can continue from the node pointed to by NextEntry. + + @param Entry A pointer to a list node used as a loop cursor during iteration + @param NextEntry A pointer to a list node used to temporarily store the next node + @param ListHead The head node of the doubly linked list + +**/ +#define BASE_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \ + for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\ + Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink) + +/** + Checks whether FirstEntry and SecondEntry are part of the same doubly-linked + list. + + If FirstEntry is NULL, then ASSERT(). + If FirstEntry->ForwardLink is NULL, then ASSERT(). + If FirstEntry->BackLink is NULL, then ASSERT(). + If SecondEntry is NULL, then ASSERT(); + If PcdMaximumLinkedListLength is not zero, and List contains more than + PcdMaximumLinkedListLength nodes, then ASSERT(). + + @param FirstEntry A pointer to a node in a linked list. + @param SecondEntry A pointer to the node to locate. + + @retval TRUE SecondEntry is in the same doubly-linked list as FirstEntry. + @retval FALSE SecondEntry isn't in the same doubly-linked list as FirstEntry, + or FirstEntry is invalid. + +**/ +BOOLEAN +EFIAPI +IsNodeInList ( + IN CONST LIST_ENTRY *FirstEntry, + IN CONST LIST_ENTRY *SecondEntry + ); + + +/** + Initializes the head node of a doubly linked list, and returns the pointer to + the head node of the doubly linked list. + + Initializes the forward and backward links of a new linked list. After + initializing a linked list with this function, the other linked list + functions may be used to add and remove nodes from the linked list. It is up + to the caller of this function to allocate the memory for ListHead. + + If ListHead is NULL, then ASSERT(). + + @param ListHead A pointer to the head node of a new doubly linked list. + + @return ListHead + +**/ +LIST_ENTRY * +EFIAPI +InitializeListHead ( + IN OUT LIST_ENTRY *ListHead + ); + + +/** + Adds a node to the beginning of a doubly linked list, and returns the pointer + to the head node of the doubly linked list. + + Adds the node Entry at the beginning of the doubly linked list denoted by + ListHead, and returns ListHead. + + If ListHead is NULL, then ASSERT(). + If Entry is NULL, then ASSERT(). + If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and prior to insertion the number + of nodes in ListHead, including the ListHead node, is greater than or + equal to PcdMaximumLinkedListLength, then ASSERT(). + + @param ListHead A pointer to the head node of a doubly linked list. + @param Entry A pointer to a node that is to be inserted at the beginning + of a doubly linked list. + + @return ListHead + +**/ +LIST_ENTRY * +EFIAPI +InsertHeadList ( + IN OUT LIST_ENTRY *ListHead, + IN OUT LIST_ENTRY *Entry + ); + + +/** + Adds a node to the end of a doubly linked list, and returns the pointer to + the head node of the doubly linked list. + + Adds the node Entry to the end of the doubly linked list denoted by ListHead, + and returns ListHead. + + If ListHead is NULL, then ASSERT(). + If Entry is NULL, then ASSERT(). + If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and prior to insertion the number + of nodes in ListHead, including the ListHead node, is greater than or + equal to PcdMaximumLinkedListLength, then ASSERT(). + + @param ListHead A pointer to the head node of a doubly linked list. + @param Entry A pointer to a node that is to be added at the end of the + doubly linked list. + + @return ListHead + +**/ +LIST_ENTRY * +EFIAPI +InsertTailList ( + IN OUT LIST_ENTRY *ListHead, + IN OUT LIST_ENTRY *Entry + ); + + +/** + Retrieves the first node of a doubly linked list. + + Returns the first node of a doubly linked list. List must have been + initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). + If List is empty, then List is returned. + + If List is NULL, then ASSERT(). + If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes + in List, including the List node, is greater than or equal to + PcdMaximumLinkedListLength, then ASSERT(). + + @param List A pointer to the head node of a doubly linked list. + + @return The first node of a doubly linked list. + @retval List The list is empty. + +**/ +LIST_ENTRY * +EFIAPI +GetFirstNode ( + IN CONST LIST_ENTRY *List + ); + + +/** + Retrieves the next node of a doubly linked list. + + Returns the node of a doubly linked list that follows Node. + List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE() + or InitializeListHead(). If List is empty, then List is returned. + + If List is NULL, then ASSERT(). + If Node is NULL, then ASSERT(). + If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and List contains more than + PcdMaximumLinkedListLength nodes, then ASSERT(). + If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT(). + + @param List A pointer to the head node of a doubly linked list. + @param Node A pointer to a node in the doubly linked list. + + @return The pointer to the next node if one exists. Otherwise List is returned. + +**/ +LIST_ENTRY * +EFIAPI +GetNextNode ( + IN CONST LIST_ENTRY *List, + IN CONST LIST_ENTRY *Node + ); + + +/** + Retrieves the previous node of a doubly linked list. + + Returns the node of a doubly linked list that precedes Node. + List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE() + or InitializeListHead(). If List is empty, then List is returned. + + If List is NULL, then ASSERT(). + If Node is NULL, then ASSERT(). + If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and List contains more than + PcdMaximumLinkedListLength nodes, then ASSERT(). + If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT(). + + @param List A pointer to the head node of a doubly linked list. + @param Node A pointer to a node in the doubly linked list. + + @return The pointer to the previous node if one exists. Otherwise List is returned. + +**/ +LIST_ENTRY * +EFIAPI +GetPreviousNode ( + IN CONST LIST_ENTRY *List, + IN CONST LIST_ENTRY *Node + ); + + +/** + Checks to see if a doubly linked list is empty or not. + + Checks to see if the doubly linked list is empty. If the linked list contains + zero nodes, this function returns TRUE. Otherwise, it returns FALSE. + + If ListHead is NULL, then ASSERT(). + If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes + in List, including the List node, is greater than or equal to + PcdMaximumLinkedListLength, then ASSERT(). + + @param ListHead A pointer to the head node of a doubly linked list. + + @retval TRUE The linked list is empty. + @retval FALSE The linked list is not empty. + +**/ +BOOLEAN +EFIAPI +IsListEmpty ( + IN CONST LIST_ENTRY *ListHead + ); + + +/** + Determines if a node in a doubly linked list is the head node of a the same + doubly linked list. This function is typically used to terminate a loop that + traverses all the nodes in a doubly linked list starting with the head node. + + Returns TRUE if Node is equal to List. Returns FALSE if Node is one of the + nodes in the doubly linked list specified by List. List must have been + initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). + + If List is NULL, then ASSERT(). + If Node is NULL, then ASSERT(). + If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(), + then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes + in List, including the List node, is greater than or equal to + PcdMaximumLinkedListLength, then ASSERT(). + If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal + to List, then ASSERT(). + + @param List A pointer to the head node of a doubly linked list. + @param Node A pointer to a node in the doubly linked list. + + @retval TRUE Node is the head of the doubly-linked list pointed by List. + @retval FALSE Node is not the head of the doubly-linked list pointed by List. + +**/ +BOOLEAN +EFIAPI +IsNull ( + IN CONST LIST_ENTRY *List, + IN CONST LIST_ENTRY *Node + ); + + +/** + Determines if a node the last node in a doubly linked list. + + Returns TRUE if Node is the last node in the doubly linked list specified by + List. Otherwise, FALSE is returned. List must have been initialized with + INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). + + If List is NULL, then ASSERT(). + If Node is NULL, then ASSERT(). + If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or + InitializeListHead(), then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes + in List, including the List node, is greater than or equal to + PcdMaximumLinkedListLength, then ASSERT(). + If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT(). + + @param List A pointer to the head node of a doubly linked list. + @param Node A pointer to a node in the doubly linked list. + + @retval TRUE Node is the last node in the linked list. + @retval FALSE Node is not the last node in the linked list. + +**/ +BOOLEAN +EFIAPI +IsNodeAtEnd ( + IN CONST LIST_ENTRY *List, + IN CONST LIST_ENTRY *Node + ); + + +/** + Swaps the location of two nodes in a doubly linked list, and returns the + first node after the swap. + + If FirstEntry is identical to SecondEntry, then SecondEntry is returned. + Otherwise, the location of the FirstEntry node is swapped with the location + of the SecondEntry node in a doubly linked list. SecondEntry must be in the + same double linked list as FirstEntry and that double linked list must have + been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). + SecondEntry is returned after the nodes are swapped. + + If FirstEntry is NULL, then ASSERT(). + If SecondEntry is NULL, then ASSERT(). + If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the + same linked list, then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes in the + linked list containing the FirstEntry and SecondEntry nodes, including + the FirstEntry and SecondEntry nodes, is greater than or equal to + PcdMaximumLinkedListLength, then ASSERT(). + + @param FirstEntry A pointer to a node in a linked list. + @param SecondEntry A pointer to another node in the same linked list. + + @return SecondEntry. + +**/ +LIST_ENTRY * +EFIAPI +SwapListEntries ( + IN OUT LIST_ENTRY *FirstEntry, + IN OUT LIST_ENTRY *SecondEntry + ); + + +/** + Removes a node from a doubly linked list, and returns the node that follows + the removed node. + + Removes the node Entry from a doubly linked list. It is up to the caller of + this function to release the memory used by this node if that is required. On + exit, the node following Entry in the doubly linked list is returned. If + Entry is the only node in the linked list, then the head node of the linked + list is returned. + + If Entry is NULL, then ASSERT(). + If Entry is the head node of an empty list, then ASSERT(). + If PcdMaximumLinkedListLength is not zero, and the number of nodes in the + linked list containing Entry, including the Entry node, is greater than + or equal to PcdMaximumLinkedListLength, then ASSERT(). + + @param Entry A pointer to a node in a linked list. + + @return Entry. + +**/ +LIST_ENTRY * +EFIAPI +RemoveEntryList ( + IN CONST LIST_ENTRY *Entry + ); + +// +// Math Services +// +/** + Prototype for comparison function for any two element types. + + @param[in] Buffer1 The pointer to first buffer. + @param[in] Buffer2 The pointer to second buffer. + + @retval 0 Buffer1 equal to Buffer2. + @return <0 Buffer1 is less than Buffer2. + @return >0 Buffer1 is greater than Buffer2. +**/ +typedef +INTN +(EFIAPI *BASE_SORT_COMPARE)( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ); + +/** + This function is identical to perform QuickSort, + except that is uses the pre-allocated buffer so the in place sorting does not need to + allocate and free buffers constantly. + + Each element must be equal sized. + + if BufferToSort is NULL, then ASSERT. + if CompareFunction is NULL, then ASSERT. + if BufferOneElement is NULL, then ASSERT. + if ElementSize is < 1, then ASSERT. + + if Count is < 2 then perform no action. + + @param[in, out] BufferToSort on call a Buffer of (possibly sorted) elements + on return a buffer of sorted elements + @param[in] Count the number of elements in the buffer to sort + @param[in] ElementSize Size of an element in bytes + @param[in] CompareFunction The function to call to perform the comparison + of any 2 elements + @param[out] BufferOneElement Caller provided buffer whose size equals to ElementSize. + It's used by QuickSort() for swapping in sorting. +**/ +VOID +EFIAPI +QuickSort ( + IN OUT VOID *BufferToSort, + IN CONST UINTN Count, + IN CONST UINTN ElementSize, + IN BASE_SORT_COMPARE CompareFunction, + OUT VOID *BufferOneElement + ); + +/** + Shifts a 64-bit integer left between 0 and 63 bits. The low bits are filled + with zeros. The shifted value is returned. + + This function shifts the 64-bit value Operand to the left by Count bits. The + low Count bits are set to zero. The shifted value is returned. + + If Count is greater than 63, then ASSERT(). + + @param Operand The 64-bit operand to shift left. + @param Count The number of bits to shift left. + + @return Operand << Count. + +**/ +UINT64 +EFIAPI +LShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ); + + +/** + Shifts a 64-bit integer right between 0 and 63 bits. This high bits are + filled with zeros. The shifted value is returned. + + This function shifts the 64-bit value Operand to the right by Count bits. The + high Count bits are set to zero. The shifted value is returned. + + If Count is greater than 63, then ASSERT(). + + @param Operand The 64-bit operand to shift right. + @param Count The number of bits to shift right. + + @return Operand >> Count + +**/ +UINT64 +EFIAPI +RShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ); + + +/** + Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled + with original integer's bit 63. The shifted value is returned. + + This function shifts the 64-bit value Operand to the right by Count bits. The + high Count bits are set to bit 63 of Operand. The shifted value is returned. + + If Count is greater than 63, then ASSERT(). + + @param Operand The 64-bit operand to shift right. + @param Count The number of bits to shift right. + + @return Operand >> Count + +**/ +UINT64 +EFIAPI +ARShiftU64 ( + IN UINT64 Operand, + IN UINTN Count + ); + + +/** + Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits + with the high bits that were rotated. + + This function rotates the 32-bit value Operand to the left by Count bits. The + low Count bits are fill with the high Count bits of Operand. The rotated + value is returned. + + If Count is greater than 31, then ASSERT(). + + @param Operand The 32-bit operand to rotate left. + @param Count The number of bits to rotate left. + + @return Operand << Count + +**/ +UINT32 +EFIAPI +LRotU32 ( + IN UINT32 Operand, + IN UINTN Count + ); + + +/** + Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits + with the low bits that were rotated. + + This function rotates the 32-bit value Operand to the right by Count bits. + The high Count bits are fill with the low Count bits of Operand. The rotated + value is returned. + + If Count is greater than 31, then ASSERT(). + + @param Operand The 32-bit operand to rotate right. + @param Count The number of bits to rotate right. + + @return Operand >> Count + +**/ +UINT32 +EFIAPI +RRotU32 ( + IN UINT32 Operand, + IN UINTN Count + ); + + +/** + Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits + with the high bits that were rotated. + + This function rotates the 64-bit value Operand to the left by Count bits. The + low Count bits are fill with the high Count bits of Operand. The rotated + value is returned. + + If Count is greater than 63, then ASSERT(). + + @param Operand The 64-bit operand to rotate left. + @param Count The number of bits to rotate left. + + @return Operand << Count + +**/ +UINT64 +EFIAPI +LRotU64 ( + IN UINT64 Operand, + IN UINTN Count + ); + + +/** + Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits + with the high low bits that were rotated. + + This function rotates the 64-bit value Operand to the right by Count bits. + The high Count bits are fill with the low Count bits of Operand. The rotated + value is returned. + + If Count is greater than 63, then ASSERT(). + + @param Operand The 64-bit operand to rotate right. + @param Count The number of bits to rotate right. + + @return Operand >> Count + +**/ +UINT64 +EFIAPI +RRotU64 ( + IN UINT64 Operand, + IN UINTN Count + ); + + +/** + Returns the bit position of the lowest bit set in a 32-bit value. + + This function computes the bit position of the lowest bit set in the 32-bit + value specified by Operand. If Operand is zero, then -1 is returned. + Otherwise, a value between 0 and 31 is returned. + + @param Operand The 32-bit operand to evaluate. + + @retval 0..31 The lowest bit set in Operand was found. + @retval -1 Operand is zero. + +**/ +INTN +EFIAPI +LowBitSet32 ( + IN UINT32 Operand + ); + + +/** + Returns the bit position of the lowest bit set in a 64-bit value. + + This function computes the bit position of the lowest bit set in the 64-bit + value specified by Operand. If Operand is zero, then -1 is returned. + Otherwise, a value between 0 and 63 is returned. + + @param Operand The 64-bit operand to evaluate. + + @retval 0..63 The lowest bit set in Operand was found. + @retval -1 Operand is zero. + + +**/ +INTN +EFIAPI +LowBitSet64 ( + IN UINT64 Operand + ); + + +/** + Returns the bit position of the highest bit set in a 32-bit value. Equivalent + to log2(x). + + This function computes the bit position of the highest bit set in the 32-bit + value specified by Operand. If Operand is zero, then -1 is returned. + Otherwise, a value between 0 and 31 is returned. + + @param Operand The 32-bit operand to evaluate. + + @retval 0..31 Position of the highest bit set in Operand if found. + @retval -1 Operand is zero. + +**/ +INTN +EFIAPI +HighBitSet32 ( + IN UINT32 Operand + ); + + +/** + Returns the bit position of the highest bit set in a 64-bit value. Equivalent + to log2(x). + + This function computes the bit position of the highest bit set in the 64-bit + value specified by Operand. If Operand is zero, then -1 is returned. + Otherwise, a value between 0 and 63 is returned. + + @param Operand The 64-bit operand to evaluate. + + @retval 0..63 Position of the highest bit set in Operand if found. + @retval -1 Operand is zero. + +**/ +INTN +EFIAPI +HighBitSet64 ( + IN UINT64 Operand + ); + + +/** + Returns the value of the highest bit set in a 32-bit value. Equivalent to + 1 << log2(x). + + This function computes the value of the highest bit set in the 32-bit value + specified by Operand. If Operand is zero, then zero is returned. + + @param Operand The 32-bit operand to evaluate. + + @return 1 << HighBitSet32(Operand) + @retval 0 Operand is zero. + +**/ +UINT32 +EFIAPI +GetPowerOfTwo32 ( + IN UINT32 Operand + ); + + +/** + Returns the value of the highest bit set in a 64-bit value. Equivalent to + 1 << log2(x). + + This function computes the value of the highest bit set in the 64-bit value + specified by Operand. If Operand is zero, then zero is returned. + + @param Operand The 64-bit operand to evaluate. + + @return 1 << HighBitSet64(Operand) + @retval 0 Operand is zero. + +**/ +UINT64 +EFIAPI +GetPowerOfTwo64 ( + IN UINT64 Operand + ); + + +/** + Switches the endianness of a 16-bit integer. + + This function swaps the bytes in a 16-bit unsigned value to switch the value + from little endian to big endian or vice versa. The byte swapped value is + returned. + + @param Value A 16-bit unsigned value. + + @return The byte swapped Value. + +**/ +UINT16 +EFIAPI +SwapBytes16 ( + IN UINT16 Value + ); + + +/** + Switches the endianness of a 32-bit integer. + + This function swaps the bytes in a 32-bit unsigned value to switch the value + from little endian to big endian or vice versa. The byte swapped value is + returned. + + @param Value A 32-bit unsigned value. + + @return The byte swapped Value. + +**/ +UINT32 +EFIAPI +SwapBytes32 ( + IN UINT32 Value + ); + + +/** + Switches the endianness of a 64-bit integer. + + This function swaps the bytes in a 64-bit unsigned value to switch the value + from little endian to big endian or vice versa. The byte swapped value is + returned. + + @param Value A 64-bit unsigned value. + + @return The byte swapped Value. + +**/ +UINT64 +EFIAPI +SwapBytes64 ( + IN UINT64 Value + ); + + +/** + Multiples a 64-bit unsigned integer by a 32-bit unsigned integer and + generates a 64-bit unsigned result. + + This function multiples the 64-bit unsigned value Multiplicand by the 32-bit + unsigned value Multiplier and generates a 64-bit unsigned result. This 64- + bit unsigned result is returned. + + @param Multiplicand A 64-bit unsigned value. + @param Multiplier A 32-bit unsigned value. + + @return Multiplicand * Multiplier + +**/ +UINT64 +EFIAPI +MultU64x32 ( + IN UINT64 Multiplicand, + IN UINT32 Multiplier + ); + + +/** + Multiples a 64-bit unsigned integer by a 64-bit unsigned integer and + generates a 64-bit unsigned result. + + This function multiples the 64-bit unsigned value Multiplicand by the 64-bit + unsigned value Multiplier and generates a 64-bit unsigned result. This 64- + bit unsigned result is returned. + + @param Multiplicand A 64-bit unsigned value. + @param Multiplier A 64-bit unsigned value. + + @return Multiplicand * Multiplier. + +**/ +UINT64 +EFIAPI +MultU64x64 ( + IN UINT64 Multiplicand, + IN UINT64 Multiplier + ); + + +/** + Multiples a 64-bit signed integer by a 64-bit signed integer and generates a + 64-bit signed result. + + This function multiples the 64-bit signed value Multiplicand by the 64-bit + signed value Multiplier and generates a 64-bit signed result. This 64-bit + signed result is returned. + + @param Multiplicand A 64-bit signed value. + @param Multiplier A 64-bit signed value. + + @return Multiplicand * Multiplier + +**/ +INT64 +EFIAPI +MultS64x64 ( + IN INT64 Multiplicand, + IN INT64 Multiplier + ); + + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates + a 64-bit unsigned result. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 64-bit unsigned quotient. This + function returns the 64-bit unsigned quotient. + + If Divisor is 0, then ASSERT(). + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + + @return Dividend / Divisor. + +**/ +UINT64 +EFIAPI +DivU64x32 ( + IN UINT64 Dividend, + IN UINT32 Divisor + ); + + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates + a 32-bit unsigned remainder. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 32-bit remainder. This function + returns the 32-bit unsigned remainder. + + If Divisor is 0, then ASSERT(). + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + + @return Dividend % Divisor. + +**/ +UINT32 +EFIAPI +ModU64x32 ( + IN UINT64 Dividend, + IN UINT32 Divisor + ); + + +/** + Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates + a 64-bit unsigned result and an optional 32-bit unsigned remainder. + + This function divides the 64-bit unsigned value Dividend by the 32-bit + unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder + is not NULL, then the 32-bit unsigned remainder is returned in Remainder. + This function returns the 64-bit unsigned quotient. + + If Divisor is 0, then ASSERT(). + + @param Dividend A 64-bit unsigned value. + @param Divisor A 32-bit unsigned value. + @param Remainder A pointer to a 32-bit unsigned value. This parameter is + optional and may be NULL. + + @return Dividend / Divisor. + +**/ +UINT64 +EFIAPI +DivU64x32Remainder ( + IN UINT64 Dividend, + IN UINT32 Divisor, + OUT UINT32 *Remainder OPTIONAL + ); + + +/** + Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates + a 64-bit unsigned result and an optional 64-bit unsigned remainder. + + This function divides the 64-bit unsigned value Dividend by the 64-bit + unsigned value Divisor and generates a 64-bit unsigned quotient. If Remainder + is not NULL, then the 64-bit unsigned remainder is returned in Remainder. + This function returns the 64-bit unsigned quotient. + + If Divisor is 0, then ASSERT(). + + @param Dividend A 64-bit unsigned value. + @param Divisor A 64-bit unsigned value. + @param Remainder A pointer to a 64-bit unsigned value. This parameter is + optional and may be NULL. + + @return Dividend / Divisor. + +**/ +UINT64 +EFIAPI +DivU64x64Remainder ( + IN UINT64 Dividend, + IN UINT64 Divisor, + OUT UINT64 *Remainder OPTIONAL + ); + + +/** + Divides a 64-bit signed integer by a 64-bit signed integer and generates a + 64-bit signed result and a optional 64-bit signed remainder. + + This function divides the 64-bit signed value Dividend by the 64-bit signed + value Divisor and generates a 64-bit signed quotient. If Remainder is not + NULL, then the 64-bit signed remainder is returned in Remainder. This + function returns the 64-bit signed quotient. + + It is the caller's responsibility to not call this function with a Divisor of 0. + If Divisor is 0, then the quotient and remainder should be assumed to be + the largest negative integer. + + If Divisor is 0, then ASSERT(). + + @param Dividend A 64-bit signed value. + @param Divisor A 64-bit signed value. + @param Remainder A pointer to a 64-bit signed value. This parameter is + optional and may be NULL. + + @return Dividend / Divisor. + +**/ +INT64 +EFIAPI +DivS64x64Remainder ( + IN INT64 Dividend, + IN INT64 Divisor, + OUT INT64 *Remainder OPTIONAL + ); + + +/** + Reads a 16-bit value from memory that may be unaligned. + + This function returns the 16-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 16-bit value that may be unaligned. + + @return The 16-bit value read from Buffer. + +**/ +UINT16 +EFIAPI +ReadUnaligned16 ( + IN CONST UINT16 *Buffer + ); + + +/** + Writes a 16-bit value to memory that may be unaligned. + + This function writes the 16-bit value specified by Value to Buffer. Value is + returned. The function guarantees that the write operation does not produce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 16-bit value that may be unaligned. + @param Value 16-bit value to write to Buffer. + + @return The 16-bit value to write to Buffer. + +**/ +UINT16 +EFIAPI +WriteUnaligned16 ( + OUT UINT16 *Buffer, + IN UINT16 Value + ); + + +/** + Reads a 24-bit value from memory that may be unaligned. + + This function returns the 24-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 24-bit value that may be unaligned. + + @return The 24-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned24 ( + IN CONST UINT32 *Buffer + ); + + +/** + Writes a 24-bit value to memory that may be unaligned. + + This function writes the 24-bit value specified by Value to Buffer. Value is + returned. The function guarantees that the write operation does not produce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 24-bit value that may be unaligned. + @param Value 24-bit value to write to Buffer. + + @return The 24-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned24 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ); + + +/** + Reads a 32-bit value from memory that may be unaligned. + + This function returns the 32-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 32-bit value that may be unaligned. + + @return The 32-bit value read from Buffer. + +**/ +UINT32 +EFIAPI +ReadUnaligned32 ( + IN CONST UINT32 *Buffer + ); + + +/** + Writes a 32-bit value to memory that may be unaligned. + + This function writes the 32-bit value specified by Value to Buffer. Value is + returned. The function guarantees that the write operation does not produce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 32-bit value that may be unaligned. + @param Value 32-bit value to write to Buffer. + + @return The 32-bit value to write to Buffer. + +**/ +UINT32 +EFIAPI +WriteUnaligned32 ( + OUT UINT32 *Buffer, + IN UINT32 Value + ); + + +/** + Reads a 64-bit value from memory that may be unaligned. + + This function returns the 64-bit value pointed to by Buffer. The function + guarantees that the read operation does not produce an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 64-bit value that may be unaligned. + + @return The 64-bit value read from Buffer. + +**/ +UINT64 +EFIAPI +ReadUnaligned64 ( + IN CONST UINT64 *Buffer + ); + + +/** + Writes a 64-bit value to memory that may be unaligned. + + This function writes the 64-bit value specified by Value to Buffer. Value is + returned. The function guarantees that the write operation does not produce + an alignment fault. + + If the Buffer is NULL, then ASSERT(). + + @param Buffer The pointer to a 64-bit value that may be unaligned. + @param Value 64-bit value to write to Buffer. + + @return The 64-bit value to write to Buffer. + +**/ +UINT64 +EFIAPI +WriteUnaligned64 ( + OUT UINT64 *Buffer, + IN UINT64 Value + ); + + +// +// Bit Field Functions +// + +/** + Returns a bit field from an 8-bit value. + + Returns the bitfield specified by the StartBit and the EndBit from Operand. + + If 8-bit operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The bit field read. + +**/ +UINT8 +EFIAPI +BitFieldRead8 ( + IN UINT8 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to an 8-bit value, and returns the result. + + Writes Value to the bit field specified by the StartBit and the EndBit in + Operand. All other bits in Operand are preserved. The new 8-bit value is + returned. + + If 8-bit operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The new 8-bit value. + +**/ +UINT8 +EFIAPI +BitFieldWrite8 ( + IN UINT8 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + + +/** + Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the + result. + + Performs a bitwise OR between the bit field specified by StartBit + and EndBit in Operand and the value specified by OrData. All other bits in + Operand are preserved. The new 8-bit value is returned. + + If 8-bit operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the read value from the value + + @return The new 8-bit value. + +**/ +UINT8 +EFIAPI +BitFieldOr8 ( + IN UINT8 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + + +/** + Reads a bit field from an 8-bit value, performs a bitwise AND, and returns + the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData. All other bits in Operand are + preserved. The new 8-bit value is returned. + + If 8-bit operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the read value from the value. + + @return The new 8-bit value. + +**/ +UINT8 +EFIAPI +BitFieldAnd8 ( + IN UINT8 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + + +/** + Reads a bit field from an 8-bit value, performs a bitwise AND followed by a + bitwise OR, and returns the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are + preserved. The new 8-bit value is returned. + + If 8-bit operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the read value from the value. + @param OrData The value to OR with the result of the AND operation. + + @return The new 8-bit value. + +**/ +UINT8 +EFIAPI +BitFieldAndThenOr8 ( + IN UINT8 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + + +/** + Returns a bit field from a 16-bit value. + + Returns the bitfield specified by the StartBit and the EndBit from Operand. + + If 16-bit operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The bit field read. + +**/ +UINT16 +EFIAPI +BitFieldRead16 ( + IN UINT16 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to a 16-bit value, and returns the result. + + Writes Value to the bit field specified by the StartBit and the EndBit in + Operand. All other bits in Operand are preserved. The new 16-bit value is + returned. + + If 16-bit operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The new 16-bit value. + +**/ +UINT16 +EFIAPI +BitFieldWrite16 ( + IN UINT16 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + + +/** + Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the + result. + + Performs a bitwise OR between the bit field specified by StartBit + and EndBit in Operand and the value specified by OrData. All other bits in + Operand are preserved. The new 16-bit value is returned. + + If 16-bit operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the read value from the value + + @return The new 16-bit value. + +**/ +UINT16 +EFIAPI +BitFieldOr16 ( + IN UINT16 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + + +/** + Reads a bit field from a 16-bit value, performs a bitwise AND, and returns + the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData. All other bits in Operand are + preserved. The new 16-bit value is returned. + + If 16-bit operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the read value from the value + + @return The new 16-bit value. + +**/ +UINT16 +EFIAPI +BitFieldAnd16 ( + IN UINT16 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + + +/** + Reads a bit field from a 16-bit value, performs a bitwise AND followed by a + bitwise OR, and returns the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are + preserved. The new 16-bit value is returned. + + If 16-bit operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the read value from the value. + @param OrData The value to OR with the result of the AND operation. + + @return The new 16-bit value. + +**/ +UINT16 +EFIAPI +BitFieldAndThenOr16 ( + IN UINT16 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + + +/** + Returns a bit field from a 32-bit value. + + Returns the bitfield specified by the StartBit and the EndBit from Operand. + + If 32-bit operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The bit field read. + +**/ +UINT32 +EFIAPI +BitFieldRead32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to a 32-bit value, and returns the result. + + Writes Value to the bit field specified by the StartBit and the EndBit in + Operand. All other bits in Operand are preserved. The new 32-bit value is + returned. + + If 32-bit operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The new 32-bit value. + +**/ +UINT32 +EFIAPI +BitFieldWrite32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + + +/** + Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the + result. + + Performs a bitwise OR between the bit field specified by StartBit + and EndBit in Operand and the value specified by OrData. All other bits in + Operand are preserved. The new 32-bit value is returned. + + If 32-bit operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the read value from the value. + + @return The new 32-bit value. + +**/ +UINT32 +EFIAPI +BitFieldOr32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + + +/** + Reads a bit field from a 32-bit value, performs a bitwise AND, and returns + the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData. All other bits in Operand are + preserved. The new 32-bit value is returned. + + If 32-bit operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the value + + @return The new 32-bit value. + +**/ +UINT32 +EFIAPI +BitFieldAnd32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + + +/** + Reads a bit field from a 32-bit value, performs a bitwise AND followed by a + bitwise OR, and returns the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are + preserved. The new 32-bit value is returned. + + If 32-bit operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the value. + @param OrData The value to OR with the result of the AND operation. + + @return The new 32-bit value. + +**/ +UINT32 +EFIAPI +BitFieldAndThenOr32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + + +/** + Returns a bit field from a 64-bit value. + + Returns the bitfield specified by the StartBit and the EndBit from Operand. + + If 64-bit operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The bit field read. + +**/ +UINT64 +EFIAPI +BitFieldRead64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to a 64-bit value, and returns the result. + + Writes Value to the bit field specified by the StartBit and the EndBit in + Operand. All other bits in Operand are preserved. The new 64-bit value is + returned. + + If 64-bit operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param Value New value of the bit field. + + @return The new 64-bit value. + +**/ +UINT64 +EFIAPI +BitFieldWrite64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + + +/** + Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the + result. + + Performs a bitwise OR between the bit field specified by StartBit + and EndBit in Operand and the value specified by OrData. All other bits in + Operand are preserved. The new 64-bit value is returned. + + If 64-bit operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param OrData The value to OR with the read value from the value + + @return The new 64-bit value. + +**/ +UINT64 +EFIAPI +BitFieldOr64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + + +/** + Reads a bit field from a 64-bit value, performs a bitwise AND, and returns + the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData. All other bits in Operand are + preserved. The new 64-bit value is returned. + + If 64-bit operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the value + + @return The new 64-bit value. + +**/ +UINT64 +EFIAPI +BitFieldAnd64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + + +/** + Reads a bit field from a 64-bit value, performs a bitwise AND followed by a + bitwise OR, and returns the result. + + Performs a bitwise AND between the bit field specified by StartBit and EndBit + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are + preserved. The new 64-bit value is returned. + + If 64-bit operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the value. + @param OrData The value to OR with the result of the AND operation. + + @return The new 64-bit value. + +**/ +UINT64 +EFIAPI +BitFieldAndThenOr64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads a bit field from a 32-bit value, counts and returns + the number of set bits. + + Counts the number of set bits in the bit field specified by + StartBit and EndBit in Operand. The count is returned. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The number of bits set between StartBit and EndBit. + +**/ +UINT8 +EFIAPI +BitFieldCountOnes32 ( + IN UINT32 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Reads a bit field from a 64-bit value, counts and returns + the number of set bits. + + Counts the number of set bits in the bit field specified by + StartBit and EndBit in Operand. The count is returned. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Operand Operand on which to perform the bitfield operation. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The number of bits set between StartBit and EndBit. + +**/ +UINT8 +EFIAPI +BitFieldCountOnes64 ( + IN UINT64 Operand, + IN UINTN StartBit, + IN UINTN EndBit + ); + +// +// Base Library Checksum Functions +// + +/** + Returns the sum of all elements in a buffer in unit of UINT8. + During calculation, the carry bits are dropped. + + This function calculates the sum of all elements in a buffer + in unit of UINT8. The carry bits in result of addition are dropped. + The result is returned as UINT8. If Length is Zero, then Zero is + returned. + + If Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the sum operation. + @param Length The size, in bytes, of Buffer. + + @return Sum The sum of Buffer with carry bits dropped during additions. + +**/ +UINT8 +EFIAPI +CalculateSum8 ( + IN CONST UINT8 *Buffer, + IN UINTN Length + ); + + +/** + Returns the two's complement checksum of all elements in a buffer + of 8-bit values. + + This function first calculates the sum of the 8-bit values in the + buffer specified by Buffer and Length. The carry bits in the result + of addition are dropped. Then, the two's complement of the sum is + returned. If Length is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the checksum operation. + @param Length The size, in bytes, of Buffer. + + @return Checksum The two's complement checksum of Buffer. + +**/ +UINT8 +EFIAPI +CalculateCheckSum8 ( + IN CONST UINT8 *Buffer, + IN UINTN Length + ); + + +/** + Returns the sum of all elements in a buffer of 16-bit values. During + calculation, the carry bits are dropped. + + This function calculates the sum of the 16-bit values in the buffer + specified by Buffer and Length. The carry bits in result of addition are dropped. + The 16-bit result is returned. If Length is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the sum operation. + @param Length The size, in bytes, of Buffer. + + @return Sum The sum of Buffer with carry bits dropped during additions. + +**/ +UINT16 +EFIAPI +CalculateSum16 ( + IN CONST UINT16 *Buffer, + IN UINTN Length + ); + + +/** + Returns the two's complement checksum of all elements in a buffer of + 16-bit values. + + This function first calculates the sum of the 16-bit values in the buffer + specified by Buffer and Length. The carry bits in the result of addition + are dropped. Then, the two's complement of the sum is returned. If Length + is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the checksum operation. + @param Length The size, in bytes, of Buffer. + + @return Checksum The two's complement checksum of Buffer. + +**/ +UINT16 +EFIAPI +CalculateCheckSum16 ( + IN CONST UINT16 *Buffer, + IN UINTN Length + ); + + +/** + Returns the sum of all elements in a buffer of 32-bit values. During + calculation, the carry bits are dropped. + + This function calculates the sum of the 32-bit values in the buffer + specified by Buffer and Length. The carry bits in result of addition are dropped. + The 32-bit result is returned. If Length is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the sum operation. + @param Length The size, in bytes, of Buffer. + + @return Sum The sum of Buffer with carry bits dropped during additions. + +**/ +UINT32 +EFIAPI +CalculateSum32 ( + IN CONST UINT32 *Buffer, + IN UINTN Length + ); + + +/** + Returns the two's complement checksum of all elements in a buffer of + 32-bit values. + + This function first calculates the sum of the 32-bit values in the buffer + specified by Buffer and Length. The carry bits in the result of addition + are dropped. Then, the two's complement of the sum is returned. If Length + is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the checksum operation. + @param Length The size, in bytes, of Buffer. + + @return Checksum The two's complement checksum of Buffer. + +**/ +UINT32 +EFIAPI +CalculateCheckSum32 ( + IN CONST UINT32 *Buffer, + IN UINTN Length + ); + + +/** + Returns the sum of all elements in a buffer of 64-bit values. During + calculation, the carry bits are dropped. + + This function calculates the sum of the 64-bit values in the buffer + specified by Buffer and Length. The carry bits in result of addition are dropped. + The 64-bit result is returned. If Length is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the sum operation. + @param Length The size, in bytes, of Buffer. + + @return Sum The sum of Buffer with carry bits dropped during additions. + +**/ +UINT64 +EFIAPI +CalculateSum64 ( + IN CONST UINT64 *Buffer, + IN UINTN Length + ); + + +/** + Returns the two's complement checksum of all elements in a buffer of + 64-bit values. + + This function first calculates the sum of the 64-bit values in the buffer + specified by Buffer and Length. The carry bits in the result of addition + are dropped. Then, the two's complement of the sum is returned. If Length + is 0, then 0 is returned. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to carry out the checksum operation. + @param Length The size, in bytes, of Buffer. + + @return Checksum The two's complement checksum of Buffer. + +**/ +UINT64 +EFIAPI +CalculateCheckSum64 ( + IN CONST UINT64 *Buffer, + IN UINTN Length + ); + +/** + Computes and returns a 32-bit CRC for a data buffer. + CRC32 value bases on ITU-T V.42. + + If Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param[in] Buffer A pointer to the buffer on which the 32-bit CRC is to be computed. + @param[in] Length The number of bytes in the buffer Data. + + @retval Crc32 The 32-bit CRC was computed for the data buffer. + +**/ +UINT32 +EFIAPI +CalculateCrc32( + IN VOID *Buffer, + IN UINTN Length + ); + +// +// Base Library CPU Functions +// + +/** + Function entry point used when a stack switch is requested with SwitchStack() + + @param Context1 Context1 parameter passed into SwitchStack(). + @param Context2 Context2 parameter passed into SwitchStack(). + +**/ +typedef +VOID +(EFIAPI *SWITCH_STACK_ENTRY_POINT)( + IN VOID *Context1, OPTIONAL + IN VOID *Context2 OPTIONAL + ); + + +/** + Used to serialize load and store operations. + + All loads and stores that proceed calls to this function are guaranteed to be + globally visible when this function returns. + +**/ +VOID +EFIAPI +MemoryFence ( + VOID + ); + + +/** + Saves the current CPU context that can be restored with a call to LongJump() + and returns 0. + + Saves the current CPU context in the buffer specified by JumpBuffer and + returns 0. The initial call to SetJump() must always return 0. Subsequent + calls to LongJump() cause a non-zero value to be returned by SetJump(). + + If JumpBuffer is NULL, then ASSERT(). + For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT(). + + NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific. + The same structure must never be used for more than one CPU architecture context. + For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module. + SetJump()/LongJump() is not currently supported for the EBC processor type. + + @param JumpBuffer A pointer to CPU context buffer. + + @retval 0 Indicates a return from SetJump(). + +**/ +RETURNS_TWICE +UINTN +EFIAPI +SetJump ( + OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer + ); + + +/** + Restores the CPU context that was saved with SetJump(). + + Restores the CPU context from the buffer specified by JumpBuffer. This + function never returns to the caller. Instead is resumes execution based on + the state of JumpBuffer. + + If JumpBuffer is NULL, then ASSERT(). + For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT(). + If Value is 0, then ASSERT(). + + @param JumpBuffer A pointer to CPU context buffer. + @param Value The value to return when the SetJump() context is + restored and must be non-zero. + +**/ +VOID +EFIAPI +LongJump ( + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, + IN UINTN Value + ); + + +/** + Enables CPU interrupts. + +**/ +VOID +EFIAPI +EnableInterrupts ( + VOID + ); + + +/** + Disables CPU interrupts. + +**/ +VOID +EFIAPI +DisableInterrupts ( + VOID + ); + + +/** + Disables CPU interrupts and returns the interrupt state prior to the disable + operation. + + @retval TRUE CPU interrupts were enabled on entry to this call. + @retval FALSE CPU interrupts were disabled on entry to this call. + +**/ +BOOLEAN +EFIAPI +SaveAndDisableInterrupts ( + VOID + ); + + +/** + Enables CPU interrupts for the smallest window required to capture any + pending interrupts. + +**/ +VOID +EFIAPI +EnableDisableInterrupts ( + VOID + ); + + +/** + Retrieves the current CPU interrupt state. + + Returns TRUE if interrupts are currently enabled. Otherwise + returns FALSE. + + @retval TRUE CPU interrupts are enabled. + @retval FALSE CPU interrupts are disabled. + +**/ +BOOLEAN +EFIAPI +GetInterruptState ( + VOID + ); + + +/** + Set the current CPU interrupt state. + + Sets the current CPU interrupt state to the state specified by + InterruptState. If InterruptState is TRUE, then interrupts are enabled. If + InterruptState is FALSE, then interrupts are disabled. InterruptState is + returned. + + @param InterruptState TRUE if interrupts should enabled. FALSE if + interrupts should be disabled. + + @return InterruptState + +**/ +BOOLEAN +EFIAPI +SetInterruptState ( + IN BOOLEAN InterruptState + ); + + +/** + Requests CPU to pause for a short period of time. + + Requests CPU to pause for a short period of time. Typically used in MP + systems to prevent memory starvation while waiting for a spin lock. + +**/ +VOID +EFIAPI +CpuPause ( + VOID + ); + + +/** + Transfers control to a function starting with a new stack. + + Transfers control to the function specified by EntryPoint using the + new stack specified by NewStack and passing in the parameters specified + by Context1 and Context2. Context1 and Context2 are optional and may + be NULL. The function EntryPoint must never return. This function + supports a variable number of arguments following the NewStack parameter. + These additional arguments are ignored on IA-32, x64, and EBC architectures. + Itanium processors expect one additional parameter of type VOID * that specifies + the new backing store pointer. + + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + @param EntryPoint A pointer to function to call with the new stack. + @param Context1 A pointer to the context to pass into the EntryPoint + function. + @param Context2 A pointer to the context to pass into the EntryPoint + function. + @param NewStack A pointer to the new stack to use for the EntryPoint + function. + @param ... This variable argument list is ignored for IA-32, x64, and + EBC architectures. For Itanium processors, this variable + argument list is expected to contain a single parameter of + type VOID * that specifies the new backing store pointer. + + +**/ +VOID +EFIAPI +SwitchStack ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack, + ... + ); + + +/** + Generates a breakpoint on the CPU. + + Generates a breakpoint on the CPU. The breakpoint must be implemented such + that code can resume normal execution after the breakpoint. + +**/ +VOID +EFIAPI +CpuBreakpoint ( + VOID + ); + + +/** + Executes an infinite loop. + + Forces the CPU to execute an infinite loop. A debugger may be used to skip + past the loop and the code that follows the loop must execute properly. This + implies that the infinite loop must not cause the code that follow it to be + optimized away. + +**/ +VOID +EFIAPI +CpuDeadLoop ( + VOID + ); + + +/** + Uses as a barrier to stop speculative execution. + + Ensures that no later instruction will execute speculatively, until all prior + instructions have completed. + +**/ +VOID +EFIAPI +SpeculationBarrier ( + VOID + ); + +#if defined (MDE_CPU_X64) +// +// The page size for the PVALIDATE instruction +// +typedef enum { + PvalidatePageSize4K = 0, + PvalidatePageSize2MB, +} PVALIDATE_PAGE_SIZE; + +// +// PVALIDATE Return Code. +// +#define PVALIDATE_RET_SUCCESS 0 +#define PVALIDATE_RET_FAIL_INPUT 1 +#define PVALIDATE_RET_SIZE_MISMATCH 6 + +// +// The PVALIDATE instruction did not make any changes to the RMP entry. +// +#define PVALIDATE_RET_NO_RMPUPDATE 255 + +/** + Execute a PVALIDATE instruction to validate or to rescinds validation of a guest + page's RMP entry. + + The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1. + + The function is available on X64. + + @param[in] PageSize The page size to use. + @param[in] Validate If TRUE, validate the guest virtual address + otherwise invalidate the guest virtual address. + @param[in] Address The guest virtual address. + + @retval PVALIDATE_RET_SUCCESS The PVALIDATE instruction succeeded, and + updated the RMP entry. + @retval PVALIDATE_RET_NO_RMPUPDATE The PVALIDATE instruction succeeded, but + did not update the RMP entry. + @return Failure code from the PVALIDATE + instruction. +**/ +UINT32 +EFIAPI +AsmPvalidate ( + IN PVALIDATE_PAGE_SIZE PageSize, + IN BOOLEAN Validate, + IN PHYSICAL_ADDRESS Address + ); + +// +// RDX settings for RMPADJUST +// +#define RMPADJUST_VMPL_MAX 3 +#define RMPADJUST_VMPL_MASK 0xFF +#define RMPADJUST_VMPL_SHIFT 0 +#define RMPADJUST_PERMISSION_MASK_MASK 0xFF +#define RMPADJUST_PERMISSION_MASK_SHIFT 8 +#define RMPADJUST_VMSA_PAGE_BIT BIT16 + +/** + Adjusts the permissions of an SEV-SNP guest page. + + Executes a RMPADJUST instruction with the register state specified by Rax, + Rcx, and Rdx. Returns Eax. This function is only available on X64. + + The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1. + + @param[in] Rax The value to load into RAX before executing the RMPADJUST + instruction. + @param[in] Rcx The value to load into RCX before executing the RMPADJUST + instruction. + @param[in] Rdx The value to load into RDX before executing the RMPADJUST + instruction. + + @return Eax +**/ +UINT32 +EFIAPI +AsmRmpAdjust ( + IN UINT64 Rax, + IN UINT64 Rcx, + IN UINT64 Rdx + ); +#endif + + +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +/// +/// IA32 and x64 Specific Functions. +/// Byte packed structure for 16-bit Real Mode EFLAGS. +/// +typedef union { + struct { + UINT32 CF:1; ///< Carry Flag. + UINT32 Reserved_0:1; ///< Reserved. + UINT32 PF:1; ///< Parity Flag. + UINT32 Reserved_1:1; ///< Reserved. + UINT32 AF:1; ///< Auxiliary Carry Flag. + UINT32 Reserved_2:1; ///< Reserved. + UINT32 ZF:1; ///< Zero Flag. + UINT32 SF:1; ///< Sign Flag. + UINT32 TF:1; ///< Trap Flag. + UINT32 IF:1; ///< Interrupt Enable Flag. + UINT32 DF:1; ///< Direction Flag. + UINT32 OF:1; ///< Overflow Flag. + UINT32 IOPL:2; ///< I/O Privilege Level. + UINT32 NT:1; ///< Nested Task. + UINT32 Reserved_3:1; ///< Reserved. + } Bits; + UINT16 Uint16; +} IA32_FLAGS16; + +/// +/// Byte packed structure for EFLAGS/RFLAGS. +/// 32-bits on IA-32. +/// 64-bits on x64. The upper 32-bits on x64 are reserved. +/// +typedef union { + struct { + UINT32 CF:1; ///< Carry Flag. + UINT32 Reserved_0:1; ///< Reserved. + UINT32 PF:1; ///< Parity Flag. + UINT32 Reserved_1:1; ///< Reserved. + UINT32 AF:1; ///< Auxiliary Carry Flag. + UINT32 Reserved_2:1; ///< Reserved. + UINT32 ZF:1; ///< Zero Flag. + UINT32 SF:1; ///< Sign Flag. + UINT32 TF:1; ///< Trap Flag. + UINT32 IF:1; ///< Interrupt Enable Flag. + UINT32 DF:1; ///< Direction Flag. + UINT32 OF:1; ///< Overflow Flag. + UINT32 IOPL:2; ///< I/O Privilege Level. + UINT32 NT:1; ///< Nested Task. + UINT32 Reserved_3:1; ///< Reserved. + UINT32 RF:1; ///< Resume Flag. + UINT32 VM:1; ///< Virtual 8086 Mode. + UINT32 AC:1; ///< Alignment Check. + UINT32 VIF:1; ///< Virtual Interrupt Flag. + UINT32 VIP:1; ///< Virtual Interrupt Pending. + UINT32 ID:1; ///< ID Flag. + UINT32 Reserved_4:10; ///< Reserved. + } Bits; + UINTN UintN; +} IA32_EFLAGS32; + +/// +/// Byte packed structure for Control Register 0 (CR0). +/// 32-bits on IA-32. +/// 64-bits on x64. The upper 32-bits on x64 are reserved. +/// +typedef union { + struct { + UINT32 PE:1; ///< Protection Enable. + UINT32 MP:1; ///< Monitor Coprocessor. + UINT32 EM:1; ///< Emulation. + UINT32 TS:1; ///< Task Switched. + UINT32 ET:1; ///< Extension Type. + UINT32 NE:1; ///< Numeric Error. + UINT32 Reserved_0:10; ///< Reserved. + UINT32 WP:1; ///< Write Protect. + UINT32 Reserved_1:1; ///< Reserved. + UINT32 AM:1; ///< Alignment Mask. + UINT32 Reserved_2:10; ///< Reserved. + UINT32 NW:1; ///< Mot Write-through. + UINT32 CD:1; ///< Cache Disable. + UINT32 PG:1; ///< Paging. + } Bits; + UINTN UintN; +} IA32_CR0; + +/// +/// Byte packed structure for Control Register 4 (CR4). +/// 32-bits on IA-32. +/// 64-bits on x64. The upper 32-bits on x64 are reserved. +/// +typedef union { + struct { + UINT32 VME:1; ///< Virtual-8086 Mode Extensions. + UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts. + UINT32 TSD:1; ///< Time Stamp Disable. + UINT32 DE:1; ///< Debugging Extensions. + UINT32 PSE:1; ///< Page Size Extensions. + UINT32 PAE:1; ///< Physical Address Extension. + UINT32 MCE:1; ///< Machine Check Enable. + UINT32 PGE:1; ///< Page Global Enable. + UINT32 PCE:1; ///< Performance Monitoring Counter + ///< Enable. + UINT32 OSFXSR:1; ///< Operating System Support for + ///< FXSAVE and FXRSTOR instructions + UINT32 OSXMMEXCPT:1; ///< Operating System Support for + ///< Unmasked SIMD Floating Point + ///< Exceptions. + UINT32 UMIP:1; ///< User-Mode Instruction Prevention. + UINT32 LA57:1; ///< Linear Address 57bit. + UINT32 VMXE:1; ///< VMX Enable. + UINT32 SMXE:1; ///< SMX Enable. + UINT32 Reserved_3:1; ///< Reserved. + UINT32 FSGSBASE:1; ///< FSGSBASE Enable. + UINT32 PCIDE:1; ///< PCID Enable. + UINT32 OSXSAVE:1; ///< XSAVE and Processor Extended States Enable. + UINT32 Reserved_4:1; ///< Reserved. + UINT32 SMEP:1; ///< SMEP Enable. + UINT32 SMAP:1; ///< SMAP Enable. + UINT32 PKE:1; ///< Protection-Key Enable. + UINT32 Reserved_5:9; ///< Reserved. + } Bits; + UINTN UintN; +} IA32_CR4; + +/// +/// Byte packed structure for a segment descriptor in a GDT/LDT. +/// +typedef union { + struct { + UINT32 LimitLow:16; + UINT32 BaseLow:16; + UINT32 BaseMid:8; + UINT32 Type:4; + UINT32 S:1; + UINT32 DPL:2; + UINT32 P:1; + UINT32 LimitHigh:4; + UINT32 AVL:1; + UINT32 L:1; + UINT32 DB:1; + UINT32 G:1; + UINT32 BaseHigh:8; + } Bits; + UINT64 Uint64; +} IA32_SEGMENT_DESCRIPTOR; + +/// +/// Byte packed structure for an IDTR, GDTR, LDTR descriptor. +/// +#pragma pack (1) +typedef struct { + UINT16 Limit; + UINTN Base; +} IA32_DESCRIPTOR; +#pragma pack () + +#define IA32_IDT_GATE_TYPE_TASK 0x85 +#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86 +#define IA32_IDT_GATE_TYPE_TRAP_16 0x87 +#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E +#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F + +#define IA32_GDT_TYPE_TSS 0x9 +#define IA32_GDT_ALIGNMENT 8 + +#if defined (MDE_CPU_IA32) +/// +/// Byte packed structure for an IA-32 Interrupt Gate Descriptor. +/// +typedef union { + struct { + UINT32 OffsetLow:16; ///< Offset bits 15..0. + UINT32 Selector:16; ///< Selector. + UINT32 Reserved_0:8; ///< Reserved. + UINT32 GateType:8; ///< Gate Type. See #defines above. + UINT32 OffsetHigh:16; ///< Offset bits 31..16. + } Bits; + UINT64 Uint64; +} IA32_IDT_GATE_DESCRIPTOR; + +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT16 PreviousTaskLink; + UINT16 Reserved_2; + UINT32 ESP0; + UINT16 SS0; + UINT16 Reserved_10; + UINT32 ESP1; + UINT16 SS1; + UINT16 Reserved_18; + UINT32 ESP2; + UINT16 SS2; + UINT16 Reserved_26; + UINT32 CR3; + UINT32 EIP; + UINT32 EFLAGS; + UINT32 EAX; + UINT32 ECX; + UINT32 EDX; + UINT32 EBX; + UINT32 ESP; + UINT32 EBP; + UINT32 ESI; + UINT32 EDI; + UINT16 ES; + UINT16 Reserved_74; + UINT16 CS; + UINT16 Reserved_78; + UINT16 SS; + UINT16 Reserved_82; + UINT16 DS; + UINT16 Reserved_86; + UINT16 FS; + UINT16 Reserved_90; + UINT16 GS; + UINT16 Reserved_94; + UINT16 LDTSegmentSelector; + UINT16 Reserved_98; + UINT16 T; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMid:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseHigh:8; ///< Base Address 31..24 + } Bits; + UINT64 Uint64; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + +#endif // defined (MDE_CPU_IA32) + +#if defined (MDE_CPU_X64) +/// +/// Byte packed structure for an x64 Interrupt Gate Descriptor. +/// +typedef union { + struct { + UINT32 OffsetLow:16; ///< Offset bits 15..0. + UINT32 Selector:16; ///< Selector. + UINT32 Reserved_0:8; ///< Reserved. + UINT32 GateType:8; ///< Gate Type. See #defines above. + UINT32 OffsetHigh:16; ///< Offset bits 31..16. + UINT32 OffsetUpper:32; ///< Offset bits 63..32. + UINT32 Reserved_1:32; ///< Reserved. + } Bits; + struct { + UINT64 Uint64; + UINT64 Uint64_1; + } Uint128; +} IA32_IDT_GATE_DESCRIPTOR; + +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT32 Reserved_0; + UINT64 RSP0; + UINT64 RSP1; + UINT64 RSP2; + UINT64 Reserved_28; + UINT64 IST[7]; + UINT64 Reserved_92; + UINT16 Reserved_100; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMidl:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseMidh:8; ///< Base Address 31..24 + UINT32 BaseHigh:32; ///< Base Address 63..32 + UINT32 Reserved_96:32; ///< Reserved + } Bits; + struct { + UINT64 Uint64; + UINT64 Uint64_1; + } Uint128; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + +#endif // defined (MDE_CPU_X64) + +/// +/// Byte packed structure for an FP/SSE/SSE2 context. +/// +typedef struct { + UINT8 Buffer[512]; +} IA32_FX_BUFFER; + +/// +/// Structures for the 16-bit real mode thunks. +/// +typedef struct { + UINT32 Reserved1; + UINT32 Reserved2; + UINT32 Reserved3; + UINT32 Reserved4; + UINT8 BL; + UINT8 BH; + UINT16 Reserved5; + UINT8 DL; + UINT8 DH; + UINT16 Reserved6; + UINT8 CL; + UINT8 CH; + UINT16 Reserved7; + UINT8 AL; + UINT8 AH; + UINT16 Reserved8; +} IA32_BYTE_REGS; + +typedef struct { + UINT16 DI; + UINT16 Reserved1; + UINT16 SI; + UINT16 Reserved2; + UINT16 BP; + UINT16 Reserved3; + UINT16 SP; + UINT16 Reserved4; + UINT16 BX; + UINT16 Reserved5; + UINT16 DX; + UINT16 Reserved6; + UINT16 CX; + UINT16 Reserved7; + UINT16 AX; + UINT16 Reserved8; +} IA32_WORD_REGS; + +typedef struct { + UINT32 EDI; + UINT32 ESI; + UINT32 EBP; + UINT32 ESP; + UINT32 EBX; + UINT32 EDX; + UINT32 ECX; + UINT32 EAX; + UINT16 DS; + UINT16 ES; + UINT16 FS; + UINT16 GS; + IA32_EFLAGS32 EFLAGS; + UINT32 Eip; + UINT16 CS; + UINT16 SS; +} IA32_DWORD_REGS; + +typedef union { + IA32_DWORD_REGS E; + IA32_WORD_REGS X; + IA32_BYTE_REGS H; +} IA32_REGISTER_SET; + +/// +/// Byte packed structure for an 16-bit real mode thunks. +/// +typedef struct { + IA32_REGISTER_SET *RealModeState; + VOID *RealModeBuffer; + UINT32 RealModeBufferSize; + UINT32 ThunkAttributes; +} THUNK_CONTEXT; + +#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001 +#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002 +#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004 + +/// +/// Type definition for representing labels in NASM source code that allow for +/// the patching of immediate operands of IA32 and X64 instructions. +/// +/// While the type is technically defined as a function type (note: not a +/// pointer-to-function type), such labels in NASM source code never stand for +/// actual functions, and identifiers declared with this function type should +/// never be called. This is also why the EFIAPI calling convention specifier +/// is missing from the typedef, and why the typedef does not follow the usual +/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID +/// return type and the VOID argument list are merely artifacts. +/// +typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID); + +/** + Retrieves CPUID information. + + Executes the CPUID instruction with EAX set to the value specified by Index. + This function always returns Index. + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + This function is only available on IA-32 and x64. + + @param Index The 32-bit value to load into EAX prior to invoking the CPUID + instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuid ( + IN UINT32 Index, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ); + + +/** + Retrieves CPUID information using an extended leaf identifier. + + Executes the CPUID instruction with EAX set to the value specified by Index + and ECX set to the value specified by SubIndex. This function always returns + Index. This function is only available on IA-32 and x64. + + If Eax is not NULL, then the value of EAX after CPUID is returned in Eax. + If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. + If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. + If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. + + @param Index The 32-bit value to load into EAX prior to invoking the + CPUID instruction. + @param SubIndex The 32-bit value to load into ECX prior to invoking the + CPUID instruction. + @param Eax The pointer to the 32-bit EAX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param Ebx The pointer to the 32-bit EBX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param Ecx The pointer to the 32-bit ECX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + @param Edx The pointer to the 32-bit EDX value returned by the CPUID + instruction. This is an optional parameter that may be + NULL. + + @return Index. + +**/ +UINT32 +EFIAPI +AsmCpuidEx ( + IN UINT32 Index, + IN UINT32 SubIndex, + OUT UINT32 *Eax, OPTIONAL + OUT UINT32 *Ebx, OPTIONAL + OUT UINT32 *Ecx, OPTIONAL + OUT UINT32 *Edx OPTIONAL + ); + + +/** + Set CD bit and clear NW bit of CR0 followed by a WBINVD. + + Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0, + and executing a WBINVD instruction. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmDisableCache ( + VOID + ); + + +/** + Perform a WBINVD and clear both the CD and NW bits of CR0. + + Enables the caches by executing a WBINVD instruction and then clear both the CD and NW + bits of CR0 to 0. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmEnableCache ( + VOID + ); + + +/** + Returns the lower 32-bits of a Machine Specific Register(MSR). + + Reads and returns the lower 32-bits of the MSR specified by Index. + No parameter checking is performed on Index, and some Index values may cause + CPU exceptions. The caller must either guarantee that Index is valid, or the + caller must set up exception handlers to catch the exceptions. This function + is only available on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The lower 32 bits of the MSR identified by Index. + +**/ +UINT32 +EFIAPI +AsmReadMsr32 ( + IN UINT32 Index + ); + + +/** + Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value. + The upper 32-bits of the MSR are set to zero. + + Writes the 32-bit value specified by Value to the MSR specified by Index. The + upper 32-bits of the MSR write are set to zero. The 32-bit value written to + the MSR is returned. No parameter checking is performed on Index or Value, + and some of these may cause CPU exceptions. The caller must either guarantee + that Index and Value are valid, or the caller must establish proper exception + handlers. This function is only available on IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 32-bit value to write to the MSR. + + @return Value + +**/ +UINT32 +EFIAPI +AsmWriteMsr32 ( + IN UINT32 Index, + IN UINT32 Value + ); + + +/** + Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and + writes the result back to the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise OR + between the lower 32-bits of the read result and the value specified by + OrData, and writes the result to the 64-bit MSR specified by Index. The lower + 32-bits of the value written to the MSR is returned. No parameter checking is + performed on Index or OrData, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and OrData are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param OrData The value to OR with the read value from the MSR. + + @return The lower 32-bit value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrOr32 ( + IN UINT32 Index, + IN UINT32 OrData + ); + + +/** + Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes + the result back to the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between the + lower 32-bits of the read result and the value specified by AndData, and + writes the result to the 64-bit MSR specified by Index. The lower 32-bits of + the value written to the MSR is returned. No parameter checking is performed + on Index or AndData, and some of these may cause CPU exceptions. The caller + must either guarantee that Index and AndData are valid, or the caller must + establish proper exception handlers. This function is only available on IA-32 + and x64. + + @param Index The 32-bit MSR index to write. + @param AndData The value to AND with the read value from the MSR. + + @return The lower 32-bit value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrAnd32 ( + IN UINT32 Index, + IN UINT32 AndData + ); + + +/** + Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR + on the lower 32-bits, and writes the result back to the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between the + lower 32-bits of the read result and the value specified by AndData + preserving the upper 32-bits, performs a bitwise OR between the + result of the AND operation and the value specified by OrData, and writes the + result to the 64-bit MSR specified by Address. The lower 32-bits of the value + written to the MSR is returned. No parameter checking is performed on Index, + AndData, or OrData, and some of these may cause CPU exceptions. The caller + must either guarantee that Index, AndData, and OrData are valid, or the + caller must establish proper exception handlers. This function is only + available on IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param AndData The value to AND with the read value from the MSR. + @param OrData The value to OR with the result of the AND operation. + + @return The lower 32-bit value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrAndThenOr32 ( + IN UINT32 Index, + IN UINT32 AndData, + IN UINT32 OrData + ); + + +/** + Reads a bit field of an MSR. + + Reads the bit field in the lower 32-bits of a 64-bit MSR. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. The caller must either guarantee that Index is valid, or the caller + must set up exception handlers to catch the exceptions. This function is only + available on IA-32 and x64. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Index The 32-bit MSR index to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The bit field read from the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrBitFieldRead32 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to an MSR. + + Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination MSR are preserved. The lower 32-bits of the MSR written is + returned. The caller must either guarantee that Index and the data written + is valid, or the caller must set up exception handlers to catch the exceptions. + This function is only available on IA-32 and x64. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The lower 32-bit of the value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrBitFieldWrite32 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the + result back to the bit field in the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit MSR specified by Index. The lower 32-bits of the value + written to the MSR are returned. Extra left bits in OrData are stripped. The + caller must either guarantee that Index and the data written is valid, or + the caller must set up exception handlers to catch the exceptions. This + function is only available on IA-32 and x64. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the read value from the MSR. + + @return The lower 32-bit of the value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrBitFieldOr32 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the + result back to the bit field in the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between the + read result and the value specified by AndData, and writes the result to the + 64-bit MSR specified by Index. The lower 32-bits of the value written to the + MSR are returned. Extra left bits in AndData are stripped. The caller must + either guarantee that Index and the data written is valid, or the caller must + set up exception handlers to catch the exceptions. This function is only + available on IA-32 and x64. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the MSR. + + @return The lower 32-bit of the value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrBitFieldAnd32 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a + bitwise OR between the read result and the value specified by + AndData, and writes the result to the 64-bit MSR specified by Index. The + lower 32-bits of the value written to the MSR are returned. Extra left bits + in both AndData and OrData are stripped. The caller must either guarantee + that Index and the data written is valid, or the caller must set up exception + handlers to catch the exceptions. This function is only available on IA-32 + and x64. + + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the MSR. + @param OrData The value to OR with the result of the AND operation. + + @return The lower 32-bit of the value written to the MSR. + +**/ +UINT32 +EFIAPI +AsmMsrBitFieldAndThenOr32 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + + +/** + Returns a 64-bit Machine Specific Register(MSR). + + Reads and returns the 64-bit MSR specified by Index. No parameter checking is + performed on Index, and some Index values may cause CPU exceptions. The + caller must either guarantee that Index is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and x64. + + @param Index The 32-bit MSR index to read. + + @return The value of the MSR identified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr64 ( + IN UINT32 Index + ); + + +/** + Writes a 64-bit value to a Machine Specific Register(MSR), and returns the + value. + + Writes the 64-bit value specified by Value to the MSR specified by Index. The + 64-bit value written to the MSR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and Value are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param Value The 64-bit value to write to the MSR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmWriteMsr64 ( + IN UINT32 Index, + IN UINT64 Value + ); + + +/** + Reads a 64-bit MSR, performs a bitwise OR, and writes the result + back to the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit MSR specified by Index. The value written to the MSR is + returned. No parameter checking is performed on Index or OrData, and some of + these may cause CPU exceptions. The caller must either guarantee that Index + and OrData are valid, or the caller must establish proper exception handlers. + This function is only available on IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param OrData The value to OR with the read value from the MSR. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrOr64 ( + IN UINT32 Index, + IN UINT64 OrData + ); + + +/** + Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the + 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between the + read result and the value specified by OrData, and writes the result to the + 64-bit MSR specified by Index. The value written to the MSR is returned. No + parameter checking is performed on Index or OrData, and some of these may + cause CPU exceptions. The caller must either guarantee that Index and OrData + are valid, or the caller must establish proper exception handlers. This + function is only available on IA-32 and x64. + + @param Index The 32-bit MSR index to write. + @param AndData The value to AND with the read value from the MSR. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrAnd64 ( + IN UINT32 Index, + IN UINT64 AndData + ); + + +/** + Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between read + result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 64-bit MSR specified by Index. The value written + to the MSR is returned. No parameter checking is performed on Index, AndData, + or OrData, and some of these may cause CPU exceptions. The caller must either + guarantee that Index, AndData, and OrData are valid, or the caller must + establish proper exception handlers. This function is only available on IA-32 + and x64. + + @param Index The 32-bit MSR index to write. + @param AndData The value to AND with the read value from the MSR. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrAndThenOr64 ( + IN UINT32 Index, + IN UINT64 AndData, + IN UINT64 OrData + ); + + +/** + Reads a bit field of an MSR. + + Reads the bit field in the 64-bit MSR. The bit field is specified by the + StartBit and the EndBit. The value of the bit field is returned. The caller + must either guarantee that Index is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and x64. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Index The 32-bit MSR index to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The value read from the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrBitFieldRead64 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit + ); + + +/** + Writes a bit field to an MSR. + + Writes Value to a bit field in a 64-bit MSR. The bit field is specified by + the StartBit and the EndBit. All other bits in the destination MSR are + preserved. The MSR written is returned. The caller must either guarantee + that Index and the data written is valid, or the caller must set up exception + handlers to catch the exceptions. This function is only available on IA-32 and x64. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param Value New value of the bit field. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrBitFieldWrite64 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise OR, and + writes the result back to the bit field in the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit MSR specified by Index. The value written to the MSR is + returned. Extra left bits in OrData are stripped. The caller must either + guarantee that Index and the data written is valid, or the caller must set up + exception handlers to catch the exceptions. This function is only available + on IA-32 and x64. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param OrData The value to OR with the read value from the bit field. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrBitFieldOr64 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the + result back to the bit field in the 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND between the + read result and the value specified by AndData, and writes the result to the + 64-bit MSR specified by Index. The value written to the MSR is returned. + Extra left bits in AndData are stripped. The caller must either guarantee + that Index and the data written is valid, or the caller must set up exception + handlers to catch the exceptions. This function is only available on IA-32 + and x64. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the bit field. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrBitFieldAnd64 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + + +/** + Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 64-bit MSR. + + Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by + a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 64-bit MSR specified by Index. The + value written to the MSR is returned. Extra left bits in both AndData and + OrData are stripped. The caller must either guarantee that Index and the data + written is valid, or the caller must set up exception handlers to catch the + exceptions. This function is only available on IA-32 and x64. + + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Index The 32-bit MSR index to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the bit field. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MSR. + +**/ +UINT64 +EFIAPI +AsmMsrBitFieldAndThenOr64 ( + IN UINT32 Index, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + + +/** + Reads the current value of the EFLAGS register. + + Reads and returns the current value of the EFLAGS register. This function is + only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a + 64-bit value on x64. + + @return EFLAGS on IA-32 or RFLAGS on x64. + +**/ +UINTN +EFIAPI +AsmReadEflags ( + VOID + ); + + +/** + Reads the current value of the Control Register 0 (CR0). + + Reads and returns the current value of CR0. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 0 (CR0). + +**/ +UINTN +EFIAPI +AsmReadCr0 ( + VOID + ); + + +/** + Reads the current value of the Control Register 2 (CR2). + + Reads and returns the current value of CR2. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 2 (CR2). + +**/ +UINTN +EFIAPI +AsmReadCr2 ( + VOID + ); + + +/** + Reads the current value of the Control Register 3 (CR3). + + Reads and returns the current value of CR3. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 3 (CR3). + +**/ +UINTN +EFIAPI +AsmReadCr3 ( + VOID + ); + + +/** + Reads the current value of the Control Register 4 (CR4). + + Reads and returns the current value of CR4. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of the Control Register 4 (CR4). + +**/ +UINTN +EFIAPI +AsmReadCr4 ( + VOID + ); + + +/** + Writes a value to Control Register 0 (CR0). + + Writes and returns a new value to CR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Cr0 The value to write to CR0. + + @return The value written to CR0. + +**/ +UINTN +EFIAPI +AsmWriteCr0 ( + UINTN Cr0 + ); + + +/** + Writes a value to Control Register 2 (CR2). + + Writes and returns a new value to CR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Cr2 The value to write to CR2. + + @return The value written to CR2. + +**/ +UINTN +EFIAPI +AsmWriteCr2 ( + UINTN Cr2 + ); + + +/** + Writes a value to Control Register 3 (CR3). + + Writes and returns a new value to CR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Cr3 The value to write to CR3. + + @return The value written to CR3. + +**/ +UINTN +EFIAPI +AsmWriteCr3 ( + UINTN Cr3 + ); + + +/** + Writes a value to Control Register 4 (CR4). + + Writes and returns a new value to CR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Cr4 The value to write to CR4. + + @return The value written to CR4. + +**/ +UINTN +EFIAPI +AsmWriteCr4 ( + UINTN Cr4 + ); + + +/** + Reads the current value of Debug Register 0 (DR0). + + Reads and returns the current value of DR0. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmReadDr0 ( + VOID + ); + + +/** + Reads the current value of Debug Register 1 (DR1). + + Reads and returns the current value of DR1. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmReadDr1 ( + VOID + ); + + +/** + Reads the current value of Debug Register 2 (DR2). + + Reads and returns the current value of DR2. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmReadDr2 ( + VOID + ); + + +/** + Reads the current value of Debug Register 3 (DR3). + + Reads and returns the current value of DR3. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmReadDr3 ( + VOID + ); + + +/** + Reads the current value of Debug Register 4 (DR4). + + Reads and returns the current value of DR4. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmReadDr4 ( + VOID + ); + + +/** + Reads the current value of Debug Register 5 (DR5). + + Reads and returns the current value of DR5. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmReadDr5 ( + VOID + ); + + +/** + Reads the current value of Debug Register 6 (DR6). + + Reads and returns the current value of DR6. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmReadDr6 ( + VOID + ); + + +/** + Reads the current value of Debug Register 7 (DR7). + + Reads and returns the current value of DR7. This function is only available + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. + + @return The value of Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmReadDr7 ( + VOID + ); + + +/** + Writes a value to Debug Register 0 (DR0). + + Writes and returns a new value to DR0. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr0 The value to write to Dr0. + + @return The value written to Debug Register 0 (DR0). + +**/ +UINTN +EFIAPI +AsmWriteDr0 ( + UINTN Dr0 + ); + + +/** + Writes a value to Debug Register 1 (DR1). + + Writes and returns a new value to DR1. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr1 The value to write to Dr1. + + @return The value written to Debug Register 1 (DR1). + +**/ +UINTN +EFIAPI +AsmWriteDr1 ( + UINTN Dr1 + ); + + +/** + Writes a value to Debug Register 2 (DR2). + + Writes and returns a new value to DR2. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr2 The value to write to Dr2. + + @return The value written to Debug Register 2 (DR2). + +**/ +UINTN +EFIAPI +AsmWriteDr2 ( + UINTN Dr2 + ); + + +/** + Writes a value to Debug Register 3 (DR3). + + Writes and returns a new value to DR3. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr3 The value to write to Dr3. + + @return The value written to Debug Register 3 (DR3). + +**/ +UINTN +EFIAPI +AsmWriteDr3 ( + UINTN Dr3 + ); + + +/** + Writes a value to Debug Register 4 (DR4). + + Writes and returns a new value to DR4. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr4 The value to write to Dr4. + + @return The value written to Debug Register 4 (DR4). + +**/ +UINTN +EFIAPI +AsmWriteDr4 ( + UINTN Dr4 + ); + + +/** + Writes a value to Debug Register 5 (DR5). + + Writes and returns a new value to DR5. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr5 The value to write to Dr5. + + @return The value written to Debug Register 5 (DR5). + +**/ +UINTN +EFIAPI +AsmWriteDr5 ( + UINTN Dr5 + ); + + +/** + Writes a value to Debug Register 6 (DR6). + + Writes and returns a new value to DR6. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr6 The value to write to Dr6. + + @return The value written to Debug Register 6 (DR6). + +**/ +UINTN +EFIAPI +AsmWriteDr6 ( + UINTN Dr6 + ); + + +/** + Writes a value to Debug Register 7 (DR7). + + Writes and returns a new value to DR7. This function is only available on + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. + + @param Dr7 The value to write to Dr7. + + @return The value written to Debug Register 7 (DR7). + +**/ +UINTN +EFIAPI +AsmWriteDr7 ( + UINTN Dr7 + ); + + +/** + Reads the current value of Code Segment Register (CS). + + Reads and returns the current value of CS. This function is only available on + IA-32 and x64. + + @return The current value of CS. + +**/ +UINT16 +EFIAPI +AsmReadCs ( + VOID + ); + + +/** + Reads the current value of Data Segment Register (DS). + + Reads and returns the current value of DS. This function is only available on + IA-32 and x64. + + @return The current value of DS. + +**/ +UINT16 +EFIAPI +AsmReadDs ( + VOID + ); + + +/** + Reads the current value of Extra Segment Register (ES). + + Reads and returns the current value of ES. This function is only available on + IA-32 and x64. + + @return The current value of ES. + +**/ +UINT16 +EFIAPI +AsmReadEs ( + VOID + ); + + +/** + Reads the current value of FS Data Segment Register (FS). + + Reads and returns the current value of FS. This function is only available on + IA-32 and x64. + + @return The current value of FS. + +**/ +UINT16 +EFIAPI +AsmReadFs ( + VOID + ); + + +/** + Reads the current value of GS Data Segment Register (GS). + + Reads and returns the current value of GS. This function is only available on + IA-32 and x64. + + @return The current value of GS. + +**/ +UINT16 +EFIAPI +AsmReadGs ( + VOID + ); + + +/** + Reads the current value of Stack Segment Register (SS). + + Reads and returns the current value of SS. This function is only available on + IA-32 and x64. + + @return The current value of SS. + +**/ +UINT16 +EFIAPI +AsmReadSs ( + VOID + ); + + +/** + Reads the current value of Task Register (TR). + + Reads and returns the current value of TR. This function is only available on + IA-32 and x64. + + @return The current value of TR. + +**/ +UINT16 +EFIAPI +AsmReadTr ( + VOID + ); + + +/** + Reads the current Global Descriptor Table Register(GDTR) descriptor. + + Reads and returns the current GDTR descriptor and returns it in Gdtr. This + function is only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +AsmReadGdtr ( + OUT IA32_DESCRIPTOR *Gdtr + ); + + +/** + Writes the current Global Descriptor Table Register (GDTR) descriptor. + + Writes and the current GDTR descriptor specified by Gdtr. This function is + only available on IA-32 and x64. + + If Gdtr is NULL, then ASSERT(). + + @param Gdtr The pointer to a GDTR descriptor. + +**/ +VOID +EFIAPI +AsmWriteGdtr ( + IN CONST IA32_DESCRIPTOR *Gdtr + ); + + +/** + Reads the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Reads and returns the current IDTR descriptor and returns it in Idtr. This + function is only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +AsmReadIdtr ( + OUT IA32_DESCRIPTOR *Idtr + ); + + +/** + Writes the current Interrupt Descriptor Table Register(IDTR) descriptor. + + Writes the current IDTR descriptor and returns it in Idtr. This function is + only available on IA-32 and x64. + + If Idtr is NULL, then ASSERT(). + + @param Idtr The pointer to a IDTR descriptor. + +**/ +VOID +EFIAPI +AsmWriteIdtr ( + IN CONST IA32_DESCRIPTOR *Idtr + ); + + +/** + Reads the current Local Descriptor Table Register(LDTR) selector. + + Reads and returns the current 16-bit LDTR descriptor value. This function is + only available on IA-32 and x64. + + @return The current selector of LDT. + +**/ +UINT16 +EFIAPI +AsmReadLdtr ( + VOID + ); + + +/** + Writes the current Local Descriptor Table Register (LDTR) selector. + + Writes and the current LDTR descriptor specified by Ldtr. This function is + only available on IA-32 and x64. + + @param Ldtr 16-bit LDTR selector value. + +**/ +VOID +EFIAPI +AsmWriteLdtr ( + IN UINT16 Ldtr + ); + + +/** + Save the current floating point/SSE/SSE2 context to a buffer. + + Saves the current floating point/SSE/SSE2 state to the buffer specified by + Buffer. Buffer must be aligned on a 16-byte boundary. This function is only + available on IA-32 and x64. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-byte boundary, then ASSERT(). + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +AsmFxSave ( + OUT IA32_FX_BUFFER *Buffer + ); + + +/** + Restores the current floating point/SSE/SSE2 context from a buffer. + + Restores the current floating point/SSE/SSE2 state from the buffer specified + by Buffer. Buffer must be aligned on a 16-byte boundary. This function is + only available on IA-32 and x64. + + If Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-byte boundary, then ASSERT(). + If Buffer was not saved with AsmFxSave(), then ASSERT(). + + @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context. + +**/ +VOID +EFIAPI +AsmFxRestore ( + IN CONST IA32_FX_BUFFER *Buffer + ); + + +/** + Reads the current value of 64-bit MMX Register #0 (MM0). + + Reads and returns the current value of MM0. This function is only available + on IA-32 and x64. + + @return The current value of MM0. + +**/ +UINT64 +EFIAPI +AsmReadMm0 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #1 (MM1). + + Reads and returns the current value of MM1. This function is only available + on IA-32 and x64. + + @return The current value of MM1. + +**/ +UINT64 +EFIAPI +AsmReadMm1 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #2 (MM2). + + Reads and returns the current value of MM2. This function is only available + on IA-32 and x64. + + @return The current value of MM2. + +**/ +UINT64 +EFIAPI +AsmReadMm2 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #3 (MM3). + + Reads and returns the current value of MM3. This function is only available + on IA-32 and x64. + + @return The current value of MM3. + +**/ +UINT64 +EFIAPI +AsmReadMm3 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #4 (MM4). + + Reads and returns the current value of MM4. This function is only available + on IA-32 and x64. + + @return The current value of MM4. + +**/ +UINT64 +EFIAPI +AsmReadMm4 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #5 (MM5). + + Reads and returns the current value of MM5. This function is only available + on IA-32 and x64. + + @return The current value of MM5. + +**/ +UINT64 +EFIAPI +AsmReadMm5 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #6 (MM6). + + Reads and returns the current value of MM6. This function is only available + on IA-32 and x64. + + @return The current value of MM6. + +**/ +UINT64 +EFIAPI +AsmReadMm6 ( + VOID + ); + + +/** + Reads the current value of 64-bit MMX Register #7 (MM7). + + Reads and returns the current value of MM7. This function is only available + on IA-32 and x64. + + @return The current value of MM7. + +**/ +UINT64 +EFIAPI +AsmReadMm7 ( + VOID + ); + + +/** + Writes the current value of 64-bit MMX Register #0 (MM0). + + Writes the current value of MM0. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM0. + +**/ +VOID +EFIAPI +AsmWriteMm0 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #1 (MM1). + + Writes the current value of MM1. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM1. + +**/ +VOID +EFIAPI +AsmWriteMm1 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #2 (MM2). + + Writes the current value of MM2. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM2. + +**/ +VOID +EFIAPI +AsmWriteMm2 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #3 (MM3). + + Writes the current value of MM3. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM3. + +**/ +VOID +EFIAPI +AsmWriteMm3 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #4 (MM4). + + Writes the current value of MM4. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM4. + +**/ +VOID +EFIAPI +AsmWriteMm4 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #5 (MM5). + + Writes the current value of MM5. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM5. + +**/ +VOID +EFIAPI +AsmWriteMm5 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #6 (MM6). + + Writes the current value of MM6. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM6. + +**/ +VOID +EFIAPI +AsmWriteMm6 ( + IN UINT64 Value + ); + + +/** + Writes the current value of 64-bit MMX Register #7 (MM7). + + Writes the current value of MM7. This function is only available on IA32 and + x64. + + @param Value The 64-bit value to write to MM7. + +**/ +VOID +EFIAPI +AsmWriteMm7 ( + IN UINT64 Value + ); + + +/** + Reads the current value of Time Stamp Counter (TSC). + + Reads and returns the current value of TSC. This function is only available + on IA-32 and x64. + + @return The current value of TSC + +**/ +UINT64 +EFIAPI +AsmReadTsc ( + VOID + ); + + +/** + Reads the current value of a Performance Counter (PMC). + + Reads and returns the current value of performance counter specified by + Index. This function is only available on IA-32 and x64. + + @param Index The 32-bit Performance Counter index to read. + + @return The value of the PMC specified by Index. + +**/ +UINT64 +EFIAPI +AsmReadPmc ( + IN UINT32 Index + ); + + +/** + Sets up a monitor buffer that is used by AsmMwait(). + + Executes a MONITOR instruction with the register state specified by Eax, Ecx + and Edx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONITOR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONITOR + instruction. + @param Edx The value to load into EDX or RDX before executing the MONITOR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +AsmMonitor ( + IN UINTN Eax, + IN UINTN Ecx, + IN UINTN Edx + ); + + +/** + Executes an MWAIT instruction. + + Executes an MWAIT instruction with the register state specified by Eax and + Ecx. Returns Eax. This function is only available on IA-32 and x64. + + @param Eax The value to load into EAX or RAX before executing the MONITOR + instruction. + @param Ecx The value to load into ECX or RCX before executing the MONITOR + instruction. + + @return Eax + +**/ +UINTN +EFIAPI +AsmMwait ( + IN UINTN Eax, + IN UINTN Ecx + ); + + +/** + Executes a WBINVD instruction. + + Executes a WBINVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmWbinvd ( + VOID + ); + + +/** + Executes a INVD instruction. + + Executes a INVD instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmInvd ( + VOID + ); + + +/** + Flushes a cache line from all the instruction and data caches within the + coherency domain of the CPU. + + Flushed the cache line specified by LinearAddress, and returns LinearAddress. + This function is only available on IA-32 and x64. + + @param LinearAddress The address of the cache line to flush. If the CPU is + in a physical addressing mode, then LinearAddress is a + physical address. If the CPU is in a virtual + addressing mode, then LinearAddress is a virtual + address. + + @return LinearAddress. +**/ +VOID * +EFIAPI +AsmFlushCacheLine ( + IN VOID *LinearAddress + ); + + +/** + Enables the 32-bit paging mode on the CPU. + + Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode. This function is + only available on IA-32. After the 32-bit paging mode is enabled, control is + transferred to the function specified by EntryPoint using the new stack + specified by NewStack and passing in the parameters specified by Context1 and + Context2. Context1 and Context2 are optional and may be NULL. The function + EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode, then ASSERT(). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling this + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit protected mode with flat descriptors. This + means all descriptors must have a base of 0 and a limit of 4GB. + 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat + descriptors. + 4) CR3 must point to valid page tables that will be used once the transition + is complete, and those page tables must guarantee that the pages for this + function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack after + paging is enabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is enabled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is enabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is enabled. + +**/ +VOID +EFIAPI +AsmEnablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ); + + +/** + Disables the 32-bit paging mode on the CPU. + + Disables the 32-bit paging mode on the CPU and returns to 32-bit protected + mode. This function assumes the current execution mode is 32-paged protected + mode. This function is only available on IA-32. After the 32-bit paging mode + is disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional and + may be NULL. The function EntryPoint must never return. + + If the current execution mode is not 32-bit paged mode, then ASSERT(). + If EntryPoint is NULL, then ASSERT(). + If NewStack is NULL, then ASSERT(). + + There are a number of constraints that must be followed before calling this + function: + 1) Interrupts must be disabled. + 2) The caller must be in 32-bit paged mode. + 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode. + 4) CR3 must point to valid page tables that guarantee that the pages for + this function and the stack are identity mapped. + + @param EntryPoint A pointer to function to call with the new stack after + paging is disabled. + @param Context1 A pointer to the context to pass into the EntryPoint + function as the first parameter after paging is disabled. + @param Context2 A pointer to the context to pass into the EntryPoint + function as the second parameter after paging is + disabled. + @param NewStack A pointer to the new stack to use for the EntryPoint + function after paging is disabled. + +**/ +VOID +EFIAPI +AsmDisablePaging32 ( + IN SWITCH_STACK_ENTRY_POINT EntryPoint, + IN VOID *Context1, OPTIONAL + IN VOID *Context2, OPTIONAL + IN VOID *NewStack + ); + + +/** + Enables the 64-bit paging mode on the CPU. + + Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables + must be properly initialized prior to calling this service. This function + assumes the current execution mode is 32-bit protected mode with flat + descriptors. This function is only available on IA-32. After the 64-bit + paging mode is enabled, control is transferred to the function specified by + EntryPoint using the new stack specified by NewStack and passing in the + parameters specified by Context1 and Context2. Context1 and Context2 are + optional and may be 0. The function EntryPoint must never return. + + If the current execution mode is not 32-bit protected mode with flat + descriptors, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPoint + is called. The descriptor in the GDT that this selector + references must be setup for long mode. + @param EntryPoint The 64-bit virtual address of the function to call with + the new stack after paging is enabled. + @param Context1 The 64-bit virtual address of the context to pass into + the EntryPoint function as the first parameter after + paging is enabled. + @param Context2 The 64-bit virtual address of the context to pass into + the EntryPoint function as the second parameter after + paging is enabled. + @param NewStack The 64-bit virtual address of the new stack to use for + the EntryPoint function after paging is enabled. + +**/ +VOID +EFIAPI +AsmEnablePaging64 ( + IN UINT16 Cs, + IN UINT64 EntryPoint, + IN UINT64 Context1, OPTIONAL + IN UINT64 Context2, OPTIONAL + IN UINT64 NewStack + ); + + +/** + Disables the 64-bit paging mode on the CPU. + + Disables the 64-bit paging mode on the CPU and returns to 32-bit protected + mode. This function assumes the current execution mode is 64-paging mode. + This function is only available on x64. After the 64-bit paging mode is + disabled, control is transferred to the function specified by EntryPoint + using the new stack specified by NewStack and passing in the parameters + specified by Context1 and Context2. Context1 and Context2 are optional and + may be 0. The function EntryPoint must never return. + + If the current execution mode is not 64-bit paged mode, then ASSERT(). + If EntryPoint is 0, then ASSERT(). + If NewStack is 0, then ASSERT(). + + @param Cs The 16-bit selector to load in the CS before EntryPoint + is called. The descriptor in the GDT that this selector + references must be setup for 32-bit protected mode. + @param EntryPoint The 64-bit virtual address of the function to call with + the new stack after paging is disabled. + @param Context1 The 64-bit virtual address of the context to pass into + the EntryPoint function as the first parameter after + paging is disabled. + @param Context2 The 64-bit virtual address of the context to pass into + the EntryPoint function as the second parameter after + paging is disabled. + @param NewStack The 64-bit virtual address of the new stack to use for + the EntryPoint function after paging is disabled. + +**/ +VOID +EFIAPI +AsmDisablePaging64 ( + IN UINT16 Cs, + IN UINT32 EntryPoint, + IN UINT32 Context1, OPTIONAL + IN UINT32 Context2, OPTIONAL + IN UINT32 NewStack + ); + + +// +// 16-bit thunking services +// + +/** + Retrieves the properties for 16-bit thunk functions. + + Computes the size of the buffer and stack below 1MB required to use the + AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This + buffer size is returned in RealModeBufferSize, and the stack size is returned + in ExtraStackSize. If parameters are passed to the 16-bit real mode code, + then the actual minimum stack size is ExtraStackSize plus the maximum number + of bytes that need to be passed to the 16-bit real mode code. + + If RealModeBufferSize is NULL, then ASSERT(). + If ExtraStackSize is NULL, then ASSERT(). + + @param RealModeBufferSize A pointer to the size of the buffer below 1MB + required to use the 16-bit thunk functions. + @param ExtraStackSize A pointer to the extra size of stack below 1MB + that the 16-bit thunk functions require for + temporary storage in the transition to and from + 16-bit real mode. + +**/ +VOID +EFIAPI +AsmGetThunk16Properties ( + OUT UINT32 *RealModeBufferSize, + OUT UINT32 *ExtraStackSize + ); + + +/** + Prepares all structures a code required to use AsmThunk16(). + + Prepares all structures and code required to use AsmThunk16(). + + This interface is limited to be used in either physical mode or virtual modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1. + + If ThunkContext is NULL, then ASSERT(). + + @param ThunkContext A pointer to the context structure that describes the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmPrepareThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ); + + +/** + Transfers control to a 16-bit real mode entry point and returns the results. + + Transfers control to a 16-bit real mode entry point and returns the results. + AsmPrepareThunk16() must be called with ThunkContext before this function is used. + This function must be called with interrupts disabled. + + The register state from the RealModeState field of ThunkContext is restored just prior + to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState, + which is used to set the interrupt state when a 16-bit real mode entry point is called. + Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState. + The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to + the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function. + The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction, + so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment + and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry + point must exit with a RETF instruction. The register state is captured into RealModeState immediately + after the RETF instruction is executed. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, + or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure + the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode. + + If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, + then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode. + This includes the base vectors, the interrupt masks, and the edge/level trigger mode. + + If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code + is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits. + + If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to + disable the A20 mask. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in + ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails, + then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports. + + If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in + ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports. + + If ThunkContext is NULL, then ASSERT(). + If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT(). + If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in + ThunkAttributes, then ASSERT(). + + This interface is limited to be used in either physical mode or virtual modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1. + + @param ThunkContext A pointer to the context structure that describes the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ); + + +/** + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. + + Prepares all structures and code for a 16-bit real mode thunk, transfers + control to a 16-bit real mode entry point, and returns the results. If the + caller only need to perform a single 16-bit real mode thunk, then this + service should be used. If the caller intends to make more than one 16-bit + real mode thunk, then it is more efficient if AsmPrepareThunk16() is called + once and AsmThunk16() can be called for each 16-bit real mode thunk. + + This interface is limited to be used in either physical mode or virtual modes with paging enabled where the + virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1. + + See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions. + + @param ThunkContext A pointer to the context structure that describes the + 16-bit real mode code to call. + +**/ +VOID +EFIAPI +AsmPrepareAndThunk16 ( + IN OUT THUNK_CONTEXT *ThunkContext + ); + +/** + Generates a 16-bit random number through RDRAND instruction. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the random result. + + @retval TRUE RDRAND call was successful. + @retval FALSE Failed attempts to call RDRAND. + + **/ +BOOLEAN +EFIAPI +AsmRdRand16 ( + OUT UINT16 *Rand + ); + +/** + Generates a 32-bit random number through RDRAND instruction. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the random result. + + @retval TRUE RDRAND call was successful. + @retval FALSE Failed attempts to call RDRAND. + +**/ +BOOLEAN +EFIAPI +AsmRdRand32 ( + OUT UINT32 *Rand + ); + +/** + Generates a 64-bit random number through RDRAND instruction. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the random result. + + @retval TRUE RDRAND call was successful. + @retval FALSE Failed attempts to call RDRAND. + +**/ +BOOLEAN +EFIAPI +AsmRdRand64 ( + OUT UINT64 *Rand + ); + +/** + Load given selector into TR register. + + @param[in] Selector Task segment selector +**/ +VOID +EFIAPI +AsmWriteTr ( + IN UINT16 Selector + ); + +/** + Performs a serializing operation on all load-from-memory instructions that + were issued prior the AsmLfence function. + + Executes a LFENCE instruction. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmLfence ( + VOID + ); + +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 and + x64. + + @param[in] Index Extended control register index + + @return The current value of the extended control register +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ); + +/** + Executes a XSETBV instruction to write a 64-bit value to a Extended Control + Register(XCR), and returns the value. + + Writes the 64-bit value specified by Value to the XCR specified by Index. The + 64-bit value written to the XCR is returned. No parameter checking is + performed on Index or Value, and some of these may cause CPU exceptions. The + caller must either guarantee that Index and Value are valid, or the caller + must establish proper exception handlers. This function is only available on + IA-32 and x64. + + @param Index The 32-bit XCR index to write. + @param Value The 64-bit value to write to the XCR. + + @return Value + +**/ +UINT64 +EFIAPI +AsmXSetBv ( + IN UINT32 Index, + IN UINT64 Value + ); + +/** + Executes a VMGEXIT instruction (VMMCALL with a REP prefix) + + Executes a VMGEXIT instruction. This function is only available on IA-32 and + x64. + +**/ +VOID +EFIAPI +AsmVmgExit ( + VOID + ); + + +/** + Patch the immediate operand of an IA32 or X64 instruction such that the byte, + word, dword or qword operand is encoded at the end of the instruction's + binary representation. + + This function should be used to update object code that was compiled with + NASM from assembly source code. Example: + + NASM source code: + + mov eax, strict dword 0 ; the imm32 zero operand will be patched + ASM_PFX(gPatchCr3): + mov cr3, eax + + C source code: + + X86_ASSEMBLY_PATCH_LABEL gPatchCr3; + PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4); + + @param[out] InstructionEnd Pointer right past the instruction to patch. The + immediate operand to patch is expected to + comprise the trailing bytes of the instruction. + If InstructionEnd is closer to address 0 than + ValueSize permits, then ASSERT(). + + @param[in] PatchValue The constant to write to the immediate operand. + The caller is responsible for ensuring that + PatchValue can be represented in the byte, word, + dword or qword operand (as indicated through + ValueSize); otherwise ASSERT(). + + @param[in] ValueSize The size of the operand in bytes; must be 1, 2, + 4, or 8. ASSERT() otherwise. +**/ +VOID +EFIAPI +PatchInstructionX86 ( + OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd, + IN UINT64 PatchValue, + IN UINTN ValueSize + ); + +#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +#endif // !defined (__BASE_LIB__) diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseMemoryLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseMemoryLib.h new file mode 100644 index 0000000000..3c764aebc5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/BaseMemoryLib.h @@ -0,0 +1,483 @@ +/** @file + Provides copy memory, fill memory, zero memory, and GUID functions. + + The Base Memory Library provides optimized implementations for common memory-based operations. + These functions should be used in place of coding your own loops to do equivalent common functions. + This allows optimized library implementations to help increase performance. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __BASE_MEMORY_LIB__ +#define __BASE_MEMORY_LIB__ + +/** + Copies a source buffer to a destination buffer, and returns the destination buffer. + + This function copies Length bytes from SourceBuffer to DestinationBuffer, and returns + DestinationBuffer. The implementation must be reentrant, and it must handle the case + where SourceBuffer overlaps DestinationBuffer. + + If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT(). + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @return DestinationBuffer. + +**/ +VOID * +EFIAPI +CopyMem ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Fills a target buffer with a byte value, and returns the target buffer. + + This function fills Length bytes of Buffer with Value, and returns Buffer. + + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The memory to set. + @param Length The number of bytes to set. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ); + +/** + Fills a target buffer with a 16-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 16-bit value specified by + Value, and returns Buffer. Value is repeated every 16-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem16 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ); + +/** + Fills a target buffer with a 32-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 32-bit value specified by + Value, and returns Buffer. Value is repeated every 32-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem32 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ); + +/** + Fills a target buffer with a 64-bit value, and returns the target buffer. + + This function fills Length bytes of Buffer with the 64-bit value specified by + Value, and returns Buffer. Value is repeated every 64-bits in for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMem64 ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ); + +/** + Fills a target buffer with a value that is size UINTN, and returns the target buffer. + + This function fills Length bytes of Buffer with the UINTN sized value specified by + Value, and returns Buffer. Value is repeated every sizeof(UINTN) bytes for Length + bytes of Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + If Buffer is not aligned on a UINTN boundary, then ASSERT(). + If Length is not aligned on a UINTN boundary, then ASSERT(). + + @param Buffer The pointer to the target buffer to fill. + @param Length The number of bytes in Buffer to fill. + @param Value The value with which to fill Length bytes of Buffer. + + @return Buffer. + +**/ +VOID * +EFIAPI +SetMemN ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINTN Value + ); + +/** + Fills a target buffer with zeros, and returns the target buffer. + + This function fills Length bytes of Buffer with zeros, and returns Buffer. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to fill with zeros. + @param Length The number of bytes in Buffer to fill with zeros. + + @return Buffer. + +**/ +VOID * +EFIAPI +ZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ); + +/** + Compares the contents of two buffers. + + This function compares Length bytes of SourceBuffer to Length bytes of DestinationBuffer. + If all Length bytes of the two buffers are identical, then 0 is returned. Otherwise, the + value returned is the first mismatched byte in SourceBuffer subtracted from the first + mismatched byte in DestinationBuffer. + + If Length > 0 and DestinationBuffer is NULL, then ASSERT(). + If Length > 0 and SourceBuffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT(). + + @param DestinationBuffer The pointer to the destination buffer to compare. + @param SourceBuffer The pointer to the source buffer to compare. + @param Length The number of bytes to compare. + + @return 0 All Length bytes of the two buffers are identical. + @retval Non-zero The first mismatched byte in SourceBuffer subtracted from the first + mismatched byte in DestinationBuffer. + +**/ +INTN +EFIAPI +CompareMem ( + IN CONST VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Scans a target buffer for an 8-bit value, and returns a pointer to the matching 8-bit value + in the target buffer. + + This function searches target the buffer specified by Buffer and Length from the lowest + address to the highest address for an 8-bit value that matches Value. If a match is found, + then a pointer to the matching byte in the target buffer is returned. If no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanMem8 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ); + +/** + Scans a target buffer for a 16-bit value, and returns a pointer to the matching 16-bit value + in the target buffer. + + This function searches target the buffer specified by Buffer and Length from the lowest + address to the highest address for a 16-bit value that matches Value. If a match is found, + then a pointer to the matching byte in the target buffer is returned. If no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanMem16 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT16 Value + ); + +/** + Scans a target buffer for a 32-bit value, and returns a pointer to the matching 32-bit value + in the target buffer. + + This function searches target the buffer specified by Buffer and Length from the lowest + address to the highest address for a 32-bit value that matches Value. If a match is found, + then a pointer to the matching byte in the target buffer is returned. If no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanMem32 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT32 Value + ); + +/** + Scans a target buffer for a 64-bit value, and returns a pointer to the matching 64-bit value + in the target buffer. + + This function searches target the buffer specified by Buffer and Length from the lowest + address to the highest address for a 64-bit value that matches Value. If a match is found, + then a pointer to the matching byte in the target buffer is returned. If no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanMem64 ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINT64 Value + ); + +/** + Scans a target buffer for a UINTN sized value, and returns a pointer to the matching + UINTN sized value in the target buffer. + + This function searches target the buffer specified by Buffer and Length from the lowest + address to the highest address for a UINTN sized value that matches Value. If a match is found, + then a pointer to the matching byte in the target buffer is returned. If no match is found, + then NULL is returned. If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a UINTN boundary, then ASSERT(). + If Length is not aligned on a UINTN boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Value The value to search for in the target buffer. + + @return A pointer to the matching byte in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanMemN ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN UINTN Value + ); + +/** + Copies a source GUID to a destination GUID. + + This function copies the contents of the 128-bit GUID specified by SourceGuid to + DestinationGuid, and returns DestinationGuid. + + If DestinationGuid is NULL, then ASSERT(). + If SourceGuid is NULL, then ASSERT(). + + @param DestinationGuid The pointer to the destination GUID. + @param SourceGuid The pointer to the source GUID. + + @return DestinationGuid. + +**/ +GUID * +EFIAPI +CopyGuid ( + OUT GUID *DestinationGuid, + IN CONST GUID *SourceGuid + ); + +/** + Compares two GUIDs. + + This function compares Guid1 to Guid2. If the GUIDs are identical then TRUE is returned. + If there are any bit differences in the two GUIDs, then FALSE is returned. + + If Guid1 is NULL, then ASSERT(). + If Guid2 is NULL, then ASSERT(). + + @param Guid1 A pointer to a 128 bit GUID. + @param Guid2 A pointer to a 128 bit GUID. + + @retval TRUE Guid1 and Guid2 are identical. + @retval FALSE Guid1 and Guid2 are not identical. + +**/ +BOOLEAN +EFIAPI +CompareGuid ( + IN CONST GUID *Guid1, + IN CONST GUID *Guid2 + ); + +/** + Scans a target buffer for a GUID, and returns a pointer to the matching GUID + in the target buffer. + + This function searches target the buffer specified by Buffer and Length from + the lowest address to the highest address at 128-bit increments for the 128-bit + GUID value that matches Guid. If a match is found, then a pointer to the matching + GUID in the target buffer is returned. If no match is found, then NULL is returned. + If Length is 0, then NULL is returned. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + If Length is not aligned on a 128-bit boundary, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to scan. + @param Length The number of bytes in Buffer to scan. + @param Guid The value to search for in the target buffer. + + @return A pointer to the matching Guid in the target buffer, otherwise NULL. + +**/ +VOID * +EFIAPI +ScanGuid ( + IN CONST VOID *Buffer, + IN UINTN Length, + IN CONST GUID *Guid + ); + +/** + Checks if the given GUID is a zero GUID. + + This function checks whether the given GUID is a zero GUID. If the GUID is + identical to a zero GUID then TRUE is returned. Otherwise, FALSE is returned. + + If Guid is NULL, then ASSERT(). + + @param Guid The pointer to a 128 bit GUID. + + @retval TRUE Guid is a zero GUID. + @retval FALSE Guid is not a zero GUID. + +**/ +BOOLEAN +EFIAPI +IsZeroGuid ( + IN CONST GUID *Guid + ); + +/** + Checks if the contents of a buffer are all zeros. + + This function checks whether the contents of a buffer are all zeros. If the + contents are all zeros, return TRUE. Otherwise, return FALSE. + + If Length > 0 and Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the buffer to be checked. + @param Length The size of the buffer (in bytes) to be checked. + + @retval TRUE Contents of the buffer are all zeros. + @retval FALSE Contents of the buffer are not all zeros. + +**/ +BOOLEAN +EFIAPI +IsZeroBuffer ( + IN CONST VOID *Buffer, + IN UINTN Length + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CacheMaintenanceLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CacheMaintenanceLib.h new file mode 100644 index 0000000000..18bd6050f4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CacheMaintenanceLib.h @@ -0,0 +1,206 @@ +/** @file + Provides services to maintain instruction and data caches. + + The Cache Maintenance Library provides abstractions for basic processor cache operations. + It removes the need to use assembly in C code. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CACHE_MAINTENANCE_LIB__ +#define __CACHE_MAINTENANCE_LIB__ + +/** + Invalidates the entire instruction cache in cache coherency domain of the + calling CPU. + +**/ +VOID +EFIAPI +InvalidateInstructionCache ( + VOID + ); + +/** + Invalidates a range of instruction cache lines in the cache coherency domain + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length. If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, then no instruction cache + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode, then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + +/** + Writes Back and Invalidates the entire data cache in cache coherency domain + of the calling CPU. + + Writes Back and Invalidates the entire data cache in cache coherency domain + of the calling CPU. This function guarantees that all dirty cache lines are + written back to system memory, and also invalidates all the data cache lines + in the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackInvalidateDataCache ( + VOID + ); + +/** + Writes Back and Invalidates a range of data cache lines in the cache + coherency domain of the calling CPU. + + Writes Back and Invalidate the data cache lines specified by Address and + Length. If Address is not aligned on a cache line boundary, then entire data + cache line containing Address is written back and invalidated. If Address + + Length is not aligned on a cache line boundary, then the entire data cache + line containing Address + Length -1 is written back and invalidated. This + function may choose to write back and invalidate the entire data cache if + that is more efficient than writing back and invalidating the specified + range. If Length is 0, then no data cache lines are written back and + invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back and + invalidate. If the CPU is in a physical addressing mode, then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + @param Length The number of bytes to write back and invalidate from the + data cache. + + @return Address of cache invalidation. + +**/ +VOID * +EFIAPI +WriteBackInvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + +/** + Writes Back the entire data cache in cache coherency domain of the calling + CPU. + + Writes Back the entire data cache in cache coherency domain of the calling + CPU. This function guarantees that all dirty cache lines are written back to + system memory. This function may also invalidate all the data cache lines in + the cache coherency domain of the calling CPU. + +**/ +VOID +EFIAPI +WriteBackDataCache ( + VOID + ); + +/** + Writes Back a range of data cache lines in the cache coherency domain of the + calling CPU. + + Writes Back the data cache lines specified by Address and Length. If Address + is not aligned on a cache line boundary, then entire data cache line + containing Address is written back. If Address + Length is not aligned on a + cache line boundary, then the entire data cache line containing Address + + Length -1 is written back. This function may choose to write back the entire + data cache if that is more efficient than writing back the specified range. + If Length is 0, then no data cache lines are written back. This function may + also invalidate all the data cache lines in the specified range of the cache + coherency domain of the calling CPU. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to write back. If + the CPU is in a physical addressing mode, then Address is a + physical address. If the CPU is in a virtual addressing + mode, then Address is a virtual address. + @param Length The number of bytes to write back from the data cache. + + @return Address of cache written in main memory. + +**/ +VOID * +EFIAPI +WriteBackDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + +/** + Invalidates the entire data cache in cache coherency domain of the calling + CPU. + + Invalidates the entire data cache in cache coherency domain of the calling + CPU. This function must be used with care because dirty cache lines are not + written back to system memory. It is typically used for cache diagnostics. If + the CPU does not support invalidation of the entire data cache, then a write + back and invalidate operation should be performed on the entire data cache. + +**/ +VOID +EFIAPI +InvalidateDataCache ( + VOID + ); + +/** + Invalidates a range of data cache lines in the cache coherency domain of the + calling CPU. + + Invalidates the data cache lines specified by Address and Length. If Address + is not aligned on a cache line boundary, then entire data cache line + containing Address is invalidated. If Address + Length is not aligned on a + cache line boundary, then the entire data cache line containing Address + + Length -1 is invalidated. This function must never invalidate any cache lines + outside the specified range. If Length is 0, the no data cache lines are + invalidated. Address is returned. This function must be used with care + because dirty cache lines are not written back to system memory. It is + typically used for cache diagnostics. If the CPU does not support + invalidation of a data cache range, then a write back and invalidate + operation should be performed on the data cache range. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the data cache lines to invalidate. If + the CPU is in a physical addressing mode, then Address is a + physical address. If the CPU is in a virtual addressing mode, + then Address is a virtual address. + @param Length The number of bytes to invalidate from the data cache. + + @return Address. + +**/ +VOID * +EFIAPI +InvalidateDataCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CpuLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CpuLib.h new file mode 100644 index 0000000000..76e4fd1708 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/CpuLib.h @@ -0,0 +1,45 @@ +/** @file + Provides CPU architecture specific functions that can not be defined + in the Base Library due to dependencies on the PAL Library + + The CPU Library provides services to flush CPU TLBs and place the CPU in a sleep state. + The implementation of these services on Itanium processors requires the use of PAL Calls. + PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point. + As a result, these services could not be defined in the Base Library. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CPU_LIB_H__ +#define __CPU_LIB_H__ + +/** + Places the CPU in a sleep state until an interrupt is received. + + Places the CPU in a sleep state until an interrupt is received. If interrupts + are disabled prior to calling this function, then the CPU will be placed in a + sleep state indefinitely. + +**/ +VOID +EFIAPI +CpuSleep ( + VOID + ); + +/** + Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. + + Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. + +**/ +VOID +EFIAPI +CpuFlushTlb ( + VOID + ); + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugLib.h new file mode 100644 index 0000000000..6967f2b68e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugLib.h @@ -0,0 +1,638 @@ +/** @file + Provides services to print debug and assert messages to a debug output device. + + The Debug library supports debug print and asserts based on a combination of macros and code. + The debug library can be turned on and off so that the debug code does not increase the size of an image. + + Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention + of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is + defined, then debug and assert related macros wrapped by it are the NULL implementations. + +Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEBUG_LIB_H__ +#define __DEBUG_LIB_H__ + +// +// Declare bits for PcdDebugPropertyMask +// +#define DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 0x01 +#define DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 0x02 +#define DEBUG_PROPERTY_DEBUG_CODE_ENABLED 0x04 +#define DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED 0x08 +#define DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED 0x10 +#define DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED 0x20 + +// +// Declare bits for PcdDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint() +// +#define DEBUG_INIT 0x00000001 // Initialization +#define DEBUG_WARN 0x00000002 // Warnings +#define DEBUG_LOAD 0x00000004 // Load events +#define DEBUG_FS 0x00000008 // EFI File system +#define DEBUG_POOL 0x00000010 // Alloc & Free (pool) +#define DEBUG_PAGE 0x00000020 // Alloc & Free (page) +#define DEBUG_INFO 0x00000040 // Informational debug messages +#define DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers +#define DEBUG_VARIABLE 0x00000100 // Variable +#define DEBUG_BM 0x00000400 // Boot Manager +#define DEBUG_BLKIO 0x00001000 // BlkIo Driver +#define DEBUG_NET 0x00004000 // Network Io Driver +#define DEBUG_UNDI 0x00010000 // UNDI Driver +#define DEBUG_LOADFILE 0x00020000 // LoadFile +#define DEBUG_EVENT 0x00080000 // Event messages +#define DEBUG_GCD 0x00100000 // Global Coherency Database changes +#define DEBUG_CACHE 0x00200000 // Memory range cachability changes +#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + // significantly impact boot performance +#define DEBUG_ERROR 0x80000000 // Error + +// +// Aliases of debug message mask bits +// +#define EFI_D_INIT DEBUG_INIT +#define EFI_D_WARN DEBUG_WARN +#define EFI_D_LOAD DEBUG_LOAD +#define EFI_D_FS DEBUG_FS +#define EFI_D_POOL DEBUG_POOL +#define EFI_D_PAGE DEBUG_PAGE +#define EFI_D_INFO DEBUG_INFO +#define EFI_D_DISPATCH DEBUG_DISPATCH +#define EFI_D_VARIABLE DEBUG_VARIABLE +#define EFI_D_BM DEBUG_BM +#define EFI_D_BLKIO DEBUG_BLKIO +#define EFI_D_NET DEBUG_NET +#define EFI_D_UNDI DEBUG_UNDI +#define EFI_D_LOADFILE DEBUG_LOADFILE +#define EFI_D_EVENT DEBUG_EVENT +#define EFI_D_VERBOSE DEBUG_VERBOSE +#define EFI_D_ERROR DEBUG_ERROR + +// +// Source file line number. +// Default is use the to compiler provided __LINE__ macro value. The __LINE__ +// mapping can be overriden by predefining DEBUG_LINE_NUMBER +// +// Defining DEBUG_LINE_NUMBER to a fixed value is useful when comparing builds +// across source code formatting changes that may add/remove lines in a source +// file. +// +#ifdef DEBUG_LINE_NUMBER +#else +#define DEBUG_LINE_NUMBER __LINE__ +#endif + +/** + Macro that converts a Boolean expression to a Null-terminated ASCII string. + + The default is to use the C pre-processor stringizing operator '#' to add + quotes around the C expression. If DEBUG_EXPRESSION_STRING_VALUE is defined + then the C expression is converted to the fixed string value. + + Defining DEBUG_EXPRESSION_STRING_VALUE to a fixed value is useful when + comparing builds across source code formatting changes that may make + changes to spaces or parenthesis in a Boolean expression. + + @param Expression Boolean expression. + +**/ + +#ifdef DEBUG_EXPRESSION_STRING_VALUE +#define DEBUG_EXPRESSION_STRING(Expression) DEBUG_EXPRESSION_STRING_VALUE +#else +#define DEBUG_EXPRESSION_STRING(Expression) #Expression +#endif + +/** + Prints a debug message to the debug output device if the specified error level is enabled. + + If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function + GetDebugPrintErrorLevel (), then print the message specified by Format and the + associated variable argument list to the debug output device. + + If Format is NULL, then ASSERT(). + + @param ErrorLevel The error level of the debug message. + @param Format The format string for the debug message to print. + @param ... The variable argument list whose contents are accessed + based on the format string specified by Format. + +**/ +VOID +EFIAPI +DebugPrint ( + IN UINTN ErrorLevel, + IN CONST CHAR8 *Format, + ... + ); + + +/** + Prints a debug message to the debug output device if the specified + error level is enabled. + + If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function + GetDebugPrintErrorLevel (), then print the message specified by Format and + the associated variable argument list to the debug output device. + + If Format is NULL, then ASSERT(). + + @param ErrorLevel The error level of the debug message. + @param Format Format string for the debug message to print. + @param VaListMarker VA_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +DebugVPrint ( + IN UINTN ErrorLevel, + IN CONST CHAR8 *Format, + IN VA_LIST VaListMarker + ); + + +/** + Prints a debug message to the debug output device if the specified + error level is enabled. + This function use BASE_LIST which would provide a more compatible + service than VA_LIST. + + If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function + GetDebugPrintErrorLevel (), then print the message specified by Format and + the associated variable argument list to the debug output device. + + If Format is NULL, then ASSERT(). + + @param ErrorLevel The error level of the debug message. + @param Format Format string for the debug message to print. + @param BaseListMarker BASE_LIST marker for the variable argument list. + +**/ +VOID +EFIAPI +DebugBPrint ( + IN UINTN ErrorLevel, + IN CONST CHAR8 *Format, + IN BASE_LIST BaseListMarker + ); + + +/** + Prints an assert message containing a filename, line number, and description. + This may be followed by a breakpoint or a dead loop. + + Print a message of the form "ASSERT (): \n" + to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of + PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if + DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then + CpuDeadLoop() is called. If neither of these bits are set, then this function + returns immediately after the message is printed to the debug output device. + DebugAssert() must actively prevent recursion. If DebugAssert() is called while + processing another DebugAssert(), then DebugAssert() must return immediately. + + If FileName is NULL, then a string of "(NULL) Filename" is printed. + If Description is NULL, then a string of "(NULL) Description" is printed. + + @param FileName The pointer to the name of the source file that generated the assert condition. + @param LineNumber The line number in the source file that generated the assert condition + @param Description The pointer to the description of the assert condition. + +**/ +VOID +EFIAPI +DebugAssert ( + IN CONST CHAR8 *FileName, + IN UINTN LineNumber, + IN CONST CHAR8 *Description + ); + + +/** + Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer. + + This function fills Length bytes of Buffer with the value specified by + PcdDebugClearMemoryValue, and returns Buffer. + + If Buffer is NULL, then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue. + @param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue. + + @return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue. + +**/ +VOID * +EFIAPI +DebugClearMemory ( + OUT VOID *Buffer, + IN UINTN Length + ); + + +/** + Returns TRUE if ASSERT() macros are enabled. + + This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of + PcdDebugProperyMask is set. Otherwise, FALSE is returned. + + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +DebugAssertEnabled ( + VOID + ); + + +/** + Returns TRUE if DEBUG() macros are enabled. + + This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of + PcdDebugProperyMask is set. Otherwise, FALSE is returned. + + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +DebugPrintEnabled ( + VOID + ); + + +/** + Returns TRUE if DEBUG_CODE() macros are enabled. + + This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of + PcdDebugProperyMask is set. Otherwise, FALSE is returned. + + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +DebugCodeEnabled ( + VOID + ); + + +/** + Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. + + This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of + PcdDebugProperyMask is set. Otherwise, FALSE is returned. + + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set. + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +DebugClearMemoryEnabled ( + VOID + ); + +/** + Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel. + + This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel. + + @retval TRUE Current ErrorLevel is supported. + @retval FALSE Current ErrorLevel is not supported. + +**/ +BOOLEAN +EFIAPI +DebugPrintLevelEnabled ( + IN CONST UINTN ErrorLevel + ); + +/** + Internal worker macro that calls DebugAssert(). + + This macro calls DebugAssert(), passing in the filename, line number, and an + expression that evaluated to FALSE. + + @param Expression Boolean expression that evaluated to FALSE + +**/ +#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED) +/** + Unit test library replacement for DebugAssert() in DebugLib. + + If FileName is NULL, then a string of "(NULL) Filename" is printed. + If Description is NULL, then a string of "(NULL) Description" is printed. + + @param FileName The pointer to the name of the source file that generated the assert condition. + @param LineNumber The line number in the source file that generated the assert condition + @param Description The pointer to the description of the assert condition. + +**/ +VOID +EFIAPI +UnitTestDebugAssert ( + IN CONST CHAR8 *FileName, + IN UINTN LineNumber, + IN CONST CHAR8 *Description + ); + +#if defined(__clang__) && defined(__FILE_NAME__) +#define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression)) +#else +#define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression)) +#endif +#else +#if defined(__clang__) && defined(__FILE_NAME__) +#define _ASSERT(Expression) DebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression)) +#else +#define _ASSERT(Expression) DebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression)) +#endif +#endif + +/** + Internal worker macro that calls DebugPrint(). + + This macro calls DebugPrint() passing in the debug error level, a format + string, and a variable argument list. + __VA_ARGS__ is not supported by EBC compiler, Microsoft Visual Studio .NET 2003 + and Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830. + + @param Expression Expression containing an error level, a format string, + and a variable argument list based on the format string. + +**/ + +#if !defined(MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400) + #define _DEBUG_PRINT(PrintLevel, ...) \ + do { \ + if (DebugPrintLevelEnabled (PrintLevel)) { \ + DebugPrint (PrintLevel, ##__VA_ARGS__); \ + } \ + } while (FALSE) + #define _DEBUG(Expression) _DEBUG_PRINT Expression +#else +#define _DEBUG(Expression) DebugPrint Expression +#endif + +/** + Macro that calls DebugAssert() if an expression evaluates to FALSE. + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED + bit of PcdDebugProperyMask is set, then this macro evaluates the Boolean + expression specified by Expression. If Expression evaluates to FALSE, then + DebugAssert() is called passing in the source filename, source line number, + and Expression. + + @param Expression Boolean expression. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define ASSERT(Expression) \ + do { \ + if (DebugAssertEnabled ()) { \ + if (!(Expression)) { \ + _ASSERT (Expression); \ + ANALYZER_UNREACHABLE (); \ + } \ + } \ + } while (FALSE) +#else + #define ASSERT(Expression) +#endif + +/** + Macro that calls DebugPrint(). + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED + bit of PcdDebugProperyMask is set, then this macro passes Expression to + DebugPrint(). + + @param Expression Expression containing an error level, a format string, + and a variable argument list based on the format string. + + +**/ +#if !defined(MDEPKG_NDEBUG) + #define DEBUG(Expression) \ + do { \ + if (DebugPrintEnabled ()) { \ + _DEBUG (Expression); \ + } \ + } while (FALSE) +#else + #define DEBUG(Expression) +#endif + +/** + Macro that calls DebugAssert() if an EFI_STATUS evaluates to an error code. + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED + bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_STATUS + value specified by StatusParameter. If StatusParameter is an error code, + then DebugAssert() is called passing in the source filename, source line + number, and StatusParameter. + + @param StatusParameter EFI_STATUS value to evaluate. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define ASSERT_EFI_ERROR(StatusParameter) \ + do { \ + if (DebugAssertEnabled ()) { \ + if (EFI_ERROR (StatusParameter)) { \ + DEBUG ((EFI_D_ERROR, "\nASSERT_EFI_ERROR (Status = %r)\n", StatusParameter)); \ + _ASSERT (!EFI_ERROR (StatusParameter)); \ + } \ + } \ + } while (FALSE) +#else + #define ASSERT_EFI_ERROR(StatusParameter) +#endif + +/** + Macro that calls DebugAssert() if a RETURN_STATUS evaluates to an error code. + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED + bit of PcdDebugProperyMask is set, then this macro evaluates the + RETURN_STATUS value specified by StatusParameter. If StatusParameter is an + error code, then DebugAssert() is called passing in the source filename, + source line number, and StatusParameter. + + @param StatusParameter RETURN_STATUS value to evaluate. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define ASSERT_RETURN_ERROR(StatusParameter) \ + do { \ + if (DebugAssertEnabled ()) { \ + if (RETURN_ERROR (StatusParameter)) { \ + DEBUG ((DEBUG_ERROR, "\nASSERT_RETURN_ERROR (Status = %r)\n", \ + StatusParameter)); \ + _ASSERT (!RETURN_ERROR (StatusParameter)); \ + } \ + } \ + } while (FALSE) +#else + #define ASSERT_RETURN_ERROR(StatusParameter) +#endif + +/** + Macro that calls DebugAssert() if a protocol is already installed in the + handle database. + + If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit + of PcdDebugProperyMask is clear, then return. + + If Handle is NULL, then a check is made to see if the protocol specified by Guid + is present on any handle in the handle database. If Handle is not NULL, then + a check is made to see if the protocol specified by Guid is present on the + handle specified by Handle. If the check finds the protocol, then DebugAssert() + is called passing in the source filename, source line number, and Guid. + + If Guid is NULL, then ASSERT(). + + @param Handle The handle to check for the protocol. This is an optional + parameter that may be NULL. If it is NULL, then the entire + handle database is searched. + + @param Guid The pointer to a protocol GUID. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \ + do { \ + if (DebugAssertEnabled ()) { \ + VOID *Instance; \ + ASSERT (Guid != NULL); \ + if (Handle == NULL) { \ + if (!EFI_ERROR (gBS->LocateProtocol ((EFI_GUID *)Guid, NULL, &Instance))) { \ + _ASSERT (Guid already installed in database); \ + } \ + } else { \ + if (!EFI_ERROR (gBS->HandleProtocol (Handle, (EFI_GUID *)Guid, &Instance))) { \ + _ASSERT (Guid already installed on Handle); \ + } \ + } \ + } \ + } while (FALSE) +#else + #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) +#endif + +/** + Macro that marks the beginning of debug source code. + + If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, + then this macro marks the beginning of source code that is included in a module. + Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END() + are not included in a module. + +**/ +#define DEBUG_CODE_BEGIN() do { if (DebugCodeEnabled ()) { UINT8 __DebugCodeLocal + + +/** + The macro that marks the end of debug source code. + + If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, + then this macro marks the end of source code that is included in a module. + Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END() + are not included in a module. + +**/ +#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE) + + +/** + The macro that declares a section of debug source code. + + If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, + then the source code specified by Expression is included in a module. + Otherwise, the source specified by Expression is not included in a module. + +**/ +#define DEBUG_CODE(Expression) \ + DEBUG_CODE_BEGIN (); \ + Expression \ + DEBUG_CODE_END () + + +/** + The macro that calls DebugClearMemory() to clear a buffer to a default value. + + If the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set, + then this macro calls DebugClearMemory() passing in Address and Length. + + @param Address The pointer to a buffer. + @param Length The number of bytes in the buffer to set. + +**/ +#define DEBUG_CLEAR_MEMORY(Address, Length) \ + do { \ + if (DebugClearMemoryEnabled ()) { \ + DebugClearMemory (Address, Length); \ + } \ + } while (FALSE) + + +/** + Macro that calls DebugAssert() if the containing record does not have a + matching signature. If the signatures matches, then a pointer to the data + structure that contains a specified field of that data structure is returned. + This is a lightweight method hide information by placing a public data + structure inside a larger private data structure and using a pointer to the + public data structure to retrieve a pointer to the private data structure. + + If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit + of PcdDebugProperyMask is clear, then this macro computes the offset, in bytes, + of the field specified by Field from the beginning of the data structure specified + by TYPE. This offset is subtracted from Record, and is used to return a pointer + to a data structure of the type specified by TYPE. + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit + of PcdDebugProperyMask is set, then this macro computes the offset, in bytes, + of field specified by Field from the beginning of the data structure specified + by TYPE. This offset is subtracted from Record, and is used to compute a pointer + to a data structure of the type specified by TYPE. The Signature field of the + data structure specified by TYPE is compared to TestSignature. If the signatures + match, then a pointer to the pointer to a data structure of the type specified by + TYPE is returned. If the signatures do not match, then DebugAssert() is called + with a description of "CR has a bad signature" and Record is returned. + + If the data type specified by TYPE does not contain the field specified by Field, + then the module will not compile. + + If TYPE does not contain a field called Signature, then the module will not + compile. + + @param Record The pointer to the field specified by Field within a data + structure of type TYPE. + + @param TYPE The name of the data structure type to return This + data structure must contain the field specified by Field. + + @param Field The name of the field in the data structure specified + by TYPE to which Record points. + + @param TestSignature The 32-bit signature value to match. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define CR(Record, TYPE, Field, TestSignature) \ + (DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \ + (TYPE *) (_ASSERT (CR has Bad Signature), Record) : \ + BASE_CR (Record, TYPE, Field) +#else + #define CR(Record, TYPE, Field, TestSignature) \ + BASE_CR (Record, TYPE, Field) +#endif + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugPrintErrorLevelLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugPrintErrorLevelLib.h new file mode 100644 index 0000000000..f57097f815 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DebugPrintErrorLevelLib.h @@ -0,0 +1,37 @@ +/** @file + Debug Print Error Level Library class + + Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _DEBUG_PRINT_ERROR_LEVEL_LIB_H_ +#define _DEBUG_PRINT_ERROR_LEVEL_LIB_H_ + +/** + Returns the debug print error level mask for the current module. + + @return Debug print error level mask for the current module. + +**/ +UINT32 +EFIAPI +GetDebugPrintErrorLevel ( + VOID + ); + +/** + Sets the global debug print error level mask fpr the entire platform. + + @param ErrorLevel Global debug print error level + + @retval TRUE The debug print error level mask was successfully set. + @retval FALSE The debug print error level mask could not be set. + +**/ +BOOLEAN +EFIAPI +SetDebugPrintErrorLevel ( + UINT32 ErrorLevel + ); +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DevicePathLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DevicePathLib.h new file mode 100644 index 0000000000..687b5b30dd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DevicePathLib.h @@ -0,0 +1,561 @@ +/** @file + Provides library functions to construct and parse UEFI Device Paths. + + This library provides defines, macros, and functions to help create and parse + EFI_DEVICE_PATH_PROTOCOL structures. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEVICE_PATH_LIB_H__ +#define __DEVICE_PATH_LIB_H__ + +#define END_DEVICE_PATH_LENGTH (sizeof (EFI_DEVICE_PATH_PROTOCOL)) + +/** + Determine whether a given device path is valid. + + @param DevicePath A pointer to a device path data structure. + @param MaxSize The maximum size of the device path data structure. + + @retval TRUE DevicePath is valid. + @retval FALSE DevicePath is NULL. + @retval FALSE Maxsize is less than sizeof(EFI_DEVICE_PATH_PROTOCOL). + @retval FALSE The length of any node node in the DevicePath is less + than sizeof (EFI_DEVICE_PATH_PROTOCOL). + @retval FALSE If MaxSize is not zero, the size of the DevicePath + exceeds MaxSize. + @retval FALSE If PcdMaximumDevicePathNodeCount is not zero, the node + count of the DevicePath exceeds PcdMaximumDevicePathNodeCount. +**/ +BOOLEAN +EFIAPI +IsDevicePathValid ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN UINTN MaxSize + ); + +/** + Returns the Type field of a device path node. + + Returns the Type field of the device path node specified by Node. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @return The Type field of the device path node specified by Node. + +**/ +UINT8 +EFIAPI +DevicePathType ( + IN CONST VOID *Node + ); + +/** + Returns the SubType field of a device path node. + + Returns the SubType field of the device path node specified by Node. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @return The SubType field of the device path node specified by Node. + +**/ +UINT8 +EFIAPI +DevicePathSubType ( + IN CONST VOID *Node + ); + +/** + Returns the 16-bit Length field of a device path node. + + Returns the 16-bit Length field of the device path node specified by Node. + Node is not required to be aligned on a 16-bit boundary, so it is recommended + that a function such as ReadUnaligned16() be used to extract the contents of + the Length field. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @return The 16-bit Length field of the device path node specified by Node. + +**/ +UINTN +EFIAPI +DevicePathNodeLength ( + IN CONST VOID *Node + ); + +/** + Returns a pointer to the next node in a device path. + + Returns a pointer to the device path node that follows the device path node specified by Node. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @return a pointer to the device path node that follows the device path node specified by Node. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +NextDevicePathNode ( + IN CONST VOID *Node + ); + +/** + Determines if a device path node is an end node of a device path. + This includes nodes that are the end of a device path instance and nodes that + are the end of an entire device path. + + Determines if the device path node specified by Node is an end node of a device path. + This includes nodes that are the end of a device path instance and nodes that are the + end of an entire device path. If Node represents an end node of a device path, + then TRUE is returned. Otherwise, FALSE is returned. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @retval TRUE The device path node specified by Node is an end node of a device path. + @retval FALSE The device path node specified by Node is not an end node of a device path. + +**/ +BOOLEAN +EFIAPI +IsDevicePathEndType ( + IN CONST VOID *Node + ); + +/** + Determines if a device path node is an end node of an entire device path. + + Determines if a device path node specified by Node is an end node of an entire device path. + If Node represents the end of an entire device path, then TRUE is returned. + Otherwise, FALSE is returned. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @retval TRUE The device path node specified by Node is the end of an entire device path. + @retval FALSE The device path node specified by Node is not the end of an entire device path. + +**/ +BOOLEAN +EFIAPI +IsDevicePathEnd ( + IN CONST VOID *Node + ); + +/** + Determines if a device path node is an end node of a device path instance. + + Determines if a device path node specified by Node is an end node of a device path instance. + If Node represents the end of a device path instance, then TRUE is returned. + Otherwise, FALSE is returned. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + + @retval TRUE The device path node specified by Node is the end of a device path instance. + @retval FALSE The device path node specified by Node is not the end of a device path instance. + +**/ +BOOLEAN +EFIAPI +IsDevicePathEndInstance ( + IN CONST VOID *Node + ); + +/** + Sets the length, in bytes, of a device path node. + + Sets the length of the device path node specified by Node to the value specified + by NodeLength. NodeLength is returned. Node is not required to be aligned on + a 16-bit boundary, so it is recommended that a function such as WriteUnaligned16() + be used to set the contents of the Length field. + + If Node is NULL, then ASSERT(). + If NodeLength >= 0x10000, then ASSERT(). + If NodeLength < sizeof (EFI_DEVICE_PATH_PROTOCOL), then ASSERT(). + + @param Node A pointer to a device path node data structure. + @param Length The length, in bytes, of the device path node. + + @return Length + +**/ +UINT16 +EFIAPI +SetDevicePathNodeLength ( + IN OUT VOID *Node, + IN UINTN Length + ); + +/** + Fills in all the fields of a device path node that is the end of an entire device path. + + Fills in all the fields of a device path node specified by Node so Node represents + the end of an entire device path. The Type field of Node is set to + END_DEVICE_PATH_TYPE, the SubType field of Node is set to + END_ENTIRE_DEVICE_PATH_SUBTYPE, and the Length field of Node is set to + END_DEVICE_PATH_LENGTH. Node is not required to be aligned on a 16-bit boundary, + so it is recommended that a function such as WriteUnaligned16() be used to set + the contents of the Length field. + + If Node is NULL, then ASSERT(). + + @param Node A pointer to a device path node data structure. + +**/ +VOID +EFIAPI +SetDevicePathEndNode ( + OUT VOID *Node + ); + +/** + Returns the size of a device path in bytes. + + This function returns the size, in bytes, of the device path data structure + specified by DevicePath including the end of device path node. + If DevicePath is NULL or invalid, then 0 is returned. + + @param DevicePath A pointer to a device path data structure. + + @retval 0 If DevicePath is NULL or invalid. + @retval Others The size of a device path in bytes. + +**/ +UINTN +EFIAPI +GetDevicePathSize ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/** + Creates a new copy of an existing device path. + + This function allocates space for a new copy of the device path specified by DevicePath. If + DevicePath is NULL, then NULL is returned. If the memory is successfully allocated, then the + contents of DevicePath are copied to the newly allocated buffer, and a pointer to that buffer + is returned. Otherwise, NULL is returned. + The memory for the new device path is allocated from EFI boot services memory. + It is the responsibility of the caller to free the memory allocated. + + @param DevicePath A pointer to a device path data structure. + + @retval NULL DevicePath is NULL or invalid. + @retval Others A pointer to the duplicated device path. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +DuplicateDevicePath ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/** + Creates a new device path by appending a second device path to a first device path. + + This function creates a new device path by appending a copy of SecondDevicePath to a copy of + FirstDevicePath in a newly allocated buffer. Only the end-of-device-path device node from + SecondDevicePath is retained. The newly created device path is returned. + If FirstDevicePath is NULL, then it is ignored, and a duplicate of SecondDevicePath is returned. + If SecondDevicePath is NULL, then it is ignored, and a duplicate of FirstDevicePath is returned. + If both FirstDevicePath and SecondDevicePath are NULL, then a copy of an end-of-device-path is + returned. + If there is not enough memory for the newly allocated buffer, then NULL is returned. + The memory for the new device path is allocated from EFI boot services memory. It is the + responsibility of the caller to free the memory allocated. + + @param FirstDevicePath A pointer to a device path data structure. + @param SecondDevicePath A pointer to a device path data structure. + + @retval NULL If there is not enough memory for the newly allocated buffer. + @retval NULL If FirstDevicePath or SecondDevicePath is invalid. + @retval Others A pointer to the new device path if success. + Or a copy an end-of-device-path if both FirstDevicePath and SecondDevicePath are NULL. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +AppendDevicePath ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *FirstDevicePath, OPTIONAL + IN CONST EFI_DEVICE_PATH_PROTOCOL *SecondDevicePath OPTIONAL + ); + +/** + Creates a new path by appending the device node to the device path. + + This function creates a new device path by appending a copy of the device node specified by + DevicePathNode to a copy of the device path specified by DevicePath in an allocated buffer. + The end-of-device-path device node is moved after the end of the appended device node. + If DevicePathNode is NULL then a copy of DevicePath is returned. + If DevicePath is NULL then a copy of DevicePathNode, followed by an end-of-device path device + node is returned. + If both DevicePathNode and DevicePath are NULL then a copy of an end-of-device-path device node + is returned. + If there is not enough memory to allocate space for the new device path, then NULL is returned. + The memory is allocated from EFI boot services memory. It is the responsibility of the caller to + free the memory allocated. + + @param DevicePath A pointer to a device path data structure. + @param DevicePathNode A pointer to a single device path node. + + @retval NULL There is not enough memory for the new device path. + @retval Others A pointer to the new device path if success. + A copy of DevicePathNode followed by an end-of-device-path node + if both FirstDevicePath and SecondDevicePath are NULL. + A copy of an end-of-device-path node if both FirstDevicePath and SecondDevicePath are NULL. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +AppendDevicePathNode ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, OPTIONAL + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathNode OPTIONAL + ); + +/** + Creates a new device path by appending the specified device path instance to the specified device + path. + + This function creates a new device path by appending a copy of the device path instance specified + by DevicePathInstance to a copy of the device path secified by DevicePath in a allocated buffer. + The end-of-device-path device node is moved after the end of the appended device path instance + and a new end-of-device-path-instance node is inserted between. + If DevicePath is NULL, then a copy if DevicePathInstance is returned. + If DevicePathInstance is NULL, then NULL is returned. + If DevicePath or DevicePathInstance is invalid, then NULL is returned. + If there is not enough memory to allocate space for the new device path, then NULL is returned. + The memory is allocated from EFI boot services memory. It is the responsibility of the caller to + free the memory allocated. + + @param DevicePath A pointer to a device path data structure. + @param DevicePathInstance A pointer to a device path instance. + + @return A pointer to the new device path. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +AppendDevicePathInstance ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, OPTIONAL + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance OPTIONAL + ); + +/** + Creates a copy of the current device path instance and returns a pointer to the next device path + instance. + + This function creates a copy of the current device path instance. It also updates DevicePath to + point to the next device path instance in the device path (or NULL if no more) and updates Size + to hold the size of the device path instance copy. + If DevicePath is NULL, then NULL is returned. + If DevicePath points to a invalid device path, then NULL is returned. + If there is not enough memory to allocate space for the new device path, then NULL is returned. + The memory is allocated from EFI boot services memory. It is the responsibility of the caller to + free the memory allocated. + If Size is NULL, then ASSERT(). + + @param DevicePath On input, this holds the pointer to the current device path + instance. On output, this holds the pointer to the next device + path instance or NULL if there are no more device path + instances in the device path pointer to a device path data + structure. + @param Size On output, this holds the size of the device path instance, in + bytes or zero, if DevicePath is NULL. + + @return A pointer to the current device path instance. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +GetNextDevicePathInstance ( + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath, + OUT UINTN *Size + ); + +/** + Creates a device node. + + This function creates a new device node in a newly allocated buffer of size NodeLength and + initializes the device path node header with NodeType and NodeSubType. The new device path node + is returned. + If NodeLength is smaller than a device path header, then NULL is returned. + If there is not enough memory to allocate space for the new device path, then NULL is returned. + The memory is allocated from EFI boot services memory. It is the responsibility of the caller to + free the memory allocated. + + @param NodeType The device node type for the new device node. + @param NodeSubType The device node sub-type for the new device node. + @param NodeLength The length of the new device node. + + @return The new device path. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +CreateDeviceNode ( + IN UINT8 NodeType, + IN UINT8 NodeSubType, + IN UINT16 NodeLength + ); + +/** + Determines if a device path is single or multi-instance. + + This function returns TRUE if the device path specified by DevicePath is multi-instance. + Otherwise, FALSE is returned. + If DevicePath is NULL or invalid, then FALSE is returned. + + @param DevicePath A pointer to a device path data structure. + + @retval TRUE DevicePath is multi-instance. + @retval FALSE DevicePath is not multi-instance, or DevicePath is NULL or invalid. + +**/ +BOOLEAN +EFIAPI +IsDevicePathMultiInstance ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/** + Retrieves the device path protocol from a handle. + + This function returns the device path protocol from the handle specified by Handle. If Handle is + NULL or Handle does not contain a device path protocol, then NULL is returned. + + @param Handle The handle from which to retrieve the device path protocol. + + @return The device path protocol from the handle specified by Handle. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +DevicePathFromHandle ( + IN EFI_HANDLE Handle + ); + +/** + Allocates a device path for a file and appends it to an existing device path. + + If Device is a valid device handle that contains a device path protocol, then a device path for + the file specified by FileName is allocated and appended to the device path associated with the + handle Device. The allocated device path is returned. If Device is NULL or Device is a handle + that does not support the device path protocol, then a device path containing a single device + path node for the file specified by FileName is allocated and returned. + The memory for the new device path is allocated from EFI boot services memory. It is the responsibility + of the caller to free the memory allocated. + + If FileName is NULL, then ASSERT(). + If FileName is not aligned on a 16-bit boundary, then ASSERT(). + + @param Device A pointer to a device handle. This parameter is optional and + may be NULL. + @param FileName A pointer to a Null-terminated Unicode string. + + @return The allocated device path. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +FileDevicePath ( + IN EFI_HANDLE Device, OPTIONAL + IN CONST CHAR16 *FileName + ); + +/** + Converts a device path to its text representation. + + @param DevicePath A Pointer to the device to be converted. + @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation + of the display node is used, where applicable. If DisplayOnly + is FALSE, then the longer text representation of the display node + is used. + @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text + representation for a device node can be used, where applicable. + + @return A pointer to the allocated text representation of the device path or + NULL if DeviceNode is NULL or there was insufficient memory. + +**/ +CHAR16 * +EFIAPI +ConvertDevicePathToText ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN BOOLEAN DisplayOnly, + IN BOOLEAN AllowShortcuts + ); + +/** + Converts a device node to its string representation. + + @param DeviceNode A Pointer to the device node to be converted. + @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation + of the display node is used, where applicable. If DisplayOnly + is FALSE, then the longer text representation of the display node + is used. + @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text + representation for a device node can be used, where applicable. + + @return A pointer to the allocated text representation of the device node or NULL if DeviceNode + is NULL or there was insufficient memory. + +**/ +CHAR16 * +EFIAPI +ConvertDeviceNodeToText ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode, + IN BOOLEAN DisplayOnly, + IN BOOLEAN AllowShortcuts + ); + +/** + Convert text to the binary representation of a device node. + + @param TextDeviceNode TextDeviceNode points to the text representation of a device + node. Conversion starts with the first character and continues + until the first non-device node character. + + @return A pointer to the EFI device node or NULL if TextDeviceNode is NULL or there was + insufficient memory or text unsupported. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +ConvertTextToDeviceNode ( + IN CONST CHAR16 *TextDeviceNode + ); + +/** + Convert text to the binary representation of a device path. + + @param TextDevicePath TextDevicePath points to the text representation of a device + path. Conversion starts with the first character and continues + until the first non-device node character. + + @return A pointer to the allocated device path or NULL if TextDeviceNode is NULL or + there was insufficient memory. + +**/ +EFI_DEVICE_PATH_PROTOCOL * +EFIAPI +ConvertTextToDevicePath ( + IN CONST CHAR16 *TextDevicePath + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeCoreEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeCoreEntryPoint.h new file mode 100644 index 0000000000..0a18966e03 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeCoreEntryPoint.h @@ -0,0 +1,93 @@ +/** @file + Module entry point library for DXE core. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/// +/// Global variable that contains a pointer to the Hob List passed into the DXE Core entry point. +/// +extern VOID *gHobList; + + +/** + The entry point of PE/COFF Image for the DXE Core. + + This function is the entry point for the DXE Core. This function is required to call + ProcessModuleEntryPointList() and ProcessModuleEntryPointList() is never expected to return. + The DXE Core is responsible for calling ProcessLibraryConstructorList() as soon as the EFI + System Table and the image handle for the DXE Core itself have been established. + If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +_ModuleEntryPoint ( + IN VOID *HobStart + ); + + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + This function is required to call _ModuleEntryPoint() passing in HobStart. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +EfiMain ( + IN VOID *HobStart + ); + + +/** + Autogenerated function that calls the library constructors for all of the module's dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other + libraries. This function is autogenerated by build tools and those build tools are + responsible for collecting the set of library instances, determine which ones have + constructors, and calling the library constructors in the proper order based upon + each of the library instances own dependencies. + + @param ImageHandle The image handle of the DXE Core. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Autogenerated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module entry points and calling them in a specified order. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +ProcessModuleEntryPointList ( + IN VOID *HobStart + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesLib.h new file mode 100644 index 0000000000..54040e8289 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesLib.h @@ -0,0 +1,324 @@ +/** @file + MDE DXE Services Library provides functions that simplify the development of DXE Drivers. + These functions help access data from sections of FFS files or from file path. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+(C) Copyright 2015 Hewlett Packard Enterprise Development LP
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DXE_SERVICES_LIB_H__ +#define __DXE_SERVICES_LIB_H__ + +/** + Searches all the available firmware volumes and returns the first matching FFS section. + + This function searches all the firmware volumes for FFS files with FV file type specified by FileType + The order that the firmware volumes is searched is not deterministic. For each available FV a search + is made for FFS file of type FileType. If the FV contains more than one FFS file with the same FileType, + the FileInstance instance will be the matched FFS file. For each FFS file found a search + is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances + of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. + Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. + It is the caller's responsibility to use FreePool() to free the allocated buffer. + See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections + are retrieved from an FFS file based on SectionType and SectionInstance. + + If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, + the search will be retried with a section type of EFI_SECTION_PE32. + This function must be called with a TPL <= TPL_NOTIFY. + + If Buffer is NULL, then ASSERT(). + If Size is NULL, then ASSERT(). + + @param FileType Indicates the FV file type to search for within all available FVs. + @param FileInstance Indicates which file instance within all available FVs specified by FileType. + FileInstance starts from zero. + @param SectionType Indicates the FFS section type to search for within the FFS file + specified by FileType with FileInstance. + @param SectionInstance Indicates which section instance within the FFS file + specified by FileType with FileInstance to retrieve. SectionInstance starts from zero. + @param Buffer On output, a pointer to a callee allocated buffer containing the FFS file section that was found. + Is it the caller's responsibility to free this buffer using FreePool(). + @param Size On output, a pointer to the size, in bytes, of Buffer. + + @retval EFI_SUCCESS The specified FFS section was returned. + @retval EFI_NOT_FOUND The specified FFS section could not be found. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve the matching FFS section. + @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a device error. + @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the firmware volume that + contains the matching FFS section does not allow reads. +**/ +EFI_STATUS +EFIAPI +GetSectionFromAnyFvByFileType ( + IN EFI_FV_FILETYPE FileType, + IN UINTN FileInstance, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + OUT VOID **Buffer, + OUT UINTN *Size + ); + +/** + Searches all the available firmware volumes and returns the first matching FFS section. + + This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid. + The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search + is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances + of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. + Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. + It is the caller's responsibility to use FreePool() to free the allocated buffer. + See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections + are retrieved from an FFS file based on SectionType and SectionInstance. + + If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, + the search will be retried with a section type of EFI_SECTION_PE32. + This function must be called with a TPL <= TPL_NOTIFY. + + If NameGuid is NULL, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If Size is NULL, then ASSERT(). + + + @param NameGuid A pointer to to the FFS filename GUID to search for + within any of the firmware volumes in the platform. + @param SectionType Indicates the FFS section type to search for within + the FFS file specified by NameGuid. + @param SectionInstance Indicates which section instance within the FFS file + specified by NameGuid to retrieve. + @param Buffer On output, a pointer to a callee-allocated buffer + containing the FFS file section that was found. + It is the caller's responsibility to free this + buffer using FreePool(). + @param Size On output, a pointer to the size, in bytes, of Buffer. + + @retval EFI_SUCCESS The specified FFS section was returned. + @retval EFI_NOT_FOUND The specified FFS section could not be found. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve + the matching FFS section. + @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a + device error. + @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the + firmware volume that contains the matching FFS + section does not allow reads. +**/ +EFI_STATUS +EFIAPI +GetSectionFromAnyFv ( + IN CONST EFI_GUID *NameGuid, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + OUT VOID **Buffer, + OUT UINTN *Size + ); + +/** + Searches the firmware volume that the currently executing module was loaded from and returns the first matching FFS section. + + This function searches the firmware volume that the currently executing module was loaded + from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found, a search + is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance + instances of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. + Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. + It is the caller's responsibility to use FreePool() to free the allocated buffer. + See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections are retrieved from + an FFS file based on SectionType and SectionInstance. + + If the currently executing module was not loaded from a firmware volume, then EFI_NOT_FOUND is returned. + If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, + the search will be retried with a section type of EFI_SECTION_PE32. + + This function must be called with a TPL <= TPL_NOTIFY. + If NameGuid is NULL, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If Size is NULL, then ASSERT(). + + @param NameGuid A pointer to to the FFS filename GUID to search for + within the firmware volumes that the currently + executing module was loaded from. + @param SectionType Indicates the FFS section type to search for within + the FFS file specified by NameGuid. + @param SectionInstance Indicates which section instance within the FFS + file specified by NameGuid to retrieve. + @param Buffer On output, a pointer to a callee allocated buffer + containing the FFS file section that was found. + It is the caller's responsibility to free this buffer + using FreePool(). + @param Size On output, a pointer to the size, in bytes, of Buffer. + + + @retval EFI_SUCCESS The specified FFS section was returned. + @retval EFI_NOT_FOUND The specified FFS section could not be found. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve + the matching FFS section. + @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a + device error. + @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the + firmware volume that contains the matching FFS + section does not allow reads. +**/ +EFI_STATUS +EFIAPI +GetSectionFromFv ( + IN CONST EFI_GUID *NameGuid, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + OUT VOID **Buffer, + OUT UINTN *Size + ); + + +/** + Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section. + + This function searches the FFS file that the currently executing module was loaded from for a FFS sections of type SectionType. + If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType, + then the SectionInstance instance is returned in Buffer. Buffer is allocated using AllocatePool(), + and the size of the allocated buffer is returned in Size. It is the caller's responsibility + to use FreePool() to free the allocated buffer. See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for + details on how sections are retrieved from an FFS file based on SectionType and SectionInstance. + + If the currently executing module was not loaded from an FFS file, then EFI_NOT_FOUND is returned. + If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, + the search will be retried with a section type of EFI_SECTION_PE32. + This function must be called with a TPL <= TPL_NOTIFY. + + If Buffer is NULL, then ASSERT(). + If Size is NULL, then ASSERT(). + + + @param SectionType Indicates the FFS section type to search for within + the FFS file that the currently executing module + was loaded from. + @param SectionInstance Indicates which section instance to retrieve within + the FFS file that the currently executing module + was loaded from. + @param Buffer On output, a pointer to a callee allocated buffer + containing the FFS file section that was found. + It is the caller's responsibility to free this buffer + using FreePool(). + @param Size On output, a pointer to the size, in bytes, of Buffer. + + @retval EFI_SUCCESS The specified FFS section was returned. + @retval EFI_NOT_FOUND The specified FFS section could not be found. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve + the matching FFS section. + @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a + device error. + @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the + firmware volume that contains the matching FFS + section does not allow reads. + +**/ +EFI_STATUS +EFIAPI +GetSectionFromFfs ( + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + OUT VOID **Buffer, + OUT UINTN *Size + ); + + +/** + Get the image file buffer data and buffer size by its device path. + + Access the file either from a firmware volume, from a file system interface, + or from the load file interface. + + Allocate memory to store the found image. The caller is responsible to free memory. + + If FilePath is NULL, then NULL is returned. + If FileSize is NULL, then NULL is returned. + If AuthenticationStatus is NULL, then NULL is returned. + + @param[in] BootPolicy The policy for Open Image File.If TRUE, + indicates that the request originates from + the boot manager, and that the boot manager is + attempting to load FilePath as a boot selection. + If FALSE, then FilePath must match an exact + file to be loaded. + @param[in] FilePath Pointer to the device path of the file that is abstracted to + the file buffer. + @param[out] FileSize Pointer to the size of the abstracted file buffer. + @param[out] AuthenticationStatus Pointer to the authentication status. + + @retval NULL FilePath is NULL, or FileSize is NULL, or AuthenticationStatus is NULL, or the file can't be found. + @retval other The abstracted file buffer. The caller is responsible to free memory. +**/ +VOID * +EFIAPI +GetFileBufferByFilePath ( + IN BOOLEAN BootPolicy, + IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath, + OUT UINTN *FileSize, + OUT UINT32 *AuthenticationStatus + ); + +/** + Searches all the available firmware volumes and returns the file device path of first matching + FFS section. + + This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid. + The order that the firmware volumes is searched is not deterministic. For each FFS file found a search + is made for FFS sections of type SectionType. + + If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, + the search will be retried with a section type of EFI_SECTION_PE32. + This function must be called with a TPL <= TPL_NOTIFY. + + If NameGuid is NULL, then ASSERT(). + + @param NameGuid A pointer to to the FFS filename GUID to search for + within any of the firmware volumes in the platform. + @param SectionType Indicates the FFS section type to search for within + the FFS file specified by NameGuid. + @param SectionInstance Indicates which section instance within the FFS file + specified by NameGuid to retrieve. + @param FvFileDevicePath Device path for the target FFS + file. + + @retval EFI_SUCCESS The specified file device path of FFS section was returned. + @retval EFI_NOT_FOUND The specified file device path of FFS section could not be found. + @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a + device error. + @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the + firmware volume that contains the matching FFS section does not + allow reads. + @retval EFI_INVALID_PARAMETER FvFileDevicePath is NULL. + +**/ +EFI_STATUS +EFIAPI +GetFileDevicePathFromAnyFv ( + IN CONST EFI_GUID *NameGuid, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + OUT EFI_DEVICE_PATH_PROTOCOL **FvFileDevicePath + ); + +/** + Allocates one or more 4KB pages of a given type from a memory region that is + accessible to PEI. + + Allocates the number of 4KB pages of type 'MemoryType' and returns a + pointer to the allocated buffer. The buffer returned is aligned on a 4KB + boundary. If Pages is 0, then NULL is returned. If there is not enough + memory remaining to satisfy the request, then NULL is returned. + + @param[in] MemoryType The memory type to allocate + @param[in] Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocatePeiAccessiblePages ( + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesTableLib.h new file mode 100644 index 0000000000..d604f41747 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/DxeServicesTableLib.h @@ -0,0 +1,28 @@ +/** @file + Provides a service to retrieve a pointer to the DXE Services Table. + Only available to DXE module types. + + This library does not contain any functions or macros. It simply exports a global + pointer to the DXE Services Table as defined in the Platform Initialization Driver + Execution Environment Core Interface Specification. The library constructor must + initialize this global pointer to the DX Services Table, so it is available at the + module's entry point. Since there is overhead in looking up the pointer to the DXE + Services Table, only those modules that actually require access to the DXE Services + Table should use this library. This will typically be DXE Drivers that require GCD + or Dispatcher services. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DXE_SERVICES_TABLE_LIB_H__ +#define __DXE_SERVICES_TABLE_LIB_H__ + +/// +/// Cache copy of the DXE Services Table +/// +extern EFI_DXE_SERVICES *gDS; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ExtractGuidedSectionLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ExtractGuidedSectionLib.h new file mode 100644 index 0000000000..95c7670ada --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ExtractGuidedSectionLib.h @@ -0,0 +1,278 @@ +/** @file + This library provides common functions to process the different guided section data. + + This library provides functions to process GUIDed sections of FFS files. Handlers may + be registered to decode GUIDed sections of FFS files. Services are provided to determine + the set of supported section GUIDs, collection information about a specific GUIDed section, + and decode a specific GUIDed section. + + A library instance that produces this library class may be used to produce a + EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI or a EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL + providing a simple method to extend the number of GUIDed sections types a platform supports. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __EXTRACT_GUIDED_SECTION_H__ +#define __EXTRACT_GUIDED_SECTION_H__ + +/** + Examines a GUIDed section and returns the size of the decoded buffer and the + size of an optional scratch buffer required to actually decode the data in a GUIDed section. + + Examines a GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, + then RETURN_UNSUPPORTED is returned. + If the required information can not be retrieved from InputSection, + then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, + then the size required to hold the decoded buffer is returned in OututBufferSize, + the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field + from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute. + + If InputSection is NULL, then ASSERT(). + If OutputBufferSize is NULL, then ASSERT(). + If ScratchBufferSize is NULL, then ASSERT(). + If SectionAttribute is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required + if the buffer specified by InputSection were decoded. + @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space + if the buffer specified by InputSection were decoded. + @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes + field of EFI_GUID_DEFINED_SECTION in the PI Specification. + + @retval RETURN_SUCCESS The information about InputSection was returned. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection. + +**/ +typedef +RETURN_STATUS +(EFIAPI *EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER)( + IN CONST VOID *InputSection, + OUT UINT32 *OutputBufferSize, + OUT UINT32 *ScratchBufferSize, + OUT UINT16 *SectionAttribute + ); + +/** + Decodes a GUIDed section into a caller allocated output buffer. + + Decodes the GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned. + If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, then InputSection + is decoded into the buffer specified by OutputBuffer and the authentication status of this + decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the + data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise, + the decoded data will be placed in caller allocated buffer specified by OutputBuffer. + + If InputSection is NULL, then ASSERT(). + If OutputBuffer is NULL, then ASSERT(). + If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT(). + If AuthenticationStatus is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation. + @param[out] ScratchBuffer A caller allocated buffer that may be required by this function + as a scratch buffer to perform the decode operation. + @param[out] AuthenticationStatus + A pointer to the authentication status of the decoded output buffer. + See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI + section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must + never be set by this handler. + + @retval RETURN_SUCCESS The buffer specified by InputSection was decoded. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded. + +**/ +typedef +RETURN_STATUS +(EFIAPI *EXTRACT_GUIDED_SECTION_DECODE_HANDLER)( + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + IN VOID *ScratchBuffer, OPTIONAL + OUT UINT32 *AuthenticationStatus + ); + +/** + Registers handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and EXTRACT_GUIDED_SECTION_DECODE_HANDLER + for a specific GUID section type. + + Registers the handlers specified by GetInfoHandler and DecodeHandler with the GUID specified by SectionGuid. + If the GUID value specified by SectionGuid has already been registered, then return RETURN_ALREADY_STARTED. + If there are not enough resources available to register the handlers then RETURN_OUT_OF_RESOURCES is returned. + + If SectionGuid is NULL, then ASSERT(). + If GetInfoHandler is NULL, then ASSERT(). + If DecodeHandler is NULL, then ASSERT(). + + @param[in] SectionGuid A pointer to the GUID associated with the the handlers + of the GUIDed section type being registered. + @param[in] GetInfoHandler Pointer to a function that examines a GUIDed section and returns the + size of the decoded buffer and the size of an optional scratch buffer + required to actually decode the data in a GUIDed section. + @param[in] DecodeHandler Pointer to a function that decodes a GUIDed section into a caller + allocated output buffer. + + @retval RETURN_SUCCESS The handlers were registered. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to register the handlers. + +**/ +RETURN_STATUS +EFIAPI +ExtractGuidedSectionRegisterHandlers ( + IN CONST GUID *SectionGuid, + IN EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER GetInfoHandler, + IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler + ); + +/** + Retrieve the list GUIDs that have been registered through ExtractGuidedSectionRegisterHandlers(). + + Sets ExtractHandlerGuidTable so it points at a callee allocated array of registered GUIDs. + The total number of GUIDs in the array are returned. Since the array of GUIDs is callee allocated + and caller must treat this array of GUIDs as read-only data. + If ExtractHandlerGuidTable is NULL, then ASSERT(). + + @param[out] ExtractHandlerGuidTable A pointer to the array of GUIDs that have been registered through + ExtractGuidedSectionRegisterHandlers(). + + @return the number of the supported extract guided Handler. + +**/ +UINTN +EFIAPI +ExtractGuidedSectionGetGuidList ( + OUT GUID **ExtractHandlerGuidTable + ); + +/** + Retrieves a GUID from a GUIDed section and uses that GUID to select an associated handler of type + EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers(). + The selected handler is used to retrieve and return the size of the decoded buffer and the size of an + optional scratch buffer required to actually decode the data in a GUIDed section. + + Examines a GUIDed section specified by InputSection. + If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(), + then RETURN_UNSUPPORTED is returned. + If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler + of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers() + is used to retrieve the OututBufferSize, ScratchSize, and Attributes values. The return status from the handler of + type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER is returned. + + If InputSection is NULL, then ASSERT(). + If OutputBufferSize is NULL, then ASSERT(). + If ScratchBufferSize is NULL, then ASSERT(). + If SectionAttribute is NULL, then ASSERT(). + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required if the buffer + specified by InputSection were decoded. + @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space if the buffer specified by + InputSection were decoded. + @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes field of + EFI_GUID_DEFINED_SECTION in the PI Specification. + + @retval RETURN_SUCCESS Get the required information successfully. + @retval RETURN_UNSUPPORTED The GUID from the section specified by InputSection does not match any of + the GUIDs registered with ExtractGuidedSectionRegisterHandlers(). + @retval Others The return status from the handler associated with the GUID retrieved from + the section specified by InputSection. + +**/ +RETURN_STATUS +EFIAPI +ExtractGuidedSectionGetInfo ( + IN CONST VOID *InputSection, + OUT UINT32 *OutputBufferSize, + OUT UINT32 *ScratchBufferSize, + OUT UINT16 *SectionAttribute + ); + +/** + Retrieves the GUID from a GUIDed section and uses that GUID to select an associated handler of type + EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers(). + The selected handler is used to decode the data in a GUIDed section and return the result in a caller + allocated output buffer. + + Decodes the GUIDed section specified by InputSection. + If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(), + then RETURN_UNSUPPORTED is returned. + If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler + of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers() + is used to decode InputSection into the buffer specified by OutputBuffer and the authentication status of this + decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the data in InputSection, + then OutputBuffer is set to point at the data in InputSection. Otherwise, the decoded data will be placed in caller + allocated buffer specified by OutputBuffer. This function is responsible for computing the EFI_AUTH_STATUS_PLATFORM_OVERRIDE + bit of in AuthenticationStatus. The return status from the handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER is returned. + + If InputSection is NULL, then ASSERT(). + If OutputBuffer is NULL, then ASSERT(). + If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT(). + If AuthenticationStatus is NULL, then ASSERT(). + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation. + @param[in] ScratchBuffer A caller allocated buffer that may be required by this function as a scratch buffer to perform the decode operation. + @param[out] AuthenticationStatus + A pointer to the authentication status of the decoded output buffer. See the definition + of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI section of the PI + Specification. + + @retval RETURN_SUCCESS The buffer specified by InputSection was decoded. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded. + +**/ +RETURN_STATUS +EFIAPI +ExtractGuidedSectionDecode ( + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + IN VOID *ScratchBuffer, OPTIONAL + OUT UINT32 *AuthenticationStatus + ); + +/** + Retrieves handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and + EXTRACT_GUIDED_SECTION_DECODE_HANDLER for a specific GUID section type. + + Retrieves the handlers associated with SectionGuid and returns them in + GetInfoHandler and DecodeHandler. + + If the GUID value specified by SectionGuid has not been registered, then + return RETURN_NOT_FOUND. + + If SectionGuid is NULL, then ASSERT(). + + @param[in] SectionGuid A pointer to the GUID associated with the handlersof the GUIDed + section type being retrieved. + @param[out] GetInfoHandler Pointer to a function that examines a GUIDed section and returns + the size of the decoded buffer and the size of an optional scratch + buffer required to actually decode the data in a GUIDed section. + This is an optional parameter that may be NULL. If it is NULL, then + the previously registered handler is not returned. + @param[out] DecodeHandler Pointer to a function that decodes a GUIDed section into a caller + allocated output buffer. This is an optional parameter that may be NULL. + If it is NULL, then the previously registered handler is not returned. + + @retval RETURN_SUCCESS The handlers were retrieved. + @retval RETURN_NOT_FOUND No handlers have been registered with the specified GUID. + +**/ +RETURN_STATUS +EFIAPI +ExtractGuidedSectionGetHandlers ( + IN CONST GUID *SectionGuid, + OUT EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *GetInfoHandler, OPTIONAL + OUT EXTRACT_GUIDED_SECTION_DECODE_HANDLER *DecodeHandler OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/FileHandleLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/FileHandleLib.h new file mode 100644 index 0000000000..c473c668ba --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/FileHandleLib.h @@ -0,0 +1,501 @@ +/** @file + Provides interface to EFI_FILE_HANDLE functionality. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FILE_HANDLE_LIBRARY_HEADER_ +#define _FILE_HANDLE_LIBRARY_HEADER_ + +#include +#include + +/// The tag for use in identifying UNICODE files. +/// If the file is UNICODE, the first 16 bits of the file will equal this value. +extern CONST UINT16 gUnicodeFileTag; + +/** + This function retrieves information about the file for the handle + specified and stores it in the allocated pool memory. + + This function allocates a buffer to store the file's information. It is the + caller's responsibility to free the buffer. + + @param[in] FileHandle The file handle of the file for which information is + being requested. + + @retval NULL Information could not be retrieved. + @retval !NULL The information about the file. +**/ +EFI_FILE_INFO* +EFIAPI +FileHandleGetInfo ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + This function sets the information about the file for the opened handle + specified. + + @param[in] FileHandle The file handle of the file for which information + is being set. + + @param[in] FileInfo The information to set. + + @retval EFI_SUCCESS The information was set. + @retval EFI_INVALID_PARAMETER A parameter was out of range or invalid. + @retval EFI_UNSUPPORTED The FileHandle does not support FileInfo. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write protected. + @retval EFI_ACCESS_DENIED The file was opened read only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +EFI_STATUS +EFIAPI +FileHandleSetInfo ( + IN EFI_FILE_HANDLE FileHandle, + IN CONST EFI_FILE_INFO *FileInfo + ); + +/** + This function reads information from an opened file. + + If FileHandle is not a directory, the function reads the requested number of + bytes from the file at the file's current position and returns them in Buffer. + If the read goes beyond the end of the file, the read length is truncated to the + end of the file. The file's current position is increased by the number of bytes + returned. If FileHandle is a directory, the function reads the directory entry + at the file's current position and returns the entry in Buffer. If the Buffer + is not large enough to hold the current directory entry, then + EFI_BUFFER_TOO_SMALL is returned and the current file position is not updated. + BufferSize is set to be the size of the buffer needed to read the entry. On + success, the current position is updated to the next directory entry. If there + are no more directory entries, the read returns a zero-length buffer. + EFI_FILE_INFO is the structure returned as the directory entry. + + @param[in] FileHandle The opened file handle. + @param[in, out] BufferSize On input, the size of buffer in bytes. On return, + the number of bytes written. + @param[out] Buffer The buffer to put read data into. + + @retval EFI_SUCCESS Data was read. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TO_SMALL Buffer is too small. ReadSize contains required + size. + +**/ +EFI_STATUS +EFIAPI +FileHandleRead( + IN EFI_FILE_HANDLE FileHandle, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Write data to a file. + + This function writes the specified number of bytes to the file at the current + file position. The current file position is advanced the actual number of bytes + written, which is returned in BufferSize. Partial writes only occur when there + has been a data error during the write attempt (such as "volume space full"). + The file is automatically grown to hold the data if required. Direct writes to + opened directories are not supported. + + @param[in] FileHandle The opened file for writing. + @param[in, out] BufferSize On input, the number of bytes in Buffer. On output, + the number of bytes written. + @param[in] Buffer The buffer containing data to write is stored. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to an open directory are not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write-protected. + @retval EFI_ACCESS_DENIED The file was opened for read only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +EFI_STATUS +EFIAPI +FileHandleWrite( + IN EFI_FILE_HANDLE FileHandle, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Close an open file handle. + + This function closes a specified file handle. All "dirty" cached file data is + flushed to the device, and the file is closed. In all cases the handle is + closed. + + @param[in] FileHandle The file handle to close. + + @retval EFI_SUCCESS The file handle was closed successfully. +**/ +EFI_STATUS +EFIAPI +FileHandleClose ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Delete a file and close the handle. + + This function closes and deletes a file. In all cases the file handle is closed. + If the file cannot be deleted, the warning code EFI_WARN_DELETE_FAILURE is + returned, but the handle is still closed. + + @param[in] FileHandle The file handle to delete. + + @retval EFI_SUCCESS The file was closed successfully. + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not + deleted. + @retval INVALID_PARAMETER One of the parameters has an invalid value. +**/ +EFI_STATUS +EFIAPI +FileHandleDelete ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Set the current position in a file. + + This function sets the current file position for the handle to the position + supplied. With the exception of moving to position 0xFFFFFFFFFFFFFFFF, only + absolute positioning is supported, and moving past the end of the file is + allowed (a subsequent write would grow the file). Moving to position + 0xFFFFFFFFFFFFFFFF causes the current position to be set to the end of the file. + If FileHandle is a directory, the only position that may be set is zero. This + has the effect of starting the read process of the directory entries over again. + + @param[in] FileHandle The file handle on which the position is being set. + @param[in] Position The byte position from the beginning of the file. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED The request for non-zero is not valid on + directories. + @retval INVALID_PARAMETER One of the parameters has an invalid value. +**/ +EFI_STATUS +EFIAPI +FileHandleSetPosition ( + IN EFI_FILE_HANDLE FileHandle, + IN UINT64 Position + ); + +/** + Gets a file's current position. + + This function retrieves the current file position for the file handle. For + directories, the current file position has no meaning outside of the file + system driver. As such, the operation is not supported. An error is returned + if FileHandle is a directory. + + @param[in] FileHandle The open file handle on which to get the position. + @param[out] Position The byte position from beginning of file. + + @retval EFI_SUCCESS The operation completed successfully. + @retval INVALID_PARAMETER One of the parameters has an invalid value. + @retval EFI_UNSUPPORTED The request is not valid on directories. +**/ +EFI_STATUS +EFIAPI +FileHandleGetPosition ( + IN EFI_FILE_HANDLE FileHandle, + OUT UINT64 *Position + ); +/** + Flushes data on a file. + + This function flushes all modified data associated with a file to a device. + + @param[in] FileHandle The file handle on which to flush data. + + @retval EFI_SUCCESS The data was flushed. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write protected. + @retval EFI_ACCESS_DENIED The file was opened for read only. +**/ +EFI_STATUS +EFIAPI +FileHandleFlush ( + IN EFI_FILE_HANDLE FileHandle + ); + +/** + Function to determine if a given handle is a directory handle. + + Open the file information on the DirHandle and verify that the Attribute + includes EFI_FILE_DIRECTORY bit set. + + @param[in] DirHandle Handle to open file. + + @retval EFI_SUCCESS DirHandle is a directory. + @retval EFI_INVALID_PARAMETER DirHandle is NULL. + The file information returns from FileHandleGetInfo is NULL. + @retval EFI_NOT_FOUND DirHandle is not a directory. +**/ +EFI_STATUS +EFIAPI +FileHandleIsDirectory ( + IN EFI_FILE_HANDLE DirHandle + ); + +/** Retrieve first entry from a directory. + + This function takes an open directory handle and gets information from the + first entry in the directory. A buffer is allocated to contain + the information and a pointer to the buffer is returned in *Buffer. The + caller can use FileHandleFindNextFile() to get subsequent directory entries. + + The buffer will be freed by FileHandleFindNextFile() when the last directory + entry is read. Otherwise, the caller must free the buffer, using FreePool, + when finished with it. + + @param[in] DirHandle The file handle of the directory to search. + @param[out] Buffer The pointer to pointer to buffer for file's information. + + @retval EFI_SUCCESS Found the first file. + @retval EFI_NOT_FOUND Cannot find the directory. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @return Others The status of FileHandleGetInfo, FileHandleSetPosition, + or FileHandleRead. +**/ +EFI_STATUS +EFIAPI +FileHandleFindFirstFile ( + IN EFI_FILE_HANDLE DirHandle, + OUT EFI_FILE_INFO **Buffer + ); + +/** Retrieve next entries from a directory. + + To use this function, the caller must first call the FileHandleFindFirstFile() + function to get the first directory entry. Subsequent directory entries are + retrieved by using the FileHandleFindNextFile() function. This function can + be called several times to get each entry from the directory. If the call of + FileHandleFindNextFile() retrieved the last directory entry, the next call of + this function will set *NoFile to TRUE and free the buffer. + + @param[in] DirHandle The file handle of the directory. + @param[out] Buffer The pointer to buffer for file's information. + @param[out] NoFile The pointer to boolean when last file is found. + + @retval EFI_SUCCESS Found the next file, or reached last file. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. +**/ +EFI_STATUS +EFIAPI +FileHandleFindNextFile( + IN EFI_FILE_HANDLE DirHandle, + OUT EFI_FILE_INFO *Buffer, + OUT BOOLEAN *NoFile + ); + +/** + Retrieve the size of a file. + + This function extracts the file size info from the FileHandle's EFI_FILE_INFO + data. + + @param[in] FileHandle The file handle from which size is retrieved. + @param[out] Size The pointer to size. + + @retval EFI_SUCCESS Operation was completed successfully. + @retval EFI_DEVICE_ERROR Cannot access the file. + @retval EFI_INVALID_PARAMETER FileHandle is NULL. + Size is NULL. +**/ +EFI_STATUS +EFIAPI +FileHandleGetSize ( + IN EFI_FILE_HANDLE FileHandle, + OUT UINT64 *Size + ); + +/** + Set the size of a file. + + This function changes the file size info from the FileHandle's EFI_FILE_INFO + data. + + @param[in] FileHandle The file handle whose size is to be changed. + @param[in] Size The new size. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Cannot access the file. + @retval EFI_INVALID_PARAMETER FileHandle is NULL. +**/ +EFI_STATUS +EFIAPI +FileHandleSetSize ( + IN EFI_FILE_HANDLE FileHandle, + IN UINT64 Size + ); + +/** + Function to get a full filename given a EFI_FILE_HANDLE somewhere lower on the + directory 'stack'. If the file is a directory, then append the '\' char at the + end of name string. If it's not a directory, then the last '\' should not be + added. + + @param[in] Handle Handle to the Directory or File to create path to. + @param[out] FullFileName Pointer to pointer to generated full file name. It + is the responsibility of the caller to free this memory + with a call to FreePool(). + @retval EFI_SUCCESS The operation was successful and FullFileName is valid. + @retval EFI_INVALID_PARAMETER Handle was NULL. + @retval EFI_INVALID_PARAMETER FullFileName was NULL. + @retval EFI_OUT_OF_MEMORY A memory allocation failed. +**/ +EFI_STATUS +EFIAPI +FileHandleGetFileName ( + IN CONST EFI_FILE_HANDLE Handle, + OUT CHAR16 **FullFileName + ); + +/** + Function to read a single line (up to but not including the \n) from a file. + + If the position upon start is 0, then the Ascii Boolean will be set. This should be + maintained and not changed for all operations with the same file. + The function will not return the \r and \n character in buffer. When an empty line is + read a CHAR_NULL character will be returned in buffer. + + @param[in] Handle FileHandle to read from. + @param[in, out] Buffer The pointer to buffer to read into. + @param[in, out] Size The pointer to number of bytes in Buffer. + @param[in] Truncate If the buffer is large enough, this has no effect. + If the buffer is is too small and Truncate is TRUE, + the line will be truncated. + If the buffer is is too small and Truncate is FALSE, + then no read will occur. + + @param[in, out] Ascii Boolean value for indicating whether the file is + Ascii (TRUE) or UCS2 (FALSE). + + @retval EFI_SUCCESS The operation was successful. The line is stored in + Buffer. + @retval EFI_INVALID_PARAMETER Handle was NULL. + @retval EFI_INVALID_PARAMETER Size was NULL. + @retval EFI_BUFFER_TOO_SMALL Size was not large enough to store the line. + Size was updated to the minimum space required. + @sa FileHandleRead +**/ +EFI_STATUS +EFIAPI +FileHandleReadLine( + IN EFI_FILE_HANDLE Handle, + IN OUT CHAR16 *Buffer, + IN OUT UINTN *Size, + IN BOOLEAN Truncate, + IN OUT BOOLEAN *Ascii + ); + +/** + Function to read a single line from a file. The \n is not included in the returned + buffer. The returned buffer must be callee freed. + + If the position upon start is 0, then the Ascii Boolean will be set. This should be + maintained and not changed for all operations with the same file. + + @param[in] Handle FileHandle to read from. + @param[in, out] Ascii Boolean value for indicating whether the file is + Ascii (TRUE) or UCS2 (FALSE). + + @return The line of text from the file. + + @sa FileHandleReadLine +**/ +CHAR16* +EFIAPI +FileHandleReturnLine( + IN EFI_FILE_HANDLE Handle, + IN OUT BOOLEAN *Ascii + ); + +/** + Function to write a line of text to a file. + + If the file is a Unicode file (with UNICODE file tag) then write the unicode + text. + If the file is an ASCII file then write the ASCII text. + If the size of file is zero (without file tag at the beginning) then write + ASCII text as default. + + @param[in] Handle FileHandle to write to. + @param[in] Buffer Buffer to write, if NULL the function will + take no action and return EFI_SUCCESS. + + @retval EFI_SUCCESS The data was written. + Buffer is NULL. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_OUT_OF_RESOURCES Unable to allocate temporary space for ASCII + string due to out of resources. + + @sa FileHandleWrite +**/ +EFI_STATUS +EFIAPI +FileHandleWriteLine( + IN EFI_FILE_HANDLE Handle, + IN CHAR16 *Buffer + ); + +/** + Function to take a formatted argument and print it to a file. + + @param[in] Handle The file handle for the file to write to. + @param[in] Format The format argument (see printlib for the format specifier). + @param[in] ... The variable arguments for the format. + + @retval EFI_SUCCESS The operation was successful. + @retval other A return value from FileHandleWriteLine. + + @sa FileHandleWriteLine +**/ +EFI_STATUS +EFIAPI +FileHandlePrintLine( + IN EFI_FILE_HANDLE Handle, + IN CONST CHAR16 *Format, + ... + ); + +/** + Function to determine if a FILE_HANDLE is at the end of the file. + + This will NOT work on directories. + + If Handle is NULL, then ASSERT(). + + @param[in] Handle The file handle. + + @retval TRUE The position is at the end of the file. + @retval FALSE The position is not at the end of the file. +**/ +BOOLEAN +EFIAPI +FileHandleEof( + IN EFI_FILE_HANDLE Handle + ); + +#endif //_FILE_HANDLE_LIBRARY_HEADER_ + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HobLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HobLib.h new file mode 100644 index 0000000000..b1adb5276f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HobLib.h @@ -0,0 +1,560 @@ +/** @file + Provides services to create and parse HOBs. Only available for PEI + and DXE module types. + + The HOB Library supports the efficient creation and searching of HOBs + defined in the PI Specification. + A HOB is a Hand-Off Block, defined in the Framework architecture, that + allows the PEI phase to pass information to the DXE phase. HOBs are position + independent and can be relocated easily to different memory locations. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __HOB_LIB_H__ +#define __HOB_LIB_H__ + +/** + Returns the pointer to the HOB list. + + This function returns the pointer to first HOB in the list. + For PEI phase, the PEI service GetHobList() can be used to retrieve the pointer + to the HOB list. For the DXE phase, the HOB list pointer can be retrieved through + the EFI System Table by looking up theHOB list GUID in the System Configuration Table. + Since the System Configuration Table does not exist that the time the DXE Core is + launched, the DXE Core uses a global variable from the DXE Core Entry Point Library + to manage the pointer to the HOB list. + + If the pointer to the HOB list is NULL, then ASSERT(). + + @return The pointer to the HOB list. + +**/ +VOID * +EFIAPI +GetHobList ( + VOID + ); + +/** + Returns the next instance of a HOB type from the starting HOB. + + This function searches the first instance of a HOB type from the starting HOB pointer. + If there does not exist such HOB type from the starting HOB pointer, it will return NULL. + In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer + unconditionally: it returns HobStart back if HobStart itself meets the requirement; + caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. + + If HobStart is NULL, then ASSERT(). + + @param Type The HOB type to return. + @param HobStart The starting HOB pointer to search from. + + @return The next instance of a HOB type from the starting HOB. + +**/ +VOID * +EFIAPI +GetNextHob ( + IN UINT16 Type, + IN CONST VOID *HobStart + ); + +/** + Returns the first instance of a HOB type among the whole HOB list. + + This function searches the first instance of a HOB type among the whole HOB list. + If there does not exist such HOB type in the HOB list, it will return NULL. + + If the pointer to the HOB list is NULL, then ASSERT(). + + @param Type The HOB type to return. + + @return The next instance of a HOB type from the starting HOB. + +**/ +VOID * +EFIAPI +GetFirstHob ( + IN UINT16 Type + ); + +/** + Returns the next instance of the matched GUID HOB from the starting HOB. + + This function searches the first instance of a HOB from the starting HOB pointer. + Such HOB should satisfy two conditions: + its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. + If there does not exist such HOB from the starting HOB pointer, it will return NULL. + Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () + to extract the data section and its size info respectively. + In contrast with macro GET_NEXT_HOB(), this function does not skip the starting HOB pointer + unconditionally: it returns HobStart back if HobStart itself meets the requirement; + caller is required to use GET_NEXT_HOB() if it wishes to skip current HobStart. + + If Guid is NULL, then ASSERT(). + If HobStart is NULL, then ASSERT(). + + @param Guid The GUID to match with in the HOB list. + @param HobStart A pointer to a Guid. + + @return The next instance of the matched GUID HOB from the starting HOB. + +**/ +VOID * +EFIAPI +GetNextGuidHob ( + IN CONST EFI_GUID *Guid, + IN CONST VOID *HobStart + ); + +/** + Returns the first instance of the matched GUID HOB among the whole HOB list. + + This function searches the first instance of a HOB among the whole HOB list. + Such HOB should satisfy two conditions: + its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to the input Guid. + If there does not exist such HOB from the starting HOB pointer, it will return NULL. + Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_SIZE () + to extract the data section and its size info respectively. + + If the pointer to the HOB list is NULL, then ASSERT(). + If Guid is NULL, then ASSERT(). + + @param Guid The GUID to match with in the HOB list. + + @return The first instance of the matched GUID HOB among the whole HOB list. + +**/ +VOID * +EFIAPI +GetFirstGuidHob ( + IN CONST EFI_GUID *Guid + ); + +/** + Get the system boot mode from the HOB list. + + This function returns the system boot mode information from the + PHIT HOB in HOB list. + + If the pointer to the HOB list is NULL, then ASSERT(). + + @param VOID + + @return The Boot Mode. + +**/ +EFI_BOOT_MODE +EFIAPI +GetBootModeHob ( + VOID + ); + +/** + Builds a HOB for a loaded PE32 module. + + This function builds a HOB for a loaded PE32 module. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If ModuleName is NULL, then ASSERT(). + If there is no additional space for HOB creation, then ASSERT(). + + @param ModuleName The GUID File Name of the module. + @param MemoryAllocationModule The 64 bit physical address of the module. + @param ModuleLength The length of the module in bytes. + @param EntryPoint The 64 bit physical address of the module entry point. + +**/ +VOID +EFIAPI +BuildModuleHob ( + IN CONST EFI_GUID *ModuleName, + IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule, + IN UINT64 ModuleLength, + IN EFI_PHYSICAL_ADDRESS EntryPoint + ); + +/** + Builds a HOB that describes a chunk of system memory with Owner GUID. + + This function builds a HOB that describes a chunk of system memory. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param ResourceType The type of resource described by this HOB. + @param ResourceAttribute The resource attributes of the memory described by this HOB. + @param PhysicalStart The 64 bit physical address of memory described by this HOB. + @param NumberOfBytes The length of the memory described by this HOB in bytes. + @param OwnerGUID GUID for the owner of this resource. + +**/ +VOID +EFIAPI +BuildResourceDescriptorWithOwnerHob ( + IN EFI_RESOURCE_TYPE ResourceType, + IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute, + IN EFI_PHYSICAL_ADDRESS PhysicalStart, + IN UINT64 NumberOfBytes, + IN EFI_GUID *OwnerGUID + ); + +/** + Builds a HOB that describes a chunk of system memory. + + This function builds a HOB that describes a chunk of system memory. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param ResourceType The type of resource described by this HOB. + @param ResourceAttribute The resource attributes of the memory described by this HOB. + @param PhysicalStart The 64 bit physical address of memory described by this HOB. + @param NumberOfBytes The length of the memory described by this HOB in bytes. + +**/ +VOID +EFIAPI +BuildResourceDescriptorHob ( + IN EFI_RESOURCE_TYPE ResourceType, + IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute, + IN EFI_PHYSICAL_ADDRESS PhysicalStart, + IN UINT64 NumberOfBytes + ); + +/** + Builds a customized HOB tagged with a GUID for identification and returns + the start address of GUID HOB data. + + This function builds a customized HOB tagged with a GUID for identification + and returns the start address of GUID HOB data so that caller can fill the customized data. + The HOB Header and Name field is already stripped. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If Guid is NULL, then ASSERT(). + If there is no additional space for HOB creation, then ASSERT(). + If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT(). + HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8. + + @param Guid The GUID to tag the customized HOB. + @param DataLength The size of the data payload for the GUID HOB. + + @retval NULL The GUID HOB could not be allocated. + @retval others The start address of GUID HOB data. + +**/ +VOID * +EFIAPI +BuildGuidHob ( + IN CONST EFI_GUID *Guid, + IN UINTN DataLength + ); + +/** + Builds a customized HOB tagged with a GUID for identification, copies the input data to the HOB + data field, and returns the start address of the GUID HOB data. + + This function builds a customized HOB tagged with a GUID for identification and copies the input + data to the HOB data field and returns the start address of the GUID HOB data. It can only be + invoked during PEI phase; for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + The HOB Header and Name field is already stripped. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If Guid is NULL, then ASSERT(). + If Data is NULL and DataLength > 0, then ASSERT(). + If there is no additional space for HOB creation, then ASSERT(). + If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT(). + HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0xFFF8. + + @param Guid The GUID to tag the customized HOB. + @param Data The data to be copied into the data field of the GUID HOB. + @param DataLength The size of the data payload for the GUID HOB. + + @retval NULL The GUID HOB could not be allocated. + @retval others The start address of GUID HOB data. + +**/ +VOID * +EFIAPI +BuildGuidDataHob ( + IN CONST EFI_GUID *Guid, + IN VOID *Data, + IN UINTN DataLength + ); + +/** + Builds a Firmware Volume HOB. + + This function builds a Firmware Volume HOB. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + If the FvImage buffer is not at its required alignment, then ASSERT(). + + @param BaseAddress The base address of the Firmware Volume. + @param Length The size of the Firmware Volume in bytes. + +**/ +VOID +EFIAPI +BuildFvHob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Builds a EFI_HOB_TYPE_FV2 HOB. + + This function builds a EFI_HOB_TYPE_FV2 HOB. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + If the FvImage buffer is not at its required alignment, then ASSERT(). + + @param BaseAddress The base address of the Firmware Volume. + @param Length The size of the Firmware Volume in bytes. + @param FvName The name of the Firmware Volume. + @param FileName The name of the file. + +**/ +VOID +EFIAPI +BuildFv2Hob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN CONST EFI_GUID *FvName, + IN CONST EFI_GUID *FileName + ); + +/** + Builds a EFI_HOB_TYPE_FV3 HOB. + + This function builds a EFI_HOB_TYPE_FV3 HOB. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + If the FvImage buffer is not at its required alignment, then ASSERT(). + + @param BaseAddress The base address of the Firmware Volume. + @param Length The size of the Firmware Volume in bytes. + @param AuthenticationStatus The authentication status. + @param ExtractedFv TRUE if the FV was extracted as a file within + another firmware volume. FALSE otherwise. + @param FvName The name of the Firmware Volume. + Valid only if IsExtractedFv is TRUE. + @param FileName The name of the file. + Valid only if IsExtractedFv is TRUE. + +**/ +VOID +EFIAPI +BuildFv3Hob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT32 AuthenticationStatus, + IN BOOLEAN ExtractedFv, + IN CONST EFI_GUID *FvName, OPTIONAL + IN CONST EFI_GUID *FileName OPTIONAL + ); + +/** + Builds a Capsule Volume HOB. + + This function builds a Capsule Volume HOB. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If the platform does not support Capsule Volume HOBs, then ASSERT(). + If there is no additional space for HOB creation, then ASSERT(). + + @param BaseAddress The base address of the Capsule Volume. + @param Length The size of the Capsule Volume in bytes. + +**/ +VOID +EFIAPI +BuildCvHob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Builds a HOB for the CPU. + + This function builds a HOB for the CPU. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param SizeOfMemorySpace The maximum physical memory addressability of the processor. + @param SizeOfIoSpace The maximum physical I/O addressability of the processor. + +**/ +VOID +EFIAPI +BuildCpuHob ( + IN UINT8 SizeOfMemorySpace, + IN UINT8 SizeOfIoSpace + ); + +/** + Builds a HOB for the Stack. + + This function builds a HOB for the stack. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param BaseAddress The 64 bit physical address of the Stack. + @param Length The length of the stack in bytes. + +**/ +VOID +EFIAPI +BuildStackHob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Builds a HOB for the BSP store. + + This function builds a HOB for BSP store. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param BaseAddress The 64 bit physical address of the BSP. + @param Length The length of the BSP store in bytes. + @param MemoryType Type of memory allocated by this HOB. + +**/ +VOID +EFIAPI +BuildBspStoreHob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN EFI_MEMORY_TYPE MemoryType + ); + +/** + Builds a HOB for the memory allocation. + + This function builds a HOB for the memory allocation. + It can only be invoked during PEI phase; + for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase. + + If there is no additional space for HOB creation, then ASSERT(). + + @param BaseAddress The 64 bit physical address of the memory. + @param Length The length of the memory allocation in bytes. + @param MemoryType Type of memory allocated by this HOB. + +**/ +VOID +EFIAPI +BuildMemoryAllocationHob ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN EFI_MEMORY_TYPE MemoryType + ); + +/** + Returns the type of a HOB. + + This macro returns the HobType field from the HOB header for the + HOB specified by HobStart. + + @param HobStart A pointer to a HOB. + + @return HobType. + +**/ +#define GET_HOB_TYPE(HobStart) \ + ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobType) + +/** + Returns the length, in bytes, of a HOB. + + This macro returns the HobLength field from the HOB header for the + HOB specified by HobStart. + + @param HobStart A pointer to a HOB. + + @return HobLength. + +**/ +#define GET_HOB_LENGTH(HobStart) \ + ((*(EFI_HOB_GENERIC_HEADER **)&(HobStart))->HobLength) + +/** + Returns a pointer to the next HOB in the HOB list. + + This macro returns a pointer to HOB that follows the + HOB specified by HobStart in the HOB List. + + @param HobStart A pointer to a HOB. + + @return A pointer to the next HOB in the HOB list. + +**/ +#define GET_NEXT_HOB(HobStart) \ + (VOID *)(*(UINT8 **)&(HobStart) + GET_HOB_LENGTH (HobStart)) + +/** + Determines if a HOB is the last HOB in the HOB list. + + This macro determine if the HOB specified by HobStart is the + last HOB in the HOB list. If HobStart is last HOB in the HOB list, + then TRUE is returned. Otherwise, FALSE is returned. + + @param HobStart A pointer to a HOB. + + @retval TRUE The HOB specified by HobStart is the last HOB in the HOB list. + @retval FALSE The HOB specified by HobStart is not the last HOB in the HOB list. + +**/ +#define END_OF_HOB_LIST(HobStart) (GET_HOB_TYPE (HobStart) == (UINT16)EFI_HOB_TYPE_END_OF_HOB_LIST) + +/** + Returns a pointer to data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. + + This macro returns a pointer to the data buffer in a HOB specified by HobStart. + HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. + + @param GuidHob A pointer to a HOB. + + @return A pointer to the data buffer in a HOB. + +**/ +#define GET_GUID_HOB_DATA(HobStart) \ + (VOID *)(*(UINT8 **)&(HobStart) + sizeof (EFI_HOB_GUID_TYPE)) + +/** + Returns the size of the data buffer from a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. + + This macro returns the size, in bytes, of the data buffer in a HOB specified by HobStart. + HobStart is assumed to be a HOB of type EFI_HOB_TYPE_GUID_EXTENSION. + + @param GuidHob A pointer to a HOB. + + @return The size of the data buffer. +**/ +#define GET_GUID_HOB_DATA_SIZE(HobStart) \ + (UINT16)(GET_HOB_LENGTH (HobStart) - sizeof (EFI_HOB_GUID_TYPE)) + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HstiLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HstiLib.h new file mode 100644 index 0000000000..83d9bc46e3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/HstiLib.h @@ -0,0 +1,152 @@ +/** @file + Provides services to create, get and update HSTI table in AIP protocol. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __HSTI_LIB_H__ +#define __HSTI_LIB_H__ + +/** + Publish HSTI table in AIP protocol. + + One system should have only one PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE. + + If the Role is NOT PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE, + SecurityFeaturesRequired field will be ignored. + + @param Hsti HSTI data + @param HstiSize HSTI size + + @retval EFI_SUCCESS The HSTI data is published in AIP protocol. + @retval EFI_ALREADY_STARTED There is already HSTI table with Role and ImplementationID published in system. + @retval EFI_VOLUME_CORRUPTED The input HSTI data does not follow HSTI specification. + @retval EFI_OUT_OF_RESOURCES There is not enough system resource to publish HSTI data in AIP protocol. +**/ +EFI_STATUS +EFIAPI +HstiLibSetTable ( + IN VOID *Hsti, + IN UINTN HstiSize + ); + +/** + Search HSTI table in AIP protocol, and return the data. + This API will return the HSTI table with indicated Role and ImplementationID, + NULL ImplementationID means to find the first HSTI table with indicated Role. + + @param Role Role of HSTI data. + @param ImplementationID ImplementationID of HSTI data. + NULL means find the first one match Role. + @param Hsti HSTI data. This buffer is allocated by callee, and it + is the responsibility of the caller to free it after + using it. + @param HstiSize HSTI size + + @retval EFI_SUCCESS The HSTI data in AIP protocol is returned. + @retval EFI_NOT_FOUND There is not HSTI table with the Role and ImplementationID published in system. +**/ +EFI_STATUS +EFIAPI +HstiLibGetTable ( + IN UINT32 Role, + IN CHAR16 *ImplementationID OPTIONAL, + OUT VOID **Hsti, + OUT UINTN *HstiSize + ); + +/** + Set FeaturesVerified in published HSTI table. + This API will update the HSTI table with indicated Role and ImplementationID, + NULL ImplementationID means to find the first HSTI table with indicated Role. + + @param Role Role of HSTI data. + @param ImplementationID ImplementationID of HSTI data. + NULL means find the first one match Role. + @param ByteIndex Byte index of FeaturesVerified of HSTI data. + @param BitMask Bit mask of FeaturesVerified of HSTI data. + + @retval EFI_SUCCESS The FeaturesVerified of HSTI data updated in AIP protocol. + @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system. + @retval EFI_UNSUPPORTED The ByteIndex is invalid. +**/ +EFI_STATUS +EFIAPI +HstiLibSetFeaturesVerified ( + IN UINT32 Role, + IN CHAR16 *ImplementationID, OPTIONAL + IN UINT32 ByteIndex, + IN UINT8 BitMask + ); + +/** + Clear FeaturesVerified in published HSTI table. + This API will update the HSTI table with indicated Role and ImplementationID, + NULL ImplementationID means to find the first HSTI table with indicated Role. + + @param Role Role of HSTI data. + @param ImplementationID ImplementationID of HSTI data. + NULL means find the first one match Role. + @param ByteIndex Byte index of FeaturesVerified of HSTI data. + @param BitMask Bit mask of FeaturesVerified of HSTI data. + + @retval EFI_SUCCESS The FeaturesVerified of HSTI data updated in AIP protocol. + @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system. + @retval EFI_UNSUPPORTED The ByteIndex is invalid. +**/ +EFI_STATUS +EFIAPI +HstiLibClearFeaturesVerified ( + IN UINT32 Role, + IN CHAR16 *ImplementationID, OPTIONAL + IN UINT32 ByteIndex, + IN UINT8 BitMask + ); + +/** + Append ErrorString in published HSTI table. + This API will update the HSTI table with indicated Role and ImplementationID, + NULL ImplementationID means to find the first HSTI table with indicated Role. + + @param Role Role of HSTI data. + @param ImplementationID ImplementationID of HSTI data. + NULL means find the first one match Role. + @param ErrorString ErrorString of HSTI data. + + @retval EFI_SUCCESS The ErrorString of HSTI data is updated in AIP protocol. + @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system. + @retval EFI_OUT_OF_RESOURCES There is not enough system resource to update ErrorString. +**/ +EFI_STATUS +EFIAPI +HstiLibAppendErrorString ( + IN UINT32 Role, + IN CHAR16 *ImplementationID, OPTIONAL + IN CHAR16 *ErrorString + ); + +/** + Set a new ErrorString in published HSTI table. + This API will update the HSTI table with indicated Role and ImplementationID, + NULL ImplementationID means to find the first HSTI table with indicated Role. + + @param Role Role of HSTI data. + @param ImplementationID ImplementationID of HSTI data. + NULL means find the first one match Role. + @param ErrorString ErrorString of HSTI data. + + @retval EFI_SUCCESS The ErrorString of HSTI data is updated in AIP protocol. + @retval EFI_NOT_STARTED There is not HSTI table with the Role and ImplementationID published in system. + @retval EFI_OUT_OF_RESOURCES There is not enough system resource to update ErrorString. +**/ +EFI_STATUS +EFIAPI +HstiLibSetErrorString ( + IN UINT32 Role, + IN CHAR16 *ImplementationID, OPTIONAL + IN CHAR16 *ErrorString + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/IoLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/IoLib.h new file mode 100644 index 0000000000..d0ffe98ecb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/IoLib.h @@ -0,0 +1,2809 @@ +/** @file + Provide services to access I/O Ports and MMIO registers. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __IO_LIB_H__ +#define __IO_LIB_H__ + +/** + Macro that converts PCI Segment and I/O Port to an address that can be + passed to the I/O Library functions. + + Computes an address that is compatible with the I/O Library functions. + The unused upper bits of Segment, and Port are stripped prior to the + generation of the address. + + @param Segment PCI Segment number. Range 0..65535. + @param Port I/O Port number. Range 0..65535. + + @return An address that the I/o Library functions need. + +**/ + +#define IO_LIB_ADDRESS(Segment,Port) \ + ( ((Port) & 0xffff) | (((Segment) & 0xffff) << 16) ) + +/** + Reads an 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +IoRead8 ( + IN UINTN Port + ); + +/** + Writes an 8-bit I/O port. + + Writes the 8-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +IoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ); + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads an 8-bit I/O port, performs a bitwise OR, and writes the + result back to the 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 8-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoOr8 ( + IN UINTN Port, + IN UINT8 OrData + ); + +/** + Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back + to the 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 8-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoAnd8 ( + IN UINTN Port, + IN UINT8 AndData + ); + +/** + Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 8-bit I/O port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoAndThenOr8 ( + IN UINTN Port, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of an I/O register. + + Reads the bit field in an 8-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Port The I/O port to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value read. + +**/ +UINT8 +EFIAPI +IoBitFieldRead8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoBitFieldWrite8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the + result back to the bit field in the 8-bit port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 8-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoBitFieldOr8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the + result back to the bit field in the 8-bit port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 8-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoBitFieldAnd8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 8-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +IoBitFieldAndThenOr8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +IoRead16 ( + IN UINTN Port + ); + +/** + Writes a 16-bit I/O port. + + Writes the 16-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +IoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ); + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 16-bit I/O port, performs a bitwise OR, and writes the + result back to the 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 16-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoOr16 ( + IN UINTN Port, + IN UINT16 OrData + ); + +/** + Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back + to the 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 16-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoAnd16 ( + IN UINTN Port, + IN UINT16 AndData + ); + +/** + Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 16-bit I/O port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoAndThenOr16 ( + IN UINTN Port, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of an I/O register. + + Reads the bit field in a 16-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Port The I/O port to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value read. + +**/ +UINT16 +EFIAPI +IoBitFieldRead16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoBitFieldWrite16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the + result back to the bit field in the 16-bit port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 16-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoBitFieldOr16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the + result back to the bit field in the 16-bit port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 16-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoBitFieldAnd16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 16-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +IoBitFieldAndThenOr16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +IoRead32 ( + IN UINTN Port + ); + +/** + Writes a 32-bit I/O port. + + Writes the 32-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +IoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ); + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 32-bit I/O port, performs a bitwise OR, and writes the + result back to the 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 32-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoOr32 ( + IN UINTN Port, + IN UINT32 OrData + ); + +/** + Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back + to the 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 32-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoAnd32 ( + IN UINTN Port, + IN UINT32 AndData + ); + +/** + Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 32-bit I/O port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoAndThenOr32 ( + IN UINTN Port, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of an I/O register. + + Reads the bit field in a 32-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Port The I/O port to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value read. + +**/ +UINT32 +EFIAPI +IoBitFieldRead32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoBitFieldWrite32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the + result back to the bit field in the 32-bit port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 32-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoBitFieldOr32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the + result back to the bit field in the 32-bit port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 32-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoBitFieldAnd32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 32-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +IoBitFieldAndThenOr32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +IoRead64 ( + IN UINTN Port + ); + +/** + Writes a 64-bit I/O port. + + Writes the 64-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT64 +EFIAPI +IoWrite64 ( + IN UINTN Port, + IN UINT64 Value + ); + +/** + Reads a 64-bit I/O port, performs a bitwise OR, and writes the + result back to the 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoOr64 ( + IN UINTN Port, + IN UINT64 OrData + ); + +/** + Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back + to the 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 64-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoAnd64 ( + IN UINTN Port, + IN UINT64 AndData + ); + +/** + Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 64-bit I/O port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 64-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + + @param Port The I/O port to write. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoAndThenOr64 ( + IN UINTN Port, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads a bit field of an I/O register. + + Reads the bit field in a 64-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Port The I/O port to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The value read. + +**/ +UINT64 +EFIAPI +IoBitFieldRead64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoBitFieldWrite64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the + result back to the bit field in the 64-bit port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoBitFieldOr64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the + result back to the bit field in the 64-bit port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 64-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoBitFieldAnd64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 64-bit port. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 64-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If Port is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Port The I/O port to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with the read value from the I/O port. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +IoBitFieldAndThenOr64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads an 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +MmioRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit MMIO register. + + Writes the 8-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +MmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise OR, and writes the + result back to the 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 8-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result + back to the 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 8-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 8-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a MMIO register. + + Reads the bit field in an 8-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address MMIO register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value read. + +**/ +UINT8 +EFIAPI +MmioBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 8-bit register is returned. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 8-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 8-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, and writes the result back to the bit field in the + 8-bit MMIO register. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 8-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +MmioBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address. The 16-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +MmioRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit MMIO register. + + Writes the 16-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +MmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise OR, and writes the + result back to the 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 16-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result + back to the 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 16-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 16-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a MMIO register. + + Reads the bit field in a 16-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address MMIO register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value read. + +**/ +UINT16 +EFIAPI +MmioBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 16-bit register is returned. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 16-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 16-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, and writes the result back to the bit field in the + 16-bit MMIO register. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 16-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +MmioBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address. The 32-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +MmioRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit MMIO register. + + Writes the 32-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +MmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise OR, and writes the + result back to the 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 32-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result + back to the 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 32-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 32-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a MMIO register. + + Reads the bit field in a 32-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address MMIO register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value read. + +**/ +UINT32 +EFIAPI +MmioBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 32-bit register is returned. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 32-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 32-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, and writes the result back to the bit field in the + 32-bit MMIO register. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 32-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +MmioBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address. The 64-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +MmioRead64 ( + IN UINTN Address + ); + +/** + Writes a 64-bit MMIO register. + + Writes the 64-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise OR, and writes the + result back to the 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 64-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result + back to the 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 64-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise + OR, and writes the result back to the 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 64-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + + @param Address The MMIO register to write. + @param AndData The value to AND with the read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads a bit field of a MMIO register. + + Reads the bit field in a 64-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address MMIO register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The value read. + +**/ +UINT64 +EFIAPI +MmioBitFieldRead64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 64-bit register is returned. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioBitFieldWrite64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and + writes the result back to the bit field in the 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise + OR between the read result and the value specified by OrData, and + writes the result to the 64-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param OrData The value to OR with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioBitFieldOr64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 64-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioBitFieldAnd64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, and writes the result back to the bit field in the + 64-bit MMIO register. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 64-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If Address is not aligned on a 64-bit boundary, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address MMIO register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param AndData The value to AND with read value from the MMIO register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +MmioBitFieldAndThenOr64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Copy data from MMIO region to system memory by using 8-bit access. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 8-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + + @param StartAddress Starting address for the MMIO region to be copied from. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer + +**/ +UINT8 * +EFIAPI +MmioReadBuffer8 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT8 *Buffer + ); + +/** + Copy data from MMIO region to system memory by using 16-bit access. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 16-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 16-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied from. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer + +**/ +UINT16 * +EFIAPI +MmioReadBuffer16 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT16 *Buffer + ); + +/** + Copy data from MMIO region to system memory by using 32-bit access. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 32-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 32-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied from. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer + +**/ +UINT32 * +EFIAPI +MmioReadBuffer32 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT32 *Buffer + ); + +/** + Copy data from MMIO region to system memory by using 64-bit access. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 64-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 64-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied from. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer + +**/ +UINT64 * +EFIAPI +MmioReadBuffer64 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT64 *Buffer + ); + +/** + Copy data from system memory to MMIO region by using 8-bit access. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 8-bit access. The total number + of byte to be copied is specified by Length. Buffer is returned. + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + + @param StartAddress Starting address for the MMIO region to be copied to. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer + +**/ +UINT8 * +EFIAPI +MmioWriteBuffer8 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT8 *Buffer + ); + +/** + Copy data from system memory to MMIO region by using 16-bit access. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 16-bit access. The total number + of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 16-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 16-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied to. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer + +**/ +UINT16 * +EFIAPI +MmioWriteBuffer16 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT16 *Buffer + ); + +/** + Copy data from system memory to MMIO region by using 32-bit access. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 32-bit access. The total number + of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 32-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 32-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied to. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer + +**/ +UINT32 * +EFIAPI +MmioWriteBuffer32 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT32 *Buffer + ); + +/** + Copy data from system memory to MMIO region by using 64-bit access. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 64-bit access. The total number + of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 64-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 64-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + + @param StartAddress Starting address for the MMIO region to be copied to. + @param Length The size, in bytes, of Buffer. + @param Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer + +**/ +UINT64 * +EFIAPI +MmioWriteBuffer64 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT64 *Buffer + ); + + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MemoryAllocationLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MemoryAllocationLib.h new file mode 100644 index 0000000000..14efb56895 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MemoryAllocationLib.h @@ -0,0 +1,487 @@ +/** @file + Provides services to allocate and free memory buffers of various memory types and alignments. + + The Memory Allocation Library abstracts various common memory allocation operations. This library + allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE, + and SMM (for example) is done via a different mechanism. Using a common library interface makes it + much easier to port algorithms from phase to phase. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MEMORY_ALLOCATION_LIB_H__ +#define __MEMORY_ALLOCATION_LIB_H__ + +/** + Allocates one or more 4KB pages of type EfiBootServicesData. + + Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocatePages ( + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiRuntimeServicesData. + + Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateRuntimePages ( + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiReservedMemoryType. + + Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL + is returned. If there is not enough memory remaining to satisfy the request, then NULL is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateReservedPages ( + IN UINTN Pages + ); + +/** + Frees one or more 4KB pages that were previously allocated with one of the page allocation + functions in the Memory Allocation Library. + + Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer + must have been allocated on a previous call to the page allocation services of the Memory + Allocation Library. If it is not possible to free allocated pages, then this function will + perform no actions. + + If Buffer was not allocated with a page allocation function in the Memory Allocation Library, + then ASSERT(). + If Pages is zero, then ASSERT(). + + @param Buffer Pointer to the buffer of pages to free. + @param Pages The number of 4 KB pages to free. + +**/ +VOID +EFIAPI +FreePages ( + IN VOID *Buffer, + IN UINTN Pages + ); + +/** + Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateAlignedPages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateAlignedRuntimePages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment. + + Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an + alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is + returned. If there is not enough memory at the specified alignment remaining to satisfy the + request, then NULL is returned. + + If Alignment is not a power of two and Alignment is not zero, then ASSERT(). + If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT(). + + @param Pages The number of 4 KB pages to allocate. + @param Alignment The requested alignment of the allocation. Must be a power of two. + If Alignment is zero, then byte alignment is used. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateAlignedReservedPages ( + IN UINTN Pages, + IN UINTN Alignment + ); + +/** + Frees one or more 4KB pages that were previously allocated with one of the aligned page + allocation functions in the Memory Allocation Library. + + Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer + must have been allocated on a previous call to the aligned page allocation services of the Memory + Allocation Library. If it is not possible to free allocated pages, then this function will + perform no actions. + + If Buffer was not allocated with an aligned page allocation function in the Memory Allocation + Library, then ASSERT(). + If Pages is zero, then ASSERT(). + + @param Buffer Pointer to the buffer of pages to free. + @param Pages The number of 4 KB pages to free. + +**/ +VOID +EFIAPI +FreeAlignedPages ( + IN VOID *Buffer, + IN UINTN Pages + ); + +/** + Allocates a buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a + pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocatePool ( + IN UINTN AllocationSize + ); + +/** + Allocates a buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns + a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateRuntimePool ( + IN UINTN AllocationSize + ); + +/** + Allocates a buffer of type EfiReservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType and returns + a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is + returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateReservedPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateZeroPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateRuntimeZeroPool ( + IN UINTN AllocationSize + ); + +/** + Allocates and zeros a buffer of type EfiReservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the + buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a + valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the + request, then NULL is returned. + + @param AllocationSize The number of bytes to allocate and zero. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateReservedZeroPool ( + IN UINTN AllocationSize + ); + +/** + Copies a buffer to an allocated buffer of type EfiBootServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Copies a buffer to an allocated buffer of type EfiRuntimeServicesData. + + Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateRuntimeCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Copies a buffer to an allocated buffer of type EfiReservedMemoryType. + + Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies + AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the + allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there + is not enough memory remaining to satisfy the request, then NULL is returned. + + If Buffer is NULL, then ASSERT(). + If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + @param AllocationSize The number of bytes to allocate and zero. + @param Buffer The buffer to copy to the allocated buffer. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocateReservedCopyPool ( + IN UINTN AllocationSize, + IN CONST VOID *Buffer + ); + +/** + Reallocates a buffer of type EfiBootServicesData. + + Allocates and zeros the number bytes specified by NewSize from memory of type + EfiBootServicesData. If OldBuffer is not NULL, then the smaller of OldSize and + NewSize bytes are copied from OldBuffer to the newly allocated buffer, and + OldBuffer is freed. A pointer to the newly allocated buffer is returned. + If NewSize is 0, then a valid buffer of 0 size is returned. If there is not + enough memory remaining to satisfy the request, then NULL is returned. + + If the allocation of the new buffer is successful and the smaller of NewSize and OldSize + is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT(). + + @param OldSize The size, in bytes, of OldBuffer. + @param NewSize The size, in bytes, of the buffer to reallocate. + @param OldBuffer The buffer to copy to the allocated buffer. This is an optional + parameter that may be NULL. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +ReallocatePool ( + IN UINTN OldSize, + IN UINTN NewSize, + IN VOID *OldBuffer OPTIONAL + ); + +/** + Reallocates a buffer of type EfiRuntimeServicesData. + + Allocates and zeros the number bytes specified by NewSize from memory of type + EfiRuntimeServicesData. If OldBuffer is not NULL, then the smaller of OldSize and + NewSize bytes are copied from OldBuffer to the newly allocated buffer, and + OldBuffer is freed. A pointer to the newly allocated buffer is returned. + If NewSize is 0, then a valid buffer of 0 size is returned. If there is not + enough memory remaining to satisfy the request, then NULL is returned. + + If the allocation of the new buffer is successful and the smaller of NewSize and OldSize + is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT(). + + @param OldSize The size, in bytes, of OldBuffer. + @param NewSize The size, in bytes, of the buffer to reallocate. + @param OldBuffer The buffer to copy to the allocated buffer. This is an optional + parameter that may be NULL. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +ReallocateRuntimePool ( + IN UINTN OldSize, + IN UINTN NewSize, + IN VOID *OldBuffer OPTIONAL + ); + +/** + Reallocates a buffer of type EfiReservedMemoryType. + + Allocates and zeros the number bytes specified by NewSize from memory of type + EfiReservedMemoryType. If OldBuffer is not NULL, then the smaller of OldSize and + NewSize bytes are copied from OldBuffer to the newly allocated buffer, and + OldBuffer is freed. A pointer to the newly allocated buffer is returned. + If NewSize is 0, then a valid buffer of 0 size is returned. If there is not + enough memory remaining to satisfy the request, then NULL is returned. + + If the allocation of the new buffer is successful and the smaller of NewSize and OldSize + is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT(). + + @param OldSize The size, in bytes, of OldBuffer. + @param NewSize The size, in bytes, of the buffer to reallocate. + @param OldBuffer The buffer to copy to the allocated buffer. This is an optional + parameter that may be NULL. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +ReallocateReservedPool ( + IN UINTN OldSize, + IN UINTN NewSize, + IN VOID *OldBuffer OPTIONAL + ); + +/** + Frees a buffer that was previously allocated with one of the pool allocation functions in the + Memory Allocation Library. + + Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the + pool allocation services of the Memory Allocation Library. If it is not possible to free pool + resources, then this function will perform no actions. + + If Buffer was not allocated with a pool allocation function in the Memory Allocation Library, + then ASSERT(). + + @param Buffer Pointer to the buffer to free. + +**/ +VOID +EFIAPI +FreePool ( + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmServicesTableLib.h new file mode 100644 index 0000000000..e9e4abebea --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmServicesTableLib.h @@ -0,0 +1,19 @@ +/** @file + Provides a service to retrieve a pointer to the Standalone MM Services Table. + Only available to MM_STANDALONE, SMM/DXE Combined and SMM module types. + +Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MM_SERVICES_TABLE_LIB_H__ +#define __MM_SERVICES_TABLE_LIB_H__ + +#include + +extern EFI_MM_SYSTEM_TABLE *gMmst; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmUnblockMemoryLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmUnblockMemoryLib.h new file mode 100644 index 0000000000..cf6b52c7c2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/MmUnblockMemoryLib.h @@ -0,0 +1,44 @@ +/** @file + MM Unblock Memory Library Interface. + + This library provides an interface to request non-MMRAM pages to be mapped/unblocked + from inside MM environment. + + For MM modules that need to access regions outside of MMRAMs, the agents that set up + these regions are responsible for invoking this API in order for these memory areas + to be accessed from inside MM. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_UNBLOCK_MEMORY_LIB_H_ +#define MM_UNBLOCK_MEMORY_LIB_H_ + +/** + This API provides a way to unblock certain data pages to be accessible inside MM environment. + + @param UnblockAddress The address of buffer caller requests to unblock, the address + has to be page aligned. + @param NumberOfPages The number of pages requested to be unblocked from MM + environment. + + @retval RETURN_SUCCESS The request goes through successfully. + @retval RETURN_NOT_AVAILABLE_YET The requested functionality is not produced yet. + @retval RETURN_UNSUPPORTED The requested functionality is not supported on current platform. + @retval RETURN_SECURITY_VIOLATION The requested address failed to pass security check for + unblocking. + @retval RETURN_INVALID_PARAMETER Input address either NULL pointer or not page aligned. + @retval RETURN_ACCESS_DENIED The request is rejected due to system has passed certain boot + phase. + +**/ +RETURN_STATUS +EFIAPI +MmUnblockMemoryRequest ( + IN PHYSICAL_ADDRESS UnblockAddress, + IN UINT64 NumberOfPages +); + +#endif // MM_UNBLOCK_MEMORY_LIB_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/OrderedCollectionLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/OrderedCollectionLib.h new file mode 100644 index 0000000000..6e1db6f859 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/OrderedCollectionLib.h @@ -0,0 +1,419 @@ +/** @file + An ordered collection library interface. + + The library class provides a set of APIs to manage an ordered collection of + items. + + Copyright (C) 2014, Red Hat, Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __ORDERED_COLLECTION_LIB__ +#define __ORDERED_COLLECTION_LIB__ + +#include + +// +// Opaque structure for a collection. +// +typedef struct ORDERED_COLLECTION ORDERED_COLLECTION; + +// +// Opaque structure for collection entries. +// +// Collection entries do not take ownership of the associated user structures, +// they only link them. This makes it easy to link the same user structure into +// several collections. If reference counting is required, the caller is +// responsible for implementing it, as part of the user structure. +// +// A pointer-to-ORDERED_COLLECTION_ENTRY is considered an "iterator". Multiple, +// simultaneous iterations are supported. +// +typedef struct ORDERED_COLLECTION_ENTRY ORDERED_COLLECTION_ENTRY; + +// +// Altering the key field of an in-collection user structure (ie. the portion +// of the user structure that ORDERED_COLLECTION_USER_COMPARE and +// ORDERED_COLLECTION_KEY_COMPARE, below, read) is not allowed in-place. The +// caller is responsible for bracketing the key change with the deletion and +// the reinsertion of the user structure, so that the changed key value is +// reflected in the collection. +// + +/** + Comparator function type for two user structures. + + @param[in] UserStruct1 Pointer to the first user structure. + + @param[in] UserStruct2 Pointer to the second user structure. + + @retval <0 If UserStruct1 compares less than UserStruct2. + + @retval 0 If UserStruct1 compares equal to UserStruct2. + + @retval >0 If UserStruct1 compares greater than UserStruct2. +**/ +typedef +INTN +(EFIAPI *ORDERED_COLLECTION_USER_COMPARE)( + IN CONST VOID *UserStruct1, + IN CONST VOID *UserStruct2 + ); + +/** + Compare a standalone key against a user structure containing an embedded key. + + @param[in] StandaloneKey Pointer to the bare key. + + @param[in] UserStruct Pointer to the user structure with the embedded + key. + + @retval <0 If StandaloneKey compares less than UserStruct's key. + + @retval 0 If StandaloneKey compares equal to UserStruct's key. + + @retval >0 If StandaloneKey compares greater than UserStruct's key. +**/ +typedef +INTN +(EFIAPI *ORDERED_COLLECTION_KEY_COMPARE)( + IN CONST VOID *StandaloneKey, + IN CONST VOID *UserStruct + ); + + +// +// Some functions below are read-only, while others are read-write. If any +// write operation is expected to run concurrently with any other operation on +// the same collection, then the caller is responsible for implementing locking +// for the whole collection. +// + +/** + Retrieve the user structure linked by the specified collection entry. + + Read-only operation. + + @param[in] Entry Pointer to the collection entry whose associated user + structure we want to retrieve. The caller is responsible + for passing a non-NULL argument. + + @return Pointer to user structure linked by Entry. +**/ +VOID * +EFIAPI +OrderedCollectionUserStruct ( + IN CONST ORDERED_COLLECTION_ENTRY *Entry + ); + + +/** + Allocate and initialize the ORDERED_COLLECTION structure. + + @param[in] UserStructCompare This caller-provided function will be used to + order two user structures linked into the + collection, during the insertion procedure. + + @param[in] KeyCompare This caller-provided function will be used to + order the standalone search key against user + structures linked into the collection, during + the lookup procedure. + + @retval NULL If allocation failed. + + @return Pointer to the allocated, initialized ORDERED_COLLECTION + structure, otherwise. +**/ +ORDERED_COLLECTION * +EFIAPI +OrderedCollectionInit ( + IN ORDERED_COLLECTION_USER_COMPARE UserStructCompare, + IN ORDERED_COLLECTION_KEY_COMPARE KeyCompare + ); + + +/** + Check whether the collection is empty (has no entries). + + Read-only operation. + + @param[in] Collection The collection to check for emptiness. + + @retval TRUE The collection is empty. + + @retval FALSE The collection is not empty. +**/ +BOOLEAN +EFIAPI +OrderedCollectionIsEmpty ( + IN CONST ORDERED_COLLECTION *Collection + ); + + +/** + Uninitialize and release an empty ORDERED_COLLECTION structure. + + Read-write operation. + + It is the caller's responsibility to delete all entries from the collection + before calling this function. + + @param[in] Collection The empty collection to uninitialize and release. +**/ +VOID +EFIAPI +OrderedCollectionUninit ( + IN ORDERED_COLLECTION *Collection + ); + + +/** + Look up the collection entry that links the user structure that matches the + specified standalone key. + + Read-only operation. + + @param[in] Collection The collection to search for StandaloneKey. + + @param[in] StandaloneKey The key to locate among the user structures linked + into Collection. StandaloneKey will be passed to + ORDERED_COLLECTION_KEY_COMPARE. + + @retval NULL StandaloneKey could not be found. + + @return The collection entry that links to the user structure matching + StandaloneKey, otherwise. +**/ +ORDERED_COLLECTION_ENTRY * +EFIAPI +OrderedCollectionFind ( + IN CONST ORDERED_COLLECTION *Collection, + IN CONST VOID *StandaloneKey + ); + + +/** + Find the collection entry of the minimum user structure stored in the + collection. + + Read-only operation. + + @param[in] Collection The collection to return the minimum entry of. The + user structure linked by the minimum entry compares + less than all other user structures in the collection. + + @retval NULL If Collection is empty. + + @return The collection entry that links the minimum user structure, + otherwise. +**/ +ORDERED_COLLECTION_ENTRY * +EFIAPI +OrderedCollectionMin ( + IN CONST ORDERED_COLLECTION *Collection + ); + + +/** + Find the collection entry of the maximum user structure stored in the + collection. + + Read-only operation. + + @param[in] Collection The collection to return the maximum entry of. The + user structure linked by the maximum entry compares + greater than all other user structures in the + collection. + + @retval NULL If Collection is empty. + + @return The collection entry that links the maximum user structure, + otherwise. +**/ +ORDERED_COLLECTION_ENTRY * +EFIAPI +OrderedCollectionMax ( + IN CONST ORDERED_COLLECTION *Collection + ); + + +/** + Get the collection entry of the least user structure that is greater than the + one linked by Entry. + + Read-only operation. + + @param[in] Entry The entry to get the successor entry of. + + @retval NULL If Entry is NULL, or Entry is the maximum entry of its + containing collection (ie. Entry has no successor entry). + + @return The collection entry linking the least user structure that is + greater than the one linked by Entry, otherwise. +**/ +ORDERED_COLLECTION_ENTRY * +EFIAPI +OrderedCollectionNext ( + IN CONST ORDERED_COLLECTION_ENTRY *Entry + ); + + +/** + Get the collection entry of the greatest user structure that is less than the + one linked by Entry. + + Read-only operation. + + @param[in] Entry The entry to get the predecessor entry of. + + @retval NULL If Entry is NULL, or Entry is the minimum entry of its + containing collection (ie. Entry has no predecessor entry). + + @return The collection entry linking the greatest user structure that + is less than the one linked by Entry, otherwise. +**/ +ORDERED_COLLECTION_ENTRY * +EFIAPI +OrderedCollectionPrev ( + IN CONST ORDERED_COLLECTION_ENTRY *Entry + ); + + +/** + Insert (link) a user structure into the collection, allocating a new + collection entry. + + Read-write operation. + + @param[in,out] Collection The collection to insert UserStruct into. + + @param[out] Entry The meaning of this optional, output-only + parameter depends on the return value of the + function. + + When insertion is successful (RETURN_SUCCESS), + Entry is set on output to the new collection entry + that now links UserStruct. + + When insertion fails due to lack of memory + (RETURN_OUT_OF_RESOURCES), Entry is not changed. + + When insertion fails due to key collision (ie. + another user structure is already in the + collection that compares equal to UserStruct), + with return value RETURN_ALREADY_STARTED, then + Entry is set on output to the entry that links the + colliding user structure. This enables + "find-or-insert" in one function call, or helps + with later removal of the colliding element. + + @param[in] UserStruct The user structure to link into the collection. + UserStruct is ordered against in-collection user + structures with the + ORDERED_COLLECTION_USER_COMPARE function. + + @retval RETURN_SUCCESS Insertion successful. A new collection entry + has been allocated, linking UserStruct. The + new collection entry is reported back in + Entry (if the caller requested it). + + Existing ORDERED_COLLECTION_ENTRY pointers + into Collection remain valid. For example, + on-going iterations in the caller can + continue with OrderedCollectionNext() / + OrderedCollectionPrev(), and they will + return the new entry at some point if user + structure order dictates it. + + @retval RETURN_OUT_OF_RESOURCES The function failed to allocate memory for + the new collection entry. The collection has + not been changed. Existing + ORDERED_COLLECTION_ENTRY pointers into + Collection remain valid. + + @retval RETURN_ALREADY_STARTED A user structure has been found in the + collection that compares equal to + UserStruct. The entry linking the colliding + user structure is reported back in Entry (if + the caller requested it). The collection has + not been changed. Existing + ORDERED_COLLECTION_ENTRY pointers into + Collection remain valid. +**/ +RETURN_STATUS +EFIAPI +OrderedCollectionInsert ( + IN OUT ORDERED_COLLECTION *Collection, + OUT ORDERED_COLLECTION_ENTRY **Entry OPTIONAL, + IN VOID *UserStruct + ); + + +/** + Delete an entry from the collection, unlinking the associated user structure. + + Read-write operation. + + @param[in,out] Collection The collection to delete Entry from. + + @param[in] Entry The collection entry to delete from Collection. + The caller is responsible for ensuring that Entry + belongs to Collection, and that Entry is non-NULL + and valid. Entry is typically an earlier return + value, or output parameter, of: + + - OrderedCollectionFind(), for deleting an entry + by user structure key, + + - OrderedCollectionMin() / OrderedCollectionMax(), + for deleting the minimum / maximum entry, + + - OrderedCollectionNext() / + OrderedCollectionPrev(), for deleting an entry + found during an iteration, + + - OrderedCollectionInsert() with return value + RETURN_ALREADY_STARTED, for deleting an entry + whose linked user structure caused collision + during insertion. + + Existing ORDERED_COLLECTION_ENTRY pointers (ie. + iterators) *different* from Entry remain valid. + For example: + + - OrderedCollectionNext() / + OrderedCollectionPrev() iterations in the caller + can be continued from Entry, if + OrderedCollectionNext() or + OrderedCollectionPrev() is called on Entry + *before* OrderedCollectionDelete() is. That is, + fetch the successor / predecessor entry first, + then delete Entry. + + - On-going iterations in the caller that would + have otherwise returned Entry at some point, as + dictated by user structure order, will correctly + reflect the absence of Entry after + OrderedCollectionDelete() is called + mid-iteration. + + @param[out] UserStruct If the caller provides this optional output-only + parameter, then on output it is set to the user + structure originally linked by Entry (which is now + freed). + + This is a convenience that may save the caller a + OrderedCollectionUserStruct() invocation before + calling OrderedCollectionDelete(), in order to + retrieve the user structure being unlinked. +**/ +VOID +EFIAPI +OrderedCollectionDelete ( + IN OUT ORDERED_COLLECTION *Collection, + IN ORDERED_COLLECTION_ENTRY *Entry, + OUT VOID **UserStruct OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PcdLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PcdLib.h new file mode 100644 index 0000000000..9a8cb70cd4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PcdLib.h @@ -0,0 +1,1734 @@ +/** @file + Provides library services to get and set Platform Configuration Database entries. + + PCD Library Class provides a PCD usage macro interface for all PCD types. + It should be included in any module that uses PCD. If a module uses dynamic/dynamicex + PCD, module should be linked to a PEIM/DXE library instance to access that PCD. + If a module uses PatchableInModule type PCD, it also needs the library instance to produce + LibPatchPcdSetPtr() interface. For FeatureFlag/Fixed PCD, the macro interface is + translated to a variable or macro that is auto-generated by build tool in + module's autogen.h/autogen.c. + The PcdGetXX(), PcdSetXX(), PcdToken(), and PcdGetNextTokenSpace() operations are + only available prior to ExitBootServices(). If access to PCD values are required + at runtime, then their values must be collected prior to ExitBootServices(). + There are no restrictions on the use of FeaturePcd(), FixedPcdGetXX(), + PatchPcdGetXX(), and PatchPcdSetXX(). + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCD_LIB_H__ +#define __PCD_LIB_H__ + + +/** + Retrieves a token number based on a token name. + + Returns the token number associated with the PCD token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve the token number for. + + @return The token number associated with the PCD. + +**/ +#define PcdToken(TokenName) _PCD_TOKEN_##TokenName + + +/** + Retrieves a Boolean PCD feature flag based on a token name. + + Returns the Boolean value for the PCD feature flag specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a feature flag PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return Boolean value for the PCD feature flag. + +**/ +#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName + + +/** + Retrieves an 8-bit fixed PCD token value based on a token name. + + Returns the 8-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 8-bit value for the token specified by TokenName. + +**/ +#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName + + +/** + Retrieves a 16-bit fixed PCD token value based on a token name. + + Returns the 16-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 16-bit value for the token specified by TokenName. + +**/ +#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName + + +/** + Retrieves a 32-bit fixed PCD token value based on a token name. + + Returns the 32-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 32-bit value for the token specified by TokenName. + +**/ +#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName + + +/** + Retrieves a 64-bit fixed PCD token value based on a token name. + + Returns the 64-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 64-bit value for the token specified by TokenName. + +**/ +#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName + + +/** + Retrieves a Boolean fixed PCD token value based on a token name. + + Returns the Boolean value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return The Boolean value for the token. + +**/ +#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName + + +/** + Retrieves a pointer to a fixed PCD token buffer based on a token name. + + Returns a pointer to the buffer for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a fixed at build PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A pointer to the buffer. + +**/ +#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName) + + +/** + Retrieves an 8-bit binary patchable PCD token value based on a token name. + + Returns the 8-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return An 8-bit binary patchable PCD token value. + +**/ +#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName + +/** + Retrieves a 16-bit binary patchable PCD token value based on a token name. + + Returns the 16-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 16-bit binary patchable PCD token value. + +**/ +#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName + + +/** + Retrieves a 32-bit binary patchable PCD token value based on a token name. + + Returns the 32-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 32-bit binary patchable PCD token value. + +**/ +#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName + + +/** + Retrieves a 64-bit binary patchable PCD token value based on a token name. + + Returns the 64-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 64-bit binary patchable PCD token value. + +**/ +#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName + + +/** + Retrieves a Boolean binary patchable PCD token value based on a token name. + + Returns the Boolean value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return The Boolean value for the token. + +**/ +#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName + + +/** + Retrieves a pointer to a binary patchable PCD token buffer based on a token name. + + Returns a pointer to the buffer for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A pointer to the buffer for the token. + +**/ +#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName) + + +/** + Sets an 8-bit binary patchable PCD token value based on a token name. + + Sets the 8-bit value for the token specified by TokenName. Value is returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param Value The 8-bit value to set. + + @return Return the Value that was set. + +**/ +#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) + + +/** + Sets a 16-bit binary patchable PCD token value based on a token name. + + Sets the 16-bit value for the token specified by TokenName. Value is returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param Value The 16-bit value to set. + + @return Return the Value that was set. + +**/ +#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) + + +/** + Sets a 32-bit binary patchable PCD token value based on a token name. + + Sets the 32-bit value for the token specified by TokenName. Value is returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param Value The 32-bit value to set. + + @return Return the Value that was set. + +**/ +#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) + + +/** + Sets a 64-bit binary patchable PCD token value based on a token name. + + Sets the 64-bit value for the token specified by TokenName. Value is returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param Value The 64-bit value to set. + + @return Return the Value that was set. + +**/ +#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) + + +/** + Sets a Boolean binary patchable PCD token value based on a token name. + + Sets the Boolean value for the token specified by TokenName. Value is returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param Value The boolean value to set. + + @return Return the Value that was set. + +**/ +#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) + + +/** + Sets a pointer to a binary patchable PCD token buffer based on a token name. + + Sets the buffer for the token specified by TokenName. Buffer is returned. + If SizeOfBuffer is greater than the maximum size supported by TokenName, then set SizeOfBuffer + to the maximum size supported by TokenName and return NULL to indicate that the set operation + was not actually performed. If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be + set to the maximum size supported by TokenName and NULL must be returned. + If TokenName is not a valid token in the token space, then the module will not build. + If TokenName is not a patchable in module PCD, then the module will not build. + + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param TokenName The name of the binary patchable PCD token to set the current value for. + @param SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param Buffer Pointer to the value to set. + + @return Return the pointer to the Buffer that was set. + +**/ +#define PatchPcdSetPtr(TokenName, Size, Buffer) \ + LibPatchPcdSetPtrAndSize ( \ + (VOID *)_gPcd_BinaryPatch_##TokenName, \ + &_gPcd_BinaryPatch_Size_##TokenName, \ + (UINTN)_PCD_PATCHABLE_##TokenName##_SIZE, \ + (Size), \ + (Buffer) \ + ) +/** + Retrieves an 8-bit PCD token value based on a token name. + + Returns the 8-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 8-bit value for the token specified by TokenName. + +**/ +#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName + + +/** + Retrieves a 16-bit PCD token value based on a token name. + + Returns the 16-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 16-bit value for the token specified by TokenName. + +**/ +#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName + + +/** + Retrieves a 32-bit PCD token value based on a token name. + + Returns the 32-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 32-bit value for the token specified by TokenName. + +**/ +#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName + + +/** + Retrieves a 64-bit PCD token value based on a token name. + + Returns the 64-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return 64-bit value for the token specified by TokenName. + +**/ +#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName + + +/** + Retrieves a pointer to a PCD token buffer based on a token name. + + Returns a pointer to the buffer for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A pointer to the buffer. + +**/ +#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName + + +/** + Retrieves a Boolean PCD token value based on a token name. + + Returns the Boolean value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A Boolean PCD token value. + +**/ +#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName + + +/** + Retrieves the size of a fixed PCD token based on a token name. + + Returns the size of the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param[in] TokenName The name of the PCD token to retrieve a current value size for. + + @return Return the size + +**/ +#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName + + +/** + Retrieves the size of a binary patchable PCD token based on a token name. + + Returns the size of the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param[in] TokenName The name of the PCD token to retrieve a current value size for. + + @return Return the size + +**/ +#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName + + +/** + Retrieves the size of the PCD token based on a token name. + + Returns the size of the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param[in] TokenName The name of the PCD token to retrieve a current value size for. + + @return Return the size + +**/ +#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName + + +/** + Retrieve the size of a given PCD token. + + Returns the size of the token specified by TokenNumber and Guid. + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value size for. + + @return Return the size. + +**/ +#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName)) + +/** + Sets a 8-bit PCD token value based on a token name. + + Sets the 8-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + @param Value The 8-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value)) + +/** + Sets a 16-bit PCD token value based on a token name. + + Sets the 16-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + @param Value The 16-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value)) + +/** + Sets a 32-bit PCD token value based on a token name. + + Sets the 32-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + @param Value The 32-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value)) + +/** + Sets a 64-bit PCD token value based on a token name. + + Sets the 64-bit value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + @param Value The 64-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value)) + +/** + Sets a pointer to a PCD token buffer based on a token name. + + Sets the buffer for the token specified by TokenName. + If SizeOfBuffer is greater than the maximum size supported by TokenName, + then set SizeOfBuffer to the maximum size supported by TokenName and return + RETURN_INVALID_PARAMETER to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size + supported by TokenName and RETURN_INVALID_PARAMETER must be returned. + If TokenName is not a valid token in the token space, then the module will not build. + + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param TokenName The name of the PCD token to set the current value for. + @param SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param Buffer A pointer to the buffer to set. + + @return The status of the set operation. + +**/ +#define PcdSetPtrS(TokenName, SizeOfBuffer, Buffer) \ + _PCD_SET_MODE_PTR_S_##TokenName ((SizeOfBuffer), (Buffer)) + + + +/** + Sets a boolean PCD token value based on a token name. + + Sets the boolean value for the token specified by TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param TokenName The name of the PCD token to retrieve a current value for. + @param Value The boolean value to set. + + @return The status of the set operation. + +**/ +#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value)) + +/** + Retrieves a token number based on a GUID and a token name. + + Returns the token number for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space, then the module will not build. + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return Return the token number. + +**/ +#define PcdTokenEx(Guid,TokenName) _PCD_TOKEN_EX_##TokenName(Guid) + +/** + Retrieves an 8-bit PCD token value based on a GUID and a token name. + + Returns the 8-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return An 8-bit PCD token value. + +**/ +#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName)) + +/** + Retrieves a 16-bit PCD token value based on a GUID and a token name. + + Returns the 16-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 16-bit PCD token value. + +**/ +#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName)) + + +/** + Retrieves a 32-bit PCD token value based on a GUID and a token name. + + Returns the 32-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 32-bit PCD token value. + +**/ +#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName)) + + +/** + Retrieves a 64-bit PCD token value based on a GUID and a token name. + + Returns the 64-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A 64-bit PCD token value. + +**/ +#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName)) + + +/** + Retrieves a pointer to a PCD token buffer based on a GUID and a token name. + + Returns a pointer to the buffer for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A pointer to a PCD token buffer. + +**/ +#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName)) + + +/** + Retrieves a Boolean PCD token value based on a GUID and a token name. + + Returns the Boolean value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to retrieve a current value for. + + @return A Boolean PCD token value. + +**/ +#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName)) + + + +/** + Sets an 8-bit PCD token value based on a GUID and a token name. + + Sets the 8-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param Value The 8-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value)) + +/** + Sets an 16-bit PCD token value based on a GUID and a token name. + + Sets the 16-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param Value The 16-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value)) + +/** + Sets an 32-bit PCD token value based on a GUID and a token name. + + Sets the 32-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param Value The 32-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value)) + +/** + Sets an 64-bit PCD token value based on a GUID and a token name. + + Sets the 64-bit value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param Value The 64-bit value to set. + + @return The status of the set operation. + +**/ +#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value)) + +/** + Sets a pointer to a PCD token buffer based on a GUID and a token name. + + Sets the buffer for the token specified by Guid and TokenName. + If SizeOfBuffer is greater than the maximum size supported by Guid and TokenName, + then set SizeOfBuffer to the maximum size supported by Guid and TokenName and return + RETURN_INVALID_PARAMETER to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size + supported by Guid and TokenName and RETURN_INVALID_PARAMETER must be returned. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param Buffer Pointer to the buffer to set. + + @return The status of the set operation. + +**/ +#define PcdSetExPtrS(Guid, TokenName, SizeOfBuffer, Buffer) \ + LibPcdSetExPtrS ((Guid), PcdTokenEx(Guid,TokenName), (SizeOfBuffer), (Buffer)) + + +/** + Sets an boolean PCD token value based on a GUID and a token name. + + Sets the boolean value for the token specified by Guid and TokenName. + If TokenName is not a valid token in the token space specified by Guid, + then the module will not build. + + If Guid is NULL, then ASSERT(). + + @param Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param TokenName The name of the PCD token to set the current value for. + @param Value The boolean value to set. + + @return The status of the set operation. + +**/ +#define PcdSetExBoolS(Guid, TokenName, Value) \ + LibPcdSetExBoolS ((Guid), PcdTokenEx(Guid,TokenName), (Value)) + +/** + This function provides a means by which SKU support can be established in the PCD infrastructure. + + Sets the current SKU in the PCD database to the value specified by SkuId. SkuId is returned. + + @param SkuId The SKU value that will be used when the PCD service retrieves and sets values + associated with a PCD token. + + @return Return the SKU ID that was set. + +**/ +UINTN +EFIAPI +LibPcdSetSku ( + IN UINTN SkuId + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 8-bit value for the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the 8-bit value for the token specified by TokenNumber. + +**/ +UINT8 +EFIAPI +LibPcdGet8 ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 16-bit value for the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the 16-bit value for the token specified by TokenNumber. + +**/ +UINT16 +EFIAPI +LibPcdGet16 ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 32-bit value for the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the 32-bit value for the token specified by TokenNumber. + +**/ +UINT32 +EFIAPI +LibPcdGet32 ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 64-bit value for the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the 64-bit value for the token specified by TokenNumber. + +**/ +UINT64 +EFIAPI +LibPcdGet64 ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the pointer to the buffer of the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the pointer to the token specified by TokenNumber. + +**/ +VOID * +EFIAPI +LibPcdGetPtr ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the Boolean value of the token specified by TokenNumber. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the Boolean value of the token specified by TokenNumber. + +**/ +BOOLEAN +EFIAPI +LibPcdGetBool ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve the size of a given PCD token. + + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Returns the size of the token specified by TokenNumber. + +**/ +UINTN +EFIAPI +LibPcdGetSize ( + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 8-bit value for the token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the UINT8. + +**/ +UINT8 +EFIAPI +LibPcdGetEx8 ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 16-bit value for the token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the UINT16. + +**/ +UINT16 +EFIAPI +LibPcdGetEx16 ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + Returns the 32-bit value for the token specified by TokenNumber and Guid. + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the UINT32. + +**/ +UINT32 +EFIAPI +LibPcdGetEx32 ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the 64-bit value for the token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the UINT64. + +**/ +UINT64 +EFIAPI +LibPcdGetEx64 ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the pointer to the buffer of token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the VOID* pointer. + +**/ +VOID * +EFIAPI +LibPcdGetExPtr ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve a value for a given PCD token. + + Returns the Boolean value of the token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the BOOLEAN. + +**/ +BOOLEAN +EFIAPI +LibPcdGetExBool ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to retrieve the size of a given PCD token. + + Returns the size of the token specified by TokenNumber and Guid. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates + which namespace to retrieve a value from. + @param[in] TokenNumber The PCD token number to retrieve a current value for. + + @return Return the size. + +**/ +UINTN +EFIAPI +LibPcdGetExSize ( + IN CONST GUID *Guid, + IN UINTN TokenNumber + ); + + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 8-bit value for the token specified by TokenNumber + to the value specified by Value. + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 8-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSet8S ( + IN UINTN TokenNumber, + IN UINT8 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 16-bit value for the token specified by TokenNumber + to the value specified by Value. + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 16-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSet16S ( + IN UINTN TokenNumber, + IN UINT16 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 32-bit value for the token specified by TokenNumber + to the value specified by Value. + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 32-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSet32S ( + IN UINTN TokenNumber, + IN UINT32 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 64-bit value for the token specified by TokenNumber + to the value specified by Value. + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 64-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSet64S ( + IN UINTN TokenNumber, + IN UINT64 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets a buffer for the token specified by TokenNumber to the value specified + by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than the maximum size + support by TokenNumber, then set SizeOfBuffer to the maximum size supported by + TokenNumber and return RETURN_INVALID_PARAMETER to indicate that the set operation + was not actually performed. + + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the + maximum size supported by TokenName and RETURN_INVALID_PARAMETER must be returned. + + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in, out] SizeOfBuffer The size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetPtrS ( + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfBuffer, + IN CONST VOID *Buffer + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the boolean value for the token specified by TokenNumber + to the value specified by Value. + + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The boolean value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetBoolS ( + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 8-bit value for the token specified by TokenNumber + to the value specified by Value. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid The pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 8-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetEx8S ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN UINT8 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 16-bit value for the token specified by TokenNumber + to the value specified by Value. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid The pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 16-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetEx16S ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN UINT16 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 32-bit value for the token specified by TokenNumber + to the value specified by Value. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid The pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 32-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetEx32S ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN UINT32 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the 64-bit value for the token specified by TokenNumber + to the value specified by Value. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid The pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The 64-bit value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetEx64S ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN UINT64 Value + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets a buffer for the token specified by TokenNumber to the value specified by + Buffer and SizeOfBuffer. If SizeOfBuffer is greater than the maximum size + support by TokenNumber, then set SizeOfBuffer to the maximum size supported by + TokenNumber and return RETURN_INVALID_PARAMETER to indicate that the set operation + was not actually performed. + + If Guid is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in, out] SizeOfBuffer The size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetExPtrS ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfBuffer, + IN VOID *Buffer + ); + +/** + This function provides a means by which to set a value for a given PCD token. + + Sets the boolean value for the token specified by TokenNumber + to the value specified by Value. + + If Guid is NULL, then ASSERT(). + + @param[in] Guid The pointer to a 128-bit unique value that + designates which namespace to set a value from. + @param[in] TokenNumber The PCD token number to set a current value for. + @param[in] Value The boolean value to set. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPcdSetExBoolS ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + +/** + This notification function serves two purposes. + + Firstly, it notifies the module that did the registration that the value of this + PCD token has been set. + Secondly, it provides a mechanism for the module that did the registration to intercept + the set operation and override the value been set if necessary. After the invocation of + the callback function, TokenData will be used by PCD service PEIM or driver to modify th + internal data in PCD database. + + @param[in] CallBackGuid The PCD token GUID being set. + @param[in] CallBackToken The PCD token number being set. + @param[in, out] TokenData A pointer to the token data being set. + @param[in] TokenDataSize The size, in bytes, of the data being set. + +**/ +typedef +VOID +(EFIAPI *PCD_CALLBACK)( + IN CONST GUID *CallBackGuid, OPTIONAL + IN UINTN CallBackToken, + IN OUT VOID *TokenData, + IN UINTN TokenDataSize + ); + + +/** + Set up a notification function that is called when a specified token is set. + + When the token specified by TokenNumber and Guid is set, + then notification function specified by NotificationFunction is called. + If Guid is NULL, then the default token space is used. + If NotificationFunction is NULL, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates which + namespace to set a value from. If NULL, then the default + token space is used. + @param[in] TokenNumber The PCD token number to monitor. + @param[in] NotificationFunction The function to call when the token + specified by Guid and TokenNumber is set. + +**/ +VOID +EFIAPI +LibPcdCallbackOnSet ( + IN CONST GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_CALLBACK NotificationFunction + ); + + +/** + Disable a notification function that was established with LibPcdCallbackonSet(). + + Disable a notification function that was previously established with LibPcdCallbackOnSet(). + If NotificationFunction is NULL, then ASSERT(). + If LibPcdCallbackOnSet() was not previously called with Guid, TokenNumber, + and NotificationFunction, then ASSERT(). + + @param[in] Guid Specify the GUID token space. + @param[in] TokenNumber Specify the token number. + @param[in] NotificationFunction The callback function to be unregistered. + +**/ +VOID +EFIAPI +LibPcdCancelCallback ( + IN CONST GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_CALLBACK NotificationFunction + ); + + +/** + Retrieves the next token in a token space. + + Retrieves the next PCD token number from the token space specified by Guid. + If Guid is NULL, then the default token space is used. If TokenNumber is 0, + then the first token number is returned. Otherwise, the token number that + follows TokenNumber in the token space is returned. If TokenNumber is the last + token number in the token space, then 0 is returned. + + If TokenNumber is not 0 and is not in the token space specified by Guid, then ASSERT(). + + @param[in] Guid Pointer to a 128-bit unique value that designates which namespace + to set a value from. If NULL, then the default token space is used. + @param[in] TokenNumber The previous PCD token number. If 0, then retrieves the first PCD + token number. + + @return The next valid token number. + +**/ +UINTN +EFIAPI +LibPcdGetNextToken ( + IN CONST GUID *Guid, OPTIONAL + IN UINTN TokenNumber + ); + + + +/** + Used to retrieve the list of available PCD token space GUIDs. + + Returns the PCD token space GUID that follows TokenSpaceGuid in the list of token spaces + in the platform. + If TokenSpaceGuid is NULL, then a pointer to the first PCD token spaces returned. + If TokenSpaceGuid is the last PCD token space GUID in the list, then NULL is returned. + + @param TokenSpaceGuid Pointer to the a PCD token space GUID + + @return The next valid token namespace. + +**/ +GUID * +EFIAPI +LibPcdGetNextTokenSpace ( + IN CONST GUID *TokenSpaceGuid + ); + + +/** + Sets a value of a patchable PCD entry that is type pointer. + + Sets the PCD entry specified by PatchVariable to the value specified by Buffer + and SizeOfBuffer. Buffer is returned. If SizeOfBuffer is greater than + MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return + NULL to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to + MaximumDatumSize and NULL must be returned. + + If PatchVariable is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[out] PatchVariable A pointer to the global variable in a module that is + the target of the set operation. + @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable. + @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to used to set the target variable. + + @return Return the pointer to the Buffer that was set. + +**/ +VOID * +EFIAPI +LibPatchPcdSetPtr ( + OUT VOID *PatchVariable, + IN UINTN MaximumDatumSize, + IN OUT UINTN *SizeOfBuffer, + IN CONST VOID *Buffer + ); + +/** + Sets a value of a patchable PCD entry that is type pointer. + + Sets the PCD entry specified by PatchVariable to the value specified + by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than MaximumDatumSize, + then set SizeOfBuffer to MaximumDatumSize and return RETURN_INVALID_PARAMETER + to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to + MaximumDatumSize and RETURN_INVALID_PARAMETER must be returned. + + If PatchVariable is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[out] PatchVariable A pointer to the global variable in a module that is + the target of the set operation. + @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable. + @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to used to set the target variable. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPatchPcdSetPtrS ( + OUT VOID *PatchVariable, + IN UINTN MaximumDatumSize, + IN OUT UINTN *SizeOfBuffer, + IN CONST VOID *Buffer + ); + +/** + Sets a value and size of a patchable PCD entry that is type pointer. + + Sets the PCD entry specified by PatchVariable to the value specified by Buffer + and SizeOfBuffer. Buffer is returned. If SizeOfBuffer is greater than + MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return + NULL to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to + MaximumDatumSize and NULL must be returned. + + If PatchVariable is NULL, then ASSERT(). + If SizeOfPatchVariable is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[out] PatchVariable A pointer to the global variable in a module that is + the target of the set operation. + @param[out] SizeOfPatchVariable A pointer to the size, in bytes, of PatchVariable. + @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable. + @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to used to set the target variable. + + @return Return the pointer to the Buffer that was set. + +**/ +VOID * +EFIAPI +LibPatchPcdSetPtrAndSize ( + OUT VOID *PatchVariable, + OUT UINTN *SizeOfPatchVariable, + IN UINTN MaximumDatumSize, + IN OUT UINTN *SizeOfBuffer, + IN CONST VOID *Buffer + ); + +/** + Sets a value and size of a patchable PCD entry that is type pointer. + + Sets the PCD entry specified by PatchVariable to the value specified + by Buffer and SizeOfBuffer. If SizeOfBuffer is greater than MaximumDatumSize, + then set SizeOfBuffer to MaximumDatumSize and return RETURN_INVALID_PARAMETER + to indicate that the set operation was not actually performed. + If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to + MaximumDatumSize and RETURN_INVALID_PARAMETER must be returned. + + If PatchVariable is NULL, then ASSERT(). + If SizeOfPatchVariable is NULL, then ASSERT(). + If SizeOfBuffer is NULL, then ASSERT(). + If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT(). + + @param[out] PatchVariable A pointer to the global variable in a module that is + the target of the set operation. + @param[out] SizeOfPatchVariable A pointer to the size, in bytes, of PatchVariable. + @param[in] MaximumDatumSize The maximum size allowed for the PCD entry specified by PatchVariable. + @param[in, out] SizeOfBuffer A pointer to the size, in bytes, of Buffer. + @param[in] Buffer A pointer to the buffer to used to set the target variable. + + @return The status of the set operation. + +**/ +RETURN_STATUS +EFIAPI +LibPatchPcdSetPtrAndSizeS ( + OUT VOID *PatchVariable, + OUT UINTN *SizeOfPatchVariable, + IN UINTN MaximumDatumSize, + IN OUT UINTN *SizeOfBuffer, + IN CONST VOID *Buffer + ); + +typedef enum { + PCD_TYPE_8, + PCD_TYPE_16, + PCD_TYPE_32, + PCD_TYPE_64, + PCD_TYPE_BOOL, + PCD_TYPE_PTR +} PCD_TYPE; + +typedef struct { + /// + /// The returned information associated with the requested TokenNumber. If + /// TokenNumber is 0, then PcdType is set to PCD_TYPE_8. + /// + PCD_TYPE PcdType; + /// + /// The size of the data in bytes associated with the TokenNumber specified. If + /// TokenNumber is 0, then PcdSize is set 0. + /// + UINTN PcdSize; + /// + /// The null-terminated ASCII string associated with a given token. If the + /// TokenNumber specified was 0, then this field corresponds to the null-terminated + /// ASCII string associated with the token's namespace Guid. If NULL, there is no + /// name associated with this request. + /// + CHAR8 *PcdName; +} PCD_INFO; + + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + If TokenNumber is not in the default token space specified, then ASSERT(). + + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + The caller is responsible for freeing the buffer that is allocated by callee for PcdInfo->PcdName. +**/ +VOID +EFIAPI +LibPcdGetInfo ( + IN UINTN TokenNumber, + OUT PCD_INFO *PcdInfo + ); + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + If TokenNumber is not in the token space specified by Guid, then ASSERT(). + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + The caller is responsible for freeing the buffer that is allocated by callee for PcdInfo->PcdName. +**/ +VOID +EFIAPI +LibPcdGetInfoEx ( + IN CONST GUID *Guid, + IN UINTN TokenNumber, + OUT PCD_INFO *PcdInfo + ); + +/** + Retrieve the currently set SKU Id. + + @return The currently set SKU Id. If the platform has not set at a SKU Id, then the + default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU + Id is returned. +**/ +UINTN +EFIAPI +LibPcdGetSku ( + VOID + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciCf8Lib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciCf8Lib.h new file mode 100644 index 0000000000..41324e5b60 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciCf8Lib.h @@ -0,0 +1,1088 @@ +/** @file + Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC. + + This library is identical to the PCI Library, except the access method for performing PCI + configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows + access to PCI Segment #0. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_CF8_LIB_H__ +#define __PCI_CF8_LIB_H__ + + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + address that can be passed to the PCI Library functions. + + Computes an address that is compatible with the PCI Library functions. The + unused upper bits of Bus, Device, Function and Register are stripped prior to + the generation of the address. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..255. + + @return The encode PCI address. + +**/ +#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +/** + Registers a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configuration registers + associated with that PCI device may be accessed after SetVirtualAddressMap() is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciCf8RegisterForRuntimeAccess ( + IN UINTN Address + ); + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8Read8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8Write8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8Or8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8And8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8AndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8BitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8BitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8BitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8BitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciCf8BitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8Read16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8Write16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8Or16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8And16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8AndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8BitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8BitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8BitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8BitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciCf8BitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8Read32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8Write32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8Or32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8And32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8AndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8BitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8BitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8BitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8BitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If the register specified by Address >= 0x100, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciCf8BitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If the register specified by StartAddress >= 0x100, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size read from StartAddress. + +**/ +UINTN +EFIAPI +PciCf8ReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAddress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If the register specified by StartAddress >= 0x100, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciCf8WriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciExpressLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciExpressLib.h new file mode 100644 index 0000000000..9d453c24eb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciExpressLib.h @@ -0,0 +1,1057 @@ +/** @file + Provides services to access PCI Configuration Space using the MMIO PCI Express window. + + This library is identical to the PCI Library, except the access method for performing PCI + configuration cycles must be through the PCI Express MMIO window whose base address + is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize. + + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_EXPRESS_LIB_H__ +#define __PCI_EXPRESS_LIB_H__ + +#include + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + address that can be passed to the PCI Library functions. + + Computes an address that is compatible with the PCI Library functions. The + unused upper bits of Bus, Device, Function and Register are stripped prior to + the generation of the address. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..4095. + + @return The encode PCI address. + +**/ +#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset)) + +/** + Registers a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configuration + registers associated with that PCI device may be accessed after SetVirtualAddressMap() + is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciExpressRegisterForRuntimeAccess ( + IN UINTN Address + ); + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size read data from StartAddress. + +**/ +UINTN +EFIAPI +PciExpressReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAddress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciExpressWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciLib.h new file mode 100644 index 0000000000..1b3c13eb2f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciLib.h @@ -0,0 +1,1056 @@ +/** @file + Provides services to access PCI Configuration Space. + + These functions perform PCI configuration cycles using the default PCI configuration + access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, + or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some + alternate access method. Modules will typically use the PCI Library for its PCI configuration + accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or + PCI Express Library may be used in conjunction with the PCI Library. The functionality of + these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use + explicit access methods. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_LIB_H__ +#define __PCI_LIB_H__ + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + address that can be passed to the PCI Library functions. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 + for PCI Express. + + @return The encoded PCI address. + +**/ +#define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \ + (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +/** + Registers a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configuration registers + associated with that PCI device may be accessed after SetVirtualAddressMap() is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciRegisterForRuntimeAccess ( + IN UINTN Address + ); + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, followed by a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAddress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentInfoLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentInfoLib.h new file mode 100644 index 0000000000..20a3eceeb8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentInfoLib.h @@ -0,0 +1,36 @@ +/** @file + Provides services to return segment information on a platform with multiple PCI segments. + + This library is consumed by PciSegmentLib to support multiple segment PCI configuration access. + + Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_SEGMENT_INFO_LIB__ +#define __PCI_SEGMENT_INFO_LIB__ + +typedef struct { + UINT16 SegmentNumber; ///< Segment number. + UINT64 BaseAddress; ///< ECAM Base address. + UINT8 StartBusNumber; ///< Start BUS number, for verifying the PCI Segment address. + UINT8 EndBusNumber; ///< End BUS number, for verifying the PCI Segment address. +} PCI_SEGMENT_INFO; + +/** + Return an array of PCI_SEGMENT_INFO holding the segment information. + + Note: The returned array/buffer is owned by callee. + + @param Count Return the count of segments. + + @retval A callee owned array holding the segment information. +**/ +PCI_SEGMENT_INFO * +EFIAPI +GetPciSegmentInfo ( + UINTN *Count + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentLib.h new file mode 100644 index 0000000000..1054a7c465 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PciSegmentLib.h @@ -0,0 +1,1043 @@ +/** @file + Provides services to access PCI Configuration Space on a platform with multiple PCI segments. + + The PCI Segment Library function provide services to read, write, and modify the PCI configuration + registers on PCI root bridges on any supported PCI segment. These library services take a single + address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. + The layout of this address parameter is as follows: + + PCI Register: Bits 0..11 + PCI Function Bits 12..14 + PCI Device Bits 15..19 + PCI Bus Bits 20..27 + Reserved Bits 28..31. Must be 0. + PCI Segment Bits 32..47 + Reserved Bits 48..63. Must be 0. + + | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register | + 63 48 47 32 31 28 27 20 19 15 14 12 11 0 + + These functions perform PCI configuration cycles using the default PCI configuration access + method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it + may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate + access method. Modules will typically use the PCI Segment Library for its PCI configuration + accesses when PCI Segments other than Segment #0 must be accessed. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_SEGMENT_LIB__ +#define __PCI_SEGMENT_LIB__ + + +/** + Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function, + and PCI Register to an address that can be passed to the PCI Segment Library functions. + + Computes an address that is compatible with the PCI Segment Library functions. + The unused upper bits of Segment, Bus, Device, Function, + and Register are stripped prior to the generation of the address. + + @param Segment PCI Segment number. Range 0..65535. + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express. + + @return The address that is compatible with the PCI Segment Library functions. + +**/ +#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \ + ((Segment != 0) ? \ + ( ((Register) & 0xfff) | \ + (((Function) & 0x07) << 12) | \ + (((Device) & 0x1f) << 15) | \ + (((Bus) & 0xff) << 20) | \ + (LShiftU64 ((Segment) & 0xffff, 32)) \ + ) : \ + ( ((Register) & 0xfff) | \ + (((Function) & 0x07) << 12) | \ + (((Device) & 0x1f) << 15) | \ + (((Bus) & 0xff) << 20) \ + ) \ + ) + +/** + Register a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ); + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ); + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ); + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by OrData, and + writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. This function + must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes + the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, writes the result back to the bit field in the 16-bit register. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ); + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise + AND between the read result and the value specified by AndData, and writes the result + to the 32-bit PCI configuration register specified by Address. The value written to + the PCI configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in AndData are stripped. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAddress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffExtraActionLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffExtraActionLib.h new file mode 100644 index 0000000000..97599d9a47 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffExtraActionLib.h @@ -0,0 +1,47 @@ +/** @file + Provides services to perform additional actions when a PE/COFF image is loaded + or unloaded. This is useful for environment where symbols need to be loaded + and unloaded to support source level debugging. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PE_COFF_EXTRA_ACTION_LIB_H__ +#define __PE_COFF_EXTRA_ACTION_LIB_H__ + +#include + +/** + Performs additional actions after a PE/COFF image has been loaded and relocated. + + If ImageContext is NULL, then ASSERT(). + + @param ImageContext Pointer to the image context structure that describes the + PE/COFF image that has already been loaded and relocated. + +**/ +VOID +EFIAPI +PeCoffLoaderRelocateImageExtraAction ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +/** + Performs additional actions just before a PE/COFF image is unloaded. Any resources + that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed. + + If ImageContext is NULL, then ASSERT(). + + @param ImageContext Pointer to the image context structure that describes the + PE/COFF image that is being unloaded. + +**/ +VOID +EFIAPI +PeCoffLoaderUnloadImageExtraAction ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffGetEntryPointLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffGetEntryPointLib.h new file mode 100644 index 0000000000..99f69a989b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffGetEntryPointLib.h @@ -0,0 +1,116 @@ +/** @file + Provides a service to retrieve the PE/COFF entry point from a PE/COFF image. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PE_COFF_GET_ENTRY_POINT_LIB_H__ +#define __PE_COFF_GET_ENTRY_POINT_LIB_H__ + +/** + Retrieves and returns a pointer to the entry point to a PE/COFF image that has been loaded + into system memory with the PE/COFF Loader Library functions. + + Retrieves the entry point to the PE/COFF image specified by Pe32Data and returns this entry + point in EntryPoint. If the entry point could not be retrieved from the PE/COFF image, then + return RETURN_INVALID_PARAMETER. Otherwise return RETURN_SUCCESS. + If Pe32Data is NULL, then ASSERT(). + If EntryPoint is NULL, then ASSERT(). + + @param Pe32Data The pointer to the PE/COFF image that is loaded in system memory. + @param EntryPoint The pointer to entry point to the PE/COFF image to return. + + @retval RETURN_SUCCESS EntryPoint was returned. + @retval RETURN_INVALID_PARAMETER The entry point could not be found in the PE/COFF image. + +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderGetEntryPoint ( + IN VOID *Pe32Data, + OUT VOID **EntryPoint + ); + +/** + Returns the machine type of a PE/COFF image. + + Returns the machine type from the PE/COFF image specified by Pe32Data. + If Pe32Data is NULL, then ASSERT(). + + @param Pe32Data The pointer to the PE/COFF image that is loaded in system + memory. + + @return Machine type or zero if not a valid image. + +**/ +UINT16 +EFIAPI +PeCoffLoaderGetMachineType ( + IN VOID *Pe32Data + ); + +/** + Returns a pointer to the PDB file name for a PE/COFF image that has been + loaded into system memory with the PE/COFF Loader Library functions. + + Returns the PDB file name for the PE/COFF image specified by Pe32Data. If + the PE/COFF image specified by Pe32Data is not a valid, then NULL is + returned. If the PE/COFF image specified by Pe32Data does not contain a + debug directory entry, then NULL is returned. If the debug directory entry + in the PE/COFF image specified by Pe32Data does not contain a PDB file name, + then NULL is returned. + If Pe32Data is NULL, then ASSERT(). + + @param Pe32Data The pointer to the PE/COFF image that is loaded in system + memory. + + @return The PDB file name for the PE/COFF image specified by Pe32Data, or NULL + if it cannot be retrieved. + +**/ +VOID * +EFIAPI +PeCoffLoaderGetPdbPointer ( + IN VOID *Pe32Data + ); + + +/** + Returns the size of the PE/COFF headers + + Returns the size of the PE/COFF header specified by Pe32Data. + If Pe32Data is NULL, then ASSERT(). + + @param Pe32Data The pointer to the PE/COFF image that is loaded in system + memory. + + @return Size of PE/COFF header in bytes, or zero if not a valid image. + +**/ +UINT32 +EFIAPI +PeCoffGetSizeOfHeaders ( + IN VOID *Pe32Data + ); + +/** + Returns PE/COFF image base specified by the address in this PE/COFF image. + + On DEBUG build, searches the PE/COFF image base forward the address in this + PE/COFF image and returns it. + + @param Address Address located in one PE/COFF image. + + @retval 0 RELEASE build or cannot find the PE/COFF image base. + @retval others PE/COFF image base found. + +**/ +UINTN +EFIAPI +PeCoffSearchImageBase ( + IN UINTN Address + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffLib.h new file mode 100644 index 0000000000..54fe513ed5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeCoffLib.h @@ -0,0 +1,386 @@ +/** @file + Provides services to load and relocate a PE/COFF image. + + The PE/COFF Loader Library abstracts the implementation of a PE/COFF loader for + IA-32, x86, IPF, and EBC processor types. The library functions are memory-based + and can be ported easily to any environment. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __BASE_PE_COFF_LIB_H__ +#define __BASE_PE_COFF_LIB_H__ + +#include +// +// Return status codes from the PE/COFF Loader services +// +#define IMAGE_ERROR_SUCCESS 0 +#define IMAGE_ERROR_IMAGE_READ 1 +#define IMAGE_ERROR_INVALID_PE_HEADER_SIGNATURE 2 +#define IMAGE_ERROR_INVALID_MACHINE_TYPE 3 +#define IMAGE_ERROR_INVALID_SUBSYSTEM 4 +#define IMAGE_ERROR_INVALID_IMAGE_ADDRESS 5 +#define IMAGE_ERROR_INVALID_IMAGE_SIZE 6 +#define IMAGE_ERROR_INVALID_SECTION_ALIGNMENT 7 +#define IMAGE_ERROR_SECTION_NOT_LOADED 8 +#define IMAGE_ERROR_FAILED_RELOCATION 9 +#define IMAGE_ERROR_FAILED_ICACHE_FLUSH 10 +#define IMAGE_ERROR_UNSUPPORTED 11 + +/** + Reads contents of a PE/COFF image. + + A function of this type reads contents of the PE/COFF image specified by FileHandle. The read + operation copies ReadSize bytes from the PE/COFF image starting at byte offset FileOffset into + the buffer specified by Buffer. The size of the buffer actually read is returned in ReadSize. + If FileOffset specifies an offset past the end of the PE/COFF image, a ReadSize of 0 is returned. + A function of this type must be registered in the ImageRead field of a PE_COFF_LOADER_IMAGE_CONTEXT + structure for the PE/COFF Loader Library service to function correctly. This function abstracts access + to a PE/COFF image so it can be implemented in an environment specific manner. For example, SEC and PEI + environments may access memory directly to read the contents of a PE/COFF image, and DXE or UEFI + environments may require protocol services to read the contents of PE/COFF image + stored on FLASH, disk, or network devices. + + If FileHandle is not a valid handle, then ASSERT(). + If ReadSize is NULL, then ASSERT(). + If Buffer is NULL, then ASSERT(). + + @param FileHandle Pointer to the file handle to read the PE/COFF image. + @param FileOffset Offset into the PE/COFF image to begin the read operation. + @param ReadSize On input, the size in bytes of the requested read operation. + On output, the number of bytes actually read. + @param Buffer Output buffer that contains the data read from the PE/COFF image. + + @retval RETURN_SUCCESS The specified portion of the PE/COFF image was + read and the size return in ReadSize. + @retval RETURN_DEVICE_ERROR The specified portion of the PE/COFF image + could not be read due to a device error. + +**/ +typedef +RETURN_STATUS +(EFIAPI *PE_COFF_LOADER_READ_FILE)( + IN VOID *FileHandle, + IN UINTN FileOffset, + IN OUT UINTN *ReadSize, + OUT VOID *Buffer + ); + +/// +/// The context structure used while PE/COFF image is being loaded and relocated. +/// +typedef struct { + /// + /// Set by PeCoffLoaderGetImageInfo() to the ImageBase in the PE/COFF header. + /// + PHYSICAL_ADDRESS ImageAddress; + /// + /// Set by PeCoffLoaderGetImageInfo() to the SizeOfImage in the PE/COFF header. + /// Image size includes the size of Debug Entry if it is present. + /// + UINT64 ImageSize; + /// + /// Is set to zero by PeCoffLoaderGetImageInfo(). If DestinationAddress is non-zero, + /// PeCoffLoaderRelocateImage() will relocate the image using this base address. + /// If the DestinationAddress is zero, the ImageAddress will be used as the base + /// address of relocation. + /// + PHYSICAL_ADDRESS DestinationAddress; + /// + /// PeCoffLoaderLoadImage() sets EntryPoint to to the entry point of the PE/COFF image. + /// + PHYSICAL_ADDRESS EntryPoint; + /// + /// Passed in by the caller to PeCoffLoaderGetImageInfo() and PeCoffLoaderLoadImage() + /// to abstract accessing the image from the library. + /// + PE_COFF_LOADER_READ_FILE ImageRead; + /// + /// Used as the FileHandle passed into the ImageRead function when it's called. + /// + VOID *Handle; + /// + /// Caller allocated buffer of size FixupDataSize that can be optionally allocated + /// prior to calling PeCoffLoaderRelocateImage(). + /// This buffer is filled with the information used to fix up the image. + /// The fixups have been applied to the image and this entry is just for information. + /// + VOID *FixupData; + /// + /// Set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header. + /// If the image is a TE image, then this field is set to 0. + /// + UINT32 SectionAlignment; + /// + /// Set by PeCoffLoaderGetImageInfo() to offset to the PE/COFF header. + /// If the PE/COFF image does not start with a DOS header, this value is zero. + /// Otherwise, it's the offset to the PE/COFF header. + /// + UINT32 PeCoffHeaderOffset; + /// + /// Set by PeCoffLoaderGetImageInfo() to the Relative Virtual Address of the debug directory, + /// if it exists in the image + /// + UINT32 DebugDirectoryEntryRva; + /// + /// Set by PeCoffLoaderLoadImage() to CodeView area of the PE/COFF Debug directory. + /// + VOID *CodeView; + /// + /// Set by PeCoffLoaderLoadImage() to point to the PDB entry contained in the CodeView area. + /// The PdbPointer points to the filename of the PDB file used for source-level debug of + /// the image by a debugger. + /// + CHAR8 *PdbPointer; + /// + /// Is set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header. + /// + UINTN SizeOfHeaders; + /// + /// Not used by this library class. Other library classes that layer on top of this library + /// class fill in this value as part of their GetImageInfo call. + /// This allows the caller of the library to know what type of memory needs to be allocated + /// to load and relocate the image. + /// + UINT32 ImageCodeMemoryType; + /// + /// Not used by this library class. Other library classes that layer on top of this library + /// class fill in this value as part of their GetImageInfo call. + /// This allows the caller of the library to know what type of memory needs to be allocated + /// to load and relocate the image. + /// + UINT32 ImageDataMemoryType; + /// + /// Set by any of the library functions if they encounter an error. + /// + UINT32 ImageError; + /// + /// Set by PeCoffLoaderLoadImage() to indicate the size of FixupData that the caller must + /// allocate before calling PeCoffLoaderRelocateImage(). + /// + UINTN FixupDataSize; + /// + /// Set by PeCoffLoaderGetImageInfo() to the machine type stored in the PE/COFF header. + /// + UINT16 Machine; + /// + /// Set by PeCoffLoaderGetImageInfo() to the subsystem type stored in the PE/COFF header. + /// + UINT16 ImageType; + /// + /// Set by PeCoffLoaderGetImageInfo() to TRUE if the PE/COFF image does not contain + /// relocation information. + /// + BOOLEAN RelocationsStripped; + /// + /// Set by PeCoffLoaderGetImageInfo() to TRUE if the image is a TE image. + /// For a definition of the TE Image format, see the Platform Initialization Pre-EFI + /// Initialization Core Interface Specification. + /// + BOOLEAN IsTeImage; + /// + /// Set by PeCoffLoaderLoadImage() to the HII resource offset + /// if the image contains a custom PE/COFF resource with the type 'HII'. + /// Otherwise, the entry remains to be 0. + /// + PHYSICAL_ADDRESS HiiResourceData; + /// + /// Private storage for implementation specific data. + /// + UINT64 Context; +} PE_COFF_LOADER_IMAGE_CONTEXT; + +/** + Retrieves information about a PE/COFF image. + + Computes the PeCoffHeaderOffset, IsTeImage, ImageType, ImageAddress, ImageSize, + DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and + DebugDirectoryEntryRva fields of the ImageContext structure. + If ImageContext is NULL, then return RETURN_INVALID_PARAMETER. + If the PE/COFF image accessed through the ImageRead service in the ImageContext + structure is not a supported PE/COFF image type, then return RETURN_UNSUPPORTED. + If any errors occur while computing the fields of ImageContext, + then the error status is returned in the ImageError field of ImageContext. + If the image is a TE image, then SectionAlignment is set to 0. + The ImageRead and Handle fields of ImageContext structure must be valid prior + to invoking this service. + + @param ImageContext The pointer to the image context structure that + describes the PE/COFF image that needs to be + examined by this function. + + @retval RETURN_SUCCESS The information on the PE/COFF image was collected. + @retval RETURN_INVALID_PARAMETER ImageContext is NULL. + @retval RETURN_UNSUPPORTED The PE/COFF image is not supported. + +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderGetImageInfo ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +/** + Applies relocation fixups to a PE/COFF image that was loaded with PeCoffLoaderLoadImage(). + + If the DestinationAddress field of ImageContext is 0, then use the ImageAddress field of + ImageContext as the relocation base address. Otherwise, use the DestinationAddress field + of ImageContext as the relocation base address. The caller must allocate the relocation + fixup log buffer and fill in the FixupData field of ImageContext prior to calling this function. + + The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, + ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, + DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of + the ImageContext structure must be valid prior to invoking this service. + + If ImageContext is NULL, then ASSERT(). + + Note that if the platform does not maintain coherency between the instruction cache(s) and the data + cache(s) in hardware, then the caller is responsible for performing cache maintenance operations + prior to transferring control to a PE/COFF image that is loaded using this library. + + @param ImageContext The pointer to the image context structure that describes the PE/COFF + image that is being relocated. + + @retval RETURN_SUCCESS The PE/COFF image was relocated. + Extended status information is in the ImageError field of ImageContext. + @retval RETURN_LOAD_ERROR The image in not a valid PE/COFF image. + Extended status information is in the ImageError field of ImageContext. + @retval RETURN_UNSUPPORTED A relocation record type is not supported. + Extended status information is in the ImageError field of ImageContext. + +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderRelocateImage ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + +/** + Loads a PE/COFF image into memory. + + Loads the PE/COFF image accessed through the ImageRead service of ImageContext into the buffer + specified by the ImageAddress and ImageSize fields of ImageContext. The caller must allocate + the load buffer and fill in the ImageAddress and ImageSize fields prior to calling this function. + The EntryPoint, FixupDataSize, CodeView, PdbPointer and HiiResourceData fields of ImageContext are computed. + The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize, + DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva + fields of the ImageContext structure must be valid prior to invoking this service. + + If ImageContext is NULL, then ASSERT(). + + Note that if the platform does not maintain coherency between the instruction cache(s) and the data + cache(s) in hardware, then the caller is responsible for performing cache maintenance operations + prior to transferring control to a PE/COFF image that is loaded using this library. + + @param ImageContext The pointer to the image context structure that describes the PE/COFF + image that is being loaded. + + @retval RETURN_SUCCESS The PE/COFF image was loaded into the buffer specified by + the ImageAddress and ImageSize fields of ImageContext. + Extended status information is in the ImageError field of ImageContext. + @retval RETURN_BUFFER_TOO_SMALL The caller did not provide a large enough buffer. + Extended status information is in the ImageError field of ImageContext. + @retval RETURN_LOAD_ERROR The PE/COFF image is an EFI Runtime image with no relocations. + Extended status information is in the ImageError field of ImageContext. + @retval RETURN_INVALID_PARAMETER The image address is invalid. + Extended status information is in the ImageError field of ImageContext. + +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderLoadImage ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); + + +/** + Reads contents of a PE/COFF image from a buffer in system memory. + + This is the default implementation of a PE_COFF_LOADER_READ_FILE function + that assumes FileHandle pointer to the beginning of a PE/COFF image. + This function reads contents of the PE/COFF image that starts at the system memory + address specified by FileHandle. The read operation copies ReadSize bytes from the + PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer. + The size of the buffer actually read is returned in ReadSize. + + If FileHandle is NULL, then ASSERT(). + If ReadSize is NULL, then ASSERT(). + If Buffer is NULL, then ASSERT(). + + @param FileHandle The pointer to base of the input stream + @param FileOffset Offset into the PE/COFF image to begin the read operation. + @param ReadSize On input, the size in bytes of the requested read operation. + On output, the number of bytes actually read. + @param Buffer Output buffer that contains the data read from the PE/COFF image. + + @retval RETURN_SUCCESS The data is read from FileOffset from the Handle into + the buffer. +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderImageReadFromMemory ( + IN VOID *FileHandle, + IN UINTN FileOffset, + IN OUT UINTN *ReadSize, + OUT VOID *Buffer + ); + + +/** + Reapply fixups on a fixed up PE32/PE32+ image to allow virtual calling at EFI + runtime. + + This function reapplies relocation fixups to the PE/COFF image specified by ImageBase + and ImageSize so the image will execute correctly when the PE/COFF image is mapped + to the address specified by VirtualImageBase. RelocationData must be identical + to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure + after this PE/COFF image was relocated with PeCoffLoaderRelocateImage(). + + Note that if the platform does not maintain coherency between the instruction cache(s) and the data + cache(s) in hardware, then the caller is responsible for performing cache maintenance operations + prior to transferring control to a PE/COFF image that is loaded using this library. + + @param ImageBase The base address of a PE/COFF image that has been loaded + and relocated into system memory. + @param VirtImageBase The request virtual address that the PE/COFF image is to + be fixed up for. + @param ImageSize The size, in bytes, of the PE/COFF image. + @param RelocationData A pointer to the relocation data that was collected when the PE/COFF + image was relocated using PeCoffLoaderRelocateImage(). + +**/ +VOID +EFIAPI +PeCoffLoaderRelocateImageForRuntime ( + IN PHYSICAL_ADDRESS ImageBase, + IN PHYSICAL_ADDRESS VirtImageBase, + IN UINTN ImageSize, + IN VOID *RelocationData + ); + +/** + Unloads a loaded PE/COFF image from memory and releases its taken resource. + Releases any environment specific resources that were allocated when the image + specified by ImageContext was loaded using PeCoffLoaderLoadImage(). + + For NT32 emulator, the PE/COFF image loaded by system needs to release. + For real platform, the PE/COFF image loaded by Core doesn't needs to be unloaded, + this function can simply return RETURN_SUCCESS. + + If ImageContext is NULL, then ASSERT(). + + @param ImageContext Pointer to the image context structure that describes the PE/COFF + image to be unloaded. + + @retval RETURN_SUCCESS The PE/COFF image was unloaded successfully. +**/ +RETURN_STATUS +EFIAPI +PeCoffLoaderUnloadImage ( + IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext + ); +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiCoreEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiCoreEntryPoint.h new file mode 100644 index 0000000000..35b52f7375 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiCoreEntryPoint.h @@ -0,0 +1,132 @@ +/** @file + Module entry point library for PEI core. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/** + The entry point of PE/COFF Image for the PEI Core. + + This function is the entry point for the PEI Foundation, which allows the SEC phase + to pass information about the stack, temporary RAM and the Boot Firmware Volume. + In addition, it also allows the SEC phase to pass services and data forward for use + during the PEI phase in the form of one or more PPIs. + There is no limit to the number of additional PPIs that can be passed from SEC into + the PEI Foundation. As part of its initialization phase, the PEI Foundation will add + these SEC-hosted PPIs to its PPI database such that both the PEI Foundation and any + modules can leverage the associated service calls and/or code in these early PPIs. + This function is required to call ProcessModuleEntryPointList() with the Context + parameter set to NULL. ProcessModuleEntryPoint() is never expected to return. + The PEI Core is responsible for calling ProcessLibraryConstructorList() as soon as + the PEI Services Table and the file handle for the PEI Core itself have been established. + If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system. + + @param SecCoreData Points to a data structure containing information about the PEI + core's operating environment, such as the size and location of + temporary RAM, the stack location and the BFV location. + + @param PpiList Points to a list of one or more PPI descriptors to be installed + initially by the PEI core. An empty PPI list consists of a single + descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. + As part of its initialization phase, the PEI Foundation will add + these SEC-hosted PPIs to its PPI database such that both the PEI + Foundation and any modules can leverage the associated service calls + and/or code in these early PPIs. + +**/ +VOID +EFIAPI +_ModuleEntryPoint( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList + ); + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + This function is required to call _ModuleEntryPoint() passing in SecCoreData and PpiList. + + @param SecCoreData Points to a data structure containing information about the PEI core's + operating environment, such as the size and location of temporary RAM, + the stack location and the BFV location. + + @param PpiList Points to a list of one or more PPI descriptors to be installed + initially by the PEI core. An empty PPI list consists of a single + descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. + As part of its initialization phase, the PEI Foundation will add these + SEC-hosted PPIs to its PPI database such that both the PEI Foundation + and any modules can leverage the associated service calls and/or code + in these early PPIs. + +**/ +VOID +EFIAPI +EfiMain ( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList + ); + +/** + Autogenerated function that calls the library constructors for all of the module's + dependent libraries. + + This function must be called by the PEI Core once an initial PEI Services Table has been established. + This function calls the set of library constructors for the set of library instances that a + module depends on. This include library instances that a module depends on directly and library + instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible for collecting + the set of library instances, determining which ones have constructors, and calling the library + constructors in the proper order based upon the dependencies of each of the library instances. + The PEI Core must call this function with a NULL FileHandle value as soon as the initial PEI + Services Table has been established. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + + +/** + Autogenerated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module entry points and calling them in a specified order. + + @param SecCoreData Points to a data structure containing information about the PEI + core's operating environment, such as the size and location of + temporary RAM, the stack location and the BFV location. + + @param PpiList Points to a list of one or more PPI descriptors to be installed + initially by the PEI core. An empty PPI list consists of a single + descriptor with the end-tag EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. + As part of its initialization phase, the PEI Foundation will add + these SEC-hosted PPIs to its PPI database such that both the PEI + Foundation and any modules can leverage the associated service calls + and/or code in these early PPIs. + @param Context A pointer to a private context structure defined by the PEI Core + implementation. The implementation of _ModuleEntryPoint() must set + this parameter is NULL to indicate that this is the first PEI phase. + +**/ +VOID +EFIAPI +ProcessModuleEntryPointList ( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList, + IN VOID *Context + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesLib.h new file mode 100644 index 0000000000..de14fb902f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesLib.h @@ -0,0 +1,559 @@ +/** @file + Provides library functions for all PEI Services. + +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PEI_SERVICES_LIB_H__ +#define __PEI_SERVICES_LIB_H__ + +/** + This service enables a given PEIM to register an interface into the PEI Foundation. + + @param PpiList A pointer to the list of interfaces that the caller shall install. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL. + @retval EFI_INVALID_PARAMETER Any of the PEI PPI descriptors in the list do not have the + EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + +**/ +EFI_STATUS +EFIAPI +PeiServicesInstallPpi ( + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList + ); + +/** + This service enables PEIMs to replace an entry in the PPI database with an alternate entry. + + @param OldPpi Pointer to the old PEI PPI Descriptors. + @param NewPpi Pointer to the new PEI PPI Descriptors. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The OldPpi or NewPpi is NULL. + @retval EFI_INVALID_PARAMETER Any of the PEI PPI descriptors in the list do not have the + EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + @retval EFI_NOT_FOUND The PPI for which the reinstallation was requested has not been + installed. + +**/ +EFI_STATUS +EFIAPI +PeiServicesReInstallPpi ( + IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi, + IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi + ); + +/** + This service enables PEIMs to discover a given instance of an interface. + + @param Guid A pointer to the GUID whose corresponding interface needs to be + found. + @param Instance The N-th instance of the interface that is required. + @param PpiDescriptor A pointer to instance of the EFI_PEI_PPI_DESCRIPTOR. + @param Ppi A pointer to the instance of the interface. + + @retval EFI_SUCCESS The interface was successfully returned. + @retval EFI_NOT_FOUND The PPI descriptor is not found in the database. + +**/ +EFI_STATUS +EFIAPI +PeiServicesLocatePpi ( + IN CONST EFI_GUID *Guid, + IN UINTN Instance, + IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, OPTIONAL + IN OUT VOID **Ppi + ); + +/** + This service enables PEIMs to register a given service to be invoked when another service is + installed or reinstalled. + + @param NotifyList A pointer to the list of notification interfaces that the caller + shall install. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The NotifyList pointer is NULL. + @retval EFI_INVALID_PARAMETER Any of the PEI notify descriptors in the list do not have the + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + +**/ +EFI_STATUS +EFIAPI +PeiServicesNotifyPpi ( + IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList + ); + +/** + This service enables PEIMs to ascertain the present value of the boot mode. + + @param BootMode A pointer to contain the value of the boot mode. + + @retval EFI_SUCCESS The boot mode was returned successfully. + @retval EFI_INVALID_PARAMETER BootMode is NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesGetBootMode ( + OUT EFI_BOOT_MODE *BootMode + ); + +/** + This service enables PEIMs to update the boot mode variable. + + @param BootMode The value of the boot mode to set. + + @retval EFI_SUCCESS The value was successfully updated + +**/ +EFI_STATUS +EFIAPI +PeiServicesSetBootMode ( + IN EFI_BOOT_MODE BootMode + ); + +/** + This service enables a PEIM to ascertain the address of the list of HOBs in memory. + + @param HobList A pointer to the list of HOBs that the PEI Foundation will initialize. + + @retval EFI_SUCCESS The list was successfully returned. + @retval EFI_NOT_AVAILABLE_YET The HOB list is not yet published. + +**/ +EFI_STATUS +EFIAPI +PeiServicesGetHobList ( + OUT VOID **HobList + ); + +/** + This service enables PEIMs to create various types of HOBs. + + @param Type The type of HOB to be installed. + @param Length The length of the HOB to be added. + @param Hob The address of a pointer that will contain the HOB header. + + @retval EFI_SUCCESS The HOB was successfully created. + @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation. + +**/ +EFI_STATUS +EFIAPI +PeiServicesCreateHob ( + IN UINT16 Type, + IN UINT16 Length, + OUT VOID **Hob + ); + +/** + This service enables PEIMs to discover additional firmware volumes. + + @param Instance This instance of the firmware volume to find. The value 0 is the + Boot Firmware Volume (BFV). + @param VolumeHandle Handle of the firmware volume header of the volume to return. + + @retval EFI_SUCCESS The volume was found. + @retval EFI_NOT_FOUND The volume was not found. + @retval EFI_INVALID_PARAMETER FwVolHeader is NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsFindNextVolume ( + IN UINTN Instance, + IN OUT EFI_PEI_FV_HANDLE *VolumeHandle + ); + +/** + This service enables PEIMs to discover additional firmware files. + + @param SearchType A filter to find files only of this type. + @param VolumeHandle Pointer to the firmware volume header of the volume to search. + This parameter must point to a valid FFS volume. + @param FileHandle Handle of the current file from which to begin searching. + + @retval EFI_SUCCESS The file was found. + @retval EFI_NOT_FOUND The file was not found. + @retval EFI_NOT_FOUND The header checksum was not zero. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsFindNextFile ( + IN EFI_FV_FILETYPE SearchType, + IN EFI_PEI_FV_HANDLE VolumeHandle, + IN OUT EFI_PEI_FILE_HANDLE *FileHandle + ); + +/** + This service enables PEIMs to discover sections of a given type within a valid FFS file. + + @param SectionType The value of the section type to find. + @param FileHandle A pointer to the file header that contains the set of sections to + be searched. + @param SectionData A pointer to the discovered section, if successful. + + @retval EFI_SUCCESS The section was found. + @retval EFI_NOT_FOUND The section was not found. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsFindSectionData ( + IN EFI_SECTION_TYPE SectionType, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData + ); + +/** + This service enables PEIMs to discover sections of a given instance and type within a valid FFS file. + + @param SectionType The value of the section type to find. + @param SectionInstance Section instance to find. + @param FileHandle A pointer to the file header that contains the set + of sections to be searched. + @param SectionData A pointer to the discovered section, if successful. + @param AuthenticationStatus A pointer to the authentication status for this section. + + @retval EFI_SUCCESS The section was found. + @retval EFI_NOT_FOUND The section was not found. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsFindSectionData3 ( + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData, + OUT UINT32 *AuthenticationStatus + ); + +/** + This service enables PEIMs to register the permanent memory configuration + that has been initialized with the PEI Foundation. + + @param MemoryBegin The value of a region of installed memory. + @param MemoryLength The corresponding length of a region of installed memory. + + @retval EFI_SUCCESS The region was successfully installed in a HOB. + @retval EFI_INVALID_PARAMETER MemoryBegin and MemoryLength are illegal for this system. + @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation. + +**/ +EFI_STATUS +EFIAPI +PeiServicesInstallPeiMemory ( + IN EFI_PHYSICAL_ADDRESS MemoryBegin, + IN UINT64 MemoryLength + ); + +/** + This service enables PEIMs to allocate memory. + + @param MemoryType Type of memory to allocate. + @param Pages The number of pages to allocate. + @param Memory Pointer of memory allocated. + + @retval EFI_SUCCESS The memory range was successfully allocated. + @retval EFI_INVALID_PARAMETER Type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode, + EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData, + EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS. + @retval EFI_OUT_OF_RESOURCES The pages could not be allocated. + +**/ +EFI_STATUS +EFIAPI +PeiServicesAllocatePages ( + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT EFI_PHYSICAL_ADDRESS *Memory + ); + +/** + This service enables PEIMs to free memory. + + @param Memory Memory to be freed. + @param Pages The number of pages to free. + + @retval EFI_SUCCESS The requested pages were freed. + @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid. + @retval EFI_NOT_FOUND The requested memory pages were not allocated with + AllocatePages(). + +**/ +EFI_STATUS +EFIAPI +PeiServicesFreePages ( + IN EFI_PHYSICAL_ADDRESS Memory, + IN UINTN Pages + ); + +/** + This service allocates memory from the Hand-Off Block (HOB) heap. + + @param Size The number of bytes to allocate from the pool. + @param Buffer If the call succeeds, a pointer to a pointer to the allocate + buffer; undefined otherwise. + + @retval EFI_SUCCESS The allocation was successful + @retval EFI_OUT_OF_RESOURCES There is not enough heap to allocate the requested size. + +**/ +EFI_STATUS +EFIAPI +PeiServicesAllocatePool ( + IN UINTN Size, + OUT VOID **Buffer + ); + +/** + Resets the entire platform. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_AVAILABLE_YET The service has not been installed yet. + +**/ +EFI_STATUS +EFIAPI +PeiServicesResetSystem ( + VOID + ); + + +/** + This service is a wrapper for the PEI Service FfsFindByName(), except the pointer to the PEI Services + Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface + Specification for details. + + @param FileName A pointer to the name of the file to + find within the firmware volume. + + @param VolumeHandle The firmware volume to search FileHandle + Upon exit, points to the found file's + handle or NULL if it could not be found. + @param FileHandle Pointer to found file handle + + @retval EFI_SUCCESS File was found. + + @retval EFI_NOT_FOUND File was not found. + + @retval EFI_INVALID_PARAMETER VolumeHandle or FileHandle or + FileName was NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsFindFileByName ( + IN CONST EFI_GUID *FileName, + IN CONST EFI_PEI_FV_HANDLE VolumeHandle, + OUT EFI_PEI_FILE_HANDLE *FileHandle + ); + + +/** + This service is a wrapper for the PEI Service FfsGetFileInfo(), except the pointer to the PEI Services + Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface + Specification for details. + + @param FileHandle Handle of the file. + + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information returned. + + @retval EFI_INVALID_PARAMETER If FileHandle does not + represent a valid file. + + @retval EFI_INVALID_PARAMETER If FileInfo is NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsGetFileInfo ( + IN CONST EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO *FileInfo + ); + +/** + This service is a wrapper for the PEI Service FfsGetFileInfo2(), except the pointer to the PEI Services + Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface + Specification for details. + + @param FileHandle Handle of the file. + + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information returned. + + @retval EFI_INVALID_PARAMETER If FileHandle does not + represent a valid file. + + @retval EFI_INVALID_PARAMETER If FileInfo is NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsGetFileInfo2 ( + IN CONST EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO2 *FileInfo + ); + +/** + This service is a wrapper for the PEI Service FfsGetVolumeInfo(), except the pointer to the PEI Services + Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface + Specification for details. + + @param VolumeHandle Handle of the volume. + + @param VolumeInfo Upon exit, points to the volume's + information. + + @retval EFI_SUCCESS File information returned. + + @retval EFI_INVALID_PARAMETER If FileHandle does not + represent a valid file. + + @retval EFI_INVALID_PARAMETER If FileInfo is NULL. + +**/ +EFI_STATUS +EFIAPI +PeiServicesFfsGetVolumeInfo ( + IN EFI_PEI_FV_HANDLE VolumeHandle, + OUT EFI_FV_INFO *VolumeInfo + ); + + +/** + This service is a wrapper for the PEI Service RegisterForShadow(), except the pointer to the PEI Services + Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface + Specification for details. + + @param FileHandle PEIM's file handle. Must be the currently + executing PEIM. + + @retval EFI_SUCCESS The PEIM was successfully registered for + shadowing. + + @retval EFI_ALREADY_STARTED The PEIM was previously + registered for shadowing. + + @retval EFI_NOT_FOUND The FileHandle does not refer to a + valid file handle. +**/ +EFI_STATUS +EFIAPI +PeiServicesRegisterForShadow ( + IN EFI_PEI_FILE_HANDLE FileHandle + ); + +/** + Install a EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance so the PEI Core will be notified about a new firmware volume. + + This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO_PPI using + the parameters passed in to initialize the fields of the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance. + If the resources can not be allocated for EFI_PEI_FIRMWARE_VOLUME_INFO_PPI, then ASSERT(). + If the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI can not be installed, then ASSERT(). + + + @param FvFormat Unique identifier of the format of the memory-mapped firmware volume. + This parameter is optional and may be NULL. + If NULL is specified, the EFI_FIRMWARE_FILE_SYSTEM2_GUID format is assumed. + @param FvInfo Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume. + The format of this buffer is specific to the FvFormat. For memory-mapped firmware volumes, + this typically points to the first byte of the firmware volume. + @param FvInfoSize The size, in bytes, of FvInfo. For memory-mapped firmware volumes, + this is typically the size of the firmware volume. + @param ParentFvName If the new firmware volume originated from a file in a different firmware volume, + then this parameter specifies the GUID name of the originating firmware volume. + Otherwise, this parameter must be NULL. + @param ParentFileName If the new firmware volume originated from a file in a different firmware volume, + then this parameter specifies the GUID file name of the originating firmware file. + Otherwise, this parameter must be NULL. +**/ +VOID +EFIAPI +PeiServicesInstallFvInfoPpi ( + IN CONST EFI_GUID *FvFormat, OPTIONAL + IN CONST VOID *FvInfo, + IN UINT32 FvInfoSize, + IN CONST EFI_GUID *ParentFvName, OPTIONAL + IN CONST EFI_GUID *ParentFileName OPTIONAL + ); + +/** + Install a EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI instance so the PEI Core will be notified about a new firmware volume. + + This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI using + the parameters passed in to initialize the fields of the EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI instance. + If the resources can not be allocated for EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI, then ASSERT(). + If the EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI can not be installed, then ASSERT(). + + @param FvFormat Unique identifier of the format of the memory-mapped + firmware volume. This parameter is optional and + may be NULL. If NULL is specified, the + EFI_FIRMWARE_FILE_SYSTEM2_GUID format is assumed. + @param FvInfo Points to a buffer which allows the + EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume. + The format of this buffer is specific to the FvFormat. + For memory-mapped firmware volumes, this typically + points to the first byte of the firmware volume. + @param FvInfoSize The size, in bytes, of FvInfo. For memory-mapped + firmware volumes, this is typically the size of + the firmware volume. + @param ParentFvName If the new firmware volume originated from a file + in a different firmware volume, then this parameter + specifies the GUID name of the originating firmware + volume. Otherwise, this parameter must be NULL. + @param ParentFileName If the new firmware volume originated from a file + in a different firmware volume, then this parameter + specifies the GUID file name of the originating + firmware file. Otherwise, this parameter must be NULL. + @param AuthenticationStatus Authentication Status +**/ +VOID +EFIAPI +PeiServicesInstallFvInfo2Ppi ( + IN CONST EFI_GUID *FvFormat, OPTIONAL + IN CONST VOID *FvInfo, + IN UINT32 FvInfoSize, + IN CONST EFI_GUID *ParentFvName, OPTIONAL + IN CONST EFI_GUID *ParentFileName, OPTIONAL + IN UINT32 AuthenticationStatus + ); + +/** + Resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown + the data buffer starts with a Null-terminated string, optionally + followed by additional binary data. The string is a description + that the caller may use to further indicate the reason for the + system reset. + +**/ +VOID +EFIAPI +PeiServicesResetSystem2 ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesTablePointerLib.h new file mode 100644 index 0000000000..eb81338943 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeiServicesTablePointerLib.h @@ -0,0 +1,68 @@ +/** @file + Provides a service to retrieve a pointer to the PEI Services Table. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PEI_SERVICES_TABLE_POINTER_LIB_H__ +#define __PEI_SERVICES_TABLE_POINTER_LIB_H__ + +/** + Retrieves the cached value of the PEI Services Table pointer. + + Returns the cached value of the PEI Services Table pointer in a CPU specific manner + as specified in the CPU binding section of the Platform Initialization Pre-EFI + Initialization Core Interface Specification. + + If the cached PEI Services Table pointer is NULL, then ASSERT(). + + @return The pointer to PeiServices. + +**/ +CONST EFI_PEI_SERVICES ** +EFIAPI +GetPeiServicesTablePointer ( + VOID + ); + +/** + Caches a pointer PEI Services Table. + + Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer + in a CPU specific manner as specified in the CPU binding section of the Platform Initialization + Pre-EFI Initialization Core Interface Specification. + + If PeiServicesTablePointer is NULL, then ASSERT(). + + @param PeiServicesTablePointer The address of PeiServices pointer. +**/ +VOID +EFIAPI +SetPeiServicesTablePointer ( + IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer + ); + +/** + Perform CPU specific actions required to migrate the PEI Services Table + pointer from temporary RAM to permanent RAM. + + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in + a dedicated CPU register. This means that there is no memory storage + associated with storing the PEI Services Table pointer, so no additional + migration actions are required for Itanium or ARM CPUs. + +**/ +VOID +EFIAPI +MigratePeiServicesTablePointer ( + VOID + ); + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeimEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeimEntryPoint.h new file mode 100644 index 0000000000..61473aafdd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PeimEntryPoint.h @@ -0,0 +1,103 @@ +/** @file + Module entry point library for PEIM. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/// +/// Declare the EFI/UEFI Specification Revision to which this driver is implemented +/// +extern CONST UINT32 _gPeimRevision; + + +/** + The entry point of PE/COFF Image for a PEIM. + + This function is the entry point for a PEIM. This function must call ProcessLibraryConstructorList() + and ProcessModuleEntryPointList(). The return value from ProcessModuleEntryPointList() is returned. + If _gPeimRevision is not zero and PeiServices->Hdr.Revision is less than _gPeimRevison, then ASSERT(). + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS The PEIM executed normally. + @retval !EFI_SUCCESS The PEIM failed to execute normally. +**/ +EFI_STATUS +EFIAPI +_ModuleEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + This function is required to call _ModuleEntryPoint() passing in FileHandle and PeiServices. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS The PEIM executed normally. + @retval !EFI_SUCCESS The PEIM failed to execute normally. + +**/ +EFI_STATUS +EFIAPI +EfiMain ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + Autogenerated function that calls the library constructors for all of the module's + dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library instances that a + module depends on. This includes library instances that a module depends on directly and library + instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible for collecting + the set of library instances, determine which ones have constructors, and calling the library + constructors in the proper order based upon each of the library instances own dependencies. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + Autogenerated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module entry points and calling them in a specified order. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS The PEIM executed normally. + @retval !EFI_SUCCESS The PEIM failed to execute normally. + +**/ +EFI_STATUS +EFIAPI +ProcessModuleEntryPointList ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PerformanceLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PerformanceLib.h new file mode 100644 index 0000000000..96b1e000f0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PerformanceLib.h @@ -0,0 +1,766 @@ +/** @file + Provides services to log the execution times and retrieve them later. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PERFORMANCE_LIB_H__ +#define __PERFORMANCE_LIB_H__ + +/// +/// Performance library propery mask bits +/// +#define PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED 0x00000001 + +// +// Public Progress Identifiers for Event Records. +// +#define PERF_EVENT_ID 0x00 + +#define MODULE_START_ID 0x01 +#define MODULE_END_ID 0x02 +#define MODULE_LOADIMAGE_START_ID 0x03 +#define MODULE_LOADIMAGE_END_ID 0x04 +#define MODULE_DB_START_ID 0x05 +#define MODULE_DB_END_ID 0x06 +#define MODULE_DB_SUPPORT_START_ID 0x07 +#define MODULE_DB_SUPPORT_END_ID 0x08 +#define MODULE_DB_STOP_START_ID 0x09 +#define MODULE_DB_STOP_END_ID 0x0A + +#define PERF_EVENTSIGNAL_START_ID 0x10 +#define PERF_EVENTSIGNAL_END_ID 0x11 +#define PERF_CALLBACK_START_ID 0x20 +#define PERF_CALLBACK_END_ID 0x21 +#define PERF_FUNCTION_START_ID 0x30 +#define PERF_FUNCTION_END_ID 0x31 +#define PERF_INMODULE_START_ID 0x40 +#define PERF_INMODULE_END_ID 0x41 +#define PERF_CROSSMODULE_START_ID 0x50 +#define PERF_CROSSMODULE_END_ID 0x51 + +// +// Declare bits for PcdPerformanceLibraryPropertyMask and +// also used as the Type parameter of LogPerformanceMeasurementEnabled(). +// +#define PERF_CORE_START_IMAGE 0x0002 +#define PERF_CORE_LOAD_IMAGE 0x0004 +#define PERF_CORE_DB_SUPPORT 0x0008 +#define PERF_CORE_DB_START 0x0010 +#define PERF_CORE_DB_STOP 0x0020 + +#define PERF_GENERAL_TYPE 0x0040 + +/** + Creates a record for the beginning of a performance measurement. + + Creates a record that contains the Handle, Token, and Module. + If TimeStamp is not zero, then TimeStamp is added to the record as the start time. + If TimeStamp is zero, then this function reads the current time stamp + and adds that time stamp value to the record as the start time. + + @param Handle Pointer to environment specific context used + to identify the component being measured. + @param Token Pointer to a Null-terminated ASCII string + that identifies the component being measured. + @param Module Pointer to a Null-terminated ASCII string + that identifies the module being measured. + @param TimeStamp 64-bit time stamp. + + @retval RETURN_SUCCESS The start of the measurement was recorded. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources to record the measurement. + @retval RETURN_DEVICE_ERROR A device error reading the time stamp. + +**/ +RETURN_STATUS +EFIAPI +StartPerformanceMeasurement ( + IN CONST VOID *Handle, OPTIONAL + IN CONST CHAR8 *Token, OPTIONAL + IN CONST CHAR8 *Module, OPTIONAL + IN UINT64 TimeStamp + ); + +/** + Fills in the end time of a performance measurement. + + Looks up the record that matches Handle, Token, and Module. + If the record can not be found then return RETURN_NOT_FOUND. + If the record is found and TimeStamp is not zero, + then TimeStamp is added to the record as the end time. + If the record is found and TimeStamp is zero, then this function reads + the current time stamp and adds that time stamp value to the record as the end time. + + @param Handle Pointer to environment specific context used + to identify the component being measured. + @param Token Pointer to a Null-terminated ASCII string + that identifies the component being measured. + @param Module Pointer to a Null-terminated ASCII string + that identifies the module being measured. + @param TimeStamp 64-bit time stamp. + + @retval RETURN_SUCCESS The end of the measurement was recorded. + @retval RETURN_NOT_FOUND The specified measurement record could not be found. + @retval RETURN_DEVICE_ERROR A device error reading the time stamp. + +**/ +RETURN_STATUS +EFIAPI +EndPerformanceMeasurement ( + IN CONST VOID *Handle, OPTIONAL + IN CONST CHAR8 *Token, OPTIONAL + IN CONST CHAR8 *Module, OPTIONAL + IN UINT64 TimeStamp + ); + +/** + Attempts to retrieve a performance measurement log entry from the performance measurement log. + It can also retrieve the log created by StartPerformanceMeasurementEx and EndPerformanceMeasurementEx, + and then eliminate the Identifier. + + Attempts to retrieve the performance log entry specified by LogEntryKey. If LogEntryKey is + zero on entry, then an attempt is made to retrieve the first entry from the performance log, + and the key for the second entry in the log is returned. If the performance log is empty, + then no entry is retrieved and zero is returned. If LogEntryKey is not zero, then the performance + log entry associated with LogEntryKey is retrieved, and the key for the next entry in the log is + returned. If LogEntryKey is the key for the last entry in the log, then the last log entry is + retrieved and an implementation specific non-zero key value that specifies the end of the performance + log is returned. If LogEntryKey is equal this implementation specific non-zero key value, then no entry + is retrieved and zero is returned. In the cases where a performance log entry can be returned, + the log entry is returned in Handle, Token, Module, StartTimeStamp, and EndTimeStamp. + If LogEntryKey is not a valid log entry key for the performance measurement log, then ASSERT(). + If Handle is NULL, then ASSERT(). + If Token is NULL, then ASSERT(). + If Module is NULL, then ASSERT(). + If StartTimeStamp is NULL, then ASSERT(). + If EndTimeStamp is NULL, then ASSERT(). + + @param LogEntryKey On entry, the key of the performance measurement log entry to retrieve. + 0, then the first performance measurement log entry is retrieved. + On exit, the key of the next performance lof entry entry. + @param Handle Pointer to environment specific context used to identify the component + being measured. + @param Token Pointer to a Null-terminated ASCII string that identifies the component + being measured. + @param Module Pointer to a Null-terminated ASCII string that identifies the module + being measured. + @param StartTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement + was started. + @param EndTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement + was ended. + + @return The key for the next performance log entry (in general case). + +**/ +UINTN +EFIAPI +GetPerformanceMeasurement ( + IN UINTN LogEntryKey, + OUT CONST VOID **Handle, + OUT CONST CHAR8 **Token, + OUT CONST CHAR8 **Module, + OUT UINT64 *StartTimeStamp, + OUT UINT64 *EndTimeStamp + ); + +/** + Creates a record for the beginning of a performance measurement. + + Creates a record that contains the Handle, Token, Module and Identifier. + If TimeStamp is not zero, then TimeStamp is added to the record as the start time. + If TimeStamp is zero, then this function reads the current time stamp + and adds that time stamp value to the record as the start time. + + @param Handle Pointer to environment specific context used + to identify the component being measured. + @param Token Pointer to a Null-terminated ASCII string + that identifies the component being measured. + @param Module Pointer to a Null-terminated ASCII string + that identifies the module being measured. + @param TimeStamp 64-bit time stamp. + @param Identifier 32-bit identifier. If the value is 0, the created record + is same as the one created by StartPerformanceMeasurement. + + @retval RETURN_SUCCESS The start of the measurement was recorded. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources to record the measurement. + @retval RETURN_DEVICE_ERROR A device error reading the time stamp. + +**/ +RETURN_STATUS +EFIAPI +StartPerformanceMeasurementEx ( + IN CONST VOID *Handle, OPTIONAL + IN CONST CHAR8 *Token, OPTIONAL + IN CONST CHAR8 *Module, OPTIONAL + IN UINT64 TimeStamp, + IN UINT32 Identifier + ); + +/** + Fills in the end time of a performance measurement. + + Looks up the record that matches Handle, Token and Module. + If the record can not be found then return RETURN_NOT_FOUND. + If the record is found and TimeStamp is not zero, + then TimeStamp is added to the record as the end time. + If the record is found and TimeStamp is zero, then this function reads + the current time stamp and adds that time stamp value to the record as the end time. + + @param Handle Pointer to environment specific context used + to identify the component being measured. + @param Token Pointer to a Null-terminated ASCII string + that identifies the component being measured. + @param Module Pointer to a Null-terminated ASCII string + that identifies the module being measured. + @param TimeStamp 64-bit time stamp. + @param Identifier 32-bit identifier. If the value is 0, the found record + is same as the one found by EndPerformanceMeasurement. + + @retval RETURN_SUCCESS The end of the measurement was recorded. + @retval RETURN_NOT_FOUND The specified measurement record could not be found. + @retval RETURN_DEVICE_ERROR A device error reading the time stamp. + +**/ +RETURN_STATUS +EFIAPI +EndPerformanceMeasurementEx ( + IN CONST VOID *Handle, OPTIONAL + IN CONST CHAR8 *Token, OPTIONAL + IN CONST CHAR8 *Module, OPTIONAL + IN UINT64 TimeStamp, + IN UINT32 Identifier + ); + +/** + Attempts to retrieve a performance measurement log entry from the performance measurement log. + It can also retrieve the log created by StartPerformanceMeasurement and EndPerformanceMeasurement, + and then assign the Identifier with 0. + + Attempts to retrieve the performance log entry specified by LogEntryKey. If LogEntryKey is + zero on entry, then an attempt is made to retrieve the first entry from the performance log, + and the key for the second entry in the log is returned. If the performance log is empty, + then no entry is retrieved and zero is returned. If LogEntryKey is not zero, then the performance + log entry associated with LogEntryKey is retrieved, and the key for the next entry in the log is + returned. If LogEntryKey is the key for the last entry in the log, then the last log entry is + retrieved and an implementation specific non-zero key value that specifies the end of the performance + log is returned. If LogEntryKey is equal this implementation specific non-zero key value, then no entry + is retrieved and zero is returned. In the cases where a performance log entry can be returned, + the log entry is returned in Handle, Token, Module, StartTimeStamp, EndTimeStamp and Identifier. + If LogEntryKey is not a valid log entry key for the performance measurement log, then ASSERT(). + If Handle is NULL, then ASSERT(). + If Token is NULL, then ASSERT(). + If Module is NULL, then ASSERT(). + If StartTimeStamp is NULL, then ASSERT(). + If EndTimeStamp is NULL, then ASSERT(). + If Identifier is NULL, then ASSERT(). + + @param LogEntryKey On entry, the key of the performance measurement log entry to retrieve. + 0, then the first performance measurement log entry is retrieved. + On exit, the key of the next performance of entry entry. + @param Handle Pointer to environment specific context used to identify the component + being measured. + @param Token Pointer to a Null-terminated ASCII string that identifies the component + being measured. + @param Module Pointer to a Null-terminated ASCII string that identifies the module + being measured. + @param StartTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement + was started. + @param EndTimeStamp Pointer to the 64-bit time stamp that was recorded when the measurement + was ended. + @param Identifier Pointer to the 32-bit identifier that was recorded. + + @return The key for the next performance log entry (in general case). + +**/ +UINTN +EFIAPI +GetPerformanceMeasurementEx ( + IN UINTN LogEntryKey, + OUT CONST VOID **Handle, + OUT CONST CHAR8 **Token, + OUT CONST CHAR8 **Module, + OUT UINT64 *StartTimeStamp, + OUT UINT64 *EndTimeStamp, + OUT UINT32 *Identifier + ); + +/** + Returns TRUE if the performance measurement macros are enabled. + + This function returns TRUE if the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of + PcdPerformanceLibraryPropertyMask is set. Otherwise FALSE is returned. + + @retval TRUE The PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of + PcdPerformanceLibraryPropertyMask is set. + @retval FALSE The PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of + PcdPerformanceLibraryPropertyMask is clear. + +**/ +BOOLEAN +EFIAPI +PerformanceMeasurementEnabled ( + VOID + ); + + +/** + Check whether the specified performance measurement can be logged. + + This function returns TRUE when the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set + and the Type disable bit in PcdPerformanceLibraryPropertyMask is not set. + + @param Type - Type of the performance measurement entry. + + @retval TRUE The performance measurement can be logged. + @retval FALSE The performance measurement can NOT be logged. + +**/ +BOOLEAN +EFIAPI +LogPerformanceMeasurementEnabled ( + IN CONST UINTN Type + ); + +/** + Create performance record with event description. + + @param CallerIdentifier - Image handle or pointer to caller ID GUID + @param Guid - Pointer to a GUID. + Used for event signal perf and callback perf to cache the event guid. + @param String - Pointer to a string describing the measurement + @param Address - Pointer to a location in memory relevant to the measurement. + @param Identifier - Performance identifier describing the type of measurement. + + @retval RETURN_SUCCESS - Successfully created performance record + @retval RETURN_OUT_OF_RESOURCES - Ran out of space to store the records + @retval RETURN_INVALID_PARAMETER - Invalid parameter passed to function - NULL + pointer or invalid Identifier. + +**/ +RETURN_STATUS +EFIAPI +LogPerformanceMeasurement ( + IN CONST VOID *CallerIdentifier, OPTIONAL + IN CONST VOID *Guid, OPTIONAL + IN CONST CHAR8 *String, OPTIONAL + IN UINT64 Address, OPTIONAL + IN UINT32 Identifier + ); + +/** + Begin Macro to measure the performance of StartImage in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT1(dsiable PERF_CORE_START_IMAGE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_START_IMAGE_BEGIN(ModuleHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the performance of StartImage in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT1 (dsiable PERF_CORE_START_IMAGE)of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_START_IMAGE_END(ModuleHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the performance of LoadImage in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT2 (dsiable PERF_CORE_LOAD_IAMGE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_LOAD_IMAGE_BEGIN(ModuleHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the performance of LoadImage in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT2 (dsiable PERF_CORE_LOAD_IAMGE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_LOAD_IMAGE_END(ModuleHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_END_ID); \ + } \ + } while (FALSE) + +/** + Start Macro to measure the performance of DriverBinding Support in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT3 (dsiable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_SUPPORT_BEGIN(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the performance of DriverBinding Support in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT3 (dsiable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_SUPPORT_END(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the performance of DriverBinding Start in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT4 (dsiable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_START_BEGIN(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the performance of DriverBinding Start in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT4 (dsiable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_START_END(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_END_ID); \ + } \ + } while (FALSE) + +/** + Start Macro to measure the performance of DriverBinding Stop in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT5 (dsiable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_STOP_BEGIN(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the performance of DriverBinding Stop in core. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT5 (dsiable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_DRIVER_BINDING_STOP_END(ModuleHandle, ControllerHandle) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \ + LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_END_ID); \ + } \ + } while (FALSE) + +/** + Macro to measure the time from power-on to this macro execution. + It can be used to log a meaningful thing which happens at a time point. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_EVENT(EventString) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, EventString , 0, PERF_EVENT_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the perofrmance of evnent signal behavior in any module. + The event guid will be passed with this macro. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_EVENT_SIGNAL_BEGIN(EventGuid) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the perofrmance of evnent signal behavior in any module. + The event guid will be passed with this macro. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_EVENT_SIGNAL_END(EventGuid) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the perofrmance of a callback function in any module. + The event guid which trigger the callback function will be passed with this macro. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_CALLBACK_BEGIN(TriggerGuid) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the perofrmance of a callback function in any module. + The event guid which trigger the callback function will be passed with this macro. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_CALLBACK_END(TriggerGuid) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the perofrmance of a general function in any module. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_FUNCTION_BEGIN() \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the perofrmance of a general function in any module. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_FUNCTION_END() \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the perofrmance of a behavior within one module. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_INMODULE_BEGIN(MeasurementString) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the perofrmance of a behavior within one module. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_INMODULE_END(MeasurementString) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_END_ID); \ + } \ + } while (FALSE) + +/** + Begin Macro to measure the perofrmance of a behavior in different modules. + Such as the performance of PEI phase, DXE phase, BDS phase. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_CROSSMODULE_BEGIN(MeasurementString) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_START_ID); \ + } \ + } while (FALSE) + +/** + End Macro to measure the perofrmance of a behavior in different modules. + Such as the performance of PEI phase, DXE phase, BDS phase. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set. + then LogPerformanceMeasurement() is called. + +**/ +#define PERF_CROSSMODULE_END(MeasurementString) \ + do { \ + if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \ + LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_END_ID); \ + } \ + } while (FALSE) + +/** + Macro that calls EndPerformanceMeasurement(). + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then EndPerformanceMeasurement() is called. + +**/ +#define PERF_END(Handle, Token, Module, TimeStamp) \ + do { \ + if (PerformanceMeasurementEnabled ()) { \ + EndPerformanceMeasurement (Handle, Token, Module, TimeStamp); \ + } \ + } while (FALSE) + +/** + Macro that calls StartPerformanceMeasurement(). + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then StartPerformanceMeasurement() is called. + +**/ +#define PERF_START(Handle, Token, Module, TimeStamp) \ + do { \ + if (PerformanceMeasurementEnabled ()) { \ + StartPerformanceMeasurement (Handle, Token, Module, TimeStamp); \ + } \ + } while (FALSE) + +/** + Macro that calls EndPerformanceMeasurementEx(). + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then EndPerformanceMeasurementEx() is called. + +**/ +#define PERF_END_EX(Handle, Token, Module, TimeStamp, Identifier) \ + do { \ + if (PerformanceMeasurementEnabled ()) { \ + EndPerformanceMeasurementEx (Handle, Token, Module, TimeStamp, Identifier); \ + } \ + } while (FALSE) + +/** + Macro that calls StartPerformanceMeasurementEx(). + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then StartPerformanceMeasurementEx() is called. + +**/ +#define PERF_START_EX(Handle, Token, Module, TimeStamp, Identifier) \ + do { \ + if (PerformanceMeasurementEnabled ()) { \ + StartPerformanceMeasurementEx (Handle, Token, Module, TimeStamp, Identifier); \ + } \ + } while (FALSE) + +/** + Macro that marks the beginning of performance measurement source code. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then this macro marks the beginning of source code that is included in a module. + Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module. + +**/ +#define PERF_CODE_BEGIN() do { if (PerformanceMeasurementEnabled ()) { UINT8 __PerformanceCodeLocal + +/** + Macro that marks the end of performance measurement source code. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then this macro marks the end of source code that is included in a module. + Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module. + +**/ +#define PERF_CODE_END() __PerformanceCodeLocal = 0; __PerformanceCodeLocal++; } } while (FALSE) + +/** + Macro that declares a section of performance measurement source code. + + If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set, + then the source code specified by Expression is included in a module. + Otherwise, the source specified by Expression is not included in a module. + + @param Expression Performance measurement source code to include in a module. + +**/ +#define PERF_CODE(Expression) \ + PERF_CODE_BEGIN (); \ + Expression \ + PERF_CODE_END () + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PostCodeLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PostCodeLib.h new file mode 100644 index 0000000000..df43c06ad8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PostCodeLib.h @@ -0,0 +1,144 @@ +/** @file + Provides services to send progress/error codes to a POST card. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __POST_CODE_LIB_H__ +#define __POST_CODE_LIB_H__ + +#define POST_CODE_PROPERTY_POST_CODE_ENABLED 0x00000008 +#define POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED 0x00000010 + +/** + Sends a 32-bit value to a POST card. + + Sends the 32-bit value specified by Value to a POST card, and returns Value. + Some implementations of this library function may perform I/O operations + directly to a POST card device. Other implementations may send Value to + ReportStatusCode(), and the status code reporting mechanism will eventually + display the 32-bit value on the status reporting device. + + PostCode() must actively prevent recursion. If PostCode() is called while + processing another Post Code Library function, then + PostCode() must return Value immediately. + + @param Value The 32-bit value to write to the POST card. + + @return The 32-bit value to write to the POST card. + +**/ +UINT32 +EFIAPI +PostCode ( + IN UINT32 Value + ); + + +/** + Sends a 32-bit value to a POST and associated ASCII string. + + Sends the 32-bit value specified by Value to a POST card, and returns Value. + If Description is not NULL, then the ASCII string specified by Description is + also passed to the handler that displays the POST card value. Some + implementations of this library function may perform I/O operations directly + to a POST card device. Other implementations may send Value to ReportStatusCode(), + and the status code reporting mechanism will eventually display the 32-bit + value on the status reporting device. + + PostCodeWithDescription()must actively prevent recursion. If + PostCodeWithDescription() is called while processing another any other Post + Code Library function, then PostCodeWithDescription() must return Value + immediately. + + @param Value The 32-bit value to write to the POST card. + @param Description Pointer to an ASCII string that is a description of the + POST code value. This is an optional parameter that may + be NULL. + + @return The 32-bit value to write to the POST card. + +**/ +UINT32 +EFIAPI +PostCodeWithDescription ( + IN UINT32 Value, + IN CONST CHAR8 *Description OPTIONAL + ); + + +/** + Returns TRUE if POST Codes are enabled. + + This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_ENABLED + bit of PcdPostCodePropertyMask is set. Otherwise FALSE is returned. + + @retval TRUE The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of + PcdPostCodeProperyMask is set. + @retval FALSE The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of + PcdPostCodeProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +PostCodeEnabled ( + VOID + ); + + +/** + Returns TRUE if POST code descriptions are enabled. + + This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED + bit of PcdPostCodePropertyMask is set. Otherwise FALSE is returned. + + @retval TRUE The POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED bit of + PcdPostCodeProperyMask is set. + @retval FALSE The POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED bit of + PcdPostCodeProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +PostCodeDescriptionEnabled ( + VOID + ); + + +/** + Sends a 32-bit value to a POST card. + + If POST codes are enabled in PcdPostCodeProperyMask, then call PostCode() + passing in Value. Value is returned. + + @param Value The 32-bit value to write to the POST card. + + @return Value The 32-bit value to write to the POST card. + +**/ +#define POST_CODE(Value) PostCodeEnabled() ? PostCode(Value) : Value + +/** + Sends a 32-bit value to a POST and associated ASCII string. + + If POST codes and POST code descriptions are enabled in + PcdPostCodeProperyMask, then call PostCodeWithDescription() passing in + Value and Description. If only POST codes are enabled, then call PostCode() + passing in Value. Value is returned. + + @param Value The 32-bit value to write to the POST card. + @param Description Pointer to an ASCII string that is a description of the + POST code value. + + @return Value The 32-bit value to write to the POST card. +**/ +#define POST_CODE_WITH_DESCRIPTION(Value,Description) \ + PostCodeEnabled() ? \ + (PostCodeDescriptionEnabled() ? \ + PostCodeWithDescription(Value,Description) : \ + PostCode(Value)) : \ + Value + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PrintLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PrintLib.h new file mode 100644 index 0000000000..59cd89cc53 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/PrintLib.h @@ -0,0 +1,935 @@ +/** @file + Provides services to print a formatted string to a buffer. All combinations of + Unicode and ASCII strings are supported. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + The Print Library functions provide a simple means to produce formatted output + strings. Many of the output functions use a format string to describe how to + format the output of variable arguments. The format string consists of normal + text and argument descriptors. There are no restrictions for how the normal + text and argument descriptors can be mixed. The following end of line(EOL) + translations must be performed on the contents of the format string: + + - '\\r' is translated to '\\r' + - '\\r\\n' is translated to '\\r\\n' + - '\\n' is translated to '\\r\\n' + - '\\n\\r' is translated to '\\r\\n' + + This does not follow the ANSI C standard for sprint(). The format of argument + descriptors is described below. The ANSI C standard for sprint() has been + followed for some of the format types, and has not been followed for others. + The exceptions are noted below. + + %[flags][width][.precision]type + + [flags]: + - - + - The field is left justified. If not flag is not specified, then the + field is right justified. + - space + - Prefix a space character to a number. Only valid for types X, x, and d. + - + + - Prefix a plus character to a number. Only valid for types X, x, and d. + If both space and + are specified, then space is ignored. + - 0 + - Pad with 0 characters to the left of a number. Only valid for types + X, x, and d. + - , + - Place a comma every 3rd digit of the number. Only valid for type d. + If 0 is also specified, then 0 is ignored. + - L, l + - The number being printed is size UINT64. Only valid for types X, x, and d. + If this flag is not specified, then the number being printed is size int. + - NOTE: All invalid flags are ignored. + + [width]: + + - * + - The width of the field is specified by a UINTN argument in the + argument list. + - number + - The number specified as a decimal value represents the width of + the field. + - NOTE: If [width] is not specified, then a field width of 0 is assumed. + + [.precision]: + + - * + - The precision of the field is specified by a UINTN argument in the + argument list. + - number + - The number specified as a decimal value represents the precision of + the field. + - NOTE: If [.precision] is not specified, then a precision of 0 is assumed. + + type: + + - % + - Print a %%. + - c + - The argument is a Unicode character. ASCII characters can be printed + using this type too by making sure bits 8..15 of the argument are set to 0. + - x + - The argument is an unsigned hexadecimal number. The characters used are 0..9 and + A..F. If the flag 'L' is not specified, then the argument is assumed + to be size int. This does not follow ANSI C. + - X + - The argument is an unsigned hexadecimal number and the number is padded with + zeros. This is equivalent to a format string of "0x". If the flag + 'L' is not specified, then the argument is assumed to be size int. + This does not follow ANSI C. + - d + - The argument is a signed decimal number. If the flag 'L' is not specified, + then the argument is assumed to be size int. + - u + - The argument is a unsigned decimal number. If the flag 'L' is not specified, + then the argument is assumed to be size int. + - p + - The argument is a pointer that is a (VOID *), and it is printed as an + unsigned hexadecimal number The characters used are 0..9 and A..F. + - a + - The argument is a pointer to an ASCII string. + This does not follow ANSI C. + - S, s + - The argument is a pointer to a Unicode string. + This does not follow ANSI C. + - g + - The argument is a pointer to a GUID structure. The GUID is printed + in the format XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX. + This does not follow ANSI C. + - t + - The argument is a pointer to an EFI_TIME structure. The time and + date are printed in the format "mm/dd/yyyy hh:mm" where mm is the + month zero padded, dd is the day zero padded, yyyy is the year zero + padded, hh is the hour zero padded, and mm is minutes zero padded. + This does not follow ANSI C. + - r + - The argument is a RETURN_STATUS value. This value is converted to + a string following the table below. This does not follow ANSI C. + - RETURN_SUCCESS + - "Success" + - RETURN_LOAD_ERROR + - "Load Error" + - RETURN_INVALID_PARAMETER + - "Invalid Parameter" + - RETURN_UNSUPPORTED + - "Unsupported" + - RETURN_BAD_BUFFER_SIZE + - "Bad Buffer Size" + - RETURN_BUFFER_TOO_SMALL + - "Buffer Too Small" + - RETURN_NOT_READY + - "Not Ready" + - RETURN_DEVICE_ERROR + - "Device Error" + - RETURN_WRITE_PROTECTED + - "Write Protected" + - RETURN_OUT_OF_RESOURCES + - "Out of Resources" + - RETURN_VOLUME_CORRUPTED + - "Volume Corrupt" + - RETURN_VOLUME_FULL + - "Volume Full" + - RETURN_NO_MEDIA + - "No Media" + - RETURN_MEDIA_CHANGED + - "Media changed" + - RETURN_NOT_FOUND + - "Not Found" + - RETURN_ACCESS_DENIED + - "Access Denied" + - RETURN_NO_RESPONSE + - "No Response" + - RETURN_NO_MAPPING + - "No mapping" + - RETURN_TIMEOUT + - "Time out" + - RETURN_NOT_STARTED + - "Not started" + - RETURN_ALREADY_STARTED + - "Already started" + - RETURN_ABORTED + - "Aborted" + - RETURN_ICMP_ERROR + - "ICMP Error" + - RETURN_TFTP_ERROR + - "TFTP Error" + - RETURN_PROTOCOL_ERROR + - "Protocol Error" + - RETURN_WARN_UNKNOWN_GLYPH + - "Warning Unknown Glyph" + - RETURN_WARN_DELETE_FAILURE + - "Warning Delete Failure" + - RETURN_WARN_WRITE_FAILURE + - "Warning Write Failure" + - RETURN_WARN_BUFFER_TOO_SMALL + - "Warning Buffer Too Small" + +**/ + +#ifndef __PRINT_LIB_H__ +#define __PRINT_LIB_H__ + +/// +/// Define the maximum number of characters that are required to +/// encode with a NULL terminator a decimal, hexadecimal, GUID, +/// or TIME value. +/// +/// Maximum Length Decimal String = 28 +/// "-9,223,372,036,854,775,808" +/// Maximum Length Hexadecimal String = 17 +/// "FFFFFFFFFFFFFFFF" +/// Maximum Length GUID = 37 +/// "00000000-0000-0000-0000-000000000000" +/// Maximum Length TIME = 18 +/// "12/12/2006 12:12" +/// +#define MAXIMUM_VALUE_CHARACTERS 38 + +/// +/// Flags bitmask values use in UnicodeValueToString() and +/// AsciiValueToString() +/// +#define LEFT_JUSTIFY 0x01 +#define COMMA_TYPE 0x08 +#define PREFIX_ZERO 0x20 +#define RADIX_HEX 0x80 + +/** + Produces a Null-terminated Unicode string in an output buffer based on + a Null-terminated Unicode format string and a VA_LIST argument list. + + This function is similar as vsnprintf_s defined in C11. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on the + contents of the format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param Marker VA_LIST marker for the variable argument list. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeVSPrint ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + IN VA_LIST Marker + ); + +/** + Produces a Null-terminated Unicode string in an output buffer based on + a Null-terminated Unicode format string and a BASE_LIST argument list. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on the + contents of the format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param Marker BASE_LIST marker for the variable argument list. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeBSPrint ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + IN BASE_LIST Marker + ); + +/** + Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated + Unicode format string and variable argument list. + + This function is similar as snprintf_s defined in C11. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list based on the contents of the format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then the output buffer is unmodified and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param ... Variable argument list whose contents are accessed based on the + format string specified by FormatString. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeSPrint ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + ... + ); + +/** + Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated + ASCII format string and a VA_LIST argument list. + + This function is similar as vsnprintf_s defined in C11. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on the + contents of the format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param Marker VA_LIST marker for the variable argument list. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeVSPrintAsciiFormat ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + IN VA_LIST Marker + ); + +/** + Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated + ASCII format string and a BASE_LIST argument list. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on the + contents of the format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param Marker BASE_LIST marker for the variable argument list. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeBSPrintAsciiFormat ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + IN BASE_LIST Marker + ); + +/** + Produces a Null-terminated Unicode string in an output buffer based on a Null-terminated + ASCII format string and variable argument list. + + This function is similar as snprintf_s defined in C11. + + Produces a Null-terminated Unicode string in the output buffer specified by StartOfBuffer + and BufferSize. + The Unicode string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list based on the contents of the + format string. + The number of Unicode characters in the produced output buffer is returned not including + the Null-terminator. + + If StartOfBuffer is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 1 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 1 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and BufferSize > + (PcdMaximumUnicodeStringLength * sizeof (CHAR16) + 1), then ASSERT(). Also, the output + buffer is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0 or 1, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + Unicode string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param ... Variable argument list whose contents are accessed based on the + format string specified by FormatString. + + @return The number of Unicode characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +UnicodeSPrintAsciiFormat ( + OUT CHAR16 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + ... + ); + +/** + Converts a decimal value to a Null-terminated Unicode string. + + Converts the decimal number specified by Value to a Null-terminated Unicode + string specified by Buffer containing at most Width characters. No padding of + spaces is ever performed. If Width is 0 then a width of + MAXIMUM_VALUE_CHARACTERS is assumed. If the conversion contains more than + Width characters, then only the first Width characters are placed in Buffer. + Additional conversion parameters are specified in Flags. + + The Flags bit LEFT_JUSTIFY is always ignored. + All conversions are left justified in Buffer. + If Width is 0, PREFIX_ZERO is ignored in Flags. + If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and + commas are inserted every 3rd digit starting from the right. + If RADIX_HEX is set in Flags, then the output buffer will be formatted in + hexadecimal format. + If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in + Buffer is a '-'. + If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, then + Buffer is padded with '0' characters so the combination of the optional '-' + sign character, '0' characters, digit characters for Value, and the + Null-terminator add up to Width characters. + + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + If an error would be returned, then the function will also ASSERT(). + + @param Buffer The pointer to the output buffer for the produced + Null-terminated Unicode string. + @param BufferSize The size of Buffer in bytes, including the + Null-terminator. + @param Flags The bitmask of flags that specify left justification, + zero pad, and commas. + @param Value The 64-bit signed value to convert to a string. + @param Width The maximum number of Unicode characters to place in + Buffer, not including the Null-terminator. + + @retval RETURN_SUCCESS The decimal value is converted. + @retval RETURN_BUFFER_TOO_SMALL If BufferSize cannot hold the converted + value. + @retval RETURN_INVALID_PARAMETER If Buffer is NULL. + If PcdMaximumUnicodeStringLength is not + zero, and BufferSize is greater than + (PcdMaximumUnicodeStringLength * + sizeof (CHAR16) + 1). + If unsupported bits are set in Flags. + If both COMMA_TYPE and RADIX_HEX are set in + Flags. + If Width >= MAXIMUM_VALUE_CHARACTERS. + +**/ +RETURN_STATUS +EFIAPI +UnicodeValueToStringS ( + IN OUT CHAR16 *Buffer, + IN UINTN BufferSize, + IN UINTN Flags, + IN INT64 Value, + IN UINTN Width + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + ASCII format string and a VA_LIST argument list. + + This function is similar as vsnprintf_s defined in C11. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on + the contents of the format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param Marker VA_LIST marker for the variable argument list. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiVSPrint ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + IN VA_LIST Marker + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + ASCII format string and a BASE_LIST argument list. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on + the contents of the format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param Marker BASE_LIST marker for the variable argument list. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiBSPrint ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + IN BASE_LIST Marker + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + ASCII format string and variable argument list. + + This function is similar as snprintf_s defined in C11. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list based on the contents of the + format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more than + PcdMaximumAsciiStringLength Ascii characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated ASCII format string. + @param ... Variable argument list whose contents are accessed based on the + format string specified by FormatString. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiSPrint ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR8 *FormatString, + ... + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + Unicode format string and a VA_LIST argument list. + + This function is similar as vsnprintf_s defined in C11. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on + the contents of the format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param Marker VA_LIST marker for the variable argument list. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiVSPrintUnicodeFormat ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + IN VA_LIST Marker + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + Unicode format string and a BASE_LIST argument list. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list specified by Marker based on + the contents of the format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param Marker BASE_LIST marker for the variable argument list. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiBSPrintUnicodeFormat ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + IN BASE_LIST Marker + ); + +/** + Produces a Null-terminated ASCII string in an output buffer based on a Null-terminated + Unicode format string and variable argument list. + + This function is similar as snprintf_s defined in C11. + + Produces a Null-terminated ASCII string in the output buffer specified by StartOfBuffer + and BufferSize. + The ASCII string is produced by parsing the format string specified by FormatString. + Arguments are pulled from the variable argument list based on the contents of the + format string. + The number of ASCII characters in the produced output buffer is returned not including + the Null-terminator. + + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If BufferSize > 0 and StartOfBuffer is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If BufferSize > 0 and FormatString is NULL, then ASSERT(). Also, the output buffer is + unmodified and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and BufferSize > + (PcdMaximumAsciiStringLength * sizeof (CHAR8)), then ASSERT(). Also, the output buffer + is unmodified and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more than + PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then + ASSERT(). Also, the output buffer is unmodified and 0 is returned. + + If BufferSize is 0, then no output buffer is produced and 0 is returned. + + @param StartOfBuffer A pointer to the output buffer for the produced Null-terminated + ASCII string. + @param BufferSize The size, in bytes, of the output buffer specified by StartOfBuffer. + @param FormatString A Null-terminated Unicode format string. + @param ... Variable argument list whose contents are accessed based on the + format string specified by FormatString. + + @return The number of ASCII characters in the produced output buffer not including the + Null-terminator. + +**/ +UINTN +EFIAPI +AsciiSPrintUnicodeFormat ( + OUT CHAR8 *StartOfBuffer, + IN UINTN BufferSize, + IN CONST CHAR16 *FormatString, + ... + ); + + +/** + Converts a decimal value to a Null-terminated Ascii string. + + Converts the decimal number specified by Value to a Null-terminated Ascii + string specified by Buffer containing at most Width characters. No padding of + spaces is ever performed. If Width is 0 then a width of + MAXIMUM_VALUE_CHARACTERS is assumed. If the conversion contains more than + Width characters, then only the first Width characters are placed in Buffer. + Additional conversion parameters are specified in Flags. + + The Flags bit LEFT_JUSTIFY is always ignored. + All conversions are left justified in Buffer. + If Width is 0, PREFIX_ZERO is ignored in Flags. + If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and + commas are inserted every 3rd digit starting from the right. + If RADIX_HEX is set in Flags, then the output buffer will be formatted in + hexadecimal format. + If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in + Buffer is a '-'. + If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, then + Buffer is padded with '0' characters so the combination of the optional '-' + sign character, '0' characters, digit characters for Value, and the + Null-terminator add up to Width characters. + + If an error would be returned, then the function will ASSERT(). + + @param Buffer The pointer to the output buffer for the produced + Null-terminated Ascii string. + @param BufferSize The size of Buffer in bytes, including the + Null-terminator. + @param Flags The bitmask of flags that specify left justification, + zero pad, and commas. + @param Value The 64-bit signed value to convert to a string. + @param Width The maximum number of Ascii characters to place in + Buffer, not including the Null-terminator. + + @retval RETURN_SUCCESS The decimal value is converted. + @retval RETURN_BUFFER_TOO_SMALL If BufferSize cannot hold the converted + value. + @retval RETURN_INVALID_PARAMETER If Buffer is NULL. + If PcdMaximumAsciiStringLength is not + zero, and BufferSize is greater than + PcdMaximumAsciiStringLength. + If unsupported bits are set in Flags. + If both COMMA_TYPE and RADIX_HEX are set in + Flags. + If Width >= MAXIMUM_VALUE_CHARACTERS. + +**/ +RETURN_STATUS +EFIAPI +AsciiValueToStringS ( + IN OUT CHAR8 *Buffer, + IN UINTN BufferSize, + IN UINTN Flags, + IN INT64 Value, + IN UINTN Width + ); + +/** + Returns the number of characters that would be produced by if the formatted + output were produced not including the Null-terminator. + + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + If FormatString is NULL, then ASSERT() and 0 is returned. + If PcdMaximumUnicodeStringLength is not zero, and FormatString contains more + than PcdMaximumUnicodeStringLength Unicode characters not including the + Null-terminator, then ASSERT() and 0 is returned. + + @param[in] FormatString A Null-terminated Unicode format string. + @param[in] Marker VA_LIST marker for the variable argument list. + + @return The number of characters that would be produced, not including the + Null-terminator. +**/ +UINTN +EFIAPI +SPrintLength ( + IN CONST CHAR16 *FormatString, + IN VA_LIST Marker + ); + +/** + Returns the number of characters that would be produced by if the formatted + output were produced not including the Null-terminator. + + If FormatString is NULL, then ASSERT() and 0 is returned. + If PcdMaximumAsciiStringLength is not zero, and FormatString contains more + than PcdMaximumAsciiStringLength Ascii characters not including the + Null-terminator, then ASSERT() and 0 is returned. + + @param[in] FormatString A Null-terminated ASCII format string. + @param[in] Marker VA_LIST marker for the variable argument list. + + @return The number of characters that would be produced, not including the + Null-terminator. +**/ +UINTN +EFIAPI +SPrintLengthAsciiFormat ( + IN CONST CHAR8 *FormatString, + IN VA_LIST Marker + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RegisterFilterLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RegisterFilterLib.h new file mode 100644 index 0000000000..5c28715a46 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RegisterFilterLib.h @@ -0,0 +1,243 @@ +/** @file + Public include file for the Port IO/MMIO/MSR RegisterFilterLib. + +Copyright (c) 2021, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef REGISTER_FILTER_LIB_H_ +#define REGISTER_FILTER_LIB_H_ + +typedef enum { + FilterWidth8, + FilterWidth16, + FilterWidth32, + FilterWidth64 +} FILTER_IO_WIDTH; + +/** + Filter IO read operation before read IO port. + It is used to filter IO read operation. + + It will return the flag to decide whether require read real IO port. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The destination buffer to store the results. + + @retval TRUE Need to excute the IO read. + @retval FALSE Skip the IO read. + +**/ +BOOLEAN +EFIAPI +FilterBeforeIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN OUT VOID *Buffer + ); + +/** + Trace IO read operation after read IO port. + It is used to trace IO operation. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +VOID +EFIAPI +FilterAfterIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); +/** + Filter IO Write operation before wirte IO port. + It is used to filter IO operation. + + It will return the flag to decide whether require read write IO port. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite data. + + @retval TRUE Need to excute the IO write. + @retval FALSE Skip the IO write. + +**/ +BOOLEAN +EFIAPI +FilterBeforeIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + + /** + Trace IO Write operation after wirte IO port. + It is used to trace IO operation. + + @param[in] Width Signifies the width of the I/O operation. + @param[in] Address The base address of the I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite data. + +**/ +VOID +EFIAPI +FilterAfterIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter memory IO before Read operation. + + It will return the flag to decide whether require read real MMIO. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the memory I/O operation. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The destination buffer to store the results. + + @retval TRUE Need to excute the MMIO read. + @retval FALSE Skip the MMIO read. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMmIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN OUT VOID *Buffer + ); + +/** + Tracer memory IO after read operation + + @param[in] Width Signifies the width of the memory I/O operation. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The destination buffer to store the results. + +**/ +VOID +EFIAPI +FilterAfterMmIoRead ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter memory IO before write operation + + It will return the flag to decide whether require wirte real MMIO. + It can be used for emulation environment. + + @param[in] Width Signifies the width of the memory I/O operation. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite data. + + @retval TRUE Need to excute the MMIO write. + @retval FALSE Skip the MMIO write. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMmIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Tracer memory IO after write operation + + @param[in] Width Signifies the width of the memory I/O operation. + @param[in] Address The base address of the memory I/O operation. + @param[in] Buffer The source buffer from which to BeforeWrite data. + +**/ +VOID +EFIAPI +FilterAfterMmIoWrite ( + IN FILTER_IO_WIDTH Width, + IN UINTN Address, + IN VOID *Buffer + ); + +/** + Filter MSR before read operation. + + It will return the flag to decide whether require read real MSR. + It can be used for emulation environment. + + @param Index The 8-bit Machine Specific Register index to BeforeWrite. + @param Value The 64-bit value to BeforeRead from the Machine Specific Register. + + @retval TRUE Need to excute the MSR read. + @retval FALSE Skip the MSR read. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMsrRead ( + IN UINT32 Index, + IN OUT UINT64 *Value + ); + +/** + Trace MSR after read operation + + @param Index The 8-bit Machine Specific Register index to BeforeWrite. + @param Value The 64-bit value to BeforeRead from the Machine Specific Register. + +**/ +VOID +EFIAPI +FilterAfterMsrRead ( + IN UINT32 Index, + IN UINT64 *Value + ); + +/** + Filter MSR before write operation + + It will return the flag to decide whether require write real MSR. + It can be used for emulation environment. + + @param Index The 8-bit Machine Specific Register index to BeforeWrite. + @param Value The 64-bit value to BeforeWrite to the Machine Specific Register. + + @retval TRUE Need to excute the MSR write. + @retval FALSE Skip the MSR write. + +**/ +BOOLEAN +EFIAPI +FilterBeforeMsrWrite ( + IN UINT32 Index, + IN UINT64 *Value + ); + +/** + Trace MSR after write operation + + @param Index The 8-bit Machine Specific Register index to BeforeWrite. + @param Value The 64-bit value to BeforeWrite to the Machine Specific Register. + +**/ +VOID +EFIAPI +FilterAfterMsrWrite ( + IN UINT32 Index, + IN UINT64 *Value + ); + +#endif // REGISTER_FILTER_LIB_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ReportStatusCodeLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ReportStatusCodeLib.h new file mode 100644 index 0000000000..0b77d78a04 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ReportStatusCodeLib.h @@ -0,0 +1,486 @@ +/** @file + Provides services to log status code records. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __REPORT_STATUS_CODE_LIB_H__ +#define __REPORT_STATUS_CODE_LIB_H__ + +#include +#include +#include + +// +// Declare bits for PcdReportStatusCodePropertyMask +// +#define REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED 0x00000001 +#define REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED 0x00000002 +#define REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED 0x00000004 + +/** + Converts a status code to an 8-bit POST code value. + + Converts the status code specified by CodeType and Value to an 8-bit POST code + and returns the 8-bit POST code in PostCode. If CodeType is an + EFI_PROGRESS_CODE or CodeType is an EFI_ERROR_CODE, then bits 0..4 of PostCode + are set to bits 16..20 of Value, and bits 5..7 of PostCode are set to bits + 24..26 of Value., and TRUE is returned. Otherwise, FALSE is returned. + + If PostCode is NULL, then ASSERT(). + + @param CodeType The type of status code being converted. + @param Value The status code value being converted. + @param PostCode A pointer to the 8-bit POST code value to return. + + @retval TRUE The status code specified by CodeType and Value was converted + to an 8-bit POST code and returned in PostCode. + @retval FALSE The status code specified by CodeType and Value could not be + converted to an 8-bit POST code value. + +**/ +BOOLEAN +EFIAPI +CodeTypeToPostCode ( + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + OUT UINT8 *PostCode + ); + + +/** + Extracts ASSERT() information from a status code structure. + + Converts the status code specified by CodeType, Value, and Data to the ASSERT() + arguments specified by Filename, Description, and LineNumber. If CodeType is + an EFI_ERROR_CODE, and CodeType has a severity of EFI_ERROR_UNRECOVERED, and + Value has an operation mask of EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, extract + Filename, Description, and LineNumber from the optional data area of the + status code buffer specified by Data. The optional data area of Data contains + a Null-terminated ASCII string for the FileName, followed by a Null-terminated + ASCII string for the Description, followed by a 32-bit LineNumber. If the + ASSERT() information could be extracted from Data, then return TRUE. + Otherwise, FALSE is returned. + + If Data is NULL, then ASSERT(). + If Filename is NULL, then ASSERT(). + If Description is NULL, then ASSERT(). + If LineNumber is NULL, then ASSERT(). + + @param CodeType The type of status code being converted. + @param Value The status code value being converted. + @param Data The pointer to status code data buffer. + @param Filename The pointer to the source file name that generated the ASSERT(). + @param Description The pointer to the description of the ASSERT(). + @param LineNumber The pointer to source line number that generated the ASSERT(). + + @retval TRUE The status code specified by CodeType, Value, and Data was + converted ASSERT() arguments specified by Filename, Description, + and LineNumber. + @retval FALSE The status code specified by CodeType, Value, and Data could + not be converted to ASSERT() arguments. + +**/ +BOOLEAN +EFIAPI +ReportStatusCodeExtractAssertInfo ( + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN CONST EFI_STATUS_CODE_DATA *Data, + OUT CHAR8 **Filename, + OUT CHAR8 **Description, + OUT UINT32 *LineNumber + ); + + +/** + Extracts DEBUG() information from a status code structure. + + Converts the status code specified by Data to the DEBUG() arguments specified + by ErrorLevel, Marker, and Format. If type GUID in Data is + EFI_STATUS_CODE_DATA_TYPE_DEBUG_GUID, then extract ErrorLevel, Marker, and + Format from the optional data area of the status code buffer specified by Data. + The optional data area of Data contains a 32-bit ErrorLevel followed by Marker + which is 12 UINTN parameters, followed by a Null-terminated ASCII string for + the Format. If the DEBUG() information could be extracted from Data, then + return TRUE. Otherwise, FALSE is returned. + + If Data is NULL, then ASSERT(). + If ErrorLevel is NULL, then ASSERT(). + If Marker is NULL, then ASSERT(). + If Format is NULL, then ASSERT(). + + @param Data The pointer to status code data buffer. + @param ErrorLevel The pointer to error level mask for a debug message. + @param Marker The pointer to the variable argument list associated with Format. + @param Format The pointer to a Null-terminated ASCII format string of a + debug message. + + @retval TRUE The status code specified by Data was converted DEBUG() arguments + specified by ErrorLevel, Marker, and Format. + @retval FALSE The status code specified by Data could not be converted to + DEBUG() arguments. + +**/ +BOOLEAN +EFIAPI +ReportStatusCodeExtractDebugInfo ( + IN CONST EFI_STATUS_CODE_DATA *Data, + OUT UINT32 *ErrorLevel, + OUT BASE_LIST *Marker, + OUT CHAR8 **Format + ); + + +/** + Reports a status code. + + Reports the status code specified by the parameters Type and Value. Status + code also require an instance, caller ID, and extended data. This function + passed in a zero instance, NULL extended data, and a caller ID of + gEfiCallerIdGuid, which is the GUID for the module. + + ReportStatusCode()must actively prevent recursion. If ReportStatusCode() + is called while processing another any other Report Status Code Library function, + then ReportStatusCode() must return immediately. + + @param Type Status code type. + @param Value Status code value. + + @retval EFI_SUCCESS The status code was reported. + @retval EFI_DEVICE_ERROR There status code could not be reported due to a + device error. + @retval EFI_UNSUPPORTED The report status code is not supported. + +**/ +EFI_STATUS +EFIAPI +ReportStatusCode ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value + ); + + +/** + Reports a status code with a Device Path Protocol as the extended data. + + Allocates and fills in the extended data section of a status code with the + Device Path Protocol specified by DevicePath. This function is responsible + for allocating a buffer large enough for the standard header and the device + path. The standard header is filled in with an implementation dependent GUID. + The status code is reported with a zero instance and a caller ID of gEfiCallerIdGuid. + + ReportStatusCodeWithDevicePath()must actively prevent recursion. If + ReportStatusCodeWithDevicePath() is called while processing another any other + Report Status Code Library function, then ReportStatusCodeWithDevicePath() + must return EFI_DEVICE_ERROR immediately. + + If DevicePath is NULL, then ASSERT(). + + @param Type The status code type. + @param Value The status code value. + @param DevicePath The pointer to the Device Path Protocol to be reported. + + @retval EFI_SUCCESS The status code was reported with the extended + data specified by DevicePath. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the + extended data section. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +EFI_STATUS +EFIAPI +ReportStatusCodeWithDevicePath ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + + +/** + Reports a status code with an extended data buffer. + + Allocates and fills in the extended data section of a status code with the + extended data specified by ExtendedData and ExtendedDataSize. ExtendedData + is assumed to be one of the data structures specified in Related Definitions. + These data structure do not have the standard header, so this function is + responsible for allocating a buffer large enough for the standard header and + the extended data passed into this function. The standard header is filled + in with an implementation dependent GUID. The status code is reported + with a zero instance and a caller ID of gEfiCallerIdGuid. + + ReportStatusCodeWithExtendedData()must actively prevent recursion. If + ReportStatusCodeWithExtendedData() is called while processing another any other + Report Status Code Library function, then ReportStatusCodeWithExtendedData() + must return EFI_DEVICE_ERROR immediately. + + If ExtendedData is NULL, then ASSERT(). + If ExtendedDataSize is 0, then ASSERT(). + + @param Type The status code type. + @param Value The status code value. + @param ExtendedData The pointer to the extended data buffer to be reported. + @param ExtendedDataSize The size, in bytes, of the extended data buffer to + be reported. + + @retval EFI_SUCCESS The status code was reported with the extended + data specified by ExtendedData and ExtendedDataSize. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the + extended data section. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +EFI_STATUS +EFIAPI +ReportStatusCodeWithExtendedData ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN CONST VOID *ExtendedData, + IN UINTN ExtendedDataSize + ); + + +/** + Reports a status code with full parameters. + + The function reports a status code. If ExtendedData is NULL and ExtendedDataSize + is 0, then an extended data buffer is not reported. If ExtendedData is not + NULL and ExtendedDataSize is not 0, then an extended data buffer is allocated. + ExtendedData is assumed not have the standard status code header, so this function + is responsible for allocating a buffer large enough for the standard header and + the extended data passed into this function. The standard header is filled in + with a GUID specified by ExtendedDataGuid. If ExtendedDataGuid is NULL, then a + GUID of gEfiStatusCodeSpecificDataGuid is used. The status code is reported with + an instance specified by Instance and a caller ID specified by CallerId. If + CallerId is NULL, then a caller ID of gEfiCallerIdGuid is used. + + ReportStatusCodeEx()must actively prevent recursion. If ReportStatusCodeEx() + is called while processing another any other Report Status Code Library function, + then ReportStatusCodeEx() must return EFI_DEVICE_ERROR immediately. + + If ExtendedData is NULL and ExtendedDataSize is not zero, then ASSERT(). + If ExtendedData is not NULL and ExtendedDataSize is zero, then ASSERT(). + + @param Type The status code type. + @param Value The status code value. + @param Instance The status code instance number. + @param CallerId The pointer to a GUID that identifies the caller of this + function. If this parameter is NULL, then a caller + ID of gEfiCallerIdGuid is used. + @param ExtendedDataGuid The pointer to the GUID for the extended data buffer. + If this parameter is NULL, then a the status code + standard header is filled in with an implementation dependent GUID. + @param ExtendedData The pointer to the extended data buffer. This is an + optional parameter that may be NULL. + @param ExtendedDataSize The size, in bytes, of the extended data buffer. + + @retval EFI_SUCCESS The status code was reported. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate + the extended data section if it was specified. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +EFI_STATUS +EFIAPI +ReportStatusCodeEx ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId OPTIONAL, + IN CONST EFI_GUID *ExtendedDataGuid OPTIONAL, + IN CONST VOID *ExtendedData OPTIONAL, + IN UINTN ExtendedDataSize + ); + + +/** + Returns TRUE if status codes of type EFI_PROGRESS_CODE are enabled + + This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED + bit of PcdReportStatusCodeProperyMask is set. Otherwise FALSE is returned. + + @retval TRUE The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is set. + @retval FALSE The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +ReportProgressCodeEnabled ( + VOID + ); + + +/** + Returns TRUE if status codes of type EFI_ERROR_CODE are enabled + + This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED + bit of PcdReportStatusCodeProperyMask is set. Otherwise, FALSE is returned. + + @retval TRUE The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is set. + @retval FALSE The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +ReportErrorCodeEnabled ( + VOID + ); + + +/** + Returns TRUE if status codes of type EFI_DEBUG_CODE are enabled + + This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED + bit of PcdReportStatusCodeProperyMask is set. Otherwise FALSE is returned. + + @retval TRUE The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is set. + @retval FALSE The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of + PcdReportStatusCodeProperyMask is clear. + +**/ +BOOLEAN +EFIAPI +ReportDebugCodeEnabled ( + VOID + ); + + +/** + Reports a status code with minimal parameters if the status code type is enabled. + + If the status code type specified by Type is enabled in + PcdReportStatusCodeProperyMask, then call ReportStatusCode() passing in Type + and Value. + + @param Type The status code type. + @param Value The status code value. + + @retval EFI_SUCCESS The status code was reported. + @retval EFI_DEVICE_ERROR There status code could not be reported due to a device error. + @retval EFI_UNSUPPORTED Report status code is not supported. + +**/ +#define REPORT_STATUS_CODE(Type,Value) \ + (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \ + ReportStatusCode(Type,Value) : \ + (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \ + ReportStatusCode(Type,Value) : \ + (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \ + ReportStatusCode(Type,Value) : \ + EFI_UNSUPPORTED + + +/** + Reports a status code with a Device Path Protocol as the extended data if the + status code type is enabled. + + If the status code type specified by Type is enabled in + PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithDevicePath() + passing in Type, Value, and DevicePath. + + @param Type The status code type. + @param Value The status code value. + @param DevicePath Pointer to the Device Path Protocol to be reported. + + @retval EFI_SUCCESS The status code was reported with the extended + data specified by DevicePath. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the + extended data section. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +#define REPORT_STATUS_CODE_WITH_DEVICE_PATH(Type,Value,DevicePathParameter) \ + (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \ + ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \ + (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \ + ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \ + (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \ + ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \ + EFI_UNSUPPORTED + + +/** + Reports a status code with an extended data buffer if the status code type + is enabled. + + If the status code type specified by Type is enabled in + PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithExtendedData() + passing in Type, Value, ExtendedData, and ExtendedDataSize. + + @param Type The status code type. + @param Value The status code value. + @param ExtendedData The pointer to the extended data buffer to be reported. + @param ExtendedDataSize The size, in bytes, of the extended data buffer to + be reported. + + @retval EFI_SUCCESS The status code was reported with the extended + data specified by ExtendedData and ExtendedDataSize. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the + extended data section. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +#define REPORT_STATUS_CODE_WITH_EXTENDED_DATA(Type,Value,ExtendedData,ExtendedDataSize) \ + (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \ + ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \ + (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \ + ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \ + (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \ + ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \ + EFI_UNSUPPORTED + +/** + Reports a status code specifying all parameters if the status code type is enabled. + + If the status code type specified by Type is enabled in + PcdReportStatusCodeProperyMask, then call ReportStatusCodeEx() passing in Type, + Value, Instance, CallerId, ExtendedDataGuid, ExtendedData, and ExtendedDataSize. + + @param Type The status code type. + @param Value The status code value. + @param Instance The status code instance number. + @param CallerId The pointer to a GUID that identifies the caller of this + function. If this parameter is NULL, then a caller + ID of gEfiCallerIdGuid is used. + @param ExtendedDataGuid Pointer to the GUID for the extended data buffer. + If this parameter is NULL, then a the status code + standard header is filled in with an implementation dependent GUID. + @param ExtendedData Pointer to the extended data buffer. This is an + optional parameter that may be NULL. + @param ExtendedDataSize The size, in bytes, of the extended data buffer. + + @retval EFI_SUCCESS The status code was reported. + @retval EFI_OUT_OF_RESOURCES There were not enough resources to allocate the + extended data section if it was specified. + @retval EFI_UNSUPPORTED The report status code is not supported. + @retval EFI_DEVICE_ERROR A call to a Report Status Code Library function + is already in progress. + +**/ +#define REPORT_STATUS_CODE_EX(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) \ + (ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \ + ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \ + (ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \ + ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \ + (ReportDebugCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_DEBUG_CODE) ? \ + ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \ + EFI_UNSUPPORTED + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ResourcePublicationLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ResourcePublicationLib.h new file mode 100644 index 0000000000..3e2a810e42 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/ResourcePublicationLib.h @@ -0,0 +1,36 @@ +/** @file + Provides a service to publish discovered system resources. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RESOURCE_PUBLICATION_LIB__ +#define __RESOURCE_PUBLICATION_LIB__ + +/** + Declares the presence of permanent system memory in the platform. + + Declares that the system memory buffer specified by MemoryBegin and MemoryLength + as permanent memory that may be used for general purpose use by software. + The amount of memory available to software may be less than MemoryLength + if published memory has alignment restrictions. + If MemoryLength is 0, then ASSERT(). + If MemoryLength is greater than (MAX_ADDRESS - MemoryBegin + 1), then ASSERT(). + + @param MemoryBegin The start address of the memory being declared. + @param MemoryLength The number of bytes of memory being declared. + + @retval RETURN_SUCCESS The memory buffer was published. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources to publish the memory buffer + +**/ +RETURN_STATUS +EFIAPI +PublishSystemMemory ( + IN PHYSICAL_ADDRESS MemoryBegin, + IN UINT64 MemoryLength + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RngLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RngLib.h new file mode 100644 index 0000000000..bed9d8e5be --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/RngLib.h @@ -0,0 +1,80 @@ +/** @file + Provides random number generator services. + +Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RNG_LIB_H__ +#define __RNG_LIB_H__ + +/** + Generates a 16-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 16-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber16 ( + OUT UINT16 *Rand + ); + +/** + Generates a 32-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 32-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber32 ( + OUT UINT32 *Rand + ); + +/** + Generates a 64-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 64-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber64 ( + OUT UINT64 *Rand + ); + +/** + Generates a 128-bit random number. + + if Rand is NULL, then ASSERT(). + + @param[out] Rand Buffer pointer to store the 128-bit random value. + + @retval TRUE Random number generated successfully. + @retval FALSE Failed to generate the random number. + +**/ +BOOLEAN +EFIAPI +GetRandomNumber128 ( + OUT UINT64 *Rand + ); + +#endif // __RNG_LIB_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3BootScriptLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3BootScriptLib.h new file mode 100644 index 0000000000..4e8e4b3ffa --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3BootScriptLib.h @@ -0,0 +1,595 @@ +/** @file + Defines library APIs used by modules to save EFI Boot Script Opcodes. + These OpCode will be restored by S3 related modules. + Note that some of the API defined in the Library class may not + be provided in the Framework version library instance, which means some of these + APIs cannot be used if the underlying firmware is Framework and not PI. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _S3_BOOT_SCRIPT_LIB_H_ +#define _S3_BOOT_SCRIPT_LIB_H_ + +#include +#include + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + address that can be passed to the S3 Boot Script Library PCI functions. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 + for PCI Express. + + @return The encoded PCI address. + +**/ +#define S3_BOOT_SCRIPT_LIB_PCI_ADDRESS(Bus,Device,Function,Register) \ + (UINT64) ( \ + (((UINTN) Bus) << 24) | \ + (((UINTN) Device) << 16) | \ + (((UINTN) Function) << 8) | \ + (((UINTN) (Register)) < 256 ? ((UINTN) (Register)) : (UINT64) (LShiftU64 ((UINT64) (Register), 32)))) + +/// +/// S3 Boot Script Width. +/// +typedef enum { + S3BootScriptWidthUint8, ///< 8-bit operation. + S3BootScriptWidthUint16, ///< 16-bit operation. + S3BootScriptWidthUint32, ///< 32-bit operation. + S3BootScriptWidthUint64, ///< 64-bit operation. + S3BootScriptWidthFifoUint8, ///< 8-bit FIFO operation. + S3BootScriptWidthFifoUint16, ///< 16-bit FIFO operation. + S3BootScriptWidthFifoUint32, ///< 32-bit FIFO operation. + S3BootScriptWidthFifoUint64, ///< 64-bit FIFO operation. + S3BootScriptWidthFillUint8, ///< 8-bit Fill operation. + S3BootScriptWidthFillUint16, ///< 16-bit Fill operation. + S3BootScriptWidthFillUint32, ///< 32-bit Fill operation. + S3BootScriptWidthFillUint64, ///< 64-bit Fill operation. + S3BootScriptWidthMaximum +} S3_BOOT_SCRIPT_LIB_WIDTH; + +/** + Save I/O write to boot script. + + @param[in] Width The width of the I/O operations. + @param[in] Address The base address of the I/O operations. + @param[in] Count The number of I/O operations to perform. + @param[in] Buffer The source buffer from which to write data. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveIoWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Adds a record for an I/O modify operation into a S3 boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Address The base address of the I/O operations. + @param[in] Data A pointer to the data to be OR-ed. + @param[in] DataMask A pointer to the data mask to be AND-ed with the data + read from the register. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveIoReadWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ); + +/** + Adds a record for a memory write operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Address The base address of the memory operations + @param[in] Count The number of memory operations to perform. + @param[in] Buffer The source buffer from which to write the data. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveMemWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Adds a record for a memory modify operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Address The base address of the memory operations. Address needs + alignment, if required + @param[in] Data A pointer to the data to be OR-ed. + @param[in] DataMask A pointer to the data mask to be AND-ed with the data + read from the register. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveMemReadWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ); + +/** + Adds a record for a PCI configuration space write operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Address The address within the PCI configuration space. + @param[in] Count The number of PCI operations to perform. + @param[in] Buffer The source buffer from which to write the data. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePciCfgWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Adds a record for a PCI configuration space modify operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Address The address within the PCI configuration space. + @param[in] Data A pointer to the data to be OR-ed.The size depends on Width. + @param[in] DataMask A pointer to the data mask to be AND-ed. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN__SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePciCfgReadWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ); + +/** + Adds a record for a PCI configuration space modify operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Segment The PCI segment number for Address. + @param[in] Address The address within the PCI configuration space. + @param[in] Count The number of PCI operations to perform. + @param[in] Buffer The source buffer from which to write the data. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePciCfg2Write ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT16 Segment, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Adds a record for a PCI configuration space modify operation into a specified boot script table. + + @param[in] Width The width of the I/O operations. + @param[in] Segment The PCI segment number for Address. + @param[in] Address The address within the PCI configuration space. + @param[in] Data A pointer to the data to be OR-ed. The size depends on Width. + @param[in] DataMask A pointer to the data mask to be AND-ed. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePciCfg2ReadWrite ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT16 Segment, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ); + +/** + Adds a record for an SMBus command execution into a specified boot script table. + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS + Command, SMBUS Data Length, and PEC. + @param[in] Operation Indicates which particular SMBus protocol it will use + to execute the SMBus transactions. + @param[in] Length A pointer to signify the number of bytes that this + operation will do. + @param[in] Buffer Contains the value of data to execute to the SMBUS + slave device. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveSmbusExecute ( + IN UINTN SmBusAddress, + IN EFI_SMBUS_OPERATION Operation, + IN UINTN *Length, + IN VOID *Buffer + ); + +/** + Adds a record for an execution stall on the processor into a specified boot script table. + + @param[in] Duration The duration in microseconds of the stall. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveStall ( + IN UINTN Duration + ); + +/** + Adds a record for dispatching specified arbitrary code into a specified boot script table. + + @param[in] EntryPoint The entry point of the code to be dispatched. + @param[in] Context The argument to be passed into the EntryPoint of the code + to be dispatched. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveDispatch2 ( + IN VOID *EntryPoint, + IN VOID *Context + ); + +/** + Adds a record for dispatching specified arbitrary code into a specified boot script table. + + @param[in] EntryPoint The entry point of the code to be dispatched. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveDispatch ( + IN VOID *EntryPoint + ); + +/** + Adds a record for memory reads of the memory location and continues when the exit + criteria is satisfied, or after a defined duration. + + Please aware, below interface is different with PI specification, Vol 5: + EFI_S3_SAVE_STATE_PROTOCOL.Write() for EFI_BOOT_SCRIPT_MEM_POLL_OPCODE. + "Duration" below is microseconds, while "Delay" in PI specification means + the number of 100ns units to poll. + + @param[in] Width The width of the memory operations. + @param[in] Address The base address of the memory operations. + @param[in] BitMask A pointer to the bit mask to be AND-ed with the data read + from the register. + @param[in] BitValue A pointer to the data value after to be Masked. + @param[in] Duration The duration in microseconds of the stall. + @param[in] LoopTimes The times of the register polling. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveMemPoll ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *BitMask, + IN VOID *BitValue, + IN UINTN Duration, + IN UINT64 LoopTimes + ); + +/** + Store arbitrary information in the boot script table. This opcode is a no-op on + dispatch and is only used for debugging script issues. + + @param[in] InformationLength Length of the data in bytes + @param[in] Information Information to be logged in the boot scrpit + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveInformation ( + IN UINT32 InformationLength, + IN VOID *Information + ); +/** + Adds a record for I/O reads the I/O location and continues when the exit criteria + is satisfied, or after a defined duration. + + @param Width The width of the I/O operations. + @param Address The base address of the I/O operations. + @param Data The comparison value used for the polling exit criteria. + @param DataMask The mask used for the polling criteria. The bits in + the bytes below Width which are zero in Data are + ignored when polling the memory address. + @param Delay The number of 100ns units to poll. Note that timer + available may be of insufficient granularity, so the + delay may be longer. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the + operation. + @retval RETURN_SUCCESS The opcode was added. + @note The FRAMEWORK version implementation does not support this API +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveIoPoll ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay + ); + +/** + Adds a record for PCI configuration space reads and continues when the exit + criteria is satisfied ,or after a defined duration. + + @param Width The width of the I/O operations. + @param Address The address within the PCI configuration space. + @param Data The comparison value used for the polling exit + criteria. + @param DataMask Mask used for the polling criteria. The bits in + the bytes below Width which are zero in Data are + ignored when polling the memory address. + @param Delay The number of 100ns units to poll. Note that timer + available may be of insufficient granularity, so the + delay may be longer. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the + operation. + @retval RETURN_SUCCESS The opcode was added. + @note The FRAMEWORK version implementation does not support this API +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePciPoll ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay + ); +/** + Adds a record for PCI configuration space reads and continues when the exit criteria + is satisfied, or after a defined duration. + + @param Width The width of the I/O operations. + @param Segment The PCI segment number for Address. + @param Address The address within the PCI configuration space. + @param Data The comparison value used for the polling exit + criteria. + @param DataMask Mask used for the polling criteria. The bits in + the bytes below Width which are zero + in Data are ignored when polling the memory address + @param Delay The number of 100ns units to poll. Note that timer + available may be of insufficient granularity so the delay + may be longer. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform the + operation. + @retval RETURN_SUCCESS The opcode was added. + @note A known Limitations in the implementation: When interpreting the opcode + EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE, EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE + and EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE, the 'Segment' parameter is assumed as + Zero, or else, assert. + The FRAMEWORK version implementation does not support this API. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSavePci2Poll ( + IN S3_BOOT_SCRIPT_LIB_WIDTH Width, + IN UINT16 Segment, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay + ); +/** + Save ASCII string information specified by Buffer to boot script with opcode + EFI_BOOT_SCRIPT_INFORMATION_OPCODE. + + @param[in] String The Null-terminated ASCII string to store into the S3 boot + script table. + + @retval RETURN_OUT_OF_RESOURCES Not enough memory for the table to perform + the operation. + @retval RETURN_SUCCESS The opcode was added. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptSaveInformationAsciiString ( + IN CONST CHAR8 *String + ); + +/** + This is an function to close the S3 boot script table. The function could only + be called in BOOT time phase. To comply with the Framework spec definition on + EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable(), this function will fulfill following things: + 1. Closes the specified boot script table + 2. It allocates a new memory pool to duplicate all the boot scripts in the specified table. + Once this function is called, the table maintained by the library will be destroyed + after it is copied into the allocated pool. + 3. Any attempts to add a script record after calling this function will cause a + new table to be created by the library. + 4. The base address of the allocated pool will be returned in Address. Note that + after using the boot script table, the CALLER is responsible for freeing the + pool that is allocated by this function. + + In Spec PI1.1, this EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is retired. This + API is supplied here to meet the requirements of the Framework Spec. + + If anyone does call CloseTable() on a real platform, then the caller is responsible + for figuring out how to get the script to run on an S3 resume because the boot script + maintained by the lib will be destroyed. + + @return the base address of the new copy of the boot script table. + +**/ +UINT8* +EFIAPI +S3BootScriptCloseTable ( + VOID + ); + +/** + Executes the S3 boot script table. + + @retval RETURN_SUCCESS The boot script table was executed successfully. + @retval RETURN_UNSUPPORTED Invalid script table or opcode. + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptExecute ( + VOID + ); +/** + Move the last boot script entry to the position + + @param BeforeOrAfter Specifies whether the opcode is stored before + (TRUE) or after (FALSE) the positionin the boot + script table specified by Position. If Position + is NULL or points to NULL then the new opcode is + inserted at the beginning of the table (if TRUE) + or end of the table (if FALSE). + @param Position On entry, specifies the position in the boot script + table where the opcode will be inserted, either + before or after, depending on BeforeOrAfter. On + exit, specifies the position of the inserted opcode + in the boot script table. + + @retval RETURN_OUT_OF_RESOURCES The table is not available. + @retval RETURN_INVALID_PARAMETER The Position is not a valid position in the + boot script table. + @retval RETURN_SUCCESS The opcode was inserted. + @note The FRAMEWORK version implementation does not support this API. +**/ +RETURN_STATUS +EFIAPI +S3BootScriptMoveLastOpcode ( + IN BOOLEAN BeforeOrAfter, + IN OUT VOID **Position OPTIONAL + ); +/** + Find a label within the boot script table and, if not present, optionally create it. + + @param BeforeOrAfter Specifies whether the opcode is stored before (TRUE) + or after (FALSE) the position in the boot script table + specified by Position. + @param CreateIfNotFound Specifies whether the label will be created if the + label does not exists (TRUE) or not (FALSE). + @param Position On entry, specifies the position in the boot script + table where the opcode will be inserted, either + before or after, depending on BeforeOrAfter. On exit, + specifies the positionof the inserted opcode in + the boot script table. + @param Label Points to the label which will be inserted in the + boot script table. + @retval EFI_SUCCESS The operation succeeded. A record was added into + the specified script table. + @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script + is not supported. If the opcode is unknow or not + supported because of the PCD Feature Flags. + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script. + @note The FRAMEWORK version implementation does not support this API + +**/ +RETURN_STATUS +EFIAPI +S3BootScriptLabel ( + IN BOOLEAN BeforeOrAfter, + IN BOOLEAN CreateIfNotFound, + IN OUT VOID **Position OPTIONAL, + IN CONST CHAR8 *Label + ); +/** + Compare two positions in the boot script table and return their relative position. + @param Position1 The positions in the boot script table to compare + @param Position2 The positions in the boot script table to compare + @param RelativePosition On return, points to the result of the comparison + + @retval EFI_SUCCESS The operation succeeded. A record was added into the + specified script table. + @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script + is not supported. If the opcode is unknow or not s + upported because of the PCD Feature Flags. + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script. + @note The FRAMEWORK version implementation does not support this API +**/ +RETURN_STATUS +EFIAPI +S3BootScriptCompare ( + IN UINT8 *Position1, + IN UINT8 *Position2, + OUT UINTN *RelativePosition + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3IoLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3IoLib.h new file mode 100644 index 0000000000..f276050d09 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3IoLib.h @@ -0,0 +1,2670 @@ +/** @file + I/O and MMIO Library Services that do I/O and also enable the I/O operation + to be replayed during an S3 resume. This library class maps directly on top + of the IoLib class. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __S3_IO_LIB_H__ +#define __S3_IO_LIB_H__ + +/** + Reads an 8-bit I/O port and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +S3IoRead8 ( + IN UINTN Port + ); + +/** + Writes an 8-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Writes the 8-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +S3IoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ); + +/** + Reads an 8-bit I/O port, performs a bitwise OR, writes the + result back to the 8-bit I/O port, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 8-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoOr8 ( + IN UINTN Port, + IN UINT8 OrData + ); + +/** + Reads an 8-bit I/O port, performs a bitwise AND, writes the result back + to the 8-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 8-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoAnd8 ( + IN UINTN Port, + IN UINT8 AndData + ); + +/** + Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 8-bit I/O port, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoAndThenOr8 ( + IN UINTN Port, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of an I/O register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in an 8-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Port The I/O port to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value read. + +**/ +UINT8 +EFIAPI +S3IoBitFieldRead8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. + Remaining bits in Value are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoBitFieldWrite8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise OR, writes the + result back to the bit field in the 8-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 8-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoBitFieldOr8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND, writes the + result back to the bit field in the 8-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 8-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoBitFieldAnd8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the + 8-bit port, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 8-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 8-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT8 +EFIAPI +S3IoBitFieldAndThenOr8 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +S3IoRead16 ( + IN UINTN Port + ); + +/** + Writes a 16-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Writes the 16-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +S3IoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ); + +/** + Reads a 16-bit I/O port, performs a bitwise OR, writes the + result back to the 16-bit I/O port, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 16-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoOr16 ( + IN UINTN Port, + IN UINT16 OrData + ); + +/** + Reads a 16-bit I/O port, performs a bitwise AND, writes the result back + to the 16-bit I/O port , and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 16-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoAnd16 ( + IN UINTN Port, + IN UINT16 AndData + ); + +/** + Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 16-bit I/O port, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoAndThenOr16 ( + IN UINTN Port, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of an I/O register saves the value in the S3 script to be + replayed on S3 resume. + + Reads the bit field in a 16-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Port The I/O port to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value read. + +**/ +UINT16 +EFIAPI +S3IoBitFieldRead16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register, and saves the value in the S3 script + to be replayed on S3 resume. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoBitFieldWrite16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise OR, writes the + result back to the bit field in the 16-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 16-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoBitFieldOr16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND, writes the + result back to the bit field in the 16-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 16-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoBitFieldAnd16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the + 16-bit port, and saves the value in the S3 script to be replayed on S3 + resume. + + Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 16-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 16-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT16 +EFIAPI +S3IoBitFieldAndThenOr16 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +S3IoRead32 ( + IN UINTN Port + ); + +/** + Writes a 32-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Writes the 32-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +S3IoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ); + +/** + Reads a 32-bit I/O port, performs a bitwise OR, writes the + result back to the 32-bit I/O port, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 32-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoOr32 ( + IN UINTN Port, + IN UINT32 OrData + ); + +/** + Reads a 32-bit I/O port, performs a bitwise AND, writes the result back + to the 32-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 32-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoAnd32 ( + IN UINTN Port, + IN UINT32 AndData + ); + +/** + Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 32-bit I/O port, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoAndThenOr32 ( + IN UINTN Port, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of an I/O register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in a 32-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Port The I/O port to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value read. + +**/ +UINT32 +EFIAPI +S3IoBitFieldRead32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoBitFieldWrite32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise OR, writes the + result back to the bit field in the 32-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 32-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoBitFieldOr32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND, writes the + result back to the bit field in the 32-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 32-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoBitFieldAnd32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the + 32-bit port, and saves the value in the S3 script to be replayed on S3 + resume. + + Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 32-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 32-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT32 +EFIAPI +S3IoBitFieldAndThenOr32 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a 64-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned. + This function must guarantee that all I/O read and write operations are + serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +S3IoRead64 ( + IN UINTN Port + ); + +/** + Writes a 64-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Writes the 64-bit I/O port specified by Port with the value specified by Value + and returns Value. This function must guarantee that all I/O read and write + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] Value The value to write to the I/O port. + + @return The value written to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoWrite64 ( + IN UINTN Port, + IN UINT64 Value + ); + +/** + Reads a 64-bit I/O port, performs a bitwise OR, writes the + result back to the 64-bit I/O port, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoOr64 ( + IN UINTN Port, + IN UINT64 OrData + ); + +/** + Reads a 64-bit I/O port, performs a bitwise AND, writes the result back + to the 64-bit I/O port, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 64-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoAnd64 ( + IN UINTN Port, + IN UINT64 AndData + ); + +/** + Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 64-bit I/O port, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, performs a bitwise OR + between the result of the AND operation and the value specified by OrData, + and writes the result to the 64-bit I/O port specified by Port. The value + written to the I/O port is returned. This function must guarantee that all + I/O read and write operations are serialized. + + If 64-bit I/O port operations are not supported, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoAndThenOr64 ( + IN UINTN Port, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads a bit field of an I/O register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in a 64-bit I/O register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Port The I/O port to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The value read. + +**/ +UINT64 +EFIAPI +S3IoBitFieldRead64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an I/O register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the I/O register. The bit field is specified + by the StartBit and the EndBit. All other bits in the destination I/O + register are preserved. The value written to the I/O port is returned. Extra + left bits in Value are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] Value New value of the bit field. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoBitFieldWrite64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise OR, writes the + result back to the bit field in the 64-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise OR + between the read result and the value specified by OrData, and writes the + result to the 64-bit I/O port specified by Port. The value written to the I/O + port is returned. This function must guarantee that all I/O read and write + operations are serialized. Extra left bits in OrData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] OrData The value to OR with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoBitFieldOr64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise AND, writes the + result back to the bit field in the 64-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND between + the read result and the value specified by AndData, and writes the result to + the 64-bit I/O port specified by Port. The value written to the I/O port is + returned. This function must guarantee that all I/O read and write operations + are serialized. Extra left bits in AndData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] AndData The value to AND with the read value from the I/O port. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoBitFieldAnd64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + +/** + Reads a bit field in a 64-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the + 64-bit port, and saves the value in the S3 script to be replayed on S3 + resume. + + Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed + by a bitwise OR between the read result and the value specified by + AndData, and writes the result to the 64-bit I/O port specified by Port. The + value written to the I/O port is returned. This function must guarantee that + all I/O read and write operations are serialized. Extra left bits in both + AndData and OrData are stripped. + + If 64-bit I/O port operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Port The I/O port to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] AndData The value to AND with the read value from the I/O port. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the I/O port. + +**/ +UINT64 +EFIAPI +S3IoBitFieldAndThenOr64 ( + IN UINTN Port, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads an 8-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +S3MmioRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Writes the 8-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] Value The value to write to the MMIO register. + + @return The value written the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise OR, writes the + result back to the 8-bit MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 8-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise AND, writes the result + back to the 8-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 8-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 8-bit MMIO register, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 8-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a MMIO register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in an 8-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address MMIO register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value read. + +**/ +UINT8 +EFIAPI +S3MmioBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to an MMIO register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 8-bit register is returned. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, + writes the result back to the bit field in the 8-bit MMIO register, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 8-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 8-bit MMIO register, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 8-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, writes the result back to the bit field in the + 8-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 8-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 8-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 8-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT8 +EFIAPI +S3MmioBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 16-bit MMIO register specified by Address. The 16-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +S3MmioRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Writes the 16-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized, and saves the value in the S3 script to be + replayed on S3 resume. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] Value The value to write to the MMIO register. + + @return The value written the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise OR, writes the + result back to the 16-bit MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 16-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise AND, writes the result + back to the 16-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 16-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 16-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 16-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a MMIO register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in a 16-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address MMIO register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value read. + +**/ +UINT16 +EFIAPI +S3MmioBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 16-bit register is returned. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, + writes the result back to the bit field in the 16-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 16-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 16-bit MMIO register and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 16-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, writes the result back to the bit field in the + 16-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 16-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 16-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 16-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT16 +EFIAPI +S3MmioBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit MMIO register saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address. The 32-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +S3MmioRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Writes the 32-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] Value The value to write to the MMIO register. + + @return The value written the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise OR, writes the + result back to the 32-bit MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 32-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise AND, writes the result + back to the 32-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 32-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 32-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 32-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads the bit field in a 32-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address MMIO register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value read. + +**/ +UINT32 +EFIAPI +S3MmioBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 32-bit register is returned. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, + writes the result back to the bit field in the 32-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 32-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 32-bit MMIO register and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 32-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, writes the result back to the bit field in the + 32-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 32-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 32-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 32-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT32 +EFIAPI +S3MmioBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a 64-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address. The 64-bit read value is + returned. This function must guarantee that all MMIO read and write + operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +S3MmioRead64 ( + IN UINTN Address + ); + +/** + Writes a 64-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Writes the 64-bit MMIO register specified by Address with the value specified + by Value and returns Value. This function must guarantee that all MMIO read + and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] Value The value to write to the MMIO register. + + @return The value written the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise OR, writes the + result back to the 64-bit MMIO register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 64-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioOr64 ( + IN UINTN Address, + IN UINT64 OrData + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise AND, writes the result + back to the 64-bit MMIO register, and saves the value in the S3 script to be + replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 64-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioAnd64 ( + IN UINTN Address, + IN UINT64 AndData + ); + +/** + Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise + inclusive OR, writes the result back to the 64-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, performs a + bitwise OR between the result of the AND operation and the value specified by + OrData, and writes the result to the 64-bit MMIO register specified by + Address. The value written to the MMIO register is returned. This function + must guarantee that all MMIO read and write operations are serialized. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioAndThenOr64 ( + IN UINTN Address, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Reads a bit field of a MMIO register saves the value in the S3 script to + be replayed on S3 resume. + + Reads the bit field in a 64-bit MMIO register. The bit field is specified by + the StartBit and the EndBit. The value of the bit field is returned. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address MMIO register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + + @return The value read. + +**/ +UINT64 +EFIAPI +S3MmioBitFieldRead64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a MMIO register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes Value to the bit field of the MMIO register. The bit field is + specified by the StartBit and the EndBit. All other bits in the destination + MMIO register are preserved. The new value of the 64-bit register is returned. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] Value New value of the bit field. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioBitFieldWrite64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 Value + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, + writes the result back to the bit field in the 64-bit MMIO register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise + inclusive OR between the read result and the value specified by OrData, and + writes the result to the 64-bit MMIO register specified by Address. The value + written to the MMIO register is returned. This function must guarantee that + all MMIO read and write operations are serialized. Extra left bits in OrData + are stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] OrData The value to OR with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioBitFieldOr64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 OrData + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and + writes the result back to the bit field in the 64-bit MMIO register, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + between the read result and the value specified by AndData, and writes the + result to the 64-bit MMIO register specified by Address. The value written to + the MMIO register is returned. This function must guarantee that all MMIO + read and write operations are serialized. Extra left bits in AndData are + stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] AndData The value to AND with the read value from the MMIO register. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioBitFieldAnd64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData + ); + +/** + Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed + by a bitwise OR, writes the result back to the bit field in the + 64-bit MMIO register, and saves the value in the S3 script to be replayed + on S3 resume. + + Reads the 64-bit MMIO register specified by Address, performs a bitwise AND + followed by a bitwise OR between the read result and the value + specified by AndData, and writes the result to the 64-bit MMIO register + specified by Address. The value written to the MMIO register is returned. + This function must guarantee that all MMIO read and write operations are + serialized. Extra left bits in both AndData and OrData are stripped. + + If 64-bit MMIO register operations are not supported, then ASSERT(). + If StartBit is greater than 63, then ASSERT(). + If EndBit is greater than 63, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The MMIO register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..63. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..63. + @param[in] AndData The value to AND with the read value from the MMIO register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the MMIO register. + +**/ +UINT64 +EFIAPI +S3MmioBitFieldAndThenOr64 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT64 AndData, + IN UINT64 OrData + ); + +/** + Copies data from MMIO region to system memory by using 8-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 8-bit access. The total + number of bytes to be copied is specified by Length. Buffer is returned. + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + + @param[in] StartAddress Starting address for the MMIO region to be copied from. + @param[in] Length Size in bytes of the copy. + @param[out] Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer. + +**/ +UINT8 * +EFIAPI +S3MmioReadBuffer8 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT8 *Buffer + ); + +/** + Copies data from MMIO region to system memory by using 16-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 16-bit access. The total + number of bytes to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 16-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 16-bit boundary, then ASSERT(). + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied from. + @param[in] Length Size in bytes of the copy. + @param[out] Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer. + +**/ +UINT16 * +EFIAPI +S3MmioReadBuffer16 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT16 *Buffer + ); + +/** + Copies data from MMIO region to system memory by using 32-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 32-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 32-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 32-bit boundary, then ASSERT(). + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied from. + @param[in] Length Size in bytes of the copy. + @param[out] Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer. + +**/ +UINT32 * +EFIAPI +S3MmioReadBuffer32 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT32 *Buffer + ); + +/** + Copies data from MMIO region to system memory by using 64-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from MMIO region specified by starting address StartAddress + to system memory specified by Buffer by using 64-bit access. The total + number of byte to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 64-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). + + If Length is not aligned on a 64-bit boundary, then ASSERT(). + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied from. + @param[in] Length Size in bytes of the copy. + @param[out] Buffer Pointer to a system memory buffer receiving the data read. + + @return Buffer. + +**/ +UINT64 * +EFIAPI +S3MmioReadBuffer64 ( + IN UINTN StartAddress, + IN UINTN Length, + OUT UINT64 *Buffer + ); + +/** + Copies data from system memory to MMIO region by using 8-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 8-bit access. The total number + of byte to be copied is specified by Length. Buffer is returned. + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + + @param[in] StartAddress Starting address for the MMIO region to be copied to. + @param[in] Length Size in bytes of the copy. + @param[in] Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer. + +**/ +UINT8 * +EFIAPI +S3MmioWriteBuffer8 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT8 *Buffer + ); + +/** + Copies data from system memory to MMIO region by using 16-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 16-bit access. The total number + of bytes to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 16-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 16-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied to. + @param[in] Length Size in bytes of the copy. + @param[in] Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer. + +**/ +UINT16 * +EFIAPI +S3MmioWriteBuffer16 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT16 *Buffer + ); + +/** + Copies data from system memory to MMIO region by using 32-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 32-bit access. The total number + of bytes to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 32-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 32-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied to. + @param[in] Length Size in bytes of the copy. + @param[in] Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer. + +**/ +UINT32 * +EFIAPI +S3MmioWriteBuffer32 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT32 *Buffer + ); + +/** + Copies data from system memory to MMIO region by using 64-bit access, + and saves the value in the S3 script to be replayed on S3 resume. + + Copy data from system memory specified by Buffer to MMIO region specified + by starting address StartAddress by using 64-bit access. The total number + of bytes to be copied is specified by Length. Buffer is returned. + + If StartAddress is not aligned on a 64-bit boundary, then ASSERT(). + + If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). + If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT(). + + If Length is not aligned on a 64-bit boundary, then ASSERT(). + + If Buffer is not aligned on a 64-bit boundary, then ASSERT(). + + @param[in] StartAddress Starting address for the MMIO region to be copied to. + @param[in] Length Size in bytes of the copy. + @param[in] Buffer Pointer to a system memory buffer containing the data to write. + + @return Buffer. + +**/ +UINT64 * +EFIAPI +S3MmioWriteBuffer64 ( + IN UINTN StartAddress, + IN UINTN Length, + IN CONST UINT64 *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciLib.h new file mode 100644 index 0000000000..2d9ddc317c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciLib.h @@ -0,0 +1,1045 @@ +/** @file + The PCI configuration Library Services that carry out PCI configuration and enable + the PCI operations to be replayed during an S3 resume. This library class + maps directly on top of the PciLib class. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __S3_PCI_LIB_H__ +#define __S3_PCI_LIB_H__ + +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an + address that can be passed to the S3 PCI Library functions. + + @param Bus The PCI Bus number. Range 0..255. + @param Device The PCI Device number. Range 0..31. + @param Function The PCI Function number. Range 0..7. + @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095 + for PCI Express. + + @return The encoded PCI address. + +**/ +#define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \ + (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) + +/** + + Reads and returns the 8-bit PCI configuration register specified by Address, + and saves the value in the S3 script to be replayed on S3 resume. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The value read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit PCI configuration register, and saves the value in the S3 + script to be replayed on S3 resume. + + Writes the 8-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciWrite8 ( + IN UINTN Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciOr8 ( + IN UINTN Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit + value, followed a bitwise OR with another 8-bit value, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port, and saves the value + in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register, and saves the value in the S3 + script to be replayed on S3 resume. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit PCI configuration register, and saves the value in the S3 + script to be replayed on S3 resume. + + Writes the 16-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciWrite16 ( + IN UINTN Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciOr16 ( + IN UINTN Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit + value, followed a bitwise OR with another 16-bit value, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 16-bit port, and saves the value + in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 16-bit register and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register, and saves the value in the S3 + script to be replayed on S3 resume. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit PCI configuration register, and saves the value in the S3 + script to be replayed on S3 resume. + + Writes the 32-bit PCI configuration register specified by Address with the + value specified by Value. Value is returned. This function must guarantee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciWrite32 ( + IN UINTN Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciOr32 ( + IN UINTN Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit + value, followed a bitwise OR with another 32-bit value, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param[in] Address The address that encodes the PCI Bus, Device, Function and + Register. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param[in] Address The PCI configuration register to read. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port, and saves the value + in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param[in] Address The PCI configuration register to write. + @param[in] StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param[in] EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param[in] AndData The value to AND with the PCI configuration register. + @param[in] OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer, + and saves the value in the S3 script to be replayed on S3 resume. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param[in] Size Size in bytes of the transfer. + @param[out] Buffer The pointer to a buffer receiving the data read. + + @return Size. + +**/ +UINTN +EFIAPI +S3PciReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space, and saves the value in the S3 script to be replayed on S3 + resume. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param[in] StartAddress Starting address that encodes the PCI Bus, Device, + Function and Register. + @param[in] Size Size in bytes of the transfer. + @param[in] Buffer The pointer to a buffer containing the data to write. + + @return Size. + +**/ +UINTN +EFIAPI +S3PciWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciSegmentLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciSegmentLib.h new file mode 100644 index 0000000000..5e8d70b4b0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3PciSegmentLib.h @@ -0,0 +1,1031 @@ +/** @file + The multiple segments PCI configuration Library Services that carry out + PCI configuration and enable the PCI operations to be replayed during an + S3 resume. This library class maps directly on top of the PciSegmentLib class. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __S3_PCI_SEGMENT_LIB__ +#define __S3_PCI_SEGMENT_LIB__ + + +/** + Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function, + and PCI Register to an address that can be passed to the S3 PCI Segment Library functions. + + Computes an address that is compatible with the PCI Segment Library functions. + The unused upper bits of Segment, Bus, Device, Function, + and Register are stripped prior to the generation of the address. + + @param Segment PCI Segment number. Range 0..65535. + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express. + + @return The address that is compatible with the PCI Segment Library functions. + +**/ +#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \ + ((Segment != 0) ? \ + ( ((Register) & 0xfff) | \ + (((Function) & 0x07) << 12) | \ + (((Device) & 0x1f) << 15) | \ + (((Bus) & 0xff) << 20) | \ + (LShiftU64 ((Segment) & 0xffff, 32)) \ + ) : \ + ( ((Register) & 0xfff) | \ + (((Function) & 0x07) << 12) | \ + (((Device) & 0x1f) << 15) | \ + (((Bus) & 0xff) << 20) \ + ) \ + ) + +/** + Reads an 8-bit PCI configuration register, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +S3PciSegmentRead8 ( + IN UINT64 Address + ); + +/** + Writes an 8-bit PCI configuration register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ); + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves + the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ); + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, + followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ); + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes + the result back to the bit field in the 8-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ); + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, writes the result back to the bit field in the 8-bit register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ); + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the 8-bit port, + and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +S3PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit PCI configuration register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +S3PciSegmentRead16 ( + IN UINT64 Address + ); + +/** + Writes a 16-bit PCI configuration register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +S3PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ); + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit + value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by OrData, and + writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. This function + must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ); + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, + followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ); + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes + the result back to the bit field in the 16-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ); + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise + AND, writes the result back to the bit field in the 16-bit register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 16-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ); + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the 16-bit port, + and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +S3PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit PCI configuration register, and saves the value in the S3 script + to be replayed on S3 resume. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +S3PciSegmentRead32 ( + IN UINT64 Address + ); + +/** + Writes a 32-bit PCI configuration register, and saves the value in the S3 script to + be replayed on S3 resume. + + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +S3PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ); + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit + value, and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by OrData, and + writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. This function + must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ); + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, + followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to + be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a bit field of a PCI configuration register, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ); + +/** + Writes a bit field to a PCI configuration register, and saves the value in + the S3 script to be replayed on S3 resume. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value New value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ); + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes + the result back to the bit field in the 32-bit port, and saves the value in the + S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ); + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register, and + saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 32-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ); + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, writes the result back to the bit field in the 32-bit port, + and saves the value in the S3 script to be replayed on S3 resume. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +S3PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Reads a range of PCI configuration registers into a caller supplied buffer, + and saves the value in the S3 script to be replayed on S3 resume. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +S3PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ); + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space, and saves the value in the S3 script to be replayed on S3 + resume. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. + @param Size Size in bytes of the transfer. + @param Buffer Pointer to a buffer containing the data to write. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +S3PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3SmbusLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3SmbusLib.h new file mode 100644 index 0000000000..471725641e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3SmbusLib.h @@ -0,0 +1,448 @@ +/** @file + Smbus Library Services that conduct SMBus transactions and enable the operatation + to be replayed during an S3 resume. This library class maps directly on top + of the SmbusLib class. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __S3_SMBUS_LIB_H__ +#define __S3_SMBUS_LIB_H__ + +/** + Executes an SMBUS quick read command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is returned in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_UNSUPPORTED The SMBus operation is not supported. + +**/ +VOID +EFIAPI +S3SmBusQuickRead ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS quick write command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is returned in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_UNSUPPORTED The SMBus operation is not supported. + +**/ +VOID +EFIAPI +S3SmBusQuickWrite ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS receive byte command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + The byte received from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte received from the SMBUS. + +**/ +UINT8 +EFIAPI +S3SmBusReceiveByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS send byte command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress. + The byte specified by Value is sent. + Only the SMBUS slave address field of SmBusAddress is required. Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 8-bit value to send. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT8 +EFIAPI +S3SmBusSendByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read data byte command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 8-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte read from the SMBUS. + +**/ +UINT8 +EFIAPI +S3SmBusReadDataByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write data byte command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress. + The 8-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 8-bit value to write. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT8 +EFIAPI +S3SmBusWriteDataByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read data word command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 16-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte read from the SMBUS. + +**/ +UINT16 +EFIAPI +S3SmBusReadDataWord ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write data word command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 16-bit value to write. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +S3SmBusWriteDataWord ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS process call command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 16-bit value returned by the process call command is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 16-bit value to write. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The 16-bit value returned by the process call command. + +**/ +UINT16 +EFIAPI +S3SmBusProcessCall ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read block command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Bytes are read from the SMBUS and stored in Buffer. + The number of bytes read is returned, and will never return a value larger than 32-bytes. + If Status is not NULL, then the status of the executed command is returned in Status. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes. + If Length in SmBusAddress is not zero, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Buffer The pointer to the buffer to store the bytes read from the SMBUS. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes read. + +**/ +UINTN +EFIAPI +S3SmBusReadBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write block command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required. + Bytes are written to the SMBUS from Buffer. + The number of bytes written is returned, and will never return a value larger than 32-bytes. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Buffer The pointer to the buffer to store the bytes read from the SMBUS. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes written. + +**/ +UINTN +EFIAPI +S3SmBusWriteBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS block process call command, and saves the value in the S3 script to be replayed + on S3 resume. + + Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required. + Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer. + If Status is not NULL, then the status of the executed command is returned in Status. + It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If WriteBuffer is NULL, then ASSERT(). + If ReadBuffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress The address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] WriteBuffer The pointer to the buffer of bytes to write to the SMBUS. + @param[out] ReadBuffer The pointer to the buffer of bytes to read from the SMBUS. + @param[out] Status The return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + was recorded in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus error (collision). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect). + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes written. + +**/ +UINTN +EFIAPI +S3SmBusBlockProcessCall ( + IN UINTN SmBusAddress, + IN VOID *WriteBuffer, + OUT VOID *ReadBuffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3StallLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3StallLib.h new file mode 100644 index 0000000000..aab86679dc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/S3StallLib.h @@ -0,0 +1,32 @@ +/** @file + Stall Services that perform stalls and also enable the Stall operatation + to be replayed during an S3 resume. This library class maps directly on top + of the Timer class. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __S3_STALL_LIB_H__ +#define __S3_STALL_LIB_H__ + +/** + Stalls the CPU for at least the given number of microseconds and saves + the value in the S3 script to be replayed on S3 resume. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param[in] MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds. + +**/ +UINTN +EFIAPI +S3Stall ( + IN UINTN MicroSeconds + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SafeIntLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SafeIntLib.h new file mode 100644 index 0000000000..e2f376f79f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SafeIntLib.h @@ -0,0 +1,3013 @@ +/** @file + This library provides helper functions to prevent integer overflow during + type conversion, addition, subtraction, and multiplication. + + Copyright (c) 2017, Microsoft Corporation + + All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __INT_SAFE_LIB_H__ +#define __INT_SAFE_LIB_H__ + +// +// It is common for -1 to be used as an error value +// +#define INT8_ERROR ((INT8) -1) +#define UINT8_ERROR MAX_UINT8 +#define CHAR8_ERROR ((CHAR8)(MAX_INT8)) +#define INT16_ERROR ((INT16) -1) +#define UINT16_ERROR MAX_UINT16 +#define CHAR16_ERROR MAX_UINT16 +#define INT32_ERROR ((INT32) -1) +#define UINT32_ERROR MAX_UINT32 +#define INT64_ERROR ((INT64) -1) +#define UINT64_ERROR MAX_UINT64 +#define INTN_ERROR ((INTN) -1) +#define UINTN_ERROR MAX_UINTN + +// +// CHAR16 is defined to be the same as UINT16, so for CHAR16 +// operations redirect to the UINT16 ones: +// +#define SafeInt8ToChar16 SafeInt8ToUint16 +#define SafeInt16ToChar16 SafeInt16ToUint16 +#define SafeInt32ToChar16 SafeInt32ToUint16 +#define SafeUint32ToChar16 SafeUint32ToUint16 +#define SafeInt64ToChar16 SafeInt64ToUint16 +#define SafeUint64ToChar16 SafeUint64ToUint16 +#define SafeIntnToChar16 SafeIntnToUint16 +#define SafeUintnToChar16 SafeUintnToUint16 + +#define SafeChar16ToInt8 SafeUint16ToInt8 +#define SafeChar16ToUint8 SafeUint16ToUint8 +#define SafeChar16ToChar8 SafeUint16ToChar8 +#define SafeChar16ToInt16 SafeUint16ToInt16 + +#define SafeChar16Mult SafeUint16Mult +#define SafeChar16Sub SafeUint16Sub +#define SafeChar16Add SafeUint16Add + +// +// Conversion functions +// +// There are three reasons for having conversion functions: +// +// 1. We are converting from a signed type to an unsigned type of the same +// size, or vice-versa. +// +// 2. We are converting to a smaller type, and we could therefore possibly +// overflow. +// +// 3. We are converting to a bigger type, and we are signed and the type we are +// converting to is unsigned. +// + +/** + INT8 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToUint8 ( + IN INT8 Operand, + OUT UINT8 *Result + ); + +/** + INT8 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToChar8 ( + IN INT8 Operand, + OUT CHAR8 *Result + ); + +/** + INT8 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToUint16 ( + IN INT8 Operand, + OUT UINT16 *Result + ); + +/** + INT8 -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToUint32 ( + IN INT8 Operand, + OUT UINT32 *Result + ); + +/** + INT8 -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToUintn ( + IN INT8 Operand, + OUT UINTN *Result + ); + +/** + INT8 -> UINT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8ToUint64 ( + IN INT8 Operand, + OUT UINT64 *Result + ); + +/** + UINT8 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint8ToInt8 ( + IN UINT8 Operand, + OUT INT8 *Result + ); + +/** + UINT8 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint8ToChar8 ( + IN UINT8 Operand, + OUT CHAR8 *Result + ); + +/** + INT16 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToInt8 ( + IN INT16 Operand, + OUT INT8 *Result + ); + +/** + INT16 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToChar8 ( + IN INT16 Operand, + OUT CHAR8 *Result + ); + +/** + INT16 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToUint8 ( + IN INT16 Operand, + OUT UINT8 *Result + ); + +/** + INT16 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToUint16 ( + IN INT16 Operand, + OUT UINT16 *Result + ); + +/** + INT16 -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToUint32 ( + IN INT16 Operand, + OUT UINT32 *Result + ); + +/** + INT16 -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToUintn ( + IN INT16 Operand, + OUT UINTN *Result + ); + +/** + INT16 -> UINT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16ToUint64 ( + IN INT16 Operand, + OUT UINT64 *Result + ); + +/** + UINT16 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16ToInt8 ( + IN UINT16 Operand, + OUT INT8 *Result + ); + +/** + UINT16 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16ToChar8 ( + IN UINT16 Operand, + OUT CHAR8 *Result + ); + +/** + UINT16 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16ToUint8 ( + IN UINT16 Operand, + OUT UINT8 *Result + ); + +/** + UINT16 -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16ToInt16 ( + IN UINT16 Operand, + OUT INT16 *Result + ); + +/** + INT32 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToInt8 ( + IN INT32 Operand, + OUT INT8 *Result + ); + +/** + INT32 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToChar8 ( + IN INT32 Operand, + OUT CHAR8 *Result + ); + +/** + INT32 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToUint8 ( + IN INT32 Operand, + OUT UINT8 *Result + ); + +/** + INT32 -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToInt16 ( + IN INT32 Operand, + OUT INT16 *Result + ); + +/** + INT32 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToUint16 ( + IN INT32 Operand, + OUT UINT16 *Result + ); + + +/** + INT32 -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToUint32 ( + IN INT32 Operand, + OUT UINT32 *Result + ); + +/** + INT32 -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToUintn ( + IN INT32 Operand, + OUT UINTN *Result + ); + +/** + INT32 -> UINT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32ToUint64 ( + IN INT32 Operand, + OUT UINT64 *Result + ); + +/** + UINT32 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToInt8 ( + IN UINT32 Operand, + OUT INT8 *Result + ); + +/** + UINT32 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToChar8 ( + IN UINT32 Operand, + OUT CHAR8 *Result + ); + +/** + UINT32 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToUint8 ( + IN UINT32 Operand, + OUT UINT8 *Result + ); + +/** + UINT32 -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToInt16 ( + IN UINT32 Operand, + OUT INT16 *Result + ); + +/** + UINT32 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToUint16 ( + IN UINT32 Operand, + OUT UINT16 *Result + ); + +/** + UINT32 -> INT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToInt32 ( + IN UINT32 Operand, + OUT INT32 *Result + ); + +/** + UINT32 -> INTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32ToIntn ( + IN UINT32 Operand, + OUT INTN *Result + ); + +/** + INTN -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToInt8 ( + IN INTN Operand, + OUT INT8 *Result + ); + +/** + INTN -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToChar8 ( + IN INTN Operand, + OUT CHAR8 *Result + ); + +/** + INTN -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToUint8 ( + IN INTN Operand, + OUT UINT8 *Result + ); + +/** + INTN -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToInt16 ( + IN INTN Operand, + OUT INT16 *Result + ); + +/** + INTN -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToUint16 ( + IN INTN Operand, + OUT UINT16 *Result + ); + +/** + INTN -> INT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToInt32 ( + IN INTN Operand, + OUT INT32 *Result + ); + +/** + INTN -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToUint32 ( + IN INTN Operand, + OUT UINT32 *Result + ); + +/** + INTN -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToUintn ( + IN INTN Operand, + OUT UINTN *Result + ); + +/** + INTN -> UINT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnToUint64 ( + IN INTN Operand, + OUT UINT64 *Result + ); + +/** + UINTN -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToInt8 ( + IN UINTN Operand, + OUT INT8 *Result + ); + +/** + UINTN -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToChar8 ( + IN UINTN Operand, + OUT CHAR8 *Result + ); + +/** + UINTN -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToUint8 ( + IN UINTN Operand, + OUT UINT8 *Result + ); + +/** + UINTN -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToInt16 ( + IN UINTN Operand, + OUT INT16 *Result + ); + +/** + UINTN -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToUint16 ( + IN UINTN Operand, + OUT UINT16 *Result + ); + +/** + UINTN -> INT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToInt32 ( + IN UINTN Operand, + OUT INT32 *Result + ); + +/** + UINTN -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToUint32 ( + IN UINTN Operand, + OUT UINT32 *Result + ); + +/** + UINTN -> INTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToIntn ( + IN UINTN Operand, + OUT INTN *Result + ); + +/** + UINTN -> INT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnToInt64 ( + IN UINTN Operand, + OUT INT64 *Result + ); + +/** + INT64 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToInt8 ( + IN INT64 Operand, + OUT INT8 *Result + ); + +/** + INT64 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToChar8 ( + IN INT64 Operand, + OUT CHAR8 *Result + ); + +/** + INT64 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToUint8 ( + IN INT64 Operand, + OUT UINT8 *Result + ); + +/** + INT64 -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToInt16 ( + IN INT64 Operand, + OUT INT16 *Result + ); + +/** + INT64 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToUint16 ( + IN INT64 Operand, + OUT UINT16 *Result + ); + +/** + INT64 -> INT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToInt32 ( + IN INT64 Operand, + OUT INT32 *Result + ); + +/** + INT64 -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToUint32 ( + IN INT64 Operand, + OUT UINT32 *Result + ); + +/** + INT64 -> INTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToIntn ( + IN INT64 Operand, + OUT INTN *Result + ); + +/** + INT64 -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToUintn ( + IN INT64 Operand, + OUT UINTN *Result + ); + +/** + INT64 -> UINT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64ToUint64 ( + IN INT64 Operand, + OUT UINT64 *Result + ); + +/** + UINT64 -> INT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToInt8 ( + IN UINT64 Operand, + OUT INT8 *Result + ); + +/** + UINT64 -> CHAR8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToChar8 ( + IN UINT64 Operand, + OUT CHAR8 *Result + ); + +/** + UINT64 -> UINT8 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToUint8 ( + IN UINT64 Operand, + OUT UINT8 *Result + ); + +/** + UINT64 -> INT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToInt16 ( + IN UINT64 Operand, + OUT INT16 *Result + ); + +/** + UINT64 -> UINT16 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToUint16 ( + IN UINT64 Operand, + OUT UINT16 *Result + ); + +/** + UINT64 -> INT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToInt32 ( + IN UINT64 Operand, + OUT INT32 *Result + ); + +/** + UINT64 -> UINT32 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToUint32 ( + IN UINT64 Operand, + OUT UINT32 *Result + ); + +/** + UINT64 -> INTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToIntn ( + IN UINT64 Operand, + OUT INTN *Result + ); + +/** + UINT64 -> UINTN conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToUintn ( + IN UINT64 Operand, + OUT UINTN *Result + ); + +/** + UINT64 -> INT64 conversion + + Converts the value specified by Operand to a value specified by Result type + and stores the converted value into the caller allocated output buffer + specified by Result. The caller must pass in a Result buffer that is at + least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the conversion results in an overflow or an underflow condition, then + Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Operand Operand to be converted to new type + @param[out] Result Pointer to the result of conversion + + @retval RETURN_SUCCESS Successful conversion + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64ToInt64 ( + IN UINT64 Operand, + OUT INT64 *Result + ); + +// +// Addition functions +// + +/** + UINT8 addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint8Add ( + IN UINT8 Augend, + IN UINT8 Addend, + OUT UINT8 *Result + ); + +/** + UINT16 addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16Add ( + IN UINT16 Augend, + IN UINT16 Addend, + OUT UINT16 *Result + ); + +/** + UINT32 addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32Add ( + IN UINT32 Augend, + IN UINT32 Addend, + OUT UINT32 *Result + ); + +/** + UINTN addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnAdd ( + IN UINTN Augend, + IN UINTN Addend, + OUT UINTN *Result + ); + +/** + UINT64 addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64Add ( + IN UINT64 Augend, + IN UINT64 Addend, + OUT UINT64 *Result + ); + +// +// Subtraction functions +// + +/** + UINT8 subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint8Sub ( + IN UINT8 Minuend, + IN UINT8 Subtrahend, + OUT UINT8 *Result + ); + +/** + UINT16 subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16Sub ( + IN UINT16 Minuend, + IN UINT16 Subtrahend, + OUT UINT16 *Result + ); + +/** + UINT32 subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32Sub ( + IN UINT32 Minuend, + IN UINT32 Subtrahend, + OUT UINT32 *Result + ); + +/** + UINTN subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnSub ( + IN UINTN Minuend, + IN UINTN Subtrahend, + OUT UINTN *Result + ); + +/** + UINT64 subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64Sub ( + IN UINT64 Minuend, + IN UINT64 Subtrahend, + OUT UINT64 *Result + ); + +// +// Multiplication functions +// + +/** + UINT8 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint8Mult ( + IN UINT8 Multiplicand, + IN UINT8 Multiplier, + OUT UINT8 *Result + ); + +/** + UINT16 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint16Mult ( + IN UINT16 Multiplicand, + IN UINT16 Multiplier, + OUT UINT16 *Result + ); + +/** + UINT32 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint32Mult ( + IN UINT32 Multiplicand, + IN UINT32 Multiplier, + OUT UINT32 *Result + ); + +/** + UINTN multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUintnMult ( + IN UINTN Multiplicand, + IN UINTN Multiplier, + OUT UINTN *Result + ); + +/** + UINT64 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeUint64Mult ( + IN UINT64 Multiplicand, + IN UINT64 Multiplier, + OUT UINT64 *Result + ); + +// +// Signed operations +// +// Strongly consider using unsigned numbers. +// +// Signed numbers are often used where unsigned numbers should be used. +// For example file sizes and array indices should always be unsigned. +// Subtracting a larger positive signed number from a smaller positive +// signed number with SafeInt32Sub will succeed, producing a negative number, +// that then must not be used as an array index (but can occasionally be +// used as a pointer index.) Similarly for adding a larger magnitude +// negative number to a smaller magnitude positive number. +// +// This library does not protect you from such errors. It tells you if your +// integer operations overflowed, not if you are doing the right thing +// with your non-overflowed integers. +// +// Likewise you can overflow a buffer with a non-overflowed unsigned index. +// + +// +// Signed addition functions +// + +/** + INT8 Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8Add ( + IN INT8 Augend, + IN INT8 Addend, + OUT INT8 *Result + ); + +/** + CHAR8 Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeChar8Add ( + IN CHAR8 Augend, + IN CHAR8 Addend, + OUT CHAR8 *Result + ); + +/** + INT16 Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16Add ( + IN INT16 Augend, + IN INT16 Addend, + OUT INT16 *Result + ); + +/** + INT32 Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32Add ( + IN INT32 Augend, + IN INT32 Addend, + OUT INT32 *Result + ); + +/** + INTN Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnAdd ( + IN INTN Augend, + IN INTN Addend, + OUT INTN *Result + ); + +/** + INT64 Addition + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Augend A number to which addend will be added + @param[in] Addend A number to be added to another + @param[out] Result Pointer to the result of addition + + @retval RETURN_SUCCESS Successful addition + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64Add ( + IN INT64 Augend, + IN INT64 Addend, + OUT INT64 *Result + ); + +// +// Signed subtraction functions +// + +/** + INT8 Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8Sub ( + IN INT8 Minuend, + IN INT8 Subtrahend, + OUT INT8 *Result + ); + +/** + CHAR8 Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeChar8Sub ( + IN CHAR8 Minuend, + IN CHAR8 Subtrahend, + OUT CHAR8 *Result + ); + +/** + INT16 Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16Sub ( + IN INT16 Minuend, + IN INT16 Subtrahend, + OUT INT16 *Result + ); + +/** + INT32 Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32Sub ( + IN INT32 Minuend, + IN INT32 Subtrahend, + OUT INT32 *Result + ); + +/** + INTN Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnSub ( + IN INTN Minuend, + IN INTN Subtrahend, + OUT INTN *Result + ); + +/** + INT64 Subtraction + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Minuend A number from which another is to be subtracted. + @param[in] Subtrahend A number to be subtracted from another + @param[out] Result Pointer to the result of subtraction + + @retval RETURN_SUCCESS Successful subtraction + @retval RETURN_BUFFER_TOO_SMALL Underflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64Sub ( + IN INT64 Minuend, + IN INT64 Subtrahend, + OUT INT64 *Result + ); + +// +// Signed multiplication functions +// + +/** + INT8 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt8Mult ( + IN INT8 Multiplicand, + IN INT8 Multiplier, + OUT INT8 *Result + ); + +/** + CHAR8 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeChar8Mult ( + IN CHAR8 Multiplicand, + IN CHAR8 Multiplier, + OUT CHAR8 *Result + ); + +/** + INT16 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt16Mult ( + IN INT16 Multiplicand, + IN INT16 Multiplier, + OUT INT16 *Result + ); + +/** + INT32 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt32Mult ( + IN INT32 Multiplicand, + IN INT32 Multiplier, + OUT INT32 *Result + ); + +/** + INTN multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeIntnMult ( + IN INTN Multiplicand, + IN INTN Multiplier, + OUT INTN *Result + ); + +/** + INT64 multiplication + + Performs the requested operation using the input parameters into a value + specified by Result type and stores the converted value into the caller + allocated output buffer specified by Result. The caller must pass in a + Result buffer that is at least as large as the Result type. + + If Result is NULL, RETURN_INVALID_PARAMETER is returned. + + If the requested operation results in an overflow or an underflow condition, + then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned. + + @param[in] Multiplicand A number that is to be multiplied by another + @param[in] Multiplier A number by which the multiplicand is to be multiplied + @param[out] Result Pointer to the result of multiplication + + @retval RETURN_SUCCESS Successful multiplication + @retval RETURN_BUFFER_TOO_SMALL Overflow + @retval RETURN_INVALID_PARAMETER Result is NULL +**/ +RETURN_STATUS +EFIAPI +SafeInt64Mult ( + IN INT64 Multiplicand, + IN INT64 Multiplier, + OUT INT64 *Result + ); + +#endif // __INT_SAFE_LIB_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SerialPortLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SerialPortLib.h new file mode 100644 index 0000000000..1cd57656f2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SerialPortLib.h @@ -0,0 +1,174 @@ +/** @file + This library class provides common serial I/O port functions. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SERIAL_PORT_LIB__ +#define __SERIAL_PORT_LIB__ + +#include +#include + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ); + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial device. + If this value is less than NumberOfBytes, then the write operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + + +/** + Read data from serial device and save the datas in buffer. + + Reads NumberOfBytes data bytes from a serial device into the buffer + specified by Buffer. The number of bytes actually read is returned. + If the return value is less than NumberOfBytes, then the rest operation failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to store the data read from the serial device. + @param NumberOfBytes Number of bytes which will be read. + + @retval 0 Read data failed, no data is to be read. + @retval >0 Actual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ); + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ); + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ); + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control signals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ); + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmbusLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmbusLib.h new file mode 100644 index 0000000000..ac747bc747 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmbusLib.h @@ -0,0 +1,491 @@ +/** @file + Provides library functions to access SMBUS devices. Libraries of this class + must be ported to a specific SMBUS controller. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMBUS_LIB__ +#define __SMBUS_LIB__ + +/** + Macro that converts SMBUS slave address, SMBUS command, SMBUS data length, + and PEC to a value that can be passed to the SMBUS Library functions. + + Computes an address that is compatible with the SMBUS Library functions. + The unused upper bits of SlaveAddress, Command, and Length are stripped + prior to the generation of the address. + + @param SlaveAddress SMBUS Slave Address. Range 0..127. + @param Command SMBUS Command. Range 0..255. + @param Length SMBUS Data Length. Range 0..32. + @param Pec TRUE if Packet Error Checking is enabled. Otherwise FALSE. + +**/ +#define SMBUS_LIB_ADDRESS(SlaveAddress,Command,Length,Pec) \ + ( ((Pec) ? BIT22: 0) | \ + (((SlaveAddress) & 0x7f) << 1) | \ + (((Command) & 0xff) << 8) | \ + (((Length) & 0x3f) << 16) \ + ) + +/** + Macro that returns the SMBUS Slave Address value from an SmBusAddress Parameter value. + + @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC +**/ +#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f) + +/** + Macro that returns the SMBUS Command value from an SmBusAddress Parameter value. + + @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC +**/ +#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff) + +/** + Macro that returns the SMBUS Data Length value from an SmBusAddress Parameter value. + + @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC +**/ +#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f) + +/** + Macro that returns the SMBUS PEC value from an SmBusAddress Parameter value. + + @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC +**/ +#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0)) + +/** + Macro that returns the set of reserved bits from an SmBusAddress Parameter value. + + @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC +**/ +#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2)) + +/** + Executes an SMBUS quick read command. + + Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is returned in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_UNSUPPORTED The SMBus operation is not supported. + +**/ +VOID +EFIAPI +SmBusQuickRead ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS quick write command. + + Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is returned in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_UNSUPPORTED The SMBus operation is not supported. + +**/ +VOID +EFIAPI +SmBusQuickWrite ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS receive byte command. + + Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + The byte received from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte received from the SMBUS. + +**/ +UINT8 +EFIAPI +SmBusReceiveByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS send byte command. + + Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress. + The byte specified by Value is sent. + Only the SMBUS slave address field of SmBusAddress is required. Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Value The 8-bit value to send. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT8 +EFIAPI +SmBusSendByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read data byte command. + + Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 8-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte read from the SMBUS. + +**/ +UINT8 +EFIAPI +SmBusReadDataByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write data byte command. + + Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress. + The 8-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Value The 8-bit value to write. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT8 +EFIAPI +SmBusWriteDataByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read data word command. + + Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 16-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The byte read from the SMBUS. + +**/ +UINT16 +EFIAPI +SmBusReadDataWord ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write data word command. + + Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Value is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Value The 16-bit value to write. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +SmBusWriteDataWord ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS process call command. + + Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + The 16-bit value returned by the process call command is returned. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Value The 16-bit value to write. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The 16-bit value returned by the process call command. + +**/ +UINT16 +EFIAPI +SmBusProcessCall ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS read block command. + + Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required. + Bytes are read from the SMBUS and stored in Buffer. + The number of bytes read is returned, and will never return a value larger than 32-bytes. + If Status is not NULL, then the status of the executed command is returned in Status. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes. + If Length in SmBusAddress is not zero, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Buffer Pointer to the buffer to store the bytes read from the SMBUS. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_SUCCESS The SMBUS command was executed. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes read. + +**/ +UINTN +EFIAPI +SmBusReadBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS write block command. + + Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required. + Bytes are written to the SMBUS from Buffer. + The number of bytes written is returned, and will never return a value larger than 32-bytes. + If Status is not NULL, then the status of the executed command is returned in Status. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param Buffer Pointer to the buffer to store the bytes read from the SMBUS. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes written. + +**/ +UINTN +EFIAPI +SmBusWriteBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + +/** + Executes an SMBUS block process call command. + + Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required. + Bytes are written to the SMBUS from WriteBuffer. Bytes are then read from the SMBUS into ReadBuffer. + If Status is not NULL, then the status of the executed command is returned in Status. + It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If WriteBuffer is NULL, then ASSERT(). + If ReadBuffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param WriteBuffer Pointer to the buffer of bytes to write to the SMBUS. + @param ReadBuffer Pointer to the buffer of bytes to read from the SMBUS. + @param Status Return status for the executed command. + This is an optional parameter and may be NULL. + RETURN_TIMEOUT A timeout occurred while executing the SMBUS command. + RETURN_DEVICE_ERROR The request was not completed because a failure + reflected in the Host Status Register bit. Device errors are a result + of a transaction collision, illegal command field, unclaimed cycle + (host initiated), or bus errors (collisions). + RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect) + RETURN_UNSUPPORTED The SMBus operation is not supported. + + @return The number of bytes written. + +**/ +UINTN +EFIAPI +SmBusBlockProcessCall ( + IN UINTN SmBusAddress, + IN VOID *WriteBuffer, + OUT VOID *ReadBuffer, + OUT RETURN_STATUS *Status OPTIONAL + ); + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmiHandlerProfileLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmiHandlerProfileLib.h new file mode 100644 index 0000000000..3db65f9e35 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmiHandlerProfileLib.h @@ -0,0 +1,81 @@ +/** @file + Provides services to log the SMI handler registration. + + This API provides services for the SMM Child Dispatch Protocols provider, + to register SMI handler information to SmmCore. + + NOTE: + There is no need to update the consumers of SMST->SmiHandlerRegister() or + the consumers of SMM Child Dispatch Protocols. + The SmmCore (who produces SMST) should have ability to register such + information directly. + The SmmChildDispatcher (who produces SMM Child Dispatch Protocols) should + be responsible to call the services to register information to SMM Core. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMI_HANDLER_PROFILE_LIB_H__ +#define __SMI_HANDLER_PROFILE_LIB_H__ + +#include + +/** + This function is called by SmmChildDispatcher module to report + a new SMI handler is registered, to SmmCore. + + @param HandlerGuid The GUID to identify the type of the handler. + For the SmmChildDispatch protocol, the HandlerGuid + must be the GUID of SmmChildDispatch protocol. + @param Handler The SMI handler. + @param CallerAddress The address of the module who registers the SMI handler. + @param Context The context of the SMI handler. + For the SmmChildDispatch protocol, the Context + must match the one defined for SmmChildDispatch protocol. + @param ContextSize The size of the context in bytes. + For the SmmChildDispatch protocol, the Context + must match the one defined for SmmChildDispatch protocol. + + @retval EFI_SUCCESS The information is recorded. + @retval EFI_UNSUPPORTED The feature is unsupported. + @retval EFI_OUT_OF_RESOURCES There is no enough resource to record the information. +**/ +EFI_STATUS +EFIAPI +SmiHandlerProfileRegisterHandler ( + IN EFI_GUID *HandlerGuid, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler, + IN PHYSICAL_ADDRESS CallerAddress, + IN VOID *Context, OPTIONAL + IN UINTN ContextSize OPTIONAL + ); + +/** + This function is called by SmmChildDispatcher module to report + an existing SMI handler is unregistered, to SmmCore. + + @param HandlerGuid The GUID to identify the type of the handler. + For the SmmChildDispatch protocol, the HandlerGuid + must be the GUID of SmmChildDispatch protocol. + @param Handler The SMI handler. + @param Context The context of the SMI handler. + If it is NOT NULL, it will be used to check what is registered. + @param ContextSize The size of the context in bytes. + If Context is NOT NULL, it will be used to check what is registered. + + @retval EFI_SUCCESS The original record is removed. + @retval EFI_UNSUPPORTED The feature is unsupported. + @retval EFI_NOT_FOUND There is no record for the HandlerGuid and handler. +**/ +EFI_STATUS +EFIAPI +SmiHandlerProfileUnregisterHandler ( + IN EFI_GUID *HandlerGuid, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler, + IN VOID *Context, OPTIONAL + IN UINTN ContextSize OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmIoLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmIoLib.h new file mode 100644 index 0000000000..49b45f8890 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmIoLib.h @@ -0,0 +1,36 @@ +/** @file + Provides services for SMM IO Operation. + + The SMM IO Library provides function for checking if IO resource is accessible inside of SMM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_IO_LIB_H_ +#define _SMM_IO_LIB_H_ + +/** + This function check if the MMIO resource is valid per processor architecture and + valid per platform design. + + @param BaseAddress The MMIO start address to be checked. + @param Length The MMIO length to be checked. + @param Owner A GUID representing the owner of the resource. + This GUID may be used by producer to correlate the device ownership of the resource. + NULL means no specific owner. + + @retval TRUE This MMIO resource is valid per processor architecture and valid per platform design. + @retval FALSE This MMIO resource is not valid per processor architecture or valid per platform design. +**/ +BOOLEAN +EFIAPI +SmmIsMmioValid ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN EFI_GUID *Owner OPTIONAL + ); + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmLib.h new file mode 100644 index 0000000000..7623ce2e1c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmLib.h @@ -0,0 +1,83 @@ +/** @file + Library class name: SmmLib + + SMM Library Services that abstracts both S/W SMI generation and detection. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMM_LIB_H__ +#define __SMM_LIB_H__ + + +/** + Triggers an SMI at boot time. + + This function triggers a software SMM interrupt at boot time. + +**/ +VOID +EFIAPI +TriggerBootServiceSoftwareSmi ( + VOID + ); + + +/** + Triggers an SMI at run time. + + This function triggers a software SMM interrupt at run time. + +**/ +VOID +EFIAPI +TriggerRuntimeSoftwareSmi ( + VOID + ); + + +/** + Test if a boot time software SMI happened. + + This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and + it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE. + + @retval TRUE A software SMI triggered at boot time happened. + @retval FALSE No software SMI happened, or the software SMI was triggered at run time. + +**/ +BOOLEAN +EFIAPI +IsBootServiceSoftwareSmi ( + VOID + ); + + +/** + Test if a run time software SMI happened. + + This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and + it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE. + + @retval TRUE A software SMI triggered at run time happened. + @retval FALSE No software SMI happened or the software SMI was triggered at boot time. + +**/ +BOOLEAN +EFIAPI +IsRuntimeSoftwareSmi ( + VOID + ); + +/** + Clear APM SMI Status Bit; Set the EOS bit. + +**/ +VOID +EFIAPI +ClearSmi ( + VOID + ); +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmMemLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmMemLib.h new file mode 100644 index 0000000000..feb81d11c9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmMemLib.h @@ -0,0 +1,132 @@ +/** @file + Provides services for SMM Memory Operation. + + The SMM Mem Library provides function for checking if buffer is outside SMRAM and valid. + It also provides functions for copy data from SMRAM to non-SMRAM, from non-SMRAM to SMRAM, + from non-SMRAM to non-SMRAM, or set data in non-SMRAM. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_MEM_LIB_H_ +#define _SMM_MEM_LIB_H_ + +/** + This function check if the buffer is valid per processor architecture and not overlap with SMRAM. + + @param Buffer The buffer start address to be checked. + @param Length The buffer length to be checked. + + @retval TRUE This buffer is valid per processor architecture and not overlap with SMRAM. + @retval FALSE This buffer is not valid per processor architecture or overlap with SMRAM. +**/ +BOOLEAN +EFIAPI +SmmIsBufferOutsideSmmValid ( + IN EFI_PHYSICAL_ADDRESS Buffer, + IN UINT64 Length + ); + +/** + Copies a source buffer (non-SMRAM) to a destination buffer (SMRAM). + + This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM). + It checks if source buffer is valid per processor architecture and not overlap with SMRAM. + If the check passes, it copies memory and returns EFI_SUCCESS. + If the check fails, it return EFI_SECURITY_VIOLATION. + The implementation must be reentrant. + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @retval EFI_SECURITY_VIOLATION The SourceBuffer is invalid per processor architecture or overlap with SMRAM. + @retval EFI_SUCCESS Memory is copied. + +**/ +EFI_STATUS +EFIAPI +SmmCopyMemToSmram ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Copies a source buffer (SMRAM) to a destination buffer (NON-SMRAM). + + This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM). + It checks if destination buffer is valid per processor architecture and not overlap with SMRAM. + If the check passes, it copies memory and returns EFI_SUCCESS. + If the check fails, it returns EFI_SECURITY_VIOLATION. + The implementation must be reentrant. + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM. + @retval EFI_SUCCESS Memory is copied. + +**/ +EFI_STATUS +EFIAPI +SmmCopyMemFromSmram ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Copies a source buffer (NON-SMRAM) to a destination buffer (NON-SMRAM). + + This function copies a source buffer (non-SMRAM) to a destination buffer (SMRAM). + It checks if source buffer and destination buffer are valid per processor architecture and not overlap with SMRAM. + If the check passes, it copies memory and returns EFI_SUCCESS. + If the check fails, it returns EFI_SECURITY_VIOLATION. + The implementation must be reentrant, and it must handle the case where source buffer overlaps destination buffer. + + @param DestinationBuffer The pointer to the destination buffer of the memory copy. + @param SourceBuffer The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from SourceBuffer to DestinationBuffer. + + @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM. + @retval EFI_SECURITY_VIOLATION The SourceBuffer is invalid per processor architecture or overlap with SMRAM. + @retval EFI_SUCCESS Memory is copied. + +**/ +EFI_STATUS +EFIAPI +SmmCopyMem ( + OUT VOID *DestinationBuffer, + IN CONST VOID *SourceBuffer, + IN UINTN Length + ); + +/** + Fills a target buffer (NON-SMRAM) with a byte value. + + This function fills a target buffer (non-SMRAM) with a byte value. + It checks if target buffer is valid per processor architecture and not overlap with SMRAM. + If the check passes, it fills memory and returns EFI_SUCCESS. + If the check fails, it returns EFI_SECURITY_VIOLATION. + + @param Buffer The memory to set. + @param Length The number of bytes to set. + @param Value The value with which to fill Length bytes of Buffer. + + @retval EFI_SECURITY_VIOLATION The Buffer is invalid per processor architecture or overlap with SMRAM. + @retval EFI_SUCCESS Memory is set. + +**/ +EFI_STATUS +EFIAPI +SmmSetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmPeriodicSmiLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmPeriodicSmiLib.h new file mode 100644 index 0000000000..c9682be2c8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmPeriodicSmiLib.h @@ -0,0 +1,178 @@ +/** @file + Provides services to enable and disable periodic SMI handlers. + +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PERIODIC_SMI_LIB_H__ +#define __PERIODIC_SMI_LIB_H__ + +#define PERIODIC_SMI_LIBRARY_ANY_CPU 0xffffffff + +/** + This function returns a pointer to a table of supported periodic + SMI tick periods in 100 ns units sorted from largest to smallest. + The table contains a array of UINT64 values terminated by a tick + period value of 0. The returned table must be treated as read-only + data and must not be freed. + + @return A pointer to a table of UINT64 tick period values in + 100ns units sorted from largest to smallest terminated + by a tick period of 0. + +**/ +UINT64 * +EFIAPI +PeriodicSmiSupportedTickPeriod ( + VOID + ); + +/** + This function returns the time in 100ns units since the periodic SMI + handler function was called. If the periodic SMI handler was resumed + through PeriodicSmiYield(), then the time returned is the time in + 100ns units since PeriodicSmiYield() returned. + + @return The actual time in 100ns units that the periodic SMI handler + has been executing. If this function is not called from within + an enabled periodic SMI handler, then 0 is returned. + +**/ +UINT64 +EFIAPI +PeriodicSmiExecutionTime ( + VOID + ); + +/** + This function returns control back to the SMM Foundation. When the next + periodic SMI for the currently executing handler is triggered, the periodic + SMI handler will restarted from its registered DispatchFunction entry point. + If this function is not called from within an enabled periodic SMI handler, + then control is returned to the calling function. + +**/ +VOID +EFIAPI +PeriodicSmiExit ( + VOID + ); + +/** + This function yields control back to the SMM Foundation. When the next + periodic SMI for the currently executing handler is triggered, the periodic + SMI handler will be resumed and this function will return. Use of this + function requires a separate stack for the periodic SMI handler. A non zero + stack size must be specified in PeriodicSmiEnable() for this function to be + used. + + If the stack size passed into PeriodicSmiEnable() was zero, the 0 is returned. + + If this function is not called from within an enabled periodic SMI handler, + then 0 is returned. + + @return The actual time in 100ns units elapsed since this function was + called. A value of 0 indicates an unknown amount of time. + +**/ +UINT64 +EFIAPI +PeriodicSmiYield ( + VOID + ); + +/** + This function is a prototype for a periodic SMI handler function + that may be enabled with PeriodicSmiEnable() and disabled with + PeriodicSmiDisable(). + + @param[in] Context Content registered with PeriodicSmiEnable(). + @param[in] ElapsedTime The actual time in 100ns units elapsed since + this function was called. A value of 0 indicates + an unknown amount of time. + +**/ +typedef +VOID +(EFIAPI *PERIODIC_SMI_LIBRARY_HANDLER) ( + IN CONST VOID *Context OPTIONAL, + IN UINT64 ElapsedTime + ); + +/** + This function enables a periodic SMI handler. + + @param[in, out] DispatchHandle A pointer to the handle associated with the + enabled periodic SMI handler. This is an + optional parameter that may be NULL. If it is + NULL, then the handle will not be returned, + which means that the periodic SMI handler can + never be disabled. + @param[in] DispatchFunction A pointer to a periodic SMI handler function. + @param[in] Context Optional content to pass into DispatchFunction. + @param[in] TickPeriod The requested tick period in 100ns units that + control should be given to the periodic SMI + handler. Must be one of the supported values + returned by PeriodicSmiSupportedPickPeriod(). + @param[in] Cpu Specifies the CPU that is required to execute + the periodic SMI handler. If Cpu is + PERIODIC_SMI_LIBRARY_ANY_CPU, then the periodic + SMI handler will always be executed on the SMST + CurrentlyExecutingCpu, which may vary across + periodic SMIs. If Cpu is between 0 and the SMST + NumberOfCpus, then the periodic SMI will always + be executed on the requested CPU. + @param[in] StackSize The size, in bytes, of the stack to allocate for + use by the periodic SMI handler. If 0, then the + default stack will be used. + + @retval EFI_INVALID_PARAMETER DispatchFunction is NULL. + @retval EFI_UNSUPPORTED TickPeriod is not a supported tick period. The + supported tick periods can be retrieved using + PeriodicSmiSupportedTickPeriod(). + @retval EFI_INVALID_PARAMETER Cpu is not PERIODIC_SMI_LIBRARY_ANY_CPU or in + the range 0 to SMST NumberOfCpus. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to enable the + periodic SMI handler. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the + stack specified by StackSize. + @retval EFI_SUCCESS The periodic SMI handler was enabled. + +**/ +EFI_STATUS +EFIAPI +PeriodicSmiEnable ( + IN OUT EFI_HANDLE *DispatchHandle, OPTIONAL + IN PERIODIC_SMI_LIBRARY_HANDLER DispatchFunction, + IN CONST VOID *Context, OPTIONAL + IN UINT64 TickPeriod, + IN UINTN Cpu, + IN UINTN StackSize + ); + +/** + This function disables a periodic SMI handler that has been previously + enabled with PeriodicSmiEnable(). + + @param[in] DispatchHandle A handle associated with a previously enabled periodic + SMI handler. This is an optional parameter that may + be NULL. If it is NULL, then the active periodic SMI + handlers is disabled. + + @retval FALSE DispatchHandle is NULL and there is no active periodic SMI handler. + @retval FALSE The periodic SMI handler specified by DispatchHandle has + not been enabled with PeriodicSmiEnable(). + @retval TRUE The periodic SMI handler specified by DispatchHandle has + been disabled. If DispatchHandle is NULL, then the active + periodic SMI handler has been disabled. + +**/ +BOOLEAN +EFIAPI +PeriodicSmiDisable ( + IN EFI_HANDLE DispatchHandle OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmServicesTableLib.h new file mode 100644 index 0000000000..110d70b89c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SmmServicesTableLib.h @@ -0,0 +1,37 @@ +/** @file + Provides a service to retrieve a pointer to the SMM Services Table. + Only available to SMM module types. + +Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMM_SERVICES_TABLE_LIB_H__ +#define __SMM_SERVICES_TABLE_LIB_H__ + +#include + +/// +/// Cache pointer to the SMM Services Table +/// +extern EFI_SMM_SYSTEM_TABLE2 *gSmst; + +/** + This function allows the caller to determine if the driver is executing in + System Management Mode(SMM). + + This function returns TRUE if the driver is executing in SMM and FALSE if the + driver is not executing in SMM. + + @retval TRUE The driver is executing in System Management Mode (SMM). + @retval FALSE The driver is not executing in System Management Mode (SMM). + +**/ +BOOLEAN +EFIAPI +InSmm ( + VOID + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h new file mode 100644 index 0000000000..a26fdcca63 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h @@ -0,0 +1,150 @@ +/** @file + Module entry point library for Standalone MM Drivers. + +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.
+Copyright (c) 2018, Linaro, Limited. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/// +/// Declare the PI Specification Revision that this driver requires to execute +/// correctly. +/// +extern CONST UINT32 _gMmRevision; + +/// +/// Declare the number of unload handler in the image. +/// +extern CONST UINT8 _gDriverUnloadImageCount; + +/** + The entry point of PE/COFF Image for a Standalone MM Driver. + + This function is the entry point for a Standalone MM Driver. + This function must call ProcessLibraryConstructorList() and + ProcessModuleEntryPointList(). + If the return status from ProcessModuleEntryPointList() + is an error status, then ProcessLibraryDestructorList() must be called. + The return value from ProcessModuleEntryPointList() is returned. + If _gMmRevision is not zero and MmSystemTable->Hdr.Revision is + less than _gMmRevision, then return EFI_INCOMPATIBLE_VERSION. + + @param ImageHandle The image handle of the Standalone MM Driver. + @param MmSystemTable A pointer to the MM System Table. + + @retval EFI_SUCCESS The Standalone MM Driver exited normally. + @retval EFI_INCOMPATIBLE_VERSION _gMmRevision is greater than + MmSystemTable->Hdr.Revision. + @retval Other Return value from + ProcessModuleEntryPointList(). + +**/ +EFI_STATUS +EFIAPI +_ModuleEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ); + + +/** + Auto generated function that calls the library constructors for all of the + module's dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library + instances that a module depends on. This includes library instances that a + module depends on directly and library instances that a module depends on + indirectly through other libraries. This function is auto generated by build + tools and those build tools are responsible for collecting the set of library + instances, determine which ones have constructors, and calling the library + constructors in the proper order based upon each of the library instances own + dependencies. + + @param ImageHandle The image handle of the Standalone MM Driver. + @param MmSystemTable A pointer to the MM System Table. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ); + + +/** + Auto generated function that calls the library descructors for all of the + module's dependent libraries. + + This function may be called by _ModuleEntryPoint(). + This function calls the set of library destructors for the set of library + instances that a module depends on. This includes library instances that a + module depends on directly and library instances that a module depends on + indirectly through other libraries. + This function is auto generated by build tools and those build tools are + responsible for collecting the set of library instances, determine which ones + have destructors, and calling the library destructors in the proper order + based upon each of the library instances own dependencies. + + @param ImageHandle The image handle of the Standalone MM Driver. + @param MmSystemTable A pointer to the MM System Table. + +**/ +VOID +EFIAPI +ProcessLibraryDestructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ); + + +/** + Auto generated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is auto generated by build tools and those build tools are + responsible for collecting the module entry points and calling them in a + specified order. + + @param ImageHandle The image handle of the Standalone MM Driver. + @param MmSystemTable A pointer to the MM System Table. + + @retval EFI_SUCCESS The Standalone MM Driver executed normally. + @retval !EFI_SUCCESS The Standalone MM Driver failed to execute normally. +**/ +EFI_STATUS +EFIAPI +ProcessModuleEntryPointList ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ); + +/** + Autogenerated function that calls a set of module unload handlers. + + This function must be called from the unload handler registered by _ModuleEntryPoint(). + This function calls the set of module unload handlers. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module unload handlers and calling them in a specified order. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + + @retval EFI_SUCCESS The unload handlers executed normally. + @retval !EFI_SUCCESS The unload handlers failed to execute normally. + +**/ +EFI_STATUS +EFIAPI +ProcessModuleUnloadList ( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SynchronizationLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SynchronizationLib.h new file mode 100644 index 0000000000..fc01b10cd4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/SynchronizationLib.h @@ -0,0 +1,287 @@ +/** @file + Provides synchronization functions. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SYNCHRONIZATION_LIB__ +#define __SYNCHRONIZATION_LIB__ + +/// +/// Definitions for SPIN_LOCK +/// +typedef volatile UINTN SPIN_LOCK; + + +/** + Retrieves the architecture-specific spin lock alignment requirements for + optimal spin lock performance. + + This function retrieves the spin lock alignment requirements for optimal + performance on a given CPU architecture. The spin lock alignment is byte alignment. + It must be a power of two and is returned by this function. If there are no alignment + requirements, then 1 must be returned. The spin lock synchronization + functions must function correctly if the spin lock size and alignment values + returned by this function are not used at all. These values are hints to the + consumers of the spin lock synchronization functions to obtain optimal spin + lock performance. + + @return The architecture-specific spin lock alignment. + +**/ +UINTN +EFIAPI +GetSpinLockProperties ( + VOID + ); + + +/** + Initializes a spin lock to the released state and returns the spin lock. + + This function initializes the spin lock specified by SpinLock to the released + state, and returns SpinLock. Optimal performance can be achieved by calling + GetSpinLockProperties() to determine the size and alignment requirements for + SpinLock. + + If SpinLock is NULL, then ASSERT(). + + @param SpinLock A pointer to the spin lock to initialize to the released + state. + + @return SpinLock in release state. + +**/ +SPIN_LOCK * +EFIAPI +InitializeSpinLock ( + OUT SPIN_LOCK *SpinLock + ); + + +/** + Waits until a spin lock can be placed in the acquired state. + + This function checks the state of the spin lock specified by SpinLock. If + SpinLock is in the released state, then this function places SpinLock in the + acquired state and returns SpinLock. Otherwise, this function waits + indefinitely for the spin lock to be released, and then places it in the + acquired state and returns SpinLock. All state transitions of SpinLock must + be performed using MP safe mechanisms. + + If SpinLock is NULL, then ASSERT(). + If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). + If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in + PcdSpinLockTimeout microseconds, then ASSERT(). + + @param SpinLock A pointer to the spin lock to place in the acquired state. + + @return SpinLock acquired lock. + +**/ +SPIN_LOCK * +EFIAPI +AcquireSpinLock ( + IN OUT SPIN_LOCK *SpinLock + ); + + +/** + Attempts to place a spin lock in the acquired state. + + This function checks the state of the spin lock specified by SpinLock. If + SpinLock is in the released state, then this function places SpinLock in the + acquired state and returns TRUE. Otherwise, FALSE is returned. All state + transitions of SpinLock must be performed using MP safe mechanisms. + + If SpinLock is NULL, then ASSERT(). + If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). + + @param SpinLock A pointer to the spin lock to place in the acquired state. + + @retval TRUE SpinLock was placed in the acquired state. + @retval FALSE SpinLock could not be acquired. + +**/ +BOOLEAN +EFIAPI +AcquireSpinLockOrFail ( + IN OUT SPIN_LOCK *SpinLock + ); + + +/** + Releases a spin lock. + + This function places the spin lock specified by SpinLock in the release state + and returns SpinLock. + + If SpinLock is NULL, then ASSERT(). + If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). + + @param SpinLock A pointer to the spin lock to release. + + @return SpinLock released lock. + +**/ +SPIN_LOCK * +EFIAPI +ReleaseSpinLock ( + IN OUT SPIN_LOCK *SpinLock + ); + + +/** + Performs an atomic increment of a 32-bit unsigned integer. + + Performs an atomic increment of the 32-bit unsigned integer specified by + Value and returns the incremented value. The increment operation must be + performed using MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the 32-bit value to increment. + + @return The incremented value. + +**/ +UINT32 +EFIAPI +InterlockedIncrement ( + IN volatile UINT32 *Value + ); + + +/** + Performs an atomic decrement of a 32-bit unsigned integer. + + Performs an atomic decrement of the 32-bit unsigned integer specified by + Value and returns the decremented value. The decrement operation must be + performed using MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the 32-bit value to decrement. + + @return The decremented value. + +**/ +UINT32 +EFIAPI +InterlockedDecrement ( + IN volatile UINT32 *Value + ); + + +/** + Performs an atomic compare exchange operation on a 16-bit unsigned integer. + + Performs an atomic compare exchange operation on the 16-bit unsigned integer + specified by Value. If Value is equal to CompareValue, then Value is set to + ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue, + then Value is returned. The compare exchange operation must be performed using + MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the 16-bit value for the compare exchange + operation. + @param CompareValue 16-bit value used in compare operation. + @param ExchangeValue 16-bit value used in exchange operation. + + @return The original *Value before exchange. +**/ +UINT16 +EFIAPI +InterlockedCompareExchange16 ( + IN OUT volatile UINT16 *Value, + IN UINT16 CompareValue, + IN UINT16 ExchangeValue + ); + +/** + Performs an atomic compare exchange operation on a 32-bit unsigned integer. + + Performs an atomic compare exchange operation on the 32-bit unsigned integer + specified by Value. If Value is equal to CompareValue, then Value is set to + ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue, + then Value is returned. The compare exchange operation must be performed using + MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the 32-bit value for the compare exchange + operation. + @param CompareValue 32-bit value used in compare operation. + @param ExchangeValue 32-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT32 +EFIAPI +InterlockedCompareExchange32 ( + IN OUT volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue + ); + + +/** + Performs an atomic compare exchange operation on a 64-bit unsigned integer. + + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned. + The compare exchange operation must be performed using MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the 64-bit value for the compare exchange + operation. + @param CompareValue 64-bit value used in compare operation. + @param ExchangeValue 64-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT64 +EFIAPI +InterlockedCompareExchange64 ( + IN OUT volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ); + + +/** + Performs an atomic compare exchange operation on a pointer value. + + Performs an atomic compare exchange operation on the pointer value specified + by Value. If Value is equal to CompareValue, then Value is set to + ExchangeValue and CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange operation must be + performed using MP safe mechanisms. + + If Value is NULL, then ASSERT(). + + @param Value A pointer to the pointer value for the compare exchange + operation. + @param CompareValue Pointer value used in compare operation. + @param ExchangeValue Pointer value used in exchange operation. + + @return The original *Value before exchange. +**/ +VOID * +EFIAPI +InterlockedCompareExchangePointer ( + IN OUT VOID * volatile *Value, + IN VOID *CompareValue, + IN VOID *ExchangeValue + ); + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/TimerLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/TimerLib.h new file mode 100644 index 0000000000..a4c2d8818b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/TimerLib.h @@ -0,0 +1,108 @@ +/** @file + Provides calibrated delay and performance counter services. + +Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __TIMER_LIB__ +#define __TIMER_LIB__ + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds inputted. + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ); + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return The value of NanoSeconds inputted. + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ); + +/** + Retrieves the current value of a 64-bit free running performance counter. + + The counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ); + +/** + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ); + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiApplicationEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiApplicationEntryPoint.h new file mode 100644 index 0000000000..b5c00c1457 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiApplicationEntryPoint.h @@ -0,0 +1,148 @@ +/** @file + Module entry point library for UEFI Applications. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_APPLICATION_ENTRY_POINT_H__ +#define __UEFI_APPLICATION_ENTRY_POINT_H__ + +/// +/// Declare the EFI/UEFI Specification Revision to which this driver is implemented +/// +extern CONST UINT32 _gUefiDriverRevision; + + +/** + Entry point to UEFI Application. + + This function is the entry point for a UEFI Application. This function must call + ProcessLibraryConstructorList(), ProcessModuleEntryPointList(), and ProcessLibraryDestructorList(). + The return value from ProcessModuleEntryPointList() is returned. + If _gUefiDriverRevision is not zero and SystemTable->Hdr.Revision is less than _gUefiDriverRevison, + then return EFI_INCOMPATIBLE_VERSION. + + @param ImageHandle The image handle of the UEFI Application. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The UEFI Application exited normally. + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision. + @retval Other Return value from ProcessModuleEntryPointList(). + +**/ +EFI_STATUS +EFIAPI +_ModuleEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + @param ImageHandle The image handle of the UEFI Application. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The UEFI Application exited normally. + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision. + @retval Other Return value from ProcessModuleEntryPointList(). + +**/ +EFI_STATUS +EFIAPI +EfiMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Invokes the library destructors for all dependent libraries and terminates + the UEFI Application. + + This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit() + with a status specified by Status. + + @param Status Status returned by the application that is exiting. + +**/ +VOID +EFIAPI +Exit ( + IN EFI_STATUS Status + ); + + +/** + Autogenerated function that calls the library constructors for all of the module's + dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible for + collecting the set of library instances, determine which ones have constructors, and + calling the library constructors in the proper order based upon each of the library + instances own dependencies. + + @param ImageHandle The image handle of the UEFI Application. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Autogenerated function that calls the library descructors for all of the module's + dependent libraries. + + This function may be called by _ModuleEntryPoint()or Exit(). + This function calls the set of library destructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible + for collecting the set of library instances, determine which ones have destructors, + and calling the library destructors in the proper order based upon each of the library + instances own dependencies. + + @param ImageHandle The image handle of the UEFI Application. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryDestructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + This function calls the set of module entry points. It must be called by _ModuleEntryPoint(). + + This function is autogenerated by build tools and those build tools are + responsible for collecting the module entry points and calling them in a specified order. + + @param ImageHandle The image handle of the UEFI Application. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The UEFI Application executed normally. + @retval !EFI_SUCCESS The UEFI Application failed to execute normally. + +**/ +EFI_STATUS +EFIAPI +ProcessModuleEntryPointList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiBootServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiBootServicesTableLib.h new file mode 100644 index 0000000000..499071bc04 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiBootServicesTableLib.h @@ -0,0 +1,28 @@ +/** @file + Provides a service to retrieve a pointer to the EFI Boot Services Table. + Only available to DXE and UEFI module types. + +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_BOOT_SERVICES_TABLE_LIB_H__ +#define __UEFI_BOOT_SERVICES_TABLE_LIB_H__ + +/// +/// Cache the Image Handle +/// +extern EFI_HANDLE gImageHandle; + +/// +/// Cache pointer to the EFI System Table +/// +extern EFI_SYSTEM_TABLE *gST; + +/// +/// Cache pointer to the EFI Boot Services Table +/// +extern EFI_BOOT_SERVICES *gBS; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDecompressLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDecompressLib.h new file mode 100644 index 0000000000..510e80aa9c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDecompressLib.h @@ -0,0 +1,102 @@ +/** @file + Provides services to decompress a buffer using the UEFI Decompress algorithm. + + The UEFI Decompress Library enables the decompression of objects that + were compressed using the UEFI compression scheme. The UEFI Decompress + Library is independent of environment and requires the caller to allocate + all required memory buffers. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_DECPOMPRESS_LIB_H__ +#define __UEFI_DECPOMPRESS_LIB_H__ + +/** + Given a compressed source buffer, this function retrieves the size of + the uncompressed buffer and the size of the scratch buffer required + to decompress the compressed source buffer. + + Retrieves the size of the uncompressed buffer and the temporary scratch buffer + required to decompress the buffer specified by Source and SourceSize. + If the size of the uncompressed buffer or the size of the scratch buffer cannot + be determined from the compressed data specified by Source and SourceData, + then RETURN_INVALID_PARAMETER is returned. Otherwise, the size of the uncompressed + buffer is returned in DestinationSize, the size of the scratch buffer is returned + in ScratchSize, and RETURN_SUCCESS is returned. + This function does not have scratch buffer available to perform a thorough + checking of the validity of the source data. It just retrieves the "Original Size" + field from the beginning bytes of the source data and output it as DestinationSize. + And ScratchSize is specific to the decompression implementation. + + If Source is NULL, then ASSERT(). + If DestinationSize is NULL, then ASSERT(). + If ScratchSize is NULL, then ASSERT(). + + @param Source The source buffer containing the compressed data. + @param SourceSize The size, in bytes, of the source buffer. + @param DestinationSize A pointer to the size, in bytes, of the uncompressed buffer + that will be generated when the compressed buffer specified + by Source and SourceSize is decompressed. + @param ScratchSize A pointer to the size, in bytes, of the scratch buffer that + is required to decompress the compressed buffer specified + by Source and SourceSize. + + @retval RETURN_SUCCESS The size of the uncompressed data was returned + in DestinationSize and the size of the scratch + buffer was returned in ScratchSize. + @retval RETURN_INVALID_PARAMETER + The size of the uncompressed data or the size of + the scratch buffer cannot be determined from + the compressed data specified by Source + and SourceSize. +**/ +RETURN_STATUS +EFIAPI +UefiDecompressGetInfo ( + IN CONST VOID *Source, + IN UINT32 SourceSize, + OUT UINT32 *DestinationSize, + OUT UINT32 *ScratchSize + ); + +/** + Decompresses a compressed source buffer. + + Extracts decompressed data to its original form. + This function is designed so that the decompression algorithm can be implemented + without using any memory services. As a result, this function is not allowed to + call any memory allocation services in its implementation. It is the caller's + responsibility to allocate and free the Destination and Scratch buffers. + If the compressed source data specified by Source is successfully decompressed + into Destination, then RETURN_SUCCESS is returned. If the compressed source data + specified by Source is not in a valid compressed data format, + then RETURN_INVALID_PARAMETER is returned. + + If Source is NULL, then ASSERT(). + If Destination is NULL, then ASSERT(). + If the required scratch buffer size > 0 and Scratch is NULL, then ASSERT(). + + @param Source The source buffer containing the compressed data. + @param Destination The destination buffer to store the decompressed data + @param Scratch A temporary scratch buffer that is used to perform the decompression. + This is an optional parameter that may be NULL if the + required scratch buffer size is 0. + + @retval RETURN_SUCCESS Decompression completed successfully, and + the uncompressed buffer is returned in Destination. + @retval RETURN_INVALID_PARAMETER + The source buffer specified by Source is corrupted + (not in a valid compressed format). +**/ +RETURN_STATUS +EFIAPI +UefiDecompress ( + IN CONST VOID *Source, + IN OUT VOID *Destination, + IN OUT VOID *Scratch OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDriverEntryPoint.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDriverEntryPoint.h new file mode 100644 index 0000000000..9eb0adf35f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiDriverEntryPoint.h @@ -0,0 +1,189 @@ +/** @file + Module entry point library for UEFI drivers, DXE Drivers, DXE Runtime Drivers, + and DXE SMM Drivers. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/// +///Declare the PI Specification Revision that this driver requires to execute correctly. +/// +extern CONST UINT32 _gDxeRevision; + +/// +/// Declare the EFI/UEFI Specification Revision to which this driver is implemented +/// +extern CONST UINT32 _gUefiDriverRevision; + +/// +/// Declare the number of unload handler in the image. +/// +extern CONST UINT8 _gDriverUnloadImageCount; + + +/** + The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + + This function is the entry point for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, + or UEFI Driver. This function must call ProcessLibraryConstructorList() and + ProcessModuleEntryPointList(). If the return status from ProcessModuleEntryPointList() + is an error status, then ProcessLibraryDestructorList() must be called. The return value + from ProcessModuleEntryPointList() is returned. If _gDriverUnloadImageCount is greater + than zero, then an unload handler must be registered for this image and the unload handler + must invoke ProcessModuleUnloadList(). + If _gUefiDriverRevision is not zero and SystemTable->Hdr.Revision is less than _gUefiDriverRevison, + then return EFI_INCOMPATIBLE_VERSION. + + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, + or UEFI Driver exited normally. + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision. + @retval Other Return value from ProcessModuleEntryPointList(). + +**/ +EFI_STATUS +EFIAPI +_ModuleEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + This function is required to call _ModuleEntryPoint() passing in ImageHandle, and SystemTable. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, + or UEFI Driver exited normally. + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than SystemTable->Hdr.Revision. + @retval Other Return value from ProcessModuleEntryPointList(). +**/ +EFI_STATUS +EFIAPI +EfiMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Invokes the library destructors for all dependent libraries and terminates the + DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + + This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit() + with a status specified by Status. + + @param Status Status returned by the driver that is exiting. + +**/ +VOID +EFIAPI +ExitDriver ( + IN EFI_STATUS Status + ); + + +/** + Autogenerated function that calls the library constructors for all of the module's + dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible + for collecting the set of library instances, determine which ones have constructors, + and calling the library constructors in the proper order based upon each of the library + instances own dependencies. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Autogenerated function that calls the library descructors for all of the module's + dependent libraries. + + This function may be called by _ModuleEntryPoint() or ExitDriver(). + This function calls the set of library destructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other libraries. + This function is autogenerated by build tools and those build tools are responsible for + collecting the set of library instances, determine which ones have destructors, and calling + the library destructors in the proper order based upon each of the library instances own dependencies. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryDestructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Autogenerated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module entry points and calling them in a specified order. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver executed normally. + @retval !EFI_SUCCESS The DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver failed to execute normally. +**/ +EFI_STATUS +EFIAPI +ProcessModuleEntryPointList ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Autogenerated function that calls a set of module unload handlers. + + This function must be called from the unload handler registered by _ModuleEntryPoint(). + This function calls the set of module unload handlers. + This function is autogenerated by build tools and those build tools are responsible + for collecting the module unload handlers and calling them in a specified order. + + @param ImageHandle The image handle of the DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. + + @retval EFI_SUCCESS The unload handlers executed normally. + @retval !EFI_SUCCESS The unload handlers failed to execute normally. + +**/ +EFI_STATUS +EFIAPI +ProcessModuleUnloadList ( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiLib.h new file mode 100644 index 0000000000..264287fb6b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiLib.h @@ -0,0 +1,1761 @@ +/** @file + Provides library functions for common UEFI operations. Only available to DXE + and UEFI module types. + + The UEFI Library provides functions and macros that simplify the development of + UEFI Drivers and UEFI Applications. These functions and macros help manage EFI + events, build simple locks utilizing EFI Task Priority Levels (TPLs), install + EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers, + and print messages on the console output and standard error devices. + + Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention + of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is + defined, then debug and assert related macros wrapped by it are the NULL implementations. + +Copyright (c) 2019, NVIDIA Corporation. All rights reserved. +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_LIB_H__ +#define __UEFI_LIB_H__ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/// +/// Unicode String Table +/// +typedef struct { + CHAR8 *Language; + CHAR16 *UnicodeString; +} EFI_UNICODE_STRING_TABLE; + +/// +/// EFI Lock Status +/// +typedef enum { + EfiLockUninitialized = 0, + EfiLockReleased = 1, + EfiLockAcquired = 2 +} EFI_LOCK_STATE; + +/// +/// EFI Lock +/// +typedef struct { + EFI_TPL Tpl; + EFI_TPL OwnerTpl; + EFI_LOCK_STATE Lock; +} EFI_LOCK; + +/** + Macro that returns the number of 100 ns units for a specified number of microseconds. + This is useful for managing EFI timer events. + + @param Microseconds The number of microseconds. + + @return The number of 100 ns units equivalent to the number of microseconds specified + by Microseconds. + +**/ +#define EFI_TIMER_PERIOD_MICROSECONDS(Microseconds) MultU64x32((UINT64)(Microseconds), 10) + +/** + Macro that returns the number of 100 ns units for a specified number of milliseconds. + This is useful for managing EFI timer events. + + @param Milliseconds The number of milliseconds. + + @return The number of 100 ns units equivalent to the number of milliseconds specified + by Milliseconds. + +**/ +#define EFI_TIMER_PERIOD_MILLISECONDS(Milliseconds) MultU64x32((UINT64)(Milliseconds), 10000) + +/** + Macro that returns the number of 100 ns units for a specified number of seconds. + This is useful for managing EFI timer events. + + @param Seconds The number of seconds. + + @return The number of 100 ns units equivalent to the number of seconds specified + by Seconds. + +**/ +#define EFI_TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000) + +/** + Macro that returns the a pointer to the next EFI_MEMORY_DESCRIPTOR in an array + returned from GetMemoryMap(). + + @param MemoryDescriptor A pointer to an EFI_MEMORY_DESCRIPTOR. + + @param Size The size, in bytes, of the current EFI_MEMORY_DESCRIPTOR. + + @return A pointer to the next EFI_MEMORY_DESCRIPTOR. + +**/ +#define NEXT_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \ + ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) + (Size))) + +/** + Retrieves a pointer to the system configuration table from the EFI System Table + based on a specified GUID. + + This function searches the list of configuration tables stored in the EFI System Table + for a table with a GUID that matches TableGuid. If a match is found, then a pointer to + the configuration table is returned in Table, and EFI_SUCCESS is returned. If a matching GUID + is not found, then EFI_NOT_FOUND is returned. + If TableGuid is NULL, then ASSERT(). + If Table is NULL, then ASSERT(). + + @param TableGuid The pointer to table's GUID type.. + @param Table The pointer to the table associated with TableGuid in the EFI System Table. + + @retval EFI_SUCCESS A configuration table matching TableGuid was found. + @retval EFI_NOT_FOUND A configuration table matching TableGuid could not be found. + +**/ +EFI_STATUS +EFIAPI +EfiGetSystemConfigurationTable ( + IN EFI_GUID *TableGuid, + OUT VOID **Table + ); + +/** + Creates and returns a notification event and registers that event with all the protocol + instances specified by ProtocolGuid. + + This function causes the notification function to be executed for every protocol of type + ProtocolGuid instance that exists in the system when this function is invoked. If there are + no instances of ProtocolGuid in the handle database at the time this function is invoked, + then the notification function is still executed one time. In addition, every time a protocol + of type ProtocolGuid instance is installed or reinstalled, the notification function is also + executed. This function returns the notification event that was created. + If ProtocolGuid is NULL, then ASSERT(). + If NotifyTpl is not a legal TPL value, then ASSERT(). + If NotifyFunction is NULL, then ASSERT(). + If Registration is NULL, then ASSERT(). + + + @param ProtocolGuid Supplies GUID of the protocol upon whose installation the event is fired. + @param NotifyTpl Supplies the task priority level of the event notifications. + @param NotifyFunction Supplies the function to notify when the event is signaled. + @param NotifyContext The context parameter to pass to NotifyFunction. + @param Registration A pointer to a memory location to receive the registration value. + This value is passed to LocateHandle() to obtain new handles that + have been added that support the ProtocolGuid-specified protocol. + + @return The notification event that was created. + +**/ +EFI_EVENT +EFIAPI +EfiCreateProtocolNotifyEvent( + IN EFI_GUID *ProtocolGuid, + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction, + IN VOID *NotifyContext, OPTIONAL + OUT VOID **Registration + ); + +/** + Creates a named event that can be signaled with EfiNamedEventSignal(). + + This function creates an event using NotifyTpl, NoifyFunction, and NotifyContext. + This event is signaled with EfiNamedEventSignal(). This provides the ability for one or more + listeners on the same event named by the GUID specified by Name. + If Name is NULL, then ASSERT(). + If NotifyTpl is not a legal TPL value, then ASSERT(). + If NotifyFunction is NULL, then ASSERT(). + + @param Name Supplies GUID name of the event. + @param NotifyTpl Supplies the task priority level of the event notifications. + @param NotifyFunction Supplies the function to notify when the event is signaled. + @param NotifyContext The context parameter to pass to NotifyFunction. + @param Registration A pointer to a memory location to receive the registration value. + + @retval EFI_SUCCESS A named event was created. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to create the named event. + +**/ +EFI_STATUS +EFIAPI +EfiNamedEventListen ( + IN CONST EFI_GUID *Name, + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction, + IN CONST VOID *NotifyContext, OPTIONAL + OUT VOID *Registration OPTIONAL + ); + +/** + Signals a named event created with EfiNamedEventListen(). + + This function signals the named event specified by Name. The named event must have been + created with EfiNamedEventListen(). + If Name is NULL, then ASSERT(). + + @param Name Supplies the GUID name of the event. + + @retval EFI_SUCCESS A named event was signaled. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to signal the named event. + +**/ +EFI_STATUS +EFIAPI +EfiNamedEventSignal ( + IN CONST EFI_GUID *Name + ); + +/** + Signals an event group by placing a new event in the group temporarily and + signaling it. + + @param[in] EventGroup Supplies the unique identifier of the event + group to signal. + + @retval EFI_SUCCESS The event group was signaled successfully. + @retval EFI_INVALID_PARAMETER EventGroup is NULL. + @return Error codes that report problems about event + creation or signaling. +**/ +EFI_STATUS +EFIAPI +EfiEventGroupSignal ( + IN CONST EFI_GUID *EventGroup + ); + +/** + An empty function that can be used as NotifyFunction parameter of + CreateEvent() or CreateEventEx(). + + @param Event Event whose notification function is being invoked. + @param Context The pointer to the notification function's context, + which is implementation-dependent. + +**/ +VOID +EFIAPI +EfiEventEmptyFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + Returns the current TPL. + + This function returns the current TPL. There is no EFI service to directly + retrieve the current TPL. Instead, the RaiseTPL() function is used to raise + the TPL to TPL_HIGH_LEVEL. This will return the current TPL. The TPL level + can then immediately be restored back to the current TPL level with a call + to RestoreTPL(). + + @return The current TPL. + +**/ +EFI_TPL +EFIAPI +EfiGetCurrentTpl ( + VOID + ); + +/** + Initializes a basic mutual exclusion lock. + + This function initializes a basic mutual exclusion lock to the released state + and returns the lock. Each lock provides mutual exclusion access at its task + priority level. Since there is no preemption or multiprocessor support in EFI, + acquiring the lock only consists of raising to the locks TPL. + If Lock is NULL, then ASSERT(). + If Priority is not a valid TPL value, then ASSERT(). + + @param Lock A pointer to the lock data structure to initialize. + @param Priority The EFI TPL associated with the lock. + + @return The lock. + +**/ +EFI_LOCK * +EFIAPI +EfiInitializeLock ( + IN OUT EFI_LOCK *Lock, + IN EFI_TPL Priority + ); + +/** + Initializes a basic mutual exclusion lock. + + This macro initializes the contents of a basic mutual exclusion lock to the + released state. Each lock provides mutual exclusion access at its task + priority level. Since there is no preemption or multiprocessor support in EFI, + acquiring the lock only consists of raising to the locks TPL. + + @param Priority The task priority level of the lock. + + @return The lock. + +**/ +#define EFI_INITIALIZE_LOCK_VARIABLE(Priority) \ + {Priority, TPL_APPLICATION, EfiLockReleased } + + +/** + Macro that calls DebugAssert() if an EFI_LOCK structure is not in the locked state. + + If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED + bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_LOCK + structure specified by Lock. If Lock is not in the locked state, then + DebugAssert() is called passing in the source filename, source line number, + and Lock. + + If Lock is NULL, then ASSERT(). + + @param LockParameter A pointer to the lock to acquire. + +**/ +#if !defined(MDEPKG_NDEBUG) + #define ASSERT_LOCKED(LockParameter) \ + do { \ + if (DebugAssertEnabled ()) { \ + ASSERT (LockParameter != NULL); \ + if ((LockParameter)->Lock != EfiLockAcquired) { \ + _ASSERT (LockParameter not locked); \ + } \ + } \ + } while (FALSE) +#else + #define ASSERT_LOCKED(LockParameter) +#endif + + +/** + Acquires ownership of a lock. + + This function raises the system's current task priority level to the task + priority level of the mutual exclusion lock. Then, it places the lock in the + acquired state. + If Lock is NULL, then ASSERT(). + If Lock is not initialized, then ASSERT(). + If Lock is already in the acquired state, then ASSERT(). + + @param Lock A pointer to the lock to acquire. + +**/ +VOID +EFIAPI +EfiAcquireLock ( + IN EFI_LOCK *Lock + ); + +/** + Acquires ownership of a lock. + + This function raises the system's current task priority level to the task priority + level of the mutual exclusion lock. Then, it attempts to place the lock in the acquired state. + If the lock is already in the acquired state, then EFI_ACCESS_DENIED is returned. + Otherwise, EFI_SUCCESS is returned. + If Lock is NULL, then ASSERT(). + If Lock is not initialized, then ASSERT(). + + @param Lock A pointer to the lock to acquire. + + @retval EFI_SUCCESS The lock was acquired. + @retval EFI_ACCESS_DENIED The lock could not be acquired because it is already owned. + +**/ +EFI_STATUS +EFIAPI +EfiAcquireLockOrFail ( + IN EFI_LOCK *Lock + ); + +/** + Releases ownership of a lock. + + This function transitions a mutual exclusion lock from the acquired state to + the released state, and restores the system's task priority level to its + previous level. + If Lock is NULL, then ASSERT(). + If Lock is not initialized, then ASSERT(). + If Lock is already in the released state, then ASSERT(). + + @param Lock A pointer to the lock to release. + +**/ +VOID +EFIAPI +EfiReleaseLock ( + IN EFI_LOCK *Lock + ); + +/** + Tests whether a controller handle is being managed by a specific driver. + + This function tests whether the driver specified by DriverBindingHandle is + currently managing the controller specified by ControllerHandle. This test + is performed by evaluating if the the protocol specified by ProtocolGuid is + present on ControllerHandle and is was opened by DriverBindingHandle with an + attribute of EFI_OPEN_PROTOCOL_BY_DRIVER. + If ProtocolGuid is NULL, then ASSERT(). + + @param ControllerHandle A handle for a controller to test. + @param DriverBindingHandle Specifies the driver binding handle for the + driver. + @param ProtocolGuid Specifies the protocol that the driver specified + by DriverBindingHandle opens in its Start() + function. + + @retval EFI_SUCCESS ControllerHandle is managed by the driver + specified by DriverBindingHandle. + @retval EFI_UNSUPPORTED ControllerHandle is not managed by the driver + specified by DriverBindingHandle. + +**/ +EFI_STATUS +EFIAPI +EfiTestManagedDevice ( + IN CONST EFI_HANDLE ControllerHandle, + IN CONST EFI_HANDLE DriverBindingHandle, + IN CONST EFI_GUID *ProtocolGuid + ); + +/** + Tests whether a child handle is a child device of the controller. + + This function tests whether ChildHandle is one of the children of + ControllerHandle. This test is performed by checking to see if the protocol + specified by ProtocolGuid is present on ControllerHandle and opened by + ChildHandle with an attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + If ProtocolGuid is NULL, then ASSERT(). + + @param ControllerHandle A handle for a (parent) controller to test. + @param ChildHandle A child handle to test. + @param ProtocolGuid Supplies the protocol that the child controller + opens on its parent controller. + + @retval EFI_SUCCESS ChildHandle is a child of the ControllerHandle. + @retval EFI_UNSUPPORTED ChildHandle is not a child of the + ControllerHandle. + +**/ +EFI_STATUS +EFIAPI +EfiTestChildHandle ( + IN CONST EFI_HANDLE ControllerHandle, + IN CONST EFI_HANDLE ChildHandle, + IN CONST EFI_GUID *ProtocolGuid + ); + +/** + This function checks the supported languages list for a target language, + This only supports RFC 4646 Languages. + + @param SupportedLanguages The supported languages + @param TargetLanguage The target language + + @retval Returns EFI_SUCCESS if the language is supported, + EFI_UNSUPPORTED otherwise + +**/ +EFI_STATUS +EFIAPI +IsLanguageSupported ( + IN CONST CHAR8 *SupportedLanguages, + IN CONST CHAR8 *TargetLanguage + ); + +/** + This function looks up a Unicode string in UnicodeStringTable. + + If Language is a member of SupportedLanguages and a Unicode string is found in + UnicodeStringTable that matches the language code specified by Language, then it + is returned in UnicodeString. + + @param Language A pointer to the ISO 639-2 language code for the + Unicode string to look up and return. + @param SupportedLanguages A pointer to the set of ISO 639-2 language codes + that the Unicode string table supports. Language + must be a member of this set. + @param UnicodeStringTable A pointer to the table of Unicode strings. + @param UnicodeString A pointer to the Unicode string from UnicodeStringTable + that matches the language specified by Language. + + @retval EFI_SUCCESS The Unicode string that matches the language + specified by Language was found + in the table of Unicode strings UnicodeStringTable, + and it was returned in UnicodeString. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is NULL. + @retval EFI_UNSUPPORTED SupportedLanguages is NULL. + @retval EFI_UNSUPPORTED UnicodeStringTable is NULL. + @retval EFI_UNSUPPORTED The language specified by Language is not a + member of SupportedLanguages. + @retval EFI_UNSUPPORTED The language specified by Language is not + supported by UnicodeStringTable. + +**/ +EFI_STATUS +EFIAPI +LookupUnicodeString ( + IN CONST CHAR8 *Language, + IN CONST CHAR8 *SupportedLanguages, + IN CONST EFI_UNICODE_STRING_TABLE *UnicodeStringTable, + OUT CHAR16 **UnicodeString + ); + +/** + This function looks up a Unicode string in UnicodeStringTable. + + If Language is a member of SupportedLanguages and a Unicode string is found in + UnicodeStringTable that matches the language code specified by Language, then + it is returned in UnicodeString. + + @param Language A pointer to an ASCII string containing the ISO 639-2 or the + RFC 4646 language code for the Unicode string to look up and + return. If Iso639Language is TRUE, then this ASCII string is + not assumed to be Null-terminated, and only the first three + characters are used. If Iso639Language is FALSE, then this ASCII + string must be Null-terminated. + @param SupportedLanguages A pointer to a Null-terminated ASCII string that contains a + set of ISO 639-2 or RFC 4646 language codes that the Unicode + string table supports. Language must be a member of this set. + If Iso639Language is TRUE, then this string contains one or more + ISO 639-2 language codes with no separator characters. If Iso639Language + is FALSE, then is string contains one or more RFC 4646 language + codes separated by ';'. + @param UnicodeStringTable A pointer to the table of Unicode strings. Type EFI_UNICODE_STRING_TABLE + is defined in "Related Definitions". + @param UnicodeString A pointer to the Null-terminated Unicode string from UnicodeStringTable + that matches the language specified by Language. + @param Iso639Language Specifies the supported language code format. If it is TRUE, then + Language and SupportedLanguages follow ISO 639-2 language code format. + Otherwise, they follow the RFC 4646 language code format. + + + @retval EFI_SUCCESS The Unicode string that matches the language specified by Language + was found in the table of Unicode strings UnicodeStringTable, and + it was returned in UnicodeString. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is NULL. + @retval EFI_UNSUPPORTED SupportedLanguages is NULL. + @retval EFI_UNSUPPORTED UnicodeStringTable is NULL. + @retval EFI_UNSUPPORTED The language specified by Language is not a member of SupportedLanguages. + @retval EFI_UNSUPPORTED The language specified by Language is not supported by UnicodeStringTable. + +**/ +EFI_STATUS +EFIAPI +LookupUnicodeString2 ( + IN CONST CHAR8 *Language, + IN CONST CHAR8 *SupportedLanguages, + IN CONST EFI_UNICODE_STRING_TABLE *UnicodeStringTable, + OUT CHAR16 **UnicodeString, + IN BOOLEAN Iso639Language + ); + +/** + This function adds a Unicode string to UnicodeStringTable. + + If Language is a member of SupportedLanguages then UnicodeString is added to + UnicodeStringTable. New buffers are allocated for both Language and + UnicodeString. The contents of Language and UnicodeString are copied into + these new buffers. These buffers are automatically freed when + FreeUnicodeStringTable() is called. + + @param Language A pointer to the ISO 639-2 language code for the Unicode + string to add. + @param SupportedLanguages A pointer to the set of ISO 639-2 language codes + that the Unicode string table supports. + Language must be a member of this set. + @param UnicodeStringTable A pointer to the table of Unicode strings. + @param UnicodeString A pointer to the Unicode string to add. + + @retval EFI_SUCCESS The Unicode string that matches the language + specified by Language was found in the table of + Unicode strings UnicodeStringTable, and it was + returned in UnicodeString. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is an empty string. + @retval EFI_UNSUPPORTED SupportedLanguages is NULL. + @retval EFI_ALREADY_STARTED A Unicode string with language Language is + already present in UnicodeStringTable. + @retval EFI_OUT_OF_RESOURCES There is not enough memory to add another + Unicode string to UnicodeStringTable. + @retval EFI_UNSUPPORTED The language specified by Language is not a + member of SupportedLanguages. + +**/ +EFI_STATUS +EFIAPI +AddUnicodeString ( + IN CONST CHAR8 *Language, + IN CONST CHAR8 *SupportedLanguages, + IN OUT EFI_UNICODE_STRING_TABLE **UnicodeStringTable, + IN CONST CHAR16 *UnicodeString + ); + +/** + This function adds the Null-terminated Unicode string specified by UnicodeString + to UnicodeStringTable. + + If Language is a member of SupportedLanguages then UnicodeString is added to + UnicodeStringTable. New buffers are allocated for both Language and UnicodeString. + The contents of Language and UnicodeString are copied into these new buffers. + These buffers are automatically freed when EfiLibFreeUnicodeStringTable() is called. + + @param Language A pointer to an ASCII string containing the ISO 639-2 or + the RFC 4646 language code for the Unicode string to add. + If Iso639Language is TRUE, then this ASCII string is not + assumed to be Null-terminated, and only the first three + chacters are used. If Iso639Language is FALSE, then this + ASCII string must be Null-terminated. + @param SupportedLanguages A pointer to a Null-terminated ASCII string that contains + a set of ISO 639-2 or RFC 4646 language codes that the Unicode + string table supports. Language must be a member of this set. + If Iso639Language is TRUE, then this string contains one or more + ISO 639-2 language codes with no separator characters. + If Iso639Language is FALSE, then is string contains one or more + RFC 4646 language codes separated by ';'. + @param UnicodeStringTable A pointer to the table of Unicode strings. Type EFI_UNICODE_STRING_TABLE + is defined in "Related Definitions". + @param UnicodeString A pointer to the Unicode string to add. + @param Iso639Language Specifies the supported language code format. If it is TRUE, + then Language and SupportedLanguages follow ISO 639-2 language code format. + Otherwise, they follow RFC 4646 language code format. + + @retval EFI_SUCCESS The Unicode string that matches the language specified by + Language was found in the table of Unicode strings UnicodeStringTable, + and it was returned in UnicodeString. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is NULL. + @retval EFI_INVALID_PARAMETER UnicodeString is an empty string. + @retval EFI_UNSUPPORTED SupportedLanguages is NULL. + @retval EFI_ALREADY_STARTED A Unicode string with language Language is already present in + UnicodeStringTable. + @retval EFI_OUT_OF_RESOURCES There is not enough memory to add another Unicode string UnicodeStringTable. + @retval EFI_UNSUPPORTED The language specified by Language is not a member of SupportedLanguages. + +**/ +EFI_STATUS +EFIAPI +AddUnicodeString2 ( + IN CONST CHAR8 *Language, + IN CONST CHAR8 *SupportedLanguages, + IN OUT EFI_UNICODE_STRING_TABLE **UnicodeStringTable, + IN CONST CHAR16 *UnicodeString, + IN BOOLEAN Iso639Language + ); + +/** + This function frees the table of Unicode strings in UnicodeStringTable. + + If UnicodeStringTable is NULL, then EFI_SUCCESS is returned. + Otherwise, each language code, and each Unicode string in the Unicode string + table are freed, and EFI_SUCCESS is returned. + + @param UnicodeStringTable A pointer to the table of Unicode strings. + + @retval EFI_SUCCESS The Unicode string table was freed. + +**/ +EFI_STATUS +EFIAPI +FreeUnicodeStringTable ( + IN EFI_UNICODE_STRING_TABLE *UnicodeStringTable + ); + + +/** + Returns the status whether get the variable success. The function retrieves + variable through the UEFI Runtime Service GetVariable(). The + returned buffer is allocated using AllocatePool(). The caller is responsible + for freeing this buffer with FreePool(). + + If Name is NULL, then ASSERT(). + If Guid is NULL, then ASSERT(). + If Value is NULL, then ASSERT(). + + @param[in] Name The pointer to a Null-terminated Unicode string. + @param[in] Guid The pointer to an EFI_GUID structure + @param[out] Value The buffer point saved the variable info. + @param[out] Size The buffer size of the variable. + + @retval EFI_OUT_OF_RESOURCES Allocate buffer failed. + @retval EFI_SUCCESS Find the specified variable. + @retval Others Errors Return errors from call to gRT->GetVariable. + +**/ +EFI_STATUS +EFIAPI +GetVariable2 ( + IN CONST CHAR16 *Name, + IN CONST EFI_GUID *Guid, + OUT VOID **Value, + OUT UINTN *Size OPTIONAL + ); + +/** + Returns a pointer to an allocated buffer that contains the contents of a + variable retrieved through the UEFI Runtime Service GetVariable(). This + function always uses the EFI_GLOBAL_VARIABLE GUID to retrieve variables. + The returned buffer is allocated using AllocatePool(). The caller is + responsible for freeing this buffer with FreePool(). + + If Name is NULL, then ASSERT(). + If Value is NULL, then ASSERT(). + + @param[in] Name The pointer to a Null-terminated Unicode string. + @param[out] Value The buffer point saved the variable info. + @param[out] Size The buffer size of the variable. + + @retval EFI_OUT_OF_RESOURCES Allocate buffer failed. + @retval EFI_SUCCESS Find the specified variable. + @retval Others Errors Return errors from call to gRT->GetVariable. + +**/ +EFI_STATUS +EFIAPI +GetEfiGlobalVariable2 ( + IN CONST CHAR16 *Name, + OUT VOID **Value, + OUT UINTN *Size OPTIONAL + ); + +/** Return the attributes of the variable. + + Returns the status whether get the variable success. The function retrieves + variable through the UEFI Runtime Service GetVariable(). The + returned buffer is allocated using AllocatePool(). The caller is responsible + for freeing this buffer with FreePool(). The attributes are returned if + the caller provides a valid Attribute parameter. + + If Name is NULL, then ASSERT(). + If Guid is NULL, then ASSERT(). + If Value is NULL, then ASSERT(). + + @param[in] Name The pointer to a Null-terminated Unicode string. + @param[in] Guid The pointer to an EFI_GUID structure + @param[out] Value The buffer point saved the variable info. + @param[out] Size The buffer size of the variable. + @param[out] Attr The pointer to the variable attributes as found in var store + + @retval EFI_OUT_OF_RESOURCES Allocate buffer failed. + @retval EFI_SUCCESS Find the specified variable. + @retval Others Errors Return errors from call to gRT->GetVariable. + +**/ +EFI_STATUS +EFIAPI +GetVariable3( + IN CONST CHAR16 *Name, + IN CONST EFI_GUID *Guid, + OUT VOID **Value, + OUT UINTN *Size OPTIONAL, + OUT UINT32 *Attr OPTIONAL + ); + +/** + Returns a pointer to an allocated buffer that contains the best matching language + from a set of supported languages. + + This function supports both ISO 639-2 and RFC 4646 language codes, but language + code types may not be mixed in a single call to this function. The language + code returned is allocated using AllocatePool(). The caller is responsible for + freeing the allocated buffer using FreePool(). This function supports a variable + argument list that allows the caller to pass in a prioritized list of language + codes to test against all the language codes in SupportedLanguages. + + If SupportedLanguages is NULL, then ASSERT(). + + @param[in] SupportedLanguages A pointer to a Null-terminated ASCII string that + contains a set of language codes in the format + specified by Iso639Language. + @param[in] Iso639Language If not zero, then all language codes are assumed to be + in ISO 639-2 format. If zero, then all language + codes are assumed to be in RFC 4646 language format + @param[in] ... A variable argument list that contains pointers to + Null-terminated ASCII strings that contain one or more + language codes in the format specified by Iso639Language. + The first language code from each of these language + code lists is used to determine if it is an exact or + close match to any of the language codes in + SupportedLanguages. Close matches only apply to RFC 4646 + language codes, and the matching algorithm from RFC 4647 + is used to determine if a close match is present. If + an exact or close match is found, then the matching + language code from SupportedLanguages is returned. If + no matches are found, then the next variable argument + parameter is evaluated. The variable argument list + is terminated by a NULL. + + @retval NULL The best matching language could not be found in SupportedLanguages. + @retval NULL There are not enough resources available to return the best matching + language. + @retval Other A pointer to a Null-terminated ASCII string that is the best matching + language in SupportedLanguages. + +**/ +CHAR8 * +EFIAPI +GetBestLanguage ( + IN CONST CHAR8 *SupportedLanguages, + IN UINTN Iso639Language, + ... + ); + +/** + Draws a dialog box to the console output device specified by + ConOut defined in the EFI_SYSTEM_TABLE and waits for a keystroke + from the console input device specified by ConIn defined in the + EFI_SYSTEM_TABLE. + + If there are no strings in the variable argument list, then ASSERT(). + If all the strings in the variable argument list are empty, then ASSERT(). + + @param[in] Attribute Specifies the foreground and background color of the popup. + @param[out] Key A pointer to the EFI_KEY value of the key that was + pressed. This is an optional parameter that may be NULL. + If it is NULL then no wait for a keypress will be performed. + @param[in] ... The variable argument list that contains pointers to Null- + terminated Unicode strings to display in the dialog box. + The variable argument list is terminated by a NULL. + +**/ +VOID +EFIAPI +CreatePopUp ( + IN UINTN Attribute, + OUT EFI_INPUT_KEY *Key, OPTIONAL + ... + ); + +/** + Retrieves the width of a Unicode character. + + This function computes and returns the width of the Unicode character specified + by UnicodeChar. + + @param UnicodeChar A Unicode character. + + @retval 0 The width if UnicodeChar could not be determined. + @retval 1 UnicodeChar is a narrow glyph. + @retval 2 UnicodeChar is a wide glyph. + +**/ +UINTN +EFIAPI +GetGlyphWidth ( + IN CHAR16 UnicodeChar + ); + +/** + Computes the display length of a Null-terminated Unicode String. + + This function computes and returns the display length of the Null-terminated Unicode + string specified by String. If String is NULL then 0 is returned. If any of the widths + of the Unicode characters in String can not be determined, then 0 is returned. The display + width of String can be computed by summing the display widths of each Unicode character + in String. Unicode characters that are narrow glyphs have a width of 1, and Unicode + characters that are width glyphs have a width of 2. + If String is not aligned on a 16-bit boundary, then ASSERT(). + + @param String A pointer to a Null-terminated Unicode string. + + @return The display length of the Null-terminated Unicode string specified by String. + +**/ +UINTN +EFIAPI +UnicodeStringDisplayLength ( + IN CONST CHAR16 *String + ); + +// +// Functions that abstract early Framework contamination of UEFI. +// +/** + Create, Signal, and Close the Ready to Boot event using EfiSignalEventReadyToBoot(). + + This function abstracts the signaling of the Ready to Boot Event. The Framework moved + from a proprietary to UEFI 2.0 based mechanism. This library abstracts the caller + from how this event is created to prevent to code form having to change with the + version of the specification supported. + +**/ +VOID +EFIAPI +EfiSignalEventReadyToBoot ( + VOID + ); + +/** + Create, Signal, and Close the Ready to Boot event using EfiSignalEventLegacyBoot(). + + This function abstracts the signaling of the Legacy Boot Event. The Framework moved from + a proprietary to UEFI 2.0 based mechanism. This library abstracts the caller from how + this event is created to prevent to code form having to change with the version of the + specification supported. + +**/ +VOID +EFIAPI +EfiSignalEventLegacyBoot ( + VOID + ); + +/** + Creates an EFI event in the Legacy Boot Event Group. + + Prior to UEFI 2.0 this was done via a non blessed UEFI extensions and this library + abstracts the implementation mechanism of this event from the caller. This function + abstracts the creation of the Legacy Boot Event. The Framework moved from a proprietary + to UEFI 2.0 based mechanism. This library abstracts the caller from how this event + is created to prevent to code form having to change with the version of the + specification supported. + If LegacyBootEvent is NULL, then ASSERT(). + + @param LegacyBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex). + + @retval EFI_SUCCESS The event was created. + @retval Other The event was not created. + +**/ +EFI_STATUS +EFIAPI +EfiCreateEventLegacyBoot ( + OUT EFI_EVENT *LegacyBootEvent + ); + +/** + Create an EFI event in the Legacy Boot Event Group and allows + the caller to specify a notification function. + + This function abstracts the creation of the Legacy Boot Event. + The Framework moved from a proprietary to UEFI 2.0 based mechanism. + This library abstracts the caller from how this event is created to prevent + to code form having to change with the version of the specification supported. + If LegacyBootEvent is NULL, then ASSERT(). + + @param NotifyTpl The task priority level of the event. + @param NotifyFunction The notification function to call when the event is signaled. + @param NotifyContext The content to pass to NotifyFunction when the event is signaled. + @param LegacyBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex). + + @retval EFI_SUCCESS The event was created. + @retval Other The event was not created. + +**/ +EFI_STATUS +EFIAPI +EfiCreateEventLegacyBootEx ( + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction, OPTIONAL + IN VOID *NotifyContext, OPTIONAL + OUT EFI_EVENT *LegacyBootEvent + ); + +/** + Create an EFI event in the Ready To Boot Event Group. + + Prior to UEFI 2.0 this was done via a non-standard UEFI extension, and this library + abstracts the implementation mechanism of this event from the caller. + This function abstracts the creation of the Ready to Boot Event. The Framework + moved from a proprietary to UEFI 2.0-based mechanism. This library abstracts + the caller from how this event is created to prevent the code form having to + change with the version of the specification supported. + If ReadyToBootEvent is NULL, then ASSERT(). + + @param ReadyToBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex). + + @retval EFI_SUCCESS The event was created. + @retval Other The event was not created. + +**/ +EFI_STATUS +EFIAPI +EfiCreateEventReadyToBoot ( + OUT EFI_EVENT *ReadyToBootEvent + ); + +/** + Create an EFI event in the Ready To Boot Event Group and allows + the caller to specify a notification function. + + This function abstracts the creation of the Ready to Boot Event. + The Framework moved from a proprietary to UEFI 2.0 based mechanism. + This library abstracts the caller from how this event is created to prevent + to code form having to change with the version of the specification supported. + If ReadyToBootEvent is NULL, then ASSERT(). + + @param NotifyTpl The task priority level of the event. + @param NotifyFunction The notification function to call when the event is signaled. + @param NotifyContext The content to pass to NotifyFunction when the event is signaled. + @param ReadyToBootEvent Returns the EFI event returned from gBS->CreateEvent(Ex). + + @retval EFI_SUCCESS The event was created. + @retval Other The event was not created. + +**/ +EFI_STATUS +EFIAPI +EfiCreateEventReadyToBootEx ( + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction, OPTIONAL + IN VOID *NotifyContext, OPTIONAL + OUT EFI_EVENT *ReadyToBootEvent + ); + +/** + Initialize a Firmware Volume (FV) Media Device Path node. + + The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification. + This library function abstracts initializing a device path node. + Initialize the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure. This device + path changed in the DXE CIS version 0.92 in a non back ward compatible way to + not conflict with the UEFI 2.0 specification. This function abstracts the + differences from the caller. + If FvDevicePathNode is NULL, then ASSERT(). + If NameGuid is NULL, then ASSERT(). + + @param FvDevicePathNode The pointer to a FV device path node to initialize + @param NameGuid FV file name to use in FvDevicePathNode + +**/ +VOID +EFIAPI +EfiInitializeFwVolDevicepathNode ( + IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode, + IN CONST EFI_GUID *NameGuid + ); + +/** + Check to see if the Firmware Volume (FV) Media Device Path is valid + + The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification. + This library function abstracts validating a device path node. + Check the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure to see if it's valid. + If it is valid, then return the GUID file name from the device path node. Otherwise, + return NULL. This device path changed in the DXE CIS version 0.92 in a non backward + compatible way to not conflict with the UEFI 2.0 specification. This function abstracts + the differences from the caller. + If FvDevicePathNode is NULL, then ASSERT(). + + @param FvDevicePathNode The pointer to FV device path to check. + + @retval NULL FvDevicePathNode is not valid. + @retval Other FvDevicePathNode is valid and pointer to NameGuid was returned. + +**/ +EFI_GUID * +EFIAPI +EfiGetNameGuidFromFwVolDevicePathNode ( + IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvDevicePathNode + ); + +/** + Prints a formatted Unicode string to the console output device specified by + ConOut defined in the EFI_SYSTEM_TABLE. + + This function prints a formatted Unicode string to the console output device + specified by ConOut in EFI_SYSTEM_TABLE and returns the number of Unicode + characters that printed to ConOut. If the length of the formatted Unicode + string is greater than PcdUefiLibMaxPrintBufferSize, then only the first + PcdUefiLibMaxPrintBufferSize characters are sent to ConOut. + If Format is NULL, then ASSERT(). + If Format is not aligned on a 16-bit boundary, then ASSERT(). + If gST->ConOut is NULL, then ASSERT(). + + @param Format A null-terminated Unicode format string. + @param ... The variable argument list whose contents are accessed based + on the format string specified by Format. + + @return Number of Unicode characters printed to ConOut. + +**/ +UINTN +EFIAPI +Print ( + IN CONST CHAR16 *Format, + ... + ); + +/** + Prints a formatted Unicode string to the console output device specified by + StdErr defined in the EFI_SYSTEM_TABLE. + + This function prints a formatted Unicode string to the console output device + specified by StdErr in EFI_SYSTEM_TABLE and returns the number of Unicode + characters that printed to StdErr. If the length of the formatted Unicode + string is greater than PcdUefiLibMaxPrintBufferSize, then only the first + PcdUefiLibMaxPrintBufferSize characters are sent to StdErr. + If Format is NULL, then ASSERT(). + If Format is not aligned on a 16-bit boundary, then ASSERT(). + If gST->StdErr is NULL, then ASSERT(). + + @param Format A null-terminated Unicode format string. + @param ... The variable argument list whose contents are accessed based + on the format string specified by Format. + + @return Number of Unicode characters printed to StdErr. + +**/ +UINTN +EFIAPI +ErrorPrint ( + IN CONST CHAR16 *Format, + ... + ); + +/** + Prints a formatted ASCII string to the console output device specified by + ConOut defined in the EFI_SYSTEM_TABLE. + + This function prints a formatted ASCII string to the console output device + specified by ConOut in EFI_SYSTEM_TABLE and returns the number of ASCII + characters that printed to ConOut. If the length of the formatted ASCII + string is greater than PcdUefiLibMaxPrintBufferSize, then only the first + PcdUefiLibMaxPrintBufferSize characters are sent to ConOut. + If Format is NULL, then ASSERT(). + If gST->ConOut is NULL, then ASSERT(). + + @param Format A null-terminated ASCII format string. + @param ... The variable argument list whose contents are accessed based + on the format string specified by Format. + + @return Number of ASCII characters printed to ConOut. + +**/ +UINTN +EFIAPI +AsciiPrint ( + IN CONST CHAR8 *Format, + ... + ); + +/** + Prints a formatted ASCII string to the console output device specified by + StdErr defined in the EFI_SYSTEM_TABLE. + + This function prints a formatted ASCII string to the console output device + specified by StdErr in EFI_SYSTEM_TABLE and returns the number of ASCII + characters that printed to StdErr. If the length of the formatted ASCII + string is greater than PcdUefiLibMaxPrintBufferSize, then only the first + PcdUefiLibMaxPrintBufferSize characters are sent to StdErr. + If Format is NULL, then ASSERT(). + If gST->StdErr is NULL, then ASSERT(). + + @param Format A null-terminated ASCII format string. + @param ... The variable argument list whose contents are accessed based + on the format string specified by Format. + + @return Number of ASCII characters printed to ConErr. + +**/ +UINTN +EFIAPI +AsciiErrorPrint ( + IN CONST CHAR8 *Format, + ... + ); + + +/** + Prints a formatted Unicode string to a graphics console device specified by + ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates. + + This function prints a formatted Unicode string to the graphics console device + specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of + Unicode characters displayed, not including partial characters that may be clipped + by the right edge of the display. If the length of the formatted Unicode string is + greater than PcdUefiLibMaxPrintBufferSize, then at most the first + PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL + is used to convert the string to a bitmap using the glyphs registered with the + HII database. No wrapping is performed, so any portions of the string the fall + outside the active display region will not be displayed. + + If a graphics console device is not associated with the ConsoleOutputHandle + defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned. + If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no + string is printed, and 0 is returned. + If Format is NULL, then ASSERT(). + If Format is not aligned on a 16-bit boundary, then ASSERT(). + If gST->ConsoleOutputHandle is NULL, then ASSERT(). + + @param PointX X coordinate to print the string. + @param PointY Y coordinate to print the string. + @param ForeGround The foreground color of the string being printed. This is + an optional parameter that may be NULL. If it is NULL, + then the foreground color of the current ConOut device + in the EFI_SYSTEM_TABLE is used. + @param BackGround The background color of the string being printed. This is + an optional parameter that may be NULL. If it is NULL, + then the background color of the current ConOut device + in the EFI_SYSTEM_TABLE is used. + @param Format A null-terminated Unicode format string. See Print Library + for the supported format string syntax. + @param ... Variable argument list whose contents are accessed based on + the format string specified by Format. + + @return The number of Unicode characters printed. + +**/ +UINTN +EFIAPI +PrintXY ( + IN UINTN PointX, + IN UINTN PointY, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround, OPTIONAL + IN CONST CHAR16 *Format, + ... + ); + +/** + Prints a formatted ASCII string to a graphics console device specified by + ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates. + + This function prints a formatted ASCII string to the graphics console device + specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of + ASCII characters displayed, not including partial characters that may be clipped + by the right edge of the display. If the length of the formatted ASCII string is + greater than PcdUefiLibMaxPrintBufferSize, then at most the first + PcdUefiLibMaxPrintBufferSize characters are printed. The EFI_HII_FONT_PROTOCOL + is used to convert the string to a bitmap using the glyphs registered with the + HII database. No wrapping is performed, so any portions of the string the fall + outside the active display region will not be displayed. + + If a graphics console device is not associated with the ConsoleOutputHandle + defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned. + If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no + string is printed, and 0 is returned. + If Format is NULL, then ASSERT(). + If gST->ConsoleOutputHandle is NULL, then ASSERT(). + + @param PointX X coordinate to print the string. + @param PointY Y coordinate to print the string. + @param ForeGround The foreground color of the string being printed. This is + an optional parameter that may be NULL. If it is NULL, + then the foreground color of the current ConOut device + in the EFI_SYSTEM_TABLE is used. + @param BackGround The background color of the string being printed. This is + an optional parameter that may be NULL. If it is NULL, + then the background color of the current ConOut device + in the EFI_SYSTEM_TABLE is used. + @param Format A null-terminated ASCII format string. See Print Library + for the supported format string syntax. + @param ... The variable argument list whose contents are accessed based on + the format string specified by Format. + + @return The number of ASCII characters printed. + +**/ +UINTN +EFIAPI +AsciiPrintXY ( + IN UINTN PointX, + IN UINTN PointY, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround, OPTIONAL + IN CONST CHAR8 *Format, + ... + ); + + +/** + Installs and completes the initialization of a Driver Binding Protocol instance. + + Installs the Driver Binding Protocol specified by DriverBinding onto the handle + specified by DriverBindingHandle. If DriverBindingHandle is NULL, then DriverBinding + is installed onto a newly created handle. DriverBindingHandle is typically the same + as the driver's ImageHandle, but it can be different if the driver produces multiple + Driver Binding Protocols. + If DriverBinding is NULL, then ASSERT(). + If DriverBinding can not be installed onto a handle, then ASSERT(). + + @param ImageHandle The image handle of the driver. + @param SystemTable The EFI System Table that was passed to the driver's entry point. + @param DriverBinding A Driver Binding Protocol instance that this driver is producing. + @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this + parameter is NULL, then a new handle is created. + + @retval EFI_SUCCESS The protocol installation completed successfully. + @retval EFI_OUT_OF_RESOURCES There was not enough system resources to install the protocol. + @retval Others Status from gBS->InstallMultipleProtocolInterfaces(). + +**/ +EFI_STATUS +EFIAPI +EfiLibInstallDriverBinding ( + IN CONST EFI_HANDLE ImageHandle, + IN CONST EFI_SYSTEM_TABLE *SystemTable, + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE DriverBindingHandle + ); + + +/** + Uninstalls a Driver Binding Protocol instance. + + If DriverBinding is NULL, then ASSERT(). + If DriverBinding can not be uninstalled, then ASSERT(). + + @param DriverBinding A Driver Binding Protocol instance that this driver produced. + + @retval EFI_SUCCESS The protocol uninstallation successfully completed. + @retval Others Status from gBS->UninstallMultipleProtocolInterfaces(). + +**/ +EFI_STATUS +EFIAPI +EfiLibUninstallDriverBinding ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding + ); + + +/** + Installs and completes the initialization of a Driver Binding Protocol instance and + optionally installs the Component Name, Driver Configuration and Driver Diagnostics Protocols. + + Initializes a driver by installing the Driver Binding Protocol together with the + optional Component Name, optional Driver Configure and optional Driver Diagnostic + Protocols onto the driver's DriverBindingHandle. If DriverBindingHandle is NULL, + then the protocols are installed onto a newly created handle. DriverBindingHandle + is typically the same as the driver's ImageHandle, but it can be different if the + driver produces multiple Driver Binding Protocols. + If DriverBinding is NULL, then ASSERT(). + If the installation fails, then ASSERT(). + + @param ImageHandle The image handle of the driver. + @param SystemTable The EFI System Table that was passed to the driver's entry point. + @param DriverBinding A Driver Binding Protocol instance that this driver is producing. + @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this + parameter is NULL, then a new handle is created. + @param ComponentName A Component Name Protocol instance that this driver is producing. + @param DriverConfiguration A Driver Configuration Protocol instance that this driver is producing. + @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver is producing. + + @retval EFI_SUCCESS The protocol installation completed successfully. + @retval EFI_OUT_OF_RESOURCES There was not enough memory in the pool to install all the protocols. + +**/ +EFI_STATUS +EFIAPI +EfiLibInstallAllDriverProtocols ( + IN CONST EFI_HANDLE ImageHandle, + IN CONST EFI_SYSTEM_TABLE *SystemTable, + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE DriverBindingHandle, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL + ); + + +/** + Uninstalls a Driver Binding Protocol instance and optionally uninstalls the + Component Name, Driver Configuration and Driver Diagnostics Protocols. + + If DriverBinding is NULL, then ASSERT(). + If the uninstallation fails, then ASSERT(). + + @param DriverBinding A Driver Binding Protocol instance that this driver produced. + @param ComponentName A Component Name Protocol instance that this driver produced. + @param DriverConfiguration A Driver Configuration Protocol instance that this driver produced. + @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver produced. + + @retval EFI_SUCCESS The protocol uninstallation successfully completed. + @retval Others Status from gBS->UninstallMultipleProtocolInterfaces(). + +**/ +EFI_STATUS +EFIAPI +EfiLibUninstallAllDriverProtocols ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL + ); + + +/** + Installs Driver Binding Protocol with optional Component Name and Component Name 2 Protocols. + + Initializes a driver by installing the Driver Binding Protocol together with the + optional Component Name and optional Component Name 2 protocols onto the driver's + DriverBindingHandle. If DriverBindingHandle is NULL, then the protocols are installed + onto a newly created handle. DriverBindingHandle is typically the same as the driver's + ImageHandle, but it can be different if the driver produces multiple Driver Binding Protocols. + If DriverBinding is NULL, then ASSERT(). + If the installation fails, then ASSERT(). + + @param ImageHandle The image handle of the driver. + @param SystemTable The EFI System Table that was passed to the driver's entry point. + @param DriverBinding A Driver Binding Protocol instance that this driver is producing. + @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this + parameter is NULL, then a new handle is created. + @param ComponentName A Component Name Protocol instance that this driver is producing. + @param ComponentName2 A Component Name 2 Protocol instance that this driver is producing. + + @retval EFI_SUCCESS The protocol installation completed successfully. + @retval EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols. + +**/ +EFI_STATUS +EFIAPI +EfiLibInstallDriverBindingComponentName2 ( + IN CONST EFI_HANDLE ImageHandle, + IN CONST EFI_SYSTEM_TABLE *SystemTable, + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE DriverBindingHandle, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL + ); + + +/** + Uninstalls Driver Binding Protocol with optional Component Name and Component Name 2 Protocols. + + If DriverBinding is NULL, then ASSERT(). + If the uninstallation fails, then ASSERT(). + + @param DriverBinding A Driver Binding Protocol instance that this driver produced. + @param ComponentName A Component Name Protocol instance that this driver produced. + @param ComponentName2 A Component Name 2 Protocol instance that this driver produced. + + @retval EFI_SUCCESS The protocol installation successfully completed. + @retval Others Status from gBS->UninstallMultipleProtocolInterfaces(). + +**/ +EFI_STATUS +EFIAPI +EfiLibUninstallDriverBindingComponentName2 ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL + ); + + +/** + Installs Driver Binding Protocol with optional Component Name, Component Name 2, Driver + Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols. + + Initializes a driver by installing the Driver Binding Protocol together with the optional + Component Name, optional Component Name 2, optional Driver Configuration, optional Driver Configuration 2, + optional Driver Diagnostic, and optional Driver Diagnostic 2 Protocols onto the driver's DriverBindingHandle. + DriverBindingHandle is typically the same as the driver's ImageHandle, but it can be different if the driver + produces multiple Driver Binding Protocols. + If DriverBinding is NULL, then ASSERT(). + If the installation fails, then ASSERT(). + + + @param ImageHandle The image handle of the driver. + @param SystemTable The EFI System Table that was passed to the driver's entry point. + @param DriverBinding A Driver Binding Protocol instance that this driver is producing. + @param DriverBindingHandle The handle that DriverBinding is to be installed onto. If this + parameter is NULL, then a new handle is created. + @param ComponentName A Component Name Protocol instance that this driver is producing. + @param ComponentName2 A Component Name 2 Protocol instance that this driver is producing. + @param DriverConfiguration A Driver Configuration Protocol instance that this driver is producing. + @param DriverConfiguration2 A Driver Configuration Protocol 2 instance that this driver is producing. + @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver is producing. + @param DriverDiagnostics2 A Driver Diagnostics Protocol 2 instance that this driver is producing. + + @retval EFI_SUCCESS The protocol installation completed successfully. + @retval EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols. + +**/ +EFI_STATUS +EFIAPI +EfiLibInstallAllDriverProtocols2 ( + IN CONST EFI_HANDLE ImageHandle, + IN CONST EFI_SYSTEM_TABLE *SystemTable, + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN EFI_HANDLE DriverBindingHandle, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL + ); + + +/** + Uninstalls Driver Binding Protocol with optional Component Name, Component Name 2, Driver + Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols. + + If DriverBinding is NULL, then ASSERT(). + If the installation fails, then ASSERT(). + + + @param DriverBinding A Driver Binding Protocol instance that this driver produced. + @param ComponentName A Component Name Protocol instance that this driver produced. + @param ComponentName2 A Component Name 2 Protocol instance that this driver produced. + @param DriverConfiguration A Driver Configuration Protocol instance that this driver produced. + @param DriverConfiguration2 A Driver Configuration Protocol 2 instance that this driver produced. + @param DriverDiagnostics A Driver Diagnostics Protocol instance that this driver produced. + @param DriverDiagnostics2 A Driver Diagnostics Protocol 2 instance that this driver produced. + + @retval EFI_SUCCESS The protocol uninstallation successfully completed. + @retval Others Status from gBS->UninstallMultipleProtocolInterfaces(). + +**/ +EFI_STATUS +EFIAPI +EfiLibUninstallAllDriverProtocols2 ( + IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding, + IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName, OPTIONAL + IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration, OPTIONAL + IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics, OPTIONAL + IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL + ); + + +/** + Appends a formatted Unicode string to a Null-terminated Unicode string + + This function appends a formatted Unicode string to the Null-terminated + Unicode string specified by String. String is optional and may be NULL. + Storage for the formatted Unicode string returned is allocated using + AllocatePool(). The pointer to the appended string is returned. The caller + is responsible for freeing the returned string. + + If String is not NULL and not aligned on a 16-bit boundary, then ASSERT(). + If FormatString is NULL, then ASSERT(). + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] String A Null-terminated Unicode string. + @param[in] FormatString A Null-terminated Unicode format string. + @param[in] Marker VA_LIST marker for the variable argument list. + + @retval NULL There was not enough available memory. + @return Null-terminated Unicode string is that is the formatted + string appended to String. +**/ +CHAR16* +EFIAPI +CatVSPrint ( + IN CHAR16 *String, OPTIONAL + IN CONST CHAR16 *FormatString, + IN VA_LIST Marker + ); + +/** + Appends a formatted Unicode string to a Null-terminated Unicode string + + This function appends a formatted Unicode string to the Null-terminated + Unicode string specified by String. String is optional and may be NULL. + Storage for the formatted Unicode string returned is allocated using + AllocatePool(). The pointer to the appended string is returned. The caller + is responsible for freeing the returned string. + + If String is not NULL and not aligned on a 16-bit boundary, then ASSERT(). + If FormatString is NULL, then ASSERT(). + If FormatString is not aligned on a 16-bit boundary, then ASSERT(). + + @param[in] String A Null-terminated Unicode string. + @param[in] FormatString A Null-terminated Unicode format string. + @param[in] ... The variable argument list whose contents are + accessed based on the format string specified by + FormatString. + + @retval NULL There was not enough available memory. + @return Null-terminated Unicode string is that is the formatted + string appended to String. +**/ +CHAR16 * +EFIAPI +CatSPrint ( + IN CHAR16 *String, OPTIONAL + IN CONST CHAR16 *FormatString, + ... + ); + +/** + Returns an array of protocol instance that matches the given protocol. + + @param[in] Protocol Provides the protocol to search for. + @param[out] NoProtocols The number of protocols returned in Buffer. + @param[out] Buffer A pointer to the buffer to return the requested + array of protocol instances that match Protocol. + The returned buffer is allocated using + EFI_BOOT_SERVICES.AllocatePool(). The caller is + responsible for freeing this buffer with + EFI_BOOT_SERVICES.FreePool(). + + @retval EFI_SUCCESS The array of protocols was returned in Buffer, + and the number of protocols in Buffer was + returned in NoProtocols. + @retval EFI_NOT_FOUND No protocols found. + @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the + matching results. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + @retval EFI_INVALID_PARAMETER NoProtocols is NULL. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + +**/ +EFI_STATUS +EFIAPI +EfiLocateProtocolBuffer ( + IN EFI_GUID *Protocol, + OUT UINTN *NoProtocols, + OUT VOID ***Buffer + ); + +/** + Open or create a file or directory, possibly creating the chain of + directories leading up to the directory. + + EfiOpenFileByDevicePath() first locates EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on + FilePath, and opens the root directory of that filesystem with + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume(). + + On the remaining device path, the longest initial sequence of + FILEPATH_DEVICE_PATH nodes is node-wise traversed with + EFI_FILE_PROTOCOL.Open(). + + (As a consequence, if OpenMode includes EFI_FILE_MODE_CREATE, and Attributes + includes EFI_FILE_DIRECTORY, and each FILEPATH_DEVICE_PATH specifies a single + pathname component, then EfiOpenFileByDevicePath() ensures that the specified + series of subdirectories exist on return.) + + The EFI_FILE_PROTOCOL identified by the last FILEPATH_DEVICE_PATH node is + output to the caller; intermediate EFI_FILE_PROTOCOL instances are closed. If + there are no FILEPATH_DEVICE_PATH nodes past the node that identifies the + filesystem, then the EFI_FILE_PROTOCOL of the root directory of the + filesystem is output to the caller. If a device path node that is different + from FILEPATH_DEVICE_PATH is encountered relative to the filesystem, the + traversal is stopped with an error, and a NULL EFI_FILE_PROTOCOL is output. + + @param[in,out] FilePath On input, the device path to the file or directory + to open or create. The caller is responsible for + ensuring that the device path pointed-to by FilePath + is well-formed. On output, FilePath points one past + the last node in the original device path that has + been successfully processed. FilePath is set on + output even if EfiOpenFileByDevicePath() returns an + error. + + @param[out] File On error, File is set to NULL. On success, File is + set to the EFI_FILE_PROTOCOL of the root directory + of the filesystem, if there are no + FILEPATH_DEVICE_PATH nodes in FilePath; otherwise, + File is set to the EFI_FILE_PROTOCOL identified by + the last node in FilePath. + + @param[in] OpenMode The OpenMode parameter to pass to + EFI_FILE_PROTOCOL.Open(). + + @param[in] Attributes The Attributes parameter to pass to + EFI_FILE_PROTOCOL.Open(). + + @retval EFI_SUCCESS The file or directory has been opened or + created. + + @retval EFI_INVALID_PARAMETER FilePath is NULL; or File is NULL; or FilePath + contains a device path node, past the node + that identifies + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, that is not a + FILEPATH_DEVICE_PATH node. + + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. + + @return Error codes propagated from the + LocateDevicePath() and OpenProtocol() boot + services, and from the + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume() + and EFI_FILE_PROTOCOL.Open() member functions. +**/ +EFI_STATUS +EFIAPI +EfiOpenFileByDevicePath ( + IN OUT EFI_DEVICE_PATH_PROTOCOL **FilePath, + OUT EFI_FILE_PROTOCOL **File, + IN UINT64 OpenMode, + IN UINT64 Attributes + ); + +/** + This function locates next ACPI table in XSDT/RSDT based on Signature and + previous returned Table. + + If PreviousTable is NULL: + This function will locate the first ACPI table in XSDT/RSDT based on + Signature in gEfiAcpi20TableGuid system configuration table first, and then + gEfiAcpi10TableGuid system configuration table. + This function will locate in XSDT first, and then RSDT. + For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in + FADT. + For FACS, this function will locate XFirmwareCtrl in FADT first, and then + FirmwareCtrl in FADT. + + If PreviousTable is not NULL: + 1. If it could be located in XSDT in gEfiAcpi20TableGuid system configuration + table, then this function will just locate next table in XSDT in + gEfiAcpi20TableGuid system configuration table. + 2. If it could be located in RSDT in gEfiAcpi20TableGuid system configuration + table, then this function will just locate next table in RSDT in + gEfiAcpi20TableGuid system configuration table. + 3. If it could be located in RSDT in gEfiAcpi10TableGuid system configuration + table, then this function will just locate next table in RSDT in + gEfiAcpi10TableGuid system configuration table. + + It's not supported that PreviousTable is not NULL but PreviousTable->Signature + is not same with Signature, NULL will be returned. + + @param Signature ACPI table signature. + @param PreviousTable Pointer to previous returned table to locate next + table, or NULL to locate first table. + + @return Next ACPI table or NULL if not found. + +**/ +EFI_ACPI_COMMON_HEADER * +EFIAPI +EfiLocateNextAcpiTable ( + IN UINT32 Signature, + IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL + ); + +/** + This function locates first ACPI table in XSDT/RSDT based on Signature. + + This function will locate the first ACPI table in XSDT/RSDT based on + Signature in gEfiAcpi20TableGuid system configuration table first, and then + gEfiAcpi10TableGuid system configuration table. + This function will locate in XSDT first, and then RSDT. + For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in + FADT. + For FACS, this function will locate XFirmwareCtrl in FADT first, and then + FirmwareCtrl in FADT. + + @param Signature ACPI table signature. + + @return First ACPI table or NULL if not found. + +**/ +EFI_ACPI_COMMON_HEADER * +EFIAPI +EfiLocateFirstAcpiTable ( + IN UINT32 Signature + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeLib.h new file mode 100644 index 0000000000..dd2576bb7d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeLib.h @@ -0,0 +1,581 @@ +/** @file + Provides library functions for each of the UEFI Runtime Services. + Only available to DXE and UEFI module types. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __UEFI_RUNTIME_LIB__ +#define __UEFI_RUNTIME_LIB__ + +/** + This function allows the caller to determine if UEFI ExitBootServices() has been called. + + This function returns TRUE after all the EVT_SIGNAL_EXIT_BOOT_SERVICES functions have + executed as a result of the OS calling ExitBootServices(). Prior to this time FALSE + is returned. This function is used by runtime code to decide it is legal to access + services that go away after ExitBootServices(). + + @retval TRUE The system has finished executing the EVT_SIGNAL_EXIT_BOOT_SERVICES event. + @retval FALSE The system has not finished executing the EVT_SIGNAL_EXIT_BOOT_SERVICES event. + +**/ +BOOLEAN +EFIAPI +EfiAtRuntime ( + VOID + ); + +/** + This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called. + + This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have + executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE + is returned. This function is used by runtime code to decide it is legal to access services + that go away after SetVirtualAddressMap(). + + @retval TRUE The system has finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. + @retval FALSE The system has not finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event. + +**/ +BOOLEAN +EFIAPI +EfiGoneVirtual ( + VOID + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetTime(). + + The GetTime() function returns a time that was valid sometime during the call to the function. + While the returned EFI_TIME structure contains TimeZone and Daylight savings time information, + the actual clock does not maintain these values. The current time zone and daylight saving time + information returned by GetTime() are the values that were last set via SetTime(). + The GetTime() function should take approximately the same amount of time to read the time each + time it is called. All reported device capabilities are to be rounded up. + During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize + access to the device before calling GetTime(). + + @param Time A pointer to storage to receive a snapshot of the current time. + @param Capabilities An optional pointer to a buffer to receive the real time clock device's + capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +EfiGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL + ); + +/** + This service is a wrapper for the UEFI Runtime Service SetTime(). + + The SetTime() function sets the real time clock device to the supplied time, and records the + current time zone and daylight savings time information. The SetTime() function is not allowed + to loop based on the current time. For example, if the device does not support a hardware reset + for the sub-resolution time, the code is not to implement the feature by waiting for the time to + wrap. + During runtime, if a PC-AT CMOS device is present in the platform, the caller must synchronize + access to the device before calling SetTime(). + + @param Time A pointer to the current time. Type EFI_TIME is defined in the GetTime() + function description. Full error checking is performed on the different + fields of the EFI_TIME structure (refer to the EFI_TIME definition in the + GetTime() function description for full details), and EFI_INVALID_PARAMETER + is returned if any field is out of range. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +EfiSetTime ( + IN EFI_TIME *Time + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetWakeupTime(). + + The alarm clock time may be rounded from the set alarm clock time to be within the resolution + of the alarm clock device. The resolution of the alarm clock device is defined to be one second. + During runtime, if a PC-AT CMOS device is present in the platform the caller must synchronize + access to the device before calling GetWakeupTime(). + + @param Enabled Indicates if the alarm is currently enabled or disabled. + @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param Time The current alarm setting. Type EFI_TIME is defined in the GetTime() + function description. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Enabled is NULL. + @retval EFI_INVALID_PARAMETER Pending is NULL. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +EfiGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ); + +/** + This service is a wrapper for the UEFI Runtime Service SetWakeupTime() + + Setting a system wakeup alarm causes the system to wake up or power on at the set time. + When the alarm fires, the alarm signal is latched until it is acknowledged by calling SetWakeupTime() + to disable the alarm. If the alarm fires before the system is put into a sleeping or off state, + since the alarm signal is latched the system will immediately wake up. If the alarm fires while + the system is off and there is insufficient power to power on the system, the system is powered + on when power is restored. + + @param Enable Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wakeup alarm for. Type EFI_TIME + is defined in the GetTime() function description. If Enable is FALSE, + then this parameter is optional, and may be NULL. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. + If Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +EfiSetWakeupTime ( + IN BOOLEAN Enable, + IN EFI_TIME *Time OPTIONAL + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetVariable(). + + Each vendor may create and manage its own variables without the risk of name conflicts by + using a unique VendorGuid. When a variable is set, its Attributes are supplied to indicate + how the data variable should be stored and maintained by the system. The attributes affect + when the variable may be accessed and volatility of the data. Any attempts to access a variable + that does not have the attribute set for runtime access will yield the EFI_NOT_FOUND error. + If the Data buffer is too small to hold the contents of the variable, the error EFI_BUFFER_TOO_SMALL + is returned and DataSize is set to the required buffer size to obtain the data. + + @param VariableName the name of the vendor's variable, it's a Null-Terminated Unicode String + @param VendorGuid Unify identifier for vendor. + @param Attributes Point to memory location to return the attributes of variable. If the point + is NULL, the parameter would be ignored. + @param DataSize As input, point to the maximum size of return Data-Buffer. + As output, point to the actual size of the returned Data-Buffer. + @param Data Point to return Data-Buffer. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. DataSize has + been updated with the size needed to complete the request. + @retval EFI_INVALID_PARAMETER VariableName is NULL. + @retval EFI_INVALID_PARAMETER VendorGuid is NULL. + @retval EFI_INVALID_PARAMETER DataSize is NULL. + @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error. + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure. +**/ +EFI_STATUS +EFIAPI +EfiGetVariable ( + IN CHAR16 *VariableName, + IN EFI_GUID *VendorGuid, + OUT UINT32 *Attributes OPTIONAL, + IN OUT UINTN *DataSize, + OUT VOID *Data + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetNextVariableName(). + + GetNextVariableName() is called multiple times to retrieve the VariableName and VendorGuid of + all variables currently available in the system. On each call to GetNextVariableName() the + previous results are passed into the interface, and on output the interface returns the next + variable name data. When the entire variable list has been returned, the error EFI_NOT_FOUND + is returned. + + @param VariableNameSize As input, point to maximum size of variable name. + As output, point to actual size of variable name. + @param VariableName As input, supplies the last VariableName that was returned by + GetNextVariableName(). + As output, returns the name of variable. The name + string is Null-Terminated Unicode string. + @param VendorGuid As input, supplies the last VendorGuid that was returned by + GetNextVriableName(). + As output, returns the VendorGuid of the current variable. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The next variable was not found. + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the result. + VariableNameSize has been updated with the size needed + to complete the request. + @retval EFI_INVALID_PARAMETER VariableNameSize is NULL. + @retval EFI_INVALID_PARAMETER VariableName is NULL. + @retval EFI_INVALID_PARAMETER VendorGuid is NULL. + @retval EFI_DEVICE_ERROR The variable name could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +EfiGetNextVariableName ( + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VendorGuid + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetNextVariableName() + + Variables are stored by the firmware and may maintain their values across power cycles. Each vendor + may create and manage its own variables without the risk of name conflicts by using a unique VendorGuid. + + @param VariableName the name of the vendor's variable, as a + Null-Terminated Unicode String + @param VendorGuid Unify identifier for vendor. + @param Attributes Point to memory location to return the attributes of variable. If the point + is NULL, the parameter would be ignored. + @param DataSize The size in bytes of Data-Buffer. + @param Data Point to the content of the variable. + + @retval EFI_SUCCESS The firmware has successfully stored the variable and its data as + defined by the Attributes. + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied, or the + DataSize exceeds the maximum allowed. + @retval EFI_INVALID_PARAMETER VariableName is an empty Unicode string. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data. + @retval EFI_DEVICE_ERROR The variable could not be saved due to a hardware failure. + @retval EFI_WRITE_PROTECTED The variable in question is read-only. + @retval EFI_WRITE_PROTECTED The variable in question cannot be deleted. + @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS + set but the AuthInfo does NOT pass the validation check carried + out by the firmware. + @retval EFI_NOT_FOUND The variable trying to be updated or deleted was not found. + +**/ +EFI_STATUS +EFIAPI +EfiSetVariable ( + IN CHAR16 *VariableName, + IN EFI_GUID *VendorGuid, + IN UINT32 Attributes, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + This service is a wrapper for the UEFI Runtime Service GetNextHighMonotonicCount(). + + The platform's monotonic counter is comprised of two 32-bit quantities: the high 32 bits and + the low 32 bits. During boot service time the low 32-bit value is volatile: it is reset to zero + on every system reset and is increased by 1 on every call to GetNextMonotonicCount(). The high + 32-bit value is nonvolatile and is increased by 1 whenever the system resets or whenever the low + 32-bit count (returned by GetNextMonoticCount()) overflows. + + @param HighCount Pointer to returned value. + + @retval EFI_SUCCESS The next high monotonic count was returned. + @retval EFI_DEVICE_ERROR The device is not functioning properly. + @retval EFI_INVALID_PARAMETER HighCount is NULL. + +**/ +EFI_STATUS +EFIAPI +EfiGetNextHighMonotonicCount ( + OUT UINT32 *HighCount + ); + +/** + This service is a wrapper for the UEFI Runtime Service ResetSystem(). + + The ResetSystem()function resets the entire platform, including all processors and devices,and reboots the system. + Calling this interface with ResetType of EfiResetCold causes a system-wide reset. This sets all circuitry within + the system to its initial state. This type of reset is asynchronous to system operation and operates without regard + to cycle boundaries. EfiResetCold is tantamount to a system power cycle. + Calling this interface with ResetType of EfiResetWarm causes a system-wide initialization. The processors are set to + their initial state, and pending cycles are not corrupted. If the system does not support this reset type, then an + EfiResetCold must be performed. + Calling this interface with ResetType of EfiResetShutdown causes the system to enter a power state equivalent to the + ACPI G2/S5 or G3 states. If the system does not support this reset type, then when the system is rebooted, it should + exhibit the EfiResetCold attributes. + The platform may optionally log the parameters from any non-normal reset that occurs. + The ResetSystem() function does not return. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. If the system reset is part of a normal operation, the status code + would be EFI_SUCCESS. If the system reset is due to some type of failure the most appropriate EFI + Status code would be used. + @param DataSizeThe size, in bytes, of ResetData. + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown the data buffer starts with a + Null-terminated Unicode string, optionally followed by additional binary data. The string is a + description that the caller may use to further indicate the reason for the system reset. ResetData + is only valid if ResetStatus is something other then EFI_SUCCESS. This pointer must be a physical + address. For a ResetType of EfiResetPlatformSpecific the data buffer also starts with a Null-terminated + string that is followed by an EFI_GUID that describes the specific type of reset to perform. +**/ +VOID +EFIAPI +EfiResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + This service is a wrapper for the UEFI Runtime Service ConvertPointer(). + + The ConvertPointer() function is used by an EFI component during the SetVirtualAddressMap() operation. + ConvertPointer()must be called using physical address pointers during the execution of SetVirtualAddressMap(). + + @param DebugDisposition Supplies type information for the pointer being converted. + @param Address The pointer to a pointer that is to be fixed to be the + value needed for the new virtual address mapping being + applied. + + @retval EFI_SUCCESS The pointer pointed to by Address was modified. + @retval EFI_NOT_FOUND The pointer pointed to by Address was not found to be part of + the current memory map. This is normally fatal. + @retval EFI_INVALID_PARAMETER Address is NULL. + @retval EFI_INVALID_PARAMETER *Address is NULL and DebugDispositio + +**/ +EFI_STATUS +EFIAPI +EfiConvertPointer ( + IN UINTN DebugDisposition, + IN OUT VOID **Address + ); + +/** + Determines the new virtual address that is to be used on subsequent memory accesses. + + For IA32, x64, and EBC, this service is a wrapper for the UEFI Runtime Service + ConvertPointer(). See the UEFI Specification for details. + For IPF, this function interprets Address as a pointer to an EFI_PLABEL structure + and both the EntryPoint and GP fields of an EFI_PLABEL are converted from physical + to virtiual addressing. Since IPF allows the GP to point to an address outside + a PE/COFF image, the physical to virtual offset for the EntryPoint field is used + to adjust the GP field. The UEFI Runtime Service ConvertPointer() is used to convert + EntryPoint and the status code for this conversion is always returned. If the convertion + of EntryPoint fails, then neither EntryPoint nor GP are modified. See the UEFI + Specification for details on the UEFI Runtime Service ConvertPointer(). + + @param DebugDisposition Supplies type information for the pointer being converted. + @param Address The pointer to a pointer that is to be fixed to be the + value needed for the new virtual address mapping being + applied. + + @return EFI_STATUS value from EfiConvertPointer(). + +**/ +EFI_STATUS +EFIAPI +EfiConvertFunctionPointer ( + IN UINTN DebugDisposition, + IN OUT VOID **Address + ); + +/** + This service is a wrapper for the UEFI Runtime Service SetVirtualAddressMap(). + + The SetVirtualAddressMap() function is used by the OS loader. The function can only be called + at runtime, and is called by the owner of the system's memory map. I.e., the component which + called ExitBootServices(). All events of type EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE must be signaled + before SetVirtualAddressMap() returns. + + @param MemoryMapSize The size in bytes of VirtualMap. + @param DescriptorSize The size in bytes of an entry in the VirtualMap. + @param DescriptorVersion The version of the structure entries in VirtualMap. + @param VirtualMap An array of memory descriptors which contain new virtual + address mapping information for all runtime ranges. Type + EFI_MEMORY_DESCRIPTOR is defined in the + GetMemoryMap() function description. + + @retval EFI_SUCCESS The virtual address map has been applied. + @retval EFI_UNSUPPORTED EFI firmware is not at runtime, or the EFI firmware is already in + virtual address mapped mode. + @retval EFI_INVALID_PARAMETER DescriptorSize or DescriptorVersion is + invalid. + @retval EFI_NO_MAPPING A virtual address was not supplied for a range in the memory + map that requires a mapping. + @retval EFI_NOT_FOUND A virtual address was supplied for an address that is not found + in the memory map. +**/ +EFI_STATUS +EFIAPI +EfiSetVirtualAddressMap ( + IN UINTN MemoryMapSize, + IN UINTN DescriptorSize, + IN UINT32 DescriptorVersion, + IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap + ); + + +/** + Convert the standard Lib double linked list to a virtual mapping. + + This service uses EfiConvertPointer() to walk a double linked list and convert all the link + pointers to their virtual mappings. This function is only guaranteed to work during the + EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event and calling it at other times has undefined results. + + @param DebugDisposition Supplies type information for the pointer being converted. + @param ListHead Head of linked list to convert. + + @retval EFI_SUCCESS Successfully executed the function. + @retval !EFI_SUCCESS Failed to execute the function. + +**/ +EFI_STATUS +EFIAPI +EfiConvertList ( + IN UINTN DebugDisposition, + IN OUT LIST_ENTRY *ListHead + ); + +/** + This service is a wrapper for the UEFI Runtime Service UpdateCapsule(). + + Passes capsules to the firmware with both virtual and physical mapping. Depending on the intended + consumption, the firmware may process the capsule immediately. If the payload should persist across a + system reset, the reset value returned from EFI_QueryCapsuleCapabilities must be passed into ResetSystem() + and will cause the capsule to be processed by the firmware as part of the reset process. + + @param CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules + being passed into update capsule. Each capsules is assumed to + stored in contiguous virtual memory. The capsules in the + CapsuleHeaderArray must be the same capsules as the + ScatterGatherList. The CapsuleHeaderArray must + have the capsules in the same order as the ScatterGatherList. + @param CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in + CaspuleHeaderArray. + @param ScatterGatherList Physical pointer to a set of + EFI_CAPSULE_BLOCK_DESCRIPTOR that describes the + location in physical memory of a set of capsules. See Related + Definitions for an explanation of how more than one capsule is + passed via this interface. The capsules in the + ScatterGatherList must be in the same order as the + CapsuleHeaderArray. This parameter is only referenced if + the capsules are defined to persist across system reset. + + @retval EFI_SUCCESS A valid capsule was passed. If CAPSULE_FLAGS_PERSIT_ACROSS_RESET is not set, + the capsule has been successfully processed by the firmware. + @retval EFI_INVALID_PARAMETER CapsuleSize is NULL, or an incompatible set of flags were + set in the capsule header. + @retval EFI_INVALID_PARAMETER CapsuleCount is 0 + @retval EFI_DEVICE_ERROR The capsule update was started, but failed due to a device error. + @retval EFI_UNSUPPORTED The capsule type is not supported on this platform. + @retval EFI_OUT_OF_RESOURCES There were insufficient resources to process the capsule. + +**/ +EFI_STATUS +EFIAPI +EfiUpdateCapsule ( + IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, + IN UINTN CapsuleCount, + IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL + ); + + +/** + This service is a wrapper for the UEFI Runtime Service QueryCapsuleCapabilities(). + + The QueryCapsuleCapabilities() function allows a caller to test to see if a capsule or + capsules can be updated via UpdateCapsule(). The Flags values in the capsule header and + size of the entire capsule is checked. + If the caller needs to query for generic capsule capability a fake EFI_CAPSULE_HEADER can be + constructed where CapsuleImageSize is equal to HeaderSize that is equal to sizeof + (EFI_CAPSULE_HEADER). To determine reset requirements, + CAPSULE_FLAGS_PERSIST_ACROSS_RESET should be set in the Flags field of the + EFI_CAPSULE_HEADER. + The firmware must support any capsule that has the + CAPSULE_FLAGS_PERSIST_ACROSS_RESET flag set in EFI_CAPSULE_HEADER. The + firmware sets the policy for what capsules are supported that do not have the + CAPSULE_FLAGS_PERSIST_ACROSS_RESET flag set. + + @param CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules + being passed into update capsule. The capsules are assumed to + stored in contiguous virtual memory. + @param CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in + CaspuleHeaderArray. + @param MaximumCapsuleSize On output the maximum size that UpdateCapsule() can + support as an argument to UpdateCapsule() via + CapsuleHeaderArray and ScatterGatherList. + Undefined on input. + @param ResetType Returns the type of reset required for the capsule update. + + @retval EFI_SUCCESS A valid answer was returned. + @retval EFI_INVALID_PARAMETER MaximumCapsuleSize is NULL. + @retval EFI_UNSUPPORTED The capsule type is not supported on this platform, and + MaximumCapsuleSize and ResetType are undefined. + @retval EFI_OUT_OF_RESOURCES There were insufficient resources to process the query request. + +**/ +EFI_STATUS +EFIAPI +EfiQueryCapsuleCapabilities ( + IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, + IN UINTN CapsuleCount, + OUT UINT64 *MaximumCapsuleSize, + OUT EFI_RESET_TYPE *ResetType + ); + + +/** + This service is a wrapper for the UEFI Runtime Service QueryVariableInfo(). + + The QueryVariableInfo() function allows a caller to obtain the information about the + maximum size of the storage space available for the EFI variables, the remaining size of the storage + space available for the EFI variables and the maximum size of each individual EFI variable, + associated with the attributes specified. + The returned MaximumVariableStorageSize, RemainingVariableStorageSize, + MaximumVariableSize information may change immediately after the call based on other + runtime activities including asynchronous error events. Also, these values associated with different + attributes are not additive in nature. + + @param Attributes Attributes bitmask to specify the type of variables on + which to return information. Refer to the + GetVariable() function description. + @param MaximumVariableStorageSize + On output the maximum size of the storage space + available for the EFI variables associated with the + attributes specified. + @param RemainingVariableStorageSize + Returns the remaining size of the storage space + available for the EFI variables associated with the + attributes specified. + @param MaximumVariableSize Returns the maximum size of the individual EFI + variables associated with the attributes specified. + + @retval EFI_SUCCESS A valid answer was returned. + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied. + @retval EFI_UNSUPPORTED EFI_UNSUPPORTED The attribute is not supported on this platform, and the + MaximumVariableStorageSize, + RemainingVariableStorageSize, MaximumVariableSize + are undefined. + +**/ +EFI_STATUS +EFIAPI +EfiQueryVariableInfo ( + IN UINT32 Attributes, + OUT UINT64 *MaximumVariableStorageSize, + OUT UINT64 *RemainingVariableStorageSize, + OUT UINT64 *MaximumVariableSize + ); + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h new file mode 100644 index 0000000000..daacc2a9e7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h @@ -0,0 +1,26 @@ +/** @file + Provides a service to retrieve a pointer to the EFI Runtime Services Table. + + This library does not contain any functions or macros. It simply exports the + global variable gRT that is a pointer to the EFI Runtime Services Table as defined + in the UEFI Specification. The global variable gRT must be preinitialized to NULL. + The library constructor must set gRT to point at the EFI Runtime Services Table so + it is available at the module's entry point. Since there is overhead in initializing + this global variable, only those modules that actually require access to the EFI + Runtime Services Table should use this library. + Only available to DXE and UEFI module types. + +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_RUNTIME_SERVICES_TABLE_LIB_H__ +#define __UEFI_RUNTIME_SERVICES_TABLE_LIB_H__ + +/// +/// Cached copy of the EFI Runtime Services Table +/// +extern EFI_RUNTIME_SERVICES *gRT; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiScsiLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiScsiLib.h new file mode 100644 index 0000000000..d35ee6b097 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiScsiLib.h @@ -0,0 +1,1303 @@ +/** @file + Provides the functions to submit Scsi commands defined in SCSI-2 specification for SCSI devices. + + This library class provides the functions to submit SCSI commands defined in SCSI-2 specification + for hard drive, CD and DVD devices that are the most common SCSI boot targets used by UEFI platforms. + This library class depends on SCSI I/O Protocol defined in UEFI Specification and SCSI-2 industry standard. + +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SCSI_LIB_H__ +#define __SCSI_LIB_H__ + +#include + +/** + Execute Test Unit Ready SCSI command on a specific SCSI target. + + Executes the Test Unit Ready command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance + for the specific SCSI target. + @param[in] Timeout The timeout in 100 ns units to use for the execution + of this SCSI Request Packet. A Timeout value of + zero means that this function will wait indefinitely + for the SCSI Request Packet to execute. If Timeout + is greater than zero, then this function will return + EFI_TIMEOUT if the time required to execute the SCSI + Request Packet is greater than Timeout. + @param[in, out] SenseData A pointer to sense data that was generated by + the execution of the SCSI Request Packet. This + buffer must be allocated by the caller. + If SenseDataLength is 0, then this parameter is + optional and may be NULL. + @param[in, out] SenseDataLength On input, a pointer to the length in bytes of + the SenseData buffer. On output, a pointer to + the number of bytes written to the SenseData buffer. + @param[out] HostAdapterStatus The status of the SCSI Host Controller that produces + the SCSI bus containing the SCSI target specified by + ScsiIo when the SCSI Request Packet was executed. + See the EFI SCSI I/O Protocol in the UEFI Specification + for details on the possible return values. + @param[out] TargetStatus The status returned by the SCSI target specified + by ScsiIo when the SCSI Request Packet was executed + on the SCSI Host Controller. See the EFI SCSI I/O + Protocol in the UEFI Specification for details on + the possible return values. + + @retval EFI_SUCCESS The command was executed successfully. + See HostAdapterStatus, TargetStatus, SenseDataLength, + and SenseData in that order for additional status + information. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Command Packets already + queued. The SCSI Request Packet was not sent, so + no additional status information is available. + The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + SCSI Request Packet. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in that + order for additional status information. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the SCSI initiator(i.e., SCSI + Host Controller). The SCSI Request Packet was not + sent, so no additional status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request + Packet to execute. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for + additional status information. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiTestUnitReadyCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus + ); + + +/** + Execute Inquiry SCSI command on a specific SCSI target. + + Executes the Inquiry command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If InquiryDataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If InquiryDataLength is non-zero and InquiryDataBuffer is not NULL, InquiryDataBuffer + must meet buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance + for the specific SCSI target. + @param[in] Timeout The timeout in 100 ns units to use for the + execution of this SCSI Request Packet. A Timeout + value of zero means that this function will wait + indefinitely for the SCSI Request Packet to execute. + If Timeout is greater than zero, then this function + will return EFI_TIMEOUT if the time required to + execute the SCSI Request Packet is greater than Timeout. + @param[in, out] SenseData A pointer to sense data that was generated + by the execution of the SCSI Request Packet. + This buffer must be allocated by the caller. + If SenseDataLength is 0, then this parameter + is optional and may be NULL. + @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer. + On output, the number of bytes written to the SenseData buffer. + @param[out] HostAdapterStatus The status of the SCSI Host Controller that + produces the SCSI bus containing the SCSI + target specified by ScsiIo when the SCSI + Request Packet was executed. See the EFI + SCSI I/O Protocol in the UEFI Specification + for details on the possible return values. + @param[out] TargetStatus The status returned by the SCSI target specified + by ScsiIo when the SCSI Request Packet was + executed on the SCSI Host Controller. + See the EFI SCSI I/O Protocol in the UEFI + Specification for details on the possible + return values. + @param[in, out] InquiryDataBuffer A pointer to inquiry data that was generated + by the execution of the SCSI Request Packet. + This buffer must be allocated by the caller. + If InquiryDataLength is 0, then this parameter + is optional and may be NULL. + @param[in, out] InquiryDataLength On input, a pointer to the length in bytes + of the InquiryDataBuffer buffer. + On output, a pointer to the number of bytes + written to the InquiryDataBuffer buffer. + @param[in] EnableVitalProductData If TRUE, then the supported vital product + data is returned in InquiryDataBuffer. + If FALSE, then the standard inquiry data is + returned in InquiryDataBuffer. + + @retval EFI_SUCCESS The command was executed successfully. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in that order + for additional status information. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire + InquiryDataBuffer could not be transferred. The actual + number of bytes transferred is returned in InquiryDataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there + are too many SCSI Command Packets already queued. + The SCSI Request Packet was not sent, so no additional + status information is available. The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI + Request Packet. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for additional + status information. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not + supported by the SCSI initiator(i.e., SCSI Host Controller). + The SCSI Request Packet was not sent, so no additional + status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request + Packet to execute. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for + additional status information. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiInquiryCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *InquiryDataBuffer, OPTIONAL + IN OUT UINT32 *InquiryDataLength, + IN BOOLEAN EnableVitalProductData + ); + + +/** + Execute Inquiry SCSI command on a specific SCSI target. + + Executes the Inquiry command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If InquiryDataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If InquiryDataLength is non-zero and InquiryDataBuffer is not NULL, InquiryDataBuffer + must meet buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance + for the specific SCSI target. + @param[in] Timeout The timeout in 100 ns units to use for the + execution of this SCSI Request Packet. A Timeout + value of zero means that this function will wait + indefinitely for the SCSI Request Packet to execute. + If Timeout is greater than zero, then this function + will return EFI_TIMEOUT if the time required to + execute the SCSI Request Packet is greater than Timeout. + @param[in, out] SenseData A pointer to sense data that was generated + by the execution of the SCSI Request Packet. + This buffer must be allocated by the caller. + If SenseDataLength is 0, then this parameter + is optional and may be NULL. + @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer. + On output, the number of bytes written to the SenseData buffer. + @param[out] HostAdapterStatus The status of the SCSI Host Controller that + produces the SCSI bus containing the SCSI + target specified by ScsiIo when the SCSI + Request Packet was executed. See the EFI + SCSI I/O Protocol in the UEFI Specification + for details on the possible return values. + @param[out] TargetStatus The status returned by the SCSI target specified + by ScsiIo when the SCSI Request Packet was + executed on the SCSI Host Controller. + See the EFI SCSI I/O Protocol in the UEFI + Specification for details on the possible + return values. + @param[in, out] InquiryDataBuffer A pointer to inquiry data that was generated + by the execution of the SCSI Request Packet. + This buffer must be allocated by the caller. + If InquiryDataLength is 0, then this parameter + is optional and may be NULL. + @param[in, out] InquiryDataLength On input, a pointer to the length in bytes + of the InquiryDataBuffer buffer. + On output, a pointer to the number of bytes + written to the InquiryDataBuffer buffer. + @param[in] EnableVitalProductData If TRUE, then the supported vital product + data for the PageCode is returned in InquiryDataBuffer. + If FALSE, then the standard inquiry data is + returned in InquiryDataBuffer and PageCode is ignored. + @param[in] PageCode The page code of the vital product data. + It's ignored if EnableVitalProductData is FALSE. + + @retval EFI_SUCCESS The command executed successfully. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in that order + for additional status information. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire + InquiryDataBuffer could not be transferred. The actual + number of bytes transferred is returned in InquiryDataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there + are too many SCSI Command Packets already queued. + The SCSI Request Packet was not sent, so no additional + status information is available. The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI + Request Packet. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for additional + status information. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not + supported by the SCSI initiator(i.e., SCSI Host Controller). + The SCSI Request Packet was not sent, so no additional + status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request + Packet to execute. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for + additional status information. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiInquiryCommandEx ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *InquiryDataBuffer, OPTIONAL + IN OUT UINT32 *InquiryDataLength, + IN BOOLEAN EnableVitalProductData, + IN UINT8 PageCode + ); + + +/** + Execute Mode Sense(10) SCSI command on a specific SCSI target. + + Executes the SCSI Mode Sense(10) command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout + after Timeout 100 ns units. The DBDField, PageControl, and PageCode parameters + are used to construct the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to the SCSI I/O Protocol instance + for the specific SCSI target. + @param[in] Timeout The timeout in 100 ns units to use for the + execution of this SCSI Request Packet. A Timeout + value of zero means that this function will wait + indefinitely for the SCSI Request Packet to execute. + If Timeout is greater than zero, then this function + will return EFI_TIMEOUT if the time required to + execute the SCSI Request Packet is greater than Timeout. + @param[in, out] SenseData A pointer to sense data that was generated + by the execution of the SCSI Request Packet. + This buffer must be allocated by the caller. + If SenseDataLength is 0, then this parameter + is optional and may be NULL. + @param[in, out] SenseDataLength On input, the length in bytes of the SenseData buffer. + On output, the number of bytes written to the SenseData buffer. + @param[out] HostAdapterStatus The status of the SCSI Host Controller that + produces the SCSI bus containing the SCSI target + specified by ScsiIo when the SCSI Request Packet + was executed. See the EFI SCSI I/O Protocol in the + UEFI Specification for details on the possible + return values. + @param[out] TargetStatus The status returned by the SCSI target specified + by ScsiIo when the SCSI Request Packet was executed + on the SCSI Host Controller. See the EFI SCSI + I/O Protocol in the UEFI Specification for details + on the possible return values. + @param[in, out] DataBuffer A pointer to data that was generated by the + execution of the SCSI Request Packet. This + buffer must be allocated by the caller. If + DataLength is 0, then this parameter is optional + and may be NULL. + @param[in, out] DataLength On input, a pointer to the length in bytes of + the DataBuffer buffer. On output, a pointer + to the number of bytes written to the DataBuffer + buffer. + @param[in] DBDField Specifies the DBD field of the CDB for this SCSI Command. + @param[in] PageControl Specifies the PC field of the CDB for this SCSI Command. + @param[in] PageCode Specifies the Page Control field of the CDB for this SCSI Command. + + @retval EFI_SUCCESS The command was executed successfully. + See HostAdapterStatus, TargetStatus, SenseDataLength, + and SenseData in that order for additional status information. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the + entire DataBuffer could not be transferred. + The actual number of bytes transferred is returned + in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Command Packets already queued. + The SCSI Request Packet was not sent, so no additional + status information is available. The caller may retry + again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + SCSI Request Packet. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order for + additional status information. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the SCSI initiator(i.e., SCSI + Host Controller). The SCSI Request Packet was not + sent, so no additional status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI + Request Packet to execute. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in that + order for additional status information. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiModeSense10Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT8 DBDField, OPTIONAL + IN UINT8 PageControl, + IN UINT8 PageCode + ); + + + +/** + Execute Request Sense SCSI command on a specific SCSI target. + + Executes the Request Sense command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are + too many SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiRequestSenseCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus + ); + + +/** + Execute Read Capacity SCSI command on a specific SCSI target. + + Executes the SCSI Read Capacity command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. The Pmi parameter is used to construct the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] Pmi Partial medium indicator. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire + DataBuffer could not be transferred. The actual + number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiReadCapacityCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN BOOLEAN Pmi + ); + + +/** + Execute Read Capacity SCSI 16 command on a specific SCSI target. + + Executes the SCSI Read Capacity 16 command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. The Pmi parameter is used to construct the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] Pmi Partial medium indicator. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire + DataBuffer could not be transferred. The actual + number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiReadCapacity16Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN BOOLEAN Pmi + ); + + +/** + Execute Read(10) SCSI command on a specific SCSI target. + + Executes the SCSI Read(10) command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout + after Timeout 100 ns units. The StartLba and SectorSize parameters are used to + construct the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer Read 10 command data. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiRead10Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT32 StartLba, + IN UINT32 SectorSize + ); + + +/** + Execute Write(10) SCSI command on a specific SCSI target. + + Executes the SCSI Write(10) command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. The StartLba and SectorSize parameters are used to construct + the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiWrite10Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT32 StartLba, + IN UINT32 SectorSize + ); + +/** + Execute Read(16) SCSI command on a specific SCSI target. + + Executes the SCSI Read(16) command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout + after Timeout 100 ns units. The StartLba and SectorSize parameters are used to + construct the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer Read 16 command data. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiRead16Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT64 StartLba, + IN UINT32 SectorSize + ); + + +/** + Execute Write(16) SCSI command on a specific SCSI target. + + Executes the SCSI Write(16) command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. The StartLba and SectorSize parameters are used to construct + the CDB for this SCSI command. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks of data that shall be transferred. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiWrite16Command ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT64 StartLba, + IN UINT32 SectorSize + ); + + +/** + Execute Security Protocol In SCSI command on a specific SCSI target. + + Executes the SCSI Security Protocol In command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If TransferLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in] SecurityProtocol The Security Protocol to use. + @param[in] SecurityProtocolSpecific The Security Protocol Specific data. + @param[in] Inc512 If TRUE, 512 increment (INC_512) bit will be set for the + SECURITY PROTOCOL IN command. + @param[in] DataLength The size in bytes of the data buffer. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[out] TransferLength A pointer to a buffer to store the size in + bytes of the data written to the data buffer. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in TransferLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiSecurityProtocolInCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN UINT8 SecurityProtocol, + IN UINT16 SecurityProtocolSpecific, + IN BOOLEAN Inc512, + IN UINTN DataLength, + IN OUT VOID *DataBuffer, OPTIONAL + OUT UINTN *TransferLength + ); + + +/** + Execute Security Protocol Out SCSI command on a specific SCSI target. + + Executes the SCSI Security Protocol Out command on the SCSI target specified by ScsiIo. + If Timeout is zero, then this function waits indefinitely for the command to complete. + If Timeout is greater than zero, then the command is executed and will timeout after + Timeout 100 ns units. + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer + alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER + gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in] SecurityProtocol The Security Protocol to use. + @param[in] SecurityProtocolSpecific The Security Protocol Specific data. + @param[in] Inc512 If TRUE, 512 increment (INC_512) bit will be set for the + SECURITY PROTOCOL OUT command. + @param[in] DataLength The size in bytes of the transfer data. + @param[in, out] DataBuffer A pointer to a data buffer. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the entire DataBuffer could + not be transferred. The actual number of bytes transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported by + the SCSI initiator(i.e., SCSI Host Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet are invalid. + +**/ +EFI_STATUS +EFIAPI +ScsiSecurityProtocolOutCommand ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN UINT8 SecurityProtocol, + IN UINT16 SecurityProtocolSpecific, + IN BOOLEAN Inc512, + IN UINTN DataLength, + IN OUT VOID *DataBuffer OPTIONAL + ); + + +/** + Execute blocking/non-blocking Read(10) SCSI command on a specific SCSI + target. + + Executes the SCSI Read(10) command on the SCSI target specified by ScsiIo. + When Event is NULL, blocking command will be executed. Otherwise non-blocking + command will be executed. + For blocking I/O, if Timeout is zero, this function will wait indefinitely + for the command to complete. If Timeout is greater than zero, then the + command is executed and will timeout after Timeout 100 ns units. + For non-blocking I/O, if Timeout is zero, Event will be signaled only after + the command to completes. If Timeout is greater than zero, Event will also be + signaled after Timeout 100 ns units. + The StartLba and SectorSize parameters are used to construct the CDB for this + SCSI command. + + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer Read 16 command data. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks + of data that shall be transferred. + @param[in] Event If the SCSI target does not support + non-blocking I/O, then Event is ignored, + and blocking I/O is performed. If Event + is NULL, then blocking I/O is performed. + If Event is not NULL and non-blocking + I/O is supported, then non-blocking I/O + is performed, and Event will be signaled + when the SCSI Read(10) command + completes. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, + but the entire DataBuffer could not be + transferred. The actual number of bytes + transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be + sent because there are too many SCSI + Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting + to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI + Request Packet is not supported by the + SCSI initiator(i.e., SCSI Host + Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the + SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet + are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due + to a lack of resources. + +**/ +EFI_STATUS +EFIAPI +ScsiRead10CommandEx ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT32 StartLba, + IN UINT32 SectorSize, + IN EFI_EVENT Event OPTIONAL + ); + + +/** + Execute blocking/non-blocking Write(10) SCSI command on a specific SCSI + target. + + Executes the SCSI Write(10) command on the SCSI target specified by ScsiIo. + When Event is NULL, blocking command will be executed. Otherwise non-blocking + command will be executed. + For blocking I/O, if Timeout is zero, this function will wait indefinitely + for the command to complete. If Timeout is greater than zero, then the + command is executed and will timeout after Timeout 100 ns units. + For non-blocking I/O, if Timeout is zero, Event will be signaled only after + the command to completes. If Timeout is greater than zero, Event will also be + signaled after Timeout 100 ns units. + The StartLba and SectorSize parameters are used to construct the CDB for this + SCSI command. + + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks + of data that shall be transferred. + @param[in] Event If the SCSI target does not support + non-blocking I/O, then Event is ignored, + and blocking I/O is performed. If Event + is NULL, then blocking I/O is performed. + If Event is not NULL and non-blocking + I/O is supported, then non-blocking I/O + is performed, and Event will be signaled + when the SCSI Write(10) command + completes. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, + but the entire DataBuffer could not be + transferred. The actual number of bytes + transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be + sent because there are too many SCSI + Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting + to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI + Request Packet is not supported by the + SCSI initiator(i.e., SCSI Host + Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the + SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet + are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due + to a lack of resources. + +**/ +EFI_STATUS +EFIAPI +ScsiWrite10CommandEx ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT32 StartLba, + IN UINT32 SectorSize, + IN EFI_EVENT Event OPTIONAL + ); + + +/** + Execute blocking/non-blocking Read(16) SCSI command on a specific SCSI + target. + + Executes the SCSI Read(16) command on the SCSI target specified by ScsiIo. + When Event is NULL, blocking command will be executed. Otherwise non-blocking + command will be executed. + For blocking I/O, if Timeout is zero, this function will wait indefinitely + for the command to complete. If Timeout is greater than zero, then the + command is executed and will timeout after Timeout 100 ns units. + For non-blocking I/O, if Timeout is zero, Event will be signaled only after + the command to completes. If Timeout is greater than zero, Event will also be + signaled after Timeout 100 ns units. + The StartLba and SectorSize parameters are used to construct the CDB for this + SCSI command. + + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo A pointer to SCSI IO protocol. + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer Read 16 command data. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks + of data that shall be transferred. + @param[in] Event If the SCSI target does not support + non-blocking I/O, then Event is ignored, + and blocking I/O is performed. If Event + is NULL, then blocking I/O is performed. + If Event is not NULL and non-blocking + I/O is supported, then non-blocking I/O + is performed, and Event will be signaled + when the SCSI Read(16) command + completes. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, + but the entire DataBuffer could not be + transferred. The actual number of bytes + transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be + sent because there are too many SCSI + Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting + to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI + Request Packet is not supported by the + SCSI initiator(i.e., SCSI Host + Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the + SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet + are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due + to a lack of resources. + +**/ +EFI_STATUS +EFIAPI +ScsiRead16CommandEx ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT64 StartLba, + IN UINT32 SectorSize, + IN EFI_EVENT Event OPTIONAL + ); + + +/** + Execute blocking/non-blocking Write(16) SCSI command on a specific SCSI + target. + + Executes the SCSI Write(16) command on the SCSI target specified by ScsiIo. + When Event is NULL, blocking command will be executed. Otherwise non-blocking + command will be executed. + For blocking I/O, if Timeout is zero, this function will wait indefinitely + for the command to complete. If Timeout is greater than zero, then the + command is executed and will timeout after Timeout 100 ns units. + For non-blocking I/O, if Timeout is zero, Event will be signaled only after + the command to completes. If Timeout is greater than zero, Event will also be + signaled after Timeout 100 ns units. + The StartLba and SectorSize parameters are used to construct the CDB for this + SCSI command. + + If ScsiIo is NULL, then ASSERT(). + If SenseDataLength is NULL, then ASSERT(). + If HostAdapterStatus is NULL, then ASSERT(). + If TargetStatus is NULL, then ASSERT(). + If DataLength is NULL, then ASSERT(). + + If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet + buffer alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise + EFI_INVALID_PARAMETER gets returned. + + @param[in] ScsiIo SCSI IO Protocol to use + @param[in] Timeout The length of timeout period. + @param[in, out] SenseData A pointer to output sense data. + @param[in, out] SenseDataLength The length of output sense data. + @param[out] HostAdapterStatus The status of Host Adapter. + @param[out] TargetStatus The status of the target. + @param[in, out] DataBuffer A pointer to a data buffer. + @param[in, out] DataLength The length of data buffer. + @param[in] StartLba The start address of LBA. + @param[in] SectorSize The number of contiguous logical blocks + of data that shall be transferred. + @param[in] Event If the SCSI target does not support + non-blocking I/O, then Event is ignored, + and blocking I/O is performed. If Event + is NULL, then blocking I/O is performed. + If Event is not NULL and non-blocking + I/O is supported, then non-blocking I/O + is performed, and Event will be signaled + when the SCSI Write(16) command + completes. + + @retval EFI_SUCCESS Command is executed successfully. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, + but the entire DataBuffer could not be + transferred. The actual number of bytes + transferred is returned in DataLength. + @retval EFI_NOT_READY The SCSI Request Packet could not be + sent because there are too many SCSI + Command Packets already queued. + @retval EFI_DEVICE_ERROR A device error occurred while attempting + to send SCSI Request Packet. + @retval EFI_UNSUPPORTED The command described by the SCSI + Request Packet is not supported by the + SCSI initiator(i.e., SCSI Host + Controller) + @retval EFI_TIMEOUT A timeout occurred while waiting for the + SCSI Request Packet to execute. + @retval EFI_INVALID_PARAMETER The contents of the SCSI Request Packet + are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due + to a lack of resources. + +**/ +EFI_STATUS +EFIAPI +ScsiWrite16CommandEx ( + IN EFI_SCSI_IO_PROTOCOL *ScsiIo, + IN UINT64 Timeout, + IN OUT VOID *SenseData, OPTIONAL + IN OUT UINT8 *SenseDataLength, + OUT UINT8 *HostAdapterStatus, + OUT UINT8 *TargetStatus, + IN OUT VOID *DataBuffer, OPTIONAL + IN OUT UINT32 *DataLength, + IN UINT64 StartLba, + IN UINT32 SectorSize, + IN EFI_EVENT Event OPTIONAL + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiUsbLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiUsbLib.h new file mode 100644 index 0000000000..256c060ea7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UefiUsbLib.h @@ -0,0 +1,557 @@ +/** @file + Provides most USB APIs to support the Hid requests defined in USB Hid 1.1 spec + and the standard requests defined in USB 1.1 spec. + +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __USB_DXE_LIB_H__ +#define __USB_DXE_LIB_H__ + +#include + +/** + Get the descriptor of the specified USB HID interface. + + Submit a UsbGetHidDescriptor() request for the USB device specified by UsbIo + and Interface, and return the HID descriptor in HidDescriptor. + If UsbIo is NULL, then ASSERT(). + If HidDescriptor is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the HID interface on the USB target. + @param HidDescriptor Pointer to the USB HID descriptor that was retrieved from + the specified USB target and interface. Type EFI_USB_HID_DESCRIPTOR + is defined in the MDE Package Industry Standard include file Usb.h. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbGetHidDescriptor ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor + ); + + +/** + Get the report descriptor of the specified USB HID interface. + + Submit a USB get HID report descriptor request for the USB device specified by + UsbIo and Interface, and return the report descriptor in DescriptorBuffer. + If UsbIo is NULL, then ASSERT(). + If DescriptorBuffer is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param DescriptorLength The size, in bytes, of DescriptorBuffer. + @param DescriptorBuffer A pointer to the buffer to store the report class descriptor. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed because the + buffer specified by DescriptorLength and DescriptorBuffer + is not large enough to hold the result of the request. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbGetReportDescriptor ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT16 DescriptorLength, + OUT UINT8 *DescriptorBuffer + ); + +/** + Get the HID protocol of the specified USB HID interface. + + Submit a USB get HID protocol request for the USB device specified by UsbIo + and Interface, and return the protocol retrieved in Protocol. + If UsbIo is NULL, then ASSERT(). + If Protocol is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param Protocol A pointer to the protocol for the specified USB target. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbGetProtocolRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + OUT UINT8 *Protocol + ); + +/** + Set the HID protocol of the specified USB HID interface. + + Submit a USB set HID protocol request for the USB device specified by UsbIo + and Interface, and set the protocol to the value specified by Protocol. + If UsbIo is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param Protocol The protocol value to set for the specified USB target. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbSetProtocolRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT8 Protocol + ); + +/** + Set the idle rate of the specified USB HID report. + + Submit a USB set HID report idle request for the USB device specified by UsbIo, + Interface, and ReportId, and set the idle rate to the value specified by Duration. + If UsbIo is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param ReportId The identifier of the report to retrieve. + @param Duration The idle rate to set for the specified USB target. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbSetIdleRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT8 ReportId, + IN UINT8 Duration + ); + +/** + Get the idle rate of the specified USB HID report. + + Submit a USB get HID report idle request for the USB device specified by UsbIo, + Interface, and ReportId, and return the ide rate in Duration. + If UsbIo is NULL, then ASSERT(). + If Duration is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param ReportId The identifier of the report to retrieve. + @param Duration A pointer to the idle rate retrieved from the specified USB target. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbGetIdleRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT8 ReportId, + OUT UINT8 *Duration + ); + +/** + Set the report descriptor of the specified USB HID interface. + + Submit a USB set HID report request for the USB device specified by UsbIo, + Interface, ReportId, and ReportType, and set the report descriptor using the + buffer specified by ReportLength and Report. + If UsbIo is NULL, then ASSERT(). + If Report is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param ReportId The identifier of the report to retrieve. + @param ReportType The type of report to retrieve. + @param ReportLength The size, in bytes, of Report. + @param Report A pointer to the report descriptor buffer to set. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbSetReportRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT8 ReportId, + IN UINT8 ReportType, + IN UINT16 ReportLen, + IN UINT8 *Report + ); + +/** + Get the report descriptor of the specified USB HID interface. + + Submit a USB get HID report request for the USB device specified by UsbIo, + Interface, ReportId, and ReportType, and return the report in the buffer + specified by Report. + If UsbIo is NULL, then ASSERT(). + If Report is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The index of the report interface on the USB target. + @param ReportId The identifier of the report to retrieve. + @param ReportType The type of report to retrieve. + @param ReportLength The size, in bytes, of Report. + @param Report A pointer to the buffer to store the report descriptor. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed because the + buffer specified by ReportLength and Report is not + large enough to hold the result of the request. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + +**/ +EFI_STATUS +EFIAPI +UsbGetReportRequest ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Interface, + IN UINT8 ReportId, + IN UINT8 ReportType, + IN UINT16 ReportLen, + OUT UINT8 *Report + ); + +/** + Get the descriptor of the specified USB device. + + Submit a USB get descriptor request for the USB device specified by UsbIo, Value, + and Index, and return the descriptor in the buffer specified by Descriptor. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Descriptor is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Value The device request value. + @param Index The device request index. + @param DescriptorLength The size, in bytes, of Descriptor. + @param Descriptor A pointer to the descriptor buffer to get. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed because the + buffer specified by DescriptorLength and Descriptor + is not large enough to hold the result of the request. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. The transfer + status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbGetDescriptor ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT16 Value, + IN UINT16 Index, + IN UINT16 DescriptorLength, + OUT VOID *Descriptor, + OUT UINT32 *Status + ); + +/** + Set the descriptor of the specified USB device. + + Submit a USB set descriptor request for the USB device specified by UsbIo, + Value, and Index, and set the descriptor using the buffer specified by DesriptorLength + and Descriptor. The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Descriptor is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Value The device request value. + @param Index The device request index. + @param DescriptorLength The size, in bytes, of Descriptor. + @param Descriptor A pointer to the descriptor buffer to set. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbSetDescriptor ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT16 Value, + IN UINT16 Index, + IN UINT16 DescriptorLength, + IN VOID *Descriptor, + OUT UINT32 *Status + ); + +/** + Get the interface setting of the specified USB device. + + Submit a USB get interface request for the USB device specified by UsbIo, + and Interface, and place the result in the buffer specified by AlternateSetting. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If AlternateSetting is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The interface index value. + @param AlternateSetting A pointer to the alternate setting to be retrieved. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbGetInterface ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT16 Interface, + OUT UINT16 *AlternateSetting, + OUT UINT32 *Status + ); + +/** + Set the interface setting of the specified USB device. + + Submit a USB set interface request for the USB device specified by UsbIo, and + Interface, and set the alternate setting to the value specified by AlternateSetting. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Interface The interface index value. + @param AlternateSetting The alternate setting to be set. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_SUCCESS The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbSetInterface ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT16 Interface, + IN UINT16 AlternateSetting, + OUT UINT32 *Status + ); + +/** + Get the device configuration. + + Submit a USB get configuration request for the USB device specified by UsbIo + and place the result in the buffer specified by ConfigurationValue. The status + of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If ConfigurationValue is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param ConfigurationValue A pointer to the device configuration to be retrieved. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbGetConfiguration ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + OUT UINT16 *ConfigurationValue, + OUT UINT32 *Status + ); + +/** + Set the device configuration. + + Submit a USB set configuration request for the USB device specified by UsbIo + and set the device configuration to the value specified by ConfigurationValue. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param ConfigurationValue The device configuration value to be set. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbSetConfiguration ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT16 ConfigurationValue, + OUT UINT32 *Status + ); + +/** + Set the specified feature of the specified device. + + Submit a USB set device feature request for the USB device specified by UsbIo, + Recipient, and Target to the value specified by Value. The status of the + transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint). + Type USB_TYPES_DEFINITION is defined in the MDE Package Industry + Standard include file Usb.h. + @param Value The value of the feature to be set. + @param Target The index of the device to be set. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbSetFeature ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN USB_TYPES_DEFINITION Recipient, + IN UINT16 Value, + IN UINT16 Target, + OUT UINT32 *Status + ); + +/** + Clear the specified feature of the specified device. + + Submit a USB clear device feature request for the USB device specified by UsbIo, + Recipient, and Target to the value specified by Value. The status of the transfer + is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint). + Type USB_TYPES_DEFINITION is defined in the MDE Package Industry Standard + include file Usb.h. + @param Value The value of the feature to be cleared. + @param Target The index of the device to be cleared. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbClearFeature ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN USB_TYPES_DEFINITION Recipient, + IN UINT16 Value, + IN UINT16 Target, + OUT UINT32 *Status + ); + +/** + Get the status of the specified device. + + Submit a USB device get status request for the USB device specified by UsbIo, + Recipient, and Target, and place the result in the buffer specified by DeviceStatus. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If DeviceStatus is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Recipient The USB data recipient type (i.e. Device, Interface, Endpoint). + Type USB_TYPES_DEFINITION is defined in the MDE Package Industry Standard + include file Usb.h. + @param Target The index of the device to be get the status of. + @param DeviceStatus A pointer to the device status to be retrieved. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + +**/ +EFI_STATUS +EFIAPI +UsbGetStatus ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN USB_TYPES_DEFINITION Recipient, + IN UINT16 Target, + OUT UINT16 *DeviceStatus, + OUT UINT32 *Status + ); + +/** + Clear halt feature of the specified usb endpoint. + + Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint. + If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND. + If the endpoint descriptor is found, then clear the halt feature of this USB endpoint. + The status of the transfer is returned in Status. + If UsbIo is NULL, then ASSERT(). + If Status is NULL, then ASSERT(). + + @param UsbIo A pointer to the USB I/O Protocol instance for the specific USB target. + @param Endpoint The endpoint address. + @param Status A pointer to the status of the transfer. + + @retval EFI_SUCCESS The request executed successfully. + @retval EFI_TIMEOUT A timeout occurred executing the request. + @retval EFI_DEVICE_ERROR The request failed due to a device error. + The transfer status is returned in Status. + @retval EFI_NOT_FOUND The specified USB endpoint descriptor can not be found + +**/ +EFI_STATUS +EFIAPI +UsbClearEndpointHalt ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Endpoint, + OUT UINT32 *Status + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UnitTestLib.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UnitTestLib.h new file mode 100644 index 0000000000..cfb591e270 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Library/UnitTestLib.h @@ -0,0 +1,844 @@ +/** @file + Provides a unit test framework. This allows tests to focus on testing logic + and the framework to focus on runnings, reporting, statistics, etc. + + Copyright (c) Microsoft Corporation.
+ Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __UNIT_TEST_LIB_H__ +#define __UNIT_TEST_LIB_H__ + +/// +/// Unit Test Status +/// +typedef UINT32 UNIT_TEST_STATUS; +#define UNIT_TEST_PASSED (0) +#define UNIT_TEST_ERROR_PREREQUISITE_NOT_MET (1) +#define UNIT_TEST_ERROR_TEST_FAILED (2) +#define UNIT_TEST_ERROR_CLEANUP_FAILED (3) +#define UNIT_TEST_SKIPPED (0xFFFFFFFD) +#define UNIT_TEST_RUNNING (0xFFFFFFFE) +#define UNIT_TEST_PENDING (0xFFFFFFFF) + +/// +/// Declare PcdUnitTestLogLevel bits and UnitTestLog() ErrorLevel parameter. +/// +#define UNIT_TEST_LOG_LEVEL_ERROR BIT0 +#define UNIT_TEST_LOG_LEVEL_WARN BIT1 +#define UNIT_TEST_LOG_LEVEL_INFO BIT2 +#define UNIT_TEST_LOG_LEVEL_VERBOSE BIT3 + +/// +/// Unit Test Framework Handle +/// +struct UNIT_TEST_FRAMEWORK_OBJECT; +typedef struct UNIT_TEST_FRAMEWORK_OBJECT *UNIT_TEST_FRAMEWORK_HANDLE; + +/// +/// Unit Test Suite Handle +/// +struct UNIT_TEST_SUITE_OBJECT; +typedef struct UNIT_TEST_SUITE_OBJECT *UNIT_TEST_SUITE_HANDLE; + +/// +/// Unit Test Handle +/// +struct UNIT_TEST_OBJECT; +typedef struct UNIT_TEST_OBJECT *UNIT_TEST_HANDLE; + +/// +/// Unit Test Context +/// +typedef VOID* UNIT_TEST_CONTEXT; + +/** + The prototype for a single UnitTest case function. + + Functions with this prototype are registered to be dispatched by the + UnitTest framework, and results are recorded as test Pass or Fail. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that the + contents are well understood by all test cases that may + consume it. + + @retval UNIT_TEST_PASSED The Unit test has completed and the test + case was successful. + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. + +**/ +typedef +UNIT_TEST_STATUS +(EFIAPI *UNIT_TEST_FUNCTION)( + IN UNIT_TEST_CONTEXT Context + ); + +/** + Unit-Test Prerequisite Function pointer type. + + Functions with this prototype are registered to be dispatched by the unit test + framework prior to a given test case. If this prereq function returns + UNIT_TEST_ERROR_PREREQUISITE_NOT_MET, the test case will be skipped. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that the + contents are well understood by all test cases that may + consume it. + + @retval UNIT_TEST_PASSED Unit test case prerequisites + are met. + @retval UNIT_TEST_ERROR_PREREQUISITE_NOT_MET Test case should be skipped. + +**/ +typedef +UNIT_TEST_STATUS +(EFIAPI *UNIT_TEST_PREREQUISITE)( + IN UNIT_TEST_CONTEXT Context + ); + +/** + Unit-Test Cleanup (after) function pointer type. + + Functions with this prototype are registered to be dispatched by the + unit test framework after a given test case. This will be called even if the + test case returns an error, but not if the prerequisite fails and the test is + skipped. The purpose of this function is to clean up any global state or + test data. + + @param[in] Context [Optional] An optional parameter that enables: + 1) test-case reuse with varied parameters and + 2) test-case re-entry for Target tests that need a + reboot. This parameter is a VOID* and it is the + responsibility of the test author to ensure that the + contents are well understood by all test cases that may + consume it. + + @retval UNIT_TEST_PASSED Test case cleanup succeeded. + @retval UNIT_TEST_ERROR_CLEANUP_FAILED Test case cleanup failed. + +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_CLEANUP)( + IN UNIT_TEST_CONTEXT Context + ); + +/** + Unit-Test Test Suite Setup (before) function pointer type. Functions with this + prototype are registered to be dispatched by the UnitTest framework prior to + running any of the test cases in a test suite. It will only be run once at + the beginning of the suite (not prior to each case). + + The purpose of this function is to set up any global state or test data. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_SUITE_SETUP)( + VOID + ); + +/** + Unit-Test Test Suite Teardown (after) function pointer type. Functions with + this prototype are registered to be dispatched by the UnitTest framework after + running all of the test cases in a test suite. It will only be run once at + the end of the suite. + + The purpose of this function is to clean up any global state or test data. +**/ +typedef +VOID +(EFIAPI *UNIT_TEST_SUITE_TEARDOWN)( + VOID + ); + +/** + Method to Initialize the Unit Test framework. This function registers the + test name and also initializes the internal state of the test framework to + receive any new suites and tests. + + @param[out] FrameworkHandle Unit test framework to be created. + @param[in] Title Null-terminated ASCII string that is the user + friendly name of the framework. String is + copied. + @param[in] ShortTitle Null-terminated ASCII short string that is the + short name of the framework with no spaces. + String is copied. + @param[in] VersionString Null-terminated ASCII version string for the + framework. String is copied. + + @retval EFI_SUCCESS The unit test framework was initialized. + @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL. + @retval EFI_INVALID_PARAMETER Title is NULL. + @retval EFI_INVALID_PARAMETER ShortTitle is NULL. + @retval EFI_INVALID_PARAMETER VersionString is NULL. + @retval EFI_INVALID_PARAMETER ShortTitle is invalid. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to + initialize the unit test framework. +**/ +EFI_STATUS +EFIAPI +InitUnitTestFramework ( + OUT UNIT_TEST_FRAMEWORK_HANDLE *FrameworkHandle, + IN CHAR8 *Title, + IN CHAR8 *ShortTitle, + IN CHAR8 *VersionString + ); + +/** + Registers a Unit Test Suite in the Unit Test Framework. + At least one test suite must be registered, because all test cases must be + within a unit test suite. + + @param[out] SuiteHandle Unit test suite to create + @param[in] FrameworkHandle Unit test framework to add unit test suite to + @param[in] Title Null-terminated ASCII string that is the user + friendly name of the test suite. String is + copied. + @param[in] Name Null-terminated ASCII string that is the short + name of the test suite with no spaces. String + is copied. + @param[in] Setup Setup function, runs before suite. This is an + optional parameter that may be NULL. + @param[in] Teardown Teardown function, runs after suite. This is an + optional parameter that may be NULL. + + @retval EFI_SUCCESS The unit test suite was created. + @retval EFI_INVALID_PARAMETER SuiteHandle is NULL. + @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL. + @retval EFI_INVALID_PARAMETER Title is NULL. + @retval EFI_INVALID_PARAMETER Name is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to + initialize the unit test suite. +**/ +EFI_STATUS +EFIAPI +CreateUnitTestSuite ( + OUT UNIT_TEST_SUITE_HANDLE *SuiteHandle, + IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle, + IN CHAR8 *Title, + IN CHAR8 *Name, + IN UNIT_TEST_SUITE_SETUP Setup OPTIONAL, + IN UNIT_TEST_SUITE_TEARDOWN Teardown OPTIONAL + ); + +/** + Adds test case to Suite + + @param[in] SuiteHandle Unit test suite to add test to. + @param[in] Description Null-terminated ASCII string that is the user + friendly description of a test. String is copied. + @param[in] Name Null-terminated ASCII string that is the short name + of the test with no spaces. String is copied. + @param[in] Function Unit test function. + @param[in] Prerequisite Prerequisite function, runs before test. This is + an optional parameter that may be NULL. + @param[in] CleanUp Clean up function, runs after test. This is an + optional parameter that may be NULL. + @param[in] Context Pointer to context. This is an optional parameter + that may be NULL. + + @retval EFI_SUCCESS The unit test case was added to Suite. + @retval EFI_INVALID_PARAMETER SuiteHandle is NULL. + @retval EFI_INVALID_PARAMETER Description is NULL. + @retval EFI_INVALID_PARAMETER Name is NULL. + @retval EFI_INVALID_PARAMETER Function is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to + add the unit test case to Suite. +**/ +EFI_STATUS +EFIAPI +AddTestCase ( + IN UNIT_TEST_SUITE_HANDLE SuiteHandle, + IN CHAR8 *Description, + IN CHAR8 *Name, + IN UNIT_TEST_FUNCTION Function, + IN UNIT_TEST_PREREQUISITE Prerequisite OPTIONAL, + IN UNIT_TEST_CLEANUP CleanUp OPTIONAL, + IN UNIT_TEST_CONTEXT Context OPTIONAL + ); + +/** + Execute all unit test cases in all unit test suites added to a Framework. + + Once a unit test framework is initialized and all unit test suites and unit + test cases are registered, this function will cause the unit test framework to + dispatch all unit test cases in sequence and record the results for reporting. + + @param[in] FrameworkHandle A handle to the current running framework that + dispatched the test. Necessary for recording + certain test events with the framework. + + @retval EFI_SUCCESS All test cases were dispatched. + @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL. +**/ +EFI_STATUS +EFIAPI +RunAllTestSuites ( + IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle + ); + +/** + Cleanup a test framework. + + After tests are run, this will teardown the entire framework and free all + allocated data within. + + @param[in] FrameworkHandle A handle to the current running framework that + dispatched the test. Necessary for recording + certain test events with the framework. + + @retval EFI_SUCCESS All resources associated with framework were + freed. + @retval EFI_INVALID_PARAMETER FrameworkHandle is NULL. +**/ +EFI_STATUS +EFIAPI +FreeUnitTestFramework ( + IN UNIT_TEST_FRAMEWORK_HANDLE FrameworkHandle + ); + +/** + Leverages a framework-specific mechanism (see UnitTestPersistenceLib if you're + a framework author) to save the state of the executing framework along with + any allocated data so that the test may be resumed upon reentry. A test case + should pass any needed context (which, to prevent an infinite loop, should be + at least the current execution count) which will be saved by the framework and + passed to the test case upon resume. + + This should be called while the current test framework is valid and active. It is + generally called from within a test case prior to quitting or rebooting. + + @param[in] ContextToSave A buffer of test case-specific data to be saved + along with framework state. Will be passed as + "Context" to the test case upon resume. This + is an optional parameter that may be NULL. + @param[in] ContextToSaveSize Size of the ContextToSave buffer. + + @retval EFI_SUCCESS The framework state and context were saved. + @retval EFI_NOT_FOUND An active framework handle was not found. + @retval EFI_INVALID_PARAMETER ContextToSave is not NULL and + ContextToSaveSize is 0. + @retval EFI_INVALID_PARAMETER ContextToSave is >= 4GB. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to + save the framework and context state. + @retval EFI_DEVICE_ERROR The framework and context state could not be + saved to a persistent storage device due to a + device error. +**/ +EFI_STATUS +EFIAPI +SaveFrameworkState ( + IN UNIT_TEST_CONTEXT ContextToSave OPTIONAL, + IN UINTN ContextToSaveSize + ); + +/** + This macro uses the framework assertion logic to check an expression for + "TRUE". If the expression evaluates to TRUE, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] Expression Expression to be evaluated for TRUE. +**/ +#define UT_ASSERT_TRUE(Expression) \ + if(!UnitTestAssertTrue ((Expression), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Expression)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check an expression for + "FALSE". If the expression evaluates to FALSE, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] Expression Expression to be evaluated for FALSE. +**/ +#define UT_ASSERT_FALSE(Expression) \ + if(!UnitTestAssertFalse ((Expression), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Expression)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether two simple + values are equal. If the values are equal, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] ValueA Value to be compared for equality (64-bit comparison). + @param[in] ValueB Value to be compared for equality (64-bit comparison). +**/ +#define UT_ASSERT_EQUAL(ValueA, ValueB) \ + if(!UnitTestAssertEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #ValueA, #ValueB)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether two memory + buffers are equal. If the buffers are equal, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] BufferA Pointer to a buffer for comparison. + @param[in] BufferB Pointer to a buffer for comparison. + @param[in] Length Number of bytes to compare in BufferA and BufferB. +**/ +#define UT_ASSERT_MEM_EQUAL(BufferA, BufferB, Length) \ + if(!UnitTestAssertMemEqual ((VOID *)(UINTN)(BufferA), (VOID *)(UINTN)(BufferB), (UINTN)Length, __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #BufferA, #BufferB)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether two simple + values are non-equal. If the values are non-equal, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] ValueA Value to be compared for inequality (64-bit comparison). + @param[in] ValueB Value to be compared for inequality (64-bit comparison). +**/ +#define UT_ASSERT_NOT_EQUAL(ValueA, ValueB) \ + if(!UnitTestAssertNotEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #ValueA, #ValueB)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether an EFI_STATUS + value is !EFI_ERROR(). If the status is !EFI_ERROR(), execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] Status EFI_STATUS value to check. +**/ +#define UT_ASSERT_NOT_EFI_ERROR(Status) \ + if(!UnitTestAssertNotEfiError ((Status), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Status)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether two EFI_STATUS + values are equal. If the values are equal, execution continues. + Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] Status EFI_STATUS values to compare for equality. + @param[in] Expected EFI_STATUS values to compare for equality. +**/ +#define UT_ASSERT_STATUS_EQUAL(Status, Expected) \ + if(!UnitTestAssertStatusEqual ((Status), (Expected), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Status)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether a pointer is + not NULL. If the pointer is not NULL, execution continues. Otherwise, the + test case immediately returns UNIT_TEST_ERROR_TEST_FAILED. + + @param[in] Pointer Pointer to be checked against NULL. +**/ +#define UT_ASSERT_NOT_NULL(Pointer) \ + if(!UnitTestAssertNotNull ((Pointer), __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, #Pointer)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } + +/** + This macro uses the framework assertion logic to check whether a function call + triggers an ASSERT() condition. The BaseLib SetJump()/LongJump() services + are used to establish a safe return point when an ASSERT() is triggered. + If an ASSERT() is triggered, unit test execution continues and Status is set + to UNIT_TEST_PASSED. Otherwise, a unit test case failure is raised and + Status is set to UNIT_TEST_ERROR_TEST_FAILED. + + If ASSERT() macros are disabled, then the test case is skipped and a warning + message is added to the unit test log. Status is set to UNIT_TEST_SKIPPED. + + @param[in] FunctionCall Function call that is expected to trigger ASSERT(). + @param[out] Status Pointer to a UNIT_TEST_STATUS return value. This + is an optional parameter that may be NULL. +**/ +#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED) + #include + + /// + /// Pointer to jump buffer used with SetJump()/LongJump() to test if a + /// function under test generates an expected ASSERT() condition. + /// + extern BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer; + + #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) \ + do { \ + UNIT_TEST_STATUS UnitTestJumpStatus; \ + BASE_LIBRARY_JUMP_BUFFER UnitTestJumpBuffer; \ + UnitTestJumpStatus = UNIT_TEST_SKIPPED; \ + if (DebugAssertEnabled ()) { \ + gUnitTestExpectAssertFailureJumpBuffer = &UnitTestJumpBuffer; \ + if (SetJump (gUnitTestExpectAssertFailureJumpBuffer) == 0) { \ + FunctionCall; \ + UnitTestJumpStatus = UNIT_TEST_ERROR_TEST_FAILED; \ + } else { \ + UnitTestJumpStatus = UNIT_TEST_PASSED; \ + } \ + gUnitTestExpectAssertFailureJumpBuffer = NULL; \ + } \ + if (!UnitTestExpectAssertFailure ( \ + UnitTestJumpStatus, \ + __FUNCTION__, DEBUG_LINE_NUMBER, __FILE__, \ + #FunctionCall, Status)) { \ + return UNIT_TEST_ERROR_TEST_FAILED; \ + } \ + } while (FALSE) +#else + #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) FunctionCall; +#endif + +/** + If Expression is TRUE, then TRUE is returned. + If Expression is FALSE, then an assert is triggered and the location of the + assert provided by FunctionName, LineNumber, FileName, and Description are + recorded and FALSE is returned. + + @param[in] Expression The BOOLEAN result of the expression evaluation. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] Description Null-terminated ASCII string of the expression being + evaluated. + + @retval TRUE Expression is TRUE. + @retval FALSE Expression is FALSE. +**/ +BOOLEAN +EFIAPI +UnitTestAssertTrue ( + IN BOOLEAN Expression, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *Description + ); + +/** + If Expression is FALSE, then TRUE is returned. + If Expression is TRUE, then an assert is triggered and the location of the + assert provided by FunctionName, LineNumber, FileName, and Description are + recorded and FALSE is returned. + + @param[in] Expression The BOOLEAN result of the expression evaluation. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] Description Null-terminated ASCII string of the expression being + evaluated. + + @retval TRUE Expression is FALSE. + @retval FALSE Expression is TRUE. +**/ +BOOLEAN +EFIAPI +UnitTestAssertFalse ( + IN BOOLEAN Expression, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *Description + ); + +/** + If Status is not an EFI_ERROR(), then TRUE is returned. + If Status is an EFI_ERROR(), then an assert is triggered and the location of + the assert provided by FunctionName, LineNumber, FileName, and Description are + recorded and FALSE is returned. + + @param[in] Status The EFI_STATUS value to evaluate. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] Description Null-terminated ASCII string of the status + expression being evaluated. + + @retval TRUE Status is not an EFI_ERROR(). + @retval FALSE Status is an EFI_ERROR(). +**/ +BOOLEAN +EFIAPI +UnitTestAssertNotEfiError ( + IN EFI_STATUS Status, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *Description + ); + +/** + If ValueA is equal ValueB, then TRUE is returned. + If ValueA is not equal to ValueB, then an assert is triggered and the location + of the assert provided by FunctionName, LineNumber, FileName, DescriptionA, + and DescriptionB are recorded and FALSE is returned. + + @param[in] ValueA 64-bit value. + @param[in] ValueB 64-bit value. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] DescriptionA Null-terminated ASCII string that is a description + of ValueA. + @param[in] DescriptionB Null-terminated ASCII string that is a description + of ValueB. + + @retval TRUE ValueA is equal to ValueB. + @retval FALSE ValueA is not equal to ValueB. +**/ +BOOLEAN +EFIAPI +UnitTestAssertEqual ( + IN UINT64 ValueA, + IN UINT64 ValueB, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *DescriptionA, + IN CONST CHAR8 *DescriptionB + ); + +/** + If the contents of BufferA are identical to the contents of BufferB, then TRUE + is returned. If the contents of BufferA are not identical to the contents of + BufferB, then an assert is triggered and the location of the assert provided + by FunctionName, LineNumber, FileName, DescriptionA, and DescriptionB are + recorded and FALSE is returned. + + @param[in] BufferA Pointer to a buffer for comparison. + @param[in] BufferB Pointer to a buffer for comparison. + @param[in] Length Number of bytes to compare in BufferA and BufferB. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] DescriptionA Null-terminated ASCII string that is a description + of BufferA. + @param[in] DescriptionB Null-terminated ASCII string that is a description + of BufferB. + + @retval TRUE The contents of BufferA are identical to the contents of + BufferB. + @retval FALSE The contents of BufferA are not identical to the contents of + BufferB. +**/ +BOOLEAN +EFIAPI +UnitTestAssertMemEqual ( + IN VOID *BufferA, + IN VOID *BufferB, + IN UINTN Length, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *DescriptionA, + IN CONST CHAR8 *DescriptionB + ); + +/** + If ValueA is not equal ValueB, then TRUE is returned. + If ValueA is equal to ValueB, then an assert is triggered and the location + of the assert provided by FunctionName, LineNumber, FileName, DescriptionA + and DescriptionB are recorded and FALSE is returned. + + @param[in] ValueA 64-bit value. + @param[in] ValueB 64-bit value. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] DescriptionA Null-terminated ASCII string that is a description + of ValueA. + @param[in] DescriptionB Null-terminated ASCII string that is a description + of ValueB. + + @retval TRUE ValueA is not equal to ValueB. + @retval FALSE ValueA is equal to ValueB. +**/ +BOOLEAN +EFIAPI +UnitTestAssertNotEqual ( + IN UINT64 ValueA, + IN UINT64 ValueB, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *DescriptionA, + IN CONST CHAR8 *DescriptionB + ); + +/** + If Status is equal to Expected, then TRUE is returned. + If Status is not equal to Expected, then an assert is triggered and the + location of the assert provided by FunctionName, LineNumber, FileName, and + Description are recorded and FALSE is returned. + + @param[in] Status EFI_STATUS value returned from an API under test. + @param[in] Expected The expected EFI_STATUS return value from an API + under test. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] Description Null-terminated ASCII string that is a description + of Status. + + @retval TRUE Status is equal to Expected. + @retval FALSE Status is not equal to Expected. +**/ +BOOLEAN +EFIAPI +UnitTestAssertStatusEqual ( + IN EFI_STATUS Status, + IN EFI_STATUS Expected, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *Description + ); + +/** + If Pointer is not equal to NULL, then TRUE is returned. + If Pointer is equal to NULL, then an assert is triggered and the location of + the assert provided by FunctionName, LineNumber, FileName, and PointerName + are recorded and FALSE is returned. + + @param[in] Pointer Pointer value to be checked against NULL. + @param[in] Expected The expected EFI_STATUS return value from a function + under test. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the assert macro. + @param[in] LineNumber The source file line number of the assert macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the assert macro. + @param[in] PointerName Null-terminated ASCII string that is a description + of Pointer. + + @retval TRUE Pointer is not equal to NULL. + @retval FALSE Pointer is equal to NULL. +**/ +BOOLEAN +EFIAPI +UnitTestAssertNotNull ( + IN VOID *Pointer, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *PointerName + ); + +/** + If UnitTestStatus is UNIT_TEST_PASSED, then log an info message and return + TRUE because an ASSERT() was expected when FunctionCall was executed and an + ASSERT() was triggered. If UnitTestStatus is UNIT_TEST_SKIPPED, then log a + warning message and return TRUE because ASSERT() macros are disabled. If + UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED, then log an error message and + return FALSE because an ASSERT() was expected when FunctionCall was executed, + but no ASSERT() conditions were triggered. The log messages contain + FunctionName, LineNumber, and FileName strings to provide the location of the + UT_EXPECT_ASSERT_FAILURE() macro. + + @param[in] UnitTestStatus The status from UT_EXPECT_ASSERT_FAILURE() that + is either pass, skipped, or failed. + @param[in] FunctionName Null-terminated ASCII string of the function + executing the UT_EXPECT_ASSERT_FAILURE() macro. + @param[in] LineNumber The source file line number of the the function + executing the UT_EXPECT_ASSERT_FAILURE() macro. + @param[in] FileName Null-terminated ASCII string of the filename + executing the UT_EXPECT_ASSERT_FAILURE() macro. + @param[in] FunctionCall Null-terminated ASCII string of the function call + executed by the UT_EXPECT_ASSERT_FAILURE() macro. + @param[out] ResultStatus Used to return the UnitTestStatus value to the + caller of UT_EXPECT_ASSERT_FAILURE(). This is + optional parameter that may be NULL. + + @retval TRUE UnitTestStatus is UNIT_TEST_PASSED. + @retval TRUE UnitTestStatus is UNIT_TEST_SKIPPED. + @retval FALSE UnitTestStatus is UNIT_TEST_ERROR_TEST_FAILED. +**/ +BOOLEAN +EFIAPI +UnitTestExpectAssertFailure ( + IN UNIT_TEST_STATUS UnitTestStatus, + IN CONST CHAR8 *FunctionName, + IN UINTN LineNumber, + IN CONST CHAR8 *FileName, + IN CONST CHAR8 *FunctionCall, + OUT UNIT_TEST_STATUS *ResultStatus OPTIONAL + ); + +/** + Test logging macro that records an ERROR message in the test framework log. + Record is associated with the currently executing test case. + + @param[in] Format Formatting string following the format defined in + MdePkg/Include/Library/PrintLib.h. + @param[in] ... Print args. +**/ +#define UT_LOG_ERROR(Format, ...) \ + UnitTestLog (UNIT_TEST_LOG_LEVEL_ERROR, Format, ##__VA_ARGS__) + +/** + Test logging macro that records a WARNING message in the test framework log. + Record is associated with the currently executing test case. + + @param[in] Format Formatting string following the format defined in + MdePkg/Include/Library/PrintLib.h. + @param[in] ... Print args. +**/ +#define UT_LOG_WARNING(Format, ...) \ + UnitTestLog (UNIT_TEST_LOG_LEVEL_WARN, Format, ##__VA_ARGS__) + +/** + Test logging macro that records an INFO message in the test framework log. + Record is associated with the currently executing test case. + + @param[in] Format Formatting string following the format defined in + MdePkg/Include/Library/PrintLib.h. + @param[in] ... Print args. +**/ +#define UT_LOG_INFO(Format, ...) \ + UnitTestLog (UNIT_TEST_LOG_LEVEL_INFO, Format, ##__VA_ARGS__) + +/** + Test logging macro that records a VERBOSE message in the test framework log. + Record is associated with the currently executing test case. + + @param[in] Format Formatting string following the format defined in + MdePkg/Include/Library/PrintLib.h. + @param[in] ... Print args. +**/ +#define UT_LOG_VERBOSE(Format, ...) \ + UnitTestLog (UNIT_TEST_LOG_LEVEL_VERBOSE, Format, ##__VA_ARGS__) + +/** + Test logging function that records a messages in the test framework log. + Record is associated with the currently executing test case. + + @param[in] ErrorLevel The error level of the unit test log message. + @param[in] Format Formatting string following the format defined in the + MdePkg/Include/Library/PrintLib.h. + @param[in] ... Print args. +**/ +VOID +EFIAPI +UnitTestLog ( + IN UINTN ErrorLevel, + IN CONST CHAR8 *Format, + ... + ); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiBootMode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiBootMode.h new file mode 100644 index 0000000000..74b499a604 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiBootMode.h @@ -0,0 +1,36 @@ +/** @file + Present the boot mode values in PI. + + Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.2.1A + +**/ + +#ifndef __PI_BOOT_MODE_H__ +#define __PI_BOOT_MODE_H__ + +/// +/// EFI boot mode +/// +typedef UINT32 EFI_BOOT_MODE; + +// +// 0x21 - 0xf..f are reserved. +// +#define BOOT_WITH_FULL_CONFIGURATION 0x00 +#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 +#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 +#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 +#define BOOT_WITH_DEFAULT_SETTINGS 0x04 +#define BOOT_ON_S4_RESUME 0x05 +#define BOOT_ON_S5_RESUME 0x06 +#define BOOT_WITH_MFG_MODE_SETTINGS 0x07 +#define BOOT_ON_S2_RESUME 0x10 +#define BOOT_ON_S3_RESUME 0x11 +#define BOOT_ON_FLASH_UPDATE 0x12 +#define BOOT_IN_RECOVERY_MODE 0x20 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDependency.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDependency.h new file mode 100644 index 0000000000..82d59175ab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDependency.h @@ -0,0 +1,41 @@ +/** @file + Present the dependency expression values in PI. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.0 + +**/ +#ifndef __PI_DEPENDENCY_H__ +#define __PI_DEPENDENCY_H__ + +/// +/// If present, this must be the first and only opcode, +/// EFI_DEP_BEFORE may be used by DXE and SMM drivers. +/// +#define EFI_DEP_BEFORE 0x00 + +/// +/// If present, this must be the first and only opcode, +/// EFI_DEP_AFTER may be used by DXE and SMM drivers. +/// +#define EFI_DEP_AFTER 0x01 + +#define EFI_DEP_PUSH 0x02 +#define EFI_DEP_AND 0x03 +#define EFI_DEP_OR 0x04 +#define EFI_DEP_NOT 0x05 +#define EFI_DEP_TRUE 0x06 +#define EFI_DEP_FALSE 0x07 +#define EFI_DEP_END 0x08 + + +/// +/// If present, this must be the first opcode, +/// EFI_DEP_SOR is only used by DXE driver. +/// +#define EFI_DEP_SOR 0x09 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDxeCis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDxeCis.h new file mode 100644 index 0000000000..d69ec89635 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiDxeCis.h @@ -0,0 +1,738 @@ +/** @file + Include file matches things in PI. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.7 + +**/ + +#ifndef __PI_DXECIS_H__ +#define __PI_DXECIS_H__ + +#include +#include + +/// +/// Global Coherencey Domain types - Memory type. +/// +typedef enum { + /// + /// A memory region that is visible to the boot processor. However, there are no system + /// components that are currently decoding this memory region. + /// + EfiGcdMemoryTypeNonExistent, + /// + /// A memory region that is visible to the boot processor. This memory region is being + /// decoded by a system component, but the memory region is not considered to be either + /// system memory or memory-mapped I/O. + /// + EfiGcdMemoryTypeReserved, + /// + /// A memory region that is visible to the boot processor. A memory controller is + /// currently decoding this memory region and the memory controller is producing a + /// tested system memory region that is available to the memory services. + /// + EfiGcdMemoryTypeSystemMemory, + /// + /// A memory region that is visible to the boot processor. This memory region is + /// currently being decoded by a component as memory-mapped I/O that can be used to + /// access I/O devices in the platform. + /// + EfiGcdMemoryTypeMemoryMappedIo, + /// + /// A memory region that is visible to the boot processor. + /// This memory supports byte-addressable non-volatility. + /// + EfiGcdMemoryTypePersistent, + // + // Keep original one for the compatibility. + // + EfiGcdMemoryTypePersistentMemory = EfiGcdMemoryTypePersistent, + /// + /// A memory region that provides higher reliability relative to other memory in the + /// system. If all memory has the same reliability, then this bit is not used. + /// + EfiGcdMemoryTypeMoreReliable, + EfiGcdMemoryTypeMaximum +} EFI_GCD_MEMORY_TYPE; + +/// +/// Global Coherencey Domain types - IO type. +/// +typedef enum { + /// + /// An I/O region that is visible to the boot processor. However, there are no system + /// components that are currently decoding this I/O region. + /// + EfiGcdIoTypeNonExistent, + /// + /// An I/O region that is visible to the boot processor. This I/O region is currently being + /// decoded by a system component, but the I/O region cannot be used to access I/O devices. + /// + EfiGcdIoTypeReserved, + /// + /// An I/O region that is visible to the boot processor. This I/O region is currently being + /// decoded by a system component that is producing I/O ports that can be used to access I/O devices. + /// + EfiGcdIoTypeIo, + EfiGcdIoTypeMaximum +} EFI_GCD_IO_TYPE; + +/// +/// The type of allocation to perform. +/// +typedef enum { + /// + /// The GCD memory space map is searched from the lowest address up to the highest address + /// looking for unallocated memory ranges. + /// + EfiGcdAllocateAnySearchBottomUp, + /// + /// The GCD memory space map is searched from the lowest address up + /// to the specified MaxAddress looking for unallocated memory ranges. + /// + EfiGcdAllocateMaxAddressSearchBottomUp, + /// + /// The GCD memory space map is checked to see if the memory range starting + /// at the specified Address is available. + /// + EfiGcdAllocateAddress, + /// + /// The GCD memory space map is searched from the highest address down to the lowest address + /// looking for unallocated memory ranges. + /// + EfiGcdAllocateAnySearchTopDown, + /// + /// The GCD memory space map is searched from the specified MaxAddress + /// down to the lowest address looking for unallocated memory ranges. + /// + EfiGcdAllocateMaxAddressSearchTopDown, + EfiGcdMaxAllocateType +} EFI_GCD_ALLOCATE_TYPE; + +/// +/// EFI_GCD_MEMORY_SPACE_DESCRIPTOR. +/// +typedef struct { + /// + /// The physical address of the first byte in the memory region. Type + /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function + /// description in the UEFI 2.0 specification. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + + /// + /// The number of bytes in the memory region. + /// + UINT64 Length; + + /// + /// The bit mask of attributes that the memory region is capable of supporting. The bit + /// mask of available attributes is defined in the GetMemoryMap() function description + /// in the UEFI 2.0 specification. + /// + UINT64 Capabilities; + /// + /// The bit mask of attributes that the memory region is currently using. The bit mask of + /// available attributes is defined in GetMemoryMap(). + /// + UINT64 Attributes; + /// + /// Type of the memory region. Type EFI_GCD_MEMORY_TYPE is defined in the + /// AddMemorySpace() function description. + /// + EFI_GCD_MEMORY_TYPE GcdMemoryType; + + /// + /// The image handle of the agent that allocated the memory resource described by + /// PhysicalStart and NumberOfBytes. If this field is NULL, then the memory + /// resource is not currently allocated. Type EFI_HANDLE is defined in + /// InstallProtocolInterface() in the UEFI 2.0 specification. + /// + EFI_HANDLE ImageHandle; + + /// + /// The device handle for which the memory resource has been allocated. If + /// ImageHandle is NULL, then the memory resource is not currently allocated. If this + /// field is NULL, then the memory resource is not associated with a device that is + /// described by a device handle. Type EFI_HANDLE is defined in + /// InstallProtocolInterface() in the UEFI 2.0 specification. + /// + EFI_HANDLE DeviceHandle; +} EFI_GCD_MEMORY_SPACE_DESCRIPTOR; + +/// +/// EFI_GCD_IO_SPACE_DESCRIPTOR. +/// +typedef struct { + /// + /// Physical address of the first byte in the I/O region. Type + /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function + /// description in the UEFI 2.0 specification. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + + /// + /// Number of bytes in the I/O region. + /// + UINT64 Length; + + /// + /// Type of the I/O region. Type EFI_GCD_IO_TYPE is defined in the + /// AddIoSpace() function description. + /// + EFI_GCD_IO_TYPE GcdIoType; + + /// + /// The image handle of the agent that allocated the I/O resource described by + /// PhysicalStart and NumberOfBytes. If this field is NULL, then the I/O + /// resource is not currently allocated. Type EFI_HANDLE is defined in + /// InstallProtocolInterface() in the UEFI 2.0 specification. + /// + EFI_HANDLE ImageHandle; + + /// + /// The device handle for which the I/O resource has been allocated. If ImageHandle + /// is NULL, then the I/O resource is not currently allocated. If this field is NULL, then + /// the I/O resource is not associated with a device that is described by a device handle. + /// Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI + /// 2.0 specification. + /// + EFI_HANDLE DeviceHandle; +} EFI_GCD_IO_SPACE_DESCRIPTOR; + + +/** + Adds reserved memory, system memory, or memory-mapped I/O resources to the + global coherency domain of the processor. + + @param GcdMemoryType The type of memory resource being added. + @param BaseAddress The physical address that is the start address + of the memory resource being added. + @param Length The size, in bytes, of the memory resource that + is being added. + @param Capabilities The bit mask of attributes that the memory + resource region supports. + + @retval EFI_SUCCESS The memory resource was added to the global + coherency domain of the processor. + @retval EFI_INVALID_PARAMETER GcdMemoryType is invalid. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to add + the memory resource to the global coherency + domain of the processor. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes + of the memory resource range specified by + BaseAddress and Length. + @retval EFI_ACCESS_DENIED One or more bytes of the memory resource range + specified by BaseAddress and Length conflicts + with a memory resource range that was previously + added to the global coherency domain of the processor. + @retval EFI_ACCESS_DENIED One or more bytes of the memory resource range + specified by BaseAddress and Length was allocated + in a prior call to AllocateMemorySpace(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ADD_MEMORY_SPACE)( + IN EFI_GCD_MEMORY_TYPE GcdMemoryType, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Capabilities + ); + +/** + Allocates nonexistent memory, reserved memory, system memory, or memorymapped + I/O resources from the global coherency domain of the processor. + + @param GcdAllocateType The type of allocation to perform. + @param GcdMemoryType The type of memory resource being allocated. + @param Alignment The log base 2 of the boundary that BaseAddress must + be aligned on output. Align with 2^Alignment. + @param Length The size in bytes of the memory resource range that + is being allocated. + @param BaseAddress A pointer to a physical address to allocate. + @param Imagehandle The image handle of the agent that is allocating + the memory resource. + @param DeviceHandle The device handle for which the memory resource + is being allocated. + + @retval EFI_INVALID_PARAMETER GcdAllocateType is invalid. + @retval EFI_INVALID_PARAMETER GcdMemoryType is invalid. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_INVALID_PARAMETER BaseAddress is NULL. + @retval EFI_INVALID_PARAMETER ImageHandle is NULL. + @retval EFI_NOT_FOUND The memory resource request could not be satisfied. + No descriptor contains the desired space. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the memory + resource from the global coherency domain of the processor. + @retval EFI_SUCCESS The memory resource was allocated from the global coherency + domain of the processor. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ALLOCATE_MEMORY_SPACE)( + IN EFI_GCD_ALLOCATE_TYPE GcdAllocateType, + IN EFI_GCD_MEMORY_TYPE GcdMemoryType, + IN UINTN Alignment, + IN UINT64 Length, + IN OUT EFI_PHYSICAL_ADDRESS *BaseAddress, + IN EFI_HANDLE ImageHandle, + IN EFI_HANDLE DeviceHandle OPTIONAL + ); + +/** + Frees nonexistent memory, reserved memory, system memory, or memory-mapped + I/O resources from the global coherency domain of the processor. + + @param BaseAddress The physical address that is the start address of the memory resource being freed. + @param Length The size in bytes of the memory resource range that is being freed. + + @retval EFI_SUCCESS The memory resource was freed from the global coherency domain of + the processor. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory + resource range specified by BaseAddress and Length. + @retval EFI_NOT_FOUND The memory resource range specified by BaseAddress and + Length was not allocated with previous calls to AllocateMemorySpace(). + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to free the memory resource + from the global coherency domain of the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FREE_MEMORY_SPACE)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Removes reserved memory, system memory, or memory-mapped I/O resources from + the global coherency domain of the processor. + + @param BaseAddress The physical address that is the start address of the memory resource being removed. + @param Length The size in bytes of the memory resource that is being removed. + + @retval EFI_SUCCESS The memory resource was removed from the global coherency + domain of the processor. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory + resource range specified by BaseAddress and Length. + @retval EFI_NOT_FOUND One or more bytes of the memory resource range specified by + BaseAddress and Length was not added with previous calls to + AddMemorySpace(). + @retval EFI_ACCESS_DEFINED One or more bytes of the memory resource range specified by + BaseAddress and Length has been allocated with AllocateMemorySpace(). + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to remove the memory + resource from the global coherency domain of the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REMOVE_MEMORY_SPACE)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Retrieves the descriptor for a memory region containing a specified address. + + @param BaseAddress The physical address that is the start address of a memory region. + @param Descriptor A pointer to a caller allocated descriptor. + + @retval EFI_SUCCESS The descriptor for the memory resource region containing + BaseAddress was returned in Descriptor. + @retval EFI_INVALID_PARAMETER Descriptor is NULL. + @retval EFI_NOT_FOUND A memory resource range containing BaseAddress was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_MEMORY_SPACE_DESCRIPTOR)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor + ); + +/** + Modifies the attributes for a memory region in the global coherency domain of the + processor. + + @param BaseAddress The physical address that is the start address of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memory region. + + @retval EFI_SUCCESS The attributes were set for the memory region. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory + resource range specified by BaseAddress and Length. + @retval EFI_UNSUPPORTED The bit mask of attributes is not support for the memory resource + range specified by BaseAddress and Length. + @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by + BaseAddress and Length cannot be modified. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of + the memory resource range. + @retval EFI_NOT_AVAILABLE_YET The attributes cannot be set because CPU architectural protocol is + not available yet. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_MEMORY_SPACE_ATTRIBUTES)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +/** + Modifies the capabilities for a memory region in the global coherency domain of the + processor. + + @param BaseAddress The physical address that is the start address of a memory region. + @param Length The size in bytes of the memory region. + @param Capabilities The bit mask of capabilities that the memory region supports. + + @retval EFI_SUCCESS The capabilities were set for the memory region. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The capabilities specified by Capabilities do not include the + memory region attributes currently in use. + @retval EFI_ACCESS_DENIED The capabilities for the memory resource range specified by + BaseAddress and Length cannot be modified. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the capabilities + of the memory resource range. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_MEMORY_SPACE_CAPABILITIES) ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Capabilities + ); + +/** + Returns a map of the memory resources in the global coherency domain of the + processor. + + @param NumberOfDescriptors A pointer to number of descriptors returned in the MemorySpaceMap buffer. + @param MemorySpaceMap A pointer to the array of EFI_GCD_MEMORY_SPACE_DESCRIPTORs. + + @retval EFI_SUCCESS The memory space map was returned in the MemorySpaceMap + buffer, and the number of descriptors in MemorySpaceMap was + returned in NumberOfDescriptors. + @retval EFI_INVALID_PARAMETER NumberOfDescriptors is NULL. + @retval EFI_INVALID_PARAMETER MemorySpaceMap is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate MemorySpaceMap. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_MEMORY_SPACE_MAP)( + OUT UINTN *NumberOfDescriptors, + OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **MemorySpaceMap + ); + +/** + Adds reserved I/O or I/O resources to the global coherency domain of the processor. + + @param GcdIoType The type of I/O resource being added. + @param BaseAddress The physical address that is the start address of the I/O resource being added. + @param Length The size in bytes of the I/O resource that is being added. + + @retval EFI_SUCCESS The I/O resource was added to the global coherency domain of + the processor. + @retval EFI_INVALID_PARAMETER GcdIoType is invalid. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to add the I/O resource to + the global coherency domain of the processor. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O + resource range specified by BaseAddress and Length. + @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by + BaseAddress and Length conflicts with an I/O resource + range that was previously added to the global coherency domain + of the processor. + @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by + BaseAddress and Length was allocated in a prior call to + AllocateIoSpace(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ADD_IO_SPACE)( + IN EFI_GCD_IO_TYPE GcdIoType, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Allocates nonexistent I/O, reserved I/O, or I/O resources from the global coherency + domain of the processor. + + @param GcdAllocateType The type of allocation to perform. + @param GcdIoType The type of I/O resource being allocated. + @param Alignment The log base 2 of the boundary that BaseAddress must be aligned on output. + @param Length The size in bytes of the I/O resource range that is being allocated. + @param BaseAddress A pointer to a physical address. + @param Imagehandle The image handle of the agent that is allocating the I/O resource. + @param DeviceHandle The device handle for which the I/O resource is being allocated. + + @retval EFI_SUCCESS The I/O resource was allocated from the global coherency domain + of the processor. + @retval EFI_INVALID_PARAMETER GcdAllocateType is invalid. + @retval EFI_INVALID_PARAMETER GcdIoType is invalid. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_INVALID_PARAMETER BaseAddress is NULL. + @retval EFI_INVALID_PARAMETER ImageHandle is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to allocate the I/O + resource from the global coherency domain of the processor. + @retval EFI_NOT_FOUND The I/O resource request could not be satisfied. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ALLOCATE_IO_SPACE)( + IN EFI_GCD_ALLOCATE_TYPE GcdAllocateType, + IN EFI_GCD_IO_TYPE GcdIoType, + IN UINTN Alignment, + IN UINT64 Length, + IN OUT EFI_PHYSICAL_ADDRESS *BaseAddress, + IN EFI_HANDLE ImageHandle, + IN EFI_HANDLE DeviceHandle OPTIONAL + ); + +/** + Frees nonexistent I/O, reserved I/O, or I/O resources from the global coherency + domain of the processor. + + @param BaseAddress The physical address that is the start address of the I/O resource being freed. + @param Length The size in bytes of the I/O resource range that is being freed. + + @retval EFI_SUCCESS The I/O resource was freed from the global coherency domain of the + processor. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O resource + range specified by BaseAddress and Length. + @retval EFI_NOT_FOUND The I/O resource range specified by BaseAddress and Length + was not allocated with previous calls to AllocateIoSpace(). + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to free the I/O resource from + the global coherency domain of the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FREE_IO_SPACE)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Removes reserved I/O or I/O resources from the global coherency domain of the + processor. + + @param BaseAddress A pointer to a physical address that is the start address of the I/O resource being + removed. + @param Length The size in bytes of the I/O resource that is being removed. + + @retval EFI_SUCCESS The I/O resource was removed from the global coherency domain + of the processor. + @retval EFI_INVALID_PARAMETER Length is zero. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the I/O + resource range specified by BaseAddress and Length. + @retval EFI_NOT_FOUND One or more bytes of the I/O resource range specified by + BaseAddress and Length was not added with previous + calls to AddIoSpace(). + @retval EFI_ACCESS_DENIED One or more bytes of the I/O resource range specified by + BaseAddress and Length has been allocated with + AllocateIoSpace(). + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to remove the I/O + resource from the global coherency domain of the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REMOVE_IO_SPACE)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length + ); + +/** + Retrieves the descriptor for an I/O region containing a specified address. + + @param BaseAddress The physical address that is the start address of an I/O region. + @param Descriptor A pointer to a caller allocated descriptor. + + @retval EFI_SUCCESS The descriptor for the I/O resource region containing + BaseAddress was returned in Descriptor. + @retval EFI_INVALID_PARAMETER Descriptor is NULL. + @retval EFI_NOT_FOUND An I/O resource range containing BaseAddress was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_IO_SPACE_DESCRIPTOR)( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + OUT EFI_GCD_IO_SPACE_DESCRIPTOR *Descriptor + ); + +/** + Returns a map of the I/O resources in the global coherency domain of the processor. + + @param NumberOfDescriptors A pointer to number of descriptors returned in the IoSpaceMap buffer. + @param MemorySpaceMap A pointer to the array of EFI_GCD_IO_SPACE_DESCRIPTORs. + + @retval EFI_SUCCESS The I/O space map was returned in the IoSpaceMap buffer, and + the number of descriptors in IoSpaceMap was returned in + NumberOfDescriptors. + @retval EFI_INVALID_PARAMETER NumberOfDescriptors is NULL. + @retval EFI_INVALID_PARAMETER IoSpaceMap is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate IoSpaceMap. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_IO_SPACE_MAP)( + OUT UINTN *NumberOfDescriptors, + OUT EFI_GCD_IO_SPACE_DESCRIPTOR **IoSpaceMap + ); + + + +/** + Loads and executed DXE drivers from firmware volumes. + + The Dispatch() function searches for DXE drivers in firmware volumes that have been + installed since the last time the Dispatch() service was called. It then evaluates + the dependency expressions of all the DXE drivers and loads and executes those DXE + drivers whose dependency expression evaluate to TRUE. This service must interact with + the Security Architectural Protocol to authenticate DXE drivers before they are executed. + This process is continued until no more DXE drivers can be executed. + + @retval EFI_SUCCESS One or more DXE driver were dispatched. + @retval EFI_NOT_FOUND No DXE drivers were dispatched. + @retval EFI_ALREADY_STARTED An attempt is being made to start the DXE Dispatcher recursively. + Thus, no action was taken. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISPATCH)( + VOID + ); + +/** + Clears the Schedule on Request (SOR) flag for a component that is stored in a firmware volume. + + @param FirmwareVolumeHandle The handle of the firmware volume that contains the file specified by FileName. + @param FileName A pointer to the name of the file in a firmware volume. + + @retval EFI_SUCCESS The DXE driver was found and its SOR bit was cleared. + @retval EFI_NOT_FOUND The DXE driver does not exist, or the DXE driver exists and its SOR + bit is not set. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCHEDULE)( + IN EFI_HANDLE FirmwareVolumeHandle, + IN CONST EFI_GUID *FileName + ); + +/** + Promotes a file stored in a firmware volume from the untrusted to the trusted state. + + @param FirmwareVolumeHandle The handle of the firmware volume that contains the file specified by FileName. + @param DriverName A pointer to the name of the file in a firmware volume. + + @return Status of promoting FFS from untrusted to trusted + state. + @retval EFI_NOT_FOUND The file was not found in the untrusted state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TRUST)( + IN EFI_HANDLE FirmwareVolumeHandle, + IN CONST EFI_GUID *FileName + ); + +/** + Creates a firmware volume handle for a firmware volume that is present in system memory. + + @param FirmwareVolumeHeader A pointer to the header of the firmware volume. + @param Size The size, in bytes, of the firmware volume. + @param FirmwareVolumeHandle On output, a pointer to the created handle. + + @retval EFI_SUCCESS The EFI_FIRMWARE_VOLUME_PROTOCOL and + EFI_DEVICE_PATH_PROTOCOL were installed onto + FirmwareVolumeHandle for the firmware volume described + by FirmwareVolumeHeader and Size. + @retval EFI_VOLUME_CORRUPTED The firmware volume described by FirmwareVolumeHeader + and Size is corrupted. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources available to produce the + EFI_FIRMWARE_VOLUME_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL + for the firmware volume described by FirmwareVolumeHeader and Size. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PROCESS_FIRMWARE_VOLUME)( + IN CONST VOID *FirmwareVolumeHeader, + IN UINTN Size, + OUT EFI_HANDLE *FirmwareVolumeHandle + ); + +// +// DXE Services Table +// +#define DXE_SERVICES_SIGNATURE 0x565245535f455844ULL +#define DXE_SPECIFICATION_MAJOR_REVISION 1 +#define DXE_SPECIFICATION_MINOR_REVISION 70 +#define DXE_SERVICES_REVISION ((DXE_SPECIFICATION_MAJOR_REVISION<<16) | (DXE_SPECIFICATION_MINOR_REVISION)) + +typedef struct { + /// + /// The table header for the DXE Services Table. + /// This header contains the DXE_SERVICES_SIGNATURE and DXE_SERVICES_REVISION values. + /// + EFI_TABLE_HEADER Hdr; + + // + // Global Coherency Domain Services + // + EFI_ADD_MEMORY_SPACE AddMemorySpace; + EFI_ALLOCATE_MEMORY_SPACE AllocateMemorySpace; + EFI_FREE_MEMORY_SPACE FreeMemorySpace; + EFI_REMOVE_MEMORY_SPACE RemoveMemorySpace; + EFI_GET_MEMORY_SPACE_DESCRIPTOR GetMemorySpaceDescriptor; + EFI_SET_MEMORY_SPACE_ATTRIBUTES SetMemorySpaceAttributes; + EFI_GET_MEMORY_SPACE_MAP GetMemorySpaceMap; + EFI_ADD_IO_SPACE AddIoSpace; + EFI_ALLOCATE_IO_SPACE AllocateIoSpace; + EFI_FREE_IO_SPACE FreeIoSpace; + EFI_REMOVE_IO_SPACE RemoveIoSpace; + EFI_GET_IO_SPACE_DESCRIPTOR GetIoSpaceDescriptor; + EFI_GET_IO_SPACE_MAP GetIoSpaceMap; + + // + // Dispatcher Services + // + EFI_DISPATCH Dispatch; + EFI_SCHEDULE Schedule; + EFI_TRUST Trust; + // + // Service to process a single firmware volume found in a capsule + // + EFI_PROCESS_FIRMWARE_VOLUME ProcessFirmwareVolume; + // + // Extensions to Global Coherency Domain Services + // + EFI_SET_MEMORY_SPACE_CAPABILITIES SetMemorySpaceCapabilities; +} DXE_SERVICES; + +typedef DXE_SERVICES EFI_DXE_SERVICES; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareFile.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareFile.h new file mode 100644 index 0000000000..bfb8fe3695 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareFile.h @@ -0,0 +1,509 @@ +/** @file + The firmware file related definitions in PI. + +Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.6. + +**/ + + +#ifndef __PI_FIRMWARE_FILE_H__ +#define __PI_FIRMWARE_FILE_H__ + +#pragma pack(1) +/// +/// Used to verify the integrity of the file. +/// +typedef union { + struct { + /// + /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file + /// header. The State and IntegrityCheck.Checksum.File fields are assumed + /// to be zero and the checksum is calculated such that the entire header sums to zero. + /// + UINT8 Header; + /// + /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes + /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit + /// checksum of the file data. + /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, + /// the IntegrityCheck.Checksum.File field must be initialized with a value of + /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the + /// EFI_FILE_DATA_VALID bit is set in the State field. + /// + UINT8 File; + } Checksum; + /// + /// This is the full 16 bits of the IntegrityCheck field. + /// + UINT16 Checksum16; +} EFI_FFS_INTEGRITY_CHECK; + +/// +/// FFS_FIXED_CHECKSUM is the checksum value used when the +/// FFS_ATTRIB_CHECKSUM attribute bit is clear. +/// +#define FFS_FIXED_CHECKSUM 0xAA + +typedef UINT8 EFI_FV_FILETYPE; +typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; +typedef UINT8 EFI_FFS_FILE_STATE; + +/// +/// File Types Definitions +/// +#define EFI_FV_FILETYPE_ALL 0x00 +#define EFI_FV_FILETYPE_RAW 0x01 +#define EFI_FV_FILETYPE_FREEFORM 0x02 +#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 +#define EFI_FV_FILETYPE_PEI_CORE 0x04 +#define EFI_FV_FILETYPE_DXE_CORE 0x05 +#define EFI_FV_FILETYPE_PEIM 0x06 +#define EFI_FV_FILETYPE_DRIVER 0x07 +#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 +#define EFI_FV_FILETYPE_APPLICATION 0x09 +#define EFI_FV_FILETYPE_MM 0x0A +#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM +#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B +#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C +#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE +#define EFI_FV_FILETYPE_MM_CORE 0x0D +#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE +#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E +#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F +#define EFI_FV_FILETYPE_OEM_MIN 0xc0 +#define EFI_FV_FILETYPE_OEM_MAX 0xdf +#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 +#define EFI_FV_FILETYPE_DEBUG_MAX 0xef +#define EFI_FV_FILETYPE_FFS_MIN 0xf0 +#define EFI_FV_FILETYPE_FFS_MAX 0xff +#define EFI_FV_FILETYPE_FFS_PAD 0xf0 +/// +/// FFS File Attributes. +/// +#define FFS_ATTRIB_LARGE_FILE 0x01 +#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02 +#define FFS_ATTRIB_FIXED 0x04 +#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 +#define FFS_ATTRIB_CHECKSUM 0x40 + +/// +/// FFS File State Bits. +/// +#define EFI_FILE_HEADER_CONSTRUCTION 0x01 +#define EFI_FILE_HEADER_VALID 0x02 +#define EFI_FILE_DATA_VALID 0x04 +#define EFI_FILE_MARKED_FOR_UPDATE 0x08 +#define EFI_FILE_DELETED 0x10 +#define EFI_FILE_HEADER_INVALID 0x20 + + +/// +/// Each file begins with the header that describe the +/// contents and state of the files. +/// +typedef struct { + /// + /// This GUID is the file name. It is used to uniquely identify the file. + /// + EFI_GUID Name; + /// + /// Used to verify the integrity of the file. + /// + EFI_FFS_INTEGRITY_CHECK IntegrityCheck; + /// + /// Identifies the type of file. + /// + EFI_FV_FILETYPE Type; + /// + /// Declares various file attribute bits. + /// + EFI_FFS_FILE_ATTRIBUTES Attributes; + /// + /// The length of the file in bytes, including the FFS header. + /// + UINT8 Size[3]; + /// + /// Used to track the state of the file throughout the life of the file from creation to deletion. + /// + EFI_FFS_FILE_STATE State; +} EFI_FFS_FILE_HEADER; + +typedef struct { + /// + /// This GUID is the file name. It is used to uniquely identify the file. There may be only + /// one instance of a file with the file name GUID of Name in any given firmware + /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. + /// + EFI_GUID Name; + + /// + /// Used to verify the integrity of the file. + /// + EFI_FFS_INTEGRITY_CHECK IntegrityCheck; + + /// + /// Identifies the type of file. + /// + EFI_FV_FILETYPE Type; + + /// + /// Declares various file attribute bits. + /// + EFI_FFS_FILE_ATTRIBUTES Attributes; + + /// + /// The length of the file in bytes, including the FFS header. + /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a + /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). + /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is + /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. + /// + UINT8 Size[3]; + + /// + /// Used to track the state of the file throughout the life of the file from creation to deletion. + /// + EFI_FFS_FILE_STATE State; + + /// + /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. + /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. + /// + UINT64 ExtendedSize; +} EFI_FFS_FILE_HEADER2; + +#define IS_FFS_FILE2(FfsFileHeaderPtr) \ + (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) + +/// +/// The argument passed as the FfsFileHeaderPtr parameter to the +/// FFS_FILE_SIZE() function-like macro below must not have side effects: +/// FfsFileHeaderPtr is evaluated multiple times. +/// +#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) ( \ + (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[0] ) | \ + (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[1] << 8) | \ + (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[2] << 16))) + +#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ + ((UINT32) (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize)) + +typedef UINT8 EFI_SECTION_TYPE; + +/// +/// Pseudo type. It is used as a wild card when retrieving sections. +/// The section type EFI_SECTION_ALL matches all section types. +/// +#define EFI_SECTION_ALL 0x00 + +/// +/// Encapsulation section Type values. +/// +#define EFI_SECTION_COMPRESSION 0x01 + +#define EFI_SECTION_GUID_DEFINED 0x02 + +#define EFI_SECTION_DISPOSABLE 0x03 + +/// +/// Leaf section Type values. +/// +#define EFI_SECTION_PE32 0x10 +#define EFI_SECTION_PIC 0x11 +#define EFI_SECTION_TE 0x12 +#define EFI_SECTION_DXE_DEPEX 0x13 +#define EFI_SECTION_VERSION 0x14 +#define EFI_SECTION_USER_INTERFACE 0x15 +#define EFI_SECTION_COMPATIBILITY16 0x16 +#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 +#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 +#define EFI_SECTION_RAW 0x19 +#define EFI_SECTION_PEI_DEPEX 0x1B +#define EFI_SECTION_MM_DEPEX 0x1C +#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX + +/// +/// Common section header. +/// +typedef struct { + /// + /// A 24-bit unsigned integer that contains the total size of the section in bytes, + /// including the EFI_COMMON_SECTION_HEADER. + /// + UINT8 Size[3]; + EFI_SECTION_TYPE Type; + /// + /// Declares the section type. + /// +} EFI_COMMON_SECTION_HEADER; + +typedef struct { + /// + /// A 24-bit unsigned integer that contains the total size of the section in bytes, + /// including the EFI_COMMON_SECTION_HEADER. + /// + UINT8 Size[3]; + + EFI_SECTION_TYPE Type; + + /// + /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If + /// Size is not equal to 0xFFFFFF, then this field does not exist. + /// + UINT32 ExtendedSize; +} EFI_COMMON_SECTION_HEADER2; + +/// +/// Leaf section type that contains an +/// IA-32 16-bit executable image. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; + +/// +/// CompressionType of EFI_COMPRESSION_SECTION. +/// +#define EFI_NOT_COMPRESSED 0x00 +#define EFI_STANDARD_COMPRESSION 0x01 +/// +/// An encapsulation section type in which the +/// section data is compressed. +/// +typedef struct { + /// + /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. + /// + EFI_COMMON_SECTION_HEADER CommonHeader; + /// + /// The UINT32 that indicates the size of the section data after decompression. + /// + UINT32 UncompressedLength; + /// + /// Indicates which compression algorithm is used. + /// + UINT8 CompressionType; +} EFI_COMPRESSION_SECTION; + +typedef struct { + /// + /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. + /// + EFI_COMMON_SECTION_HEADER2 CommonHeader; + /// + /// UINT32 that indicates the size of the section data after decompression. + /// + UINT32 UncompressedLength; + /// + /// Indicates which compression algorithm is used. + /// + UINT8 CompressionType; +} EFI_COMPRESSION_SECTION2; + +/// +/// An encapsulation section type in which the section data is disposable. +/// A disposable section is an encapsulation section in which the section data may be disposed of during +/// the process of creating or updating a firmware image without significant impact on the usefulness of +/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This +/// allows optional or descriptive data to be included with the firmware file which can be removed in +/// order to conserve space. The contents of this section are implementation specific, but might contain +/// debug data or detailed integration instructions. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; + +/// +/// The leaf section which could be used to determine the dispatch order of DXEs. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; + +/// +/// The leaf section which contains a PI FV. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; + +/// +/// The leaf section which contains a single GUID. +/// +typedef struct { + /// + /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. + /// + EFI_COMMON_SECTION_HEADER CommonHeader; + /// + /// This GUID is defined by the creator of the file. It is a vendor-defined file type. + /// + EFI_GUID SubTypeGuid; +} EFI_FREEFORM_SUBTYPE_GUID_SECTION; + +typedef struct { + /// + /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. + /// + EFI_COMMON_SECTION_HEADER2 CommonHeader; + /// + /// This GUID is defined by the creator of the file. It is a vendor-defined file type. + /// + EFI_GUID SubTypeGuid; +} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; + +/// +/// Attributes of EFI_GUID_DEFINED_SECTION. +/// +#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 +#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 +/// +/// The leaf section which is encapsulation defined by specific GUID. +/// +typedef struct { + /// + /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. + /// + EFI_COMMON_SECTION_HEADER CommonHeader; + /// + /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. + /// + EFI_GUID SectionDefinitionGuid; + /// + /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. + /// + UINT16 DataOffset; + /// + /// The bit field that declares some specific characteristics of the section contents. + /// + UINT16 Attributes; +} EFI_GUID_DEFINED_SECTION; + +typedef struct { + /// + /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. + /// + EFI_COMMON_SECTION_HEADER2 CommonHeader; + /// + /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. + /// + EFI_GUID SectionDefinitionGuid; + /// + /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. + /// + UINT16 DataOffset; + /// + /// The bit field that declares some specific characteristics of the section contents. + /// + UINT16 Attributes; +} EFI_GUID_DEFINED_SECTION2; + +/// +/// The leaf section which contains PE32+ image. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; + +/// +/// The leaf section used to determine the dispatch order of PEIMs. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; + +/// +/// A leaf section type that contains a position-independent-code (PIC) image. +/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. +/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be +/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all +/// relocation information has been stripped from the image and the image can be moved and will +/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must +/// be used if the section is 16MB or larger. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; + +/// +/// The leaf section which constains the position-independent-code image. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; + +/// +/// The leaf section which contains an array of zero or more bytes. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; + +/// +/// The SMM dependency expression section is a leaf section that contains a dependency expression that +/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the +/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform +/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. +/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol +/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. +/// +typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; +typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; + +/// +/// The leaf section which contains a unicode string that +/// is human readable file name. +/// +typedef struct { + EFI_COMMON_SECTION_HEADER CommonHeader; + + /// + /// Array of unicode string. + /// + CHAR16 FileNameString[1]; +} EFI_USER_INTERFACE_SECTION; + +typedef struct { + EFI_COMMON_SECTION_HEADER2 CommonHeader; + CHAR16 FileNameString[1]; +} EFI_USER_INTERFACE_SECTION2; + +/// +/// The leaf section which contains a numeric build number and +/// an optional unicode string that represents the file revision. +/// +typedef struct { + EFI_COMMON_SECTION_HEADER CommonHeader; + UINT16 BuildNumber; + + /// + /// Array of unicode string. + /// + CHAR16 VersionString[1]; +} EFI_VERSION_SECTION; + +typedef struct { + EFI_COMMON_SECTION_HEADER2 CommonHeader; + /// + /// A UINT16 that represents a particular build. Subsequent builds have monotonically + /// increasing build numbers relative to earlier builds. + /// + UINT16 BuildNumber; + CHAR16 VersionString[1]; +} EFI_VERSION_SECTION2; + +/// +/// The argument passed as the SectionHeaderPtr parameter to the SECTION_SIZE() +/// and IS_SECTION2() function-like macros below must not have side effects: +/// SectionHeaderPtr is evaluated multiple times. +/// +#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) ( \ + (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[0] ) | \ + (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[1] << 8) | \ + (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[2] << 16))) + +#define IS_SECTION2(SectionHeaderPtr) \ + (SECTION_SIZE (SectionHeaderPtr) == 0x00ffffff) + +#define SECTION2_SIZE(SectionHeaderPtr) \ + (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) + +#pragma pack() + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareVolume.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareVolume.h new file mode 100644 index 0000000000..ca13075b77 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiFirmwareVolume.h @@ -0,0 +1,247 @@ +/** @file + The firmware volume related definitions in PI. + + Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.6 + +**/ + +#ifndef __PI_FIRMWAREVOLUME_H__ +#define __PI_FIRMWAREVOLUME_H__ + +/// +/// EFI_FV_FILE_ATTRIBUTES +/// +typedef UINT32 EFI_FV_FILE_ATTRIBUTES; + +// +// Value of EFI_FV_FILE_ATTRIBUTES. +// +#define EFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F +#define EFI_FV_FILE_ATTRIB_FIXED 0x00000100 +#define EFI_FV_FILE_ATTRIB_MEMORY_MAPPED 0x00000200 + +/// +/// type of EFI FVB attribute +/// +typedef UINT32 EFI_FVB_ATTRIBUTES_2; + +// +// Attributes bit definitions +// +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 +#define EFI_FVB2_READ_STATUS 0x00000004 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 +#define EFI_FVB2_WRITE_STATUS 0x00000020 +#define EFI_FVB2_LOCK_CAP 0x00000040 +#define EFI_FVB2_LOCK_STATUS 0x00000080 +#define EFI_FVB2_STICKY_WRITE 0x00000200 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400 +#define EFI_FVB2_ERASE_POLARITY 0x00000800 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 +#define EFI_FVB2_ALIGNMENT 0x001F0000 +#define EFI_FVB2_ALIGNMENT_1 0x00000000 +#define EFI_FVB2_ALIGNMENT_2 0x00010000 +#define EFI_FVB2_ALIGNMENT_4 0x00020000 +#define EFI_FVB2_ALIGNMENT_8 0x00030000 +#define EFI_FVB2_ALIGNMENT_16 0x00040000 +#define EFI_FVB2_ALIGNMENT_32 0x00050000 +#define EFI_FVB2_ALIGNMENT_64 0x00060000 +#define EFI_FVB2_ALIGNMENT_128 0x00070000 +#define EFI_FVB2_ALIGNMENT_256 0x00080000 +#define EFI_FVB2_ALIGNMENT_512 0x00090000 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 +#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000 + +typedef struct { + /// + /// The number of sequential blocks which are of the same size. + /// + UINT32 NumBlocks; + /// + /// The size of the blocks. + /// + UINT32 Length; +} EFI_FV_BLOCK_MAP_ENTRY; + +/// +/// Describes the features and layout of the firmware volume. +/// +typedef struct { + /// + /// The first 16 bytes are reserved to allow for the reset vector of + /// processors whose reset vector is at address 0. + /// + UINT8 ZeroVector[16]; + /// + /// Declares the file system with which the firmware volume is formatted. + /// + EFI_GUID FileSystemGuid; + /// + /// Length in bytes of the complete firmware volume, including the header. + /// + UINT64 FvLength; + /// + /// Set to EFI_FVH_SIGNATURE + /// + UINT32 Signature; + /// + /// Declares capabilities and power-on defaults for the firmware volume. + /// + EFI_FVB_ATTRIBUTES_2 Attributes; + /// + /// Length in bytes of the complete firmware volume header. + /// + UINT16 HeaderLength; + /// + /// A 16-bit checksum of the firmware volume header. A valid header sums to zero. + /// + UINT16 Checksum; + /// + /// Offset, relative to the start of the header, of the extended header + /// (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is no extended header. + /// + UINT16 ExtHeaderOffset; + /// + /// This field must always be set to zero. + /// + UINT8 Reserved[1]; + /// + /// Set to 2. Future versions of this specification may define new header fields and will + /// increment the Revision field accordingly. + /// + UINT8 Revision; + /// + /// An array of run-length encoded FvBlockMapEntry structures. The array is + /// terminated with an entry of {0,0}. + /// + EFI_FV_BLOCK_MAP_ENTRY BlockMap[1]; +} EFI_FIRMWARE_VOLUME_HEADER; + +#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H') + +/// +/// Firmware Volume Header Revision definition +/// +#define EFI_FVH_REVISION 0x02 + +/// +/// Extension header pointed by ExtHeaderOffset of volume header. +/// +typedef struct { + /// + /// Firmware volume name. + /// + EFI_GUID FvName; + /// + /// Size of the rest of the extension header, including this structure. + /// + UINT32 ExtHeaderSize; +} EFI_FIRMWARE_VOLUME_EXT_HEADER; + +/// +/// Entry struture for describing FV extension header +/// +typedef struct { + /// + /// Size of this header extension. + /// + UINT16 ExtEntrySize; + /// + /// Type of the header. + /// + UINT16 ExtEntryType; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY; + +#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 +/// +/// This extension header provides a mapping between a GUID and an OEM file type. +/// +typedef struct { + /// + /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. + /// + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + /// + /// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit + /// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types. + /// + UINT32 TypeMask; + /// + /// An array of GUIDs, each GUID representing an OEM file type. + /// + /// EFI_GUID Types[1]; + /// +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE; + +#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002 + +/// +/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific +/// GUID FormatType type which includes a length and a successive series of data bytes. +/// +typedef struct { + /// + /// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE. + /// + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + /// + /// Vendor-specific GUID. + /// + EFI_GUID FormatType; + /// + /// An arry of bytes of length Length. + /// + /// UINT8 Data[1]; + /// +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE; + +#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03 + +/// +/// The EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find +/// out how many EFI_FVB2_ERASE_POLARITY bytes are at the end of the FV. +/// +typedef struct { + /// + /// Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE. + /// + EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; + /// + /// The number of bytes of the FV that are in uses. The remaining + /// EFI_FIRMWARE_VOLUME_HEADER FvLength minus UsedSize bytes in + /// the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY. + /// + UINT32 UsedSize; +} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiHob.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiHob.h new file mode 100644 index 0000000000..b38b15aee6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiHob.h @@ -0,0 +1,512 @@ +/** @file + HOB related definitions in PI. + +Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.6 + +**/ + +#ifndef __PI_HOB_H__ +#define __PI_HOB_H__ + +// +// HobType of EFI_HOB_GENERIC_HEADER. +// +#define EFI_HOB_TYPE_HANDOFF 0x0001 +#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 +#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 +#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 +#define EFI_HOB_TYPE_FV 0x0005 +#define EFI_HOB_TYPE_CPU 0x0006 +#define EFI_HOB_TYPE_MEMORY_POOL 0x0007 +#define EFI_HOB_TYPE_FV2 0x0009 +#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A +#define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B +#define EFI_HOB_TYPE_FV3 0x000C +#define EFI_HOB_TYPE_UNUSED 0xFFFE +#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF + +/// +/// Describes the format and size of the data inside the HOB. +/// All HOBs must contain this generic HOB header. +/// +typedef struct { + /// + /// Identifies the HOB data structure type. + /// + UINT16 HobType; + /// + /// The length in bytes of the HOB. + /// + UINT16 HobLength; + /// + /// This field must always be set to zero. + /// + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + + +/// +/// Value of version in EFI_HOB_HANDOFF_INFO_TABLE. +/// +#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009 + +/// +/// Contains general state information used by the HOB producer phase. +/// This HOB must be the first one in the HOB list. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// The version number pertaining to the PHIT HOB definition. + /// This value is four bytes in length to provide an 8-byte aligned entry + /// when it is combined with the 4-byte BootMode. + /// + UINT32 Version; + /// + /// The system boot mode as determined during the HOB producer phase. + /// + EFI_BOOT_MODE BootMode; + /// + /// The highest address location of memory that is allocated for use by the HOB producer + /// phase. This address must be 4-KB aligned to meet page restrictions of UEFI. + /// + EFI_PHYSICAL_ADDRESS EfiMemoryTop; + /// + /// The lowest address location of memory that is allocated for use by the HOB producer phase. + /// + EFI_PHYSICAL_ADDRESS EfiMemoryBottom; + /// + /// The highest address location of free memory that is currently available + /// for use by the HOB producer phase. + /// + EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; + /// + /// The lowest address location of free memory that is available for use by the HOB producer phase. + /// + EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; + /// + /// The end of the HOB list. + /// + EFI_PHYSICAL_ADDRESS EfiEndOfHobList; +} EFI_HOB_HANDOFF_INFO_TABLE; + +/// +/// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the +/// various attributes of the logical memory allocation. The type field will be used for +/// subsequent inclusion in the UEFI memory map. +/// +typedef struct { + /// + /// A GUID that defines the memory allocation region's type and purpose, as well as + /// other fields within the memory allocation HOB. This GUID is used to define the + /// additional data within the HOB that may be present for the memory allocation HOB. + /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 + /// specification. + /// + EFI_GUID Name; + + /// + /// The base address of memory allocated by this HOB. Type + /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 + /// specification. + /// + EFI_PHYSICAL_ADDRESS MemoryBaseAddress; + + /// + /// The length in bytes of memory allocated by this HOB. + /// + UINT64 MemoryLength; + + /// + /// Defines the type of memory allocated by this HOB. The memory type definition + /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined + /// in AllocatePages() in the UEFI 2.0 specification. + /// + EFI_MEMORY_TYPE MemoryType; + + /// + /// Padding for Itanium processor family + /// + UINT8 Reserved[4]; +} EFI_HOB_MEMORY_ALLOCATION_HEADER; + +/// +/// Describes all memory ranges used during the HOB producer +/// phase that exist outside the HOB list. This HOB type +/// describes how memory is used, not the physical attributes of memory. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the + /// various attributes of the logical memory allocation. + /// + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; + // + // Additional data pertaining to the "Name" Guid memory + // may go here. + // +} EFI_HOB_MEMORY_ALLOCATION; + + +/// +/// Describes the memory stack that is produced by the HOB producer +/// phase and upon which all post-memory-installed executable +/// content in the HOB producer phase is executing. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the + /// various attributes of the logical memory allocation. + /// + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; +} EFI_HOB_MEMORY_ALLOCATION_STACK; + +/// +/// Defines the location of the boot-strap +/// processor (BSP) BSPStore ("Backing Store Pointer Store"). +/// This HOB is valid for the Itanium processor family only +/// register overflow store. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the + /// various attributes of the logical memory allocation. + /// + EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; +} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE; + +/// +/// Defines the location and entry point of the HOB consumer phase. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the + /// various attributes of the logical memory allocation. + /// + EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader; + /// + /// The GUID specifying the values of the firmware file system name + /// that contains the HOB consumer phase component. + /// + EFI_GUID ModuleName; + /// + /// The address of the memory-mapped firmware volume + /// that contains the HOB consumer phase firmware file. + /// + EFI_PHYSICAL_ADDRESS EntryPoint; +} EFI_HOB_MEMORY_ALLOCATION_MODULE; + +/// +/// The resource type. +/// +typedef UINT32 EFI_RESOURCE_TYPE; + +// +// Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR. +// +#define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 +#define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 +#define EFI_RESOURCE_IO 0x00000002 +#define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 +#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004 +#define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 +#define EFI_RESOURCE_IO_RESERVED 0x00000006 +#define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 + +/// +/// A type of recount attribute type. +/// +typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; + +// +// These types can be ORed together as needed. +// +// The following attributes are used to describe settings +// +#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 +#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 +#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 +#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 +// +// This is typically used as memory cacheability attribute today. +// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED +// as Physical write protected attribute, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED +// means Memory cacheability attribute: The memory supports being programmed with +// a writeprotected cacheable attribute. +// +#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 +#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 +#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000 +// +// The rest of the attributes are used to describe capabilities +// +#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 +#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 +#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 +#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 +#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 +#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 +#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 +#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 +#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 +#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 +#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000 +// +// This is typically used as memory cacheability attribute today. +// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE +// as Memory capability attribute: The memory supports being protected from processor +// writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute: +// The memory supports being programmed with a writeprotected cacheable attribute. +// +#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000 +#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000 +#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000 + +#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000 +#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000 + +// +// Physical memory relative reliability attribute. This +// memory provides higher reliability relative to other +// memory in the system. If all memory has the same +// reliability, then this bit is not used. +// +#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000 + +/// +/// Describes the resource properties of all fixed, +/// nonrelocatable resource ranges found on the processor +/// host bus during the HOB producer phase. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// A GUID representing the owner of the resource. This GUID is used by HOB + /// consumer phase components to correlate device ownership of a resource. + /// + EFI_GUID Owner; + /// + /// The resource type enumeration as defined by EFI_RESOURCE_TYPE. + /// + EFI_RESOURCE_TYPE ResourceType; + /// + /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE. + /// + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + /// + /// The physical start address of the resource region. + /// + EFI_PHYSICAL_ADDRESS PhysicalStart; + /// + /// The number of bytes of the resource region. + /// + UINT64 ResourceLength; +} EFI_HOB_RESOURCE_DESCRIPTOR; + +/// +/// Allows writers of executable content in the HOB producer phase to +/// maintain and manage HOBs with specific GUID. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// A GUID that defines the contents of this HOB. + /// + EFI_GUID Name; + // + // Guid specific data goes here + // +} EFI_HOB_GUID_TYPE; + +/// +/// Details the location of firmware volumes that contain firmware files. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// The physical memory-mapped base address of the firmware volume. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + /// + /// The length in bytes of the firmware volume. + /// + UINT64 Length; +} EFI_HOB_FIRMWARE_VOLUME; + +/// +/// Details the location of a firmware volume that was extracted +/// from a file within another firmware volume. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// The physical memory-mapped base address of the firmware volume. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + /// + /// The length in bytes of the firmware volume. + /// + UINT64 Length; + /// + /// The name of the firmware volume. + /// + EFI_GUID FvName; + /// + /// The name of the firmware file that contained this firmware volume. + /// + EFI_GUID FileName; +} EFI_HOB_FIRMWARE_VOLUME2; + +/// +/// Details the location of a firmware volume that was extracted +/// from a file within another firmware volume. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// The physical memory-mapped base address of the firmware volume. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + /// + /// The length in bytes of the firmware volume. + /// + UINT64 Length; + /// + /// The authentication status. + /// + UINT32 AuthenticationStatus; + /// + /// TRUE if the FV was extracted as a file within another firmware volume. + /// FALSE otherwise. + /// + BOOLEAN ExtractedFv; + /// + /// The name of the firmware volume. + /// Valid only if IsExtractedFv is TRUE. + /// + EFI_GUID FvName; + /// + /// The name of the firmware file that contained this firmware volume. + /// Valid only if IsExtractedFv is TRUE. + /// + EFI_GUID FileName; +} EFI_HOB_FIRMWARE_VOLUME3; + +/// +/// Describes processor information, such as address space and I/O space capabilities. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU. + /// + EFI_HOB_GENERIC_HEADER Header; + /// + /// Identifies the maximum physical memory addressability of the processor. + /// + UINT8 SizeOfMemorySpace; + /// + /// Identifies the maximum physical I/O addressability of the processor. + /// + UINT8 SizeOfIoSpace; + /// + /// This field will always be set to zero. + /// + UINT8 Reserved[6]; +} EFI_HOB_CPU; + + +/// +/// Describes pool memory allocations. +/// +typedef struct { + /// + /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL. + /// + EFI_HOB_GENERIC_HEADER Header; +} EFI_HOB_MEMORY_POOL; + +/// +/// Each UEFI capsule HOB details the location of a UEFI capsule. It includes a base address and length +/// which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated +/// CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware +/// sometime after the UEFI UpdateCapsule service invocation with the +/// CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER. +/// +typedef struct { + /// + /// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE. + /// + EFI_HOB_GENERIC_HEADER Header; + + /// + /// The physical memory-mapped base address of an UEFI capsule. This value is set to + /// point to the base of the contiguous memory of the UEFI capsule. + /// The length of the contiguous memory in bytes. + /// + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 Length; +} EFI_HOB_UEFI_CAPSULE; + +/// +/// Union of all the possible HOB Types. +/// +typedef union { + EFI_HOB_GENERIC_HEADER *Header; + EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable; + EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; + EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore; + EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack; + EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; + EFI_HOB_GUID_TYPE *Guid; + EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume; + EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2; + EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3; + EFI_HOB_CPU *Cpu; + EFI_HOB_MEMORY_POOL *Pool; + EFI_HOB_UEFI_CAPSULE *Capsule; + UINT8 *Raw; +} EFI_PEI_HOB_POINTERS; + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiI2c.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiI2c.h new file mode 100644 index 0000000000..45f0917aee --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiI2c.h @@ -0,0 +1,301 @@ +/** @file + Include file matches things in PI. + +Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.3 + +**/ + +#ifndef __PI_I2C_H__ +#define __PI_I2C_H__ + +/// +/// A 10-bit slave address is or'ed with the following value enabling the +/// I2C protocol stack to address the duplicated address space between 0 +// and 127 in 10-bit mode. +/// +#define I2C_ADDRESSING_10_BIT 0x80000000 + +/// +/// I2C controller capabilities +/// +/// The EFI_I2C_CONTROLLER_CAPABILITIES specifies the capabilities of the +/// I2C host controller. The StructureSizeInBytes enables variations of +/// this structure to be identified if there is need to extend this +/// structure in the future. +/// +typedef struct { + /// + /// Length of this data structure in bytes + /// + UINT32 StructureSizeInBytes; + + /// + /// The maximum number of bytes the I2C host controller is able to + /// receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + /// + /// The maximum number of bytes the I2C host controller is able to send + /// on the I2C bus. + /// + UINT32 MaximumTransmitBytes; + + /// + /// The maximum number of bytes in the I2C bus transaction. + /// + UINT32 MaximumTotalBytes; +} EFI_I2C_CONTROLLER_CAPABILITIES; + +/// +/// I2C device description +/// +/// The EFI_I2C_ENUMERATE_PROTOCOL uses the EFI_I2C_DEVICE to describe +/// the platform specific details associated with an I2C device. This +/// description is passed to the I2C bus driver during enumeration where +/// it is made available to the third party I2C device driver via the +/// EFI_I2C_IO_PROTOCOL. +/// +typedef struct { + /// + /// Unique value assigned by the silicon manufacture or the third + /// party I2C driver writer for the I2C part. This value logically + /// combines both the manufacture name and the I2C part number into + /// a single value specified as a GUID. + /// + CONST EFI_GUID *DeviceGuid; + + /// + /// Unique ID of the I2C part within the system + /// + UINT32 DeviceIndex; + + /// + /// Hardware revision - ACPI _HRV value. See the Advanced + /// Configuration and Power Interface Specification, Revision 5.0 + /// for the field format and the Plug and play support for I2C + /// web-page for restriction on values. + /// + /// http://www.acpi.info/spec.htm + /// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx + /// + UINT32 HardwareRevision; + + /// + /// I2C bus configuration for the I2C device + /// + UINT32 I2cBusConfiguration; + + /// + /// Number of slave addresses for the I2C device. + /// + UINT32 SlaveAddressCount; + + /// + /// Pointer to the array of slave addresses for the I2C device. + /// + CONST UINT32 *SlaveAddressArray; +} EFI_I2C_DEVICE; + +/// +/// Define the I2C flags +/// +/// I2C read operation when set +#define I2C_FLAG_READ 0x00000001 + +/// +/// Define the flags for SMBus operation +/// +/// The following flags are also present in only the first I2C operation +/// and are ignored when present in other operations. These flags +/// describe a particular SMB transaction as shown in the following table. +/// + +/// SMBus operation +#define I2C_FLAG_SMBUS_OPERATION 0x00010000 + +/// SMBus block operation +/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update +/// the LengthInBytes field of the operation in the request packet with +/// the actual number of bytes read or written. These values are only +/// valid when the entire I2C transaction is successful. +/// This flag also changes the LengthInBytes meaning to be: A maximum +/// of LengthInBytes is to be read from the device. The first byte +/// read contains the number of bytes remaining to be read, plus an +/// optional PEC value. +#define I2C_FLAG_SMBUS_BLOCK 0x00020000 + +/// SMBus process call operation +#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000 + +/// SMBus use packet error code (PEC) +/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit +/// to indicate that the PEC value was checked by the hardware and is +/// not appended to the returned read data. +/// +#define I2C_FLAG_SMBUS_PEC 0x00080000 + +//---------------------------------------------------------------------- +/// +/// QuickRead: OperationCount=1, +/// LengthInBytes=0, Flags=I2C_FLAG_READ +/// QuickWrite: OperationCount=1, +/// LengthInBytes=0, Flags=0 +/// +/// +/// ReceiveByte: OperationCount=1, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_READ +/// ReceiveByte+PEC: OperationCount=1, +/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_READ +/// | I2C_FLAG_SMBUS_PEC +/// +/// +/// SendByte: OperationCount=1, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// SendByte+PEC: OperationCount=1, +/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PEC +/// +/// +/// ReadDataByte: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// LengthInBytes=1, Flags=I2C_FLAG_READ +/// ReadDataByte+PEC: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PEC +/// LengthInBytes=2, Flags=I2C_FLAG_READ +/// +/// +/// WriteDataByte: OperationCount=1, +/// LengthInBytes=2, Flags=I2C_FLAG_SMBUS_OPERATION +/// WriteDataByte+PEC: OperationCount=1, +/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PEC +/// +/// +/// ReadDataWord: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// LengthInBytes=2, Flags=I2C_FLAG_READ +/// ReadDataWord+PEC: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PEC +/// LengthInBytes=3, Flags=I2C_FLAG_READ +/// +/// +/// WriteDataWord: OperationCount=1, +/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION +/// WriteDataWord+PEC: OperationCount=1, +/// LengthInBytes=4, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PEC +/// +/// +/// ReadBlock: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_BLOCK +/// LengthInBytes=33, Flags=I2C_FLAG_READ +/// ReadBlock+PEC: OperationCount=2, +/// LengthInBytes=1, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_BLOCK +/// | I2C_FLAG_SMBUS_PEC +/// LengthInBytes=34, Flags=I2C_FLAG_READ +/// +/// +/// WriteBlock: OperationCount=1, +/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_BLOCK +/// WriteBlock+PEC: OperationCount=1, +/// LengthInBytes=N+3, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_BLOCK +/// | I2C_FLAG_SMBUS_PEC +/// +/// +/// ProcessCall: OperationCount=2, +/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PROCESS_CALL +/// LengthInBytes=2, Flags=I2C_FLAG_READ +/// ProcessCall+PEC: OperationCount=2, +/// LengthInBytes=3, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PROCESS_CALL +/// | I2C_FLAG_SMBUS_PEC +/// LengthInBytes=3, Flags=I2C_FLAG_READ +/// +/// +/// BlkProcessCall: OperationCount=2, +/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PROCESS_CALL +/// | I2C_FLAG_SMBUS_BLOCK +/// LengthInBytes=33, Flags=I2C_FLAG_READ +/// BlkProcessCall+PEC: OperationCount=2, +/// LengthInBytes=N+2, Flags=I2C_FLAG_SMBUS_OPERATION +/// | I2C_FLAG_SMBUS_PROCESS_CALL +/// | I2C_FLAG_SMBUS_BLOCK +/// | I2C_FLAG_SMBUS_PEC +/// LengthInBytes=34, Flags=I2C_FLAG_READ +/// +//---------------------------------------------------------------------- + +/// +/// I2C device operation +/// +/// The EFI_I2C_OPERATION describes a subset of an I2C transaction in which +/// the I2C controller is either sending or receiving bytes from the bus. +/// Some transactions will consist of a single operation while others will +/// be two or more. +/// +/// Note: Some I2C controllers do not support read or write ping (address +/// only) operation and will return EFI_UNSUPPORTED status when these +/// operations are requested. +/// +/// Note: I2C controllers which do not support complex transactions requiring +/// multiple repeated start bits return EFI_UNSUPPORTED without processing +/// any of the transaction. +/// +typedef struct { + /// + /// Flags to qualify the I2C operation. + /// + UINT32 Flags; + + /// + /// Number of bytes to send to or receive from the I2C device. A ping + /// (address only byte/bytes) is indicated by setting the LengthInBytes + /// to zero. + /// + UINT32 LengthInBytes; + + /// + /// Pointer to a buffer containing the data to send or to receive from + /// the I2C device. The Buffer must be at least LengthInBytes in size. + /// + UINT8 *Buffer; +} EFI_I2C_OPERATION; + +/// +/// I2C device request +/// +/// The EFI_I2C_REQUEST_PACKET describes a single I2C transaction. The +/// transaction starts with a start bit followed by the first operation +/// in the operation array. Subsequent operations are separated with +/// repeated start bits and the last operation is followed by a stop bit +/// which concludes the transaction. Each operation is described by one +/// of the elements in the Operation array. +/// +typedef struct { + /// + /// Number of elements in the operation array + /// + UINTN OperationCount; + + /// + /// Description of the I2C operation + /// + EFI_I2C_OPERATION Operation [1]; +} EFI_I2C_REQUEST_PACKET; + +#endif // __PI_I2C_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMmCis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMmCis.h new file mode 100644 index 0000000000..a802ad076a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMmCis.h @@ -0,0 +1,345 @@ +/** @file + Common definitions in the Platform Initialization Specification version 1.5 + VOLUME 4 Management Mode Core Interface version. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PI_MMCIS_H_ +#define _PI_MMCIS_H_ + +#include +#include + +typedef struct _EFI_MM_SYSTEM_TABLE EFI_MM_SYSTEM_TABLE; + +/// +/// The Management Mode System Table (MMST) signature +/// +#define MM_MMST_SIGNATURE SIGNATURE_32 ('S', 'M', 'S', 'T') +/// +/// The Management Mode System Table (MMST) revision is 1.6 +/// +#define MM_SPECIFICATION_MAJOR_REVISION 1 +#define MM_SPECIFICATION_MINOR_REVISION 60 +#define EFI_MM_SYSTEM_TABLE_REVISION ((MM_SPECIFICATION_MAJOR_REVISION<<16) | (MM_SPECIFICATION_MINOR_REVISION)) + +/** + Adds, updates, or removes a configuration table entry from the Management Mode System Table. + + The MmInstallConfigurationTable() function is used to maintain the list + of configuration tables that are stored in the Management Mode System + Table. The list is stored as an array of (GUID, Pointer) pairs. The list + must be allocated from pool memory with PoolType set to EfiRuntimeServicesData. + + @param[in] SystemTable A pointer to the MM System Table (MMST). + @param[in] Guid A pointer to the GUID for the entry to add, update, or remove. + @param[in] Table A pointer to the buffer of the table to add. + @param[in] TableSize The size of the table to install. + + @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed. + @retval EFI_INVALID_PARAMETER Guid is not valid. + @retval EFI_NOT_FOUND An attempt was made to delete a non-existent entry. + @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_INSTALL_CONFIGURATION_TABLE)( + IN CONST EFI_MM_SYSTEM_TABLE *SystemTable, + IN CONST EFI_GUID *Guid, + IN VOID *Table, + IN UINTN TableSize + ); + +/** + This service lets the caller to get one distinct application processor (AP) to execute + a caller-provided code stream while in MM. + + @param[in] Procedure A pointer to the code stream to be run on the designated + AP of the system. + @param[in] CpuNumber The zero-based index of the processor number of the AP + on which the code stream is supposed to run. + @param[in,out] ProcArguments Allows the caller to pass a list of parameters to the code + that is run by the AP. + + @retval EFI_SUCCESS The call was successful and the return parameters are valid. + @retval EFI_INVALID_PARAMETER The input arguments are out of range. + @retval EFI_INVALID_PARAMETER The CPU requested is not available on this SMI invocation. + @retval EFI_INVALID_PARAMETER The CPU cannot support an additional service invocation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_STARTUP_THIS_AP)( + IN EFI_AP_PROCEDURE Procedure, + IN UINTN CpuNumber, + IN OUT VOID *ProcArguments OPTIONAL + ); + +/** + Function prototype for protocol install notification. + + @param[in] Protocol Points to the protocol's unique identifier. + @param[in] Interface Points to the interface instance. + @param[in] Handle The handle on which the interface was installed. + + @return Status Code +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_NOTIFY_FN)( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ); + +/** + Register a callback function be called when a particular protocol interface is installed. + + The MmRegisterProtocolNotify() function creates a registration Function that is to be + called whenever a protocol interface is installed for Protocol by + MmInstallProtocolInterface(). + If Function == NULL and Registration is an existing registration, then the callback is unhooked. + + @param[in] Protocol The unique ID of the protocol for which the event is to be registered. + @param[in] Function Points to the notification function. + @param[out] Registration A pointer to a memory location to receive the registration value. + + @retval EFI_SUCCESS Successfully returned the registration record + that has been added or unhooked. + @retval EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL. + @retval EFI_OUT_OF_RESOURCES Not enough memory resource to finish the request. + @retval EFI_NOT_FOUND If the registration is not found when Function == NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_REGISTER_PROTOCOL_NOTIFY)( + IN CONST EFI_GUID *Protocol, + IN EFI_MM_NOTIFY_FN Function, + OUT VOID **Registration + ); + +/** + Manage MMI of a particular type. + + @param[in] HandlerType Points to the handler type or NULL for root MMI handlers. + @param[in] Context Points to an optional context buffer. + @param[in,out] CommBuffer Points to the optional communication buffer. + @param[in,out] CommBufferSize Points to the size of the optional communication buffer. + + @retval EFI_WARN_INTERRUPT_SOURCE_PENDING Interrupt source was processed successfully but not quiesced. + @retval EFI_INTERRUPT_PENDING One or more SMI sources could not be quiesced. + @retval EFI_NOT_FOUND Interrupt source was not handled or quiesced. + @retval EFI_SUCCESS Interrupt source was handled and quiesced. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_INTERRUPT_MANAGE)( + IN CONST EFI_GUID *HandlerType, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL + ); + +/** + Main entry point for an MM handler dispatch or communicate-based callback. + + @param[in] DispatchHandle The unique handle assigned to this handler by MmiHandlerRegister(). + @param[in] Context Points to an optional handler context which was specified when the + handler was registered. + @param[in,out] CommBuffer A pointer to a collection of data in memory that will + be conveyed from a non-MM environment into an MM environment. + @param[in,out] CommBufferSize The size of the CommBuffer. + + @retval EFI_SUCCESS The interrupt was handled and quiesced. No other handlers + should still be called. + @retval EFI_WARN_INTERRUPT_SOURCE_QUIESCED The interrupt has been quiesced but other handlers should + still be called. + @retval EFI_WARN_INTERRUPT_SOURCE_PENDING The interrupt is still pending and other handlers should still + be called. + @retval EFI_INTERRUPT_PENDING The interrupt could not be quiesced. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_HANDLER_ENTRY_POINT)( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL + ); + +/** + Registers a handler to execute within MM. + + @param[in] Handler Handler service function pointer. + @param[in] HandlerType Points to the handler type or NULL for root MMI handlers. + @param[out] DispatchHandle On return, contains a unique handle which can be used to later + unregister the handler function. + + @retval EFI_SUCCESS MMI handler added successfully. + @retval EFI_INVALID_PARAMETER Handler is NULL or DispatchHandle is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_INTERRUPT_REGISTER)( + IN EFI_MM_HANDLER_ENTRY_POINT Handler, + IN CONST EFI_GUID *HandlerType OPTIONAL, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a handler in MM. + + @param[in] DispatchHandle The handle that was specified when the handler was registered. + + @retval EFI_SUCCESS Handler function was successfully unregistered. + @retval EFI_INVALID_PARAMETER DispatchHandle does not refer to a valid handle. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_INTERRUPT_UNREGISTER)( + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Processor information and functionality needed by MM Foundation. +/// +typedef struct _EFI_MM_ENTRY_CONTEXT { + EFI_MM_STARTUP_THIS_AP MmStartupThisAp; + /// + /// A number between zero and the NumberOfCpus field. This field designates which + /// processor is executing the MM Foundation. + /// + UINTN CurrentlyExecutingCpu; + /// + /// The number of possible processors in the platform. This is a 1 based + /// counter. This does not indicate the number of processors that entered MM. + /// + UINTN NumberOfCpus; + /// + /// Points to an array, where each element describes the number of bytes in the + /// corresponding save state specified by CpuSaveState. There are always + /// NumberOfCpus entries in the array. + /// + UINTN *CpuSaveStateSize; + /// + /// Points to an array, where each element is a pointer to a CPU save state. The + /// corresponding element in CpuSaveStateSize specifies the number of bytes in the + /// save state area. There are always NumberOfCpus entries in the array. + /// + VOID **CpuSaveState; +} EFI_MM_ENTRY_CONTEXT; + +/** + This function is the main entry point to the MM Foundation. + + @param[in] MmEntryContext Processor information and functionality needed by MM Foundation. +**/ +typedef +VOID +(EFIAPI *EFI_MM_ENTRY_POINT)( + IN CONST EFI_MM_ENTRY_CONTEXT *MmEntryContext + ); + +/// +/// Management Mode System Table (MMST) +/// +/// The Management Mode System Table (MMST) is a table that contains a collection of common +/// services for managing MMRAM allocation and providing basic I/O services. These services are +/// intended for both preboot and runtime usage. +/// +struct _EFI_MM_SYSTEM_TABLE { + /// + /// The table header for the SMST. + /// + EFI_TABLE_HEADER Hdr; + /// + /// A pointer to a NULL-terminated Unicode string containing the vendor name. + /// It is permissible for this pointer to be NULL. + /// + CHAR16 *MmFirmwareVendor; + /// + /// The particular revision of the firmware. + /// + UINT32 MmFirmwareRevision; + + EFI_MM_INSTALL_CONFIGURATION_TABLE MmInstallConfigurationTable; + + /// + /// I/O Service + /// + EFI_MM_CPU_IO_PROTOCOL MmIo; + + /// + /// Runtime memory services + /// + EFI_ALLOCATE_POOL MmAllocatePool; + EFI_FREE_POOL MmFreePool; + EFI_ALLOCATE_PAGES MmAllocatePages; + EFI_FREE_PAGES MmFreePages; + + /// + /// MP service + /// + EFI_MM_STARTUP_THIS_AP MmStartupThisAp; + + /// + /// CPU information records + /// + + /// + /// A number between zero and and the NumberOfCpus field. This field designates + /// which processor is executing the MM infrastructure. + /// + UINTN CurrentlyExecutingCpu; + /// + /// The number of possible processors in the platform. This is a 1 based counter. + /// + UINTN NumberOfCpus; + /// + /// Points to an array, where each element describes the number of bytes in the + /// corresponding save state specified by CpuSaveState. There are always + /// NumberOfCpus entries in the array. + /// + UINTN *CpuSaveStateSize; + /// + /// Points to an array, where each element is a pointer to a CPU save state. The + /// corresponding element in CpuSaveStateSize specifies the number of bytes in the + /// save state area. There are always NumberOfCpus entries in the array. + /// + VOID **CpuSaveState; + + /// + /// Extensibility table + /// + + /// + /// The number of UEFI Configuration Tables in the buffer MmConfigurationTable. + /// + UINTN NumberOfTableEntries; + /// + /// A pointer to the UEFI Configuration Tables. The number of entries in the table is + /// NumberOfTableEntries. + /// + EFI_CONFIGURATION_TABLE *MmConfigurationTable; + + /// + /// Protocol services + /// + EFI_INSTALL_PROTOCOL_INTERFACE MmInstallProtocolInterface; + EFI_UNINSTALL_PROTOCOL_INTERFACE MmUninstallProtocolInterface; + EFI_HANDLE_PROTOCOL MmHandleProtocol; + EFI_MM_REGISTER_PROTOCOL_NOTIFY MmRegisterProtocolNotify; + EFI_LOCATE_HANDLE MmLocateHandle; + EFI_LOCATE_PROTOCOL MmLocateProtocol; + + /// + /// MMI Management functions + /// + EFI_MM_INTERRUPT_MANAGE MmiManage; + EFI_MM_INTERRUPT_REGISTER MmiHandlerRegister; + EFI_MM_INTERRUPT_UNREGISTER MmiHandlerUnRegister; +}; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMultiPhase.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMultiPhase.h new file mode 100644 index 0000000000..04624d4614 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiMultiPhase.h @@ -0,0 +1,211 @@ +/** @file + Include file matches things in PI for multiple module types. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + These elements are defined in UEFI Platform Initialization Specification 1.2. + +**/ + +#ifndef __PI_MULTIPHASE_H__ +#define __PI_MULTIPHASE_H__ + +#include +#include +#include +#include +#include +#include +#include + +/** + Produces an error code in the range reserved for use by the Platform Initialization + Architecture Specification. + + The supported 32-bit range is 0xA0000000-0xBFFFFFFF + The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF + + @param StatusCode The status code value to convert into a warning code. + StatusCode must be in the range 0x00000000..0x1FFFFFFF. + + @return The value specified by StatusCode in the PI reserved range. + +**/ +#define DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode) + +/// +/// If this value is returned by an EFI image, then the image should be unloaded. +/// +#define EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1) + +/// +/// If this value is returned by an API, it means the capability is not yet +/// installed/available/ready to use. +/// +#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2) + +/// +/// Success and warning codes reserved for use by PI. +/// Supported 32-bit range is 0x20000000-0x3fffffff. +/// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff. +/// +#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a)) + +/// +/// Error codes reserved for use by PI. +/// Supported 32-bit range is 0xa0000000-0xbfffffff. +/// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff. +/// +#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a)) + +/// +/// Return status codes defined in SMM CIS. +/// +#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0) + +#define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0) +#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1) + +/// +/// Bitmask of values for Authentication Status. +/// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL +/// and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI +/// +/// xx00 Image was not signed. +/// xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the +/// signature was tested, and the signature passed authentication test). +/// 0010 Image was signed, the signature was tested, and the signature passed authentication test. +/// 0110 Image was signed and the signature was not tested. +/// 1010 Image was signed, the signature was tested, and the signature failed the authentication test. +/// +///@{ +#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01 +#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02 +#define EFI_AUTH_STATUS_NOT_TESTED 0x04 +#define EFI_AUTH_STATUS_TEST_FAILED 0x08 +#define EFI_AUTH_STATUS_ALL 0x0f +///@} + +/// +/// MMRAM states and capabilities +/// +#define EFI_MMRAM_OPEN 0x00000001 +#define EFI_MMRAM_CLOSED 0x00000002 +#define EFI_MMRAM_LOCKED 0x00000004 +#define EFI_CACHEABLE 0x00000008 +#define EFI_ALLOCATED 0x00000010 +#define EFI_NEEDS_TESTING 0x00000020 +#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040 + +#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN +#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED +#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED + +/// +/// Structure describing a MMRAM region and its accessibility attributes. +/// +typedef struct { + /// + /// Designates the physical address of the MMRAM in memory. This view of memory is + /// the same as seen by I/O-based agents, for example, but it may not be the address seen + /// by the processors. + /// + EFI_PHYSICAL_ADDRESS PhysicalStart; + /// + /// Designates the address of the MMRAM, as seen by software executing on the + /// processors. This address may or may not match PhysicalStart. + /// + EFI_PHYSICAL_ADDRESS CpuStart; + /// + /// Describes the number of bytes in the MMRAM region. + /// + UINT64 PhysicalSize; + /// + /// Describes the accessibility attributes of the MMRAM. These attributes include the + /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical + /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC + /// initialization). + /// + UINT64 RegionState; +} EFI_MMRAM_DESCRIPTOR; + +typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR; + +/// +/// Structure describing a MMRAM region which cannot be used for the MMRAM heap. +/// +typedef struct _EFI_MM_RESERVED_MMRAM_REGION { + /// + /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open. + /// Ignored if MmramReservedSize is 0. + /// + EFI_PHYSICAL_ADDRESS MmramReservedStart; + /// + /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the + /// last MMRAM area. + /// + UINT64 MmramReservedSize; +} EFI_MM_RESERVED_MMRAM_REGION; + +typedef enum { + EFI_PCD_TYPE_8, + EFI_PCD_TYPE_16, + EFI_PCD_TYPE_32, + EFI_PCD_TYPE_64, + EFI_PCD_TYPE_BOOL, + EFI_PCD_TYPE_PTR +} EFI_PCD_TYPE; + +typedef struct { + /// + /// The returned information associated with the requested TokenNumber. If + /// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8. + /// + EFI_PCD_TYPE PcdType; + /// + /// The size of the data in bytes associated with the TokenNumber specified. If + /// TokenNumber is 0, then PcdSize is set 0. + /// + UINTN PcdSize; + /// + /// The null-terminated ASCII string associated with a given token. If the + /// TokenNumber specified was 0, then this field corresponds to the null-terminated + /// ASCII string associated with the token's namespace Guid. If NULL, there is no + /// name associated with this request. + /// + CHAR8 *PcdName; +} EFI_PCD_INFO; + +/** + The function prototype for invoking a function on an Application Processor. + + This definition is used by the UEFI MP Serices Protocol, and the + PI SMM System Table. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +typedef +VOID +(EFIAPI *EFI_AP_PROCEDURE)( + IN OUT VOID *Buffer + ); + +/** + The function prototype for invoking a function on an Application Processor. + + This definition is used by the UEFI MM MP Serices Protocol. + + @param[in] ProcedureArgument The pointer to private data buffer. + + @retval EFI_SUCCESS Excutive the procedure successfully + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_AP_PROCEDURE2)( + IN VOID *ProcedureArgument +); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiPeiCis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiPeiCis.h new file mode 100644 index 0000000000..3f25f58c95 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiPeiCis.h @@ -0,0 +1,1061 @@ +/** @file + PI PEI master include file. This file should match the PI spec. + +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.7. + +**/ + +#ifndef __PI_PEICIS_H__ +#define __PI_PEICIS_H__ + +#include +#include + +/// +/// The handles of EFI FV. +/// +typedef VOID *EFI_PEI_FV_HANDLE; + +/// +/// The handles of EFI FFS. +/// +typedef VOID *EFI_PEI_FILE_HANDLE; + +/// +/// Declare the forward reference data structure for EFI_PEI_SERVICE. +/// +typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES; + +/// +/// Declare the forward reference data structure for EFI_PEI_NOTIFY_DESCRIPTOR. +/// +typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR; + + +#include +#include + + +/** + The PEI Dispatcher will invoke each PEIM one time. During this pass, the PEI + Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header. + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS The PEI completed successfully. + @retval !EFI_SUCCESS There is error in PEIM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEIM_ENTRY_POINT2)( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + Entry point of the notification callback function itself within the PEIM. + + @param PeiServices Indirect reference to the PEI Services Table. + @param NotifyDescriptor Address of the notification descriptor data structure. + @param Ppi Address of the PPI that was installed. + + @return Status of the notification. + The status code returned from this function is ignored. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEIM_NOTIFY_ENTRY_POINT)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +// +// PEI Ppi Services List Descriptors +// +#define EFI_PEI_PPI_DESCRIPTOR_PIC 0x00000001 +#define EFI_PEI_PPI_DESCRIPTOR_PPI 0x00000010 +#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK 0x00000020 +#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH 0x00000040 +#define EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES 0x00000060 +#define EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST 0x80000000 + +/// +/// The data structure through which a PEIM describes available services to the PEI Foundation. +/// +typedef struct { + /// + /// This field is a set of flags describing the characteristics of this imported table entry. + /// All flags are defined as EFI_PEI_PPI_DESCRIPTOR_***, which can also be combined into one. + /// + UINTN Flags; + /// + /// The address of the EFI_GUID that names the interface. + /// + EFI_GUID *Guid; + /// + /// A pointer to the PPI. It contains the information necessary to install a service. + /// + VOID *Ppi; +} EFI_PEI_PPI_DESCRIPTOR; + +/// +/// The data structure in a given PEIM that tells the PEI +/// Foundation where to invoke the notification service. +/// +struct _EFI_PEI_NOTIFY_DESCRIPTOR { + /// + /// Details if the type of notification are callback or dispatch. + /// + UINTN Flags; + /// + /// The address of the EFI_GUID that names the interface. + /// + EFI_GUID *Guid; + /// + /// Address of the notification callback function itself within the PEIM. + /// + EFI_PEIM_NOTIFY_ENTRY_POINT Notify; +}; + +/// +/// This data structure is the means by which callable services are installed and +/// notifications are registered in the PEI phase. +/// +typedef union { + /// + /// The typedef structure of the notification descriptor. + /// + EFI_PEI_NOTIFY_DESCRIPTOR Notify; + /// + /// The typedef structure of the PPI descriptor. + /// + EFI_PEI_PPI_DESCRIPTOR Ppi; +} EFI_PEI_DESCRIPTOR; + +/** + This service is the first one provided by the PEI Foundation. This function + installs an interface in the PEI PPI database by GUID. The purpose of the + service is to publish an interface that other parties can use to call + additional PEIMs. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table + published by the PEI Foundation. + @param PpiList A pointer to the list of interfaces that the caller shall install. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI + descriptors in the list do not have the + EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_INSTALL_PPI)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList + ); + +/** + This function reinstalls an interface in the PEI PPI database by GUID. + The purpose of the service is to publish an interface that other parties + can use to replace a same-named interface in the protocol database + with a different interface. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table + published by the PEI Foundation. + @param OldPpi A pointer to the former PPI in the database. + @param NewPpi A pointer to the new interfaces that the caller shall install. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI descriptors in the + list do not have the EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + @retval EFI_NOT_FOUND The PPI for which the reinstallation was requested has not been installed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_REINSTALL_PPI)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi, + IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi + ); + +/** + This function locates an interface in the PEI PPI database by GUID. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES published by the PEI Foundation. + @param Guid A pointer to the GUID whose corresponding interface needs to be found. + @param Instance The N-th instance of the interface that is required. + @param PpiDescriptor A pointer to instance of the EFI_PEI_PPI_DESCRIPTOR. + @param Ppi A pointer to the instance of the interface. + + @retval EFI_SUCCESS The interface was successfully returned. + @retval EFI_NOT_FOUND The PPI descriptor is not found in the database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_LOCATE_PPI)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_GUID *Guid, + IN UINTN Instance, + IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL, + IN OUT VOID **Ppi + ); + +/** + This function installs a notification service to be called back when a + given interface is installed or reinstalled. The purpose of the service + is to publish an interface that other parties can use to call additional PPIs + that may materialize later. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param NotifyList A pointer to the list of notification interfaces that the caller shall install. + + @retval EFI_SUCCESS The interface was successfully installed. + @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL, or any of the PEI PPI descriptors in the + list do not have the EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the Flags field. + @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_NOTIFY_PPI)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList + ); + +/** + This function returns the present value of the boot mode. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param BootMode A pointer to contain the value of the boot mode. + + @retval EFI_SUCCESS The boot mode returned successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_BOOT_MODE)( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_BOOT_MODE *BootMode + ); + +/** + This function sets the value of the boot mode. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param BootMode The value of the boot mode to set. + + @retval EFI_SUCCESS The boot mode returned successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SET_BOOT_MODE)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_BOOT_MODE BootMode + ); + +/** + This function returns the pointer to the list of Hand-Off Blocks (HOBs) in memory. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation + @param HobList A pointer to the list of HOBs that the PEI Foundation will initialize + + @retval EFI_SUCCESS The list was successfully returned. + @retval EFI_NOT_AVAILABLE_YET The HOB list is not yet published. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_HOB_LIST)( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT VOID **HobList + ); + +/** + This service, published by the PEI Foundation, abstracts the creation of a Hand-Off Block's (HOB's) headers. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param Type The type of HOB to be installed. + @param Length The length of the HOB to be added. + @param Hob The address of a pointer that will contain the HOB header. + + @retval EFI_SUCCESS The HOB was successfully created. + @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_CREATE_HOB)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT16 Type, + IN UINT16 Length, + IN OUT VOID **Hob + ); + +/** + The purpose of the service is to abstract the capability of the PEI + Foundation to discover instances of firmware volumes in the system. + + This service enables PEIMs to discover additional firmware volumes. The PEI Foundation uses this + service to abstract the locations and formats of various firmware volumes. These volumes include + the Boot Firmware Volume and any other volumes exposed by EFI_PEI_FV_PPI. The service + returns a volume handle of type EFI_PEI_FV_HANDLE, which must be unique within the system. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param Instance This instance of the firmware volume to find. + The value 0 is the Boot Firmware Volume (BFV). + @param VolumeHandle On exit, points to the next volumn handle or NULL if it does not exist. + + @retval EFI_SUCCESS The volume was found. + @retval EFI_NOT_FOUND The volume was not found. + @retval EFI_INVALID_PARAMETER VolumeHandle is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_FIND_NEXT_VOLUME2)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN Instance, + OUT EFI_PEI_FV_HANDLE *VolumeHandle + ); + +/** + Searches for the next matching file in the firmware volume. + + This service enables PEIMs to discover firmware files within a specified volume. + To find the first instance of a firmware file, pass a FileHandle value of NULL into the service. + The service returns a file handle of type EFI_PEI_FILE_HANDLE, which must be unique within + the system. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param SearchType A filter to find files only of this type. + @param FvHandle Handle of firmware volume in which to search. + @param FileHandle On entry, points to the current handle from which to begin searching + or NULL to start at the beginning of the firmware volume. + On exit, points the file handle of the next file in the volume or NULL + if there are no more files. + + @retval EFI_SUCCESS The file was found. + @retval EFI_NOT_FOUND The file was not found. + @retval EFI_NOT_FOUND The header checksum was not zero. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_FIND_NEXT_FILE2)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_FV_FILETYPE SearchType, + IN CONST EFI_PEI_FV_HANDLE FvHandle, + IN OUT EFI_PEI_FILE_HANDLE *FileHandle + ); + +/** + Searches for the next matching section within the specified file. + + This service enables PEI modules to discover the first section of a given type within a valid file. + This service will search within encapsulation sections (compression and GUIDed) as well. It will + search inside of a GUIDed section or a compressed section, but may not, for example, search a + GUIDed section inside a GUIDes section. + This service will not search within compression sections or GUIDed sections that require + extraction if memory is not present. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param SectionType The value of the section type to find. + @param FileHandle Handle of the firmware file to search. + @param SectionData A pointer to the discovered section, if successful. + + @retval EFI_SUCCESS The section was found. + @retval EFI_NOT_FOUND The section was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA2)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_SECTION_TYPE SectionType, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData + ); + +/** + Searches for the next matching section within the specified file. + + This service enables PEI modules to discover the section of a given type within a valid file. + This service will search within encapsulation sections (compression and GUIDed) as well. It will + search inside of a GUIDed section or a compressed section, but may not, for example, search a + GUIDed section inside a GUIDes section. + This service will not search within compression sections or GUIDed sections that require + extraction if memory is not present. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param SectionType The value of the section type to find. + @param SectionInstance Section instance to find. + @param FileHandle Handle of the firmware file to search. + @param SectionData A pointer to the discovered section, if successful. + @param AuthenticationStatus A pointer to the authentication status for this section. + + @retval EFI_SUCCESS The section was found. + @retval EFI_NOT_FOUND The section was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_FIND_SECTION_DATA3)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData, + OUT UINT32 *AuthenticationStatus + ); + +/** + This function registers the found memory configuration with the PEI Foundation. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param MemoryBegin The value of a region of installed memory. + @param MemoryLength The corresponding length of a region of installed memory. + + @retval EFI_SUCCESS The region was successfully installed in a HOB. + @retval EFI_INVALID_PARAMETER MemoryBegin and MemoryLength are illegal for this system. + @retval EFI_OUT_OF_RESOURCES There is no additional space for HOB creation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_INSTALL_PEI_MEMORY)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS MemoryBegin, + IN UINT64 MemoryLength + ); + +/** + The purpose of the service is to publish an interface that allows + PEIMs to allocate memory ranges that are managed by the PEI Foundation. + + Prior to InstallPeiMemory() being called, PEI will allocate pages from the heap. + After InstallPeiMemory() is called, PEI will allocate pages within the region + of memory provided by InstallPeiMemory() service in a best-effort fashion. + Location-specific allocations are not managed by the PEI foundation code. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param MemoryType The type of memory to allocate. + @param Pages The number of contiguous 4 KB pages to allocate. + @param Memory A pointer to a physical address. On output, the address is set to the base + of the page range that was allocated. + + @retval EFI_SUCCESS The memory range was successfully allocated. + @retval EFI_OUT_OF_RESOURCES The pages could not be allocated. + @retval EFI_INVALID_PARAMETER The type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode, + EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData, + EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_ALLOCATE_PAGES)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT EFI_PHYSICAL_ADDRESS *Memory + ); + +/** + Frees memory pages. + + @param[in] PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param[in] Memory The base physical address of the pages to be freed. + @param[in] Pages The number of contiguous 4 KB pages to free. + + @retval EFI_SUCCESS The requested pages were freed. + @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid. + @retval EFI_NOT_FOUND The requested memory pages were not allocated with + AllocatePages(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FREE_PAGES) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS Memory, + IN UINTN Pages + ); + +/** + The purpose of this service is to publish an interface that + allows PEIMs to allocate memory ranges that are managed by the PEI Foundation. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param Size The number of bytes to allocate from the pool. + @param Buffer If the call succeeds, a pointer to a pointer to the allocated buffer; undefined otherwise. + + @retval EFI_SUCCESS The allocation was successful. + @retval EFI_OUT_OF_RESOURCES There is not enough heap to allocate the requested size. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_ALLOCATE_POOL)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN Size, + OUT VOID **Buffer + ); + +/** + This service copies the contents of one buffer to another buffer. + + @param Destination The pointer to the destination buffer of the memory copy. + @param Source The pointer to the source buffer of the memory copy. + @param Length The number of bytes to copy from Source to Destination. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_COPY_MEM)( + IN VOID *Destination, + IN VOID *Source, + IN UINTN Length + ); + +/** + The service fills a buffer with a specified value. + + @param Buffer The pointer to the buffer to fill. + @param Size The number of bytes in Buffer to fill. + @param Value The value to fill Buffer with. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_SET_MEM)( + IN VOID *Buffer, + IN UINTN Size, + IN UINT8 Value + ); + +/** + This service publishes an interface that allows PEIMs to report status codes. + + ReportStatusCode() is called by PEIMs that wish to report status information on their + progress. The principal use model is for a PEIM to emit one of the standard 32-bit error codes. This + will allow a platform owner to ascertain the state of the system, especially under conditions where + the full consoles might not have been installed. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation. + @param Type Indicates the type of status code being reported. + @param Value Describes the current status of a hardware or + software entity. This includes information about the class and + subclass that is used to classify the entity as well as an operation. + For progress codes, the operation is the current activity. + For error codes, it is the exception.For debug codes,it is not defined at this time. + @param Instance The enumeration of a hardware or software entity within + the system. A system may contain multiple entities that match a class/subclass + pairing. The instance differentiates between them. An instance of 0 indicates + that instance information is unavailable, not meaningful, or not relevant. + Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify the caller. + This parameter allows the status code driver to apply different rules to + different callers. + @param Data This optional parameter may be used to pass additional data. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_AVAILABLE_YET No progress code provider has installed an interface in the system. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_REPORT_STATUS_CODE)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId OPTIONAL, + IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL + ); + +/** + Resets the entire platform. + + This service resets the entire platform, including all processors + and devices, and reboots the system. + This service will never return EFI_SUCCESS. + + @param PeiServices An indirect pointer to the EFI_PEI_SERVICES + table published by the PEI Foundation. + + @retval EFI_NOT_AVAILABLE_YET The service has not been installed yet. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_RESET_SYSTEM)( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/** + Resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown + the data buffer starts with a Null-terminated string, optionally + followed by additional binary data. The string is a description + that the caller may use to further indicate the reason for the + system reset. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_RESET2_SYSTEM) ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Find a file within a volume by its name. + + This service searches for files with a specific name, within + either the specified firmware volume or all firmware volumes. + The service returns a file handle of type EFI_PEI_FILE_HANDLE, + which must be unique within the system. + + @param FileName A pointer to the name of the file to + find within the firmware volume. + @param VolumeHandle The firmware volume to search. + @param FileHandle Upon exit, points to the found file's + handle or NULL if it could not be found. + + @retval EFI_SUCCESS The file was found. + @retval EFI_NOT_FOUND The file was not found. + @retval EFI_INVALID_PARAMETER VolumeHandle or FileHandle or + FileName was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_FIND_BY_NAME)( + IN CONST EFI_GUID *FileName, + IN EFI_PEI_FV_HANDLE VolumeHandle, + OUT EFI_PEI_FILE_HANDLE *FileHandle + ); + +/// +/// The information of the FV file. +/// +typedef struct { + /// + /// Name of the file. + /// + EFI_GUID FileName; + /// + /// File type. + /// + EFI_FV_FILETYPE FileType; + /// + /// Attributes of the file. + /// + EFI_FV_FILE_ATTRIBUTES FileAttributes; + /// + /// Points to the file's data (not the header). + /// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED + /// is zero. + /// + VOID *Buffer; + /// + /// Size of the file's data. + /// + UINT32 BufferSize; +} EFI_FV_FILE_INFO; + +/// +/// The information with authentication status of the FV file. +/// +typedef struct { + /// + /// Name of the file. + /// + EFI_GUID FileName; + /// + /// File type. + /// + EFI_FV_FILETYPE FileType; + /// + /// Attributes of the file. + /// + EFI_FV_FILE_ATTRIBUTES FileAttributes; + /// + /// Points to the file's data (not the header). + /// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED + /// is zero. + /// + VOID *Buffer; + /// + /// Size of the file's data. + /// + UINT32 BufferSize; + /// + /// Authentication status for this file. + /// + UINT32 AuthenticationStatus; +} EFI_FV_FILE_INFO2; + +/** + Returns information about a specific file. + + This function returns information about a specific file, + including its file name, type, attributes, starting address and + size. If the firmware volume is not memory mapped, then the + Buffer member will be NULL. + + @param FileHandle The handle of the file. + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information was returned. + @retval EFI_INVALID_PARAMETER FileHandle does not + represent a valid file. + @retval EFI_INVALID_PARAMETER FileInfo is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_GET_FILE_INFO)( + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO *FileInfo + ); + +/** + Returns information about a specific file. + + This function returns information about a specific file, + including its file name, type, attributes, starting address, size and authentication status. + If the firmware volume is not memory mapped, then the Buffer member will be NULL. + + @param FileHandle The handle of the file. + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information was returned. + @retval EFI_INVALID_PARAMETER FileHandle does not + represent a valid file. + @retval EFI_INVALID_PARAMETER FileInfo is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_GET_FILE_INFO2)( + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO2 *FileInfo + ); + +/// +/// The information of the FV volume. +/// +typedef struct { + /// + /// Attributes of the firmware volume. + /// + EFI_FVB_ATTRIBUTES_2 FvAttributes; + /// + /// Format of the firmware volume. + /// + EFI_GUID FvFormat; + /// + /// Name of the firmware volume. + /// + EFI_GUID FvName; + /// + /// Points to the first byte of the firmware + /// volume, if bit EFI_FVB_MEMORY_MAPPED is + /// set in FvAttributes. + /// + VOID *FvStart; + /// + /// Size of the firmware volume. + /// + UINT64 FvSize; +} EFI_FV_INFO; + +/** + Returns information about the specified volume. + + This function returns information about a specific firmware + volume, including its name, type, attributes, starting address + and size. + + @param VolumeHandle Handle of the volume. + @param VolumeInfo Upon exit, points to the volume's information. + + @retval EFI_SUCCESS The volume information returned. + @retval EFI_INVALID_PARAMETER If VolumeHandle does not represent a valid volume. + @retval EFI_INVALID_PARAMETER If VolumeHandle is NULL. + @retval EFI_SUCCESS Information was successfully returned. + @retval EFI_INVALID_PARAMETER The volume designated by the VolumeHandle is not available. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FFS_GET_VOLUME_INFO)( + IN EFI_PEI_FV_HANDLE VolumeHandle, + OUT EFI_FV_INFO *VolumeInfo + ); + +/** + Register a PEIM so that it will be shadowed and called again. + + This service registers a file handle so that after memory is + available, the PEIM will be re-loaded into permanent memory and + re-initialized. The PEIM registered this way will always be + initialized twice. The first time, this function call will + return EFI_SUCCESS. The second time, this function call will + return EFI_ALREADY_STARTED. Depending on the order in which + PEIMs are dispatched, the PEIM making this call may be + initialized after permanent memory is installed, even the first + time. + + @param FileHandle PEIM's file handle. Must be the currently + executing PEIM. + + @retval EFI_SUCCESS The PEIM was successfully registered for + shadowing. + @retval EFI_ALREADY_STARTED The PEIM was previously + registered for shadowing. + @retval EFI_NOT_FOUND The FileHandle does not refer to a + valid file handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_REGISTER_FOR_SHADOW)( + IN EFI_PEI_FILE_HANDLE FileHandle + ); + + +// +// PEI Specification Revision information +// +#define PEI_SPECIFICATION_MAJOR_REVISION 1 +#define PEI_SPECIFICATION_MINOR_REVISION 70 +/// +/// Specification inconsistency here: +/// In the PI1.0 spec, PEI_SERVICES_SIGNATURE is defined as 0x5652455320494550. But +/// to pass a multiple tool chain, it appends an ULL. +/// +// +// PEI Services Table +// +#define PEI_SERVICES_SIGNATURE 0x5652455320494550ULL +/// +/// Specification inconsistency here: +/// In the PI1.0 specification, there is a typo error in PEI_SERVICES_REVISION. In the specification the defintion is +/// #define ((PEI_SPECIFICATION_MAJOR_REVISION<<16) |(PEI_SPECIFICATION_MINOR_REVISION)) +/// and it should be as follows: +/// +#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION)) + +/// +/// EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI +/// Foundation. These services fall into various classes, including the following: +/// - Managing the boot mode +/// - Allocating both early and permanent memory +/// - Supporting the Firmware File System (FFS) +/// - Abstracting the PPI database abstraction +/// - Creating Hand-Off Blocks (HOBs). +/// +struct _EFI_PEI_SERVICES { + /// + /// The table header for the PEI Services Table. + /// + EFI_TABLE_HEADER Hdr; + + // + // PPI Functions + // + EFI_PEI_INSTALL_PPI InstallPpi; + EFI_PEI_REINSTALL_PPI ReInstallPpi; + EFI_PEI_LOCATE_PPI LocatePpi; + EFI_PEI_NOTIFY_PPI NotifyPpi; + + // + // Boot Mode Functions + // + EFI_PEI_GET_BOOT_MODE GetBootMode; + EFI_PEI_SET_BOOT_MODE SetBootMode; + + // + // HOB Functions + // + EFI_PEI_GET_HOB_LIST GetHobList; + EFI_PEI_CREATE_HOB CreateHob; + + // + // Firmware Volume Functions + // + EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume; + EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile; + EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData; + + // + // PEI Memory Functions + // + EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory; + EFI_PEI_ALLOCATE_PAGES AllocatePages; + EFI_PEI_ALLOCATE_POOL AllocatePool; + EFI_PEI_COPY_MEM CopyMem; + EFI_PEI_SET_MEM SetMem; + + // + // Status Code + // + EFI_PEI_REPORT_STATUS_CODE ReportStatusCode; + + // + // Reset + // + EFI_PEI_RESET_SYSTEM ResetSystem; + + // + // (the following interfaces are installed by publishing PEIM) + // I/O Abstractions + // + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + + // + // Future Installed Services + // + EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName; + EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo; + EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo; + EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow; + EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3; + EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2; + EFI_PEI_RESET2_SYSTEM ResetSystem2; + EFI_PEI_FREE_PAGES FreePages; +}; + + +/// +/// EFI_SEC_PEI_HAND_OFF structure holds information about +/// PEI core's operating environment, such as the size of location of +/// temporary RAM, the stack location and BFV location. +/// +typedef struct _EFI_SEC_PEI_HAND_OFF { + /// + /// Size of the data structure. + /// + UINT16 DataSize; + + /// + /// Points to the first byte of the boot firmware volume, + /// which the PEI Dispatcher should search for + /// PEI modules. + /// + VOID *BootFirmwareVolumeBase; + + /// + /// Size of the boot firmware volume, in bytes. + /// + UINTN BootFirmwareVolumeSize; + + /// + /// Points to the first byte of the temporary RAM. + /// + VOID *TemporaryRamBase; + + /// + /// Size of the temporary RAM, in bytes. + /// + UINTN TemporaryRamSize; + + /// + /// Points to the first byte of the temporary RAM + /// available for use by the PEI Foundation. The area + /// described by PeiTemporaryRamBase and PeiTemporaryRamSize + /// must not extend outside beyond the area described by + /// TemporaryRamBase & TemporaryRamSize. This area should not + /// overlap with the area reported by StackBase and + /// StackSize. + /// + VOID *PeiTemporaryRamBase; + + /// + /// The size of the available temporary RAM available for + /// use by the PEI Foundation, in bytes. + /// + UINTN PeiTemporaryRamSize; + + /// + /// Points to the first byte of the stack. + /// This are may be part of the memory described by + /// TemporaryRamBase and TemporaryRamSize + /// or may be an entirely separate area. + /// + VOID *StackBase; + + /// + /// Size of the stack, in bytes. + /// + UINTN StackSize; +} EFI_SEC_PEI_HAND_OFF; + + +/** + The entry point of PEI Foundation. + + This function is the entry point for the PEI Foundation, which + allows the SEC phase to pass information about the stack, + temporary RAM and the Boot Firmware Volume. In addition, it also + allows the SEC phase to pass services and data forward for use + during the PEI phase in the form of one or more PPIs. These PPI's + will be installed and/or immediately signaled if they are + notification type. There is no limit to the number of additional + PPIs that can be passed from SEC into the PEI Foundation. As part + of its initialization phase, the PEI Foundation will add these + SEC-hosted PPIs to its PPI database such that both the PEI + Foundation and any modules can leverage the associated service + calls and/or code in these early PPIs. + + @param SecCoreData Points to a data structure containing + information about the PEI core's + operating environment, such as the size + and location of temporary RAM, the stack + location and the BFV location. + + @param PpiList Points to a list of one or more PPI + descriptors to be installed initially by + the PEI core. An empty PPI list consists + of a single descriptor with the end-tag + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. + As part of its initialization phase, the + PEI Foundation will add these SEC-hosted + PPIs to its PPI database such that both + the PEI Foundation and any modules can + leverage the associated service calls + and/or code in these early PPIs. + + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CORE_ENTRY_POINT)( + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList +); + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiS3BootScript.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiS3BootScript.h new file mode 100644 index 0000000000..b1c4de2859 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiS3BootScript.h @@ -0,0 +1,53 @@ +/** @file + This file contains the boot script defintions that are shared between the + Boot Script Executor PPI and the Boot Script Save Protocol. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PI_S3_BOOT_SCRIPT_H_ +#define _PI_S3_BOOT_SCRIPT_H_ + +//******************************************* +// EFI Boot Script Opcode definitions +//******************************************* +#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00 +#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01 +#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02 +#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03 +#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04 +#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05 +#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06 +#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07 +#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08 +#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09 +#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A +#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B +#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C +#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D +#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E +#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F +#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10 + +//******************************************* +// EFI_BOOT_SCRIPT_WIDTH +//******************************************* +typedef enum { + EfiBootScriptWidthUint8, + EfiBootScriptWidthUint16, + EfiBootScriptWidthUint32, + EfiBootScriptWidthUint64, + EfiBootScriptWidthFifoUint8, + EfiBootScriptWidthFifoUint16, + EfiBootScriptWidthFifoUint32, + EfiBootScriptWidthFifoUint64, + EfiBootScriptWidthFillUint8, + EfiBootScriptWidthFillUint16, + EfiBootScriptWidthFillUint32, + EfiBootScriptWidthFillUint64, + EfiBootScriptWidthMaximum +} EFI_BOOT_SCRIPT_WIDTH; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiSmmCis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiSmmCis.h new file mode 100644 index 0000000000..f081dc2aaf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiSmmCis.h @@ -0,0 +1,200 @@ +/** @file + Common definitions in the Platform Initialization Specification version 1.4a + VOLUME 4 System Management Mode Core Interface version. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PI_SMMCIS_H_ +#define _PI_SMMCIS_H_ + +#include +#include + +typedef struct _EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2; +// +// Define new MM related definition introduced by PI 1.5. +// +#define SMM_SMST_SIGNATURE MM_MMST_SIGNATURE +#define SMM_SPECIFICATION_MAJOR_REVISION MM_SPECIFICATION_MAJOR_REVISION +#define SMM_SPECIFICATION_MINOR_REVISION MM_SPECIFICATION_MINOR_REVISION +#define EFI_SMM_SYSTEM_TABLE2_REVISION EFI_MM_SYSTEM_TABLE_REVISION + +/** + Adds, updates, or removes a configuration table entry from the System Management System Table. + + The SmmInstallConfigurationTable() function is used to maintain the list + of configuration tables that are stored in the System Management System + Table. The list is stored as an array of (GUID, Pointer) pairs. The list + must be allocated from pool memory with PoolType set to EfiRuntimeServicesData. + + @param[in] SystemTable A pointer to the SMM System Table (SMST). + @param[in] Guid A pointer to the GUID for the entry to add, update, or remove. + @param[in] Table A pointer to the buffer of the table to add. + @param[in] TableSize The size of the table to install. + + @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed. + @retval EFI_INVALID_PARAMETER Guid is not valid. + @retval EFI_NOT_FOUND An attempt was made to delete a non-existent entry. + @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_INSTALL_CONFIGURATION_TABLE2)( + IN CONST EFI_SMM_SYSTEM_TABLE2 *SystemTable, + IN CONST EFI_GUID *Guid, + IN VOID *Table, + IN UINTN TableSize + ); + +typedef EFI_MM_STARTUP_THIS_AP EFI_SMM_STARTUP_THIS_AP; +typedef EFI_MM_NOTIFY_FN EFI_SMM_NOTIFY_FN; +typedef EFI_MM_REGISTER_PROTOCOL_NOTIFY EFI_SMM_REGISTER_PROTOCOL_NOTIFY; +typedef EFI_MM_INTERRUPT_MANAGE EFI_SMM_INTERRUPT_MANAGE; +typedef EFI_MM_HANDLER_ENTRY_POINT EFI_SMM_HANDLER_ENTRY_POINT2; +typedef EFI_MM_INTERRUPT_REGISTER EFI_SMM_INTERRUPT_REGISTER; +typedef EFI_MM_INTERRUPT_UNREGISTER EFI_SMM_INTERRUPT_UNREGISTER; + +/// +/// Processor information and functionality needed by SMM Foundation. +/// +typedef struct _EFI_SMM_ENTRY_CONTEXT { + EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp; + /// + /// A number between zero and the NumberOfCpus field. This field designates which + /// processor is executing the SMM Foundation. + /// + UINTN CurrentlyExecutingCpu; + /// + /// The number of possible processors in the platform. This is a 1 based + /// counter. This does not indicate the number of processors that entered SMM. + /// + UINTN NumberOfCpus; + /// + /// Points to an array, where each element describes the number of bytes in the + /// corresponding save state specified by CpuSaveState. There are always + /// NumberOfCpus entries in the array. + /// + UINTN *CpuSaveStateSize; + /// + /// Points to an array, where each element is a pointer to a CPU save state. The + /// corresponding element in CpuSaveStateSize specifies the number of bytes in the + /// save state area. There are always NumberOfCpus entries in the array. + /// + VOID **CpuSaveState; +} EFI_SMM_ENTRY_CONTEXT; + +/** + This function is the main entry point to the SMM Foundation. + + @param[in] SmmEntryContext Processor information and functionality needed by SMM Foundation. +**/ +typedef +VOID +(EFIAPI *EFI_SMM_ENTRY_POINT)( + IN CONST EFI_SMM_ENTRY_CONTEXT *SmmEntryContext + ); + +/// +/// System Management System Table (SMST) +/// +/// The System Management System Table (SMST) is a table that contains a collection of common +/// services for managing SMRAM allocation and providing basic I/O services. These services are +/// intended for both preboot and runtime usage. +/// +struct _EFI_SMM_SYSTEM_TABLE2 { + /// + /// The table header for the SMST. + /// + EFI_TABLE_HEADER Hdr; + /// + /// A pointer to a NULL-terminated Unicode string containing the vendor name. + /// It is permissible for this pointer to be NULL. + /// + CHAR16 *SmmFirmwareVendor; + /// + /// The particular revision of the firmware. + /// + UINT32 SmmFirmwareRevision; + + EFI_SMM_INSTALL_CONFIGURATION_TABLE2 SmmInstallConfigurationTable; + + /// + /// I/O Service + /// + EFI_SMM_CPU_IO2_PROTOCOL SmmIo; + + /// + /// Runtime memory services + /// + EFI_ALLOCATE_POOL SmmAllocatePool; + EFI_FREE_POOL SmmFreePool; + EFI_ALLOCATE_PAGES SmmAllocatePages; + EFI_FREE_PAGES SmmFreePages; + + /// + /// MP service + /// + EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp; + + /// + /// CPU information records + /// + + /// + /// A number between zero and and the NumberOfCpus field. This field designates + /// which processor is executing the SMM infrastructure. + /// + UINTN CurrentlyExecutingCpu; + /// + /// The number of possible processors in the platform. This is a 1 based counter. + /// + UINTN NumberOfCpus; + /// + /// Points to an array, where each element describes the number of bytes in the + /// corresponding save state specified by CpuSaveState. There are always + /// NumberOfCpus entries in the array. + /// + UINTN *CpuSaveStateSize; + /// + /// Points to an array, where each element is a pointer to a CPU save state. The + /// corresponding element in CpuSaveStateSize specifies the number of bytes in the + /// save state area. There are always NumberOfCpus entries in the array. + /// + VOID **CpuSaveState; + + /// + /// Extensibility table + /// + + /// + /// The number of UEFI Configuration Tables in the buffer SmmConfigurationTable. + /// + UINTN NumberOfTableEntries; + /// + /// A pointer to the UEFI Configuration Tables. The number of entries in the table is + /// NumberOfTableEntries. + /// + EFI_CONFIGURATION_TABLE *SmmConfigurationTable; + + /// + /// Protocol services + /// + EFI_INSTALL_PROTOCOL_INTERFACE SmmInstallProtocolInterface; + EFI_UNINSTALL_PROTOCOL_INTERFACE SmmUninstallProtocolInterface; + EFI_HANDLE_PROTOCOL SmmHandleProtocol; + EFI_SMM_REGISTER_PROTOCOL_NOTIFY SmmRegisterProtocolNotify; + EFI_LOCATE_HANDLE SmmLocateHandle; + EFI_LOCATE_PROTOCOL SmmLocateProtocol; + + /// + /// SMI Management functions + /// + EFI_SMM_INTERRUPT_MANAGE SmiManage; + EFI_SMM_INTERRUPT_REGISTER SmiHandlerRegister; + EFI_SMM_INTERRUPT_UNREGISTER SmiHandlerUnRegister; +}; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiStatusCode.h new file mode 100644 index 0000000000..e484f2027f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Pi/PiStatusCode.h @@ -0,0 +1,1207 @@ +/** @file + StatusCode related definitions in PI. + +Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + These status codes are defined in UEFI Platform Initialization Specification 1.2, + Volume 3: Shared Architectural Elements. + +**/ + +#ifndef __PI_STATUS_CODE_H__ +#define __PI_STATUS_CODE_H__ + +// +// Required for IA32, X64, IPF, ARM and EBC defines for CPU exception types +// +#include + +/// +/// Status Code Type Definition. +/// +typedef UINT32 EFI_STATUS_CODE_TYPE; + +/// +/// A Status Code Type is made up of the code type and severity. +/// All values masked by EFI_STATUS_CODE_RESERVED_MASK are +/// reserved for use by this specification. +/// +///@{ +#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF +#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000 +#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00 +///@} + +/// +/// Definition of code types. All other values masked by +/// EFI_STATUS_CODE_TYPE_MASK are reserved for use by +/// this specification. +/// +///@{ +#define EFI_PROGRESS_CODE 0x00000001 +#define EFI_ERROR_CODE 0x00000002 +#define EFI_DEBUG_CODE 0x00000003 +///@} + +/// +/// Definitions of severities, all other values masked by +/// EFI_STATUS_CODE_SEVERITY_MASK are reserved for use by +/// this specification. +/// Uncontained errors are major errors that could not contained +/// to the specific component that is reporting the error. +/// For example, if a memory error was not detected early enough, +/// the bad data could be consumed by other drivers. +/// +///@{ +#define EFI_ERROR_MINOR 0x40000000 +#define EFI_ERROR_MAJOR 0x80000000 +#define EFI_ERROR_UNRECOVERED 0x90000000 +#define EFI_ERROR_UNCONTAINED 0xa0000000 +///@} + +/// +/// Status Code Value Definition. +/// +typedef UINT32 EFI_STATUS_CODE_VALUE; + +/// +/// A Status Code Value is made up of the class, subclass, and +/// an operation. +/// +///@{ +#define EFI_STATUS_CODE_CLASS_MASK 0xFF000000 +#define EFI_STATUS_CODE_SUBCLASS_MASK 0x00FF0000 +#define EFI_STATUS_CODE_OPERATION_MASK 0x0000FFFF +///@} + +/// +/// Definition of Status Code extended data header. +/// The data will follow HeaderSize bytes from the beginning of +/// the structure and is Size bytes long. +/// +typedef struct { + /// + /// The size of the structure. This is specified to enable future expansion. + /// + UINT16 HeaderSize; + /// + /// The size of the data in bytes. This does not include the size of the header structure. + /// + UINT16 Size; + /// + /// The GUID defining the type of the data. + /// + EFI_GUID Type; +} EFI_STATUS_CODE_DATA; + +/// +/// General partitioning scheme for Progress and Error Codes are: +/// - 0x0000-0x0FFF Shared by all sub-classes in a given class. +/// - 0x1000-0x7FFF Subclass Specific. +/// - 0x8000-0xFFFF OEM specific. +///@{ +#define EFI_SUBCLASS_SPECIFIC 0x1000 +#define EFI_OEM_SPECIFIC 0x8000 +///@} + +/// +/// Debug Code definitions for all classes and subclass. +/// Only one debug code is defined at this point and should +/// be used for anything that is sent to the debug stream. +/// +///@{ +#define EFI_DC_UNSPECIFIED 0x0 +///@} + +/// +/// Class definitions. +/// Values of 4-127 are reserved for future use by this specification. +/// Values in the range 127-255 are reserved for OEM use. +/// +///@{ +#define EFI_COMPUTING_UNIT 0x00000000 +#define EFI_PERIPHERAL 0x01000000 +#define EFI_IO_BUS 0x02000000 +#define EFI_SOFTWARE 0x03000000 +///@} + +/// +/// Computing Unit Subclass definitions. +/// Values of 8-127 are reserved for future use by this specification. +/// Values of 128-255 are reserved for OEM use. +/// +///@{ +#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000) +#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000) +#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000) +#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000) +#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000) +#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000) +#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000) +///@} + +/// +/// Computing Unit Class Progress Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_CU_PC_INIT_BEGIN 0x00000000 +#define EFI_CU_PC_INIT_END 0x00000001 +///@} + +// +// Computing Unit Unspecified Subclass Progress Code definitions. +// + +/// +/// Computing Unit Host Processor Subclass Progress Code definitions. +///@{ +#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008) +///@} + +// +// Computing Unit Firmware Processor Subclass Progress Code definitions. +// + +// +// Computing Unit IO Processor Subclass Progress Code definitions. +// + +/// +/// Computing Unit Cache Subclass Progress Code definitions. +/// +///@{ +#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001) +///@} + +/// +/// Computing Unit Memory Subclass Progress Code definitions. +/// +///@{ +#define EFI_CU_MEMORY_PC_SPD_READ (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_MEMORY_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_MEMORY_PC_TIMING (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CU_MEMORY_PC_CONFIGURING (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_CU_MEMORY_PC_OPTIMIZING (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_CU_MEMORY_PC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_CU_MEMORY_PC_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000006) +///@} + +// +// Computing Unit Chipset Subclass Progress Code definitions. +// + +/// +/// South Bridge initialization prior to memory detection. +/// +#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000) + +/// +/// North Bridge initialization prior to memory detection. +/// +#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001) + +/// +/// South Bridge initialization after memory detection. +/// +#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002) + +/// +/// North Bridge initialization after memory detection. +/// +#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003) + +/// +/// PCI Host Bridge DXE initialization. +/// +#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004) + +/// +/// North Bridge DXE initialization. +/// +#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005) + +/// +/// North Bridge specific SMM initialization in DXE. +/// +#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006) + +/// +/// Initialization of the South Bridge specific UEFI Runtime Services. +/// +#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007) + +/// +/// South Bridge DXE initialization +/// +#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008) + +/// +/// South Bridge specific SMM initialization in DXE. +/// +#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009) + +/// +/// Initialization of the South Bridge devices. +/// +#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT (EFI_SUBCLASS_SPECIFIC|0x0000000a) + +/// +/// Computing Unit Class Error Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_CU_EC_NON_SPECIFIC 0x00000000 +#define EFI_CU_EC_DISABLED 0x00000001 +#define EFI_CU_EC_NOT_SUPPORTED 0x00000002 +#define EFI_CU_EC_NOT_DETECTED 0x00000003 +#define EFI_CU_EC_NOT_CONFIGURED 0x00000004 +///@} + +// +// Computing Unit Unspecified Subclass Error Code definitions. +// + +/// +/// Computing Unit Host Processor Subclass Error Code definitions. +/// +///@{ +#define EFI_CU_HP_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_HP_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_HP_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CU_HP_EC_TIMER_EXPIRED (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_CU_HP_EC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_CU_HP_EC_INTERNAL (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_CU_HP_EC_THERMAL (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_CU_HP_EC_LOW_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_CU_HP_EC_HIGH_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_CU_HP_EC_CACHE (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_CU_HP_EC_MICROCODE_UPDATE (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +#define EFI_CU_HP_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000B) +#define EFI_CU_HP_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000C) +#define EFI_CU_HP_EC_NO_MICROCODE_UPDATE (EFI_SUBCLASS_SPECIFIC | 0x0000000D) +///@} + +/// +/// Computing Unit Firmware Processor Subclass Error Code definitions. +/// +///@{ +#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +// +// Computing Unit IO Processor Subclass Error Code definitions. +// + +/// +/// Computing Unit Cache Subclass Error Code definitions. +/// +///@{ +#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003) +///@} + +/// +/// Computing Unit Memory Subclass Error Code definitions. +/// +///@{ +#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +///@} + +/// +/// Computing Unit Chipset Subclass Error Code definitions. +/// +///@{ +#define EFI_CHIPSET_EC_BAD_BATTERY (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_CHIPSET_EC_DXE_NB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_CHIPSET_EC_DXE_SB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_CHIPSET_EC_INTRUDER_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000003) +///@} + +/// +/// Peripheral Subclass definitions. +/// Values of 12-127 are reserved for future use by this specification. +/// Values of 128-255 are reserved for OEM use. +/// +///@{ +#define EFI_PERIPHERAL_UNSPECIFIED (EFI_PERIPHERAL | 0x00000000) +#define EFI_PERIPHERAL_KEYBOARD (EFI_PERIPHERAL | 0x00010000) +#define EFI_PERIPHERAL_MOUSE (EFI_PERIPHERAL | 0x00020000) +#define EFI_PERIPHERAL_LOCAL_CONSOLE (EFI_PERIPHERAL | 0x00030000) +#define EFI_PERIPHERAL_REMOTE_CONSOLE (EFI_PERIPHERAL | 0x00040000) +#define EFI_PERIPHERAL_SERIAL_PORT (EFI_PERIPHERAL | 0x00050000) +#define EFI_PERIPHERAL_PARALLEL_PORT (EFI_PERIPHERAL | 0x00060000) +#define EFI_PERIPHERAL_FIXED_MEDIA (EFI_PERIPHERAL | 0x00070000) +#define EFI_PERIPHERAL_REMOVABLE_MEDIA (EFI_PERIPHERAL | 0x00080000) +#define EFI_PERIPHERAL_AUDIO_INPUT (EFI_PERIPHERAL | 0x00090000) +#define EFI_PERIPHERAL_AUDIO_OUTPUT (EFI_PERIPHERAL | 0x000A0000) +#define EFI_PERIPHERAL_LCD_DEVICE (EFI_PERIPHERAL | 0x000B0000) +#define EFI_PERIPHERAL_NETWORK (EFI_PERIPHERAL | 0x000C0000) +#define EFI_PERIPHERAL_DOCKING (EFI_PERIPHERAL | 0x000D0000) +///@} + +/// +/// Peripheral Class Progress Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_P_PC_INIT 0x00000000 +#define EFI_P_PC_RESET 0x00000001 +#define EFI_P_PC_DISABLE 0x00000002 +#define EFI_P_PC_PRESENCE_DETECT 0x00000003 +#define EFI_P_PC_ENABLE 0x00000004 +#define EFI_P_PC_RECONFIG 0x00000005 +#define EFI_P_PC_DETECTED 0x00000006 +#define EFI_P_PC_REMOVED 0x00000007 +///@} + +// +// Peripheral Class Unspecified Subclass Progress Code definitions. +// + +/// +/// Peripheral Class Keyboard Subclass Progress Code definitions. +/// +///@{ +#define EFI_P_KEYBOARD_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_P_KEYBOARD_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000001) +///@} + +/// +/// Peripheral Class Mouse Subclass Progress Code definitions. +/// +///@{ +#define EFI_P_MOUSE_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000000) +///@} + +// +// Peripheral Class Local Console Subclass Progress Code definitions. +// + +// +// Peripheral Class Remote Console Subclass Progress Code definitions. +// + +/// +/// Peripheral Class Serial Port Subclass Progress Code definitions. +/// +///@{ +#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000) +///@} + +// +// Peripheral Class Parallel Port Subclass Progress Code definitions. +// + +// +// Peripheral Class Fixed Media Subclass Progress Code definitions. +// + +// +// Peripheral Class Removable Media Subclass Progress Code definitions. +// + +// +// Peripheral Class Audio Input Subclass Progress Code definitions. +// + +// +// Peripheral Class Audio Output Subclass Progress Code definitions. +// + +// +// Peripheral Class LCD Device Subclass Progress Code definitions. +// + +// +// Peripheral Class Network Subclass Progress Code definitions. +// + +/// +/// Peripheral Class Error Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_P_EC_NON_SPECIFIC 0x00000000 +#define EFI_P_EC_DISABLED 0x00000001 +#define EFI_P_EC_NOT_SUPPORTED 0x00000002 +#define EFI_P_EC_NOT_DETECTED 0x00000003 +#define EFI_P_EC_NOT_CONFIGURED 0x00000004 +#define EFI_P_EC_INTERFACE_ERROR 0x00000005 +#define EFI_P_EC_CONTROLLER_ERROR 0x00000006 +#define EFI_P_EC_INPUT_ERROR 0x00000007 +#define EFI_P_EC_OUTPUT_ERROR 0x00000008 +#define EFI_P_EC_RESOURCE_CONFLICT 0x00000009 +///@} + +// +// Peripheral Class Unspecified Subclass Error Code definitions. +// + +/// +/// Peripheral Class Keyboard Subclass Error Code definitions. +/// +///@{ +#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +/// +/// Peripheral Class Mouse Subclass Error Code definitions. +/// +///@{ +#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000) +///@} + +// +// Peripheral Class Local Console Subclass Error Code definitions. +// + +// +// Peripheral Class Remote Console Subclass Error Code definitions. +// + +// +// Peripheral Class Serial Port Subclass Error Code definitions. +// + +// +// Peripheral Class Parallel Port Subclass Error Code definitions. +// + +// +// Peripheral Class Fixed Media Subclass Error Code definitions. +// + +// +// Peripheral Class Removable Media Subclass Error Code definitions. +// + +// +// Peripheral Class Audio Input Subclass Error Code definitions. +// + +// +// Peripheral Class Audio Output Subclass Error Code definitions. +// + +// +// Peripheral Class LCD Device Subclass Error Code definitions. +// + +// +// Peripheral Class Network Subclass Error Code definitions. +// + +/// +/// IO Bus Subclass definitions. +/// Values of 14-127 are reserved for future use by this specification. +/// Values of 128-255 are reserved for OEM use. +/// +///@{ +#define EFI_IO_BUS_UNSPECIFIED (EFI_IO_BUS | 0x00000000) +#define EFI_IO_BUS_PCI (EFI_IO_BUS | 0x00010000) +#define EFI_IO_BUS_USB (EFI_IO_BUS | 0x00020000) +#define EFI_IO_BUS_IBA (EFI_IO_BUS | 0x00030000) +#define EFI_IO_BUS_AGP (EFI_IO_BUS | 0x00040000) +#define EFI_IO_BUS_PC_CARD (EFI_IO_BUS | 0x00050000) +#define EFI_IO_BUS_LPC (EFI_IO_BUS | 0x00060000) +#define EFI_IO_BUS_SCSI (EFI_IO_BUS | 0x00070000) +#define EFI_IO_BUS_ATA_ATAPI (EFI_IO_BUS | 0x00080000) +#define EFI_IO_BUS_FC (EFI_IO_BUS | 0x00090000) +#define EFI_IO_BUS_IP_NETWORK (EFI_IO_BUS | 0x000A0000) +#define EFI_IO_BUS_SMBUS (EFI_IO_BUS | 0x000B0000) +#define EFI_IO_BUS_I2C (EFI_IO_BUS | 0x000C0000) +///@} + +/// +/// IO Bus Class Progress Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_IOB_PC_INIT 0x00000000 +#define EFI_IOB_PC_RESET 0x00000001 +#define EFI_IOB_PC_DISABLE 0x00000002 +#define EFI_IOB_PC_DETECT 0x00000003 +#define EFI_IOB_PC_ENABLE 0x00000004 +#define EFI_IOB_PC_RECONFIG 0x00000005 +#define EFI_IOB_PC_HOTPLUG 0x00000006 +///@} + +// +// IO Bus Class Unspecified Subclass Progress Code definitions. +// + +/// +/// IO Bus Class PCI Subclass Progress Code definitions. +/// +///@{ +#define EFI_IOB_PCI_BUS_ENUM (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_IOB_PCI_RES_ALLOC (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_IOB_PCI_HPC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +// +// IO Bus Class USB Subclass Progress Code definitions. +// + +// +// IO Bus Class IBA Subclass Progress Code definitions. +// + +// +// IO Bus Class AGP Subclass Progress Code definitions. +// + +// +// IO Bus Class PC Card Subclass Progress Code definitions. +// + +// +// IO Bus Class LPC Subclass Progress Code definitions. +// + +// +// IO Bus Class SCSI Subclass Progress Code definitions. +// + +// +// IO Bus Class ATA/ATAPI Subclass Progress Code definitions. +// +#define EFI_IOB_ATA_BUS_SMART_ENABLE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_IOB_ATA_BUS_SMART_DISABLE (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000003) +// +// IO Bus Class FC Subclass Progress Code definitions. +// + +// +// IO Bus Class IP Network Subclass Progress Code definitions. +// + +// +// IO Bus Class SMBUS Subclass Progress Code definitions. +// + +// +// IO Bus Class I2C Subclass Progress Code definitions. +// + +/// +/// IO Bus Class Error Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_IOB_EC_NON_SPECIFIC 0x00000000 +#define EFI_IOB_EC_DISABLED 0x00000001 +#define EFI_IOB_EC_NOT_SUPPORTED 0x00000002 +#define EFI_IOB_EC_NOT_DETECTED 0x00000003 +#define EFI_IOB_EC_NOT_CONFIGURED 0x00000004 +#define EFI_IOB_EC_INTERFACE_ERROR 0x00000005 +#define EFI_IOB_EC_CONTROLLER_ERROR 0x00000006 +#define EFI_IOB_EC_READ_ERROR 0x00000007 +#define EFI_IOB_EC_WRITE_ERROR 0x00000008 +#define EFI_IOB_EC_RESOURCE_CONFLICT 0x00000009 +///@} + +// +// IO Bus Class Unspecified Subclass Error Code definitions. +// + +/// +/// IO Bus Class PCI Subclass Error Code definitions. +/// +///@{ +#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001) +///@} + +// +// IO Bus Class USB Subclass Error Code definitions. +// + +// +// IO Bus Class IBA Subclass Error Code definitions. +// + +// +// IO Bus Class AGP Subclass Error Code definitions. +// + +// +// IO Bus Class PC Card Subclass Error Code definitions. +// + +// +// IO Bus Class LPC Subclass Error Code definitions. +// + +// +// IO Bus Class SCSI Subclass Error Code definitions. +// + +// +// IO Bus Class ATA/ATAPI Subclass Error Code definitions. +// +#define EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_IOB_ATA_BUS_SMART_DISABLED (EFI_SUBCLASS_SPECIFIC | 0x00000001) + +// +// IO Bus Class FC Subclass Error Code definitions. +// + +// +// IO Bus Class IP Network Subclass Error Code definitions. +// + +// +// IO Bus Class SMBUS Subclass Error Code definitions. +// + +// +// IO Bus Class I2C Subclass Error Code definitions. +// + +/// +/// Software Subclass definitions. +/// Values of 14-127 are reserved for future use by this specification. +/// Values of 128-255 are reserved for OEM use. +/// +///@{ +#define EFI_SOFTWARE_UNSPECIFIED (EFI_SOFTWARE | 0x00000000) +#define EFI_SOFTWARE_SEC (EFI_SOFTWARE | 0x00010000) +#define EFI_SOFTWARE_PEI_CORE (EFI_SOFTWARE | 0x00020000) +#define EFI_SOFTWARE_PEI_MODULE (EFI_SOFTWARE | 0x00030000) +#define EFI_SOFTWARE_DXE_CORE (EFI_SOFTWARE | 0x00040000) +#define EFI_SOFTWARE_DXE_BS_DRIVER (EFI_SOFTWARE | 0x00050000) +#define EFI_SOFTWARE_DXE_RT_DRIVER (EFI_SOFTWARE | 0x00060000) +#define EFI_SOFTWARE_SMM_DRIVER (EFI_SOFTWARE | 0x00070000) +#define EFI_SOFTWARE_EFI_APPLICATION (EFI_SOFTWARE | 0x00080000) +#define EFI_SOFTWARE_EFI_OS_LOADER (EFI_SOFTWARE | 0x00090000) +#define EFI_SOFTWARE_RT (EFI_SOFTWARE | 0x000A0000) +#define EFI_SOFTWARE_AL (EFI_SOFTWARE | 0x000B0000) +#define EFI_SOFTWARE_EBC_EXCEPTION (EFI_SOFTWARE | 0x000C0000) +#define EFI_SOFTWARE_IA32_EXCEPTION (EFI_SOFTWARE | 0x000D0000) +#define EFI_SOFTWARE_IPF_EXCEPTION (EFI_SOFTWARE | 0x000E0000) +#define EFI_SOFTWARE_PEI_SERVICE (EFI_SOFTWARE | 0x000F0000) +#define EFI_SOFTWARE_EFI_BOOT_SERVICE (EFI_SOFTWARE | 0x00100000) +#define EFI_SOFTWARE_EFI_RUNTIME_SERVICE (EFI_SOFTWARE | 0x00110000) +#define EFI_SOFTWARE_EFI_DXE_SERVICE (EFI_SOFTWARE | 0x00120000) +#define EFI_SOFTWARE_X64_EXCEPTION (EFI_SOFTWARE | 0x00130000) +#define EFI_SOFTWARE_ARM_EXCEPTION (EFI_SOFTWARE | 0x00140000) + +///@} + +/// +/// Software Class Progress Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_SW_PC_INIT 0x00000000 +#define EFI_SW_PC_LOAD 0x00000001 +#define EFI_SW_PC_INIT_BEGIN 0x00000002 +#define EFI_SW_PC_INIT_END 0x00000003 +#define EFI_SW_PC_AUTHENTICATE_BEGIN 0x00000004 +#define EFI_SW_PC_AUTHENTICATE_END 0x00000005 +#define EFI_SW_PC_INPUT_WAIT 0x00000006 +#define EFI_SW_PC_USER_SETUP 0x00000007 +///@} + +// +// Software Class Unspecified Subclass Progress Code definitions. +// + +/// +/// Software Class SEC Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +///@} + +/// +/// Software Class PEI Core Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_PEI_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_PEI_CORE_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +/// +/// Software Class PEI Module Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_PEI_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PEI_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_PEI_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_PEI_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_PEI_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_PEI_PC_S3_BOOT_SCRIPT (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_PEI_PC_OS_WAKE (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_PEI_PC_S3_STARTED (EFI_SUBCLASS_SPECIFIC | 0x00000007) +///@} + +/// +/// Software Class DXE Core Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_DXE_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_DXE_CORE_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_DXE_CORE_PC_START_DRIVER (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_DXE_CORE_PC_ARCH_READY (EFI_SUBCLASS_SPECIFIC | 0x00000004) +///@} + +/// +/// Software Class DXE BS Driver Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009) +///@} + +// +// Software Class SMM Driver Subclass Progress Code definitions. +// + +// +// Software Class EFI Application Subclass Progress Code definitions. +// + +// +// Software Class EFI OS Loader Subclass Progress Code definitions. +// + +/// +/// Software Class EFI RT Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_RT_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_RT_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_RT_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +// +// Software Class X64 Exception Subclass Progress Code definitions. +// + +// +// Software Class ARM Exception Subclass Progress Code definitions. +// + +// +// Software Class EBC Exception Subclass Progress Code definitions. +// + +// +// Software Class IA32 Exception Subclass Progress Code definitions. +// + +// +// Software Class X64 Exception Subclass Progress Code definitions. +// + +// +// Software Class IPF Exception Subclass Progress Code definitions. +// + +/// +/// Software Class PEI Services Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_PS_PC_INSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PS_PC_REINSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_PS_PC_LOCATE_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_PS_PC_NOTIFY_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_PS_PC_GET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_PS_PC_SET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_PS_PC_GET_HOB_LIST (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_PS_PC_CREATE_HOB (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_PS_PC_FFS_FIND_NEXT_VOLUME (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_PS_PC_FFS_FIND_NEXT_FILE (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_SW_PS_PC_FFS_FIND_SECTION_DATA (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +#define EFI_SW_PS_PC_INSTALL_PEI_MEMORY (EFI_SUBCLASS_SPECIFIC | 0x0000000B) +#define EFI_SW_PS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x0000000C) +#define EFI_SW_PS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x0000000D) +#define EFI_SW_PS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000E) +#define EFI_SW_PS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000F) +#define EFI_SW_PS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x00000010) +#define EFI_SW_PS_PC_FFS_FIND_FILE_BY_NAME (EFI_SUBCLASS_SPECIFIC | 0x00000013) +#define EFI_SW_PS_PC_FFS_GET_FILE_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000014) +#define EFI_SW_PS_PC_FFS_GET_VOLUME_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000015) +#define EFI_SW_PS_PC_FFS_REGISTER_FOR_SHADOW (EFI_SUBCLASS_SPECIFIC | 0x00000016) +///@} + +/// +/// Software Class EFI Boot Services Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_BS_PC_RAISE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_BS_PC_RESTORE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_BS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_BS_PC_FREE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_BS_PC_GET_MEMORY_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_BS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_BS_PC_FREE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_BS_PC_CREATE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_BS_PC_SET_TIMER (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_BS_PC_WAIT_FOR_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_SW_BS_PC_SIGNAL_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +#define EFI_SW_BS_PC_CLOSE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000B) +#define EFI_SW_BS_PC_CHECK_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000C) +#define EFI_SW_BS_PC_INSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000D) +#define EFI_SW_BS_PC_REINSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000E) +#define EFI_SW_BS_PC_UNINSTALL_PROTOCOL_INTERFACE (EFI_SUBCLASS_SPECIFIC | 0x0000000F) +#define EFI_SW_BS_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000010) +#define EFI_SW_BS_PC_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000011) +#define EFI_SW_BS_PC_REGISTER_PROTOCOL_NOTIFY (EFI_SUBCLASS_SPECIFIC | 0x00000012) +#define EFI_SW_BS_PC_LOCATE_HANDLE (EFI_SUBCLASS_SPECIFIC | 0x00000013) +#define EFI_SW_BS_PC_INSTALL_CONFIGURATION_TABLE (EFI_SUBCLASS_SPECIFIC | 0x00000014) +#define EFI_SW_BS_PC_LOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000015) +#define EFI_SW_BS_PC_START_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000016) +#define EFI_SW_BS_PC_EXIT (EFI_SUBCLASS_SPECIFIC | 0x00000017) +#define EFI_SW_BS_PC_UNLOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000018) +#define EFI_SW_BS_PC_EXIT_BOOT_SERVICES (EFI_SUBCLASS_SPECIFIC | 0x00000019) +#define EFI_SW_BS_PC_GET_NEXT_MONOTONIC_COUNT (EFI_SUBCLASS_SPECIFIC | 0x0000001A) +#define EFI_SW_BS_PC_STALL (EFI_SUBCLASS_SPECIFIC | 0x0000001B) +#define EFI_SW_BS_PC_SET_WATCHDOG_TIMER (EFI_SUBCLASS_SPECIFIC | 0x0000001C) +#define EFI_SW_BS_PC_CONNECT_CONTROLLER (EFI_SUBCLASS_SPECIFIC | 0x0000001D) +#define EFI_SW_BS_PC_DISCONNECT_CONTROLLER (EFI_SUBCLASS_SPECIFIC | 0x0000001E) +#define EFI_SW_BS_PC_OPEN_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x0000001F) +#define EFI_SW_BS_PC_CLOSE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000020) +#define EFI_SW_BS_PC_OPEN_PROTOCOL_INFORMATION (EFI_SUBCLASS_SPECIFIC | 0x00000021) +#define EFI_SW_BS_PC_PROTOCOLS_PER_HANDLE (EFI_SUBCLASS_SPECIFIC | 0x00000022) +#define EFI_SW_BS_PC_LOCATE_HANDLE_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000023) +#define EFI_SW_BS_PC_LOCATE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000024) +#define EFI_SW_BS_PC_INSTALL_MULTIPLE_INTERFACES (EFI_SUBCLASS_SPECIFIC | 0x00000025) +#define EFI_SW_BS_PC_UNINSTALL_MULTIPLE_INTERFACES (EFI_SUBCLASS_SPECIFIC | 0x00000026) +#define EFI_SW_BS_PC_CALCULATE_CRC_32 (EFI_SUBCLASS_SPECIFIC | 0x00000027) +#define EFI_SW_BS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000028) +#define EFI_SW_BS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000029) +#define EFI_SW_BS_PC_CREATE_EVENT_EX (EFI_SUBCLASS_SPECIFIC | 0x0000002A) +///@} + +/// +/// Software Class EFI Runtime Services Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_RS_PC_GET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_RS_PC_SET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_RS_PC_GET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_RS_PC_SET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_RS_PC_SET_VIRTUAL_ADDRESS_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_RS_PC_CONVERT_POINTER (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_RS_PC_GET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_RS_PC_GET_NEXT_VARIABLE_NAME (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_RS_PC_SET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_RS_PC_GET_NEXT_HIGH_MONOTONIC_COUNT (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_SW_RS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +#define EFI_SW_RS_PC_UPDATE_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x0000000B) +#define EFI_SW_RS_PC_QUERY_CAPSULE_CAPABILITIES (EFI_SUBCLASS_SPECIFIC | 0x0000000C) +#define EFI_SW_RS_PC_QUERY_VARIABLE_INFO (EFI_SUBCLASS_SPECIFIC | 0x0000000D) +///@} + +/// +/// Software Class EFI DXE Services Subclass Progress Code definitions +/// +///@{ +#define EFI_SW_DS_PC_ADD_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_DS_PC_ALLOCATE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_DS_PC_FREE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_DS_PC_REMOVE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_DS_PC_GET_MEMORY_SPACE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_DS_PC_SET_MEMORY_SPACE_ATTRIBUTES (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_DS_PC_GET_MEMORY_SPACE_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_DS_PC_ADD_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_DS_PC_ALLOCATE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_DS_PC_FREE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000009) +#define EFI_SW_DS_PC_REMOVE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x0000000A) +#define EFI_SW_DS_PC_GET_IO_SPACE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x0000000B) +#define EFI_SW_DS_PC_GET_IO_SPACE_MAP (EFI_SUBCLASS_SPECIFIC | 0x0000000C) +#define EFI_SW_DS_PC_DISPATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000D) +#define EFI_SW_DS_PC_SCHEDULE (EFI_SUBCLASS_SPECIFIC | 0x0000000E) +#define EFI_SW_DS_PC_TRUST (EFI_SUBCLASS_SPECIFIC | 0x0000000F) +#define EFI_SW_DS_PC_PROCESS_FIRMWARE_VOLUME (EFI_SUBCLASS_SPECIFIC | 0x00000010) +///@} + +/// +/// Software Class Error Code definitions. +/// These are shared by all subclasses. +/// +///@{ +#define EFI_SW_EC_NON_SPECIFIC 0x00000000 +#define EFI_SW_EC_LOAD_ERROR 0x00000001 +#define EFI_SW_EC_INVALID_PARAMETER 0x00000002 +#define EFI_SW_EC_UNSUPPORTED 0x00000003 +#define EFI_SW_EC_INVALID_BUFFER 0x00000004 +#define EFI_SW_EC_OUT_OF_RESOURCES 0x00000005 +#define EFI_SW_EC_ABORTED 0x00000006 +#define EFI_SW_EC_ILLEGAL_SOFTWARE_STATE 0x00000007 +#define EFI_SW_EC_ILLEGAL_HARDWARE_STATE 0x00000008 +#define EFI_SW_EC_START_ERROR 0x00000009 +#define EFI_SW_EC_BAD_DATE_TIME 0x0000000A +#define EFI_SW_EC_CFG_INVALID 0x0000000B +#define EFI_SW_EC_CFG_CLR_REQUEST 0x0000000C +#define EFI_SW_EC_CFG_DEFAULT 0x0000000D +#define EFI_SW_EC_PWD_INVALID 0x0000000E +#define EFI_SW_EC_PWD_CLR_REQUEST 0x0000000F +#define EFI_SW_EC_PWD_CLEARED 0x00000010 +#define EFI_SW_EC_EVENT_LOG_FULL 0x00000011 +#define EFI_SW_EC_WRITE_PROTECTED 0x00000012 +#define EFI_SW_EC_FV_CORRUPTED 0x00000013 +///@} + +// +// Software Class Unspecified Subclass Error Code definitions. +// + +// +// Software Class SEC Subclass Error Code definitions. +// + +/// +/// Software Class PEI Core Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_PEI_CORE_EC_DXE_CORRUPT (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PEI_CORE_EC_DXEIPL_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_PEI_CORE_EC_MEMORY_NOT_INSTALLED (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +/// +/// Software Class PEI Module Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006) +#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007) +#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008) +#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009) +///@} + +/// +/// Software Class DXE Foundation Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000) +///@} + + +/// +/// Software Class DXE Boot Service Driver Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_DXE_BS_EC_LEGACY_OPROM_NO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_DXE_BS_EC_INVALID_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_DXE_BS_EC_BOOT_OPTION_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_DXE_BS_EC_INVALID_IDE_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000004) +///@} + +// +// Software Class DXE Runtime Service Driver Subclass Error Code definitions. +// + +// +// Software Class SMM Driver Subclass Error Code definitions. +// + +// +// Software Class EFI Application Subclass Error Code definitions. +// + +// +// Software Class EFI OS Loader Subclass Error Code definitions. +// + +// +// Software Class EFI RT Subclass Error Code definitions. +// + +// +// Software Class EFI AL Subclass Error Code definitions. +// + +/// +/// Software Class EBC Exception Subclass Error Code definitions. +/// These exceptions are derived from the debug protocol definitions in the EFI +/// specification. +/// +///@{ +#define EFI_SW_EC_EBC_UNDEFINED 0x00000000 +#define EFI_SW_EC_EBC_DIVIDE_ERROR EXCEPT_EBC_DIVIDE_ERROR +#define EFI_SW_EC_EBC_DEBUG EXCEPT_EBC_DEBUG +#define EFI_SW_EC_EBC_BREAKPOINT EXCEPT_EBC_BREAKPOINT +#define EFI_SW_EC_EBC_OVERFLOW EXCEPT_EBC_OVERFLOW +#define EFI_SW_EC_EBC_INVALID_OPCODE EXCEPT_EBC_INVALID_OPCODE +#define EFI_SW_EC_EBC_STACK_FAULT EXCEPT_EBC_STACK_FAULT +#define EFI_SW_EC_EBC_ALIGNMENT_CHECK EXCEPT_EBC_ALIGNMENT_CHECK +#define EFI_SW_EC_EBC_INSTRUCTION_ENCODING EXCEPT_EBC_INSTRUCTION_ENCODING +#define EFI_SW_EC_EBC_BAD_BREAK EXCEPT_EBC_BAD_BREAK +#define EFI_SW_EC_EBC_STEP EXCEPT_EBC_STEP +///@} + +/// +/// Software Class IA32 Exception Subclass Error Code definitions. +/// These exceptions are derived from the debug protocol definitions in the EFI +/// specification. +/// +///@{ +#define EFI_SW_EC_IA32_DIVIDE_ERROR EXCEPT_IA32_DIVIDE_ERROR +#define EFI_SW_EC_IA32_DEBUG EXCEPT_IA32_DEBUG +#define EFI_SW_EC_IA32_NMI EXCEPT_IA32_NMI +#define EFI_SW_EC_IA32_BREAKPOINT EXCEPT_IA32_BREAKPOINT +#define EFI_SW_EC_IA32_OVERFLOW EXCEPT_IA32_OVERFLOW +#define EFI_SW_EC_IA32_BOUND EXCEPT_IA32_BOUND +#define EFI_SW_EC_IA32_INVALID_OPCODE EXCEPT_IA32_INVALID_OPCODE +#define EFI_SW_EC_IA32_DOUBLE_FAULT EXCEPT_IA32_DOUBLE_FAULT +#define EFI_SW_EC_IA32_INVALID_TSS EXCEPT_IA32_INVALID_TSS +#define EFI_SW_EC_IA32_SEG_NOT_PRESENT EXCEPT_IA32_SEG_NOT_PRESENT +#define EFI_SW_EC_IA32_STACK_FAULT EXCEPT_IA32_STACK_FAULT +#define EFI_SW_EC_IA32_GP_FAULT EXCEPT_IA32_GP_FAULT +#define EFI_SW_EC_IA32_PAGE_FAULT EXCEPT_IA32_PAGE_FAULT +#define EFI_SW_EC_IA32_FP_ERROR EXCEPT_IA32_FP_ERROR +#define EFI_SW_EC_IA32_ALIGNMENT_CHECK EXCEPT_IA32_ALIGNMENT_CHECK +#define EFI_SW_EC_IA32_MACHINE_CHECK EXCEPT_IA32_MACHINE_CHECK +#define EFI_SW_EC_IA32_SIMD EXCEPT_IA32_SIMD +///@} + +/// +/// Software Class IPF Exception Subclass Error Code definitions. +/// These exceptions are derived from the debug protocol definitions in the EFI +/// specification. +/// +///@{ +#define EFI_SW_EC_IPF_ALT_DTLB EXCEPT_IPF_ALT_DTLB +#define EFI_SW_EC_IPF_DNESTED_TLB EXCEPT_IPF_DNESTED_TLB +#define EFI_SW_EC_IPF_BREAKPOINT EXCEPT_IPF_BREAKPOINT +#define EFI_SW_EC_IPF_EXTERNAL_INTERRUPT EXCEPT_IPF_EXTERNAL_INTERRUPT +#define EFI_SW_EC_IPF_GEN_EXCEPT EXCEPT_IPF_GEN_EXCEPT +#define EFI_SW_EC_IPF_NAT_CONSUMPTION EXCEPT_IPF_NAT_CONSUMPTION +#define EFI_SW_EC_IPF_DEBUG_EXCEPT EXCEPT_IPF_DEBUG_EXCEPT +#define EFI_SW_EC_IPF_UNALIGNED_ACCESS EXCEPT_IPF_UNALIGNED_ACCESS +#define EFI_SW_EC_IPF_FP_FAULT EXCEPT_IPF_FP_FAULT +#define EFI_SW_EC_IPF_FP_TRAP EXCEPT_IPF_FP_TRAP +#define EFI_SW_EC_IPF_TAKEN_BRANCH EXCEPT_IPF_TAKEN_BRANCH +#define EFI_SW_EC_IPF_SINGLE_STEP EXCEPT_IPF_SINGLE_STEP +///@} + +/// +/// Software Class PEI Service Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_PS_EC_RESET_NOT_AVAILABLE (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_PS_EC_MEMORY_INSTALLED_TWICE (EFI_SUBCLASS_SPECIFIC | 0x00000001) +///@} + +// +// Software Class EFI Boot Service Subclass Error Code definitions. +// + +// +// Software Class EFI Runtime Service Subclass Error Code definitions. +// + +/// +/// Software Class EFI DXE Service Subclass Error Code definitions. +/// +///@{ +#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005) +#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006) +///@} + +/// +/// Software Class DXE RT Driver Subclass Progress Code definitions. +/// +///@{ +#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002) +#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003) +#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004) +#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005) +///@} + +/// +/// Software Class X64 Exception Subclass Error Code definitions. +/// These exceptions are derived from the debug protocol +/// definitions in the EFI specification. +/// +///@{ +#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR +#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG +#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI +#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT +#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW +#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND +#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE +#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT +#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS +#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT +#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT +#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT +#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT +#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR +#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK +#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK +#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD +///@} + +/// +/// Software Class ARM Exception Subclass Error Code definitions. +/// These exceptions are derived from the debug protocol +/// definitions in the EFI specification. +/// +///@{ +#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET +#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION +#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT +#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT +#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT +#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED +#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ +#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ +///@} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiDxe.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiDxe.h new file mode 100644 index 0000000000..32aa1083c7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiDxe.h @@ -0,0 +1,19 @@ +/** @file + + Root include file for Mde Package DXE_CORE, DXE, RUNTIME, SMM, SAL type modules. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PI_DXE_H__ +#define __PI_DXE_H__ + +#include +#include + +#include + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiMm.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiMm.h new file mode 100644 index 0000000000..006c285fce --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiMm.h @@ -0,0 +1,19 @@ +/** @file + + Root include file for Mde Package MM modules. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PI_MM_H__ +#define __PI_MM_H__ + +#include +#include + +#include + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiPei.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiPei.h new file mode 100644 index 0000000000..277d8c85f3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiPei.h @@ -0,0 +1,21 @@ +/** @file + + Root include file for Mde Package SEC, PEIM, PEI_CORE type modules. + + This is the include file for any module of type PEIM. PEIM + modules only use types defined via this include file and can + be ported easily to any environment. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PI_PEI_H__ +#define __PI_PEI_H__ + +#include +#include + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiSmm.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiSmm.h new file mode 100644 index 0000000000..3db3c41c08 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/PiSmm.h @@ -0,0 +1,19 @@ +/** @file + + Root include file for Mde Package SMM modules. + +Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PI_SMM_H__ +#define __PI_SMM_H__ + +#include +#include + +#include + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo.h new file mode 100644 index 0000000000..220c5ba137 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo.h @@ -0,0 +1,232 @@ +/** @file + Provides the services required to access a block I/O device during PEI recovery + boot mode. + + The Recovery Module PPI and the Device Recovery Module PPI are device neutral. + This PPI is device specific and addresses the most common form of recovery + media-block I/O devices such as legacy floppy, CD-ROM, or IDE devices. + + The Recovery Block I/O PPI is used to access block devices. Because the Recovery + Block I/O PPIs that are provided by the PEI ATAPI driver and PEI legacy floppy + driver are the same, here we define a set of general PPIs for both drivers to use. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1: + Pre-EFI Initialization Core Interface. + +**/ + +#ifndef _PEI_BLOCK_IO_H_ +#define _PEI_BLOCK_IO_H_ + +/// +/// Global ID for EFI_PEI_RECOVERY_BLOCK_IO_PPI +/// +#define EFI_PEI_RECOVERY_BLOCK_IO_PPI_GUID \ + { \ + 0x695d8aa1, 0x42ee, 0x4c46, { 0x80, 0x5c, 0x6e, 0xa6, 0xbc, 0xe7, 0x99, 0xe3 } \ + } + +/// +/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI. +/// +typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI; + +/// +/// All blocks on the recovery device are addressed with a 64-bit Logical Block Address (LBA). +/// +typedef UINT64 EFI_PEI_LBA; + +/// +/// EFI_PEI_BLOCK_DEVICE_TYPE +/// +typedef enum { + LegacyFloppy = 0, ///< The recovery device is a floppy. + IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM + IdeLS120 = 2, ///< The recovery device is an IDE LS-120 + UsbMassStorage= 3, ///< The recovery device is a USB Mass Storage device + SD = 4, ///< The recovery device is a Secure Digital device + EMMC = 5, ///< The recovery device is a eMMC device + UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device + MaxDeviceType +} EFI_PEI_BLOCK_DEVICE_TYPE; + +/// +/// Specification inconsistency here: +/// PEI_BLOCK_IO_MEDIA has been changed to EFI_PEI_BLOCK_IO_MEDIA. +/// Inconsistency exists in UEFI Platform Initialization Specification 1.2 +/// Volume 1: Pre-EFI Initialization Core Interface, where all references to +/// this structure name are with the "EFI_" prefix, except for the definition +/// which is without "EFI_". So the name of PEI_BLOCK_IO_MEDIA is taken as the +/// exception, and EFI_PEI_BLOCK_IO_MEDIA is used to comply with most of +/// the specification. +/// +typedef struct { + /// + /// The type of media device being referenced by DeviceIndex. + /// + EFI_PEI_BLOCK_DEVICE_TYPE DeviceType; + /// + /// A flag that indicates if media is present. This flag is always set for + /// nonremovable media devices. + /// + BOOLEAN MediaPresent; + /// + /// The last logical block that the device supports. + /// + UINTN LastBlock; + /// + /// The size of a logical block in bytes. + /// + UINTN BlockSize; +} EFI_PEI_BLOCK_IO_MEDIA; + +/** + Gets the count of block I/O devices that one specific block driver detects. + + This function is used for getting the count of block I/O devices that one + specific block driver detects. To the PEI ATAPI driver, it returns the number + of all the detected ATAPI devices it detects during the enumeration process. + To the PEI legacy floppy driver, it returns the number of all the legacy + devices it finds during its enumeration process. If no device is detected, + then the function will return zero. + + @param[in] PeiServices General-purpose services that are available + to every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI + instance. + @param[out] NumberBlockDevices The number of block I/O devices discovered. + + @retval EFI_SUCCESS The operation performed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + OUT UINTN *NumberBlockDevices + ); + +/** + Gets a block device's media information. + + This function will provide the caller with the specified block device's media + information. If the media changes, calling this function will update the media + information accordingly. + + @param[in] PeiServices General-purpose services that are available to every + PEIM + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, the PPIs that + want to talk to a single device must specify the + device index that was assigned during the enumeration + process. This index is a number from one to + NumberBlockDevices. + @param[out] MediaInfo The media information of the specified block media. + The caller is responsible for the ownership of this + data structure. + + @par Note: + The MediaInfo structure describes an enumeration of possible block device + types. This enumeration exists because no device paths are actually passed + across interfaces that describe the type or class of hardware that is publishing + the block I/O interface. This enumeration will allow for policy decisions + in the Recovery PEIM, such as "Try to recover from legacy floppy first, + LS-120 second, CD-ROM third." If there are multiple partitions abstracted + by a given device type, they should be reported in ascending order; this + order also applies to nested partitions, such as legacy MBR, where the + outermost partitions would have precedence in the reporting order. The + same logic applies to systems such as IDE that have precedence relationships + like "Master/Slave" or "Primary/Secondary". The master device should be + reported first, the slave second. + + @retval EFI_SUCCESS Media information about the specified block device + was obtained successfully. + @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + IN UINTN DeviceIndex, + OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo + ); + +/** + Reads the requested number of blocks from the specified block device. + + The function reads the requested number of blocks from the device. All the + blocks are read, or an error is returned. If there is no media in the device, + the function returns EFI_NO_MEDIA. + + @param[in] PeiServices General-purpose services that are available to + every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, PPIs that + want to talk to a single device must specify the device + index that was assigned during the enumeration process. + This index is a number from one to NumberBlockDevices. + @param[in] StartLBA The starting logical block address (LBA) to read from + on the device + @param[in] BufferSize The size of the Buffer in bytes. This number must be + a multiple of the intrinsic block size of the device. + @param[out] Buffer A pointer to the destination buffer for the data. + The caller is responsible for the ownership of the + buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting + to perform the read operation. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not + valid, or the buffer is not properly aligned. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of + the intrinsic block size of the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_READ_BLOCKS)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This, + IN UINTN DeviceIndex, + IN EFI_PEI_LBA StartLBA, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/// +/// EFI_PEI_RECOVERY_BLOCK_IO_PPI provides the services that are required +/// to access a block I/O device during PEI recovery boot mode. +/// +struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI { + /// + /// Gets the number of block I/O devices that the specific block driver manages. + /// + EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices; + + /// + /// Gets the specified media information. + /// + EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo; + + /// + /// Reads the requested number of blocks from the specified block device. + /// + EFI_PEI_READ_BLOCKS ReadBlocks; +}; + +extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo2.h new file mode 100644 index 0000000000..992429488d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BlockIo2.h @@ -0,0 +1,217 @@ +/** @file + Provides the services required to access a block I/O 2 device during PEI recovery + boot mode. + +Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.4 Volume 1: + Pre-EFI Initialization Core Interface. + +**/ + +#ifndef _PEI_BLOCK_IO2_H_ +#define _PEI_BLOCK_IO2_H_ + +#include +#include + +/// +/// Global ID for EFI_PEI_RECOVERY_BLOCK_IO2_PPI +/// +#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_GUID \ + { \ + 0x26cc0fad, 0xbeb3, 0x478a, { 0x91, 0xb2, 0xc, 0x18, 0x8f, 0x72, 0x61, 0x98 } \ + } + +/// +/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI. +/// +typedef struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI EFI_PEI_RECOVERY_BLOCK_IO2_PPI; + +#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION 0x00010000 + +typedef struct { + /// + /// A type of interface that the device being referenced by DeviceIndex is + /// attached to. This field re-uses Messaging Device Path Node sub-type values + /// as defined by Section 9.3.5 Messaging Device Path of UEFI Specification. + /// When more than one sub-type is associated with the interface, sub-type with + /// the smallest number must be used. + /// + UINT8 InterfaceType; + /// + /// A flag that indicates if media is removable. + /// + BOOLEAN RemovableMedia; + /// + /// A flag that indicates if media is present. This flag is always set for + /// non-removable media devices. + /// + BOOLEAN MediaPresent; + /// + /// A flag that indicates if media is read-only. + /// + BOOLEAN ReadOnly; + /// + /// The size of a logical block in bytes. + /// + UINT32 BlockSize; + /// + /// The last logical block that the device supports. + /// + EFI_PEI_LBA LastBlock; +} EFI_PEI_BLOCK_IO2_MEDIA; + +/** + Gets the count of block I/O devices that one specific block driver detects. + + This function is used for getting the count of block I/O devices that one + specific block driver detects. To the PEI ATAPI driver, it returns the number + of all the detected ATAPI devices it detects during the enumeration process. + To the PEI legacy floppy driver, it returns the number of all the legacy + devices it finds during its enumeration process. If no device is detected, + then the function will return zero. + + @param[in] PeiServices General-purpose services that are available + to every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI + instance. + @param[out] NumberBlockDevices The number of block I/O devices discovered. + + @retval EFI_SUCCESS The operation performed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_NUMBER_BLOCK_DEVICES2)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This, + OUT UINTN *NumberBlockDevices + ); + +/** + Gets a block device's media information. + + This function will provide the caller with the specified block device's media + information. If the media changes, calling this function will update the media + information accordingly. + + @param[in] PeiServices General-purpose services that are available to every + PEIM + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, the PPIs that + want to talk to a single device must specify the + device index that was assigned during the enumeration + process. This index is a number from one to + NumberBlockDevices. + @param[out] MediaInfo The media information of the specified block media. + The caller is responsible for the ownership of this + data structure. + + @par Note: + The MediaInfo structure describes an enumeration of possible block device + types. This enumeration exists because no device paths are actually passed + across interfaces that describe the type or class of hardware that is publishing + the block I/O interface. This enumeration will allow for policy decisions + in the Recovery PEIM, such as "Try to recover from legacy floppy first, + LS-120 second, CD-ROM third." If there are multiple partitions abstracted + by a given device type, they should be reported in ascending order; this + order also applies to nested partitions, such as legacy MBR, where the + outermost partitions would have precedence in the reporting order. The + same logic applies to systems such as IDE that have precedence relationships + like "Master/Slave" or "Primary/Secondary". The master device should be + reported first, the slave second. + + @retval EFI_SUCCESS Media information about the specified block device + was obtained successfully. + @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This, + IN UINTN DeviceIndex, + OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo + ); + +/** + Reads the requested number of blocks from the specified block device. + + The function reads the requested number of blocks from the device. All the + blocks are read, or an error is returned. If there is no media in the device, + the function returns EFI_NO_MEDIA. + + @param[in] PeiServices General-purpose services that are available to + every PEIM. + @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance. + @param[in] DeviceIndex Specifies the block device to which the function wants + to talk. Because the driver that implements Block I/O + PPIs will manage multiple block devices, PPIs that + want to talk to a single device must specify the device + index that was assigned during the enumeration process. + This index is a number from one to NumberBlockDevices. + @param[in] StartLBA The starting logical block address (LBA) to read from + on the device + @param[in] BufferSize The size of the Buffer in bytes. This number must be + a multiple of the intrinsic block size of the device. + @param[out] Buffer A pointer to the destination buffer for the data. + The caller is responsible for the ownership of the + buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting + to perform the read operation. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not + valid, or the buffer is not properly aligned. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of + the intrinsic block size of the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_READ_BLOCKS2)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This, + IN UINTN DeviceIndex, + IN EFI_PEI_LBA StartLBA, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/// +/// EFI_PEI_RECOVERY_BLOCK_IO_PPI provides the services that are required +/// to access a block I/O device during PEI recovery boot mode. +/// +struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI { + /// + /// The revision to which the interface adheres. + /// All future revisions must be backwards compatible. + /// + UINT64 Revision; + /// + /// Gets the number of block I/O devices that the specific block driver manages. + /// + EFI_PEI_GET_NUMBER_BLOCK_DEVICES2 GetNumberOfBlockDevices; + + /// + /// Gets the specified media information. + /// + EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2 GetBlockDeviceMediaInfo; + + /// + /// Reads the requested number of blocks from the specified block device. + /// + EFI_PEI_READ_BLOCKS2 ReadBlocks; +}; + +extern EFI_GUID gEfiPeiVirtualBlockIo2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BootInRecoveryMode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BootInRecoveryMode.h new file mode 100644 index 0000000000..11b463e8ab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/BootInRecoveryMode.h @@ -0,0 +1,24 @@ +/** @file + This PPI is installed by the platform PEIM to designate that a recovery boot + is in progress. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __BOOT_IN_RECOVERY_MODE_PPI_H__ +#define __BOOT_IN_RECOVERY_MODE_PPI_H__ + +#define EFI_PEI_BOOT_IN_RECOVERY_MODE_PPI \ + { \ + 0x17ee496a, 0xd8e4, 0x4b9a, {0x94, 0xd1, 0xce, 0x82, 0x72, 0x30, 0x8, 0x50 } \ + } + + +extern EFI_GUID gEfiPeiBootInRecoveryModePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Capsule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Capsule.h new file mode 100644 index 0000000000..34b3e9bb19 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Capsule.h @@ -0,0 +1,130 @@ +/** @file + Defines the APIs that enable PEI services to work with + the underlying capsule capabilities of the platform. + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.4. + +**/ + +#ifndef _PEI_CAPSULE_PPI_H_ +#define _PEI_CAPSULE_PPI_H_ + +/// +/// Global ID for the EFI_PEI_CAPSULE_PPI. +/// +#define EFI_PEI_CAPSULE_PPI_GUID \ + { \ + 0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d } \ + } + +/// +/// Forward declaration for the EFI_PEI_CAPSULE_PPI. +/// +typedef struct _EFI_PEI_CAPSULE_PPI EFI_PEI_CAPSULE_PPI; + +/// +/// Keep name backwards compatible before PI Version 1.4 +/// +typedef struct _EFI_PEI_CAPSULE_PPI PEI_CAPSULE_PPI; + +/** + Upon determining that there is a capsule to operate on, this service + will use a series of EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine + the current location of the various capsule fragments and coalesce them + into a contiguous region of system memory. + + @param[in] PeiServices Pointer to the PEI Services Table. + @param[out] MemoryBase Pointer to the base of a block of memory into which the buffers will be coalesced. + On output, this variable will hold the base address + of a coalesced capsule. + @param[out] MemorySize Size of the memory region pointed to by MemoryBase. + On output, this variable will contain the size of the + coalesced capsule. + + @retval EFI_NOT_FOUND If: boot mode could not be determined, or the + boot mode is not flash-update, or the capsule descriptors were not found. + @retval EFI_BUFFER_TOO_SMALL The capsule could not be coalesced in the provided memory region. + @retval EFI_SUCCESS There was no capsule, or the capsule was processed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_CAPSULE_COALESCE)( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID **MemoryBase, + IN OUT UINTN *MemSize + ); + +/** + Determine if a capsule needs to be processed. + The means by which the presence of a capsule is determined is platform + specific. For example, an implementation could be driven by the presence + of a Capsule EFI Variable containing a list of EFI_CAPSULE_BLOCK_DESCRIPTOR + entries. If present, return EFI_SUCCESS, otherwise return EFI_NOT_FOUND. + + @param[in] PeiServices Pointer to the PEI Services Table. + + @retval EFI_SUCCESS If a capsule is available. + @retval EFI_NOT_FOUND No capsule detected. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE)( + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + The Capsule PPI service that gets called after memory is available. The + capsule coalesce function, which must be called first, returns a base + address and size. Once the memory init PEIM has discovered memory, + it should call this function and pass in the base address and size + returned by the Coalesce() function. Then this function can create a + capsule HOB and return. + + @par Notes: + This function assumes it will not be called until the + actual capsule update. + + @param[in] PeiServices Pointer to the PEI Services Table. + @param[in] CapsuleBase Address returned by the capsule coalesce function. + @param[in] CapsuleSize Value returned by the capsule coalesce function. + + @retval EFI_VOLUME_CORRUPTED CapsuleBase does not appear to point to a + coalesced capsule. + @retval EFI_SUCCESS Capsule HOB was created successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_CAPSULE_CREATE_STATE)( + IN EFI_PEI_SERVICES **PeiServices, + IN VOID *CapsuleBase, + IN UINTN CapsuleSize + ); + +/// +/// This PPI provides several services in PEI to work with the underlying +/// capsule capabilities of the platform. These services include the ability +/// for PEI to coalesce a capsule from a scattered set of memory locations +/// into a contiguous space in memory, detect if a capsule is present for +/// processing, and once memory is available, create a HOB for the capsule. +/// +struct _EFI_PEI_CAPSULE_PPI { + EFI_PEI_CAPSULE_COALESCE Coalesce; + EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate; + EFI_PEI_CAPSULE_CREATE_STATE CreateState; +}; + +/// +/// Keep name backwards compatible before PI Version 1.4 +/// +extern EFI_GUID gPeiCapsulePpiGuid; + +extern EFI_GUID gEfiPeiCapsulePpiGuid; + +#endif // #ifndef _PEI_CAPSULE_PPI_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/CpuIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/CpuIo.h new file mode 100644 index 0000000000..fe700d38ce --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/CpuIo.h @@ -0,0 +1,422 @@ +/** @file + This PPI provides a set of memory and I/O-based services. + The perspective of the services is that of the processor, not the bus or system. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_CPUIO_PPI_H__ +#define __PEI_CPUIO_PPI_H__ + +#define EFI_PEI_CPU_IO_PPI_INSTALLED_GUID \ + { 0xe6af1f7b, 0xfc3f, 0x46da, {0xa8, 0x28, 0xa3, 0xb4, 0x57, 0xa4, 0x42, 0x82 } } + +typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI; + +/// +/// EFI_PEI_CPU_IO_PPI_WIDTH. +/// +typedef enum { + EfiPeiCpuIoWidthUint8, + EfiPeiCpuIoWidthUint16, + EfiPeiCpuIoWidthUint32, + EfiPeiCpuIoWidthUint64, + EfiPeiCpuIoWidthFifoUint8, + EfiPeiCpuIoWidthFifoUint16, + EfiPeiCpuIoWidthFifoUint32, + EfiPeiCpuIoWidthFifoUint64, + EfiPeiCpuIoWidthFillUint8, + EfiPeiCpuIoWidthFillUint16, + EfiPeiCpuIoWidthFillUint32, + EfiPeiCpuIoWidthFillUint64, + EfiPeiCpuIoWidthMaximum +} EFI_PEI_CPU_IO_PPI_WIDTH; + +/** + Memory-based access services and I/O-based access services. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Width The width of the access. Enumerated in bytes. + @param[in] Address The physical address of the access. + @param[in] Count The number of accesses to perform. + @param[in, out] Buffer A pointer to the buffer of data. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_YET_AVAILABLE The service has not been installed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_MEM)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN EFI_PEI_CPU_IO_PPI_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +/// +/// EFI_PEI_CPU_IO_PPI_ACCESS +/// +typedef struct { + /// + /// This service provides the various modalities of memory and I/O read. + /// + EFI_PEI_CPU_IO_PPI_IO_MEM Read; + /// + /// This service provides the various modalities of memory and I/O write. + /// + EFI_PEI_CPU_IO_PPI_IO_MEM Write; +} EFI_PEI_CPU_IO_PPI_ACCESS; + +/** + 8-bit I/O read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return An 8-bit value returned from the I/O space. + +**/ +typedef +UINT8 +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ8)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 16-bit I/O read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 16-bit value returned from the I/O space. + +**/ +typedef +UINT16 +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ16)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 32-bit I/O read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 32-bit value returned from the I/O space. + +**/ +typedef +UINT32 +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ32)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 64-bit I/O read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 64-bit value returned from the I/O space. + +**/ +typedef +UINT64 +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_READ64)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 8-bit I/O write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE8)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT8 Data + ); + +/** + 16-bit I/O write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE16)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT16 Data + ); + +/** + 32-bit I/O write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE32)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT32 Data + ); + +/** + 64-bit I/O write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_IO_WRITE64)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT64 Data + ); + +/** + 8-bit memory read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return An 8-bit value returned from the memory space. + +**/ +typedef +UINT8 +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ8)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 16-bit memory read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 16-bit value returned from the memory space. + +**/ +typedef +UINT16 +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ16)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 32-bit memory read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 32-bit value returned from the memory space. + +**/ +typedef +UINT32 +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ32)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 64-bit memory read operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + + @return A 64-bit value returned from the memory space. + +**/ +typedef +UINT64 +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_READ64)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address + ); + +/** + 8-bit memory write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE8)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT8 Data + ); + +/** + 16-bit memory write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE16)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT16 Data + ); + +/** + 32-bit memory write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE32)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT32 Data + ); + +/** + 64-bit memory write operations. + + @param[in] PeiServices An indirect pointer to the PEI Services Table published + by the PEI Foundation. + @param[in] This The pointer to local data for the interface. + @param[in] Address The physical address of the access. + @param[in] Data The data to write. + +**/ +typedef +VOID +(EFIAPI *EFI_PEI_CPU_IO_PPI_MEM_WRITE64)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_CPU_IO_PPI *This, + IN UINT64 Address, + IN UINT64 Data + ); + +/// +/// EFI_PEI_CPU_IO_PPI provides a set of memory and I/O-based services. +/// The perspective of the services is that of the processor, not that of the +/// bus or system. +/// +struct _EFI_PEI_CPU_IO_PPI { + /// + /// Collection of memory-access services. + /// + EFI_PEI_CPU_IO_PPI_ACCESS Mem; + /// + /// Collection of I/O-access services. + /// + EFI_PEI_CPU_IO_PPI_ACCESS Io; + + EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8; + EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16; + EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32; + EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64; + + EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8; + EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16; + EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32; + EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64; + + EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8; + EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16; + EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32; + EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64; + + EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8; + EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16; + EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32; + EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64; +}; + +extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Decompress.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Decompress.h new file mode 100644 index 0000000000..adbe11f57e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Decompress.h @@ -0,0 +1,68 @@ +/** @file + Provides decompression services to the PEI Foundation. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __DECOMPRESS_PPI_H__ +#define __DECOMPRESS_PPI_H__ + +#define EFI_PEI_DECOMPRESS_PPI_GUID \ + { 0x1a36e4e7, 0xfab6, 0x476a, { 0x8e, 0x75, 0x69, 0x5a, 0x5, 0x76, 0xfd, 0xd7 } } + +typedef struct _EFI_PEI_DECOMPRESS_PPI EFI_PEI_DECOMPRESS_PPI; + +/** + Decompress a single compression section in a firmware file. + + Decompresses the data in a compressed section and returns it + as a series of standard PI Firmware File Sections. The + required memory is allocated from permanent memory. + + @param This Points to this instance of the + EFI_PEI_DECOMPRESS_PEI PPI. + @param InputSection Points to the compressed section. + @param OutputBuffer Holds the returned pointer to the + decompressed sections. + @param OutputSize Holds the returned size of the decompress + section streams. + + @retval EFI_SUCCESS The section was decompressed + successfully. OutputBuffer contains the + resulting data and OutputSize contains + the resulting size. + @retval EFI_OUT_OF_RESOURCES Unable to allocate sufficient + memory to hold the decompressed data. + @retval EFI_UNSUPPORTED The compression type specified + in the compression header is unsupported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_DECOMPRESS_DECOMPRESS)( + IN CONST EFI_PEI_DECOMPRESS_PPI *This, + IN CONST EFI_COMPRESSION_SECTION *InputSection, + OUT VOID **OutputBuffer, + OUT UINTN *OutputSize +); + + +/// +/// This PPI's single member function decompresses a compression +/// encapsulated section. It is used by the PEI Foundation to +/// process sectioned files. Prior to the installation of this PPI, +/// compression sections will be ignored. +/// +struct _EFI_PEI_DECOMPRESS_PPI { + EFI_PEI_DECOMPRESS_DECOMPRESS Decompress; +}; + + +extern EFI_GUID gEfiPeiDecompressPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DelayedDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DelayedDispatch.h new file mode 100644 index 0000000000..a51da027b8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DelayedDispatch.h @@ -0,0 +1,85 @@ +/** @file + EFI Delayed Dispatch PPI as defined in the PI 1.7 Specification + + Provide timed event service in PEI + + Copyright (c) 2020, American Megatrends International LLC. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __DELAYED_DISPATCH_PPI_H__ +#define __DELAYED_DISPATCH_PPI_H__ + +/// +/// Global ID for EFI_DELAYED_DISPATCH_PPI_GUID +/// +#define EFI_DELAYED_DISPATCH_PPI_GUID \ + { \ + 0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6} } \ + } + + +/** + Delayed Dispatch function. This routine is called sometime after the required + delay. Upon return, if NewDelay is 0, the function is unregistered. If NewDelay + is not zero, this routine will be called again after the new delay period. + + @param[in,out] Context Pointer to Context. Can be updated by routine. + @param[out] NewDelay The new delay in us. Leave at 0 to unregister callback. + +**/ + +typedef +VOID +(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION) ( + IN OUT UINT64 *Context, + OUT UINT32 *NewDelay + ); + + +/// +/// The forward declaration for EFI_DELAYED_DISPATCH_PPI +/// + +typedef struct _EFI_DELAYED_DISPATCH_PPI EFI_DELAYED_DISPATCH_PPI; + + +/** +Register a callback to be called after a minimum delay has occurred. + +This service is the single member function of the EFI_DELAYED_DISPATCH_PPI + + @param This Pointer to the EFI_DELAYED_DISPATCH_PPI instance + @param Function Function to call back + @param Context Context data + @param Delay Delay interval + + @retval EFI_SUCCESS Function successfully loaded + @retval EFI_INVALID_PARAMETER One of the Arguments is not supported + @retval EFI_OUT_OF_RESOURCES No more entries + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DELAYED_DISPATCH_REGISTER)( + IN EFI_DELAYED_DISPATCH_PPI *This, + IN EFI_DELAYED_DISPATCH_FUNCTION Function, + IN UINT64 Context, + OUT UINT32 Delay + ); + + +/// +/// This PPI is a pointer to the Delayed Dispatch Service. +/// This service will be published by the Pei Foundation. The PEI Foundation +/// will use this service to relaunch a known function that requests a delayed +/// execution. +/// +struct _EFI_DELAYED_DISPATCH_PPI { + EFI_DELAYED_DISPATCH_REGISTER Register; +}; + + +extern EFI_GUID gEfiPeiDelayedDispatchPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DeviceRecoveryModule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DeviceRecoveryModule.h new file mode 100644 index 0000000000..24fcc20d66 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DeviceRecoveryModule.h @@ -0,0 +1,138 @@ +/** @file + This file declares the Device Recovery Module PPI. + + The interface of this PPI does the following: + - Reports the number of recovery DXE capsules that exist on the associated device(s) + - Finds the requested firmware binary capsule + - Loads that capsule into memory + + A device can be either a group of devices, such as a block device, or an individual device. + The module determines the internal search order, with capsule number 1 as the highest load + priority and number N as the lowest priority. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1: + Pre-EFI Initialization Core Interface + +**/ + +#ifndef _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ +#define _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ + +#define EFI_PEI_DEVICE_RECOVERY_MODULE_PPI_GUID \ + { \ + 0x0DE2CE25, 0x446A, 0x45a7, {0xBF, 0xC9, 0x37, 0xDA, 0x26, 0x34, 0x4B, 0x37 } \ + } + +typedef struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI; + +/** + Returns the number of DXE capsules residing on the device. + + This function searches for DXE capsules from the associated device and returns + the number and maximum size in bytes of the capsules discovered. Entry 1 is + assumed to be the highest load priority and entry N is assumed to be the lowest + priority. + + @param[in] PeiServices General-purpose services that are available + to every PEIM + @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI + instance. + @param[out] NumberRecoveryCapsules Pointer to a caller-allocated UINTN. On + output, *NumberRecoveryCapsules contains + the number of recovery capsule images + available for retrieval from this PEIM + instance. + + @retval EFI_SUCCESS One or more capsules were discovered. + @retval EFI_DEVICE_ERROR A device error occurred. + @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This, + OUT UINTN *NumberRecoveryCapsules + ); + +/** + Returns the size and type of the requested recovery capsule. + + This function gets the size and type of the capsule specified by CapsuleInstance. + + @param[in] PeiServices General-purpose services that are available to every PEIM + @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI + instance. + @param[in] CapsuleInstance Specifies for which capsule instance to retrieve + the information. This parameter must be between + one and the value returned by GetNumberRecoveryCapsules() + in NumberRecoveryCapsules. + @param[out] Size A pointer to a caller-allocated UINTN in which + the size of the requested recovery module is + returned. + @param[out] CapsuleType A pointer to a caller-allocated EFI_GUID in which + the type of the requested recovery capsule is + returned. The semantic meaning of the value + returned is defined by the implementation. + + @retval EFI_SUCCESS One or more capsules were discovered. + @retval EFI_DEVICE_ERROR A device error occurred. + @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This, + IN UINTN CapsuleInstance, + OUT UINTN *Size, + OUT EFI_GUID *CapsuleType + ); + +/** + Loads a DXE capsule from some media into memory. + + This function, by whatever mechanism, retrieves a DXE capsule from some device + and loads it into memory. Note that the published interface is device neutral. + + @param[in] PeiServices General-purpose services that are available + to every PEIM + @param[in] This Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI + instance. + @param[in] CapsuleInstance Specifies which capsule instance to retrieve. + @param[out] Buffer Specifies a caller-allocated buffer in which + the requested recovery capsule will be returned. + + @retval EFI_SUCCESS The capsule was loaded correctly. + @retval EFI_DEVICE_ERROR A device error occurred. + @retval EFI_NOT_FOUND A requested recovery DXE capsule cannot be found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *This, + IN UINTN CapsuleInstance, + OUT VOID *Buffer + ); + +/// +/// Presents a standard interface to EFI_PEI_DEVICE_RECOVERY_MODULE_PPI, +/// regardless of the underlying device(s). +/// +struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI { + EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules; ///< Returns the number of DXE capsules residing on the device. + EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo; ///< Returns the size and type of the requested recovery capsule. + EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE capsule from some media into memory. +}; + +extern EFI_GUID gEfiPeiDeviceRecoveryModulePpiGuid; + +#endif /* _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ */ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DxeIpl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DxeIpl.h new file mode 100644 index 0000000000..512a0f6324 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/DxeIpl.h @@ -0,0 +1,66 @@ +/** @file + This file declares DXE Initial Program Load PPI. + When the PEI core is done it calls the DXE IPL PPI to load the DXE Foundation. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __DXE_IPL_H__ +#define __DXE_IPL_H__ + +#define EFI_DXE_IPL_PPI_GUID \ + { \ + 0xae8ce5d, 0xe448, 0x4437, {0xa8, 0xd7, 0xeb, 0xf5, 0xf1, 0x94, 0xf7, 0x31 } \ + } + +typedef struct _EFI_DXE_IPL_PPI EFI_DXE_IPL_PPI; + +/** + The architectural PPI that the PEI Foundation invokes when + there are no additional PEIMs to invoke. + + This function is invoked by the PEI Foundation. + The PEI Foundation will invoke this service when there are + no additional PEIMs to invoke in the system. + If this PPI does not exist, it is an error condition and + an ill-formed firmware set. The DXE IPL PPI should never + return after having been invoked by the PEI Foundation. + The DXE IPL PPI can do many things internally, including the following: + - Invoke the DXE entry point from a firmware volume + - Invoke the recovery processing modules + - Invoke the S3 resume modules + + @param This Pointer to the DXE IPL PPI instance + @param PeiServices Pointer to the PEI Services Table. + @param HobList Pointer to the list of Hand-Off Block (HOB) entries. + + @retval EFI_SUCCESS Upon this return code, the PEI Foundation should enter + some exception handling.Under normal circumstances, + the DXE IPL PPI should not return. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DXE_IPL_ENTRY)( + IN CONST EFI_DXE_IPL_PPI *This, + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_HOB_POINTERS HobList + ); + +/// +/// Final service to be invoked by the PEI Foundation. +/// The DXE IPL PPI is responsible for locating and loading the DXE Foundation. +/// The DXE IPL PPI may use PEI services to locate and load the DXE Foundation. +/// +struct _EFI_DXE_IPL_PPI { + EFI_DXE_IPL_ENTRY Entry; +}; + +extern EFI_GUID gEfiDxeIplPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/EndOfPeiPhase.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/EndOfPeiPhase.h new file mode 100644 index 0000000000..99b4cbee76 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/EndOfPeiPhase.h @@ -0,0 +1,25 @@ +/** @file + This PPI will be installed at the end of PEI for all boot paths, including + normal, recovery, and S3. It allows for PEIMs to possibly quiesce hardware, + build handoff information for the next phase of execution, + or provide some terminal processing behavior. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __END_OF_PEI_PHASE_PPI_H__ +#define __END_OF_PEI_PHASE_PPI_H__ + +#define EFI_PEI_END_OF_PEI_PHASE_PPI_GUID \ + { \ + 0x605EA650, 0xC65C, 0x42e1, {0xBA, 0x80, 0x91, 0xA5, 0x2A, 0xB6, 0x18, 0xC6 } \ + } + +extern EFI_GUID gEfiEndOfPeiSignalPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolume.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolume.h new file mode 100644 index 0000000000..296686589e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolume.h @@ -0,0 +1,288 @@ +/** @file + This file provides functions for accessing a memory-mapped firmware volume of a specific format. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is from PI Version 1.0 errata. + +**/ + +#ifndef __FIRMWARE_VOLUME_PPI_H__ +#define __FIRMWARE_VOLUME_PPI_H__ + +/// +/// The GUID for this PPI is the same as the firmware volume format GUID. +/// The FV format can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined +/// format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is the PI Firmware Volume format. +/// +typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI EFI_PEI_FIRMWARE_VOLUME_PPI; + + +/** + Process a firmware volume and create a volume handle. + + Create a volume handle from the information in the buffer. For + memory-mapped firmware volumes, Buffer and BufferSize refer to + the start of the firmware volume and the firmware volume size. + For non memory-mapped firmware volumes, this points to a + buffer which contains the necessary information for creating + the firmware volume handle. Normally, these values are derived + from the EFI_FIRMWARE_VOLUME_INFO_PPI. + + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param Buffer Points to the start of the buffer. + @param BufferSize Size of the buffer. + @param FvHandle Points to the returned firmware volume + handle. The firmware volume handle must + be unique within the system. + + @retval EFI_SUCCESS Firmware volume handle created. + @retval EFI_VOLUME_CORRUPTED Volume was corrupt. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_PROCESS_FV)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN VOID *Buffer, + IN UINTN BufferSize, + OUT EFI_PEI_FV_HANDLE *FvHandle +); + +/** + Finds the next file of the specified type. + + This service enables PEI modules to discover additional firmware files. + The FileHandle must be unique within the system. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param SearchType A filter to find only files of this type. Type + EFI_FV_FILETYPE_ALL causes no filtering to be + done. + @param FvHandle Handle of firmware volume in which to + search. + @param FileHandle Points to the current handle from which to + begin searching or NULL to start at the + beginning of the firmware volume. Updated + upon return to reflect the file found. + + @retval EFI_SUCCESS The file was found. + @retval EFI_NOT_FOUND The file was not found. FileHandle contains NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_FIND_FILE_TYPE)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_FV_FILETYPE SearchType, + IN EFI_PEI_FV_HANDLE FvHandle, + IN OUT EFI_PEI_FILE_HANDLE *FileHandle +); + + +/** + Find a file within a volume by its name. + + This service searches for files with a specific name, within + either the specified firmware volume or all firmware volumes. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param FileName A pointer to the name of the file to find + within the firmware volume. + @param FvHandle Upon entry, the pointer to the firmware + volume to search or NULL if all firmware + volumes should be searched. Upon exit, the + actual firmware volume in which the file was + found. + @param FileHandle Upon exit, points to the found file's + handle or NULL if it could not be found. + + @retval EFI_SUCCESS File was found. + @retval EFI_NOT_FOUND File was not found. + @retval EFI_INVALID_PARAMETER FvHandle or FileHandle or + FileName was NULL. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_FIND_FILE_NAME)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN CONST EFI_GUID *FileName, + IN EFI_PEI_FV_HANDLE *FvHandle, + OUT EFI_PEI_FILE_HANDLE *FileHandle +); + + +/** + Returns information about a specific file. + + This function returns information about a specific + file, including its file name, type, attributes, starting + address and size. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param FileHandle Handle of the file. + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information returned. + @retval EFI_INVALID_PARAMETER If FileHandle does not + represent a valid file. + @retval EFI_INVALID_PARAMETER If FileInfo is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_GET_FILE_INFO)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO *FileInfo +); + +/** + Returns information about a specific file. + + This function returns information about a specific + file, including its file name, type, attributes, starting + address, size and authentication status. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param FileHandle Handle of the file. + @param FileInfo Upon exit, points to the file's + information. + + @retval EFI_SUCCESS File information returned. + @retval EFI_INVALID_PARAMETER If FileHandle does not + represent a valid file. + @retval EFI_INVALID_PARAMETER If FileInfo is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_GET_FILE_INFO2)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_FV_FILE_INFO2 *FileInfo +); + +/** + This function returns information about the firmware volume. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param FvHandle Handle to the firmware handle. + @param VolumeInfo Points to the returned firmware volume + information. + + @retval EFI_SUCCESS Information returned successfully. + @retval EFI_INVALID_PARAMETER FvHandle does not indicate a valid + firmware volume or VolumeInfo is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_GET_INFO)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_PEI_FV_HANDLE FvHandle, + OUT EFI_FV_INFO *VolumeInfo +); + +/** + Find the next matching section in the firmware file. + + This service enables PEI modules to discover sections + of a given type within a valid file. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param SearchType A filter to find only sections of this + type. + @param FileHandle Handle of firmware file in which to + search. + @param SectionData Updated upon return to point to the + section found. + + @retval EFI_SUCCESS Section was found. + @retval EFI_NOT_FOUND Section of the specified type was not + found. SectionData contains NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_FIND_SECTION)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_SECTION_TYPE SearchType, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData +); + +/** + Find the next matching section in the firmware file. + + This service enables PEI modules to discover sections + of a given instance and type within a valid file. + + @param This Points to this instance of the + EFI_PEI_FIRMWARE_VOLUME_PPI. + @param SearchType A filter to find only sections of this + type. + @param SearchInstance A filter to find the specific instance + of sections. + @param FileHandle Handle of firmware file in which to + search. + @param SectionData Updated upon return to point to the + section found. + @param AuthenticationStatus Updated upon return to point to the + authentication status for this section. + + @retval EFI_SUCCESS Section was found. + @retval EFI_NOT_FOUND Section of the specified type was not + found. SectionData contains NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_FV_FIND_SECTION2)( + IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This, + IN EFI_SECTION_TYPE SearchType, + IN UINTN SearchInstance, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT VOID **SectionData, + OUT UINT32 *AuthenticationStatus +); + +#define EFI_PEI_FIRMWARE_VOLUME_PPI_SIGNATURE SIGNATURE_32 ('P', 'F', 'V', 'P') +#define EFI_PEI_FIRMWARE_VOLUME_PPI_REVISION 0x00010030 + +/// +/// This PPI provides functions for accessing a memory-mapped firmware volume of a specific format. +/// +struct _EFI_PEI_FIRMWARE_VOLUME_PPI { + EFI_PEI_FV_PROCESS_FV ProcessVolume; + EFI_PEI_FV_FIND_FILE_TYPE FindFileByType; + EFI_PEI_FV_FIND_FILE_NAME FindFileByName; + EFI_PEI_FV_GET_FILE_INFO GetFileInfo; + EFI_PEI_FV_GET_INFO GetVolumeInfo; + EFI_PEI_FV_FIND_SECTION FindSectionByType; + EFI_PEI_FV_GET_FILE_INFO2 GetFileInfo2; + EFI_PEI_FV_FIND_SECTION2 FindSectionByType2; + /// + /// Signature is used to keep backward-compatibility, set to {'P','F','V','P'}. + /// + UINT32 Signature; + /// + /// Revision for further extension. + /// + UINT32 Revision; +}; + +extern EFI_GUID gEfiPeiFirmwareVolumePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo.h new file mode 100644 index 0000000000..e10b9c4afc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo.h @@ -0,0 +1,62 @@ +/** @file + This file provides location and format of a firmware volume. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO_H__ +#define __EFI_PEI_FIRMWARE_VOLUME_INFO_H__ + + + +#define EFI_PEI_FIRMWARE_VOLUME_INFO_PPI_GUID \ +{ 0x49edb1c1, 0xbf21, 0x4761, { 0xbb, 0x12, 0xeb, 0x0, 0x31, 0xaa, 0xbb, 0x39 } } + +typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI EFI_PEI_FIRMWARE_VOLUME_INFO_PPI; + +/// +/// This PPI describes the location and format of a firmware volume. +/// The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for +/// a user-defined format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is +/// the PI Firmware Volume format. +/// +struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI { + /// + /// Unique identifier of the format of the memory-mapped firmware volume. + /// + EFI_GUID FvFormat; + /// + /// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process + /// the volume. The format of this buffer is specific to the FvFormat. + /// For memory-mapped firmware volumes, this typically points to the first byte + /// of the firmware volume. + /// + VOID *FvInfo; + /// + /// Size of the data provided by FvInfo. For memory-mapped firmware volumes, + /// this is typically the size of the firmware volume. + /// + UINT32 FvInfoSize; + /// + /// If the firmware volume originally came from a firmware file, then these + /// point to the parent firmware volume name and firmware volume file. + /// If it did not originally come from a firmware file, these should be NULL. + /// + EFI_GUID *ParentFvName; + /// + /// If the firmware volume originally came from a firmware file, then these + /// point to the parent firmware volume name and firmware volume file. + /// If it did not originally come from a firmware file, these should be NULL. + /// + EFI_GUID *ParentFileName; +}; + +extern EFI_GUID gEfiPeiFirmwareVolumeInfoPpiGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h new file mode 100644 index 0000000000..f7b9cde994 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h @@ -0,0 +1,66 @@ +/** @file + This file provides location, format and authentication status of a firmware volume. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.3 errata. + +**/ + +#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__ +#define __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__ + + + +#define EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI_GUID \ +{ 0xea7ca24b, 0xded5, 0x4dad, { 0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 } } + +typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI; + +/// +/// This PPI describes the location and format of a firmware volume. +/// The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for +/// a user-defined format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is +/// the PI Firmware Volume format. +/// +struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI { + /// + /// Unique identifier of the format of the memory-mapped firmware volume. + /// + EFI_GUID FvFormat; + /// + /// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process + /// the volume. The format of this buffer is specific to the FvFormat. + /// For memory-mapped firmware volumes, this typically points to the first byte + /// of the firmware volume. + /// + VOID *FvInfo; + /// + /// Size of the data provided by FvInfo. For memory-mapped firmware volumes, + /// this is typically the size of the firmware volume. + /// + UINT32 FvInfoSize; + /// + /// If the firmware volume originally came from a firmware file, then these + /// point to the parent firmware volume name and firmware volume file. + /// If it did not originally come from a firmware file, these should be NULL. + /// + EFI_GUID *ParentFvName; + /// + /// If the firmware volume originally came from a firmware file, then these + /// point to the parent firmware volume name and firmware volume file. + /// If it did not originally come from a firmware file, these should be NULL. + /// + EFI_GUID *ParentFileName; + /// + /// Authentication Status. + /// + UINT32 AuthenticationStatus; +}; + +extern EFI_GUID gEfiPeiFirmwareVolumeInfo2PpiGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Graphics.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Graphics.h new file mode 100644 index 0000000000..d1fca7896b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Graphics.h @@ -0,0 +1,79 @@ +/** @file + This file declares Graphics PPI. + This PPI is the main interface exposed by the Graphics PEIM to be used by the + other firmware modules. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.4. + +**/ + +#ifndef __PEI_GRAPHICS_PPI_H__ +#define __PEI_GRAPHICS_PPI_H__ + +#include + +#define EFI_PEI_GRAPHICS_PPI_GUID \ + { \ + 0x6ecd1463, 0x4a4a, 0x461b, { 0xaf, 0x5f, 0x5a, 0x33, 0xe3, 0xb2, 0x16, 0x2b } \ + } + +typedef struct _EFI_PEI_GRAPHICS_PPI EFI_PEI_GRAPHICS_PPI; + +/** + The GraphicsPpiInit initializes the graphics subsystem in phases. + + @param[in] GraphicsPolicyPtr GraphicsPolicyPtr points to a configuration data + block of policy settings required by Graphics PEIM. + + @retval EFI_SUCCESS The invocation was successful. + @retval EFI_INVALID_PARAMETER The phase parameter is not valid. + @retval EFI_NOT_ABORTED The stages was not called in the proper order. + @retval EFI_NOT_FOUND The PeiGraphicsPlatformPolicyPpi is not located. + @retval EFI_DEVICE_ERROR The initialization failed due to device error. + @retval EFI_NOT_READY The previous init stage is still in progress and not + ready for the current initialization phase yet. The + platform code should call this again sometime later. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GRAPHICS_INIT) ( + IN VOID *GraphicsPolicyPtr + ); + +/** + The GraphicsPpiGetMode returns the mode information supported by the Graphics PEI + Module. + + @param[in, out] Mode Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data. + + @retval EFI_SUCCESS Valid mode information was returned. + @retval EFI_INVALID_PARAMETER The Mode parameter is not valid. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video + mode. + @retval EFI_NOT_READY The Graphics Initialization is not competed and Mode + information is not yet available.The platform code + should call this again after the Graphics + initialization is done. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GRAPHICS_GET_MODE) ( + IN OUT EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode + ); + +/// +/// This PPI is the main interface exposed by the Graphics PEIM to be used by the other +/// firmware modules. +/// +struct _EFI_PEI_GRAPHICS_PPI { + EFI_PEI_GRAPHICS_INIT GraphicsPpiInit; + EFI_PEI_GRAPHICS_GET_MODE GraphicsPpiGetMode; +}; + +extern EFI_GUID gEfiPeiGraphicsPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/GuidedSectionExtraction.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/GuidedSectionExtraction.h new file mode 100644 index 0000000000..3ac6503833 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/GuidedSectionExtraction.h @@ -0,0 +1,98 @@ +/** @file + If a GUID-defined section is encountered when doing section extraction, + the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance + calls the appropriate instance of the GUIDed Section Extraction PPI + to extract the section stream contained therein. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __EFI_GUIDED_SECTION_EXTRACTION_PPI_H__ +#define __EFI_GUIDED_SECTION_EXTRACTION_PPI_H__ + +// +// Typically, protocol interface structures are identified +// by associating them with a GUID. Each instance of +// a protocol with a given GUID must have +// the same interface structure. While all instances of +// the GUIDed Section Extraction PPI must have +// the same interface structure, they do not all have +// te same GUID. The GUID that is associated with +// an instance of the GUIDed Section Extraction Protocol +// is used to correlate it with the GUIDed section type +// that it is intended to process. +// + + +typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI; + + +/** + Processes the input section and returns the data contained therein + along with the authentication status. + + The ExtractSection() function processes the input section and + returns a pointer to the section contents. If the section being + extracted does not require processing (if the section + GuidedSectionHeader.Attributes has the + EFI_GUIDED_SECTION_PROCESSING_REQUIRED field cleared), then + OutputBuffer is just updated to point to the start of the + section's contents. Otherwise, *Buffer must be allocated + from PEI permanent memory. + + @param This Indicates the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI + instance. + @param InputSection Buffer containing the input GUIDed section to be + processed. + @param OutputBuffer *OutputBuffer is allocated from PEI permanent memory + and contains the new section stream. + @param OutputSize A pointer to a caller-allocated UINTN in which + the size of *OutputBuffer allocation is stored. + If the function returns anything other than + EFI_SUCCESS, the value of *OutputSize is undefined. + @param AuthenticationStatus A pointer to a caller-allocated UINT32 that indicates + the authentication status of the output buffer. + If the input section's + GuidedSectionHeader.Attributes field has the + EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit as clear, + *AuthenticationStatus must return zero. These bits + reflect the status of the extraction operation. + If the function returns anything other than EFI_SUCCESS, + the value of *AuthenticationStatus is undefined. + + @retval EFI_SUCCESS The InputSection was successfully processed and the + section contents were returned. + @retval EFI_OUT_OF_RESOURCES The system has insufficient resources to process the request. + @retval EFI_INVALID_PARAMETER The GUID in InputSection does not match this instance of the + GUIDed Section Extraction PPI. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_EXTRACT_GUIDED_SECTION)( + IN CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI *This, + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + OUT UINTN *OutputSize, + OUT UINT32 *AuthenticationStatus +); + +/// +/// If a GUID-defined section is encountered when doing section extraction, +/// the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance +/// calls the appropriate instance of the GUIDed Section +/// Extraction PPI to extract the section stream contained +/// therein. +/// +struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI { + EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection; +}; + + + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/I2cMaster.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/I2cMaster.h new file mode 100644 index 0000000000..e6d14503ec --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/I2cMaster.h @@ -0,0 +1,102 @@ +/** @file + This PPI manipulates the I2C host controller to perform transactions as a master + on the I2C bus using the current state of any switches or multiplexers in the I2C bus. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.3. + +**/ + +#ifndef __I2C_MASTER_PPI_H__ +#define __I2C_MASTER_PPI_H__ + +#include + +#define EFI_PEI_I2C_MASTER_PPI_GUID \ + { 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, 0x51, 0xfc, 0x62, 0x80 }} + +typedef struct _EFI_PEI_I2C_MASTER_PPI EFI_PEI_I2C_MASTER_PPI; + +/** + Set the frequency for the I2C clock line. + + @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure. + @param BusClockHertz Pointer to the requested I2C bus clock frequency in Hertz. + Upon return this value contains the actual frequency + in use by the I2C controller. + + @retval EFI_SUCCESS The bus frequency was set successfully. + @retval EFI_INVALID_PARAMETER BusClockHertz is NULL + @retval EFI_UNSUPPORTED The controller does not support this frequency. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY) ( + IN EFI_PEI_I2C_MASTER_PPI *This, + IN UINTN *BusClockHertz + ); + +/** + Reset the I2C controller and configure it for use. + + @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure. + + @retval EFI_SUCCESS The reset completed successfully. + @retval EFI_DEVICE_ERROR The reset operation failed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET) ( + IN CONST EFI_PEI_I2C_MASTER_PPI *This + ); + +/** + Start an I2C transaction on the host controller. + + @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure. + @param SlaveAddress Address of the device on the I2C bus. + Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses, + clear this bit for 7-bit addressing. + Bits 0-6 are used for 7-bit I2C slave addresses and + bits 0-9 are used for 10-bit I2C slave addresses. + @param RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction. + + @retval EFI_SUCCESS The transaction completed successfully. + @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the transaction. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_NO_RESPONSE The I2C device is not responding to the slave address. + EFI_DEVICE_ERROR will be returned if the controller cannot distinguish when the NACK occurred. + @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction + @retval EFI_UNSUPPORTED The controller does not support the requested transaction. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST) ( + IN CONST EFI_PEI_I2C_MASTER_PPI *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket + ); + +/// +/// This PPI manipulates the I2C host controller to perform transactions as a master on the I2C bus +/// using the current state of any switches or multiplexers in the I2C bus. +/// +struct _EFI_PEI_I2C_MASTER_PPI { + EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency; + EFI_PEI_I2C_MASTER_PPI_RESET Reset; + EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest; + CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities; + EFI_GUID Identifier; +}; + +extern EFI_GUID gEfiPeiI2cMasterPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/IsaHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/IsaHc.h new file mode 100644 index 0000000000..2cbcce2854 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/IsaHc.h @@ -0,0 +1,113 @@ +/** @file + This PPI opens or closes an I/O aperture in a ISA HOST controller. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is from PI Version 1.2.1. + +**/ + +#ifndef __ISA_HC_PPI_H__ +#define __ISA_HC_PPI_H__ + +#define EFI_ISA_HC_PPI_GUID \ + { \ + 0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58} \ + } + +typedef struct _EFI_ISA_HC_PPI EFI_ISA_HC_PPI; +typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI; + +/** + Open I/O aperture. + + This function opens an I/O aperture in a ISA Host Controller for the I/O + addresses specified by IoAddress to IoAddress + IoLength - 1. It is possible + that more than one caller may be assigned to the same aperture. + It may be possible that a single hardware aperture may be used for more than + one device. This function tracks the number of times that each aperture is + referenced, and does not close the hardware aperture (via CloseIoAperture()) + until there are no more references to it. + + @param This A pointer to this instance of the EFI_ISA_HC_PPI. + @param IoAddress An unsigned integer that specifies the first byte of + the I/O space required. + @param IoLength An unsigned integer that specifies the number of + bytes of the I/O space required. + @param IoApertureHandle A pointer to the returned I/O aperture handle. + This value can be used on subsequent calls to CloseIoAperture(). + + @retval EFI_SUCCESS The I/O aperture was opened successfully. + @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller. + @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_ISA_HC_OPEN_IO) ( + IN CONST EFI_ISA_HC_PPI *This, + IN UINT16 IoAddress, + IN UINT16 IoLength, + OUT UINT64 *IoApertureHandle + ); + +/** + Close I/O aperture. + + This function closes a previously opened I/O aperture handle. If there are no + more I/O aperture handles that refer to the hardware I/O aperture resource, + then the hardware I/O aperture is closed. + It may be possible that a single hardware aperture may be used for more than + one device. This function tracks the number of times that each aperture is + referenced, and does not close the hardware aperture (via CloseIoAperture()) + until there are no more references to it. + + @param This A pointer to this instance of the EFI_ISA_HC_PPI. + @param IoApertureHandle The I/O aperture handle previously returned from a + call to OpenIoAperture(). + + @retval EFI_SUCCESS The I/O aperture was closed successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO) ( + IN CONST EFI_ISA_HC_PPI *This, + IN UINT64 IoApertureHandle + ); + +/// +/// This PPI provides functions for opening or closing an I/O aperture. +/// +struct _EFI_ISA_HC_PPI { + /// + /// An unsigned integer that specifies the version of the PPI structure. + /// + UINT32 Version; + /// + /// The address of the ISA/LPC Bridge device. + /// For PCI, this is the segment, bus, device and function of the a ISA/LPC + /// Bridge device. + /// + /// If bits 24-31 are 0, then the definition is: + /// Bits 0:2 - Function + /// Bits 3-7 - Device + /// Bits 8:15 - Bus + /// Bits 16-23 - Segment + /// Bits 24-31 - Bus Type + /// If bits 24-31 are 0xff, then the definition is platform-specific. + /// + UINT32 Address; + /// + /// Opens an aperture on a positive-decode ISA Host Controller. + /// + EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture; + /// + /// Closes an aperture on a positive-decode ISA Host Controller. + /// + EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture; +}; + +extern EFI_GUID gEfiIsaHcPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadFile.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadFile.h new file mode 100644 index 0000000000..3bedf9ab37 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadFile.h @@ -0,0 +1,71 @@ +/** @file + Load image file from fv to memory. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __LOAD_FILE_PPI_H__ +#define __LOAD_FILE_PPI_H__ + +#define EFI_PEI_LOAD_FILE_PPI_GUID \ + { 0xb9e0abfe, 0x5979, 0x4914, { 0x97, 0x7f, 0x6d, 0xee, 0x78, 0xc2, 0x78, 0xa6 } } + + +typedef struct _EFI_PEI_LOAD_FILE_PPI EFI_PEI_LOAD_FILE_PPI; + +/** + Loads a PEIM into memory for subsequent execution. + + This service is the single member function of EFI_LOAD_FILE_PPI. + This service separates image loading and relocating from the PEI Foundation. + + @param This Interface pointer that implements + the Load File PPI instance. + @param FileHandle File handle of the file to load. + @param ImageAddress Pointer to the address of the loaded image. + @param ImageSize Pointer to the size of the loaded image. + @param EntryPoint Pointer to the entry point of the image. + @param AuthenticationState On exit, points to the attestation + authentication state of the image + or 0 if no attestation was performed. + + @retval EFI_SUCCESS The image was loaded successfully. + @retval EFI_OUT_OF_RESOURCES There was not enough memory. + @retval EFI_LOAD_ERROR There was no supported image in the file. + @retval EFI_INVALID_PARAMETER FileHandle was not a valid firmware file handle. + @retval EFI_INVALID_PARAMETER EntryPoint was NULL. + @retval EFI_UNSUPPORTED An image requires relocations or is not + memory mapped. + @retval EFI_WARN_BUFFER_TOO_SMALL + There is not enough heap to allocate the requested size. + This will not prevent the XIP image from being invoked. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_LOAD_FILE)( + IN CONST EFI_PEI_LOAD_FILE_PPI *This, + IN EFI_PEI_FILE_HANDLE FileHandle, + OUT EFI_PHYSICAL_ADDRESS *ImageAddress, + OUT UINT64 *ImageSize, + OUT EFI_PHYSICAL_ADDRESS *EntryPoint, + OUT UINT32 *AuthenticationState +); + +/// +/// This PPI is a pointer to the Load File service. +/// This service will be published by a PEIM. The PEI Foundation +/// will use this service to launch the known PEI module images. +/// +struct _EFI_PEI_LOAD_FILE_PPI { + EFI_PEI_LOAD_FILE LoadFile; +}; + +extern EFI_GUID gEfiPeiLoadFilePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadImage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadImage.h new file mode 100644 index 0000000000..4077eb4224 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/LoadImage.h @@ -0,0 +1,46 @@ +/** @file + The file describes the PPI which notifies other drivers + of the PEIM being initialized by the PEI Dispatcher. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __LOADED_IMAGE_PPI_H__ +#define __LOADED_IMAGE_PPI_H__ + +#define EFI_PEI_LOADED_IMAGE_PPI_GUID \ + { 0xc1fcd448, 0x6300, 0x4458, { 0xb8, 0x64, 0x28, 0xdf, 0x1, 0x53, 0x64, 0xbc } } + + +typedef struct _EFI_PEI_LOADED_IMAGE_PPI EFI_PEI_LOADED_IMAGE_PPI; + +/// +/// This interface is installed by the PEI Dispatcher after the image has been +/// loaded and after all security checks have been performed, +/// to notify other PEIMs of the files which are being loaded. +/// +struct _EFI_PEI_LOADED_IMAGE_PPI { + /// + /// Address of the image at the address where it will be executed. + /// + EFI_PHYSICAL_ADDRESS ImageAddress; + /// + /// Size of the image as it will be executed. + /// + UINT64 ImageSize; + /// + /// File handle from which the image was loaded. + /// Can be NULL, indicating the image was not loaded from a handle. + /// + EFI_PEI_FILE_HANDLE FileHandle; +}; + + +extern EFI_GUID gEfiPeiLoadedImagePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MasterBootMode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MasterBootMode.h new file mode 100644 index 0000000000..d3d4b7e712 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MasterBootMode.h @@ -0,0 +1,26 @@ +/** @file + This file declares Boot Mode PPI. + + The Master Boot Mode PPI is installed by a PEIM to signal that a final + boot has been determined and set. This signal is useful in that PEIMs + with boot-mode-specific behavior can put this PPI in their dependency expression. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __MASTER_BOOT_MODE_PPI_H__ +#define __MASTER_BOOT_MODE_PPI_H__ + +#define EFI_PEI_MASTER_BOOT_MODE_PEIM_PPI \ + { \ + 0x7408d748, 0xfc8c, 0x4ee6, {0x92, 0x88, 0xc4, 0xbe, 0xc0, 0x92, 0xa4, 0x10 } \ + } + +extern EFI_GUID gEfiPeiMasterBootModePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MemoryDiscovered.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MemoryDiscovered.h new file mode 100644 index 0000000000..0109a215cb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MemoryDiscovered.h @@ -0,0 +1,26 @@ +/** @file + This file declares Memory Discovered PPI. + + This PPI is published by the PEI Foundation when the main memory is installed. + It is essentially a PPI with no associated interface. Its purpose is to be used + as a signal for other PEIMs who can register for a notification on its installation. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_MEMORY_DISCOVERED_PPI_H__ +#define __PEI_MEMORY_DISCOVERED_PPI_H__ + +#define EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI_GUID \ + { \ + 0xf894643d, 0xc449, 0x42d1, {0x8e, 0xa8, 0x85, 0xbd, 0xd8, 0xc6, 0x5b, 0xde } \ + } + +extern EFI_GUID gEfiPeiMemoryDiscoveredPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmAccess.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmAccess.h new file mode 100644 index 0000000000..6335872ef6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmAccess.h @@ -0,0 +1,155 @@ +/** @file + EFI MM Access PPI definition. + + This PPI is used to control the visibility of the MMRAM on the platform. + The EFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The + principal functionality found in the memory controller includes the following: + - Exposing the MMRAM to all non-MM agents, or the "open" state + - Shrouding the MMRAM to all but the MM agents, or the "closed" state + - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be + perturbed by either boot service or runtime agents + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.5. + +**/ + +#ifndef _MM_ACCESS_PPI_H_ +#define _MM_ACCESS_PPI_H_ + +#define EFI_PEI_MM_ACCESS_PPI_GUID \ + { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }} + +typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI; + +/** + Opens the MMRAM area to be accessible by a PEIM. + + This function "opens" MMRAM so that it is visible while not inside of MM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function + should return EFI_DEVICE_ERROR if the MMRAM configuration is locked. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + @param This The EFI_PEI_MM_ACCESS_PPI instance. + @param DescriptorIndex The region of MMRAM to Open. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM. + @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_OPEN)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Inhibits access to the MMRAM. + + This function "closes" MMRAM so that it is not visible while outside of MM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + @param This The EFI_PEI_MM_ACCESS_PPI instance. + @param DescriptorIndex The region of MMRAM to Close. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM. + @retval EFI_DEVICE_ERROR MMRAM cannot be closed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_CLOSE)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + This function prohibits access to the MMRAM region. This function is usually implemented such + that it is a write-once operation. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + @param This The EFI_PEI_MM_ACCESS_PPI instance. + @param DescriptorIndex The region of MMRAM to Lock. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_LOCK)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Queries the memory controller for the possible regions that will support MMRAM. + + This function describes the MMRAM regions. + This data structure forms the contract between the MM_ACCESS and MM_IPL drivers. There is an + ambiguity when any MMRAM region is remapped. For example, on some chipsets, some MMRAM + regions can be initialized at one physical address but is later accessed at another processor address. + There is currently no way for the MM IPL driver to know that it must use two different addresses + depending on what it is trying to do. As a result, initial configuration and loading can use the + physical address PhysicalStart while MMRAM is open. However, once the region has been + closed and needs to be accessed by agents in MM, the CpuStart address must be used. + This PPI publishes the available memory that the chipset can shroud for the use of installing code. + These regions serve the dual purpose of describing which regions have been open, closed, or locked. + In addition, these regions may include overlapping memory ranges, depending on the chipset + implementation. The latter might include a chipset that supports T-SEG, where memory near the top + of the physical DRAM can be allocated for MMRAM too. + The key thing to note is that the regions that are described by the PPI are a subset of the capabilities + of the hardware. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + @param This The EFI_PEI_MM_ACCESS_PPI instance. + @param MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is + the size of the buffer that is allocated by the caller. On output, it is the size of the + buffer that was returned by the firmware if the buffer was large enough, or, if the + buffer was too small, the size of the buffer that is needed to contain the map. + @param MmramMap A pointer to the buffer in which firmware places the current memory map. The map is + an array of EFI_MMRAM_DESCRIPTORs + + @retval EFI_SUCCESS The chipset supported the given resource. + @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current + buffer size needed to hold the memory map is returned in + MmramMapSize. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_CAPABILITIES)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN OUT UINTN *MmramMapSize, + IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap + ); + +/// +/// EFI MM Access PPI is used to control the visibility of the MMRAM on the platform. +/// It abstracts the location and characteristics of MMRAM. The platform should report +/// all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or +/// memory controller would publish this PPI. +/// +struct _EFI_PEI_MM_ACCESS_PPI { + EFI_PEI_MM_OPEN Open; + EFI_PEI_MM_CLOSE Close; + EFI_PEI_MM_LOCK Lock; + EFI_PEI_MM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gEfiPeiMmAccessPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmCommunication.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmCommunication.h new file mode 100644 index 0000000000..db3b26b7f5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmCommunication.h @@ -0,0 +1,72 @@ +/** @file + EFI MM Communication PPI definition. + + This PPI provides a means of communicating between drivers outside + of MM and MMI handlers inside of MM in PEI phase. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef MM_COMMUNICATION_PPI_H_ +#define MM_COMMUNICATION_PPI_H_ + +#define EFI_PEI_MM_COMMUNICATION_PPI_GUID \ + { \ + 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \ + } + +typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI; + +/** + Communicates with a registered handler. + + This function provides a service to send and receive messages from a registered PEI service. + The EFI_PEI_MM_COMMUNICATION_PPI driver is responsible for doing any of the copies such that + the data lives in PEI-service-accessible RAM. + + A given implementation of the EFI_PEI_MM_COMMUNICATION_PPI may choose to use the + EFI_MM_CONTROL_PPI for effecting the mode transition, or it may use some other method. + + The agent invoking the communication interface must be physical/virtually 1:1 mapped. + + To avoid confusion in interpreting frames, the CommBuffer parameter should always begin with + EFI_MM_COMMUNICATE_HEADER. The header data is mandatory for messages sent into the MM agent. + + Once inside of MM, the MM infrastructure will call all registered handlers with the same + HandlerType as the GUID specified by HeaderGuid and the CommBuffer pointing to Data. + + This function is not reentrant. + + @param[in] This The EFI_PEI_MM_COMMUNICATION_PPI instance. + @param[in] CommBuffer Pointer to the buffer to convey into MMRAM. + @param[in] CommSize The size of the data buffer being passed in. On exit, the + size of data being returned. Zero if the handler does not + wish to reply with any data. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The buffer was NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_COMMUNICATE)( + IN CONST EFI_PEI_MM_COMMUNICATION_PPI *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize + ); + +/// +/// EFI MM Communication PPI provides services for communicating between PEIM and a registered +/// MMI handler. +/// +struct _EFI_PEI_MM_COMMUNICATION_PPI { + EFI_PEI_MM_COMMUNICATE Communicate; +}; + +extern EFI_GUID gEfiPeiMmCommunicationPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmConfiguration.h new file mode 100644 index 0000000000..4859c2f1ef --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmConfiguration.h @@ -0,0 +1,62 @@ +/** @file + EFI MM Configuration PPI as defined in PI 1.5 specification. + + This PPI is used to: + 1) report the portions of MMRAM regions which cannot be used for the MMRAM heap. + 2) register the MM Foundation entry point with the processor code. The entry + point will be invoked by the MM processor entry code. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MM_CONFIGURATION_PPI_H_ +#define MM_CONFIGURATION_PPI_H_ + +#include + +#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \ + { \ + 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } \ + } + +typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI; + +/** + This function registers the MM Foundation entry point with the processor code. This entry point will be + invoked by the MM Processor entry code as defined in PI specification. + + @param[in] This The EFI_PEI_MM_CONFIGURATION_PPI instance. + @param[in] MmEntryPoint MM Foundation entry point. + + @retval EFI_SUCCESS The entry-point was successfully registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) ( + IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This, + IN EFI_MM_ENTRY_POINT MmEntryPoint + ); + +/// +/// This PPI is a PPI published by a CPU PEIM to indicate which areas within MMRAM are reserved for use by +/// the CPU for any purpose, such as stack, save state or MM entry point. If a platform chooses to let a CPU +/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM. +/// +/// The MmramReservedRegions points to an array of one or more EFI_MM_RESERVED_MMRAM_REGION structures, with +/// the last structure having the MmramReservedSize set to 0. An empty array would contain only the last +/// structure. +/// +/// The RegisterMmEntry() function allows the MM IPL PEIM to register the MM Foundation entry point with the +/// MM entry vector code. +/// +struct _EFI_PEI_MM_CONFIGURATION_PPI { + EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions; + EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry; +}; + +extern EFI_GUID gEfiPeiMmConfigurationPpi; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmControl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmControl.h new file mode 100644 index 0000000000..dc5cf62e19 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MmControl.h @@ -0,0 +1,90 @@ +/** @file + EFI MM Control PPI definition. + + This PPI is used initiate synchronous MMI activations. This PPI could be published by a processor + driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the APM port. + Because of the possibility of performing MMI IPI transactions, the ability to generate this event + from a platform chipset agent is an optional capability for both IA-32 and x64-based systems. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.5. + +**/ + + +#ifndef _MM_CONTROL_PPI_H_ +#define _MM_CONTROL_PPI_H_ + +#define EFI_PEI_MM_CONTROL_PPI_GUID \ + { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 } + +typedef struct _EFI_PEI_MM_CONTROL_PPI EFI_PEI_MM_CONTROL_PPI; + +/** + Invokes PPI activation from the PI PEI environment. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + @param This The PEI_MM_CONTROL_PPI instance. + @param ArgumentBuffer The value passed to the MMI handler. This value corresponds to the + SwMmiInputValue in the RegisterContext parameter for the Register() + function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Context parameter + in the call to the DispatchFunction + @param ArgumentBufferSize The size of the data passed in ArgumentBuffer or NULL if ArgumentBuffer is NULL. + @param Periodic An optional mechanism to periodically repeat activation. + @param ActivationInterval An optional parameter to repeat at this period one + time or, if the Periodic Boolean is set, periodically. + + @retval EFI_SUCCESS The MMI has been engendered. + @retval EFI_DEVICE_ERROR The timing is unsupported. + @retval EFI_INVALID_PARAMETER The activation period is unsupported. + @retval EFI_NOT_STARTED The MM base service has not been initialized. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_ACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + Clears any system state that was created in response to the Trigger() call. + + @param PeiServices General purpose services available to every PEIM. + @param This The PEI_MM_CONTROL_PPI instance. + @param Periodic Optional parameter to repeat at this period one + time or, if the Periodic Boolean is set, periodically. + + @retval EFI_SUCCESS The MMI has been engendered. + @retval EFI_DEVICE_ERROR The source could not be cleared. + @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MM_DEACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ); + +/// +/// The EFI_PEI_MM_CONTROL_PPI is produced by a PEIM. It provides an abstraction of the +/// platform hardware that generates an MMI. There are often I/O ports that, when accessed, will +/// generate the MMI. Also, the hardware optionally supports the periodic generation of these signals. +/// +struct _EFI_PEI_MM_CONTROL_PPI { + EFI_PEI_MM_ACTIVATE Trigger; + EFI_PEI_MM_DEACTIVATE Clear; +}; + +extern EFI_GUID gEfiPeiMmControlPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MpServices.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MpServices.h new file mode 100644 index 0000000000..b7dfb3bc58 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/MpServices.h @@ -0,0 +1,277 @@ +/** @file + This file declares UEFI PI Multi-processor PPI. + This PPI is installed by some platform or chipset-specific PEIM that abstracts + handling multiprocessor support. + + Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.4. + +**/ + +#ifndef __PEI_MP_SERVICES_PPI_H__ +#define __PEI_MP_SERVICES_PPI_H__ + +#include + +#define EFI_PEI_MP_SERVICES_PPI_GUID \ + { \ + 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } \ + } + +typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI ; + +/** + Get the number of CPU's. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This Pointer to this instance of the PPI. + @param[out] NumberOfProcessors Pointer to the total number of logical processors in + the system, including the BSP and disabled APs. + @param[out] NumberOfEnabledProcessors + Number of processors in the system that are enabled. + + @retval EFI_SUCCESS The number of logical processors and enabled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL. + NumberOfEnabledProcessors is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors + ); + +/** + Get information on a specific CPU. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This Pointer to this instance of the PPI. + @param[in] ProcessorNumber Pointer to the total number of logical processors in + the system, including the BSP and disabled APs. + @param[out] ProcessorInfoBuffer Number of processors in the system that are enabled. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist in the platform. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + ); + +/** + Activate all of the application processors. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] Procedure A pointer to the function to be run on enabled APs of + the system. + @param[in] SingleThread If TRUE, then all the enabled APs execute the function + specified by Procedure one by one, in ascending order + of processor handle number. If FALSE, then all the + enabled APs execute the function specified by Procedure + simultaneously. + @param[in] TimeoutInMicroSeconds + Indicates the time limit in microseconds for APs to + return from Procedure, for blocking mode only. Zero + means infinity. If the timeout expires before all APs + return from Procedure, then Procedure on the failed APs + is terminated. All enabled APs are available for next + function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() + or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the + timeout expires in blocking mode, BSP returns + EFI_TIMEOUT. + @param[in] ProcedureArgument The parameter passed into Procedure for all APs. + + @retval EFI_SUCCESS In blocking mode, all APs have finished before the + timeout expired. + @retval EFI_DEVICE_ERROR Caller processor is AP. + @retval EFI_NOT_STARTED No enabled APs exist in the system. + @retval EFI_NOT_READY Any enabled APs are busy. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before all + enabled APs have finished. + @retval EFI_INVALID_PARAMETER Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL + ); + +/** + Activate a specific application processor. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] Procedure A pointer to the function to be run on enabled APs of + the system. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] TimeoutInMicroSeconds + Indicates the time limit in microseconds for APs to + return from Procedure, for blocking mode only. Zero + means infinity. If the timeout expires before all APs + return from Procedure, then Procedure on the failed APs + is terminated. All enabled APs are available for next + function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() + or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the + timeout expires in blocking mode, BSP returns + EFI_TIMEOUT. + @param[in] ProcedureArgument The parameter passed into Procedure for all APs. + + @retval EFI_SUCCESS In blocking mode, specified AP finished before the + timeout expires. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before the + specified AP has finished. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP. + @retval EFI_INVALID_PARAMETER Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL + ); + +/** + Switch the boot strap processor. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an enabled + AP. Otherwise, it will be disabled. + + @retval EFI_SUCCESS BSP successfully switched. + @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this + service returning. + @retval EFI_UNSUPPORTED Switching the BSP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled + AP. + @retval EFI_NOT_READY The specified AP is busy. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP + ); + +/** + Enable or disable an application processor. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + @param[in] EnableAP Specifies the new state for the processor for enabled, + FALSE for disabled. + @param[in] HealthFlag If not NULL, a pointer to a value that specifies the + new health status of the AP. This flag corresponds to + StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). + Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other + bits are ignored. If it is NULL, this parameter is + ignored. + + @retval EFI_SUCCESS The specified AP was enabled or disabled successfully. + @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior + to this service returning. + @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber + does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL + ); + +/** + Identify the currently executing processor. + + @param[in] PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance. + @param[out] ProcessorNumber The handle number of the AP. The range is from 0 to the + total number of logical processors minus 1. The total + number of logical processors can be retrieved by + EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). + + @retval EFI_SUCCESS The current processor handle number was returned in + ProcessorNumber. + @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI) ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MP_SERVICES_PPI *This, + OUT UINTN *ProcessorNumber + ); + +/// +/// This PPI is installed by some platform or chipset-specific PEIM that abstracts +/// handling multiprocessor support. +/// +struct _EFI_PEI_MP_SERVICES_PPI { + EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; + EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; + EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; + EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; + EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP; + EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; + EFI_PEI_MP_SERVICES_WHOAMI WhoAmI; +}; + +extern EFI_GUID gEfiPeiMpServicesPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Pcd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Pcd.h new file mode 100644 index 0000000000..efd102e78a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Pcd.h @@ -0,0 +1,854 @@ +/** @file + Native Platform Configuration Database (PCD) PPI + + Different with the EFI_PCD_PPI defined in PI 1.2 specification, the native + PCD PPI provide interfaces for dynamic and dynamic-ex type PCD. + The interfaces for dynamic type PCD do not require the token space guid as parameter, + but interfaces for dynamic-ex type PCD require token space guid as parameter. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCD_PPI_H__ +#define __PCD_PPI_H__ + +#define PCD_PPI_GUID \ + { 0x6e81c58, 0x4ad7, 0x44bc, { 0x83, 0x90, 0xf1, 0x2, 0x65, 0xf7, 0x24, 0x80 } } + +#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0) + + +/** + Sets the SKU value for subsequent calls to set or get PCD token values. + + SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. + SetSku() is normally called only once by the system. + + For each item (token), the database can hold a single value that applies to all SKUs, + or multiple values, where each value is associated with a specific SKU Id. Items with multiple, + SKU-specific values are called SKU enabled. + + The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255. + For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the + single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the + last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token, + the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been + set for that Id, the results are unpredictable. + + @param[in] SkuId The SKU value that will be used when the PCD service will retrieve and + set values associated with a PCD token. + + @retval VOID + +**/ +typedef +VOID +(EFIAPI *PCD_PPI_SET_SKU)( + IN UINTN SkuId + ); + + + +/** + Retrieves an 8-bit value for a given PCD token. + + Retrieves the current byte-sized value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT8 value. + +**/ +typedef +UINT8 +(EFIAPI *PCD_PPI_GET8)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 16-bit value for a given PCD token. + + Retrieves the current 16-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT16 value. + +**/ +typedef +UINT16 +(EFIAPI *PCD_PPI_GET16)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 32-bit value for a given PCD token. + + Retrieves the current 32-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT32 value. + +**/ +typedef +UINT32 +(EFIAPI *PCD_PPI_GET32)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 64-bit value for a given PCD token. + + Retrieves the current 64-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT64 value. + +**/ +typedef +UINT64 +(EFIAPI *PCD_PPI_GET64)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a pointer to a value for a given PCD token. + + Retrieves the current pointer to the buffer for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The pointer to the buffer to be retrieved. + +**/ +typedef +VOID * +(EFIAPI *PCD_PPI_GET_POINTER)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a Boolean value for a given PCD token. + + Retrieves the current boolean value for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The Boolean value. + +**/ +typedef +BOOLEAN +(EFIAPI *PCD_PPI_GET_BOOLEAN)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves the size of the value for a given PCD token. + + Retrieves the current size of a particular PCD token. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The size of the value for the PCD token. + +**/ +typedef +UINTN +(EFIAPI *PCD_PPI_GET_SIZE)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves an 8-bit value for a given PCD token and token space. + + Retrieves the 8-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 8-bit value for the PCD token. + +**/ +typedef +UINT8 +(EFIAPI *PCD_PPI_GET_EX_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 16-bit value for a given PCD token and token space. + + Retrieves the 16-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 16-bit value for the PCD token. + +**/ +typedef +UINT16 +(EFIAPI *PCD_PPI_GET_EX_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 32-bit value for a given PCD token and token space. + + Retrieves the 32-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 32-bit value for the PCD token. + +**/ +typedef +UINT32 +(EFIAPI *PCD_PPI_GET_EX_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 64-bit value for a given PCD token and token space. + + Retrieves the 64-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 64-bit value for the PCD token. + +**/ +typedef +UINT64 +(EFIAPI *PCD_PPI_GET_EX_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a pointer to a value for a given PCD token and token space. + + Retrieves the current pointer to the buffer for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The pointer to the buffer to be retrieved. + +**/ +typedef +VOID * +(EFIAPI *PCD_PPI_GET_EX_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves an Boolean value for a given PCD token and token space. + + Retrieves the Boolean value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size Boolean value for the PCD token. + +**/ +typedef +BOOLEAN +(EFIAPI *PCD_PPI_GET_EX_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves the size of the value for a given PCD token and token space. + + Retrieves the current size of a particular PCD token. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size of the value for the PCD token. + +**/ +typedef +UINTN +(EFIAPI *PCD_PPI_GET_EX_SIZE)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET8)( + IN UINTN TokenNumber, + IN UINT8 Value + ); + + + +/** + Sets a 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET16)( + IN UINTN TokenNumber, + IN UINT16 Value + ); + + + +/** + Sets a 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET32)( + IN UINTN TokenNumber, + IN UINT32 Value + ); + + + +/** + Sets a 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET64)( + IN UINTN TokenNumber, + IN UINT64 Value + ); + +/** + Sets a value of a specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in, out] SizeOfValue A pointer to the length of the value being set for the PCD token. + On input, if the SizeOfValue is greater than the maximum size supported + for this TokenNumber then the output value of SizeOfValue will reflect + the maximum size supported for this TokenNumber. + @param[in] Buffer The buffer to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_POINTER)( + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfValue, + IN VOID *Buffer + ); + +/** + Sets an Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_BOOLEAN)( + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + + + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT8 Value + ); + + + +/** + Sets a 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT16 Value + ); + + + +/** + Sets a 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT32 Value + ); + + + +/** + Sets a 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT64 Value + ); + + + +/** + Sets a value of a specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in, out] SizeOfValue A pointer to the length of the value being set for the PCD token. + On input, if the SizeOfValue is greater than the maximum size supported + for this TokenNumber then the output value of SizeOfValue will reflect + the maximum size supported for this TokenNumber. + @param[in] Buffer The buffer to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfValue, + IN VOID *Buffer + ); + +/** + Sets an Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_SET_EX_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + + + +/** + Callback on SET function prototype definition. + + This notification function serves two purposes. Firstly, it notifies the module + which did the registration that the value of this PCD token has been set. Secondly, + it provides a mechanism for the module which did the registration to intercept the set + operation and override the value been set if necessary. After the invocation of the + callback function, TokenData will be used by PCD service PEIM to modify the internal data + in PCD database. + + @param[in] CallBackGuid The PCD token GUID being set. + @param[in] CallBackToken The PCD token number being set. + @param[in, out] TokenData A pointer to the token data being set. + @param[in] TokenDataSize The size, in bytes, of the data being set. + + @retval VOID + +**/ +typedef +VOID +(EFIAPI *PCD_PPI_CALLBACK)( + IN CONST EFI_GUID *CallBackGuid, OPTIONAL + IN UINTN CallBackToken, + IN OUT VOID *TokenData, + IN UINTN TokenDataSize + ); + + + +/** + Specifies a function to be called anytime the value of a designated token is changed. + + @param[in] TokenNumber The PCD token number. + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event + for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_CALLBACK_ONSET)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_PPI_CALLBACK CallBackFunction + ); + + + +/** + Cancels a previously set callback function for a particular PCD token number. + + @param[in] TokenNumber The PCD token number. + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event + for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_CANCEL_CALLBACK)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_PPI_CALLBACK CallBackFunction + ); + + + +/** + Retrieves the next valid token number in a given namespace. + + This is useful since the PCD infrastructure contains a sparse list of token numbers, + and one cannot a priori know what token numbers are valid in the database. + + If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned. + If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned. + If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned. + If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned. + The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid. + If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned. + If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned. + If TokenNumber is not present in the token space specified by Guid, then EFI_NOT_FOUND is returned. + + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + This is an optional parameter that may be NULL. If this parameter is NULL, then a request + is being made to retrieve tokens from the default token space. + @param[in, out] TokenNumber A pointer to the PCD token number to use to find the subsequent token number. + + @retval EFI_SUCCESS The PCD service has retrieved the next valid token number. + @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_GET_NEXT_TOKEN)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN OUT UINTN *TokenNumber + ); + + + +/** + Retrieves the next valid PCD token namespace for a given namespace. + + Gets the next valid token namespace for a given namespace. This is useful to traverse the valid + token namespaces on a platform. + + @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token + namespace from which the search will start. On output, it designates the next valid + token namespace on the platform. If *Guid is NULL, then the GUID of the first token + space of the current platform is returned. If the search cannot locate the next valid + token namespace, an error is returned and the value of *Guid is undefined. + + @retval EFI_SUCCESS The PCD service retrieved the value requested. + @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PPI_GET_NEXT_TOKENSPACE)( + IN OUT CONST EFI_GUID **Guid + ); + + + +/// +/// This service abstracts the ability to set/get Platform Configuration Database (PCD). +/// +typedef struct { + PCD_PPI_SET_SKU SetSku; + + PCD_PPI_GET8 Get8; + PCD_PPI_GET16 Get16; + PCD_PPI_GET32 Get32; + PCD_PPI_GET64 Get64; + PCD_PPI_GET_POINTER GetPtr; + PCD_PPI_GET_BOOLEAN GetBool; + PCD_PPI_GET_SIZE GetSize; + + PCD_PPI_GET_EX_8 Get8Ex; + PCD_PPI_GET_EX_16 Get16Ex; + PCD_PPI_GET_EX_32 Get32Ex; + PCD_PPI_GET_EX_64 Get64Ex; + PCD_PPI_GET_EX_POINTER GetPtrEx; + PCD_PPI_GET_EX_BOOLEAN GetBoolEx; + PCD_PPI_GET_EX_SIZE GetSizeEx; + + PCD_PPI_SET8 Set8; + PCD_PPI_SET16 Set16; + PCD_PPI_SET32 Set32; + PCD_PPI_SET64 Set64; + PCD_PPI_SET_POINTER SetPtr; + PCD_PPI_SET_BOOLEAN SetBool; + + PCD_PPI_SET_EX_8 Set8Ex; + PCD_PPI_SET_EX_16 Set16Ex; + PCD_PPI_SET_EX_32 Set32Ex; + PCD_PPI_SET_EX_64 Set64Ex; + PCD_PPI_SET_EX_POINTER SetPtrEx; + PCD_PPI_SET_EX_BOOLEAN SetBoolEx; + + PCD_PPI_CALLBACK_ONSET CallbackOnSet; + PCD_PPI_CANCEL_CALLBACK CancelCallback; + PCD_PPI_GET_NEXT_TOKEN GetNextToken; + PCD_PPI_GET_NEXT_TOKENSPACE GetNextTokenSpace; +} PCD_PPI; + + +extern EFI_GUID gPcdPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PcdInfo.h new file mode 100644 index 0000000000..c199c0063d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PcdInfo.h @@ -0,0 +1,99 @@ +/** @file + Native Platform Configuration Database (PCD) INFO PPI + + The PPI that provides additional information about items that reside in the PCD database. + + Different with the EFI_GET_PCD_INFO_PPI defined in PI 1.2.1 specification, + the native PCD INFO PPI provide interfaces for dynamic and dynamic-ex type PCD. + The interfaces for dynamic type PCD do not require the token space guid as parameter, + but interfaces for dynamic-ex type PCD require token space guid as parameter. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCD_INFO_PPI_H__ +#define __PCD_INFO_PPI_H__ + +extern EFI_GUID gGetPcdInfoPpiGuid; + +#define GET_PCD_INFO_PPI_GUID \ + { 0x4d8b155b, 0xc059, 0x4c8f, { 0x89, 0x26, 0x6, 0xfd, 0x43, 0x31, 0xdb, 0x8a } } + +/// +/// The forward declaration for GET_PCD_INFO_PPI. +/// +typedef struct _GET_PCD_INFO_PPI GET_PCD_INFO_PPI; + +/** + Retrieve additional information associated with a PCD token in the default token space. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_PCD_INFO_PPI_GET_INFO) ( + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_PCD_INFO_PPI_GET_INFO_EX) ( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve the currently set SKU Id. + + @return The currently set SKU Id. If the platform has not set at a SKU Id, then the + default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU + Id is returned. +**/ +typedef +UINTN +(EFIAPI *GET_PCD_INFO_PPI_GET_SKU) ( + VOID +); + +/// +/// This is the PCD service to use when querying for some additional data that can be contained in the +/// PCD database. +/// +struct _GET_PCD_INFO_PPI { + /// + /// Retrieve additional information associated with a PCD. + /// + GET_PCD_INFO_PPI_GET_INFO GetInfo; + GET_PCD_INFO_PPI_GET_INFO_EX GetInfoEx; + /// + /// Retrieve the currently set SKU Id. + /// + GET_PCD_INFO_PPI_GET_SKU GetSku; +}; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PciCfg2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PciCfg2.h new file mode 100644 index 0000000000..17b67a7209 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PciCfg2.h @@ -0,0 +1,178 @@ +/** @file + This file declares PciCfg2 PPI. + + This ppi Provides platform or chipset-specific access to + the PCI configuration space for a specific PCI segment. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_PCI_CFG2_H__ +#define __PEI_PCI_CFG2_H__ + +#include + +#define EFI_PEI_PCI_CFG2_PPI_GUID \ + { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } } + +typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI; + +#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \ + (UINT64) ( \ + (((UINTN) bus) << 24) | \ + (((UINTN) dev) << 16) | \ + (((UINTN) func) << 8) | \ + (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +/// +/// EFI_PEI_PCI_CFG_PPI_WIDTH +/// +typedef enum { + /// + /// 8-bit access + /// + EfiPeiPciCfgWidthUint8 = 0, + /// + /// 16-bit access + /// + EfiPeiPciCfgWidthUint16 = 1, + /// + /// 32-bit access + /// + EfiPeiPciCfgWidthUint32 = 2, + /// + /// 64-bit access + /// + EfiPeiPciCfgWidthUint64 = 3, + EfiPeiPciCfgWidthMaximum +} EFI_PEI_PCI_CFG_PPI_WIDTH; + +/// +/// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS +/// +typedef struct { + /// + /// 8-bit register offset within the PCI configuration space for a given device's function + /// space. + /// + UINT8 Register; + /// + /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a + /// given device. + /// + UINT8 Function; + /// + /// Only the 5 least-significant bits are used to encode one of 32 possible devices. + /// + UINT8 Device; + /// + /// 8-bit value to encode between 0 and 255 buses. + /// + UINT8 Bus; + /// + /// Register number in PCI configuration space. If this field is zero, then Register is used + /// for the register number. If this field is non-zero, then Register is ignored and this field + /// is used for the register number. + /// + UINT32 ExtendedRegister; +} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS; + +/** + Reads from or write to a given location in the PCI configuration space. + + @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation. + + @param This Pointer to local data for the interface. + + @param Width The width of the access. Enumerated in bytes. + See EFI_PEI_PCI_CFG_PPI_WIDTH above. + + @param Address The physical address of the access. The format of + the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS. + + @param Buffer A pointer to the buffer of data.. + + + @retval EFI_SUCCESS The function completed successfully. + + @retval EFI_DEVICE_ERROR There was a problem with the transaction. + + @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this + time. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_PCI_CFG2_PPI *This, + IN EFI_PEI_PCI_CFG_PPI_WIDTH Width, + IN UINT64 Address, + IN OUT VOID *Buffer +); + + +/** + Performs a read-modify-write operation on the contents + from a given location in the PCI configuration space. + + @param PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + + @param This Pointer to local data for the interface. + + @param Width The width of the access. Enumerated in bytes. Type + EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read(). + + @param Address The physical address of the access. + + @param SetBits Points to value to bitwise-OR with the read configuration value. + + The size of the value is determined by Width. + + @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value. + The size of the value is determined by Width. + + + @retval EFI_SUCCESS The function completed successfully. + + @retval EFI_DEVICE_ERROR There was a problem with the transaction. + + @retval EFI_DEVICE_NOT_READY The device is not capable of supporting + the operation at this time. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_PCI_CFG2_PPI *This, + IN EFI_PEI_PCI_CFG_PPI_WIDTH Width, + IN UINT64 Address, + IN VOID *SetBits, + IN VOID *ClearBits +); + +/// +/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI +/// controllers behind a PCI root bridge controller. +/// +struct _EFI_PEI_PCI_CFG2_PPI { + EFI_PEI_PCI_CFG2_PPI_IO Read; + EFI_PEI_PCI_CFG2_PPI_IO Write; + EFI_PEI_PCI_CFG2_PPI_RW Modify; + /// + /// The PCI bus segment which the specified functions will access. + /// + UINT16 Segment; +}; + + +extern EFI_GUID gEfiPciCfg2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PeiCoreFvLocation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PeiCoreFvLocation.h new file mode 100644 index 0000000000..72a308eaf7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PeiCoreFvLocation.h @@ -0,0 +1,42 @@ +/** @file + Header file for Pei Core FV Location PPI. + + This PPI contains a pointer to the firmware volume which contains the PEI Foundation. + If the PEI Foundation does not reside in the BFV, then SEC must pass this PPI as a part + of the PPI list provided to the PEI Foundation Entry Point, otherwise the PEI Foundation + shall assume that it resides within the BFV. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 1: + Standards + +**/ + + +#ifndef _EFI_PEI_CORE_FV_LOCATION_H_ +#define _EFI_PEI_CORE_FV_LOCATION_H_ + +/// +/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI +/// +#define EFI_PEI_CORE_FV_LOCATION_GUID \ + { \ + 0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 } \ + } + +/// +/// This PPI provides location of EFI PeiCoreFv. +/// +typedef struct { + /// + /// Pointer to the first byte of the firmware volume which contains the PEI Foundation. + /// + VOID *PeiCoreFvLocation; +} EFI_PEI_CORE_FV_LOCATION_PPI; + +extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid; + +#endif // _EFI_PEI_CORE_FV_LOCATION_H_ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcd.h new file mode 100644 index 0000000000..58c3be8fcb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcd.h @@ -0,0 +1,426 @@ +/** @file + Platform Configuration Database (PCD) PPI defined in PI 1.2 Vol3 + + A platform database that contains a variety of current platform settings or + directives that can be accessed by a driver or application. + PI PCD ppi only provide the accessing interfaces for Dynamic-Ex type PCD. + + This is the base PCD service API that provides an abstraction for accessing configuration content in + the platform. It a seamless mechanism for extracting information regardless of where the + information is stored (such as in Read-only data, or an EFI Variable). + This protocol allows access to data through size-granular APIs and provides a mechanism for a + firmware component to monitor specific settings and be alerted when a setting is changed. + + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.2 Vol 3. +**/ + +#ifndef __PI_PCD_PPI_H__ +#define __PI_PCD_PPI_H__ + +extern EFI_GUID gEfiPeiPcdPpiGuid; + +#define EFI_PEI_PCD_PPI_GUID \ + { 0x1f34d25, 0x4de2, 0x23ad, { 0x3f, 0xf3, 0x36, 0x35, 0x3f, 0xf3, 0x23, 0xf1 } } + +#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0) + +/** + SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. SetSku() is + normally called only once by the system. + For each item (token), the database can hold a single value that applies to all SKUs, or multiple + values, where each value is associated with a specific SKU Id. Items with multiple, SKU-specific + values are called SKU enabled. + The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255. For tokens that are + not SKU enabled, the system ignores any set SKU Id and works with the single value for that token. + For SKU-enabled tokens, the system will use the SKU Id set by the last call to SetSku(). If no + SKU Id is set or the currently set SKU Id isn't valid for the specified token, the system uses the + default SKU Id. If the system attempts to use the default SKU Id and no value has been set for that + Id, the results are unpredictable. + + @param[in] SkuId The SKU value to set. +**/ +typedef +VOID +(EFIAPI *EFI_PEI_PCD_PPI_SET_SKU)( + IN UINTN SkuId +); + +/** + Retrieves the current byte-sized value for a PCD token number. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return 8-bit value for a given PCD token. +**/ +typedef +UINT8 +(EFIAPI *EFI_PEI_PCD_PPI_GET_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current word-sized value for a PCD token number. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return 16-bit value for a given PCD token. +**/ +typedef +UINT16 +(EFIAPI *EFI_PEI_PCD_PPI_GET_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current 32-bit value for a PCD token number. If the TokenNumber is invalid, the + results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return 32-bit value for a given PCD token. +**/ +typedef +UINT32 +(EFIAPI *EFI_PEI_PCD_PPI_GET_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current 64-bit value for a PCD token number. If the TokenNumber is invalid, the + results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return 64-bit value for a given PCD token. +**/ +typedef +UINT64 +(EFIAPI *EFI_PEI_PCD_PPI_GET_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current pointer to the value for a PCD token number. There should not be any + alignment assumptions about the pointer that is returned by this function call. If the TokenNumber + is invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. +**/ +typedef +VOID * +(EFIAPI *EFI_PEI_PCD_PPI_GET_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current Boolean-sized value for a PCD token number. If the TokenNumber is + invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return Boolean value for a given PCD token. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_PEI_PCD_PPI_GET_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are + unpredictable. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + + @return the size of the value for a given PCD token. +**/ +typedef +UINTN +(EFIAPI *EFI_PEI_PCD_PPI_GET_SIZE)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT8 Value +); + +/** + Sets an 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT16 Value +); + +/** + Sets an 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT32 Value +); + +/** + Sets an 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT64 Value +); + +/** + Sets a value of the specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] SizeOfValue The length of the value being set for the PCD token. If too large of a length is + specified, upon return from this function the value of SizeOfValue will reflect the + maximum size for the PCD token. + @param[in] Buffer A pointer to the buffer containing the value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfValue, + IN VOID *Buffer +); + +/** + Sets a Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_SET_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN BOOLEAN Value +); + +typedef +VOID +(EFIAPI *EFI_PEI_PCD_PPI_CALLBACK)( + IN EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN OUT VOID *TokenData, + IN UINTN TokenDatSize +); + +/** + Specifies a function to be called anytime the value of a designated token is changed. + + @param[in] Guid The 128-bit unique value that designates which namespace to monitor. If NULL, use + the standard platform namespace. + @param[in] CallBackToken The PCD token number to monitor. + @param[in] CallBackFunction The function prototype that will be called when the value associated with the + CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event for the + CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_CALLBACK_ON_SET)( + IN CONST EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction +); + +/** + Cancels a previously set callback function for a particular PCD token number. + + @param[in] Guid The 128-bit unique value that designates which namespace to monitor. If NULL, use + the standard platform namespace. + @param[in] CallBackToken The PCD token number to cancel monitoring. + @param[in] CallBackFunction The function prototype that was originally passed to the CallBackOnSet function. + + @retval EFI_SUCCESS The PCD service has cancelled the call event associated with the + CallBackToken. + @retval EFI_INVALID_PARAMETER The PCD service did not match the CallBackFunction to one + that is currently being monitored. + @retval EFI_NOT_FOUND The PCD service could not find data the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_CANCEL_CALLBACK)( + IN CONST EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction +); + +/** + Retrieves the next valid PCD token for a given namespace. + + This provides a means by which to get the next valid token number in a given namespace. This is + useful since the PCD infrastructure has a sparse list of token numbers in it, and one cannot a priori + know what token numbers are valid in the database. + + @param[in] Guid The 128-bit unique value that designates which namespace to extract the value from. + @param[in] TokenNumber A pointer to the PCD token number to use to find the subsequent token number. To + retrieve the "first" token, have the pointer reference a TokenNumber value of 0. + + @retval EFI_SUCCESS The PCD service has retrieved the value requested. + @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN)( + IN CONST EFI_GUID *Guid OPTIONAL, + IN UINTN *TokenNumber +); + +/** + Retrieves the next valid PCD token namespace for a given namespace. + + Gets the next valid token namespace for a given namespace. This is useful to traverse the valid + token namespaces on a platform. + + @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token + namespace from which the search will start. On output, it designates the next valid + token namespace on the platform. If *Guid is NULL, then the GUID of the first token + space of the current platform is returned. If the search cannot locate the next valid + token namespace, an error is returned and the value of *Guid is undefined. + + @retval EFI_SUCCESS The PCD service retrieved the value requested. + @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE)( + IN OUT CONST EFI_GUID **Guid +); + +typedef struct { + EFI_PEI_PCD_PPI_SET_SKU SetSku; + EFI_PEI_PCD_PPI_GET_8 Get8; + EFI_PEI_PCD_PPI_GET_16 Get16; + EFI_PEI_PCD_PPI_GET_32 Get32; + EFI_PEI_PCD_PPI_GET_64 Get64; + EFI_PEI_PCD_PPI_GET_POINTER GetPtr; + EFI_PEI_PCD_PPI_GET_BOOLEAN GetBool; + EFI_PEI_PCD_PPI_GET_SIZE GetSize; + EFI_PEI_PCD_PPI_SET_8 Set8; + EFI_PEI_PCD_PPI_SET_16 Set16; + EFI_PEI_PCD_PPI_SET_32 Set32; + EFI_PEI_PCD_PPI_SET_64 Set64; + EFI_PEI_PCD_PPI_SET_POINTER SetPtr; + EFI_PEI_PCD_PPI_SET_BOOLEAN SetBool; + EFI_PEI_PCD_PPI_CALLBACK_ON_SET CallbackOnSet; + EFI_PEI_PCD_PPI_CANCEL_CALLBACK CancelCallback; + EFI_PEI_PCD_PPI_GET_NEXT_TOKEN GetNextToken; + EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE GetNextTokenSpace; +} EFI_PEI_PCD_PPI; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcdInfo.h new file mode 100644 index 0000000000..0248b4607c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/PiPcdInfo.h @@ -0,0 +1,76 @@ +/** @file + Platform Configuration Database (PCD) Info Ppi defined in PI 1.2.1 Vol3. + + The PPI that provides additional information about items that reside in the PCD database. + + Copyright (c) 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.2.1 Vol 3. +**/ + +#ifndef __PI_PCD_INFO_PPI_H__ +#define __PI_PCD_INFO_PPI_H__ + +extern EFI_GUID gEfiGetPcdInfoPpiGuid; + +#define EFI_GET_PCD_INFO_PPI_GUID \ + { 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69, 0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } } + +/// +/// The forward declaration for EFI_GET_PCD_INFO_PPI. +/// +typedef struct _EFI_GET_PCD_INFO_PPI EFI_GET_PCD_INFO_PPI; + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_INFO) ( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve the currently set SKU Id. + + @return The currently set SKU Id. If the platform has not set at a SKU Id, then the + default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU + Id is returned. +**/ +typedef +UINTN +(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_SKU) ( + VOID +); + +/// +/// This is the PCD service to use when querying for some additional data that can be contained in the +/// PCD database. +/// +struct _EFI_GET_PCD_INFO_PPI { + /// + /// Retrieve additional information associated with a PCD. + /// + EFI_GET_PCD_INFO_PPI_GET_INFO GetInfo; + /// + /// Retrieve the currently set SKU Id. + /// + EFI_GET_PCD_INFO_PPI_GET_SKU GetSku; +}; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReadOnlyVariable2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReadOnlyVariable2.h new file mode 100644 index 0000000000..95e21a96a3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReadOnlyVariable2.h @@ -0,0 +1,111 @@ +/** @file + This file declares Read-only Variable Service2 PPI. + This ppi permits read-only access to the UEFI variable store during the PEI phase. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_READ_ONLY_VARIABLE2_PPI_H__ +#define __PEI_READ_ONLY_VARIABLE2_PPI_H__ + +#define EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID \ + { 0x2ab86ef5, 0xecb5, 0x4134, { 0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4 } } + + +typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI EFI_PEI_READ_ONLY_VARIABLE2_PPI; + +/** + This service retrieves a variable's value using its name and GUID. + + Read the specified variable from the UEFI variable store. If the Data + buffer is too small to hold the contents of the variable, + the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the + required buffer size to obtain the data. + + @param This A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI. + @param VariableName A pointer to a null-terminated string that is the variable's name. + @param VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of + VariableGuid and VariableName must be unique. + @param Attributes If non-NULL, on return, points to the variable's attributes. + @param DataSize On entry, points to the size in bytes of the Data buffer. + On return, points to the size of the data returned in Data. + @param Data Points to the buffer which will hold the returned variable value. + May be NULL with a zero DataSize in order to determine the size of the buffer needed. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data. + DataSize is updated with the size required for + the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_VARIABLE2)( + IN CONST EFI_PEI_READ_ONLY_VARIABLE2_PPI *This, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + OUT UINT32 *Attributes, + IN OUT UINTN *DataSize, + OUT VOID *Data OPTIONAL + ); + + +/** + Return the next variable name and GUID. + + This function is called multiple times to retrieve the VariableName + and VariableGuid of all variables currently available in the system. + On each call, the previous results are passed into the interface, + and, on return, the interface returns the data for the next + interface. When the entire variable list has been returned, + EFI_NOT_FOUND is returned. + + @param This A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI. + + @param VariableNameSize On entry, points to the size of the buffer pointed to by VariableName. + On return, the size of the variable name buffer. + @param VariableName On entry, a pointer to a null-terminated string that is the variable's name. + On return, points to the next variable's null-terminated name string. + + @param VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID. + On return, a pointer to the next variable's GUID. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable could not be found. + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting + data. VariableNameSize is updated with the size + required for the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or + VariableNameSize is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_GET_NEXT_VARIABLE_NAME2)( + IN CONST EFI_PEI_READ_ONLY_VARIABLE2_PPI *This, + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VariableGuid + ); + +/// +/// This PPI provides a lightweight, read-only variant of the full EFI +/// variable services. +/// +struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI { + EFI_PEI_GET_VARIABLE2 GetVariable; + EFI_PEI_GET_NEXT_VARIABLE_NAME2 NextVariableName; +}; + +extern EFI_GUID gEfiPeiReadOnlyVariable2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/RecoveryModule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/RecoveryModule.h new file mode 100644 index 0000000000..5b7dde32c2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/RecoveryModule.h @@ -0,0 +1,81 @@ +/** @file + This file declares Recovery Module PPI. This PPI is used to find and load the + recovery files. + + A module that produces this PPI has many roles and is responsible for the following: + -# Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI. + GetNumberRecoveryCapsules() to determine if one or more DXE recovery + entities exist. + -# If no capsules exist, then performing appropriate error handling. + -# Allocating a buffer of MaxRecoveryCapsuleSize as determined by + EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.GetRecoveryCapsuleInfo() or + larger. + -# Determining the policy in which DXE recovery capsules are loaded. + -# Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI. + LoadRecoveryCapsule() for capsule number x. + -# If the load failed, performing appropriate error handling. + -# Performing security checks for a loaded DXE recovery capsule. + -# If the security checks failed, then logging the failure in a data HOB. + -# If the security checks failed, then determining the next + EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()capsule number; + otherwise, go to step 11. + -# If more DXE recovery capsules exist, then go to step 5; otherwise, perform + error handling. + -# Decomposing the capsule loaded by EFI_PEI_DEVICE_RECOVERY_MODULE_PPI. + LoadRecoveryCapsule() into its components. It is assumed that the path + parameters are redundant for recovery and Setup parameters are either + redundant or canned. + -# Invalidating all HOB entries for updateable firmware volume entries. + This invalidation prevents possible errant drivers from being executed. + -# Updating the HOB table with the recovery DXE firmware volume information + generated from the capsule decomposition. + -# Returning to the PEI Dispatcher. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Errata B Volume 1: + Pre-EFI Initialization Core Interface + +**/ + +#ifndef __PEI_RECOVERY_MODULE_PPI_H__ +#define __PEI_RECOVERY_MODULE_PPI_H__ + +#define EFI_PEI_RECOVERY_MODULE_PPI_GUID \ + { \ + 0xFB6D9542, 0x612D, 0x4f45, {0x87, 0x2F, 0x5C, 0xFF, 0x52, 0xE9, 0x3D, 0xCF } \ + } + +typedef struct _EFI_PEI_RECOVERY_MODULE_PPI EFI_PEI_RECOVERY_MODULE_PPI; + +/** + Loads a DXE capsule from some media into memory and updates the HOB table + with the DXE firmware volume information. + + @param PeiServices General-purpose services that are available to every PEIM. + @param This Indicates the EFI_PEI_RECOVERY_MODULE_PPI instance. + + @retval EFI_SUCCESS The capsule was loaded correctly. + @retval EFI_DEVICE_ERROR A device error occurred. + @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_LOAD_RECOVERY_CAPSULE)( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_RECOVERY_MODULE_PPI *This + ); + +/// +/// Finds and loads the recovery files. +/// +struct _EFI_PEI_RECOVERY_MODULE_PPI { + EFI_PEI_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE binary capsule into memory. +}; + +extern EFI_GUID gEfiPeiRecoveryModulePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReportStatusCodeHandler.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReportStatusCodeHandler.h new file mode 100644 index 0000000000..89767a0912 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/ReportStatusCodeHandler.h @@ -0,0 +1,76 @@ +/** @file + This PPI provides registering and unregistering services to status code consumers. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __REPORT_STATUS_CODE_HANDLER_PPI_H__ +#define __REPORT_STATUS_CODE_HANDLER_PPI_H__ + +#define EFI_PEI_RSC_HANDLER_PPI_GUID \ + { \ + 0x65d394, 0x9951, 0x4144, {0x82, 0xa3, 0xa, 0xfc, 0x85, 0x79, 0xc2, 0x51} \ + } + +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_RSC_HANDLER_CALLBACK)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId, + IN CONST EFI_STATUS_CODE_DATA *Data +); + +/** + Register the callback function for ReportStatusCode() notification. + + When this function is called the function pointer is added to an internal list and any future calls to + ReportStatusCode() will be forwarded to the Callback function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is called + when a call to ReportStatusCode() occurs. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No more functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It can't be registered again. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_RSC_HANDLER_REGISTER)( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback +); + +/** + Remove a previously registered callback function from the notification list. + + ReportStatusCode() messages will no longer be forwarded to the Callback function. + + @param[in] Callback A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is to be + unregistered. + + @retval EFI_SUCCESS The function was successfully unregistered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_NOT_FOUND The callback function was not found to be unregistered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_RSC_HANDLER_UNREGISTER)( + IN EFI_PEI_RSC_HANDLER_CALLBACK Callback +); + +typedef struct _EFI_PEI_RSC_HANDLER_PPI { + EFI_PEI_RSC_HANDLER_REGISTER Register; + EFI_PEI_RSC_HANDLER_UNREGISTER Unregister; +} EFI_PEI_RSC_HANDLER_PPI; + +extern EFI_GUID gEfiPeiRscHandlerPpiGuid; + +#endif // __REPORT_STATUS_CODE_HANDLER_PPI_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset.h new file mode 100644 index 0000000000..db27cc320e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset.h @@ -0,0 +1,38 @@ +/** @file + This file declares Reset PPI used to reset the platform. + + This PPI is installed by some platform- or chipset-specific PEIM that + abstracts the Reset Service to other agents. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __RESET_PPI_H__ +#define __RESET_PPI_H__ + +#define EFI_PEI_RESET_PPI_GUID \ + { \ + 0xef398d58, 0x9dfd, 0x4103, {0xbf, 0x94, 0x78, 0xc6, 0xf4, 0xfe, 0x71, 0x2f } \ + } + +// +// EFI_PEI_RESET_PPI.ResetSystem() is equivalent to the +// PEI Service ResetSystem(). +// It is introduced in PIPeiCis.h. +// + +/// +/// This PPI provides provide a simple reset service. +/// +typedef struct { + EFI_PEI_RESET_SYSTEM ResetSystem; +} EFI_PEI_RESET_PPI; + +extern EFI_GUID gEfiPeiResetPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset2.h new file mode 100644 index 0000000000..ae49d33ab4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Reset2.h @@ -0,0 +1,32 @@ +/** @file + This file declares Reset2 PPI used to reset the platform. + + This PPI is installed by some platform- or chipset-specific PEIM that + abstracts the Reset Service to other agents. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.4. + +**/ + +#ifndef __RESET2_PPI_H__ +#define __RESET2_PPI_H__ + +#define EFI_PEI_RESET2_PPI_GUID \ + { \ + 0x6cc45765, 0xcce4, 0x42fd, {0xbc, 0x56, 0x1, 0x1a, 0xaa, 0xc6, 0xc9, 0xa8 } \ + } + +/// +/// This PPI provides provide a simple reset service. +/// +typedef struct _EFI_PEI_RESET2_PPI { + EFI_PEI_RESET2_SYSTEM ResetSystem; +} EFI_PEI_RESET2_PPI; + +extern EFI_GUID gEfiPeiReset2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/S3Resume2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/S3Resume2.h new file mode 100644 index 0000000000..eb051ae85c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/S3Resume2.h @@ -0,0 +1,86 @@ +/** @file + This PPI produces functions to interpret and execute the PI boot script table. + + This PPI is published by a PEIM and provides for the restoration of the platform's + configuration when resuming from the ACPI S3 power state. The ability to execute + the boot script may depend on the availability of other PPIs. For example, if + the boot script includes an SMBus command, this PEIM looks for the relevant PPI + that is able to execute that command. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: + Standards + +**/ + +#ifndef __PEI_S3_RESUME_PPI_H__ +#define __PEI_S3_RESUME_PPI_H__ + +/// +/// Global ID for EFI_PEI_S3_RESUME2_PPI +/// +#define EFI_PEI_S3_RESUME2_PPI_GUID \ + { \ + 0x6D582DBC, 0xDB85, 0x4514, {0x8F, 0xCC, 0x5A, 0xDF, 0x62, 0x27, 0xB1, 0x47 } \ + } + +/// +/// Forward declaration for EFI_PEI_S3_RESUME_PPI +/// +typedef struct _EFI_PEI_S3_RESUME2_PPI EFI_PEI_S3_RESUME2_PPI; + +/** + Restores the platform to its preboot configuration for an S3 resume and + jumps to the OS waking vector. + + This function will restore the platform to its pre-boot configuration that was + pre-stored in the boot script table and transfer control to OS waking vector. + Upon invocation, this function is responsible for locating the following + information before jumping to OS waking vector: + - ACPI tables + - boot script table + - any other information that it needs + + The S3RestoreConfig() function then executes the pre-stored boot script table + and transitions the platform to the pre-boot state. The boot script is recorded + during regular boot using the EFI_S3_SAVE_STATE_PROTOCOL.Write() and + EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions. Finally, this function + transfers control to the OS waking vector. If the OS supports only a real-mode + waking vector, this function will switch from flat mode to real mode before + jumping to the waking vector. If all platform pre-boot configurations are + successfully restored and all other necessary information is ready, this + function will never return and instead will directly jump to the OS waking + vector. If this function returns, it indicates that the attempt to resume + from the ACPI S3 sleep state failed. + + @param[in] This Pointer to this instance of the PEI_S3_RESUME_PPI + + @retval EFI_ABORTED Execution of the S3 resume boot script table failed. + @retval EFI_NOT_FOUND Some necessary information that is used for the S3 + resume boot path could not be located. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2)( + IN EFI_PEI_S3_RESUME2_PPI *This + ); + +/** + EFI_PEI_S3_RESUME2_PPI accomplishes the firmware S3 resume boot + path and transfers control to OS. +**/ +struct _EFI_PEI_S3_RESUME2_PPI { + /// + /// Restores the platform to its preboot configuration for an S3 resume and + /// jumps to the OS waking vector. + /// + EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2 S3RestoreConfig2; +}; + +extern EFI_GUID gEfiPeiS3Resume2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecHobData.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecHobData.h new file mode 100644 index 0000000000..85d966832d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecHobData.h @@ -0,0 +1,59 @@ +/** @file + This file declares Sec Hob Data PPI. + + This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list. + +Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.5. + +**/ + +#ifndef __SEC_HOB_DATA_PPI_H__ +#define __SEC_HOB_DATA_PPI_H__ + +#include + +#define EFI_SEC_HOB_DATA_PPI_GUID \ + { \ + 0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } \ + } + +typedef struct _EFI_SEC_HOB_DATA_PPI EFI_SEC_HOB_DATA_PPI; + +/** + Return a pointer to a buffer containing zero or more HOBs that + will be installed into the PEI HOB List. + + This function returns a pointer to a pointer to zero or more HOBs, + terminated with a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST. + Note: The HobList must not contain a EFI_HOB_HANDOFF_INFO_TABLE HOB (PHIT) HOB. + + @param[in] This Pointer to this PPI structure. + @param[out] HobList A pointer to a returned pointer to zero or more HOBs. + If no HOBs are to be returned, then the returned pointer + is a pointer to a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST. + + @retval EFI_SUCCESS This function completed successfully. + @retval EFI_NOT_FOUND No HOBS are available. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SEC_HOB_DATA_GET) ( + IN CONST EFI_SEC_HOB_DATA_PPI *This, + OUT EFI_HOB_GENERIC_HEADER **HobList +); + +/// +/// This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list. +/// +struct _EFI_SEC_HOB_DATA_PPI { + EFI_SEC_HOB_DATA_GET GetHobs; +}; + +extern EFI_GUID gEfiSecHobDataPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation.h new file mode 100644 index 0000000000..5246d2ac35 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation.h @@ -0,0 +1,182 @@ +/** @file + This file declares Sec Platform Information PPI. + + This service is the primary handoff state into the PEI Foundation. + The Security (SEC) component creates the early, transitory memory + environment and also encapsulates knowledge of at least the + location of the Boot Firmware Volume (BFV). + +Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __SEC_PLATFORM_INFORMATION_PPI_H__ +#define __SEC_PLATFORM_INFORMATION_PPI_H__ + +#include + +#define EFI_SEC_PLATFORM_INFORMATION_GUID \ + { \ + 0x6f8c2b35, 0xfef4, 0x448d, {0x82, 0x56, 0xe1, 0x1b, 0x19, 0xd6, 0x10, 0x77 } \ + } + +typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI; + + +/// +/// EFI_HEALTH_FLAGS +/// Contains information generated by microcode, hardware, and/or the Itanium +/// processor PAL code about the state of the processor upon reset. +/// +typedef union { + struct { + /// + /// A 2-bit field indicating self-test state after reset. + /// + UINT32 Status : 2; + /// + /// A 1-bit field indicating whether testing has occurred. + /// If this field is zero, the processor has not been tested, + /// and no further fields in the self-test State parameter are valid. + /// + UINT32 Tested : 1; + /// + /// Reserved 13 bits. + /// + UINT32 Reserved1 :13; + /// + /// A 1-bit field. If set to 1, this indicates that virtual + /// memory features are not available. + /// + UINT32 VirtualMemoryUnavailable : 1; + /// + /// A 1-bit field. If set to 1, this indicates that IA-32 execution + /// is not available. + /// + UINT32 Ia32ExecutionUnavailable : 1; + /// + /// A 1-bit field. If set to 1, this indicates that the floating + /// point unit is not available. + /// + UINT32 FloatingPointUnavailable : 1; + /// + /// A 1-bit field. If set to 1, this indicates miscellaneous + /// functional failure other than vm, ia, or fp. + /// The test status field provides additional information on + /// test failures when the State field returns a value of + /// performance restricted or functionally restricted. + /// The value returned is implementation dependent. + /// + UINT32 MiscFeaturesUnavailable : 1; + /// + /// Reserved 12 bits. + /// + UINT32 Reserved2 :12; + } Bits; + UINT32 Uint32; +} EFI_HEALTH_FLAGS; + +#define NORMAL_BOOT_CALL 0x0 +#define RECOVERY_CHECK_CALL 0x3 + +typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS; +typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS; +/// +/// The hand-off status structure for Itanium architecture. +/// +typedef struct { + /// + /// SALE_ENTRY state : 3 = Recovery_Check + /// and 0 = RESET or Normal_Boot phase. + /// + UINT8 BootPhase; + /// + /// Firmware status on entry to SALE. + /// + UINT8 FWStatus; + UINT16 Reserved1; + UINT32 Reserved2; + /// + /// Geographically significant unique processor ID assigned by PAL. + /// + UINT16 ProcId; + UINT16 Reserved3; + UINT8 IdMask; + UINT8 EidMask; + UINT16 Reserved4; + /// + /// Address to make PAL calls. + /// + UINT64 PalCallAddress; + /// + /// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET + /// return address, and if entry state is RESET, this contains + /// address for PAL_authentication call. + /// + UINT64 PalSpecialAddress; + /// + /// GR35 from PALE_EXIT state. + /// + UINT64 SelfTestStatus; + /// + /// GR37 from PALE_EXIT state. + /// + UINT64 SelfTestControl; + UINT64 MemoryBufferRequired; +} ITANIUM_HANDOFF_STATUS; + +/// +/// EFI_SEC_PLATFORM_INFORMATION_RECORD. +/// +typedef union { + IA32_HANDOFF_STATUS IA32HealthFlags; + X64_HANDOFF_STATUS x64HealthFlags; + ITANIUM_HANDOFF_STATUS ItaniumHealthFlags; +} EFI_SEC_PLATFORM_INFORMATION_RECORD; + +/** + This interface conveys state information out of the Security (SEC) phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the + PEI Foundation. As such, if the platform supports the built-in self test (BIST) on IA-32 Intel + architecture or the PAL-A handoff state for Itanium architecture, this information is encapsulated + into the data structure abstracted by this service. This information is collected for the boot-strap + processor (BSP) on IA-32. For Itanium architecture, it is available on all processors that execute + the PEI Foundation. + + @param PeiServices The pointer to the PEI Services Table. + @param StructureSize The pointer to the variable describing size of the input buffer. + @param PlatformInformationRecord The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to + hold the record is returned in StructureSize. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SEC_PLATFORM_INFORMATION)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord +); + + +/// +/// This service abstracts platform-specific information. It is necessary +/// to convey this information to the PEI Foundation so that it can +/// discover where to begin dispatching PEIMs. +/// +struct _EFI_SEC_PLATFORM_INFORMATION_PPI { + EFI_SEC_PLATFORM_INFORMATION PlatformInformation; +}; + + +extern EFI_GUID gEfiSecPlatformInformationPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation2.h new file mode 100644 index 0000000000..a61ece7991 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SecPlatformInformation2.h @@ -0,0 +1,79 @@ +/** @file + This file declares Sec Platform Information2 PPI. + + This service is the primary handoff state into the PEI Foundation. + This service abstracts platform-specific information for many CPU's. + +Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced from PI Version 1.4. + +**/ + +#ifndef __SEC_PLATFORM_INFORMATION2_PPI_H__ +#define __SEC_PLATFORM_INFORMATION2_PPI_H__ + +#include + +#define EFI_SEC_PLATFORM_INFORMATION2_GUID \ + { \ + 0x9e9f374b, 0x8f16, 0x4230, {0x98, 0x24, 0x58, 0x46, 0xee, 0x76, 0x6a, 0x97 } \ + } + +typedef struct _EFI_SEC_PLATFORM_INFORMATION2_PPI EFI_SEC_PLATFORM_INFORMATION2_PPI; + +/// +/// EFI_SEC_PLATFORM_INFORMATION_CPU. +/// +typedef struct { + UINT32 CpuLocation; + EFI_SEC_PLATFORM_INFORMATION_RECORD InfoRecord; +} EFI_SEC_PLATFORM_INFORMATION_CPU; + +/// +/// EFI_SEC_PLATFORM_INFORMATION_RECORD2. +/// +typedef struct { + /// + /// The CPU location would be the local APIC ID + /// + UINT32 NumberOfCpus; + EFI_SEC_PLATFORM_INFORMATION_CPU CpuInstance[1]; +} EFI_SEC_PLATFORM_INFORMATION_RECORD2; + +/** + This interface conveys state information out of the Security (SEC) phase into PEI. + + This service is published by the SEC phase. + + @param PeiServices The pointer to the PEI Services Table. + @param StructureSize The pointer to the variable describing size of the input buffer. + @param PlatformInformationRecord2 The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. The current buffer size needed to + hold the record is returned in StructureSize. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SEC_PLATFORM_INFORMATION2)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 +); + +/// +/// This service abstracts platform-specific information for many CPU's. +/// It is the multi-processor equivalent of PlatformInformation for +/// implementations that synchronize some, if not all CPU's in the SEC phase. +/// +struct _EFI_SEC_PLATFORM_INFORMATION2_PPI { + EFI_SEC_PLATFORM_INFORMATION2 PlatformInformation2; +}; + +extern EFI_GUID gEfiSecPlatformInformation2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Security2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Security2.h new file mode 100644 index 0000000000..887f6ef5fa --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Security2.h @@ -0,0 +1,95 @@ +/** @file + This file declares Pei Security2 PPI. + + This PPI is installed by some platform PEIM that abstracts the security + policy to the PEI Foundation, namely the case of a PEIM's authentication + state being returned during the PEI section extraction process. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __SECURITY2_PPI_H__ +#define __SECURITY2_PPI_H__ + +#define EFI_PEI_SECURITY2_PPI_GUID \ + { 0xdcd0be23, 0x9586, 0x40f4, { 0xb6, 0x43, 0x6, 0x52, 0x2c, 0xed, 0x4e, 0xde } } + + +typedef struct _EFI_PEI_SECURITY2_PPI EFI_PEI_SECURITY2_PPI; + +/** + Allows the platform builder to implement a security policy + in response to varying file authentication states. + + This service is published by some platform PEIM. The purpose of + this service is to expose a given platform's policy-based + response to the PEI Foundation. For example, if there is a PEIM + in a GUIDed encapsulation section and the extraction of the PEI + file section yields an authentication failure, there is no a + priori policy in the PEI Foundation. Specifically, this + situation leads to the question whether PEIMs that are either + not in GUIDed sections or are in sections whose authentication + fails should still be executed. + + @param PeiServices An indirect pointer to the PEI Services + Table published by the PEI Foundation. + @param This Interface pointer that implements the + particular EFI_PEI_SECURITY2_PPI instance. + @param AuthenticationStatus Authentication status of the file. + xx00 Image was not signed. + xxx1 Platform security policy override. + Assumes same meaning as 0010 (the image was signed, the + signature was tested, and the signature passed authentication test). + 0010 Image was signed, the signature was tested, + and the signature passed authentication test. + 0110 Image was signed and the signature was not tested. + 1010 Image was signed, the signature was tested, + and the signature failed the authentication test. + @param FvHandle Handle of the volume in which the file + resides. This allows different policies + depending on different firmware volumes. + @param FileHandle Handle of the file under review. + @param DeferExecution Pointer to a variable that alerts the + PEI Foundation to defer execution of a + PEIM. + + @retval EFI_SUCCESS The service performed its action successfully. + @retval EFI_SECURITY_VIOLATION The object cannot be trusted. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SECURITY_AUTHENTICATION_STATE)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_SECURITY2_PPI *This, + IN UINT32 AuthenticationStatus, + IN EFI_PEI_FV_HANDLE FvHandle, + IN EFI_PEI_FILE_HANDLE FileHandle, + IN OUT BOOLEAN *DeferExecution +); + +/// +/// This PPI is a means by which the platform builder can indicate +/// a response to a PEIM's authentication state. This can be in +/// the form of a requirement for the PEI Foundation to skip a +/// module using the DeferExecution Boolean output in the +/// AuthenticationState() member function. Alternately, the +/// Security PPI can invoke something like a cryptographic PPI +/// that hashes the PEIM contents to log attestations, for which +/// the FileHandle parameter in AuthenticationState() will be +/// useful. If this PPI does not exist, PEIMs will be considered +/// trusted. +/// +struct _EFI_PEI_SECURITY2_PPI { + EFI_PEI_SECURITY_AUTHENTICATION_STATE AuthenticationState; +}; + + +extern EFI_GUID gEfiPeiSecurity2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Smbus2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Smbus2.h new file mode 100644 index 0000000000..69f9fa181a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Smbus2.h @@ -0,0 +1,197 @@ +/** @file + This file declares Smbus2 PPI. + This PPI provides the basic I/O interfaces that a PEIM uses to access its + SMBus controller and the slave devices attached to it. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __PEI_SMBUS2_PPI_H__ +#define __PEI_SMBUS2_PPI_H__ + +#include + +#define EFI_PEI_SMBUS2_PPI_GUID \ + { 0x9ca93627, 0xb65b, 0x4324, { 0xa2, 0x2, 0xc0, 0xb4, 0x61, 0x76, 0x45, 0x43 } } + + +typedef struct _EFI_PEI_SMBUS2_PPI EFI_PEI_SMBUS2_PPI; + +/** + Executes an SMBus operation to an SMBus controller. Returns when either + the command has been executed or an error is encountered in doing the operation. + + @param This A pointer to the EFI_PEI_SMBUS2_PPI instance. + @param SlaveAddress The SMBUS hardware address to which the SMBUS device is preassigned or + allocated. + @param Command This command is transmitted by the SMBus host controller to the SMBus slave + device and the interpretation is SMBus slave device specific. + It can mean the offset to a list of functions inside + an SMBus slave device. Not all operations or slave devices support + this command's registers. + @param Operation Signifies which particular SMBus hardware protocol instance that it + will use to execute the SMBus transactions. + This SMBus hardware protocol is defined by the System Management Bus (SMBus) + Specification and is not related to UEFI. + @param PecCheck Defines if Packet Error Code (PEC) checking is required for this operation. + @param Length Signifies the number of bytes that this operation will do. + The maximum number of bytes can be revision specific and operation specific. + This parameter will contain the actual number of bytes that are executed + for this operation. Not all operations require this argument. + @param Buffer Contains the value of data to execute to the SMBus slave device. + Not all operations require this argument. + The length of this buffer is identified by Length. + + + @retval EFI_SUCCESS The last data that was returned from the access + matched the poll exit criteria. + @retval EFI_CRC_ERROR The checksum is not correct (PEC is incorrect) + @retval EFI_TIMEOUT Timeout expired before the operation was completed. + Timeout is determined by the SMBus host controller device. + @retval EFI_OUT_OF_RESOURCES The request could not be completed + due to a lack of resources. + @retval EFI_DEVICE_ERROR The request was not completed because + a failure reflected in the Host Status Register bit. + @retval EFI_INVALID_PARAMETER Operation is not defined in EFI_SMBUS_OPERATION. + Or Length/Buffer is NULL for operations except for EfiSmbusQuickRead and + EfiSmbusQuickWrite. Or Length is outside the range of valid values. + @retval EFI_UNSUPPORTED The SMBus operation or PEC is not supported. + @retval EFI_BUFFER_TOO_SMALL Buffer is not sufficient for this operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION)( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +); + +/** + The ArpDevice() function enumerates the entire bus or enumerates a specific + device that is identified by SmbusUdid. + + @param This A pointer to the EFI_PEI_SMBUS2_PPI instance. + @param ArpAll A Boolean expression that indicates if the host drivers need + to enumerate all the devices or enumerate only the device that is identified + by SmbusUdid. If ArpAll is TRUE, SmbusUdid and SlaveAddress are optional. + If ArpAll is FALSE, ArpDevice will enumerate SmbusUdid and the address + will be at SlaveAddress. + @param SmbusUdid The targeted SMBus Unique Device Identifier (UDID). + The UDID may not exist for SMBus devices with fixed addresses. + @param SlaveAddress The new SMBus address for the slave device for + which the operation is targeted. + + @retval EFI_SUCCESS The SMBus slave device address was set. + @retval EFI_INVALID_PARAMETER SlaveAddress is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed + due to a lack of resources. + @retval EFI_TIMEOUT The SMBus slave device did not respond. + @retval EFI_DEVICE_ERROR The request was not completed because the transaction failed. + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not implemented by this PEIM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SMBUS2_PPI_ARP_DEVICE)( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +); + +/** + The GetArpMap() function returns the mapping of all the SMBus devices + that are enumerated by the SMBus host driver. + + @param This A pointer to the EFI_PEI_SMBUS2_PPI instance. + @param Length Size of the buffer that contains the SMBus device map. + @param SmbusDeviceMap The pointer to the device map as enumerated + by the SMBus controller driver. + + @retval EFI_SUCCESS The device map was returned correctly in the buffer. + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not implemented by this PEIM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SMBUS2_PPI_GET_ARP_MAP)( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +); + +/** + CallBack function can be registered in EFI_PEI_SMBUS2_PPI_NOTIFY. + + @param This A pointer to the EFI_PEI_SMBUS2_PPI instance. + @param SlaveAddress The SMBUS hardware address to which the SMBUS + device is preassigned or allocated. + @param Data Data of the SMBus host notify command that + the caller wants to be called. + + @retval EFI_SUCCESS NotifyFunction has been registered. + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not + implemented by this PEIM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SMBUS_NOTIFY2_FUNCTION)( + IN CONST EFI_PEI_SMBUS2_PPI *SmbusPpi, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data +); + +/** + The Notify() function registers all the callback functions to allow the + bus driver to call these functions when the SlaveAddress/Data pair happens. + + @param This A pointer to the EFI_PEI_SMBUS2_PPI instance. + @param SlaveAddress Address that the host controller detects as + sending a message and calls all the registered functions. + @param Data Data that the host controller detects as sending a message + and calls all the registered functions. + @param NotifyFunction The function to call when the bus driver + detects the SlaveAddress and Data pair. + + @retval EFI_SUCCESS NotifyFunction has been registered. + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are not + implemented by this PEIM. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SMBUS2_PPI_NOTIFY)( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction +); + +/// +/// Provides the basic I/O interfaces that a PEIM uses to access +/// its SMBus controller and the slave devices attached to it. +/// +struct _EFI_PEI_SMBUS2_PPI { + EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION Execute; + EFI_PEI_SMBUS2_PPI_ARP_DEVICE ArpDevice; + EFI_PEI_SMBUS2_PPI_GET_ARP_MAP GetArpMap; + EFI_PEI_SMBUS2_PPI_NOTIFY Notify; + /// + /// Identifier which uniquely identifies this SMBus controller in a system. + /// + EFI_GUID Identifier; +}; + +extern EFI_GUID gEfiPeiSmbus2PpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Stall.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Stall.h new file mode 100644 index 0000000000..f0dc62a25d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/Stall.h @@ -0,0 +1,56 @@ +/** @file + This file declares Stall PPI. + + This ppi abstracts the blocking stall service to other agents. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __STALL_PPI_H__ +#define __STALL_PPI_H__ + +#define EFI_PEI_STALL_PPI_GUID \ + { 0x1f4c6f90, 0xb06b, 0x48d8, {0xa2, 0x01, 0xba, 0xe5, 0xf1, 0xcd, 0x7d, 0x56 } } + +typedef struct _EFI_PEI_STALL_PPI EFI_PEI_STALL_PPI; + +/** + The Stall() function provides a blocking stall for at least the number + of microseconds stipulated in the final argument of the API. + + @param PeiServices An indirect pointer to the PEI Services Table + published by the PEI Foundation. + @param This Pointer to the local data for the interface. + @param Microseconds Number of microseconds for which to stall. + + @retval EFI_SUCCESS The service provided at least the required delay. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_STALL)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ); + +/// +/// This service provides a simple, blocking stall with platform-specific resolution. +/// +struct _EFI_PEI_STALL_PPI { + /// + /// The resolution in microseconds of the stall services. + /// + UINTN Resolution; + + EFI_PEI_STALL Stall; +}; + +extern EFI_GUID gEfiPeiStallPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/StatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/StatusCode.h new file mode 100644 index 0000000000..29de3fc48b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/StatusCode.h @@ -0,0 +1,35 @@ +/** @file + This file declares Status Code PPI. + This ppi provides a service that allows PEIMs to report status codes. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __STATUS_CODE_PPI_H__ +#define __STATUS_CODE_PPI_H__ + +#define EFI_PEI_REPORT_PROGRESS_CODE_PPI_GUID \ + { 0x229832d3, 0x7a30, 0x4b36, {0xb8, 0x27, 0xf4, 0xc, 0xb7, 0xd4, 0x54, 0x36 } } + +// +// EFI_PEI_PROGRESS_CODE_PPI.ReportStatusCode() is equivalent to the +// PEI Service ReportStatusCode(). +// It is introduced in PIPeiCis.h. +// + +/// +/// This PPI provides the service to report status code. +/// There can be only one instance of this service in the system. +/// +typedef struct { + EFI_PEI_REPORT_STATUS_CODE ReportStatusCode; +} EFI_PEI_PROGRESS_CODE_PPI; + +extern EFI_GUID gEfiPeiStatusCodePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SuperIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SuperIo.h new file mode 100644 index 0000000000..319155f5fe --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/SuperIo.h @@ -0,0 +1,183 @@ +/** @file + This PPI provides the super I/O register access functionality. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is from PI Version 1.2.1. + +**/ + +#ifndef __EFI_SUPER_IO_PPI_H__ +#define __EFI_SUPER_IO_PPI_H__ + +#include + +#define EFI_SIO_PPI_GUID \ + { \ + 0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22} \ + } + +typedef struct _EFI_SIO_PPI EFI_SIO_PPI; +typedef struct _EFI_SIO_PPI *PEFI_SIO_PPI; + +typedef UINT16 EFI_SIO_REGISTER; +#define EFI_SIO_REG(ldn,reg) (EFI_SIO_REGISTER) (((ldn) << 8) | reg) +#define EFI_SIO_LDN_GLOBAL 0xFF + +/** + Read a Super I/O register. + + The register is specified as an 8-bit logical device number and an 8-bit + register value. The logical device numbers for specific SIO devices can be + determined using the Info member of the PPI structure. + + @param PeiServices A pointer to a pointer to the PEI Services. + @param This A pointer to this instance of the EFI_SIO_PPI. + @param ExitCfgMode A boolean specifying whether the driver should turn on + configuration mode (FALSE) or turn off configuration mode + (TRUE) after completing the read operation. The driver must + track the current state of the configuration mode (if any) + and turn on configuration mode (if necessary) prior to + register access. + @param Register A value specifying the logical device number (bits 15:8) + and the register to read (bits 7:0). The logical device + number of EFI_SIO_LDN_GLOBAL indicates that global + registers will be used. + @param IoData A pointer to the returned register value. + + @retval EFI_SUCCESS Success. + @retval EFI_TIMEOUT The register could not be read in the a reasonable + amount of time. The exact time is device-specific. + @retval EFI_INVALID_PARAMETERS Register was out of range for this device. + @retval EFI_INVALID_PARAMETERS IoData was NULL + @retval EFI_DEVICE_ERROR There was a device fault or the device was not present. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SIO_REGISTER_READ)( + IN EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_SIO_PPI *This, + IN BOOLEAN ExitCfgMode, + IN EFI_SIO_REGISTER Register, + OUT UINT8 *IoData + ); + +/** + Write a Super I/O register. + + The register is specified as an 8-bit logical device number and an 8-bit register + value. The logical device numbers for specific SIO devices can be determined + using the Info member of the PPI structure. + + @param PeiServices A pointer to a pointer to the PEI Services. + @param This A pointer to this instance of the EFI_SIO_PPI. + @param ExitCfgMode A boolean specifying whether the driver should turn on + configuration mode (FALSE) or turn off configuration mode + (TRUE) after completing the read operation. The driver must + track the current state of the configuration mode (if any) + and turn on configuration mode (if necessary) prior to + register access. + @param Register A value specifying the logical device number (bits 15:8) + and the register to read (bits 7:0). The logical device + number of EFI_SIO_LDN_GLOBAL indicates that global + registers will be used. + @param IoData A pointer to the returned register value. + + @retval EFI_SUCCESS Success. + @retval EFI_TIMEOUT The register could not be read in the a reasonable + amount of time. The exact time is device-specific. + @retval EFI_INVALID_PARAMETERS Register was out of range for this device. + @retval EFI_INVALID_PARAMETERS IoData was NULL + @retval EFI_DEVICE_ERROR There was a device fault or the device was not present. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SIO_REGISTER_WRITE)( + IN EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_SIO_PPI *This, + IN BOOLEAN ExitCfgMode, + IN EFI_SIO_REGISTER Register, + IN UINT8 IoData + ); + +/** + Provides an interface for a table based programming of the Super I/O registers. + + The Modify() function provides an interface for table based programming of the + Super I/O registers. This function can be used to perform programming of + multiple Super I/O registers with a single function call. For each table entry, + the Register is read, its content is bitwise ANDed with AndMask, and then ORed + with OrMask before being written back to the Register. The Super I/O driver + must track the current state of the Super I/O and enable the configuration mode + of Super I/O if necessary prior to table processing. Once the table is processed, + the Super I/O device must be returned to the original state. + + @param PeiServices A pointer to a pointer to the PEI Services. + @param This A pointer to this instance of the EFI_SIO_PPI. + @param Command A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY + structures. Each structure specifies a single Super I/O register + modify operation. + @param NumberOfCommands The number of elements in the Command array. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETERS Command is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PEI_SIO_REGISTER_MODIFY)( + IN EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_SIO_PPI *This, + IN CONST EFI_SIO_REGISTER_MODIFY *Command, + IN UINTN NumberOfCommands + ); + +/// +/// Specifies the end of the information list. +/// +#define EFI_ACPI_PNP_HID_END EFI_PNP_ID (0x0000) + +typedef UINT32 EFI_ACPI_HID; +typedef UINT32 EFI_ACPI_UID; +#pragma pack(1) +typedef struct _EFI_SIO_INFO { + EFI_ACPI_HID Hid; + EFI_ACPI_UID Uid; + UINT8 Ldn; +} EFI_SIO_INFO, *PEFI_SIO_INFO; +#pragma pack() + +/// +/// This PPI provides low-level access to Super I/O registers using Read() and +/// Write(). It also uniquely identifies this Super I/O controller using a GUID +/// and provides mappings between ACPI style PNP IDs and the logical device numbers. +/// There is one instance of this PPI per Super I/O device. +/// +struct _EFI_SIO_PPI { + /// + /// This function reads a register's value from the Super I/O controller. + /// + EFI_PEI_SIO_REGISTER_READ Read; + /// + /// This function writes a value to a register in the Super I/O controller. + /// + EFI_PEI_SIO_REGISTER_WRITE Write; + /// + /// This function modifies zero or more registers in the Super I/O controller + /// using a table. + /// + EFI_PEI_SIO_REGISTER_MODIFY Modify; + /// + /// This GUID uniquely identifies the Super I/O controller. + /// + EFI_GUID SioGuid; + /// + /// This pointer is to an array which maps EISA identifiers to logical devices numbers. + /// + PEFI_SIO_INFO Info; +}; + +extern EFI_GUID gEfiSioPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamDone.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamDone.h new file mode 100644 index 0000000000..7af15586bd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamDone.h @@ -0,0 +1,46 @@ +/** @file + This file declares Temporary RAM Done PPI. + The PPI that provides a service to disable the use of Temporary RAM. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.2.1. + +**/ + +#ifndef __TEMPORARY_RAM_DONE_H__ +#define __TEMPORARY_RAM_DONE_H__ + +#define EFI_PEI_TEMPORARY_RAM_DONE_PPI_GUID \ + { 0xceab683c, 0xec56, 0x4a2d, { 0xa9, 0x6, 0x40, 0x53, 0xfa, 0x4e, 0x9c, 0x16 } } + +/** + TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked + by the PEI Foundation after the EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI is installed. + + @retval EFI_SUCCESS Use of Temporary RAM was disabled. + @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_PEI_TEMPORARY_RAM_DONE) ( + VOID + ); + +/// +/// This is an optional PPI that may be produced by SEC or a PEIM. If present, it provide a service to +/// disable the use of Temporary RAM. This service may only be called by the PEI Foundation after the +/// transition from Temporary RAM to Permanent RAM is complete. This PPI provides an alternative +/// to the Temporary RAM Migration PPI for system architectures that allow Temporary RAM and +/// Permanent RAM to be enabled and accessed at the same time with no side effects. +/// +typedef struct _EFI_PEI_TEMPORARY_RAM_DONE_PPI { + EFI_PEI_TEMPORARY_RAM_DONE TemporaryRamDone; +} EFI_PEI_TEMPORARY_RAM_DONE_PPI; + +extern EFI_GUID gEfiTemporaryRamDonePpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamSupport.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamSupport.h new file mode 100644 index 0000000000..e904d65671 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/TemporaryRamSupport.h @@ -0,0 +1,60 @@ +/** @file + This file declares Temporary RAM Support PPI. + This Ppi provides the service that migrates temporary RAM into permanent memory. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.0. + +**/ + +#ifndef __TEMPORARY_RAM_SUPPORT_H__ +#define __TEMPORARY_RAM_SUPPORT_H__ + +/// +/// Note: The GUID name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID is different from the current +/// PI 1.2 spec. +/// +#define EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID \ + { 0xdbe23aa9, 0xa345, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} } + + +/** + This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into + permanent memory. + + @param PeiServices Pointer to the PEI Services Table. + @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the + Temporary RAM contents. + @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the + Temporary RAM contents. + @param CopySize Amount of memory to migrate from temporary to permanent memory. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when + TemporaryMemoryBase > PermanentMemoryBase. + +**/ +typedef +EFI_STATUS +(EFIAPI * TEMPORARY_RAM_MIGRATION)( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize +); + +/// +/// This service abstracts the ability to migrate contents of the platform early memory store. +/// Note: The name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI is different from the current PI 1.2 spec. +/// This PPI was optional. +/// +typedef struct { + TEMPORARY_RAM_MIGRATION TemporaryRamMigration; +} EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI; + +extern EFI_GUID gEfiTemporaryRamSupportPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/VectorHandoffInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/VectorHandoffInfo.h new file mode 100644 index 0000000000..52c904a4e1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Ppi/VectorHandoffInfo.h @@ -0,0 +1,69 @@ +/** @file + This file declares Vector Handoff Info PPI that describes an array of + interrupt and/or exception vectors that are in use and need to persist. + + This is an optional PPI that may be produced by SEC. If present, it provides + a description of the interrupt and/or exception vectors that were established + in the SEC Phase and need to persist into PEI and DXE. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is introduced in PI Version 1.2.1. + +**/ + +#ifndef __VECTOR_HANDOFF_INFO_H__ +#define __VECTOR_HANDOFF_INFO_H__ + +/// +/// NOTE: EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID can also be used in the PEI Phase +/// to build a GUIDed HOB that contains an array of EFI_VECTOR_HANDOFF_INFO. +/// +#define EFI_PEI_VECTOR_HANDOFF_INFO_PPI_GUID \ + { 0x3cd652b4, 0x6d33, 0x4dce, { 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca }} + +/// +/// Vector Handoff Info Attributes +///@{ +#define EFI_VECTOR_HANDOFF_DO_NOT_HOOK 0x00000000 +#define EFI_VECTOR_HANDOFF_HOOK_BEFORE 0x00000001 +#define EFI_VECTOR_HANDOFF_HOOK_AFTER 0x00000002 +#define EFI_VECTOR_HANDOFF_LAST_ENTRY 0x80000000 +///@} + +/// +/// EFI_VECTOR_HANDOFF_INFO entries that describes the interrupt and/or +/// exception vectors in use in the PEI Phase. +/// +typedef struct { + // + // The interrupt or exception vector that is in use and must be preserved. + // + UINT32 VectorNumber; + // + // A bitmask that describes the attributes of the interrupt or exception vector. + // + UINT32 Attribute; + // + // The GUID identifies the party who created the entry. For the + // EFI_VECTOR_HANDOFF_DO_NOT_HOOK case, this establishes the single owner. + // + EFI_GUID Owner; +} EFI_VECTOR_HANDOFF_INFO; + +/// +/// Provides a description of the interrupt and/or exception vectors that +/// were established in the SEC Phase and need to persist into PEI and DXE. +/// +typedef struct _EFI_PEI_VECTOR_HANDOFF_INFO_PPI { + // + // Pointer to an array of interrupt and /or exception vectors. + // + EFI_VECTOR_HANDOFF_INFO *Info; +} EFI_PEI_VECTOR_HANDOFF_INFO_PPI; + +extern EFI_GUID gEfiVectorHandoffInfoPpiGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AbsolutePointer.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AbsolutePointer.h new file mode 100644 index 0000000000..ff8f37b27e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AbsolutePointer.h @@ -0,0 +1,202 @@ +/** @file + The file provides services that allow information about an + absolute pointer device to be retrieved. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.3. + +**/ + +#ifndef __ABSOLUTE_POINTER_H__ +#define __ABSOLUTE_POINTER_H__ + + +#define EFI_ABSOLUTE_POINTER_PROTOCOL_GUID \ + { 0x8D59D32B, 0xC655, 0x4AE9, { 0x9B, 0x15, 0xF2, 0x59, 0x04, 0x99, 0x2A, 0x43 } } + + +typedef struct _EFI_ABSOLUTE_POINTER_PROTOCOL EFI_ABSOLUTE_POINTER_PROTOCOL; + + +//******************************************************* +// EFI_ABSOLUTE_POINTER_MODE +//******************************************************* + + +/** + The following data values in the EFI_ABSOLUTE_POINTER_MODE + interface are read-only and are changed by using the appropriate + interface functions. +**/ +typedef struct { + UINT64 AbsoluteMinX; ///< The Absolute Minimum of the device on the x-axis + UINT64 AbsoluteMinY; ///< The Absolute Minimum of the device on the y axis. + UINT64 AbsoluteMinZ; ///< The Absolute Minimum of the device on the z-axis + UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the + ///< AbsoluteMinX is 0, then the pointer device does not support a xaxis + UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the + ///< AbsoluteMinX is 0, then the pointer device does not support a yaxis. + UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the + ///< AbsoluteMinX is 0, then the pointer device does not support a zaxis + UINT32 Attributes; ///< The following bits are set as needed (or'd together) to indicate the + ///< capabilities of the device supported. The remaining bits are undefined + ///< and should be 0 +} EFI_ABSOLUTE_POINTER_MODE; + +/// +/// If set, indicates this device supports an alternate button input. +/// +#define EFI_ABSP_SupportsAltActive 0x00000001 + +/// +/// If set, indicates this device returns pressure data in parameter CurrentZ. +/// +#define EFI_ABSP_SupportsPressureAsZ 0x00000002 + + +/** + This function resets the pointer device hardware. As part of + initialization process, the firmware/device will make a quick + but reasonable attempt to verify that the device is + functioning. If the ExtendedVerification flag is TRUE the + firmware may take an extended amount of time to verify the + device is operating on reset. Otherwise the reset operation is + to occur as quickly as possible. The hardware verification + process is not defined by this specification and is left up to + the platform firmware or driver to implement. + + @param This A pointer to the EFI_ABSOLUTE_POINTER_PROTOCOL + instance. + + @param ExtendedVerification Indicates that the driver may + perform a more exhaustive + verification operation of the + device during reset. + + @retval EFI_SUCCESS The device was reset. + + @retval EFI_DEVICE_ERROR The device is not functioning + correctly and could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ABSOLUTE_POINTER_RESET)( + IN EFI_ABSOLUTE_POINTER_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +); + +/// +/// This bit is set if the touch sensor is active. +/// +#define EFI_ABSP_TouchActive 0x00000001 + +/// +/// This bit is set if the alt sensor, such as pen-side button, is active +/// +#define EFI_ABS_AltActive 0x00000002 + + +/** + Definition of EFI_ABSOLUTE_POINTER_STATE. +**/ +typedef struct { + /// + /// The unsigned position of the activation on the x axis. If the AboluteMinX + /// and the AboluteMaxX fields of the EFI_ABSOLUTE_POINTER_MODE structure are + /// both 0, then this pointer device does not support an x-axis, and this field + /// must be ignored. + /// + UINT64 CurrentX; + + /// + /// The unsigned position of the activation on the y axis. If the AboluteMinY + /// and the AboluteMaxY fields of the EFI_ABSOLUTE_POINTER_MODE structure are + /// both 0, then this pointer device does not support an y-axis, and this field + /// must be ignored. + /// + UINT64 CurrentY; + + /// + /// The unsigned position of the activation on the z axis, or the pressure + /// measurement. If the AboluteMinZ and the AboluteMaxZ fields of the + /// EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device + /// does not support an z-axis, and this field must be ignored. + /// + UINT64 CurrentZ; + + /// + /// Bits are set to 1 in this structure item to indicate that device buttons are + /// active. + /// + UINT32 ActiveButtons; +} EFI_ABSOLUTE_POINTER_STATE; + +/** + The GetState() function retrieves the current state of a pointer + device. This includes information on the active state associated + with the pointer device and the current position of the axes + associated with the pointer device. If the state of the pointer + device has not changed since the last call to GetState(), then + EFI_NOT_READY is returned. If the state of the pointer device + has changed since the last call to GetState(), then the state + information is placed in State, and EFI_SUCCESS is returned. If + a device error occurs while attempting to retrieve the state + information, then EFI_DEVICE_ERROR is returned. + + + @param This A pointer to the EFI_ABSOLUTE_POINTER_PROTOCOL + instance. + + @param State A pointer to the state information on the + pointer device. + + @retval EFI_SUCCESS The state of the pointer device was + returned in State. + + @retval EFI_NOT_READY The state of the pointer device has not + changed since the last call to GetState(). + + @retval EFI_DEVICE_ERROR A device error occurred while + attempting to retrieve the pointer + device's current state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ABSOLUTE_POINTER_GET_STATE)( + IN EFI_ABSOLUTE_POINTER_PROTOCOL *This, + OUT EFI_ABSOLUTE_POINTER_STATE *State +); + + +/// +/// The EFI_ABSOLUTE_POINTER_PROTOCOL provides a set of services +/// for a pointer device that can be used as an input device from an +/// application written to this specification. The services include +/// the ability to: reset the pointer device, retrieve the state of +/// the pointer device, and retrieve the capabilities of the pointer +/// device. The service also provides certain data items describing the device. +/// +struct _EFI_ABSOLUTE_POINTER_PROTOCOL { + EFI_ABSOLUTE_POINTER_RESET Reset; + EFI_ABSOLUTE_POINTER_GET_STATE GetState; + /// + /// Event to use with WaitForEvent() to wait for input from the pointer device. + /// + EFI_EVENT WaitForInput; + /// + /// Pointer to EFI_ABSOLUTE_POINTER_MODE data. + /// + EFI_ABSOLUTE_POINTER_MODE *Mode; +}; + + +extern EFI_GUID gEfiAbsolutePointerProtocolGuid; + + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h new file mode 100644 index 0000000000..e837167605 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h @@ -0,0 +1,263 @@ +/** @file + This protocol provides services for creating ACPI system description tables. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.2. + +**/ + +#ifndef __ACPI_SYSTEM_DESCRIPTION_TABLE_H___ +#define __ACPI_SYSTEM_DESCRIPTION_TABLE_H___ + +#define EFI_ACPI_SDT_PROTOCOL_GUID \ + { 0xeb97088e, 0xcfdf, 0x49c6, { 0xbe, 0x4b, 0xd9, 0x6, 0xa5, 0xb2, 0xe, 0x86 }} + +typedef UINT32 EFI_ACPI_TABLE_VERSION; +typedef VOID *EFI_ACPI_HANDLE; + +#define EFI_ACPI_TABLE_VERSION_NONE (1 << 0) +#define EFI_ACPI_TABLE_VERSION_1_0B (1 << 1) +#define EFI_ACPI_TABLE_VERSION_2_0 (1 << 2) +#define EFI_ACPI_TABLE_VERSION_3_0 (1 << 3) +#define EFI_ACPI_TABLE_VERSION_4_0 (1 << 4) +#define EFI_ACPI_TABLE_VERSION_5_0 (1 << 5) + +typedef UINT32 EFI_ACPI_DATA_TYPE; +#define EFI_ACPI_DATA_TYPE_NONE 0 +#define EFI_ACPI_DATA_TYPE_OPCODE 1 +#define EFI_ACPI_DATA_TYPE_NAME_STRING 2 +#define EFI_ACPI_DATA_TYPE_OP 3 +#define EFI_ACPI_DATA_TYPE_UINT 4 +#define EFI_ACPI_DATA_TYPE_STRING 5 +#define EFI_ACPI_DATA_TYPE_CHILD 6 + +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + CHAR8 OemId[6]; + CHAR8 OemTableId[8]; + UINT32 OemRevision; + UINT32 CreatorId; + UINT32 CreatorRevision; +} EFI_ACPI_SDT_HEADER; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_NOTIFICATION_FN)( + IN EFI_ACPI_SDT_HEADER *Table, ///< A pointer to the ACPI table header. + IN EFI_ACPI_TABLE_VERSION Version, ///< The ACPI table's version. + IN UINTN TableKey ///< The table key for this ACPI table. +); + +/** + Returns a requested ACPI table. + + The GetAcpiTable() function returns a pointer to a buffer containing the ACPI table associated + with the Index that was input. The following structures are not considered elements in the list of + ACPI tables: + - Root System Description Pointer (RSD_PTR) + - Root System Description Table (RSDT) + - Extended System Description Table (XSDT) + Version is updated with a bit map containing all the versions of ACPI of which the table is a + member. For tables installed via the EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable() interface, + the function returns the value of EFI_ACPI_STD_PROTOCOL.AcpiVersion. + + @param[in] Index The zero-based index of the table to retrieve. + @param[out] Table Pointer for returning the table buffer. + @param[out] Version On return, updated with the ACPI versions to which this table belongs. Type + EFI_ACPI_TABLE_VERSION is defined in "Related Definitions" in the + EFI_ACPI_SDT_PROTOCOL. + @param[out] TableKey On return, points to the table key for the specified ACPI system definition table. + This is identical to the table key used in the EFI_ACPI_TABLE_PROTOCOL. + The TableKey can be passed to EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable() + to uninstall the table. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The requested index is too large and a table was not found. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_GET_ACPI_TABLE2)( + IN UINTN Index, + OUT EFI_ACPI_SDT_HEADER **Table, + OUT EFI_ACPI_TABLE_VERSION *Version, + OUT UINTN *TableKey +); + +/** + Register or unregister a callback when an ACPI table is installed. + + This function registers or unregisters a function which will be called whenever a new ACPI table is + installed. + + @param[in] Register If TRUE, then the specified function will be registered. If FALSE, then the specified + function will be unregistered. + @param[in] Notification Points to the callback function to be registered or unregistered. + + @retval EFI_SUCCESS Callback successfully registered or unregistered. + @retval EFI_INVALID_PARAMETER Notification is NULL + @retval EFI_INVALID_PARAMETER Register is FALSE and Notification does not match a known registration function. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_REGISTER_NOTIFY)( + IN BOOLEAN Register, + IN EFI_ACPI_NOTIFICATION_FN Notification +); + +/** + Create a handle from an ACPI opcode + + @param[in] Buffer Points to the ACPI opcode. + @param[out] Handle Upon return, holds the handle. + + @retval EFI_SUCCESS Success + @retval EFI_INVALID_PARAMETER Buffer is NULL or Handle is NULL or Buffer points to an + invalid opcode. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_OPEN)( + IN VOID *Buffer, + OUT EFI_ACPI_HANDLE *Handle +); + +/** + Create a handle for the first ACPI opcode in an ACPI system description table. + + @param[in] TableKey The table key for the ACPI table, as returned by GetTable(). + @param[out] Handle On return, points to the newly created ACPI handle. + + @retval EFI_SUCCESS Handle created successfully. + @retval EFI_NOT_FOUND TableKey does not refer to a valid ACPI table. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_OPEN_SDT)( + IN UINTN TableKey, + OUT EFI_ACPI_HANDLE *Handle +); + +/** + Close an ACPI handle. + + @param[in] Handle Returns the handle. + + @retval EFI_SUCCESS Success + @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_CLOSE)( + IN EFI_ACPI_HANDLE Handle +); + +/** + Return the child ACPI objects. + + @param[in] ParentHandle Parent handle. + @param[in, out] Handle On entry, points to the previously returned handle or NULL to start with the first + handle. On return, points to the next returned ACPI handle or NULL if there are no + child objects. + + @retval EFI_SUCCESS Success + @retval EFI_INVALID_PARAMETER ParentHandle is NULL or does not refer to a valid ACPI object. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_GET_CHILD)( + IN EFI_ACPI_HANDLE ParentHandle, + IN OUT EFI_ACPI_HANDLE *Handle +); + +/** + Retrieve information about an ACPI object. + + @param[in] Handle ACPI object handle. + @param[in] Index Index of the data to retrieve from the object. In general, indexes read from left-to-right + in the ACPI encoding, with index 0 always being the ACPI opcode. + @param[out] DataType Points to the returned data type or EFI_ACPI_DATA_TYPE_NONE if no data exists + for the specified index. + @param[out] Data Upon return, points to the pointer to the data. + @param[out] DataSize Upon return, points to the size of Data. + + @retval +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_GET_OPTION)( + IN EFI_ACPI_HANDLE Handle, + IN UINTN Index, + OUT EFI_ACPI_DATA_TYPE *DataType, + OUT CONST VOID **Data, + OUT UINTN *DataSize +); + +/** + Change information about an ACPI object. + + @param[in] Handle ACPI object handle. + @param[in] Index Index of the data to retrieve from the object. In general, indexes read from left-to-right + in the ACPI encoding, with index 0 always being the ACPI opcode. + @param[in] Data Points to the data. + @param[in] DataSize The size of the Data. + + @retval EFI_SUCCESS Success + @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object. + @retval EFI_BAD_BUFFER_SIZE Data cannot be accommodated in the space occupied by + the option. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_SET_OPTION)( + IN EFI_ACPI_HANDLE Handle, + IN UINTN Index, + IN CONST VOID *Data, + IN UINTN DataSize +); + +/** + Returns the handle of the ACPI object representing the specified ACPI path + + @param[in] HandleIn Points to the handle of the object representing the starting point for the path search. + @param[in] AcpiPath Points to the ACPI path, which conforms to the ACPI encoded path format. + @param[out] HandleOut On return, points to the ACPI object which represents AcpiPath, relative to + HandleIn. + + @retval EFI_SUCCESS Success + @retval EFI_INVALID_PARAMETER HandleIn is NULL or does not refer to a valid ACPI object. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_FIND_PATH)( + IN EFI_ACPI_HANDLE HandleIn, + IN VOID *AcpiPath, + OUT EFI_ACPI_HANDLE *HandleOut +); + +typedef struct _EFI_ACPI_SDT_PROTOCOL { + /// + /// A bit map containing all the ACPI versions supported by this protocol. + /// + EFI_ACPI_TABLE_VERSION AcpiVersion; + EFI_ACPI_GET_ACPI_TABLE2 GetAcpiTable; + EFI_ACPI_REGISTER_NOTIFY RegisterNotify; + EFI_ACPI_OPEN Open; + EFI_ACPI_OPEN_SDT OpenSdt; + EFI_ACPI_CLOSE Close; + EFI_ACPI_GET_CHILD GetChild; + EFI_ACPI_GET_OPTION GetOption; + EFI_ACPI_SET_OPTION SetOption; + EFI_ACPI_FIND_PATH FindPath; +} EFI_ACPI_SDT_PROTOCOL; + +extern EFI_GUID gEfiAcpiSdtProtocolGuid; + +#endif // __ACPI_SYSTEM_DESCRIPTION_TABLE_H___ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiTable.h new file mode 100644 index 0000000000..a428ea1b9d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AcpiTable.h @@ -0,0 +1,124 @@ +/** @file + The file provides the protocol to install or remove an ACPI + table from a platform. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.3. + +**/ + +#ifndef __ACPI_TABLE_H___ +#define __ACPI_TABLE_H___ + +#define EFI_ACPI_TABLE_PROTOCOL_GUID \ + { 0xffe06bdd, 0x6107, 0x46a6, { 0x7b, 0xb2, 0x5a, 0x9c, 0x7e, 0xc5, 0x27, 0x5c }} + + +typedef struct _EFI_ACPI_TABLE_PROTOCOL EFI_ACPI_TABLE_PROTOCOL; + +/** + + The InstallAcpiTable() function allows a caller to install an + ACPI table. When successful, the table will be linked by the + RSDT/XSDT. AcpiTableBuffer specifies the table to be installed. + InstallAcpiTable() will make a copy of the table and insert the + copy into the RSDT/XSDT. InstallAcpiTable() must insert the new + table at the end of the RSDT/XSDT. To prevent namespace + collision, ACPI tables may be created using UEFI ACPI table + format. If this protocol is used to install a table with a + signature already present in the system, the new table will not + replace the existing table. It is a platform implementation + decision to add a new table with a signature matching an + existing table or disallow duplicate table signatures and + return EFI_ACCESS_DENIED. On successful output, TableKey is + initialized with a unique key. Its value may be used in a + subsequent call to UninstallAcpiTable to remove an ACPI table. + If an EFI application is running at the time of this call, the + relevant EFI_CONFIGURATION_TABLE pointer to the RSDT is no + longer considered valid. + + + @param This A pointer to a EFI_ACPI_TABLE_PROTOCOL. + + @param AcpiTableBuffer A pointer to a buffer containing the + ACPI table to be installed. + + @param AcpiTableBufferSize Specifies the size, in bytes, of + the AcpiTableBuffer buffer. + + + @param TableKey Returns a key to refer to the ACPI table. + + @retval EFI_SUCCESS The table was successfully inserted + + @retval EFI_INVALID_PARAMETER Either AcpiTableBuffer is NULL, + TableKey is NULL, or + AcpiTableBufferSize and the size + field embedded in the ACPI table + pointed to by AcpiTableBuffer + are not in sync. + + @retval EFI_OUT_OF_RESOURCES Insufficient resources exist to + complete the request. + @retval EFI_ACCESS_DENIED The table signature matches a table already + present in the system and platform policy + does not allow duplicate tables of this type. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_TABLE_INSTALL_ACPI_TABLE)( + IN EFI_ACPI_TABLE_PROTOCOL *This, + IN VOID *AcpiTableBuffer, + IN UINTN AcpiTableBufferSize, + OUT UINTN *TableKey +); + + +/** + + The UninstallAcpiTable() function allows a caller to remove an + ACPI table. The routine will remove its reference from the + RSDT/XSDT. A table is referenced by the TableKey parameter + returned from a prior call to InstallAcpiTable(). If an EFI + application is running at the time of this call, the relevant + EFI_CONFIGURATION_TABLE pointer to the RSDT is no longer + considered valid. + + @param This A pointer to a EFI_ACPI_TABLE_PROTOCOL. + + @param TableKey Specifies the table to uninstall. The key was + returned from InstallAcpiTable(). + + @retval EFI_SUCCESS The table was successfully inserted + + @retval EFI_NOT_FOUND TableKey does not refer to a valid key + for a table entry. + + @retval EFI_OUT_OF_RESOURCES Insufficient resources exist to + complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE)( + IN EFI_ACPI_TABLE_PROTOCOL *This, + IN UINTN TableKey +); + +/// +/// The EFI_ACPI_TABLE_PROTOCOL provides the ability for a component +/// to install and uninstall ACPI tables from a platform. +/// +struct _EFI_ACPI_TABLE_PROTOCOL { + EFI_ACPI_TABLE_INSTALL_ACPI_TABLE InstallAcpiTable; + EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE UninstallAcpiTable; +}; + +extern EFI_GUID gEfiAcpiTableProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AdapterInformation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AdapterInformation.h new file mode 100644 index 0000000000..c0cff5ae05 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AdapterInformation.h @@ -0,0 +1,254 @@ +/** @file + EFI Adapter Information Protocol definition. + The EFI Adapter Information Protocol is used to dynamically and quickly discover + or set device information for an adapter. + + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.4 + +**/ + +#ifndef __EFI_ADAPTER_INFORMATION_PROTOCOL_H__ +#define __EFI_ADAPTER_INFORMATION_PROTOCOL_H__ + + +#define EFI_ADAPTER_INFORMATION_PROTOCOL_GUID \ + { \ + 0xE5DD1403, 0xD622, 0xC24E, {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 } \ + } + +#define EFI_ADAPTER_INFO_MEDIA_STATE_GUID \ + { \ + 0xD7C74207, 0xA831, 0x4A26, {0xB1, 0xF5, 0xD1, 0x93, 0x06, 0x5C, 0xE8, 0xB6 } \ + } + +#define EFI_ADAPTER_INFO_NETWORK_BOOT_GUID \ + { \ + 0x1FBD2960, 0x4130, 0x41E5, {0x94, 0xAC, 0xD2, 0xCF, 0x03, 0x7F, 0xB3, 0x7C } \ + } + +#define EFI_ADAPTER_INFO_SAN_MAC_ADDRESS_GUID \ + { \ + 0x114da5ef, 0x2cf1, 0x4e12, {0x9b, 0xbb, 0xc4, 0x70, 0xb5, 0x52, 0x5, 0xd9 } \ + } + +#define EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT_GUID \ + { \ + 0x4bd56be3, 0x4975, 0x4d8a, {0xa0, 0xad, 0xc4, 0x91, 0x20, 0x4b, 0x5d, 0x4d} \ + } + +#define EFI_ADAPTER_INFO_MEDIA_TYPE_GUID \ + { \ + 0x8484472f, 0x71ec, 0x411a, { 0xb3, 0x9c, 0x62, 0xcd, 0x94, 0xd9, 0x91, 0x6e } \ + } + + +typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL EFI_ADAPTER_INFORMATION_PROTOCOL; + +/// +/// EFI_ADAPTER_INFO_MEDIA_STATE +/// +typedef struct { + /// + /// Returns the current media state status. MediaState can have any of the following values: + /// EFI_SUCCESS: There is media attached to the network adapter. EFI_NOT_READY: This detects a bounced state. + /// There was media attached to the network adapter, but it was removed and reattached. EFI_NO_MEDIA: There is + /// not any media attached to the network. + /// + EFI_STATUS MediaState; +} EFI_ADAPTER_INFO_MEDIA_STATE; + +/// +/// EFI_ADAPTER_INFO_MEDIA_TYPE +/// +typedef struct { + /// + /// Indicates the current media type. MediaType can have any of the following values: + /// 1: Ethernet Network Adapter + /// 2: Ethernet Wireless Network Adapter + /// 3~255: Reserved + /// + UINT8 MediaType; +} EFI_ADAPTER_INFO_MEDIA_TYPE; + +/// +/// EFI_ADAPTER_INFO_NETWORK_BOOT +/// +typedef struct { + /// + /// TRUE if the adapter supports booting from iSCSI IPv4 targets. + /// + BOOLEAN iScsiIpv4BootCapablity; + /// + /// TRUE if the adapter supports booting from iSCSI IPv6 targets. + /// + BOOLEAN iScsiIpv6BootCapablity; + /// + /// TRUE if the adapter supports booting from FCoE targets. + /// + BOOLEAN FCoeBootCapablity; + /// + /// TRUE if the adapter supports an offload engine (such as TCP + /// Offload Engine (TOE)) for its iSCSI or FCoE boot operations. + /// + BOOLEAN OffloadCapability; + /// + /// TRUE if the adapter supports multipath I/O (MPIO) for its iSCSI + /// boot operations. + /// + BOOLEAN iScsiMpioCapability; + /// + /// TRUE if the adapter is currently configured to boot from iSCSI + /// IPv4 targets. + /// + BOOLEAN iScsiIpv4Boot; + /// + /// TRUE if the adapter is currently configured to boot from iSCSI + /// IPv6 targets. + /// + BOOLEAN iScsiIpv6Boot; + /// + /// TRUE if the adapter is currently configured to boot from FCoE targets. + /// + BOOLEAN FCoeBoot; +} EFI_ADAPTER_INFO_NETWORK_BOOT; + +/// +/// EFI_ADAPTER_INFO_SAN_MAC_ADDRESS +/// +typedef struct { + /// + /// Returns the SAN MAC address for the adapter.For adapters that support today's 802.3 ethernet + /// networking and Fibre-Channel Over Ethernet (FCOE), this conveys the FCOE SAN MAC address from the adapter. + /// + EFI_MAC_ADDRESS SanMacAddress; +} EFI_ADAPTER_INFO_SAN_MAC_ADDRESS; + +/// +/// EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT +/// +typedef struct { + /// + /// Returns capability of UNDI to support IPv6 traffic. + /// + BOOLEAN Ipv6Support; +} EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT; + +/** + Returns the current state information for the adapter. + + This function returns information of type InformationType from the adapter. + If an adapter does not support the requested informational type, then + EFI_UNSUPPORTED is returned. + + @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance. + @param[in] InformationType A pointer to an EFI_GUID that defines the contents of InformationBlock. + @param[out] InforamtionBlock The service returns a pointer to the buffer with the InformationBlock + structure which contains details about the data specific to InformationType. + @param[out] InforamtionBlockSize The driver returns the size of the InformationBlock in bytes. + + @retval EFI_SUCCESS The InformationType information was retrieved. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER InformationBlock is NULL. + @retval EFI_INVALID_PARAMETER InformationBlockSize is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ADAPTER_INFO_GET_INFO)( + IN EFI_ADAPTER_INFORMATION_PROTOCOL *This, + IN EFI_GUID *InformationType, + OUT VOID **InformationBlock, + OUT UINTN *InformationBlockSize + ); + +/** + Sets state information for an adapter. + + This function sends information of type InformationType for an adapter. + If an adapter does not support the requested information type, then EFI_UNSUPPORTED + is returned. + + @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance. + @param[in] InformationType A pointer to an EFI_GUID that defines the contents of InformationBlock. + @param[in] InforamtionBlock A pointer to the InformationBlock structure which contains details + about the data specific to InformationType. + @param[in] InforamtionBlockSize The size of the InformationBlock in bytes. + + @retval EFI_SUCCESS The information was received and interpreted successfully. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER InformationBlock is NULL. + @retval EFI_WRITE_PROTECTED The InformationType cannot be modified using EFI_ADAPTER_INFO_SET_INFO(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ADAPTER_INFO_SET_INFO)( + IN EFI_ADAPTER_INFORMATION_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN VOID *InformationBlock, + IN UINTN InformationBlockSize + ); + +/** + Get a list of supported information types for this instance of the protocol. + + This function returns a list of InformationType GUIDs that are supported on an + adapter with this instance of EFI_ADAPTER_INFORMATION_PROTOCOL. The list is returned + in InfoTypesBuffer, and the number of GUID pointers in InfoTypesBuffer is returned in + InfoTypesBufferCount. + + @param[in] This A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance. + @param[out] InfoTypesBuffer A pointer to the array of InformationType GUIDs that are supported + by This. + @param[out] InfoTypesBufferCount A pointer to the number of GUIDs present in InfoTypesBuffer. + + @retval EFI_SUCCESS The list of information type GUIDs that are supported on this adapter was + returned in InfoTypesBuffer. The number of information type GUIDs was + returned in InfoTypesBufferCount. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER InfoTypesBuffer is NULL. + @retval EFI_INVALID_PARAMETER InfoTypesBufferCount is NULL. + @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the results. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES)( + IN EFI_ADAPTER_INFORMATION_PROTOCOL *This, + OUT EFI_GUID **InfoTypesBuffer, + OUT UINTN *InfoTypesBufferCount + ); + +/// +/// EFI_ADAPTER_INFORMATION_PROTOCOL +/// The protocol for adapter provides the following services. +/// - Gets device state information from adapter. +/// - Sets device information for adapter. +/// - Gets a list of supported information types for this instance of the protocol. +/// +struct _EFI_ADAPTER_INFORMATION_PROTOCOL { + EFI_ADAPTER_INFO_GET_INFO GetInformation; + EFI_ADAPTER_INFO_SET_INFO SetInformation; + EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES GetSupportedTypes; +}; + +extern EFI_GUID gEfiAdapterInformationProtocolGuid; + +extern EFI_GUID gEfiAdapterInfoMediaStateGuid; + +extern EFI_GUID gEfiAdapterInfoNetworkBootGuid; + +extern EFI_GUID gEfiAdapterInfoSanMacAddressGuid; + +extern EFI_GUID gEfiAdapterInfoUndiIpv6SupportGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Arp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Arp.h new file mode 100644 index 0000000000..d6b109e3ab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Arp.h @@ -0,0 +1,379 @@ +/** @file + EFI ARP Protocol Definition + + The EFI ARP Service Binding Protocol is used to locate EFI + ARP Protocol drivers to create and destroy child of the + driver to communicate with other host using ARP protocol. + The EFI ARP Protocol provides services to map IP network + address to hardware address used by a data link protocol. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.0. + +**/ + +#ifndef __EFI_ARP_PROTOCOL_H__ +#define __EFI_ARP_PROTOCOL_H__ + +#define EFI_ARP_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xf44c00ee, 0x1f2c, 0x4a00, {0xaa, 0x9, 0x1c, 0x9f, 0x3e, 0x8, 0x0, 0xa3 } \ + } + +#define EFI_ARP_PROTOCOL_GUID \ + { \ + 0xf4b427bb, 0xba21, 0x4f16, {0xbc, 0x4e, 0x43, 0xe4, 0x16, 0xab, 0x61, 0x9c } \ + } + +typedef struct _EFI_ARP_PROTOCOL EFI_ARP_PROTOCOL; + +typedef struct { + /// + /// Length in bytes of this entry. + /// + UINT32 Size; + + /// + /// Set to TRUE if this entry is a "deny" entry. + /// Set to FALSE if this entry is a "normal" entry. + /// + BOOLEAN DenyFlag; + + /// + /// Set to TRUE if this entry will not time out. + /// Set to FALSE if this entry will time out. + /// + BOOLEAN StaticFlag; + + /// + /// 16-bit ARP hardware identifier number. + /// + UINT16 HwAddressType; + + /// + /// 16-bit protocol type number. + /// + UINT16 SwAddressType; + + /// + /// The length of the hardware address. + /// + UINT8 HwAddressLength; + + /// + /// The length of the protocol address. + /// + UINT8 SwAddressLength; +} EFI_ARP_FIND_DATA; + +typedef struct { + /// + /// 16-bit protocol type number in host byte order. + /// + UINT16 SwAddressType; + + /// + /// The length in bytes of the station's protocol address to register. + /// + UINT8 SwAddressLength; + + /// + /// The pointer to the first byte of the protocol address to register. For + /// example, if SwAddressType is 0x0800 (IP), then + /// StationAddress points to the first byte of this station's IP + /// address stored in network byte order. + /// + VOID *StationAddress; + + /// + /// The timeout value in 100-ns units that is associated with each + /// new dynamic ARP cache entry. If it is set to zero, the value is + /// implementation-specific. + /// + UINT32 EntryTimeOut; + + /// + /// The number of retries before a MAC address is resolved. If it is + /// set to zero, the value is implementation-specific. + /// + UINT32 RetryCount; + + /// + /// The timeout value in 100-ns units that is used to wait for the ARP + /// reply packet or the timeout value between two retries. Set to zero + /// to use implementation-specific value. + /// + UINT32 RetryTimeOut; +} EFI_ARP_CONFIG_DATA; + + +/** + This function is used to assign a station address to the ARP cache for this instance + of the ARP driver. + + Each ARP instance has one station address. The EFI_ARP_PROTOCOL driver will + respond to ARP requests that match this registered station address. A call to + this function with the ConfigData field set to NULL will reset this ARP instance. + + Once a protocol type and station address have been assigned to this ARP instance, + all the following ARP functions will use this information. Attempting to change + the protocol type or station address to a configured ARP instance will result in errors. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + @param ConfigData The pointer to the EFI_ARP_CONFIG_DATA structure. + + @retval EFI_SUCCESS The new station address was successfully + registered. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + * This is NULL. + * SwAddressLength is zero when ConfigData is not NULL. + * StationAddress is NULL when ConfigData is not NULL. + @retval EFI_ACCESS_DENIED The SwAddressType, SwAddressLength, or + StationAddress is different from the one that is + already registered. + @retval EFI_OUT_OF_RESOURCES Storage for the new StationAddress could not be + allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_CONFIGURE)( + IN EFI_ARP_PROTOCOL *This, + IN EFI_ARP_CONFIG_DATA *ConfigData OPTIONAL + ); + +/** + This function is used to insert entries into the ARP cache. + + ARP cache entries are typically inserted and updated by network protocol drivers + as network traffic is processed. Most ARP cache entries will time out and be + deleted if the network traffic stops. ARP cache entries that were inserted + by the Add() function may be static (will not time out) or dynamic (will time out). + Default ARP cache timeout values are not covered in most network protocol + specifications (although RFC 1122 comes pretty close) and will only be + discussed in general terms in this specification. The timeout values that are + used in the EFI Sample Implementation should be used only as a guideline. + Final product implementations of the EFI network stack should be tuned for + their expected network environments. + + @param This Pointer to the EFI_ARP_PROTOCOL instance. + @param DenyFlag Set to TRUE if this entry is a deny entry. Set to + FALSE if this entry is a normal entry. + @param TargetSwAddress Pointer to a protocol address to add (or deny). + May be set to NULL if DenyFlag is TRUE. + @param TargetHwAddress Pointer to a hardware address to add (or deny). + May be set to NULL if DenyFlag is TRUE. + @param TimeoutValue Time in 100-ns units that this entry will remain + in the ARP cache. A value of zero means that the + entry is permanent. A nonzero value will override + the one given by Configure() if the entry to be + added is a dynamic entry. + @param Overwrite If TRUE, the matching cache entry will be + overwritten with the supplied parameters. If + FALSE, EFI_ACCESS_DENIED is returned if the + corresponding cache entry already exists. + + @retval EFI_SUCCESS The entry has been added or updated. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + * This is NULL. + * DenyFlag is FALSE and TargetHwAddress is NULL. + * DenyFlag is FALSE and TargetSwAddress is NULL. + * TargetHwAddress is NULL and TargetSwAddress is NULL. + * Neither TargetSwAddress nor TargetHwAddress are NULL when DenyFlag is + TRUE. + @retval EFI_OUT_OF_RESOURCES The new ARP cache entry could not be allocated. + @retval EFI_ACCESS_DENIED The ARP cache entry already exists and Overwrite + is not true. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_ADD)( + IN EFI_ARP_PROTOCOL *This, + IN BOOLEAN DenyFlag, + IN VOID *TargetSwAddress OPTIONAL, + IN VOID *TargetHwAddress OPTIONAL, + IN UINT32 TimeoutValue, + IN BOOLEAN Overwrite + ); + +/** + This function searches the ARP cache for matching entries and allocates a buffer into + which those entries are copied. + + The first part of the allocated buffer is EFI_ARP_FIND_DATA, following which + are protocol address pairs and hardware address pairs. + When finding a specific protocol address (BySwAddress is TRUE and AddressBuffer + is not NULL), the ARP cache timeout for the found entry is reset if Refresh is + set to TRUE. If the found ARP cache entry is a permanent entry, it is not + affected by Refresh. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + @param BySwAddress Set to TRUE to look for matching software protocol + addresses. Set to FALSE to look for matching + hardware protocol addresses. + @param AddressBuffer The pointer to the address buffer. Set to NULL + to match all addresses. + @param EntryLength The size of an entry in the entries buffer. + @param EntryCount The number of ARP cache entries that are found by + the specified criteria. + @param Entries The pointer to the buffer that will receive the ARP + cache entries. + @param Refresh Set to TRUE to refresh the timeout value of the + matching ARP cache entry. + + @retval EFI_SUCCESS The requested ARP cache entries were copied into + the buffer. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. Both EntryCount and EntryLength are + NULL, when Refresh is FALSE. + @retval EFI_NOT_FOUND No matching entries were found. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_FIND)( + IN EFI_ARP_PROTOCOL *This, + IN BOOLEAN BySwAddress, + IN VOID *AddressBuffer OPTIONAL, + OUT UINT32 *EntryLength OPTIONAL, + OUT UINT32 *EntryCount OPTIONAL, + OUT EFI_ARP_FIND_DATA **Entries OPTIONAL, + IN BOOLEAN Refresh + ); + + +/** + This function removes specified ARP cache entries. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + @param BySwAddress Set to TRUE to delete matching protocol addresses. + Set to FALSE to delete matching hardware + addresses. + @param AddressBuffer The pointer to the address buffer that is used as a + key to look for the cache entry. Set to NULL to + delete all entries. + + @retval EFI_SUCCESS The entry was removed from the ARP cache. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_FOUND The specified deletion key was not found. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_DELETE)( + IN EFI_ARP_PROTOCOL *This, + IN BOOLEAN BySwAddress, + IN VOID *AddressBuffer OPTIONAL + ); + +/** + This function delete all dynamic entries from the ARP cache that match the specified + software protocol type. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + + @retval EFI_SUCCESS The cache has been flushed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_FOUND There are no matching dynamic cache entries. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_FLUSH)( + IN EFI_ARP_PROTOCOL *This + ); + +/** + This function tries to resolve the TargetSwAddress and optionally returns a + TargetHwAddress if it already exists in the ARP cache. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + @param TargetSwAddress The pointer to the protocol address to resolve. + @param ResolvedEvent The pointer to the event that will be signaled when + the address is resolved or some error occurs. + @param TargetHwAddress The pointer to the buffer for the resolved hardware + address in network byte order. + + @retval EFI_SUCCESS The data is copied from the ARP cache into the + TargetHwAddress buffer. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. TargetHwAddress is NULL. + @retval EFI_ACCESS_DENIED The requested address is not present in the normal + ARP cache but is present in the deny address list. + Outgoing traffic to that address is forbidden. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + @retval EFI_NOT_READY The request has been started and is not finished. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_REQUEST)( + IN EFI_ARP_PROTOCOL *This, + IN VOID *TargetSwAddress OPTIONAL, + IN EFI_EVENT ResolvedEvent OPTIONAL, + OUT VOID *TargetHwAddress + ); + +/** + This function aborts the previous ARP request (identified by This, TargetSwAddress + and ResolvedEvent) that is issued by EFI_ARP_PROTOCOL.Request(). + + If the request is in the internal ARP request queue, the request is aborted + immediately and its ResolvedEvent is signaled. Only an asynchronous address + request needs to be canceled. If TargeSwAddress and ResolveEvent are both + NULL, all the pending asynchronous requests that have been issued by This + instance will be cancelled and their corresponding events will be signaled. + + @param This The pointer to the EFI_ARP_PROTOCOL instance. + @param TargetSwAddress The pointer to the protocol address in previous + request session. + @param ResolvedEvent Pointer to the event that is used as the + notification event in previous request session. + + @retval EFI_SUCCESS The pending request session(s) is/are aborted and + corresponding event(s) is/are signaled. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. TargetSwAddress is not NULL and + ResolvedEvent is NULL. TargetSwAddress is NULL and + ResolvedEvent is not NULL. + @retval EFI_NOT_STARTED The ARP driver instance has not been configured. + @retval EFI_NOT_FOUND The request is not issued by + EFI_ARP_PROTOCOL.Request(). + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ARP_CANCEL)( + IN EFI_ARP_PROTOCOL *This, + IN VOID *TargetSwAddress OPTIONAL, + IN EFI_EVENT ResolvedEvent OPTIONAL + ); + +/// +/// ARP is used to resolve local network protocol addresses into +/// network hardware addresses. +/// +struct _EFI_ARP_PROTOCOL { + EFI_ARP_CONFIGURE Configure; + EFI_ARP_ADD Add; + EFI_ARP_FIND Find; + EFI_ARP_DELETE Delete; + EFI_ARP_FLUSH Flush; + EFI_ARP_REQUEST Request; + EFI_ARP_CANCEL Cancel; +}; + + +extern EFI_GUID gEfiArpServiceBindingProtocolGuid; +extern EFI_GUID gEfiArpProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AtaPassThru.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AtaPassThru.h new file mode 100644 index 0000000000..06b7c31d09 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AtaPassThru.h @@ -0,0 +1,468 @@ +/** @file + The EFI_ATA_PASS_THRU_PROTOCOL provides information about an ATA controller and the ability + to send ATA Command Blocks to any ATA device attached to that ATA controller. The information + includes the attributes of the ATA controller. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.3. + +**/ + +#ifndef __ATA_PASS_THROUGH_H__ +#define __ATA_PASS_THROUGH_H__ + +#define EFI_ATA_PASS_THRU_PROTOCOL_GUID \ + { \ + 0x1d3de7f0, 0x807, 0x424f, {0xaa, 0x69, 0x11, 0xa5, 0x4e, 0x19, 0xa4, 0x6f } \ + } + +typedef struct _EFI_ATA_PASS_THRU_PROTOCOL EFI_ATA_PASS_THRU_PROTOCOL; + +typedef struct { + UINT32 Attributes; + UINT32 IoAlign; +} EFI_ATA_PASS_THRU_MODE; + +/// +/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for physical +/// devices on the ATA controller. +/// +#define EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001 +/// +/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for logical +/// devices on the ATA controller. +/// +#define EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002 +/// +/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface supports non blocking +/// I/O. Every EFI_ATA_PASS_THRU_PROTOCOL must support blocking I/O. The support of non-blocking +/// I/O is optional. +/// +#define EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004 + +typedef struct _EFI_ATA_COMMAND_BLOCK { + UINT8 Reserved1[2]; + UINT8 AtaCommand; + UINT8 AtaFeatures; + UINT8 AtaSectorNumber; + UINT8 AtaCylinderLow; + UINT8 AtaCylinderHigh; + UINT8 AtaDeviceHead; + UINT8 AtaSectorNumberExp; + UINT8 AtaCylinderLowExp; + UINT8 AtaCylinderHighExp; + UINT8 AtaFeaturesExp; + UINT8 AtaSectorCount; + UINT8 AtaSectorCountExp; + UINT8 Reserved2[6]; +} EFI_ATA_COMMAND_BLOCK; + +typedef struct _EFI_ATA_STATUS_BLOCK { + UINT8 Reserved1[2]; + UINT8 AtaStatus; + UINT8 AtaError; + UINT8 AtaSectorNumber; + UINT8 AtaCylinderLow; + UINT8 AtaCylinderHigh; + UINT8 AtaDeviceHead; + UINT8 AtaSectorNumberExp; + UINT8 AtaCylinderLowExp; + UINT8 AtaCylinderHighExp; + UINT8 Reserved2; + UINT8 AtaSectorCount; + UINT8 AtaSectorCountExp; + UINT8 Reserved3[6]; +} EFI_ATA_STATUS_BLOCK; + +typedef UINT8 EFI_ATA_PASS_THRU_CMD_PROTOCOL; + +#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET 0x00 +#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET 0x01 +#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA 0x02 +#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN 0x04 +#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT 0x05 +#define EFI_ATA_PASS_THRU_PROTOCOL_DMA 0x06 +#define EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED 0x07 +#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC 0x08 +#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET 0x09 +#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN 0x0A +#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT 0x0B +#define EFI_ATA_PASS_THRU_PROTOCOL_FPDMA 0x0C +#define EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE 0xFF + +typedef UINT8 EFI_ATA_PASS_THRU_LENGTH; + +#define EFI_ATA_PASS_THRU_LENGTH_BYTES 0x80 + + +#define EFI_ATA_PASS_THRU_LENGTH_MASK 0x70 +#define EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER 0x00 +#define EFI_ATA_PASS_THRU_LENGTH_FEATURES 0x10 +#define EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT 0x20 +#define EFI_ATA_PASS_THRU_LENGTH_TPSIU 0x30 + +#define EFI_ATA_PASS_THRU_LENGTH_COUNT 0x0F + +typedef struct { + /// + /// A pointer to the sense data that was generated by the execution of the ATA + /// command. It must be aligned to the boundary specified in the IoAlign field + /// in the EFI_ATA_PASS_THRU_MODE structure. + /// + EFI_ATA_STATUS_BLOCK *Asb; + /// + /// A pointer to buffer that contains the Command Data Block to send to the ATA + /// device specified by Port and PortMultiplierPort. + /// + EFI_ATA_COMMAND_BLOCK *Acb; + /// + /// The timeout, in 100 ns units, to use for the execution of this ATA command. + /// A Timeout value of 0 means that this function will wait indefinitely for the + /// ATA command to execute. If Timeout is greater than zero, then this function + /// will return EFI_TIMEOUT if the time required to execute the ATA command is + /// greater than Timeout. + /// + UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the ATA controller and the + /// ATA device for read and bidirectional commands. For all write and non data + /// commands where InTransferLength is 0 this field is optional and may be NULL. + /// If this field is not NULL, then it must be aligned on the boundary specified + /// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure. + /// + VOID *InDataBuffer; + /// + /// A pointer to the data buffer to transfer between the ATA controller and the + /// ATA device for write or bidirectional commands. For all read and non data + /// commands where OutTransferLength is 0 this field is optional and may be NULL. + /// If this field is not NULL, then it must be aligned on the boundary specified + /// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure. + /// + VOID *OutDataBuffer; + /// + /// On input, the size, in bytes, of InDataBuffer. On output, the number of bytes + /// transferred between the ATA controller and the ATA device. If InTransferLength + /// is larger than the ATA controller can handle, no data will be transferred, + /// InTransferLength will be updated to contain the number of bytes that the ATA + /// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned. + /// + UINT32 InTransferLength; + /// + /// On Input, the size, in bytes of OutDataBuffer. On Output, the Number of bytes + /// transferred between ATA Controller and the ATA device. If OutTransferLength is + /// larger than the ATA controller can handle, no data will be transferred, + /// OutTransferLength will be updated to contain the number of bytes that the ATA + /// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned. + /// + UINT32 OutTransferLength; + /// + /// Specifies the protocol used when the ATA device executes the command. + /// + EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol; + /// + /// Specifies the way in which the ATA command length is encoded. + /// + EFI_ATA_PASS_THRU_LENGTH Length; +} EFI_ATA_PASS_THRU_COMMAND_PACKET; + + +/** + Sends an ATA command to an ATA device that is attached to the ATA controller. This function + supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, + and the non-blocking I/O functionality is optional. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] Port The port number of the ATA device to send the command. + @param[in] PortMultiplierPort The port multiplier port number of the ATA device to send the command. + If there is no port multiplier, then specify 0xFFFF. + @param[in,out] Packet A pointer to the ATA command to send to the ATA device specified by Port + and PortMultiplierPort. + @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking + I/O is performed. If Event is NULL, then blocking I/O is performed. If + Event is not NULL and non blocking I/O is supported, then non-blocking + I/O is performed, and Event will be signaled when the ATA command completes. + + @retval EFI_SUCCESS The ATA command was sent by the host. For bi-directional commands, + InTransferLength bytes were transferred from InDataBuffer. For write and + bi-directional commands, OutTransferLength bytes were transferred by OutDataBuffer. + @retval EFI_BAD_BUFFER_SIZE The ATA command was not executed. The number of bytes that could be transferred + is returned in InTransferLength. For write and bi-directional commands, + OutTransferLength bytes were transferred by OutDataBuffer. + @retval EFI_NOT_READY The ATA command could not be sent because there are too many ATA commands + already queued. The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the ATA command. + @retval EFI_INVALID_PARAMETER Port, PortMultiplierPort, or the contents of Acb are invalid. The ATA + command was not sent, so no additional status information is available. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_PASSTHRU)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN UINT16 Port, + IN UINT16 PortMultiplierPort, + IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/** + Used to retrieve the list of legal port numbers for ATA devices on an ATA controller. + These can either be the list of ports where ATA devices are actually present or the + list of legal port numbers for the ATA controller. Regardless, the caller of this + function must probe the port number returned to see if an ATA device is actually + present at that location on the ATA controller. + + The GetNextPort() function retrieves the port number on an ATA controller. If on input + Port is 0xFFFF, then the port number of the first port on the ATA controller is returned + in Port and EFI_SUCCESS is returned. + + If Port is a port number that was returned on a previous call to GetNextPort(), then the + port number of the next port on the ATA controller is returned in Port, and EFI_SUCCESS + is returned. If Port is not 0xFFFF and Port was not returned on a previous call to + GetNextPort(), then EFI_INVALID_PARAMETER is returned. + + If Port is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is + returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in,out] Port On input, a pointer to the port number on the ATA controller. + On output, a pointer to the next port number on the ATA + controller. An input value of 0xFFFF retrieves the first port + number on the ATA controller. + + @retval EFI_SUCCESS The next port number on the ATA controller was returned in Port. + @retval EFI_NOT_FOUND There are no more ports on this ATA controller. + @retval EFI_INVALID_PARAMETER Port is not 0xFFFF and Port was not returned on a previous call + to GetNextPort(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_PORT)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN OUT UINT16 *Port + ); + +/** + Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA + controller. These can either be the list of port multiplier ports where ATA devices are actually + present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this + function must probe the port number and port multiplier port number returned to see if an ATA + device is actually present. + + The GetNextDevice() function retrieves the port multiplier port number of an ATA device + present on a port of an ATA controller. + + If PortMultiplierPort points to a port multiplier port number value that was returned on a + previous call to GetNextDevice(), then the port multiplier port number of the next ATA device + on the port of the ATA controller is returned in PortMultiplierPort, and EFI_SUCCESS is + returned. + + If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first + ATA device on port of the ATA controller is returned in PortMultiplierPort and + EFI_SUCCESS is returned. + + If PortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort + was not returned on a previous call to GetNextDevice(), then EFI_INVALID_PARAMETER + is returned. + + If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of + the ATA controller, then EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] Port The port number present on the ATA controller. + @param[in,out] PortMultiplierPort On input, a pointer to the port multiplier port number of an + ATA device present on the ATA controller. + If on input a PortMultiplierPort of 0xFFFF is specified, + then the port multiplier port number of the first ATA device + is returned. On output, a pointer to the port multiplier port + number of the next ATA device present on an ATA controller. + + @retval EFI_SUCCESS The port multiplier port number of the next ATA device on the port + of the ATA controller was returned in PortMultiplierPort. + @retval EFI_NOT_FOUND There are no more ATA devices on this port of the ATA controller. + @retval EFI_INVALID_PARAMETER PortMultiplierPort is not 0xFFFF, and PortMultiplierPort was not + returned on a previous call to GetNextDevice(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_GET_NEXT_DEVICE)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN UINT16 Port, + IN OUT UINT16 *PortMultiplierPort + ); + +/** + Used to allocate and build a device path node for an ATA device on an ATA controller. + + The BuildDevicePath() function allocates and builds a single device node for the ATA + device specified by Port and PortMultiplierPort. If the ATA device specified by Port and + PortMultiplierPort is not present on the ATA controller, then EFI_NOT_FOUND is returned. + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. If there are not enough + resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of + DevicePath are initialized to describe the ATA device specified by Port and PortMultiplierPort, + and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] Port Port specifies the port number of the ATA device for which a + device path node is to be allocated and built. + @param[in] PortMultiplierPort The port multiplier port number of the ATA device for which a + device path node is to be allocated and built. If there is no + port multiplier, then specify 0xFFFF. + @param[out] DevicePath A pointer to a single device path node that describes the ATA + device specified by Port and PortMultiplierPort. This function + is responsible for allocating the buffer DevicePath with the + boot service AllocatePool(). It is the caller's responsibility + to free DevicePath when the caller is finished with DevicePath. + @retval EFI_SUCCESS The device path node that describes the ATA device specified by + Port and PortMultiplierPort was allocated and returned in DevicePath. + @retval EFI_NOT_FOUND The ATA device specified by Port and PortMultiplierPort does not + exist on the ATA controller. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN UINT16 Port, + IN UINT16 PortMultiplierPort, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Used to translate a device path node to a port number and port multiplier port number. + + The GetDevice() function determines the port and port multiplier port number associated with + the ATA device described by DevicePath. If DevicePath is a device path node type that the + ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents + DevicePath into a port number and port multiplier port number. + + If this translation is successful, then that port number and port multiplier port number are returned + in Port and PortMultiplierPort, and EFI_SUCCESS is returned. + + If DevicePath, Port, or PortMultiplierPort are NULL, then EFI_INVALID_PARAMETER is returned. + + If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then + EFI_UNSUPPORTED is returned. + + If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not + a valid translation from DevicePath to a port number and port multiplier port number, then + EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] DevicePath A pointer to the device path node that describes an ATA device on the + ATA controller. + @param[out] Port On return, points to the port number of an ATA device on the ATA controller. + @param[out] PortMultiplierPort On return, points to the port multiplier port number of an ATA device + on the ATA controller. + + @retval EFI_SUCCESS DevicePath was successfully translated to a port number and port multiplier + port number, and they were returned in Port and PortMultiplierPort. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_INVALID_PARAMETER Port is NULL. + @retval EFI_INVALID_PARAMETER PortMultiplierPort is NULL. + @retval EFI_UNSUPPORTED This driver does not support the device path node type in DevicePath. + @retval EFI_NOT_FOUND A valid translation from DevicePath to a port number and port multiplier + port number does not exist. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_GET_DEVICE)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT16 *Port, + OUT UINT16 *PortMultiplierPort + ); + +/** + Resets a specific port on the ATA controller. This operation also resets all the ATA devices + connected to the port. + + The ResetChannel() function resets an a specific port on an ATA controller. This operation + resets all the ATA devices connected to that port. If this ATA controller does not support + a reset port operation, then EFI_UNSUPPORTED is returned. + + If a device error occurs while executing that port reset operation, then EFI_DEVICE_ERROR is + returned. + + If a timeout occurs during the execution of the port reset operation, then EFI_TIMEOUT is returned. + + If the port reset operation is completed, then EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] Port The port number on the ATA controller. + + @retval EFI_SUCCESS The ATA controller port was reset. + @retval EFI_UNSUPPORTED The ATA controller does not support a port reset operation. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA port. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA port. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_RESET_PORT)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN UINT16 Port + ); + +/** + Resets an ATA device that is connected to an ATA controller. + + The ResetDevice() function resets the ATA device specified by Port and PortMultiplierPort. + If this ATA controller does not support a device reset operation, then EFI_UNSUPPORTED is + returned. + + If Port or PortMultiplierPort are not in a valid range for this ATA controller, then + EFI_INVALID_PARAMETER is returned. + + If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR + is returned. + + If a timeout occurs during the execution of the device reset operation, then EFI_TIMEOUT is + returned. + + If the device reset operation is completed, then EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. + @param[in] Port Port represents the port number of the ATA device to be reset. + @param[in] PortMultiplierPort The port multiplier port number of the ATA device to reset. + If there is no port multiplier, then specify 0xFFFF. + @retval EFI_SUCCESS The ATA device specified by Port and PortMultiplierPort was reset. + @retval EFI_UNSUPPORTED The ATA controller does not support a device reset operation. + @retval EFI_INVALID_PARAMETER Port or PortMultiplierPort are invalid. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the ATA device + specified by Port and PortMultiplierPort. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset the ATA device + specified by Port and PortMultiplierPort. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ATA_PASS_THRU_RESET_DEVICE)( + IN EFI_ATA_PASS_THRU_PROTOCOL *This, + IN UINT16 Port, + IN UINT16 PortMultiplierPort + ); + +struct _EFI_ATA_PASS_THRU_PROTOCOL { + EFI_ATA_PASS_THRU_MODE *Mode; + EFI_ATA_PASS_THRU_PASSTHRU PassThru; + EFI_ATA_PASS_THRU_GET_NEXT_PORT GetNextPort; + EFI_ATA_PASS_THRU_GET_NEXT_DEVICE GetNextDevice; + EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath; + EFI_ATA_PASS_THRU_GET_DEVICE GetDevice; + EFI_ATA_PASS_THRU_RESET_PORT ResetPort; + EFI_ATA_PASS_THRU_RESET_DEVICE ResetDevice; +}; + +extern EFI_GUID gEfiAtaPassThruProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AuthenticationInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AuthenticationInfo.h new file mode 100644 index 0000000000..fe85c2a0a1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/AuthenticationInfo.h @@ -0,0 +1,231 @@ +/** @file + EFI_AUTHENTICATION_INFO_PROTOCOL as defined in UEFI 2.0. + This protocol is used on any device handle to obtain authentication information + associated with the physical or logical device. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __AUTHENTICATION_INFO_H__ +#define __AUTHENTICATION_INFO_H__ + +#define EFI_AUTHENTICATION_INFO_PROTOCOL_GUID \ + { \ + 0x7671d9d0, 0x53db, 0x4173, {0xaa, 0x69, 0x23, 0x27, 0xf2, 0x1f, 0x0b, 0xc7 } \ + } + +#define EFI_AUTHENTICATION_CHAP_RADIUS_GUID \ + { \ + 0xd6062b50, 0x15ca, 0x11da, {0x92, 0x19, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \ + } + +#define EFI_AUTHENTICATION_CHAP_LOCAL_GUID \ + { \ + 0xc280c73e, 0x15ca, 0x11da, {0xb0, 0xca, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \ + } + +typedef struct _EFI_AUTHENTICATION_INFO_PROTOCOL EFI_AUTHENTICATION_INFO_PROTOCOL; + +#pragma pack(1) +typedef struct { + /// + /// Authentication Type GUID. + /// + EFI_GUID Guid; + + /// + /// Length of this structure in bytes. + /// + UINT16 Length; +} AUTH_NODE_HEADER; + +typedef struct { + AUTH_NODE_HEADER Header; + + /// + /// RADIUS Server IPv4 or IPv6 Address. + /// + UINT8 RadiusIpAddr[16]; ///< IPv4 or IPv6 address. + + /// + /// Reserved for future use. + /// + UINT16 Reserved; + + /// + /// Network Access Server IPv4 or IPv6 Address (OPTIONAL). + /// + UINT8 NasIpAddr[16]; ///< IPv4 or IPv6 address. + + /// + /// Network Access Server Secret Length in bytes (OPTIONAL). + /// + UINT16 NasSecretLength; + + /// + /// Network Access Server Secret (OPTIONAL). + /// + UINT8 NasSecret[1]; + + /// + /// CHAP Initiator Secret Length in bytes on offset NasSecret + NasSecretLength. + /// + /// UINT16 ChapSecretLength; + /// + /// CHAP Initiator Secret. + /// + /// UINT8 ChapSecret[]; + /// + /// CHAP Initiator Name Length in bytes on offset ChapSecret + ChapSecretLength. + /// + /// UINT16 ChapNameLength; + /// + /// CHAP Initiator Name. + /// + /// UINT8 ChapName[]; + /// + /// Reverse CHAP Name Length in bytes on offset ChapName + ChapNameLength. + /// + /// UINT16 ReverseChapNameLength; + /// + /// Reverse CHAP Name. + /// + /// UINT8 ReverseChapName[]; + /// + /// Reverse CHAP Secret Length in bytes on offseet ReverseChapName + ReverseChapNameLength. + /// + /// UINT16 ReverseChapSecretLength; + /// + /// Reverse CHAP Secret. + /// + /// UINT8 ReverseChapSecret[]; + /// +} CHAP_RADIUS_AUTH_NODE; + +typedef struct { + AUTH_NODE_HEADER Header; + + /// + /// Reserved for future use. + /// + UINT16 Reserved; + + /// + /// User Secret Length in bytes. + /// + UINT16 UserSecretLength; + + /// + /// User Secret. + /// + UINT8 UserSecret[1]; + + /// + /// User Name Length in bytes on offset UserSecret + UserSecretLength. + /// + /// UINT16 UserNameLength; + /// + /// User Name. + /// + /// UINT8 UserName[]; + /// + /// CHAP Initiator Secret Length in bytes on offset UserName + UserNameLength. + /// + /// UINT16 ChapSecretLength; + /// + /// CHAP Initiator Secret. + /// + /// UINT8 ChapSecret[]; + /// + /// CHAP Initiator Name Length in bytes on offset ChapSecret + ChapSecretLength. + /// + /// UINT16 ChapNameLength; + /// + /// CHAP Initiator Name. + /// + /// UINT8 ChapName[]; + /// + /// Reverse CHAP Name Length in bytes on offset ChapName + ChapNameLength. + /// + /// UINT16 ReverseChapNameLength; + /// + /// Reverse CHAP Name. + /// + /// UINT8 ReverseChapName[]; + /// + /// Reverse CHAP Secret Length in bytes on offset ReverseChapName + ReverseChapNameLength. + /// + /// UINT16 ReverseChapSecretLength; + /// + /// Reverse CHAP Secret. + /// + /// UINT8 ReverseChapSecret[]; + /// +} CHAP_LOCAL_AUTH_NODE; +#pragma pack() + +/** + Retrieves the authentication information associated with a particular controller handle. + + @param[in] This The pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL. + @param[in] ControllerHandle The handle to the Controller. + @param[out] Buffer The pointer to the authentication information. This function is + responsible for allocating the buffer and it is the caller's + responsibility to free buffer when the caller is finished with buffer. + + @retval EFI_SUCCESS Successfully retrieved authentication information + for the given ControllerHandle. + @retval EFI_INVALID_PARAMETER No matching authentication information found for + the given ControllerHandle. + @retval EFI_DEVICE_ERROR The authentication information could not be retrieved + due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_GET)( + IN EFI_AUTHENTICATION_INFO_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + OUT VOID **Buffer + ); + +/** + Set the authentication information for a given controller handle. + + @param[in] This The pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL. + @param[in] ControllerHandle The handle to the Controller. + @param[in] Buffer The pointer to the authentication information. + + @retval EFI_SUCCESS Successfully set authentication information for the + given ControllerHandle. + @retval EFI_UNSUPPORTED If the platform policies do not allow setting of + the authentication information. + @retval EFI_DEVICE_ERROR The authentication information could not be configured + due to a hardware error. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_AUTHENTICATION_INFO_PROTOCOL_SET)( + IN EFI_AUTHENTICATION_INFO_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN VOID *Buffer + ); + +/// +/// This protocol is used on any device handle to obtain authentication +/// information associated with the physical or logical device. +/// +struct _EFI_AUTHENTICATION_INFO_PROTOCOL { + EFI_AUTHENTICATION_INFO_PROTOCOL_GET Get; + EFI_AUTHENTICATION_INFO_PROTOCOL_SET Set; +}; + +extern EFI_GUID gEfiAuthenticationInfoProtocolGuid; +extern EFI_GUID gEfiAuthenticationChapRadiusGuid; +extern EFI_GUID gEfiAuthenticationChapLocalGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bds.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bds.h new file mode 100644 index 0000000000..7ca7777c9e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bds.h @@ -0,0 +1,66 @@ +/** @file + Boot Device Selection Architectural Protocol as defined in PI spec Volume 2 DXE + + When the DXE core is done it calls the BDS via this protocol. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_BDS_H__ +#define __ARCH_PROTOCOL_BDS_H__ + +/// +/// Global ID for the BDS Architectural Protocol +/// +#define EFI_BDS_ARCH_PROTOCOL_GUID \ + { 0x665E3FF6, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } } + +/// +/// Declare forward reference for the BDS Architectural Protocol +/// +typedef struct _EFI_BDS_ARCH_PROTOCOL EFI_BDS_ARCH_PROTOCOL; + +/** + This function uses policy data from the platform to determine what operating + system or system utility should be loaded and invoked. This function call + also optionally make the use of user input to determine the operating system + or system utility to be loaded and invoked. When the DXE Core has dispatched + all the drivers on the dispatch queue, this function is called. This + function will attempt to connect the boot devices required to load and invoke + the selected operating system or system utility. During this process, + additional firmware volumes may be discovered that may contain addition DXE + drivers that can be dispatched by the DXE Core. If a boot device cannot be + fully connected, this function calls the DXE Service Dispatch() to allow the + DXE drivers from any newly discovered firmware volumes to be dispatched. + Then the boot device connection can be attempted again. If the same boot + device connection operation fails twice in a row, then that boot device has + failed, and should be skipped. This function should never return. + + @param This The EFI_BDS_ARCH_PROTOCOL instance. + + @return None. + +**/ +typedef +VOID +(EFIAPI *EFI_BDS_ENTRY)( + IN EFI_BDS_ARCH_PROTOCOL *This + ); + +/// +/// The EFI_BDS_ARCH_PROTOCOL transfers control from DXE to an operating +/// system or a system utility. If there are not enough drivers initialized +/// when this protocol is used to access the required boot device(s), then +/// this protocol should add drivers to the dispatch queue and return control +/// back to the dispatcher. Once the required boot devices are available, then +/// the boot device can be used to load and invoke an OS or a system utility. +/// +struct _EFI_BDS_ARCH_PROTOCOL { + EFI_BDS_ENTRY Entry; +}; + +extern EFI_GUID gEfiBdsArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bis.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bis.h new file mode 100644 index 0000000000..23dc6577fb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Bis.h @@ -0,0 +1,445 @@ +/** @file + The EFI_BIS_PROTOCOL is used to check a digital signature of a data block + against a digital certificate for the purpose of an integrity and authorization check. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in EFI Specification 1.10. + +**/ + +#ifndef __BIS_H__ +#define __BIS_H__ + +#define EFI_BIS_PROTOCOL_GUID \ + { \ + 0x0b64aab0, 0x5429, 0x11d4, {0x98, 0x16, 0x00, 0xa0, 0xc9, 0x1f, 0xad, 0xcf } \ + } + +// +// X-Intel-BIS-ParameterSet +// Attribute value +// Binary Value of X-Intel-BIS-ParameterSet Attribute. +// (Value is Base-64 encoded in actual signed manifest). +// +#define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID \ + { \ + 0xedd35e31, 0x7b9, 0x11d2, { 0x83,0xa3,0x0,0xa0,0xc9,0x1f,0xad,0xcf } \ + } + + + +typedef struct _EFI_BIS_PROTOCOL EFI_BIS_PROTOCOL; + + +// +// Basic types +// +typedef VOID *BIS_APPLICATION_HANDLE; +typedef UINT16 BIS_ALG_ID; +typedef UINT32 BIS_CERT_ID; + +/// +/// EFI_BIS_DATA instances obtained from BIS must be freed by calling Free( ). +/// +typedef struct { + UINT32 Length; ///< The length of Data in 8 bit bytes. + UINT8 *Data; ///< 32 Bit Flat Address of data. +} EFI_BIS_DATA; + +/// +/// EFI_BIS_VERSION type. +/// +typedef struct { + UINT32 Major; ///< The major BIS version number. + UINT32 Minor; ///< A minor BIS version number. +} EFI_BIS_VERSION; + +// +// ----------------------------------------------------// +// Use these values to initialize EFI_BIS_VERSION.Major +// and to interpret results of Initialize. +// ----------------------------------------------------// +// +#define BIS_CURRENT_VERSION_MAJOR BIS_VERSION_1 +#define BIS_VERSION_1 1 + +/// +/// EFI_BIS_SIGNATURE_INFO type. +/// +typedef struct { + BIS_CERT_ID CertificateID; ///< Truncated hash of platform Boot Object + BIS_ALG_ID AlgorithmID; ///< A signature algorithm number. + UINT16 KeyLength; ///< The length of alg. keys in bits. +} EFI_BIS_SIGNATURE_INFO; + +/// +/// values for EFI_BIS_SIGNATURE_INFO.AlgorithmID. +/// The exact numeric values come from the +/// "Common Data Security Architecture (CDSA) Specification". +/// +#define BIS_ALG_DSA (41) // CSSM_ALGID_DSA +#define BIS_ALG_RSA_MD5 (42) // CSSM_ALGID_MD5_WITH_RSA +/// +/// values for EFI_BIS_SIGNATURE_INFO.CertificateId. +/// +#define BIS_CERT_ID_DSA BIS_ALG_DSA // CSSM_ALGID_DSA +#define BIS_CERT_ID_RSA_MD5 BIS_ALG_RSA_MD5 // CSSM_ALGID_MD5_WITH_RSA +/// +/// The mask value that gets applied to the truncated hash of a +/// platform Boot Object Authorization Certificate to create the certificateID. +/// A certificateID must not have any bits set to the value 1 other than bits in +/// this mask. +/// +#define BIS_CERT_ID_MASK (0xFF7F7FFF) + +/// +/// Macros for dealing with the EFI_BIS_DATA object obtained +/// from BIS_GetSignatureInfo(). +/// BIS_GET_SIGINFO_COUNT - tells how many EFI_BIS_SIGNATURE_INFO +/// elements are contained in a EFI_BIS_DATA struct pointed to +/// by the provided EFI_BIS_DATA*. +/// +#define BIS_GET_SIGINFO_COUNT(BisDataPtr) ((BisDataPtr)->Length / sizeof (EFI_BIS_SIGNATURE_INFO)) + +/// +/// BIS_GET_SIGINFO_ARRAY - produces a EFI_BIS_SIGNATURE_INFO* +/// from a given EFI_BIS_DATA*. +/// +#define BIS_GET_SIGINFO_ARRAY(BisDataPtr) ((EFI_BIS_SIGNATURE_INFO *) (BisDataPtr)->Data) + +/// +/// Support an old name for backward compatibility. +/// +#define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUIDVALUE \ + BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID + +/** + Initializes the BIS service, checking that it is compatible with the version requested by the caller. + After this call, other BIS functions may be invoked. + + @param This A pointer to the EFI_BIS_PROTOCOL object. + @param AppHandle The function writes the new BIS_APPLICATION_HANDLE if + successful, otherwise it writes NULL. The caller must eventually + destroy this handle by calling Shutdown(). + @param InterfaceVersion On input, the caller supplies the major version number of the + interface version desired. + On output, both the major and minor + version numbers are updated with the major and minor version + numbers of the interface. This update is done whether or not the + initialization was successful. + @param TargetAddress Indicates a network or device address of the BIS platform to connect to. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INCOMPATIBLE_VERSION The InterfaceVersion.Major requested by the + caller was not compatible with the interface version of the + implementation. The InterfaceVersion.Major has + been updated with the current interface version. + @retval EFI_UNSUPPORTED This is a local-platform implementation and + TargetAddress.Data was not NULL, or + TargetAddress.Data was any other value that was not + supported by the implementation. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_DEVICE_ERROR One of the following device errors: + * The function encountered an unexpected internal failure while initializing a cryptographic software module + * No cryptographic software module with compatible version was found + found + * A resource limitation was encountered while using a cryptographic software module. + @retval EFI_INVALID_PARAMETER The This parameter supplied by the caller is NULL or does not + reference a valid EFI_BIS_PROTOCOL object. Or, + the AppHandle parameter supplied by the caller is NULL or + an invalid memory reference. Or, + the InterfaceVersion parameter supplied by the caller + is NULL or an invalid memory reference. Or, + the TargetAddress parameter supplied by the caller is + NULL or an invalid memory reference. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_INITIALIZE)( + IN EFI_BIS_PROTOCOL *This, + OUT BIS_APPLICATION_HANDLE *AppHandle, + IN OUT EFI_BIS_VERSION *InterfaceVersion, + IN EFI_BIS_DATA *TargetAddress + ); + +/** + Frees memory structures allocated and returned by other functions in the EFI_BIS protocol. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param ToFree An EFI_BIS_DATA* and associated memory block to be freed. + This EFI_BIS_DATA* must have been allocated by one of the other BIS functions. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER The ToFree parameter is not or is no longer a memory resource + associated with this AppHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_FREE)( + IN BIS_APPLICATION_HANDLE AppHandle, + IN EFI_BIS_DATA *ToFree + ); + +/** + Shuts down an application's instance of the BIS service, invalidating the application handle. After + this call, other BIS functions may no longer be invoked using the application handle value. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not, or is no longer, a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_DEVICE_ERROR The function encountered an unexpected internal failure while + returning resources associated with a cryptographic software module, or + while trying to shut down a cryptographic software module. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_SHUTDOWN)( + IN BIS_APPLICATION_HANDLE AppHandle + ); + +/** + Retrieves the certificate that has been configured as the identity of the organization designated as + the source of authorization for signatures of boot objects. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param Certificate The function writes an allocated EFI_BIS_DATA* containing the Boot + Object Authorization Certificate object. The caller must + eventually free the memory allocated by this function using the function Free(). + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_NOT_FOUND There is no Boot Object Authorization Certificate currently installed. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER The Certificate parameter supplied by the caller is NULL or + an invalid memory reference. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE)( + IN BIS_APPLICATION_HANDLE AppHandle, + OUT EFI_BIS_DATA **Certificate + ); + +/** + Verifies the integrity and authorization of the indicated data object according to the + indicated credentials. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param Credentials A Signed Manifest containing verification information for the indicated + data object. + @param DataObject An in-memory copy of the raw data object to be verified. + @param IsVerified The function writes TRUE if the verification succeeded, otherwise + FALSE. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_SECURITY_VIOLATION The signed manifest supplied as the Credentials parameter + was invalid (could not be parsed) or Platform-specific authorization failed, etc. + @retval EFI_DEVICE_ERROR An unexpected internal error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_VERIFY_BOOT_OBJECT)( + IN BIS_APPLICATION_HANDLE AppHandle, + IN EFI_BIS_DATA *Credentials, + IN EFI_BIS_DATA *DataObject, + OUT BOOLEAN *IsVerified + ); + +/** + Retrieves the current status of the Boot Authorization Check Flag. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param CheckIsRequired The function writes the value TRUE if a Boot Authorization Check is + currently required on this platform, otherwise the function writes + FALSE. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER The CheckIsRequired parameter supplied by the caller is + NULL or an invalid memory reference. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG)( + IN BIS_APPLICATION_HANDLE AppHandle, + OUT BOOLEAN *CheckIsRequired + ); + +/** + Retrieves a unique token value to be included in the request credential for the next update of any + parameter in the Boot Object Authorization set + + @param AppHandle An opaque handle that identifies the caller's + instance of initialization of the BIS service. + @param UpdateToken The function writes an allocated EFI_BIS_DATA* + containing the newunique update token value. + The caller musteventually free the memory allocated + by this function using the function Free(). + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER The UpdateToken parameter supplied by the caller is NULL or + an invalid memory reference. + @retval EFI_DEVICE_ERROR An unexpected internal error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN)( + IN BIS_APPLICATION_HANDLE AppHandle, + OUT EFI_BIS_DATA **UpdateToken + ); + +/** + Updates one of the configurable parameters of the Boot Object Authorization set. + + @param AppHandle An opaque handle that identifies the caller's + instance of initialization of the BIS service. + @param RequestCredential This is a Signed Manifest with embedded attributes + that carry the details of the requested update. + @param NewUpdateToken The function writes an allocated EFI_BIS_DATA* + containing the new unique update token value. + The caller must eventually free the memory allocated + by this function using the function Free(). + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_SECURITY_VIOLATION The signed manifest supplied as the RequestCredential parameter + was invalid (could not be parsed) or Platform-specific authorization failed, etc. + @retval EFI_DEVICE_ERROR An unexpected internal error occurred while analyzing the new + certificate's key algorithm, or while attempting to retrieve + the public key algorithm of the manifest's signer's certificate, + or An unexpected internal error occurred in a cryptographic software module. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION)( + IN BIS_APPLICATION_HANDLE AppHandle, + IN EFI_BIS_DATA *RequestCredential, + OUT EFI_BIS_DATA **NewUpdateToken + ); + +/** + Verifies the integrity and authorization of the indicated data object according to the indicated + credentials and authority certificate. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param Credentials A Signed Manifest containing verification information for the + indicated data object. + @param DataObject An in-memory copy of the raw data object to be verified. + @param SectionName An ASCII string giving the section name in the + manifest holding the verification information (in other words, + hash value) that corresponds to DataObject. + @param AuthorityCertificate A digital certificate whose public key must match the signer's + public key which is found in the credentials. + @param IsVerified The function writes TRUE if the verification was successful. + Otherwise, the function writes FALSE. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_SECURITY_VIOLATION The Credentials.Data supplied by the caller is NULL, + or the AuthorityCertificate supplied by the caller was + invalid (could not be parsed), + or Platform-specific authorization failed, etc. + @retval EFI_DEVICE_ERROR An unexpected internal error occurred while attempting to retrieve + the public key algorithm of the manifest's signer's certificate, + or An unexpected internal error occurred in a cryptographic software module. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL)( + IN BIS_APPLICATION_HANDLE AppHandle, + IN EFI_BIS_DATA *Credentials, + IN EFI_BIS_DATA *DataObject, + IN EFI_BIS_DATA *SectionName, + IN EFI_BIS_DATA *AuthorityCertificate, + OUT BOOLEAN *IsVerified + ); + +/** + Retrieves a list of digital certificate identifier, digital signature algorithm, hash algorithm, and keylength + combinations that the platform supports. + + @param AppHandle An opaque handle that identifies the caller's instance of initialization + of the BIS service. + @param SignatureInfo The function writes an allocated EFI_BIS_DATA* containing the array + of EFI_BIS_SIGNATURE_INFO structures representing the supported + digital certificate identifier, algorithm, and key length combinations. + The caller must eventually free the memory allocated by this function using the function Free(). + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NO_MAPPING The AppHandle parameter is not or is no longer a valid + application instance handle associated with the EFI_BIS protocol. + @retval EFI_OUT_OF_RESOURCES The function failed due to lack of memory or other resources. + @retval EFI_INVALID_PARAMETER The SignatureInfo parameter supplied by the caller is NULL + or an invalid memory reference. + @retval EFI_DEVICE_ERROR An unexpected internal error occurred in a + cryptographic software module, or + The function encountered an unexpected internal consistency check + failure (possible corruption of stored Boot Object Authorization Certificate). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BIS_GET_SIGNATURE_INFO)( + IN BIS_APPLICATION_HANDLE AppHandle, + OUT EFI_BIS_DATA **SignatureInfo + ); + +/// +/// The EFI_BIS_PROTOCOL is used to check a digital signature of a data block against a digital +/// certificate for the purpose of an integrity and authorization check. +/// +struct _EFI_BIS_PROTOCOL { + EFI_BIS_INITIALIZE Initialize; + EFI_BIS_SHUTDOWN Shutdown; + EFI_BIS_FREE Free; + EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE GetBootObjectAuthorizationCertificate; + EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG GetBootObjectAuthorizationCheckFlag; + EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN GetBootObjectAuthorizationUpdateToken; + EFI_BIS_GET_SIGNATURE_INFO GetSignatureInfo; + EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION UpdateBootObjectAuthorization; + EFI_BIS_VERIFY_BOOT_OBJECT VerifyBootObject; + EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL VerifyObjectWithCredential; +}; + +extern EFI_GUID gEfiBisProtocolGuid; +extern EFI_GUID gBootObjectAuthorizationParmsetGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo.h new file mode 100644 index 0000000000..107ea92082 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo.h @@ -0,0 +1,235 @@ +/** @file + Block IO protocol as defined in the UEFI 2.0 specification. + + The Block IO protocol is used to abstract block devices like hard drives, + DVD-ROMs and floppy drives. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __BLOCK_IO_H__ +#define __BLOCK_IO_H__ + +#define EFI_BLOCK_IO_PROTOCOL_GUID \ + { \ + 0x964e5b21, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL; + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO; + +/** + Reset the Block Device. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Driver may perform diagnostics on reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning properly and could + not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_RESET)( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Read BufferSize bytes from Lba into Buffer. + + @param This Indicates a pointer to the calling context. + @param MediaId Id of the media, changes every time the media is replaced. + @param Lba The starting Logical Block Address to read from + @param BufferSize Size of Buffer, must be a multiple of device block size. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while performing the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_READ)( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Write BufferSize bytes from Lba into Buffer. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. The caller is + responsible for writing to only legitimate locations. + @param BufferSize Size of Buffer, must be a multiple of device block size. + @param Buffer A pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data was written correctly to the device. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_WRITE)( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush the Block Device. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data was written to the device + @retval EFI_DEVICE_ERROR The device reported an error while writting back the data + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_FLUSH)( + IN EFI_BLOCK_IO_PROTOCOL *This + ); + +/** + Block IO read only mode data and updated only via members of BlockIO +**/ +typedef struct { + /// + /// The curent media Id. If the media changes, this value is changed. + /// + UINT32 MediaId; + + /// + /// TRUE if the media is removable; otherwise, FALSE. + /// + BOOLEAN RemovableMedia; + + /// + /// TRUE if there is a media currently present in the device; + /// othersise, FALSE. THis field shows the media present status + /// as of the most recent ReadBlocks() or WriteBlocks() call. + /// + BOOLEAN MediaPresent; + + /// + /// TRUE if LBA 0 is the first block of a partition; otherwise + /// FALSE. For media with only one partition this would be TRUE. + /// + BOOLEAN LogicalPartition; + + /// + /// TRUE if the media is marked read-only otherwise, FALSE. + /// This field shows the read-only status as of the most recent WriteBlocks () call. + /// + BOOLEAN ReadOnly; + + /// + /// TRUE if the WriteBlock () function caches write data. + /// + BOOLEAN WriteCaching; + + /// + /// The intrinsic block size of the device. If the media changes, then + /// this field is updated. + /// + UINT32 BlockSize; + + /// + /// Supplies the alignment requirement for any buffer to read or write block(s). + /// + UINT32 IoAlign; + + /// + /// The last logical block address on the device. + /// If the media changes, then this field is updated. + /// + EFI_LBA LastBlock; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to + /// a physical block boundary. + /// + EFI_LBA LowestAlignedLba; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks + /// per physical block. + /// + UINT32 LogicalBlocksPerPhysicalBlock; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length + /// granularity as a number of logical blocks. + /// + UINT32 OptimalTransferLengthGranularity; +} EFI_BLOCK_IO_MEDIA; + +#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000 +#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001 +#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F + +/// +/// Revision defined in EFI1.1. +/// +#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION + +/// +/// This protocol provides control over block devices. +/// +struct _EFI_BLOCK_IO_PROTOCOL { + /// + /// The revision to which the block IO interface adheres. All future + /// revisions must be backwards compatible. If a future version is not + /// back wards compatible, it is not the same GUID. + /// + UINT64 Revision; + /// + /// Pointer to the EFI_BLOCK_IO_MEDIA data for this device. + /// + EFI_BLOCK_IO_MEDIA *Media; + + EFI_BLOCK_RESET Reset; + EFI_BLOCK_READ ReadBlocks; + EFI_BLOCK_WRITE WriteBlocks; + EFI_BLOCK_FLUSH FlushBlocks; + +}; + +extern EFI_GUID gEfiBlockIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo2.h new file mode 100644 index 0000000000..75ea914ffc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIo2.h @@ -0,0 +1,200 @@ +/** @file + Block IO2 protocol as defined in the UEFI 2.3.1 specification. + + The Block IO2 protocol defines an extension to the Block IO protocol which + enables the ability to read and write data at a block level in a non-blocking + manner. + + Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __BLOCK_IO2_H__ +#define __BLOCK_IO2_H__ + +#include + +#define EFI_BLOCK_IO2_PROTOCOL_GUID \ + { \ + 0xa77b2472, 0xe282, 0x4e9f, {0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1} \ + } + +typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL; + +/** + The struct of Block IO2 Token. +**/ +typedef struct { + + /// + /// If Event is NULL, then blocking I/O is performed.If Event is not NULL and + /// non-blocking I/O is supported, then non-blocking I/O is performed, and + /// Event will be signaled when the read request is completed. + /// + EFI_EVENT Event; + + /// + /// Defines whether or not the signaled event encountered an error. + /// + EFI_STATUS TransactionStatus; +} EFI_BLOCK_IO2_TOKEN; + + +/** + Reset the block device hardware. + + @param[in] This Indicates a pointer to the calling context. + @param[in] ExtendedVerification Indicates that the driver may perform a more + exhausive verification operation of the device + during reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning properly and could + not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_RESET_EX) ( + IN EFI_BLOCK_IO2_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Read BufferSize bytes from Lba into Buffer. + + This function reads the requested number of blocks from the device. All the + blocks are read, or an error is returned. + If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_or EFI_MEDIA_CHANGED is returned and + non-blocking I/O is being used, the Event associated with this request will + not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId Id of the media, changes every time the media is + replaced. + @param[in] Lba The starting Logical Block Address to read from. + @param[in, out] Token A pointer to the token associated with the transaction. + @param[in] BufferSize Size of Buffer, must be a multiple of device block size. + @param[out] Buffer A pointer to the destination buffer for the data. The + caller is responsible for either having implicit or + explicit ownership of the buffer. + + @retval EFI_SUCCESS The read request was queued if Token->Event is + not NULL.The data was read correctly from the + device if the Token->Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while performing + the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the + intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack + of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_READ_EX) ( + IN EFI_BLOCK_IO2_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Write BufferSize bytes from Lba into Buffer. + + This function writes the requested number of blocks to the device. All blocks + are written, or an error is returned.If EFI_DEVICE_ERROR, EFI_NO_MEDIA, + EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED is returned and non-blocking I/O is + being used, the Event associated with this request will not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId The media ID that the write request is for. + @param[in] Lba The starting logical block address to be written. The + caller is responsible for writing to only legitimate + locations. + @param[in, out] Token A pointer to the token associated with the transaction. + @param[in] BufferSize Size of Buffer, must be a multiple of device block size. + @param[in] Buffer A pointer to the source buffer for the data. + + @retval EFI_SUCCESS The write request was queued if Event is not NULL. + The data was written correctly to the device if + the Event is NULL. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack + of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_WRITE_EX) ( + IN EFI_BLOCK_IO2_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO2_TOKEN *Token, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush the Block Device. + + If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED + is returned and non-blocking I/O is being used, the Event associated with + this request will not be signaled. + + @param[in] This Indicates a pointer to the calling context. + @param[in,out] Token A pointer to the token associated with the transaction + + @retval EFI_SUCCESS The flush request was queued if Event is not NULL. + All outstanding data was written correctly to the + device if the Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while writting back + the data. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack + of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_FLUSH_EX) ( + IN EFI_BLOCK_IO2_PROTOCOL *This, + IN OUT EFI_BLOCK_IO2_TOKEN *Token + ); + +/// +/// The Block I/O2 protocol defines an extension to the Block I/O protocol which +/// enables the ability to read and write data at a block level in a non-blocking +// manner. +/// +struct _EFI_BLOCK_IO2_PROTOCOL { + /// + /// A pointer to the EFI_BLOCK_IO_MEDIA data for this device. + /// Type EFI_BLOCK_IO_MEDIA is defined in BlockIo.h. + /// + EFI_BLOCK_IO_MEDIA *Media; + + EFI_BLOCK_RESET_EX Reset; + EFI_BLOCK_READ_EX ReadBlocksEx; + EFI_BLOCK_WRITE_EX WriteBlocksEx; + EFI_BLOCK_FLUSH_EX FlushBlocksEx; +}; + +extern EFI_GUID gEfiBlockIo2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIoCrypto.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIoCrypto.h new file mode 100644 index 0000000000..178d31830f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BlockIoCrypto.h @@ -0,0 +1,524 @@ +/** @file + The UEFI Inline Cryptographic Interface protocol provides services to abstract + access to inline cryptographic capabilities. + + Copyright (c) 2015-2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + +**/ + +#ifndef __BLOCK_IO_CRYPTO_H__ +#define __BLOCK_IO_CRYPTO_H__ + +#include + +#define EFI_BLOCK_IO_CRYPTO_PROTOCOL_GUID \ + { \ + 0xa00490ba, 0x3f1a, 0x4b4c, {0xab, 0x90, 0x4f, 0xa9, 0x97, 0x26, 0xa1, 0xe8} \ + } + +typedef struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL EFI_BLOCK_IO_CRYPTO_PROTOCOL; + +/// +/// The struct of Block I/O Crypto Token. +/// +typedef struct { + // + // If Event is NULL, then blocking I/O is performed. If Event is not NULL and + // non-blocking I/O is supported, then non-blocking I/O is performed, and + // Event will be signaled when the read request is completed and data was + // decrypted (when Index was specified). + // + EFI_EVENT Event; + // + // Defines whether or not the signaled event encountered an error. + // + EFI_STATUS TransactionStatus; +} EFI_BLOCK_IO_CRYPTO_TOKEN; + +typedef struct { + // + // GUID of the algorithm. + // + EFI_GUID Algorithm; + // + // Specifies KeySizein bits used with this Algorithm. + // + UINT64 KeySize; + // + // Specifies bitmask of block sizes supported by this algorithm. + // Bit j being set means that 2^j bytes crypto block size is supported. + // + UINT64 CryptoBlockSizeBitMask; +} EFI_BLOCK_IO_CRYPTO_CAPABILITY; + +/// +/// EFI_BLOCK_IO_CRYPTO_IV_INPUT structure is used as a common header in CryptoIvInput +/// parameters passed to the ReadExtended and WriteExtended methods for Inline +/// Cryptographic Interface. +/// Its purpose is to pass size of the entire CryptoIvInputparameter memory buffer to +/// the Inline Cryptographic Interface. +/// +typedef struct { + UINT64 InputSize; +} EFI_BLOCK_IO_CRYPTO_IV_INPUT; + +#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_XTS \ + { \ + 0x2f87ba6a, 0x5c04, 0x4385, {0xa7, 0x80, 0xf3, 0xbf, 0x78, 0xa9, 0x7b, 0xec} \ + } + +extern EFI_GUID gEfiBlockIoCryptoAlgoAesXtsGuid; + +typedef struct { + EFI_BLOCK_IO_CRYPTO_IV_INPUT Header; + UINT64 CryptoBlockNumber; + UINT64 CryptoBlockByteSize; +} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_XTS; + +#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_CBC_MICROSOFT_BITLOCKER \ + { \ + 0x689e4c62, 0x70bf, 0x4cf3, {0x88, 0xbb, 0x33, 0xb3, 0x18, 0x26, 0x86, 0x70} \ + } + +extern EFI_GUID gEfiBlockIoCryptoAlgoAesCbcMsBitlockerGuid; + +typedef struct { + EFI_BLOCK_IO_CRYPTO_IV_INPUT Header; + UINT64 CryptoBlockByteOffset; + UINT64 CryptoBlockByteSize; +} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_CBC_MICROSOFT_BITLOCKER; + +#define EFI_BLOCK_IO_CRYPTO_INDEX_ANY 0xFFFFFFFFFFFFFFFF + +typedef struct { + // + // Is inline cryptographic capability supported on this device. + // + BOOLEAN Supported; + // + // Maximum number of keys that can be configured at the same time. + // + UINT64 KeyCount; + // + // Number of supported capabilities. + // + UINT64 CapabilityCount; + // + // Array of supported capabilities. + // + EFI_BLOCK_IO_CRYPTO_CAPABILITY Capabilities[1]; +} EFI_BLOCK_IO_CRYPTO_CAPABILITIES; + +typedef struct { + // + // Configuration table index. A special Index EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be + // used to set any available entry in the configuration table. + // + UINT64 Index; + // + // Identifies the owner of the configuration table entry. Entry can also be used + // with the Nil value to clear key from the configuration table index. + // + EFI_GUID KeyOwnerGuid; + // + // A supported capability to be used. The CryptoBlockSizeBitMask field of the + // structure should have only one bit set from the supported mask. + // + EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability; + // + // Pointer to the key. The size of the key is defined by the KeySize field of + // the capability specified by the Capability parameter. + // + VOID *CryptoKey; +} EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY; + +typedef struct { + // + // Configuration table index. + // + UINT64 Index; + // + // Identifies the current owner of the entry. + // + EFI_GUID KeyOwnerGuid; + // + // The capability to be used. The CryptoBlockSizeBitMask field of the structure + // has only one bit set from the supported mask. + // + EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability; +} EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY; + +/** + Reset the block device hardware. + + The Reset() function resets the block device hardware. + + As part of the initialization process, the firmware/device will make a quick but + reasonable attempt to verify that the device is functioning. + + If the ExtendedVerificationflag is TRUE the firmware may take an extended amount + of time to verify the device is operating on reset. Otherwise the reset operation + is to occur as quickly as possible. + + The hardware verification process is not defined by this specification and is left + up to the platform firmware or driver to implement. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in] ExtendedVerification Indicates that the driver may perform a more exhausive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could + not be reset. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_RESET) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Get the capabilities of the underlying inline cryptographic interface. + + The GetCapabilities() function determines whether pre-OS controllable inline crypto + is supported by the system for the current disk and, if so, returns the capabilities + of the crypto engine. + + The caller is responsible for providing the Capabilities structure with a sufficient + number of entries. + + If the structure is too small, the EFI_BUFFER_TOO_SMALL error code is returned and the + CapabilityCount field contains the number of entries needed to contain the capabilities. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[out] Capabilities Pointer to the EFI_BLOCK_IO_CRYPTO_CAPABILITIES structure. + + @retval EFI_SUCCESS The ICI is ready for use. + @retval EFI_BUFFER_TOO_SMALL The Capabilities structure was too small. The number of + entries needed is returned in the CapabilityCount field + of the structure. + @retval EFI_NO_RESPONSE No response was received from the ICI. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER Capabilities is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + OUT EFI_BLOCK_IO_CRYPTO_CAPABILITIES *Capabilities + ); + +/** + Set the configuration of the underlying inline cryptographic interface. + + The SetConfiguration() function allows the user to set the current configuration of the + inline cryptographic interface and should be called before attempting any crypto operations. + + This configures the configuration table entries with algorithms, key sizes and keys. Each + configured entry can later be referred to by index at the time of storage transaction. + + The configuration table index will refer to the combination ofKeyOwnerGuid, Algorithm, and + CryptoKey. + + KeyOwnerGuid identifies the component taking ownership of the entry. It helps components to + identify their own entries, cooperate with other owner components, and avoid conflicts. This + Guid identifier is there to help coordination between cooperating components and not a security + or synchronization feature. The Nil GUID can be used by a component to release use of entry + owned. It is also used to identify potentially available entries (see GetConfiguration). + + CryptoKey specifies algorithm-specific key material to use within parameters of selected crypto + capability. + + This function is called infrequently typically once, on device start, before IO starts. It + can be called at later times in cases the number of keysused on the drive is higher than what + can be configured at a time or a new key has to be added. + + Components setting or changing an entry or entries for a given index or indices must ensure + that IO referencing affected indices is temporarily blocked (run-down) at the time of change. + + Indices parameters in each parameter table entry allow to set only a portion of the available + table entries in the crypto module anywhere from single entry to entire table supported. + + If corresponding table entry or entries being set are already in use by another owner the call + should be failed and none of the entries should be modified. The interface implementation must + enforce atomicity of this operation (should either succeed fully or fail completely without + modifying state). + + Note that components using GetConfiguration command to discover available entries should be + prepared that by the time of calling SetConfiguration the previously available entry may have + become occupied. Such components should be prepared to re-try the sequence of operations. + + Alternatively EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be used to have the implementation discover + and allocate available,if any, indices atomically. + + An optional ResultingTable pointer can be provided by the caller to receive the newly configured + entries. The array provided by the caller must have at least ConfigurationCount of entries. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in] ConfigurationCount Number of entries being configured with this call. + @param[in] ConfigurationTable Pointer to a table used to populate the configuration table. + @param[out] ResultingTable Optional pointer to a table that receives the newly configured + entries. + + @retval EFI_SUCCESS The ICI is ready for use. + @retval EFI_NO_RESPONSE No response was received from the ICI. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER ConfigurationTable is NULL. + @retval EFI_INVALID_PARAMETER ConfigurationCount is 0. + @retval EFI_OUT_OF_RESOURCES Could not find the requested number of available entries in the + configuration table. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN UINT64 ConfigurationCount, + IN EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY *ConfigurationTable, + OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ResultingTable OPTIONAL + ); + +/** + Get the configuration of the underlying inline cryptographic interface. + + The GetConfiguration() function allows the user to get the configuration of the inline + cryptographic interface. + + Retrieves, entirely or partially, the currently configured key table. Note that the keys + themselves are not retrieved, but rather just indices, owner GUIDs and capabilities. + + If fewer entries than specified by ConfigurationCount are returned, the Index field of the + unused entries is set to EFI_BLOCK_IO_CRYPTO_INDEX_ANY. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in] StartIndex Configuration table index at which to start the configuration + query. + @param[in] ConfigurationCount Number of entries to return in the response table. + @param[in] KeyOwnerGuid Optional parameter to filter response down to entries with a + given owner. A pointer to the Nil value can be used to return + available entries. Set to NULL when no owner filtering is required. + @param[out] ConfigurationTable Table of configured configuration table entries (with no CryptoKey + returned): configuration table index, KeyOwnerGuid, Capability. + Should have sufficient space to store up to ConfigurationCount + entries. + + @retval EFI_SUCCESS The ICI is ready for use. + @retval EFI_NO_RESPONSE No response was received from the ICI. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the ICI. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER Configuration table is NULL. + @retval EFI_INVALID_PARAMETER StartIndex is out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN UINT64 StartIndex, + IN UINT64 ConfigurationCount, + IN EFI_GUID *KeyOwnerGuid OPTIONAL, + OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ConfigurationTable +); + +/** + Reads the requested number of blocks from the device and optionally decrypts + them inline. + + TheReadExtended() function allows the caller to perform a storage device read + operation. The function reads the requested number of blocks from the device + and then if Index is specified decrypts them inline. All the blocks are read + and decrypted (if decryption requested), or an error is returned. + + If there is no media in the device, the function returns EFI_NO_MEDIA. If the + MediaId is not the ID for the current media in the device, the function returns + EFI_MEDIA_CHANGED. + + If EFI_DEVICE_ERROR, EFI_NO_MEDIA, or EFI_MEDIA_CHANGED is returned and nonblocking + I/O is being used, the Event associated with this request will not be signaled. + + In addition to standard storage transaction parameters (LBA, IO size, and buffer), + this command will also specify a configuration table Index and CryptoIvInput + when data has to be decrypted inline by the controller after being read from + the storage device. If an Index parameter is not specified, no decryption is + performed. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in] MediaId The media ID that the read request is for. + @param[in] LBA The starting logical block address to read from on + the device. + @param[in, out] Token A pointer to the token associated with the transaction. + @param[in] BufferSize The size of the Buffer in bytes. This must be a multiple + of the intrinsic block size of the device. + @param[out] Buffer A pointer to the destination buffer for the data. The + caller is responsible for either having implicit or + explicit ownership of the buffer. + @param[in] Index A pointer to the configuration table index. This is + optional. + @param[in] CryptoIvInput A pointer to a buffer that contains additional + cryptographic parameters as required by the capability + referenced by the configuration table index, such as + cryptographic initialization vector. + + @retval EFI_SUCCESS The read request was queued if Token-> Event is not NULL. + The data was read correctly from the device if the + Token->Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform + the read operation and/or decryption operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER This is NULL, or the read request contains LBAs that are + not valid, or the buffer is not on proper alignment. + @retval EFI_INVALID_PARAMETER CryptoIvInput is incorrect. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of + resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_READ_EXTENDED) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token, + IN UINT64 BufferSize, + OUT VOID *Buffer, + IN UINT64 *Index OPTIONAL, + IN VOID *CryptoIvInput OPTIONAL + ); + +/** + Optionally encrypts a specified number of blocks inline and then writes to the + device. + + The WriteExtended() function allows the caller to perform a storage device write + operation. The function encrypts the requested number of blocks inline if Index + is specified and then writes them to the device. All the blocks are encrypted + (if encryption requested) and written, or an error is returned. + + If there is no media in the device, the function returns EFI_NO_MEDIA. If the + MediaId is not the ID for the current media in the device, the function returns + EFI_MEDIA_CHANGED. + + If EFI_DEVICE_ERROR, EFI_NO_MEDIA, or EFI_MEDIA_CHANGED is returned and nonblocking + I/O is being used, the Event associated with this request will not be signaled. + + In addition to standard storage transaction parameters (LBA, IO size, and buffer), + this command will also specify a configuration table Index and a CryptoIvInput + when data has to be decrypted inline by the controller before being written to + the storage device. If no Index parameter is specified, no encryption is performed. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in] MediaId The media ID that the read request is for. + @param[in] LBA The starting logical block address to read from on + the device. + @param[in, out] Token A pointer to the token associated with the transaction. + @param[in] BufferSize The size of the Buffer in bytes. This must be a multiple + of the intrinsic block size of the device. + @param[in] Buffer A pointer to the source buffer for the data. + @param[in] Index A pointer to the configuration table index. This is + optional. + @param[in] CryptoIvInput A pointer to a buffer that contains additional + cryptographic parameters as required by the capability + referenced by the configuration table index, such as + cryptographic initialization vector. + + @retval EFI_SUCCESS The request to encrypt (optionally) and write was queued + if Event is not NULL. The data was encrypted (optionally) + and written correctly to the device if the Event is NULL. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to encrypt + blocks or to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER This is NULL, or the write request contains LBAs that are + not valid, or the buffer is not on proper alignment. + @retval EFI_INVALID_PARAMETER CryptoIvInput is incorrect. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of + resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token, + IN UINT64 BufferSize, + IN VOID *Buffer, + IN UINT64 *Index OPTIONAL, + IN VOID *CryptoIvInput OPTIONAL + ); + +/** + Flushes all modified data toa physical block device. + + The FlushBlocks() function flushes all modified data to the physical block device. + Any modified data that has to be encrypted must have been already encrypted as a + part of WriteExtended() operation - inline crypto operation cannot be a part of + flush operation. + + All data written to the device prior to the flush must be physically written before + returning EFI_SUCCESS from this function. This would include any cached data the + driver may have cached, and cached data the device may have cached. A flush may + cause a read request following the flush to force a device access. + + If EFI_DEVICE_ERROR, EFI_NO_MEDIA, EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED is + returned and non-blocking I/O is being used, the Event associated with this request + will not be signaled. + + @param[in] This Pointer to the EFI_BLOCK_IO_CRYPTO_PROTOCOL instance. + @param[in, out] Token A pointer to the token associated with the transaction. + + @retval EFI_SUCCESS The flush request was queued if Event is not NULL. All + outstanding data was written correctly to the device if + the Event is NULL. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of + resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_IO_CRYPTO_FLUSH) ( + IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This, + IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token + ); + +/// +/// The EFI_BLOCK_IO_CRYPTO_PROTOCOL defines a UEFI protocol that can be used by UEFI +/// drivers and applications to perform block encryption on a storage device, such as UFS. +/// +struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL { + EFI_BLOCK_IO_MEDIA *Media; + EFI_BLOCK_IO_CRYPTO_RESET Reset; + EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES GetCapabilities; + EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION SetConfiguration; + EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION GetConfiguration; + EFI_BLOCK_IO_CRYPTO_READ_EXTENDED ReadExtended; + EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED WriteExtended; + EFI_BLOCK_IO_CRYPTO_FLUSH FlushBlocks; +}; + +extern EFI_GUID gEfiBlockIoCryptoProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothAttribute.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothAttribute.h new file mode 100644 index 0000000000..eb39ea27f0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothAttribute.h @@ -0,0 +1,277 @@ +/** @file + EFI Bluetooth Attribute Protocol as defined in UEFI 2.7. + This protocol provides service for Bluetooth ATT (Attribute Protocol) and GATT (Generic + Attribute Profile) based protocol interfaces. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __EFI_BLUETOOTH_ATTRIBUTE_H__ +#define __EFI_BLUETOOTH_ATTRIBUTE_H__ + +#define EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x5639867a, 0x8c8e, 0x408d, { 0xac, 0x2f, 0x4b, 0x61, 0xbd, 0xc0, 0xbb, 0xbb } \ + } + +#define EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL_GUID \ + { \ + 0x898890e9, 0x84b2, 0x4f3a, { 0x8c, 0x58, 0xd8, 0x57, 0x78, 0x13, 0xe0, 0xac } \ + } + +typedef struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL; + +#pragma pack(1) + +// +// Bluetooth UUID +// +typedef struct { + UINT8 Length; + union { + UINT16 Uuid16; + UINT32 Uuid32; + UINT8 Uuid128[16]; + } Data; +} EFI_BLUETOOTH_UUID; + + +#define UUID_16BIT_TYPE_LEN 2 +#define UUID_32BIT_TYPE_LEN 4 +#define UUID_128BIT_TYPE_LEN 16 + +#define BLUETOOTH_IS_ATTRIBUTE_OF_TYPE(a,t) ((a)->Type.Length == UUID_16BIT_TYPE_LEN && (a)->Type.Data.Uuid16 == (t)) + +// +// Bluetooth Attribute Permission +// +typedef union { + struct { + UINT16 Readable : 1; + UINT16 ReadEncryption : 1; + UINT16 ReadAuthentication : 1; + UINT16 ReadAuthorization : 1; + UINT16 ReadKeySize : 5; + UINT16 Reserved1 : 7; + UINT16 Writeable : 1; + UINT16 WriteEncryption : 1; + UINT16 WriteAuthentication : 1; + UINT16 WriteAuthorization : 1; + UINT16 WriteKeySize : 5; + UINT16 Reserved2 : 7; + } Permission; + UINT32 Data32; +} EFI_BLUETOOTH_ATTRIBUTE_PERMISSION; + +typedef struct { + EFI_BLUETOOTH_UUID Type; + UINT16 Length; + UINT16 AttributeHandle; + EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission; +} EFI_BLUETOOTH_ATTRIBUTE_HEADER; + +typedef struct { + EFI_BLUETOOTH_ATTRIBUTE_HEADER Header; + UINT16 EndGroupHandle; + EFI_BLUETOOTH_UUID ServiceUuid; +} EFI_BLUETOOTH_GATT_PRIMARY_SERVICE_INFO; + +typedef struct { + EFI_BLUETOOTH_ATTRIBUTE_HEADER Header; + UINT16 StartGroupHandle; + UINT16 EndGroupHandle; + EFI_BLUETOOTH_UUID ServiceUuid; +} EFI_BLUETOOTH_GATT_INCLUDE_SERVICE_INFO; + +typedef struct { + EFI_BLUETOOTH_ATTRIBUTE_HEADER Header; + UINT8 CharacteristicProperties; + UINT16 CharacteristicValueHandle; + EFI_BLUETOOTH_UUID CharacteristicUuid; +} EFI_BLUETOOTH_GATT_CHARACTERISTIC_INFO; + +typedef struct { + EFI_BLUETOOTH_ATTRIBUTE_HEADER Header; + EFI_BLUETOOTH_UUID CharacteristicDescriptorUuid; +} EFI_BLUETOOTH_GATT_CHARACTERISTIC_DESCRIPTOR_INFO; + +#pragma pack() + +typedef struct { + UINT16 AttributeHandle; +} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION; + +typedef struct { + UINT16 AttributeHandle; +} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION; + +typedef struct { + UINT32 Version; + UINT8 AttributeOpCode; + union { + EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION Notification; + EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION Indication; + } Parameter; +} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER; + +typedef struct { + UINT32 Version; + BLUETOOTH_LE_ADDRESS BD_ADDR; + BLUETOOTH_LE_ADDRESS DirectAddress; + UINT8 RSSI; + UINTN AdvertisementDataSize; + VOID *AdvertisementData; +} EFI_BLUETOOTH_LE_DEVICE_INFO; + +/** + The callback function to send request. + + @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. + @param[in] Data Data received. The first byte is the attribute opcode, followed by opcode specific + fields. See Bluetooth specification, Vol 3, Part F, Attribute Protocol. It might be a + normal RESPONSE message, or ERROR RESPONSE messag + @param[in] DataLength The length of Data in bytes. + @param[in] Context The context passed from the callback registration request. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION) ( + IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This, + IN VOID *Data, + IN UINTN DataLength, + IN VOID *Context + ); + +/** + Send a "REQUEST" or "COMMAND" message to remote server and receive a "RESPONSE" message + for "REQUEST" from remote server according to Bluetooth attribute protocol data unit(PDU). + + @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. + @param[in] Data Data of a REQUEST or COMMAND message. The first byte is the attribute PDU + related opcode, followed by opcode specific fields. See Bluetooth specification, + Vol 3, Part F, Attribute Protocol. + @param[in] DataLength The length of Data in bytes. + @param[in] Callback Callback function to notify the RESPONSE is received to the caller, with the + response buffer. Caller must check the response buffer content to know if the + request action is success or fail. It may be NULL if the data is a COMMAND. + @param[in] Context Data passed into Callback function. It is optional parameter and may be NULL. + + @retval EFI_SUCCESS The request is sent successfully. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid due to following conditions: + - The Buffer is NULL. + - The BufferLength is 0. + - The opcode in Buffer is not a valid OPCODE according to Bluetooth specification. + - The Callback is NULL. + @retval EFI_DEVICE_ERROR Sending the request failed due to the host controller or the device error. + @retval EFI_NOT_READY A GATT operation is already underway for this device. + @retval EFI_UNSUPPORTED The attribute does not support the corresponding operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST) ( + IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This, + IN VOID *Data, + IN UINTN DataLength, + IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + Register or unregister a server initiated message, such as NOTIFICATION or INDICATION, on a + characteristic value on remote server. + + @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. + @param[in] CallbackParameter The parameter of the callback. + @param[in] Callback Callback function for server initiated attribute protocol. NULL callback + function means unregister the server initiated callback. + @param[in] Context Data passed into Callback function. It is optional parameter and may be NULL. + + @retval EFI_SUCCESS The callback function is registered or unregistered successfully + @retval EFI_INVALID_PARAMETER The attribute opcode is not server initiated message opcode. See + Bluetooth specification, Vol 3, Part F, Attribute Protocol. + @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute + opcode and attribute handle, when the Callback is not NULL. + @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode + and attribute handle, when the Callback is NULL. + @retval EFI_NOT_READY A GATT operation is already underway for this device. + @retval EFI_UNSUPPORTED The attribute does not support notification. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION)( + IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This, + IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER *CallbackParameter, + IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + Get Bluetooth discovered service information. + + @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. + @param[out] ServiceInfoSize A pointer to the size, in bytes, of the ServiceInfo buffer. + @param[out] ServiceInfo A pointer to a callee allocated buffer that returns Bluetooth + discovered service information. Callee allocates this buffer by + using EFI Boot Service AllocatePool(). + + @retval EFI_SUCCESS The Bluetooth discovered service information is returned successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth discovered + service information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO)( + IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This, + OUT UINTN *ServiceInfoSize, + OUT VOID **ServiceInfo + ); + +/** + Get Bluetooth device information. + + @param[in] This Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance. + @param[out] DeviceInfoSize A pointer to the size, in bytes, of the DeviceInfo buffer. + @param[out] DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth + device information. Callee allocates this buffer by using EFI Boot + Service AllocatePool(). If this device is Bluetooth classic + device, EFI_BLUETOOTH_DEVICE_INFO should be used. If + this device is Bluetooth LE device, EFI_BLUETOOTH_LE_DEVICE_INFO + should be used. + + @retval EFI_SUCCESS The Bluetooth device information is returned successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth device + information + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO)( + IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This, + OUT UINTN *DeviceInfoSize, + OUT VOID **DeviceInfo + ); + +struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL { + EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST SendRequest; + EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION RegisterForServerNotification; + EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO GetServiceInfo; + EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO GetDeviceInfo; +}; + + +extern EFI_GUID gEfiBluetoothAttributeProtocolGuid; +extern EFI_GUID gEfiBluetoothAttributeServiceBindingProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothConfig.h new file mode 100644 index 0000000000..8a60131734 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothConfig.h @@ -0,0 +1,523 @@ +/** @file + EFI Bluetooth Configuration Protocol as defined in UEFI 2.7. + This protocol abstracts user interface configuration for Bluetooth device. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __EFI_BLUETOOTH_CONFIG_PROTOCOL_H__ +#define __EFI_BLUETOOTH_CONFIG_PROTOCOL_H__ + +#include + +#define EFI_BLUETOOTH_CONFIG_PROTOCOL_GUID \ + { \ + 0x62960cf3, 0x40ff, 0x4263, { 0xa7, 0x7c, 0xdf, 0xde, 0xbd, 0x19, 0x1b, 0x4b } \ + } + +typedef struct _EFI_BLUETOOTH_CONFIG_PROTOCOL EFI_BLUETOOTH_CONFIG_PROTOCOL; + +typedef UINT32 EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE; +#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_CONNECTED 0x1 +#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_PAIRED 0x2 + +/// +/// EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION +/// +typedef struct { + /// + /// 48bit Bluetooth device address. + /// + BLUETOOTH_ADDRESS BDAddr; + /// + /// State of the remote deive + /// + UINT8 RemoteDeviceState; + /// + /// Bluetooth ClassOfDevice. See Bluetooth specification for detail. + /// + BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice; + /// + /// Remote device name + /// + UINT8 RemoteDeviceName[BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE]; +} EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION; + +/// +/// EFI_BLUETOOTH_CONFIG_DATA_TYPE +/// +typedef enum { + /// + /// Local/Remote Bluetooth device name. Data structure is zero terminated CHAR8[]. + /// + EfiBluetoothConfigDataTypeDeviceName, + /// + /// Local/Remote Bluetooth device ClassOfDevice. Data structure is BLUETOOTH_CLASS_OF_DEVICE. + /// + EfiBluetoothConfigDataTypeClassOfDevice, + /// + /// Remote Bluetooth device state. Data structure is EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE. + /// + EfiBluetoothConfigDataTypeRemoteDeviceState, /* Relevant for LE*/ + /// + /// Local/Remote Bluetooth device SDP information. Data structure is UINT8[]. + /// + EfiBluetoothConfigDataTypeSdpInfo, + /// + /// Local Bluetooth device address. Data structure is BLUETOOTH_ADDRESS. + /// + EfiBluetoothConfigDataTypeBDADDR, /* Relevant for LE*/ + /// + /// Local Bluetooth discoverable state. Data structure is UINT8. (Page scan and/or Inquiry scan) + /// + EfiBluetoothConfigDataTypeDiscoverable, /* Relevant for LE*/ + /// + /// Local Bluetooth controller stored paired device list. Data structure is BLUETOOTH_ADDRESS[]. + /// + EfiBluetoothConfigDataTypeControllerStoredPairedDeviceList, + /// + /// Local available device list. Data structure is BLUETOOTH_ADDRESS[]. + /// + EfiBluetoothConfigDataTypeAvailableDeviceList, + EfiBluetoothConfigDataTypeRandomAddress, /* Relevant for LE*/ + EfiBluetoothConfigDataTypeRSSI, /* Relevant for LE*/ + /// + /// Advertisement report. Data structure is UNIT8[]. + /// + EfiBluetoothConfigDataTypeAdvertisementData, /* Relevant for LE*/ + EfiBluetoothConfigDataTypeIoCapability, /* Relevant for LE*/ + EfiBluetoothConfigDataTypeOOBDataFlag, /* Relevant for LE*/ + /// + /// KeyType of Authentication Requirements flag of local + /// device as UINT8, indicating requested security properties. + /// See Bluetooth specification 3.H.3.5.1. BIT0: MITM, BIT1:SC. + /// + EfiBluetoothConfigDataTypeKeyType, /* Relevant for LE*/ + EfiBluetoothConfigDataTypeEncKeySize, /* Relevant for LE*/ + EfiBluetoothConfigDataTypeMax, +} EFI_BLUETOOTH_CONFIG_DATA_TYPE; + +/// +/// EFI_BLUETOOTH_PIN_CALLBACK_TYPE. +/// +typedef enum { + /// + /// For SSP - passkey entry. Input buffer is Passkey (4 bytes). No output buffer. + /// See Bluetooth HCI command for detail. + /// + EfiBluetoothCallbackTypeUserPasskeyNotification, + /// + /// For SSP - just work and numeric comparison. Input buffer is numeric value (4 bytes). + /// Output buffer is BOOLEAN (1 byte). See Bluetooth HCI command for detail. + /// + EfiBluetoothCallbackTypeUserConfirmationRequest, + /// + /// For SSP - OOB. See Bluetooth HCI command for detail. + /// + EfiBluetoothCallbackTypeOOBDataRequest, + /// + /// For legacy paring. No input buffer. Output buffer is PIN code( <= 16 bytes). + /// See Bluetooth HCI command for detail. + /// + EfiBluetoothCallbackTypePinCodeRequest, + EfiBluetoothCallbackTypeMax +} EFI_BLUETOOTH_PIN_CALLBACK_TYPE; + +/// +/// EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE. +/// +typedef enum { + /// + /// This callback is called when Bluetooth receive Disconnection_Complete event. Input buffer is Event + /// Parameters of Disconnection_Complete Event defined in Bluetooth specification. + /// + EfiBluetoothConnCallbackTypeDisconnected, + /// + /// This callback is called when Bluetooth receive Connection_Complete event. Input buffer is Event + /// Parameters of Connection_Complete Event defined in Bluetooth specification. + /// + EfiBluetoothConnCallbackTypeConnected, + /// + /// This callback is called when Bluetooth receive Authentication_Complete event. Input buffer is Event + /// Parameters of Authentication_Complete Event defined in Bluetooth specification. + /// + EfiBluetoothConnCallbackTypeAuthenticated, + /// + /// This callback is called when Bluetooth receive Encryption_Change event. Input buffer is Event + /// Parameters of Encryption_Change Event defined in Bluetooth specification. + /// + EfiBluetoothConnCallbackTypeEncrypted +} EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE; + + +/** + Initialize Bluetooth host controller and local device. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + + @retval EFI_SUCCESS The Bluetooth host controller and local device is initialized successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to initialize the Bluetooth host controller + and local device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_INIT)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This + ); + +/** + Callback function, it is called if a Bluetooth device is found during scan process. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Context Context passed from scan request. + @param CallbackInfo Data related to scan result. NULL CallbackInfo means scan complete. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION) ( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION *CallbackInfo + ); + +/** + Scan Bluetooth device. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param ReScan If TRUE, a new scan request is submitted no matter there is scan result before. + If FALSE and there is scan result, the previous scan result is returned and no scan request + is submitted. + @param ScanType Bluetooth scan type, Inquiry and/or Page. See Bluetooth specification for detail. + @param Callback The callback function. This function is called if a Bluetooth device is found during scan + process. + @param Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The Bluetooth scan request is submitted. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to scan the Bluetooth device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN BOOLEAN ReScan, + IN UINT8 ScanType, + IN EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + Connect a Bluetooth device. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param BD_ADDR The address of Bluetooth device to be connected. + + @retval EFI_SUCCESS The Bluetooth device is connected successfully. + @retval EFI_ALREADY_STARTED The Bluetooth device is already connected. + @retval EFI_NOT_FOUND The Bluetooth device is not found. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to connect the Bluetooth device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_CONNECT)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN BLUETOOTH_ADDRESS *BD_ADDR + ); + +/** + Disconnect a Bluetooth device. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param BD_ADDR The address of Bluetooth device to be connected. + @param Reason Bluetooth disconnect reason. See Bluetooth specification for detail. + + @retval EFI_SUCCESS The Bluetooth device is disconnected successfully. + @retval EFI_NOT_STARTED The Bluetooth device is not connected. + @retval EFI_NOT_FOUND The Bluetooth device is not found. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the Bluetooth device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_DISCONNECT)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN BLUETOOTH_ADDRESS *BD_ADDR, + IN UINT8 Reason + ); + +/** + Get Bluetooth configuration data. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param DataType Configuration data type. + @param DataSize On input, indicates the size, in bytes, of the data buffer specified by Data. + On output, indicates the amount of data actually returned. + @param Data A pointer to the buffer of data that will be returned. + + @retval EFI_SUCCESS The Bluetooth configuration data is returned successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is NULL. + - *DataSize is not 0 and Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The DataType is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. + *DataSize has been updated with the size needed to complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_DATA)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN OUT UINTN *DataSize, + IN OUT VOID *Data + ); + +/** + Set Bluetooth configuration data. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param DataType Configuration data type. + @param DataSize Indicates the size, in bytes, of the data buffer specified by Data. + @param Data A pointer to the buffer of data that will be set. + + @retval EFI_SUCCESS The Bluetooth configuration data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is 0. + - Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_BUFFER_TOO_SMALL Cannot set configuration data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_SET_DATA)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Get remove Bluetooth device configuration data. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param DataType Configuration data type. + @param BDAddr Remote Bluetooth device address. + @param DataSize On input, indicates the size, in bytes, of the data buffer specified by Data. + On output, indicates the amount of data actually returned. + @param Data A pointer to the buffer of data that will be returned. + + @retval EFI_SUCCESS The remote Bluetooth device configuration data is returned successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is NULL. + - *DataSize is not 0 and Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The DataType is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. + *DataSize has been updated with the size needed to complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN BLUETOOTH_ADDRESS *BDAddr, + IN OUT UINTN *DataSize, + IN OUT VOID *Data + ); + +/** + The callback function for PIN code. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Context Context passed from registration. + @param CallbackType Callback type in EFI_BLUETOOTH_PIN_CALLBACK_TYPE. + @param InputBuffer A pointer to the buffer of data that is input from callback caller. + @param InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer. + @param OutputBuffer A pointer to the buffer of data that will be output from callback callee. + Callee allocates this buffer by using EFI Boot Service AllocatePool(). + @param OutputBufferSize Indicates the size, in bytes, of the data buffer specified by OutputBuffer. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN EFI_BLUETOOTH_PIN_CALLBACK_TYPE CallbackType, + IN VOID *InputBuffer, + IN UINTN InputBufferSize, + OUT VOID **OutputBuffer, + OUT UINTN *OutputBufferSize + ); + +/** + Register PIN callback function. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Callback The callback function. NULL means unregister. + @param Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The PIN callback function is registered successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + The callback function to get link key. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Context Context passed from registration. + @param BDAddr A pointer to Bluetooth device address. + @param LinkKey A pointer to the buffer of link key. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN BLUETOOTH_ADDRESS *BDAddr, + OUT UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE] + ); + +/** + Register get link key callback function. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Callback The callback function. NULL means unregister. + @param Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The link key callback function is registered successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + The callback function to set link key. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Context Context passed from registration. + @param BDAddr A pointer to Bluetooth device address. + @param LinkKey A pointer to the buffer of link key. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN BLUETOOTH_ADDRESS *BDAddr, + IN UINT8 LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE] + ); + +/** + Register set link key callback function. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Callback The callback function. NULL means unregister. + @param Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The link key callback function is registered successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/** + The callback function. It is called after connect completed. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Context Context passed from registration. + @param CallbackType Callback type in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE. + @param BDAddr A pointer to Bluetooth device address. + @param InputBuffer A pointer to the buffer of data that is input from callback caller. + @param InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType, + IN BLUETOOTH_ADDRESS *BDAddr, + IN VOID *InputBuffer, + IN UINTN InputBufferSize + ); + +/** + Register link connect complete callback function. + + @param This Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance. + @param Callback The callback function. NULL means unregister. + @param Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The link connect complete callback function is registered successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK)( + IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +/// +/// This protocol abstracts user interface configuration for Bluetooth device. +/// +struct _EFI_BLUETOOTH_CONFIG_PROTOCOL { + EFI_BLUETOOTH_CONFIG_INIT Init; + EFI_BLUETOOTH_CONFIG_SCAN Scan; + EFI_BLUETOOTH_CONFIG_CONNECT Connect; + EFI_BLUETOOTH_CONFIG_DISCONNECT Disconnect; + EFI_BLUETOOTH_CONFIG_GET_DATA GetData; + EFI_BLUETOOTH_CONFIG_SET_DATA SetData; + EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA GetRemoteData; + EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK RegisterPinCallback; + EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK RegisterGetLinkKeyCallback; + EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK RegisterSetLinkKeyCallback; + EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback; +}; + +extern EFI_GUID gEfiBluetoothConfigProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothHc.h new file mode 100644 index 0000000000..9bcb777e78 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothHc.h @@ -0,0 +1,418 @@ +/** @file + EFI Bluetooth Host Controller Protocol as defined in UEFI 2.5. + This protocol abstracts the Bluetooth host controller layer message transmit and receive. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_BLUETOOTH_HC_PROTOCOL_H__ +#define __EFI_BLUETOOTH_HC_PROTOCOL_H__ + +#define EFI_BLUETOOTH_HC_PROTOCOL_GUID \ + { \ + 0xb3930571, 0xbeba, 0x4fc5, { 0x92, 0x3, 0x94, 0x27, 0x24, 0x2e, 0x6a, 0x43 } \ + } + +typedef struct _EFI_BLUETOOTH_HC_PROTOCOL EFI_BLUETOOTH_HC_PROTOCOL; + +/** + Send HCI command packet. + + The SendCommand() function sends HCI command packet. Buffer holds the whole HCI + command packet, including OpCode, OCF, OGF, parameter length, and parameters. When + this function is returned, it just means the HCI command packet is sent, it does not mean + the command is success or complete. Caller might need to wait a command status event + to know the command status, or wait a command complete event to know if the + command is completed. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[in] Buffer A pointer to the buffer of data that will be transmitted to + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI command packet is sent successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Sending HCI command packet fail due to timeout. + @retval EFI_DEVICE_ERROR Sending HCI command packet fail due to host controller or device + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_SEND_COMMAND)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive HCI event packet. + + The ReceiveEvent() function receives HCI event packet. Buffer holds the whole HCI event + packet, including EventCode, parameter length, and parameters. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[out] Buffer A pointer to the buffer of data that will be received from + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI event packet is received successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Receiving HCI event packet fail due to timeout. + @retval EFI_DEVICE_ERROR Receiving HCI event packet fail due to host controller or device + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_EVENT)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + IN UINTN Timeout + ); + +/** + The async callback of AsyncReceiveEvent(). + + @param[in] Data Data received via asynchronous transfer. + @param[in] DataLength The length of Data in bytes, received via asynchronous + transfer. + @param[in] Context Context passed from asynchronous transfer request. + + @retval EFI_SUCCESS The callback does execute successfully. + @retval Others The callback doesn't execute successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK) ( + IN VOID *Data, + IN UINTN DataLength, + IN VOID *Context + ); + +/** + Receive HCI event packet in non-blocking way. + + The AsyncReceiveEvent() function receives HCI event packet in non-blocking way. Data + in Callback function holds the whole HCI event packet, including EventCode, parameter + length, and parameters. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the + request is deleted. + @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the + transfer is to be executed. + @param[in] DataLength Specifies the length, in bytes, of the data to be received. + @param[in] Callback The callback function. This function is called if the + asynchronous transfer is completed. + @param[in] Context Data passed into Callback function. This is optional + parameter and may be NULL. + + @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + DataLength is 0. + If IsNewTransfer is TRUE, and an asynchronous receive + request already exists. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT) ( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN BOOLEAN IsNewTransfer, + IN UINTN PollingInterval, + IN UINTN DataLength, + IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback, + IN VOID *Context + ); + +/** + Send HCI ACL data packet. + + The SendACLData() function sends HCI ACL data packet. Buffer holds the whole HCI ACL + data packet, including Handle, PB flag, BC flag, data length, and data. + + The SendACLData() function and ReceiveACLData() function just send and receive data + payload from application layer. In order to protect the payload data, the Bluetooth bus is + required to call HCI_Set_Connection_Encryption command to enable hardware based + encryption after authentication completed, according to pairing mode and host + capability. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[in] Buffer A pointer to the buffer of data that will be transmitted to + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI ACL data packet is sent successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Sending HCI ACL data packet fail due to timeout. + @retval EFI_DEVICE_ERROR Sending HCI ACL data packet fail due to host controller or device + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_SEND_ACL_DATA)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive HCI ACL data packet. + + The ReceiveACLData() function receives HCI ACL data packet. Buffer holds the whole HCI + ACL data packet, including Handle, PB flag, BC flag, data length, and data. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[out] Buffer A pointer to the buffer of data that will be received from + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI ACL data packet is received successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Receiving HCI ACL data packet fail due to timeout. + @retval EFI_DEVICE_ERROR Receiving HCI ACL data packet fail due to host controller or device + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive HCI ACL data packet in non-blocking way. + + The AsyncReceiveACLData() function receives HCI ACL data packet in non-blocking way. + Data in Callback holds the whole HCI ACL data packet, including Handle, PB flag, BC flag, + data length, and data. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the + request is deleted. + @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the + transfer is to be executed. + @param[in] DataLength Specifies the length, in bytes, of the data to be received. + @param[in] Callback The callback function. This function is called if the + asynchronous transfer is completed. + @param[in] Context Data passed into Callback function. This is optional + parameter and may be NULL. + + @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + DataLength is 0. + If IsNewTransfer is TRUE, and an asynchronous receive + request already exists. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA) ( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN BOOLEAN IsNewTransfer, + IN UINTN PollingInterval, + IN UINTN DataLength, + IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback, + IN VOID *Context + ); + +/** + Send HCI SCO data packet. + + The SendSCOData() function sends HCI SCO data packet. Buffer holds the whole HCI SCO + data packet, including ConnectionHandle, PacketStatus flag, data length, and data. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[in] Buffer A pointer to the buffer of data that will be transmitted to + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI SCO data packet is sent successfully. + @retval EFI_UNSUPPORTED The implementation does not support HCI SCO transfer. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Sending HCI SCO data packet fail due to timeout. + @retval EFI_DEVICE_ERROR Sending HCI SCO data packet fail due to host controller or device + error. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_SEND_SCO_DATA)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive HCI SCO data packet. + + The ReceiveSCOData() function receives HCI SCO data packet. Buffer holds the whole HCI + SCO data packet, including ConnectionHandle, PacketStatus flag, data length, and data. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in,out] BufferSize On input, indicates the size, in bytes, of the data buffer + specified by Buffer. On output, indicates the amount of + data actually transferred. + @param[out] Buffer A pointer to the buffer of data that will be received from + Bluetooth host controller. + @param[in] Timeout Indicating the transfer should be completed within this + time frame. The units are in milliseconds. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The HCI SCO data packet is received successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is 0. + Buffer is NULL. + @retval EFI_TIMEOUT Receiving HCI SCO data packet fail due to timeout. + @retval EFI_DEVICE_ERROR Receiving HCI SCO data packet fail due to host controller or device + error. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA)( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive HCI SCO data packet in non-blocking way. + + The AsyncReceiveSCOData() function receives HCI SCO data packet in non-blocking way. + Data in Callback holds the whole HCI SCO data packet, including ConnectionHandle, + PacketStatus flag, data length, and data. + + @param[in] This Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance. + @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the + request is deleted. + @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the + transfer is to be executed. + @param[in] DataLength Specifies the length, in bytes, of the data to be received. + @param[in] Callback The callback function. This function is called if the + asynchronous transfer is completed. + @param[in] Context Data passed into Callback function. This is optional + parameter and may be NULL. + + @retval EFI_SUCCESS The HCI asynchronous receive request is submitted successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + DataLength is 0. + If IsNewTransfer is TRUE, and an asynchronous receive + request already exists. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA) ( + IN EFI_BLUETOOTH_HC_PROTOCOL *This, + IN BOOLEAN IsNewTransfer, + IN UINTN PollingInterval, + IN UINTN DataLength, + IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback, + IN VOID *Context + ); + +// +// The EFI_BLUETOOTH_HC_PROTOCOL is used to transmit or receive HCI layer data packets. +// +struct _EFI_BLUETOOTH_HC_PROTOCOL { + // + // Send HCI command packet. + // + EFI_BLUETOOTH_HC_SEND_COMMAND SendCommand; + // + // Receive HCI event packets. + // + EFI_BLUETOOTH_HC_RECEIVE_EVENT ReceiveEvent; + // + // Non-blocking receive HCI event packets. + // + EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT AsyncReceiveEvent; + // + // Send HCI ACL (asynchronous connection-oriented) data packets. + // + EFI_BLUETOOTH_HC_SEND_ACL_DATA SendACLData; + // + // Receive HCI ACL data packets. + // + EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA ReceiveACLData; + // + // Non-blocking receive HCI ACL data packets. + // + EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA AsyncReceiveACLData; + // + // Send HCI synchronous (SCO and eSCO) data packets. + // + EFI_BLUETOOTH_HC_SEND_SCO_DATA SendSCOData; + // + // Receive HCI synchronous data packets. + // + EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA ReceiveSCOData; + // + // Non-blocking receive HCI synchronous data packets. + // + EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA AsyncReceiveSCOData; +}; + +extern EFI_GUID gEfiBluetoothHcProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothIo.h new file mode 100644 index 0000000000..6530d8e104 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothIo.h @@ -0,0 +1,411 @@ +/** @file + EFI Bluetooth IO Service Binding Protocol as defined in UEFI 2.5. + EFI Bluetooth IO Protocol as defined in UEFI 2.5. + The EFI Bluetooth IO Service Binding Protocol is used to locate EFI Bluetooth IO Protocol drivers to + create and destroy child of the driver to communicate with other Bluetooth device by using Bluetooth IO protocol. + + Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_BLUETOOTH_IO_PROTOCOL_H__ +#define __EFI_BLUETOOTH_IO_PROTOCOL_H__ + +#include + +#define EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x388278d3, 0x7b85, 0x42f0, { 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab } \ + } + +#define EFI_BLUETOOTH_IO_PROTOCOL_GUID \ + { \ + 0x467313de, 0x4e30, 0x43f1, { 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5 } \ + } + +typedef struct _EFI_BLUETOOTH_IO_PROTOCOL EFI_BLUETOOTH_IO_PROTOCOL; + +/// +/// EFI_BLUETOOTH_DEVICE_INFO +/// +typedef struct { + /// + /// The version of the structure + /// + UINT32 Version; + /// + /// 48bit Bluetooth device address. + /// + BLUETOOTH_ADDRESS BD_ADDR; + /// + /// Bluetooth PageScanRepetitionMode. See Bluetooth specification for detail. + /// + UINT8 PageScanRepetitionMode; + /// + /// Bluetooth ClassOfDevice. See Bluetooth specification for detail. + /// + BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice; + /// + /// Bluetooth CloseOffset. See Bluetooth specification for detail. + /// + UINT16 ClockOffset; + /// + /// Bluetooth RSSI. See Bluetooth specification for detail. + /// + UINT8 RSSI; + /// + /// Bluetooth ExtendedInquiryResponse. See Bluetooth specification for detail. + /// + UINT8 ExtendedInquiryResponse[240]; +} EFI_BLUETOOTH_DEVICE_INFO; + +/** + Get Bluetooth device information. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[out] DeviceInfoSize A pointer to the size, in bytes, of the DeviceInfo buffer. + @param[out] DeviceInfo A pointer to a callee allocated buffer that returns Bluetooth device information. + + @retval EFI_SUCCESS The Bluetooth device information is returned successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth device information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_GET_DEVICE_INFO)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + OUT UINTN *DeviceInfoSize, + OUT VOID **DeviceInfo + ); + +/** + Get Bluetooth SDP information. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[out] SdpInfoSize A pointer to the size, in bytes, of the SdpInfo buffer. + @param[out] SdpInfo A pointer to a callee allocated buffer that returns Bluetooth SDP information. + + @retval EFI_SUCCESS The Bluetooth device information is returned successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the Bluetooth SDP information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_GET_SDP_INFO)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + OUT UINTN *SdpInfoSize, + OUT VOID **SdpInfo + ); + +/** + Send L2CAP message (including L2CAP header). + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer. + On output, indicates the amount of data actually transferred. + @param[in] Buffer A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer. + @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in + milliseconds. If Timeout is 0, then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The L2CAP message is sent successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - BufferSize is NULL. + - *BufferSize is 0. + - Buffer is NULL. + @retval EFI_TIMEOUT Sending L2CAP message fail due to timeout. + @retval EFI_DEVICE_ERROR Sending L2CAP message fail due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_SEND)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive L2CAP message (including L2CAP header). + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer. + On output, indicates the amount of data actually transferred. + @param[out] Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer. + @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in + milliseconds. If Timeout is 0, then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The L2CAP message is received successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - BufferSize is NULL. + - *BufferSize is 0. + - Buffer is NULL. + @retval EFI_TIMEOUT Receiving L2CAP message fail due to timeout. + @retval EFI_DEVICE_ERROR Receiving L2CAP message fail due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + IN UINTN Timeout + ); + +/** + Callback function, it is called when asynchronous transfer is completed. + + @param[in] ChannelID Bluetooth L2CAP message channel ID. + @param[in] Data Data received via asynchronous transfer. + @param[in] DataLength The length of Data in bytes, received via asynchronous transfer. + @param[in] Context Context passed from asynchronous transfer request. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK) ( + IN UINT16 ChannelID, + IN VOID *Data, + IN UINTN DataLength, + IN VOID *Context + ); + +/** + Receive L2CAP message (including L2CAP header) in non-blocking way. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] IsNewTransfer If TRUE, a new transfer will be submitted. If FALSE, the request is deleted. + @param[in] PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be executed. + @param[in] DataLength Specifies the length, in bytes, of the data to be received. + @param[in] Callback The callback function. This function is called if the asynchronous transfer is + completed. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The L2CAP asynchronous receive request is submitted successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataLength is 0. + - If IsNewTransfer is TRUE, and an asynchronous receive request already exists. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN BOOLEAN IsNewTransfer, + IN UINTN PollingInterval, + IN UINTN DataLength, + IN EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK Callback, + IN VOID *Context + ); + +/** + Send L2CAP message (excluding L2CAP header) to a specific channel. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to send. + @param[in, out] BufferSize On input, indicates the size, in bytes, of the data buffer specified by Buffer. + On output, indicates the amount of data actually transferred. + @param[in] Buffer A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer. + @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in + milliseconds. If Timeout is 0, then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The L2CAP message is sent successfully. + @retval EFI_NOT_FOUND Handle is invalid or not found. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - BufferSize is NULL. + - *BufferSize is 0. + - Buffer is NULL. + @retval EFI_TIMEOUT Sending L2CAP message fail due to timeout. + @retval EFI_DEVICE_ERROR Sending L2CAP message fail due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_SEND)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN EFI_HANDLE Handle, + IN OUT UINTN *BufferSize, + IN VOID *Buffer, + IN UINTN Timeout + ); + +/** + Receive L2CAP message (excluding L2CAP header) from a specific channel. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] Handle A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive. + @param[out] BufferSize Indicates the size, in bytes, of the data buffer specified by Buffer. + @param[out] Buffer A pointer to the buffer of data that will be received from Bluetooth L2CAP layer. + @param[in] Timeout Indicating the transfer should be completed within this time frame. The units are in + milliseconds. If Timeout is 0, then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + + @retval EFI_SUCCESS The L2CAP message is received successfully. + @retval EFI_NOT_FOUND Handle is invalid or not found. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - BufferSize is NULL. + - *BufferSize is 0. + - Buffer is NULL. + @retval EFI_TIMEOUT Receiving L2CAP message fail due to timeout. + @retval EFI_DEVICE_ERROR Receiving L2CAP message fail due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RECEIVE)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN EFI_HANDLE Handle, + OUT UINTN *BufferSize, + OUT VOID **Buffer, + IN UINTN Timeout + ); + +/** + Callback function, it is called when asynchronous transfer is completed. + + @param[in] Data Data received via asynchronous transfer. + @param[in] DataLength The length of Data in bytes, received via asynchronous transfer. + @param[in] Context Context passed from asynchronous transfer request. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK) ( + IN VOID *Data, + IN UINTN DataLength, + IN VOID *Context + ); + +/** + Receive L2CAP message (excluding L2CAP header) in non-blocking way from a specific channel. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] Handel A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel + to receive. + @param[in] Callback The callback function. This function is called if the asynchronous transfer is + completed. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The L2CAP asynchronous receive request is submitted successfully. + @retval EFI_NOT_FOUND Handle is invalid or not found. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataLength is 0. + - If an asynchronous receive request already exists on same Handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN EFI_HANDLE Handle, + IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback, + IN VOID* Context + ); + +/** + Do L2CAP connection. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[out] Handel A handle to indicate this L2CAP connection. + @param[in] Psm Bluetooth PSM. See Bluetooth specification for detail. + @param[in] Mtu Bluetooth MTU. See Bluetooth specification for detail. + @param[in] Callback The callback function. This function is called whenever there is message received + in this channel. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The Bluetooth L2CAP layer connection is created successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - Handle is NULL. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP connection. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_CONNECT)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + OUT EFI_HANDLE *Handle, + IN UINT16 Psm, + IN UINT16 Mtu, + IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback, + IN VOID *Context + ); + +/** + Do L2CAP disconnection. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[in] Handel A handle to indicate this L2CAP connection. + + @retval EFI_SUCCESS The Bluetooth L2CAP layer is disconnected successfully. + @retval EFI_NOT_FOUND Handle is invalid or not found. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to do Bluetooth L2CAP disconnection. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_DISCONNECT)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + IN EFI_HANDLE Handle + ); + +/** + Register L2CAP callback function for special channel. + + @param[in] This Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance. + @param[out] Handel A handle to indicate this L2CAP connection. + @param[in] Psm Bluetooth PSM. See Bluetooth specification for detail. + @param[in] Mtu Bluetooth MTU. See Bluetooth specification for detail. + @param[in] Callback The callback function. This function is called whenever there is message received + in this channel. NULL means unregister. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The Bluetooth L2CAP callback function is registered successfully. + @retval EFI_ALREADY_STARTED The callback function already exists when register. + @retval EFI_NOT_FOUND The callback function does not exist when unregister. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE)( + IN EFI_BLUETOOTH_IO_PROTOCOL *This, + OUT EFI_HANDLE *Handle, + IN UINT16 Psm, + IN UINT16 Mtu, + IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback, + IN VOID *Context + ); + +/// +/// This protocol provides service for Bluetooth L2CAP (Logical Link Control and Adaptation Protocol) +/// and SDP (Service Discovery Protocol). +/// +struct _EFI_BLUETOOTH_IO_PROTOCOL { + EFI_BLUETOOTH_IO_GET_DEVICE_INFO GetDeviceInfo; + EFI_BLUETOOTH_IO_GET_SDP_INFO GetSdpInfo; + EFI_BLUETOOTH_IO_L2CAP_RAW_SEND L2CapRawSend; + EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE L2CapRawReceive; + EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE L2CapRawAsyncReceive; + EFI_BLUETOOTH_IO_L2CAP_SEND L2CapSend; + EFI_BLUETOOTH_IO_L2CAP_RECEIVE L2CapReceive; + EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE L2CapAsyncReceive; + EFI_BLUETOOTH_IO_L2CAP_CONNECT L2CapConnect; + EFI_BLUETOOTH_IO_L2CAP_DISCONNECT L2CapDisconnect; + EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE L2CapRegisterService; +}; + +extern EFI_GUID gEfiBluetoothIoServiceBindingProtocolGuid; +extern EFI_GUID gEfiBluetoothIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothLeConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothLeConfig.h new file mode 100644 index 0000000000..eb92015d9c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BluetoothLeConfig.h @@ -0,0 +1,630 @@ +/** @file + EFI Bluetooth LE Config Protocol as defined in UEFI 2.7. + This protocol abstracts user interface configuration for BluetoothLe device. + + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __EFI_BLUETOOTH_LE_CONFIG_H__ +#define __EFI_BLUETOOTH_LE_CONFIG_H__ + +#include +#include + +#define EFI_BLUETOOTH_LE_CONFIG_PROTOCOL_GUID \ + { \ + 0x8f76da58, 0x1f99, 0x4275, { 0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 } \ + } + +typedef struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL EFI_BLUETOOTH_LE_CONFIG_PROTOCOL; + +/** + Initialize BluetoothLE host controller and local device. + + The Init() function initializes BluetoothLE host controller and local device. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + + @retval EFI_SUCCESS The BluetoothLE host controller and local device is initialized successfully. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to initialize the BluetoothLE host controller + and local device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_INIT)( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This + ); + +typedef struct { + /// + /// The version of the structure. A value of zero represents the EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER + /// structure as defined here. Future version of this specification may extend this data structure in a + /// backward compatible way and increase the value of Version. + /// + UINT32 Version; + /// + /// Passive scanning or active scanning. See Bluetooth specification. + /// + UINT8 ScanType; + /// + /// Recommended scan interval to be used while performing scan. + /// + UINT16 ScanInterval; + /// + /// Recommended scan window to be used while performing a scan. + /// + UINT16 ScanWindow; + /// + /// Recommended scanning filter policy to be used while performing a scan. + /// + UINT8 ScanningFilterPolicy; + /// + /// This is one byte flag to serve as a filter to remove unneeded scan + /// result. For example, set BIT0 means scan in LE Limited Discoverable + /// Mode. Set BIT1 means scan in LE General Discoverable Mode. + /// + UINT8 AdvertisementFlagFilter; +} EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER; + +typedef struct{ + BLUETOOTH_LE_ADDRESS BDAddr; + BLUETOOTH_LE_ADDRESS DirectAddress; + UINT8 RemoteDeviceState; + INT8 RSSI; + UINTN AdvertisementDataSize; + VOID *AdvertisementData; +} EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION; + +/** + Callback function, it is called if a BluetoothLE device is found during scan process. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Context Context passed from scan request. + @param[in] CallbackInfo Data related to scan result. NULL CallbackInfo means scan complete. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION *CallbackInfo + ); + +/** + Scan BluetoothLE device. + + The Scan() function scans BluetoothLE device. When this function is returned, it just means scan + request is submitted. It does not mean scan process is started or finished. Whenever there is a + BluetoothLE device is found, the Callback function will be called. Callback function might be + called before this function returns or after this function returns + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] ReScan If TRUE, a new scan request is submitted no matter there is scan result before. + If FALSE and there is scan result, the previous scan result is returned and no scan request + is submitted. + @param[in] Timeout Duration in milliseconds for which to scan. + @param[in] ScanParameter If it is not NULL, the ScanParameter is used to perform a scan by the BluetoothLE bus driver. + If it is NULL, the default parameter is used. + @param[in] Callback The callback function. This function is called if a BluetoothLE device is found during + scan process. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The Bluetooth scan request is submitted. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to scan the BluetoothLE device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN)( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN BOOLEAN ReScan, + IN UINT32 Timeout, + IN EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER *ScanParameter, OPTIONAL + IN EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION Callback, + IN VOID *Context + ); + +typedef struct { + /// + /// The version of the structure. A value of zero represents the + /// EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER + /// structure as defined here. Future version of this specification may + /// extend this data structure in a backward compatible way and + /// increase the value of Version. + /// + UINT32 Version; + /// + /// Recommended scan interval to be used while performing scan before connect. + /// + UINT16 ScanInterval; + /// + /// Recommended scan window to be used while performing a connection + /// + UINT16 ScanWindow; + /// + /// Minimum allowed connection interval. Shall be less than or equal to ConnIntervalMax. + /// + UINT16 ConnIntervalMin; + /// + /// Maximum allowed connection interval. Shall be greater than or equal to ConnIntervalMin. + /// + UINT16 ConnIntervalMax; + /// + /// Slave latency for the connection in number of connection events. + /// + UINT16 ConnLatency; + /// + /// Link supervision timeout for the connection. + /// + UINT16 SupervisionTimeout; +} EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER; + +/** + Connect a BluetoothLE device. + + The Connect() function connects a Bluetooth device. When this function is returned successfully, + a new EFI_BLUETOOTH_IO_PROTOCOL is created. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] AutoReconnect If TRUE, the BluetoothLE host controller needs to do an auto + reconnect. If FALSE, the BluetoothLE host controller does not do + an auto reconnect. + @param[in] DoBonding If TRUE, the BluetoothLE host controller needs to do a bonding. + If FALSE, the BluetoothLE host controller does not do a bonding. + @param[in] ConnectParameter If it is not NULL, the ConnectParameter is used to perform a + scan by the BluetoothLE bus driver. If it is NULL, the default + parameter is used. + @param[in] BD_ADDR The address of the BluetoothLE device to be connected. + + @retval EFI_SUCCESS The BluetoothLE device is connected successfully. + @retval EFI_ALREADY_STARTED The BluetoothLE device is already connected. + @retval EFI_NOT_FOUND The BluetoothLE device is not found. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to connect the BluetoothLE device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT)( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN BOOLEAN AutoReconnect, + IN BOOLEAN DoBonding, + IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER *ConnectParameter, OPTIONAL + IN BLUETOOTH_LE_ADDRESS *BD_ADDR + ); + +/** + Disconnect a BluetoothLE device. + + The Disconnect() function disconnects a BluetoothLE device. When this function is returned + successfully, the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL associated with this device is + destroyed and all services associated are stopped. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] BD_ADDR The address of BluetoothLE device to be connected. + @param[in] Reason Bluetooth disconnect reason. See Bluetooth specification for detail. + + @retval EFI_SUCCESS The BluetoothLE device is disconnected successfully. + @retval EFI_NOT_STARTED The BluetoothLE device is not connected. + @retval EFI_NOT_FOUND The BluetoothLE device is not found. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to disconnect the BluetoothLE device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_DISCONNECT)( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN BLUETOOTH_LE_ADDRESS *BD_ADDR, + IN UINT8 Reason + ); + +/** + Get BluetoothLE configuration data. + + The GetData() function returns BluetoothLE configuration data. For remote BluetoothLE device + configuration data, please use GetRemoteData() function with valid BD_ADDR. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] DataType Configuration data type. + @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified by Data. + On output, indicates the amount of data actually returned. + @param[in, out] Data A pointer to the buffer of data that will be returned. + + @retval EFI_SUCCESS The BluetoothLE configuration data is returned successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is NULL. + - *DataSize is 0. + - Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The DataType is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN OUT UINTN *DataSize, + IN OUT VOID *Data OPTIONAL + ); + +/** + Set BluetoothLE configuration data. + + The SetData() function sets local BluetoothLE device configuration data. Not all DataType can be + set. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] DataType Configuration data type. + @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data. + @param[in] Data A pointer to the buffer of data that will be set. + + @retval EFI_SUCCESS The BluetoothLE configuration data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is 0. + - Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_WRITE_PROTECTED Cannot set configuration data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Get remove BluetoothLE device configuration data. + + The GetRemoteData() function returns remote BluetoothLE device configuration data. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] DataType Configuration data type. + @param[in] BDAddr Remote BluetoothLE device address. + @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified by Data. + On output, indicates the amount of data actually returned. + @param[in, out] Data A pointer to the buffer of data that will be returned. + + @retval EFI_SUCCESS The remote BluetoothLE device configuration data is returned successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - DataSize is NULL. + - *DataSize is 0. + - Data is NULL. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The DataType is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN OUT UINTN *DataSize, + IN OUT VOID *Data + ); + +typedef enum { + /// + /// It indicates an authorization request. No data is associated with the callback + /// input. In the output data, the application should return the authorization value. + /// The data structure is BOOLEAN. TRUE means YES. FALSE means NO. + /// + EfiBluetoothSmpAuthorizationRequestEvent, + /// + /// It indicates that a passkey has been generated locally by the driver, and the same + /// passkey should be entered at the remote device. The callback input data is the + /// passkey of type UINT32, to be displayed by the application. No output data + /// should be returned. + /// + EfiBluetoothSmpPasskeyReadyEvent, + /// + /// It indicates that the driver is requesting for the passkey has been generated at + /// the remote device. No data is associated with the callback input. The output data + /// is the passkey of type UINT32, to be entered by the user. + /// + EfiBluetoothSmpPasskeyRequestEvent, + /// + /// It indicates that the driver is requesting for the passkey that has been pre-shared + /// out-of-band with the remote device. No data is associated with the callback + /// input. The output data is the stored OOB data of type UINT8[16]. + /// + EfiBluetoothSmpOOBDataRequestEvent, + /// + /// In indicates that a number have been generated locally by the bus driver, and + /// also at the remote device, and the bus driver wants to know if the two numbers + /// match. The callback input data is the number of type UINT32. The output data + /// is confirmation value of type BOOLEAN. TRUE means comparison pass. FALSE + /// means comparison fail. + /// + EfiBluetoothSmpNumericComparisonEvent, +} EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE; + +/** + The callback function for SMP. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Context Data passed into callback function. This is optional parameter + and may be NULL. + @param[in] BDAddr Remote BluetoothLE device address. + @param[in] EventDataType Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE. + @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data. + @param[in] Data A pointer to the buffer of data. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Register Security Manager Protocol callback function for user authentication/authorization. + + The RegisterSmpAuthCallback() function register Security Manager Protocol callback + function for user authentication/authorization. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Callback Callback function for user authentication/authorization. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The SMP callback function is registered successfully. + @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute + opcode and attribute handle, when the Callback is not NULL. + @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode + and attribute handle, when the Callback is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_LE_SMP_CALLBACK Callback, + IN VOID *Context + ); + +/** + Send user authentication/authorization to remote device. + + The SendSmpAuthData() function sends user authentication/authorization to remote device. It + should be used to send these information after the caller gets the request data from the callback + function by RegisterSmpAuthCallback(). + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] BDAddr Remote BluetoothLE device address. + @param[in] EventDataType Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE. + @param[in] DataSize The size of Data in bytes, of the data buffer specified by Data. + @param[in] Data A pointer to the buffer of data that will be sent. The data format + depends on the type of SMP event data being responded to. + + @retval EFI_SUCCESS The SMP authorization data is sent successfully. + @retval EFI_NOT_READY SMP is not in the correct state to receive the auth data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType, + IN UINTN DataSize, + IN VOID *Data + ); + +typedef enum { + // For local device only + EfiBluetoothSmpLocalIR, /* If Key hierarchy is supported */ + EfiBluetoothSmpLocalER, /* If Key hierarchy is supported */ + EfiBluetoothSmpLocalDHK, /* If Key hierarchy is supported. OPTIONAL */ + // For peer specific + EfiBluetoothSmpKeysDistributed = 0x1000, + EfiBluetoothSmpKeySize, + EfiBluetoothSmpKeyType, + EfiBluetoothSmpPeerLTK, + EfiBluetoothSmpPeerIRK, + EfiBluetoothSmpPeerCSRK, + EfiBluetoothSmpPeerRand, + EfiBluetoothSmpPeerEDIV, + EfiBluetoothSmpPeerSignCounter, + EfiBluetoothSmpLocalLTK, /* If Key hierarchy not supported */ + EfiBluetoothSmpLocalIRK, /* If Key hierarchy not supported */ + EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not supported */ + EfiBluetoothSmpLocalSignCounter, + EfiBluetoothSmpLocalDIV, + EfiBluetoothSmpPeerAddressList, + EfiBluetoothSmpMax, +} EFI_BLUETOOTH_LE_SMP_DATA_TYPE; + +/** + The callback function to get SMP data. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Context Data passed into callback function. This is optional parameter + and may be NULL. + @param[in] BDAddr Remote BluetoothLE device address. For Local device setting, it + should be NULL. + @param[in] DataType Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE. + @param[in, out] DataSize On input, indicates the size, in bytes, of the data buffer specified + by Data. On output, indicates the amount of data actually returned. + @param[out] Data A pointer to the buffer of data that will be returned. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE DataType, + IN OUT UINTN *DataSize, + OUT VOID *Data + ); + +/** + Register a callback function to get SMP related data. + + The RegisterSmpGetDataCallback() function registers a callback function to get SMP related data. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Callback Callback function for SMP get data. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The SMP get data callback function is registered successfully. + @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute + opcode and attribute handle, when the Callback is not NULL. + @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode + and attribute handle, when the Callback is NULL +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK Callback, + IN VOID *Context + ); + +/** + The callback function to set SMP data. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Context Data passed into callback function. This is optional parameter + and may be NULL. + @param[in] BDAddr Remote BluetoothLE device address. + @param[in] DataType Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE. + @param[in] DataSize Indicates the size, in bytes, of the data buffer specified by Data. + @param[in] Data A pointer to the buffer of data. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE Type, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Register a callback function to set SMP related data. + + The RegisterSmpSetDataCallback() function registers a callback function to set SMP related data. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Callback Callback function for SMP set data. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The SMP set data callback function is registered successfully. + @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute + opcode and attribute handle, when the Callback is not NULL. + @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode + and attribute handle, when the Callback is NULL +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK Callback, + IN VOID *Context + ); + +/** + The callback function to hook connect complete event. + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Context Data passed into callback function. This is optional parameter + and may be NULL. + @param[in] CallbackType The value defined in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE. + @param[in] BDAddr Remote BluetoothLE device address. + @param[in] InputBuffer A pointer to the buffer of data that is input from callback caller. + @param[in] InputBufferSize Indicates the size, in bytes, of the data buffer specified by InputBuffer. + + @retval EFI_SUCCESS The callback function complete successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN VOID *Context, + IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType, + IN BLUETOOTH_LE_ADDRESS *BDAddr, + IN VOID *InputBuffer, + IN UINTN InputBufferSize + ); + +/** + Register link connect complete callback function. + + The RegisterLinkConnectCompleteCallback() function registers Bluetooth link connect + complete callback function. The Bluetooth Configuration driver may call + RegisterLinkConnectCompleteCallback() to register a callback function. During pairing, + Bluetooth bus driver must trigger this callback function to report device state, if it is registered. + Then Bluetooth Configuration driver will get information on device connection, according to + CallbackType defined by EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE + + @param[in] This Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance. + @param[in] Callback The callback function. NULL means unregister. + @param[in] Context Data passed into Callback function. This is optional parameter and may be NULL. + + @retval EFI_SUCCESS The link connect complete callback function is registered successfully. + @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute + opcode and attribute handle, when the Callback is not NULL. + @retval EFI_NOT_STARTED A callback function is not registered on the same attribute opcode + and attribute handle, when the Callback is NULL +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK) ( + IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This, + IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK Callback, + IN VOID *Context + ); + +/// +/// This protocol abstracts user interface configuration for BluetoothLe device. +/// +struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL { + EFI_BLUETOOTH_LE_CONFIG_INIT Init; + EFI_BLUETOOTH_LE_CONFIG_SCAN Scan; + EFI_BLUETOOTH_LE_CONFIG_CONNECT Connect; + EFI_BLUETOOTH_LE_CONFIG_DISCONNECT Disconnect; + EFI_BLUETOOTH_LE_CONFIG_GET_DATA GetData; + EFI_BLUETOOTH_LE_CONFIG_SET_DATA SetData; + EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA GetRemoteData; + EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK RegisterSmpAuthCallback; + EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA SendSmpAuthData; + EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK RegisterSmpGetDataCallback; + EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK RegisterSmpSetDataCallback; + EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback; +}; + +extern EFI_GUID gEfiBluetoothLeConfigProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BootManagerPolicy.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BootManagerPolicy.h new file mode 100644 index 0000000000..42e90fdede --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BootManagerPolicy.h @@ -0,0 +1,132 @@ +/** @file + Boot Manager Policy Protocol as defined in UEFI Specification. + + This protocol is used by EFI Applications to request the UEFI Boot Manager + to connect devices using platform policy. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __BOOT_MANAGER_POLICY_H__ +#define __BOOT_MANAGER_POLICY_H__ + +#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_GUID \ + { \ + 0xFEDF8E0C, 0xE147, 0x11E3, { 0x99, 0x03, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \ + } + +#define EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID \ + { \ + 0xCAB0E94C, 0xE15F, 0x11E3, { 0x91, 0x8D, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \ + } + +#define EFI_BOOT_MANAGER_POLICY_NETWORK_GUID \ + { \ + 0xD04159DC, 0xE15F, 0x11E3, { 0xB2, 0x61, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \ + } + +#define EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID \ + { \ + 0x113B2126, 0xFC8A, 0x11E3, { 0xBD, 0x6C, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \ + } + +typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCOL; + +#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000 + +/** + Connect a device path following the platforms EFI Boot Manager policy. + + The ConnectDevicePath() function allows the caller to connect a DevicePath using the + same policy as the EFI Boot Manger. + + @param[in] This A pointer to the EFI_BOOT_MANAGER_POLICY_PROTOCOL instance. + @param[in] DevicePath Points to the start of the EFI device path to connect. + If DevicePath is NULL then all the controllers in the + system will be connected using the platforms EFI Boot + Manager policy. + @param[in] Recursive If TRUE, then ConnectController() is called recursively + until the entire tree of controllers below the + controller specified by DevicePath have been created. + If FALSE, then the tree of controllers is only expanded + one level. If DevicePath is NULL then Recursive is ignored. + + @retval EFI_SUCCESS The DevicePath was connected. + @retval EFI_NOT_FOUND The DevicePath was not found. + @retval EFI_NOT_FOUND No driver was connected to DevicePath. + @retval EFI_SECURITY_VIOLATION The user has no permission to start UEFI device + drivers on the DevicePath. + @retval EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH)( + IN EFI_BOOT_MANAGER_POLICY_PROTOCOL *This, + IN EFI_DEVICE_PATH *DevicePath, + IN BOOLEAN Recursive + ); + +/** + Connect a class of devices using the platform Boot Manager policy. + + The ConnectDeviceClass() function allows the caller to request that the Boot + Manager connect a class of devices. + + If Class is EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID then the Boot Manager will + use platform policy to connect consoles. Some platforms may restrict the + number of consoles connected as they attempt to fast boot, and calling + ConnectDeviceClass() with a Class value of EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID + must connect the set of consoles that follow the Boot Manager platform policy, + and the EFI_SIMPLE_TEXT_INPUT_PROTOCOL, EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL, and + the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL are produced on the connected handles. + The Boot Manager may restrict which consoles get connect due to platform policy, + for example a security policy may require that a given console is not connected. + + If Class is EFI_BOOT_MANAGER_POLICY_NETWORK_GUID then the Boot Manager will + connect the protocols the platforms supports for UEFI general purpose network + applications on one or more handles. If more than one network controller is + available a platform will connect, one, many, or all of the networks based + on platform policy. Connecting UEFI networking protocols, like EFI_DHCP4_PROTOCOL, + does not establish connections on the network. The UEFI general purpose network + application that called ConnectDeviceClass() may need to use the published + protocols to establish the network connection. The Boot Manager can optionally + have a policy to establish a network connection. + + If Class is EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID then the Boot Manager + will connect all UEFI drivers using the UEFI Boot Service + EFI_BOOT_SERVICES.ConnectController(). If the Boot Manager has policy + associated with connect all UEFI drivers this policy will be used. + + A platform can also define platform specific Class values as a properly generated + EFI_GUID would never conflict with this specification. + + @param[in] This A pointer to the EFI_BOOT_MANAGER_POLICY_PROTOCOL instance. + @param[in] Class A pointer to an EFI_GUID that represents a class of devices + that will be connected using the Boot Mangers platform policy. + + @retval EFI_SUCCESS At least one devices of the Class was connected. + @retval EFI_DEVICE_ERROR Devices were not connected due to an error. + @retval EFI_NOT_FOUND The Class is not supported by the platform. + @retval EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS)( + IN EFI_BOOT_MANAGER_POLICY_PROTOCOL *This, + IN EFI_GUID *Class + ); + +struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL { + UINT64 Revision; + EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH ConnectDevicePath; + EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS ConnectDeviceClass; +}; + +extern EFI_GUID gEfiBootManagerPolicyProtocolGuid; + +extern EFI_GUID gEfiBootManagerPolicyConsoleGuid; +extern EFI_GUID gEfiBootManagerPolicyNetworkGuid; +extern EFI_GUID gEfiBootManagerPolicyConnectAllGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BusSpecificDriverOverride.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BusSpecificDriverOverride.h new file mode 100644 index 0000000000..878458e9c8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/BusSpecificDriverOverride.h @@ -0,0 +1,66 @@ +/** @file + Bus Specific Driver Override protocol as defined in the UEFI 2.0 specification. + + Bus drivers that have a bus specific algorithm for matching drivers to controllers are + required to produce this protocol for each controller. For example, a PCI Bus Driver will produce an + instance of this protocol for every PCI controller that has a PCI option ROM that contains one or + more UEFI drivers. The protocol instance is attached to the handle of the PCI controller. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_H_ +#define _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_H_ + +/// +/// Global ID for the Bus Specific Driver Override Protocol +/// +#define EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL_GUID \ + { \ + 0x3bc1b285, 0x8a15, 0x4a82, {0xaa, 0xbf, 0x4d, 0x7d, 0x13, 0xfb, 0x32, 0x65 } \ + } + +typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL; + +// +// Prototypes for the Bus Specific Driver Override Protocol +// + +/** + Uses a bus specific algorithm to retrieve a driver image handle for a controller. + + @param This A pointer to the EFI_BUS_SPECIFIC_DRIVER_ + OVERRIDE_PROTOCOL instance. + @param DriverImageHandle On input, a pointer to the previous driver image handle returned + by GetDriver(). On output, a pointer to the next driver + image handle. Passing in a NULL, will return the first driver + image handle. + + @retval EFI_SUCCESS A bus specific override driver is returned in DriverImageHandle. + @retval EFI_NOT_FOUND The end of the list of override drivers was reached. + A bus specific override driver is not returned in DriverImageHandle. + @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a + previous call to GetDriver(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER)( + IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This, + IN OUT EFI_HANDLE *DriverImageHandle + ); + +/// +/// This protocol matches one or more drivers to a controller. This protocol is produced by a bus driver, +/// and it is installed on the child handles of buses that require a bus specific algorithm for matching +/// drivers to controllers. +/// +struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL { + EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER GetDriver; +}; + +extern EFI_GUID gEfiBusSpecificDriverOverrideProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Capsule.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Capsule.h new file mode 100644 index 0000000000..0122b6ebcd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Capsule.h @@ -0,0 +1,29 @@ +/** @file + Capsule Architectural Protocol as defined in PI1.0a Specification VOLUME 2 DXE + + The DXE Driver that produces this protocol must be a runtime driver. + The driver is responsible for initializing the CapsuleUpdate() and + QueryCapsuleCapabilities() fields of the UEFI Runtime Services Table. + After the two fields of the UEFI Runtime Services Table have been initialized, + the driver must install the EFI_CAPSULE_ARCH_PROTOCOL_GUID on a new handle + with a NULL interface pointer. The installation of this protocol informs + the DXE Foundation that the Capsule related services are now available and + that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services Table. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_CAPSULE_ARCH_H__ +#define __ARCH_PROTOCOL_CAPSULE_ARCH_H__ + +// +// Global ID for the Capsule Architectural Protocol +// +#define EFI_CAPSULE_ARCH_PROTOCOL_GUID \ + { 0x5053697e, 0x2cbc, 0x4819, {0x90, 0xd9, 0x05, 0x80, 0xde, 0xee, 0x57, 0x54 }} + +extern EFI_GUID gEfiCapsuleArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName.h new file mode 100644 index 0000000000..91344fc576 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName.h @@ -0,0 +1,123 @@ +/** @file + EFI Component Name Protocol as defined in the EFI 1.1 specification. + This protocol is used to retrieve user readable names of EFI Drivers + and controllers managed by EFI Drivers. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_COMPONENT_NAME_H__ +#define __EFI_COMPONENT_NAME_H__ + +/// +/// The global ID for the Component Name Protocol. +/// +#define EFI_COMPONENT_NAME_PROTOCOL_GUID \ + { \ + 0x107a772c, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_COMPONENT_NAME_PROTOCOL EFI_COMPONENT_NAME_PROTOCOL; + + +/** + Retrieves a Unicode string that is the user-readable name of the EFI Driver. + + @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance. + @param Language A pointer to a three-character ISO 639-2 language identifier. + This is the language of the driver name that that the caller + is requesting, and it must match one of the languages specified + in SupportedLanguages. The number of languages supported by a + driver is up to the driver writer. + @param DriverName A pointer to the Unicode string to return. This Unicode string + is the name of the driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by This + and the language specified by Language was returned + in DriverName. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER DriverName is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_COMPONENT_NAME_GET_DRIVER_NAME)( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by an EFI Driver. + + @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance. + @param ControllerHandle The handle of a controller that the driver specified by + This is managing. This handle specifies the controller + whose name is to be returned. + @param ChildHandle The handle of the child controller to retrieve the name + of. This is an optional parameter that may be NULL. It + will be NULL for device drivers. It will also be NULL + for a bus drivers that wish to retrieve the name of the + bus controller. It will not be NULL for a bus driver + that wishes to retrieve the name of a child controller. + @param Language A pointer to a three character ISO 639-2 language + identifier. This is the language of the controller name + that the caller is requesting, and it must match one + of the languages specified in SupportedLanguages. The + number of languages supported by a driver is up to the + driver writer. + @param ControllerName A pointer to the Unicode string to return. This Unicode + string is the name of the controller specified by + ControllerHandle and ChildHandle in the language specified + by Language, from the point of view of the driver specified + by This. + + @retval EFI_SUCCESS The Unicode string for the user-readable name in the + language specified by Language for the driver + specified by This was returned in DriverName. + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + @retval EFI_UNSUPPORTED The driver specified by This is not currently managing + the controller specified by ControllerHandle and + ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_COMPONENT_NAME_GET_CONTROLLER_NAME)( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/// +/// This protocol is used to retrieve user readable names of drivers +/// and controllers managed by UEFI Drivers. +/// +struct _EFI_COMPONENT_NAME_PROTOCOL { + EFI_COMPONENT_NAME_GET_DRIVER_NAME GetDriverName; + EFI_COMPONENT_NAME_GET_CONTROLLER_NAME GetControllerName; + /// + /// A Null-terminated ASCII string that contains one or more + /// ISO 639-2 language codes. This is the list of language codes + /// that this protocol supports. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiComponentNameProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName2.h new file mode 100644 index 0000000000..3d20150170 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ComponentName2.h @@ -0,0 +1,166 @@ +/** @file + UEFI Component Name 2 Protocol as defined in the UEFI 2.1 specification. + This protocol is used to retrieve user readable names of drivers + and controllers managed by UEFI Drivers. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_COMPONENT_NAME2_H__ +#define __EFI_COMPONENT_NAME2_H__ + +/// +/// Global ID for the Component Name Protocol +/// +#define EFI_COMPONENT_NAME2_PROTOCOL_GUID \ + {0x6a7a5cff, 0xe8d9, 0x4f70, { 0xba, 0xda, 0x75, 0xab, 0x30, 0x25, 0xce, 0x14 } } + +typedef struct _EFI_COMPONENT_NAME2_PROTOCOL EFI_COMPONENT_NAME2_PROTOCOL; + + +/** + Retrieves a string that is the user readable name of + the EFI Driver. + + @param This A pointer to the + EFI_COMPONENT_NAME2_PROTOCOL instance. + + @param Language A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller + is requesting, and it must match one of the + languages specified in SupportedLanguages. + The number of languages supported by a + driver is up to the driver writer. Language + is specified in RFC 4646 language code + format. + + @param DriverName A pointer to the string to return. + This string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The string for the + Driver specified by This and the + language specified by Language + was returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This + does not support the language + specified by Language. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_COMPONENT_NAME2_GET_DRIVER_NAME)( + IN EFI_COMPONENT_NAME2_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + + +/** + Retrieves a string that is the user readable name of + the controller that is being managed by an EFI Driver. + + @param This A pointer to the + EFI_COMPONENT_NAME2_PROTOCOL instance. + + @param ControllerHandle The handle of a controller that the + driver specified by This is managing. + This handle specifies the controller + whose name is to be returned. + + @param ChildHandle The handle of the child controller to + retrieve the name of. This is an + optional parameter that may be NULL. + It will be NULL for device drivers. + It will also be NULL for bus + drivers that wish to retrieve the + name of the bus controller. It will + not be NULL for a bus driver that + wishes to retrieve the name of a + child controller. + + @param Language A pointer to a Null-terminated ASCII + string array indicating the language. + This is the language of the driver + name that the caller is requesting, + and it must match one of the + languages specified in + SupportedLanguages. The number of + languages supported by a driver is up + to the driver writer. Language is + specified in RFC 4646 language code + format. + + @param ControllerName A pointer to the string to return. + This string is the name of the controller + specified by ControllerHandle and ChildHandle + in the language specified by Language + from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The string for the user + readable name in the language + specified by Language for the + driver specified by This was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it + is not a valid EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is + not currently managing the + controller specified by + ControllerHandle and + ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This + does not support the language + specified by Language. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)( + IN EFI_COMPONENT_NAME2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/// +/// This protocol is used to retrieve user readable names of drivers +/// and controllers managed by UEFI Drivers. +/// +struct _EFI_COMPONENT_NAME2_PROTOCOL { + EFI_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; + EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; + + /// + /// A Null-terminated ASCII string array that contains one or more + /// supported language codes. This is the list of language codes that + /// this protocol supports. The number of languages supported by a + /// driver is up to the driver writer. SupportedLanguages is + /// specified in RFC 4646 format. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiComponentName2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Cpu.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Cpu.h new file mode 100644 index 0000000000..72e0612523 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Cpu.h @@ -0,0 +1,294 @@ +/** @file + CPU Architectural Protocol as defined in PI spec Volume 2 DXE + + This code abstracts the DXE core from processor implementation details. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_CPU_H__ +#define __ARCH_PROTOCOL_CPU_H__ + +#include + +#define EFI_CPU_ARCH_PROTOCOL_GUID \ + { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } + +typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL; + +/// +/// The type of flush operation +/// +typedef enum { + EfiCpuFlushTypeWriteBackInvalidate, + EfiCpuFlushTypeWriteBack, + EfiCpuFlushTypeInvalidate, + EfiCpuMaxFlushType +} EFI_CPU_FLUSH_TYPE; + +/// +/// The type of processor INIT. +/// +typedef enum { + EfiCpuInit, + EfiCpuMaxInitType +} EFI_CPU_INIT_TYPE; + +/** + EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. + + @param InterruptType Defines the type of interrupt or exception that + occurred on the processor.This parameter is processor architecture specific. + @param SystemContext A pointer to the processor context when + the interrupt occurred on the processor. + + @return None + +**/ +typedef +VOID +(EFIAPI *EFI_CPU_INTERRUPT_HANDLER)( + IN CONST EFI_EXCEPTION_TYPE InterruptType, + IN CONST EFI_SYSTEM_CONTEXT SystemContext + ); + +/** + This function flushes the range of addresses from Start to Start+Length + from the processor's data cache. If Start is not aligned to a cache line + boundary, then the bytes before Start to the preceding cache line boundary + are also flushed. If Start+Length is not aligned to a cache line boundary, + then the bytes past Start+Length to the end of the next cache line boundary + are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be + supported. If the data cache is fully coherent with all DMA operations, then + this function can just return EFI_SUCCESS. If the processor does not support + flushing a range of the data cache, then the entire data cache can be flushed. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param Start The beginning physical address to flush from the processor's data + cache. + @param Length The number of bytes to flush from the processor's data cache. This + function may flush more bytes than Length specifies depending upon + the granularity of the flush operation that the processor supports. + @param FlushType Specifies the type of flush operation to perform. + + @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from + the processor's data cache. + @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified + by FlushType. + @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed + from the processor's data cache. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE)( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + + +/** + This function enables interrupt processing by the processor. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS Interrupts are enabled on the processor. + @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_ENABLE_INTERRUPT)( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + + +/** + This function disables interrupt processing by the processor. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS Interrupts are disabled on the processor. + @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_DISABLE_INTERRUPT)( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + + +/** + This function retrieves the processor's current interrupt state a returns it in + State. If interrupts are currently enabled, then TRUE is returned. If interrupts + are currently disabled, then FALSE is returned. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param State A pointer to the processor's current interrupt state. Set to TRUE if + interrupts are enabled and FALSE if interrupts are disabled. + + @retval EFI_SUCCESS The processor's current interrupt state was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE)( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + + +/** + This function generates an INIT on the processor. If this function succeeds, then the + processor will be reset, and control will not be returned to the caller. If InitType is + not supported by this processor, or the processor cannot programmatically generate an + INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error + occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param InitType The type of processor INIT to perform. + + @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen. + @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported + by this processor. + @retval EFI_DEVICE_ERROR The processor INIT failed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_INIT)( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + + +/** + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + The installed handler is called once for each processor interrupt or exception. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts + are enabled and FALSE if interrupts are disabled. + @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. If this parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER)( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + + +/** + This function reads the processor timer specified by TimerIndex and returns it in TimerValue. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter + must be between 0 and NumberOfTimers-1. + @param TimerValue Pointer to the returned timer value. + @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment + of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is + returned. This parameter is optional and may be NULL. + + @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue. + @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers. + @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid. + @retval EFI_UNSUPPORTED The processor does not have any readable timers. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_GET_TIMER_VALUE)( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + + +/** + This function modifies the attributes for the memory region specified by BaseAddress and + Length from their current attributes to the attributes specified by Attributes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memory region. + + @retval EFI_SUCCESS The attributes were set for the memory region. + @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combination of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory + resource range specified by BaseAddress and Length. + The bit mask of attributes is not support for the memory resource + range specified by BaseAddress and Length. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES)( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + + +/// +/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE +/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt +/// vectors and exception vectors, reading internal processor timers, resetting the processor, and +/// determining the processor frequency. +/// +struct _EFI_CPU_ARCH_PROTOCOL { + EFI_CPU_FLUSH_DATA_CACHE FlushDataCache; + EFI_CPU_ENABLE_INTERRUPT EnableInterrupt; + EFI_CPU_DISABLE_INTERRUPT DisableInterrupt; + EFI_CPU_GET_INTERRUPT_STATE GetInterruptState; + EFI_CPU_INIT Init; + EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler; + EFI_CPU_GET_TIMER_VALUE GetTimerValue; + EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes; + /// + /// The number of timers that are available in a processor. The value in this + /// field is a constant that must not be modified after the CPU Architectural + /// Protocol is installed. All consumers must treat this as a read-only field. + /// + UINT32 NumberOfTimers; + /// + /// The size, in bytes, of the alignment required for DMA buffer allocations. + /// This is typically the size of the largest data cache line in the platform. + /// The value in this field is a constant that must not be modified after the + /// CPU Architectural Protocol is installed. All consumers must treat this as + /// a read-only field. + /// + UINT32 DmaBufferAlignment; +}; + +extern EFI_GUID gEfiCpuArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/CpuIo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/CpuIo2.h new file mode 100644 index 0000000000..173b00d5c3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/CpuIo2.h @@ -0,0 +1,136 @@ +/** @file + This files describes the CPU I/O 2 Protocol. + + This protocol provides an I/O abstraction for a system processor. This protocol + is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions. + The I/O or memory primitives can be used by the consumer of the protocol to materialize + bus-specific configuration cycles, such as the transitional configuration address and data + ports for PCI. Only drivers that require direct access to the entire system should use this + protocol. + + Note: This is a boot-services only protocol and it may not be used by runtime drivers after + ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime + protocol and can be used by runtime drivers after ExitBootServices(). + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef __CPU_IO2_H__ +#define __CPU_IO2_H__ + +#define EFI_CPU_IO2_PROTOCOL_GUID \ + { \ + 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \ + } + +typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL; + +/// +/// Enumeration that defines the width of the I/O operation. +/// +typedef enum { + EfiCpuIoWidthUint8, + EfiCpuIoWidthUint16, + EfiCpuIoWidthUint32, + EfiCpuIoWidthUint64, + EfiCpuIoWidthFifoUint8, + EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, + EfiCpuIoWidthFifoUint64, + EfiCpuIoWidthFillUint8, + EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, + EfiCpuIoWidthFillUint64, + EfiCpuIoWidthMaximum +} EFI_CPU_IO_PROTOCOL_WIDTH; + +/** + Enables a driver to access registers in the PI CPU I/O space. + + The Io.Read() and Io.Write() functions enable a driver to access PCI controller + registers in the PI CPU I/O space. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for + each of the Count operations that is performed. + + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times on the same Address. + + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is + incremented for each of the Count operations that is performed. The read or + write operation is performed Count times from the first element of Buffer. + + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number + of bytes moved is Width size * Count, starting at Address. + @param[in, out] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the PI system. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)( + IN EFI_CPU_IO2_PROTOCOL *This, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +/// +/// Service for read and write accesses. +/// +typedef struct { + /// + /// This service provides the various modalities of memory and I/O read. + /// + EFI_CPU_IO_PROTOCOL_IO_MEM Read; + /// + /// This service provides the various modalities of memory and I/O write. + /// + EFI_CPU_IO_PROTOCOL_IO_MEM Write; +} EFI_CPU_IO_PROTOCOL_ACCESS; + +/// +/// Provides the basic memory and I/O interfaces that are used to abstract +/// accesses to devices in a system. +/// +struct _EFI_CPU_IO2_PROTOCOL { + /// + /// Enables a driver to access memory-mapped registers in the EFI system memory space. + /// + EFI_CPU_IO_PROTOCOL_ACCESS Mem; + /// + /// Enables a driver to access registers in the EFI CPU I/O space. + /// + EFI_CPU_IO_PROTOCOL_ACCESS Io; +}; + +extern EFI_GUID gEfiCpuIo2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugPort.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugPort.h new file mode 100644 index 0000000000..d3aa3bbf2a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugPort.h @@ -0,0 +1,140 @@ +/** @file + + The file defines the EFI Debugport protocol. + This protocol is used by debug agent to communicate with the + remote debug host. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEBUG_PORT_H__ +#define __DEBUG_PORT_H__ + + +/// +/// DebugPortIo protocol {EBA4E8D2-3858-41EC-A281-2647BA9660D0} +/// +#define EFI_DEBUGPORT_PROTOCOL_GUID \ + { \ + 0xEBA4E8D2, 0x3858, 0x41EC, {0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 } \ + } + +extern EFI_GUID gEfiDebugPortProtocolGuid; + +typedef struct _EFI_DEBUGPORT_PROTOCOL EFI_DEBUGPORT_PROTOCOL; + +// +// DebugPort member functions +// + +/** + Resets the debugport. + + @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance. + + @retval EFI_SUCCESS The debugport device was reset and is in usable state. + @retval EFI_DEVICE_ERROR The debugport device could not be reset and is unusable. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEBUGPORT_RESET)( + IN EFI_DEBUGPORT_PROTOCOL *This + ); + +/** + Writes data to the debugport. + + @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance. + @param Timeout The number of microseconds to wait before timing out a write operation. + @param BufferSize On input, the requested number of bytes of data to write. On output, the + number of bytes of data actually written. + @param Buffer A pointer to a buffer containing the data to write. + + @retval EFI_SUCCESS The data was written. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEBUGPORT_WRITE)( + IN EFI_DEBUGPORT_PROTOCOL *This, + IN UINT32 Timeout, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Reads data from the debugport. + + @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance. + @param Timeout The number of microseconds to wait before timing out a read operation. + @param BufferSize On input, the requested number of bytes of data to read. On output, the + number of bytes of data actually number of bytes + of data read and returned in Buffer. + @param Buffer A pointer to a buffer into which the data read will be saved. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The operation was stopped due to a timeout or overrun. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEBUGPORT_READ)( + IN EFI_DEBUGPORT_PROTOCOL *This, + IN UINT32 Timeout, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Checks to see if any data is available to be read from the debugport device. + + @param This A pointer to the EFI_DEBUGPORT_PROTOCOL instance. + + @retval EFI_SUCCESS At least one byte of data is available to be read. + @retval EFI_DEVICE_ERROR The debugport device is not functioning correctly. + @retval EFI_NOT_READY No data is available to be read. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEBUGPORT_POLL)( + IN EFI_DEBUGPORT_PROTOCOL *This + ); + +/// +/// This protocol provides the communication link between the debug agent and the remote host. +/// +struct _EFI_DEBUGPORT_PROTOCOL { + EFI_DEBUGPORT_RESET Reset; + EFI_DEBUGPORT_WRITE Write; + EFI_DEBUGPORT_READ Read; + EFI_DEBUGPORT_POLL Poll; +}; + +// +// DEBUGPORT variable definitions... +// +#define EFI_DEBUGPORT_VARIABLE_NAME L"DEBUGPORT" +#define EFI_DEBUGPORT_VARIABLE_GUID EFI_DEBUGPORT_PROTOCOL_GUID + +extern EFI_GUID gEfiDebugPortVariableGuid; + +// +// DebugPort device path definitions... +// +#define DEVICE_PATH_MESSAGING_DEBUGPORT EFI_DEBUGPORT_PROTOCOL_GUID + +extern EFI_GUID gEfiDebugPortDevicePathGuid; + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + EFI_GUID Guid; +} DEBUGPORT_DEVICE_PATH; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugSupport.h new file mode 100644 index 0000000000..3ab78ee1ba --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DebugSupport.h @@ -0,0 +1,827 @@ +/** @file + DebugSupport protocol and supporting definitions as defined in the UEFI2.4 + specification. + + The DebugSupport protocol is used by source level debuggers to abstract the + processor and handle context save and restore operations. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEBUG_SUPPORT_H__ +#define __DEBUG_SUPPORT_H__ + +#include + +typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL; + +/// +/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}. +/// +#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \ + { \ + 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \ + } + +/// +/// Processor exception to be hooked. +/// All exception types for IA32, X64, Itanium and EBC processors are defined. +/// +typedef INTN EFI_EXCEPTION_TYPE; + +/// +/// IA-32 processor exception types. +/// +#define EXCEPT_IA32_DIVIDE_ERROR 0 +#define EXCEPT_IA32_DEBUG 1 +#define EXCEPT_IA32_NMI 2 +#define EXCEPT_IA32_BREAKPOINT 3 +#define EXCEPT_IA32_OVERFLOW 4 +#define EXCEPT_IA32_BOUND 5 +#define EXCEPT_IA32_INVALID_OPCODE 6 +#define EXCEPT_IA32_DOUBLE_FAULT 8 +#define EXCEPT_IA32_INVALID_TSS 10 +#define EXCEPT_IA32_SEG_NOT_PRESENT 11 +#define EXCEPT_IA32_STACK_FAULT 12 +#define EXCEPT_IA32_GP_FAULT 13 +#define EXCEPT_IA32_PAGE_FAULT 14 +#define EXCEPT_IA32_FP_ERROR 16 +#define EXCEPT_IA32_ALIGNMENT_CHECK 17 +#define EXCEPT_IA32_MACHINE_CHECK 18 +#define EXCEPT_IA32_SIMD 19 + +/// +/// FXSAVE_STATE. +/// FP / MMX / XMM registers (see fxrstor instruction definition). +/// +typedef struct { + UINT16 Fcw; + UINT16 Fsw; + UINT16 Ftw; + UINT16 Opcode; + UINT32 Eip; + UINT16 Cs; + UINT16 Reserved1; + UINT32 DataOffset; + UINT16 Ds; + UINT8 Reserved2[10]; + UINT8 St0Mm0[10], Reserved3[6]; + UINT8 St1Mm1[10], Reserved4[6]; + UINT8 St2Mm2[10], Reserved5[6]; + UINT8 St3Mm3[10], Reserved6[6]; + UINT8 St4Mm4[10], Reserved7[6]; + UINT8 St5Mm5[10], Reserved8[6]; + UINT8 St6Mm6[10], Reserved9[6]; + UINT8 St7Mm7[10], Reserved10[6]; + UINT8 Xmm0[16]; + UINT8 Xmm1[16]; + UINT8 Xmm2[16]; + UINT8 Xmm3[16]; + UINT8 Xmm4[16]; + UINT8 Xmm5[16]; + UINT8 Xmm6[16]; + UINT8 Xmm7[16]; + UINT8 Reserved11[14 * 16]; +} EFI_FX_SAVE_STATE_IA32; + +/// +/// IA-32 processor context definition. +/// +typedef struct { + UINT32 ExceptionData; + EFI_FX_SAVE_STATE_IA32 FxSaveState; + UINT32 Dr0; + UINT32 Dr1; + UINT32 Dr2; + UINT32 Dr3; + UINT32 Dr6; + UINT32 Dr7; + UINT32 Cr0; + UINT32 Cr1; /* Reserved */ + UINT32 Cr2; + UINT32 Cr3; + UINT32 Cr4; + UINT32 Eflags; + UINT32 Ldtr; + UINT32 Tr; + UINT32 Gdtr[2]; + UINT32 Idtr[2]; + UINT32 Eip; + UINT32 Gs; + UINT32 Fs; + UINT32 Es; + UINT32 Ds; + UINT32 Cs; + UINT32 Ss; + UINT32 Edi; + UINT32 Esi; + UINT32 Ebp; + UINT32 Esp; + UINT32 Ebx; + UINT32 Edx; + UINT32 Ecx; + UINT32 Eax; +} EFI_SYSTEM_CONTEXT_IA32; + +/// +/// x64 processor exception types. +/// +#define EXCEPT_X64_DIVIDE_ERROR 0 +#define EXCEPT_X64_DEBUG 1 +#define EXCEPT_X64_NMI 2 +#define EXCEPT_X64_BREAKPOINT 3 +#define EXCEPT_X64_OVERFLOW 4 +#define EXCEPT_X64_BOUND 5 +#define EXCEPT_X64_INVALID_OPCODE 6 +#define EXCEPT_X64_DOUBLE_FAULT 8 +#define EXCEPT_X64_INVALID_TSS 10 +#define EXCEPT_X64_SEG_NOT_PRESENT 11 +#define EXCEPT_X64_STACK_FAULT 12 +#define EXCEPT_X64_GP_FAULT 13 +#define EXCEPT_X64_PAGE_FAULT 14 +#define EXCEPT_X64_FP_ERROR 16 +#define EXCEPT_X64_ALIGNMENT_CHECK 17 +#define EXCEPT_X64_MACHINE_CHECK 18 +#define EXCEPT_X64_SIMD 19 + +/// +/// FXSAVE_STATE. +/// FP / MMX / XMM registers (see fxrstor instruction definition). +/// +typedef struct { + UINT16 Fcw; + UINT16 Fsw; + UINT16 Ftw; + UINT16 Opcode; + UINT64 Rip; + UINT64 DataOffset; + UINT8 Reserved1[8]; + UINT8 St0Mm0[10], Reserved2[6]; + UINT8 St1Mm1[10], Reserved3[6]; + UINT8 St2Mm2[10], Reserved4[6]; + UINT8 St3Mm3[10], Reserved5[6]; + UINT8 St4Mm4[10], Reserved6[6]; + UINT8 St5Mm5[10], Reserved7[6]; + UINT8 St6Mm6[10], Reserved8[6]; + UINT8 St7Mm7[10], Reserved9[6]; + UINT8 Xmm0[16]; + UINT8 Xmm1[16]; + UINT8 Xmm2[16]; + UINT8 Xmm3[16]; + UINT8 Xmm4[16]; + UINT8 Xmm5[16]; + UINT8 Xmm6[16]; + UINT8 Xmm7[16]; + // + // NOTE: UEFI 2.0 spec definition as follows. + // + UINT8 Reserved11[14 * 16]; +} EFI_FX_SAVE_STATE_X64; + +/// +/// x64 processor context definition. +/// +typedef struct { + UINT64 ExceptionData; + EFI_FX_SAVE_STATE_X64 FxSaveState; + UINT64 Dr0; + UINT64 Dr1; + UINT64 Dr2; + UINT64 Dr3; + UINT64 Dr6; + UINT64 Dr7; + UINT64 Cr0; + UINT64 Cr1; /* Reserved */ + UINT64 Cr2; + UINT64 Cr3; + UINT64 Cr4; + UINT64 Cr8; + UINT64 Rflags; + UINT64 Ldtr; + UINT64 Tr; + UINT64 Gdtr[2]; + UINT64 Idtr[2]; + UINT64 Rip; + UINT64 Gs; + UINT64 Fs; + UINT64 Es; + UINT64 Ds; + UINT64 Cs; + UINT64 Ss; + UINT64 Rdi; + UINT64 Rsi; + UINT64 Rbp; + UINT64 Rsp; + UINT64 Rbx; + UINT64 Rdx; + UINT64 Rcx; + UINT64 Rax; + UINT64 R8; + UINT64 R9; + UINT64 R10; + UINT64 R11; + UINT64 R12; + UINT64 R13; + UINT64 R14; + UINT64 R15; +} EFI_SYSTEM_CONTEXT_X64; + +/// +/// Itanium Processor Family Exception types. +/// +#define EXCEPT_IPF_VHTP_TRANSLATION 0 +#define EXCEPT_IPF_INSTRUCTION_TLB 1 +#define EXCEPT_IPF_DATA_TLB 2 +#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3 +#define EXCEPT_IPF_ALT_DATA_TLB 4 +#define EXCEPT_IPF_DATA_NESTED_TLB 5 +#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6 +#define EXCEPT_IPF_DATA_KEY_MISSED 7 +#define EXCEPT_IPF_DIRTY_BIT 8 +#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9 +#define EXCEPT_IPF_DATA_ACCESS_BIT 10 +#define EXCEPT_IPF_BREAKPOINT 11 +#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12 +// +// 13 - 19 reserved +// +#define EXCEPT_IPF_PAGE_NOT_PRESENT 20 +#define EXCEPT_IPF_KEY_PERMISSION 21 +#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22 +#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23 +#define EXCEPT_IPF_GENERAL_EXCEPTION 24 +#define EXCEPT_IPF_DISABLED_FP_REGISTER 25 +#define EXCEPT_IPF_NAT_CONSUMPTION 26 +#define EXCEPT_IPF_SPECULATION 27 +// +// 28 reserved +// +#define EXCEPT_IPF_DEBUG 29 +#define EXCEPT_IPF_UNALIGNED_REFERENCE 30 +#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31 +#define EXCEPT_IPF_FP_FAULT 32 +#define EXCEPT_IPF_FP_TRAP 33 +#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34 +#define EXCEPT_IPF_TAKEN_BRANCH 35 +#define EXCEPT_IPF_SINGLE_STEP 36 +// +// 37 - 44 reserved +// +#define EXCEPT_IPF_IA32_EXCEPTION 45 +#define EXCEPT_IPF_IA32_INTERCEPT 46 +#define EXCEPT_IPF_IA32_INTERRUPT 47 + +/// +/// IPF processor context definition. +/// +typedef struct { + // + // The first reserved field is necessary to preserve alignment for the correct + // bits in UNAT and to insure F2 is 16 byte aligned. + // + UINT64 Reserved; + UINT64 R1; + UINT64 R2; + UINT64 R3; + UINT64 R4; + UINT64 R5; + UINT64 R6; + UINT64 R7; + UINT64 R8; + UINT64 R9; + UINT64 R10; + UINT64 R11; + UINT64 R12; + UINT64 R13; + UINT64 R14; + UINT64 R15; + UINT64 R16; + UINT64 R17; + UINT64 R18; + UINT64 R19; + UINT64 R20; + UINT64 R21; + UINT64 R22; + UINT64 R23; + UINT64 R24; + UINT64 R25; + UINT64 R26; + UINT64 R27; + UINT64 R28; + UINT64 R29; + UINT64 R30; + UINT64 R31; + + UINT64 F2[2]; + UINT64 F3[2]; + UINT64 F4[2]; + UINT64 F5[2]; + UINT64 F6[2]; + UINT64 F7[2]; + UINT64 F8[2]; + UINT64 F9[2]; + UINT64 F10[2]; + UINT64 F11[2]; + UINT64 F12[2]; + UINT64 F13[2]; + UINT64 F14[2]; + UINT64 F15[2]; + UINT64 F16[2]; + UINT64 F17[2]; + UINT64 F18[2]; + UINT64 F19[2]; + UINT64 F20[2]; + UINT64 F21[2]; + UINT64 F22[2]; + UINT64 F23[2]; + UINT64 F24[2]; + UINT64 F25[2]; + UINT64 F26[2]; + UINT64 F27[2]; + UINT64 F28[2]; + UINT64 F29[2]; + UINT64 F30[2]; + UINT64 F31[2]; + + UINT64 Pr; + + UINT64 B0; + UINT64 B1; + UINT64 B2; + UINT64 B3; + UINT64 B4; + UINT64 B5; + UINT64 B6; + UINT64 B7; + + // + // application registers + // + UINT64 ArRsc; + UINT64 ArBsp; + UINT64 ArBspstore; + UINT64 ArRnat; + + UINT64 ArFcr; + + UINT64 ArEflag; + UINT64 ArCsd; + UINT64 ArSsd; + UINT64 ArCflg; + UINT64 ArFsr; + UINT64 ArFir; + UINT64 ArFdr; + + UINT64 ArCcv; + + UINT64 ArUnat; + + UINT64 ArFpsr; + + UINT64 ArPfs; + UINT64 ArLc; + UINT64 ArEc; + + // + // control registers + // + UINT64 CrDcr; + UINT64 CrItm; + UINT64 CrIva; + UINT64 CrPta; + UINT64 CrIpsr; + UINT64 CrIsr; + UINT64 CrIip; + UINT64 CrIfa; + UINT64 CrItir; + UINT64 CrIipa; + UINT64 CrIfs; + UINT64 CrIim; + UINT64 CrIha; + + // + // debug registers + // + UINT64 Dbr0; + UINT64 Dbr1; + UINT64 Dbr2; + UINT64 Dbr3; + UINT64 Dbr4; + UINT64 Dbr5; + UINT64 Dbr6; + UINT64 Dbr7; + + UINT64 Ibr0; + UINT64 Ibr1; + UINT64 Ibr2; + UINT64 Ibr3; + UINT64 Ibr4; + UINT64 Ibr5; + UINT64 Ibr6; + UINT64 Ibr7; + + // + // virtual registers - nat bits for R1-R31 + // + UINT64 IntNat; + +} EFI_SYSTEM_CONTEXT_IPF; + +/// +/// EBC processor exception types. +/// +#define EXCEPT_EBC_UNDEFINED 0 +#define EXCEPT_EBC_DIVIDE_ERROR 1 +#define EXCEPT_EBC_DEBUG 2 +#define EXCEPT_EBC_BREAKPOINT 3 +#define EXCEPT_EBC_OVERFLOW 4 +#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range. +#define EXCEPT_EBC_STACK_FAULT 6 +#define EXCEPT_EBC_ALIGNMENT_CHECK 7 +#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction. +#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK. +#define EXCEPT_EBC_STEP 10 ///< To support debug stepping. +/// +/// For coding convenience, define the maximum valid EBC exception. +/// +#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP + +/// +/// EBC processor context definition. +/// +typedef struct { + UINT64 R0; + UINT64 R1; + UINT64 R2; + UINT64 R3; + UINT64 R4; + UINT64 R5; + UINT64 R6; + UINT64 R7; + UINT64 Flags; + UINT64 ControlFlags; + UINT64 Ip; +} EFI_SYSTEM_CONTEXT_EBC; + + + +/// +/// ARM processor exception types. +/// +#define EXCEPT_ARM_RESET 0 +#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1 +#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2 +#define EXCEPT_ARM_PREFETCH_ABORT 3 +#define EXCEPT_ARM_DATA_ABORT 4 +#define EXCEPT_ARM_RESERVED 5 +#define EXCEPT_ARM_IRQ 6 +#define EXCEPT_ARM_FIQ 7 + +/// +/// For coding convenience, define the maximum valid ARM exception. +/// +#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ + +/// +/// ARM processor context definition. +/// +typedef struct { + UINT32 R0; + UINT32 R1; + UINT32 R2; + UINT32 R3; + UINT32 R4; + UINT32 R5; + UINT32 R6; + UINT32 R7; + UINT32 R8; + UINT32 R9; + UINT32 R10; + UINT32 R11; + UINT32 R12; + UINT32 SP; + UINT32 LR; + UINT32 PC; + UINT32 CPSR; + UINT32 DFSR; + UINT32 DFAR; + UINT32 IFSR; + UINT32 IFAR; +} EFI_SYSTEM_CONTEXT_ARM; + + +/// +/// AARCH64 processor exception types. +/// +#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0 +#define EXCEPT_AARCH64_IRQ 1 +#define EXCEPT_AARCH64_FIQ 2 +#define EXCEPT_AARCH64_SERROR 3 + +/// +/// For coding convenience, define the maximum valid ARM exception. +/// +#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR + +typedef struct { + // General Purpose Registers + UINT64 X0; + UINT64 X1; + UINT64 X2; + UINT64 X3; + UINT64 X4; + UINT64 X5; + UINT64 X6; + UINT64 X7; + UINT64 X8; + UINT64 X9; + UINT64 X10; + UINT64 X11; + UINT64 X12; + UINT64 X13; + UINT64 X14; + UINT64 X15; + UINT64 X16; + UINT64 X17; + UINT64 X18; + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 FP; // x29 - Frame pointer + UINT64 LR; // x30 - Link Register + UINT64 SP; // x31 - Stack pointer + + // FP/SIMD Registers + UINT64 V0[2]; + UINT64 V1[2]; + UINT64 V2[2]; + UINT64 V3[2]; + UINT64 V4[2]; + UINT64 V5[2]; + UINT64 V6[2]; + UINT64 V7[2]; + UINT64 V8[2]; + UINT64 V9[2]; + UINT64 V10[2]; + UINT64 V11[2]; + UINT64 V12[2]; + UINT64 V13[2]; + UINT64 V14[2]; + UINT64 V15[2]; + UINT64 V16[2]; + UINT64 V17[2]; + UINT64 V18[2]; + UINT64 V19[2]; + UINT64 V20[2]; + UINT64 V21[2]; + UINT64 V22[2]; + UINT64 V23[2]; + UINT64 V24[2]; + UINT64 V25[2]; + UINT64 V26[2]; + UINT64 V27[2]; + UINT64 V28[2]; + UINT64 V29[2]; + UINT64 V30[2]; + UINT64 V31[2]; + + UINT64 ELR; // Exception Link Register + UINT64 SPSR; // Saved Processor Status Register + UINT64 FPSR; // Floating Point Status Register + UINT64 ESR; // Exception syndrome register + UINT64 FAR; // Fault Address Register +} EFI_SYSTEM_CONTEXT_AARCH64; + +/// +/// RISC-V processor exception types. +/// +#define EXCEPT_RISCV_INST_MISALIGNED 0 +#define EXCEPT_RISCV_INST_ACCESS_FAULT 1 +#define EXCEPT_RISCV_ILLEGAL_INST 2 +#define EXCEPT_RISCV_BREAKPOINT 3 +#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4 +#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5 +#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6 +#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7 +#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8 +#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9 +#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10 +#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11 + +#define EXCEPT_RISCV_SOFTWARE_INT 0x0 +#define EXCEPT_RISCV_TIMER_INT 0x1 + +typedef struct { + UINT64 X0; + UINT64 X1; + UINT64 X2; + UINT64 X3; + UINT64 X4; + UINT64 X5; + UINT64 X6; + UINT64 X7; + UINT64 X8; + UINT64 X9; + UINT64 X10; + UINT64 X11; + UINT64 X12; + UINT64 X13; + UINT64 X14; + UINT64 X15; + UINT64 X16; + UINT64 X17; + UINT64 X18; + UINT64 X19; + UINT64 X20; + UINT64 X21; + UINT64 X22; + UINT64 X23; + UINT64 X24; + UINT64 X25; + UINT64 X26; + UINT64 X27; + UINT64 X28; + UINT64 X29; + UINT64 X30; + UINT64 X31; +} EFI_SYSTEM_CONTEXT_RISCV64; + +/// +/// Universal EFI_SYSTEM_CONTEXT definition. +/// +typedef union { + EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc; + EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32; + EFI_SYSTEM_CONTEXT_X64 *SystemContextX64; + EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf; + EFI_SYSTEM_CONTEXT_ARM *SystemContextArm; + EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64; + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64; +} EFI_SYSTEM_CONTEXT; + +// +// DebugSupport callback function prototypes +// + +/** + Registers and enables an exception callback function for the specified exception. + + @param ExceptionType Exception types in EBC, IA-32, x64, or IPF. + @param SystemContext Exception content. + +**/ +typedef +VOID +(EFIAPI *EFI_EXCEPTION_CALLBACK)( + IN EFI_EXCEPTION_TYPE ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + +/** + Registers and enables the on-target debug agent's periodic entry point. + + @param SystemContext Exception content. + +**/ +typedef +VOID +(EFIAPI *EFI_PERIODIC_CALLBACK)( + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + +/// +/// Machine type definition +/// +typedef enum { + IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C + IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664 + IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200 + IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC + IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2 + IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64 +} EFI_INSTRUCTION_SET_ARCHITECTURE; + + +// +// DebugSupport member function definitions +// + +/** + Returns the maximum value that may be used for the ProcessorIndex parameter in + RegisterPeriodicCallback() and RegisterExceptionCallback(). + + @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance. + @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported + processor index is returned. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)( + IN EFI_DEBUG_SUPPORT_PROTOCOL *This, + OUT UINTN *MaxProcessorIndex + ); + +/** + Registers a function to be called back periodically in interrupt context. + + @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance. + @param ProcessorIndex Specifies which processor the callback function applies to. + @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main + periodic entry point of the debug agent. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback + function was previously registered. + @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback + function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)( + IN EFI_DEBUG_SUPPORT_PROTOCOL *This, + IN UINTN ProcessorIndex, + IN EFI_PERIODIC_CALLBACK PeriodicCallback + ); + +/** + Registers a function to be called when a given processor exception occurs. + + @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance. + @param ProcessorIndex Specifies which processor the callback function applies to. + @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called + when the processor exception specified by ExceptionType occurs. + @param ExceptionType Specifies which processor exception to hook. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback + function was previously registered. + @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback + function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)( + IN EFI_DEBUG_SUPPORT_PROTOCOL *This, + IN UINTN ProcessorIndex, + IN EFI_EXCEPTION_CALLBACK ExceptionCallback, + IN EFI_EXCEPTION_TYPE ExceptionType + ); + +/** + Invalidates processor instruction cache for a memory range. Subsequent execution in this range + causes a fresh memory fetch to retrieve code to be executed. + + @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance. + @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated. + @param Start Specifies the physical base of the memory range to be invalidated. + @param Length Specifies the minimum number of bytes in the processor's instruction + cache to invalidate. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)( + IN EFI_DEBUG_SUPPORT_PROTOCOL *This, + IN UINTN ProcessorIndex, + IN VOID *Start, + IN UINT64 Length + ); + +/// +/// This protocol provides the services to allow the debug agent to register +/// callback functions that are called either periodically or when specific +/// processor exceptions occur. +/// +struct _EFI_DEBUG_SUPPORT_PROTOCOL { + /// + /// Declares the processor architecture for this instance of the EFI Debug Support protocol. + /// + EFI_INSTRUCTION_SET_ARCHITECTURE Isa; + EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex; + EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback; + EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback; + EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache; +}; + +extern EFI_GUID gEfiDebugSupportProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Decompress.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Decompress.h new file mode 100644 index 0000000000..9ca3e14b5a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Decompress.h @@ -0,0 +1,116 @@ +/** @file + The Decompress Protocol Interface as defined in UEFI spec + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DECOMPRESS_H__ +#define __DECOMPRESS_H__ + +#define EFI_DECOMPRESS_PROTOCOL_GUID \ + { \ + 0xd8117cfe, 0x94a6, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_DECOMPRESS_PROTOCOL EFI_DECOMPRESS_PROTOCOL; + +/** + The GetInfo() function retrieves the size of the uncompressed buffer + and the temporary scratch buffer required to decompress the buffer + specified by Source and SourceSize. If the size of the uncompressed + buffer or the size of the scratch buffer cannot be determined from + the compressed data specified by Source and SourceData, then + EFI_INVALID_PARAMETER is returned. Otherwise, the size of the uncompressed + buffer is returned in DestinationSize, the size of the scratch buffer is + returned in ScratchSize, and EFI_SUCCESS is returned. + + The GetInfo() function does not have a scratch buffer available to perform + a thorough checking of the validity of the source data. It just retrieves + the 'Original Size' field from the beginning bytes of the source data and + output it as DestinationSize. And ScratchSize is specific to the decompression + implementation. + + @param This A pointer to the EFI_DECOMPRESS_PROTOCOL instance. + @param Source The source buffer containing the compressed data. + @param SourceSize The size, in bytes, of source buffer. + @param DestinationSize A pointer to the size, in bytes, of the uncompressed buffer + that will be generated when the compressed buffer specified + by Source and SourceSize is decompressed. + @param ScratchSize A pointer to the size, in bytes, of the scratch buffer that + is required to decompress the compressed buffer specified by + Source and SourceSize. + + @retval EFI_SUCCESS The size of the uncompressed data was returned in DestinationSize + and the size of the scratch buffer was returned in ScratchSize. + @retval EFI_INVALID_PARAMETER The size of the uncompressed data or the size of the scratch + buffer cannot be determined from the compressed data specified by + Source and SourceData. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DECOMPRESS_GET_INFO)( + IN EFI_DECOMPRESS_PROTOCOL *This, + IN VOID *Source, + IN UINT32 SourceSize, + OUT UINT32 *DestinationSize, + OUT UINT32 *ScratchSize + ); + +/** + The Decompress() function extracts decompressed data to its original form. + + This protocol is designed so that the decompression algorithm can be + implemented without using any memory services. As a result, the + Decompress() function is not allowed to call AllocatePool() or + AllocatePages() in its implementation. It is the caller's responsibility + to allocate and free the Destination and Scratch buffers. + + If the compressed source data specified by Source and SourceSize is + successfully decompressed into Destination, then EFI_SUCCESS is returned. + If the compressed source data specified by Source and SourceSize is not in + a valid compressed data format, then EFI_INVALID_PARAMETER is returned. + + @param This A pointer to the EFI_DECOMPRESS_PROTOCOL instance. + @param Source The source buffer containing the compressed data. + @param SourceSize The size of source data. + @param Destination On output, the destination buffer that contains + the uncompressed data. + @param DestinationSize The size of destination buffer. The size of destination + buffer needed is obtained from GetInfo(). + @param Scratch A temporary scratch buffer that is used to perform the + decompression. + @param ScratchSize The size of scratch buffer. The size of scratch buffer needed + is obtained from GetInfo(). + + @retval EFI_SUCCESS Decompression completed successfully, and the uncompressed + buffer is returned in Destination. + @retval EFI_INVALID_PARAMETER The source buffer specified by Source and SourceSize is + corrupted (not in a valid compressed format). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DECOMPRESS_DECOMPRESS)( + IN EFI_DECOMPRESS_PROTOCOL *This, + IN VOID *Source, + IN UINT32 SourceSize, + IN OUT VOID *Destination, + IN UINT32 DestinationSize, + IN OUT VOID *Scratch, + IN UINT32 ScratchSize + ); + +/// +/// Provides a decompression service. +/// +struct _EFI_DECOMPRESS_PROTOCOL { + EFI_DECOMPRESS_GET_INFO GetInfo; + EFI_DECOMPRESS_DECOMPRESS Decompress; +}; + +extern EFI_GUID gEfiDecompressProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeferredImageLoad.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeferredImageLoad.h new file mode 100644 index 0000000000..7161ce02fe --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeferredImageLoad.h @@ -0,0 +1,74 @@ +/** @file + UEFI 2.2 Deferred Image Load Protocol definition. + + This protocol returns information about images whose load was denied because of security + considerations. This information can be used by the Boot Manager or another agent to reevaluate the + images when the current security profile has been changed, such as when the current user profile + changes. There can be more than one instance of this protocol installed. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEFERRED_IMAGE_LOAD_H__ +#define __DEFERRED_IMAGE_LOAD_H__ + +/// +/// Global ID for the Deferred Image Load Protocol +/// +#define EFI_DEFERRED_IMAGE_LOAD_PROTOCOL_GUID \ + { \ + 0x15853d7c, 0x3ddf, 0x43e0, { 0xa1, 0xcb, 0xeb, 0xf8, 0x5b, 0x8f, 0x87, 0x2c } \ + }; + +typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL EFI_DEFERRED_IMAGE_LOAD_PROTOCOL; + +/** + Returns information about a deferred image. + + This function returns information about a single deferred image. The deferred images are numbered + consecutively, starting with 0. If there is no image which corresponds to ImageIndex, then + EFI_NOT_FOUND is returned. All deferred images may be returned by iteratively calling this + function until EFI_NOT_FOUND is returned. + Image may be NULL and ImageSize set to 0 if the decision to defer execution was made because + of the location of the executable image rather than its actual contents. record handle until + there are no more, at which point UserInfo will point to NULL. + + @param[in] This Points to this instance of the EFI_DEFERRED_IMAGE_LOAD_PROTOCOL. + @param[in] ImageIndex Zero-based index of the deferred index. + @param[out] ImageDevicePath On return, points to a pointer to the device path of the image. + The device path should not be freed by the caller. + @param[out] Image On return, points to the first byte of the image or NULL if the + image is not available. The image should not be freed by the caller + unless LoadImage() has been called successfully. + @param[out] ImageSize On return, the size of the image, or 0 if the image is not available. + @param[out] BootOption On return, points to TRUE if the image was intended as a boot option + or FALSE if it was not intended as a boot option. + + @retval EFI_SUCCESS Image information returned successfully. + @retval EFI_NOT_FOUND ImageIndex does not refer to a valid image. + @retval EFI_INVALID_PARAMETER ImageDevicePath is NULL or Image is NULL or ImageSize is NULL or + BootOption is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEFERRED_IMAGE_INFO)( + IN EFI_DEFERRED_IMAGE_LOAD_PROTOCOL *This, + IN UINTN ImageIndex, + OUT EFI_DEVICE_PATH_PROTOCOL **ImageDevicePath, + OUT VOID **Image, + OUT UINTN *ImageSize, + OUT BOOLEAN *BootOption + ); + +/// +/// This protocol returns information about a deferred image. +/// +struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL { + EFI_DEFERRED_IMAGE_INFO GetImageInfo; +}; + +extern EFI_GUID gEfiDeferredImageLoadProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeviceIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeviceIo.h new file mode 100644 index 0000000000..7d52f1238b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DeviceIo.h @@ -0,0 +1,262 @@ +/** @file + Device IO protocol as defined in the EFI 1.10 specification. + + Device IO is used to abstract hardware access to devices. It includes + memory mapped IO, IO, PCI Config space, and DMA. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEVICE_IO_H__ +#define __DEVICE_IO_H__ + +#define EFI_DEVICE_IO_PROTOCOL_GUID \ + { \ + 0xaf6ac311, 0x84c3, 0x11d2, {0x8e, 0x3c, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct _EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL; + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL_GUID + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_INTERFACE; + +/// +/// Device IO Access Width +/// +typedef enum { + IO_UINT8 = 0, + IO_UINT16 = 1, + IO_UINT32 = 2, + IO_UINT64 = 3, + // + // Below enumerations are added in "Extensible Firmware Interface Specification, + // Version 1.10, Specification Update, Version 001". + // + MMIO_COPY_UINT8 = 4, + MMIO_COPY_UINT16 = 5, + MMIO_COPY_UINT32 = 6, + MMIO_COPY_UINT64 = 7 +} EFI_IO_WIDTH; + +/** + Enables a driver to access device registers in the appropriate memory or I/O space. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param Width Signifies the width of the I/O operations. + @param Address The base address of the I/O operations. + @param Count The number of I/O operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. If + Width is MMIO_COPY_UINT8, MMIO_COPY_UINT16, + MMIO_COPY_UINT32, or MMIO_COPY_UINT64, then + Buffer is interpreted as a base address of an I/O operation such as Address. + + @retval EFI_SUCCESS The data was read from or written to the device. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Width is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DEVICE_IO)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN EFI_IO_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +typedef struct { + EFI_DEVICE_IO Read; + EFI_DEVICE_IO Write; +} EFI_IO_ACCESS; + +/** + Provides an EFI Device Path for a PCI device with the given PCI configuration space address. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param PciAddress The PCI configuration space address of the device whose Device Path + is going to be returned. + @param PciDevicePath A pointer to the pointer for the EFI Device Path for PciAddress. + Memory for the Device Path is allocated from the pool. + + @retval EFI_SUCCESS The PciDevicePath returns a pointer to a valid EFI Device Path. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_UNSUPPORTED The PciAddress does not map to a valid EFI Device Path. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_DEVICE_PATH)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN UINT64 PciAddress, + IN OUT EFI_DEVICE_PATH_PROTOCOL **PciDevicePath + ); + +typedef enum { + /// + /// A read operation from system memory by a bus master. + /// + EfiBusMasterRead, + + /// + /// A write operation to system memory by a bus master. + /// + EfiBusMasterWrite, + + /// + /// Provides both read and write access to system memory + /// by both the processor and a bus master. The buffer is + /// coherent from both the processor's and the bus master's + /// point of view. + /// + EfiBusMasterCommonBuffer +} EFI_IO_OPERATION_TYPE; + +/** + Provides the device-specific addresses needed to access system memory. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param Operation Indicates if the bus master is going to read or write to system memory. + @param HostAddress The system memory address to map to the device. + @param NumberOfBytes On input, the number of bytes to map. + On output, the number of bytes that were mapped. + @param DeviceAddress The resulting map address for the bus master device to use to access the + hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. + @retval EFI_INVALID_PARAMETER The Operation or HostAddress is undefined. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IO_MAP)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN EFI_IO_OPERATION_TYPE Operation, + IN EFI_PHYSICAL_ADDRESS *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IO_UNMAP)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an EFIBusMasterCommonBuffer mapping. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param Type The type allocation to perform. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + @retval EFI_INVALID_PARAMETER The requested memory type is invalid. + @retval EFI_UNSUPPORTED The requested HostAddress is not supported on + this platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IO_ALLOCATE_BUFFER)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT EFI_PHYSICAL_ADDRESS *HostAddress + ); + +/** + Flushes any posted write data to the device. + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + + @retval EFI_SUCCESS The buffers were flushed. + @retval EFI_DEVICE_ERROR The buffers were not flushed due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IO_FLUSH)( + IN EFI_DEVICE_IO_PROTOCOL *This + ); + +/** + Frees pages that were allocated with AllocateBuffer(). + + @param This A pointer to the EFI_DEVICE_IO_INTERFACE instance. + @param Pages The number of pages to free. + @param HostAddress The base address of the range to free. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_NOT_FOUND The requested memory pages were not allocated with + AllocateBuffer(). + @retval EFI_INVALID_PARAMETER HostAddress is not page aligned or Pages is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IO_FREE_BUFFER)( + IN EFI_DEVICE_IO_PROTOCOL *This, + IN UINTN Pages, + IN EFI_PHYSICAL_ADDRESS HostAddress + ); + +/// +/// This protocol provides the basic Memory, I/O, and PCI interfaces that +/// are used to abstract accesses to devices. +/// +struct _EFI_DEVICE_IO_PROTOCOL { + /// + /// Allows reads and writes to memory mapped I/O space. + /// + EFI_IO_ACCESS Mem; + /// + /// Allows reads and writes to I/O space. + /// + EFI_IO_ACCESS Io; + /// + /// Allows reads and writes to PCI configuration space. + /// + EFI_IO_ACCESS Pci; + EFI_IO_MAP Map; + EFI_PCI_DEVICE_PATH PciDevicePath; + EFI_IO_UNMAP Unmap; + EFI_IO_ALLOCATE_BUFFER AllocateBuffer; + EFI_IO_FLUSH Flush; + EFI_IO_FREE_BUFFER FreeBuffer; +}; + +extern EFI_GUID gEfiDeviceIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePath.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePath.h new file mode 100644 index 0000000000..5eeca70c8b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePath.h @@ -0,0 +1,1379 @@ +/** @file + The device path protocol as defined in UEFI 2.0. + + The device path represents a programmatic path to a device, + from a software point of view. The path must persist from boot to boot, so + it can not contain things like PCI bus numbers that change from boot to boot. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DEVICE_PATH_PROTOCOL_H__ +#define __EFI_DEVICE_PATH_PROTOCOL_H__ + +#include +#include +#include + +/// +/// Device Path protocol. +/// +#define EFI_DEVICE_PATH_PROTOCOL_GUID \ + { \ + 0x9576e91, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +/// +/// Device Path guid definition for backward-compatible with EFI1.1. +/// +#define DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH_PROTOCOL_GUID + +#pragma pack(1) + +/** + This protocol can be used on any device handle to obtain generic path/location + information concerning the physical device or logical device. If the handle does + not logically map to a physical device, the handle may not necessarily support + the device path protocol. The device path describes the location of the device + the handle is for. The size of the Device Path can be determined from the structures + that make up the Device Path. +**/ +typedef struct { + UINT8 Type; ///< 0x01 Hardware Device Path. + ///< 0x02 ACPI Device Path. + ///< 0x03 Messaging Device Path. + ///< 0x04 Media Device Path. + ///< 0x05 BIOS Boot Specification Device Path. + ///< 0x7F End of Hardware Device Path. + + UINT8 SubType; ///< Varies by Type + ///< 0xFF End Entire Device Path, or + ///< 0x01 End This Instance of a Device Path and start a new + ///< Device Path. + + UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define + ///< type of data. Size of data is included in Length. + +} EFI_DEVICE_PATH_PROTOCOL; + +/// +/// Device Path protocol definition for backward-compatible with EFI1.1. +/// +typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH; + +/// +/// Hardware Device Paths. +/// +#define HARDWARE_DEVICE_PATH 0x01 + +/// +/// PCI Device Path SubType. +/// +#define HW_PCI_DP 0x01 + +/// +/// PCI Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// PCI Function Number. + /// + UINT8 Function; + /// + /// PCI Device Number. + /// + UINT8 Device; +} PCI_DEVICE_PATH; + +/// +/// PCCARD Device Path SubType. +/// +#define HW_PCCARD_DP 0x02 + +/// +/// PCCARD Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Function Number (0 = First Function). + /// + UINT8 FunctionNumber; +} PCCARD_DEVICE_PATH; + +/// +/// Memory Mapped Device Path SubType. +/// +#define HW_MEMMAP_DP 0x03 + +/// +/// Memory Mapped Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// EFI_MEMORY_TYPE + /// + UINT32 MemoryType; + /// + /// Starting Memory Address. + /// + EFI_PHYSICAL_ADDRESS StartingAddress; + /// + /// Ending Memory Address. + /// + EFI_PHYSICAL_ADDRESS EndingAddress; +} MEMMAP_DEVICE_PATH; + +/// +/// Hardware Vendor Device Path SubType. +/// +#define HW_VENDOR_DP 0x04 + +/// +/// The Vendor Device Path allows the creation of vendor-defined Device Paths. A vendor must +/// allocate a Vendor GUID for a Device Path. The Vendor GUID can then be used to define the +/// contents on the n bytes that follow in the Vendor Device Path node. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Vendor-assigned GUID that defines the data that follows. + /// + EFI_GUID Guid; + /// + /// Vendor-defined variable size data. + /// +} VENDOR_DEVICE_PATH; + +/// +/// Controller Device Path SubType. +/// +#define HW_CONTROLLER_DP 0x05 + +/// +/// Controller Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Controller number. + /// + UINT32 ControllerNumber; +} CONTROLLER_DEVICE_PATH; + +/// +/// BMC Device Path SubType. +/// +#define HW_BMC_DP 0x06 + +/// +/// BMC Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Interface Type. + /// + UINT8 InterfaceType; + /// + /// Base Address. + /// + UINT8 BaseAddress[8]; +} BMC_DEVICE_PATH; + +/// +/// ACPI Device Paths. +/// +#define ACPI_DEVICE_PATH 0x02 + +/// +/// ACPI Device Path SubType. +/// +#define ACPI_DP 0x01 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Device's PnP hardware ID stored in a numeric 32-bit + /// compressed EISA-type ID. This value must match the + /// corresponding _HID in the ACPI name space. + /// + UINT32 HID; + /// + /// Unique ID that is required by ACPI if two devices have the + /// same _HID. This value must also match the corresponding + /// _UID/_HID pair in the ACPI name space. Only the 32-bit + /// numeric value type of _UID is supported. Thus, strings must + /// not be used for the _UID in the ACPI name space. + /// + UINT32 UID; +} ACPI_HID_DEVICE_PATH; + +/// +/// Expanded ACPI Device Path SubType. +/// +#define ACPI_EXTENDED_DP 0x02 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Device's PnP hardware ID stored in a numeric 32-bit + /// compressed EISA-type ID. This value must match the + /// corresponding _HID in the ACPI name space. + /// + UINT32 HID; + /// + /// Unique ID that is required by ACPI if two devices have the + /// same _HID. This value must also match the corresponding + /// _UID/_HID pair in the ACPI name space. + /// + UINT32 UID; + /// + /// Device's compatible PnP hardware ID stored in a numeric + /// 32-bit compressed EISA-type ID. This value must match at + /// least one of the compatible device IDs returned by the + /// corresponding _CID in the ACPI name space. + /// + UINT32 CID; + /// + /// Optional variable length _HIDSTR. + /// Optional variable length _UIDSTR. + /// Optional variable length _CIDSTR. + /// +} ACPI_EXTENDED_HID_DEVICE_PATH; + +// +// EISA ID Macro +// EISA ID Definition 32-bits +// bits[15:0] - three character compressed ASCII EISA ID. +// bits[31:16] - binary number +// Compressed ASCII is 5 bits per character 0b00001 = 'A' 0b11010 = 'Z' +// +#define PNP_EISA_ID_CONST 0x41d0 +#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16)) +#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId))) +#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId))) + +#define PNP_EISA_ID_MASK 0xffff +#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16) + +/// +/// ACPI _ADR Device Path SubType. +/// +#define ACPI_ADR_DP 0x03 + +/// +/// The _ADR device path is used to contain video output device attributes to support the Graphics +/// Output Protocol. The device path can contain multiple _ADR entries if multiple video output +/// devices are displaying the same output. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// _ADR value. For video output devices the value of this + /// field comes from Table B-2 of the ACPI 3.0 specification. At + /// least one _ADR value is required. + /// + UINT32 ADR; + // + // This device path may optionally contain more than one _ADR entry. + // +} ACPI_ADR_DEVICE_PATH; + +/// +/// ACPI NVDIMM Device Path SubType. +/// +#define ACPI_NVDIMM_DP 0x04 +/// +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// NFIT Device Handle, the _ADR of the NVDIMM device. + /// The value of this field comes from Section 9.20.3 of the ACPI 6.2A specification. + /// + UINT32 NFITDeviceHandle; +} ACPI_NVDIMM_DEVICE_PATH; + +#define ACPI_ADR_DISPLAY_TYPE_OTHER 0 +#define ACPI_ADR_DISPLAY_TYPE_VGA 1 +#define ACPI_ADR_DISPLAY_TYPE_TV 2 +#define ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL 3 +#define ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL 4 + +#define ACPI_DISPLAY_ADR(_DeviceIdScheme, _HeadId, _NonVgaOutput, _BiosCanDetect, _VendorInfo, _Type, _Port, _Index) \ + ((UINT32)( ((UINT32)((_DeviceIdScheme) & 0x1) << 31) | \ + (((_HeadId) & 0x7) << 18) | \ + (((_NonVgaOutput) & 0x1) << 17) | \ + (((_BiosCanDetect) & 0x1) << 16) | \ + (((_VendorInfo) & 0xf) << 12) | \ + (((_Type) & 0xf) << 8) | \ + (((_Port) & 0xf) << 4) | \ + ((_Index) & 0xf) )) + +/// +/// Messaging Device Paths. +/// This Device Path is used to describe the connection of devices outside the resource domain of the +/// system. This Device Path can describe physical messaging information like SCSI ID, or abstract +/// information like networking protocol IP addresses. +/// +#define MESSAGING_DEVICE_PATH 0x03 + +/// +/// ATAPI Device Path SubType +/// +#define MSG_ATAPI_DP 0x01 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Set to zero for primary, or one for secondary. + /// + UINT8 PrimarySecondary; + /// + /// Set to zero for master, or one for slave mode. + /// + UINT8 SlaveMaster; + /// + /// Logical Unit Number. + /// + UINT16 Lun; +} ATAPI_DEVICE_PATH; + +/// +/// SCSI Device Path SubType. +/// +#define MSG_SCSI_DP 0x02 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Target ID on the SCSI bus (PUN). + /// + UINT16 Pun; + /// + /// Logical Unit Number (LUN). + /// + UINT16 Lun; +} SCSI_DEVICE_PATH; + +/// +/// Fibre Channel SubType. +/// +#define MSG_FIBRECHANNEL_DP 0x03 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Reserved for the future. + /// + UINT32 Reserved; + /// + /// Fibre Channel World Wide Number. + /// + UINT64 WWN; + /// + /// Fibre Channel Logical Unit Number. + /// + UINT64 Lun; +} FIBRECHANNEL_DEVICE_PATH; + +/// +/// Fibre Channel Ex SubType. +/// +#define MSG_FIBRECHANNELEX_DP 0x15 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Reserved for the future. + /// + UINT32 Reserved; + /// + /// 8 byte array containing Fibre Channel End Device Port Name. + /// + UINT8 WWN[8]; + /// + /// 8 byte array containing Fibre Channel Logical Unit Number. + /// + UINT8 Lun[8]; +} FIBRECHANNELEX_DEVICE_PATH; + +/// +/// 1394 Device Path SubType +/// +#define MSG_1394_DP 0x04 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Reserved for the future. + /// + UINT32 Reserved; + /// + /// 1394 Global Unique ID (GUID). + /// + UINT64 Guid; +} F1394_DEVICE_PATH; + +/// +/// USB Device Path SubType. +/// +#define MSG_USB_DP 0x05 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// USB Parent Port Number. + /// + UINT8 ParentPortNumber; + /// + /// USB Interface Number. + /// + UINT8 InterfaceNumber; +} USB_DEVICE_PATH; + +/// +/// USB Class Device Path SubType. +/// +#define MSG_USB_CLASS_DP 0x0f +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Vendor ID assigned by USB-IF. A value of 0xFFFF will + /// match any Vendor ID. + /// + UINT16 VendorId; + /// + /// Product ID assigned by USB-IF. A value of 0xFFFF will + /// match any Product ID. + /// + UINT16 ProductId; + /// + /// The class code assigned by the USB-IF. A value of 0xFF + /// will match any class code. + /// + UINT8 DeviceClass; + /// + /// The subclass code assigned by the USB-IF. A value of + /// 0xFF will match any subclass code. + /// + UINT8 DeviceSubClass; + /// + /// The protocol code assigned by the USB-IF. A value of + /// 0xFF will match any protocol code. + /// + UINT8 DeviceProtocol; +} USB_CLASS_DEVICE_PATH; + +/// +/// USB WWID Device Path SubType. +/// +#define MSG_USB_WWID_DP 0x10 + +/// +/// This device path describes a USB device using its serial number. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// USB interface number. + /// + UINT16 InterfaceNumber; + /// + /// USB vendor id of the device. + /// + UINT16 VendorId; + /// + /// USB product id of the device. + /// + UINT16 ProductId; + /// + /// Last 64-or-fewer UTF-16 characters of the USB + /// serial number. The length of the string is + /// determined by the Length field less the offset of the + /// Serial Number field (10) + /// + /// CHAR16 SerialNumber[...]; +} USB_WWID_DEVICE_PATH; + +/// +/// Device Logical Unit SubType. +/// +#define MSG_DEVICE_LOGICAL_UNIT_DP 0x11 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Logical Unit Number for the interface. + /// + UINT8 Lun; +} DEVICE_LOGICAL_UNIT_DEVICE_PATH; + +/// +/// SATA Device Path SubType. +/// +#define MSG_SATA_DP 0x12 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// The HBA port number that facilitates the connection to the + /// device or a port multiplier. The value 0xFFFF is reserved. + /// + UINT16 HBAPortNumber; + /// + /// The Port multiplier port number that facilitates the connection + /// to the device. Must be set to 0xFFFF if the device is directly + /// connected to the HBA. + /// + UINT16 PortMultiplierPortNumber; + /// + /// Logical Unit Number. + /// + UINT16 Lun; +} SATA_DEVICE_PATH; + +/// +/// Flag for if the device is directly connected to the HBA. +/// +#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000 + +/// +/// I2O Device Path SubType. +/// +#define MSG_I2O_DP 0x06 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Target ID (TID) for a device. + /// + UINT32 Tid; +} I2O_DEVICE_PATH; + +/// +/// MAC Address Device Path SubType. +/// +#define MSG_MAC_ADDR_DP 0x0b +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// The MAC address for a network interface padded with 0s. + /// + EFI_MAC_ADDRESS MacAddress; + /// + /// Network interface type(i.e. 802.3, FDDI). + /// + UINT8 IfType; +} MAC_ADDR_DEVICE_PATH; + +/// +/// IPv4 Device Path SubType +/// +#define MSG_IPv4_DP 0x0c +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// The local IPv4 address. + /// + EFI_IPv4_ADDRESS LocalIpAddress; + /// + /// The remote IPv4 address. + /// + EFI_IPv4_ADDRESS RemoteIpAddress; + /// + /// The local port number. + /// + UINT16 LocalPort; + /// + /// The remote port number. + /// + UINT16 RemotePort; + /// + /// The network protocol(i.e. UDP, TCP). + /// + UINT16 Protocol; + /// + /// 0x00 - The Source IP Address was assigned though DHCP. + /// 0x01 - The Source IP Address is statically bound. + /// + BOOLEAN StaticIpAddress; + /// + /// The gateway IP address + /// + EFI_IPv4_ADDRESS GatewayIpAddress; + /// + /// The subnet mask + /// + EFI_IPv4_ADDRESS SubnetMask; +} IPv4_DEVICE_PATH; + +/// +/// IPv6 Device Path SubType. +/// +#define MSG_IPv6_DP 0x0d +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// The local IPv6 address. + /// + EFI_IPv6_ADDRESS LocalIpAddress; + /// + /// The remote IPv6 address. + /// + EFI_IPv6_ADDRESS RemoteIpAddress; + /// + /// The local port number. + /// + UINT16 LocalPort; + /// + /// The remote port number. + /// + UINT16 RemotePort; + /// + /// The network protocol(i.e. UDP, TCP). + /// + UINT16 Protocol; + /// + /// 0x00 - The Local IP Address was manually configured. + /// 0x01 - The Local IP Address is assigned through IPv6 + /// stateless auto-configuration. + /// 0x02 - The Local IP Address is assigned through IPv6 + /// stateful configuration. + /// + UINT8 IpAddressOrigin; + /// + /// The prefix length + /// + UINT8 PrefixLength; + /// + /// The gateway IP address + /// + EFI_IPv6_ADDRESS GatewayIpAddress; +} IPv6_DEVICE_PATH; + +/// +/// InfiniBand Device Path SubType. +/// +#define MSG_INFINIBAND_DP 0x09 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Flags to help identify/manage InfiniBand device path elements: + /// Bit 0 - IOC/Service (0b = IOC, 1b = Service). + /// Bit 1 - Extend Boot Environment. + /// Bit 2 - Console Protocol. + /// Bit 3 - Storage Protocol. + /// Bit 4 - Network Protocol. + /// All other bits are reserved. + /// + UINT32 ResourceFlags; + /// + /// 128-bit Global Identifier for remote fabric port. + /// + UINT8 PortGid[16]; + /// + /// 64-bit unique identifier to remote IOC or server process. + /// Interpretation of field specified by Resource Flags (bit 0). + /// + UINT64 ServiceId; + /// + /// 64-bit persistent ID of remote IOC port. + /// + UINT64 TargetPortId; + /// + /// 64-bit persistent ID of remote device. + /// + UINT64 DeviceId; +} INFINIBAND_DEVICE_PATH; + +#define INFINIBAND_RESOURCE_FLAG_IOC_SERVICE 0x01 +#define INFINIBAND_RESOURCE_FLAG_EXTENDED_BOOT_ENVIRONMENT 0x02 +#define INFINIBAND_RESOURCE_FLAG_CONSOLE_PROTOCOL 0x04 +#define INFINIBAND_RESOURCE_FLAG_STORAGE_PROTOCOL 0x08 +#define INFINIBAND_RESOURCE_FLAG_NETWORK_PROTOCOL 0x10 + +/// +/// UART Device Path SubType. +/// +#define MSG_UART_DP 0x0e +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Reserved. + /// + UINT32 Reserved; + /// + /// The baud rate setting for the UART style device. A value of 0 + /// means that the device's default baud rate will be used. + /// + UINT64 BaudRate; + /// + /// The number of data bits for the UART style device. A value + /// of 0 means that the device's default number of data bits will be used. + /// + UINT8 DataBits; + /// + /// The parity setting for the UART style device. + /// Parity 0x00 - Default Parity. + /// Parity 0x01 - No Parity. + /// Parity 0x02 - Even Parity. + /// Parity 0x03 - Odd Parity. + /// Parity 0x04 - Mark Parity. + /// Parity 0x05 - Space Parity. + /// + UINT8 Parity; + /// + /// The number of stop bits for the UART style device. + /// Stop Bits 0x00 - Default Stop Bits. + /// Stop Bits 0x01 - 1 Stop Bit. + /// Stop Bits 0x02 - 1.5 Stop Bits. + /// Stop Bits 0x03 - 2 Stop Bits. + /// + UINT8 StopBits; +} UART_DEVICE_PATH; + +/// +/// NVDIMM Namespace Device Path SubType. +/// +#define NVDIMM_NAMESPACE_DP 0x20 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Namespace unique label identifier UUID. + /// + EFI_GUID Uuid; +} NVDIMM_NAMESPACE_DEVICE_PATH; + +// +// Use VENDOR_DEVICE_PATH struct +// +#define MSG_VENDOR_DP 0x0a +typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH; + +#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID +#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID +#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID +#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID + +/// +/// A new device path node is defined to declare flow control characteristics. +/// UART Flow Control Messaging Device Path +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL GUID. + /// + EFI_GUID Guid; + /// + /// Bitmap of supported flow control types. + /// Bit 0 set indicates hardware flow control. + /// Bit 1 set indicates Xon/Xoff flow control. + /// All other bits are reserved and are clear. + /// + UINT32 FlowControlMap; +} UART_FLOW_CONTROL_DEVICE_PATH; + +#define UART_FLOW_CONTROL_HARDWARE 0x00000001 +#define UART_FLOW_CONTROL_XON_XOFF 0x00000010 + +#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID +/// +/// Serial Attached SCSI (SAS) Device Path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// DEVICE_PATH_MESSAGING_SAS GUID. + /// + EFI_GUID Guid; + /// + /// Reserved for future use. + /// + UINT32 Reserved; + /// + /// SAS Address for Serial Attached SCSI Target. + /// + UINT64 SasAddress; + /// + /// SAS Logical Unit Number. + /// + UINT64 Lun; + /// + /// More Information about the device and its interconnect. + /// + UINT16 DeviceTopology; + /// + /// Relative Target Port (RTP). + /// + UINT16 RelativeTargetPort; +} SAS_DEVICE_PATH; + +/// +/// Serial Attached SCSI (SAS) Ex Device Path SubType +/// +#define MSG_SASEX_DP 0x16 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// 8-byte array of the SAS Address for Serial Attached SCSI Target Port. + /// + UINT8 SasAddress[8]; + /// + /// 8-byte array of the SAS Logical Unit Number. + /// + UINT8 Lun[8]; + /// + /// More Information about the device and its interconnect. + /// + UINT16 DeviceTopology; + /// + /// Relative Target Port (RTP). + /// + UINT16 RelativeTargetPort; +} SASEX_DEVICE_PATH; + +/// +/// NvmExpress Namespace Device Path SubType. +/// +#define MSG_NVME_NAMESPACE_DP 0x17 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + UINT32 NamespaceId; + UINT64 NamespaceUuid; +} NVME_NAMESPACE_DEVICE_PATH; + +/// +/// DNS Device Path SubType +/// +#define MSG_DNS_DP 0x1F +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Indicates the DNS server address is IPv4 or IPv6 address. + /// + UINT8 IsIPv6; + /// + /// Instance of the DNS server address. + /// + EFI_IP_ADDRESS DnsServerIp[]; +} DNS_DEVICE_PATH; + +/// +/// Uniform Resource Identifiers (URI) Device Path SubType +/// +#define MSG_URI_DP 0x18 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Instance of the URI pursuant to RFC 3986. + /// + CHAR8 Uri[]; +} URI_DEVICE_PATH; + +/// +/// Universal Flash Storage (UFS) Device Path SubType. +/// +#define MSG_UFS_DP 0x19 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Target ID on the UFS bus (PUN). + /// + UINT8 Pun; + /// + /// Logical Unit Number (LUN). + /// + UINT8 Lun; +} UFS_DEVICE_PATH; + +/// +/// SD (Secure Digital) Device Path SubType. +/// +#define MSG_SD_DP 0x1A +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + UINT8 SlotNumber; +} SD_DEVICE_PATH; + +/// +/// EMMC (Embedded MMC) Device Path SubType. +/// +#define MSG_EMMC_DP 0x1D +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + UINT8 SlotNumber; +} EMMC_DEVICE_PATH; + +/// +/// iSCSI Device Path SubType +/// +#define MSG_ISCSI_DP 0x13 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Network Protocol (0 = TCP, 1+ = reserved). + /// + UINT16 NetworkProtocol; + /// + /// iSCSI Login Options. + /// + UINT16 LoginOption; + /// + /// iSCSI Logical Unit Number. + /// + UINT64 Lun; + /// + /// iSCSI Target Portal group tag the initiator intends + /// to establish a session with. + /// + UINT16 TargetPortalGroupTag; + /// + /// iSCSI NodeTarget Name. The length of the name + /// is determined by subtracting the offset of this field from Length. + /// + /// CHAR8 iSCSI Target Name. +} ISCSI_DEVICE_PATH; + +#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000 +#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002 +#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000 +#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008 +#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000 +#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000 +#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000 +#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000 + +/// +/// VLAN Device Path SubType. +/// +#define MSG_VLAN_DP 0x14 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// VLAN identifier (0-4094). + /// + UINT16 VlanId; +} VLAN_DEVICE_PATH; + +/// +/// Bluetooth Device Path SubType. +/// +#define MSG_BLUETOOTH_DP 0x1b +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// 48bit Bluetooth device address. + /// + BLUETOOTH_ADDRESS BD_ADDR; +} BLUETOOTH_DEVICE_PATH; + +/// +/// Wi-Fi Device Path SubType. +/// +#define MSG_WIFI_DP 0x1C +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Service set identifier. A 32-byte octets string. + /// + UINT8 SSId[32]; +} WIFI_DEVICE_PATH; + +/// +/// Bluetooth LE Device Path SubType. +/// +#define MSG_BLUETOOTH_LE_DP 0x1E +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + BLUETOOTH_LE_ADDRESS Address; +} BLUETOOTH_LE_DEVICE_PATH; + +// +// Media Device Path +// +#define MEDIA_DEVICE_PATH 0x04 + +/// +/// Hard Drive Media Device Path SubType. +/// +#define MEDIA_HARDDRIVE_DP 0x01 + +/// +/// The Hard Drive Media Device Path is used to represent a partition on a hard drive. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Describes the entry in a partition table, starting with entry 1. + /// Partition number zero represents the entire device. Valid + /// partition numbers for a MBR partition are [1, 4]. Valid + /// partition numbers for a GPT partition are [1, NumberOfPartitionEntries]. + /// + UINT32 PartitionNumber; + /// + /// Starting LBA of the partition on the hard drive. + /// + UINT64 PartitionStart; + /// + /// Size of the partition in units of Logical Blocks. + /// + UINT64 PartitionSize; + /// + /// Signature unique to this partition: + /// If SignatureType is 0, this field has to be initialized with 16 zeros. + /// If SignatureType is 1, the MBR signature is stored in the first 4 bytes of this field. + /// The other 12 bytes are initialized with zeros. + /// If SignatureType is 2, this field contains a 16 byte signature. + /// + UINT8 Signature[16]; + /// + /// Partition Format: (Unused values reserved). + /// 0x01 - PC-AT compatible legacy MBR. + /// 0x02 - GUID Partition Table. + /// + UINT8 MBRType; + /// + /// Type of Disk Signature: (Unused values reserved). + /// 0x00 - No Disk Signature. + /// 0x01 - 32-bit signature from address 0x1b8 of the type 0x01 MBR. + /// 0x02 - GUID signature. + /// + UINT8 SignatureType; +} HARDDRIVE_DEVICE_PATH; + +#define MBR_TYPE_PCAT 0x01 +#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02 + +#define NO_DISK_SIGNATURE 0x00 +#define SIGNATURE_TYPE_MBR 0x01 +#define SIGNATURE_TYPE_GUID 0x02 + +/// +/// CD-ROM Media Device Path SubType. +/// +#define MEDIA_CDROM_DP 0x02 + +/// +/// The CD-ROM Media Device Path is used to define a system partition that exists on a CD-ROM. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Boot Entry number from the Boot Catalog. The Initial/Default entry is defined as zero. + /// + UINT32 BootEntry; + /// + /// Starting RBA of the partition on the medium. CD-ROMs use Relative logical Block Addressing. + /// + UINT64 PartitionStart; + /// + /// Size of the partition in units of Blocks, also called Sectors. + /// + UINT64 PartitionSize; +} CDROM_DEVICE_PATH; + +// +// Use VENDOR_DEVICE_PATH struct +// +#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype. + +/// +/// File Path Media Device Path SubType +/// +#define MEDIA_FILEPATH_DP 0x04 +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// A NULL-terminated Path string including directory and file names. + /// + CHAR16 PathName[1]; +} FILEPATH_DEVICE_PATH; + +#define SIZE_OF_FILEPATH_DEVICE_PATH OFFSET_OF(FILEPATH_DEVICE_PATH,PathName) + +/// +/// Media Protocol Device Path SubType. +/// +#define MEDIA_PROTOCOL_DP 0x05 + +/// +/// The Media Protocol Device Path is used to denote the protocol that is being +/// used in a device path at the location of the path specified. +/// Many protocols are inherent to the style of device path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// The ID of the protocol. + /// + EFI_GUID Protocol; +} MEDIA_PROTOCOL_DEVICE_PATH; + +/// +/// PIWG Firmware File SubType. +/// +#define MEDIA_PIWG_FW_FILE_DP 0x06 + +/// +/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware file. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Firmware file name + /// + EFI_GUID FvFileName; +} MEDIA_FW_VOL_FILEPATH_DEVICE_PATH; + +/// +/// PIWG Firmware Volume Device Path SubType. +/// +#define MEDIA_PIWG_FW_VOL_DP 0x07 + +/// +/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware volume. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Firmware volume name. + /// + EFI_GUID FvName; +} MEDIA_FW_VOL_DEVICE_PATH; + +/// +/// Media relative offset range device path. +/// +#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08 + +/// +/// Used to describe the offset range of media relative. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + UINT32 Reserved; + UINT64 StartingOffset; + UINT64 EndingOffset; +} MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH; + +/// +/// This GUID defines a RAM Disk supporting a raw disk format in volatile memory. +/// +#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE + +extern EFI_GUID gEfiVirtualDiskGuid; + +/// +/// This GUID defines a RAM Disk supporting an ISO image in volatile memory. +/// +#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE + +extern EFI_GUID gEfiVirtualCdGuid; + +/// +/// This GUID defines a RAM Disk supporting a raw disk format in persistent memory. +/// +#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT + +extern EFI_GUID gEfiPersistentVirtualDiskGuid; + +/// +/// This GUID defines a RAM Disk supporting an ISO image in persistent memory. +/// +#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT + +extern EFI_GUID gEfiPersistentVirtualCdGuid; + +/// +/// Media ram disk device path. +/// +#define MEDIA_RAM_DISK_DP 0x09 + +/// +/// Used to describe the ram disk device path. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Starting Memory Address. + /// + UINT32 StartingAddr[2]; + /// + /// Ending Memory Address. + /// + UINT32 EndingAddr[2]; + /// + /// GUID that defines the type of the RAM Disk. + /// + EFI_GUID TypeGuid; + /// + /// RAM Diskinstance number, if supported. The default value is zero. + /// + UINT16 Instance; +} MEDIA_RAM_DISK_DEVICE_PATH; + +/// +/// BIOS Boot Specification Device Path. +/// +#define BBS_DEVICE_PATH 0x05 + +/// +/// BIOS Boot Specification Device Path SubType. +/// +#define BBS_BBS_DP 0x01 + +/// +/// This Device Path is used to describe the booting of non-EFI-aware operating systems. +/// +typedef struct { + EFI_DEVICE_PATH_PROTOCOL Header; + /// + /// Device Type as defined by the BIOS Boot Specification. + /// + UINT16 DeviceType; + /// + /// Status Flags as defined by the BIOS Boot Specification. + /// + UINT16 StatusFlag; + /// + /// Null-terminated ASCII string that describes the boot device to a user. + /// + CHAR8 String[1]; +} BBS_BBS_DEVICE_PATH; + +// +// DeviceType definitions - from BBS specification +// +#define BBS_TYPE_FLOPPY 0x01 +#define BBS_TYPE_HARDDRIVE 0x02 +#define BBS_TYPE_CDROM 0x03 +#define BBS_TYPE_PCMCIA 0x04 +#define BBS_TYPE_USB 0x05 +#define BBS_TYPE_EMBEDDED_NETWORK 0x06 +#define BBS_TYPE_BEV 0x80 +#define BBS_TYPE_UNKNOWN 0xFF + + +/// +/// Union of all possible Device Paths and pointers to Device Paths. +/// +typedef union { + EFI_DEVICE_PATH_PROTOCOL DevPath; + PCI_DEVICE_PATH Pci; + PCCARD_DEVICE_PATH PcCard; + MEMMAP_DEVICE_PATH MemMap; + VENDOR_DEVICE_PATH Vendor; + + CONTROLLER_DEVICE_PATH Controller; + BMC_DEVICE_PATH Bmc; + ACPI_HID_DEVICE_PATH Acpi; + ACPI_EXTENDED_HID_DEVICE_PATH ExtendedAcpi; + ACPI_ADR_DEVICE_PATH AcpiAdr; + + ATAPI_DEVICE_PATH Atapi; + SCSI_DEVICE_PATH Scsi; + ISCSI_DEVICE_PATH Iscsi; + FIBRECHANNEL_DEVICE_PATH FibreChannel; + FIBRECHANNELEX_DEVICE_PATH FibreChannelEx; + + F1394_DEVICE_PATH F1394; + USB_DEVICE_PATH Usb; + SATA_DEVICE_PATH Sata; + USB_CLASS_DEVICE_PATH UsbClass; + USB_WWID_DEVICE_PATH UsbWwid; + DEVICE_LOGICAL_UNIT_DEVICE_PATH LogicUnit; + I2O_DEVICE_PATH I2O; + MAC_ADDR_DEVICE_PATH MacAddr; + IPv4_DEVICE_PATH Ipv4; + IPv6_DEVICE_PATH Ipv6; + VLAN_DEVICE_PATH Vlan; + INFINIBAND_DEVICE_PATH InfiniBand; + UART_DEVICE_PATH Uart; + UART_FLOW_CONTROL_DEVICE_PATH UartFlowControl; + SAS_DEVICE_PATH Sas; + SASEX_DEVICE_PATH SasEx; + NVME_NAMESPACE_DEVICE_PATH NvmeNamespace; + DNS_DEVICE_PATH Dns; + URI_DEVICE_PATH Uri; + BLUETOOTH_DEVICE_PATH Bluetooth; + WIFI_DEVICE_PATH WiFi; + UFS_DEVICE_PATH Ufs; + SD_DEVICE_PATH Sd; + EMMC_DEVICE_PATH Emmc; + HARDDRIVE_DEVICE_PATH HardDrive; + CDROM_DEVICE_PATH CD; + + FILEPATH_DEVICE_PATH FilePath; + MEDIA_PROTOCOL_DEVICE_PATH MediaProtocol; + + MEDIA_FW_VOL_DEVICE_PATH FirmwareVolume; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FirmwareFile; + MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH Offset; + MEDIA_RAM_DISK_DEVICE_PATH RamDisk; + BBS_BBS_DEVICE_PATH Bbs; +} EFI_DEV_PATH; + + + +typedef union { + EFI_DEVICE_PATH_PROTOCOL *DevPath; + PCI_DEVICE_PATH *Pci; + PCCARD_DEVICE_PATH *PcCard; + MEMMAP_DEVICE_PATH *MemMap; + VENDOR_DEVICE_PATH *Vendor; + + CONTROLLER_DEVICE_PATH *Controller; + BMC_DEVICE_PATH *Bmc; + ACPI_HID_DEVICE_PATH *Acpi; + ACPI_EXTENDED_HID_DEVICE_PATH *ExtendedAcpi; + ACPI_ADR_DEVICE_PATH *AcpiAdr; + + ATAPI_DEVICE_PATH *Atapi; + SCSI_DEVICE_PATH *Scsi; + ISCSI_DEVICE_PATH *Iscsi; + FIBRECHANNEL_DEVICE_PATH *FibreChannel; + FIBRECHANNELEX_DEVICE_PATH *FibreChannelEx; + + F1394_DEVICE_PATH *F1394; + USB_DEVICE_PATH *Usb; + SATA_DEVICE_PATH *Sata; + USB_CLASS_DEVICE_PATH *UsbClass; + USB_WWID_DEVICE_PATH *UsbWwid; + DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicUnit; + I2O_DEVICE_PATH *I2O; + MAC_ADDR_DEVICE_PATH *MacAddr; + IPv4_DEVICE_PATH *Ipv4; + IPv6_DEVICE_PATH *Ipv6; + VLAN_DEVICE_PATH *Vlan; + INFINIBAND_DEVICE_PATH *InfiniBand; + UART_DEVICE_PATH *Uart; + UART_FLOW_CONTROL_DEVICE_PATH *UartFlowControl; + SAS_DEVICE_PATH *Sas; + SASEX_DEVICE_PATH *SasEx; + NVME_NAMESPACE_DEVICE_PATH *NvmeNamespace; + DNS_DEVICE_PATH *Dns; + URI_DEVICE_PATH *Uri; + BLUETOOTH_DEVICE_PATH *Bluetooth; + WIFI_DEVICE_PATH *WiFi; + UFS_DEVICE_PATH *Ufs; + SD_DEVICE_PATH *Sd; + EMMC_DEVICE_PATH *Emmc; + HARDDRIVE_DEVICE_PATH *HardDrive; + CDROM_DEVICE_PATH *CD; + + FILEPATH_DEVICE_PATH *FilePath; + MEDIA_PROTOCOL_DEVICE_PATH *MediaProtocol; + + MEDIA_FW_VOL_DEVICE_PATH *FirmwareVolume; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FirmwareFile; + MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset; + MEDIA_RAM_DISK_DEVICE_PATH *RamDisk; + BBS_BBS_DEVICE_PATH *Bbs; + UINT8 *Raw; +} EFI_DEV_PATH_PTR; + +#pragma pack() + +#define END_DEVICE_PATH_TYPE 0x7f +#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF +#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01 + +extern EFI_GUID gEfiDevicePathProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathFromText.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathFromText.h new file mode 100644 index 0000000000..998fa5cd65 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathFromText.h @@ -0,0 +1,66 @@ +/** @file + EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL as defined in UEFI 2.0. + This protocol provides service to convert text to device paths and device nodes. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEVICE_PATH_FROM_TEXT_PROTOCOL_H__ +#define __DEVICE_PATH_FROM_TEXT_PROTOCOL_H__ + +/// +/// Device Path From Text protocol +/// +#define EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL_GUID \ + { \ + 0x5c99a21, 0xc70f, 0x4ad2, {0x8a, 0x5f, 0x35, 0xdf, 0x33, 0x43, 0xf5, 0x1e } \ + } + +/** + Convert text to the binary representation of a device node. + + @param TextDeviceNode TextDeviceNode points to the text representation of a device + node. Conversion starts with the first character and continues + until the first non-device node character. + + @retval a_pointer Pointer to the EFI device node. + @retval NULL if TextDeviceNode is NULL or there was insufficient memory. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_NODE)( + IN CONST CHAR16 *TextDeviceNode + ); + + +/** + Convert text to the binary representation of a device node. + + @param TextDeviceNode TextDevicePath points to the text representation of a device + path. Conversion starts with the first character and continues + until the first non-device path character. + + @retval a_pointer Pointer to the allocated device path. + @retval NULL if TextDeviceNode is NULL or there was insufficient memory. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_PATH)( + IN CONST CHAR16 *TextDevicePath + ); + +/// +/// This protocol converts text to device paths and device nodes. +/// +typedef struct { + EFI_DEVICE_PATH_FROM_TEXT_NODE ConvertTextToDeviceNode; + EFI_DEVICE_PATH_FROM_TEXT_PATH ConvertTextToDevicePath; +} EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL; + +extern EFI_GUID gEfiDevicePathFromTextProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathToText.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathToText.h new file mode 100644 index 0000000000..4a8cdaffb3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathToText.h @@ -0,0 +1,79 @@ +/** @file + EFI_DEVICE_PATH_TO_TEXT_PROTOCOL as defined in UEFI 2.0. + This protocol provides service to convert device nodes and paths to text. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEVICE_PATH_TO_TEXT_PROTOCOL_H__ +#define __DEVICE_PATH_TO_TEXT_PROTOCOL_H__ + +/// +/// Device Path To Text protocol +/// +#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \ + { \ + 0x8b843e20, 0x8132, 0x4852, {0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c } \ + } + +/** + Convert a device node to its text representation. + + @param DeviceNode Points to the device node to be converted. + @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation + of the display node is used, where applicable. If DisplayOnly + is FALSE, then the longer text representation of the display node + is used. + @param AllowShortcuts If AllowShortcuts is TRUE, then the shortcut forms of text + representation for a device node can be used, where applicable. + + @retval a_pointer a pointer to the allocated text representation of the device node data + @retval NULL if DeviceNode is NULL or there was insufficient memory. + +**/ +typedef +CHAR16* +(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_NODE)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode, + IN BOOLEAN DisplayOnly, + IN BOOLEAN AllowShortcuts + ); + +/** + Convert a device path to its text representation. + + @param DevicePath Points to the device path to be converted. + @param DisplayOnly If DisplayOnly is TRUE, then the shorter text representation + of the display node is used, where applicable. If DisplayOnly + is FALSE, then the longer text representation of the display node + is used. + @param AllowShortcuts The AllowShortcuts is FALSE, then the shortcut forms of + text representation for a device node cannot be used. + + @retval a_pointer a pointer to the allocated text representation of the device node. + @retval NULL if DevicePath is NULL or there was insufficient memory. + +**/ +typedef +CHAR16* +(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_PATH)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN BOOLEAN DisplayOnly, + IN BOOLEAN AllowShortcuts + ); + +/// +/// This protocol converts device paths and device nodes to text. +/// +typedef struct { + EFI_DEVICE_PATH_TO_TEXT_NODE ConvertDeviceNodeToText; + EFI_DEVICE_PATH_TO_TEXT_PATH ConvertDevicePathToText; +} EFI_DEVICE_PATH_TO_TEXT_PROTOCOL; + +extern EFI_GUID gEfiDevicePathToTextProtocolGuid; + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathUtilities.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathUtilities.h new file mode 100644 index 0000000000..68c91f05f1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DevicePathUtilities.h @@ -0,0 +1,186 @@ +/** @file + EFI_DEVICE_PATH_UTILITIES_PROTOCOL as defined in UEFI 2.0. + Use to create and manipulate device paths and device nodes. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEVICE_PATH_UTILITIES_PROTOCOL_H__ +#define __DEVICE_PATH_UTILITIES_PROTOCOL_H__ + +/// +/// Device Path Utilities protocol +/// +#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \ + { \ + 0x379be4e, 0xd706, 0x437d, {0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4 } \ + } + +/** + Returns the size of the device path, in bytes. + + @param DevicePath Points to the start of the EFI device path. + + @return Size Size of the specified device path, in bytes, including the end-of-path tag. + @retval 0 DevicePath is NULL + +**/ +typedef +UINTN +(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + + +/** + Create a duplicate of the specified path. + + @param DevicePath Points to the source EFI device path. + + @retval Pointer A pointer to the duplicate device path. + @retval NULL insufficient memory or DevicePath is NULL + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/** + Create a new path by appending the second device path to the first. + If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned. + If Src1 is non-NULL and Src2 is NULL, then a duplicate of Src1 is returned. + If Src1 and Src2 are both NULL, then a copy of an end-of-device-path is returned. + + @param Src1 Points to the first device path. + @param Src2 Points to the second device path. + + @retval Pointer A pointer to the newly created device path. + @retval NULL Memory could not be allocated + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_PATH)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1, + IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2 + ); + +/** + Creates a new path by appending the device node to the device path. + If DeviceNode is NULL then a copy of DevicePath is returned. + If DevicePath is NULL then a copy of DeviceNode, followed by an end-of-device path device node is returned. + If both DeviceNode and DevicePath are NULL then a copy of an end-of-device-path device node is returned. + + @param DevicePath Points to the device path. + @param DeviceNode Points to the device node. + + @retval Pointer A pointer to the allocated device node. + @retval NULL There was insufficient memory. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_NODE)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode + ); + +/** + Creates a new path by appending the specified device path instance to the specified device path. + + @param DevicePath Points to the device path. If NULL, then ignored. + @param DevicePathInstance Points to the device path instance. + + @retval Pointer A pointer to the newly created device path + @retval NULL Memory could not be allocated or DevicePathInstance is NULL. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance + ); + +/** + Creates a copy of the current device path instance and returns a pointer to the next device path + instance. + + @param DevicePathInstance On input, this holds the pointer to the current device path + instance. On output, this holds the pointer to the next + device path instance or NULL if there are no more device + path instances in the device path. + @param DevicePathInstanceSize On output, this holds the size of the device path instance, + in bytes or zero, if DevicePathInstance is NULL. + If NULL, then the instance size is not output. + + @retval Pointer A pointer to the copy of the current device path instance. + @retval NULL DevicePathInstace was NULL on entry or there was insufficient memory. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE)( + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathInstance, + OUT UINTN *DevicePathInstanceSize + ); + +/** + Creates a device node + + @param NodeType NodeType is the device node type (EFI_DEVICE_PATH.Type) for + the new device node. + @param NodeSubType NodeSubType is the device node sub-type + EFI_DEVICE_PATH.SubType) for the new device node. + @param NodeLength NodeLength is the length of the device node + (EFI_DEVICE_PATH.Length) for the new device node. + + @retval Pointer A pointer to the newly created device node. + @retval NULL NodeLength is less than + the size of the header or there was insufficient memory. + +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL* +(EFIAPI *EFI_DEVICE_PATH_UTILS_CREATE_NODE)( + IN UINT8 NodeType, + IN UINT8 NodeSubType, + IN UINT16 NodeLength +); + +/** + Returns whether a device path is multi-instance. + + @param DevicePath Points to the device path. If NULL, then ignored. + + @retval TRUE The device path has more than one instance + @retval FALSE The device path is empty or contains only a single instance. + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/// +/// This protocol is used to creates and manipulates device paths and device nodes. +/// +typedef struct { + EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize; + EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH DuplicateDevicePath; + EFI_DEVICE_PATH_UTILS_APPEND_PATH AppendDevicePath; + EFI_DEVICE_PATH_UTILS_APPEND_NODE AppendDeviceNode; + EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE AppendDevicePathInstance; + EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE GetNextDevicePathInstance; + EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE IsDevicePathMultiInstance; + EFI_DEVICE_PATH_UTILS_CREATE_NODE CreateDeviceNode; +} EFI_DEVICE_PATH_UTILITIES_PROTOCOL; + +extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp4.h new file mode 100644 index 0000000000..05a0a6e204 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp4.h @@ -0,0 +1,774 @@ +/** @file + EFI_DHCP4_PROTOCOL as defined in UEFI 2.0. + EFI_DHCP4_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0. + These protocols are used to collect configuration information for the EFI IPv4 Protocol + drivers and to provide DHCPv4 server and PXE boot server discovery services. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.0. + +**/ + +#ifndef __EFI_DHCP4_PROTOCOL_H__ +#define __EFI_DHCP4_PROTOCOL_H__ + +#define EFI_DHCP4_PROTOCOL_GUID \ + { \ + 0x8a219718, 0x4ef5, 0x4761, {0x91, 0xc8, 0xc0, 0xf0, 0x4b, 0xda, 0x9e, 0x56 } \ + } + +#define EFI_DHCP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x9d9a39d8, 0xbd42, 0x4a73, {0xa4, 0xd5, 0x8e, 0xe9, 0x4b, 0xe1, 0x13, 0x80 } \ + } + +typedef struct _EFI_DHCP4_PROTOCOL EFI_DHCP4_PROTOCOL; + + +#pragma pack(1) +typedef struct { + /// + /// DHCP option code. + /// + UINT8 OpCode; + /// + /// Length of the DHCP option data. Not present if OpCode is 0 or 255. + /// + UINT8 Length; + /// + /// Start of the DHCP option data. Not present if OpCode is 0 or 255 or if Length is zero. + /// + UINT8 Data[1]; +} EFI_DHCP4_PACKET_OPTION; +#pragma pack() + + +#pragma pack(1) +/// +/// EFI_DHCP4_PACKET defines the format of DHCPv4 packets. See RFC 2131 for more information. +/// +typedef struct { + UINT8 OpCode; + UINT8 HwType; + UINT8 HwAddrLen; + UINT8 Hops; + UINT32 Xid; + UINT16 Seconds; + UINT16 Reserved; + EFI_IPv4_ADDRESS ClientAddr; ///< Client IP address from client. + EFI_IPv4_ADDRESS YourAddr; ///< Client IP address from server. + EFI_IPv4_ADDRESS ServerAddr; ///< IP address of next server in bootstrap. + EFI_IPv4_ADDRESS GatewayAddr; ///< Relay agent IP address. + UINT8 ClientHwAddr[16]; ///< Client hardware address. + CHAR8 ServerName[64]; + CHAR8 BootFileName[128]; +}EFI_DHCP4_HEADER; +#pragma pack() + + +#pragma pack(1) +typedef struct { + /// + /// Size of the EFI_DHCP4_PACKET buffer. + /// + UINT32 Size; + /// + /// Length of the EFI_DHCP4_PACKET from the first byte of the Header field + /// to the last byte of the Option[] field. + /// + UINT32 Length; + + struct { + /// + /// DHCP packet header. + /// + EFI_DHCP4_HEADER Header; + /// + /// DHCP magik cookie in network byte order. + /// + UINT32 Magik; + /// + /// Start of the DHCP packed option data. + /// + UINT8 Option[1]; + } Dhcp4; +} EFI_DHCP4_PACKET; +#pragma pack() + + +typedef enum { + /// + /// The EFI DHCPv4 Protocol driver is stopped. + /// + Dhcp4Stopped = 0x0, + /// + /// The EFI DHCPv4 Protocol driver is inactive. + /// + Dhcp4Init = 0x1, + /// + /// The EFI DHCPv4 Protocol driver is collecting DHCP offer packets from DHCP servers. + /// + Dhcp4Selecting = 0x2, + /// + /// The EFI DHCPv4 Protocol driver has sent the request to the DHCP server and is waiting for a response. + /// + Dhcp4Requesting = 0x3, + /// + /// The DHCP configuration has completed. + /// + Dhcp4Bound = 0x4, + /// + /// The DHCP configuration is being renewed and another request has + /// been sent out, but it has not received a response from the server yet. + /// + Dhcp4Renewing = 0x5, + /// + /// The DHCP configuration has timed out and the EFI DHCPv4 + /// Protocol driver is trying to extend the lease time. + /// + Dhcp4Rebinding = 0x6, + /// + /// The EFI DHCPv4 Protocol driver was initialized with a previously + /// allocated or known IP address. + /// + Dhcp4InitReboot = 0x7, + /// + /// The EFI DHCPv4 Protocol driver is seeking to reuse the previously + /// allocated IP address by sending a request to the DHCP server. + /// + Dhcp4Rebooting = 0x8 +} EFI_DHCP4_STATE; + + +typedef enum{ + /// + /// The packet to start the configuration sequence is about to be sent. + /// + Dhcp4SendDiscover = 0x01, + /// + /// A reply packet was just received. + /// + Dhcp4RcvdOffer = 0x02, + /// + /// It is time for Dhcp4Callback to select an offer. + /// + Dhcp4SelectOffer = 0x03, + /// + /// A request packet is about to be sent. + /// + Dhcp4SendRequest = 0x04, + /// + /// A DHCPACK packet was received and will be passed to Dhcp4Callback. + /// + Dhcp4RcvdAck = 0x05, + /// + /// A DHCPNAK packet was received and will be passed to Dhcp4Callback. + /// + Dhcp4RcvdNak = 0x06, + /// + /// A decline packet is about to be sent. + /// + Dhcp4SendDecline = 0x07, + /// + /// The DHCP configuration process has completed. No packet is associated with this event. + /// + Dhcp4BoundCompleted = 0x08, + /// + /// It is time to enter the Dhcp4Renewing state and to contact the server + /// that originally issued the network address. No packet is associated with this event. + /// + Dhcp4EnterRenewing = 0x09, + /// + /// It is time to enter the Dhcp4Rebinding state and to contact any server. + /// No packet is associated with this event. + /// + Dhcp4EnterRebinding = 0x0a, + /// + /// The configured IP address was lost either because the lease has expired, + /// the user released the configuration, or a DHCPNAK packet was received in + /// the Dhcp4Renewing or Dhcp4Rebinding state. No packet is associated with this event. + /// + Dhcp4AddressLost = 0x0b, + /// + /// The DHCP process failed because a DHCPNAK packet was received or the user + /// aborted the DHCP process at a time when the configuration was not available yet. + /// No packet is associated with this event. + /// + Dhcp4Fail = 0x0c +} EFI_DHCP4_EVENT; + +/** + Callback routine. + + EFI_DHCP4_CALLBACK is provided by the consumer of the EFI DHCPv4 Protocol driver + to intercept events that occurred in the configuration process. This structure + provides advanced control of each state transition of the DHCP process. The + returned status code determines the behavior of the EFI DHCPv4 Protocol driver. + There are three possible returned values, which are described in the following + table. + + @param This The pointer to the EFI DHCPv4 Protocol instance that is used to + configure this callback function. + @param Context The pointer to the context that is initialized by + EFI_DHCP4_PROTOCOL.Configure(). + @param CurrentState The current operational state of the EFI DHCPv4 Protocol + driver. + @param Dhcp4Event The event that occurs in the current state, which usually means a + state transition. + @param Packet The DHCP packet that is going to be sent or already received. + @param NewPacket The packet that is used to replace the above Packet. + + @retval EFI_SUCCESS Tells the EFI DHCPv4 Protocol driver to continue the DHCP process. + When it is in the Dhcp4Selecting state, it tells the EFI DHCPv4 Protocol + driver to stop collecting additional packets. The driver will exit + the Dhcp4Selecting state and enter the Dhcp4Requesting state. + @retval EFI_NOT_READY Only used in the Dhcp4Selecting state. The EFI DHCPv4 Protocol + driver will continue to wait for more packets until the retry + timeout expires. + @retval EFI_ABORTED Tells the EFI DHCPv4 Protocol driver to abort the current process and + return to the Dhcp4Init or Dhcp4InitReboot state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_CALLBACK)( + IN EFI_DHCP4_PROTOCOL *This, + IN VOID *Context, + IN EFI_DHCP4_STATE CurrentState, + IN EFI_DHCP4_EVENT Dhcp4Event, + IN EFI_DHCP4_PACKET *Packet OPTIONAL, + OUT EFI_DHCP4_PACKET **NewPacket OPTIONAL + ); + +typedef struct { + /// + /// The number of times to try sending a packet during the Dhcp4SendDiscover + /// event and waiting for a response during the Dhcp4RcvdOffer event. + /// Set to zero to use the default try counts and timeout values. + /// + UINT32 DiscoverTryCount; + /// + /// The maximum amount of time (in seconds) to wait for returned packets in each + /// of the retries. Timeout values of zero will default to a timeout value + /// of one second. Set to NULL to use default timeout values. + /// + UINT32 *DiscoverTimeout; + /// + /// The number of times to try sending a packet during the Dhcp4SendRequest event + /// and waiting for a response during the Dhcp4RcvdAck event before accepting + /// failure. Set to zero to use the default try counts and timeout values. + /// + UINT32 RequestTryCount; + /// + /// The maximum amount of time (in seconds) to wait for return packets in each of the retries. + /// Timeout values of zero will default to a timeout value of one second. + /// Set to NULL to use default timeout values. + /// + UINT32 *RequestTimeout; + /// + /// For a DHCPDISCOVER, setting this parameter to the previously allocated IP + /// address will cause the EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state. + /// And set this field to 0.0.0.0 to enter the Dhcp4Init state. + /// For a DHCPINFORM this parameter should be set to the client network address + /// which was assigned to the client during a DHCPDISCOVER. + /// + EFI_IPv4_ADDRESS ClientAddress; + /// + /// The callback function to intercept various events that occurred in + /// the DHCP configuration process. Set to NULL to ignore all those events. + /// + EFI_DHCP4_CALLBACK Dhcp4Callback; + /// + /// The pointer to the context that will be passed to Dhcp4Callback when it is called. + /// + VOID *CallbackContext; + /// + /// Number of DHCP options in the OptionList. + /// + UINT32 OptionCount; + /// + /// List of DHCP options to be included in every packet that is sent during the + /// Dhcp4SendDiscover event. Pad options are appended automatically by DHCP driver + /// in outgoing DHCP packets. If OptionList itself contains pad option, they are + /// ignored by the driver. OptionList can be freed after EFI_DHCP4_PROTOCOL.Configure() + /// returns. Ignored if OptionCount is zero. + /// + EFI_DHCP4_PACKET_OPTION **OptionList; +} EFI_DHCP4_CONFIG_DATA; + + +typedef struct { + /// + /// The EFI DHCPv4 Protocol driver operating state. + /// + EFI_DHCP4_STATE State; + /// + /// The configuration data of the current EFI DHCPv4 Protocol driver instance. + /// + EFI_DHCP4_CONFIG_DATA ConfigData; + /// + /// The client IP address that was acquired from the DHCP server. If it is zero, + /// the DHCP acquisition has not completed yet and the following fields in this structure are undefined. + /// + EFI_IPv4_ADDRESS ClientAddress; + /// + /// The local hardware address. + /// + EFI_MAC_ADDRESS ClientMacAddress; + /// + /// The server IP address that is providing the DHCP service to this client. + /// + EFI_IPv4_ADDRESS ServerAddress; + /// + /// The router IP address that was acquired from the DHCP server. + /// May be zero if the server does not offer this address. + /// + EFI_IPv4_ADDRESS RouterAddress; + /// + /// The subnet mask of the connected network that was acquired from the DHCP server. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// The lease time (in 1-second units) of the configured IP address. + /// The value 0xFFFFFFFF means that the lease time is infinite. + /// A default lease of 7 days is used if the DHCP server does not provide a value. + /// + UINT32 LeaseTime; + /// + /// The cached latest DHCPACK or DHCPNAK or BOOTP REPLY packet. May be NULL if no packet is cached. + /// + EFI_DHCP4_PACKET *ReplyPacket; +} EFI_DHCP4_MODE_DATA; + + +typedef struct { + /// + /// Alternate listening address. It can be a unicast, multicast, or broadcast address. + /// + EFI_IPv4_ADDRESS ListenAddress; + /// + /// The subnet mask of above listening unicast/broadcast IP address. + /// Ignored if ListenAddress is a multicast address. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// Alternate station source (or listening) port number. + /// If zero, then the default station port number (68) will be used. + /// + UINT16 ListenPort; +} EFI_DHCP4_LISTEN_POINT; + + +typedef struct { + /// + /// The completion status of transmitting and receiving. + /// + EFI_STATUS Status; + /// + /// If not NULL, the event that will be signaled when the collection process + /// completes. If NULL, this function will busy-wait until the collection process competes. + /// + EFI_EVENT CompletionEvent; + /// + /// The pointer to the server IP address. This address may be a unicast, multicast, or broadcast address. + /// + EFI_IPv4_ADDRESS RemoteAddress; + /// + /// The server listening port number. If zero, the default server listening port number (67) will be used. + /// + UINT16 RemotePort; + /// + /// The pointer to the gateway address to override the existing setting. + /// + EFI_IPv4_ADDRESS GatewayAddress; + /// + /// The number of entries in ListenPoints. If zero, the default station address and port number 68 are used. + /// + UINT32 ListenPointCount; + /// + /// An array of station address and port number pairs that are used as receiving filters. + /// The first entry is also used as the source address and source port of the outgoing packet. + /// + EFI_DHCP4_LISTEN_POINT *ListenPoints; + /// + /// The number of seconds to collect responses. Zero is invalid. + /// + UINT32 TimeoutValue; + /// + /// The pointer to the packet to be transmitted. + /// + EFI_DHCP4_PACKET *Packet; + /// + /// Number of received packets. + /// + UINT32 ResponseCount; + /// + /// The pointer to the allocated list of received packets. + /// + EFI_DHCP4_PACKET *ResponseList; +} EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN; + + +/** + Returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol driver. + + The GetModeData() function returns the current operating mode and cached data + packet for the EFI DHCPv4 Protocol driver. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param Dhcp4ModeData The pointer to storage for the EFI_DHCP4_MODE_DATA structure. + + @retval EFI_SUCCESS The mode data was returned. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_GET_MODE_DATA)( + IN EFI_DHCP4_PROTOCOL *This, + OUT EFI_DHCP4_MODE_DATA *Dhcp4ModeData + ); + +/** + Initializes, changes, or resets the operational settings for the EFI DHCPv4 Protocol driver. + + The Configure() function is used to initialize, change, or reset the operational + settings of the EFI DHCPv4 Protocol driver for the communication device on which + the EFI DHCPv4 Service Binding Protocol is installed. This function can be + successfully called only if both of the following are true: + * This instance of the EFI DHCPv4 Protocol driver is in the Dhcp4Stopped, Dhcp4Init, + Dhcp4InitReboot, or Dhcp4Bound states. + * No other EFI DHCPv4 Protocol driver instance that is controlled by this EFI + DHCPv4 Service Binding Protocol driver instance has configured this EFI DHCPv4 + Protocol driver. + When this driver is in the Dhcp4Stopped state, it can transfer into one of the + following two possible initial states: + * Dhcp4Init + * Dhcp4InitReboot. + The driver can transfer into these states by calling Configure() with a non-NULL + Dhcp4CfgData. The driver will transfer into the appropriate state based on the + supplied client network address in the ClientAddress parameter and DHCP options + in the OptionList parameter as described in RFC 2131. + When Configure() is called successfully while Dhcp4CfgData is set to NULL, the + default configuring data will be reset in the EFI DHCPv4 Protocol driver and + the state of the EFI DHCPv4 Protocol driver will not be changed. If one instance + wants to make it possible for another instance to configure the EFI DHCPv4 Protocol + driver, it must call this function with Dhcp4CfgData set to NULL. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param Dhcp4CfgData The pointer to the EFI_DHCP4_CONFIG_DATA. + + @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init or + Dhcp4InitReboot state, if the original state of this driver + was Dhcp4Stopped, Dhcp4Init,Dhcp4InitReboot, or Dhcp4Bound + and the value of Dhcp4CfgData was not NULL. + Otherwise, the state was left unchanged. + @retval EFI_ACCESS_DENIED This instance of the EFI DHCPv4 Protocol driver was not in the + Dhcp4Stopped, Dhcp4Init, Dhcp4InitReboot, or Dhcp4Bound state; + Or onother instance of this EFI DHCPv4 Protocol driver is already + in a valid configured state. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + This is NULL. + DiscoverTryCount > 0 and DiscoverTimeout is NULL + RequestTryCount > 0 and RequestTimeout is NULL. + OptionCount >0 and OptionList is NULL. + ClientAddress is not a valid unicast address. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_CONFIGURE)( + IN EFI_DHCP4_PROTOCOL *This, + IN EFI_DHCP4_CONFIG_DATA *Dhcp4CfgData OPTIONAL + ); + + +/** + Starts the DHCP configuration process. + + The Start() function starts the DHCP configuration process. This function can + be called only when the EFI DHCPv4 Protocol driver is in the Dhcp4Init or + Dhcp4InitReboot state. + If the DHCP process completes successfully, the state of the EFI DHCPv4 Protocol + driver will be transferred through Dhcp4Selecting and Dhcp4Requesting to the + Dhcp4Bound state. The CompletionEvent will then be signaled if it is not NULL. + If the process aborts, either by the user or by some unexpected network error, + the state is restored to the Dhcp4Init state. The Start() function can be called + again to restart the process. + Refer to RFC 2131 for precise state transitions during this process. At the + time when each event occurs in this process, the callback function that was set + by EFI_DHCP4_PROTOCOL.Configure() will be called and the user can take this + opportunity to control the process. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param CompletionEvent If not NULL, it indicates the event that will be signaled when the + EFI DHCPv4 Protocol driver is transferred into the + Dhcp4Bound state or when the DHCP process is aborted. + EFI_DHCP4_PROTOCOL.GetModeData() can be called to + check the completion status. If NULL, + EFI_DHCP4_PROTOCOL.Start() will wait until the driver + is transferred into the Dhcp4Bound state or the process fails. + + @retval EFI_SUCCESS The DHCP configuration process has started, or it has completed + when CompletionEvent is NULL. + @retval EFI_NOT_STARTED The EFI DHCPv4 Protocol driver is in the Dhcp4Stopped + state. EFI_DHCP4_PROTOCOL. Configure() needs to be called. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_TIMEOUT The DHCP configuration process failed because no response was + received from the server within the specified timeout value. + @retval EFI_ABORTED The user aborted the DHCP process. + @retval EFI_ALREADY_STARTED Some other EFI DHCPv4 Protocol instance already started the + DHCP process. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_START)( + IN EFI_DHCP4_PROTOCOL *This, + IN EFI_EVENT CompletionEvent OPTIONAL + ); + +/** + Extends the lease time by sending a request packet. + + The RenewRebind() function is used to manually extend the lease time when the + EFI DHCPv4 Protocol driver is in the Dhcp4Bound state, and the lease time has + not expired yet. This function will send a request packet to the previously + found server (or to any server when RebindRequest is TRUE) and transfer the + state into the Dhcp4Renewing state (or Dhcp4Rebinding when RebindingRequest is + TRUE). When a response is received, the state is returned to Dhcp4Bound. + If no response is received before the try count is exceeded (the RequestTryCount + field that is specified in EFI_DHCP4_CONFIG_DATA) but before the lease time that + was issued by the previous server expires, the driver will return to the Dhcp4Bound + state, and the previous configuration is restored. The outgoing and incoming packets + can be captured by the EFI_DHCP4_CALLBACK function. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param RebindRequest If TRUE, this function broadcasts the request packets and enters + the Dhcp4Rebinding state. Otherwise, it sends a unicast + request packet and enters the Dhcp4Renewing state. + @param CompletionEvent If not NULL, this event is signaled when the renew/rebind phase + completes or some error occurs. + EFI_DHCP4_PROTOCOL.GetModeData() can be called to + check the completion status. If NULL, + EFI_DHCP4_PROTOCOL.RenewRebind() will busy-wait + until the DHCP process finishes. + + @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the + Dhcp4Renewing state or is back to the Dhcp4Bound state. + @retval EFI_NOT_STARTED The EFI DHCPv4 Protocol driver is in the Dhcp4Stopped + state. EFI_DHCP4_PROTOCOL.Configure() needs to + be called. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_TIMEOUT There was no response from the server when the try count was + exceeded. + @retval EFI_ACCESS_DENIED The driver is not in the Dhcp4Bound state. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_RENEW_REBIND)( + IN EFI_DHCP4_PROTOCOL *This, + IN BOOLEAN RebindRequest, + IN EFI_EVENT CompletionEvent OPTIONAL + ); + +/** + Releases the current address configuration. + + The Release() function releases the current configured IP address by doing either + of the following: + * Sending a DHCPRELEASE packet when the EFI DHCPv4 Protocol driver is in the + Dhcp4Bound state + * Setting the previously assigned IP address that was provided with the + EFI_DHCP4_PROTOCOL.Configure() function to 0.0.0.0 when the driver is in + Dhcp4InitReboot state + After a successful call to this function, the EFI DHCPv4 Protocol driver returns + to the Dhcp4Init state, and any subsequent incoming packets will be discarded silently. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + + @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Init phase. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_ACCESS_DENIED The EFI DHCPv4 Protocol driver is not Dhcp4InitReboot state. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_RELEASE)( + IN EFI_DHCP4_PROTOCOL *This + ); + +/** + Stops the current address configuration. + + The Stop() function is used to stop the DHCP configuration process. After this + function is called successfully, the EFI DHCPv4 Protocol driver is transferred + into the Dhcp4Stopped state. EFI_DHCP4_PROTOCOL.Configure() needs to be called + before DHCP configuration process can be started again. This function can be + called when the EFI DHCPv4 Protocol driver is in any state. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + + @retval EFI_SUCCESS The EFI DHCPv4 Protocol driver is now in the Dhcp4Stopped phase. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_STOP)( + IN EFI_DHCP4_PROTOCOL *This + ); + +/** + Builds a DHCP packet, given the options to be appended or deleted or replaced. + + The Build() function is used to assemble a new packet from the original packet + by replacing or deleting existing options or appending new options. This function + does not change any state of the EFI DHCPv4 Protocol driver and can be used at + any time. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param SeedPacket Initial packet to be used as a base for building new packet. + @param DeleteCount Number of opcodes in the DeleteList. + @param DeleteList List of opcodes to be deleted from the seed packet. + Ignored if DeleteCount is zero. + @param AppendCount Number of entries in the OptionList. + @param AppendList The pointer to a DHCP option list to be appended to SeedPacket. + If SeedPacket also contains options in this list, they are + replaced by new options (except pad option). Ignored if + AppendCount is zero. Type EFI_DHCP4_PACKET_OPTION + @param NewPacket The pointer to storage for the pointer to the new allocated packet. + Use the EFI Boot Service FreePool() on the resulting pointer + when done with the packet. + + @retval EFI_SUCCESS The new packet was built. + @retval EFI_OUT_OF_RESOURCES Storage for the new packet could not be allocated. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + SeedPacket is NULL. + SeedPacket is not a well-formed DHCP packet. + AppendCount is not zero and AppendList is NULL. + DeleteCount is not zero and DeleteList is NULL. + NewPacket is NULL + Both DeleteCount and AppendCount are zero and + NewPacket is not NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_BUILD)( + IN EFI_DHCP4_PROTOCOL *This, + IN EFI_DHCP4_PACKET *SeedPacket, + IN UINT32 DeleteCount, + IN UINT8 *DeleteList OPTIONAL, + IN UINT32 AppendCount, + IN EFI_DHCP4_PACKET_OPTION *AppendList[] OPTIONAL, + OUT EFI_DHCP4_PACKET **NewPacket + ); + + +/** + Transmits a DHCP formatted packet and optionally waits for responses. + + The TransmitReceive() function is used to transmit a DHCP packet and optionally + wait for the response from servers. This function does not change the state of + the EFI DHCPv4 Protocol driver. It can be used at any time because of this. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param Token The pointer to the EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN structure. + + @retval EFI_SUCCESS The packet was successfully queued for transmission. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token.RemoteAddress is zero. + Token.Packet is NULL. + Token.Packet is not a well-formed DHCP packet. + The transaction ID in Token.Packet is in use by another DHCP process. + @retval EFI_NOT_READY The previous call to this function has not finished yet. Try to call + this function after collection process completes. + @retval EFI_NO_MAPPING The default station address is not available yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_UNSUPPORTED The implementation doesn't support this function + @retval Others Some other unexpected error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_TRANSMIT_RECEIVE)( + IN EFI_DHCP4_PROTOCOL *This, + IN EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN *Token + ); + + +/** + Parses the packed DHCP option data. + + The Parse() function is used to retrieve the option list from a DHCP packet. + If *OptionCount isn't zero, and there is enough space for all the DHCP options + in the Packet, each element of PacketOptionList is set to point to somewhere in + the Packet->Dhcp4.Option where a new DHCP option begins. If RFC3396 is supported, + the caller should reassemble the parsed DHCP options to get the final result. + If *OptionCount is zero or there isn't enough space for all of them, the number + of DHCP options in the Packet is returned in OptionCount. + + @param This The pointer to the EFI_DHCP4_PROTOCOL instance. + @param Packet The pointer to packet to be parsed. + @param OptionCount On input, the number of entries in the PacketOptionList. + On output, the number of entries that were written into the + PacketOptionList. + @param PacketOptionList A list of packet option entries to be filled in. End option or pad + options are not included. + + @retval EFI_SUCCESS The packet was successfully parsed. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + The packet is NULL. + The packet is not a well-formed DHCP packet. + OptionCount is NULL. + @retval EFI_BUFFER_TOO_SMALL One or more of the following conditions is TRUE: + 1) *OptionCount is smaller than the number of options that + were found in the Packet. + 2) PacketOptionList is NULL. + @retval EFI_OUT_OF_RESOURCE The packet failed to parse because of a resource shortage. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP4_PARSE)( + IN EFI_DHCP4_PROTOCOL *This, + IN EFI_DHCP4_PACKET *Packet, + IN OUT UINT32 *OptionCount, + OUT EFI_DHCP4_PACKET_OPTION *PacketOptionList[] OPTIONAL + ); + +/// +/// This protocol is used to collect configuration information for the EFI IPv4 Protocol drivers +/// and to provide DHCPv4 server and PXE boot server discovery services. +/// +struct _EFI_DHCP4_PROTOCOL { + EFI_DHCP4_GET_MODE_DATA GetModeData; + EFI_DHCP4_CONFIGURE Configure; + EFI_DHCP4_START Start; + EFI_DHCP4_RENEW_REBIND RenewRebind; + EFI_DHCP4_RELEASE Release; + EFI_DHCP4_STOP Stop; + EFI_DHCP4_BUILD Build; + EFI_DHCP4_TRANSMIT_RECEIVE TransmitReceive; + EFI_DHCP4_PARSE Parse; +}; + +extern EFI_GUID gEfiDhcp4ProtocolGuid; +extern EFI_GUID gEfiDhcp4ServiceBindingProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp6.h new file mode 100644 index 0000000000..ca79afa2d5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dhcp6.h @@ -0,0 +1,780 @@ +/** @file + UEFI Dynamic Host Configuration Protocol 6 Definition, which is used to get IPv6 + addresses and other configuration parameters from DHCPv6 servers. + + Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_DHCP6_PROTOCOL_H__ +#define __EFI_DHCP6_PROTOCOL_H__ + +#define EFI_DHCP6_PROTOCOL_GUID \ + { \ + 0x87c8bad7, 0x595, 0x4053, {0x82, 0x97, 0xde, 0xde, 0x39, 0x5f, 0x5d, 0x5b } \ + } + +#define EFI_DHCP6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x9fb9a8a1, 0x2f4a, 0x43a6, {0x88, 0x9c, 0xd0, 0xf7, 0xb6, 0xc4, 0x7a, 0xd5 } \ + } + +typedef struct _EFI_DHCP6_PROTOCOL EFI_DHCP6_PROTOCOL; + +typedef enum { + /// + /// The EFI DHCPv6 Protocol instance is configured, and start() needs + /// to be called + /// + Dhcp6Init = 0x0, + /// + /// A Solicit packet is sent out to discover DHCPv6 server, and the EFI + /// DHCPv6 Protocol instance is collecting Advertise packets. + /// + Dhcp6Selecting = 0x1, + /// + /// A Request is sent out to the DHCPv6 server, and the EFI DHCPv6 + /// Protocol instance is waiting for Reply packet. + /// + Dhcp6Requesting = 0x2, + /// + /// A Decline packet is sent out to indicate one or more addresses of the + /// configured IA are in use by another node, and the EFI DHCPv6. + /// Protocol instance is waiting for Reply packet. + /// + Dhcp6Declining = 0x3, + /// + /// A Confirm packet is sent out to confirm the IPv6 addresses of the + /// configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet. + /// + Dhcp6Confirming = 0x4, + /// + /// A Release packet is sent out to release one or more IPv6 addresses of + /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet. + /// + Dhcp6Releasing = 0x5, + /// + /// The DHCPv6 S.A.R.R process is completed for the configured IA. + /// + Dhcp6Bound = 0x6, + /// + /// A Renew packet is sent out to extend lifetime for the IPv6 addresses of + /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet. + /// + Dhcp6Renewing = 0x7, + /// + /// A Rebind packet is sent out to extend lifetime for the IPv6 addresses of + /// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet. + /// + Dhcp6Rebinding = 0x8 +} EFI_DHCP6_STATE; + +typedef enum { + /// + /// A Solicit packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6SendSolicit = 0x0, + /// + /// An Advertise packet is received and will be passed to Dhcp6Callback. + /// + Dhcp6RcvdAdvertise = 0x1, + /// + /// It is time for Dhcp6Callback to determine whether select the default Advertise + /// packet by RFC 3315 policy, or overwrite it by specific user policy. + /// + Dhcp6SelectAdvertise = 0x2, + /// + /// A Request packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6SendRequest = 0x3, + /// + /// A Reply packet is received and will be passed to Dhcp6Callback. + /// + Dhcp6RcvdReply = 0x4, + /// + /// A Reconfigure packet is received and will be passed to Dhcp6Callback. + /// + Dhcp6RcvdReconfigure = 0x5, + /// + /// A Decline packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6SendDecline = 0x6, + /// + /// A Confirm packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6SendConfirm = 0x7, + /// + /// A Release packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6SendRelease = 0x8, + /// + /// A Renew packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6EnterRenewing = 0x9, + /// + /// A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and + /// can be modified or replaced in Dhcp6Callback. + /// + Dhcp6EnterRebinding = 0xa +} EFI_DHCP6_EVENT; + +/// +/// An IA which carries assigned not temporary address. +/// +#define EFI_DHCP6_IA_TYPE_NA 3 +/// +/// An IA which carries assigned temporary address. +/// +#define EFI_DHCP6_IA_TYPE_TA 4 + +#pragma pack(1) +/// +/// EFI_DHCP6_PACKET_OPTION +/// defines the format of the DHCPv6 option, See RFC 3315 for more information. +/// This data structure is used to reference option data that is packed in the DHCPv6 packet. +/// +typedef struct { + /// + /// The DHCPv6 option code, stored in network order. + /// + UINT16 OpCode; + /// + /// Length of the DHCPv6 option data, stored in network order. + /// From the first byte to the last byte of the Data field. + /// + UINT16 OpLen; + /// + /// The data for the DHCPv6 option, stored in network order. + /// + UINT8 Data[1]; +} EFI_DHCP6_PACKET_OPTION; + +/// +/// EFI_DHCP6_HEADER +/// defines the format of the DHCPv6 header. See RFC 3315 for more information. +/// +typedef struct{ + /// + /// The DHCPv6 transaction ID. + /// + UINT32 MessageType:8; + /// + /// The DHCPv6 message type. + /// + UINT32 TransactionId:24; +} EFI_DHCP6_HEADER; + +/// +/// EFI_DHCP6_PACKET +/// defines the format of the DHCPv6 packet. See RFC 3315 for more information. +/// +typedef struct { + /// + /// Size of the EFI_DHCP6_PACKET buffer. + /// + UINT32 Size; + /// + /// Length of the EFI_DHCP6_PACKET from the first byte of the Header field to the last + /// byte of the Option[] field. + /// + UINT32 Length; + struct{ + /// + /// The DHCPv6 packet header. + /// + EFI_DHCP6_HEADER Header; + /// + /// Start of the DHCPv6 packed option data. + /// + UINT8 Option[1]; + } Dhcp6; +} EFI_DHCP6_PACKET; + +#pragma pack() + +typedef struct { + /// + /// Length of DUID in octects. + /// + UINT16 Length; + /// + /// Array of DUID octects. + /// + UINT8 Duid[1]; +} EFI_DHCP6_DUID; + +typedef struct { + /// + /// Initial retransmission timeout. + /// + UINT32 Irt; + /// + /// Maximum retransmission count for one packet. If Mrc is zero, there's no upper limit + /// for retransmission count. + /// + UINT32 Mrc; + /// + /// Maximum retransmission timeout for each retry. It's the upper bound of the number of + /// retransmission timeout. If Mrt is zero, there is no upper limit for retransmission + /// timeout. + /// + UINT32 Mrt; + /// + /// Maximum retransmission duration for one packet. It's the upper bound of the numbers + /// the client may retransmit a message. If Mrd is zero, there's no upper limit for + /// retransmission duration. + /// + UINT32 Mrd; +} EFI_DHCP6_RETRANSMISSION; + +typedef struct { + /// + /// The IPv6 address. + /// + EFI_IPv6_ADDRESS IpAddress; + /// + /// The preferred lifetime in unit of seconds for the IPv6 address. + /// + UINT32 PreferredLifetime; + /// + /// The valid lifetime in unit of seconds for the IPv6 address. + /// + UINT32 ValidLifetime; +} EFI_DHCP6_IA_ADDRESS; + +typedef struct { + UINT16 Type; ///< Type for an IA. + UINT32 IaId; ///< The identifier for an IA. +} EFI_DHCP6_IA_DESCRIPTOR; + +typedef struct { + /// + /// The descriptor for IA. + /// + EFI_DHCP6_IA_DESCRIPTOR Descriptor; + /// + /// The state of the configured IA. + /// + EFI_DHCP6_STATE State; + /// + /// Pointer to the cached latest Reply packet. May be NULL if no packet is cached. + /// + EFI_DHCP6_PACKET *ReplyPacket; + /// + /// Number of IPv6 addresses of the configured IA. + /// + UINT32 IaAddressCount; + /// + /// List of the IPv6 addresses of the configured IA. When the state of the configured IA is + /// in Dhcp6Bound, Dhcp6Renewing and Dhcp6Rebinding, the IPv6 addresses are usable. + /// + EFI_DHCP6_IA_ADDRESS IaAddress[1]; +} EFI_DHCP6_IA; + +typedef struct { + /// + /// Pointer to the DHCPv6 unique identifier. The caller is responsible for freeing this buffer. + /// + EFI_DHCP6_DUID *ClientId; + /// + /// Pointer to the configured IA of current instance. The caller can free this buffer after + /// using it. + /// + EFI_DHCP6_IA *Ia; +} EFI_DHCP6_MODE_DATA; + +/** + EFI_DHCP6_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to + intercept events that occurs in the DHCPv6 S.A.R.R process. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this + callback function. + @param[in] Context Pointer to the context that is initialized by EFI_DHCP6_PROTOCOL.Configure(). + @param[in] CurrentState The current state of the configured IA. + @param[in] Dhcp6Event The event that occurs in the current state, which usually means a state transition. + @param[in] Packet Pointer to the DHCPv6 packet that is about to be sent or has been received. + The EFI DHCPv6 Protocol instance is responsible for freeing the buffer. + @param[out] NewPacket Pointer to the new DHCPv6 packet to overwrite the Packet. NewPacket can not + share the buffer with Packet. If *NewPacket is not NULL, the EFI DHCPv6 + Protocol instance is responsible for freeing the buffer. + + @retval EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to continue the DHCPv6 S.A.R.R process. + @retval EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the DHCPv6 S.A.R.R process, + and the state of the configured IA will be transferred to Dhcp6Init. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_CALLBACK)( + IN EFI_DHCP6_PROTOCOL *This, + IN VOID *Context, + IN EFI_DHCP6_STATE CurrentState, + IN EFI_DHCP6_EVENT Dhcp6Event, + IN EFI_DHCP6_PACKET *Packet, + OUT EFI_DHCP6_PACKET **NewPacket OPTIONAL + ); + +typedef struct { + /// + /// The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R + /// process. Set to NULL to ignore all those events. + /// + EFI_DHCP6_CALLBACK Dhcp6Callback; + /// + /// Pointer to the context that will be passed to Dhcp6Callback. + /// + VOID *CallbackContext; + /// + /// Number of the DHCPv6 options in the OptionList. + /// + UINT32 OptionCount; + /// + /// List of the DHCPv6 options to be included in Solicit and Request packet. The buffer + /// can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. Ignored if + /// OptionCount is zero. OptionList should not contain Client Identifier option + /// and any IA option, which will be appended by EFI DHCPv6 Protocol instance + /// automatically. + /// + EFI_DHCP6_PACKET_OPTION **OptionList; + /// + /// The descriptor for the IA of the EFI DHCPv6 Protocol instance. + /// + EFI_DHCP6_IA_DESCRIPTOR IaDescriptor; + /// + /// If not NULL, the event will be signaled when any IPv6 address information of the + /// configured IA is updated, including IPv6 address, preferred lifetime and valid + /// lifetime, or the DHCPv6 S.A.R.R process fails. Otherwise, Start(), + /// renewrebind(), decline(), release() and stop() will be blocking + /// operations, and they will wait for the exchange process completion or failure. + /// + EFI_EVENT IaInfoEvent; + /// + /// If TRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconfigure packet. + /// Otherwise, it will ignore it. Reconfigure Accept option can not be specified through + /// OptionList parameter. + /// + BOOLEAN ReconfigureAccept; + /// + /// If TRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid + /// Commit option. Otherwise, Rapid Commit option will not be included in Solicit + /// packet. Rapid Commit option can not be specified through OptionList parameter. + /// + BOOLEAN RapidCommit; + /// + /// Parameter to control Solicit packet retransmission behavior. The + /// buffer can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. + /// + EFI_DHCP6_RETRANSMISSION *SolicitRetransmission; +} EFI_DHCP6_CONFIG_DATA; + +/** + EFI_DHCP6_INFO_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol + instance to intercept events that occurs in the DHCPv6 Information Request exchange process. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this + callback function. + @param[in] Context Pointer to the context that is initialized in the EFI_DHCP6_PROTOCOL.InfoRequest(). + @param[in] Packet Pointer to Reply packet that has been received. The EFI DHCPv6 Protocol instance is + responsible for freeing the buffer. + + @retval EFI_SUCCESS Tell the EFI DHCPv6 Protocol instance to finish Information Request exchange process. + @retval EFI_NOT_READY Tell the EFI DHCPv6 Protocol instance to continue Information Request exchange process. + @retval EFI_ABORTED Tell the EFI DHCPv6 Protocol instance to abort the Information Request exchange process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_INFO_CALLBACK)( + IN EFI_DHCP6_PROTOCOL *This, + IN VOID *Context, + IN EFI_DHCP6_PACKET *Packet + ); + +/** + Retrieve the current operating mode data and configuration data for the EFI DHCPv6 Protocol instance. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + @param[out] Dhcp6ModeData Pointer to the DHCPv6 mode data structure. The caller is responsible for freeing this + structure and each reference buffer. + @param[out] Dhcp6ConfigData Pointer to the DHCPv6 configuration data structure. The caller is responsible for + freeing this structure and each reference buffer. + + @retval EFI_SUCCESS The mode data was returned. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Protocol instance has not been configured when Dhcp6ConfigData is not NULL. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + - This is NULL. + - Both Dhcp6ConfigData and Dhcp6ModeData are NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_GET_MODE_DATA)( + IN EFI_DHCP6_PROTOCOL *This, + OUT EFI_DHCP6_MODE_DATA *Dhcp6ModeData OPTIONAL, + OUT EFI_DHCP6_CONFIG_DATA *Dhcp6ConfigData OPTIONAL + ); + +/** + Initialize or clean up the configuration data for the EFI DHCPv6 Protocol instance. + + The Configure() function is used to initialize or clean up the configuration data of the EFI + DHCPv6 Protocol instance. + - When Dhcp6CfgData is not NULL and Configure() is called successfully, the + configuration data will be initialized in the EFI DHCPv6 Protocol instance and the state of the + configured IA will be transferred into Dhcp6Init. + - When Dhcp6CfgData is NULL and Configure() is called successfully, the configuration + data will be cleaned up and no IA will be associated with the EFI DHCPv6 Protocol instance. + + To update the configuration data for an EFI DCHPv6 Protocol instance, the original data must be + cleaned up before setting the new configuration data. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + @param[in] Dhcp6CfgData Pointer to the DHCPv6 configuration data structure. + + @retval EFI_SUCCESS The mode data was returned. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE + - This is NULL. + - OptionCount > 0 and OptionList is NULL. + - OptionList is not NULL, and Client Id option, Reconfigure Accept option, + Rapid Commit option or any IA option is specified in the OptionList. + - IaDescriptor.Type is neither EFI_DHCP6_IA_TYPE_NA nor EFI_DHCP6_IA_TYPE_NA. + - IaDescriptor is not unique. + - Both IaInfoEvent and SolicitRetransimssion are NULL. + - SolicitRetransmission is not NULL, and both SolicitRetransimssion->Mrc and + SolicitRetransmission->Mrd are zero. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Protocol instance has been already configured + when Dhcp6CfgData is not NULL. + The EFI DHCPv6 Protocol instance has already started the + DHCPv6 S.A.R.R when Dhcp6CfgData is NULL. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_CONFIGURE)( + IN EFI_DHCP6_PROTOCOL *This, + IN EFI_DHCP6_CONFIG_DATA *Dhcp6CfgData OPTIONAL + ); + +/** + Start the DHCPv6 S.A.R.R process. + + The Start() function starts the DHCPv6 S.A.R.R process. This function can be called only when + the state of the configured IA is in the Dhcp6Init state. If the DHCPv6 S.A.R.R process completes + successfully, the state of the configured IA will be transferred through Dhcp6Selecting and + Dhcp6Requesting to Dhcp6Bound state. The update of the IPv6 addresses will be notified through + EFI_DHCP6_CONFIG_DATA.IaInfoEvent. At the time when each event occurs in this process, the + callback function set by EFI_DHCP6_PROTOCOL.Configure() will be called and the user can take + this opportunity to control the process. If EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the + Start() function call is a blocking operation. It will return after the DHCPv6 S.A.R.R process + completes or aborted by users. If the process is aborted by system or network error, the state of + the configured IA will be transferred to Dhcp6Init. The Start() function can be called again to + restart the process. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + + @retval EFI_SUCCESS The DHCPv6 S.A.R.R process is completed and at least one IPv6 + address has been bound to the configured IA when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. + The DHCPv6 S.A.R.R process is started when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ALREADY_STARTED The DHCPv6 S.A.R.R process has already started. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_NO_RESPONSE The DHCPv6 S.A.R.R process failed because of no response. + @retval EFI_NO_MAPPING No IPv6 address has been bound to the configured IA after the + DHCPv6 S.A.R.R process. + @retval EFI_ABORTED The DHCPv6 S.A.R.R process aborted by user. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_START)( + IN EFI_DHCP6_PROTOCOL *This + ); + +/** + Request configuration information without the assignment of any IA addresses of the client. + + The InfoRequest() function is used to request configuration information without the assignment + of any IPv6 address of the client. Client sends out Information Request packet to obtain + the required configuration information, and DHCPv6 server responds with Reply packet containing + the information for the client. The received Reply packet will be passed to the user by + ReplyCallback function. If user returns EFI_NOT_READY from ReplyCallback, the EFI DHCPv6 + Protocol instance will continue to receive other Reply packets unless timeout according to + the Retransmission parameter. Otherwise, the Information Request exchange process will be + finished successfully if user returns EFI_SUCCESS from ReplyCallback. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + @param[in] SendClientId If TRUE, the EFI DHCPv6 Protocol instance will build Client + Identifier option and include it into Information Request + packet. If FALSE, Client Identifier option will not be included. + Client Identifier option can not be specified through OptionList + parameter. + @param[in] OptionRequest Pointer to the Option Request option in the Information Request + packet. Option Request option can not be specified through + OptionList parameter. + @param[in] OptionCount Number of options in OptionList. + @param[in] OptionList List of other DHCPv6 options. These options will be appended + to the Option Request option. The caller is responsible for + freeing this buffer. Type is defined in EFI_DHCP6_PROTOCOL.GetModeData(). + @param[in] Retransmission Parameter to control Information Request packet retransmission + behavior. The buffer can be freed after EFI_DHCP6_PROTOCOL.InfoRequest() + returns. + @param[in] TimeoutEvent If not NULL, this event is signaled when the information request + exchange aborted because of no response. If NULL, the function + call is a blocking operation; and it will return after the + information-request exchange process finish or aborted by users. + @param[in] ReplyCallback The callback function is to intercept various events that occur + in the Information Request exchange process. It should not be + set to NULL. + @param[in] CallbackContext Pointer to the context that will be passed to ReplyCallback. + + @retval EFI_SUCCESS The DHCPv6 S.A.R.R process is completed and at least one IPv6 + @retval EFI_SUCCESS The DHCPv6 information request exchange process completed + when TimeoutEvent is NULL. Information Request packet has been + sent to DHCPv6 server when TimeoutEvent is not NULL. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + - This is NULL. + - OptionRequest is NULL or OptionRequest->OpCode is invalid. + - OptionCount > 0 and OptionList is NULL. + - OptionList is not NULL, and Client Identify option or + Option Request option is specified in the OptionList. + - Retransimssion is NULL. + - Both Retransimssion->Mrc and Retransmission->Mrd are zero. + - ReplyCallback is NULL. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_NO_RESPONSE The DHCPv6 information request exchange process failed + because of no response, or not all requested-options are + responded by DHCPv6 servers when Timeout happened. + @retval EFI_ABORTED The DHCPv6 information request exchange process aborted by user. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_INFO_REQUEST)( + IN EFI_DHCP6_PROTOCOL *This, + IN BOOLEAN SendClientId, + IN EFI_DHCP6_PACKET_OPTION *OptionRequest, + IN UINT32 OptionCount, + IN EFI_DHCP6_PACKET_OPTION *OptionList[] OPTIONAL, + IN EFI_DHCP6_RETRANSMISSION *Retransmission, + IN EFI_EVENT TimeoutEvent OPTIONAL, + IN EFI_DHCP6_INFO_CALLBACK ReplyCallback, + IN VOID *CallbackContext OPTIONAL + ); + +/** + Manually extend the valid and preferred lifetimes for the IPv6 addresses of the configured + IA and update other configuration parameters by sending Renew or Rebind packet. + + The RenewRebind() function is used to manually extend the valid and preferred lifetimes for the + IPv6 addresses of the configured IA and update other configuration parameters by sending Renew or + Rebind packet. + - When RebindRequest is FALSE and the state of the configured IA is Dhcp6Bound, it + will send Renew packet to the previously DHCPv6 server and transfer the state of the configured + IA to Dhcp6Renewing. If valid Reply packet received, the state transfers to Dhcp6Bound + and the valid and preferred timer restarts. If fails, the state transfers to Dhcp6Bound but the + timer continues. + - When RebindRequest is TRUE and the state of the configured IA is Dhcp6Bound, it will + send Rebind packet. If valid Reply packet received, the state transfers to Dhcp6Bound and the + valid and preferred timer restarts. If fails, the state transfers to Dhcp6Init and the IA can't + be used. + + @param[in] This Pointer to the EFI_DHCP4_PROTOCOL instance. + @param[in] RebindRequest If TRUE, it will send Rebind packet and enter the Dhcp6Rebinding state. + Otherwise, it will send Renew packet and enter the Dhcp6Renewing state. + + @retval EFI_SUCCESS The DHCPv6 renew/rebind exchange process has completed and at + least one IPv6 address of the configured IA has been bound again + when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. + The EFI DHCPv6 Protocol instance has sent Renew or Rebind packet + when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the state + of the configured IA is not in Dhcp6Bound. + @retval EFI_ALREADY_STARTED The state of the configured IA has already entered Dhcp6Renewing + when RebindRequest is FALSE. + The state of the configured IA has already entered Dhcp6Rebinding + when RebindRequest is TRUE. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or system error occurred. + @retval EFI_NO_RESPONSE The DHCPv6 renew/rebind exchange process failed because of no response. + @retval EFI_NO_MAPPING No IPv6 address has been bound to the configured IA after the DHCPv6 + renew/rebind exchange process. + @retval EFI_ABORTED The DHCPv6 renew/rebind exchange process aborted by user. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_RENEW_REBIND)( + IN EFI_DHCP6_PROTOCOL *This, + IN BOOLEAN RebindRequest + ); + +/** + Inform that one or more IPv6 addresses assigned by a server are already in use by + another node. + + The Decline() function is used to manually decline the assignment of IPv6 addresses, which + have been already used by another node. If all IPv6 addresses of the configured IA are declined + through this function, the state of the IA will switch through Dhcp6Declining to Dhcp6Init, + otherwise, the state of the IA will restore to Dhcp6Bound after the declining process. The + Decline() can only be called when the IA is in Dhcp6Bound state. If the + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, this function is a blocking operation. It + will return after the declining process finishes, or aborted by user. + + @param[in] This Pointer to the EFI_DHCP4_PROTOCOL instance. + @param[in] AddressCount Number of declining IPv6 addresses. + @param[in] Addresses Pointer to the buffer stored all the declining IPv6 addresses. + + @retval EFI_SUCCESS The DHCPv6 decline exchange process has completed when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. + The EFI DHCPv6 Protocol instance has sent Decline packet when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE + - This is NULL. + - AddressCount is zero or Addresses is NULL. + @retval EFI_NOT_FOUND Any specified IPv6 address is not correlated with the configured IA + for this instance. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the + state of the configured IA is not in Dhcp6Bound. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_ABORTED The DHCPv6 decline exchange process aborted by user. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_DECLINE)( + IN EFI_DHCP6_PROTOCOL *This, + IN UINT32 AddressCount, + IN EFI_IPv6_ADDRESS *Addresses + ); + +/** + Release one or more IPv6 addresses associated with the configured IA for current instance. + + The Release() function is used to manually release the one or more IPv6 address. If AddressCount + is zero, it will release all IPv6 addresses of the configured IA. If all IPv6 addresses of the IA + are released through this function, the state of the IA will switch through Dhcp6Releasing to + Dhcp6Init, otherwise, the state of the IA will restore to Dhcp6Bound after the releasing process. + The Release() can only be called when the IA is in Dhcp6Bound state. If the + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the function is a blocking operation. It will return + after the releasing process finishes, or aborted by user. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + @param[in] AddressCount Number of releasing IPv6 addresses. + @param[in] Addresses Pointer to the buffer stored all the releasing IPv6 addresses. + Ignored if AddressCount is zero. + @retval EFI_SUCCESS The DHCPv6 release exchange process has completed when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. + The EFI DHCPv6 Protocol instance has sent Release packet when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE + - This is NULL. + - AddressCount is not zero or Addresses is NULL. + @retval EFI_NOT_FOUND Any specified IPv6 address is not correlated with the configured + IA for this instance. + @retval EFI_ACCESS_DENIED The EFI DHCPv6 Child instance hasn't been configured, or the + state of the configured IA is not in Dhcp6Bound. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_ABORTED The DHCPv6 release exchange process aborted by user. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_RELEASE)( + IN EFI_DHCP6_PROTOCOL *This, + IN UINT32 AddressCount, + IN EFI_IPv6_ADDRESS *Addresses + ); + +/** + Stop the DHCPv6 S.A.R.R process. + + The Stop() function is used to stop the DHCPv6 S.A.R.R process. If this function is called + successfully, all the IPv6 addresses of the configured IA will be released and the state of + the configured IA will be transferred to Dhcp6Init. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + + @retval EFI_SUCCESS The DHCPv6 S.A.R.R process has been stopped when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. + The EFI DHCPv6 Protocol instance has sent Release packet if + need release or has been stopped if needn't, when + EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_STOP)( + IN EFI_DHCP6_PROTOCOL *This + ); + +/** + Parse the option data in the DHCPv6 packet. + + The Parse() function is used to retrieve the option list in the DHCPv6 packet. + + @param[in] This Pointer to the EFI_DHCP6_PROTOCOL instance. + + @param[in] Packet Pointer to packet to be parsed. + @param[in] OptionCount On input, the number of entries in the PacketOptionList. + On output, the number of DHCPv6 options in the Packet. + @param[in] PacketOptionList List of pointers to the DHCPv6 options in the Packet. + The OpCode and OpLen in EFI_DHCP6_PACKET_OPTION are + both stored in network byte order. + @retval EFI_SUCCESS The packet was successfully parsed. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE + - This is NULL. + - Packet is NULL. + - Packet is not a well-formed DHCPv6 packet. + - OptionCount is NULL. + - *OptionCount is not zero and PacketOptionList is NULL. + @retval EFI_BUFFER_TOO_SMALL *OptionCount is smaller than the number of options that were + found in the Packet. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DHCP6_PARSE)( + IN EFI_DHCP6_PROTOCOL *This, + IN EFI_DHCP6_PACKET *Packet, + IN OUT UINT32 *OptionCount, + OUT EFI_DHCP6_PACKET_OPTION *PacketOptionList[] OPTIONAL +); + +/// +/// The EFI DHCPv6 Protocol is used to get IPv6 addresses and other configuration parameters +/// from DHCPv6 servers. +/// +struct _EFI_DHCP6_PROTOCOL { + EFI_DHCP6_GET_MODE_DATA GetModeData; + EFI_DHCP6_CONFIGURE Configure; + EFI_DHCP6_START Start; + EFI_DHCP6_INFO_REQUEST InfoRequest; + EFI_DHCP6_RENEW_REBIND RenewRebind; + EFI_DHCP6_DECLINE Decline; + EFI_DHCP6_RELEASE Release; + EFI_DHCP6_STOP Stop; + EFI_DHCP6_PARSE Parse; +}; + +extern EFI_GUID gEfiDhcp6ProtocolGuid; +extern EFI_GUID gEfiDhcp6ServiceBindingProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskInfo.h new file mode 100644 index 0000000000..e0215d61df --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskInfo.h @@ -0,0 +1,221 @@ +/** @file + Provides the basic interfaces to abstract platform information regarding an + IDE controller. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.6 + Volume 5: Standards + +**/ + +#ifndef __DISK_INFO_H__ +#define __DISK_INFO_H__ + +/// +/// Global ID for EFI_DISK_INFO_PROTOCOL +/// +#define EFI_DISK_INFO_PROTOCOL_GUID \ + { \ + 0xd432a67f, 0x14dc, 0x484b, {0xb3, 0xbb, 0x3f, 0x2, 0x91, 0x84, 0x93, 0x27 } \ + } + +/// +/// Forward declaration for EFI_DISK_INFO_PROTOCOL +/// +typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL; + +/// +/// Global ID for an IDE interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_IDE_INTERFACE_GUID \ + { \ + 0x5e948fe3, 0x26d3, 0x42b5, {0xaf, 0x17, 0x61, 0x2, 0x87, 0x18, 0x8d, 0xec } \ + } + +/// +/// Global ID for a SCSI interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_SCSI_INTERFACE_GUID \ + { \ + 0x8f74baa, 0xea36, 0x41d9, {0x95, 0x21, 0x21, 0xa7, 0xf, 0x87, 0x80, 0xbc } \ + } + +/// +/// Global ID for a USB interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_USB_INTERFACE_GUID \ + { \ + 0xcb871572, 0xc11a, 0x47b5, {0xb4, 0x92, 0x67, 0x5e, 0xaf, 0xa7, 0x77, 0x27 } \ + } + +/// +/// Global ID for an AHCI interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_AHCI_INTERFACE_GUID \ + { \ + 0x9e498932, 0x4abc, 0x45af, {0xa3, 0x4d, 0x2, 0x47, 0x78, 0x7b, 0xe7, 0xc6 } \ + } + +/// +/// Global ID for a NVME interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_NVME_INTERFACE_GUID \ + { \ + 0x3ab14680, 0x5d3f, 0x4a4d, {0xbc, 0xdc, 0xcc, 0x38, 0x0, 0x18, 0xc7, 0xf7 } \ + } + +/// +/// Global ID for a UFS interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_UFS_INTERFACE_GUID \ + { \ + 0x4b3029cc, 0x6b98, 0x47fb, { 0xbc, 0x96, 0x76, 0xdc, 0xb8, 0x4, 0x41, 0xf0 } \ + } + +/// +/// Global ID for an SD/MMC interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface +/// +#define EFI_DISK_INFO_SD_MMC_INTERFACE_GUID \ + { \ + 0x8deec992, 0xd39c, 0x4a5c, { 0xab, 0x6b, 0x98, 0x6e, 0x14, 0x24, 0x2b, 0x9d } \ + } + +/** + Provides inquiry information for the controller type. + + This function is used by the IDE bus driver to get inquiry data. Data format + of Identify data is defined by the Interface GUID. + + @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance. + @param[in,out] InquiryData Pointer to a buffer for the inquiry data. + @param[in,out] InquiryDataSize Pointer to the value for the inquiry data size. + + @retval EFI_SUCCESS The command was accepted without any errors. + @retval EFI_NOT_FOUND Device does not support this data class + @retval EFI_DEVICE_ERROR Error reading InquiryData from device + @retval EFI_BUFFER_TOO_SMALL InquiryDataSize not big enough + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_INFO_INQUIRY)( + IN EFI_DISK_INFO_PROTOCOL *This, + IN OUT VOID *InquiryData, + IN OUT UINT32 *InquiryDataSize + ); + +/** + Provides identify information for the controller type. + + This function is used by the IDE bus driver to get identify data. Data format + of Identify data is defined by the Interface GUID. + + @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL + instance. + @param[in,out] IdentifyData Pointer to a buffer for the identify data. + @param[in,out] IdentifyDataSize Pointer to the value for the identify data + size. + + @retval EFI_SUCCESS The command was accepted without any errors. + @retval EFI_NOT_FOUND Device does not support this data class + @retval EFI_DEVICE_ERROR Error reading IdentifyData from device + @retval EFI_BUFFER_TOO_SMALL IdentifyDataSize not big enough + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_INFO_IDENTIFY)( + IN EFI_DISK_INFO_PROTOCOL *This, + IN OUT VOID *IdentifyData, + IN OUT UINT32 *IdentifyDataSize + ); + +/** + Provides sense data information for the controller type. + + This function is used by the IDE bus driver to get sense data. + Data format of Sense data is defined by the Interface GUID. + + @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance. + @param[in,out] SenseData Pointer to the SenseData. + @param[in,out] SenseDataSize Size of SenseData in bytes. + @param[out] SenseDataNumber Pointer to the value for the sense data size. + + @retval EFI_SUCCESS The command was accepted without any errors. + @retval EFI_NOT_FOUND Device does not support this data class. + @retval EFI_DEVICE_ERROR Error reading SenseData from device. + @retval EFI_BUFFER_TOO_SMALL SenseDataSize not big enough. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_INFO_SENSE_DATA)( + IN EFI_DISK_INFO_PROTOCOL *This, + IN OUT VOID *SenseData, + IN OUT UINT32 *SenseDataSize, + OUT UINT8 *SenseDataNumber + ); + +/** + This function is used by the IDE bus driver to get controller information. + + @param[in] This Pointer to the EFI_DISK_INFO_PROTOCOL instance. + @param[out] IdeChannel Pointer to the Ide Channel number. Primary or secondary. + @param[out] IdeDevice Pointer to the Ide Device number. Master or slave. + + @retval EFI_SUCCESS IdeChannel and IdeDevice are valid. + @retval EFI_UNSUPPORTED This is not an IDE device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_INFO_WHICH_IDE)( + IN EFI_DISK_INFO_PROTOCOL *This, + OUT UINT32 *IdeChannel, + OUT UINT32 *IdeDevice + ); + +/// +/// The EFI_DISK_INFO_PROTOCOL provides controller specific information. +/// +struct _EFI_DISK_INFO_PROTOCOL { + /// + /// A GUID that defines the format of buffers for the other member functions + /// of this protocol. + /// + EFI_GUID Interface; + /// + /// Return the results of the Inquiry command to a drive in InquiryData. Data + /// format of Inquiry data is defined by the Interface GUID. + /// + EFI_DISK_INFO_INQUIRY Inquiry; + /// + /// Return the results of the Identify command to a drive in IdentifyData. Data + /// format of Identify data is defined by the Interface GUID. + /// + EFI_DISK_INFO_IDENTIFY Identify; + /// + /// Return the results of the Request Sense command to a drive in SenseData. Data + /// format of Sense data is defined by the Interface GUID. + /// + EFI_DISK_INFO_SENSE_DATA SenseData; + /// + /// Specific controller. + /// + EFI_DISK_INFO_WHICH_IDE WhichIde; +}; + +extern EFI_GUID gEfiDiskInfoProtocolGuid; + +extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid; +extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid; +extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid; +extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid; +extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid; +extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid; +extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo.h new file mode 100644 index 0000000000..d6e6a47b31 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo.h @@ -0,0 +1,111 @@ +/** @file + Disk IO protocol as defined in the UEFI 2.0 specification. + + The Disk IO protocol is used to convert block oriented devices into byte + oriented devices. The Disk IO protocol is intended to layer on top of the + Block IO protocol. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DISK_IO_H__ +#define __DISK_IO_H__ + +#define EFI_DISK_IO_PROTOCOL_GUID \ + { \ + 0xce345171, 0xba0b, 0x11d2, {0x8e, 0x4f, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define DISK_IO_PROTOCOL EFI_DISK_IO_PROTOCOL_GUID + +typedef struct _EFI_DISK_IO_PROTOCOL EFI_DISK_IO_PROTOCOL; + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_DISK_IO_PROTOCOL EFI_DISK_IO; + +/** + Read BufferSize bytes from Offset into Buffer. + + @param This Protocol instance pointer. + @param MediaId Id of the media, changes every time the media is replaced. + @param Offset The starting byte offset to read from + @param BufferSize Size of Buffer + @param Buffer Buffer containing read data + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while performing the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_INVALID_PARAMETER The read request contains device addresses that are not + valid for the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_READ)( + IN EFI_DISK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Offset, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Writes a specified number of bytes to a device. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to be written. + @param Offset The starting byte offset on the logical block I/O device to write. + @param BufferSize The size in bytes of Buffer. The number of bytes to write to the device. + @param Buffer A pointer to the buffer containing the data to be written. + + @retval EFI_SUCCESS The data was written correctly to the device. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_INVALID_PARAMETER The write request contains device addresses that are not + valid for the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_WRITE)( + IN EFI_DISK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Offset, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +#define EFI_DISK_IO_PROTOCOL_REVISION 0x00010000 + +/// +/// Revision defined in EFI1.1 +/// +#define EFI_DISK_IO_INTERFACE_REVISION EFI_DISK_IO_PROTOCOL_REVISION + +/// +/// This protocol is used to abstract Block I/O interfaces. +/// +struct _EFI_DISK_IO_PROTOCOL { + /// + /// The revision to which the disk I/O interface adheres. All future + /// revisions must be backwards compatible. If a future version is not + /// backwards compatible, it is not the same GUID. + /// + UINT64 Revision; + EFI_DISK_READ ReadDisk; + EFI_DISK_WRITE WriteDisk; +}; + +extern EFI_GUID gEfiDiskIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo2.h new file mode 100644 index 0000000000..b3dfb24be3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DiskIo2.h @@ -0,0 +1,166 @@ +/** @file + Disk I/O 2 protocol as defined in the UEFI 2.4 specification. + + The Disk I/O 2 protocol defines an extension to the Disk I/O protocol to enable + non-blocking / asynchronous byte-oriented disk operation. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DISK_IO2_H__ +#define __DISK_IO2_H__ + +#define EFI_DISK_IO2_PROTOCOL_GUID \ + { \ + 0x151c8eae, 0x7f2c, 0x472c, 0x9e, 0x54, 0x98, 0x28, 0x19, 0x4f, 0x6a, 0x88 \ + } + +typedef struct _EFI_DISK_IO2_PROTOCOL EFI_DISK_IO2_PROTOCOL; + +/** + The struct of Disk IO2 Token. +**/ +typedef struct { + // + // If Event is NULL, then blocking I/O is performed. + // If Event is not NULL and non-blocking I/O is supported, then non-blocking I/O is performed, + // and Event will be signaled when the I/O request is completed. + // The caller must be prepared to handle the case where the callback associated with Event occurs + // before the original asynchronous I/O request call returns. + // + EFI_EVENT Event; + + // + // Defines whether or not the signaled event encountered an error. + // + EFI_STATUS TransactionStatus; +} EFI_DISK_IO2_TOKEN; + +/** + Terminate outstanding asynchronous requests to a device. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding requests were successfully terminated. + @retval EFI_DEVICE_ERROR The device reported an error while performing the cancel + operation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_CANCEL_EX) ( + IN EFI_DISK_IO2_PROTOCOL *This + ); + +/** + Reads a specified number of bytes from a device. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to be read. + @param Offset The starting byte offset on the logical block I/O device to read from. + @param Token A pointer to the token associated with the transaction. + If this field is NULL, synchronous/blocking IO is performed. + @param BufferSize The size in bytes of Buffer. The number of bytes to read from the device. + @param Buffer A pointer to the destination buffer for the data. + The caller is responsible either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read correctly from the device. + If Event is not NULL (asynchronous I/O): The request was successfully queued for processing. + Event will be signaled upon completion. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_NO_MEDIA There is no medium in the device. + @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium. + @retval EFI_INVALID_PARAMETER The read request contains device addresses that are not valid for the device. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_READ_EX) ( + IN EFI_DISK_IO2_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Offset, + IN OUT EFI_DISK_IO2_TOKEN *Token, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Writes a specified number of bytes to a device. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to be written. + @param Offset The starting byte offset on the logical block I/O device to write to. + @param Token A pointer to the token associated with the transaction. + If this field is NULL, synchronous/blocking IO is performed. + @param BufferSize The size in bytes of Buffer. The number of bytes to write to the device. + @param Buffer A pointer to the buffer containing the data to be written. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was written correctly to the device. + If Event is not NULL (asynchronous I/O): The request was successfully queued for processing. + Event will be signaled upon completion. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write operation. + @retval EFI_NO_MEDIA There is no medium in the device. + @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium. + @retval EFI_INVALID_PARAMETER The write request contains device addresses that are not valid for the device. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_WRITE_EX) ( + IN EFI_DISK_IO2_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Offset, + IN OUT EFI_DISK_IO2_TOKEN *Token, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flushes all modified data to the physical device. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to be written. + @param Token A pointer to the token associated with the transaction. + If this field is NULL, synchronous/blocking IO is performed. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was flushed successfully to the device. + If Event is not NULL (asynchronous I/O): The request was successfully queued for processing. + Event will be signaled upon completion. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write operation. + @retval EFI_NO_MEDIA There is no medium in the device. + @retval EFI_MEDIA_CHNAGED The MediaId is not for the current medium. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISK_FLUSH_EX) ( + IN EFI_DISK_IO2_PROTOCOL *This, + IN OUT EFI_DISK_IO2_TOKEN *Token + ); + +#define EFI_DISK_IO2_PROTOCOL_REVISION 0x00020000 + +/// +/// This protocol is used to abstract Block I/O interfaces. +/// +struct _EFI_DISK_IO2_PROTOCOL { + /// + /// The revision to which the disk I/O interface adheres. All future + /// revisions must be backwards compatible. If a future version is not + /// backwards compatible, it is not the same GUID. + /// + UINT64 Revision; + EFI_DISK_CANCEL_EX Cancel; + EFI_DISK_READ_EX ReadDiskEx; + EFI_DISK_WRITE_EX WriteDiskEx; + EFI_DISK_FLUSH_EX FlushDiskEx; +}; + +extern EFI_GUID gEfiDiskIo2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns4.h new file mode 100644 index 0000000000..d02713f706 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns4.h @@ -0,0 +1,537 @@ +/** @file + This file defines the EFI Domain Name Service Binding Protocol interface. It is split + into the following two main sections: + DNSv4 Service Binding Protocol (DNSv4SB) + DNSv4 Protocol (DNSv4) + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_DNS4_PROTOCOL_H__ +#define __EFI_DNS4_PROTOCOL_H__ + +#define EFI_DNS4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xb625b186, 0xe063, 0x44f7, {0x89, 0x5, 0x6a, 0x74, 0xdc, 0x6f, 0x52, 0xb4 } \ + } + +#define EFI_DNS4_PROTOCOL_GUID \ + { \ + 0xae3d28cc, 0xe05b, 0x4fa1, {0xa0, 0x11, 0x7e, 0xb5, 0x5a, 0x3f, 0x14, 0x1 } \ + } + +typedef struct _EFI_DNS4_PROTOCOL EFI_DNS4_PROTOCOL; + +/// +/// EFI_DNS4_CONFIG_DATA +/// +typedef struct { + /// + /// Count of the DNS servers. When used with GetModeData(), + /// this field is the count of originally configured servers when + /// Configure() was called for this instance. When used with + /// Configure() this is the count of caller-supplied servers. If the + /// DnsServerListCount is zero, the DNS server configuration + /// will be retrieved from DHCP server automatically. + /// + UINTN DnsServerListCount; + /// + /// Pointer to DNS server list containing DnsServerListCount entries or NULL + /// if DnsServerListCountis 0. For Configure(), this will be NULL when there are + /// no caller supplied server addresses, and, the DNS instance will retrieve + /// DNS server from DHCP Server. The provided DNS server list is + /// recommended to be filled up in the sequence of preference. When + /// used with GetModeData(), the buffer containing the list will + /// be allocated by the driver implementing this protocol and must be + /// freed by the caller. When used with Configure(), the buffer + /// containing the list will be allocated and released by the caller. + /// + EFI_IPv4_ADDRESS *DnsServerList; + /// + /// Set to TRUE to use the default IP address/subnet mask and default routing table. + /// + BOOLEAN UseDefaultSetting; + /// + /// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS + /// query will not lookup local DNS cache. + /// + BOOLEAN EnableDnsCache; + /// + /// Use the protocol number defined in "Links to UEFI-Related + /// Documents"(http://uefi.org/uefi) under the heading "IANA + /// Protocol Numbers". Only TCP or UDP are supported, and other + /// protocol values are invalid. An implementation can choose to + /// support only UDP, or both TCP and UDP. + /// + UINT8 Protocol; + /// + /// If UseDefaultSetting is FALSE indicates the station address to use. + /// + EFI_IPv4_ADDRESS StationIp; + /// + /// If UseDefaultSetting is FALSE indicates the subnet mask to use. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// Local port number. Set to zero to use the automatically assigned port number. + /// + UINT16 LocalPort; + /// + /// Retry number if no response received after RetryInterval. + /// + UINT32 RetryCount; + /// + /// Minimum interval of retry is 2 second. If the retry interval is less than 2 + /// seconds, then use the 2 seconds. + /// + UINT32 RetryInterval; +} EFI_DNS4_CONFIG_DATA; + + +/// +/// EFI_DNS4_CACHE_ENTRY +/// +typedef struct { + /// + /// Host name. + /// + CHAR16 *HostName; + /// + /// IP address of this host. + /// + EFI_IPv4_ADDRESS *IpAddress; + /// + /// Time in second unit that this entry will remain in DNS cache. A value of zero + /// means that this entry is permanent. A nonzero value will override the existing + /// one if this entry to be added is dynamic entry. Implementations may set its + /// default timeout value for the dynamically created DNS cache entry after one DNS + /// resolve succeeds. + /// + UINT32 Timeout; +} EFI_DNS4_CACHE_ENTRY; + +/// +/// EFI_DNS4_MODE_DATA +/// +typedef struct { + /// + /// The configuration data of this instance. + /// + EFI_DNS4_CONFIG_DATA DnsConfigData; + /// + /// Number of configured DNS server. Each DNS instance has its own DNS server + /// configuration. + /// + UINT32 DnsServerCount; + /// + /// Pointer to common list of addresses of all configured DNS server + /// used by EFI_DNS4_PROTOCOL instances. List will include + /// DNS servers configured by this or any other EFI_DNS4_PROTOCOL instance. + /// The storage for this list is allocated by the driver publishing this + /// protocol, and must be freed by the caller. + /// + EFI_IPv4_ADDRESS *DnsServerList; + /// + /// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances. + /// + UINT32 DnsCacheCount; + /// + /// Pointer to a buffer containing DnsCacheCount DNS Cache + /// entry structures. The storage for this list is allocated by the driver + /// publishing this protocol and must be freed by caller. + /// + EFI_DNS4_CACHE_ENTRY *DnsCacheList; +} EFI_DNS4_MODE_DATA; + +/// +/// DNS_HOST_TO_ADDR_DATA +/// +typedef struct { + /// + /// Number of the returned IP addresses. + /// + UINT32 IpCount; + /// + /// Pointer to the all the returned IP addresses. + /// + EFI_IPv4_ADDRESS *IpList; +} DNS_HOST_TO_ADDR_DATA; + +/// +/// DNS_ADDR_TO_HOST_DATA +/// +typedef struct { + /// + /// Pointer to the primary name for this host address. It's the caller's + /// responsibility to free the response memory. + /// + CHAR16 *HostName; +} DNS_ADDR_TO_HOST_DATA; + +/// +/// DNS_RESOURCE_RECORD +/// +typedef struct { + /// + /// The Owner name. + /// + CHAR8 *QName; + /// + /// The Type Code of this RR. + /// + UINT16 QType; + /// + /// The CLASS code of this RR. + /// + UINT16 QClass; + /// + /// 32 bit integer which specify the time interval that the resource record may be + /// cached before the source of the information should again be consulted. Zero means + /// this RR can not be cached. + /// + UINT32 TTL; + /// + /// 16 big integer which specify the length of RData. + /// + UINT16 DataLength; + /// + /// A string of octets that describe the resource, the format of this information + /// varies according to QType and QClass difference. + /// + CHAR8 *RData; +} DNS_RESOURCE_RECORD; + +/// +/// DNS_GENERAL_LOOKUP_DATA +/// +typedef struct { + /// + /// Number of returned matching RRs. + /// + UINTN RRCount; + /// + /// Pointer to the all the returned matching RRs. It's caller responsibility to free + /// the allocated memory to hold the returned RRs. + /// + DNS_RESOURCE_RECORD *RRList; +} DNS_GENERAL_LOOKUP_DATA; + +/// +/// EFI_DNS4_COMPLETION_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI DNS + /// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: The host name to address translation completed successfully. + /// EFI_NOT_FOUND: No matching Resource Record (RR) is found. + /// EFI_TIMEOUT: No DNS server reachable, or RetryCount was exhausted without + /// response from all specified DNS servers. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_STATUS Status; + /// + /// Retry number if no response received after RetryInterval. If zero, use the + /// parameter configured through Dns.Configure() interface. + /// + UINT32 RetryCount; + /// + /// Minimum interval of retry is 2 second. If the retry interval is less than 2 + /// seconds, then use the 2 seconds. If zero, use the parameter configured through + /// Dns.Configure() interface. + UINT32 RetryInterval; + /// + /// DNSv4 completion token data + /// + union { + /// + /// When the Token is used for host name to address translation, H2AData is a pointer + /// to the DNS_HOST_TO_ADDR_DATA. + /// + DNS_HOST_TO_ADDR_DATA *H2AData; + /// + /// When the Token is used for host address to host name translation, A2HData is a + /// pointer to the DNS_ADDR_TO_HOST_DATA. + /// + DNS_ADDR_TO_HOST_DATA *A2HData; + /// + /// When the Token is used for a general lookup function, GLookupDATA is a pointer to + /// the DNS_GENERAL_LOOKUP_DATA. + /// + DNS_GENERAL_LOOKUP_DATA *GLookupData; + } RspData; +} EFI_DNS4_COMPLETION_TOKEN; + +/** + Retrieve mode data of this DNS instance. + + This function is used to retrieve DNS mode data for this DNS instance. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[out] DnsModeData Point to the mode data. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED When DnsConfigData is queried, no configuration data + is available because this instance has not been + configured. + @retval EFI_INVALID_PARAMETER This is NULL or DnsModeData is NULL. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_GET_MODE_DATA) ( + IN EFI_DNS4_PROTOCOL *This, + OUT EFI_DNS4_MODE_DATA *DnsModeData + ); + +/** + Configure this DNS instance. + + This function is used to configure DNS mode data for this DNS instance. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] DnsConfigData Point to the Configuration data. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED The designated protocol is not supported. + @retval EFI_INVALID_PARAMETER This is NULL. + The StationIp address provided in DnsConfigData is not a + valid unicast. + DnsServerList is NULL while DnsServerListCount + is not ZERO. + DnsServerListCount is ZERO while DnsServerList + is not NULL + @retval EFI_OUT_OF_RESOURCES The DNS instance data or required space could not be + allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The + EFI DNSv4 Protocol instance is not configured. + @retval EFI_ALREADY_STARTED Second call to Configure() with DnsConfigData. To + reconfigure the instance the caller must call Configure() + with NULL first to return driver to unconfigured state. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_CONFIGURE) ( + IN EFI_DNS4_PROTOCOL *This, + IN EFI_DNS4_CONFIG_DATA *DnsConfigData + ); + +/** + Host name to host address translation. + + The HostNameToIp () function is used to translate the host name to host IP address. A + type A query is used to get the one or more IP addresses for this host. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] HostName Host name. + @param[in] Token Point to the completion token to translate host name + to host address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + HostName is NULL. HostName string is unsupported format. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_NOT_STARTED This instance has not been started. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_HOST_NAME_TO_IP) ( + IN EFI_DNS4_PROTOCOL *This, + IN CHAR16 *HostName, + IN EFI_DNS4_COMPLETION_TOKEN *Token + ); + +/** + IPv4 address to host name translation also known as Reverse DNS lookup. + + The IpToHostName() function is used to translate the host address to host name. A type PTR + query is used to get the primary name of the host. Support of this function is optional. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] IpAddress Ip Address. + @param[in] Token Point to the completion token to translate host + address to host name. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + IpAddress is not valid IP address . + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_ALREADY_STARTED This Token is being used in another DNS session. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_IP_TO_HOST_NAME) ( + IN EFI_DNS4_PROTOCOL *This, + IN EFI_IPv4_ADDRESS IpAddress, + IN EFI_DNS4_COMPLETION_TOKEN *Token + ); + +/** + Retrieve arbitrary information from the DNS server. + + This GeneralLookup() function retrieves arbitrary information from the DNS. The caller + supplies a QNAME, QTYPE, and QCLASS, and all of the matching RRs are returned. All + RR content (e.g., TTL) was returned. The caller need parse the returned RR to get + required information. The function is optional. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] QName Pointer to Query Name. + @param[in] QType Query Type. + @param[in] QClass Query Name. + @param[in] Token Point to the completion token to retrieve arbitrary + information. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED This function is not supported. Or the requested + QType is not supported + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + QName is NULL. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_ALREADY_STARTED This Token is being used in another DNS session. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_GENERAL_LOOKUP) ( + IN EFI_DNS4_PROTOCOL *This, + IN CHAR8 *QName, + IN UINT16 QType, + IN UINT16 QClass, + IN EFI_DNS4_COMPLETION_TOKEN *Token + ); + +/** + This function is to update the DNS Cache. + + The UpdateDnsCache() function is used to add/delete/modify DNS cache entry. DNS cache + can be normally dynamically updated after the DNS resolve succeeds. This function + provided capability to manually add/delete/modify the DNS cache. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] DeleteFlag If FALSE, this function is to add one entry to the + DNS Cahce. If TRUE, this function will delete + matching DNS Cache entry. + @param[in] Override If TRUE, the maching DNS cache entry will be + overwritten with the supplied parameter. If FALSE, + EFI_ACCESS_DENIED will be returned if the entry to + be added is already existed. + @param[in] DnsCacheEntry Pointer to DNS Cache entry. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + DnsCacheEntry.HostName is NULL. + DnsCacheEntry.IpAddress is NULL. + DnsCacheEntry.Timeout is zero. + @retval EFI_ACCESS_DENIED The DNS cache entry already exists and Override is + not TRUE. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_UPDATE_DNS_CACHE) ( + IN EFI_DNS4_PROTOCOL *This, + IN BOOLEAN DeleteFlag, + IN BOOLEAN Override, + IN EFI_DNS4_CACHE_ENTRY DnsCacheEntry + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase the + rate that data packets are moved between the communications device and the transmit + and receive queues. + In some systems, the periodic timer event in the managed network driver may not poll + the underlying communications device fast enough to transmit and/or receive all data + packets without missing incoming packets or dropping outgoing packets. Drivers and + applications that are experiencing packet loss should try calling the Poll() + function more often. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI DNS Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive + queue. Consider increasing the polling rate. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_POLL) ( + IN EFI_DNS4_PROTOCOL *This + ); + +/** + Abort an asynchronous DNS operation, including translation between IP and Host, and + general look up behavior. + + The Cancel() function is used to abort a pending resolution request. After calling + this function, Token.Status will be set to EFI_ABORTED and then Token.Event will be + signaled. If the token is not in one of the queues, which usually means that the + asynchronous operation has completed, this function will not signal the token and + EFI_NOT_FOUND is returned. + + @param[in] This Pointer to EFI_DNS4_PROTOCOL instance. + @param[in] Token Pointer to a token that has been issued by + EFI_DNS4_PROTOCOL.HostNameToIp (), + EFI_DNS4_PROTOCOL.IpToHostName() or + EFI_DNS4_PROTOCOL.GeneralLookup(). + If NULL, all pending tokens are aborted. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI DNS4 Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_FOUND When Token is not NULL, and the asynchronous DNS + operation was not found in the transmit queue. It + was either completed or was not issued by + HostNameToIp(), IpToHostName() or GeneralLookup(). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS4_CANCEL) ( + IN EFI_DNS4_PROTOCOL *This, + IN EFI_DNS4_COMPLETION_TOKEN *Token + ); + +/// +/// The EFI_DNS4_Protocol provides the function to get the host name and address +/// mapping, also provides pass through interface to retrieve arbitrary information +/// from DNS. +/// +struct _EFI_DNS4_PROTOCOL { + EFI_DNS4_GET_MODE_DATA GetModeData; + EFI_DNS4_CONFIGURE Configure; + EFI_DNS4_HOST_NAME_TO_IP HostNameToIp; + EFI_DNS4_IP_TO_HOST_NAME IpToHostName; + EFI_DNS4_GENERAL_LOOKUP GeneralLookUp; + EFI_DNS4_UPDATE_DNS_CACHE UpdateDnsCache; + EFI_DNS4_POLL Poll; + EFI_DNS4_CANCEL Cancel; +}; + +extern EFI_GUID gEfiDns4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiDns4ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns6.h new file mode 100644 index 0000000000..9839b822c1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Dns6.h @@ -0,0 +1,533 @@ +/** @file + This file defines the EFI DNSv6 (Domain Name Service version 6) Protocol. It is split + into the following two main sections: + DNSv6 Service Binding Protocol (DNSv6SB) + DNSv6 Protocol (DNSv6) + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_DNS6_PROTOCOL_H__ +#define __EFI_DNS6_PROTOCOL_H__ + +#define EFI_DNS6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x7f1647c8, 0xb76e, 0x44b2, {0xa5, 0x65, 0xf7, 0xf, 0xf1, 0x9c, 0xd1, 0x9e } \ + } + +#define EFI_DNS6_PROTOCOL_GUID \ + { \ + 0xca37bc1f, 0xa327, 0x4ae9, {0x82, 0x8a, 0x8c, 0x40, 0xd8, 0x50, 0x6a, 0x17 } \ + } + +typedef struct _EFI_DNS6_PROTOCOL EFI_DNS6_PROTOCOL; + +/// +/// EFI_DNS6_CONFIG_DATA +/// +typedef struct { + /// + /// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS query + /// will not lookup local DNS cache. + /// + BOOLEAN EnableDnsCache; + /// + /// Use the protocol number defined in + /// http://www.iana.org/assignments/protocol-numbers. Beside TCP/UDP, Other protocol + /// is invalid value. An implementation can choose to support UDP, or both TCP and UDP. + /// + UINT8 Protocol; + /// + /// The local IP address to use. Set to zero to let the underlying IPv6 + /// driver choose a source address. If not zero it must be one of the + /// configured IP addresses in the underlying IPv6 driver. + /// + EFI_IPv6_ADDRESS StationIp; + /// + /// Local port number. Set to zero to use the automatically assigned port number. + /// + UINT16 LocalPort; + /// + /// Count of the DNS servers. When used with GetModeData(), + /// this field is the count of originally configured servers when + /// Configure() was called for this instance. When used with + /// Configure() this is the count of caller-supplied servers. If the + /// DnsServerListCount is zero, the DNS server configuration + /// will be retrieved from DHCP server automatically. + /// + UINT32 DnsServerCount; + /// + /// Pointer to DNS server list containing DnsServerListCount + /// entries or NULL if DnsServerListCount is 0. For Configure(), + /// this will be NULL when there are no caller supplied server addresses + /// and the DNS instance will retrieve DNS server from DHCP Server. + /// The provided DNS server list is recommended to be filled up in the sequence + /// of preference. When used with GetModeData(), the buffer containing the list + /// will be allocated by the driver implementing this protocol and must be + /// freed by the caller. When used with Configure(), the buffer + /// containing the list will be allocated and released by the caller. + /// + EFI_IPv6_ADDRESS *DnsServerList; + /// + /// Retry number if no response received after RetryInterval. + /// + UINT32 RetryCount; + /// + /// Minimum interval of retry is 2 second. If the retry interval is less than 2 + /// seconds, then use the 2 seconds. + UINT32 RetryInterval; +} EFI_DNS6_CONFIG_DATA; + +/// +/// EFI_DNS6_CACHE_ENTRY +/// +typedef struct { + /// + /// Host name. This should be interpreted as Unicode characters. + /// + CHAR16 *HostName; + /// + /// IP address of this host. + /// + EFI_IPv6_ADDRESS *IpAddress; + /// + /// Time in second unit that this entry will remain in DNS cache. A value of zero means + /// that this entry is permanent. A nonzero value will override the existing one if + /// this entry to be added is dynamic entry. Implementations may set its default + /// timeout value for the dynamically created DNS cache entry after one DNS resolve + /// succeeds. + UINT32 Timeout; +} EFI_DNS6_CACHE_ENTRY; + +/// +/// EFI_DNS6_MODE_DATA +/// +typedef struct { + /// + /// The configuration data of this instance. + /// + EFI_DNS6_CONFIG_DATA DnsConfigData; + /// + /// Number of configured DNS6 servers. + /// + UINT32 DnsServerCount; + /// + /// Pointer to common list of addresses of all configured DNS server used by EFI_DNS6_PROTOCOL + /// instances. List will include DNS servers configured by this or any other EFI_DNS6_PROTOCOL + /// instance. The storage for this list is allocated by the driver publishing this protocol, + /// and must be freed by the caller. + /// + EFI_IPv6_ADDRESS *DnsServerList; + /// + /// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances. + /// + UINT32 DnsCacheCount; + /// + /// Pointer to a buffer containing DnsCacheCount DNS Cache + /// entry structures. The storage for thislist is allocated by the driver + /// publishing this protocol and must be freed by caller. + /// + EFI_DNS6_CACHE_ENTRY *DnsCacheList; +} EFI_DNS6_MODE_DATA; + +/// +/// DNS6_HOST_TO_ADDR_DATA +/// +typedef struct { + /// + /// Number of the returned IP address. + /// + UINT32 IpCount; + /// + /// Pointer to the all the returned IP address. + /// + EFI_IPv6_ADDRESS *IpList; +} DNS6_HOST_TO_ADDR_DATA; + +/// +/// DNS6_ADDR_TO_HOST_DATA +/// +typedef struct { + /// + /// Pointer to the primary name for this host address. It's the caller's + /// responsibility to free the response memory. + /// + CHAR16 *HostName; +} DNS6_ADDR_TO_HOST_DATA; + +/// +/// DNS6_RESOURCE_RECORD +/// +typedef struct { + /// + /// The Owner name. + /// + CHAR8 *QName; + /// + /// The Type Code of this RR. + /// + UINT16 QType; + /// + /// The CLASS code of this RR. + /// + UINT16 QClass; + /// + /// 32 bit integer which specify the time interval that the resource record may be + /// cached before the source of the information should again be consulted. Zero means + /// this RR cannot be cached. + /// + UINT32 TTL; + /// + /// 16 big integer which specify the length of RData. + /// + UINT16 DataLength; + /// + /// A string of octets that describe the resource, the format of this information + /// varies according to QType and QClass difference. + /// + CHAR8 *RData; +} DNS6_RESOURCE_RECORD; + +/// +/// DNS6_GENERAL_LOOKUP_DATA +/// +typedef struct { + /// + /// Number of returned matching RRs. + /// + UINTN RRCount; + /// + /// Pointer to the all the returned matching RRs. It's caller responsibility to free + /// the allocated memory to hold the returned RRs. + /// + DNS6_RESOURCE_RECORD *RRList; +} DNS6_GENERAL_LOOKUP_DATA; + +/// +/// EFI_DNS6_COMPLETION_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI DNSv6 + /// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: The host name to address translation completed successfully. + /// EFI_NOT_FOUND: No matching Resource Record (RR) is found. + /// EFI_TIMEOUT: No DNS server reachable, or RetryCount was exhausted without + /// response from all specified DNS servers. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_STATUS Status; + /// + /// The parameter configured through DNSv6.Configure() interface. Retry number if no + /// response received after RetryInterval. + /// + UINT32 RetryCount; + /// + /// The parameter configured through DNSv6.Configure() interface. Minimum interval of + /// retry is 2 seconds. If the retry interval is less than 2 seconds, then use the 2 + /// seconds. + /// + UINT32 RetryInterval; + /// + /// DNSv6 completion token data + /// + union { + /// + /// When the Token is used for host name to address translation, H2AData is a pointer + /// to the DNS6_HOST_TO_ADDR_DATA. + /// + DNS6_HOST_TO_ADDR_DATA *H2AData; + /// + /// When the Token is used for host address to host name translation, A2HData is a + /// pointer to the DNS6_ADDR_TO_HOST_DATA. + /// + DNS6_ADDR_TO_HOST_DATA *A2HData; + /// + /// When the Token is used for a general lookup function, GLookupDATA is a pointer to + /// the DNS6_GENERAL_LOOKUP_DATA. + /// + DNS6_GENERAL_LOOKUP_DATA *GLookupData; + } RspData; +} EFI_DNS6_COMPLETION_TOKEN; + +/** + Retrieve mode data of this DNS instance. + + This function is used to retrieve DNS mode data for this DNS instance. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[out] DnsModeData Pointer to the caller-allocated storage for the + EFI_DNS6_MODE_DATA data. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED When DnsConfigData is queried, no configuration data + is available because this instance has not been + configured. + @retval EFI_INVALID_PARAMETER This is NULL or DnsModeData is NULL. + @retval EFI_OUT_OF_RESOURCE Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_DNS6_GET_MODE_DATA)( + IN EFI_DNS6_PROTOCOL *This, + OUT EFI_DNS6_MODE_DATA *DnsModeData + ); + +/** + Configure this DNS instance. + + The Configure() function is used to set and change the configuration data for this + EFI DNSv6 Protocol driver instance. Reset the DNS instance if DnsConfigData is NULL. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] DnsConfigData Pointer to the configuration data structure. All associated + storage to be allocated and released by caller. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + The StationIp address provided in DnsConfigData is not zero and not a valid unicast. + DnsServerList is NULL while DnsServerList Count is not ZERO. + DnsServerList Count is ZERO while DnsServerList is not NULL. + @retval EFI_OUT_OF_RESOURCES The DNS instance data or required space could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The + EFI DNSv6 Protocol instance is not configured. + @retval EFI_UNSUPPORTED The designated protocol is not supported. + @retval EFI_ALREADY_STARTED Second call to Configure() with DnsConfigData. To + reconfigure the instance the caller must call Configure() with + NULL first to return driver to unconfigured state. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_DNS6_CONFIGURE)( + IN EFI_DNS6_PROTOCOL *This, + IN EFI_DNS6_CONFIG_DATA *DnsConfigData + ); + +/** + Host name to host address translation. + + The HostNameToIp () function is used to translate the host name to host IP address. A + type AAAA query is used to get the one or more IPv6 addresses for this host. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] HostName Host name. + @param[in] Token Point to the completion token to translate host name + to host address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + HostName is NULL or buffer contained unsupported characters. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_ALREADY_STARTED This Token is being used in another DNS session. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_HOST_NAME_TO_IP) ( + IN EFI_DNS6_PROTOCOL *This, + IN CHAR16 *HostName, + IN EFI_DNS6_COMPLETION_TOKEN *Token + ); + +/** + Host address to host name translation. + + The IpToHostName () function is used to translate the host address to host name. A + type PTR query is used to get the primary name of the host. Implementation can choose + to support this function or not. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] IpAddress Ip Address. + @param[in] Token Point to the completion token to translate host + address to host name. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + IpAddress is not valid IP address. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_IP_TO_HOST_NAME) ( + IN EFI_DNS6_PROTOCOL *This, + IN EFI_IPv6_ADDRESS IpAddress, + IN EFI_DNS6_COMPLETION_TOKEN *Token + ); + +/** + This function provides capability to retrieve arbitrary information from the DNS + server. + + This GeneralLookup() function retrieves arbitrary information from the DNS. The caller + supplies a QNAME, QTYPE, and QCLASS, and all of the matching RRs are returned. All + RR content (e.g., TTL) was returned. The caller need parse the returned RR to get + required information. The function is optional. Implementation can choose to support + it or not. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] QName Pointer to Query Name. + @param[in] QType Query Type. + @param[in] QClass Query Name. + @param[in] Token Point to the completion token to retrieve arbitrary + information. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED This function is not supported. Or the requested + QType is not supported + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token.Event is NULL. + QName is NULL. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_OUT_OF_RESOURCES Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_GENERAL_LOOKUP) ( + IN EFI_DNS6_PROTOCOL *This, + IN CHAR8 *QName, + IN UINT16 QType, + IN UINT16 QClass, + IN EFI_DNS6_COMPLETION_TOKEN *Token + ); + +/** + This function is to update the DNS Cache. + + The UpdateDnsCache() function is used to add/delete/modify DNS cache entry. DNS cache + can be normally dynamically updated after the DNS resolve succeeds. This function + provided capability to manually add/delete/modify the DNS cache. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] DeleteFlag If FALSE, this function is to add one entry to the + DNS Cahce. If TRUE, this function will delete + matching DNS Cache entry. + @param[in] Override If TRUE, the maching DNS cache entry will be + overwritten with the supplied parameter. If FALSE, + EFI_ACCESS_DENIED will be returned if the entry to + be added is already existed. + @param[in] DnsCacheEntry Pointer to DNS Cache entry. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + DnsCacheEntry.HostName is NULL. + DnsCacheEntry.IpAddress is NULL. + DnsCacheEntry.Timeout is zero. + @retval EFI_ACCESS_DENIED The DNS cache entry already exists and Override is + not TRUE. + @retval EFI_OUT_OF_RESOURCE Failed to allocate needed resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_UPDATE_DNS_CACHE) ( + IN EFI_DNS6_PROTOCOL *This, + IN BOOLEAN DeleteFlag, + IN BOOLEAN Override, + IN EFI_DNS6_CACHE_ENTRY DnsCacheEntry + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase the + rate that data packets are moved between the communications device and the transmit + and receive queues. + + In some systems, the periodic timer event in the managed network driver may not poll + the underlying communications device fast enough to transmit and/or receive all data + packets without missing incoming packets or dropping outgoing packets. Drivers and + applications that are experiencing packet loss should try calling the Poll() + function more often. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI DNS Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NO_MAPPING There is no source address is available for use. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive + queue. Consider increasing the polling rate. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_POLL) ( + IN EFI_DNS6_PROTOCOL *This + ); + +/** + Abort an asynchronous DNS operation, including translation between IP and Host, and + general look up behavior. + + The Cancel() function is used to abort a pending resolution request. After calling + this function, Token.Status will be set to EFI_ABORTED and then Token.Event will be + signaled. If the token is not in one of the queues, which usually means that the + asynchronous operation has completed, this function will not signal the token and + EFI_NOT_FOUND is returned. + + @param[in] This Pointer to EFI_DNS6_PROTOCOL instance. + @param[in] Token Pointer to a token that has been issued by + EFI_DNS6_PROTOCOL.HostNameToIp (), + EFI_DNS6_PROTOCOL.IpToHostName() or + EFI_DNS6_PROTOCOL.GeneralLookup(). + If NULL, all pending tokens are aborted. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI DNS6 Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NO_MAPPING There's no source address is available for use. + @retval EFI_NOT_FOUND When Token is not NULL, and the asynchronous DNS + operation was not found in the transmit queue. It + was either completed or was not issued by + HostNameToIp(), IpToHostName() or GeneralLookup(). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DNS6_CANCEL) ( + IN EFI_DNS6_PROTOCOL *This, + IN EFI_DNS6_COMPLETION_TOKEN *Token + ); + +/// +/// The EFI_DNS6_PROTOCOL provides the function to get the host name and address +/// mapping, also provide pass through interface to retrieve arbitrary information from +/// DNSv6. +/// +struct _EFI_DNS6_PROTOCOL { + EFI_DNS6_GET_MODE_DATA GetModeData; + EFI_DNS6_CONFIGURE Configure; + EFI_DNS6_HOST_NAME_TO_IP HostNameToIp; + EFI_DNS6_IP_TO_HOST_NAME IpToHostName; + EFI_DNS6_GENERAL_LOOKUP GeneralLookUp; + EFI_DNS6_UPDATE_DNS_CACHE UpdateDnsCache; + EFI_DNS6_POLL Poll; + EFI_DNS6_CANCEL Cancel; +}; + +extern EFI_GUID gEfiDns6ServiceBindingProtocolGuid; +extern EFI_GUID gEfiDns6ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverBinding.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverBinding.h new file mode 100644 index 0000000000..fca636f22d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverBinding.h @@ -0,0 +1,195 @@ +/** @file + UEFI DriverBinding Protocol is defined in UEFI specification. + + This protocol is produced by every driver that follows the UEFI Driver Model, + and it is the central component that allows drivers and controllers to be managed. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_BINDING_H__ +#define __EFI_DRIVER_BINDING_H__ + +/// +/// The global ID for the ControllerHandle Driver Protocol. +/// +#define EFI_DRIVER_BINDING_PROTOCOL_GUID \ + { \ + 0x18a031ab, 0xb443, 0x4d1a, {0xa5, 0xc0, 0xc, 0x9, 0x26, 0x1e, 0x9f, 0x71 } \ + } + +typedef struct _EFI_DRIVER_BINDING_PROTOCOL EFI_DRIVER_BINDING_PROTOCOL; + +/** + Tests to see if this driver supports a given controller. If a child device is provided, + it further tests to see if this driver supports creating a handle for the specified child device. + + This function checks to see if the driver specified by This supports the device specified by + ControllerHandle. Drivers will typically use the device path attached to + ControllerHandle and/or the services from the bus I/O abstraction attached to + ControllerHandle to determine if the driver supports ControllerHandle. This function + may be called many times during platform initialization. In order to reduce boot times, the tests + performed by this function must be very small, and take as little time as possible to execute. This + function must not change the state of any hardware devices, and this function must be aware that the + device specified by ControllerHandle may already be managed by the same driver or a + different driver. This function must match its calls to AllocatePages() with FreePages(), + AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol(). + Because ControllerHandle may have been previously started by the same driver, if a protocol is + already in the opened state, then it must not be closed with CloseProtocol(). This is required + to guarantee the state of ControllerHandle is not modified by this function. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle The handle of the controller to test. This handle + must support a protocol interface that supplies + an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This + parameter is ignored by device drivers, and is optional for bus + drivers. For bus drivers, if this parameter is not NULL, then + the bus driver must determine if the bus controller specified + by ControllerHandle and the child controller specified + by RemainingDevicePath are both supported by this + bus driver. + + @retval EFI_SUCCESS The device specified by ControllerHandle and + RemainingDevicePath is supported by the driver specified by This. + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and + RemainingDevicePath is already being managed by the driver + specified by This. + @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and + RemainingDevicePath is already being managed by a different + driver or an application that requires exclusive access. + Currently not implemented. + @retval EFI_UNSUPPORTED The device specified by ControllerHandle and + RemainingDevicePath is not supported by the driver specified by This. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_BINDING_SUPPORTED)( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +/** + Starts a device controller or a bus controller. + + The Start() function is designed to be invoked from the EFI boot service ConnectController(). + As a result, much of the error checking on the parameters to Start() has been moved into this + common boot service. It is legal to call Start() from other locations, + but the following calling restrictions must be followed, or the system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE. + 2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned + EFI_DEVICE_PATH_PROTOCOL. + 3. Prior to calling Start(), the Supported() function for the driver specified by This must + have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle The handle of the controller to start. This handle + must support a protocol interface that supplies + an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a device path. This + parameter is ignored by device drivers, and is optional for bus + drivers. For a bus driver, if this parameter is NULL, then handles + for all the children of Controller are created by this driver. + If this parameter is not NULL and the first Device Path Node is + not the End of Device Path Node, then only the handle for the + child device specified by the first Device Path Node of + RemainingDevicePath is created by this driver. + If the first Device Path Node of RemainingDevicePath is + the End of Device Path Node, no child handle is created by this + driver. + + @retval EFI_SUCCESS The device was started. + @retval EFI_DEVICE_ERROR The device could not be started due to a device error.Currently not implemented. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval Others The driver failded to start the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_BINDING_START)( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +/** + Stops a device controller or a bus controller. + + The Stop() function is designed to be invoked from the EFI boot service DisconnectController(). + As a result, much of the error checking on the parameters to Stop() has been moved + into this common boot service. It is legal to call Stop() from other locations, + but the following calling restrictions must be followed, or the system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this + same driver's Start() function. + 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid + EFI_HANDLE. In addition, all of these handles must have been created in this driver's + Start() function, and the Start() function must have called OpenProtocol() on + ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param[in] ControllerHandle A handle to the device being stopped. The handle must + support a bus specific I/O protocol for the driver + to use to stop the device. + @param[in] NumberOfChildren The number of child device handles in ChildHandleBuffer. + @param[in] ChildHandleBuffer An array of child handles to be freed. May be NULL + if NumberOfChildren is 0. + + @retval EFI_SUCCESS The device was stopped. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_BINDING_STOP)( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +/// +/// This protocol provides the services required to determine if a driver supports a given controller. +/// If a controller is supported, then it also provides routines to start and stop the controller. +/// +struct _EFI_DRIVER_BINDING_PROTOCOL { + EFI_DRIVER_BINDING_SUPPORTED Supported; + EFI_DRIVER_BINDING_START Start; + EFI_DRIVER_BINDING_STOP Stop; + + /// + /// The version number of the UEFI driver that produced the + /// EFI_DRIVER_BINDING_PROTOCOL. This field is used by + /// the EFI boot service ConnectController() to determine + /// the order that driver's Supported() service will be used when + /// a controller needs to be started. EFI Driver Binding Protocol + /// instances with higher Version values will be used before ones + /// with lower Version values. The Version values of 0x0- + /// 0x0f and 0xfffffff0-0xffffffff are reserved for + /// platform/OEM specific drivers. The Version values of 0x10- + /// 0xffffffef are reserved for IHV-developed drivers. + /// + UINT32 Version; + + /// + /// The image handle of the UEFI driver that produced this instance + /// of the EFI_DRIVER_BINDING_PROTOCOL. + /// + EFI_HANDLE ImageHandle; + + /// + /// The handle on which this instance of the + /// EFI_DRIVER_BINDING_PROTOCOL is installed. In most + /// cases, this is the same handle as ImageHandle. However, for + /// UEFI drivers that produce more than one instance of the + /// EFI_DRIVER_BINDING_PROTOCOL, this value may not be + /// the same as ImageHandle. + /// + EFI_HANDLE DriverBindingHandle; +}; + +extern EFI_GUID gEfiDriverBindingProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration.h new file mode 100644 index 0000000000..2a0018fabd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration.h @@ -0,0 +1,161 @@ +/** @file + EFI Driver Configuration Protocol + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_CONFIGURATION_H__ +#define __EFI_DRIVER_CONFIGURATION_H__ + +#include + +/// +/// Global ID for the Driver Configuration Protocol defined in EFI 1.1 +/// +#define EFI_DRIVER_CONFIGURATION_PROTOCOL_GUID \ + { \ + 0x107a772b, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_DRIVER_CONFIGURATION_PROTOCOL EFI_DRIVER_CONFIGURATION_PROTOCOL; + +/** + Allows the user to set controller specific options for a controller that a + driver is currently managing. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance. + @param ControllerHandle The handle of the controller to set options on. + @param ChildHandle The handle of the child controller to set options on. This + is an optional parameter that may be NULL. It will be NULL + for device drivers, and for bus drivers that wish to set + options for the bus controller. It will not be NULL for a + bus driver that wishes to set options for one of its child + controllers. + @param Language A pointer to a three character ISO 639-2 language identifier. + This is the language of the user interface that should be + presented to the user, and it must match one of the languages + specified in SupportedLanguages. The number of languages + supported by a driver is up to the driver writer. + @param ActionRequired A pointer to the action that the calling agent is required + to perform when this function returns. See "Related + Definitions" for a list of the actions that the calling + agent is required to perform prior to accessing + ControllerHandle again. + + @retval EFI_SUCCESS The driver specified by This successfully set the + configuration options for the controller specified + by ControllerHandle.. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ActionRequired is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support setting + configuration options for the controller specified by + ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + @retval EFI_DEVICE_ERROR A device error occurred while attempt to set the + configuration options for the controller specified + by ControllerHandle and ChildHandle. + @retval EFI_OUT_RESOURCES There are not enough resources available to set the + configuration options for the controller specified + by ControllerHandle and ChildHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION_SET_OPTIONS)( + IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired + ); + +/** + Tests to see if a controller's current configuration options are valid. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance. + @param ControllerHandle The handle of the controller to test if it's current + configuration options are valid. + @param ChildHandle The handle of the child controller to test if it's current + configuration options are valid. This is an optional + parameter that may be NULL. It will be NULL for device + drivers. It will also be NULL for bus drivers that wish + to test the configuration options for the bus controller. + It will not be NULL for a bus driver that wishes to test + configuration options for one of its child controllers. + + @retval EFI_SUCCESS The controller specified by ControllerHandle and + ChildHandle that is being managed by the driver + specified by This has a valid set of configuration + options. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by ControllerHandle + and ChildHandle. + @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and + ChildHandle that is being managed by the driver + specified by This has an invalid set of configuration + options. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION_OPTIONS_VALID)( + IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL + ); + +/** + Forces a driver to set the default configuration options for a controller. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance. + @param ControllerHandle The handle of the controller to force default configuration options on. + @param ChildHandle The handle of the child controller to force default configuration options on This is an optional parameter that may be NULL. It will be NULL for device drivers. It will also be NULL for bus drivers that wish to force default configuration options for the bus controller. It will not be NULL for a bus driver that wishes to force default configuration options for one of its child controllers. + @param DefaultType The type of default configuration options to force on the controller specified by ControllerHandle and ChildHandle. See Table 9-1 for legal values. A DefaultType of 0x00000000 must be supported by this protocol. + @param ActionRequired A pointer to the action that the calling agent is required to perform when this function returns. See "Related Definitions" in Section 9.1 for a list of the actions that the calling agent is required to perform prior to accessing ControllerHandle again. + + @retval EFI_SUCCESS The driver specified by This successfully forced the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ActionRequired is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support forcing the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the configuration type specified by DefaultType. + @retval EFI_DEVICE_ERROR A device error occurred while attempt to force the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_OUT_RESOURCES There are not enough resources available to force the default configuration options on the controller specified by ControllerHandle and ChildHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS)( + IN EFI_DRIVER_CONFIGURATION_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN UINT32 DefaultType, + OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired + ); + + +/// +/// Used to set configuration options for a controller that an EFI Driver is managing. +/// +struct _EFI_DRIVER_CONFIGURATION_PROTOCOL { + EFI_DRIVER_CONFIGURATION_SET_OPTIONS SetOptions; + EFI_DRIVER_CONFIGURATION_OPTIONS_VALID OptionsValid; + EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS ForceDefaults; + /// + /// A Null-terminated ASCII string that contains one or more + /// ISO 639-2 language codes. This is the list of language + /// codes that this protocol supports. + /// + CHAR8 *SupportedLanguages; +}; + + +extern EFI_GUID gEfiDriverConfigurationProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration2.h new file mode 100644 index 0000000000..066968670b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverConfiguration2.h @@ -0,0 +1,184 @@ +/** @file + UEFI Driver Configuration2 Protocol + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_CONFIGURATION2_H__ +#define __EFI_DRIVER_CONFIGURATION2_H__ + +/// +/// Global ID for the Driver Configuration Protocol defined in UEFI 2.0 +/// +#define EFI_DRIVER_CONFIGURATION2_PROTOCOL_GUID \ + { \ + 0xbfd7dc1d, 0x24f1, 0x40d9, {0x82, 0xe7, 0x2e, 0x09, 0xbb, 0x6b, 0x4e, 0xbe } \ + } + +typedef struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL EFI_DRIVER_CONFIGURATION2_PROTOCOL; + +typedef enum { + /// + /// The controller is still in a usable state. No actions + /// are required before this controller can be used again. + /// + EfiDriverConfigurationActionNone = 0, + /// + /// The driver has detected that the controller is not in a + /// usable state, and it needs to be stopped. + /// + EfiDriverConfigurationActionStopController = 1, + /// + /// This controller needs to be stopped and restarted + /// before it can be used again. + /// + EfiDriverConfigurationActionRestartController = 2, + /// + /// A configuration change has been made that requires the platform to be restarted before + /// the controller can be used again. + /// + EfiDriverConfigurationActionRestartPlatform = 3, + EfiDriverConfigurationActionMaximum +} EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED; + +#define EFI_DRIVER_CONFIGURATION_SAFE_DEFAULTS 0x00000000 +#define EFI_DRIVER_CONFIGURATION_MANUFACTURING_DEFAULTS 0x00000001 +#define EFI_DRIVER_CONFIGURATION_CUSTOM_DEFAULTS 0x00000002 +#define EFI_DRIVER_CONFIGURATION_PERORMANCE_DEFAULTS 0x00000003 + +/** + Allows the user to set controller specific options for a controller that a + driver is currently managing. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance. + @param ControllerHandle The handle of the controller to set options on. + @param ChildHandle The handle of the child controller to set options on. This + is an optional parameter that may be NULL. It will be NULL + for device drivers, and for bus drivers that wish to set + options for the bus controller. It will not be NULL for a + bus driver that wishes to set options for one of its child + controllers. + @param Language A Null-terminated ASCII string that contains one or more RFC 4646 + language codes. This is the list of language codes that this + protocol supports. The number of languages + supported by a driver is up to the driver writer. + @param ActionRequired A pointer to the action that the calling agent is required + to perform when this function returns. See "Related + Definitions" for a list of the actions that the calling + agent is required to perform prior to accessing + ControllerHandle again. + + @retval EFI_SUCCESS The driver specified by This successfully set the + configuration options for the controller specified + by ControllerHandle. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ActionRequired is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support setting + configuration options for the controller specified by + ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to set the + configuration options for the controller specified + by ControllerHandle and ChildHandle. + @retval EFI_OUT_RESOURCES There are not enough resources available to set the + configuration options for the controller specified + by ControllerHandle and ChildHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION2_SET_OPTIONS)( + IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired + ); + +/** + Tests to see if a controller's current configuration options are valid. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance. + @param ControllerHandle The handle of the controller to test if it's current + configuration options are valid. + @param ChildHandle The handle of the child controller to test if it's current + configuration options are valid. This is an optional + parameter that may be NULL. It will be NULL for device + drivers. It will also be NULL for bus drivers that wish + to test the configuration options for the bus controller. + It will not be NULL for a bus driver that wishes to test + configuration options for one of its child controllers. + + @retval EFI_SUCCESS The controller specified by ControllerHandle and + ChildHandle that is being managed by the driver + specified by This has a valid set of configuration + options. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by ControllerHandle + and ChildHandle. + @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and + ChildHandle that is being managed by the driver + specified by This has an invalid set of configuration + options. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID)( + IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL + ); + +/** + Forces a driver to set the default configuration options for a controller. + + @param This A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance. + @param ControllerHandle The handle of the controller to force default configuration options on. + @param ChildHandle The handle of the child controller to force default configuration options on This is an optional parameter that may be NULL. It will be NULL for device drivers. It will also be NULL for bus drivers that wish to force default configuration options for the bus controller. It will not be NULL for a bus driver that wishes to force default configuration options for one of its child controllers. + @param DefaultType The type of default configuration options to force on the controller specified by ControllerHandle and ChildHandle. See Table 9-1 for legal values. A DefaultType of 0x00000000 must be supported by this protocol. + @param ActionRequired A pointer to the action that the calling agent is required to perform when this function returns. See "Related Definitions" in Section 9.1 for a list of the actions that the calling agent is required to perform prior to accessing ControllerHandle again. + + @retval EFI_SUCCESS The driver specified by This successfully forced the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ActionRequired is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support forcing the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the configuration type specified by DefaultType. + @retval EFI_DEVICE_ERROR A device error occurred while attempt to force the default configuration options on the controller specified by ControllerHandle and ChildHandle. + @retval EFI_OUT_RESOURCES There are not enough resources available to force the default configuration options on the controller specified by ControllerHandle and ChildHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS)( + IN EFI_DRIVER_CONFIGURATION2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN UINT32 DefaultType, + OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired + ); + +/// +/// Used to set configuration options for a controller that an EFI Driver is managing. +/// +struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL { + EFI_DRIVER_CONFIGURATION2_SET_OPTIONS SetOptions; + EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID OptionsValid; + EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS ForceDefaults; + /// + /// A Null-terminated ASCII string that contains one or more RFC 4646 + /// language codes. This is the list of language codes that this protocol supports. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiDriverConfiguration2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics.h new file mode 100644 index 0000000000..53ebe08529 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics.h @@ -0,0 +1,125 @@ +/** @file + EFI Driver Diagnostics Protocol + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_DIAGNOSTICS_H__ +#define __EFI_DRIVER_DIAGNOSTICS_H__ + +/// +/// The global ID for the Driver Diagnostics Protocol as defined in EFI 1.1. +/// +#define EFI_DRIVER_DIAGNOSTICS_PROTOCOL_GUID \ + { \ + 0x0784924f, 0xe296, 0x11d4, {0x9a, 0x49, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL EFI_DRIVER_DIAGNOSTICS_PROTOCOL; + +typedef enum { + /// + /// Performs standard diagnostics on the controller. + /// + EfiDriverDiagnosticTypeStandard = 0, + /// + /// This is an optional diagnostic type that performs diagnostics on the controller that may + /// take an extended amount of time to execute. + /// + EfiDriverDiagnosticTypeExtended = 1, + /// + /// This is an optional diagnostic type that performs diagnostics on the controller that are + /// suitable for a manufacturing and test environment. + /// + EfiDriverDiagnosticTypeManufacturing= 2, + /// + /// This is an optional diagnostic type that would only be used in the situation where an + /// EFI_NOT_READY had been returned by a previous call to RunDiagnostics() + /// and there is a desire to cancel the current running diagnostics operation. + /// + EfiDriverDiagnosticTypeCancel = 3, + EfiDriverDiagnosticTypeMaximum +} EFI_DRIVER_DIAGNOSTIC_TYPE; + +/** + Runs diagnostics on a controller. + + @param This A pointer to the EFI_DRIVER_DIAGNOSTICS_PROTOCOL instance. + @param ControllerHandle The handle of the controller to run diagnostics on. + @param ChildHandle The handle of the child controller to run diagnostics on + This is an optional parameter that may be NULL. It will + be NULL for device drivers. It will also be NULL for a + bus drivers that wish to run diagnostics on the bus + controller. It will not be NULL for a bus driver that + wishes to run diagnostics on one of its child controllers. + @param DiagnosticType Indicates type of diagnostics to perform on the controller + specified by ControllerHandle and ChildHandle. See + "Related Definitions" for the list of supported types. + @param Language A pointer to a three character ISO 639-2 language + identifier. This is the language in which the optional + error message should be returned in Buffer, and it must + match one of the languages specified in SupportedLanguages. + The number of languages supported by a driver is up to + the driver writer. + @param ErrorType A GUID that defines the format of the data returned in Buffer. + @param BufferSize The size, in bytes, of the data returned in Buffer. + @param Buffer A buffer that contains a Null-terminated string + plus some additional data whose format is defined by + ErrorType. Buffer is allocated by this function with + AllocatePool(), and it is the caller's responsibility + to free it with a call to FreePool(). + + @retval EFI_SUCCESS The controller specified by ControllerHandle and + ChildHandle passed the diagnostic. + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL, and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER ErrorType is NULL. + @retval EFI_INVALID_PARAMETER BufferType is NULL. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support + running diagnostics for the controller specified + by ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + type of diagnostic specified by DiagnosticType. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to complete + the diagnostics. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to return + the status information in ErrorType, BufferSize, + and Buffer. + @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and + ChildHandle did not pass the diagnostic. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS)( + IN EFI_DRIVER_DIAGNOSTICS_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType, + IN CHAR8 *Language, + OUT EFI_GUID **ErrorType, + OUT UINTN *BufferSize, + OUT CHAR16 **Buffer + ); + +/// +/// Used to perform diagnostics on a controller that an EFI Driver is managing. +/// +struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL { + EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS RunDiagnostics; + /// + /// A Null-terminated ASCII string that contains one or more ISO 639-2 + /// language codes. This is the list of language codes that this protocol supports. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiDriverDiagnosticsProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics2.h new file mode 100644 index 0000000000..b0b4c8cd67 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverDiagnostics2.h @@ -0,0 +1,105 @@ +/** @file + UEFI Driver Diagnostics2 Protocol + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_DIAGNOSTICS2_H__ +#define __EFI_DRIVER_DIAGNOSTICS2_H__ + +#include + +#define EFI_DRIVER_DIAGNOSTICS2_PROTOCOL_GUID \ + { \ + 0x4d330321, 0x025f, 0x4aac, {0x90, 0xd8, 0x5e, 0xd9, 0x00, 0x17, 0x3b, 0x63 } \ + } + +typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL EFI_DRIVER_DIAGNOSTICS2_PROTOCOL; + +/** + Runs diagnostics on a controller. + + @param This A pointer to the EFI_DRIVER_DIAGNOSTICS2_PROTOCOL instance. + @param ControllerHandle The handle of the controller to run diagnostics on. + @param ChildHandle The handle of the child controller to run diagnostics on + This is an optional parameter that may be NULL. It will + be NULL for device drivers. It will also be NULL for + bus drivers that wish to run diagnostics on the bus + controller. It will not be NULL for a bus driver that + wishes to run diagnostics on one of its child controllers. + @param DiagnosticType Indicates the type of diagnostics to perform on the controller + specified by ControllerHandle and ChildHandle. See + "Related Definitions" for the list of supported types. + @param Language A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller + is requesting, and it must match one of the + languages specified in SupportedLanguages. + The number of languages supported by a + driver is up to the driver writer. Language + is specified in RFC 4646 language code format. + @param ErrorType A GUID that defines the format of the data returned in Buffer. + @param BufferSize The size, in bytes, of the data returned in Buffer. + @param Buffer A buffer that contains a Null-terminated Unicode string + plus some additional data whose format is defined by + ErrorType. Buffer is allocated by this function with + AllocatePool(), and it is the caller's responsibility + to free it with a call to FreePool(). + + @retval EFI_SUCCESS The controller specified by ControllerHandle and + ChildHandle passed the diagnostic. + @retval EFI_ACCESS_DENIED The request for initiating diagnostics was unable + to be complete due to some underlying hardware or + software state. + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER ErrorType is NULL. + @retval EFI_INVALID_PARAMETER BufferType is NULL. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support + running diagnostics for the controller specified + by ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + type of diagnostic specified by DiagnosticType. + @retval EFI_UNSUPPORTED The driver specified by This does not support the + language specified by Language. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to complete + the diagnostics. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to return + the status information in ErrorType, BufferSize, + and Buffer. + @retval EFI_DEVICE_ERROR The controller specified by ControllerHandle and + ChildHandle did not pass the diagnostic. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS)( + IN EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType, + IN CHAR8 *Language, + OUT EFI_GUID **ErrorType, + OUT UINTN *BufferSize, + OUT CHAR16 **Buffer + ); + +/// +/// Used to perform diagnostics on a controller that an EFI Driver is managing. +/// +struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL { + EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics; + /// + /// A Null-terminated ASCII string that contains one or more RFC 4646 + /// language codes. This is the list of language codes that this protocol supports. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiDriverDiagnostics2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverFamilyOverride.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverFamilyOverride.h new file mode 100644 index 0000000000..5b06f0b0e0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverFamilyOverride.h @@ -0,0 +1,60 @@ +/** @file + UEFI Driver Family Protocol + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_DRIVER_FAMILY_OVERRIDE_H__ +#define __EFI_DRIVER_FAMILY_OVERRIDE_H__ + +#define EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL_GUID \ + { \ + 0xb1ee129e, 0xda36, 0x4181, { 0x91, 0xf8, 0x4, 0xa4, 0x92, 0x37, 0x66, 0xa7 } \ + } + +typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL; + +// +// Prototypes for the Driver Family Override Protocol +// +// +/** + This function returns the version value associated with the driver specified by This. + + Retrieves the version of the driver that is used by the EFI Boot Service ConnectController() + to sort the set of Driver Binding Protocols in order from highest priority to lowest priority. + For drivers that support the Driver Family Override Protocol, those drivers are sorted so that + the drivers with higher values returned by GetVersion() are higher priority than drivers that + return lower values from GetVersion(). + + @param This A pointer to the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL instance. + + @return The version value associated with the driver specified by This. + +**/ +typedef +UINT32 +(EFIAPI *EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION)( + IN EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL *This + ); + +/// +/// When installed, the Driver Family Override Protocol produces a GUID that represents +/// a family of drivers. Drivers with the same GUID are members of the same family +/// When drivers are connected to controllers, drivers with a higher revision value +/// in the same driver family are connected with a higher priority than drivers +/// with a lower revision value in the same driver family. The EFI Boot Service +/// Connect Controller uses five rules to build a prioritized list of drivers when +/// a request is made to connect a driver to a controller. The Driver Family Protocol +/// rule is between the Platform Specific Driver Override Protocol and above the +/// Bus Specific Driver Override Protocol. +/// +struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL { + EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion; +}; + +extern EFI_GUID gEfiDriverFamilyOverrideProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverHealth.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverHealth.h new file mode 100644 index 0000000000..691d205ec0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverHealth.h @@ -0,0 +1,241 @@ +/** @file + EFI Driver Health Protocol definitions. + + When installed, the Driver Health Protocol produces a collection of services that allow + the health status for a controller to be retrieved. If a controller is not in a usable + state, status messages may be reported to the user, repair operations can be invoked, + and the user may be asked to make software and/or hardware configuration changes. + + The Driver Health Protocol is optionally produced by a driver that follows the + EFI Driver Model. If an EFI Driver needs to report health status to the platform, + provide warning or error messages to the user, perform length repair operations, + or request the user to make hardware or software configuration changes, then the + Driver Health Protocol must be produced. + + A controller that is managed by driver that follows the EFI Driver Model and + produces the Driver Health Protocol must report the current health of the + controllers that the driver is currently managing. The controller can initially + be healthy, failed, require repair, or require configuration. If a controller + requires configuration, and the user make configuration changes, the controller + may then need to be reconnected or the system may need to be rebooted for the + configuration changes to take affect. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Specification 2.3d + +**/ + +#ifndef __EFI_DRIVER_HEALTH_H__ +#define __EFI_DRIVER_HEALTH_H__ + +#define EFI_DRIVER_HEALTH_PROTOCOL_GUID \ + { \ + 0x2a534210, 0x9280, 0x41d8, { 0xae, 0x79, 0xca, 0xda, 0x1, 0xa2, 0xb1, 0x27 } \ + } + +typedef struct _EFI_DRIVER_HEALTH_PROTOCOL EFI_DRIVER_HEALTH_PROTOCOL; + +/// +/// EFI_DRIVER_HEALTH_HEALTH_STATUS +/// +typedef enum { + EfiDriverHealthStatusHealthy, + EfiDriverHealthStatusRepairRequired, + EfiDriverHealthStatusConfigurationRequired, + EfiDriverHealthStatusFailed, + EfiDriverHealthStatusReconnectRequired, + EfiDriverHealthStatusRebootRequired +} EFI_DRIVER_HEALTH_STATUS; + +/// +/// EFI_DRIVER_HEALTH_HII_MESSAGE +/// +typedef struct { + EFI_HII_HANDLE HiiHandle; + EFI_STRING_ID StringId; + + /// + /// 64-bit numeric value of the warning/error specified by this message. + /// A value of 0x0000000000000000 is used to indicate that MessageCode is not specified. + /// The values 0x0000000000000001 to 0x0fffffffffffffff are reserved for allocation by the UEFI Specification. + /// The values 0x1000000000000000 to 0x1fffffffffffffff are reserved for IHV-developed drivers. + /// The values 0x8000000000000000 to 0x8fffffffffffffff is reserved for platform/OEM drivers. + /// All other values are reserved and should not be used. + /// + UINT64 MessageCode; +} EFI_DRIVER_HEALTH_HII_MESSAGE; + +/** + Reports the progress of a repair operation + + @param[in] Value A value between 0 and Limit that identifies the current + progress of the repair operation. + + @param[in] Limit The maximum value of Value for the current repair operation. + For example, a driver that wants to specify progress in + percent would use a Limit value of 100. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_HEALTH_REPAIR_NOTIFY)( + IN UINTN Value, + IN UINTN Limit + ); + +/** + Retrieves the health status of a controller in the platform. This function can also + optionally return warning messages, error messages, and a set of HII Forms that may + be repair a controller that is not proper configured. + + @param[in] This A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance. + + @param[in] ControllerHandle The handle of the controller to retrieve the health status + on. This is an optional parameter that may be NULL. If + this parameter is NULL, then the value of ChildHandle is + ignored, and the combined health status of all the devices + that the driver is managing is returned. + + @param[in] ChildHandle The handle of the child controller to retrieve the health + status on. This is an optional parameter that may be NULL. + This parameter is ignored of ControllerHandle is NULL. It + will be NULL for device drivers. It will also be NULL for + bus drivers when an attempt is made to collect the health + status of the bus controller. If will not be NULL when an + attempt is made to collect the health status for a child + controller produced by the driver. + + @param[out] HealthStatus A pointer to the health status that is returned by this + function. This is an optional parameter that may be NULL. + This parameter is ignored of ControllerHandle is NULL. + The health status for the controller specified by + ControllerHandle and ChildHandle is returned. + + @param[out] MessageList A pointer to an array of warning or error messages associated + with the controller specified by ControllerHandle and + ChildHandle. This is an optional parameter that may be NULL. + MessageList is allocated by this function with the EFI Boot + Service AllocatePool(), and it is the caller's responsibility + to free MessageList with the EFI Boot Service FreePool(). + Each message is specified by tuple of an EFI_HII_HANDLE and + an EFI_STRING_ID. The array of messages is terminated by tuple + containing a EFI_HII_HANDLE with a value of NULL. The + EFI_HII_STRING_PROTOCOL.GetString() function can be used to + retrieve the warning or error message as a Null-terminated + string in a specific language. Messages may be + returned for any of the HealthStatus values except + EfiDriverHealthStatusReconnectRequired and + EfiDriverHealthStatusRebootRequired. + + @param[out] FormHiiHandle A pointer to the HII handle containing the HII form used when + configuration is required. The HII handle is associated with + the controller specified by ControllerHandle and ChildHandle. + If this is NULL, then no HII form is available. An HII handle + will only be returned with a HealthStatus value of + EfiDriverHealthStatusConfigurationRequired. + + @retval EFI_SUCCESS ControllerHandle is NULL, and all the controllers + managed by this driver specified by This have a health + status of EfiDriverHealthStatusHealthy with no warning + messages to be returned. The ChildHandle, HealthStatus, + MessageList, and FormList parameters are ignored. + + @retval EFI_DEVICE_ERROR ControllerHandle is NULL, and one or more of the + controllers managed by this driver specified by This + do not have a health status of EfiDriverHealthStatusHealthy. + The ChildHandle, HealthStatus, MessageList, and + FormList parameters are ignored. + + @retval EFI_DEVICE_ERROR ControllerHandle is NULL, and one or more of the + controllers managed by this driver specified by This + have one or more warning and/or error messages. + The ChildHandle, HealthStatus, MessageList, and + FormList parameters are ignored. + + @retval EFI_SUCCESS ControllerHandle is not NULL and the health status + of the controller specified by ControllerHandle and + ChildHandle was returned in HealthStatus. A list + of warning and error messages may be optionally + returned in MessageList, and a list of HII Forms + may be optionally returned in FormList. + + @retval EFI_UNSUPPORTED ControllerHandle is not NULL, and the controller + specified by ControllerHandle and ChildHandle is not + currently being managed by the driver specified by This. + + @retval EFI_INVALID_PARAMETER HealthStatus is NULL. + + @retval EFI_OUT_OF_RESOURCES MessageList is not NULL, and there are not enough + resource available to allocate memory for MessageList. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_HEALTH_GET_HEALTH_STATUS)( + IN EFI_DRIVER_HEALTH_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle OPTIONAL, + IN EFI_HANDLE ChildHandle OPTIONAL, + OUT EFI_DRIVER_HEALTH_STATUS *HealthStatus, + OUT EFI_DRIVER_HEALTH_HII_MESSAGE **MessageList OPTIONAL, + OUT EFI_HII_HANDLE *FormHiiHandle OPTIONAL + ); + +/** + Performs a repair operation on a controller in the platform. This function can + optionally report repair progress information back to the platform. + + @param[in] This A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance. + @param[in] ControllerHandle The handle of the controller to repair. + @param[in] ChildHandle The handle of the child controller to repair. This is + an optional parameter that may be NULL. It will be NULL + for device drivers. It will also be NULL for bus + drivers when an attempt is made to repair a bus controller. + If will not be NULL when an attempt is made to repair a + child controller produced by the driver. + @param[in] RepairNotify A notification function that may be used by a driver to + report the progress of the repair operation. This is + an optional parameter that may be NULL. + + + @retval EFI_SUCCESS An attempt to repair the controller specified by + ControllerHandle and ChildHandle was performed. + The result of the repair operation can bet + determined by calling GetHealthStatus(). + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by ControllerHandle + and ChildHandle. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to perform the + repair operation. + +*/ +typedef +EFI_STATUS +(EFIAPI *EFI_DRIVER_HEALTH_REPAIR)( + IN EFI_DRIVER_HEALTH_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN EFI_DRIVER_HEALTH_REPAIR_NOTIFY RepairNotify OPTIONAL + ); + +/// +/// When installed, the Driver Health Protocol produces a collection of services +/// that allow the health status for a controller to be retrieved. If a controller +/// is not in a usable state, status messages may be reported to the user, repair +/// operations can be invoked, and the user may be asked to make software and/or +/// hardware configuration changes. +/// +struct _EFI_DRIVER_HEALTH_PROTOCOL { + EFI_DRIVER_HEALTH_GET_HEALTH_STATUS GetHealthStatus; + EFI_DRIVER_HEALTH_REPAIR Repair; +}; + +extern EFI_GUID gEfiDriverHealthProtocolGuid; + +#endif + + + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h new file mode 100644 index 0000000000..056ac3addf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h @@ -0,0 +1,40 @@ +/** @file + The protocol provides information about the version of the EFI + specification that a driver is following. This protocol is + required for EFI drivers that are on PCI and other plug-in + cards. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DRIVER_SUPPORTED_EFI_VERSION_H__ +#define __DRIVER_SUPPORTED_EFI_VERSION_H__ + +#define EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL_GUID \ + { 0x5c198761, 0x16a8, 0x4e69, { 0x97, 0x2c, 0x89, 0xd6, 0x79, 0x54, 0xf8, 0x1d } } + + +/// +/// The EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL provides a +/// mechanism for an EFI driver to publish the version of the EFI +/// specification it conforms to. This protocol must be placed on +/// the driver's image handle when the driver's entry point is +/// called. +/// +typedef struct _EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL { + /// + /// The size, in bytes, of the entire structure. Future versions of this + /// specification may grow the size of the structure. + /// + UINT32 Length; + /// + /// The latest version of the UEFI specification that this driver conforms to. + /// + UINT32 FirmwareVersion; +} EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL; + +extern EFI_GUID gEfiDriverSupportedEfiVersionProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeMmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeMmReadyToLock.h new file mode 100644 index 0000000000..d406aeefc3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeMmReadyToLock.h @@ -0,0 +1,19 @@ +/** @file + DXE MM Ready To Lock protocol introduced in the PI 1.5 specification. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _DXE_MM_READY_TO_LOCK_H_ +#define _DXE_MM_READY_TO_LOCK_H_ + +#define EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID \ + { \ + 0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e } \ + } + +extern EFI_GUID gEfiDxeMmReadyToLockProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeSmmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeSmmReadyToLock.h new file mode 100644 index 0000000000..e4756dfc30 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/DxeSmmReadyToLock.h @@ -0,0 +1,34 @@ +/** @file + DXE SMM Ready To Lock protocol introduced in the PI 1.2 specification. + + According to PI 1.4a specification, this UEFI protocol indicates that + resources and services that should not be used by the third party code + are about to be locked. + This protocol is a mandatory protocol published by PI platform code. + This protocol in tandem with the End of DXE Event facilitates transition + of the platform from the environment where all of the components are + under the authority of the platform manufacturer to the environment where + third party extensible modules such as UEFI drivers and UEFI applications + are executed. The protocol is published immediately after signaling of the + End of DXE Event. PI modules that need to lock or protect their resources + in anticipation of the invocation of 3rd party extensible modules should + register for notification on installation of this protocol and effect the + appropriate protections in their notification handlers. For example, PI + platform code may choose to use notification handler to lock SMM by invoking + EFI_SMM_ACCESS2_PROTOCOL.Lock() function. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _DXE_SMM_READY_TO_LOCK_H_ +#define _DXE_SMM_READY_TO_LOCK_H_ + +#include + +#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID + +extern EFI_GUID gEfiDxeSmmReadyToLockProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Eap.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Eap.h new file mode 100644 index 0000000000..3c2afa4cd4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Eap.h @@ -0,0 +1,156 @@ +/** @file + EFI EAP(Extended Authenticaton Protocol) Protocol Definition + The EFI EAP Protocol is used to abstract the ability to configure and extend the + EAP framework. + The definitions in this file are defined in UEFI Specification 2.3.1B, which have + not been verified by one implementation yet. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_EAP_PROTOCOL_H__ +#define __EFI_EAP_PROTOCOL_H__ + + +#define EFI_EAP_PROTOCOL_GUID \ + { \ + 0x5d9f96db, 0xe731, 0x4caa, {0xa0, 0xd, 0x72, 0xe1, 0x87, 0xcd, 0x77, 0x62 } \ + } + +typedef struct _EFI_EAP_PROTOCOL EFI_EAP_PROTOCOL; + +/// +/// Type for the identification number assigned to the Port by the +/// System in which the Port resides. +/// +typedef VOID * EFI_PORT_HANDLE; + +/// +/// EAP Authentication Method Type (RFC 3748) +///@{ +#define EFI_EAP_TYPE_TLS 13 ///< REQUIRED - RFC 5216 +///@} + +// +// EAP_TYPE MD5, OTP and TOEKN_CARD has been removed from UEFI2.3.1B. +// Definitions are kept for backward compatibility. +// +#define EFI_EAP_TYPE_MD5 4 +#define EFI_EAP_TYPE_OTP 5 +#define EFI_EAP_TYPE_TOKEN_CARD 6 + +/** + One user provided EAP authentication method. + + Build EAP response packet in response to the EAP request packet specified by + (RequestBuffer, RequestSize). + + @param[in] PortNumber Specified the Port where the EAP request packet comes. + @param[in] RequestBuffer Pointer to the most recently received EAP- Request packet. + @param[in] RequestSize Packet size in bytes for the most recently received + EAP-Request packet. + @param[in] Buffer Pointer to the buffer to hold the built packet. + @param[in, out] BufferSize Pointer to the buffer size in bytes. + On input, it is the buffer size provided by the caller. + On output, it is the buffer size in fact needed to contain + the packet. + + @retval EFI_SUCCESS The required EAP response packet is built successfully. + @retval others Failures are encountered during the packet building process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_BUILD_RESPONSE_PACKET)( + IN EFI_PORT_HANDLE PortNumber, + IN UINT8 *RequestBuffer, + IN UINTN RequestSize, + IN UINT8 *Buffer, + IN OUT UINTN *BufferSize + ); + +/** + Set the desired EAP authentication method for the Port. + + The SetDesiredAuthMethod() function sets the desired EAP authentication method indicated + by EapAuthType for the Port. + + If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is + returned. + If the EAP authentication method of EapAuthType is unsupported by the Ports, then it will + return EFI_UNSUPPORTED. + The cryptographic strength of EFI_EAP_TYPE_TLS shall be at least of hash strength + SHA-256 and RSA key length of at least 2048 bits. + + @param[in] This A pointer to the EFI_EAP_PROTOCOL instance that indicates + the calling context. + @param[in] EapAuthType The type of the EAP authentication method to register. It should + be the type value defined by RFC. See RFC 2284 for details. + @param[in] Handler The handler of the EAP authentication method to register. + + @retval EFI_SUCCESS The EAP authentication method of EapAuthType is + registered successfully. + @retval EFI_INVALID_PARAMETER EapAuthType is an invalid EAP authentication type. + @retval EFI_UNSUPPORTED The EAP authentication method of EapAuthType is + unsupported by the Port. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD)( + IN EFI_EAP_PROTOCOL *This, + IN UINT8 EapAuthType + ); + +/** + Register an EAP authentication method. + + The RegisterAuthMethod() function registers the user provided EAP authentication method, + the type of which is EapAuthType and the handler of which is Handler. + + If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is + returned. + If there is not enough system memory to perform the registration, then + EFI_OUT_OF_RESOURCES is returned. + + @param[in] This A pointer to the EFI_EAP_PROTOCOL instance that indicates + the calling context. + @param[in] EapAuthType The type of the EAP authentication method to register. It should + be the type value defined by RFC. See RFC 2284 for details. + @param[in] Handler The handler of the EAP authentication method to register. + + @retval EFI_SUCCESS The EAP authentication method of EapAuthType is + registered successfully. + @retval EFI_INVALID_PARAMETER EapAuthType is an invalid EAP authentication type. + @retval EFI_OUT_OF_RESOURCES There is not enough system memory to perform the registration. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_REGISTER_AUTHENTICATION_METHOD)( + IN EFI_EAP_PROTOCOL *This, + IN UINT8 EapAuthType, + IN EFI_EAP_BUILD_RESPONSE_PACKET Handler + ); + +/// +/// EFI_EAP_PROTOCOL +/// is used to configure the desired EAP authentication method for the EAP +/// framework and extend the EAP framework by registering new EAP authentication +/// method on a Port. The EAP framework is built on a per-Port basis. Herein, a +/// Port means a NIC. For the details of EAP protocol, please refer to RFC 2284. +/// +struct _EFI_EAP_PROTOCOL { + EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD SetDesiredAuthMethod; + EFI_EAP_REGISTER_AUTHENTICATION_METHOD RegisterAuthMethod; +}; + +extern EFI_GUID gEfiEapProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapConfiguration.h new file mode 100644 index 0000000000..698d835410 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapConfiguration.h @@ -0,0 +1,153 @@ +/** @file + This file defines the EFI EAP Configuration protocol. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_EAP_CONFIGURATION_PROTOCOL_H__ +#define __EFI_EAP_CONFIGURATION_PROTOCOL_H__ + +/// +/// EFI EAP Configuration protocol provides a way to set and get EAP configuration. +/// +#define EFI_EAP_CONFIGURATION_PROTOCOL_GUID \ + { \ + 0xe5b58dbb, 0x7688, 0x44b4, {0x97, 0xbf, 0x5f, 0x1d, 0x4b, 0x7c, 0xc8, 0xdb } \ + } + +typedef struct _EFI_EAP_CONFIGURATION_PROTOCOL EFI_EAP_CONFIGURATION_PROTOCOL; + +/// +/// Make sure it not conflict with any real EapTypeXXX +/// +#define EFI_EAP_TYPE_ATTRIBUTE 0 + +typedef enum { + /// + /// EFI_EAP_TYPE_ATTRIBUTE + /// + EfiEapConfigEapAuthMethod, + EfiEapConfigEapSupportedAuthMethod, + /// + /// EapTypeIdentity + /// + EfiEapConfigIdentityString, + /// + /// EapTypeEAPTLS/EapTypePEAP + /// + EfiEapConfigEapTlsCACert, + EfiEapConfigEapTlsClientCert, + EfiEapConfigEapTlsClientPrivateKeyFile, + EfiEapConfigEapTlsClientPrivateKeyFilePassword, // ASCII format, Volatile + EfiEapConfigEapTlsCipherSuite, + EfiEapConfigEapTlsSupportedCipherSuite, + /// + /// EapTypeMSChapV2 + /// + EfiEapConfigEapMSChapV2Password, // UNICODE format, Volatile + /// + /// EapTypePEAP + /// + EfiEapConfigEap2ndAuthMethod, + /// + /// More... + /// +} EFI_EAP_CONFIG_DATA_TYPE; + +/// +/// EFI_EAP_TYPE +/// +typedef UINT8 EFI_EAP_TYPE; +#define EFI_EAP_TYPE_ATTRIBUTE 0 +#define EFI_EAP_TYPE_IDENTITY 1 +#define EFI_EAP_TYPE_NOTIFICATION 2 +#define EFI_EAP_TYPE_NAK 3 +#define EFI_EAP_TYPE_MD5CHALLENGE 4 +#define EFI_EAP_TYPE_OTP 5 +#define EFI_EAP_TYPE_GTC 6 +#define EFI_EAP_TYPE_EAPTLS 13 +#define EFI_EAP_TYPE_EAPSIM 18 +#define EFI_EAP_TYPE_TTLS 21 +#define EFI_EAP_TYPE_PEAP 25 +#define EFI_EAP_TYPE_MSCHAPV2 26 +#define EFI_EAP_TYPE_EAP_EXTENSION 33 + +/** + Set EAP configuration data. + + The SetData() function sets EAP configuration to non-volatile storage or volatile + storage. + + @param[in] This Pointer to the EFI_EAP_CONFIGURATION_PROTOCOL instance. + @param[in] EapType EAP type. + @param[in] DataType Configuration data type. + @param[in] Data Pointer to configuration data. + @param[in] DataSize Total size of configuration data. + + @retval EFI_SUCCESS The EAP configuration data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + Data is NULL. + DataSize is 0. + @retval EFI_UNSUPPORTED The EapType or DataType is unsupported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_CONFIGURATION_SET_DATA) ( + IN EFI_EAP_CONFIGURATION_PROTOCOL *This, + IN EFI_EAP_TYPE EapType, + IN EFI_EAP_CONFIG_DATA_TYPE DataType, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get EAP configuration data. + + The GetData() function gets EAP configuration. + + @param[in] This Pointer to the EFI_EAP_CONFIGURATION_PROTOCOL instance. + @param[in] EapType EAP type. + @param[in] DataType Configuration data type. + @param[in, out] Data Pointer to configuration data. + @param[in, out] DataSize Total size of configuration data. On input, it means + the size of Data buffer. On output, it means the size + of copied Data buffer if EFI_SUCCESS, and means the + size of desired Data buffer if EFI_BUFFER_TOO_SMALL. + + @retval EFI_SUCCESS The EAP configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + Data is NULL. + DataSize is NULL. + @retval EFI_UNSUPPORTED The EapType or DataType is unsupported. + @retval EFI_NOT_FOUND The EAP configuration data is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_CONFIGURATION_GET_DATA) ( + IN EFI_EAP_CONFIGURATION_PROTOCOL *This, + IN EFI_EAP_TYPE EapType, + IN EFI_EAP_CONFIG_DATA_TYPE DataType, + IN OUT VOID *Data, + IN OUT UINTN *DataSize + ); + +/// +/// The EFI_EAP_CONFIGURATION_PROTOCOL +/// is designed to provide a way to set and get EAP configuration, such as Certificate, +/// private key file. +/// +struct _EFI_EAP_CONFIGURATION_PROTOCOL { + EFI_EAP_CONFIGURATION_SET_DATA SetData; + EFI_EAP_CONFIGURATION_GET_DATA GetData; +}; + +extern EFI_GUID gEfiEapConfigurationProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement.h new file mode 100644 index 0000000000..c65bc1bdf0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement.h @@ -0,0 +1,397 @@ +/** @file + EFI EAP Management Protocol Definition + The EFI EAP Management Protocol is designed to provide ease of management and + ease of test for EAPOL state machine. It is intended for the supplicant side. + It conforms to IEEE 802.1x specification. + The definitions in this file are defined in UEFI Specification 2.2, which have + not been verified by one implementation yet. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_EAP_MANAGEMENT_PROTOCOL_H__ +#define __EFI_EAP_MANAGEMENT_PROTOCOL_H__ + +#include + +#define EFI_EAP_MANAGEMENT_PROTOCOL_GUID \ + { \ + 0xbb62e663, 0x625d, 0x40b2, {0xa0, 0x88, 0xbb, 0xe8, 0x36, 0x23, 0xa2, 0x45 } \ + } + +typedef struct _EFI_EAP_MANAGEMENT_PROTOCOL EFI_EAP_MANAGEMENT_PROTOCOL; + +/// +/// PAE Capabilities +/// +///@{ +#define PAE_SUPPORT_AUTHENTICATOR 0x01 +#define PAE_SUPPORT_SUPPLICANT 0x02 +///@} + +/// +/// EFI_EAPOL_PORT_INFO +/// +typedef struct _EFI_EAPOL_PORT_INFO { + /// + /// The identification number assigned to the Port by the System in + /// which the Port resides. + /// + EFI_PORT_HANDLE PortNumber; + /// + /// The protocol version number of the EAPOL implementation + /// supported by the Port. + /// + UINT8 ProtocolVersion; + /// + /// The capabilities of the PAE associated with the Port. This field + /// indicates whether Authenticator functionality, Supplicant + /// functionality, both, or neither, is supported by the Port's PAE. + /// + UINT8 PaeCapabilities; +} EFI_EAPOL_PORT_INFO; + +/// +/// Supplicant PAE state machine (IEEE Std 802.1X Section 8.5.10) +/// +typedef enum _EFI_EAPOL_SUPPLICANT_PAE_STATE { + Logoff, + Disconnected, + Connecting, + Acquired, + Authenticating, + Held, + Authenticated, + MaxSupplicantPaeState +} EFI_EAPOL_SUPPLICANT_PAE_STATE; + +/// +/// Definitions for ValidFieldMask +/// +///@{ +#define AUTH_PERIOD_FIELD_VALID 0x01 +#define HELD_PERIOD_FIELD_VALID 0x02 +#define START_PERIOD_FIELD_VALID 0x04 +#define MAX_START_FIELD_VALID 0x08 +///@} + +/// +/// EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION +/// +typedef struct _EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION { + /// + /// Indicates which of the following fields are valid. + /// + UINT8 ValidFieldMask; + /// + /// The initial value for the authWhile timer. Its default value is 30s. + /// + UINTN AuthPeriod; + /// + /// The initial value for the heldWhile timer. Its default value is 60s. + /// + UINTN HeldPeriod; + /// + /// The initial value for the startWhen timer. Its default value is 30s. + /// + UINTN StartPeriod; + /// + /// The maximum number of successive EAPOL-Start messages will + /// be sent before the Supplicant assumes that there is no + /// Authenticator present. Its default value is 3. + /// + UINTN MaxStart; +} EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION; + +/// +/// Supplicant Statistics (IEEE Std 802.1X Section 9.5.2) +/// +typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS { + /// + /// The number of EAPOL frames of any type that have been received by this Supplican. + /// + UINTN EapolFramesReceived; + /// + /// The number of EAPOL frames of any type that have been transmitted by this Supplicant. + /// + UINTN EapolFramesTransmitted; + /// + /// The number of EAPOL Start frames that have been transmitted by this Supplicant. + /// + UINTN EapolStartFramesTransmitted; + /// + /// The number of EAPOL Logoff frames that have been transmitted by this Supplicant. + /// + UINTN EapolLogoffFramesTransmitted; + /// + /// The number of EAP Resp/Id frames that have been transmitted by this Supplicant. + /// + UINTN EapRespIdFramesTransmitted; + /// + /// The number of valid EAP Response frames (other than Resp/Id frames) that have been + /// transmitted by this Supplicant. + /// + UINTN EapResponseFramesTransmitted; + /// + /// The number of EAP Req/Id frames that have been received by this Supplicant. + /// + UINTN EapReqIdFramesReceived; + /// + /// The number of EAP Request frames (other than Rq/Id frames) that have been received + /// by this Supplicant. + /// + UINTN EapRequestFramesReceived; + /// + /// The number of EAPOL frames that have been received by this Supplicant in which the + /// frame type is not recognized. + /// + UINTN InvalidEapolFramesReceived; + /// + /// The number of EAPOL frames that have been received by this Supplicant in which the + /// Packet Body Length field (7.5.5) is invalid. + /// + UINTN EapLengthErrorFramesReceived; + /// + /// The protocol version number carried in the most recently received EAPOL frame. + /// + UINTN LastEapolFrameVersion; + /// + /// The source MAC address carried in the most recently received EAPOL frame. + /// + UINTN LastEapolFrameSource; +} EFI_EAPOL_SUPPLICANT_PAE_STATISTICS; + +/** + Read the system configuration information associated with the Port. + + The GetSystemConfiguration() function reads the system configuration + information associated with the Port, including the value of the + SystemAuthControl parameter of the System is returned in SystemAuthControl + and the Port's information is returned in the buffer pointed to by PortInfo. + The Port's information is optional. + If PortInfo is NULL, then reading the Port's information is ignored. + + If SystemAuthControl is NULL, then EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + @param[out] SystemAuthControl Returns the value of the SystemAuthControl + parameter of the System. + TRUE means Enabled. FALSE means Disabled. + @param[out] PortInfo Returns EFI_EAPOL_PORT_INFO structure to describe + the Port's information. This parameter can be NULL + to ignore reading the Port's information. + + @retval EFI_SUCCESS The system configuration information of the + Port is read successfully. + @retval EFI_INVALID_PARAMETER SystemAuthControl is NULL. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_GET_SYSTEM_CONFIGURATION)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This, + OUT BOOLEAN *SystemAuthControl, + OUT EFI_EAPOL_PORT_INFO *PortInfo OPTIONAL + ); + +/** + Set the system configuration information associated with the Port. + + The SetSystemConfiguration() function sets the value of the SystemAuthControl + parameter of the System to SystemAuthControl. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + @param[in] SystemAuthControl The desired value of the SystemAuthControl + parameter of the System. + TRUE means Enabled. FALSE means Disabled. + + @retval EFI_SUCCESS The system configuration information of the + Port is set successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_SET_SYSTEM_CONFIGURATION)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This, + IN BOOLEAN SystemAuthControl + ); + +/** + Cause the EAPOL state machines for the Port to be initialized. + + The InitializePort() function causes the EAPOL state machines for the Port. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + + @retval EFI_SUCCESS The Port is initialized successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_INITIALIZE_PORT)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This + ); + +/** + Notify the EAPOL state machines for the Port that the user of the System has + logged on. + + The UserLogon() function notifies the EAPOL state machines for the Port. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + + @retval EFI_SUCCESS The Port is notified successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_USER_LOGON)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This + ); + +/** + Notify the EAPOL state machines for the Port that the user of the System has + logged off. + + The UserLogoff() function notifies the EAPOL state machines for the Port. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + + @retval EFI_SUCCESS The Port is notified successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_USER_LOGOFF)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This + ); + +/** + Read the status of the Supplicant PAE state machine for the Port, including the + current state and the configuration of the operational parameters. + + The GetSupplicantStatus() function reads the status of the Supplicant PAE state + machine for the Port, including the current state CurrentState and the configuration + of the operational parameters Configuration. The configuration of the operational + parameters is optional. If Configuration is NULL, then reading the configuration + is ignored. The operational parameters in Configuration to be read can also be + specified by Configuration.ValidFieldMask. + + If CurrentState is NULL, then EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + @param[out] CurrentState Returns the current state of the Supplicant PAE + state machine for the Port. + @param[in, out] Configuration Returns the configuration of the operational + parameters of the Supplicant PAE state machine + for the Port as required. This parameter can be + NULL to ignore reading the configuration. + On input, Configuration.ValidFieldMask specifies the + operational parameters to be read. + On output, Configuration returns the configuration + of the required operational parameters. + + @retval EFI_SUCCESS The configuration of the operational parameter + of the Supplicant PAE state machine for the Port + is set successfully. + @retval EFI_INVALID_PARAMETER CurrentState is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATUS)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This, + OUT EFI_EAPOL_SUPPLICANT_PAE_STATE *CurrentState, + IN OUT EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration OPTIONAL + ); + +/** + Set the configuration of the operational parameter of the Supplicant PAE + state machine for the Port. + + The SetSupplicantConfiguration() function sets the configuration of the + operational Parameter of the Supplicant PAE state machine for the Port to + Configuration. The operational parameters in Configuration to be set can be + specified by Configuration.ValidFieldMask. + + If Configuration is NULL, then EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + @param[in] Configuration The desired configuration of the operational + parameters of the Supplicant PAE state machine + for the Port as required. + + @retval EFI_SUCCESS The configuration of the operational parameter + of the Supplicant PAE state machine for the Port + is set successfully. + @retval EFI_INVALID_PARAMETER Configuration is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_SET_SUPPLICANT_CONFIGURATION)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This, + IN EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION *Configuration + ); + +/** + Read the statistical information regarding the operation of the Supplicant + associated with the Port. + + The GetSupplicantStatistics() function reads the statistical information + Statistics regarding the operation of the Supplicant associated with the Port. + + If Statistics is NULL, then EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL + instance that indicates the calling context. + @param[out] Statistics Returns the statistical information regarding the + operation of the Supplicant for the Port. + + @retval EFI_SUCCESS The statistical information regarding the operation + of the Supplicant for the Port is read successfully. + @retval EFI_INVALID_PARAMETER Statistics is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_GET_SUPPLICANT_STATISTICS)( + IN EFI_EAP_MANAGEMENT_PROTOCOL *This, + OUT EFI_EAPOL_SUPPLICANT_PAE_STATISTICS *Statistics + ); + +/// +/// EFI_EAP_MANAGEMENT_PROTOCOL +/// is used to control, configure and monitor EAPOL state machine on +/// a Port. EAPOL state machine is built on a per-Port basis. Herein, +/// a Port means a NIC. For the details of EAPOL, please refer to +/// IEEE 802.1x specification. +/// +struct _EFI_EAP_MANAGEMENT_PROTOCOL { + EFI_EAP_GET_SYSTEM_CONFIGURATION GetSystemConfiguration; + EFI_EAP_SET_SYSTEM_CONFIGURATION SetSystemConfiguration; + EFI_EAP_INITIALIZE_PORT InitializePort; + EFI_EAP_USER_LOGON UserLogon; + EFI_EAP_USER_LOGOFF UserLogoff; + EFI_EAP_GET_SUPPLICANT_STATUS GetSupplicantStatus; + EFI_EAP_SET_SUPPLICANT_CONFIGURATION SetSupplicantConfiguration; + EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics; +}; + +extern EFI_GUID gEfiEapManagementProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement2.h new file mode 100644 index 0000000000..faae59116f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EapManagement2.h @@ -0,0 +1,81 @@ +/** @file + This file defines the EFI EAP Management2 protocol. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_EAP_MANAGEMENT2_PROTOCOL_H__ +#define __EFI_EAP_MANAGEMENT2_PROTOCOL_H__ + +#include + +/// +/// This EFI EAP Management2 protocol provides the ability to configure and control EAPOL +/// state machine, and retrieve the information, status and the statistics information of +/// EAPOL state machine. +/// +#define EFI_EAP_MANAGEMENT2_PROTOCOL_GUID \ + { \ + 0x5e93c847, 0x456d, 0x40b3, {0xa6, 0xb4, 0x78, 0xb0, 0xc9, 0xcf, 0x7f, 0x20 } \ + } + +typedef struct _EFI_EAP_MANAGEMENT2_PROTOCOL EFI_EAP_MANAGEMENT2_PROTOCOL; + +/** + Return key generated through EAP process. + + The GetKey() function return the key generated through EAP process, so that the 802.11 + MAC layer driver can use MSK to derive more keys, e.g. PMK (Pairwise Master Key). + + @param[in] This Pointer to the EFI_EAP_MANAGEMENT2_PROTOCOL instance. + @param[in, out] Msk Pointer to MSK (Master Session Key) buffer. + @param[in, out] MskSize MSK buffer size. + @param[in, out] Emsk Pointer to EMSK (Extended Master Session Key) buffer. + @param[in, out] EmskSize EMSK buffer size. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + Msk is NULL. + MskSize is NULL. + Emsk is NULL. + EmskSize is NULL. + @retval EFI_NOT_READY MSK and EMSK are not generated in current session yet. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EAP_GET_KEY) ( + IN EFI_EAP_MANAGEMENT2_PROTOCOL *This, + IN OUT UINT8 *Msk, + IN OUT UINTN *MskSize, + IN OUT UINT8 *Emsk, + IN OUT UINT8 *EmskSize + ); + +/// +/// The EFI_EAP_MANAGEMENT2_PROTOCOL +/// is used to control, configure and monitor EAPOL state machine on a Port, and return +/// information of the Port. EAPOL state machine is built on a per-Port basis. Herein, a +/// Port means a NIC. For the details of EAPOL, please refer to IEEE 802.1x +/// specification. +/// +struct _EFI_EAP_MANAGEMENT2_PROTOCOL { + EFI_EAP_GET_SYSTEM_CONFIGURATION GetSystemConfiguration; + EFI_EAP_SET_SYSTEM_CONFIGURATION SetSystemConfiguration; + EFI_EAP_INITIALIZE_PORT InitializePort; + EFI_EAP_USER_LOGON UserLogon; + EFI_EAP_USER_LOGOFF UserLogoff; + EFI_EAP_GET_SUPPLICANT_STATUS GetSupplicantStatus; + EFI_EAP_SET_SUPPLICANT_CONFIGURATION SetSupplicantConfiguration; + EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics; + EFI_EAP_GET_KEY GetKey; +}; + +extern EFI_GUID gEfiEapManagement2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ebc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ebc.h new file mode 100644 index 0000000000..ff28fcacb2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ebc.h @@ -0,0 +1,308 @@ +/** @file + Describes the protocol interface to the EBC interpreter. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_EBC_PROTOCOL_H__ +#define __EFI_EBC_PROTOCOL_H__ + +#define EFI_EBC_INTERPRETER_PROTOCOL_GUID \ + { \ + 0x13AC6DD1, 0x73D0, 0x11D4, {0xB0, 0x6B, 0x00, 0xAA, 0x00, 0xBD, 0x6D, 0xE7 } \ + } + +// +// Define OPCODES +// +#define OPCODE_BREAK 0x00 +#define OPCODE_JMP 0x01 +#define OPCODE_JMP8 0x02 +#define OPCODE_CALL 0x03 +#define OPCODE_RET 0x04 +#define OPCODE_CMPEQ 0x05 +#define OPCODE_CMPLTE 0x06 +#define OPCODE_CMPGTE 0x07 +#define OPCODE_CMPULTE 0x08 +#define OPCODE_CMPUGTE 0x09 +#define OPCODE_NOT 0x0A +#define OPCODE_NEG 0x0B +#define OPCODE_ADD 0x0C +#define OPCODE_SUB 0x0D +#define OPCODE_MUL 0x0E +#define OPCODE_MULU 0x0F +#define OPCODE_DIV 0x10 +#define OPCODE_DIVU 0x11 +#define OPCODE_MOD 0x12 +#define OPCODE_MODU 0x13 +#define OPCODE_AND 0x14 +#define OPCODE_OR 0x15 +#define OPCODE_XOR 0x16 +#define OPCODE_SHL 0x17 +#define OPCODE_SHR 0x18 +#define OPCODE_ASHR 0x19 +#define OPCODE_EXTNDB 0x1A +#define OPCODE_EXTNDW 0x1B +#define OPCODE_EXTNDD 0x1C +#define OPCODE_MOVBW 0x1D +#define OPCODE_MOVWW 0x1E +#define OPCODE_MOVDW 0x1F +#define OPCODE_MOVQW 0x20 +#define OPCODE_MOVBD 0x21 +#define OPCODE_MOVWD 0x22 +#define OPCODE_MOVDD 0x23 +#define OPCODE_MOVQD 0x24 +#define OPCODE_MOVSNW 0x25 // Move signed natural with word index +#define OPCODE_MOVSND 0x26 // Move signed natural with dword index +// +// #define OPCODE_27 0x27 +// +#define OPCODE_MOVQQ 0x28 // Does this go away? +#define OPCODE_LOADSP 0x29 +#define OPCODE_STORESP 0x2A +#define OPCODE_PUSH 0x2B +#define OPCODE_POP 0x2C +#define OPCODE_CMPIEQ 0x2D +#define OPCODE_CMPILTE 0x2E +#define OPCODE_CMPIGTE 0x2F +#define OPCODE_CMPIULTE 0x30 +#define OPCODE_CMPIUGTE 0x31 +#define OPCODE_MOVNW 0x32 +#define OPCODE_MOVND 0x33 +// +// #define OPCODE_34 0x34 +// +#define OPCODE_PUSHN 0x35 +#define OPCODE_POPN 0x36 +#define OPCODE_MOVI 0x37 +#define OPCODE_MOVIN 0x38 +#define OPCODE_MOVREL 0x39 + +// +// Bit masks for opcode encodings +// +#define OPCODE_M_OPCODE 0x3F // bits of interest for first level decode +#define OPCODE_M_IMMDATA 0x80 +#define OPCODE_M_IMMDATA64 0x40 +#define OPCODE_M_64BIT 0x40 // for CMP +#define OPCODE_M_RELADDR 0x10 // for CALL instruction +#define OPCODE_M_CMPI32_DATA 0x80 // for CMPI +#define OPCODE_M_CMPI64 0x40 // for CMPI 32 or 64 bit comparison +#define OPERAND_M_MOVIN_N 0x80 +#define OPERAND_M_CMPI_INDEX 0x10 + +// +// Masks for instructions that encode presence of indexes for operand1 and/or +// operand2. +// +#define OPCODE_M_IMMED_OP1 0x80 +#define OPCODE_M_IMMED_OP2 0x40 + +// +// Bit masks for operand encodings +// +#define OPERAND_M_INDIRECT1 0x08 +#define OPERAND_M_INDIRECT2 0x80 +#define OPERAND_M_OP1 0x07 +#define OPERAND_M_OP2 0x70 + +// +// Masks for data manipulation instructions +// +#define DATAMANIP_M_64 0x40 // 64-bit width operation +#define DATAMANIP_M_IMMDATA 0x80 + +// +// For MOV instructions, need a mask for the opcode when immediate +// data applies to R2. +// +#define OPCODE_M_IMMED_OP2 0x40 + +// +// The MOVI/MOVIn instructions use bit 6 of operands byte to indicate +// if an index is present. Then bits 4 and 5 are used to indicate the width +// of the move. +// +#define MOVI_M_IMMDATA 0x40 +#define MOVI_M_DATAWIDTH 0xC0 +#define MOVI_DATAWIDTH16 0x40 +#define MOVI_DATAWIDTH32 0x80 +#define MOVI_DATAWIDTH64 0xC0 +#define MOVI_M_MOVEWIDTH 0x30 +#define MOVI_MOVEWIDTH8 0x00 +#define MOVI_MOVEWIDTH16 0x10 +#define MOVI_MOVEWIDTH32 0x20 +#define MOVI_MOVEWIDTH64 0x30 + +// +// Masks for CALL instruction encodings +// +#define OPERAND_M_RELATIVE_ADDR 0x10 +#define OPERAND_M_NATIVE_CALL 0x20 + +// +// Masks for decoding push/pop instructions +// +#define PUSHPOP_M_IMMDATA 0x80 // opcode bit indicating immediate data +#define PUSHPOP_M_64 0x40 // opcode bit indicating 64-bit operation +// +// Mask for operand of JMP instruction +// +#define JMP_M_RELATIVE 0x10 +#define JMP_M_CONDITIONAL 0x80 +#define JMP_M_CS 0x40 + +// +// Macros to determine if a given operand is indirect +// +#define OPERAND1_INDIRECT(op) ((op) & OPERAND_M_INDIRECT1) +#define OPERAND2_INDIRECT(op) ((op) & OPERAND_M_INDIRECT2) + +// +// Macros to extract the operands from second byte of instructions +// +#define OPERAND1_REGNUM(op) ((op) & OPERAND_M_OP1) +#define OPERAND2_REGNUM(op) (((op) & OPERAND_M_OP2) >> 4) + +#define OPERAND1_CHAR(op) ('0' + OPERAND1_REGNUM (op)) +#define OPERAND2_CHAR(op) ('0' + OPERAND2_REGNUM (op)) + +// +// Condition masks usually for byte 1 encodings of code +// +#define CONDITION_M_CONDITIONAL 0x80 +#define CONDITION_M_CS 0x40 + +/// +/// Protocol Guid Name defined in spec. +/// +#define EFI_EBC_PROTOCOL_GUID EFI_EBC_INTERPRETER_PROTOCOL_GUID + +/// +/// Define for forward reference. +/// +typedef struct _EFI_EBC_PROTOCOL EFI_EBC_PROTOCOL; + +/** + Creates a thunk for an EBC entry point, returning the address of the thunk. + + A PE32+ EBC image, like any other PE32+ image, contains an optional header that specifies the + entry point for image execution. However, for EBC images, this is the entry point of EBC + instructions, so is not directly executable by the native processor. Therefore, when an EBC image is + loaded, the loader must call this service to get a pointer to native code (thunk) that can be executed, + which will invoke the interpreter to begin execution at the original EBC entry point. + + @param This A pointer to the EFI_EBC_PROTOCOL instance. + @param ImageHandle Handle of image for which the thunk is being created. + @param EbcEntryPoint Address of the actual EBC entry point or protocol service the thunk should call. + @param Thunk Returned pointer to a thunk created. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Image entry point is not 2-byte aligned. + @retval EFI_OUT_OF_RESOURCES Memory could not be allocated for the thunk. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EBC_CREATE_THUNK)( + IN EFI_EBC_PROTOCOL *This, + IN EFI_HANDLE ImageHandle, + IN VOID *EbcEntryPoint, + OUT VOID **Thunk + ); + +/** + Called prior to unloading an EBC image from memory. + + This function is called after an EBC image has exited, but before the image is actually unloaded. It + is intended to provide the interpreter with the opportunity to perform any cleanup that may be + necessary as a result of loading and executing the image. + + @param This A pointer to the EFI_EBC_PROTOCOL instance. + @param ImageHandle Image handle of the EBC image that is being unloaded from memory. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Image handle is not recognized as belonging + to an EBC image that has been executed. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EBC_UNLOAD_IMAGE)( + IN EFI_EBC_PROTOCOL *This, + IN EFI_HANDLE ImageHandle + ); + +/** + This is the prototype for the Flush callback routine. A pointer to a routine + of this type is passed to the EBC EFI_EBC_REGISTER_ICACHE_FLUSH protocol service. + + @param Start The beginning physical address to flush from the processor's instruction cache. + @param Length The number of bytes to flush from the processor's instruction cache. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EBC_ICACHE_FLUSH)( + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length + ); + +/** + Registers a callback function that the EBC interpreter calls to flush + the processor instruction cache following creation of thunks. + + @param This A pointer to the EFI_EBC_PROTOCOL instance. + @param Flush Pointer to a function of type EBC_ICACH_FLUSH. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EBC_REGISTER_ICACHE_FLUSH)( + IN EFI_EBC_PROTOCOL *This, + IN EBC_ICACHE_FLUSH Flush + ); + +/** + Called to get the version of the interpreter. + + This function is called to get the version of the loaded EBC interpreter. The value and format of the + returned version is identical to that returned by the EBC BREAK 1 instruction. + + @param This A pointer to the EFI_EBC_PROTOCOL instance. + @param Version Pointer to where to store the returned version of the interpreter. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER Version pointer is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EBC_GET_VERSION)( + IN EFI_EBC_PROTOCOL *This, + IN OUT UINT64 *Version + ); + +/// +/// The EFI EBC protocol provides services to load and execute EBC images, which will typically be +/// loaded into option ROMs. The image loader will load the EBC image, perform standard relocations, +/// and invoke the CreateThunk() service to create a thunk for the EBC image's entry point. The +/// image can then be run using the standard EFI start image services. +/// +struct _EFI_EBC_PROTOCOL { + EFI_EBC_CREATE_THUNK CreateThunk; + EFI_EBC_UNLOAD_IMAGE UnloadImage; + EFI_EBC_REGISTER_ICACHE_FLUSH RegisterICacheFlush; + EFI_EBC_GET_VERSION GetVersion; +}; + +// +// Extern the global EBC protocol GUID +// +extern EFI_GUID gEfiEbcProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidActive.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidActive.h new file mode 100644 index 0000000000..531d077334 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidActive.h @@ -0,0 +1,46 @@ +/** @file + EDID Active Protocol from the UEFI 2.0 specification. + + Placed on the video output device child handle that is actively displaying output. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EDID_ACTIVE_H__ +#define __EDID_ACTIVE_H__ + +#define EFI_EDID_ACTIVE_PROTOCOL_GUID \ + { \ + 0xbd8c1056, 0x9f36, 0x44ec, {0x92, 0xa8, 0xa6, 0x33, 0x7f, 0x81, 0x79, 0x86 } \ + } + +/// +/// This protocol contains the EDID information for an active video output device. This is either the +/// EDID information retrieved from the EFI_EDID_OVERRIDE_PROTOCOL if an override is +/// available, or an identical copy of the EDID information from the +/// EFI_EDID_DISCOVERED_PROTOCOL if no overrides are available. +/// +typedef struct { + /// + /// The size, in bytes, of the Edid buffer. 0 if no EDID information + /// is available from the video output device. Otherwise, it must be a + /// minimum of 128 bytes. + /// + UINT32 SizeOfEdid; + + /// + /// A pointer to a read-only array of bytes that contains the EDID + /// information for an active video output device. This pointer is + /// NULL if no EDID information is available for the video output + /// device. The minimum size of a valid Edid buffer is 128 bytes. + /// EDID information is defined in the E-EDID EEPROM + /// specification published by VESA (www.vesa.org). + /// + UINT8 *Edid; +} EFI_EDID_ACTIVE_PROTOCOL; + +extern EFI_GUID gEfiEdidActiveProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidDiscovered.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidDiscovered.h new file mode 100644 index 0000000000..4975564adc --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidDiscovered.h @@ -0,0 +1,44 @@ +/** @file + EDID Discovered Protocol from the UEFI 2.0 specification. + + This protocol is placed on the video output device child handle. It represents + the EDID information being used for the output device represented by the child handle. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EDID_DISCOVERED_H__ +#define __EDID_DISCOVERED_H__ + +#define EFI_EDID_DISCOVERED_PROTOCOL_GUID \ + { \ + 0x1c0c34f6, 0xd380, 0x41fa, {0xa0, 0x49, 0x8a, 0xd0, 0x6c, 0x1a, 0x66, 0xaa } \ + } + +/// +/// This protocol contains the EDID information retrieved from a video output device. +/// +typedef struct { + /// + /// The size, in bytes, of the Edid buffer. 0 if no EDID information + /// is available from the video output device. Otherwise, it must be a + /// minimum of 128 bytes. + /// + UINT32 SizeOfEdid; + + /// + /// A pointer to a read-only array of bytes that contains the EDID + /// information for an active video output device. This pointer is + /// NULL if no EDID information is available for the video output + /// device. The minimum size of a valid Edid buffer is 128 bytes. + /// EDID information is defined in the E-EDID EEPROM + /// specification published by VESA (www.vesa.org). + /// + UINT8 *Edid; +} EFI_EDID_DISCOVERED_PROTOCOL; + +extern EFI_GUID gEfiEdidDiscoveredProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidOverride.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidOverride.h new file mode 100644 index 0000000000..6c7c082eab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EdidOverride.h @@ -0,0 +1,61 @@ +/** @file + EDID Override Protocol from the UEFI 2.0 specification. + + Allow platform to provide EDID information to the producer of the Graphics Output + protocol. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EDID_OVERRIDE_H__ +#define __EDID_OVERRIDE_H__ + +#define EFI_EDID_OVERRIDE_PROTOCOL_GUID \ + { \ + 0x48ecb431, 0xfb72, 0x45c0, {0xa9, 0x22, 0xf4, 0x58, 0xfe, 0x4, 0xb, 0xd5 } \ + } + +typedef struct _EFI_EDID_OVERRIDE_PROTOCOL EFI_EDID_OVERRIDE_PROTOCOL; + +#define EFI_EDID_OVERRIDE_DONT_OVERRIDE 0x01 +#define EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG 0x02 + +/** + Returns policy information and potentially a replacement EDID for the specified video output device. + + @param This The EFI_EDID_OVERRIDE_PROTOCOL instance. + @param ChildHandle A child handle produced by the Graphics Output EFI + driver that represents a video output device. + @param Attributes The attributes associated with ChildHandle video output device. + @param EdidSize A pointer to the size, in bytes, of the Edid buffer. + @param Edid A pointer to callee allocated buffer that contains the EDID that + should be used for ChildHandle. A value of NULL + represents no EDID override for ChildHandle. + + @retval EFI_SUCCESS Valid overrides returned for ChildHandle. + @retval EFI_UNSUPPORTED ChildHandle has no overrides. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID)( + IN EFI_EDID_OVERRIDE_PROTOCOL *This, + IN EFI_HANDLE *ChildHandle, + OUT UINT32 *Attributes, + OUT UINTN *EdidSize, + OUT UINT8 **Edid + ); + +/// +/// This protocol is produced by the platform to allow the platform to provide +/// EDID information to the producer of the Graphics Output protocol. +/// +struct _EFI_EDID_OVERRIDE_PROTOCOL { + EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID GetEdid; +}; + +extern EFI_GUID gEfiEdidOverrideProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EraseBlock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EraseBlock.h new file mode 100644 index 0000000000..bfedcf32c2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/EraseBlock.h @@ -0,0 +1,99 @@ +/** @file + This file defines the EFI Erase Block Protocol. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.6 + +**/ + +#ifndef __EFI_ERASE_BLOCK_PROTOCOL_H__ +#define __EFI_ERASE_BLOCK_PROTOCOL_H__ + +#define EFI_ERASE_BLOCK_PROTOCOL_GUID \ + { \ + 0x95a9a93e, 0xa86e, 0x4926, { 0xaa, 0xef, 0x99, 0x18, 0xe7, 0x72, 0xd9, 0x87 } \ + } + +typedef struct _EFI_ERASE_BLOCK_PROTOCOL EFI_ERASE_BLOCK_PROTOCOL; + +#define EFI_ERASE_BLOCK_PROTOCOL_REVISION ((2<<16) | (60)) + +/// +/// EFI_ERASE_BLOCK_TOKEN +/// +typedef struct { + // + // If Event is NULL, then blocking I/O is performed. If Event is not NULL and + // non-blocking I/O is supported, then non-blocking I/O is performed, and + // Event will be signaled when the erase request is completed. + // + EFI_EVENT Event; + // + // Defines whether the signaled event encountered an error. + // + EFI_STATUS TransactionStatus; +} EFI_ERASE_BLOCK_TOKEN; + +/** + Erase a specified number of device blocks. + + @param[in] This Indicates a pointer to the calling context. + @param[in] MediaId The media ID that the erase request is for. + @param[in] LBA The starting logical block address to be + erased. The caller is responsible for erasing + only legitimate locations. + @param[in, out] Token A pointer to the token associated with the + transaction. + @param[in] Size The size in bytes to be erased. This must be + a multiple of the physical block size of the + device. + + @retval EFI_SUCCESS The erase request was queued if Event is not + NULL. The data was erased correctly to the + device if the Event is NULL.to the device. + @retval EFI_WRITE_PROTECTED The device cannot be erased due to write + protection. + @retval EFI_DEVICE_ERROR The device reported an error while attempting + to perform the erase operation. + @retval EFI_INVALID_PARAMETER The erase request contains LBAs that are not + valid. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BLOCK_ERASE) ( + IN EFI_ERASE_BLOCK_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA LBA, + IN OUT EFI_ERASE_BLOCK_TOKEN *Token, + IN UINTN Size + ); + +/// +/// The EFI Erase Block Protocol provides the ability for a device to expose +/// erase functionality. This optional protocol is installed on the same handle +/// as the EFI_BLOCK_IO_PROTOCOL or EFI_BLOCK_IO2_PROTOCOL. +/// +struct _EFI_ERASE_BLOCK_PROTOCOL { + // + // The revision to which the EFI_ERASE_BLOCK_PROTOCOL adheres. All future + // revisions must be backwards compatible. If a future version is not + // backwards compatible, it is not the same GUID. + // + UINT64 Revision; + // + // Returns the erase length granularity as a number of logical blocks. A + // value of 1 means the erase granularity is one logical block. + // + UINT32 EraseLengthGranularity; + EFI_BLOCK_ERASE EraseBlocks; +}; + +extern EFI_GUID gEfiEraseBlockProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareManagement.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareManagement.h new file mode 100644 index 0000000000..d998b5738e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareManagement.h @@ -0,0 +1,564 @@ +/** @file + UEFI Firmware Management Protocol definition + Firmware Management Protocol provides an abstraction for device to provide firmware + management support. The base requirements for managing device firmware images include + identifying firmware image revision level and programming the image into the device. + + GetImageInfo() is the only required function. GetImage(), SetImage(), + CheckImage(), GetPackageInfo(), and SetPackageInfo() shall return + EFI_UNSUPPORTED if not supported by the driver. + + Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2014, Hewlett-Packard Development Company, L.P.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.3 + +**/ + +#ifndef __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__ +#define __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__ + + +#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \ + { \ + 0x86c77a67, 0xb97, 0x4633, {0xa1, 0x87, 0x49, 0x10, 0x4d, 0x6, 0x85, 0xc7 } \ + } + +typedef struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL EFI_FIRMWARE_MANAGEMENT_PROTOCOL; + +/// +/// Dependency Expression Opcode +/// +#define EFI_FMP_DEP_PUSH_GUID 0x00 +#define EFI_FMP_DEP_PUSH_VERSION 0x01 +#define EFI_FMP_DEP_VERSION_STR 0x02 +#define EFI_FMP_DEP_AND 0x03 +#define EFI_FMP_DEP_OR 0x04 +#define EFI_FMP_DEP_NOT 0x05 +#define EFI_FMP_DEP_TRUE 0x06 +#define EFI_FMP_DEP_FALSE 0x07 +#define EFI_FMP_DEP_EQ 0x08 +#define EFI_FMP_DEP_GT 0x09 +#define EFI_FMP_DEP_GTE 0x0A +#define EFI_FMP_DEP_LT 0x0B +#define EFI_FMP_DEP_LTE 0x0C +#define EFI_FMP_DEP_END 0x0D + +/// +/// Image Attribute - Dependency +/// +typedef struct { + UINT8 Dependencies[1]; +} EFI_FIRMWARE_IMAGE_DEP; + +/// +/// EFI_FIRMWARE_IMAGE_DESCRIPTOR +/// +typedef struct { + /// + /// A unique number identifying the firmware image within the device. The number is + /// between 1 and DescriptorCount. + /// + UINT8 ImageIndex; + /// + /// A unique GUID identifying the firmware image type. + /// + EFI_GUID ImageTypeId; + /// + /// A unique number identifying the firmware image. + /// + UINT64 ImageId; + /// + /// A pointer to a null-terminated string representing the firmware image name. + /// + CHAR16 *ImageIdName; + /// + /// Identifies the version of the device firmware. The format is vendor specific and new + /// version must have a greater value than an old version. + /// + UINT32 Version; + /// + /// A pointer to a null-terminated string representing the firmware image version name. + /// + CHAR16 *VersionName; + /// + /// Size of the image in bytes. If size=0, then only ImageIndex and ImageTypeId are valid. + /// + UINTN Size; + /// + /// Image attributes that are supported by this device. See 'Image Attribute Definitions' + /// for possible returned values of this parameter. A value of 1 indicates the attribute is + /// supported and the current setting value is indicated in AttributesSetting. A + /// value of 0 indicates the attribute is not supported and the current setting value in + /// AttributesSetting is meaningless. + /// + UINT64 AttributesSupported; + /// + /// Image attributes. See 'Image Attribute Definitions' for possible returned values of + /// this parameter. + /// + UINT64 AttributesSetting; + /// + /// Image compatibilities. See 'Image Compatibility Definitions' for possible returned + /// values of this parameter. + /// + UINT64 Compatibilities; + /// + /// Describes the lowest ImageDescriptor version that the device will accept. Only + /// present in version 2 or higher. + /// + UINT32 LowestSupportedImageVersion; + /// + /// Describes the version that was last attempted to update. If no update attempted the + /// value will be 0. If the update attempted was improperly formatted and no version + /// number was available then the value will be zero. Only present in version 3 or higher. + UINT32 LastAttemptVersion; + /// + /// Describes the status that was last attempted to update. If no update has been attempted + /// the value will be LAST_ATTEMPT_STATUS_SUCCESS. Only present in version 3 or higher. + /// + UINT32 LastAttemptStatus; + /// + /// An optional number to identify the unique hardware instance within the system for + /// devices that may have multiple instances (Example: a plug in pci network card). This + /// number must be unique within the namespace of the ImageTypeId GUID and + /// ImageIndex. For FMP instances that have multiple descriptors for a single + /// hardware instance, all descriptors must have the same HardwareInstance value. + /// This number must be consistent between boots and should be based on some sort of + /// hardware identified unique id (serial number, etc) whenever possible. If a hardware + /// based number is not available the FMP provider may use some other characteristic + /// such as device path, bus/dev/function, slot num, etc for generating the + /// HardwareInstance. For implementations that will never have more than one + /// instance a zero can be used. A zero means the FMP provider is not able to determine a + /// unique hardware instance number or a hardware instance number is not needed. Only + /// present in version 3 or higher. + /// + UINT64 HardwareInstance; + EFI_FIRMWARE_IMAGE_DEP *Dependencies; +} EFI_FIRMWARE_IMAGE_DESCRIPTOR; + + +// +// Image Attribute Definitions +// +/// +/// The attribute IMAGE_ATTRIBUTE_IMAGE_UPDATABLE indicates this device supports firmware +/// image update. +/// +#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001 +/// +/// The attribute IMAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is required +/// for the new firmware image to take effect after a firmware update. The device is the device hosting +/// the firmware image. +/// +#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002 +/// +/// The attribute IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication is +/// required to perform the following image operations: GetImage(), SetImage(), and +/// CheckImage(). See 'Image Attribute - Authentication'. +/// +#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004 +/// +/// The attribute IMAGE_ATTRIBUTE_IN_USE indicates the current state of the firmware image. +/// This distinguishes firmware images in a device that supports redundant images. +/// +#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008 +/// +/// The attribute IMAGE_ATTRIBUTE_UEFI_IMAGE indicates that this image is an EFI compatible image. +/// +#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010 +/// +/// The attribute IMAGE_ATTRIBUTE_DEPENDENCY indicates that there is an EFI_FIRMWARE_IMAGE_DEP +/// section associated with the image. +/// +#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020 + + +// +// Image Compatibility Definitions +// +/// +/// Values from 0x0000000000000002 thru 0x000000000000FFFF are reserved for future assignments. +/// Values from 0x0000000000010000 thru 0xFFFFFFFFFFFFFFFF are used by firmware vendor for +/// compatibility check. +/// +#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001 + +/// +/// Descriptor Version exposed by GetImageInfo() function +/// +#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4 + + +/// +/// Image Attribute - Authentication Required +/// +typedef struct { + /// + /// It is included in the signature of AuthInfo. It is used to ensure freshness/no replay. + /// It is incremented during each firmware image operation. + /// + UINT64 MonotonicCount; + /// + /// Provides the authorization for the firmware image operations. It is a signature across + /// the image data and the Monotonic Count value. Caller uses the private key that is + /// associated with a public key that has been provisioned via the key exchange. + /// Because this is defined as a signature, WIN_CERTIFICATE_UEFI_GUID.CertType must + /// be EFI_CERT_TYPE_PKCS7_GUID. + /// + WIN_CERTIFICATE_UEFI_GUID AuthInfo; +} EFI_FIRMWARE_IMAGE_AUTHENTICATION; + + +// +// ImageUpdatable Definitions +// +/// +/// IMAGE_UPDATABLE_VALID indicates SetImage() will accept the new image and update the +/// device with the new image. The version of the new image could be higher or lower than +/// the current image. SetImage VendorCode is optional but can be used for vendor +/// specific action. +/// +#define IMAGE_UPDATABLE_VALID 0x0000000000000001 +/// +/// IMAGE_UPDATABLE_INVALID indicates SetImage() will reject the new image. No additional +/// information is provided for the rejection. +/// +#define IMAGE_UPDATABLE_INVALID 0x0000000000000002 +/// +/// IMAGE_UPDATABLE_INVALID_TYPE indicates SetImage() will reject the new image. The +/// rejection is due to the new image is not a firmware image recognized for this device. +/// +#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004 +/// +/// IMAGE_UPDATABLE_INVALID_OLD indicates SetImage() will reject the new image. The +/// rejection is due to the new image version is older than the current firmware image +/// version in the device. The device firmware update policy does not support firmware +/// version downgrade. +/// +#define IMAGE_UPDATABLE_INVALID_OLD 0x0000000000000008 +/// +/// IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE indicates SetImage() will accept and update +/// the new image only if a correct VendorCode is provided or else image would be +/// rejected and SetImage will return appropriate error. +/// +#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0000000000000010 + + +// +// Package Attribute Definitions +// +/// +/// The attribute PACKAGE_ATTRIBUTE_VERSION_UPDATABLE indicates this device supports the +/// update of the firmware package version. +/// +#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001 +/// +/// The attribute PACKAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is +/// required for the new package info to take effect after an update. +/// +#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002 +/// +/// The attribute PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication +/// is required to update the package info. +/// +#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004 + +/** + Callback function to report the process of the firmware updating. + + @param[in] Completion A value between 1 and 100 indicating the current completion + progress of the firmware update. Completion progress is + reported as from 1 to 100 percent. A value of 0 is used by + the driver to indicate that progress reporting is not supported. + + @retval EFI_SUCCESS SetImage() continues to do the callback if supported. + @retval other SetImage() discontinues the callback and completes + the update and returns. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS)( + IN UINTN Completion + ); + +/** + Returns information about the current firmware image(s) of the device. + + This function allows a copy of the current firmware image to be created and saved. + The saved copy could later been used, for example, in firmware image recovery or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[in, out] ImageInfoSize A pointer to the size, in bytes, of the ImageInfo buffer. + On input, this is the size of the buffer allocated by the caller. + On output, it is the size of the buffer returned by the firmware + if the buffer was large enough, or the size of the buffer needed + to contain the image(s) information if the buffer was too small. + @param[in, out] ImageInfo A pointer to the buffer in which firmware places the current image(s) + information. The information is an array of EFI_FIRMWARE_IMAGE_DESCRIPTORs. + @param[out] DescriptorVersion A pointer to the location in which firmware returns the version number + associated with the EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] DescriptorCount A pointer to the location in which firmware returns the number of + descriptors or firmware images within this device. + @param[out] DescriptorSize A pointer to the location in which firmware returns the size, in bytes, + of an individual EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] PackageVersion A version number that represents all the firmware images in the device. + The format is vendor specific and new version must have a greater value + than the old version. If PackageVersion is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE indicates that package version comparison + is to be performed using PackageVersionName. A value of 0xFFFFFFFD indicates + that package version update is in progress. + @param[out] PackageVersionName A pointer to a pointer to a null-terminated string representing the + package version name. The buffer is allocated by this function with + AllocatePool(), and it is the caller's responsibility to free it with a call + to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated with the new image. + @retval EFI_BUFFER_TOO_SMALL The ImageInfo buffer was too small. The current buffer size + needed to hold the image(s) information is returned in ImageInfoSize. + @retval EFI_INVALID_PARAMETER ImageInfoSize is NULL. + @retval EFI_DEVICE_ERROR Valid information could not be returned. Possible corrupted image. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN OUT UINTN *ImageInfoSize, + IN OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageInfo, + OUT UINT32 *DescriptorVersion, + OUT UINT8 *DescriptorCount, + OUT UINTN *DescriptorSize, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName + ); + +/** + Retrieves a copy of the current firmware image of the device. + + This function allows a copy of the current firmware image to be created and saved. + The saved copy could later been used, for example, in firmware image recovery or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware image(s) within the device. + The number is between 1 and DescriptorCount. + @param[out] Image Points to the buffer where the current image is copied to. + @param[in, out] ImageSize On entry, points to the size of the buffer pointed to by Image, in bytes. + On return, points to the length of the image, in bytes. + + @retval EFI_SUCCESS The device was successfully updated with the new image. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too small to hold the + image. The current buffer size needed to hold the image is returned + in ImageSize. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_NOT_FOUND The current image is not copied to the buffer. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + OUT VOID *Image, + IN OUT UINTN *ImageSize + ); + +/** + Updates the firmware image of the device. + + This function updates the hardware with the new firmware image. + This function returns EFI_UNSUPPORTED if the firmware image is not updatable. + If the firmware image is updatable, the function should perform the following minimal validations + before proceeding to do the firmware image update. + - Validate the image authentication if image has attribute + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. The function returns + EFI_SECURITY_VIOLATION if the validation fails. + - Validate the image is a supported image for this device. The function returns EFI_ABORTED if + the image is unsupported. The function can optionally provide more detailed information on + why the image is not a supported image. + - Validate the data from VendorCode if not null. Image validation must be performed before + VendorCode data validation. VendorCode data is ignored or considered invalid if image + validation failed. The function returns EFI_ABORTED if the data is invalid. + + VendorCode enables vendor to implement vendor-specific firmware image update policy. Null if + the caller did not specify the policy or use the default policy. As an example, vendor can implement + a policy to allow an option to force a firmware image update when the abort reason is due to the new + firmware image version is older than the current firmware image version or bad image checksum. + Sensitive operations such as those wiping the entire firmware image and render the device to be + non-functional should be encoded in the image itself rather than passed with the VendorCode. + AbortReason enables vendor to have the option to provide a more detailed description of the abort + reason to the caller. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware image(s) within the device. + The number is between 1 and DescriptorCount. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[in] VendorCode This enables vendor to implement vendor-specific firmware image update policy. + Null indicates the caller did not specify the policy or use the default policy. + @param[in] Progress A function used by the driver to report the progress of the firmware update. + @param[out] AbortReason A pointer to a pointer to a null-terminated string providing more + details for the aborted operation. The buffer is allocated by this function + with AllocatePool(), and it is the caller's responsibility to free it with a + call to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated with the new image. + @retval EFI_ABORTED The operation is aborted. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, + OUT CHAR16 **AbortReason + ); + +/** + Checks if the firmware image is valid for the device. + + This function allows firmware update application to validate the firmware image without + invoking the SetImage() first. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware image(s) within the device. + The number is between 1 and DescriptorCount. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[out] ImageUpdatable Indicates if the new image is valid for update. It also provides, + if available, additional information if the image is invalid. + + @retval EFI_SUCCESS The image was successfully checked. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *ImageUpdatable + ); + +/** + Returns information about the firmware package. + + This function returns package information. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[out] PackageVersion A version number that represents all the firmware images in the device. + The format is vendor specific and new version must have a greater value + than the old version. If PackageVersion is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE indicates that package version + comparison is to be performed using PackageVersionName. A value of + 0xFFFFFFFD indicates that package version update is in progress. + @param[out] PackageVersionName A pointer to a pointer to a null-terminated string representing + the package version name. The buffer is allocated by this function with + AllocatePool(), and it is the caller's responsibility to free it with a + call to FreePool(). + @param[out] PackageVersionNameMaxLen The maximum length of package version name if device supports update of + package version name. A value of 0 indicates the device does not support + update of package version name. Length is the number of Unicode characters, + including the terminating null character. + @param[out] AttributesSupported Package attributes that are supported by this device. See 'Package Attribute + Definitions' for possible returned values of this parameter. A value of 1 + indicates the attribute is supported and the current setting value is + indicated in AttributesSetting. A value of 0 indicates the attribute is not + supported and the current setting value in AttributesSetting is meaningless. + @param[out] AttributesSetting Package attributes. See 'Package Attribute Definitions' for possible returned + values of this parameter + + @retval EFI_SUCCESS The package information was successfully returned. + @retval EFI_UNSUPPORTED The operation is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName, + OUT UINT32 *PackageVersionNameMaxLen, + OUT UINT64 *AttributesSupported, + OUT UINT64 *AttributesSetting + ); + +/** + Updates information about the firmware package. + + This function updates package information. + This function returns EFI_UNSUPPORTED if the package information is not updatable. + VendorCode enables vendor to implement vendor-specific package information update policy. + Null if the caller did not specify this policy or use the default policy. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance. + @param[in] Image Points to the authentication image. + Null if authentication is not required. + @param[in] ImageSize Size of the authentication image in bytes. + 0 if authentication is not required. + @param[in] VendorCode This enables vendor to implement vendor-specific firmware + image update policy. + Null indicates the caller did not specify this policy or use + the default policy. + @param[in] PackageVersion The new package version. + @param[in] PackageVersionName A pointer to the new null-terminated Unicode string representing + the package version name. + The string length is equal to or less than the value returned in + PackageVersionNameMaxLen. + + @retval EFI_SUCCESS The device was successfully updated with the new package + information. + @retval EFI_INVALID_PARAMETER The PackageVersionName length is longer than the value + returned in PackageVersionNameMaxLen. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO)( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN UINT32 PackageVersion, + IN CONST CHAR16 *PackageVersionName + ); + +/// +/// EFI_FIRMWARE_MANAGEMENT_PROTOCOL +/// The protocol for managing firmware provides the following services. +/// - Get the attributes of the current firmware image. Attributes include revision level. +/// - Get a copy of the current firmware image. As an example, this service could be used by a +/// management application to facilitate a firmware roll-back. +/// - Program the device with a firmware image supplied by the user. +/// - Label all the firmware images within a device with a single version. +/// +struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL { + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO GetImageInfo; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE GetImage; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE SetImage; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE CheckImage; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO GetPackageInfo; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO SetPackageInfo; +}; + +extern EFI_GUID gEfiFirmwareManagementProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolume2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolume2.h new file mode 100644 index 0000000000..cc52ecc794 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolume2.h @@ -0,0 +1,756 @@ +/** @file + The Firmware Volume Protocol provides file-level access to the firmware volume. + Each firmware volume driver must produce an instance of the + Firmware Volume Protocol if the firmware volume is to be visible to + the system during the DXE phase. The Firmware Volume Protocol also provides + mechanisms for determining and modifying some attributes of the firmware volume. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: PI + Version 1.00. + +**/ + +#ifndef __FIRMWARE_VOLUME2_H__ +#define __FIRMWARE_VOLUME2_H__ + +#define EFI_FIRMWARE_VOLUME2_PROTOCOL_GUID \ + { 0x220e73b6, 0x6bdb, 0x4413, { 0x84, 0x5, 0xb9, 0x74, 0xb1, 0x8, 0x61, 0x9a } } + +typedef struct _EFI_FIRMWARE_VOLUME2_PROTOCOL EFI_FIRMWARE_VOLUME2_PROTOCOL; + + +/// +/// EFI_FV_ATTRIBUTES +/// +typedef UINT64 EFI_FV_ATTRIBUTES; + +// +// EFI_FV_ATTRIBUTES bit definitions +// +// EFI_FV_ATTRIBUTES bit semantics +#define EFI_FV2_READ_DISABLE_CAP 0x0000000000000001ULL +#define EFI_FV2_READ_ENABLE_CAP 0x0000000000000002ULL +#define EFI_FV2_READ_STATUS 0x0000000000000004ULL +#define EFI_FV2_WRITE_DISABLE_CAP 0x0000000000000008ULL +#define EFI_FV2_WRITE_ENABLE_CAP 0x0000000000000010ULL +#define EFI_FV2_WRITE_STATUS 0x0000000000000020ULL +#define EFI_FV2_LOCK_CAP 0x0000000000000040ULL +#define EFI_FV2_LOCK_STATUS 0x0000000000000080ULL +#define EFI_FV2_WRITE_POLICY_RELIABLE 0x0000000000000100ULL +#define EFI_FV2_READ_LOCK_CAP 0x0000000000001000ULL +#define EFI_FV2_READ_LOCK_STATUS 0x0000000000002000ULL +#define EFI_FV2_WRITE_LOCK_CAP 0x0000000000004000ULL +#define EFI_FV2_WRITE_LOCK_STATUS 0x0000000000008000ULL +#define EFI_FV2_ALIGNMENT 0x00000000001F0000ULL +#define EFI_FV2_ALIGNMENT_1 0x0000000000000000ULL +#define EFI_FV2_ALIGNMENT_2 0x0000000000010000ULL +#define EFI_FV2_ALIGNMENT_4 0x0000000000020000ULL +#define EFI_FV2_ALIGNMENT_8 0x0000000000030000ULL +#define EFI_FV2_ALIGNMENT_16 0x0000000000040000ULL +#define EFI_FV2_ALIGNMENT_32 0x0000000000050000ULL +#define EFI_FV2_ALIGNMENT_64 0x0000000000060000ULL +#define EFI_FV2_ALIGNMENT_128 0x0000000000070000ULL +#define EFI_FV2_ALIGNMENT_256 0x0000000000080000ULL +#define EFI_FV2_ALIGNMENT_512 0x0000000000090000ULL +#define EFI_FV2_ALIGNMENT_1K 0x00000000000A0000ULL +#define EFI_FV2_ALIGNMENT_2K 0x00000000000B0000ULL +#define EFI_FV2_ALIGNMENT_4K 0x00000000000C0000ULL +#define EFI_FV2_ALIGNMENT_8K 0x00000000000D0000ULL +#define EFI_FV2_ALIGNMENT_16K 0x00000000000E0000ULL +#define EFI_FV2_ALIGNMENT_32K 0x00000000000F0000ULL +#define EFI_FV2_ALIGNMENT_64K 0x0000000000100000ULL +#define EFI_FV2_ALIGNMENT_128K 0x0000000000110000ULL +#define EFI_FV2_ALIGNMENT_256K 0x0000000000120000ULL +#define EFI_FV2_ALIGNMENT_512K 0x0000000000130000ULL +#define EFI_FV2_ALIGNMENT_1M 0x0000000000140000ULL +#define EFI_FV2_ALIGNMENT_2M 0x0000000000150000ULL +#define EFI_FV2_ALIGNMENT_4M 0x0000000000160000ULL +#define EFI_FV2_ALIGNMENT_8M 0x0000000000170000ULL +#define EFI_FV2_ALIGNMENT_16M 0x0000000000180000ULL +#define EFI_FV2_ALIGNMENT_32M 0x0000000000190000ULL +#define EFI_FV2_ALIGNMENT_64M 0x00000000001A0000ULL +#define EFI_FV2_ALIGNMENT_128M 0x00000000001B0000ULL +#define EFI_FV2_ALIGNMENT_256M 0x00000000001C0000ULL +#define EFI_FV2_ALIGNMENT_512M 0x00000000001D0000ULL +#define EFI_FV2_ALIGNMENT_1G 0x00000000001E0000ULL +#define EFI_FV2_ALIGNMENT_2G 0x00000000001F0000ULL + +/** + Returns the attributes and current settings of the firmware volume. + + Because of constraints imposed by the underlying firmware + storage, an instance of the Firmware Volume Protocol may not + be to able to support all possible variations of this + architecture. These constraints and the current state of the + firmware volume are exposed to the caller using the + GetVolumeAttributes() function. GetVolumeAttributes() is + callable only from TPL_NOTIFY and below. Behavior of + GetVolumeAttributes() at any EFI_TPL above TPL_NOTIFY is + undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param FvAttributes Pointer to an EFI_FV_ATTRIBUTES in which + the attributes and current settings are + returned. + + + @retval EFI_SUCCESS The firmware volume attributes were + returned. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_GET_ATTRIBUTES)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + OUT EFI_FV_ATTRIBUTES *FvAttributes +); + + +/** + Modifies the current settings of the firmware volume according to the input parameter. + + The SetVolumeAttributes() function is used to set configurable + firmware volume attributes. Only EFI_FV_READ_STATUS, + EFI_FV_WRITE_STATUS, and EFI_FV_LOCK_STATUS may be modified, and + then only in accordance with the declared capabilities. All + other bits of FvAttributes are ignored on input. On successful + return, all bits of *FvAttributes are valid and it contains the + completed EFI_FV_ATTRIBUTES for the volume. To modify an + attribute, the corresponding status bit in the EFI_FV_ATTRIBUTES + is set to the desired value on input. The EFI_FV_LOCK_STATUS bit + does not affect the ability to read or write the firmware + volume. Rather, once the EFI_FV_LOCK_STATUS bit is set, it + prevents further modification to all the attribute bits. + SetVolumeAttributes() is callable only from TPL_NOTIFY and + below. Behavior of SetVolumeAttributes() at any EFI_TPL above + TPL_NOTIFY is undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param FvAttributes On input, FvAttributes is a pointer to + an EFI_FV_ATTRIBUTES containing the + desired firmware volume settings. On + successful return, it contains the new + settings of the firmware volume. On + unsuccessful return, FvAttributes is not + modified and the firmware volume + settings are not changed. + + @retval EFI_SUCCESS The requested firmware volume attributes + were set and the resulting + EFI_FV_ATTRIBUTES is returned in + FvAttributes. + + @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS + is set to 1 on input, but the + device does not support enabling + reads + (FvAttributes:EFI_FV_READ_ENABLE + is clear on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + + @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_READ_STATUS + is cleared to 0 on input, but + the device does not support + disabling reads + (FvAttributes:EFI_FV_READ_DISABL + is clear on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + + @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS + is set to 1 on input, but the + device does not support enabling + writes + (FvAttributes:EFI_FV_WRITE_ENABL + is clear on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + + @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_WRITE_STATUS + is cleared to 0 on input, but + the device does not support + disabling writes + (FvAttributes:EFI_FV_WRITE_DISAB + is clear on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + + @retval EFI_INVALID_PARAMETER FvAttributes:EFI_FV_LOCK_STATUS + is set on input, but the device + does not support locking + (FvAttributes:EFI_FV_LOCK_CAP is + clear on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + + @retval EFI_ACCESS_DENIED Device is locked and does not + allow attribute modification + (FvAttributes:EFI_FV_LOCK_STATUS + is set on return from + GetVolumeAttributes()). Actual + volume attributes are unchanged. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_SET_ATTRIBUTES)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN OUT EFI_FV_ATTRIBUTES *FvAttributes +); + + +/** + Retrieves a file and/or file information from the firmware volume. + + ReadFile() is used to retrieve any file from a firmware volume + during the DXE phase. The actual binary encoding of the file in + the firmware volume media may be in any arbitrary format as long + as it does the following: It is accessed using the Firmware + Volume Protocol. The image that is returned follows the image + format defined in Code Definitions: PI Firmware File Format. + If the input value of Buffer==NULL, it indicates the caller is + requesting only that the type, attributes, and size of the + file be returned and that there is no output buffer. In this + case, the following occurs: + - BufferSize is returned with the size that is required to + successfully complete the read. + - The output parameters FoundType and *FileAttributes are + returned with valid values. + - The returned value of *AuthenticationStatus is undefined. + + If the input value of Buffer!=NULL, the output buffer is + specified by a double indirection of the Buffer parameter. The + input value of *Buffer is used to determine if the output + buffer is caller allocated or is dynamically allocated by + ReadFile(). If the input value of *Buffer!=NULL, it indicates + the output buffer is caller allocated. In this case, the input + value of *BufferSize indicates the size of the + caller-allocated output buffer. If the output buffer is not + large enough to contain the entire requested output, it is + filled up to the point that the output buffer is exhausted and + EFI_WARN_BUFFER_TOO_SMALL is returned, and then BufferSize is + returned with the size required to successfully complete the + read. All other output parameters are returned with valid + values. If the input value of *Buffer==NULL, it indicates the + output buffer is to be allocated by ReadFile(). In this case, + ReadFile() will allocate an appropriately sized buffer from + boot services pool memory, which will be returned in Buffer. + The size of the new buffer is returned in BufferSize and all + other output parameters are returned with valid values. + ReadFile() is callable only from TPL_NOTIFY and below. + Behavior of ReadFile() at any EFI_TPL above TPL_NOTIFY is + undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param NameGuid Pointer to an EFI_GUID, which is the file + name. All firmware file names are EFI_GUIDs. + A single firmware volume must not have two + valid files with the same file name + EFI_GUID. + + @param Buffer Pointer to a pointer to a buffer in which the + file contents are returned, not including the + file header. + + @param BufferSize Pointer to a caller-allocated UINTN. It + indicates the size of the memory + represented by Buffer. + + @param FoundType Pointer to a caller-allocated EFI_FV_FILETYPE. + + @param FileAttributes Pointer to a caller-allocated + EFI_FV_FILE_ATTRIBUTES. + + @param AuthenticationStatus Pointer to a caller-allocated + UINT32 in which the + authentication status is + returned. + + @retval EFI_SUCCESS The call completed successfully. + + @retval EFI_WARN_BUFFER_TOO_SMALL The buffer is too small to + contain the requested + output. The buffer is + filled and the output is + truncated. + + @retval EFI_OUT_OF_RESOURCES An allocation failure occurred. + + @retval EFI_NOT_FOUND Name was not found in the firmware volume. + + @retval EFI_DEVICE_ERROR A hardware error occurred when + attempting to access the firmware volume. + + @retval EFI_ACCESS_DENIED The firmware volume is configured to + disallow reads. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_READ_FILE)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN CONST EFI_GUID *NameGuid, + IN OUT VOID **Buffer, + IN OUT UINTN *BufferSize, + OUT EFI_FV_FILETYPE *FoundType, + OUT EFI_FV_FILE_ATTRIBUTES *FileAttributes, + OUT UINT32 *AuthenticationStatus +); + + + +/** + Locates the requested section within a file and returns it in a buffer. + + ReadSection() is used to retrieve a specific section from a file + within a firmware volume. The section returned is determined + using a depth-first, left-to-right search algorithm through all + sections found in the specified file. The output buffer is specified by a double indirection + of the Buffer parameter. The input value of Buffer is used to + determine if the output buffer is caller allocated or is + dynamically allocated by ReadSection(). If the input value of + Buffer!=NULL, it indicates that the output buffer is caller + allocated. In this case, the input value of *BufferSize + indicates the size of the caller-allocated output buffer. If + the output buffer is not large enough to contain the entire + requested output, it is filled up to the point that the output + buffer is exhausted and EFI_WARN_BUFFER_TOO_SMALL is returned, + and then BufferSize is returned with the size that is required + to successfully complete the read. All other + output parameters are returned with valid values. If the input + value of *Buffer==NULL, it indicates the output buffer is to + be allocated by ReadSection(). In this case, ReadSection() + will allocate an appropriately sized buffer from boot services + pool memory, which will be returned in *Buffer. The size of + the new buffer is returned in *BufferSize and all other output + parameters are returned with valid values. ReadSection() is + callable only from TPL_NOTIFY and below. Behavior of + ReadSection() at any EFI_TPL above TPL_NOTIFY is + undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param NameGuid Pointer to an EFI_GUID, which indicates the + file name from which the requested section + will be read. + + @param SectionType Indicates the section type to return. + SectionType in conjunction with + SectionInstance indicates which section to + return. + + @param SectionInstance Indicates which instance of sections + with a type of SectionType to return. + SectionType in conjunction with + SectionInstance indicates which + section to return. SectionInstance is + zero based. + + @param Buffer Pointer to a pointer to a buffer in which the + section contents are returned, not including + the section header. + + @param BufferSize Pointer to a caller-allocated UINTN. It + indicates the size of the memory + represented by Buffer. + + @param AuthenticationStatus Pointer to a caller-allocated + UINT32 in which the authentication + status is returned. + + + @retval EFI_SUCCESS The call completed successfully. + + @retval EFI_WARN_BUFFER_TOO_SMALL The caller-allocated + buffer is too small to + contain the requested + output. The buffer is + filled and the output is + truncated. + + @retval EFI_OUT_OF_RESOURCES An allocation failure occurred. + + @retval EFI_NOT_FOUND The requested file was not found in + the firmware volume. EFI_NOT_FOUND The + requested section was not found in the + specified file. + + @retval EFI_DEVICE_ERROR A hardware error occurred when + attempting to access the firmware + volume. + + @retval EFI_ACCESS_DENIED The firmware volume is configured to + disallow reads. EFI_PROTOCOL_ERROR + The requested section was not found, + but the file could not be fully + parsed because a required + GUIDED_SECTION_EXTRACTION_PROTOCOL + was not found. It is possible the + requested section exists within the + file and could be successfully + extracted once the required + GUIDED_SECTION_EXTRACTION_PROTOCOL + is published. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_READ_SECTION)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN CONST EFI_GUID *NameGuid, + IN EFI_SECTION_TYPE SectionType, + IN UINTN SectionInstance, + IN OUT VOID **Buffer, + IN OUT UINTN *BufferSize, + OUT UINT32 *AuthenticationStatus +); + +/// +/// EFI_FV_WRITE_POLICY, two policies (unreliable write and reliable write) are defined. +/// +typedef UINT32 EFI_FV_WRITE_POLICY; +#define EFI_FV_UNRELIABLE_WRITE 0x00000000 +#define EFI_FV_RELIABLE_WRITE 0x00000001 + +// +// EFI_FV_WRITE_FILE_DATA +// +typedef struct { + /// + /// Pointer to a GUID, which is the file name to be written. + /// + EFI_GUID *NameGuid; + /// + /// Indicates the type of file to be written. + /// + EFI_FV_FILETYPE Type; + /// + /// Indicates the attributes for the file to be written. + /// + EFI_FV_FILE_ATTRIBUTES FileAttributes; + /// + /// Pointer to a buffer containing the file to be written. + /// + VOID *Buffer; + /// + /// Indicates the size of the file image contained in Buffer. + /// + UINT32 BufferSize; +} EFI_FV_WRITE_FILE_DATA; + +/** + Locates the requested section within a file and returns it in a buffer. + + WriteFile() is used to write one or more files to a firmware + volume. Each file to be written is described by an + EFI_FV_WRITE_FILE_DATA structure. The caller must ensure that + any required alignment for all files listed in the FileData + array is compatible with the firmware volume. Firmware volume + capabilities can be determined using the GetVolumeAttributes() + call. Similarly, if the WritePolicy is set to + EFI_FV_RELIABLE_WRITE, the caller must check the firmware volume + capabilities to ensure EFI_FV_RELIABLE_WRITE is supported by the + firmware volume. EFI_FV_UNRELIABLE_WRITE must always be + supported. Writing a file with a size of zero + (FileData[n].BufferSize == 0) deletes the file from the firmware + volume if it exists. Deleting a file must be done one at a time. + Deleting a file as part of a multiple file write is not allowed. + Platform Initialization Specification VOLUME 3 Shared + Architectural Elements 84 August 21, 2006 Version 1.0 + WriteFile() is callable only from TPL_NOTIFY and below. + Behavior of WriteFile() at any EFI_TPL above TPL_NOTIFY is + undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param NumberOfFiles Indicates the number of elements in the array pointed to by FileData + + @param WritePolicy Indicates the level of reliability for the + write in the event of a power failure or + other system failure during the write + operation. + + @param FileData Pointer to an array of + EFI_FV_WRITE_FILE_DATA. Each element of + FileData[] represents a file to be written. + + + @retval EFI_SUCCESS The write completed successfully. + + @retval EFI_OUT_OF_RESOURCES The firmware volume does not + have enough free space to + storefile(s). + + @retval EFI_DEVICE_ERROR A hardware error occurred when + attempting to access the firmware volume. + + @retval EFI_WRITE_PROTECTED The firmware volume is + configured to disallow writes. + + @retval EFI_NOT_FOUND A delete was requested, but the + requested file was not found in the + firmware volume. + + @retval EFI_INVALID_PARAMETER A delete was requested with a + multiple file write. + + @retval EFI_INVALID_PARAMETER An unsupported WritePolicy was + requested. + + @retval EFI_INVALID_PARAMETER An unknown file type was + specified. + + @retval EFI_INVALID_PARAMETER A file system specific error + has occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_WRITE_FILE)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN UINT32 NumberOfFiles, + IN EFI_FV_WRITE_POLICY WritePolicy, + IN EFI_FV_WRITE_FILE_DATA *FileData +); + + +/** + Retrieves information about the next file in the firmware volume store + that matches the search criteria. + + GetNextFile() is the interface that is used to search a firmware + volume for a particular file. It is called successively until + the desired file is located or the function returns + EFI_NOT_FOUND. To filter uninteresting files from the output, + the type of file to search for may be specified in FileType. For + example, if *FileType is EFI_FV_FILETYPE_DRIVER, only files of + this type will be returned in the output. If *FileType is + EFI_FV_FILETYPE_ALL, no filtering of file types is done. The Key + parameter is used to indicate a starting point of the search. If + the buffer *Key is completely initialized to zero, the search + re-initialized and starts at the beginning. Subsequent calls to + GetNextFile() must maintain the value of *Key returned by the + immediately previous call. The actual contents of *Key are + implementation specific and no semantic content is implied. + GetNextFile() is callable only from TPL_NOTIFY and below. + Behavior of GetNextFile() at any EFI_TPL above TPL_NOTIFY is + undefined. + + @param This Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance. + + @param Key Pointer to a caller-allocated buffer that contains implementation-specific data that is + used to track where to begin the search for the next file. The size of the buffer must be + at least This->KeySize bytes long. To re-initialize the search and begin from the + beginning of the firmware volume, the entire buffer must be cleared to zero. Other + than clearing the buffer to initiate a new search, the caller must not modify the data in + the buffer between calls to GetNextFile(). + + @param FileType Pointer to a caller-allocated + EFI_FV_FILETYPE. The GetNextFile() API can + filter its search for files based on the + value of the FileType input. A *FileType + input of EFI_FV_FILETYPE_ALL causes + GetNextFile() to search for files of all + types. If a file is found, the file's type + is returned in FileType. *FileType is not + modified if no file is found. + + @param NameGuid Pointer to a caller-allocated EFI_GUID. If a + matching file is found, the file's name is + returned in NameGuid. If no matching file is + found, *NameGuid is not modified. + + @param Attributes Pointer to a caller-allocated + EFI_FV_FILE_ATTRIBUTES. If a matching file + is found, the file's attributes are returned + in Attributes. If no matching file is found, + Attributes is not modified. Type + EFI_FV_FILE_ATTRIBUTES is defined in + ReadFile(). + + @param Size Pointer to a caller-allocated UINTN. If a + matching file is found, the file's size is + returned in *Size. If no matching file is found, + Size is not modified. + + @retval EFI_SUCCESS The output parameters are filled with data + obtained from the first matching file that + was found. + + @retval FI_NOT_FOUND No files of type FileType were found. + + + @retval EFI_DEVICE_ERROR A hardware error occurred when + attempting to access the firmware + volume. + + @retval EFI_ACCESS_DENIED The firmware volume is configured to + disallow reads. + + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FV_GET_NEXT_FILE)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN OUT VOID *Key, + IN OUT EFI_FV_FILETYPE *FileType, + OUT EFI_GUID *NameGuid, + OUT EFI_FV_FILE_ATTRIBUTES *Attributes, + OUT UINTN *Size +); + +/** + Return information about a firmware volume. + + The GetInfo() function returns information of type + InformationType for the requested firmware volume. If the volume + does not support the requested information type, then + EFI_UNSUPPORTED is returned. If the buffer is not large enough + to hold the requested structure, EFI_BUFFER_TOO_SMALL is + returned and the BufferSize is set to the size of buffer that is + required to make the request. The information types defined by + this specification are required information types that all file + systems must support. + + @param This A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL + instance that is the file handle the requested + information is for. + + @param InformationType The type identifier for the + information being requested. + + @param BufferSize On input, the size of Buffer. On output, + the amount of data returned in Buffer. In + both cases, the size is measured in bytes. + + @param Buffer A pointer to the data buffer to return. The + buffer's type is indicated by InformationType. + + + @retval EFI_SUCCESS The information was retrieved. + + @retval EFI_UNSUPPORTED The InformationType is not known. + + @retval EFI_NO_MEDIA The device has no medium. + + @retval EFI_DEVICE_ERROR The device reported an error. + + @retval EFI_VOLUME_CORRUPTED The file system structures are + corrupted. + + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to + read the current directory + entry. BufferSize has been + updated with the size needed to + complete the request. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FV_GET_INFO)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN CONST EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer +); + + +/** + Sets information about a firmware volume. + + The SetInfo() function sets information of type InformationType + on the requested firmware volume. + + + @param This A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL + instance that is the file handle the information + is for. + + @param InformationType The type identifier for the + information being set. + + @param BufferSize The size, in bytes, of Buffer. + + @param Buffer A pointer to the data buffer to write. The + buffer's type is indicated by InformationType. + + @retval EFI_SUCCESS The information was set. + + @retval EFI_UNSUPPORTED The InformationType is not known. + + @retval EFI_NO_MEDIA The device has no medium. + + @retval EFI_DEVICE_ERROR The device reported an error. + + @retval EFI_VOLUME_CORRUPTED The file system structures are + corrupted. + + + @retval EFI_WRITE_PROTECTED The media is read only. + + @retval EFI_VOLUME_FULL The volume is full. + + @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the + size of the type indicated by + InformationType. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FV_SET_INFO)( + IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This, + IN CONST EFI_GUID *InformationType, + IN UINTN BufferSize, + IN CONST VOID *Buffer +); + + +/// +/// The Firmware Volume Protocol contains the file-level +/// abstraction to the firmware volume as well as some firmware +/// volume attribute reporting and configuration services. The +/// Firmware Volume Protocol is the interface used by all parts of +/// DXE that are not directly involved with managing the firmware +/// volume itself. This abstraction allows many varied types of +/// firmware volume implementations. A firmware volume may be a +/// flash device or it may be a file in the UEFI system partition, +/// for example. This level of firmware volume implementation +/// detail is not visible to the consumers of the Firmware Volume +/// Protocol. +/// +struct _EFI_FIRMWARE_VOLUME2_PROTOCOL { + EFI_FV_GET_ATTRIBUTES GetVolumeAttributes; + EFI_FV_SET_ATTRIBUTES SetVolumeAttributes; + EFI_FV_READ_FILE ReadFile; + EFI_FV_READ_SECTION ReadSection; + EFI_FV_WRITE_FILE WriteFile; + EFI_FV_GET_NEXT_FILE GetNextFile; + + /// + /// Data field that indicates the size in bytes + /// of the Key input buffer for the + /// GetNextFile() API. + /// + UINT32 KeySize; + + /// + /// Handle of the parent firmware volume. + /// + EFI_HANDLE ParentHandle; + EFI_FV_GET_INFO GetInfo; + EFI_FV_SET_INFO SetInfo; +}; + + +extern EFI_GUID gEfiFirmwareVolume2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolumeBlock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolumeBlock.h new file mode 100644 index 0000000000..3be86b0039 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FirmwareVolumeBlock.h @@ -0,0 +1,360 @@ +/** @file + This file provides control over block-oriented firmware devices. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: PI + Version 1.0 and 1.2. + +**/ + +#ifndef __FIRMWARE_VOLUME_BLOCK_H__ +#define __FIRMWARE_VOLUME_BLOCK_H__ + +// +// EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL is defined in PI 1.0 spec and its GUID value +// is later updated to be the same as that of EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL +// defined in PI 1.2 spec. +// +#define EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID \ + { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } } + +#define EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL_GUID \ + { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } } + +typedef struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL; + +typedef EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL; + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the + attributes and current settings are + returned. Type EFI_FVB_ATTRIBUTES_2 is defined + in EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were + returned. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_GET_ATTRIBUTES)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes +); + + +/** + The SetAttributes() function sets configurable firmware volume + attributes and returns the new settings of the firmware volume. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to + EFI_FVB_ATTRIBUTES_2 that contains the + desired firmware volume settings. On + successful return, it contains the new + settings of the firmware volume. Type + EFI_FVB_ATTRIBUTES_2 is defined in + EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in + conflict with the capabilities + as declared in the firmware + volume header. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_SET_ATTRIBUTES)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes +); + + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_UNSUPPORTED The firmware volume is not memory mapped. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_GET_PHYSICAL_ADDRESS)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address +); + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba Indicates the block for which to return the size. + + @param BlockSize Pointer to a caller-allocated UINTN in which + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_GET_BLOCK_SIZE)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks +); + + +/** + Reads the specified number of bytes into a buffer from the specified block. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index + from which to read. + + @param Offset Offset into the block at which to begin reading. + + @param NumBytes Pointer to a UINTN. At entry, *NumBytes + contains the total size of the buffer. At + exit, *NumBytes contains the total number of + bytes read. + + @param Buffer Pointer to a caller-allocated buffer that will + be used to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, + and contents are in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA + boundary. On output, NumBytes + contains the total number of bytes + returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + ReadDisabled state. + + @retval EFI_DEVICE_ERROR The block device is not + functioning correctly and could + not be read. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FVB_READ)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer +); + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writing. + + @param NumBytes The pointer to a UINTN. At entry, *NumBytes + contains the total size of the buffer. At + exit, *NumBytes contains the total number of + bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that + contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an + LBA boundary. On output, NumBytes + contains the total number of bytes + actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + WriteDisabled state. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning + and could not be written. + + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_WRITE)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer +); + + + + +/// +/// EFI_LBA_LIST_TERMINATOR +/// +#define EFI_LBA_LIST_TERMINATOR 0xFFFFFFFFFFFFFFFFULL + + +/** + Erases and initializes a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL + instance. + + @param ... The variable argument list is a list of tuples. + Each tuple describes a range of LBAs to erase + and consists of the following: + - An EFI_LBA that indicates the starting LBA + - A UINTN that indicates the number of blocks to + erase. + + The list is terminated with an + EFI_LBA_LIST_TERMINATOR. For example, the + following indicates that two ranges of blocks + (5-7 and 10-11) are to be erased: EraseBlocks + (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR); + + @retval EFI_SUCCESS The erase request successfully + completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the + WriteDisabled state. + @retval EFI_DEVICE_ERROR The block device is not functioning + correctly and could not be written. + The firmware device may have been + partially erased. + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed + in the variable argument list do + not exist in the firmware volume. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_FVB_ERASE_BLOCKS)( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... +); + +/// +/// The Firmware Volume Block Protocol is the low-level interface +/// to a firmware volume. File-level access to a firmware volume +/// should not be done using the Firmware Volume Block Protocol. +/// Normal access to a firmware volume must use the Firmware +/// Volume Protocol. Typically, only the file system driver that +/// produces the Firmware Volume Protocol will bind to the +/// Firmware Volume Block Protocol. +/// +struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL{ + EFI_FVB_GET_ATTRIBUTES GetAttributes; + EFI_FVB_SET_ATTRIBUTES SetAttributes; + EFI_FVB_GET_PHYSICAL_ADDRESS GetPhysicalAddress; + EFI_FVB_GET_BLOCK_SIZE GetBlockSize; + EFI_FVB_READ Read; + EFI_FVB_WRITE Write; + EFI_FVB_ERASE_BLOCKS EraseBlocks; + /// + /// The handle of the parent firmware volume. + /// + EFI_HANDLE ParentHandle; +}; + + +extern EFI_GUID gEfiFirmwareVolumeBlockProtocolGuid; +extern EFI_GUID gEfiFirmwareVolumeBlock2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FormBrowser2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FormBrowser2.h new file mode 100644 index 0000000000..8bc26d6fda --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/FormBrowser2.h @@ -0,0 +1,174 @@ +/** @file + This protocol is defined in UEFI spec. + + The EFI_FORM_BROWSER2_PROTOCOL is the interface to call for drivers to + leverage the EFI configuration driver interface. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_FORM_BROWSER2_H__ +#define __EFI_FORM_BROWSER2_H__ + +#include + +#define EFI_FORM_BROWSER2_PROTOCOL_GUID \ + {0xb9d4c360, 0xbcfb, 0x4f9b, {0x92, 0x98, 0x53, 0xc1, 0x36, 0x98, 0x22, 0x58 }} + + +typedef struct _EFI_FORM_BROWSER2_PROTOCOL EFI_FORM_BROWSER2_PROTOCOL; + + + +/** + + @param LeftColumn The value that designates the text column + where the browser window will begin from + the left-hand side of the screen + + @param RightColumn The value that designates the text + column where the browser window will end + on the right-hand side of the screen. + + @param TopRow The value that designates the text row from the + top of the screen where the browser window + will start. + + @param BottomRow The value that designates the text row from the + bottom of the screen where the browser + window will end. +**/ +typedef struct { + UINTN LeftColumn; + UINTN RightColumn; + UINTN TopRow; + UINTN BottomRow; +} EFI_SCREEN_DESCRIPTOR; + +typedef UINTN EFI_BROWSER_ACTION_REQUEST; + +#define EFI_BROWSER_ACTION_REQUEST_NONE 0 +#define EFI_BROWSER_ACTION_REQUEST_RESET 1 +#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2 +#define EFI_BROWSER_ACTION_REQUEST_EXIT 3 +#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4 +#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5 +#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6 +#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7 +#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8 + + +/** + Initialize the browser to display the specified configuration forms. + + This function is the primary interface to the internal forms-based browser. + The forms browser will display forms associated with the specified Handles. + The browser will select all forms in packages which have the specified Type + and (for EFI_HII_PACKAGE_TYPE_GUID) the specified PackageGuid. + + @param This A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance + + @param Handles A pointer to an array of Handles. This value should correspond + to the value of the HII form package that is required to be displayed. + + @param HandleCount The number of Handles specified in Handle. + + @param FormSetGuid This field points to the EFI_GUID which must match the Guid field or one of the + elements of the ClassId field in the EFI_IFR_FORM_SET op-code. If + FormsetGuid is NULL, then this function will display the form set class + EFI_HII_PLATFORM_SETUP_FORMSET_GUID. + + @param FormId This field specifies the identifier of the form within the form set to render as the first + displayable page. If this field has a value of 0x0000, then the Forms Browser will + render the first enabled form in the form set. + + @param ScreenDimensions Points to recommended form dimensions, including any non-content area, in + characters. + + @param ActionRequest Points to the action recommended by the form. + + @retval EFI_SUCCESS The function completed successfully + + @retval EFI_NOT_FOUND The variable was not found. + + @retval EFI_INVALID_PARAMETER One of the parameters has an + invalid value. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SEND_FORM2)( + IN CONST EFI_FORM_BROWSER2_PROTOCOL *This, + IN EFI_HII_HANDLE *Handle, + IN UINTN HandleCount, + IN EFI_GUID *FormSetGuid, OPTIONAL + IN EFI_FORM_ID FormId, OPTIONAL + IN CONST EFI_SCREEN_DESCRIPTOR *ScreenDimensions, OPTIONAL + OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest OPTIONAL +); + + +/** + This function is called by a callback handler to retrieve uncommitted state data from the browser. + + This routine is called by a routine which was called by the + browser. This routine called this service in the browser to + retrieve or set certain uncommitted state information. + + @param This A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance. + + @param ResultsDataSize A pointer to the size of the buffer + associated with ResultsData. On input, the size in + bytes of ResultsData. On output, the size of data + returned in ResultsData. + + @param ResultsData A string returned from an IFR browser or + equivalent. The results string will have + no routing information in them. + + @param RetrieveData A BOOLEAN field which allows an agent to + retrieve (if RetrieveData = TRUE) data + from the uncommitted browser state + information or set (if RetrieveData = + FALSE) data in the uncommitted browser + state information. + + @param VariableGuid An optional field to indicate the target + variable GUID name to use. + + @param VariableName An optional field to indicate the target + human-readable variable name. + + @retval EFI_SUCCESS The results have been distributed or are + awaiting distribution. + + @retval EFI_OUT_OF_RESOURCES The ResultsDataSize specified + was too small to contain the + results data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_BROWSER_CALLBACK2)( + IN CONST EFI_FORM_BROWSER2_PROTOCOL *This, + IN OUT UINTN *ResultsDataSize, + IN OUT EFI_STRING ResultsData, + IN CONST BOOLEAN RetrieveData, + IN CONST EFI_GUID *VariableGuid, OPTIONAL + IN CONST CHAR16 *VariableName OPTIONAL +); + +/// +/// This interface will allow the caller to direct the configuration +/// driver to use either the HII database or use the passed-in packet of data. +/// +struct _EFI_FORM_BROWSER2_PROTOCOL { + EFI_SEND_FORM2 SendForm; + EFI_BROWSER_CALLBACK2 BrowserCallback; +} ; + +extern EFI_GUID gEfiFormBrowser2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ftp4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ftp4.h new file mode 100644 index 0000000000..22b97ebda6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ftp4.h @@ -0,0 +1,518 @@ +/** @file + EFI FTPv4 (File Transfer Protocol version 4) Protocol Definition + The EFI FTPv4 Protocol is used to locate communication devices that are + supported by an EFI FTPv4 Protocol driver and to create and destroy instances + of the EFI FTPv4 Protocol child protocol driver that can use the underlying + communication device. + The definitions in this file are defined in UEFI Specification 2.3, which have + not been verified by one implementation yet. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_FTP4_PROTOCOL_H__ +#define __EFI_FTP4_PROTOCOL_H__ + + +#define EFI_FTP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xfaaecb1, 0x226e, 0x4782, {0xaa, 0xce, 0x7d, 0xb9, 0xbc, 0xbf, 0x4d, 0xaf } \ + } + +#define EFI_FTP4_PROTOCOL_GUID \ + { \ + 0xeb338826, 0x681b, 0x4295, {0xb3, 0x56, 0x2b, 0x36, 0x4c, 0x75, 0x7b, 0x9 } \ + } + +typedef struct _EFI_FTP4_PROTOCOL EFI_FTP4_PROTOCOL; + +/// +/// EFI_FTP4_CONNECTION_TOKEN +/// +typedef struct { + /// + /// The Event to signal after the connection is established and Status field is updated + /// by the EFI FTP v4 Protocol driver. The type of Event must be + /// EVENT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower than or + /// equal to TPL_CALLBACK. If it is set to NULL, this function will not return until the + /// function completes. + /// + EFI_EVENT Event; + /// + /// The variable to receive the result of the completed operation. + /// EFI_SUCCESS: The FTP connection is established successfully + /// EFI_ACCESS_DENIED: The FTP server denied the access the user's request to access it. + /// EFI_CONNECTION_RESET: The connect fails because the connection is reset either by instance + /// itself or communication peer. + /// EFI_TIMEOUT: The connection establishment timer expired and no more specific + /// information is available. + /// EFI_NETWORK_UNREACHABLE: The active open fails because an ICMP network unreachable error is + /// received. + /// EFI_HOST_UNREACHABLE: The active open fails because an ICMP host unreachable error is + /// received. + /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable error is + /// received. + /// EFI_PORT_UNREACHABLE: The connection establishment timer times out and an ICMP port + /// unreachable error is received. + /// EFI_ICMP_ERROR: The connection establishment timer timeout and some other ICMP + /// error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// + EFI_STATUS Status; +} EFI_FTP4_CONNECTION_TOKEN; + +/// +/// EFI_FTP4_CONFIG_DATA +/// +typedef struct { + /// + /// Pointer to a ASCII string that contains user name. The caller is + /// responsible for freeing Username after GetModeData() is called. + /// + UINT8 *Username; + /// + /// Pointer to a ASCII string that contains password. The caller is + /// responsible for freeing Password after GetModeData() is called. + /// + UINT8 *Password; + /// + /// Set it to TRUE to initiate an active data connection. Set it to + /// FALSE to initiate a passive data connection. + /// + BOOLEAN Active; + /// + /// Boolean value indicating if default network settting used. + /// + BOOLEAN UseDefaultSetting; + /// + /// IP address of station if UseDefaultSetting is FALSE. + /// + EFI_IPv4_ADDRESS StationIp; + /// + /// Subnet mask of station if UseDefaultSetting is FALSE. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// IP address of gateway if UseDefaultSetting is FALSE. + /// + EFI_IPv4_ADDRESS GatewayIp; + /// + /// IP address of FTPv4 server. + /// + EFI_IPv4_ADDRESS ServerIp; + /// + /// FTPv4 server port number of control connection, and the default + /// value is 21 as convention. + /// + UINT16 ServerPort; + /// + /// FTPv4 server port number of data connection. If it is zero, use + /// (ServerPort - 1) by convention. + /// + UINT16 AltDataPort; + /// + /// A byte indicate the representation type. The right 4 bit is used for + /// first parameter, the left 4 bit is use for second parameter + /// - For the first parameter, 0x0 = image, 0x1 = EBCDIC, 0x2 = ASCII, 0x3 = local + /// - For the second parameter, 0x0 = Non-print, 0x1 = Telnet format effectors, 0x2 = + /// Carriage Control. + /// - If it is a local type, the second parameter is the local byte byte size. + /// - If it is a image type, the second parameter is undefined. + /// + UINT8 RepType; + /// + /// Defines the file structure in FTP used. 0x00 = file, 0x01 = record, 0x02 = page. + /// + UINT8 FileStruct; + /// + /// Defines the transifer mode used in FTP. 0x00 = stream, 0x01 = Block, 0x02 = Compressed. + /// + UINT8 TransMode; +} EFI_FTP4_CONFIG_DATA; + +typedef struct _EFI_FTP4_COMMAND_TOKEN EFI_FTP4_COMMAND_TOKEN; + +/** + Callback function when process inbound or outbound data. + + If it is receiving function that leads to inbound data, the callback function + is called when data buffer is full. Then, old data in the data buffer should be + flushed and new data is stored from the beginning of data buffer. + If it is a transmit function that lead to outbound data and the size of + Data in daata buffer has been transmitted, this callback function is called to + supply additional data to be transmitted. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that + are used in this operation. + @return User defined Status. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_DATA_CALLBACK)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_COMMAND_TOKEN *Token + ); + +/// +/// EFI_FTP4_COMMAND_TOKEN +/// +struct _EFI_FTP4_COMMAND_TOKEN { + /// + /// The Event to signal after request is finished and Status field + /// is updated by the EFI FTP v4 Protocol driver. The type of Event + /// must be EVT_NOTIFY_SIGNAL, and its Task Priority Level + /// (TPL) must be lower than or equal to TPL_CALLBACK. If it is + /// set to NULL, related function must wait until the function + /// completes. + /// + EFI_EVENT Event; + /// + /// Pointer to a null-terminated ASCII name string. + /// + UINT8 *Pathname; + /// + /// The size of data buffer in bytes. + /// + UINT64 DataBufferSize; + /// + /// Pointer to the data buffer. Data downloaded from FTP server + /// through connection is downloaded here. + /// + VOID *DataBuffer; + /// + /// Pointer to a callback function. If it is receiving function that leads + /// to inbound data, the callback function is called when databuffer is + /// full. Then, old data in the data buffer should be flushed and new + /// data is stored from the beginning of data buffer. If it is a transmit + /// function that lead to outbound data and DataBufferSize of + /// Data in DataBuffer has been transmitted, this callback + /// function is called to supply additional data to be transmitted. The + /// size of additional data to be transmitted is indicated in + /// DataBufferSize, again. If there is no data remained, + /// DataBufferSize should be set to 0. + /// + EFI_FTP4_DATA_CALLBACK DataCallback; + /// + /// Pointer to the parameter for DataCallback. + /// + VOID *Context; + /// + /// The variable to receive the result of the completed operation. + /// EFI_SUCCESS: The FTP command is completed successfully. + /// EFI_ACCESS_DENIED: The FTP server denied the access to the requested file. + /// EFI_CONNECTION_RESET: The connect fails because the connection is reset either + /// by instance itself or communication peer. + /// EFI_TIMEOUT: The connection establishment timer expired and no more + /// specific information is available. + /// EFI_NETWORK_UNREACHABLE: The active open fails because an ICMP network unreachable + /// error is received. + /// EFI_HOST_UNREACHABLE: The active open fails because an ICMP host unreachable + /// error is received. + /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable + /// error is received. + /// EFI_PORT_UNREACHABLE: The connection establishment timer times out and an ICMP port + /// unreachable error is received. + /// EFI_ICMP_ERROR: The connection establishment timer timeout and some other ICMP + /// error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// + EFI_STATUS Status; +}; + +/** + Gets the current operational settings. + + The GetModeData() function reads the current operational settings of this + EFI FTPv4 Protocol driver instance. EFI_FTP4_CONFIG_DATA is defined in the + EFI_FTP4_PROTOCOL.Configure. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[out] ModeData Pointer to storage for the EFI FTPv4 Protocol driver + mode data. The string buffers for Username and Password + in EFI_FTP4_CONFIG_DATA are allocated by the function, + and the caller should take the responsibility to free the + buffer later. + + @retval EFI_SUCCESS This function is called successfully. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - ModeData is NULL. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_GET_MODE_DATA)( + IN EFI_FTP4_PROTOCOL *This, + OUT EFI_FTP4_CONFIG_DATA *ModeData + ); + +/** + Disconnecting a FTP connection gracefully. + + The Connect() function will initiate a connection request to the remote FTP server + with the corresponding connection token. If this function returns EFI_SUCCESS, the + connection sequence is initiated successfully. If the connection succeeds or faild + due to any error, the Token->Event will be signaled and Token->Status will be updated + accordingly. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token used to establish control connection. + + @retval EFI_SUCCESS The connection sequence is successfully initiated. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - Token is NULL. + - Token->Event is NULL. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_CONNECT)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_CONNECTION_TOKEN *Token + ); + +/** + Disconnecting a FTP connection gracefully. + + The Close() function will initiate a close request to the remote FTP server with the + corresponding connection token. If this function returns EFI_SUCCESS, the control + connection with the remote FTP server is closed. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token used to close control connection. + + @retval EFI_SUCCESS The close request is successfully initiated. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - Token is NULL. + - Token->Event is NULL. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_CLOSE)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_CONNECTION_TOKEN *Token + ); + +/** + Sets or clears the operational parameters for the FTP child driver. + + The Configure() function will configure the connected FTP session with the + configuration setting specified in FtpConfigData. The configuration data can + be reset by calling Configure() with FtpConfigData set to NULL. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] FtpConfigData Pointer to configuration data that will be assigned to + the FTP child driver instance. If NULL, the FTP child + driver instance is reset to startup defaults and all + pending transmit and receive requests are flushed. + + @retval EFI_SUCCESS The FTPv4 driver was configured successfully. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + - This is NULL. + - FtpConfigData.RepType is invalid. + - FtpConfigData.FileStruct is invalid. + - FtpConfigData.TransMode is invalid. + - IP address in FtpConfigData is invalid. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_UNSUPPORTED One or more of the configuration parameters are not supported + by this implementation. + @retval EFI_OUT_OF_RESOURCES The EFI FTPv4 Protocol driver instance data could not be + allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI FTPv4 + Protocol driver instance is not configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_CONFIGURE)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_CONFIG_DATA *FtpConfigData OPTIONAL + ); + + +/** + Downloads a file from an FTPv4 server. + + The ReadFile() function is used to initialize and start an FTPv4 download process + and optionally wait for completion. When the download operation completes, whether + successfully or not, the Token.Status field is updated by the EFI FTPv4 Protocol + driver and then Token.Event is signaled (if it is not NULL). + + Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size + is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for + processing data and then new data will be placed at the beginning of Token.DataBuffer. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that + are used in this operation. + + @retval EFI_SUCCESS The data file is being downloaded successfully. + @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid. + - This is NULL. + - Token is NULL. + - Token.Pathname is NULL. + - Token. DataBuffer is NULL. + - Token. DataBufferSize is 0. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_READ_FILE)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_COMMAND_TOKEN *Token + ); + +/** + Uploads a file from an FTPv4 server. + + The WriteFile() function is used to initialize and start an FTPv4 upload process and + optionally wait for completion. When the upload operation completes, whether successfully + or not, the Token.Status field is updated by the EFI FTPv4 Protocol driver and then + Token.Event is signaled (if it is not NULL). Data to be uploaded to server is stored + into Token.DataBuffer. Token.DataBufferSize is the number bytes to be transferred. + If the file size is larger than Token.DataBufferSize, Token.DataCallback will be called + to allow for processing data and then new data will be placed at the beginning of + Token.DataBuffer. Token.DataBufferSize is updated to reflect the actual number of bytes + to be transferred. Token.DataBufferSize is set to 0 by the call back to indicate the + completion of data transfer. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that + are used in this operation. + + @retval EFI_SUCCESS TThe data file is being uploaded successfully. + @retval EFI_UNSUPPORTED The operation is not supported by this implementation. + @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid. + - This is NULL. + - Token is NULL. + - Token.Pathname is NULL. + - Token. DataBuffer is NULL. + - Token. DataBufferSize is 0. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_WRITE_FILE)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_COMMAND_TOKEN *Token + ); + +/** + Download a data file "directory" from a FTPv4 server. May be unsupported in some EFI + implementations. + + The ReadDirectory() function is used to return a list of files on the FTPv4 server that + logically (or operationally) related to Token.Pathname, and optionally wait for completion. + When the download operation completes, whether successfully or not, the Token.Status field + is updated by the EFI FTPv4 Protocol driver and then Token.Event is signaled (if it is not + NULL). Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size + is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for processing + data and then new data will be placed at the beginning of Token.DataBuffer. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that + are used in this operation. + + @retval EFI_SUCCESS The file list information is being downloaded successfully. + @retval EFI_UNSUPPORTED The operation is not supported by this implementation. + @retval EFI_INVALID_PARAMETER One or more of the parameters is not valid. + - This is NULL. + - Token is NULL. + - Token. DataBuffer is NULL. + - Token. DataBufferSize is 0. + @retval EFI_NOT_STARTED The EFI FTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_READ_DIRECTORY)( + IN EFI_FTP4_PROTOCOL *This, + IN EFI_FTP4_COMMAND_TOKEN *Token + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase the + rate that data packets are moved between the communications device and the transmit + and receive queues. In some systems, the periodic timer event in the managed network + driver may not poll the underlying communications device fast enough to transmit + and/or receive all data packets without missing incoming packets or dropping outgoing + packets. Drivers and applications that are experiencing packet loss should try calling + the Poll() function more often. + + @param[in] This Pointer to the EFI_FTP4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI FTPv4 Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR EapAuthType An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FTP4_POLL)( + IN EFI_FTP4_PROTOCOL *This + ); + +/// +/// EFI_FTP4_PROTOCOL +/// provides basic services for client-side FTP (File Transfer Protocol) +/// operations. +/// +struct _EFI_FTP4_PROTOCOL { + EFI_FTP4_GET_MODE_DATA GetModeData; + EFI_FTP4_CONNECT Connect; + EFI_FTP4_CLOSE Close; + EFI_FTP4_CONFIGURE Configure; + EFI_FTP4_READ_FILE ReadFile; + EFI_FTP4_WRITE_FILE WriteFile; + EFI_FTP4_READ_DIRECTORY ReadDirectory; + EFI_FTP4_POLL Poll; +}; + +extern EFI_GUID gEfiFtp4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiFtp4ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GraphicsOutput.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GraphicsOutput.h new file mode 100644 index 0000000000..9ba38c577a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GraphicsOutput.h @@ -0,0 +1,270 @@ +/** @file + Graphics Output Protocol from the UEFI 2.0 specification. + + Abstraction of a very simple graphics device. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __GRAPHICS_OUTPUT_H__ +#define __GRAPHICS_OUTPUT_H__ + +#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \ + { \ + 0x9042a9de, 0x23dc, 0x4a38, {0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a } \ + } + +typedef struct _EFI_GRAPHICS_OUTPUT_PROTOCOL EFI_GRAPHICS_OUTPUT_PROTOCOL; + +typedef struct { + UINT32 RedMask; + UINT32 GreenMask; + UINT32 BlueMask; + UINT32 ReservedMask; +} EFI_PIXEL_BITMASK; + +typedef enum { + /// + /// A pixel is 32-bits and byte zero represents red, byte one represents green, + /// byte two represents blue, and byte three is reserved. This is the definition + /// for the physical frame buffer. The byte values for the red, green, and blue + /// components represent the color intensity. This color intensity value range + /// from a minimum intensity of 0 to maximum intensity of 255. + /// + PixelRedGreenBlueReserved8BitPerColor, + /// + /// A pixel is 32-bits and byte zero represents blue, byte one represents green, + /// byte two represents red, and byte three is reserved. This is the definition + /// for the physical frame buffer. The byte values for the red, green, and blue + /// components represent the color intensity. This color intensity value range + /// from a minimum intensity of 0 to maximum intensity of 255. + /// + PixelBlueGreenRedReserved8BitPerColor, + /// + /// The Pixel definition of the physical frame buffer. + /// + PixelBitMask, + /// + /// This mode does not support a physical frame buffer. + /// + PixelBltOnly, + /// + /// Valid EFI_GRAPHICS_PIXEL_FORMAT enum values are less than this value. + /// + PixelFormatMax +} EFI_GRAPHICS_PIXEL_FORMAT; + +typedef struct { + /// + /// The version of this data structure. A value of zero represents the + /// EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as defined in this specification. + /// + UINT32 Version; + /// + /// The size of video screen in pixels in the X dimension. + /// + UINT32 HorizontalResolution; + /// + /// The size of video screen in pixels in the Y dimension. + /// + UINT32 VerticalResolution; + /// + /// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly + /// implies that a linear frame buffer is not available for this mode. + /// + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + /// + /// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask. + /// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reserved. + /// + EFI_PIXEL_BITMASK PixelInformation; + /// + /// Defines the number of pixel elements per video memory line. + /// + UINT32 PixelsPerScanLine; +} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION; + +/** + Returns information for an available graphics mode that the graphics device + and the set of active video output devices supports. + + @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance. + @param ModeNumber The mode number to return information on. + @param SizeOfInfo A pointer to the size, in bytes, of the Info buffer. + @param Info A pointer to callee allocated buffer that returns information about ModeNumber. + + @retval EFI_SUCCESS Valid mode information was returned. + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video mode. + @retval EFI_INVALID_PARAMETER ModeNumber is not valid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE)( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info + ); + +/** + Set the video device into the specified mode and clears the visible portions of + the output display to black. + + @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance. + @param ModeNumber Abstraction that defines the current video mode. + + @retval EFI_SUCCESS The graphics mode specified by ModeNumber was selected. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED ModeNumber is not supported by this device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE)( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber + ); + +typedef struct { + UINT8 Blue; + UINT8 Green; + UINT8 Red; + UINT8 Reserved; +} EFI_GRAPHICS_OUTPUT_BLT_PIXEL; + +typedef union { + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel; + UINT32 Raw; +} EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION; + +/// +/// actions for BltOperations +/// +typedef enum { + /// + /// Write data from the BltBuffer pixel (0, 0) + /// directly to every pixel of the video display rectangle + /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). + /// Only one pixel will be used from the BltBuffer. Delta is NOT used. + /// + EfiBltVideoFill, + + /// + /// Read data from the video display rectangle + /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in + /// the BltBuffer rectangle (DestinationX, DestinationY ) + /// (DestinationX + Width, DestinationY + Height). If DestinationX or + /// DestinationY is not zero then Delta must be set to the length in bytes + /// of a row in the BltBuffer. + /// + EfiBltVideoToBltBuffer, + + /// + /// Write data from the BltBuffer rectangle + /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the + /// video display rectangle (DestinationX, DestinationY) + /// (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is + /// not zero then Delta must be set to the length in bytes of a row in the + /// BltBuffer. + /// + EfiBltBufferToVideo, + + /// + /// Copy from the video display rectangle (SourceX, SourceY) + /// (SourceX + Width, SourceY + Height) to the video display rectangle + /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). + /// The BltBuffer and Delta are not used in this mode. + /// + EfiBltVideoToVideo, + + EfiGraphicsOutputBltOperationMax +} EFI_GRAPHICS_OUTPUT_BLT_OPERATION; + +/** + Blt a rectangle of pixels on the graphics screen. Blt stands for BLock Transfer. + + @param This Protocol instance pointer. + @param BltBuffer The data to transfer to the graphics screen. + Size is at least Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL). + @param BltOperation The operation to perform when copying BltBuffer on to the graphics screen. + @param SourceX The X coordinate of source for the BltOperation. + @param SourceY The Y coordinate of source for the BltOperation. + @param DestinationX The X coordinate of destination for the BltOperation. + @param DestinationY The Y coordinate of destination for the BltOperation. + @param Width The width of a rectangle in the blt rectangle in pixels. + @param Height The height of a rectangle in the blt rectangle in pixels. + @param Delta Not used for EfiBltVideoFill or the EfiBltVideoToVideo operation. + If a Delta of zero is used, the entire BltBuffer is being operated on. + If a subrectangle of the BltBuffer is being used then Delta + represents the number of bytes in a row of the BltBuffer. + + @retval EFI_SUCCESS BltBuffer was drawn to the graphics screen. + @retval EFI_INVALID_PARAMETER BltOperation is not valid. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT)( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL + ); + +typedef struct { + /// + /// The number of modes supported by QueryMode() and SetMode(). + /// + UINT32 MaxMode; + /// + /// Current Mode of the graphics device. Valid mode numbers are 0 to MaxMode -1. + /// + UINT32 Mode; + /// + /// Pointer to read-only EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data. + /// + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info; + /// + /// Size of Info structure in bytes. + /// + UINTN SizeOfInfo; + /// + /// Base address of graphics linear frame buffer. + /// Offset zero in FrameBufferBase represents the upper left pixel of the display. + /// + EFI_PHYSICAL_ADDRESS FrameBufferBase; + /// + /// Amount of frame buffer needed to support the active mode as defined by + /// PixelsPerScanLine xVerticalResolution x PixelElementSize. + /// + UINTN FrameBufferSize; +} EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE; + +/// +/// Provides a basic abstraction to set video modes and copy pixels to and from +/// the graphics controller's frame buffer. The linear address of the hardware +/// frame buffer is also exposed so software can write directly to the video hardware. +/// +struct _EFI_GRAPHICS_OUTPUT_PROTOCOL { + EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode; + EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode; + EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt; + /// + /// Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data. + /// + EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode; +}; + +extern EFI_GUID gEfiGraphicsOutputProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GuidedSectionExtraction.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GuidedSectionExtraction.h new file mode 100644 index 0000000000..e44d639889 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/GuidedSectionExtraction.h @@ -0,0 +1,135 @@ +/** @file + If a GUID-defined section is encountered when doing section + extraction, the section extraction driver calls the appropriate + instance of the GUIDed Section Extraction Protocol to extract + the section stream contained therein. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: PI + Version 1.00. + +**/ + +#ifndef __GUID_SECTION_EXTRACTION_PROTOCOL_H__ +#define __GUID_SECTION_EXTRACTION_PROTOCOL_H__ + +// +// The protocol interface structures are identified by associating +// them with a GUID. Each instance of a protocol with a given +// GUID must have the same interface structure. While all instances +// of the GUIDed Section Extraction Protocol must have the same +// interface structure, they do not all have the same GUID. The +// GUID that is associated with an instance of the GUIDed Section +// Extraction Protocol is used to correlate it with the GUIDed +// section type that it is intended to process. +// + +typedef struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL; + + +/** + The ExtractSection() function processes the input section and + allocates a buffer from the pool in which it returns the section + contents. If the section being extracted contains + authentication information (the section's + GuidedSectionHeader.Attributes field has the + EFI_GUIDED_SECTION_AUTH_STATUS_VALID bit set), the values + returned in AuthenticationStatus must reflect the results of + the authentication operation. Depending on the algorithm and + size of the encapsulated data, the time that is required to do + a full authentication may be prohibitively long for some + classes of systems. To indicate this, use + EFI_SECURITY_POLICY_PROTOCOL_GUID, which may be published by + the security policy driver (see the Platform Initialization + Driver Execution Environment Core Interface Specification for + more details and the GUID definition). If the + EFI_SECURITY_POLICY_PROTOCOL_GUID exists in the handle + database, then, if possible, full authentication should be + skipped and the section contents simply returned in the + OutputBuffer. In this case, the + EFI_AUTH_STATUS_PLATFORM_OVERRIDE bit AuthenticationStatus + must be set on return. ExtractSection() is callable only from + TPL_NOTIFY and below. Behavior of ExtractSection() at any + EFI_TPL above TPL_NOTIFY is undefined. Type EFI_TPL is + defined in RaiseTPL() in the UEFI 2.0 specification. + + + @param This Indicates the EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL instance. + + @param InputSection Buffer containing the input GUIDed section + to be processed. OutputBuffer OutputBuffer + is allocated from boot services pool + memory and contains the new section + stream. The caller is responsible for + freeing this buffer. + + @param OutputSize A pointer to a caller-allocated UINTN in + which the size of OutputBuffer allocation + is stored. If the function returns + anything other than EFI_SUCCESS, the value + of OutputSize is undefined. + + @param AuthenticationStatus A pointer to a caller-allocated + UINT32 that indicates the + authentication status of the + output buffer. If the input + section's + GuidedSectionHeader.Attributes + field has the + EFI_GUIDED_SECTION_AUTH_STATUS_VAL + bit as clear, AuthenticationStatus + must return zero. Both local bits + (19:16) and aggregate bits (3:0) + in AuthenticationStatus are + returned by ExtractSection(). + These bits reflect the status of + the extraction operation. The bit + pattern in both regions must be + the same, as the local and + aggregate authentication statuses + have equivalent meaning at this + level. If the function returns + anything other than EFI_SUCCESS, + the value of AuthenticationStatus + is undefined. + + @retval EFI_SUCCESS The InputSection was successfully + processed and the section contents were + returned. + + @retval EFI_OUT_OF_RESOURCES The system has insufficient + resources to process the + request. + + @retval EFI_INVALID_PARAMETER The GUID in InputSection does + not match this instance of the + GUIDed Section Extraction + Protocol. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXTRACT_GUIDED_SECTION)( + IN CONST EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL *This, + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + OUT UINTN *OutputSize, + OUT UINT32 *AuthenticationStatus +); + + +/// +/// Typically, protocol interface structures are identified by associating them with a GUID. Each +/// instance of a protocol with a given GUID must have the same interface structure. While all instances +/// of the GUIDed Section Extraction Protocol must have the same interface structure, they do not all +/// have the same GUID. The GUID that is associated with an instance of the GUIDed Section +/// Extraction Protocol is used to correlate it with the GUIDed section type that it is intended to process. +/// +struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL { + EFI_EXTRACT_GUIDED_SECTION ExtractSection; +}; + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash.h new file mode 100644 index 0000000000..178926a1c4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash.h @@ -0,0 +1,169 @@ +/** @file + EFI_HASH_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0. + EFI_HASH_PROTOCOL as defined in UEFI 2.0. + The EFI Hash Service Binding Protocol is used to locate hashing services support + provided by a driver and to create and destroy instances of the EFI Hash Protocol + so that a multiple drivers can use the underlying hashing services. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_HASH_PROTOCOL_H__ +#define __EFI_HASH_PROTOCOL_H__ + +#define EFI_HASH_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x42881c98, 0xa4f3, 0x44b0, {0xa3, 0x9d, 0xdf, 0xa1, 0x86, 0x67, 0xd8, 0xcd } \ + } + +#define EFI_HASH_PROTOCOL_GUID \ + { \ + 0xc5184932, 0xdba5, 0x46db, {0xa5, 0xba, 0xcc, 0x0b, 0xda, 0x9c, 0x14, 0x35 } \ + } + +#define EFI_HASH_ALGORITHM_SHA1_GUID \ + { \ + 0x2ae9d80f, 0x3fb2, 0x4095, {0xb7, 0xb1, 0xe9, 0x31, 0x57, 0xb9, 0x46, 0xb6 } \ + } + +#define EFI_HASH_ALGORITHM_SHA224_GUID \ + { \ + 0x8df01a06, 0x9bd5, 0x4bf7, {0xb0, 0x21, 0xdb, 0x4f, 0xd9, 0xcc, 0xf4, 0x5b } \ + } + +#define EFI_HASH_ALGORITHM_SHA256_GUID \ + { \ + 0x51aa59de, 0xfdf2, 0x4ea3, {0xbc, 0x63, 0x87, 0x5f, 0xb7, 0x84, 0x2e, 0xe9 } \ + } + +#define EFI_HASH_ALGORITHM_SHA384_GUID \ + { \ + 0xefa96432, 0xde33, 0x4dd2, {0xae, 0xe6, 0x32, 0x8c, 0x33, 0xdf, 0x77, 0x7a } \ + } + +#define EFI_HASH_ALGORITHM_SHA512_GUID \ + { \ + 0xcaa4381e, 0x750c, 0x4770, {0xb8, 0x70, 0x7a, 0x23, 0xb4, 0xe4, 0x21, 0x30 } \ + } + +#define EFI_HASH_ALGORTIHM_MD5_GUID \ + { \ + 0xaf7c79c, 0x65b5, 0x4319, {0xb0, 0xae, 0x44, 0xec, 0x48, 0x4e, 0x4a, 0xd7 } \ + } + +#define EFI_HASH_ALGORITHM_SHA1_NOPAD_GUID \ + { \ + 0x24c5dc2f, 0x53e2, 0x40ca, {0x9e, 0xd6, 0xa5, 0xd9, 0xa4, 0x9f, 0x46, 0x3b } \ + } + +#define EFI_HASH_ALGORITHM_SHA256_NOPAD_GUID \ + { \ + 0x8628752a, 0x6cb7, 0x4814, {0x96, 0xfc, 0x24, 0xa8, 0x15, 0xac, 0x22, 0x26 } \ + } + +// +// Note: Use of the following algorithms with EFI_HASH_PROTOCOL is deprecated. +// EFI_HASH_ALGORITHM_SHA1_GUID +// EFI_HASH_ALGORITHM_SHA224_GUID +// EFI_HASH_ALGORITHM_SHA256_GUID +// EFI_HASH_ALGORITHM_SHA384_GUID +// EFI_HASH_ALGORITHM_SHA512_GUID +// EFI_HASH_ALGORTIHM_MD5_GUID +// + +typedef struct _EFI_HASH_PROTOCOL EFI_HASH_PROTOCOL; + +typedef UINT8 EFI_MD5_HASH[16]; +typedef UINT8 EFI_SHA1_HASH[20]; +typedef UINT8 EFI_SHA224_HASH[28]; +typedef UINT8 EFI_SHA256_HASH[32]; +typedef UINT8 EFI_SHA384_HASH[48]; +typedef UINT8 EFI_SHA512_HASH[64]; + +typedef union { + EFI_MD5_HASH *Md5Hash; + EFI_SHA1_HASH *Sha1Hash; + EFI_SHA224_HASH *Sha224Hash; + EFI_SHA256_HASH *Sha256Hash; + EFI_SHA384_HASH *Sha384Hash; + EFI_SHA512_HASH *Sha512Hash; +} EFI_HASH_OUTPUT; + +/** + Returns the size of the hash which results from a specific algorithm. + + @param[in] This Points to this instance of EFI_HASH_PROTOCOL. + @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use. + @param[out] HashSize Holds the returned size of the algorithm's hash. + + @retval EFI_SUCCESS Hash size returned successfully. + @retval EFI_INVALID_PARAMETER HashSize is NULL or HashAlgorithm is NULL. + @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported + by this driver. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH_GET_HASH_SIZE)( + IN CONST EFI_HASH_PROTOCOL *This, + IN CONST EFI_GUID *HashAlgorithm, + OUT UINTN *HashSize + ); + +/** + Creates a hash for the specified message text. + + @param[in] This Points to this instance of EFI_HASH_PROTOCOL. + @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use. + @param[in] Extend Specifies whether to create a new hash (FALSE) or extend the specified + existing hash (TRUE). + @param[in] Message Points to the start of the message. + @param[in] MessageSize The size of Message, in bytes. + @param[in,out] Hash On input, if Extend is TRUE, then this parameter holds a pointer + to a pointer to an array containing the hash to extend. If Extend + is FALSE, then this parameter holds a pointer to a pointer to a + caller-allocated array that will receive the result of the hash + computation. On output (regardless of the value of Extend), the + array will contain the result of the hash computation. + + @retval EFI_SUCCESS Hash returned successfully. + @retval EFI_INVALID_PARAMETER Message or Hash, HashAlgorithm is NULL or MessageSize is 0. + MessageSize is not an integer multiple of block size. + @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this + driver. Or, Extend is TRUE, and the algorithm doesn't support extending the hash. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH_HASH)( + IN CONST EFI_HASH_PROTOCOL *This, + IN CONST EFI_GUID *HashAlgorithm, + IN BOOLEAN Extend, + IN CONST UINT8 *Message, + IN UINT64 MessageSize, + IN OUT EFI_HASH_OUTPUT *Hash + ); + +/// +/// This protocol allows creating a hash of an arbitrary message digest +/// using one or more hash algorithms. +/// +struct _EFI_HASH_PROTOCOL { + EFI_HASH_GET_HASH_SIZE GetHashSize; + EFI_HASH_HASH Hash; +}; + +extern EFI_GUID gEfiHashServiceBindingProtocolGuid; +extern EFI_GUID gEfiHashProtocolGuid; +extern EFI_GUID gEfiHashAlgorithmSha1Guid; +extern EFI_GUID gEfiHashAlgorithmSha224Guid; +extern EFI_GUID gEfiHashAlgorithmSha256Guid; +extern EFI_GUID gEfiHashAlgorithmSha384Guid; +extern EFI_GUID gEfiHashAlgorithmSha512Guid; +extern EFI_GUID gEfiHashAlgorithmMD5Guid; +extern EFI_GUID gEfiHashAlgorithmSha1NoPadGuid; +extern EFI_GUID gEfiHashAlgorithmSha256NoPadGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash2.h new file mode 100644 index 0000000000..9ad0e3023d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Hash2.h @@ -0,0 +1,196 @@ +/** @file + EFI_HASH2_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.5. + EFI_HASH2_PROTOCOL as defined in UEFI 2.5. + The EFI Hash2 Service Binding Protocol is used to locate hashing services support + provided by a driver and to create and destroy instances of the EFI Hash2 Protocol + so that a multiple drivers can use the underlying hashing services. + EFI_HASH2_PROTOCOL describes hashing functions for which the algorithm-required + message padding and finalization are performed by the supporting driver. + +Copyright (c) 2015, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_HASH2_PROTOCOL_H__ +#define __EFI_HASH2_PROTOCOL_H__ + +#define EFI_HASH2_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xda836f8d, 0x217f, 0x4ca0, { 0x99, 0xc2, 0x1c, 0xa4, 0xe1, 0x60, 0x77, 0xea } \ + } + +#define EFI_HASH2_PROTOCOL_GUID \ + { \ + 0x55b1d734, 0xc5e1, 0x49db, { 0x96, 0x47, 0xb1, 0x6a, 0xfb, 0xe, 0x30, 0x5b } \ + } + +#include + +// +// NOTE: +// Algorithms EFI_HASH_ALGORITHM_SHA1_NOPAD and +// EFI_HASH_ALGORITHM_SHA256_NOPAD_GUID are not compatible with +// EFI_HASH2_PROTOCOL and will return EFI_UNSUPPORTED if used with any +// EFI_HASH2_PROTOCOL function. +// + +// +// Note: SHA-1 and MD5 are included for backwards compatibility. +// New driver implementations are encouraged to consider stronger algorithms. +// + +typedef struct _EFI_HASH2_PROTOCOL EFI_HASH2_PROTOCOL; + +typedef UINT8 EFI_MD5_HASH2[16]; +typedef UINT8 EFI_SHA1_HASH2[20]; +typedef UINT8 EFI_SHA224_HASH2[28]; +typedef UINT8 EFI_SHA256_HASH2[32]; +typedef UINT8 EFI_SHA384_HASH2[48]; +typedef UINT8 EFI_SHA512_HASH2[64]; + +typedef union { + EFI_MD5_HASH2 Md5Hash; + EFI_SHA1_HASH2 Sha1Hash; + EFI_SHA224_HASH2 Sha224Hash; + EFI_SHA256_HASH2 Sha256Hash; + EFI_SHA384_HASH2 Sha384Hash; + EFI_SHA512_HASH2 Sha512Hash; +} EFI_HASH2_OUTPUT; + +/** + Returns the size of the hash which results from a specific algorithm. + + @param[in] This Points to this instance of EFI_HASH2_PROTOCOL. + @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use. + @param[out] HashSize Holds the returned size of the algorithm's hash. + + @retval EFI_SUCCESS Hash size returned successfully. + @retval EFI_INVALID_PARAMETER This or HashSize is NULL. + @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver + or HashAlgorithm is null. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH2_GET_HASH_SIZE)( + IN CONST EFI_HASH2_PROTOCOL *This, + IN CONST EFI_GUID *HashAlgorithm, + OUT UINTN *HashSize + ); + +/** + Creates a hash for the specified message text. The hash is not extendable. + The output is final with any algorithm-required padding added by the function. + + @param[in] This Points to this instance of EFI_HASH2_PROTOCOL. + @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use. + @param[in] Message Points to the start of the message. + @param[in] MessageSize The size of Message, in bytes. + @param[in,out] Hash On input, points to a caller-allocated buffer of the size + returned by GetHashSize() for the specified HashAlgorithm. + On output, the buffer holds the resulting hash computed from the message. + + @retval EFI_SUCCESS Hash returned successfully. + @retval EFI_INVALID_PARAMETER This or Hash is NULL. + @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver + or HashAlgorithm is Null. + @retval EFI_OUT_OF_RESOURCES Some resource required by the function is not available + or MessageSize is greater than platform maximum. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH2_HASH)( + IN CONST EFI_HASH2_PROTOCOL *This, + IN CONST EFI_GUID *HashAlgorithm, + IN CONST UINT8 *Message, + IN UINTN MessageSize, + IN OUT EFI_HASH2_OUTPUT *Hash + ); + +/** + This function must be called to initialize a digest calculation to be subsequently performed using the + EFI_HASH2_PROTOCOL functions HashUpdate() and HashFinal(). + + @param[in] This Points to this instance of EFI_HASH2_PROTOCOL. + @param[in] HashAlgorithm Points to the EFI_GUID which identifies the algorithm to use. + + @retval EFI_SUCCESS Initialized successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_UNSUPPORTED The algorithm specified by HashAlgorithm is not supported by this driver + or HashAlgorithm is Null. + @retval EFI_OUT_OF_RESOURCES Process failed due to lack of required resource. + @retval EFI_ALREADY_STARTED This function is called when the operation in progress is still in processing Hash(), + or HashInit() is already called before and not terminated by HashFinal() yet on the same instance. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH2_HASH_INIT)( + IN CONST EFI_HASH2_PROTOCOL *This, + IN CONST EFI_GUID *HashAlgorithm + ); + +/** + Updates the hash of a computation in progress by adding a message text. + + @param[in] This Points to this instance of EFI_HASH2_PROTOCOL. + @param[in] Message Points to the start of the message. + @param[in] MessageSize The size of Message, in bytes. + + @retval EFI_SUCCESS Digest in progress updated successfully. + @retval EFI_INVALID_PARAMETER This or Hash is NULL. + @retval EFI_OUT_OF_RESOURCES Some resource required by the function is not available + or MessageSize is greater than platform maximum. + @retval EFI_NOT_READY This call was not preceded by a valid call to HashInit(), + or the operation in progress was terminated by a call to Hash() or HashFinal() on the same instance. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH2_HASH_UPDATE)( + IN CONST EFI_HASH2_PROTOCOL *This, + IN CONST UINT8 *Message, + IN UINTN MessageSize + ); + +/** + Finalizes a hash operation in progress and returns calculation result. + The output is final with any necessary padding added by the function. + The hash may not be further updated or extended after HashFinal(). + + @param[in] This Points to this instance of EFI_HASH2_PROTOCOL. + @param[in,out] Hash On input, points to a caller-allocated buffer of the size + returned by GetHashSize() for the specified HashAlgorithm specified in preceding HashInit(). + On output, the buffer holds the resulting hash computed from the message. + + @retval EFI_SUCCESS Hash returned successfully. + @retval EFI_INVALID_PARAMETER This or Hash is NULL. + @retval EFI_NOT_READY This call was not preceded by a valid call to HashInit() and at least one call to HashUpdate(), + or the operation in progress was canceled by a call to Hash() on the same instance. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HASH2_HASH_FINAL)( + IN CONST EFI_HASH2_PROTOCOL *This, + IN OUT EFI_HASH2_OUTPUT *Hash + ); + +/// +/// This protocol describes hashing functions for which the algorithm-required message padding and +/// finalization are performed by the supporting driver. +/// +struct _EFI_HASH2_PROTOCOL { + EFI_HASH2_GET_HASH_SIZE GetHashSize; + EFI_HASH2_HASH Hash; + EFI_HASH2_HASH_INIT HashInit; + EFI_HASH2_HASH_UPDATE HashUpdate; + EFI_HASH2_HASH_FINAL HashFinal; +}; + +extern EFI_GUID gEfiHash2ServiceBindingProtocolGuid; +extern EFI_GUID gEfiHash2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigAccess.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigAccess.h new file mode 100644 index 0000000000..21feba5fea --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigAccess.h @@ -0,0 +1,220 @@ +/** @file + + The EFI HII results processing protocol invokes this type of protocol + when it needs to forward results to a driver's configuration handler. + This protocol is published by drivers providing and requesting + configuration data from HII. It may only be invoked by HII. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + +**/ + + +#ifndef __EFI_HII_CONFIG_ACCESS_H__ +#define __EFI_HII_CONFIG_ACCESS_H__ + +#include + +#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \ + { 0x330d4706, 0xf2a0, 0x4e4f, { 0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85 } } + +typedef struct _EFI_HII_CONFIG_ACCESS_PROTOCOL EFI_HII_CONFIG_ACCESS_PROTOCOL; + +typedef UINTN EFI_BROWSER_ACTION; + +#define EFI_BROWSER_ACTION_CHANGING 0 +#define EFI_BROWSER_ACTION_CHANGED 1 +#define EFI_BROWSER_ACTION_RETRIEVE 2 +#define EFI_BROWSER_ACTION_FORM_OPEN 3 +#define EFI_BROWSER_ACTION_FORM_CLOSE 4 +#define EFI_BROWSER_ACTION_SUBMITTED 5 +#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000 +#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001 +#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002 +#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000 +#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000 +#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000 + +/** + + This function allows the caller to request the current + configuration for one or more named elements. The resulting + string is in format. Any and all alternative + configuration strings shall also be appended to the end of the + current configuration string. If they are, they must appear + after the current configuration. They must contain the same + routing (GUID, NAME, PATH) as the current configuration string. + They must have an additional description indicating the type of + alternative configuration the string represents, + "ALTCFG=". That (when + converted from Hex UNICODE to binary) is a reference to a + string in the associated string pack. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. + + @param Request A null-terminated Unicode string in + format. Note that this + includes the routing information as well as + the configurable name / value pairs. It is + invalid for this string to be in + format. + If a NULL is passed in for the Request field, + all of the settings being abstracted by this function + will be returned in the Results field. In addition, + if a ConfigHdr is passed in with no request elements, + all of the settings being abstracted for that particular + ConfigHdr reference will be returned in the Results Field. + + @param Progress On return, points to a character in the + Request string. Points to the string's null + terminator if request was successful. Points + to the most recent "&" before the first + failing name / value pair (or the beginning + of the string if the failure is in the first + name / value pair) if the request was not + successful. + + @param Results A null-terminated Unicode string in + format which has all values + filled in for the names in the Request string. + String to be allocated by the called function. + + @retval EFI_SUCCESS The Results string is filled with the + values corresponding to all requested + names. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the + parts of the results that must be + stored awaiting possible future + protocols. + + @retval EFI_NOT_FOUND A configuration element matching + the routing data is not found. + Progress set to the first character + in the routing header. + + @retval EFI_INVALID_PARAMETER Illegal syntax. Progress set + to most recent "&" before the + error or the beginning of the + string. + + @retval EFI_INVALID_PARAMETER Unknown name. Progress points + to the & before the name in + question. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_ACCESS_EXTRACT_CONFIG)( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN CONST EFI_STRING Request, + OUT EFI_STRING *Progress, + OUT EFI_STRING *Results +); + + +/** + + This function applies changes in a driver's configuration. + Input is a Configuration, which has the routing data for this + driver followed by name / value configuration pairs. The driver + must apply those pairs to its configurable storage. If the + driver's configuration is stored in a linear block of data + and the driver's name / value pairs are in + format, it may use the ConfigToBlock helper function (above) to + simplify the job. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. + + @param Configuration A null-terminated Unicode string in + format. + + @param Progress A pointer to a string filled in with the + offset of the most recent '&' before the + first failing name / value pair (or the + beginn ing of the string if the failure + is in the first name / value pair) or + the terminating NULL if all was + successful. + + @retval EFI_SUCCESS The results have been distributed or are + awaiting distribution. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the + parts of the results that must be + stored awaiting possible future + protocols. + + @retval EFI_INVALID_PARAMETERS Passing in a NULL for the + Results parameter would result + in this type of error. + + @retval EFI_NOT_FOUND Target for the specified routing data + was not found + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_ACCESS_ROUTE_CONFIG)( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN CONST EFI_STRING Configuration, + OUT EFI_STRING *Progress +); + +/** + + This function is called to provide results data to the driver. + This data consists of a unique key that is used to identify + which data is either being passed back or being asked for. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL. + @param Action Specifies the type of action taken by the browser. + @param QuestionId A unique value which is sent to the original + exporting driver so that it can identify the type + of data to expect. The format of the data tends to + vary based on the opcode that generated the callback. + @param Type The type of value for the question. + @param Value A pointer to the data being sent to the original + exporting driver. + @param ActionRequest On return, points to the action requested by the + callback function. + + @retval EFI_SUCCESS The callback successfully handled the action. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the + variable and its data. + @retval EFI_DEVICE_ERROR The variable could not be saved. + @retval EFI_UNSUPPORTED The specified Action is not supported by the + callback. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_ACCESS_FORM_CALLBACK)( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN EFI_BROWSER_ACTION Action, + IN EFI_QUESTION_ID QuestionId, + IN UINT8 Type, + IN OUT EFI_IFR_TYPE_VALUE *Value, + OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest + ) + ; + +/// +/// This protocol provides a callable interface between the HII and +/// drivers. Only drivers which provide IFR data to HII are required +/// to publish this protocol. +/// +struct _EFI_HII_CONFIG_ACCESS_PROTOCOL { + EFI_HII_ACCESS_EXTRACT_CONFIG ExtractConfig; + EFI_HII_ACCESS_ROUTE_CONFIG RouteConfig; + EFI_HII_ACCESS_FORM_CALLBACK Callback; +} ; + +extern EFI_GUID gEfiHiiConfigAccessProtocolGuid; + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigKeyword.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigKeyword.h new file mode 100644 index 0000000000..5786fbc369 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigKeyword.h @@ -0,0 +1,199 @@ +/** @file + The file provides the mechanism to set and get the values + associated with a keyword exposed through a x-UEFI- prefixed + configuration language namespace. + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + + +**/ + +#ifndef __EFI_CONFIG_KEYWORD_HANDLER_H__ +#define __EFI_CONFIG_KEYWORD_HANDLER_H__ + +#define EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL_GUID \ +{ \ + 0x0a8badd5, 0x03b8, 0x4d19, {0xb1, 0x28, 0x7b, 0x8f, 0x0e, 0xda, 0xa5, 0x96 } \ +} + +//*********************************************************** +// Progress Errors +//*********************************************************** +#define KEYWORD_HANDLER_NO_ERROR 0x00000000 +#define KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND 0x00000001 +#define KEYWORD_HANDLER_MALFORMED_STRING 0x00000002 +#define KEYWORD_HANDLER_KEYWORD_NOT_FOUND 0x00000004 +#define KEYWORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED 0x00000008 +#define KEYWORD_HANDLER_ACCESS_NOT_PERMITTED 0x00000010 +#define KEYWORD_HANDLER_UNDEFINED_PROCESSING_ERROR 0x80000000 + +typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL; + +/** + + This function accepts a formatted string, finds the associated + keyword owners, creates a string from it and forwards it to the + EFI_HII_ROUTING_PROTOCOL.RouteConfig function. + + If there is an issue in resolving the contents of the KeywordString, then the + function returns an error and also sets the Progress and ProgressErr with the + appropriate information about where the issue occurred and additional data about + the nature of the issue. + + In the case when KeywordString containing multiple keywords, when an EFI_NOT_FOUND + error is generated during processing the second or later keyword element, the system + storage associated with earlier keywords is not modified. All elements of the + KeywordString must successfully pass all tests for format and access prior to making + any modifications to storage. + + In the case when EFI_DEVICE_ERROR is returned from the processing of a KeywordString + containing multiple keywords, the state of storage associated with earlier keywords + is undefined. + + + @param This Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance. + + @param KeywordString A null-terminated string in format. + + @param Progress On return, points to a character in the KeywordString. + Points to the string's NULL terminator if the request + was successful. Points to the most recent '&' before + the first failing name / value pair (or the beginning + of the string if the failure is in the first name / value + pair) if the request was not successful. + + @param ProgressErr If during the processing of the KeywordString there was + a failure, this parameter gives additional information + about the possible source of the problem. The various + errors are defined in "Related Definitions" below. + + + @retval EFI_SUCCESS The specified action was completed successfully. + + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + 1. KeywordString is NULL. + 2. Parsing of the KeywordString resulted in an + error. See Progress and ProgressErr for more data. + + @retval EFI_NOT_FOUND An element of the KeywordString was not found. + See ProgressErr for more data. + + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + See ProgressErr for more data. + + @retval EFI_ACCESS_DENIED The action violated system policy. See ProgressErr + for more data. + + @retval EFI_DEVICE_ERROR An unexpected system error occurred. See ProgressErr + for more data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_SET_DATA) ( + IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This, + IN CONST EFI_STRING KeywordString, + OUT EFI_STRING *Progress, + OUT UINT32 *ProgressErr + ); + + +/** + + This function accepts a formatted string, finds the underlying + keyword owners, creates a string from it and forwards it to the + EFI_HII_ROUTING_PROTOCOL.ExtractConfig function. + + If there is an issue in resolving the contents of the KeywordString, then the function + returns an EFI_INVALID_PARAMETER and also set the Progress and ProgressErr with the + appropriate information about where the issue occurred and additional data about the + nature of the issue. + + In the case when KeywordString is NULL, or contains multiple keywords, or when + EFI_NOT_FOUND is generated while processing the keyword elements, the Results string + contains values returned for all keywords processed prior to the keyword generating the + error but no values for the keyword with error or any following keywords. + + + @param This Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance. + + @param NameSpaceId A null-terminated string containing the platform configuration + language to search through in the system. If a NULL is passed + in, then it is assumed that any platform configuration language + with the prefix of "x-UEFI-" are searched. + + @param KeywordString A null-terminated string in format. If a + NULL is passed in the KeywordString field, all of the known + keywords in the system for the NameSpaceId specified are + returned in the Results field. + + @param Progress On return, points to a character in the KeywordString. Points + to the string's NULL terminator if the request was successful. + Points to the most recent '&' before the first failing name / value + pair (or the beginning of the string if the failure is in the first + name / value pair) if the request was not successful. + + @param ProgressErr If during the processing of the KeywordString there was a + failure, this parameter gives additional information about the + possible source of the problem. See the definitions in SetData() + for valid value definitions. + + @param Results A null-terminated string in format is returned + which has all the values filled in for the keywords in the + KeywordString. This is a callee-allocated field, and must be freed + by the caller after being used. + + @retval EFI_SUCCESS The specified action was completed successfully. + + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + 1.Progress, ProgressErr, or Results is NULL. + 2.Parsing of the KeywordString resulted in an error. See + Progress and ProgressErr for more data. + + + @retval EFI_NOT_FOUND An element of the KeywordString was not found. See + ProgressErr for more data. + + @retval EFI_NOT_FOUND The NamespaceId specified was not found. See ProgressErr + for more data. + + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. See + ProgressErr for more data. + + @retval EFI_ACCESS_DENIED The action violated system policy. See ProgressErr for + more data. + + @retval EFI_DEVICE_ERROR An unexpected system error occurred. See ProgressErr + for more data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_GET_DATA) ( + IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This, + IN CONST EFI_STRING NameSpaceId, OPTIONAL + IN CONST EFI_STRING KeywordString, OPTIONAL + OUT EFI_STRING *Progress, + OUT UINT32 *ProgressErr, + OUT EFI_STRING *Results + ); + +/// +/// The EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL provides the mechanism +/// to set and get the values associated with a keyword exposed +/// through a x-UEFI- prefixed configuration language namespace +/// + +struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL { + EFI_CONFIG_KEYWORD_HANDLER_SET_DATA SetData; + EFI_CONFIG_KEYWORD_HANDLER_GET_DATA GetData; +}; + +extern EFI_GUID gEfiConfigKeywordHandlerProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigRouting.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigRouting.h new file mode 100644 index 0000000000..88f98d19fd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiConfigRouting.h @@ -0,0 +1,417 @@ +/** @file + The file provides services to manage the movement of + configuration data from drivers to configuration applications. + It then serves as the single point to receive configuration + information from configuration applications, routing the + results to the appropriate drivers. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + + +**/ + +#ifndef __HII_CONFIG_ROUTING_H__ +#define __HII_CONFIG_ROUTING_H__ + +#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \ + { 0x587e72d7, 0xcc50, 0x4f79, { 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f } } + + +typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL; + +/** + + This function allows the caller to request the current + configuration for one or more named elements from one or more + drivers. The resulting string is in the standard HII + configuration string format. If Successful, Results contains an + equivalent string with "=" and the values associated with all + names added in. The expected implementation is for each + substring in the Request to call the HII + Configuration Routing Protocol ExtractProtocol function for the + driver corresponding to the at the start of the + substring. The request fails if no driver + matches the substring. Note: Alternative + configuration strings may also be appended to the end of the + current configuration string. If they are, they must appear + after the current configuration. They must contain the same + routing (GUID, NAME, PATH) as the current configuration string. + They must have an additional description indicating the type of + alternative configuration the string represents, + "ALTCFG=". That (when converted from + hexadecimal (encoded as text) to binary) is a reference to a string in the + associated string pack. As an example, assume that the Request + string is: + GUID=...&NAME=00480050&PATH=...&Fred&George&Ron&Neville A result + might be: + GUID=...&NAME=00480050&PATH=...&Fred=16&George=16&Ron=12&Neville=11& + GUID=...&NAME=00480050&PATH=...&ALTCFG=0037&Fred=12&Neville=7 + + @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL + instance. + + @param Request A null-terminated string in format. + + @param Progress On return, points to a character in the + Request string. Points to the string's null + terminator if the request was successful. Points + to the most recent '&' before the first + failing name / value pair (or the beginning + of the string if the failure is in the first + name / value pair) if the request was not + successful + + @param Results A null-terminated string in format + which has all values filled in for the names in the + Request string. + + @retval EFI_SUCCESS The Results string is filled with the + values corresponding to all requested + names. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the + parts of the results that must be + stored awaiting possible future + protocols. + + @retval EFI_INVALID_PARAMETER For example, passing in a NULL + for the Request parameter + would result in this type of + error. The Progress parameter + is set to NULL. + + @retval EFI_NOT_FOUND Routing data doesn't match any + known driver. Progress set to + the "G" in "GUID" of the + routing header that doesn't + match. Note: There is no + requirement that all routing + data be validated before any + configuration extraction. + + @retval EFI_INVALID_PARAMETER Illegal syntax. Progress set + to the most recent & before the + error, or the beginning of the + string. + @retval EFI_INVALID_PARAMETER The ExtractConfig function of the + underlying HII Configuration + Access Protocol returned + EFI_INVALID_PARAMETER. Progress + set to most recent & before the + error or the beginning of the + string. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_EXTRACT_CONFIG)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + IN CONST EFI_STRING Request, + OUT EFI_STRING *Progress, + OUT EFI_STRING *Results +); + +/** + This function allows the caller to request the current configuration + for the entirety of the current HII database and returns the data in + a null-terminated string. + + This function allows the caller to request the current + configuration for all of the current HII database. The results + include both the current and alternate configurations as + described in ExtractConfig() above. + + @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance. + + @param Results Null-terminated Unicode string in + format which has all values + filled in for the entirety of the current HII + database. String to be allocated by the called + function. De-allocation is up to the caller. + + @retval EFI_SUCCESS The Results string is filled with the + values corresponding to all requested + names. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the + parts of the results that must be + stored awaiting possible future + protocols. + + @retval EFI_INVALID_PARAMETERS For example, passing in a NULL + for the Results parameter + would result in this type of + error. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_EXPORT_CONFIG)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + OUT EFI_STRING *Results +); + +/** + + This function routes the results of processing forms to the + appropriate targets. It scans for within the string + and passes the header and subsequent body to the driver whose + location is described in the . Many s may + appear as a single request. The expected implementation is to + hand off the various substrings to the + Configuration Access Protocol RouteConfig routine corresponding + to the driver whose routing information is defined by the + in turn. + + @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance. + + @param Configuration A null-terminated string in format. + + @param Progress A pointer to a string filled in with the + offset of the most recent '&' before the + first failing name / value pair (or the + beginning of the string if the failure is in + the first name / value pair), or the + terminating NULL if all was successful. + + @retval EFI_SUCCESS The results have been distributed or are + awaiting distribution. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the + parts of the results that must be + stored awaiting possible future + protocols. + + @retval EFI_INVALID_PARAMETERS Passing in a NULL for the + Results parameter would result + in this type of error. + + @retval EFI_NOT_FOUND The target for the specified routing data + was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_ROUTE_CONFIG)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + IN CONST EFI_STRING Configuration, + OUT EFI_STRING *Progress +); + + +/** + + This function extracts the current configuration from a block of + bytes. To do so, it requires that the ConfigRequest string + consists of a list of formatted names. It uses the + offset in the name to determine the index into the Block to + start the extraction and the width of each name to determine the + number of bytes to extract. These are mapped to a string + using the equivalent of the C "%x" format (with optional leading + spaces). The call fails if, for any (offset, width) pair in + ConfigRequest, offset+value >= BlockSize. + + @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance. + + @param ConfigRequest A null-terminated string in format. + + @param Block An array of bytes defining the block's + configuration. + + @param BlockSize The length in bytes of Block. + + @param Config The filled-in configuration string. String + allocated by the function. Returned only if + call is successful. The null-terminated string + will be format. + + @param Progress A pointer to a string filled in with the + offset of the most recent '&' before the + first failing name / value pair (or the + beginning of the string if the failure is in + the first name / value pair), or the + terminating NULL if all was successful. + + @retval EFI_SUCCESS The request succeeded. Progress points + to the null terminator at the end of the + ConfigRequest string. + + @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate + Config. Progress points to the + first character of ConfigRequest. + + @retval EFI_INVALID_PARAMETERS Passing in a NULL for the + ConfigRequest or Block + parameter would result in this + type of error. Progress points + to the first character of + ConfigRequest. + + @retval EFI_NOT_FOUND The target for the specified routing data + was not found. Progress points to the + 'G' in "GUID" of the errant routing + data. + @retval EFI_DEVICE_ERROR The block is not large enough. Progress undefined. + + @retval EFI_INVALID_PARAMETER Encountered non + formatted string. Block is + left updated and Progress + points at the '&' preceding + the first non-. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_BLOCK_TO_CONFIG)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + IN CONST EFI_STRING ConfigRequest, + IN CONST UINT8 *Block, + IN CONST UINTN BlockSize, + OUT EFI_STRING *Config, + OUT EFI_STRING *Progress +); + + + +/** + This function maps a configuration containing a series of + formatted name value pairs in ConfigResp into a + Block so it may be stored in a linear mapped storage such as a + UEFI Variable. If present, the function skips GUID, NAME, and + PATH in . It stops when it finds a non- + name / value pair (after skipping the routing header) or when it + reaches the end of the string. + Example Assume an existing block containing: 00 01 02 03 04 05 + And the ConfigResp string is: + OFFSET=4&WIDTH=1&VALUE=7&OFFSET=0&WIDTH=2&VALUE=AA55 + The results are + 55 AA 02 07 04 05 + + @param This Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance. + + @param ConfigResp A null-terminated string in format. + + @param Block A possibly null array of bytes + representing the current block. Only + bytes referenced in the ConfigResp + string in the block are modified. If + this parameter is null or if the + BlockLength parameter is (on input) + shorter than required by the + Configuration string, only the BlockSize + parameter is updated, and an appropriate + status (see below) is returned. + + @param BlockSize The length of the Block in units of UINT8. + On input, this is the size of the Block. On + output, if successful, contains the largest + index of the modified byte in the Block, or + the required buffer size if the Block is not + large enough. + + @param Progress On return, points to an element of the + ConfigResp string filled in with the offset + of the most recent "&" before the first + failing name / value pair (or the beginning + of the string if the failure is in the first + name / value pair), or the terminating NULL + if all was successful. + + @retval EFI_SUCCESS The request succeeded. Progress points to the null + terminator at the end of the ConfigResp string. + @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate Config. Progress + points to the first character of ConfigResp. + @retval EFI_INVALID_PARAMETER Passing in a NULL for the ConfigResp or + Block parameter would result in this type of + error. Progress points to the first character of + ConfigResp. + @retval EFI_INVALID_PARAMETER Encountered non formatted name / + value pair. Block is left updated and + Progress points at the '&' preceding the first + non-. + @retval EFI_DEVICE_ERROR Block not large enough. Progress undefined. + @retval EFI_NOT_FOUND Target for the specified routing data was not found. + Progress points to the "G" in "GUID" of the errant + routing data. + @retval EFI_BUFFER_TOO_SMALL Block not large enough. Progress undefined. + BlockSize is updated with the required buffer size. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_CONFIG_TO_BLOCK)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + IN CONST EFI_STRING ConfigResp, + IN OUT UINT8 *Block, + IN OUT UINTN *BlockSize, + OUT EFI_STRING *Progress +); + +/** + This helper function is to be called by drivers to extract portions of + a larger configuration string. + + @param This A pointer to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance. + @param ConfigResp A null-terminated string in format. + @param Guid A pointer to the GUID value to search for in the + routing portion of the ConfigResp string when retrieving + the requested data. If Guid is NULL, then all GUID + values will be searched for. + @param Name A pointer to the NAME value to search for in the + routing portion of the ConfigResp string when retrieving + the requested data. If Name is NULL, then all Name + values will be searched for. + @param DevicePath A pointer to the PATH value to search for in the + routing portion of the ConfigResp string when retrieving + the requested data. If DevicePath is NULL, then all + DevicePath values will be searched for. + @param AltCfgId A pointer to the ALTCFG value to search for in the + routing portion of the ConfigResp string when retrieving + the requested data. If this parameter is NULL, + then the current setting will be retrieved. + @param AltCfgResp A pointer to a buffer which will be allocated by the + function which contains the retrieved string as requested. + This buffer is only allocated if the call was successful. + The null-terminated string will be format. + + @retval EFI_SUCCESS The request succeeded. The requested data was extracted + and placed in the newly allocated AltCfgResp buffer. + @retval EFI_OUT_OF_RESOURCES Not enough memory to allocate AltCfgResp. + @retval EFI_INVALID_PARAMETER Any parameter is invalid. + @retval EFI_NOT_FOUND The target for the specified routing data was not found. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_GET_ALT_CFG)( + IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This, + IN CONST EFI_STRING ConfigResp, + IN CONST EFI_GUID *Guid, + IN CONST EFI_STRING Name, + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN CONST UINT16 *AltCfgId, + OUT EFI_STRING *AltCfgResp + ); + +/// +/// This protocol defines the configuration routing interfaces +/// between external applications and the HII. There may only be one +/// instance of this protocol in the system. +/// +struct _EFI_HII_CONFIG_ROUTING_PROTOCOL { + EFI_HII_EXTRACT_CONFIG ExtractConfig; + EFI_HII_EXPORT_CONFIG ExportConfig; + EFI_HII_ROUTE_CONFIG RouteConfig; + EFI_HII_BLOCK_TO_CONFIG BlockToConfig; + EFI_HII_CONFIG_TO_BLOCK ConfigToBlock; + EFI_HII_GET_ALT_CFG GetAltConfig; +}; + +extern EFI_GUID gEfiHiiConfigRoutingProtocolGuid; + + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiDatabase.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiDatabase.h new file mode 100644 index 0000000000..8ea5b7d909 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiDatabase.h @@ -0,0 +1,528 @@ +/** @file + The file provides Database manager for HII-related data + structures. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + +**/ + +#ifndef __HII_DATABASE_H__ +#define __HII_DATABASE_H__ + +#define EFI_HII_DATABASE_PROTOCOL_GUID \ + { 0xef9fc172, 0xa1b2, 0x4693, { 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42 } } + + +typedef struct _EFI_HII_DATABASE_PROTOCOL EFI_HII_DATABASE_PROTOCOL; + + +/// +/// EFI_HII_DATABASE_NOTIFY_TYPE. +/// +typedef UINTN EFI_HII_DATABASE_NOTIFY_TYPE; + +#define EFI_HII_DATABASE_NOTIFY_NEW_PACK 0x00000001 +#define EFI_HII_DATABASE_NOTIFY_REMOVE_PACK 0x00000002 +#define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004 +#define EFI_HII_DATABASE_NOTIFY_ADD_PACK 0x00000008 +/** + + Functions which are registered to receive notification of + database events have this prototype. The actual event is encoded + in NotifyType. The following table describes how PackageType, + PackageGuid, Handle, and Package are used for each of the + notification types. + + @param PackageType Package type of the notification. + + @param PackageGuid If PackageType is + EFI_HII_PACKAGE_TYPE_GUID, then this is + the pointer to the GUID from the Guid + field of EFI_HII_PACKAGE_GUID_HEADER. + Otherwise, it must be NULL. + + @param Package Points to the package referred to by the notification. + + @param Handle The handle of the package + list which contains the specified package. + + @param NotifyType The type of change concerning the + database. See + EFI_HII_DATABASE_NOTIFY_TYPE. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_NOTIFY)( + IN UINT8 PackageType, + IN CONST EFI_GUID *PackageGuid, + IN CONST EFI_HII_PACKAGE_HEADER *Package, + IN EFI_HII_HANDLE Handle, + IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType +); + +/** + + This function adds the packages in the package list to the + database and returns a handle. If there is a + EFI_DEVICE_PATH_PROTOCOL associated with the DriverHandle, then + this function will create a package of type + EFI_PACKAGE_TYPE_DEVICE_PATH and add it to the package list. For + each package in the package list, registered functions with the + notification type NEW_PACK and having the same package type will + be called. For each call to NewPackageList(), there should be a + corresponding call to + EFI_HII_DATABASE_PROTOCOL.RemovePackageList(). + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param PackageList A pointer to an EFI_HII_PACKAGE_LIST_HEADER structure. + + @param DriverHandle Associate the package list with this EFI handle. + If a NULL is specified, this data will not be associate + with any drivers and cannot have a callback induced. + + @param Handle A pointer to the EFI_HII_HANDLE instance. + + @retval EFI_SUCCESS The package list associated with the + Handle was added to the HII database. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate necessary + resources for the new database + contents. + + @retval EFI_INVALID_PARAMETER PackageList is NULL, or Handle is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_NEW_PACK)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList, + IN EFI_HANDLE DriverHandle, OPTIONAL + OUT EFI_HII_HANDLE *Handle +); + + +/** + + This function removes the package list that is associated with a + handle Handle from the HII database. Before removing the + package, any registered functions with the notification type + REMOVE_PACK and the same package type will be called. For each + call to EFI_HII_DATABASE_PROTOCOL.NewPackageList(), there should + be a corresponding call to RemovePackageList. + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param Handle The handle that was registered to the data + that is requested for removal. + + @retval EFI_SUCCESS The data associated with the Handle was + removed from the HII database. + @retval EFI_NOT_FOUND The specified Handle is not in database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_REMOVE_PACK)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN EFI_HII_HANDLE Handle +); + + +/** + + This function updates the existing package list (which has the + specified Handle) in the HII databases, using the new package + list specified by PackageList. The update process has the + following steps: Collect all the package types in the package + list specified by PackageList. A package type consists of the + Type field of EFI_HII_PACKAGE_HEADER and, if the Type is + EFI_HII_PACKAGE_TYPE_GUID, the Guid field, as defined in + EFI_HII_PACKAGE_GUID_HEADER. Iterate through the packages within + the existing package list in the HII database specified by + Handle. If a package's type matches one of the collected types collected + in step 1, then perform the following steps: + - Call any functions registered with the notification type + REMOVE_PACK. + - Remove the package from the package list and the HII + database. + Add all of the packages within the new package list specified + by PackageList, using the following steps: + - Add the package to the package list and the HII database. + - Call any functions registered with the notification type + ADD_PACK. + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param Handle The handle that was registered to the data + that is requested for removal. + + @param PackageList A pointer to an EFI_HII_PACKAGE_LIST + package. + + @retval EFI_SUCCESS The HII database was successfully updated. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate enough memory + for the updated database. + + @retval EFI_INVALID_PARAMETER PackageList was NULL. + @retval EFI_NOT_FOUND The specified Handle is not in database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_UPDATE_PACK)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN EFI_HII_HANDLE Handle, + IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList +); + + +/** + + This function returns a list of the package handles of the + specified type that are currently active in the database. The + pseudo-type EFI_HII_PACKAGE_TYPE_ALL will cause all package + handles to be listed. + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param PackageType Specifies the package type of the packages + to list or EFI_HII_PACKAGE_TYPE_ALL for + all packages to be listed. + + @param PackageGuid If PackageType is + EFI_HII_PACKAGE_TYPE_GUID, then this is + the pointer to the GUID which must match + the Guid field of + EFI_HII_PACKAGE_GUID_HEADER. Otherwise, it + must be NULL. + + @param HandleBufferLength On input, a pointer to the length + of the handle buffer. On output, + the length of the handle buffer + that is required for the handles found. + + @param Handle An array of EFI_HII_HANDLE instances returned. + + @retval EFI_SUCCESS The matching handles are outputted successfully. + HandleBufferLength is updated with the actual length. + @retval EFI_BUFFER_TOO_SMALL The HandleBufferLength parameter + indicates that Handle is too + small to support the number of + handles. HandleBufferLength is + updated with a value that will + enable the data to fit. + @retval EFI_NOT_FOUND No matching handle could be found in database. + @retval EFI_INVALID_PARAMETER HandleBufferLength was NULL. + @retval EFI_INVALID_PARAMETER The value referenced by HandleBufferLength was not + zero and Handle was NULL. + @retval EFI_INVALID_PARAMETER PackageType is not a EFI_HII_PACKAGE_TYPE_GUID but + PackageGuid is not NULL, PackageType is a EFI_HII_ + PACKAGE_TYPE_GUID but PackageGuid is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_LIST_PACKS)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN UINT8 PackageType, + IN CONST EFI_GUID *PackageGuid, + IN OUT UINTN *HandleBufferLength, + OUT EFI_HII_HANDLE *Handle +); + +/** + + This function will export one or all package lists in the + database to a buffer. For each package list exported, this + function will call functions registered with EXPORT_PACK and + then copy the package list to the buffer. The registered + functions may call EFI_HII_DATABASE_PROTOCOL.UpdatePackageList() + to modify the package list before it is copied to the buffer. If + the specified BufferSize is too small, then the status + EFI_OUT_OF_RESOURCES will be returned and the actual package + size will be returned in BufferSize. + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + + @param Handle An EFI_HII_HANDLE that corresponds to the + desired package list in the HII database to + export or NULL to indicate all package lists + should be exported. + + @param BufferSize On input, a pointer to the length of the + buffer. On output, the length of the + buffer that is required for the exported + data. + + @param Buffer A pointer to a buffer that will contain the + results of the export function. + + + @retval EFI_SUCCESS Package exported. + + @retval EFI_OUT_OF_RESOURCES BufferSize is too small to hold the package. + + @retval EFI_NOT_FOUND The specified Handle could not be found in the + current database. + + @retval EFI_INVALID_PARAMETER BufferSize was NULL. + + @retval EFI_INVALID_PARAMETER The value referenced by BufferSize was not zero + and Buffer was NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_EXPORT_PACKS)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN EFI_HII_HANDLE Handle, + IN OUT UINTN *BufferSize, + OUT EFI_HII_PACKAGE_LIST_HEADER *Buffer +); + + +/** + + + This function registers a function which will be called when + specified actions related to packages of the specified type + occur in the HII database. By registering a function, other + HII-related drivers are notified when specific package types + are added, removed or updated in the HII database. Each driver + or application which registers a notification should use + EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify() before + exiting. + + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param PackageType The package type. See + EFI_HII_PACKAGE_TYPE_x in EFI_HII_PACKAGE_HEADER. + + @param PackageGuid If PackageType is + EFI_HII_PACKAGE_TYPE_GUID, then this is + the pointer to the GUID which must match + the Guid field of + EFI_HII_PACKAGE_GUID_HEADER. Otherwise, it + must be NULL. + + @param PackageNotifyFn Points to the function to be called + when the event specified by + NotificationType occurs. See + EFI_HII_DATABASE_NOTIFY. + + @param NotifyType Describes the types of notification which + this function will be receiving. See + EFI_HII_DATABASE_NOTIFY_TYPE for a + list of types. + + @param NotifyHandle Points to the unique handle assigned to + the registered notification. Can be used + in EFI_HII_DATABASE_PROTOCOL.UnregisterPack + to stop notifications. + + + @retval EFI_SUCCESS Notification registered successfully. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate necessary + data structures. + + @retval EFI_INVALID_PARAMETER PackageGuid is not NULL when + PackageType is not + EFI_HII_PACKAGE_TYPE_GUID. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_REGISTER_NOTIFY)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN UINT8 PackageType, + IN CONST EFI_GUID *PackageGuid, + IN EFI_HII_DATABASE_NOTIFY PackageNotifyFn, + IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType, + OUT EFI_HANDLE *NotifyHandle +); + + +/** + + Removes the specified HII database package-related notification. + + @param This A pointer to the EFI_HII_DATABASE_PROTOCOL instance. + + @param NotificationHandle The handle of the notification + function being unregistered. + + @retval EFI_SUCCESS Successsfully unregistered the notification. + + @retval EFI_NOT_FOUND The incoming notification handle does not exist + in the current hii database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_UNREGISTER_NOTIFY)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN EFI_HANDLE NotificationHandle +); + + +/** + + This routine retrieves an array of GUID values for each keyboard + layout that was previously registered in the system. + + @param This A pointer to the EFI_HII_PROTOCOL instance. + + @param KeyGuidBufferLength On input, a pointer to the length + of the keyboard GUID buffer. On + output, the length of the handle + buffer that is required for the + handles found. + + @param KeyGuidBuffer An array of keyboard layout GUID + instances returned. + + @retval EFI_SUCCESS KeyGuidBuffer was updated successfully. + + @retval EFI_BUFFER_TOO_SMALL The KeyGuidBufferLength + parameter indicates that + KeyGuidBuffer is too small to + support the number of GUIDs. + KeyGuidBufferLength is updated + with a value that will enable + the data to fit. + @retval EFI_INVALID_PARAMETER The KeyGuidBufferLength is NULL. + @retval EFI_INVALID_PARAMETER The value referenced by + KeyGuidBufferLength is not + zero and KeyGuidBuffer is NULL. + @retval EFI_NOT_FOUND There was no keyboard layout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_FIND_KEYBOARD_LAYOUTS)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN OUT UINT16 *KeyGuidBufferLength, + OUT EFI_GUID *KeyGuidBuffer +); + + +/** + + This routine retrieves the requested keyboard layout. The layout + is a physical description of the keys on a keyboard, and the + character(s) that are associated with a particular set of key + strokes. + + @param This A pointer to the EFI_HII_PROTOCOL instance. + + @param KeyGuid A pointer to the unique ID associated with a + given keyboard layout. If KeyGuid is NULL then + the current layout will be retrieved. + + @param KeyboardLayoutLength On input, a pointer to the length of the + KeyboardLayout buffer. On output, the length of + the data placed into KeyboardLayout. + + @param KeyboardLayout A pointer to a buffer containing the + retrieved keyboard layout. + + @retval EFI_SUCCESS The keyboard layout was retrieved + successfully. + + @retval EFI_NOT_FOUND The requested keyboard layout was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_KEYBOARD_LAYOUT)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN CONST EFI_GUID *KeyGuid, + IN OUT UINT16 *KeyboardLayoutLength, + OUT EFI_HII_KEYBOARD_LAYOUT *KeyboardLayout +); + +/** + + This routine sets the default keyboard layout to the one + referenced by KeyGuid. When this routine is called, an event + will be signaled of the EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID + group type. This is so that agents which are sensitive to the + current keyboard layout being changed can be notified of this + change. + + @param This A pointer to the EFI_HII_PROTOCOL instance. + + @param KeyGuid A pointer to the unique ID associated with a + given keyboard layout. + + @retval EFI_SUCCESS The current keyboard layout was successfully set. + + @retval EFI_NOT_FOUND The referenced keyboard layout was not + found, so action was taken. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_SET_KEYBOARD_LAYOUT)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN CONST EFI_GUID *KeyGuid +); + +/** + + Return the EFI handle associated with a package list. + + @param This A pointer to the EFI_HII_PROTOCOL instance. + + @param PackageListHandle An EFI_HII_HANDLE that corresponds + to the desired package list in the + HIIdatabase. + + @param DriverHandle On return, contains the EFI_HANDLE which + was registered with the package list in + NewPackageList(). + + @retval EFI_SUCCESS The DriverHandle was returned successfully. + + @retval EFI_INVALID_PARAMETER The PackageListHandle was not valid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DATABASE_GET_PACK_HANDLE)( + IN CONST EFI_HII_DATABASE_PROTOCOL *This, + IN EFI_HII_HANDLE PackageListHandle, + OUT EFI_HANDLE *DriverHandle +); + +/// +/// Database manager for HII-related data structures. +/// +struct _EFI_HII_DATABASE_PROTOCOL { + EFI_HII_DATABASE_NEW_PACK NewPackageList; + EFI_HII_DATABASE_REMOVE_PACK RemovePackageList; + EFI_HII_DATABASE_UPDATE_PACK UpdatePackageList; + EFI_HII_DATABASE_LIST_PACKS ListPackageLists; + EFI_HII_DATABASE_EXPORT_PACKS ExportPackageLists; + EFI_HII_DATABASE_REGISTER_NOTIFY RegisterPackageNotify; + EFI_HII_DATABASE_UNREGISTER_NOTIFY UnregisterPackageNotify; + EFI_HII_FIND_KEYBOARD_LAYOUTS FindKeyboardLayouts; + EFI_HII_GET_KEYBOARD_LAYOUT GetKeyboardLayout; + EFI_HII_SET_KEYBOARD_LAYOUT SetKeyboardLayout; + EFI_HII_DATABASE_GET_PACK_HANDLE GetPackageListHandle; +}; + +extern EFI_GUID gEfiHiiDatabaseProtocolGuid; + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiFont.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiFont.h new file mode 100644 index 0000000000..c229e39442 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiFont.h @@ -0,0 +1,469 @@ +/** @file + The file provides services to retrieve font information. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + +**/ + +#ifndef __HII_FONT_H__ +#define __HII_FONT_H__ + +#include +#include + +#define EFI_HII_FONT_PROTOCOL_GUID \ +{ 0xe9ca4775, 0x8657, 0x47fc, { 0x97, 0xe7, 0x7e, 0xd6, 0x5a, 0x8, 0x43, 0x24 } } + +typedef struct _EFI_HII_FONT_PROTOCOL EFI_HII_FONT_PROTOCOL; + +typedef VOID *EFI_FONT_HANDLE; + +/// +/// EFI_HII_OUT_FLAGS. +/// +typedef UINT32 EFI_HII_OUT_FLAGS; + +#define EFI_HII_OUT_FLAG_CLIP 0x00000001 +#define EFI_HII_OUT_FLAG_WRAP 0x00000002 +#define EFI_HII_OUT_FLAG_CLIP_CLEAN_Y 0x00000004 +#define EFI_HII_OUT_FLAG_CLIP_CLEAN_X 0x00000008 +#define EFI_HII_OUT_FLAG_TRANSPARENT 0x00000010 +#define EFI_HII_IGNORE_IF_NO_GLYPH 0x00000020 +#define EFI_HII_IGNORE_LINE_BREAK 0x00000040 +#define EFI_HII_DIRECT_TO_SCREEN 0x00000080 + +/** + Definition of EFI_HII_ROW_INFO. +**/ +typedef struct _EFI_HII_ROW_INFO { + /// + /// The index of the first character in the string which is displayed on the line. + /// + UINTN StartIndex; + /// + /// The index of the last character in the string which is displayed on the line. + /// If this is the same as StartIndex, then no characters are displayed. + /// + UINTN EndIndex; + UINTN LineHeight; ///< The height of the line, in pixels. + UINTN LineWidth; ///< The width of the text on the line, in pixels. + + /// + /// The font baseline offset in pixels from the bottom of the row, or 0 if none. + /// + UINTN BaselineOffset; +} EFI_HII_ROW_INFO; + +/// +/// Font info flag. All flags (FONT, SIZE, STYLE, and COLOR) are defined. +/// They are defined as EFI_FONT_INFO_*** +/// +typedef UINT32 EFI_FONT_INFO_MASK; + +#define EFI_FONT_INFO_SYS_FONT 0x00000001 +#define EFI_FONT_INFO_SYS_SIZE 0x00000002 +#define EFI_FONT_INFO_SYS_STYLE 0x00000004 +#define EFI_FONT_INFO_SYS_FORE_COLOR 0x00000010 +#define EFI_FONT_INFO_SYS_BACK_COLOR 0x00000020 +#define EFI_FONT_INFO_RESIZE 0x00001000 +#define EFI_FONT_INFO_RESTYLE 0x00002000 +#define EFI_FONT_INFO_ANY_FONT 0x00010000 +#define EFI_FONT_INFO_ANY_SIZE 0x00020000 +#define EFI_FONT_INFO_ANY_STYLE 0x00040000 + +// +// EFI_FONT_INFO +// +typedef struct { + EFI_HII_FONT_STYLE FontStyle; + UINT16 FontSize; ///< character cell height in pixels + CHAR16 FontName[1]; +} EFI_FONT_INFO; + +/** + Describes font output-related information. + + This structure is used for describing the way in which a string + should be rendered in a particular font. FontInfo specifies the + basic font information and ForegroundColor and BackgroundColor + specify the color in which they should be displayed. The flags + in FontInfoMask describe where the system default should be + supplied instead of the specified information. The flags also + describe what options can be used to make a match between the + font requested and the font available. +**/ +typedef struct _EFI_FONT_DISPLAY_INFO { + EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor; + EFI_FONT_INFO_MASK FontInfoMask; + EFI_FONT_INFO FontInfo; +} EFI_FONT_DISPLAY_INFO; + +/** + + This function renders a string to a bitmap or the screen using + the specified font, color and options. It either draws the + string and glyphs on an existing bitmap, allocates a new bitmap, + or uses the screen. The strings can be clipped or wrapped. + Optionally, the function also returns the information about each + row and the character position on that row. If + EFI_HII_OUT_FLAG_CLIP is set, then text will be formatted only + based on explicit line breaks and all pixels which would lie + outside the bounding box specified by Width and Height are + ignored. The information in the RowInfoArray only describes + characters which are at least partially displayed. For the final + row, the LineHeight and BaseLine may describe pixels that are + outside the limit specified by Height (unless + EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is specified) even though those + pixels were not drawn. The LineWidth may describe pixels which + are outside the limit specified by Width (unless + EFI_HII_OUT_FLAG_CLIP_CLEAN_X is specified) even though those + pixels were not drawn. If EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set, + then it modifies the behavior of EFI_HII_OUT_FLAG_CLIP so that + if a character's right-most on pixel cannot fit, then it will + not be drawn at all. This flag requires that + EFI_HII_OUT_FLAG_CLIP be set. If EFI_HII_OUT_FLAG_CLIP_CLEAN_Y + is set, then it modifies the behavior of EFI_HII_OUT_FLAG_CLIP + so that if a row's bottom-most pixel cannot fit, then it will + not be drawn at all. This flag requires that + EFI_HII_OUT_FLAG_CLIP be set. If EFI_HII_OUT_FLAG_WRAP is set, + then text will be wrapped at the right-most line-break + opportunity prior to a character whose right-most extent would + exceed Width. If no line-break opportunity can be found, then + the text will behave as if EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set. + This flag cannot be used with EFI_HII_OUT_FLAG_CLIP_CLEAN_X. If + EFI_HII_OUT_FLAG_TRANSPARENT is set, then BackgroundColor is + ignored and all 'off' pixels in the character's drawn + will use the pixel value from Blt. This flag cannot be used if + Blt is NULL upon entry. If EFI_HII_IGNORE_IF_NO_GLYPH is set, + then characters which have no glyphs are not drawn. Otherwise, + they are replaced with Unicode character code 0xFFFD (REPLACEMENT + CHARACTER). If EFI_HII_IGNORE_LINE_BREAK is set, then explicit + line break characters will be ignored. If + EFI_HII_DIRECT_TO_SCREEN is set, then the string will be written + directly to the output device specified by Screen. Otherwise the + string will be rendered to the bitmap specified by Bitmap. + + @param This A pointer to the EFI_HII_FONT_PROTOCOL instance. + + @param Flags Describes how the string is to be drawn. + + @param String Points to the null-terminated string to be + + @param StringInfo Points to the string output information, + including the color and font. If NULL, then + the string will be output in the default + system font and color. + + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The string will be drawn onto + this image and EFI_HII_OUT_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image and + the pointer updated on exit. It is the caller's + responsibility to free this buffer. + + @param BltX, BltY Specifies the offset from the left and top + edge of the image of the first character + cell in the image. + + @param RowInfoArray If this is non-NULL on entry, then on + exit, this will point to an allocated buffer + containing row information and + RowInfoArraySize will be updated to contain + the number of elements. This array describes + the characters that were at least partially + drawn and the heights of the rows. It is the + caller's responsibility to free this buffer. + + @param RowInfoArraySize If this is non-NULL on entry, then on + exit it contains the number of + elements in RowInfoArray. + + @param ColumnInfoArray If this is non-NULL, then on return it + will be filled with the horizontal + offset for each character in the + string on the row where it is + displayed. Non-printing characters + will have the offset ~0. The caller is + responsible for allocating a buffer large + enough so that there is one entry for + each character in the string, not + including the null-terminator. It is + possible when character display is + normalized that some character cells + overlap. + + @retval EFI_SUCCESS The string was successfully updated. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for RowInfoArray or Blt. + + @retval EFI_INVALID_PARAMETER The String or Blt was NULL. + + @retval EFI_INVALID_PARAMETER Flags were invalid combination. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_STRING_TO_IMAGE)( + IN CONST EFI_HII_FONT_PROTOCOL *This, + IN EFI_HII_OUT_FLAGS Flags, + IN CONST EFI_STRING String, + IN CONST EFI_FONT_DISPLAY_INFO *StringInfo, + IN OUT EFI_IMAGE_OUTPUT **Blt, + IN UINTN BltX, + IN UINTN BltY, + OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL, + OUT UINTN *RowInfoArraySize OPTIONAL, + OUT UINTN *ColumnInfoArray OPTIONAL +); + + + +/** + + This function renders a string as a bitmap or to the screen + and can clip or wrap the string. The bitmap is either supplied + by the caller or allocated by the function. The + strings are drawn with the font, size and style specified and + can be drawn transparently or opaquely. The function can also + return information about each row and each character's + position on the row. If EFI_HII_OUT_FLAG_CLIP is set, then + text will be formatted based only on explicit line breaks, and + all pixels that would lie outside the bounding box specified + by Width and Height are ignored. The information in the + RowInfoArray only describes characters which are at least + partially displayed. For the final row, the LineHeight and + BaseLine may describe pixels which are outside the limit + specified by Height (unless EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is + specified) even though those pixels were not drawn. If + EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set, then it modifies the + behavior of EFI_HII_OUT_FLAG_CLIP so that if a character's + right-most on pixel cannot fit, then it will not be drawn at + all. This flag requires that EFI_HII_OUT_FLAG_CLIP be set. If + EFI_HII_OUT_FLAG_CLIP_CLEAN_Y is set, then it modifies the + behavior of EFI_HII_OUT_FLAG_CLIP so that if a row's bottom + most pixel cannot fit, then it will not be drawn at all. This + flag requires that EFI_HII_OUT_FLAG_CLIP be set. If + EFI_HII_OUT_FLAG_WRAP is set, then text will be wrapped at the + right-most line-break opportunity prior to a character whose + right-most extent would exceed Width. If no line-break + opportunity can be found, then the text will behave as if + EFI_HII_OUT_FLAG_CLIP_CLEAN_X is set. This flag cannot be used + with EFI_HII_OUT_FLAG_CLIP_CLEAN_X. If + EFI_HII_OUT_FLAG_TRANSPARENT is set, then BackgroundColor is + ignored and all off" pixels in the character's glyph will + use the pixel value from Blt. This flag cannot be used if Blt + is NULL upon entry. If EFI_HII_IGNORE_IF_NO_GLYPH is set, then + characters which have no glyphs are not drawn. Otherwise, they + are replaced with Unicode character code 0xFFFD (REPLACEMENT + CHARACTER). If EFI_HII_IGNORE_LINE_BREAK is set, then explicit + line break characters will be ignored. If + EFI_HII_DIRECT_TO_SCREEN is set, then the string will be + written directly to the output device specified by Screen. + Otherwise the string will be rendered to the bitmap specified + by Bitmap. + + + @param This A pointer to the EFI_HII_FONT_PROTOCOL instance. + + @param Flags Describes how the string is to be drawn. + + @param PackageList + The package list in the HII database to + search for the specified string. + + @param StringId The string's id, which is unique within + PackageList. + + @param Language Points to the language for the retrieved + string. If NULL, then the current system + language is used. + + @param StringInfo Points to the string output information, + including the color and font. If NULL, then + the string will be output in the default + system font and color. + + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The string will be drawn onto + this image and EFI_HII_OUT_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image and + the pointer updated on exit. It is the caller's + responsibility to free this buffer. + + @param BltX, BltY Specifies the offset from the left and top + edge of the output image of the first + character cell in the image. + + @param RowInfoArray If this is non-NULL on entry, then on + exit, this will point to an allocated + buffer containing row information and + RowInfoArraySize will be updated to + contain the number of elements. This array + describes the characters which were at + least partially drawn and the heights of + the rows. It is the caller's + responsibility to free this buffer. + + @param RowInfoArraySize If this is non-NULL on entry, then on + exit it contains the number of + elements in RowInfoArray. + + @param ColumnInfoArray If non-NULL, on return it is filled + with the horizontal offset for each + character in the string on the row + where it is displayed. Non-printing + characters will have the offset ~0. + The caller is responsible to allocate + a buffer large enough so that there is + one entry for each character in the + string, not including the + null-terminator. It is possible when + character display is normalized that + some character cells overlap. + + + @retval EFI_SUCCESS The string was successfully updated. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output + buffer for RowInfoArray or Blt. + + @retval EFI_INVALID_PARAMETER The String, or Blt, or Height, or + Width was NULL. + @retval EFI_INVALID_PARAMETER The Blt or PackageList was NULL. + @retval EFI_INVALID_PARAMETER Flags were invalid combination. + @retval EFI_NOT_FOUND The specified PackageList is not in the Database, + or the stringid is not in the specified PackageList. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_STRING_ID_TO_IMAGE)( + IN CONST EFI_HII_FONT_PROTOCOL *This, + IN EFI_HII_OUT_FLAGS Flags, + IN EFI_HII_HANDLE PackageList, + IN EFI_STRING_ID StringId, + IN CONST CHAR8 *Language, + IN CONST EFI_FONT_DISPLAY_INFO *StringInfo OPTIONAL, + IN OUT EFI_IMAGE_OUTPUT **Blt, + IN UINTN BltX, + IN UINTN BltY, + OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL, + OUT UINTN *RowInfoArraySize OPTIONAL, + OUT UINTN *ColumnInfoArray OPTIONAL +); + + +/** + + Convert the glyph for a single character into a bitmap. + + @param This A pointer to the EFI_HII_FONT_PROTOCOL instance. + + @param Char The character to retrieve. + + @param StringInfo Points to the string font and color + information or NULL if the string should use + the default system font and color. + + @param Blt This must point to a NULL on entry. A buffer will + be allocated to hold the output and the pointer + updated on exit. It is the caller's responsibility + to free this buffer. + + @param Baseline The number of pixels from the bottom of the bitmap + to the baseline. + + + @retval EFI_SUCCESS The glyph bitmap created. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate the output buffer Blt. + + @retval EFI_WARN_UNKNOWN_GLYPH The glyph was unknown and was + replaced with the glyph for + Unicode character code 0xFFFD. + + @retval EFI_INVALID_PARAMETER Blt is NULL, or Width is NULL, or + Height is NULL + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_GLYPH)( + IN CONST EFI_HII_FONT_PROTOCOL *This, + IN CONST CHAR16 Char, + IN CONST EFI_FONT_DISPLAY_INFO *StringInfo, + OUT EFI_IMAGE_OUTPUT **Blt, + OUT UINTN *Baseline OPTIONAL +); + +/** + + This function iterates through fonts which match the specified + font, using the specified criteria. If String is non-NULL, then + all of the characters in the string must exist in order for a + candidate font to be returned. + + @param This A pointer to the EFI_HII_FONT_PROTOCOL instance. + + @param FontHandle On entry, points to the font handle returned + by a previous call to GetFontInfo() or NULL + to start with the first font. On return, + points to the returned font handle or points + to NULL if there are no more matching fonts. + + @param StringInfoIn Upon entry, points to the font to return + information about. If NULL, then the information + about the system default font will be returned. + + @param StringInfoOut Upon return, contains the matching font's information. + If NULL, then no information is returned. This buffer + is allocated with a call to the Boot Service AllocatePool(). + It is the caller's responsibility to call the Boot + Service FreePool() when the caller no longer requires + the contents of StringInfoOut. + + @param String Points to the string which will be tested to + determine if all characters are available. If + NULL, then any font is acceptable. + + @retval EFI_SUCCESS Matching font returned successfully. + + @retval EFI_NOT_FOUND No matching font was found. + + @retval EFI_OUT_OF_RESOURCES There were insufficient resources to complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_FONT_INFO)( + IN CONST EFI_HII_FONT_PROTOCOL *This, + IN OUT EFI_FONT_HANDLE *FontHandle, + IN CONST EFI_FONT_DISPLAY_INFO *StringInfoIn, OPTIONAL + OUT EFI_FONT_DISPLAY_INFO **StringInfoOut, + IN CONST EFI_STRING String OPTIONAL +); + +/// +/// The protocol provides the service to retrieve the font informations. +/// +struct _EFI_HII_FONT_PROTOCOL { + EFI_HII_STRING_TO_IMAGE StringToImage; + EFI_HII_STRING_ID_TO_IMAGE StringIdToImage; + EFI_HII_GET_GLYPH GetGlyph; + EFI_HII_GET_FONT_INFO GetFontInfo; +}; + +extern EFI_GUID gEfiHiiFontProtocolGuid; + + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImage.h new file mode 100644 index 0000000000..ef4559988e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImage.h @@ -0,0 +1,353 @@ +/** @file + The file provides services to access to images in the images database. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + +**/ + +#ifndef __HII_IMAGE_H__ +#define __HII_IMAGE_H__ + +#include + +#define EFI_HII_IMAGE_PROTOCOL_GUID \ + { 0x31a6406a, 0x6bdf, 0x4e46, { 0xb2, 0xa2, 0xeb, 0xaa, 0x89, 0xc4, 0x9, 0x20 } } + +typedef struct _EFI_HII_IMAGE_PROTOCOL EFI_HII_IMAGE_PROTOCOL; + + +/// +/// Flags in EFI_IMAGE_INPUT +/// +#define EFI_IMAGE_TRANSPARENT 0x00000001 + +/** + + Definition of EFI_IMAGE_INPUT. + + @param Flags Describe image characteristics. If + EFI_IMAGE_TRANSPARENT is set, then the image was + designed for transparent display. + + @param Width Image width, in pixels. + + @param Height Image height, in pixels. + + @param Bitmap A pointer to the actual bitmap, organized left-to-right, + top-to-bottom. The size of the bitmap is + Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL). + + +**/ +typedef struct _EFI_IMAGE_INPUT { + UINT32 Flags; + UINT16 Width; + UINT16 Height; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap; +} EFI_IMAGE_INPUT; + + +/** + + This function adds the image Image to the group of images + owned by PackageList, and returns a new image identifier + (ImageId). + + @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance. + + @param PackageList Handle of the package list where this image will be added. + + @param ImageId On return, contains the new image id, which is + unique within PackageList. + + @param Image Points to the image. + + @retval EFI_SUCCESS The new image was added + successfully + + @retval EFI_OUT_OF_RESOURCES Could not add the image. + + @retval EFI_INVALID_PARAMETER Image is NULL or ImageId is + NULL. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_NEW_IMAGE)( + IN CONST EFI_HII_IMAGE_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + OUT EFI_IMAGE_ID *ImageId, + IN CONST EFI_IMAGE_INPUT *Image +); + +/** + + This function retrieves the image specified by ImageId which + is associated with the specified PackageList and copies it + into the buffer specified by Image. If the image specified by + ImageId is not present in the specified PackageList, then + EFI_NOT_FOUND is returned. If the buffer specified by + ImageSize is too small to hold the image, then + EFI_BUFFER_TOO_SMALL will be returned. ImageSize will be + updated to the size of buffer actually required to hold the + image. + + @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance. + + @param PackageList The package list in the HII database to + search for the specified image. + + @param ImageId The image's id, which is unique within + PackageList. + + @param Image Points to the new image. + + @retval EFI_SUCCESS The image was returned successfully. + + @retval EFI_NOT_FOUND The image specified by ImageId is not + available. Or The specified PackageList is not in the database. + + @retval EFI_INVALID_PARAMETER The Image or Langugae was NULL. + @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there was not + enough memory. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_IMAGE)( + IN CONST EFI_HII_IMAGE_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + OUT EFI_IMAGE_INPUT *Image +); + +/** + + This function updates the image specified by ImageId in the + specified PackageListHandle to the image specified by Image. + + + @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance. + + @param PackageList The package list containing the images. + + @param ImageId The image id, which is unique within PackageList. + + @param Image Points to the image. + + @retval EFI_SUCCESS The image was successfully updated. + + @retval EFI_NOT_FOUND The image specified by ImageId is not in the database. + The specified PackageList is not in the database. + + @retval EFI_INVALID_PARAMETER The Image or Language was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_SET_IMAGE)( + IN CONST EFI_HII_IMAGE_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + IN CONST EFI_IMAGE_INPUT *Image +); + + +/// +/// EFI_HII_DRAW_FLAGS describes how the image is to be drawn. +/// These flags are defined as EFI_HII_DRAW_FLAG_*** +/// +typedef UINT32 EFI_HII_DRAW_FLAGS; + +#define EFI_HII_DRAW_FLAG_CLIP 0x00000001 +#define EFI_HII_DRAW_FLAG_TRANSPARENT 0x00000030 +#define EFI_HII_DRAW_FLAG_DEFAULT 0x00000000 +#define EFI_HII_DRAW_FLAG_FORCE_TRANS 0x00000010 +#define EFI_HII_DRAW_FLAG_FORCE_OPAQUE 0x00000020 +#define EFI_HII_DIRECT_TO_SCREEN 0x00000080 + +/** + + Definition of EFI_IMAGE_OUTPUT. + + @param Width Width of the output image. + + @param Height Height of the output image. + + @param Bitmap Points to the output bitmap. + + @param Screen Points to the EFI_GRAPHICS_OUTPUT_PROTOCOL which + describes the screen on which to draw the + specified image. + +**/ +typedef struct _EFI_IMAGE_OUTPUT { + UINT16 Width; + UINT16 Height; + union { + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap; + EFI_GRAPHICS_OUTPUT_PROTOCOL *Screen; + } Image; +} EFI_IMAGE_OUTPUT; + + +/** + + This function renders an image to a bitmap or the screen using + the specified color and options. It draws the image on an + existing bitmap, allocates a new bitmap or uses the screen. The + images can be clipped. If EFI_HII_DRAW_FLAG_CLIP is set, then + all pixels drawn outside the bounding box specified by Width and + Height are ignored. If EFI_HII_DRAW_FLAG_TRANSPARENT is set, + then all 'off' pixels in the images drawn will use the + pixel value from Blt. This flag cannot be used if Blt is NULL + upon entry. If EFI_HII_DIRECT_TO_SCREEN is set, then the image + will be written directly to the output device specified by + Screen. Otherwise the image will be rendered to the bitmap + specified by Bitmap. + + + @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance. + + @param Flags Describes how the image is to be drawn. + EFI_HII_DRAW_FLAGS is defined in Related + Definitions, below. + + @param Image Points to the image to be displayed. + + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The image will be drawn onto + this image and EFI_HII_DRAW_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image and + the pointer updated on exit. It is the caller's + responsibility to free this buffer. + + @param BltX, BltY Specifies the offset from the left and top + edge of the image of the first pixel in + the image. + + @retval EFI_SUCCESS The image was successfully updated. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output + buffer for RowInfoArray or Blt. + + @retval EFI_INVALID_PARAMETER The Image or Blt or Height or + Width was NULL. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DRAW_IMAGE)( + IN CONST EFI_HII_IMAGE_PROTOCOL *This, + IN EFI_HII_DRAW_FLAGS Flags, + IN CONST EFI_IMAGE_INPUT *Image, + IN OUT EFI_IMAGE_OUTPUT **Blt, + IN UINTN BltX, + IN UINTN BltY +); + +/** + + This function renders an image as a bitmap or to the screen and + can clip the image. The bitmap is either supplied by the caller + or else is allocated by the function. The images can be drawn + transparently or opaquely. If EFI_HII_DRAW_FLAG_CLIP is set, + then all pixels drawn outside the bounding box specified by + Width and Height are ignored. If EFI_HII_DRAW_FLAG_TRANSPARENT + is set, then all "off" pixels in the character's glyph will + use the pixel value from Blt. This flag cannot be used if Blt + is NULL upon entry. If EFI_HII_DIRECT_TO_SCREEN is set, then + the image will be written directly to the output device + specified by Screen. Otherwise the image will be rendered to + the bitmap specified by Bitmap. + This function renders an image to a bitmap or the screen using + the specified color and options. It draws the image on an + existing bitmap, allocates a new bitmap or uses the screen. The + images can be clipped. If EFI_HII_DRAW_FLAG_CLIP is set, then + all pixels drawn outside the bounding box specified by Width and + Height are ignored. The EFI_HII_DRAW_FLAG_TRANSPARENT flag + determines whether the image will be drawn transparent or + opaque. If EFI_HII_DRAW_FLAG_FORCE_TRANS is set, then the image + will be drawn so that all 'off' pixels in the image will + be drawn using the pixel value from Blt and all other pixels + will be copied. If EFI_HII_DRAW_FLAG_FORCE_OPAQUE is set, then + the image's pixels will be copied directly to the + destination. If EFI_HII_DRAW_FLAG_DEFAULT is set, then the image + will be drawn transparently or opaque, depending on the + image's transparency setting (see EFI_IMAGE_TRANSPARENT). + Images cannot be drawn transparently if Blt is NULL. If + EFI_HII_DIRECT_TO_SCREEN is set, then the image will be written + directly to the output device specified by Screen. Otherwise the + image will be rendered to the bitmap specified by Bitmap. + + @param This A pointer to the EFI_HII_IMAGE_PROTOCOL instance. + + @param Flags Describes how the image is to be drawn. + + @param PackageList The package list in the HII database to + search for the specified image. + + @param ImageId The image's id, which is unique within PackageList. + + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The image will be drawn onto + this image and EFI_HII_DRAW_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image and + the pointer updated on exit. It is the caller's + responsibility to free this buffer. + + @param BltX, BltY Specifies the offset from the left and top + edge of the output image of the first + pixel in the image. + + @retval EFI_SUCCESS The image was successfully updated. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output + buffer for RowInfoArray or Blt. + + @retval EFI_NOT_FOUND The image specified by ImageId is not in the database. + Or The specified PackageList is not in the database. + + @retval EFI_INVALID_PARAMETER The Blt was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DRAW_IMAGE_ID)( +IN CONST EFI_HII_IMAGE_PROTOCOL *This, +IN EFI_HII_DRAW_FLAGS Flags, +IN EFI_HII_HANDLE PackageList, +IN EFI_IMAGE_ID ImageId, +IN OUT EFI_IMAGE_OUTPUT **Blt, +IN UINTN BltX, +IN UINTN BltY +); + + +/// +/// Services to access to images in the images database. +/// +struct _EFI_HII_IMAGE_PROTOCOL { + EFI_HII_NEW_IMAGE NewImage; + EFI_HII_GET_IMAGE GetImage; + EFI_HII_SET_IMAGE SetImage; + EFI_HII_DRAW_IMAGE DrawImage; + EFI_HII_DRAW_IMAGE_ID DrawImageId; +}; + +extern EFI_GUID gEfiHiiImageProtocolGuid; + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageDecoder.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageDecoder.h new file mode 100644 index 0000000000..965c59a9e0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageDecoder.h @@ -0,0 +1,200 @@ +/** @file + This protocol provides generic image decoder interfaces to various image formats. + +(C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ Copyright (c) 2016-2018, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.6. + +**/ +#ifndef __HII_IMAGE_DECODER_H__ +#define __HII_IMAGE_DECODER_H__ + +#include + +#define EFI_HII_IMAGE_DECODER_PROTOCOL_GUID \ + {0x9e66f251, 0x727c, 0x418c, { 0xbf, 0xd6, 0xc2, 0xb4, 0x25, 0x28, 0x18, 0xea }} + + +#define EFI_HII_IMAGE_DECODER_NAME_JPEG_GUID \ + {0xefefd093, 0xd9b, 0x46eb, { 0xa8, 0x56, 0x48, 0x35, 0x7, 0x0, 0xc9, 0x8 }} + +#define EFI_HII_IMAGE_DECODER_NAME_PNG_GUID \ + {0xaf060190, 0x5e3a, 0x4025, { 0xaf, 0xbd, 0xe1, 0xf9, 0x5, 0xbf, 0xaa, 0x4c }} + +typedef struct _EFI_HII_IMAGE_DECODER_PROTOCOL EFI_HII_IMAGE_DECODER_PROTOCOL; + +typedef enum { + EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGB = 0x0, + EFI_HII_IMAGE_DECODER_COLOR_TYPE_RGBA = 0x1, + EFI_HII_IMAGE_DECODER_COLOR_TYPE_CMYK = 0x2, + EFI_HII_IMAGE_DECODER_COLOR_TYPE_UNKNOWN = 0xFF +} EFI_HII_IMAGE_DECODER_COLOR_TYPE; + +// +// EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER +// +// DecoderName Name of the decoder +// ImageInfoSize The size of entire image information structure in bytes +// ImageWidth The image width +// ImageHeight The image height +// ColorType The color type, see EFI_HII_IMAGE_DECODER_COLOR_TYPE. +// ColorDepthInBits The color depth in bits +// +typedef struct _EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER { + EFI_GUID DecoderName; + UINT16 ImageInfoSize; + UINT16 ImageWidth; + UINT16 ImageHeight; + EFI_HII_IMAGE_DECODER_COLOR_TYPE ColorType; + UINT8 ColorDepthInBits; +} EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER; + +#define EFI_IMAGE_JPEG_SCANTYPE_PROGREESSIVE 0x01 +#define EFI_IMAGE_JPEG_SCANTYPE_INTERLACED 0x02 + +// +// EFI_HII_IMAGE_DECODER_JPEG_INFO +// Header The common header +// ScanType The scan type of JPEG image +// Reserved Reserved +// +typedef struct _EFI_HII_IMAGE_DECODER_JPEG_INFO { + EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header; + UINT16 ScanType; + UINT64 Reserved; +} EFI_HII_IMAGE_DECODER_JPEG_INFO; + +// +// EFI_HII_IMAGE_DECODER_PNG_INFO +// Header The common header +// Channels Number of channels in the PNG image +// Reserved Reserved +// +typedef struct _EFI_HII_IMAGE_DECODER_PNG_INFO { + EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header; + UINT16 Channels; + UINT64 Reserved; +} EFI_HII_IMAGE_DECODER_PNG_INFO; + +// +// EFI_HII_IMAGE_DECODER_OTHER_INFO +// +typedef struct _EFI_HII_IMAGE_DECODER_OTHER_INFO { + EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header; + CHAR16 ImageExtenion[1]; + // + // Variable length of image file extension name. + // +} EFI_HII_IMAGE_DECODER_OTHER_INFO; + +/** + There could be more than one EFI_HII_IMAGE_DECODER_PROTOCOL instances installed + in the system for different image formats. This function returns the decoder + name which callers can use to find the proper image decoder for the image. It + is possible to support multiple image formats in one EFI_HII_IMAGE_DECODER_PROTOCOL. + The capability of the supported image formats is returned in DecoderName and + NumberOfDecoderName. + + @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance. + @param DecoderName Pointer to a dimension to retrieve the decoder + names in EFI_GUID format. The number of the + decoder names is returned in NumberOfDecoderName. + @param NumberofDecoderName Pointer to retrieve the number of decoders which + supported by this decoder driver. + + @retval EFI_SUCCESS Get decoder name success. + @retval EFI_UNSUPPORTED Get decoder name fail. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_IMAGE_DECODER_GET_NAME)( + IN EFI_HII_IMAGE_DECODER_PROTOCOL *This, + IN OUT EFI_GUID **DecoderName, + IN OUT UINT16 *NumberOfDecoderName + ); + +/** + This function returns the image information of the given image raw data. This + function first checks whether the image raw data is supported by this decoder + or not. This function may go through the first few bytes in the image raw data + for the specific data structure or the image signature. If the image is not supported + by this image decoder, this function returns EFI_UNSUPPORTED to the caller. + Otherwise, this function returns the proper image information to the caller. + It is the caller?s responsibility to free the ImageInfo. + + @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance. + @param Image Pointer to the image raw data. + @param SizeOfImage Size of the entire image raw data. + @param ImageInfo Pointer to receive EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER. + + @retval EFI_SUCCESS Get image info success. + @retval EFI_UNSUPPORTED Unsupported format of image. + @retval EFI_INVALID_PARAMETER Incorrect parameter. + @retval EFI_BAD_BUFFER_SIZE Not enough memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO)( + IN EFI_HII_IMAGE_DECODER_PROTOCOL *This, + IN VOID *Image, + IN UINTN SizeOfImage, + IN OUT EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER **ImageInfo + ); + +/** + This function decodes the image which the image type of this image is supported + by this EFI_HII_IMAGE_DECODER_PROTOCOL. If **Bitmap is not NULL, the caller intends + to put the image in the given image buffer. That allows the caller to put an + image overlap on the original image. The transparency is handled by the image + decoder because the transparency capability depends on the image format. Callers + can set Transparent to FALSE to force disabling the transparency process on the + image. Forcing Transparent to FALSE may also improve the performance of the image + decoding because the image decoder can skip the transparency processing. If **Bitmap + is NULL, the image decoder allocates the memory buffer for the EFI_IMAGE_OUTPUT + and decodes the image to the image buffer. It is the caller?s responsibility to + free the memory for EFI_IMAGE_OUTPUT. Image decoder doesn?t have to handle the + transparency in this case because there is no background image given by the caller. + The background color in this case is all black (#00000000). + + @param This EFI_HII_IMAGE_DECODER_PROTOCOL instance. + @param Image Pointer to the image raw data. + @param ImageRawDataSize Size of the entire image raw data. + @param Blt EFI_IMAGE_OUTPUT to receive the image or overlap + the image on the original buffer. + @param Transparent BOOLEAN value indicates whether the image decoder + has to handle the transparent image or not. + + + @retval EFI_SUCCESS Image decode success. + @retval EFI_UNSUPPORTED Unsupported format of image. + @retval EFI_INVALID_PARAMETER Incorrect parameter. + @retval EFI_BAD_BUFFER_SIZE Not enough memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_IMAGE_DECODER_DECODE)( + IN EFI_HII_IMAGE_DECODER_PROTOCOL *This, + IN VOID *Image, + IN UINTN ImageRawDataSize, + IN OUT EFI_IMAGE_OUTPUT **Bitmap, + IN BOOLEAN Transparent + ); + +struct _EFI_HII_IMAGE_DECODER_PROTOCOL { + EFI_HII_IMAGE_DECODER_GET_NAME GetImageDecoderName; + EFI_HII_IMAGE_DECODER_GET_IMAGE_INFO GetImageInfo; + EFI_HII_IMAGE_DECODER_DECODE DecodeImage; +}; + +extern EFI_GUID gEfiHiiImageDecoderProtocolGuid; +extern EFI_GUID gEfiHiiImageDecoderNameJpegGuid; +extern EFI_GUID gEfiHiiImageDecoderNamePngGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageEx.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageEx.h new file mode 100644 index 0000000000..c0402b7bbb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiImageEx.h @@ -0,0 +1,248 @@ +/** @file + Protocol which allows access to the images in the images database. + +(C) Copyright 2016-2018 Hewlett Packard Enterprise Development LP
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.6. + +**/ + +#ifndef __EFI_HII_IMAGE_EX_H__ +#define __EFI_HII_IMAGE_EX_H__ + +#include + +// +// Global ID for the Hii Image Ex Protocol. +// +#define EFI_HII_IMAGE_EX_PROTOCOL_GUID \ + {0x1a1241e6, 0x8f19, 0x41a9, { 0xbc, 0xe, 0xe8, 0xef, 0x39, 0xe0, 0x65, 0x46 }} + +typedef struct _EFI_HII_IMAGE_EX_PROTOCOL EFI_HII_IMAGE_EX_PROTOCOL; + +/** + The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.NewImage(). + This protocol invokes EFI_HII_IMAGE_PROTOCOL.NewImage() implicitly. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param PackageList Handle of the package list where this image will + be added. + @param ImageId On return, contains the new image id, which is + unique within PackageList. + @param Image Points to the image. + + @retval EFI_SUCCESS The new image was added successfully. + @retval EFI_NOT_FOUND The specified PackageList could not be found in + database. + @retval EFI_OUT_OF_RESOURCES Could not add the image due to lack of resources. + @retval EFI_INVALID_PARAMETER Image is NULL or ImageId is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_NEW_IMAGE_EX)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + OUT EFI_IMAGE_ID *ImageId, + IN CONST EFI_IMAGE_INPUT *Image + ); + +/** + Return the information about the image, associated with the package list. + The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.GetImage(). + + This function is similar to EFI_HII_IMAGE_PROTOCOL.GetImage().The difference is that + this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the + system if the decoder of the certain image type is not supported by the + EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the + EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that + supports the requested image type. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param PackageList The package list in the HII database to search for the + specified image. + @param ImageId The image's id, which is unique within PackageList. + @param Image Points to the image. + + @retval EFI_SUCCESS The new image was returned successfully. + @retval EFI_NOT_FOUND The image specified by ImageId is not available. The specified + PackageList is not in the Database. + @retval EFI_INVALID_PARAMETER Image was NULL or ImageId was 0. + @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there + was not enough memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_IMAGE_EX)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + OUT EFI_IMAGE_INPUT *Image + ); + +/** + Change the information about the image. + + Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes + EFI_HII_IMAGE_PROTOCOL.SetImage()implicitly. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param PackageList The package list containing the images. + @param ImageId The image's id, which is unique within PackageList. + @param Image Points to the image. + + @retval EFI_SUCCESS The new image was successfully updated. + @retval EFI_NOT_FOUND The image specified by ImageId is not in the + database. The specified PackageList is not in + the database. + @retval EFI_INVALID_PARAMETER The Image was NULL, the ImageId was 0 or + the Image->Bitmap was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_SET_IMAGE_EX)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + IN CONST EFI_IMAGE_INPUT *Image + ); + +/** + Renders an image to a bitmap or to the display. + + The prototype of this extension function is the same with + EFI_HII_IMAGE_PROTOCOL.DrawImage(). This protocol invokes + EFI_HII_IMAGE_PROTOCOL.DrawImage() implicitly. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param Flags Describes how the image is to be drawn. + @param Image Points to the image to be displayed. + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The image will be drawn onto + this image and EFI_HII_DRAW_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image and + the pointer updated on exit. It is the caller's + responsibility to free this buffer. + @param BltX Specifies the offset from the left and top edge of + the output image of the first pixel in the image. + @param BltY Specifies the offset from the left and top edge of + the output image of the first pixel in the image. + + @retval EFI_SUCCESS The image was successfully drawn. + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for Blt. + @retval EFI_INVALID_PARAMETER The Image or Blt was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DRAW_IMAGE_EX)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_DRAW_FLAGS Flags, + IN CONST EFI_IMAGE_INPUT *Image, + IN OUT EFI_IMAGE_OUTPUT **Blt, + IN UINTN BltX, + IN UINTN BltY + ); + +/** + Renders an image to a bitmap or the screen containing the contents of the specified + image. + + This function is similar to EFI_HII_IMAGE_PROTOCOL.DrawImageId(). The difference is that + this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the + system if the decoder of the certain image type is not supported by the + EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the + EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that + supports the requested image type. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param Flags Describes how the image is to be drawn. + @param PackageList The package list in the HII database to search for + the specified image. + @param ImageId The image's id, which is unique within PackageList. + @param Blt If this points to a non-NULL on entry, this points + to the image, which is Width pixels wide and + Height pixels high. The image will be drawn onto + this image and EFI_HII_DRAW_FLAG_CLIP is implied. + If this points to a NULL on entry, then a buffer + will be allocated to hold the generated image + and the pointer updated on exit. It is the caller's + responsibility to free this buffer. + @param BltX Specifies the offset from the left and top edge of + the output image of the first pixel in the image. + @param BltY Specifies the offset from the left and top edge of + the output image of the first pixel in the image. + + @retval EFI_SUCCESS The image was successfully drawn. + @retval EFI_OUT_OF_RESOURCES Unable to allocate an output buffer for Blt. + @retval EFI_INVALID_PARAMETER The Blt was NULL or ImageId was 0. + @retval EFI_NOT_FOUND The image specified by ImageId is not in the database. + The specified PackageList is not in the database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_DRAW_IMAGE_ID_EX)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_DRAW_FLAGS Flags, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + IN OUT EFI_IMAGE_OUTPUT **Blt, + IN UINTN BltX, + IN UINTN BltY + ); + +/** + This function returns the image information to EFI_IMAGE_OUTPUT. Only the width + and height are returned to the EFI_IMAGE_OUTPUT instead of decoding the image + to the buffer. This function is used to get the geometry of the image. This function + will try to locate all of the EFI_HII_IMAGE_DECODER_PROTOCOL installed on the + system if the decoder of image type is not supported by the EFI_HII_IMAGE_EX_PROTOCOL. + + @param This A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance. + @param PackageList Handle of the package list where this image will + be searched. + @param ImageId The image's id, which is unique within PackageList. + @param Image Points to the image. + + @retval EFI_SUCCESS The new image was returned successfully. + @retval EFI_NOT_FOUND The image specified by ImageId is not in the + database. The specified PackageList is not in the database. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too small to + hold the image. + @retval EFI_INVALID_PARAMETER The Image was NULL or the ImageId was 0. + @retval EFI_OUT_OF_RESOURCES The bitmap could not be retrieved because there + was not enough memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_IMAGE_INFO)( + IN CONST EFI_HII_IMAGE_EX_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_IMAGE_ID ImageId, + OUT EFI_IMAGE_OUTPUT *Image + ); + +/// +/// Protocol which allows access to the images in the images database. +/// +struct _EFI_HII_IMAGE_EX_PROTOCOL { + EFI_HII_NEW_IMAGE_EX NewImageEx; + EFI_HII_GET_IMAGE_EX GetImageEx; + EFI_HII_SET_IMAGE_EX SetImageEx; + EFI_HII_DRAW_IMAGE_EX DrawImageEx; + EFI_HII_DRAW_IMAGE_ID_EX DrawImageIdEx; + EFI_HII_GET_IMAGE_INFO GetImageInfo; +}; + +extern EFI_GUID gEfiHiiImageExProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPackageList.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPackageList.h new file mode 100644 index 0000000000..a161edfa59 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPackageList.h @@ -0,0 +1,27 @@ +/** @file + EFI_HII_PACKAGE_LIST_PROTOCOL as defined in UEFI 2.1. + Boot service LoadImage() installs EFI_HII_PACKAGE_LIST_PROTOCOL on the handle + if the image contains a custom PE/COFF resource with the type 'HII'. + The protocol's interface pointer points to the HII package list, which is + contained in the resource's data. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __HII_PACKAGE_LIST_H__ +#define __HII_PACKAGE_LIST_H__ + +#define EFI_HII_PACKAGE_LIST_PROTOCOL_GUID \ + { 0x6a1ee763, 0xd47a, 0x43b4, {0xaa, 0xbe, 0xef, 0x1d, 0xe2, 0xab, 0x56, 0xfc}} + +typedef EFI_HII_PACKAGE_LIST_HEADER * EFI_HII_PACKAGE_LIST_PROTOCOL; + +extern EFI_GUID gEfiHiiPackageListProtocolGuid; + + + +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPopup.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPopup.h new file mode 100644 index 0000000000..a0e17b63a0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiPopup.h @@ -0,0 +1,78 @@ +/** @file + This protocol provides services to display a popup window. + The protocol is typically produced by the forms browser and consumed by a driver callback handler. + + Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.7. + +**/ + +#ifndef __HII_POPUP_H__ +#define __HII_POPUP_H__ + +#define EFI_HII_POPUP_PROTOCOL_GUID \ + {0x4311edc0, 0x6054, 0x46d4, {0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc}} + +#define EFI_HII_POPUP_PROTOCOL_REVISION 1 + +typedef struct _EFI_HII_POPUP_PROTOCOL EFI_HII_POPUP_PROTOCOL; + +typedef enum { + EfiHiiPopupStyleInfo, + EfiHiiPopupStyleWarning, + EfiHiiPopupStyleError +} EFI_HII_POPUP_STYLE; + +typedef enum { + EfiHiiPopupTypeOk, + EfiHiiPopupTypeOkCancel, + EfiHiiPopupTypeYesNo, + EfiHiiPopupTypeYesNoCancel +} EFI_HII_POPUP_TYPE; + +typedef enum { + EfiHiiPopupSelectionOk, + EfiHiiPopupSelectionCancel, + EfiHiiPopupSelectionYes, + EfiHiiPopupSelectionNo +} EFI_HII_POPUP_SELECTION; + +/** + Displays a popup window. + + @param This A pointer to the EFI_HII_POPUP_PROTOCOL instance. + @param PopupStyle Popup style to use. + @param PopupType Type of the popup to display. + @param HiiHandle HII handle of the string pack containing Message + @param Message A message to display in the popup box. + @param UserSelection User selection. + + @retval EFI_SUCCESS The popup box was successfully displayed. + @retval EFI_INVALID_PARAMETER HiiHandle and Message do not define a valid HII string. + @retval EFI_INVALID_PARAMETER PopupType is not one of the values defined by this specification. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to display the popup box. + +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HII_CREATE_POPUP) ( + IN EFI_HII_POPUP_PROTOCOL *This, + IN EFI_HII_POPUP_STYLE PopupStyle, + IN EFI_HII_POPUP_TYPE PopupType, + IN EFI_HII_HANDLE HiiHandle, + IN EFI_STRING_ID Message, + OUT EFI_HII_POPUP_SELECTION *UserSelection OPTIONAL +); + +struct _EFI_HII_POPUP_PROTOCOL { + UINT64 Revision; + EFI_HII_CREATE_POPUP CreatePopup; +}; + +extern EFI_GUID gEfiHiiPopupProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiString.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiString.h new file mode 100644 index 0000000000..989d181f5a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HiiString.h @@ -0,0 +1,238 @@ +/** @file + The file provides services to manipulate string data. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.1. + +**/ + +#ifndef __HII_STRING_H__ +#define __HII_STRING_H__ + +#include + +#define EFI_HII_STRING_PROTOCOL_GUID \ + { 0xfd96974, 0x23aa, 0x4cdc, { 0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a } } + +typedef struct _EFI_HII_STRING_PROTOCOL EFI_HII_STRING_PROTOCOL; + +/** + This function adds the string String to the group of strings owned by PackageList, with the + specified font information StringFontInfo, and returns a new string id. + The new string identifier is guaranteed to be unique within the package list. + That new string identifier is reserved for all languages in the package list. + + @param This A pointer to the EFI_HII_STRING_PROTOCOL instance. + @param PackageList The handle of the package list where this string will + be added. + @param StringId On return, contains the new strings id, which is + unique within PackageList. + @param Language Points to the language for the new string. + @param LanguageName Points to the printable language name to associate + with the passed in Language field.If LanguageName + is not NULL and the string package header's + LanguageName associated with a given Language is + not zero, the LanguageName being passed in will + be ignored. + @param String Points to the new null-terminated string. + @param StringFontInfo Points to the new string's font information or + NULL if the string should have the default system + font, size and style. + + @retval EFI_SUCCESS The new string was added successfully. + @retval EFI_NOT_FOUND The specified PackageList could not be found in + database. + @retval EFI_OUT_OF_RESOURCES Could not add the string due to lack of resources. + @retval EFI_INVALID_PARAMETER String is NULL, or StringId is NULL, or Language is NULL. + @retval EFI_INVALID_PARAMETER The specified StringFontInfo does not exist in + current database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_NEW_STRING)( + IN CONST EFI_HII_STRING_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + OUT EFI_STRING_ID *StringId, + IN CONST CHAR8 *Language, + IN CONST CHAR16 *LanguageName, OPTIONAL + IN CONST EFI_STRING String, + IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL +); + + +/** + This function retrieves the string specified by StringId which is associated + with the specified PackageList in the language Language and copies it into + the buffer specified by String. + + @param This A pointer to the EFI_HII_STRING_PROTOCOL instance. + @param Language Points to the language for the retrieved string. + @param PackageList The package list in the HII database to search for + the specified string. + @param StringId The string's id, which is unique within + PackageList. + @param String Points to the new null-terminated string. + @param StringSize On entry, points to the size of the buffer pointed + to by String, in bytes. On return, points to the + length of the string, in bytes. + @param StringFontInfo If not NULL, points to the string's font + information. It's caller's responsibility to free + this buffer. + + @retval EFI_SUCCESS The string was returned successfully. + @retval EFI_NOT_FOUND The string specified by StringId is not available. + The specified PackageList is not in the database. + @retval EFI_INVALID_LANGUAGE The string specified by StringId is available but + not in the specified language. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by StringSize is too small to + hold the string. + @retval EFI_INVALID_PARAMETER The Language or StringSize was NULL. + @retval EFI_INVALID_PARAMETER The value referenced by StringSize was not zero and + String was NULL. + @retval EFI_OUT_OF_RESOURCES There were insufficient resources to complete the + request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_STRING)( + IN CONST EFI_HII_STRING_PROTOCOL *This, + IN CONST CHAR8 *Language, + IN EFI_HII_HANDLE PackageList, + IN EFI_STRING_ID StringId, + OUT EFI_STRING String, + IN OUT UINTN *StringSize, + OUT EFI_FONT_INFO **StringFontInfo OPTIONAL +); + +/** + This function updates the string specified by StringId in the specified PackageList to the text + specified by String and, optionally, the font information specified by StringFontInfo. + + @param This A pointer to the EFI_HII_STRING_PROTOCOL instance. + @param PackageList The package list containing the strings. + @param StringId The string's id, which is unique within + PackageList. + @param Language Points to the language for the updated string. + @param String Points to the new null-terminated string. + @param StringFontInfo Points to the string's font information or NULL if + the string font information is not changed. + + @retval EFI_SUCCESS The string was updated successfully. + @retval EFI_NOT_FOUND The string specified by StringId is not in the + database. + @retval EFI_INVALID_PARAMETER The String or Language was NULL. + @retval EFI_INVALID_PARAMETER The specified StringFontInfo does not exist in + current database. + @retval EFI_OUT_OF_RESOURCES The system is out of resources to accomplish the + task. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_SET_STRING)( + IN CONST EFI_HII_STRING_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN EFI_STRING_ID StringId, + IN CONST CHAR8 *Language, + IN EFI_STRING String, + IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL +); + + +/** + This function returns the list of supported languages. + + @param This A pointer to the EFI_HII_STRING_PROTOCOL instance. + @param PackageList The package list to examine. + @param Languages Points to the buffer to hold the returned + null-terminated ASCII string. + @param LanguagesSize On entry, points to the size of the buffer pointed + to by Languages, in bytes. On return, points to + the length of Languages, in bytes. + + @retval EFI_SUCCESS The languages were returned successfully. + @retval EFI_INVALID_PARAMETER The LanguagesSize was NULL. + @retval EFI_INVALID_PARAMETER The value referenced by LanguagesSize is not zero + and Languages is NULL. + @retval EFI_BUFFER_TOO_SMALL The LanguagesSize is too small to hold the list of + supported languages. LanguageSize is updated to + contain the required size. + @retval EFI_NOT_FOUND Could not find string package in specified + packagelist. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_LANGUAGES)( + IN CONST EFI_HII_STRING_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN OUT CHAR8 *Languages, + IN OUT UINTN *LanguagesSize +); + + +/** + Each string package has associated with it a single primary language and zero + or more secondary languages. This routine returns the secondary languages + associated with a package list. + + @param This A pointer to the EFI_HII_STRING_PROTOCOL instance. + @param PackageList The package list to examine. + @param PrimaryLanguage Points to the null-terminated ASCII string that specifies + the primary language. Languages are specified in the + format specified in Appendix M of the UEFI 2.0 specification. + @param SecondaryLanguages Points to the buffer to hold the returned null-terminated + ASCII string that describes the list of + secondary languages for the specified + PrimaryLanguage. If there are no secondary + languages, the function returns successfully, but + this is set to NULL. + @param SecondaryLanguagesSize On entry, points to the size of the buffer pointed + to by SecondaryLanguages, in bytes. On return, + points to the length of SecondaryLanguages in bytes. + + @retval EFI_SUCCESS Secondary languages were correctly returned. + @retval EFI_INVALID_PARAMETER PrimaryLanguage or SecondaryLanguagesSize was NULL. + @retval EFI_INVALID_PARAMETER The value referenced by SecondaryLanguagesSize is not + zero and SecondaryLanguages is NULL. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by SecondaryLanguagesSize is + too small to hold the returned information. + SecondaryLanguageSize is updated to hold the size of + the buffer required. + @retval EFI_INVALID_LANGUAGE The language specified by PrimaryLanguage is not + present in the specified package list. + @retval EFI_NOT_FOUND The specified PackageList is not in the Database. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HII_GET_2ND_LANGUAGES)( + IN CONST EFI_HII_STRING_PROTOCOL *This, + IN EFI_HII_HANDLE PackageList, + IN CONST CHAR8 *PrimaryLanguage, + IN OUT CHAR8 *SecondaryLanguages, + IN OUT UINTN *SecondaryLanguagesSize +); + + +/// +/// Services to manipulate the string. +/// +struct _EFI_HII_STRING_PROTOCOL { + EFI_HII_NEW_STRING NewString; + EFI_HII_GET_STRING GetString; + EFI_HII_SET_STRING SetString; + EFI_HII_GET_LANGUAGES GetLanguages; + EFI_HII_GET_2ND_LANGUAGES GetSecondaryLanguages; +}; + + +extern EFI_GUID gEfiHiiStringProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Http.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Http.h new file mode 100644 index 0000000000..30a691bd2d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Http.h @@ -0,0 +1,516 @@ +/** @file + This file defines the EFI HTTP Protocol interface. It is split into + the following two main sections: + HTTP Service Binding Protocol (HTTPSB) + HTTP Protocol (HTTP) + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_HTTP_PROTOCOL_H__ +#define __EFI_HTTP_PROTOCOL_H__ + +#define EFI_HTTP_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xbdc8e6af, 0xd9bc, 0x4379, {0xa7, 0x2a, 0xe0, 0xc4, 0xe7, 0x5d, 0xae, 0x1c } \ + } + +#define EFI_HTTP_PROTOCOL_GUID \ + { \ + 0x7a59b29b, 0x910b, 0x4171, {0x82, 0x42, 0xa8, 0x5a, 0x0d, 0xf2, 0x5b, 0x5b } \ + } + +typedef struct _EFI_HTTP_PROTOCOL EFI_HTTP_PROTOCOL; + +/// +/// EFI_HTTP_VERSION +/// +typedef enum { + HttpVersion10, + HttpVersion11, + HttpVersionUnsupported +} EFI_HTTP_VERSION; + +/// +/// EFI_HTTP_METHOD +/// +typedef enum { + HttpMethodGet, + HttpMethodPost, + HttpMethodPatch, + HttpMethodOptions, + HttpMethodConnect, + HttpMethodHead, + HttpMethodPut, + HttpMethodDelete, + HttpMethodTrace, + HttpMethodMax +} EFI_HTTP_METHOD; + +/// +/// EFI_HTTP_STATUS_CODE +/// +typedef enum { + HTTP_STATUS_UNSUPPORTED_STATUS = 0, + HTTP_STATUS_100_CONTINUE, + HTTP_STATUS_101_SWITCHING_PROTOCOLS, + HTTP_STATUS_200_OK, + HTTP_STATUS_201_CREATED, + HTTP_STATUS_202_ACCEPTED, + HTTP_STATUS_203_NON_AUTHORITATIVE_INFORMATION, + HTTP_STATUS_204_NO_CONTENT, + HTTP_STATUS_205_RESET_CONTENT, + HTTP_STATUS_206_PARTIAL_CONTENT, + HTTP_STATUS_300_MULTIPLE_CHOICES, + HTTP_STATUS_301_MOVED_PERMANENTLY, + HTTP_STATUS_302_FOUND, + HTTP_STATUS_303_SEE_OTHER, + HTTP_STATUS_304_NOT_MODIFIED, + HTTP_STATUS_305_USE_PROXY, + HTTP_STATUS_307_TEMPORARY_REDIRECT, + HTTP_STATUS_400_BAD_REQUEST, + HTTP_STATUS_401_UNAUTHORIZED, + HTTP_STATUS_402_PAYMENT_REQUIRED, + HTTP_STATUS_403_FORBIDDEN, + HTTP_STATUS_404_NOT_FOUND, + HTTP_STATUS_405_METHOD_NOT_ALLOWED, + HTTP_STATUS_406_NOT_ACCEPTABLE, + HTTP_STATUS_407_PROXY_AUTHENTICATION_REQUIRED, + HTTP_STATUS_408_REQUEST_TIME_OUT, + HTTP_STATUS_409_CONFLICT, + HTTP_STATUS_410_GONE, + HTTP_STATUS_411_LENGTH_REQUIRED, + HTTP_STATUS_412_PRECONDITION_FAILED, + HTTP_STATUS_413_REQUEST_ENTITY_TOO_LARGE, + HTTP_STATUS_414_REQUEST_URI_TOO_LARGE, + HTTP_STATUS_415_UNSUPPORTED_MEDIA_TYPE, + HTTP_STATUS_416_REQUESTED_RANGE_NOT_SATISFIED, + HTTP_STATUS_417_EXPECTATION_FAILED, + HTTP_STATUS_500_INTERNAL_SERVER_ERROR, + HTTP_STATUS_501_NOT_IMPLEMENTED, + HTTP_STATUS_502_BAD_GATEWAY, + HTTP_STATUS_503_SERVICE_UNAVAILABLE, + HTTP_STATUS_504_GATEWAY_TIME_OUT, + HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED, + HTTP_STATUS_308_PERMANENT_REDIRECT +} EFI_HTTP_STATUS_CODE; + +/// +/// EFI_HTTPv4_ACCESS_POINT +/// +typedef struct { + /// + /// Set to TRUE to instruct the EFI HTTP instance to use the default address + /// information in every TCP connection made by this instance. In addition, when set + /// to TRUE, LocalAddress and LocalSubnet are ignored. + /// + BOOLEAN UseDefaultAddress; + /// + /// If UseDefaultAddress is set to FALSE, this defines the local IP address to be + /// used in every TCP connection opened by this instance. + /// + EFI_IPv4_ADDRESS LocalAddress; + /// + /// If UseDefaultAddress is set to FALSE, this defines the local subnet to be used + /// in every TCP connection opened by this instance. + /// + EFI_IPv4_ADDRESS LocalSubnet; + /// + /// This defines the local port to be used in + /// every TCP connection opened by this instance. + /// + UINT16 LocalPort; +} EFI_HTTPv4_ACCESS_POINT; + +/// +/// EFI_HTTPv6_ACCESS_POINT +/// +typedef struct { + /// + /// Local IP address to be used in every TCP connection opened by this instance. + /// + EFI_IPv6_ADDRESS LocalAddress; + /// + /// Local port to be used in every TCP connection opened by this instance. + /// + UINT16 LocalPort; +} EFI_HTTPv6_ACCESS_POINT; + +/// +/// EFI_HTTP_CONFIG_DATA_ACCESS_POINT +/// + + +typedef struct { + /// + /// HTTP version that this instance will support. + /// + EFI_HTTP_VERSION HttpVersion; + /// + /// Time out (in milliseconds) when blocking for requests. + /// + UINT32 TimeOutMillisec; + /// + /// Defines behavior of EFI DNS and TCP protocols consumed by this instance. If + /// FALSE, this instance will use EFI_DNS4_PROTOCOL and EFI_TCP4_PROTOCOL. If TRUE, + /// this instance will use EFI_DNS6_PROTOCOL and EFI_TCP6_PROTOCOL. + /// + BOOLEAN LocalAddressIsIPv6; + + union { + /// + /// When LocalAddressIsIPv6 is FALSE, this points to the local address, subnet, and + /// port used by the underlying TCP protocol. + /// + EFI_HTTPv4_ACCESS_POINT *IPv4Node; + /// + /// When LocalAddressIsIPv6 is TRUE, this points to the local IPv6 address and port + /// used by the underlying TCP protocol. + /// + EFI_HTTPv6_ACCESS_POINT *IPv6Node; + } AccessPoint; +} EFI_HTTP_CONFIG_DATA; + +/// +/// EFI_HTTP_REQUEST_DATA +/// +typedef struct { + /// + /// The HTTP method (e.g. GET, POST) for this HTTP Request. + /// + EFI_HTTP_METHOD Method; + /// + /// The URI of a remote host. From the information in this field, the HTTP instance + /// will be able to determine whether to use HTTP or HTTPS and will also be able to + /// determine the port number to use. If no port number is specified, port 80 (HTTP) + /// is assumed. See RFC 3986 for more details on URI syntax. + /// + CHAR16 *Url; +} EFI_HTTP_REQUEST_DATA; + +/// +/// EFI_HTTP_RESPONSE_DATA +/// +typedef struct { + /// + /// Response status code returned by the remote host. + /// + EFI_HTTP_STATUS_CODE StatusCode; +} EFI_HTTP_RESPONSE_DATA; + +/// +/// EFI_HTTP_HEADER +/// +typedef struct { + /// + /// Null terminated string which describes a field name. See RFC 2616 Section 14 for + /// detailed information about field names. + /// + CHAR8 *FieldName; + /// + /// Null terminated string which describes the corresponding field value. See RFC 2616 + /// Section 14 for detailed information about field values. + /// + CHAR8 *FieldValue; +} EFI_HTTP_HEADER; + +/// +/// EFI_HTTP_MESSAGE +/// +typedef struct { + /// + /// HTTP message data. + /// + union { + /// + /// When the token is used to send a HTTP request, Request is a pointer to storage that + /// contains such data as URL and HTTP method. + /// + EFI_HTTP_REQUEST_DATA *Request; + /// + /// When used to await a response, Response points to storage containing HTTP response + /// status code. + /// + EFI_HTTP_RESPONSE_DATA *Response; + } Data; + /// + /// Number of HTTP header structures in Headers list. On request, this count is + /// provided by the caller. On response, this count is provided by the HTTP driver. + /// + UINTN HeaderCount; + /// + /// Array containing list of HTTP headers. On request, this array is populated by the + /// caller. On response, this array is allocated and populated by the HTTP driver. It + /// is the responsibility of the caller to free this memory on both request and + /// response. + /// + EFI_HTTP_HEADER *Headers; + /// + /// Length in bytes of the HTTP body. This can be zero depending on the HttpMethod type. + /// + UINTN BodyLength; + /// + /// Body associated with the HTTP request or response. This can be NULL depending on + /// the HttpMethod type. + /// + VOID *Body; +} EFI_HTTP_MESSAGE; + + +/// +/// EFI_HTTP_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI HTTP + /// Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. The Task Priority + /// Level (TPL) of Event must be lower than or equal to TPL_CALLBACK. + /// + EFI_EVENT Event; + /// + /// Status will be set to one of the following value if the HTTP request is + /// successfully sent or if an unexpected error occurs: + /// EFI_SUCCESS: The HTTP request was successfully sent to the remote host. + /// EFI_HTTP_ERROR: The response message was successfully received but contains a + /// HTTP error. The response status code is returned in token. + /// EFI_ABORTED: The HTTP request was cancelled by the caller and removed from + /// the transmit queue. + /// EFI_TIMEOUT: The HTTP request timed out before reaching the remote host. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// + EFI_STATUS Status; + /// + /// Pointer to storage containing HTTP message data. + /// + EFI_HTTP_MESSAGE *Message; +} EFI_HTTP_TOKEN; + +/** + Returns the operational parameters for the current HTTP child instance. + + The GetModeData() function is used to read the current mode data (operational + parameters) for this HTTP protocol instance. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + @param[out] HttpConfigData Point to buffer for operational parameters of this + HTTP instance. It is the responsibility of the caller + to allocate the memory for HttpConfigData and + HttpConfigData->AccessPoint.IPv6Node/IPv4Node. In fact, + it is recommended to allocate sufficient memory to record + IPv6Node since it is big enough for all possibilities. + + @retval EFI_SUCCESS Operation succeeded. + @retval EFI_INVALID_PARAMETER This is NULL. + HttpConfigData is NULL. + HttpConfigData->AccessPoint.IPv4Node or + HttpConfigData->AccessPoint.IPv6Node is NULL. + @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_GET_MODE_DATA)( + IN EFI_HTTP_PROTOCOL *This, + OUT EFI_HTTP_CONFIG_DATA *HttpConfigData + ); + +/** + Initialize or brutally reset the operational parameters for this EFI HTTP instance. + + The Configure() function does the following: + When HttpConfigData is not NULL Initialize this EFI HTTP instance by configuring + timeout, local address, port, etc. + When HttpConfigData is NULL, reset this EFI HTTP instance by closing all active + connections with remote hosts, canceling all asynchronous tokens, and flush request + and response buffers without informing the appropriate hosts. + + No other EFI HTTP function can be executed by this instance until the Configure() + function is executed and returns successfully. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + @param[in] HttpConfigData Pointer to the configure data to configure the instance. + + @retval EFI_SUCCESS Operation succeeded. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + HttpConfigData->LocalAddressIsIPv6 is FALSE and + HttpConfigData->AccessPoint.IPv4Node is NULL. + HttpConfigData->LocalAddressIsIPv6 is TRUE and + HttpConfigData->AccessPoint.IPv6Node is NULL. + @retval EFI_ALREADY_STARTED Reinitialize this HTTP instance without calling + Configure() with NULL to reset it. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources when + executing Configure(). + @retval EFI_UNSUPPORTED One or more options in ConfigData are not supported + in the implementation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_CONFIGURE)( + IN EFI_HTTP_PROTOCOL *This, + IN EFI_HTTP_CONFIG_DATA *HttpConfigData OPTIONAL + ); + +/** + The Request() function queues an HTTP request to this HTTP instance, + similar to Transmit() function in the EFI TCP driver. When the HTTP request is sent + successfully, or if there is an error, Status in token will be updated and Event will + be signaled. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + @param[in] Token Pointer to storage containing HTTP request token. + + @retval EFI_SUCCESS Outgoing data was processed. + @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit or receive queue. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token->Message is NULL. + Token->Message->Body is not NULL, + Token->Message->BodyLength is non-zero, and + Token->Message->Data is NULL, but a previous call to + Request()has not been completed successfully. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources. + @retval EFI_UNSUPPORTED The HTTP method is not supported in current implementation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_REQUEST) ( + IN EFI_HTTP_PROTOCOL *This, + IN EFI_HTTP_TOKEN *Token + ); + +/** + Abort an asynchronous HTTP request or response token. + + The Cancel() function aborts a pending HTTP request or response transaction. If + Token is not NULL and the token is in transmit or receive queues when it is being + cancelled, its Token->Status will be set to EFI_ABORTED and then Token->Event will + be signaled. If the token is not in one of the queues, which usually means that the + asynchronous operation has completed, EFI_NOT_FOUND is returned. If Token is NULL, + all asynchronous tokens issued by Request() or Response() will be aborted. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + @param[in] Token Point to storage containing HTTP request or response + token. + + @retval EFI_SUCCESS Request and Response queues are successfully flushed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance hasn't been configured. + @retval EFI_NOT_FOUND The asynchronous request or response token is not + found. + @retval EFI_UNSUPPORTED The implementation does not support this function. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_CANCEL)( + IN EFI_HTTP_PROTOCOL *This, + IN EFI_HTTP_TOKEN *Token + ); + +/** + The Response() function queues an HTTP response to this HTTP instance, similar to + Receive() function in the EFI TCP driver. When the HTTP Response is received successfully, + or if there is an error, Status in token will be updated and Event will be signaled. + + The HTTP driver will queue a receive token to the underlying TCP instance. When data + is received in the underlying TCP instance, the data will be parsed and Token will + be populated with the response data. If the data received from the remote host + contains an incomplete or invalid HTTP header, the HTTP driver will continue waiting + (asynchronously) for more data to be sent from the remote host before signaling + Event in Token. + + It is the responsibility of the caller to allocate a buffer for Body and specify the + size in BodyLength. If the remote host provides a response that contains a content + body, up to BodyLength bytes will be copied from the receive buffer into Body and + BodyLength will be updated with the amount of bytes received and copied to Body. This + allows the client to download a large file in chunks instead of into one contiguous + block of memory. Similar to HTTP request, if Body is not NULL and BodyLength is + non-zero and all other fields are NULL or 0, the HTTP driver will queue a receive + token to underlying TCP instance. If data arrives in the receive buffer, up to + BodyLength bytes of data will be copied to Body. The HTTP driver will then update + BodyLength with the amount of bytes received and copied to Body. + + If the HTTP driver does not have an open underlying TCP connection with the host + specified in the response URL, Request() will return EFI_ACCESS_DENIED. This is + consistent with RFC 2616 recommendation that HTTP clients should attempt to maintain + an open TCP connection between client and host. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + @param[in] Token Pointer to storage containing HTTP response token. + + @retval EFI_SUCCESS Allocation succeeded. + @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been + initialized. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Token is NULL. + Token->Message->Headers is NULL. + Token->Message is NULL. + Token->Message->Body is not NULL, + Token->Message->BodyLength is non-zero, and + Token->Message->Data is NULL, but a previous call to + Response() has not been completed successfully. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources. + @retval EFI_ACCESS_DENIED An open TCP connection is not present with the host + specified by response URL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_RESPONSE) ( + IN EFI_HTTP_PROTOCOL *This, + IN EFI_HTTP_TOKEN *Token + ); + +/** + The Poll() function can be used by network drivers and applications to increase the + rate that data packets are moved between the communication devices and the transmit + and receive queues. + + In some systems, the periodic timer event in the managed network driver may not poll + the underlying communications device fast enough to transmit and/or receive all data + packets without missing incoming packets or dropping outgoing packets. Drivers and + applications that are experiencing packet loss should try calling the Poll() function + more often. + + @param[in] This Pointer to EFI_HTTP_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed.. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_READY No incoming or outgoing data is processed. + @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been started. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_POLL) ( + IN EFI_HTTP_PROTOCOL *This + ); + +/// +/// The EFI HTTP protocol is designed to be used by EFI drivers and applications to +/// create and transmit HTTP Requests, as well as handle HTTP responses that are +/// returned by a remote host. This EFI protocol uses and relies on an underlying EFI +/// TCP protocol. +/// +struct _EFI_HTTP_PROTOCOL { + EFI_HTTP_GET_MODE_DATA GetModeData; + EFI_HTTP_CONFIGURE Configure; + EFI_HTTP_REQUEST Request; + EFI_HTTP_CANCEL Cancel; + EFI_HTTP_RESPONSE Response; + EFI_HTTP_POLL Poll; +}; + +extern EFI_GUID gEfiHttpServiceBindingProtocolGuid; +extern EFI_GUID gEfiHttpProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpBootCallback.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpBootCallback.h new file mode 100644 index 0000000000..2381c9dbc7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpBootCallback.h @@ -0,0 +1,94 @@ +/** @file + This file defines the EFI HTTP Boot Callback Protocol interface. + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __EFI_HTTP_BOOT_CALLBACK_H__ +#define __EFI_HTTP_BOOT_CALLBACK_H__ + +#define EFI_HTTP_BOOT_CALLBACK_PROTOCOL_GUID \ + { \ + 0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58, 0x20, 0xb1, 0xd6, 0x52, 0x99} \ + } + +typedef struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL EFI_HTTP_BOOT_CALLBACK_PROTOCOL; + +/// +/// EFI_HTTP_BOOT_CALLBACK_DATA_TYPE +/// +typedef enum { + /// + /// Data points to a DHCP4 packet which is about to transmit or has received. + /// + HttpBootDhcp4, + /// + /// Data points to a DHCP6 packet which is about to be transmit or has received. + /// + HttpBootDhcp6, + /// + /// Data points to an EFI_HTTP_MESSAGE structure, whichcontians a HTTP request message + /// to be transmitted. + /// + HttpBootHttpRequest, + /// + /// Data points to an EFI_HTTP_MESSAGE structure, which contians a received HTTP + /// response message. + /// + HttpBootHttpResponse, + /// + /// Part of the entity body has been received from the HTTP server. Data points to the + /// buffer of the entity body data. + /// + HttpBootHttpEntityBody, + HttpBootTypeMax +} EFI_HTTP_BOOT_CALLBACK_DATA_TYPE; + +/** + Callback function that is invoked when the HTTP Boot driver is about to transmit or has received a + packet. + + This function is invoked when the HTTP Boot driver is about to transmit or has received packet. + Parameters DataType and Received specify the type of event and the format of the buffer pointed + to by Data. Due to the polling nature of UEFI device drivers, this callback function should not + execute for more than 5 ms. + The returned status code determines the behavior of the HTTP Boot driver. + + @param[in] This Pointer to the EFI_HTTP_BOOT_CALLBACK_PROTOCOL instance. + @param[in] DataType The event that occurs in the current state. + @param[in] Received TRUE if the callback is being invoked due to a receive event. + FALSE if the callback is being invoked due to a transmit event. + @param[in] DataLength The length in bytes of the buffer pointed to by Data. + @param[in] Data A pointer to the buffer of data, the data type is specified by + DataType. + + @retval EFI_SUCCESS Tells the HTTP Boot driver to continue the HTTP Boot process. + @retval EFI_ABORTED Tells the HTTP Boot driver to abort the current HTTP Boot process. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_HTTP_BOOT_CALLBACK) ( + IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This, + IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPE DataType, + IN BOOLEAN Received, + IN UINT32 DataLength, + IN VOID *Data OPTIONAL + ); + +/// +/// EFI HTTP Boot Callback Protocol is invoked when the HTTP Boot driver is about to transmit or +/// has received a packet. The EFI HTTP Boot Callback Protocol must be installed on the same handle +/// as the Load File Protocol for the HTTP Boot. +/// +struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL { + EFI_HTTP_BOOT_CALLBACK Callback; +}; + +extern EFI_GUID gEfiHttpBootCallbackProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpUtilities.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpUtilities.h new file mode 100644 index 0000000000..b54666295b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/HttpUtilities.h @@ -0,0 +1,118 @@ +/** @file + EFI HTTP Utilities protocol provides a platform independent abstraction for HTTP + message comprehension. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_HTTP_UTILITIES_PROTOCOL_H__ +#define __EFI_HTTP_UTILITIES_PROTOCOL_H__ + +#include + +#define EFI_HTTP_UTILITIES_PROTOCOL_GUID \ + { \ + 0x3e35c163, 0x4074, 0x45dd, {0x43, 0x1e, 0x23, 0x98, 0x9d, 0xd8, 0x6b, 0x32 } \ + } + +typedef struct _EFI_HTTP_UTILITIES_PROTOCOL EFI_HTTP_UTILITIES_PROTOCOL; + + +/** + Create HTTP header based on a combination of seed header, fields + to delete, and fields to append. + + The Build() function is used to manage the headers portion of an + HTTP message by providing the ability to add, remove, or replace + HTTP headers. + + @param[in] This Pointer to EFI_HTTP_UTILITIES_PROTOCOL instance. + @param[in] SeedMessageSize Size of the initial HTTP header. This can be zero. + @param[in] SeedMessage Initial HTTP header to be used as a base for + building a new HTTP header. If NULL, + SeedMessageSize is ignored. + @param[in] DeleteCount Number of null-terminated HTTP header field names + in DeleteList. + @param[in] DeleteList List of null-terminated HTTP header field names to + remove from SeedMessage. Only the field names are + in this list because the field values are irrelevant + to this operation. + @param[in] AppendCount Number of header fields in AppendList. + @param[in] AppendList List of HTTP headers to populate NewMessage with. + If SeedMessage is not NULL, AppendList will be + appended to the existing list from SeedMessage in + NewMessage. + @param[out] NewMessageSize Pointer to number of header fields in NewMessage. + @param[out] NewMessage Pointer to a new list of HTTP headers based on. + + @retval EFI_SUCCESS Add, remove, and replace operations succeeded. + @retval EFI_OUT_OF_RESOURCES Could not allocate memory for NewMessage. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_UTILS_BUILD) ( + IN EFI_HTTP_UTILITIES_PROTOCOL *This, + IN UINTN SeedMessageSize, + IN VOID *SeedMessage, OPTIONAL + IN UINTN DeleteCount, + IN CHAR8 *DeleteList[], OPTIONAL + IN UINTN AppendCount, + IN EFI_HTTP_HEADER *AppendList[], OPTIONAL + OUT UINTN *NewMessageSize, + OUT VOID **NewMessage + ); + +/** + Parses HTTP header and produces an array of key/value pairs. + + The Parse() function is used to transform data stored in HttpHeader + into a list of fields paired with their corresponding values. + + @param[in] This Pointer to EFI_HTTP_UTILITIES_PROTOCOL instance. + @param[in] HttpMessage Contains raw unformatted HTTP header string. + @param[in] HttpMessageSize Size of HTTP header. + @param[out] HeaderFields Array of key/value header pairs. + @param[out] FieldCount Number of headers in HeaderFields. + + @retval EFI_SUCCESS Allocation succeeded. + @retval EFI_NOT_STARTED This EFI HTTP Protocol instance has not been + initialized. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + HttpMessage is NULL. + HeaderFields is NULL. + FieldCount is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HTTP_UTILS_PARSE) ( + IN EFI_HTTP_UTILITIES_PROTOCOL *This, + IN CHAR8 *HttpMessage, + IN UINTN HttpMessageSize, + OUT EFI_HTTP_HEADER **HeaderFields, + OUT UINTN *FieldCount + ); + + +/// +/// EFI_HTTP_UTILITIES_PROTOCOL +/// designed to be used by EFI drivers and applications to parse HTTP +/// headers from a byte stream. This driver is neither dependent on +/// network connectivity, nor the existence of an underlying network +/// infrastructure. +/// +struct _EFI_HTTP_UTILITIES_PROTOCOL { + EFI_HTTP_UTILS_BUILD Build; + EFI_HTTP_UTILS_PARSE Parse; +}; + +extern EFI_GUID gEfiHttpUtilitiesProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h new file mode 100644 index 0000000000..848e141567 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h @@ -0,0 +1,165 @@ +/** @file + I2C Bus Configuration Management Protocol as defined in the PI 1.3 specification. + + The EFI I2C bus configuration management protocol provides platform specific + services that allow the I2C host protocol to reconfigure the switches and multiplexers + and set the clock frequency for the I2C bus. This protocol also enables the I2C host protocol + to reset an I2C device which may be locking up the I2C bus by holding the clock or data line low. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.3. + +**/ + +#ifndef __I2C_BUS_CONFIGURATION_MANAGEMENT_H__ +#define __I2C_BUS_CONFIGURATION_MANAGEMENT_H__ + +#define EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_GUID \ + { 0x55b71fb5, 0x17c6, 0x410e, { 0xb5, 0xbd, 0x5f, 0xa2, 0xe3, 0xd4, 0x46, 0x6b }} + +/// +/// I2C bus configuration management protocol +/// +/// The EFI I2C bus configuration management protocol provides platform +/// specific services that allow the I2C host protocol to reconfigure the +/// switches and multiplexers and set the clock frequency for the I2C bus. +/// This protocol also enables the I2C host protocol to reset an I2C device +/// which may be locking up the I2C bus by holding the clock or data line +/// low. +/// +/// The I2C protocol stack uses the concept of an I2C bus configuration as +/// a way to describe a particular state of the switches and multiplexers +/// in the I2C bus. +/// +/// A simple I2C bus does not have any multiplexers or switches is described +/// to the I2C protocol stack with a single I2C bus configuration which +/// specifies the I2C bus frequency. +/// +/// An I2C bus with switches and multiplexers use an I2C bus configuration +/// to describe each of the unique settings for the switches and multiplexers +/// and the I2C bus frequency. However the I2C bus configuration management +/// protocol only needs to define the I2C bus configurations that the software +/// uses, which may be a subset of the total. +/// +/// The I2C bus configuration description includes a list of I2C devices +/// which may be accessed when this I2C bus configuration is enabled. I2C +/// devices before a switch or multiplexer must be included in one I2C bus +/// configuration while I2C devices after a switch or multiplexer are on +/// another I2C bus configuration. +/// +/// The I2C bus configuration management protocol is an optional protocol. +/// When the I2C bus configuration protocol is not defined the I2C host +/// protocol does not start and the I2C master protocol may be used for +/// other purposes such as SMBus traffic. When the I2C bus configuration +/// protocol is available, the I2C host protocol uses the I2C bus +/// configuration protocol to call into the platform specific code to set +/// the switches and multiplexers and set the maximum I2C bus frequency. +/// +/// The platform designers determine the maximum I2C bus frequency by +/// selecting a frequency which supports all of the I2C devices on the +/// I2C bus for the setting of switches and multiplexers. The platform +/// designers must validate this against the I2C device data sheets and +/// any limits of the I2C controller or bus length. +/// +/// During I2C device enumeration, the I2C bus driver retrieves the I2C +/// bus configuration that must be used to perform I2C transactions to +/// each I2C device. This I2C bus configuration value is passed into +/// the I2C host protocol to identify the I2C bus configuration required +/// to access a specific I2C device. The I2C host protocol calls +/// EnableBusConfiguration() to set the switches and multiplexers in the +/// I2C bus and the I2C clock frequency. The I2C host protocol may +/// optimize calls to EnableBusConfiguration() by only making the call +/// when the I2C bus configuration value changes between I2C requests. +/// +/// When I2C transactions are required on the same I2C bus to change the +/// state of multiplexers or switches, the I2C master protocol must be +/// used to perform the necessary I2C transactions. +/// +/// It is up to the platform specific code to choose the proper I2C bus +/// configuration when ExitBootServices() is called. Some operating systems +/// are not able to manage the I2C bus configurations and must use the I2C +/// bus configuration that is established by the platform firmware before +/// ExitBootServices() returns. +/// +typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL; + + +/** + Enable access to an I2C bus configuration. + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + Reconfigure the switches and multiplexers in the I2C bus to enable + access to a specific I2C bus configuration. Also select the maximum + clock frequency for this I2C bus configuration. + + This routine uses the I2C Master protocol to perform I2C transactions + on the local bus. This eliminates any recursion in the I2C stack for + configuration transactions on the same I2C bus. This works because the + local I2C bus is idle while the I2C bus configuration is being enabled. + + If I2C transactions must be performed on other I2C busses, then the + EFI_I2C_HOST_PROTOCOL, the EFI_I2C_IO_PROTCOL, or a third party I2C + driver interface for a specific device must be used. This requirement + is because the I2C host protocol controls the flow of requests to the + I2C controller. Use the EFI_I2C_HOST_PROTOCOL when the I2C device is + not enumerated by the EFI_I2C_ENUMERATE_PROTOCOL. Use a protocol + produced by a third party driver when it is available or the + EFI_I2C_IO_PROTOCOL when the third party driver is not available but + the device is enumerated with the EFI_I2C_ENUMERATE_PROTOCOL. + + When Event is NULL, EnableI2cBusConfiguration operates synchronously + and returns the I2C completion status as its return value. + + @param[in] This Pointer to an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL + structure. + @param[in] I2cBusConfiguration Index of an I2C bus configuration. All + values in the range of zero to N-1 are + valid where N is the total number of I2C + bus configurations for an I2C bus. + @param[in] Event Event to signal when the transaction is complete + @param[out] I2cStatus Buffer to receive the transaction status. + + @return When Event is NULL, EnableI2cBusConfiguration operates synchrouously + and returns the I2C completion status as its return value. In this case it is + recommended to use NULL for I2cStatus. The values returned from + EnableI2cBusConfiguration are: + + @retval EFI_SUCCESS The asynchronous bus configuration request + was successfully started when Event is not + NULL. + @retval EFI_SUCCESS The bus configuration request completed + successfully when Event is NULL. + @retval EFI_DEVICE_ERROR The bus configuration failed. + @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION) ( + IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + IN EFI_EVENT Event OPTIONAL, + IN EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// I2C bus configuration management protocol +/// +struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL { + /// + /// Enable an I2C bus configuration for use. + /// + EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration; +}; + +/// +/// Reference to variable defined in the .DEC file +/// +extern EFI_GUID gEfiI2cBusConfigurationManagementProtocolGuid; + +#endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cEnumerate.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cEnumerate.h new file mode 100644 index 0000000000..d7bcb15ea8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cEnumerate.h @@ -0,0 +1,104 @@ +/** @file + I2C Device Enumerate Protocol as defined in the PI 1.3 specification. + + This protocol supports the enumerations of device on the I2C bus. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.3. + +**/ + +#ifndef __I2C_ENUMERATE_H__ +#define __I2C_ENUMERATE_H__ + +#include + +#define EFI_I2C_ENUMERATE_PROTOCOL_GUID { 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, 0xe7, 0x01, 0x89, 0x4c }} + +typedef struct _EFI_I2C_ENUMERATE_PROTOCOL EFI_I2C_ENUMERATE_PROTOCOL; + +/** + Enumerate the I2C devices + + This function enables the caller to traverse the set of I2C devices + on an I2C bus. + + @param[in] This The platform data for the next device on + the I2C bus was returned successfully. + @param[in, out] Device Pointer to a buffer containing an + EFI_I2C_DEVICE structure. Enumeration is + started by setting the initial EFI_I2C_DEVICE + structure pointer to NULL. The buffer + receives an EFI_I2C_DEVICE structure pointer + to the next I2C device. + + @retval EFI_SUCCESS The platform data for the next device on + the I2C bus was returned successfully. + @retval EFI_INVALID_PARAMETER Device is NULL + @retval EFI_NO_MAPPING *Device does not point to a valid + EFI_I2C_DEVICE structure returned in a + previous call Enumerate(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) ( + IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, + IN OUT CONST EFI_I2C_DEVICE **Device + ); + +/** + Get the requested I2C bus frequency for a specified bus configuration. + + This function returns the requested I2C bus clock frequency for the + I2cBusConfiguration. This routine is provided for diagnostic purposes + and is meant to be called after calling Enumerate to get the + I2cBusConfiguration value. + + @param[in] This Pointer to an EFI_I2C_ENUMERATE_PROTOCOL + structure. + @param[in] I2cBusConfiguration I2C bus configuration to access the I2C + device + @param[out] *BusClockHertz Pointer to a buffer to receive the I2C + bus clock frequency in Hertz + + @retval EFI_SUCCESS The I2C bus frequency was returned + successfully. + @retval EFI_INVALID_PARAMETER BusClockHertz was NULL + @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY) ( + IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + OUT UINTN *BusClockHertz + ); + +/// +/// I2C Enumerate protocol +/// +struct _EFI_I2C_ENUMERATE_PROTOCOL { + /// + /// Traverse the set of I2C devices on an I2C bus. This routine + /// returns the next I2C device on an I2C bus. + /// + EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate; + + /// + /// Get the requested I2C bus frequency for a specified bus + /// configuration. + /// + EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY GetBusFrequency; +}; + +/// +/// Reference to variable defined in the .DEC file +/// +extern EFI_GUID gEfiI2cEnumerateProtocolGuid; + +#endif // __I2C_ENUMERATE_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cHost.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cHost.h new file mode 100644 index 0000000000..27373a0784 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cHost.h @@ -0,0 +1,146 @@ +/** @file + I2C Host Protocol as defined in the PI 1.3 specification. + + This protocol provides callers with the ability to do I/O transactions + to all of the devices on the I2C bus. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.3. + +**/ + +#ifndef __I2C_HOST_H__ +#define __I2C_HOST_H__ + +#include + +#define EFI_I2C_HOST_PROTOCOL_GUID { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }} + +/// +/// I2C Host Protocol +/// +/// The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL +/// to produce an instance of the EFI_I2C_IO_PROTOCOL for each I2C +/// device on an I2C bus. +/// +/// The EFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to +/// callers to perform transactions to any device on the I2C bus. +/// Internally, the I2C host protocol manages the flow of the I2C +/// transactions to the host controller, keeping them in FIFO order. +/// Prior to each transaction, the I2C host protocol ensures that the +/// switches and multiplexers are properly configured. The I2C host +/// protocol then starts the transaction on the host controller using +/// the EFI_I2C_MASTER_PROTOCOL. +/// +typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL; + + +/** + Queue an I2C transaction for execution on the I2C controller. + + This routine must be called at or below TPL_NOTIFY. For + synchronous requests this routine must be called at or below + TPL_CALLBACK. + + The I2C host protocol uses the concept of I2C bus configurations + to describe the I2C bus. An I2C bus configuration is defined as + a unique setting of the multiplexers and switches in the I2C bus + which enable access to one or more I2C devices. When using a + switch to divide a bus, due to bus frequency differences, the + I2C bus configuration management protocol defines an I2C bus + configuration for the I2C devices on each side of the switch. + When using a multiplexer, the I2C bus configuration management + defines an I2C bus configuration for each of the selector values + required to control the multiplexer. See Figure 1 in the I2C -bus + specification and user manual for a complex I2C bus configuration. + + The I2C host protocol processes all transactions in FIFO order. + Prior to performing the transaction, the I2C host protocol calls + EnableI2cBusConfiguration to reconfigure the switches and + multiplexers in the I2C bus enabling access to the specified I2C + device. The EnableI2cBusConfiguration also selects the I2C bus + frequency for the I2C device. After the I2C bus is configured, + the I2C host protocol calls the I2C master protocol to start the + I2C transaction. + + When Event is NULL, QueueRequest() operates synchronously and + returns the I2C completion status as its return value. + + When Event is not NULL, QueueRequest() synchronously returns + EFI_SUCCESS indicating that the asynchronously I2C transaction was + queued. The values above are returned in the buffer pointed to by + I2cStatus upon the completion of the I2C transaction when I2cStatus + is not NULL. + + @param[in] This Pointer to an EFI_I2C_HOST_PROTOCOL structure. + @param[in] I2cBusConfiguration I2C bus configuration to access the I2C + device + @param[in] SlaveAddress Address of the device on the I2C bus. Set + the I2C_ADDRESSING_10_BIT when using 10-bit + addresses, clear this bit for 7-bit addressing. + Bits 0-6 are used for 7-bit I2C slave addresses + and bits 0-9 are used for 10-bit I2C slave + addresses. + @param[in] Event Event to signal for asynchronous transactions, + NULL for synchronous transactions + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure + describing the I2C transaction + @param[out] I2cStatus Optional buffer to receive the I2C transaction + completion status + + @retval EFI_SUCCESS The asynchronous transaction was successfully + queued when Event is not NULL. + @retval EFI_SUCCESS The transaction completed successfully when + Event is NULL. + @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is + too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the + transaction. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter + @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value + @retval EFI_NO_RESPONSE The I2C device is not responding to the slave + address. EFI_DEVICE_ERROR will be returned + if the controller cannot distinguish when the + NACK occurred. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction + @retval EFI_UNSUPPORTED The controller does not support the requested + transaction. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST) ( + IN CONST EFI_I2C_HOST_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + IN UINTN SlaveAddress, + IN EFI_EVENT Event OPTIONAL, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// I2C Host Protocol +/// +struct _EFI_I2C_HOST_PROTOCOL { + /// + /// Queue an I2C transaction for execution on the I2C bus + /// + EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest; + + /// + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure + /// containing the capabilities of the I2C host controller. + /// + CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities; +}; + +/// +/// Reference to variable defined in the .DEC file +/// +extern EFI_GUID gEfiI2cHostProtocolGuid; + +#endif // __I2C_HOST_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cIo.h new file mode 100644 index 0000000000..282308ecd4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cIo.h @@ -0,0 +1,166 @@ +/** @file + I2C I/O Protocol as defined in the PI 1.3 specification. + + The EFI I2C I/O protocol enables the user to manipulate a single + I2C device independent of the host controller and I2C design. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.3. + +**/ + +#ifndef __I2C_IO_H__ +#define __I2C_IO_H__ + +#include + +#define EFI_I2C_IO_PROTOCOL_GUID { 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, 0x06, 0x65, 0xa2, 0x8e }} + +/// +/// I2C I/O protocol +/// +/// The I2C IO protocol enables access to a specific device on the I2C +/// bus. +/// +/// Each I2C device is identified uniquely in the system by the tuple +/// DeviceGuid:DeviceIndex. The DeviceGuid represents the manufacture +/// and part number and is provided by the silicon vendor or the third +/// party I2C device driver writer. The DeviceIndex identifies the part +/// within the system by using a unique number and is created by the +/// board designer or the writer of the EFI_I2C_ENUMERATE_PROTOCOL. +/// +/// I2C slave addressing is abstracted to validate addresses and limit +/// operation to the specified I2C device. The third party providing +/// the I2C device support provides an ordered list of slave addresses +/// for the I2C device required to implement the EFI_I2C_ENUMERATE_PROTOCOL. +/// The order of the list must be preserved. +/// +typedef struct _EFI_I2C_IO_PROTOCOL EFI_I2C_IO_PROTOCOL; + + +/** + Queue an I2C transaction for execution on the I2C device. + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + This routine queues an I2C transaction to the I2C controller for + execution on the I2C bus. + + When Event is NULL, QueueRequest() operates synchronously and returns + the I2C completion status as its return value. + + When Event is not NULL, QueueRequest() synchronously returns EFI_SUCCESS + indicating that the asynchronous I2C transaction was queued. The values + above are returned in the buffer pointed to by I2cStatus upon the + completion of the I2C transaction when I2cStatus is not NULL. + + The upper layer driver writer provides the following to the platform + vendor: + + 1. Vendor specific GUID for the I2C part + 2. Guidance on proper construction of the slave address array when the + I2C device uses more than one slave address. The I2C bus protocol + uses the SlaveAddressIndex to perform relative to physical address + translation to access the blocks of hardware within the I2C device. + + @param[in] This Pointer to an EFI_I2C_IO_PROTOCOL structure. + @param[in] SlaveAddressIndex Index value into an array of slave addresses + for the I2C device. The values in the array + are specified by the board designer, with the + third party I2C device driver writer providing + the slave address order. + + For devices that have a single slave address, + this value must be zero. If the I2C device + uses more than one slave address then the + third party (upper level) I2C driver writer + needs to specify the order of entries in the + slave address array. + + \ref ThirdPartyI2cDrivers "Third Party I2C + Drivers" section in I2cMaster.h. + @param[in] Event Event to signal for asynchronous transactions, + NULL for synchronous transactions + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure + describing the I2C transaction + @param[out] I2cStatus Optional buffer to receive the I2C transaction + completion status + + @retval EFI_SUCCESS The asynchronous transaction was successfully + queued when Event is not NULL. + @retval EFI_SUCCESS The transaction completed successfully when + Event is NULL. + @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too + large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the + transaction. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL. + @retval EFI_NO_MAPPING The EFI_I2C_HOST_PROTOCOL could not set the + bus configuration required to access this I2C + device. + @retval EFI_NO_RESPONSE The I2C device is not responding to the slave + address selected by SlaveAddressIndex. + EFI_DEVICE_ERROR will be returned if the + controller cannot distinguish when the NACK + occurred. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction + @retval EFI_UNSUPPORTED The controller does not support the requested + transaction. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST) ( + IN CONST EFI_I2C_IO_PROTOCOL *This, + IN UINTN SlaveAddressIndex, + IN EFI_EVENT Event OPTIONAL, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// I2C I/O protocol +/// +struct _EFI_I2C_IO_PROTOCOL { + /// + /// Queue an I2C transaction for execution on the I2C device. + /// + EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST QueueRequest; + + /// + /// Unique value assigned by the silicon manufacture or the third + /// party I2C driver writer for the I2C part. This value logically + /// combines both the manufacture name and the I2C part number into + /// a single value specified as a GUID. + /// + CONST EFI_GUID *DeviceGuid; + + /// + /// Unique ID of the I2C part within the system + /// + UINT32 DeviceIndex; + + /// + /// Hardware revision - ACPI _HRV value. See the Advanced Configuration + /// and Power Interface Specification, Revision 5.0 for the field format + /// and the Plug and play support for I2C web-page for restriction on values. + /// + UINT32 HardwareRevision; + + /// + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing + /// the capabilities of the I2C host controller. + /// + CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities; +}; + +/// +/// Reference to variable defined in the .DEC file +/// +extern EFI_GUID gEfiI2cIoProtocolGuid; + +#endif // __I2C_IO_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cMaster.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cMaster.h new file mode 100644 index 0000000000..e3053ffa75 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/I2cMaster.h @@ -0,0 +1,186 @@ +/** @file + I2C Master Protocol as defined in the PI 1.3 specification. + + This protocol manipulates the I2C host controller to perform transactions as a master + on the I2C bus using the current state of any switches or multiplexers in the I2C bus. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.3. + +**/ + +#ifndef __I2C_MASTER_H__ +#define __I2C_MASTER_H__ + +#include + +#define EFI_I2C_MASTER_PROTOCOL_GUID { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }} + +typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL; + +/** + Set the frequency for the I2C clock line. + + This routine must be called at or below TPL_NOTIFY. + + The software and controller do a best case effort of using the specified + frequency for the I2C bus. If the frequency does not match exactly then + the I2C master protocol selects the next lower frequency to avoid + exceeding the operating conditions for any of the I2C devices on the bus. + For example if 400 KHz was specified and the controller's divide network + only supports 402 KHz or 398 KHz then the I2C master protocol selects 398 + KHz. If there are not lower frequencies available, then return + EFI_UNSUPPORTED. + + @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure + @param[in] BusClockHertz Pointer to the requested I2C bus clock frequency + in Hertz. Upon return this value contains the + actual frequency in use by the I2C controller. + + @retval EFI_SUCCESS The bus frequency was set successfully. + @retval EFI_ALREADY_STARTED The controller is busy with another transaction. + @retval EFI_INVALID_PARAMETER BusClockHertz is NULL + @retval EFI_UNSUPPORTED The controller does not support this frequency. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN OUT UINTN *BusClockHertz + ); + +/** + Reset the I2C controller and configure it for use + + This routine must be called at or below TPL_NOTIFY. + + The I2C controller is reset. The caller must call SetBusFrequench() after + calling Reset(). + + @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure. + + @retval EFI_SUCCESS The reset completed successfully. + @retval EFI_ALREADY_STARTED The controller is busy with another transaction. + @retval EFI_DEVICE_ERROR The reset operation failed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ); + +/** + Start an I2C transaction on the host controller. + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + This function initiates an I2C transaction on the controller. To + enable proper error handling by the I2C protocol stack, the I2C + master protocol does not support queuing but instead only manages + one I2C transaction at a time. This API requires that the I2C bus + is in the correct configuration for the I2C transaction. + + The transaction is performed by sending a start-bit and selecting the + I2C device with the specified I2C slave address and then performing + the specified I2C operations. When multiple operations are requested + they are separated with a repeated start bit and the slave address. + The transaction is terminated with a stop bit. + + When Event is NULL, StartRequest operates synchronously and returns + the I2C completion status as its return value. + + When Event is not NULL, StartRequest synchronously returns EFI_SUCCESS + indicating that the I2C transaction was started asynchronously. The + transaction status value is returned in the buffer pointed to by + I2cStatus upon the completion of the I2C transaction when I2cStatus + is not NULL. After the transaction status is returned the Event is + signaled. + + Note: The typical consumer of this API is the I2C host protocol. + Extreme care must be taken by other consumers of this API to prevent + confusing the third party I2C drivers due to a state change at the + I2C device which the third party I2C drivers did not initiate. I2C + platform specific code may use this API within these guidelines. + + @param[in] This Pointer to an EFI_I2C_MASTER_PROTOCOL structure. + @param[in] SlaveAddress Address of the device on the I2C bus. Set the + I2C_ADDRESSING_10_BIT when using 10-bit addresses, + clear this bit for 7-bit addressing. Bits 0-6 + are used for 7-bit I2C slave addresses and bits + 0-9 are used for 10-bit I2C slave addresses. + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET + structure describing the I2C transaction. + @param[in] Event Event to signal for asynchronous transactions, + NULL for asynchronous transactions + @param[out] I2cStatus Optional buffer to receive the I2C transaction + completion status + + @retval EFI_SUCCESS The asynchronous transaction was successfully + started when Event is not NULL. + @retval EFI_SUCCESS The transaction completed successfully when + Event is NULL. + @retval EFI_ALREADY_STARTED The controller is busy with another transaction. + @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too + large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the + transaction. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter + @retval EFI_NO_RESPONSE The I2C device is not responding to the slave + address. EFI_DEVICE_ERROR will be returned if + the controller cannot distinguish when the NACK + occurred. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction + @retval EFI_UNSUPPORTED The controller does not support the requested + transaction. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST) ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + IN EFI_EVENT Event OPTIONAL, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// I2C master mode protocol +/// +/// This protocol manipulates the I2C host controller to perform transactions as a +/// master on the I2C bus using the current state of any switches or multiplexers +/// in the I2C bus. +/// +struct _EFI_I2C_MASTER_PROTOCOL { + /// + /// Set the clock frequency for the I2C bus. + /// + EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency; + + /// + /// Reset the I2C host controller. + /// + EFI_I2C_MASTER_PROTOCOL_RESET Reset; + + /// + /// Start an I2C transaction in master mode on the host controller. + /// + EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest; + + /// + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing + /// the capabilities of the I2C host controller. + /// + CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities; +}; + +extern EFI_GUID gEfiI2cMasterProtocolGuid; + +#endif // __I2C_MASTER_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IScsiInitiatorName.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IScsiInitiatorName.h new file mode 100644 index 0000000000..d8f9e885a2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IScsiInitiatorName.h @@ -0,0 +1,81 @@ +/** @file + EFI_ISCSI_INITIATOR_NAME_PROTOCOL as defined in UEFI 2.0. + It provides the ability to get and set the iSCSI Initiator Name. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ISCSI_INITIATOR_NAME_H__ +#define __ISCSI_INITIATOR_NAME_H__ + +#define EFI_ISCSI_INITIATOR_NAME_PROTOCOL_GUID \ +{ \ + 0x59324945, 0xec44, 0x4c0d, {0xb1, 0xcd, 0x9d, 0xb1, 0x39, 0xdf, 0x7, 0xc } \ +} + +typedef struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL EFI_ISCSI_INITIATOR_NAME_PROTOCOL; + +/** + Retrieves the current set value of iSCSI Initiator Name. + + @param This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance. + @param BufferSize Size of the buffer in bytes pointed to by Buffer / Actual size of the + variable data buffer. + @param Buffer Pointer to the buffer for data to be read. The data is a null-terminated UTF-8 encoded string. + The maximum length is 223 characters, including the null-terminator. + + @retval EFI_SUCCESS Data was successfully retrieved into the provided buffer and the + BufferSize was sufficient to handle the iSCSI initiator name + @retval EFI_BUFFER_TOO_SMALL BufferSize is too small for the result. + @retval EFI_INVALID_PARAMETER BufferSize or Buffer is NULL. + @retval EFI_DEVICE_ERROR The iSCSI initiator name could not be retrieved due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ISCSI_INITIATOR_NAME_GET)( + IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + + + +/** + Sets the iSCSI Initiator Name. + + @param This Pointer to the EFI_ISCSI_INITIATOR_NAME_PROTOCOL instance. + @param BufferSize Size of the buffer in bytes pointed to by Buffer. + @param Buffer Pointer to the buffer for data to be written. The data is a null-terminated UTF-8 encoded string. + The maximum length is 223 characters, including the null-terminator. + + @retval EFI_SUCCESS Data was successfully stored by the protocol. + @retval EFI_UNSUPPORTED Platform policies do not allow for data to be written. + @retval EFI_INVALID_PARAMETER BufferSize or Buffer is NULL, or BufferSize exceeds the maximum allowed limit. + @retval EFI_DEVICE_ERROR The data could not be stored due to a hardware error. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data. + @retval EFI_PROTOCOL_ERROR Input iSCSI initiator name does not adhere to RFC 3720 + (and other related protocols) + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_ISCSI_INITIATOR_NAME_SET)( + IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/// +/// iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name. +/// +struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL { + EFI_ISCSI_INITIATOR_NAME_GET Get; + EFI_ISCSI_INITIATOR_NAME_SET Set; +}; + +extern EFI_GUID gEfiIScsiInitiatorNameProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IdeControllerInit.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IdeControllerInit.h new file mode 100644 index 0000000000..9b5b789450 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IdeControllerInit.h @@ -0,0 +1,559 @@ +/** @file + This file declares EFI IDE Controller Init Protocol + + The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information + to the driver entity. This protocol is mandatory for IDE controllers if the + IDE devices behind the controller are to be enumerated by a driver entity. + + There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE + controller in a system. It is installed on the handle that corresponds to the + IDE controller. A driver entity that wishes to manage an IDE bus and possibly + IDE devices in a system will have to retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL + instance that is associated with the controller to be managed. + + A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards. + +**/ + +#ifndef _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_ +#define _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_ + +#include + +/// +/// Global ID for the EFI_IDE_CONTROLLER_INIT_PROTOCOL. +/// +#define EFI_IDE_CONTROLLER_INIT_PROTOCOL_GUID \ + { \ + 0xa1e37052, 0x80d9, 0x4e65, {0xa3, 0x17, 0x3e, 0x9a, 0x55, 0xc4, 0x3e, 0xc9 } \ + } + +/// +/// Forward declaration for EFI_IDE_CONTROLLER_INIT_PROTOCOL. +/// +typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL; + +/// +/// The phase of the IDE Controller enumeration. +/// +typedef enum { + /// + /// The driver entity is about to begin enumerating the devices + /// behind the specified channel. This notification can be used to + /// perform any chipset-specific programming. + /// + EfiIdeBeforeChannelEnumeration, + /// + /// The driver entity has completed enumerating the devices + /// behind the specified channel. This notification can be used to + /// perform any chipset-specific programming. + /// + EfiIdeAfterChannelEnumeration, + /// + /// The driver entity is about to reset the devices behind the + /// specified channel. This notification can be used to perform any + /// chipset-specific programming. + /// + EfiIdeBeforeChannelReset, + /// + /// The driver entity has completed resetting the devices behind + /// the specified channel. This notification can be used to perform + /// any chipset-specific programming. + /// + EfiIdeAfterChannelReset, + /// + /// The driver entity is about to detect the presence of devices + /// behind the specified channel. This notification can be used to + /// set up the bus signals to default levels or for implementing + /// predelays. + /// + EfiIdeBusBeforeDevicePresenceDetection, + /// + /// The driver entity is done with detecting the presence of + /// devices behind the specified channel. This notification can be + /// used to perform any chipset-specific programming. + /// + EfiIdeBusAfterDevicePresenceDetection, + /// + /// The IDE bus is requesting the IDE controller driver to + /// reprogram the IDE controller hardware and thereby reset all + /// the mode and timing settings to default settings. + /// + EfiIdeResetMode, + EfiIdeBusPhaseMaximum +} EFI_IDE_CONTROLLER_ENUM_PHASE; + +/// +/// This extended mode describes the SATA physical protocol. +/// SATA physical layers can operate at different speeds. +/// These speeds are defined below. Various PATA protocols +/// and associated modes are not applicable to SATA devices. +/// +typedef enum { + EfiAtaSataTransferProtocol +} EFI_ATA_EXT_TRANSFER_PROTOCOL; + +/// +/// Automatically detects the optimum SATA speed. +/// +#define EFI_SATA_AUTO_SPEED 0 + +/// +/// Indicates a first-generation (Gen1) SATA speed. +/// +#define EFI_SATA_GEN1_SPEED 1 + +/// +/// Indicates a second-generation (Gen2) SATA speed. +/// +#define EFI_SATA_GEN2_SPEED 2 + +/// +/// EFI_ATA_MODE structure. +/// +typedef struct { + BOOLEAN Valid; ///< TRUE if Mode is valid. + UINT32 Mode; ///< The actual ATA mode. This field is not a bit map. +} EFI_ATA_MODE; + +/// +/// EFI_ATA_EXTENDED_MODE structure +/// +typedef struct { + /// + /// An enumeration defining various transfer protocols other than the protocols + /// that exist at the time this specification was developed (i.e., PIO, single + /// word DMA, multiword DMA, and UDMA). Each transfer protocol is associated + /// with a mode. The various transfer protocols are defined by the ATA/ATAPI + /// specification. This enumeration makes the interface extensible because we + /// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL + /// is defined below. + /// + EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol; + /// + /// The mode for operating the transfer protocol that is identified by TransferProtocol. + /// + UINT32 Mode; +} EFI_ATA_EXTENDED_MODE; + +/// +/// EFI_ATA_COLLECTIVE_MODE structure. +/// +typedef struct { + /// + /// This field specifies the PIO mode. PIO modes are defined in the ATA/ATAPI + /// specification. The ATA/ATAPI specification defines the enumeration. In + /// other words, a value of 1 in this field means PIO mode 1. The actual meaning + /// of PIO mode 1 is governed by the ATA/ATAPI specification. Type EFI_ATA_MODE + /// is defined below. + /// + EFI_ATA_MODE PioMode; + /// + /// This field specifies the single word DMA mode. Single word DMA modes are defined + /// in the ATA/ATAPI specification, versions 1 and 2. Single word DMA support was + /// obsoleted in the ATA/ATAPI specification, version 3. Therefore, most devices and + /// controllers will not support this transfer mode. The ATA/ATAPI specification defines + /// the enumeration. In other words, a value of 1 in this field means single word DMA + /// mode 1. The actual meaning of single word DMA mode 1 is governed by the ATA/ + /// ATAPI specification. + /// + EFI_ATA_MODE SingleWordDmaMode; + /// + /// This field specifies the multiword DMA mode. Various multiword DMA modes are + /// defined in the ATA/ATAPI specification. A value of 1 in this field means multiword + /// DMA mode 1. The actual meaning of multiword DMA mode 1 is governed by the + /// ATA/ATAPI specification. + /// + EFI_ATA_MODE MultiWordDmaMode; + /// + /// This field specifies the ultra DMA (UDMA) mode. UDMA modes are defined in the + /// ATA/ATAPI specification. A value of 1 in this field means UDMA mode 1. The + /// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification. + /// + EFI_ATA_MODE UdmaMode; + /// + /// The number of extended-mode bitmap entries. Extended modes describe transfer + /// protocols beyond PIO, single word DMA, multiword DMA, and UDMA. This field + /// can be zero and provides extensibility. + /// + UINT32 ExtModeCount; + /// + /// ExtModeCount number of entries. Each entry represents a transfer protocol other + /// than the ones defined above (i.e., PIO, single word DMA, multiword DMA, and + /// UDMA). This field is defined for extensibility. At this time, only one extended + /// transfer protocol is defined to cover SATA transfers. Type + /// EFI_ATA_EXTENDED_MODE is defined below. + /// + EFI_ATA_EXTENDED_MODE ExtMode[1]; +} EFI_ATA_COLLECTIVE_MODE; + +/// +/// EFI_ATA_IDENTIFY_DATA & EFI_ATAPI_IDENTIFY_DATA structure +/// +/// The definition of these two structures is not part of the protocol +/// definition because the ATA/ATAPI Specification controls the definition +/// of all the fields. The ATA/ATAPI Specification can obsolete old fields +/// or redefine existing fields. +typedef ATA_IDENTIFY_DATA EFI_ATA_IDENTIFY_DATA; +typedef ATAPI_IDENTIFY_DATA EFI_ATAPI_IDENTIFY_DATA; + +/// +/// This flag indicates whether the IDENTIFY data is a response from an ATA device +/// (EFI_ATA_IDENTIFY_DATA) or response from an ATAPI device +/// (EFI_ATAPI_IDENTIFY_DATA). According to the ATA/ATAPI specification, +/// EFI_IDENTIFY_DATA is for an ATA device if bit 15 of the Config field is zero. +/// The Config field is common to both EFI_ATA_IDENTIFY_DATA and +/// EFI_ATAPI_IDENTIFY_DATA. +/// +#define EFI_ATAPI_DEVICE_IDENTIFY_DATA 0x8000 + +/// +/// EFI_IDENTIFY_DATA structure. +/// +typedef union { + /// + /// The data that is returned by an ATA device upon successful completion + /// of the ATA IDENTIFY_DEVICE command. + /// + EFI_ATA_IDENTIFY_DATA AtaData; + /// + /// The data that is returned by an ATAPI device upon successful completion + /// of the ATA IDENTIFY_PACKET_DEVICE command. + /// + EFI_ATAPI_IDENTIFY_DATA AtapiData; +} EFI_IDENTIFY_DATA; + +/** + Returns the information about the specified IDE channel. + + This function can be used to obtain information about a particular IDE channel. + The driver entity uses this information during the enumeration process. + + If Enabled is set to FALSE, the driver entity will not scan the channel. Note + that it will not prevent an operating system driver from scanning the channel. + + For most of today's controllers, MaxDevices will either be 1 or 2. For SATA + controllers, this value will always be 1. SATA configurations can contain SATA + port multipliers. SATA port multipliers behave like SATA bridges and can support + up to 16 devices on the other side. If a SATA port out of the IDE controller + is connected to a port multiplier, MaxDevices will be set to the number of SATA + devices that the port multiplier supports. Because today's port multipliers + support up to fifteen SATA devices, this number can be as large as fifteen. The IDE + bus driver is required to scan for the presence of port multipliers behind an SATA + controller and enumerate up to MaxDevices number of devices behind the port + multiplier. + + In this context, the devices behind a port multiplier constitute a channel. + + @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Channel Zero-based channel number. + @param[out] Enabled TRUE if this channel is enabled. Disabled channels + are not scanned to see if any devices are present. + @param[out] MaxDevices The maximum number of IDE devices that the bus driver + can expect on this channel. For the ATA/ATAPI + specification, version 6, this number will either be + one or two. For Serial ATA (SATA) configurations with a + port multiplier, this number can be as large as fifteen. + + @retval EFI_SUCCESS Information was returned without any errors. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_GET_CHANNEL_INFO)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN UINT8 Channel, + OUT BOOLEAN *Enabled, + OUT UINT8 *MaxDevices + ); + +/** + The notifications from the driver entity that it is about to enter a certain + phase of the IDE channel enumeration process. + + This function can be used to notify the IDE controller driver to perform + specific actions, including any chipset-specific initialization, so that the + chipset is ready to enter the next phase. Seven notification points are defined + at this time. + + More synchronization points may be added as required in the future. + + @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Phase The phase during enumeration. + @param[in] Channel Zero-based channel number. + + @retval EFI_SUCCESS The notification was accepted without any errors. + @retval EFI_UNSUPPORTED Phase is not supported. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + @retval EFI_NOT_READY This phase cannot be entered at this time; for + example, an attempt was made to enter a Phase + without having entered one or more previous + Phase. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_NOTIFY_PHASE)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase, + IN UINT8 Channel + ); + +/** + Submits the device information to the IDE controller driver. + + This function is used by the driver entity to pass detailed information about + a particular device to the IDE controller driver. The driver entity obtains + this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData + is the pointer to the response data buffer. The IdentifyData buffer is owned + by the driver entity, and the IDE controller driver must make a local copy + of the entire buffer or parts of the buffer as needed. The original IdentifyData + buffer pointer may not be valid when + + - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or + - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point. + + The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to + compute the optimum mode for the device. These fields are not limited to the + timing information. For example, an implementation of the IDE controller driver + may examine the vendor and type/mode field to match known bad drives. + + The driver entity may submit drive information in any order, as long as it + submits information for all the devices belonging to the enumeration group + before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device + in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() + should be called with IdentifyData set to NULL. The IDE controller driver may + not have any other mechanism to know whether a device is present or not. Therefore, + setting IdentifyData to NULL does not constitute an error condition. + EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a + given (Channel, Device) pair. + + @param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Channel Zero-based channel number. + @param[in] Device Zero-based device number on the Channel. + @param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command. + + @retval EFI_SUCCESS The information was accepted without any errors. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + @retval EFI_INVALID_PARAMETER Device is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_SUBMIT_DATA)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN UINT8 Channel, + IN UINT8 Device, + IN EFI_IDENTIFY_DATA *IdentifyData + ); + +/** + Disqualifies specific modes for an IDE device. + + This function allows the driver entity or other drivers (such as platform + drivers) to reject certain timing modes and request the IDE controller driver + to recalculate modes. This function allows the driver entity and the IDE + controller driver to negotiate the timings on a per-device basis. This function + is useful in the case of drives that lie about their capabilities. An example + is when the IDE device fails to accept the timing modes that are calculated + by the IDE controller driver based on the response to the Identify Drive command. + + If the driver entity does not want to limit the ATA timing modes and leave that + decision to the IDE controller driver, it can either not call this function for + the given device or call this function and set the Valid flag to FALSE for all + modes that are listed in EFI_ATA_COLLECTIVE_MODE. + + The driver entity may disqualify modes for a device in any order and any number + of times. + + This function can be called multiple times to invalidate multiple modes of the + same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI + specification for more information on PIO modes. + + For Serial ATA (SATA) controllers, this member function can be used to disqualify + a higher transfer rate mode on a given channel. For example, a platform driver + may inform the IDE controller driver to not use second-generation (Gen2) speeds + for a certain SATA drive. + + @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Channel The zero-based channel number. + @param[in] Device The zero-based device number on the Channel. + @param[in] BadModes The modes that the device does not support and that + should be disqualified. + + @retval EFI_SUCCESS The modes were accepted without any errors. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + @retval EFI_INVALID_PARAMETER Device is invalid. + @retval EFI_INVALID_PARAMETER IdentifyData is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_DISQUALIFY_MODE)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN UINT8 Channel, + IN UINT8 Device, + IN EFI_ATA_COLLECTIVE_MODE *BadModes + ); + +/** + Returns the information about the optimum modes for the specified IDE device. + + This function is used by the driver entity to obtain the optimum ATA modes for + a specific device. The IDE controller driver takes into account the following + while calculating the mode: + - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() + - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() + + The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() + for all the devices that belong to an enumeration group before calling + EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group. + + The IDE controller driver will use controller- and possibly platform-specific + algorithms to arrive at SupportedModes. The IDE controller may base its + decision on user preferences and other considerations as well. This function + may be called multiple times because the driver entity may renegotiate the mode + with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode(). + + The driver entity may collect timing information for various devices in any + order. The driver entity is responsible for making sure that all the dependencies + are satisfied. For example, the SupportedModes information for device A that + was previously returned may become stale after a call to + EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B. + + The buffer SupportedModes is allocated by the callee because the caller does + not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE + is defined in a way that allows for future extensibility and can be of variable + length. This memory pool should be deallocated by the caller when it is no + longer necessary. + + The IDE controller driver for a Serial ATA (SATA) controller can use this + member function to force a lower speed (first-generation [Gen1] speeds on a + second-generation [Gen2]-capable hardware). The IDE controller driver can + also allow the driver entity to stay with the speed that has been negotiated + by the physical layer. + + @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Channel A zero-based channel number. + @param[in] Device A zero-based device number on the Channel. + @param[out] SupportedModes The optimum modes for the device. + + @retval EFI_SUCCESS SupportedModes was returned. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + @retval EFI_INVALID_PARAMETER Device is invalid. + @retval EFI_INVALID_PARAMETER SupportedModes is NULL. + @retval EFI_NOT_READY Modes cannot be calculated due to a lack of + data. This error may happen if + EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() + and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData() + were not called for at least one drive in the + same enumeration group. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_CALCULATE_MODE)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN UINT8 Channel, + IN UINT8 Device, + OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes + ); + +/** + Commands the IDE controller driver to program the IDE controller hardware + so that the specified device can operate at the specified mode. + + This function is used by the driver entity to instruct the IDE controller + driver to program the IDE controller hardware to the specified modes. This + function can be called only once for a particular device. For a Serial ATA + (SATA) Advanced Host Controller Interface (AHCI) controller, no controller- + specific programming may be required. + + @param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. + @param[in] Channel Zero-based channel number. + @param[in] Device Zero-based device number on the Channel. + @param[in] Modes The modes to set. + + @retval EFI_SUCCESS The command was accepted without any errors. + @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). + @retval EFI_INVALID_PARAMETER Device is invalid. + @retval EFI_NOT_READY Modes cannot be set at this time due to lack of data. + @retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure. + The driver entity should not use this device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IDE_CONTROLLER_SET_TIMING)( + IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This, + IN UINT8 Channel, + IN UINT8 Device, + IN EFI_ATA_COLLECTIVE_MODE *Modes + ); + +/// +/// Provides the basic interfaces to abstract an IDE controller. +/// +struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL { + /// + /// Returns the information about a specific channel. + /// + EFI_IDE_CONTROLLER_GET_CHANNEL_INFO GetChannelInfo; + + /// + /// The notification that the driver entity is about to enter the + /// specified phase during the enumeration process. + /// + EFI_IDE_CONTROLLER_NOTIFY_PHASE NotifyPhase; + + /// + /// Submits the Drive Identify data that was returned by the device. + /// + EFI_IDE_CONTROLLER_SUBMIT_DATA SubmitData; + + /// + /// Submits information about modes that should be disqualified. The specified + /// IDE device does not support these modes and these modes should not be + /// returned by EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() + /// + EFI_IDE_CONTROLLER_DISQUALIFY_MODE DisqualifyMode; + + /// + /// Calculates and returns the optimum mode for a particular IDE device. + /// + EFI_IDE_CONTROLLER_CALCULATE_MODE CalculateMode; + + /// + /// Programs the IDE controller hardware to the default timing or per the modes + /// that were returned by the last call to EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode(). + /// + EFI_IDE_CONTROLLER_SET_TIMING SetTiming; + + /// + /// Set to TRUE if the enumeration group includes all the channels that are + /// produced by this controller. Set to FALSE if an enumeration group consists of + /// only one channel. + /// + BOOLEAN EnumAll; + + /// + /// The number of channels that are produced by this controller. Parallel ATA + /// (PATA) controllers can support up to two channels. Advanced Host Controller + /// Interface (AHCI) Serial ATA (SATA) controllers can support up to 32 channels, + /// each of which can have up to one device. In the presence of a multiplier, + /// each channel can have fifteen devices. + /// + UINT8 ChannelCount; +}; + +extern EFI_GUID gEfiIdeControllerInitProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h new file mode 100644 index 0000000000..d963cb43f4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h @@ -0,0 +1,167 @@ +/** @file + This file declares Incompatible PCI Device Support Protocol + + Allows the PCI bus driver to support resource allocation for some PCI devices + that do not comply with the PCI Specification. + + @par Note: + This protocol is optional. Only those platforms that implement this protocol + will have the capability to support incompatible PCI devices. The absence of + this protocol can cause the PCI bus driver to configure these incompatible + PCI devices incorrectly. As a result, these devices may not work properly. + + The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver + to support resource allocation for some PCI devices that do not comply with the + PCI Specification. This protocol can find some incompatible PCI devices and + report their special resource requirements to the PCI bus driver. The generic + PCI bus driver does not have prior knowledge of any incompatible PCI devices. + It interfaces with the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out + if a device is incompatible and to obtain the special configuration requirements + for a specific incompatible PCI device. + + This protocol is optional, and only one instance of this protocol can be present + in the system. If a platform supports this protocol, this protocol is produced + by a Driver Execution Environment (DXE) driver and must be made available before + the Boot Device Selection (BDS) phase. The PCI bus driver will look for the + presence of this protocol before it begins PCI enumeration. If this protocol + exists in a platform, it indicates that the platform has the capability to support + those incompatible PCI devices. However, final support for incompatible PCI + devices still depends on the implementation of the PCI bus driver. The PCI bus + driver may fully, partially, or not even support these incompatible devices. + + During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address + Registers (BARs) for each PCI device regardless of whether the PCI device is + incompatible or not to determine the resource requirements so that the PCI bus + driver can invoke the proper PCI resources for them. Generally, this resource + information includes the following: + - Resource type + - Resource length + - Alignment + + However, some incompatible PCI devices may have special requirements. As a result, + the length or the alignment that is derived through BAR probing may not be exactly + the same as the actual resource requirement of the device. For example, there + are some devices that request I/O resources at a length of 0x100 from their I/O + BAR, but these incompatible devices will never work correctly if an odd I/O base + address, such as 0x100, 0x300, or 0x500, is assigned to the BAR. Instead, these + devices request an even base address, such as 0x200 or 0x400. The Incompatible + PCI Device Support Protocol can then be used to obtain these special resource + requirements for these incompatible PCI devices. In this way, the PCI bus driver + will take special consideration for these devices during PCI resource allocation + to ensure that they can work correctly. + + This protocol may support the following incompatible PCI BAR types: + - I/O or memory length that is different from what the BAR reports + - I/O or memory alignment that is different from what the BAR reports + - Fixed I/O or memory base address + + See the Conventional PCI Specification 3.0 for the details of how a PCI BAR + reports the resource length and the alignment that it requires. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_ +#define _INCOMPATIBLE_PCI_DEVICE_SUPPORT_H_ + +/// +/// Global ID for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL +/// +#define EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL_GUID \ + { \ + 0xeb23f55a, 0x7863, 0x4ac2, {0x8d, 0x3d, 0x95, 0x65, 0x35, 0xde, 0x03, 0x75} \ + } + +/// +/// Forward declaration for EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL +/// +typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL; + +/** + Returns a list of ACPI resource descriptors that detail the special resource + configuration requirements for an incompatible PCI device. + + This function returns a list of ACPI resource descriptors that detail the + special resource configuration requirements for an incompatible PCI device. + + Prior to bus enumeration, the PCI bus driver will look for the presence + of the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this + protocol can be present in the system. For each PCI device that the PCI bus + driver discovers, the PCI bus driver calls this function with the device's vendor + ID, device ID, revision ID, subsystem vendor ID, and subsystem device ID. If the + VendorId, DeviceId, RevisionId, SubsystemVendorId, or SubsystemDeviceId value is + set to (UINTN)-1, that field will be ignored. The ID values that are not (UINTN)-1 + will be used to identify the current device. + + This function will only return EFI_SUCCESS. However, if the device is an + incompatible PCI device, a list of ACPI resource descriptors will be returned + in Configuration. Otherwise, NULL will be returned in Configuration instead. + The PCI bus driver does not need to allocate memory for Configuration. However, + it is the PCI bus driver's responsibility to free it. The PCI bus driver then + can configure this device with the information that is derived from this list + of resource nodes, rather than the result of BAR probing. + + Only the following two resource descriptor types from the ACPI Specification + may be used to describe the incompatible PCI device resource requirements: + - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0) + - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0) + + The QWORD Address Space Descriptor can describe memory, I/O, and bus number + ranges for dynamic or fixed resources. The configuration of a PCI root bridge + is described with one or more QWORD Address Space Descriptors, followed by an + End Tag. See the ACPI Specification for details on the field values. + + @param[in] This Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL + instance. + @param[in] VendorId A unique ID to identify the manufacturer of + the PCI device. See the Conventional PCI + Specification 3.0 for details. + @param[in] DeviceId A unique ID to identify the particular PCI + device. See the Conventional PCI Specification + 3.0 for details. + @param[in] RevisionId A PCI device-specific revision identifier. + See the Conventional PCI Specification 3.0 + for details. + @param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the + Conventional PCI Specification 3.0 for details. + @param[in] SubsystemDeviceId Specifies the subsystem device ID. See the + Conventional PCI Specification 3.0 for details. + @param[out] Configuration A list of ACPI resource descriptors that detail + the configuration requirement. + + @retval EFI_SUCCESS The function always returns EFI_SUCCESS. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE)( + IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This, + IN UINTN VendorId, + IN UINTN DeviceId, + IN UINTN RevisionId, + IN UINTN SubsystemVendorId, + IN UINTN SubsystemDeviceId, + OUT VOID **Configuration + ); + +/// +/// Interface structure for the Incompatible PCI Device Support Protocol +/// +struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL { + /// + /// Returns a list of ACPI resource descriptors that detail any special + /// resource configuration requirements if the specified device is a recognized + /// incompatible PCI device. + /// + EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice; +}; + +extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4.h new file mode 100644 index 0000000000..519c80d629 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4.h @@ -0,0 +1,606 @@ +/** @file + This file defines the EFI IPv4 (Internet Protocol version 4) + Protocol interface. It is split into the following three main + sections: + - EFI IPv4 Service Binding Protocol + - EFI IPv4 Variable (deprecated in UEFI 2.4B) + - EFI IPv4 Protocol. + The EFI IPv4 Protocol provides basic network IPv4 packet I/O services, + which includes support foR a subset of the Internet Control Message + Protocol (ICMP) and may include support for the Internet Group Management + Protocol (IGMP). + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0. + +**/ + +#ifndef __EFI_IP4_PROTOCOL_H__ +#define __EFI_IP4_PROTOCOL_H__ + +#include + +#define EFI_IP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xc51711e7, 0xb4bf, 0x404a, {0xbf, 0xb8, 0x0a, 0x04, 0x8e, 0xf1, 0xff, 0xe4 } \ + } + +#define EFI_IP4_PROTOCOL_GUID \ + { \ + 0x41d94cd2, 0x35b6, 0x455a, {0x82, 0x58, 0xd4, 0xe5, 0x13, 0x34, 0xaa, 0xdd } \ + } + +typedef struct _EFI_IP4_PROTOCOL EFI_IP4_PROTOCOL; + +/// +/// EFI_IP4_ADDRESS_PAIR is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE InstanceHandle; + EFI_IPv4_ADDRESS Ip4Address; + EFI_IPv4_ADDRESS SubnetMask; +} EFI_IP4_ADDRESS_PAIR; + +/// +/// EFI_IP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE DriverHandle; + UINT32 AddressCount; + EFI_IP4_ADDRESS_PAIR AddressPairs[1]; +} EFI_IP4_VARIABLE_DATA; + +typedef struct { + /// + /// The default IPv4 protocol packets to send and receive. Ignored + /// when AcceptPromiscuous is TRUE. + /// + UINT8 DefaultProtocol; + /// + /// Set to TRUE to receive all IPv4 packets that get through the receive filters. + /// Set to FALSE to receive only the DefaultProtocol IPv4 + /// packets that get through the receive filters. + /// + BOOLEAN AcceptAnyProtocol; + /// + /// Set to TRUE to receive ICMP error report packets. Ignored when + /// AcceptPromiscuous or AcceptAnyProtocol is TRUE. + /// + BOOLEAN AcceptIcmpErrors; + /// + /// Set to TRUE to receive broadcast IPv4 packets. Ignored when + /// AcceptPromiscuous is TRUE. + /// Set to FALSE to stop receiving broadcast IPv4 packets. + /// + BOOLEAN AcceptBroadcast; + /// + /// Set to TRUE to receive all IPv4 packets that are sent to any + /// hardware address or any protocol address. + /// Set to FALSE to stop receiving all promiscuous IPv4 packets + /// + BOOLEAN AcceptPromiscuous; + /// + /// Set to TRUE to use the default IPv4 address and default routing table. + /// + BOOLEAN UseDefaultAddress; + /// + /// The station IPv4 address that will be assigned to this EFI IPv4Protocol instance. + /// + EFI_IPv4_ADDRESS StationAddress; + /// + /// The subnet address mask that is associated with the station address. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// TypeOfService field in transmitted IPv4 packets. + /// + UINT8 TypeOfService; + /// + /// TimeToLive field in transmitted IPv4 packets. + /// + UINT8 TimeToLive; + /// + /// State of the DoNotFragment bit in transmitted IPv4 packets. + /// + BOOLEAN DoNotFragment; + /// + /// Set to TRUE to send and receive unformatted packets. The other + /// IPv4 receive filters are still applied. Fragmentation is disabled for RawData mode. + /// + BOOLEAN RawData; + /// + /// The timer timeout value (number of microseconds) for the + /// receive timeout event to be associated with each assembled + /// packet. Zero means do not drop assembled packets. + /// + UINT32 ReceiveTimeout; + /// + /// The timer timeout value (number of microseconds) for the + /// transmit timeout event to be associated with each outgoing + /// packet. Zero means do not drop outgoing packets. + /// + UINT32 TransmitTimeout; +} EFI_IP4_CONFIG_DATA; + + +typedef struct { + EFI_IPv4_ADDRESS SubnetAddress; + EFI_IPv4_ADDRESS SubnetMask; + EFI_IPv4_ADDRESS GatewayAddress; +} EFI_IP4_ROUTE_TABLE; + +typedef struct { + UINT8 Type; + UINT8 Code; +} EFI_IP4_ICMP_TYPE; + +typedef struct { + /// + /// Set to TRUE after this EFI IPv4 Protocol instance has been successfully configured. + /// + BOOLEAN IsStarted; + /// + /// The maximum packet size, in bytes, of the packet which the upper layer driver could feed. + /// + UINT32 MaxPacketSize; + /// + /// Current configuration settings. + /// + EFI_IP4_CONFIG_DATA ConfigData; + /// + /// Set to TRUE when the EFI IPv4 Protocol instance has a station address and subnet mask. + /// + BOOLEAN IsConfigured; + /// + /// Number of joined multicast groups. + /// + UINT32 GroupCount; + /// + /// List of joined multicast group addresses. + /// + EFI_IPv4_ADDRESS *GroupTable; + /// + /// Number of entries in the routing table. + /// + UINT32 RouteCount; + /// + /// Routing table entries. + /// + EFI_IP4_ROUTE_TABLE *RouteTable; + /// + /// Number of entries in the supported ICMP types list. + /// + UINT32 IcmpTypeCount; + /// + /// Array of ICMP types and codes that are supported by this EFI IPv4 Protocol driver + /// + EFI_IP4_ICMP_TYPE *IcmpTypeList; +} EFI_IP4_MODE_DATA; + +#pragma pack(1) + +typedef struct { + UINT8 HeaderLength:4; + UINT8 Version:4; + UINT8 TypeOfService; + UINT16 TotalLength; + UINT16 Identification; + UINT16 Fragmentation; + UINT8 TimeToLive; + UINT8 Protocol; + UINT16 Checksum; + EFI_IPv4_ADDRESS SourceAddress; + EFI_IPv4_ADDRESS DestinationAddress; +} EFI_IP4_HEADER; +#pragma pack() + + +typedef struct { + UINT32 FragmentLength; + VOID *FragmentBuffer; +} EFI_IP4_FRAGMENT_DATA; + + +typedef struct { + EFI_TIME TimeStamp; + EFI_EVENT RecycleSignal; + UINT32 HeaderLength; + EFI_IP4_HEADER *Header; + UINT32 OptionsLength; + VOID *Options; + UINT32 DataLength; + UINT32 FragmentCount; + EFI_IP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_IP4_RECEIVE_DATA; + + +typedef struct { + EFI_IPv4_ADDRESS SourceAddress; + EFI_IPv4_ADDRESS GatewayAddress; + UINT8 Protocol; + UINT8 TypeOfService; + UINT8 TimeToLive; + BOOLEAN DoNotFragment; +} EFI_IP4_OVERRIDE_DATA; + +typedef struct { + EFI_IPv4_ADDRESS DestinationAddress; + EFI_IP4_OVERRIDE_DATA *OverrideData; //OPTIONAL + UINT32 OptionsLength; //OPTIONAL + VOID *OptionsBuffer; //OPTIONAL + UINT32 TotalDataLength; + UINT32 FragmentCount; + EFI_IP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_IP4_TRANSMIT_DATA; + +typedef struct { + /// + /// This Event will be signaled after the Status field is updated + /// by the EFI IPv4 Protocol driver. The type of Event must be + /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// + EFI_EVENT Event; + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// + EFI_STATUS Status; + union { + /// + /// When this token is used for receiving, RxData is a pointer to the EFI_IP4_RECEIVE_DATA. + /// + EFI_IP4_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to the EFI_IP4_TRANSMIT_DATA. + /// + EFI_IP4_TRANSMIT_DATA *TxData; + } Packet; +} EFI_IP4_COMPLETION_TOKEN; + +/** + Gets the current operational settings for this instance of the EFI IPv4 Protocol driver. + + The GetModeData() function returns the current operational mode data for this + driver instance. The data fields in EFI_IP4_MODE_DATA are read only. This + function is used optionally to retrieve the operational mode data of underlying + networks or drivers. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param Ip4ModeData The pointer to the EFI IPv4 Protocol mode data structure. + @param MnpConfigData The pointer to the managed network configuration data structure. + @param SnpModeData The pointer to the simple network mode data structure. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_GET_MODE_DATA)( + IN CONST EFI_IP4_PROTOCOL *This, + OUT EFI_IP4_MODE_DATA *Ip4ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + +/** + Assigns an IPv4 address and subnet mask to this EFI IPv4 Protocol driver instance. + + The Configure() function is used to set, change, or reset the operational + parameters and filter settings for this EFI IPv4 Protocol instance. Until these + parameters have been set, no network traffic can be sent or received by this + instance. Once the parameters have been reset (by calling this function with + IpConfigData set to NULL), no more traffic can be sent or received until these + parameters have been set again. Each EFI IPv4 Protocol instance can be started + and stopped independently of each other by enabling or disabling their receive + filter settings with the Configure() function. + + When IpConfigData.UseDefaultAddress is set to FALSE, the new station address will + be appended as an alias address into the addresses list in the EFI IPv4 Protocol + driver. While set to TRUE, Configure() will trigger the EFI_IP4_CONFIG_PROTOCOL + to retrieve the default IPv4 address if it is not available yet. Clients could + frequently call GetModeData() to check the status to ensure that the default IPv4 + address is ready. + + If operational parameters are reset or changed, any pending transmit and receive + requests will be cancelled. Their completion token status will be set to EFI_ABORTED + and their events will be signaled. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param IpConfigData The pointer to the EFI IPv4 Protocol configuration data structure. + + @retval EFI_SUCCESS The driver instance was successfully opened. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + IpConfigData.StationAddress is not a unicast IPv4 address. + IpConfigData.SubnetMask is not a valid IPv4 subnet + @retval EFI_UNSUPPORTED One or more of the following conditions is TRUE: + A configuration protocol (DHCP, BOOTP, RARP, etc.) could + not be located when clients choose to use the default IPv4 + address. This EFI IPv4 Protocol implementation does not + support this requested filter or timeout setting. + @retval EFI_OUT_OF_RESOURCES The EFI IPv4 Protocol driver instance data could not be allocated. + @retval EFI_ALREADY_STARTED The interface is already open and must be stopped before the + IPv4 address or subnet mask can be changed. The interface must + also be stopped when switching to/from raw packet mode. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv4 + Protocol driver instance is not opened. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIGURE)( + IN EFI_IP4_PROTOCOL *This, + IN EFI_IP4_CONFIG_DATA *IpConfigData OPTIONAL + ); + +/** + Joins and leaves multicast groups. + + The Groups() function is used to join and leave multicast group sessions. Joining + a group will enable reception of matching multicast packets. Leaving a group will + disable the multicast packet reception. + + If JoinFlag is FALSE and GroupAddress is NULL, all joined groups will be left. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param JoinFlag Set to TRUE to join the multicast group session and FALSE to leave. + @param GroupAddress The pointer to the IPv4 multicast address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following is TRUE: + - This is NULL. + - JoinFlag is TRUE and GroupAddress is NULL. + - GroupAddress is not NULL and *GroupAddress is + not a multicast IPv4 address. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES System resources could not be allocated. + @retval EFI_UNSUPPORTED This EFI IPv4 Protocol implementation does not support multicast groups. + @retval EFI_ALREADY_STARTED The group address is already in the group table (when + JoinFlag is TRUE). + @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_GROUPS)( + IN EFI_IP4_PROTOCOL *This, + IN BOOLEAN JoinFlag, + IN EFI_IPv4_ADDRESS *GroupAddress OPTIONAL + ); + +/** + Adds and deletes routing table entries. + + The Routes() function adds a route to or deletes a route from the routing table. + + Routes are determined by comparing the SubnetAddress with the destination IPv4 + address arithmetically AND-ed with the SubnetMask. The gateway address must be + on the same subnet as the configured station address. + + The default route is added with SubnetAddress and SubnetMask both set to 0.0.0.0. + The default route matches all destination IPv4 addresses that do not match any + other routes. + + A GatewayAddress that is zero is a nonroute. Packets are sent to the destination + IP address if it can be found in the ARP cache or on the local subnet. One automatic + nonroute entry will be inserted into the routing table for outgoing packets that + are addressed to a local subnet (gateway address of 0.0.0.0). + + Each EFI IPv4 Protocol instance has its own independent routing table. Those EFI + IPv4 Protocol instances that use the default IPv4 address will also have copies + of the routing table that was provided by the EFI_IP4_CONFIG_PROTOCOL, and these + copies will be updated whenever the EIF IPv4 Protocol driver reconfigures its + instances. As a result, client modification to the routing table will be lost. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param DeleteRoute Set to TRUE to delete this route from the routing table. Set to + FALSE to add this route to the routing table. SubnetAddress + and SubnetMask are used as the key to each route entry. + @param SubnetAddress The address of the subnet that needs to be routed. + @param SubnetMask The subnet mask of SubnetAddress. + @param GatewayAddress The unicast gateway IPv4 address for this route. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The driver instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - SubnetAddress is NULL. + - SubnetMask is NULL. + - GatewayAddress is NULL. + - *SubnetAddress is not a valid subnet address. + - *SubnetMask is not a valid subnet mask. + - *GatewayAddress is not a valid unicast IPv4 address. + @retval EFI_OUT_OF_RESOURCES Could not add the entry to the routing table. + @retval EFI_NOT_FOUND This route is not in the routing table (when DeleteRoute is TRUE). + @retval EFI_ACCESS_DENIED The route is already defined in the routing table (when + DeleteRoute is FALSE). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_ROUTES)( + IN EFI_IP4_PROTOCOL *This, + IN BOOLEAN DeleteRoute, + IN EFI_IPv4_ADDRESS *SubnetAddress, + IN EFI_IPv4_ADDRESS *SubnetMask, + IN EFI_IPv4_ADDRESS *GatewayAddress + ); + +/** + Places outgoing data packets into the transmit queue. + + The Transmit() function places a sending request in the transmit queue of this + EFI IPv4 Protocol instance. Whenever the packet in the token is sent out or some + errors occur, the event in the token will be signaled and the status is updated. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param Token The pointer to the transmit token. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more pameters are invalid. + @retval EFI_ACCESS_DENIED The transmit completion token with the same Token.Event + was already in the transmit queue. + @retval EFI_NOT_READY The completion token could not be queued because the transmit + queue is full. + @retval EFI_NOT_FOUND Not route is found to destination address. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data. + @retval EFI_BUFFER_TOO_SMALL Token.Packet.TxData.TotalDataLength is too + short to transmit. + @retval EFI_BAD_BUFFER_SIZE The length of the IPv4 header + option length + total data length is + greater than MTU (or greater than the maximum packet size if + Token.Packet.TxData.OverrideData. + DoNotFragment is TRUE.) + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_TRANSMIT)( + IN EFI_IP4_PROTOCOL *This, + IN EFI_IP4_COMPLETION_TOKEN *Token + ); + +/** + Places a receiving request into the receiving queue. + + The Receive() function places a completion token into the receive packet queue. + This function is always asynchronous. + + The Token.Event field in the completion token must be filled in by the caller + and cannot be NULL. When the receive operation completes, the EFI IPv4 Protocol + driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event + is signaled. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param Token The pointer to a token that is associated with the receive data descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI IPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, RARP, etc.) + is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system + resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + The EFI IPv4 Protocol instance has been reset to startup defaults. + @retval EFI_ACCESS_DENIED The receive completion token with the same Token.Event was already + in the receive queue. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + @retval EFI_ICMP_ERROR An ICMP error packet was received. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_RECEIVE)( + IN EFI_IP4_PROTOCOL *This, + IN EFI_IP4_COMPLETION_TOKEN *Token + ); + +/** + Abort an asynchronous transmit or receive request. + + The Cancel() function is used to abort a pending transmit or receive request. + If the token is in the transmit or receive request queues, after calling this + function, Token->Status will be set to EFI_ABORTED and then Token->Event will + be signaled. If the token is not in one of the queues, which usually means the + asynchronous operation has completed, this function will not signal the token + and EFI_NOT_FOUND is returned. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + @param Token The pointer to a token that has been issued by + EFI_IP4_PROTOCOL.Transmit() or + EFI_IP4_PROTOCOL.Receive(). If NULL, all pending + tokens are aborted. Type EFI_IP4_COMPLETION_TOKEN is + defined in EFI_IP4_PROTOCOL.Transmit(). + + @retval EFI_SUCCESS The asynchronous I/O request was aborted and + Token->Event was signaled. When Token is NULL, all + pending requests were aborted and their events were signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was + not found in the transmit or receive queue. It has either completed + or was not issued by Transmit() and Receive(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CANCEL)( + IN EFI_IP4_PROTOCOL *This, + IN EFI_IP4_COMPLETION_TOKEN *Token OPTIONAL + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function polls for incoming data packets and processes outgoing data + packets. Network drivers and applications can call the EFI_IP4_PROTOCOL.Poll() + function to increase the rate that data packets are moved between the communications + device and the transmit and receive queues. + + In some systems the periodic timer event may not poll the underlying communications + device fast enough to transmit and/or receive all data packets without missing + incoming packets or dropping outgoing packets. Drivers and applications that are + experiencing packet loss should try calling the EFI_IP4_PROTOCOL.Poll() function + more often. + + @param This The pointer to the EFI_IP4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI IPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY No incoming or outgoing data is processed. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_POLL)( + IN EFI_IP4_PROTOCOL *This + ); + +/// +/// The EFI IPv4 Protocol implements a simple packet-oriented interface that can be +/// used by drivers, daemons, and applications to transmit and receive network packets. +/// +struct _EFI_IP4_PROTOCOL { + EFI_IP4_GET_MODE_DATA GetModeData; + EFI_IP4_CONFIGURE Configure; + EFI_IP4_GROUPS Groups; + EFI_IP4_ROUTES Routes; + EFI_IP4_TRANSMIT Transmit; + EFI_IP4_RECEIVE Receive; + EFI_IP4_CANCEL Cancel; + EFI_IP4_POLL Poll; +}; + +extern EFI_GUID gEfiIp4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiIp4ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config.h new file mode 100644 index 0000000000..6f991feb34 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config.h @@ -0,0 +1,176 @@ +/** @file + This file provides a definition of the EFI IPv4 Configuration + Protocol. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0. + +**/ +#ifndef __EFI_IP4CONFIG_PROTOCOL_H__ +#define __EFI_IP4CONFIG_PROTOCOL_H__ + +#include + +#define EFI_IP4_CONFIG_PROTOCOL_GUID \ + { \ + 0x3b95aa31, 0x3793, 0x434b, {0x86, 0x67, 0xc8, 0x07, 0x08, 0x92, 0xe0, 0x5e } \ + } + +typedef struct _EFI_IP4_CONFIG_PROTOCOL EFI_IP4_CONFIG_PROTOCOL; + +#define IP4_CONFIG_VARIABLE_ATTRIBUTES \ + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS) + +/// +/// EFI_IP4_IPCONFIG_DATA contains the minimum IPv4 configuration data +/// that is needed to start basic network communication. The StationAddress +/// and SubnetMask must be a valid unicast IP address and subnet mask. +/// If RouteTableSize is not zero, then RouteTable contains a properly +/// formatted routing table for the StationAddress/SubnetMask, with the +/// last entry in the table being the default route. +/// +typedef struct { + /// + /// Default station IP address, stored in network byte order. + /// + EFI_IPv4_ADDRESS StationAddress; + /// + /// Default subnet mask, stored in network byte order. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// Number of entries in the following RouteTable. May be zero. + /// + UINT32 RouteTableSize; + /// + /// Default routing table data (stored in network byte order). + /// Ignored if RouteTableSize is zero. + /// + EFI_IP4_ROUTE_TABLE *RouteTable; +} EFI_IP4_IPCONFIG_DATA; + + +/** + Starts running the configuration policy for the EFI IPv4 Protocol driver. + + The Start() function is called to determine and to begin the platform + configuration policy by the EFI IPv4 Protocol driver. This determination may + be as simple as returning EFI_UNSUPPORTED if there is no EFI IPv4 Protocol + driver configuration policy. It may be as involved as loading some defaults + from nonvolatile storage, downloading dynamic data from a DHCP server, and + checking permissions with a site policy server. + Starting the configuration policy is just the beginning. It may finish almost + instantly or it may take several minutes before it fails to retrieve configuration + information from one or more servers. Once the policy is started, drivers + should use the DoneEvent parameter to determine when the configuration policy + has completed. EFI_IP4_CONFIG_PROTOCOL.GetData() must then be called to + determine if the configuration succeeded or failed. + Until the configuration completes successfully, EFI IPv4 Protocol driver instances + that are attempting to use default configurations must return EFI_NO_MAPPING. + Once the configuration is complete, the EFI IPv4 Configuration Protocol driver + signals DoneEvent. The configuration may need to be updated in the future. + Note that in this case the EFI IPv4 Configuration Protocol driver must signal + ReconfigEvent, and all EFI IPv4 Protocol driver instances that are using default + configurations must return EFI_NO_MAPPING until the configuration policy has + been rerun. + + @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance. + @param DoneEvent Event that will be signaled when the EFI IPv4 + Protocol driver configuration policy completes + execution. This event must be of type EVT_NOTIFY_SIGNAL. + @param ReconfigEvent Event that will be signaled when the EFI IPv4 + Protocol driver configuration needs to be updated. + This event must be of type EVT_NOTIFY_SIGNAL. + + @retval EFI_SUCCESS The configuration policy for the EFI IPv4 Protocol + driver is now running. + @retval EFI_INVALID_PARAMETER One or more of the following parameters is NULL: + This + DoneEvent + ReconfigEvent + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ALREADY_STARTED The configuration policy for the EFI IPv4 Protocol + driver was already started. + @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred. + @retval EFI_UNSUPPORTED This interface does not support the EFI IPv4 Protocol + driver configuration. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG_START)( + IN EFI_IP4_CONFIG_PROTOCOL *This, + IN EFI_EVENT DoneEvent, + IN EFI_EVENT ReconfigEvent + ); + +/** + Stops running the configuration policy for the EFI IPv4 Protocol driver. + + The Stop() function stops the configuration policy for the EFI IPv4 Protocol driver. + All configuration data will be lost after calling Stop(). + + @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance. + + @retval EFI_SUCCESS The configuration policy for the EFI IPv4 Protocol + driver has been stopped. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED The configuration policy for the EFI IPv4 Protocol + driver was not started. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG_STOP)( + IN EFI_IP4_CONFIG_PROTOCOL *This + ); + +/** + Returns the default configuration data (if any) for the EFI IPv4 Protocol driver. + + The GetData() function returns the current configuration data for the EFI IPv4 + Protocol driver after the configuration policy has completed. + + @param This The pointer to the EFI_IP4_CONFIG_PROTOCOL instance. + @param IpConfigDataSize On input, the size of the IpConfigData buffer. + On output, the count of bytes that were written + into the IpConfigData buffer. + @param IpConfigData The pointer to the EFI IPv4 Configuration Protocol + driver configuration data structure. + Type EFI_IP4_IPCONFIG_DATA is defined in + "Related Definitions" below. + + @retval EFI_SUCCESS The EFI IPv4 Protocol driver configuration has been returned. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED The configuration policy for the EFI IPv4 Protocol + driver is not running. + @retval EFI_NOT_READY EFI IPv4 Protocol driver configuration is still running. + @retval EFI_ABORTED EFI IPv4 Protocol driver configuration could not complete. + @retval EFI_BUFFER_TOO_SMALL *IpConfigDataSize is smaller than the configuration + data buffer or IpConfigData is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG_GET_DATA)( + IN EFI_IP4_CONFIG_PROTOCOL *This, + IN OUT UINTN *IpConfigDataSize, + OUT EFI_IP4_IPCONFIG_DATA *IpConfigData OPTIONAL + ); + +/// +/// The EFI_IP4_CONFIG_PROTOCOL driver performs platform-dependent and policy-dependent +/// configurations for the EFI IPv4 Protocol driver. +/// +struct _EFI_IP4_CONFIG_PROTOCOL { + EFI_IP4_CONFIG_START Start; + EFI_IP4_CONFIG_STOP Stop; + EFI_IP4_CONFIG_GET_DATA GetData; +}; + +extern EFI_GUID gEfiIp4ConfigProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config2.h new file mode 100644 index 0000000000..e1c4a7e3ff --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip4Config2.h @@ -0,0 +1,317 @@ +/** @file + This file provides a definition of the EFI IPv4 Configuration II + Protocol. + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Revision Reference: +This Protocol is introduced in UEFI Specification 2.5 + +**/ +#ifndef __EFI_IP4CONFIG2_PROTOCOL_H__ +#define __EFI_IP4CONFIG2_PROTOCOL_H__ + +#include + +#define EFI_IP4_CONFIG2_PROTOCOL_GUID \ + { \ + 0x5b446ed1, 0xe30b, 0x4faa, {0x87, 0x1a, 0x36, 0x54, 0xec, 0xa3, 0x60, 0x80 } \ + } + +typedef struct _EFI_IP4_CONFIG2_PROTOCOL EFI_IP4_CONFIG2_PROTOCOL; + + +/// +/// EFI_IP4_CONFIG2_DATA_TYPE +/// +typedef enum { + /// + /// The interface information of the communication device this EFI + /// IPv4 Configuration II Protocol instance manages. This type of + /// data is read only. The corresponding Data is of type + /// EFI_IP4_CONFIG2_INTERFACE_INFO. + /// + Ip4Config2DataTypeInterfaceInfo, + /// + /// The general configuration policy for the EFI IPv4 network stack + /// running on the communication device this EFI IPv4 + /// Configuration II Protocol instance manages. The policy will + /// affect other configuration settings. The corresponding Data is of + /// type EFI_IP4_CONFIG2_POLICY. + /// + Ip4Config2DataTypePolicy, + /// + /// The station addresses set manually for the EFI IPv4 network + /// stack. It is only configurable when the policy is + /// Ip4Config2PolicyStatic. The corresponding Data is of + /// type EFI_IP4_CONFIG2_MANUAL_ADDRESS. When DataSize + /// is 0 and Data is NULL, the existing configuration is cleared + /// from the EFI IPv4 Configuration II Protocol instance. + /// + Ip4Config2DataTypeManualAddress, + /// + /// The gateway addresses set manually for the EFI IPv4 network + /// stack running on the communication device this EFI IPv4 + /// Configuration II Protocol manages. It is not configurable when + /// the policy is Ip4Config2PolicyDhcp. The gateway + /// addresses must be unicast IPv4 addresses. The corresponding + /// Data is a pointer to an array of EFI_IPv4_ADDRESS instances. + /// When DataSize is 0 and Data is NULL, the existing configuration + /// is cleared from the EFI IPv4 Configuration II Protocol instance. + /// + Ip4Config2DataTypeGateway, + /// + /// The DNS server list for the EFI IPv4 network stack running on + /// the communication device this EFI IPv4 Configuration II + /// Protocol manages. It is not configurable when the policy is + /// Ip4Config2PolicyDhcp. The DNS server addresses must be + /// unicast IPv4 addresses. The corresponding Data is a pointer to + /// an array of EFI_IPv4_ADDRESS instances. When DataSize + /// is 0 and Data is NULL, the existing configuration is cleared + /// from the EFI IPv4 Configuration II Protocol instance. + /// + Ip4Config2DataTypeDnsServer, + Ip4Config2DataTypeMaximum +} EFI_IP4_CONFIG2_DATA_TYPE; + +/// +/// EFI_IP4_CONFIG2_INTERFACE_INFO related definitions +/// +#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32 + +/// +/// EFI_IP4_CONFIG2_INTERFACE_INFO +/// +typedef struct { + /// + /// The name of the interface. It is a NULL-terminated Unicode string. + /// + CHAR16 Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE]; + /// + /// The interface type of the network interface. See RFC 1700, + /// section "Number Hardware Type". + /// + UINT8 IfType; + /// + /// The size, in bytes, of the network interface's hardware address. + /// + UINT32 HwAddressSize; + /// + /// The hardware address for the network interface. + /// + EFI_MAC_ADDRESS HwAddress; + /// + /// The station IPv4 address of this EFI IPv4 network stack. + /// + EFI_IPv4_ADDRESS StationAddress; + /// + /// The subnet address mask that is associated with the station address. + /// + EFI_IPv4_ADDRESS SubnetMask; + /// + /// Size of the following RouteTable, in bytes. May be zero. + /// + UINT32 RouteTableSize; + /// + /// The route table of the IPv4 network stack runs on this interface. + /// Set to NULL if RouteTableSize is zero. Type EFI_IP4_ROUTE_TABLE is defined in + /// EFI_IP4_PROTOCOL.GetModeData(). + /// + EFI_IP4_ROUTE_TABLE *RouteTable OPTIONAL; +} EFI_IP4_CONFIG2_INTERFACE_INFO; + +/// +/// EFI_IP4_CONFIG2_POLICY +/// +typedef enum { + /// + /// Under this policy, the Ip4Config2DataTypeManualAddress, + /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration + /// data are required to be set manually. The EFI IPv4 Protocol will get all + /// required configuration such as IPv4 address, subnet mask and + /// gateway settings from the EFI IPv4 Configuration II protocol. + /// + Ip4Config2PolicyStatic, + /// + /// Under this policy, the Ip4Config2DataTypeManualAddress, + /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration data are + /// not allowed to set via SetData(). All of these configurations are retrieved from DHCP + /// server or other auto-configuration mechanism. + /// + Ip4Config2PolicyDhcp, + Ip4Config2PolicyMax +} EFI_IP4_CONFIG2_POLICY; + +/// +/// EFI_IP4_CONFIG2_MANUAL_ADDRESS +/// +typedef struct { + /// + /// The IPv4 unicast address. + /// + EFI_IPv4_ADDRESS Address; + /// + /// The subnet mask. + /// + EFI_IPv4_ADDRESS SubnetMask; +} EFI_IP4_CONFIG2_MANUAL_ADDRESS; + +/** + Set the configuration for the EFI IPv4 network stack running on the communication device this EFI + IPv4 Configuration II Protocol instance manages. + + This function is used to set the configuration data of type DataType for the EFI IPv4 network stack + running on the communication device this EFI IPv4 Configuration II Protocol instance manages. + The successfully configured data is valid after system reset or power-off. + The DataSize is used to calculate the count of structure instances in the Data for some + DataType that multiple structure instances are allowed. + This function is always non-blocking. When setting some typeof configuration data, an + asynchronous process is invoked to check the correctness of the data, such as doing address conflict + detection on the manually set local IPv4 address. EFI_NOT_READY is returned immediately to + indicate that such an asynchronous process is invoked and the process is not finished yet. The caller + willing to get the result of the asynchronous process is required to call RegisterDataNotify() + to register an event on the specified configuration data. Once the event is signaled, the caller can call + GetData()to get back the configuration data in order to know the result. For other types of + configuration data that do not require an asynchronous configuration process, the result of the + operation is immediately returned. + + @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance. + @param[in] DataType The type of data to set. + @param[in] DataSize Size of the buffer pointed to by Data in bytes. + @param[in] Data The data buffer to set. The type ofthe data buffer is associated + with the DataType. + + @retval EFI_SUCCESS The specified configuration data for the EFI IPv4 network stack is set + successfully. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + This is NULL. + One or more fields in Data and DataSize do not match the + requirement of the data type indicated by DataType. + @retval EFI_WRITE_PROTECTED The specified configuration data is read-only or the specified configuration + data can not be set under the current policy. + @retval EFI_ACCESS_DENIED Another set operation on the specified configuration data is already in process. + @retval EFI_NOT_READY An asynchronous process is invoked to set the specified configuration data and + the process is not finished yet. + @retval EFI_BAD_BUFFER_SIZE The DataSize does not match the size of the type indicated by DataType. + @retval EFI_UNSUPPORTED This DataType is not supported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG2_SET_DATA) ( + IN EFI_IP4_CONFIG2_PROTOCOL *This, + IN EFI_IP4_CONFIG2_DATA_TYPE DataType, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Get the configuration data for the EFI IPv4 network stack running on the communication device this + EFI IPv4 Configuration II Protocol instance manages. + + This function returns the configuration data of type DataType for the EFI IPv4 network stack + running on the communication device this EFI IPv4 Configuration II Protocol instance manages. + The caller is responsible for allocating the buffer usedto return the specified configuration data and + the required size will be returned to the caller if the size of the buffer is too small. + EFI_NOT_READY is returned if the specified configuration data is not ready due to an already in + progress asynchronous configuration process. The caller can call RegisterDataNotify() to + register an event on the specified configuration data. Once the asynchronous configuration process is + finished, the event will be signaled and a subsequent GetData() call will return the specified + configuration data. + + @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance. + @param[in] DataType The type of data to get. + @param[out] DataSize On input, in bytes, the size of Data. On output, in bytes, the size + of buffer required to store the specified configuration data. + @param[in] Data The data buffer in which the configuration data is returned. The + type of the data buffer is associated with the DataType. Ignored + if DataSize is 0. + + @retval EFI_SUCCESS The specified configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE: + This is NULL. + DataSize is NULL. + Data is NULL if *DataSizeis not zero. + @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the specified configuration data + and the required size is returned in DataSize. + @retval EFI_NOT_READY The specified configuration data is not ready due to an already in + progress asynchronous configuration process. + @retval EFI_NOT_FOUND The specified configuration data is not found. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG2_GET_DATA) ( + IN EFI_IP4_CONFIG2_PROTOCOL *This, + IN EFI_IP4_CONFIG2_DATA_TYPE DataType, + IN OUT UINTN *DataSize, + IN VOID *Data OPTIONAL + ); + +/** + Register an event that is to be signaled whenever a configuration process on the specified + configuration data is done. + + This function registers an event that is to be signaled whenever a configuration process on the + specified configuration data is done. An event can be registered for different DataType + simultaneously and the caller is responsible for determining which type of configuration data causes + the signaling of the event in such case. + + @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance. + @param[in] DataType The type of data to unregister the event for. + @param[in] Event The event to register. + + @retval EFI_SUCCESS The notification event for the specified configuration data is + registered. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_UNSUPPORTED The configuration data type specified by DataType is not supported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The Event is already registered for the DataType. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG2_REGISTER_NOTIFY) ( + IN EFI_IP4_CONFIG2_PROTOCOL *This, + IN EFI_IP4_CONFIG2_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/** + Remove a previously registered event for the specified configuration data. + + This function removes a previously registeredevent for the specified configuration data. + + @param[in] This Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance. + @param[in] DataType The type of data to remove the previously registered event for. + @param[in] Event The event to unregister. + + @retval EFI_SUCCESS The event registered for the specified configuration data is removed. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_NOT_FOUND The Eventhas not been registered for the specified DataType. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP4_CONFIG2_UNREGISTER_NOTIFY) ( + IN EFI_IP4_CONFIG2_PROTOCOL *This, + IN EFI_IP4_CONFIG2_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/// +/// The EFI_IP4_CONFIG2_PROTOCOL is designed to be the central repository for the common +/// configurations and the administrator configurable settings for the EFI IPv4 network stack. +/// An EFI IPv4 Configuration II Protocol instance will be installed on each communication device that +/// the EFI IPv4 network stack runs on. +/// +struct _EFI_IP4_CONFIG2_PROTOCOL { + EFI_IP4_CONFIG2_SET_DATA SetData; + EFI_IP4_CONFIG2_GET_DATA GetData; + EFI_IP4_CONFIG2_REGISTER_NOTIFY RegisterDataNotify; + EFI_IP4_CONFIG2_UNREGISTER_NOTIFY UnregisterDataNotify; +}; + +extern EFI_GUID gEfiIp4Config2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6.h new file mode 100644 index 0000000000..c82f36501d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6.h @@ -0,0 +1,947 @@ +/** @file + This file defines the EFI IPv6 (Internet Protocol version 6) + Protocol interface. It is split into the following three main + sections: + - EFI IPv6 Service Binding Protocol + - EFI IPv6 Variable (deprecated in UEFI 2.4B) + - EFI IPv6 Protocol + The EFI IPv6 Protocol provides basic network IPv6 packet I/O services, + which includes support for Neighbor Discovery Protocol (ND), Multicast + Listener Discovery Protocol (MLD), and a subset of the Internet Control + Message Protocol (ICMPv6). + + Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_IP6_PROTOCOL_H__ +#define __EFI_IP6_PROTOCOL_H__ + +#include + + +#define EFI_IP6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xec835dd3, 0xfe0f, 0x617b, {0xa6, 0x21, 0xb3, 0x50, 0xc3, 0xe1, 0x33, 0x88 } \ + } + +#define EFI_IP6_PROTOCOL_GUID \ + { \ + 0x2c8759d5, 0x5c2d, 0x66ef, {0x92, 0x5f, 0xb6, 0x6c, 0x10, 0x19, 0x57, 0xe2 } \ + } + +typedef struct _EFI_IP6_PROTOCOL EFI_IP6_PROTOCOL; + +/// +/// EFI_IP6_ADDRESS_PAIR is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct{ + /// + /// The EFI IPv6 Protocol instance handle that is using this address/prefix pair. + /// + EFI_HANDLE InstanceHandle; + /// + /// IPv6 address in network byte order. + /// + EFI_IPv6_ADDRESS Ip6Address; + /// + /// The length of the prefix associated with the Ip6Address. + /// + UINT8 PrefixLength; +} EFI_IP6_ADDRESS_PAIR; + +/// +/// EFI_IP6_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + /// + /// The handle of the driver that creates this entry. + /// + EFI_HANDLE DriverHandle; + /// + /// The number of IPv6 address pairs that follow this data structure. + /// + UINT32 AddressCount; + /// + /// List of IPv6 address pairs that are currently in use. + /// + EFI_IP6_ADDRESS_PAIR AddressPairs[1]; +} EFI_IP6_VARIABLE_DATA; + +/// +/// ICMPv6 type definitions for error messages +/// +///@{ +#define ICMP_V6_DEST_UNREACHABLE 0x1 +#define ICMP_V6_PACKET_TOO_BIG 0x2 +#define ICMP_V6_TIME_EXCEEDED 0x3 +#define ICMP_V6_PARAMETER_PROBLEM 0x4 +///@} + +/// +/// ICMPv6 type definition for informational messages +/// +///@{ +#define ICMP_V6_ECHO_REQUEST 0x80 +#define ICMP_V6_ECHO_REPLY 0x81 +#define ICMP_V6_LISTENER_QUERY 0x82 +#define ICMP_V6_LISTENER_REPORT 0x83 +#define ICMP_V6_LISTENER_DONE 0x84 +#define ICMP_V6_ROUTER_SOLICIT 0x85 +#define ICMP_V6_ROUTER_ADVERTISE 0x86 +#define ICMP_V6_NEIGHBOR_SOLICIT 0x87 +#define ICMP_V6_NEIGHBOR_ADVERTISE 0x88 +#define ICMP_V6_REDIRECT 0x89 +#define ICMP_V6_LISTENER_REPORT_2 0x8F +///@} + +/// +/// ICMPv6 code definitions for ICMP_V6_DEST_UNREACHABLE +/// +///@{ +#define ICMP_V6_NO_ROUTE_TO_DEST 0x0 +#define ICMP_V6_COMM_PROHIBITED 0x1 +#define ICMP_V6_BEYOND_SCOPE 0x2 +#define ICMP_V6_ADDR_UNREACHABLE 0x3 +#define ICMP_V6_PORT_UNREACHABLE 0x4 +#define ICMP_V6_SOURCE_ADDR_FAILED 0x5 +#define ICMP_V6_ROUTE_REJECTED 0x6 +///@} + +/// +/// ICMPv6 code definitions for ICMP_V6_TIME_EXCEEDED +/// +///@{ +#define ICMP_V6_TIMEOUT_HOP_LIMIT 0x0 +#define ICMP_V6_TIMEOUT_REASSEMBLE 0x1 +///@} + +/// +/// ICMPv6 code definitions for ICMP_V6_PARAMETER_PROBLEM +/// +///@{ +#define ICMP_V6_ERRONEOUS_HEADER 0x0 +#define ICMP_V6_UNRECOGNIZE_NEXT_HDR 0x1 +#define ICMP_V6_UNRECOGNIZE_OPTION 0x2 +///@} + +/// +/// EFI_IP6_CONFIG_DATA +/// is used to report and change IPv6 session parameters. +/// +typedef struct { + /// + /// For the IPv6 packet to send and receive, this is the default value + /// of the 'Next Header' field in the last IPv6 extension header or in + /// the IPv6 header if there are no extension headers. Ignored when + /// AcceptPromiscuous is TRUE. + /// + UINT8 DefaultProtocol; + /// + /// Set to TRUE to receive all IPv6 packets that get through the + /// receive filters. + /// Set to FALSE to receive only the DefaultProtocol IPv6 + /// packets that get through the receive filters. Ignored when + /// AcceptPromiscuous is TRUE. + /// + BOOLEAN AcceptAnyProtocol; + /// + /// Set to TRUE to receive ICMP error report packets. Ignored when + /// AcceptPromiscuous or AcceptAnyProtocol is TRUE. + /// + BOOLEAN AcceptIcmpErrors; + /// + /// Set to TRUE to receive all IPv6 packets that are sent to any + /// hardware address or any protocol address. Set to FALSE to stop + /// receiving all promiscuous IPv6 packets. + /// + BOOLEAN AcceptPromiscuous; + /// + /// The destination address of the packets that will be transmitted. + /// Ignored if it is unspecified. + /// + EFI_IPv6_ADDRESS DestinationAddress; + /// + /// The station IPv6 address that will be assigned to this EFI IPv6 + /// Protocol instance. This field can be set and changed only when + /// the EFI IPv6 driver is transitioning from the stopped to the started + /// states. If the StationAddress is specified, the EFI IPv6 Protocol + /// driver will deliver only incoming IPv6 packets whose destination + /// matches this IPv6 address exactly. The StationAddress is required + /// to be one of currently configured IPv6 addresses. An address + /// containing all zeroes is also accepted as a special case. Under this + /// situation, the IPv6 driver is responsible for binding a source + /// address to this EFI IPv6 protocol instance according to the source + /// address selection algorithm. Only incoming packets destined to + /// the selected address will be delivered to the user. And the + /// selected station address can be retrieved through later + /// GetModeData() call. If no address is available for selecting, + /// EFI_NO_MAPPING will be returned, and the station address will + /// only be successfully bound to this EFI IPv6 protocol instance + /// after IP6ModeData.IsConfigured changed to TRUE. + /// + EFI_IPv6_ADDRESS StationAddress; + /// + /// TrafficClass field in transmitted IPv6 packets. Default value + /// is zero. + /// + UINT8 TrafficClass; + /// + /// HopLimit field in transmitted IPv6 packets. + /// + UINT8 HopLimit; + /// + /// FlowLabel field in transmitted IPv6 packets. Default value is + /// zero. + /// + UINT32 FlowLabel; + /// + /// The timer timeout value (number of microseconds) for the + /// receive timeout event to be associated with each assembled + /// packet. Zero means do not drop assembled packets. + /// + UINT32 ReceiveTimeout; + /// + /// The timer timeout value (number of microseconds) for the + /// transmit timeout event to be associated with each outgoing + /// packet. Zero means do not drop outgoing packets. + /// + UINT32 TransmitTimeout; +} EFI_IP6_CONFIG_DATA; + +/// +/// EFI_IP6_ADDRESS_INFO +/// +typedef struct { + EFI_IPv6_ADDRESS Address; ///< The IPv6 address. + UINT8 PrefixLength; ///< The length of the prefix associated with the Address. +} EFI_IP6_ADDRESS_INFO; + +/// +/// EFI_IP6_ROUTE_TABLE +/// is the entry structure that is used in routing tables +/// +typedef struct { + /// + /// The IPv6 address of the gateway to be used as the next hop for + /// packets to this prefix. If the IPv6 address is all zeros, then the + /// prefix is on-link. + /// + EFI_IPv6_ADDRESS Gateway; + /// + /// The destination prefix to be routed. + /// + EFI_IPv6_ADDRESS Destination; + /// + /// The length of the prefix associated with the Destination. + /// + UINT8 PrefixLength; +} EFI_IP6_ROUTE_TABLE; + +/// +/// EFI_IP6_NEIGHBOR_STATE +/// +typedef enum { + /// + /// Address resolution is being performed on this entry. Specially, + /// Neighbor Solicitation has been sent to the solicited-node + /// multicast address of the target, but corresponding Neighbor + /// Advertisement has not been received. + /// + EfiNeighborInComplete, + /// + /// Positive confirmation was received that the forward path to the + /// neighbor was functioning properly. + /// + EfiNeighborReachable, + /// + ///Reachable Time has elapsed since the last positive confirmation + ///was received. In this state, the forward path to the neighbor was + ///functioning properly. + /// + EfiNeighborStale, + /// + /// This state is an optimization that gives upper-layer protocols + /// additional time to provide reachability confirmation. + /// + EfiNeighborDelay, + /// + /// A reachability confirmation is actively sought by retransmitting + /// Neighbor Solicitations every RetransTimer milliseconds until a + /// reachability confirmation is received. + /// + EfiNeighborProbe +} EFI_IP6_NEIGHBOR_STATE; + +/// +/// EFI_IP6_NEIGHBOR_CACHE +/// is the entry structure that is used in neighbor cache. It records a set +/// of entries about individual neighbors to which traffic has been sent recently. +/// +typedef struct { + EFI_IPv6_ADDRESS Neighbor; ///< The on-link unicast/anycast IP address of the neighbor. + EFI_MAC_ADDRESS LinkAddress; ///< Link-layer address of the neighbor. + EFI_IP6_NEIGHBOR_STATE State; ///< State of this neighbor cache entry. +} EFI_IP6_NEIGHBOR_CACHE; + +/// +/// EFI_IP6_ICMP_TYPE +/// is used to describe those ICMP messages that are supported by this EFI +/// IPv6 Protocol driver. +/// +typedef struct { + UINT8 Type; ///< The type of ICMP message. + UINT8 Code; ///< The code of the ICMP message. +} EFI_IP6_ICMP_TYPE; + +/// +/// EFI_IP6_MODE_DATA +/// +typedef struct { + /// + /// Set to TRUE after this EFI IPv6 Protocol instance is started. + /// All other fields in this structure are undefined until this field is TRUE. + /// Set to FALSE when the EFI IPv6 Protocol instance is stopped. + /// + BOOLEAN IsStarted; + /// + /// The maximum packet size, in bytes, of the packet which the upper layer driver could feed. + /// + UINT32 MaxPacketSize; + /// + /// Current configuration settings. Undefined until IsStarted is TRUE. + /// + EFI_IP6_CONFIG_DATA ConfigData; + /// + /// Set to TRUE when the EFI IPv6 Protocol instance is configured. + /// The instance is configured when it has a station address and + /// corresponding prefix length. + /// Set to FALSE when the EFI IPv6 Protocol instance is not configured. + /// + BOOLEAN IsConfigured; + /// + /// Number of configured IPv6 addresses on this interface. + /// + UINT32 AddressCount; + /// + /// List of currently configured IPv6 addresses and corresponding + /// prefix lengths assigned to this interface. It is caller's + /// responsibility to free this buffer. + /// + EFI_IP6_ADDRESS_INFO *AddressList; + /// + /// Number of joined multicast groups. Undefined until + /// IsConfigured is TRUE. + /// + UINT32 GroupCount; + /// + /// List of joined multicast group addresses. It is caller's + /// responsibility to free this buffer. Undefined until + /// IsConfigured is TRUE. + /// + EFI_IPv6_ADDRESS *GroupTable; + /// + /// Number of entries in the routing table. Undefined until + /// IsConfigured is TRUE. + /// + UINT32 RouteCount; + /// + /// Routing table entries. It is caller's responsibility to free this buffer. + /// + EFI_IP6_ROUTE_TABLE *RouteTable; + /// + /// Number of entries in the neighbor cache. Undefined until + /// IsConfigured is TRUE. + /// + UINT32 NeighborCount; + /// + /// Neighbor cache entries. It is caller's responsibility to free this + /// buffer. Undefined until IsConfigured is TRUE. + /// + EFI_IP6_NEIGHBOR_CACHE *NeighborCache; + /// + /// Number of entries in the prefix table. Undefined until + /// IsConfigured is TRUE. + /// + UINT32 PrefixCount; + /// + /// On-link Prefix table entries. It is caller's responsibility to free this + /// buffer. Undefined until IsConfigured is TRUE. + /// + EFI_IP6_ADDRESS_INFO *PrefixTable; + /// + /// Number of entries in the supported ICMP types list. + /// + UINT32 IcmpTypeCount; + /// + /// Array of ICMP types and codes that are supported by this EFI + /// IPv6 Protocol driver. It is caller's responsibility to free this + /// buffer. + /// + EFI_IP6_ICMP_TYPE *IcmpTypeList; +} EFI_IP6_MODE_DATA; + +/// +/// EFI_IP6_HEADER +/// The fields in the IPv6 header structure are defined in the Internet +/// Protocol version6 specification. +/// +#pragma pack(1) +typedef struct _EFI_IP6_HEADER { + UINT8 TrafficClassH:4; + UINT8 Version:4; + UINT8 FlowLabelH:4; + UINT8 TrafficClassL:4; + UINT16 FlowLabelL; + UINT16 PayloadLength; + UINT8 NextHeader; + UINT8 HopLimit; + EFI_IPv6_ADDRESS SourceAddress; + EFI_IPv6_ADDRESS DestinationAddress; +} EFI_IP6_HEADER; +#pragma pack() + +/// +/// EFI_IP6_FRAGMENT_DATA +/// describes the location and length of the IPv6 packet +/// fragment to transmit or that has been received. +/// +typedef struct _EFI_IP6_FRAGMENT_DATA { + UINT32 FragmentLength; ///< Length of fragment data. This field may not be set to zero. + VOID *FragmentBuffer; ///< Pointer to fragment data. This field may not be set to NULL. +} EFI_IP6_FRAGMENT_DATA; + +/// +/// EFI_IP6_RECEIVE_DATA +/// +typedef struct _EFI_IP6_RECEIVE_DATA { + /// + /// Time when the EFI IPv6 Protocol driver accepted the packet. + /// Ignored if it is zero. + /// + EFI_TIME TimeStamp; + /// + /// After this event is signaled, the receive data structure is released + /// and must not be referenced. + /// + EFI_EVENT RecycleSignal; + /// + ///Length of the IPv6 packet headers, including both the IPv6 + ///header and any extension headers. + /// + UINT32 HeaderLength; + /// + /// Pointer to the IPv6 packet header. If the IPv6 packet was + /// fragmented, this argument is a pointer to the header in the first + /// fragment. + /// + EFI_IP6_HEADER *Header; + /// + /// Sum of the lengths of IPv6 packet buffers in FragmentTable. May + /// be zero. + /// + UINT32 DataLength; + /// + /// Number of IPv6 payload fragments. May be zero. + /// + UINT32 FragmentCount; + /// + /// Array of payload fragment lengths and buffer pointers. + /// + EFI_IP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_IP6_RECEIVE_DATA; + +/// +/// EFI_IP6_OVERRIDE_DATA +/// The information and flags in the override data structure will override +/// default parameters or settings for one Transmit() function call. +/// +typedef struct _EFI_IP6_OVERRIDE_DATA { + UINT8 Protocol; ///< Protocol type override. + UINT8 HopLimit; ///< Hop-Limit override. + UINT32 FlowLabel; ///< Flow-Label override. +} EFI_IP6_OVERRIDE_DATA; + +/// +/// EFI_IP6_TRANSMIT_DATA +/// +typedef struct _EFI_IP6_TRANSMIT_DATA { + /// + /// The destination IPv6 address. If it is unspecified, + /// ConfigData.DestinationAddress will be used instead. + /// + EFI_IPv6_ADDRESS DestinationAddress; + /// + /// If not NULL, the IPv6 transmission control override data. + /// + EFI_IP6_OVERRIDE_DATA *OverrideData; + /// + /// Total length in byte of the IPv6 extension headers specified in + /// ExtHdrs. + /// + UINT32 ExtHdrsLength; + /// + /// Pointer to the IPv6 extension headers. The IP layer will append + /// the required extension headers if they are not specified by + /// ExtHdrs. Ignored if ExtHdrsLength is zero. + /// + VOID *ExtHdrs; + /// + /// The protocol of first extension header in ExtHdrs. Ignored if + /// ExtHdrsLength is zero. + /// + UINT8 NextHeader; + /// + /// Total length in bytes of the FragmentTable data to transmit. + /// + UINT32 DataLength; + /// + /// Number of entries in the fragment data table. + /// + UINT32 FragmentCount; + /// + /// Start of the fragment data table. + /// + EFI_IP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_IP6_TRANSMIT_DATA; + +/// +/// EFI_IP6_COMPLETION_TOKEN +/// structures are used for both transmit and receive operations. +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by + /// the EFI IPv6 Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// - EFI_SUCCESS: The receive or transmit completed + /// successfully. + /// - EFI_ABORTED: The receive or transmit was aborted + /// - EFI_TIMEOUT: The transmit timeout expired. + /// - EFI_ICMP_ERROR: An ICMP error packet was received. + /// - EFI_DEVICE_ERROR: An unexpected system or network + /// error occurred. + /// - EFI_SECURITY_VIOLATION: The transmit or receive was + /// failed because of an IPsec policy check. + /// - EFI_NO_MEDIA: There was a media error. + /// + EFI_STATUS Status; + union { + /// + /// When the Token is used for receiving, RxData is a pointer to the EFI_IP6_RECEIVE_DATA. + /// + EFI_IP6_RECEIVE_DATA *RxData; + /// + /// When the Token is used for transmitting, TxData is a pointer to the EFI_IP6_TRANSMIT_DATA. + /// + EFI_IP6_TRANSMIT_DATA *TxData; + } Packet; +} EFI_IP6_COMPLETION_TOKEN; + +/** + Gets the current operational settings for this instance of the EFI IPv6 Protocol driver. + + The GetModeData() function returns the current operational mode data for this driver instance. + The data fields in EFI_IP6_MODE_DATA are read only. This function is used optionally to + retrieve the operational mode data of underlying networks or drivers.. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[out] Ip6ModeData Pointer to the EFI IPv6 Protocol mode data structure. + @param[out] MnpConfigData Pointer to the managed network configuration data structure. + @param[out] SnpModeData Pointer to the simple network mode data structure. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_GET_MODE_DATA)( + IN EFI_IP6_PROTOCOL *This, + OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + +/** + Assigns an IPv6 address and subnet mask to this EFI IPv6 Protocol driver instance. + + The Configure() function is used to set, change, or reset the operational parameters and filter + settings for this EFI IPv6 Protocol instance. Until these parameters have been set, no network traffic + can be sent or received by this instance. Once the parameters have been reset (by calling this + function with Ip6ConfigData set to NULL), no more traffic can be sent or received until these + parameters have been set again. Each EFI IPv6 Protocol instance can be started and stopped + independently of each other by enabling or disabling their receive filter settings with the + Configure() function. + + If Ip6ConfigData.StationAddress is a valid non-zero IPv6 unicast address, it is required + to be one of the currently configured IPv6 addresses list in the EFI IPv6 drivers, or else + EFI_INVALID_PARAMETER will be returned. If Ip6ConfigData.StationAddress is + unspecified, the IPv6 driver will bind a source address according to the source address selection + algorithm. Clients could frequently call GetModeData() to check get currently configured IPv6 + address list in the EFI IPv6 driver. If both Ip6ConfigData.StationAddress and + Ip6ConfigData.Destination are unspecified, when transmitting the packet afterwards, the + source address filled in each outgoing IPv6 packet is decided based on the destination of this packet. . + + If operational parameters are reset or changed, any pending transmit and receive requests will be + cancelled. Their completion token status will be set to EFI_ABORTED and their events will be + signaled. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] Ip6ConfigData Pointer to the EFI IPv6 Protocol configuration data structure. + + @retval EFI_SUCCESS The driver instance was successfully opened. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Ip6ConfigData.StationAddress is neither zero nor + a unicast IPv6 address. + - Ip6ConfigData.StationAddress is neither zero nor + one of the configured IP addresses in the EFI IPv6 driver. + - Ip6ConfigData.DefaultProtocol is illegal. + @retval EFI_OUT_OF_RESOURCES The EFI IPv6 Protocol driver instance data could not be allocated. + @retval EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for + this instance, but no source address was available for use. + @retval EFI_ALREADY_STARTED The interface is already open and must be stopped before the IPv6 + address or prefix length can be changed. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI IPv6 + Protocol driver instance is not opened. + @retval EFI_UNSUPPORTED Default protocol specified through + Ip6ConfigData.DefaulProtocol isn't supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CONFIGURE)( + IN EFI_IP6_PROTOCOL *This, + IN EFI_IP6_CONFIG_DATA *Ip6ConfigData OPTIONAL + ); + +/** + Joins and leaves multicast groups. + + The Groups() function is used to join and leave multicast group sessions. Joining a group will + enable reception of matching multicast packets. Leaving a group will disable reception of matching + multicast packets. Source-Specific Multicast isn't required to be supported. + + If JoinFlag is FALSE and GroupAddress is NULL, all joined groups will be left. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] JoinFlag Set to TRUE to join the multicast group session and FALSE to leave. + @param[in] GroupAddress Pointer to the IPv6 multicast address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following is TRUE: + - This is NULL. + - JoinFlag is TRUE and GroupAddress is NULL. + - GroupAddress is not NULL and *GroupAddress is + not a multicast IPv6 address. + - GroupAddress is not NULL and *GroupAddress is in the + range of SSM destination address. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_OUT_OF_RESOURCES System resources could not be allocated. + @retval EFI_UNSUPPORTED This EFI IPv6 Protocol implementation does not support multicast groups. + @retval EFI_ALREADY_STARTED The group address is already in the group table (when + JoinFlag is TRUE). + @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_GROUPS)( + IN EFI_IP6_PROTOCOL *This, + IN BOOLEAN JoinFlag, + IN EFI_IPv6_ADDRESS *GroupAddress OPTIONAL + ); + +/** + Adds and deletes routing table entries. + + The Routes() function adds a route to or deletes a route from the routing table. + + Routes are determined by comparing the leftmost PrefixLength bits of Destination with + the destination IPv6 address arithmetically. The gateway address must be on the same subnet as the + configured station address. + + The default route is added with Destination and PrefixLegth both set to all zeros. The + default route matches all destination IPv6 addresses that do not match any other routes. + + All EFI IPv6 Protocol instances share a routing table. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] DeleteRoute Set to TRUE to delete this route from the routing table. Set to + FALSE to add this route to the routing table. Destination, + PrefixLength and Gateway are used as the key to each + route entry. + @param[in] Destination The address prefix of the subnet that needs to be routed. + @param[in] PrefixLength The prefix length of Destination. Ignored if Destination + is NULL. + @param[in] GatewayAddress The unicast gateway IPv6 address for this route. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The driver instance has not been started. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - When DeleteRoute is TRUE, both Destination and + GatewayAddress are NULL. + - When DeleteRoute is FALSE, either Destination or + GatewayAddress is NULL. + - *GatewayAddress is not a valid unicast IPv6 address. + - *GatewayAddress is one of the local configured IPv6 + addresses. + @retval EFI_OUT_OF_RESOURCES Could not add the entry to the routing table. + @retval EFI_NOT_FOUND This route is not in the routing table (when DeleteRoute is TRUE). + @retval EFI_ACCESS_DENIED The route is already defined in the routing table (when + DeleteRoute is FALSE). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_ROUTES)( + IN EFI_IP6_PROTOCOL *This, + IN BOOLEAN DeleteRoute, + IN EFI_IPv6_ADDRESS *Destination OPTIONAL, + IN UINT8 PrefixLength, + IN EFI_IPv6_ADDRESS *GatewayAddress OPTIONAL + ); + +/** + Add or delete Neighbor cache entries. + + The Neighbors() function is used to add, update, or delete an entry from neighbor cache. + IPv6 neighbor cache entries are typically inserted and updated by the network protocol driver as + network traffic is processed. Most neighbor cache entries will time out and be deleted if the network + traffic stops. Neighbor cache entries that were inserted by Neighbors() may be static (will not + timeout) or dynamic (will time out). + + The implementation should follow the neighbor cache timeout mechanism which is defined in + RFC4861. The default neighbor cache timeout value should be tuned for the expected network + environment + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] DeleteFlag Set to TRUE to delete the specified cache entry, set to FALSE to + add (or update, if it already exists and Override is TRUE) the + specified cache entry. TargetIp6Address is used as the key + to find the requested cache entry. + @param[in] TargetIp6Address Pointer to Target IPv6 address. + @param[in] TargetLinkAddress Pointer to link-layer address of the target. Ignored if NULL. + @param[in] Timeout Time in 100-ns units that this entry will remain in the neighbor + cache, it will be deleted after Timeout. A value of zero means that + the entry is permanent. A non-zero value means that the entry is + dynamic. + @param[in] Override If TRUE, the cached link-layer address of the matching entry will + be overridden and updated; if FALSE, EFI_ACCESS_DENIED + will be returned if a corresponding cache entry already existed. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - TargetIpAddress is NULL. + - *TargetLinkAddress is invalid when not NULL. + - *TargetIpAddress is not a valid unicast IPv6 address. + - *TargetIpAddress is one of the local configured IPv6 + addresses. + @retval EFI_OUT_OF_RESOURCES Could not add the entry to the neighbor cache. + @retval EFI_NOT_FOUND This entry is not in the neighbor cache (when DeleteFlag is + TRUE or when DeleteFlag is FALSE while + TargetLinkAddress is NULL.). + @retval EFI_ACCESS_DENIED The to-be-added entry is already defined in the neighbor cache, + and that entry is tagged as un-overridden (when DeleteFlag + is FALSE). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_NEIGHBORS)( + IN EFI_IP6_PROTOCOL *This, + IN BOOLEAN DeleteFlag, + IN EFI_IPv6_ADDRESS *TargetIp6Address, + IN EFI_MAC_ADDRESS *TargetLinkAddress, + IN UINT32 Timeout, + IN BOOLEAN Override + ); + +/** + Places outgoing data packets into the transmit queue. + + The Transmit() function places a sending request in the transmit queue of this + EFI IPv6 Protocol instance. Whenever the packet in the token is sent out or some + errors occur, the event in the token will be signaled and the status is updated. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] Token Pointer to the transmit token. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NO_MAPPING The IPv6 driver was responsible for choosing a source address for + this transmission, but no source address was available for use. + @retval EFI_INVALID_PARAMETER One or more of the following is TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + - Token.Packet.TxData is NULL. + - Token.Packet.ExtHdrsLength is not zero and Token.Packet.ExtHdrs is NULL. + - Token.Packet.FragmentCount is zero. + - One or more of the Token.Packet.TxData.FragmentTable[].FragmentLength fields is zero. + - One or more of the Token.Packet.TxData.FragmentTable[].FragmentBuffer fields is NULL. + - Token.Packet.TxData.DataLength is zero or not equal to the sum of fragment lengths. + - Token.Packet.TxData.DestinationAddress is non-zero when DestinationAddress is configured as + non-zero when doing Configure() for this EFI IPv6 protocol instance. + - Token.Packet.TxData.DestinationAddress is unspecified when DestinationAddress is unspecified + when doing Configure() for this EFI IPv6 protocol instance. + @retval EFI_ACCESS_DENIED The transmit completion token with the same Token.Event + was already in the transmit queue. + @retval EFI_NOT_READY The completion token could not be queued because the transmit + queue is full. + @retval EFI_NOT_FOUND Not route is found to destination address. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data. + @retval EFI_BUFFER_TOO_SMALL Token.Packet.TxData.TotalDataLength is too + short to transmit. + @retval EFI_BAD_BUFFER_SIZE If Token.Packet.TxData.DataLength is beyond the + maximum that which can be described through the Fragment Offset + field in Fragment header when performing fragmentation. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_TRANSMIT)( + IN EFI_IP6_PROTOCOL *This, + IN EFI_IP6_COMPLETION_TOKEN *Token + ); + +/** + Places a receiving request into the receiving queue. + + The Receive() function places a completion token into the receive packet queue. + This function is always asynchronous. + + The Token.Event field in the completion token must be filled in by the caller + and cannot be NULL. When the receive operation completes, the EFI IPv6 Protocol + driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event + is signaled. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] Token Pointer to a token that is associated with the receive data descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI IPv6 Protocol instance has not been started. + @retval EFI_NO_MAPPING When IP6 driver responsible for binding source address to this instance, + while no source address is available for use. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system + resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + The EFI IPv6 Protocol instance has been reset to startup defaults. + @retval EFI_ACCESS_DENIED The receive completion token with the same Token.Event was already + in the receive queue. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_RECEIVE)( + IN EFI_IP6_PROTOCOL *This, + IN EFI_IP6_COMPLETION_TOKEN *Token + ); + +/** + Abort an asynchronous transmit or receive request. + + The Cancel() function is used to abort a pending transmit or receive request. + If the token is in the transmit or receive request queues, after calling this + function, Token->Status will be set to EFI_ABORTED and then Token->Event will + be signaled. If the token is not in one of the queues, which usually means the + asynchronous operation has completed, this function will not signal the token + and EFI_NOT_FOUND is returned. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + @param[in] Token Pointer to a token that has been issued by + EFI_IP6_PROTOCOL.Transmit() or + EFI_IP6_PROTOCOL.Receive(). If NULL, all pending + tokens are aborted. Type EFI_IP6_COMPLETION_TOKEN is + defined in EFI_IP6_PROTOCOL.Transmit(). + + @retval EFI_SUCCESS The asynchronous I/O request was aborted and + Token->Event was signaled. When Token is NULL, all + pending requests were aborted and their events were signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was + not found in the transmit or receive queue. It has either completed + or was not issued by Transmit() and Receive(). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CANCEL)( + IN EFI_IP6_PROTOCOL *This, + IN EFI_IP6_COMPLETION_TOKEN *Token OPTIONAL + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function polls for incoming data packets and processes outgoing data + packets. Network drivers and applications can call the EFI_IP6_PROTOCOL.Poll() + function to increase the rate that data packets are moved between the communications + device and the transmit and receive queues. + + In some systems the periodic timer event may not poll the underlying communications + device fast enough to transmit and/or receive all data packets without missing + incoming packets or dropping outgoing packets. Drivers and applications that are + experiencing packet loss should try calling the EFI_IP6_PROTOCOL.Poll() function + more often. + + @param[in] This Pointer to the EFI_IP6_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI IPv6 Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY No incoming or outgoing data is processed. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_POLL)( + IN EFI_IP6_PROTOCOL *This + ); + +/// +/// The EFI IPv6 Protocol implements a simple packet-oriented interface that can be +/// used by drivers, daemons, and applications to transmit and receive network packets. +/// +struct _EFI_IP6_PROTOCOL { + EFI_IP6_GET_MODE_DATA GetModeData; + EFI_IP6_CONFIGURE Configure; + EFI_IP6_GROUPS Groups; + EFI_IP6_ROUTES Routes; + EFI_IP6_NEIGHBORS Neighbors; + EFI_IP6_TRANSMIT Transmit; + EFI_IP6_RECEIVE Receive; + EFI_IP6_CANCEL Cancel; + EFI_IP6_POLL Poll; +}; + +extern EFI_GUID gEfiIp6ServiceBindingProtocolGuid; +extern EFI_GUID gEfiIp6ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6Config.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6Config.h new file mode 100644 index 0000000000..fe93ba24e8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Ip6Config.h @@ -0,0 +1,368 @@ +/** @file + This file provides a definition of the EFI IPv6 Configuration + Protocol. + +Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __EFI_IP6CONFIG_PROTOCOL_H__ +#define __EFI_IP6CONFIG_PROTOCOL_H__ + +#include + +#define EFI_IP6_CONFIG_PROTOCOL_GUID \ + { \ + 0x937fe521, 0x95ae, 0x4d1a, {0x89, 0x29, 0x48, 0xbc, 0xd9, 0x0a, 0xd3, 0x1a } \ + } + +typedef struct _EFI_IP6_CONFIG_PROTOCOL EFI_IP6_CONFIG_PROTOCOL; + +/// +/// EFI_IP6_CONFIG_DATA_TYPE +/// +typedef enum { + /// + /// The interface information of the communication + /// device this EFI IPv6 Configuration Protocol instance manages. + /// This type of data is read only.The corresponding Data is of type + /// EFI_IP6_CONFIG_INTERFACE_INFO. + /// + Ip6ConfigDataTypeInterfaceInfo, + /// + /// The alternative interface ID for the + /// communication device this EFI IPv6 Configuration Protocol + /// instance manages if the link local IPv6 address generated from + /// the interfaced ID based on the default source the EFI IPv6 + /// Protocol uses is a duplicate address. The length of the interface + /// ID is 64 bit. The corresponding Data is of type + /// EFI_IP6_CONFIG_INTERFACE_ID. + /// + Ip6ConfigDataTypeAltInterfaceId, + /// + /// The general configuration policy for the EFI IPv6 network + /// stack running on the communication device this EFI IPv6 + /// Configuration Protocol instance manages. The policy will affect + /// other configuration settings. The corresponding Data is of type + /// EFI_IP6_CONFIG_POLICY. + /// + Ip6ConfigDataTypePolicy, + /// + /// The number of consecutive + /// Neighbor Solicitation messages sent while performing Duplicate + /// Address Detection on a tentative address. A value of zero + /// indicates that Duplicate Address Detection will not be performed + /// on tentative addresses. The corresponding Data is of type + /// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS. + /// + Ip6ConfigDataTypeDupAddrDetectTransmits, + /// + /// The station addresses set manually for the EFI + /// IPv6 network stack. It is only configurable when the policy is + /// Ip6ConfigPolicyManual. The corresponding Data is a + /// pointer to an array of EFI_IPv6_ADDRESS instances. When + /// DataSize is 0 and Data is NULL, the existing configuration + /// is cleared from the EFI IPv6 Configuration Protocol instance. + /// + Ip6ConfigDataTypeManualAddress, + /// + /// The gateway addresses set manually for the EFI IPv6 + /// network stack running on the communication device this EFI + /// IPv6 Configuration Protocol manages. It is not configurable when + /// the policy is Ip6ConfigPolicyAutomatic. The gateway + /// addresses must be unicast IPv6 addresses. The corresponding + /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances. + /// When DataSize is 0 and Data is NULL, the existing configuration + /// is cleared from the EFI IPv6 Configuration Protocol instance. + /// + Ip6ConfigDataTypeGateway, + /// + /// The DNS server list for the EFI IPv6 network stack + /// running on the communication device this EFI IPv6 + /// Configuration Protocol manages. It is not configurable when the + /// policy is Ip6ConfigPolicyAutomatic.The DNS server + /// addresses must be unicast IPv6 addresses. The corresponding + /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances. + /// When DataSize is 0 and Data is NULL, the existing configuration + /// is cleared from the EFI IPv6 Configuration Protocol instance. + /// + Ip6ConfigDataTypeDnsServer, + /// + /// The number of this enumeration memebers. + /// + Ip6ConfigDataTypeMaximum +} EFI_IP6_CONFIG_DATA_TYPE; + +/// +/// EFI_IP6_CONFIG_INTERFACE_INFO +/// describes the operational state of the interface this +/// EFI IPv6 Configuration Protocol instance manages. +/// +typedef struct { + /// + /// The name of the interface. It is a NULL-terminated string. + /// + CHAR16 Name[32]; + /// + /// The interface type of the network interface. + /// + UINT8 IfType; + /// + /// The size, in bytes, of the network interface's hardware address. + /// + UINT32 HwAddressSize; + /// + /// The hardware address for the network interface. + /// + EFI_MAC_ADDRESS HwAddress; + /// + /// Number of EFI_IP6_ADDRESS_INFO structures pointed to by AddressInfo. + /// + UINT32 AddressInfoCount; + /// + /// Pointer to an array of EFI_IP6_ADDRESS_INFO instances + /// which contain the local IPv6 addresses and the corresponding + /// prefix length information. Set to NULL if AddressInfoCount + /// is zero. + /// + EFI_IP6_ADDRESS_INFO *AddressInfo; + /// + /// Number of route table entries in the following RouteTable. + /// + UINT32 RouteCount; + /// + /// The route table of the IPv6 network stack runs on this interface. + /// Set to NULL if RouteCount is zero. + /// + EFI_IP6_ROUTE_TABLE *RouteTable; +} EFI_IP6_CONFIG_INTERFACE_INFO; + +/// +/// EFI_IP6_CONFIG_INTERFACE_ID +/// describes the 64-bit interface ID. +/// +typedef struct { + UINT8 Id[8]; +} EFI_IP6_CONFIG_INTERFACE_ID; + +/// +/// EFI_IP6_CONFIG_POLICY +/// defines the general configuration policy the EFI IPv6 +/// Configuration Protocol supports. +/// +typedef enum { + /// + /// Under this policy, the IpI6ConfigDataTypeManualAddress, + /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer + /// configuration data are required to be set manually. + /// The EFI IPv6 Protocol will get all required configuration + /// such as address, prefix and gateway settings from the EFI + /// IPv6 Configuration protocol. + /// + Ip6ConfigPolicyManual, + /// + /// Under this policy, the IpI6ConfigDataTypeManualAddress, + /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer + /// configuration data are not allowed to set via SetData(). + /// All of these configurations are retrieved from some auto + /// configuration mechanism. + /// The EFI IPv6 Protocol will use the IPv6 stateless address + /// autoconfiguration mechanism and/or the IPv6 stateful address + /// autoconfiguration mechanism described in the related RFCs to + /// get address and other configuration information + /// + Ip6ConfigPolicyAutomatic +} EFI_IP6_CONFIG_POLICY; + +/// +/// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS +/// describes the number of consecutive Neighbor Solicitation messages sent +/// while performing Duplicate Address Detection on a tentative address. +/// The default value for a newly detected communication device is 1. +/// +typedef struct { + UINT32 DupAddrDetectTransmits; ///< The number of consecutive Neighbor Solicitation messages sent. +} EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS; + +/// +/// EFI_IP6_CONFIG_MANUAL_ADDRESS +/// is used to set the station address information for the EFI IPv6 network +/// stack manually when the policy is Ip6ConfigPolicyManual. +/// +typedef struct { + EFI_IPv6_ADDRESS Address; ///< The IPv6 unicast address. + BOOLEAN IsAnycast; ///< Set to TRUE if Address is anycast. + UINT8 PrefixLength; ///< The length, in bits, of the prefix associated with this Address. +} EFI_IP6_CONFIG_MANUAL_ADDRESS; + + +/** + Set the configuration for the EFI IPv6 network stack running on the communication + device this EFI IPv6 Configuration Protocol instance manages. + + This function is used to set the configuration data of type DataType for the EFI + IPv6 network stack running on the communication device this EFI IPv6 Configuration + Protocol instance manages. + + The DataSize is used to calculate the count of structure instances in the Data for + some DataType that multiple structure instances are allowed. + + This function is always non-blocking. When setting some type of configuration data, + an asynchronous process is invoked to check the correctness of the data, such as + doing Duplicate Address Detection on the manually set local IPv6 addresses. + EFI_NOT_READY is returned immediately to indicate that such an asynchronous process + is invoked and the process is not finished yet. The caller willing to get the result + of the asynchronous process is required to call RegisterDataNotify() to register an + event on the specified configuration data. Once the event is signaled, the caller + can call GetData() to get back the configuration data in order to know the result. + For other types of configuration data that do not require an asynchronous configuration + process, the result of the operation is immediately returned. + + @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to set. + @param[in] DataSize Size of the buffer pointed to by Data in bytes. + @param[in] Data The data buffer to set. The type of the data buffer is + associated with the DataType. + + @retval EFI_SUCCESS The specified configuration data for the EFI IPv6 + network stack is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - One or more fields in Data and DataSize do not match the + requirement of the data type indicated by DataType. + @retval EFI_WRITE_PROTECTED The specified configuration data is read-only or the specified + configuration data can not be set under the current policy + @retval EFI_ACCESS_DENIED Another set operation on the specified configuration + data is already in process. + @retval EFI_NOT_READY An asynchronous process is invoked to set the specified + configuration data and the process is not finished yet. + @retval EFI_BAD_BUFFER_SIZE The DataSize does not match the size of the type + indicated by DataType. + @retval EFI_UNSUPPORTED This DataType is not supported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_DEVICE_ERROR An unexpected system error or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CONFIG_SET_DATA)( + IN EFI_IP6_CONFIG_PROTOCOL *This, + IN EFI_IP6_CONFIG_DATA_TYPE DataType, + IN UINTN DataSize, + IN VOID *Data + ); + +/** + Get the configuration data for the EFI IPv6 network stack running on the communication + device this EFI IPv6 Configuration Protocol instance manages. + + This function returns the configuration data of type DataType for the EFI IPv6 network + stack running on the communication device this EFI IPv6 Configuration Protocol instance + manages. + + The caller is responsible for allocating the buffer used to return the specified + configuration data and the required size will be returned to the caller if the size of + the buffer is too small. + + EFI_NOT_READY is returned if the specified configuration data is not ready due to an + already in progress asynchronous configuration process. The caller can call RegisterDataNotify() + to register an event on the specified configuration data. Once the asynchronous configuration + process is finished, the event will be signaled and a subsequent GetData() call will return + the specified configuration data. + + @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to get. + @param[in,out] DataSize On input, in bytes, the size of Data. On output, in bytes, the + size of buffer required to store the specified configuration data. + @param[in] Data The data buffer in which the configuration data is returned. The + type of the data buffer is associated with the DataType. + + @retval EFI_SUCCESS The specified configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE: + - This is NULL. + - DataSize is NULL. + - Data is NULL if *DataSize is not zero. + @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the specified configuration data + and the required size is returned in DataSize. + @retval EFI_NOT_READY The specified configuration data is not ready due to an already in + progress asynchronous configuration process. + @retval EFI_NOT_FOUND The specified configuration data is not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CONFIG_GET_DATA)( + IN EFI_IP6_CONFIG_PROTOCOL *This, + IN EFI_IP6_CONFIG_DATA_TYPE DataType, + IN OUT UINTN *DataSize, + IN VOID *Data OPTIONAL + ); + +/** + Register an event that is to be signaled whenever a configuration process on the specified + configuration data is done. + + This function registers an event that is to be signaled whenever a configuration process + on the specified configuration data is done. An event can be registered for different DataType + simultaneously and the caller is responsible for determining which type of configuration data + causes the signaling of the event in such case. + + @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to unregister the event for. + @param[in] Event The event to register. + + @retval EFI_SUCCESS The notification event for the specified configuration data is + registered. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_UNSUPPORTED The configuration data type specified by DataType is not + supported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The Event is already registered for the DataType. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CONFIG_REGISTER_NOTIFY)( + IN EFI_IP6_CONFIG_PROTOCOL *This, + IN EFI_IP6_CONFIG_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/** + Remove a previously registered event for the specified configuration data. + + This function removes a previously registered event for the specified configuration data. + + @param[in] This Pointer to the EFI_IP6_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to remove the previously registered event for. + @param[in] Event The event to unregister. + + @retval EFI_SUCCESS The event registered for the specified configuration data is removed. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_NOT_FOUND The Event has not been registered for the specified + DataType. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IP6_CONFIG_UNREGISTER_NOTIFY)( + IN EFI_IP6_CONFIG_PROTOCOL *This, + IN EFI_IP6_CONFIG_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/// +/// The EFI_IP6_CONFIG_PROTOCOL provides the mechanism to set and get various +/// types of configurations for the EFI IPv6 network stack. +/// +struct _EFI_IP6_CONFIG_PROTOCOL { + EFI_IP6_CONFIG_SET_DATA SetData; + EFI_IP6_CONFIG_GET_DATA GetData; + EFI_IP6_CONFIG_REGISTER_NOTIFY RegisterDataNotify; + EFI_IP6_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify; +}; + +extern EFI_GUID gEfiIp6ConfigProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSec.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSec.h new file mode 100644 index 0000000000..b51936c490 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSec.h @@ -0,0 +1,218 @@ +/** @file + EFI IPSEC Protocol Definition + The EFI_IPSEC_PROTOCOL is used to abstract the ability to deal with the individual + packets sent and received by the host and provide packet-level security for IP + datagram. + The EFI_IPSEC2_PROTOCOL is used to abstract the ability to deal with the individual + packets sent and received by the host and provide packet-level security for IP + datagram. In addition, it supports the Option (extension header) processing in + IPsec which doesn't support in EFI_IPSEC_PROTOCOL. It is also recommended to + use EFI_IPSEC2_PROTOCOL instead of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel + Mode. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + The EFI_IPSEC2_PROTOCOL is introduced in UEFI Specification 2.3D. + +**/ + +#ifndef __EFI_IPSEC_PROTOCOL_H__ +#define __EFI_IPSEC_PROTOCOL_H__ + +#include + +#define EFI_IPSEC_PROTOCOL_GUID \ + { \ + 0xdfb386f7, 0xe100, 0x43ad, {0x9c, 0x9a, 0xed, 0x90, 0xd0, 0x8a, 0x5e, 0x12 } \ + } + +#define EFI_IPSEC2_PROTOCOL_GUID \ + { \ + 0xa3979e64, 0xace8, 0x4ddc, {0xbc, 0x7, 0x4d, 0x66, 0xb8, 0xfd, 0x9, 0x77 } \ + } + +typedef struct _EFI_IPSEC_PROTOCOL EFI_IPSEC_PROTOCOL; +typedef struct _EFI_IPSEC2_PROTOCOL EFI_IPSEC2_PROTOCOL; + +/// +/// EFI_IPSEC_FRAGMENT_DATA +/// defines the instances of packet fragments. +/// +typedef struct _EFI_IPSEC_FRAGMENT_DATA { + UINT32 FragmentLength; + VOID *FragmentBuffer; +} EFI_IPSEC_FRAGMENT_DATA; + + +/** + Handles IPsec packet processing for inbound and outbound IP packets. + + The EFI_IPSEC_PROCESS process routine handles each inbound or outbound packet. + The behavior is that it can perform one of the following actions: + bypass the packet, discard the packet, or protect the packet. + + @param[in] This Pointer to the EFI_IPSEC_PROTOCOL instance. + @param[in] NicHandle Instance of the network interface. + @param[in] IpVer IPV4 or IPV6. + @param[in, out] IpHead Pointer to the IP Header. + @param[in] LastHead The protocol of the next layer to be processed by IPsec. + @param[in] OptionsBuffer Pointer to the options buffer. + @param[in] OptionsLength Length of the options buffer. + @param[in, out] FragmentTable Pointer to a list of fragments. + @param[in] FragmentCount Number of fragments. + @param[in] TrafficDirection Traffic direction. + @param[out] RecycleSignal Event for recycling of resources. + + @retval EFI_SUCCESS The packet was bypassed and all buffers remain the same. + @retval EFI_SUCCESS The packet was protected. + @retval EFI_ACCESS_DENIED The packet was discarded. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_PROCESS)( + IN EFI_IPSEC_PROTOCOL *This, + IN EFI_HANDLE NicHandle, + IN UINT8 IpVer, + IN OUT VOID *IpHead, + IN UINT8 *LastHead, + IN VOID *OptionsBuffer, + IN UINT32 OptionsLength, + IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable, + IN UINT32 *FragmentCount, + IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection, + OUT EFI_EVENT *RecycleSignal + ); + +/// +/// EFI_IPSEC_PROTOCOL +/// provides the ability for securing IP communications by authenticating +/// and/or encrypting each IP packet in a data stream. +// EFI_IPSEC_PROTOCOL can be consumed by both the IPv4 and IPv6 stack. +// A user can employ this protocol for IPsec package handling in both IPv4 +// and IPv6 environment. +/// +struct _EFI_IPSEC_PROTOCOL { + EFI_IPSEC_PROCESS Process; ///< Handle the IPsec message. + EFI_EVENT DisabledEvent; ///< Event signaled when the interface is disabled. + BOOLEAN DisabledFlag; ///< State of the interface. +}; + +/** + Handles IPsec processing for both inbound and outbound IP packets. Compare with + Process() in EFI_IPSEC_PROTOCOL, this interface has the capability to process + Option(Extension Header). + + The EFI_IPSEC2_PROCESS process routine handles each inbound or outbound packet. + The behavior is that it can perform one of the following actions: + bypass the packet, discard the packet, or protect the packet. + + @param[in] This Pointer to the EFI_IPSEC2_PROTOCOL instance. + @param[in] NicHandle Instance of the network interface. + @param[in] IpVer IP version.IPv4 or IPv6. + @param[in, out] IpHead Pointer to the IP Header it is either + the EFI_IP4_HEADER or EFI_IP6_HEADER. + On input, it contains the IP header. + On output, 1) in tunnel mode and the + traffic direction is inbound, the buffer + will be reset to zero by IPsec; 2) in + tunnel mode and the traffic direction + is outbound, the buffer will reset to + be the tunnel IP header.3) in transport + mode, the related fielders (like payload + length, Next header) in IP header will + be modified according to the condition. + @param[in, out] LastHead For IP4, it is the next protocol in IP + header. For IP6 it is the Next Header + of the last extension header. + @param[in, out] OptionsBuffer On input, it contains the options + (extensions header) to be processed by + IPsec. On output, 1) in tunnel mode and + the traffic direction is outbound, it + will be set to NULL, and that means this + contents was wrapped after inner header + and should not be concatenated after + tunnel header again; 2) in transport + mode and the traffic direction is inbound, + if there are IP options (extension headers) + protected by IPsec, IPsec will concatenate + the those options after the input options + (extension headers); 3) on other situations, + the output of contents of OptionsBuffer + might be same with input's. The caller + should take the responsibility to free + the buffer both on input and on output. + @param[in, out] OptionsLength On input, the input length of the options + buffer. On output, the output length of + the options buffer. + @param[in, out] FragmentTable Pointer to a list of fragments. On input, + these fragments contain the IP payload. + On output, 1) in tunnel mode and the traffic + direction is inbound, the fragments contain + the whole IP payload which is from the + IP inner header to the last byte of the + packet; 2) in tunnel mode and the traffic + direction is the outbound, the fragments + contains the whole encapsulated payload + which encapsulates the whole IP payload + between the encapsulated header and + encapsulated trailer fields. 3) in transport + mode and the traffic direction is inbound, + the fragments contains the IP payload + which is from the next layer protocol to + the last byte of the packet; 4) in transport + mode and the traffic direction is outbound, + the fragments contains the whole encapsulated + payload which encapsulates the next layer + protocol information between the encapsulated + header and encapsulated trailer fields. + @param[in, out] FragmentCount Number of fragments. + @param[in] TrafficDirection Traffic direction. + @param[out] RecycleSignal Event for recycling of resources. + + @retval EFI_SUCCESS The packet was processed by IPsec successfully. + @retval EFI_ACCESS_DENIED The packet was discarded. + @retval EFI_NOT_READY The IKE negotiation is invoked and the packet + was discarded. + @retval EFI_INVALID_PARAMETER One or more of following are TRUE: + If OptionsBuffer is NULL; + If OptionsLength is NULL; + If FragmentTable is NULL; + If FragmentCount is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_PROCESSEXT) ( + IN EFI_IPSEC2_PROTOCOL *This, + IN EFI_HANDLE NicHandle, + IN UINT8 IpVer, + IN OUT VOID *IpHead, + IN OUT UINT8 *LastHead, + IN OUT VOID **OptionsBuffer, + IN OUT UINT32 *OptionsLength, + IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable, + IN OUT UINT32 *FragmentCount, + IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection, + OUT EFI_EVENT *RecycleSignal + ); + +/// +/// EFI_IPSEC2_PROTOCOL +/// supports the Option (extension header) processing in IPsec which doesn't support +/// in EFI_IPSEC_PROTOCOL. It is also recommended to use EFI_IPSEC2_PROTOCOL instead +/// of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel Mode. +/// provides the ability for securing IP communications by authenticating and/or +/// encrypting each IP packet in a data stream. +/// +struct _EFI_IPSEC2_PROTOCOL { +EFI_IPSEC_PROCESSEXT ProcessExt; +EFI_EVENT DisabledEvent; +BOOLEAN DisabledFlag; +}; + +extern EFI_GUID gEfiIpSecProtocolGuid; +extern EFI_GUID gEfiIpSec2ProtocolGuid; +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSecConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSecConfig.h new file mode 100644 index 0000000000..78a201d4a4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IpSecConfig.h @@ -0,0 +1,801 @@ +/** @file + EFI IPsec Configuration Protocol Definition + The EFI_IPSEC_CONFIG_PROTOCOL provides the mechanism to set and retrieve security and + policy related information for the EFI IPsec protocol driver. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_IPSE_CCONFIG_PROTOCOL_H__ +#define __EFI_IPSE_CCONFIG_PROTOCOL_H__ + + +#define EFI_IPSEC_CONFIG_PROTOCOL_GUID \ + { \ + 0xce5e5929, 0xc7a3, 0x4602, {0xad, 0x9e, 0xc9, 0xda, 0xf9, 0x4e, 0xbf, 0xcf } \ + } + +typedef struct _EFI_IPSEC_CONFIG_PROTOCOL EFI_IPSEC_CONFIG_PROTOCOL; + +/// +/// EFI_IPSEC_CONFIG_DATA_TYPE +/// +typedef enum { + /// + /// The IPsec Security Policy Database (aka SPD) setting. In IPsec, + /// an essential element of Security Association (SA) processing is + /// underlying SPD that specifies what services are to be offered to + /// IP datagram and in what fashion. The SPD must be consulted + /// during the processing of all traffic (inbound and outbound), + /// including traffic not protected by IPsec, that traverses the IPsec + /// boundary. With this DataType, SetData() function is to set + /// the SPD entry information, which may add one new entry, delete + /// one existed entry or flush the whole database according to the + /// parameter values. The corresponding Data is of type + /// EFI_IPSEC_SPD_DATA + /// + IPsecConfigDataTypeSpd, + /// + /// The IPsec Security Association Database (aka SAD) setting. A + /// SA is a simplex connection that affords security services to the + /// traffic carried by it. Security services are afforded to an SA by the + /// use of AH, or ESP, but not both. The corresponding Data is of + /// type EFI_IPSEC_SAD_DATA. + /// + IPsecConfigDataTypeSad, + /// + /// The IPsec Peer Authorization Database (aka PAD) setting, which + /// provides the link between the SPD and a security association + /// management protocol. The PAD entry specifies the + /// authentication protocol (e.g. IKEv1, IKEv2) method used and the + /// authentication data. The corresponding Data is of type + /// EFI_IPSEC_PAD_DATA. + /// + IPsecConfigDataTypePad, + IPsecConfigDataTypeMaximum +} EFI_IPSEC_CONFIG_DATA_TYPE; + +/// +/// EFI_IP_ADDRESS_INFO +/// +typedef struct _EFI_IP_ADDRESS_INFO { + EFI_IP_ADDRESS Address; ///< The IPv4 or IPv6 address + UINT8 PrefixLength; ///< The length of the prefix associated with the Address. +} EFI_IP_ADDRESS_INFO; + + +/// +/// EFI_IPSEC_SPD_SELECTOR +/// +typedef struct _EFI_IPSEC_SPD_SELECTOR { + /// + /// Specifies the actual number of entries in LocalAddress. + /// + UINT32 LocalAddressCount; + /// + /// A list of ranges of IPv4 or IPv6 addresses, which refers to the + /// addresses being protected by IPsec policy. + /// + EFI_IP_ADDRESS_INFO *LocalAddress; + /// + /// Specifies the actual number of entries in RemoteAddress. + /// + UINT32 RemoteAddressCount; + /// + /// A list of ranges of IPv4 or IPv6 addresses, which are peer entities + /// to LocalAddress. + /// + EFI_IP_ADDRESS_INFO *RemoteAddress; + /// + /// Next layer protocol. Obtained from the IPv4 Protocol or the IPv6 + /// Next Header fields. The next layer protocol is whatever comes + /// after any IP extension headers that are present. A zero value is a + /// wildcard that matches any value in NextLayerProtocol field. + /// + UINT16 NextLayerProtocol; + /// + /// Local Port if the Next Layer Protocol uses two ports (as do TCP, + /// UDP, and others). A zero value is a wildcard that matches any + /// value in LocalPort field. + /// + UINT16 LocalPort; + /// + /// A designed port range size. The start port is LocalPort, and + /// the total number of ports is described by LocalPortRange. + /// This field is ignored if NextLayerProtocol does not use + /// ports. + /// + UINT16 LocalPortRange; + /// + /// Remote Port if the Next Layer Protocol uses two ports. A zero + /// value is a wildcard that matches any value in RemotePort field. + /// + UINT16 RemotePort; + /// + /// A designed port range size. The start port is RemotePort, and + /// the total number of ports is described by RemotePortRange. + /// This field is ignored if NextLayerProtocol does not use ports. + /// + UINT16 RemotePortRange; +} EFI_IPSEC_SPD_SELECTOR; + +/// +/// EFI_IPSEC_TRAFFIC_DIR +/// represents the directionality in an SPD entry. +/// +typedef enum { + /// + /// The EfiIPsecInBound refers to traffic entering an IPsec implementation via + /// the unprotected interface or emitted by the implementation on the unprotected + /// side of the boundary and directed towards the protected interface. + /// + EfiIPsecInBound, + /// + /// The EfiIPsecOutBound refers to traffic entering the implementation via + /// the protected interface, or emitted by the implementation on the protected side + /// of the boundary and directed toward the unprotected interface. + /// + EfiIPsecOutBound +} EFI_IPSEC_TRAFFIC_DIR; + +/// +/// EFI_IPSEC_ACTION +/// represents three possible processing choices. +/// +typedef enum { + /// + /// Refers to traffic that is not allowed to traverse the IPsec boundary. + /// + EfiIPsecActionDiscard, + /// + /// Refers to traffic that is allowed to cross the IPsec boundary + /// without protection. + /// + EfiIPsecActionBypass, + /// + /// Refers to traffic that is afforded IPsec protection, and for such + /// traffic the SPD must specify the security protocols to be + /// employed, their mode, security service options, and the + /// cryptographic algorithms to be used. + /// + EfiIPsecActionProtect +} EFI_IPSEC_ACTION; + +/// +/// EFI_IPSEC_SA_LIFETIME +/// defines the lifetime of an SA, which represents when a SA must be +/// replaced or terminated. A value of all 0 for each field removes +/// the limitation of a SA lifetime. +/// +typedef struct _EFI_IPSEC_SA_LIFETIME { + /// + /// The number of bytes to which the IPsec cryptographic algorithm + /// can be applied. For ESP, this is the encryption algorithm and for + /// AH, this is the authentication algorithm. The ByteCount + /// includes pad bytes for cryptographic operations. + /// + UINT64 ByteCount; + /// + /// A time interval in second that warns the implementation to + /// initiate action such as setting up a replacement SA. + /// + UINT64 SoftLifetime; + /// + /// A time interval in second when the current SA ends and is + /// destroyed. + /// + UINT64 HardLifetime; +} EFI_IPSEC_SA_LIFETIME; + +/// +/// EFI_IPSEC_MODE +/// There are two modes of IPsec operation: transport mode and tunnel mode. In +/// EfiIPsecTransport mode, AH and ESP provide protection primarily for next layer protocols; +/// In EfiIPsecTunnel mode, AH and ESP are applied to tunneled IP packets. +/// +typedef enum { + EfiIPsecTransport, + EfiIPsecTunnel +} EFI_IPSEC_MODE; + +/// +/// EFI_IPSEC_TUNNEL_DF_OPTION +/// The option of copying the DF bit from an outbound package to +/// the tunnel mode header that it emits, when traffic is carried +/// via a tunnel mode SA. This applies to SAs where both inner and +/// outer headers are IPv4. +/// +typedef enum { + EfiIPsecTunnelClearDf, ///< Clear DF bit from inner header. + EfiIPsecTunnelSetDf, ///< Set DF bit from inner header. + EfiIPsecTunnelCopyDf ///< Copy DF bit from inner header. +} EFI_IPSEC_TUNNEL_DF_OPTION; + +/// +/// EFI_IPSEC_TUNNEL_OPTION +/// +typedef struct _EFI_IPSEC_TUNNEL_OPTION { + /// + /// Local tunnel address when IPsec mode is EfiIPsecTunnel. + /// + EFI_IP_ADDRESS LocalTunnelAddress; + /// + /// Remote tunnel address when IPsec mode is EfiIPsecTunnel. + /// + EFI_IP_ADDRESS RemoteTunnelAddress; + /// + /// The option of copying the DF bit from an outbound package + /// to the tunnel mode header that it emits, when traffic is + /// carried via a tunnel mode SA. + /// + EFI_IPSEC_TUNNEL_DF_OPTION DF; +} EFI_IPSEC_TUNNEL_OPTION; + +/// +/// EFI_IPSEC_PROTOCOL_TYPE +/// +typedef enum { + EfiIPsecAH, ///< IP Authentication Header protocol which is specified in RFC 4302. + EfiIPsecESP ///< IP Encapsulating Security Payload which is specified in RFC 4303. +} EFI_IPSEC_PROTOCOL_TYPE; + +/// +/// EFI_IPSEC_PROCESS_POLICY +/// describes a policy list for traffic processing. +/// +typedef struct _EFI_IPSEC_PROCESS_POLICY { + /// + /// Extended Sequence Number. Is this SA using extended sequence + /// numbers. 64 bit counter is used if TRUE. + /// + BOOLEAN ExtSeqNum; + /// + /// A flag indicating whether overflow of the sequence number + /// counter should generate an auditable event and prevent + /// transmission of additional packets on the SA, or whether rollover + /// is permitted. + /// + BOOLEAN SeqOverflow; + /// + /// Is this SA using stateful fragment checking. TRUE represents + /// stateful fragment checking. + /// + BOOLEAN FragCheck; + /// + /// A time interval after which a SA must be replaced with a new SA + /// (and new SPI) or terminated. + /// + EFI_IPSEC_SA_LIFETIME SaLifetime; + /// + /// IPsec mode: tunnel or transport. + /// + EFI_IPSEC_MODE Mode; + /// + /// Tunnel Option. TunnelOption is ignored if Mode is EfiIPsecTransport. + /// + EFI_IPSEC_TUNNEL_OPTION *TunnelOption; + /// + /// IPsec protocol: AH or ESP + /// + EFI_IPSEC_PROTOCOL_TYPE Proto; + /// + /// Cryptographic algorithm type used for authentication. + /// + UINT8 AuthAlgoId; + /// + /// Cryptographic algorithm type used for encryption. EncAlgo is + /// NULL when IPsec protocol is AH. For ESP protocol, EncAlgo + /// can also be used to describe the algorithm if a combined mode + /// algorithm is used. + /// + UINT8 EncAlgoId; +} EFI_IPSEC_PROCESS_POLICY; + +/// +/// EFI_IPSEC_SA_ID +/// A triplet to identify an SA, consisting of the following members. +/// +typedef struct _EFI_IPSEC_SA_ID { + /// + /// Security Parameter Index (aka SPI). An arbitrary 32-bit value + /// that is used by a receiver to identity the SA to which an incoming + /// package should be bound. + /// + UINT32 Spi; + /// + /// IPsec protocol: AH or ESP + /// + EFI_IPSEC_PROTOCOL_TYPE Proto; + /// + /// Destination IP address. + /// + EFI_IP_ADDRESS DestAddress; +} EFI_IPSEC_SA_ID; + + +#define MAX_PEERID_LEN 128 + +/// +/// EFI_IPSEC_SPD_DATA +/// +typedef struct _EFI_IPSEC_SPD_DATA { + /// + /// A null-terminated ASCII name string which is used as a symbolic + /// identifier for an IPsec Local or Remote address. + /// + UINT8 Name[MAX_PEERID_LEN]; + /// + /// Bit-mapped list describing Populate from Packet flags. When + /// creating a SA, if PackageFlag bit is set to TRUE, instantiate + /// the selector from the corresponding field in the package that + /// triggered the creation of the SA, else from the value(s) in the + /// corresponding SPD entry. The PackageFlag bit setting for + /// corresponding selector field of EFI_IPSEC_SPD_SELECTOR: + /// Bit 0: EFI_IPSEC_SPD_SELECTOR.LocalAddress + /// Bit 1: EFI_IPSEC_SPD_SELECTOR.RemoteAddress + /// Bit 2: + /// EFI_IPSEC_SPD_SELECTOR.NextLayerProtocol + /// Bit 3: EFI_IPSEC_SPD_SELECTOR.LocalPort + /// Bit 4: EFI_IPSEC_SPD_SELECTOR.RemotePort + /// Others: Reserved. + /// + UINT32 PackageFlag; + /// + /// The traffic direction of data gram. + /// + EFI_IPSEC_TRAFFIC_DIR TrafficDirection; + /// + /// Processing choices to indicate which action is required by this + /// policy. + /// + EFI_IPSEC_ACTION Action; + /// + /// The policy and rule information for a SPD entry. + /// + EFI_IPSEC_PROCESS_POLICY *ProcessingPolicy; + /// + /// Specifies the actual number of entries in SaId list. + /// + UINTN SaIdCount; + /// + /// The SAD entry used for the traffic processing. The + /// existed SAD entry links indicate this is the manual key case. + /// + EFI_IPSEC_SA_ID SaId[1]; +} EFI_IPSEC_SPD_DATA; + +/// +/// EFI_IPSEC_AH_ALGO_INFO +/// The security algorithm selection for IPsec AH authentication. +/// The required authentication algorithm is specified in RFC 4305. +/// +typedef struct _EFI_IPSEC_AH_ALGO_INFO { + UINT8 AuthAlgoId; + UINTN AuthKeyLength; + VOID *AuthKey; +} EFI_IPSEC_AH_ALGO_INFO; + +/// +/// EFI_IPSEC_ESP_ALGO_INFO +/// The security algorithm selection for IPsec ESP encryption and authentication. +/// The required authentication algorithm is specified in RFC 4305. +/// EncAlgoId fields can also specify an ESP combined mode algorithm +/// (e.g. AES with CCM mode, specified in RFC 4309), which provides both +/// confidentiality and authentication services. +/// +typedef struct _EFI_IPSEC_ESP_ALGO_INFO { + UINT8 EncAlgoId; + UINTN EncKeyLength; + VOID *EncKey; + UINT8 AuthAlgoId; + UINTN AuthKeyLength; + VOID *AuthKey; +} EFI_IPSEC_ESP_ALGO_INFO; + +/// +/// EFI_IPSEC_ALGO_INFO +/// +typedef union { + EFI_IPSEC_AH_ALGO_INFO AhAlgoInfo; + EFI_IPSEC_ESP_ALGO_INFO EspAlgoInfo; +} EFI_IPSEC_ALGO_INFO; + +/// +/// EFI_IPSEC_SA_DATA +/// +typedef struct _EFI_IPSEC_SA_DATA { + /// + /// IPsec mode: tunnel or transport. + /// + EFI_IPSEC_MODE Mode; + /// + /// Sequence Number Counter. A 64-bit counter used to generate the + /// sequence number field in AH or ESP headers. + /// + UINT64 SNCount; + /// + /// Anti-Replay Window. A 64-bit counter and a bit-map used to + /// determine whether an inbound AH or ESP packet is a replay. + /// + UINT8 AntiReplayWindows; + /// + /// AH/ESP cryptographic algorithm, key and parameters. + /// + EFI_IPSEC_ALGO_INFO AlgoInfo; + /// + /// Lifetime of this SA. + /// + EFI_IPSEC_SA_LIFETIME SaLifetime; + /// + /// Any observed path MTU and aging variables. The Path MTU + /// processing is defined in section 8 of RFC 4301. + /// + UINT32 PathMTU; + /// + /// Link to one SPD entry. + /// + EFI_IPSEC_SPD_SELECTOR *SpdSelector; + /// + /// Indication of whether it's manually set or negotiated automatically. + /// If ManualSet is FALSE, the corresponding SA entry is inserted through + /// IKE protocol negotiation. + /// + BOOLEAN ManualSet; +} EFI_IPSEC_SA_DATA; + +/// +/// EFI_IPSEC_SA_DATA2 +/// +typedef struct _EFI_IPSEC_SA_DATA2 { + /// + /// IPsec mode: tunnel or transport + /// + EFI_IPSEC_MODE Mode; + /// + /// Sequence Number Counter. A 64-bit counter used to generate the sequence + /// number field in AH or ESP headers. + /// + UINT64 SNCount; + /// + /// Anti-Replay Window. A 64-bit counter and a bit-map used to determine + /// whether an inbound AH or ESP packet is a replay. + /// + UINT8 AntiReplayWindows; + /// + /// AH/ESP cryptographic algorithm, key and parameters. + /// + EFI_IPSEC_ALGO_INFO AlgoInfo; + /// + /// Lifetime of this SA. + /// + EFI_IPSEC_SA_LIFETIME SaLifetime; + /// + /// Any observed path MTU and aging variables. The Path MTU processing is + /// defined in section 8 of RFC 4301. + /// + UINT32 PathMTU; + /// + /// Link to one SPD entry + /// + EFI_IPSEC_SPD_SELECTOR *SpdSelector; + /// + /// Indication of whether it's manually set or negotiated automatically. + /// If ManualSet is FALSE, the corresponding SA entry is inserted through IKE + /// protocol negotiation + /// + BOOLEAN ManualSet; + /// + /// The tunnel header IP source address. + /// + EFI_IP_ADDRESS TunnelSourceAddress; + /// + /// The tunnel header IP destination address. + /// + EFI_IP_ADDRESS TunnelDestinationAddress; +} EFI_IPSEC_SA_DATA2; + + +/// +/// EFI_IPSEC_PAD_ID +/// specifies the identifier for PAD entry, which is also used for SPD lookup. +/// IpAddress Pointer to the IPv4 or IPv6 address range. +/// +typedef struct _EFI_IPSEC_PAD_ID { + /// + /// Flag to identify which type of PAD Id is used. + /// + BOOLEAN PeerIdValid; + union { + /// + /// Pointer to the IPv4 or IPv6 address range. + /// + EFI_IP_ADDRESS_INFO IpAddress; + /// + /// Pointer to a null terminated ASCII string + /// representing the symbolic names. A PeerId can be a DNS + /// name, Distinguished Name, RFC 822 email address or Key ID + /// (specified in section 4.4.3.1 of RFC 4301) + /// + UINT8 PeerId[MAX_PEERID_LEN]; + } Id; +} EFI_IPSEC_PAD_ID; + +/// +/// EFI_IPSEC_CONFIG_SELECTOR +/// describes the expected IPsec configuration data selector +/// of type EFI_IPSEC_CONFIG_DATA_TYPE. +/// +typedef union { + EFI_IPSEC_SPD_SELECTOR SpdSelector; + EFI_IPSEC_SA_ID SaId; + EFI_IPSEC_PAD_ID PadId; +} EFI_IPSEC_CONFIG_SELECTOR; + +/// +/// EFI_IPSEC_AUTH_PROTOCOL_TYPE +/// defines the possible authentication protocol for IPsec +/// security association management. +/// +typedef enum { + EfiIPsecAuthProtocolIKEv1, + EfiIPsecAuthProtocolIKEv2, + EfiIPsecAuthProtocolMaximum +} EFI_IPSEC_AUTH_PROTOCOL_TYPE; + +/// +/// EFI_IPSEC_AUTH_METHOD +/// +typedef enum { + /// + /// Using Pre-shared Keys for manual security associations. + /// + EfiIPsecAuthMethodPreSharedSecret, + /// + /// IKE employs X.509 certificates for SA establishment. + /// + EfiIPsecAuthMethodCertificates, + EfiIPsecAuthMethodMaximum +} EFI_IPSEC_AUTH_METHOD; + +/// +/// EFI_IPSEC_PAD_DATA +/// +typedef struct _EFI_IPSEC_PAD_DATA { + /// + /// Authentication Protocol for IPsec security association management. + /// + EFI_IPSEC_AUTH_PROTOCOL_TYPE AuthProtocol; + /// + /// Authentication method used. + /// + EFI_IPSEC_AUTH_METHOD AuthMethod; + /// + /// The IKE ID payload will be used as a symbolic name for SPD + /// lookup if IkeIdFlag is TRUE. Otherwise, the remote IP + /// address provided in traffic selector playloads will be used. + /// + BOOLEAN IkeIdFlag; + /// + /// The size of Authentication data buffer, in bytes. + /// + UINTN AuthDataSize; + /// + /// Buffer for Authentication data, (e.g., the pre-shared secret or the + /// trust anchor relative to which the peer's certificate will be + /// validated). + /// + VOID *AuthData; + /// + /// The size of RevocationData, in bytes + /// + UINTN RevocationDataSize; + /// + /// Pointer to CRL or OCSP data, if certificates are used for + /// authentication method. + /// + VOID *RevocationData; +} EFI_IPSEC_PAD_DATA; + + +/** + Set the security association, security policy and peer authorization configuration + information for the EFI IPsec driver. + + This function is used to set the IPsec configuration information of type DataType for + the EFI IPsec driver. + The IPsec configuration data has a unique selector/identifier separately to identify + a data entry. The selector structure depends on DataType's definition. + Using SetData() with a Data of NULL causes the IPsec configuration data entry identified + by DataType and Selector to be deleted. + + @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to be set. + @param[in] Selector Pointer to an entry selector on operated configuration data + specified by DataType. A NULL Selector causes the entire + specified-type configuration information to be flushed. + @param[in] Data The data buffer to be set. The structure of the data buffer is + associated with the DataType. + @param[in] InsertBefore Pointer to one entry selector which describes the expected + position the new data entry will be added. If InsertBefore is NULL, + the new entry will be appended the end of database. + + @retval EFI_SUCCESS The specified configuration entry data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + @retval EFI_UNSUPPORTED The specified DataType is not supported. + @retval EFI_OUT_OF_RESOURCED The required system resource could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_CONFIG_SET_DATA)( + IN EFI_IPSEC_CONFIG_PROTOCOL *This, + IN EFI_IPSEC_CONFIG_DATA_TYPE DataType, + IN EFI_IPSEC_CONFIG_SELECTOR *Selector, + IN VOID *Data, + IN EFI_IPSEC_CONFIG_SELECTOR *InsertBefore OPTIONAL + ); + +/** + Return the configuration value for the EFI IPsec driver. + + This function lookup the data entry from IPsec database or IKEv2 configuration + information. The expected data type and unique identification are described in + DataType and Selector parameters. + + @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to retrieve. + @param[in] Selector Pointer to an entry selector which is an identifier of the IPsec + configuration data entry. + @param[in, out] DataSize On output the size of data returned in Data. + @param[out] Data The buffer to return the contents of the IPsec configuration data. + The type of the data buffer is associated with the DataType. + + @retval EFI_SUCCESS The specified configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE: + - This is NULL. + - Selector is NULL. + - DataSize is NULL. + - Data is NULL and *DataSize is not zero + @retval EFI_NOT_FOUND The configuration data specified by Selector is not found. + @retval EFI_UNSUPPORTED The specified DataType is not supported. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. DataSize has been + updated with the size needed to complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_CONFIG_GET_DATA)( + IN EFI_IPSEC_CONFIG_PROTOCOL *This, + IN EFI_IPSEC_CONFIG_DATA_TYPE DataType, + IN EFI_IPSEC_CONFIG_SELECTOR *Selector, + IN OUT UINTN *DataSize, + OUT VOID *Data + ); + +/** + Enumerates the current selector for IPsec configuration data entry. + + This function is called multiple times to retrieve the entry Selector in IPsec + configuration database. On each call to GetNextSelector(), the next entry + Selector are retrieved into the output interface. + + If the entire IPsec configuration database has been iterated, the error + EFI_NOT_FOUND is returned. + If the Selector buffer is too small for the next Selector copy, an + EFI_BUFFER_TOO_SMALL error is returned, and SelectorSize is updated to reflect + the size of buffer needed. + + On the initial call to GetNextSelector() to start the IPsec configuration database + search, a pointer to the buffer with all zero value is passed in Selector. Calls + to SetData() between calls to GetNextSelector may produce unpredictable results. + + @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance. + @param[in] DataType The type of IPsec configuration data to retrieve. + @param[in, out] SelectorSize The size of the Selector buffer. + @param[in, out] Selector On input, supplies the pointer to last Selector that was + returned by GetNextSelector(). + On output, returns one copy of the current entry Selector + of a given DataType. + + @retval EFI_SUCCESS The specified configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE: + - This is NULL. + - SelectorSize is NULL. + - Selector is NULL. + @retval EFI_NOT_FOUND The next configuration data entry was not found. + @retval EFI_UNSUPPORTED The specified DataType is not supported. + @retval EFI_BUFFER_TOO_SMALL The SelectorSize is too small for the result. This parameter + has been updated with the size needed to complete the search + request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR)( + IN EFI_IPSEC_CONFIG_PROTOCOL *This, + IN EFI_IPSEC_CONFIG_DATA_TYPE DataType, + IN OUT UINTN *SelectorSize, + IN OUT EFI_IPSEC_CONFIG_SELECTOR *Selector + ); + +/** + Register an event that is to be signaled whenever a configuration process on the + specified IPsec configuration information is done. + + This function registers an event that is to be signaled whenever a configuration + process on the specified IPsec configuration data is done (e.g. IPsec security + policy database configuration is ready). An event can be registered for different + DataType simultaneously and the caller is responsible for determining which type + of configuration data causes the signaling of the event in such case. + + @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance. + @param[in] DataType The type of data to be registered the event for. + @param[in] Event The event to be registered. + + @retval EFI_SUCCESS The event is registered successfully. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_ACCESS_DENIED The Event is already registered for the DataType. + @retval EFI_UNSUPPORTED The notify registration unsupported or the specified + DataType is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_CONFIG_REGISTER_NOTIFY)( + IN EFI_IPSEC_CONFIG_PROTOCOL *This, + IN EFI_IPSEC_CONFIG_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/** + Remove the specified event that is previously registered on the specified IPsec + configuration data. + + This function removes a previously registered event for the specified configuration data. + + @param[in] This Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance. + @param[in] DataType The configuration data type to remove the registered event for. + @param[in] Event The event to be unregistered. + + @retval EFI_SUCCESS The event is removed successfully. + @retval EFI_NOT_FOUND The Event specified by DataType could not be found in the + database. + @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL. + @retval EFI_UNSUPPORTED The notify registration unsupported or the specified + DataType is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY)( + IN EFI_IPSEC_CONFIG_PROTOCOL *This, + IN EFI_IPSEC_CONFIG_DATA_TYPE DataType, + IN EFI_EVENT Event + ); + +/// +/// EFI_IPSEC_CONFIG_PROTOCOL +/// provides the ability to set and lookup the IPsec SAD (Security Association Database), +/// SPD (Security Policy Database) data entry and configure the security association +/// management protocol such as IKEv2. This protocol is used as the central +/// repository of any policy-specific configuration for EFI IPsec driver. +/// EFI_IPSEC_CONFIG_PROTOCOL can be bound to both IPv4 and IPv6 stack. User can use this +/// protocol for IPsec configuration in both IPv4 and IPv6 environment. +/// +struct _EFI_IPSEC_CONFIG_PROTOCOL { + EFI_IPSEC_CONFIG_SET_DATA SetData; + EFI_IPSEC_CONFIG_GET_DATA GetData; + EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR GetNextSelector; + EFI_IPSEC_CONFIG_REGISTER_NOTIFY RegisterDataNotify; + EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify; +}; + +extern EFI_GUID gEfiIpSecConfigProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IsaHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IsaHc.h new file mode 100644 index 0000000000..66f19a755b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/IsaHc.h @@ -0,0 +1,110 @@ +/** @file + ISA HC Protocol as defined in the PI 1.2.1 specification. + + This protocol provides registration for ISA devices on a positive- or + subtractive-decode ISA bus. It allows devices to be registered and also + handles opening and closing the apertures which are positively-decoded. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.2.1. + +**/ + +#ifndef __ISA_HC_PROTOCOL_H__ +#define __ISA_HC_PROTOCOL_H__ + +#define EFI_ISA_HC_PROTOCOL_GUID \ + { \ + 0xbcdaf080, 0x1bde, 0x4e22, {0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4} \ + } + +#define EFI_ISA_HC_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81} \ + } + +typedef struct _EFI_ISA_HC_PROTOCOL EFI_ISA_HC_PROTOCOL; +typedef struct _EFI_ISA_HC_PROTOCOL *PEFI_ISA_HC_PROTOCOL; + +/** + Open I/O aperture. + + This function opens an I/O aperture in a ISA Host Controller for the I/O addresses + specified by IoAddress to IoAddress + IoLength - 1. It may be possible that a + single hardware aperture may be used for more than one device. This function + tracks the number of times that each aperture is referenced, and does not close + the hardware aperture (via CloseIoAperture()) until there are no more references to it. + + @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL. + @param IoAddress An unsigned integer that specifies the first byte of the + I/O space required. + @param IoLength An unsigned integer that specifies the number of bytes + of the I/O space required. + @param IoApertureHandle A pointer to the returned I/O aperture handle. This + value can be used on subsequent calls to CloseIoAperture(). + + @retval EFI_SUCCESS The I/O aperture was opened successfully. + @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller. + @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ISA_HC_OPEN_IO) ( + IN CONST EFI_ISA_HC_PROTOCOL *This, + IN UINT16 IoAddress, + IN UINT16 IoLength, + OUT UINT64 *IoApertureHandle + ); + +/** + Close I/O aperture. + + This function closes a previously opened I/O aperture handle. If there are no + more I/O aperture handles that refer to the hardware I/O aperture resource, + then the hardware I/O aperture is closed. It may be possible that a single + hardware aperture may be used for more than one device. This function tracks + the number of times that each aperture is referenced, and does not close the + hardware aperture (via CloseIoAperture()) until there are no more references to it. + + @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL. + @param IoApertureHandle The I/O aperture handle previously returned from a + call to OpenIoAperture(). + + @retval EFI_SUCCESS The IO aperture was closed successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ISA_HC_CLOSE_IO) ( + IN CONST EFI_ISA_HC_PROTOCOL *This, + IN UINT64 IoApertureHandle + ); + +/// +/// ISA HC Protocol +/// +struct _EFI_ISA_HC_PROTOCOL { + /// + /// The version of this protocol. Higher version numbers are backward + /// compatible with lower version numbers. + /// + UINT32 Version; + /// + /// Open an I/O aperture. + /// + EFI_ISA_HC_OPEN_IO OpenIoAperture; + /// + /// Close an I/O aperture. + /// + EFI_ISA_HC_CLOSE_IO CloseIoAperture; +}; + +/// +/// Reference to variable defined in the .DEC file +/// +extern EFI_GUID gEfiIsaHcProtocolGuid; +extern EFI_GUID gEfiIsaHcServiceBindingProtocolGuid; + +#endif // __ISA_HC_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Kms.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Kms.h new file mode 100644 index 0000000000..0b261a2589 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Kms.h @@ -0,0 +1,1337 @@ +/** @file + The Key Management Service (KMS) protocol as defined in the UEFI 2.3.1 specification is to + provides services to generate, store, retrieve, and manage cryptographic keys. + The intention is to specify a simple generic protocol that could be used for many implementations. + + A driver implementing the protocol may need to provide basic key service that consists of a + key store and cryptographic key generation capability. It may connect to an external key + server over the network, or to a Hardware Security Module (HSM) attached to the system it + runs on, or anything else that is capable of providing the key management service. + + Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __KMS_H__ +#define __KMS_H__ + +#define EFI_KMS_PROTOCOL_GUID \ + { \ + 0xEC3A978D, 0x7C4E, 0x48FA, {0x9A, 0xBE, 0x6A, 0xD9, 0x1C, 0xC8, 0xF8, 0x11 } \ + } + +typedef struct _EFI_KMS_PROTOCOL EFI_KMS_PROTOCOL; + +// +// Where appropriate, EFI_KMS_DATA_TYPE values may be combined using a bitwise 'OR' +// operation to indicate support for multiple data types. +// +#define EFI_KMS_DATA_TYPE_NONE 0 +#define EFI_KMS_DATA_TYPE_BINARY 1 +#define EFI_KMS_DATA_TYPE_ASCII 2 +#define EFI_KMS_DATA_TYPE_UNICODE 4 +#define EFI_KMS_DATA_TYPE_UTF8 8 + + +// +// The key formats recognized by the KMS protocol are defined by an EFI_GUID which specifies +// a (key-algorithm, key-size) pair. The names of these GUIDs are in the format +// EFI_KMS_KEY_(key-algorithm)_(key-size)_GUID, where the key-size is expressed in bits. +// The key formats recognized fall into three categories, generic (no algorithm), hash algorithms, +// and encrypted algorithms. +// + +/// +/// The following GUIDs define formats that contain generic key data of a specific size in bits, +/// but which is not associated with any specific key algorithm(s). +///@{ +#define EFI_KMS_FORMAT_GENERIC_128_GUID \ + { \ + 0xec8a3d69, 0x6ddf, 0x4108, {0x94, 0x76, 0x73, 0x37, 0xfc, 0x52, 0x21, 0x36 } \ + } +#define EFI_KMS_FORMAT_GENERIC_160_GUID \ + { \ + 0xa3b3e6f8, 0xefca, 0x4bc1, {0x88, 0xfb, 0xcb, 0x87, 0x33, 0x9b, 0x25, 0x79 } \ + } +#define EFI_KMS_FORMAT_GENERIC_256_GUID \ + { \ + 0x70f64793, 0xc323, 0x4261, {0xac, 0x2c, 0xd8, 0x76, 0xf2, 0x7c, 0x53, 0x45 } \ + } +#define EFI_KMS_FORMAT_GENERIC_512_GUID \ + { \ + 0x978fe043, 0xd7af, 0x422e, {0x8a, 0x92, 0x2b, 0x48, 0xe4, 0x63, 0xbd, 0xe6 } \ + } +#define EFI_KMS_FORMAT_GENERIC_1024_GUID \ + { \ + 0x43be0b44, 0x874b, 0x4ead, {0xb0, 0x9c, 0x24, 0x1a, 0x4f, 0xbd, 0x7e, 0xb3 } \ + } +#define EFI_KMS_FORMAT_GENERIC_2048_GUID \ + { \ + 0x40093f23, 0x630c, 0x4626, {0x9c, 0x48, 0x40, 0x37, 0x3b, 0x19, 0xcb, 0xbe } \ + } +#define EFI_KMS_FORMAT_GENERIC_3072_GUID \ + { \ + 0xb9237513, 0x6c44, 0x4411, {0xa9, 0x90, 0x21, 0xe5, 0x56, 0xe0, 0x5a, 0xde } \ + } +#define EFI_KMS_FORMAT_GENERIC_DYNAMIC_GUID \ + { \ + 0x2156e996, 0x66de, 0x4b27, {0x9c, 0xc9, 0xb0, 0x9f, 0xac, 0x4d, 0x2, 0xbe } \ + } +///@} + +/// +/// These GUIDS define key data formats that contain data generated by basic hash algorithms +/// with no cryptographic properties. +///@{ +#define EFI_KMS_FORMAT_MD2_128_GUID \ + { \ + 0x78be11c4, 0xee44, 0x4a22, {0x9f, 0x05, 0x03, 0x85, 0x2e, 0xc5, 0xc9, 0x78 } \ + } +#define EFI_KMS_FORMAT_MDC2_128_GUID \ + { \ + 0xf7ad60f8, 0xefa8, 0x44a3, {0x91, 0x13, 0x23, 0x1f, 0x39, 0x9e, 0xb4, 0xc7 } \ + } +#define EFI_KMS_FORMAT_MD4_128_GUID \ + { \ + 0xd1c17aa1, 0xcac5, 0x400f, {0xbe, 0x17, 0xe2, 0xa2, 0xae, 0x06, 0x67, 0x7c } \ + } +#define EFI_KMS_FORMAT_MDC4_128_GUID \ + { \ + 0x3fa4f847, 0xd8eb, 0x4df4, {0xbd, 0x49, 0x10, 0x3a, 0x0a, 0x84, 0x7b, 0xbc } \ + } +#define EFI_KMS_FORMAT_MD5_128_GUID \ + { \ + 0xdcbc3662, 0x9cda, 0x4b52, {0xa0, 0x4c, 0x82, 0xeb, 0x1d, 0x23, 0x48, 0xc7 } \ + } +#define EFI_KMS_FORMAT_MD5SHA_128_GUID \ + { \ + 0x1c178237, 0x6897, 0x459e, {0x9d, 0x36, 0x67, 0xce, 0x8e, 0xf9, 0x4f, 0x76 } \ + } +#define EFI_KMS_FORMAT_SHA1_160_GUID \ + { \ + 0x453c5e5a, 0x482d, 0x43f0, {0x87, 0xc9, 0x59, 0x41, 0xf3, 0xa3, 0x8a, 0xc2 } \ + } +#define EFI_KMS_FORMAT_SHA256_256_GUID \ + { \ + 0x6bb4f5cd, 0x8022, 0x448d, {0xbc, 0x6d, 0x77, 0x1b, 0xae, 0x93, 0x5f, 0xc6 } \ + } +#define EFI_KMS_FORMAT_SHA512_512_GUID \ + { \ + 0x2f240e12, 0xe14d, 0x475c, {0x83, 0xb0, 0xef, 0xff, 0x22, 0xd7, 0x7b, 0xe7 } \ + } +///@} + +/// +/// These GUIDs define key data formats that contain data generated by cryptographic key algorithms. +/// There may or may not be a separate data hashing algorithm associated with the key algorithm. +///@{ +#define EFI_KMS_FORMAT_AESXTS_128_GUID \ + { \ + 0x4776e33f, 0xdb47, 0x479a, {0xa2, 0x5f, 0xa1, 0xcd, 0x0a, 0xfa, 0xb3, 0x8b } \ + } +#define EFI_KMS_FORMAT_AESXTS_256_GUID \ + { \ + 0xdc7e8613, 0xc4bb, 0x4db0, {0x84, 0x62, 0x13, 0x51, 0x13, 0x57, 0xab, 0xe2 } \ + } +#define EFI_KMS_FORMAT_AESCBC_128_GUID \ + { \ + 0xa0e8ee6a, 0x0e92, 0x44d4, {0x86, 0x1b, 0x0e, 0xaa, 0x4a, 0xca, 0x44, 0xa2 } \ + } +#define EFI_KMS_FORMAT_AESCBC_256_GUID \ + { \ + 0xd7e69789, 0x1f68, 0x45e8, {0x96, 0xef, 0x3b, 0x64, 0x07, 0xa5, 0xb2, 0xdc } \ + } +#define EFI_KMS_FORMAT_RSASHA1_1024_GUID \ + { \ + 0x56417bed, 0x6bbe, 0x4882, {0x86, 0xa0, 0x3a, 0xe8, 0xbb, 0x17, 0xf8, 0xf9 } \ + } +#define EFI_KMS_FORMAT_RSASHA1_2048_GUID \ + { \ + 0xf66447d4, 0x75a6, 0x463e, {0xa8, 0x19, 0x07, 0x7f, 0x2d, 0xda, 0x05, 0xe9 } \ + } +#define EFI_KMS_FORMAT_RSASHA256_2048_GUID \ + { \ + 0xa477af13, 0x877d, 0x4060, {0xba, 0xa1, 0x25, 0xd1, 0xbe, 0xa0, 0x8a, 0xd3 } \ + } +#define EFI_KMS_FORMAT_RSASHA256_3072_GUID \ + { \ + 0x4e1356c2, 0xeed, 0x463f, {0x81, 0x47, 0x99, 0x33, 0xab, 0xdb, 0xc7, 0xd5 } \ + } +///@} + +#define EFI_KMS_ATTRIBUTE_TYPE_NONE 0x00 +#define EFI_KMS_ATTRIBUTE_TYPE_INTEGER 0x01 +#define EFI_KMS_ATTRIBUTE_TYPE_LONG_INTEGER 0x02 +#define EFI_KMS_ATTRIBUTE_TYPE_BIG_INTEGER 0x03 +#define EFI_KMS_ATTRIBUTE_TYPE_ENUMERATION 0x04 +#define EFI_KMS_ATTRIBUTE_TYPE_BOOLEAN 0x05 +#define EFI_KMS_ATTRIBUTE_TYPE_BYTE_STRING 0x06 +#define EFI_KMS_ATTRIBUTE_TYPE_TEXT_STRING 0x07 +#define EFI_KMS_ATTRIBUTE_TYPE_DATE_TIME 0x08 +#define EFI_KMS_ATTRIBUTE_TYPE_INTERVAL 0x09 +#define EFI_KMS_ATTRIBUTE_TYPE_STRUCTURE 0x0A +#define EFI_KMS_ATTRIBUTE_TYPE_DYNAMIC 0x0B + +typedef struct { + /// + /// Length in bytes of the KeyData. + /// + UINT32 KeySize; + /// + /// The data of the key. + /// + UINT8 KeyData[1]; +} EFI_KMS_FORMAT_GENERIC_DYNAMIC; + +typedef struct { + /// + /// The size in bytes for the client identifier. + /// + UINT16 ClientIdSize; + /// + /// Pointer to a valid client identifier. + /// + VOID *ClientId; + /// + /// The client name string type used by this client. The string type set here must be one of + /// the string types reported in the ClientNameStringTypes field of the KMS protocol. If the + /// KMS does not support client names, this field should be set to EFI_KMS_DATA_TYPE_NONE. + /// + UINT8 ClientNameType; + /// + /// The size in characters for the client name. This field will be ignored if + /// ClientNameStringType is set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it must contain + /// number of characters contained in the ClientName field. + /// + UINT8 ClientNameCount; + /// + /// Pointer to a client name. This field will be ignored if ClientNameStringType is set to + /// EFI_KMS_DATA_TYPE_NONE. Otherwise, it must point to a valid string of the specified type. + /// + VOID *ClientName; +} EFI_KMS_CLIENT_INFO; + +typedef struct { + /// + /// The size of the KeyIdentifier field in bytes. This field is limited to the range 0 to 255. + /// + UINT8 KeyIdentifierSize; + /// + /// Pointer to an array of KeyIdentifierType elements. + /// + VOID *KeyIdentifier; + /// + /// An EFI_GUID which specifies the algorithm and key value size for this key. + /// + EFI_GUID KeyFormat; + /// + /// Pointer to a key value for a key specified by the KeyFormat field. A NULL value for this + /// field indicates that no key is available. + /// + VOID *KeyValue; + /// + /// Specifies the results of KMS operations performed with this descriptor. This field is used + /// to indicate the status of individual operations when a KMS function is called with multiple + /// EFI_KMS_KEY_DESCRIPTOR structures. + /// KeyStatus codes returned for the individual key requests are: + /// EFI_SUCCESS Successfully processed this key. + /// EFI_WARN_STALE_DATA Successfully processed this key, however, the key's parameters + /// exceed internal policies/limits and should be replaced. + /// EFI_COMPROMISED_DATA Successfully processed this key, but the key may have been + /// compromised and must be replaced. + /// EFI_UNSUPPORTED Key format is not supported by the service. + /// EFI_OUT_OF_RESOURCES Could not allocate resources for the key processing. + /// EFI_TIMEOUT Timed out waiting for device or key server. + /// EFI_DEVICE_ERROR Device or key server error. + /// EFI_INVALID_PARAMETER KeyFormat is invalid. + /// EFI_NOT_FOUND The key does not exist on the KMS. + /// + EFI_STATUS KeyStatus; +} EFI_KMS_KEY_DESCRIPTOR; + +typedef struct { + /// + /// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The + /// definition of the value is outside the scope of this standard and may be defined by the KMS. + /// + UINT16 Tag; + /// + /// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The + /// definition of the value is outside the scope of this standard and may be defined by the KMS. + /// + UINT16 Type; + /// + /// Length in bytes of the KeyAttributeData. + /// + UINT32 Length; + /// + /// An array of bytes to hold the attribute data associated with the KeyAttributeIdentifier. + /// + UINT8 KeyAttributeData[1]; +} EFI_KMS_DYNAMIC_FIELD; + +typedef struct { + /// + /// The number of members in the EFI_KMS_DYNAMIC_ATTRIBUTE structure. + /// + UINT32 FieldCount; + /// + /// An array of EFI_KMS_DYNAMIC_FIELD structures. + /// + EFI_KMS_DYNAMIC_FIELD Field[1]; +} EFI_KMS_DYNAMIC_ATTRIBUTE; + +typedef struct { + /// + /// The data type used for the KeyAttributeIdentifier field. Values for this field are defined + /// by the EFI_KMS_DATA_TYPE constants, except that EFI_KMS_DATA_TYPE_BINARY is not + /// valid for this field. + /// + UINT8 KeyAttributeIdentifierType; + /// + /// The length of the KeyAttributeIdentifier field in units defined by KeyAttributeIdentifierType + /// field. This field is limited to the range 0 to 255. + /// + UINT8 KeyAttributeIdentifierCount; + /// + /// Pointer to an array of KeyAttributeIdentifierType elements. For string types, there must + /// not be a null-termination element at the end of the array. + /// + VOID *KeyAttributeIdentifier; + /// + /// The instance number of this attribute. If there is only one instance, the value is set to + /// one. If this value is set to 0xFFFF (all binary 1's) then this field should be ignored if an + /// output or treated as a wild card matching any value if it is an input. If the attribute is + /// stored with this field, it will match any attribute request regardless of the setting of the + /// field in the request. If set to 0xFFFF in the request, it will match any attribute with the + /// same KeyAttributeIdentifier. + /// + UINT16 KeyAttributeInstance; + /// + /// The data type of the KeyAttributeValue (e.g. struct, bool, etc.). See the list of + /// KeyAttributeType definitions. + /// + UINT16 KeyAttributeType; + /// + /// The size in bytes of the KeyAttribute field. A value of zero for this field indicates that no + /// key attribute value is available. + /// + UINT16 KeyAttributeValueSize; + /// + /// Pointer to a key attribute value for the attribute specified by the KeyAttributeIdentifier + /// field. If the KeyAttributeValueSize field is zero, then this field must be NULL. + /// + VOID *KeyAttributeValue; + /// + /// KeyAttributeStatusSpecifies the results of KMS operations performed with this attribute. + /// This field is used to indicate the status of individual operations when a KMS function is + /// called with multiple EFI_KMS_KEY_ATTRIBUTE structures. + /// KeyAttributeStatus codes returned for the individual key attribute requests are: + /// EFI_SUCCESS Successfully processed this request. + /// EFI_WARN_STALE_DATA Successfully processed this request, however, the key's + /// parameters exceed internal policies/limits and should be replaced. + /// EFI_COMPROMISED_DATA Successfully processed this request, but the key may have been + /// compromised and must be replaced. + /// EFI_UNSUPPORTED Key attribute format is not supported by the service. + /// EFI_OUT_OF_RESOURCES Could not allocate resources for the request processing. + /// EFI_TIMEOUT Timed out waiting for device or key server. + /// EFI_DEVICE_ERROR Device or key server error. + /// EFI_INVALID_PARAMETER A field in the EFI_KMS_KEY_ATTRIBUTE structure is invalid. + /// EFI_NOT_FOUND The key attribute does not exist on the KMS. + /// + EFI_STATUS KeyAttributeStatus; +} EFI_KMS_KEY_ATTRIBUTE; + +/** + Get the current status of the key management service. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + + @retval EFI_SUCCESS The KMS is ready for use. + @retval EFI_NOT_READY No connection to the KMS is available. + @retval EFI_NO_MAPPING No valid connection configuration exists for the KMS. + @retval EFI_NO_RESPONSE No response was received from the KMS. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_GET_SERVICE_STATUS) ( + IN EFI_KMS_PROTOCOL *This + ); + +/** + Register client information with the supported KMS. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS The client information has been accepted by the KMS. + @retval EFI_NOT_READY No connection to the KMS is available. + @retval EFI_NO_RESPONSE There was no response from the device or the key server. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS. + @retval EFI_OUT_OF_RESOURCES Required resources were not available to perform the function. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_UNSUPPORTED The KMS does not support the use of client identifiers. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_REGISTER_CLIENT) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Request that the KMS generate one or more new keys and associate them with key identifiers. + The key value(s) is returned to the caller. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be + processed by this operation. On return, this number + will be updated with the number of key descriptors + successfully processed. + @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR + structures which describe the keys to be generated. + On input, the KeyIdentifierSize and the KeyIdentifier + may specify an identifier to be used for the key, + but this is not required. The KeyFormat field must + specify a key format GUID reported as supported by + the KeyFormats field of the EFI_KMS_PROTOCOL. + The value for this field in the first key descriptor will + be considered the default value for subsequent key + descriptors requested in this operation if those key + descriptors have a NULL GUID in the key format field. + On output, the KeyIdentifierSize and KeyIdentifier fields + will specify an identifier for the key which will be either + the original identifier if one was provided, or an identifier + generated either by the KMS or the KMS protocol + implementation. The KeyFormat field will be updated + with the GUID used to generate the key if it was a + NULL GUID, and the KeyValue field will contain a pointer + to memory containing the key value for the generated + key. Memory for both the KeyIdentifier and the KeyValue + fields will be allocated with the BOOT_SERVICES_DATA + type and must be freed by the caller when it is no longer + needed. Also, the KeyStatus field must reflect the result + of the request relative to that key. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully generated and retrieved all requested keys. + @retval EFI_UNSUPPORTED This function is not supported by the KMS. --OR-- + One (or more) of the key requests submitted is not supported by + the KMS. Check individual key request(s) to see which ones + may have been processed. + @retval EFI_OUT_OF_RESOURCES Required resources were not available to perform the function. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + request(s) to see which ones may have been processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either no id was + provided or an invalid id was provided. + @retval EFI_DEVICE_ERROR An error occurred when attempting to access the KMS. Check + individual key request(s) to see which ones may have been + processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyDescriptorCount is NULL, or Keys is NULL. + @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures + could not be processed properly. KeyDescriptorCount + contains the number of structures which were successfully + processed. Individual structures will reflect the status of the + processing for that structure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_CREATE_KEY) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINT16 *KeyDescriptorCount, + IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Retrieve an existing key. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be + processed by this operation. On return, this number + will be updated with the number of key descriptors + successfully processed. + @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR + structures which describe the keys to be retrieved + from the KMS. + On input, the KeyIdentifierSize and the KeyIdentifier + must specify an identifier to be used to retrieve a + specific key. All other fields in the descriptor should + be NULL. + On output, the KeyIdentifierSize and KeyIdentifier fields + will be unchanged, while the KeyFormat and KeyValue + fields will be updated values associated with this key + identifier. Memory for the KeyValue field will be + allocated with the BOOT_SERVICES_DATA type and + must be freed by the caller when it is no longer needed. + Also, the KeyStatus field will reflect the result of the + request relative to the individual key descriptor. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully retrieved all requested keys. + @retval EFI_OUT_OF_RESOURCES Could not allocate resources for the method processing. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + request(s) to see which ones may have been processed. + @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with a single identifier, and the + KeyValue buffer does not contain enough structures + (KeyDescriptorCount) to contain all the key data, then + the available structures will be filled and + KeyDescriptorCount will be updated to indicate the + number of keys which could not be processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to + see which ones may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyDescriptorCount is NULL, or Keys is NULL. + @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures + could not be processed properly. KeyDescriptorCount + contains the number of structures which were successfully + processed. Individual structures will reflect the status of the + processing for that structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_GET_KEY) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINT16 *KeyDescriptorCount, + IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Add a new key. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be + processed by this operation. On normal return, this + number will be updated with the number of key + descriptors successfully processed. + @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR + structures which describe the keys to be added. + On input, the KeyId field for first key must contain + valid identifier data to be used for adding a key to + the KMS. The values for these fields in this key + definition will be considered default values for + subsequent keys requested in this operation. A value + of 0 in any subsequent KeyId field will be replaced + with the current default value. The KeyFormat and + KeyValue fields for each key to be added must contain + consistent values to be associated with the given KeyId. + On return, the KeyStatus field will reflect the result + of the operation for each key request. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully added all requested keys. + @retval EFI_OUT_OF_RESOURCES Could not allocate required resources. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + request(s) to see which ones may have been processed. + @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with a single identifier, and the + KeyValue buffer does not contain enough structures + (KeyDescriptorCount) to contain all the key data, then + the available structures will be filled and + KeyDescriptorCount will be updated to indicate the + number of keys which could not be processed + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to + see which ones may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyDescriptorCount is NULL, or Keys is NULL. + @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures + could not be processed properly. KeyDescriptorCount + contains the number of structures which were successfully + processed. Individual structures will reflect the status of the + processing for that structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_ADD_KEY) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINT16 *KeyDescriptorCount, + IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Delete an existing key from the KMS database. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors to be + processed by this operation. On normal return, this + number will be updated with the number of key + descriptors successfully processed. + @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR + structures which describe the keys to be deleted. + On input, the KeyId field for first key must contain + valid identifier data to be used for adding a key to + the KMS. The values for these fields in this key + definition will be considered default values for + subsequent keys requested in this operation. A value + of 0 in any subsequent KeyId field will be replaced + with the current default value. The KeyFormat and + KeyValue fields are ignored, but should be 0. + On return, the KeyStatus field will reflect the result + of the operation for each key request. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully deleted all requested keys. + @retval EFI_OUT_OF_RESOURCES Could not allocate required resources. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + request(s) to see which ones may have been processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key request(s) to + see which ones may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyDescriptorCount is NULL, or Keys is NULL. + @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_DESCRIPTOR structures + could not be processed properly. KeyDescriptorCount + contains the number of structures which were successfully + processed. Individual structures will reflect the status of the + processing for that structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_DELETE_KEY) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINT16 *KeyDescriptorCount, + IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Get one or more attributes associated with a specified key identifier. + If none are found, the returned attributes count contains a value of zero. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable. + @param[in] KeyIdentifier Pointer to the key identifier associated with this key. + @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE + structures associated with the Key identifier. If none + are found, the count value is zero on return. + On input this value reflects the number of KeyAttributes + that may be returned. + On output, the value reflects the number of completed + KeyAttributes structures found. + @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE + structures associated with the Key Identifier. + On input, the fields in the structure should be NULL. + On output, the attribute fields will have updated values + for attributes associated with this key identifier. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully retrieved all key attributes. + @retval EFI_OUT_OF_RESOURCES Could not allocate resources for the method processing. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + attribute request(s) to see which ones may have been + processed. + @retval EFI_BUFFER_TOO_SMALL If multiple key attributes are associated with a single identifier, + and the KeyAttributes buffer does not contain enough + structures (KeyAttributesCount) to contain all the key + attributes data, then the available structures will be filled and + KeyAttributesCount will be updated to indicate the + number of key attributes which could not be processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute + request(s) (i.e. key attribute status for each) to see which ones + may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyIdentifierSize is NULL , or KeyIdentifier + is NULL, or KeyAttributes is NULL, or + KeyAttributesSize is NULL. + @retval EFI_NOT_FOUND The KeyIdentifier could not be found. + KeyAttributesCount contains zero. Individual + structures will reflect the status of the processing for that + structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_GET_KEY_ATTRIBUTES) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN UINT8 *KeyIdentifierSize, + IN CONST VOID *KeyIdentifier, + IN OUT UINT16 *KeyAttributesCount, + IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Add one or more attributes to a key specified by a key identifier. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable. + @param[in] KeyIdentifier Pointer to the key identifier associated with this key. + @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE + structures to associate with the Key. On normal returns, + this number will be updated with the number of key + attributes successfully processed. + @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE + structures providing the attribute information to + associate with the key. + On input, the values for the fields in the structure + are completely filled in. + On return the KeyAttributeStatus field will reflect the + result of the operation for each key attribute request. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully added all requested key attributes. + @retval EFI_OUT_OF_RESOURCES Could not allocate required resources. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + attribute request(s) to see which ones may have been + processed. + @retval EFI_BUFFER_TOO_SMALL If multiple keys attributes are associated with a single key + identifier, and the attributes buffer does not contain + enough structures (KeyAttributesCount) to contain all + the data, then the available structures will be filled and + KeyAttributesCount will be updated to indicate the + number of key attributes which could not be processed. The + status of each key attribute is also updated indicating success or + failure for that attribute in case there are other errors for those + attributes that could be processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute + request(s) (i.e. key attribute status for each) to see which ones + may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyAttributesCount is NULL, or KeyAttributes + is NULL, or KeyIdentifierSize is NULL, or + KeyIdentifer is NULL. + @retval EFI_NOT_FOUND The KeyIdentifier could not be found. On return the + KeyAttributesCount contains the number of attributes + processed. Individual structures will reflect the status of the + processing for that structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_ADD_KEY_ATTRIBUTES) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN UINT8 *KeyIdentifierSize, + IN CONST VOID *KeyIdentifier, + IN OUT UINT16 *KeyAttributesCount, + IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Delete attributes to a key specified by a key identifier. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in] KeyIdentifierSize Pointer to the size in bytes of the KeyIdentifier variable. + @param[in] KeyIdentifier Pointer to the key identifier associated with this key. + @param[in, out] KeyAttributesCount Pointer to the number of EFI_KMS_KEY_ATTRIBUTE + structures to associate with the Key. + On input, the count value is one or more. + On normal returns, this number will be updated with + the number of key attributes successfully processed. + @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE + structures providing the attribute information to + associate with the key. + On input, the values for the fields in the structure + are completely filled in. + On return the KeyAttributeStatus field will reflect the + result of the operation for each key attribute request. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully deleted all requested key attributes. + @retval EFI_OUT_OF_RESOURCES Could not allocate required resources. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + attribute request(s) to see which ones may have been + processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute + request(s) (i.e. key attribute status for each) to see which ones + may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyAttributesCount is NULL, or + KeyAttributes is NULL, or KeyIdentifierSize + is NULL, or KeyIdentifer is NULL. + @retval EFI_NOT_FOUND The KeyIdentifier could not be found or the attribute + could not be found. On return the KeyAttributesCount + contains the number of attributes processed. Individual + structures will reflect the status of the processing for that + structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_DELETE_KEY_ATTRIBUTES) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN UINT8 *KeyIdentifierSize, + IN CONST VOID *KeyIdentifier, + IN OUT UINT16 *KeyAttributesCount, + IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/** + Retrieve one or more key that has matched all of the specified key attributes. + + @param[in] This Pointer to the EFI_KMS_PROTOCOL instance. + @param[in] Client Pointer to a valid EFI_KMS_CLIENT_INFO structure. + @param[in, out] KeyAttributesCount Pointer to a count of the number of key attribute structures + that must be matched for each returned key descriptor. + On input the count value is one or more. + On normal returns, this number will be updated with + the number of key attributes successfully processed. + @param[in, out] KeyAttributes Pointer to an array of EFI_KMS_KEY_ATTRIBUTE + structure to search for. + On input, the values for the fields in the structure are + completely filled in. + On return the KeyAttributeStatus field will reflect the + result of the operation for each key attribute request. + @param[in, out] KeyDescriptorCount Pointer to a count of the number of key descriptors matched + by this operation. + On entry, this number will be zero. + On return, this number will be updated to the number + of key descriptors successfully found. + @param[in, out] KeyDescriptors Pointer to an array of EFI_KMS_KEY_DESCRIPTOR + structures which describe the keys from the KMS + having the KeyAttribute(s) specified. + On input, this pointer will be NULL. + On output, the array will contain an + EFI_KMS_KEY_DESCRIPTOR structure for each key + meeting the search criteria. Memory for the array + and all KeyValue fields will be allocated with the + EfiBootServicesData type and must be freed by the + caller when it is no longer needed. Also, the KeyStatus + field of each descriptor will reflect the result of the + request relative to that key descriptor. + @param[in, out] ClientDataSize Pointer to the size, in bytes, of an arbitrary block of + data specified by the ClientData parameter. This + parameter may be NULL, in which case the ClientData + parameter will be ignored and no data will be + transferred to or from the KMS. If the parameter is + not NULL, then ClientData must be a valid pointer. + If the value pointed to is 0, no data will be transferred + to the KMS, but data may be returned by the KMS. + For all non-zero values *ClientData will be transferred + to the KMS, which may also return data to the caller. + In all cases, the value upon return to the caller will + be the size of the data block returned to the caller, + which will be zero if no data is returned from the KMS. + @param[in, out] ClientData Pointer to a pointer to an arbitrary block of data of + *ClientDataSize that is to be passed directly to the + KMS if it supports the use of client data. This + parameter may be NULL if and only if the + ClientDataSize parameter is also NULL. Upon return to + the caller, *ClientData points to a block of data of + *ClientDataSize that was returned from the KMS. + If the returned value for *ClientDataSize is zero, + then the returned value for *ClientData must be NULL + and should be ignored by the caller. The KMS protocol + consumer is responsible for freeing all valid buffers + used for client data regardless of whether they are + allocated by the caller for input to the function or by + the implementation for output back to the caller. + + @retval EFI_SUCCESS Successfully retrieved all requested keys. + @retval EFI_OUT_OF_RESOURCES Could not allocate required resources. + @retval EFI_TIMEOUT Timed out waiting for device or key server. Check individual key + attribute request(s) to see which ones may have been + processed. + @retval EFI_BUFFER_TOO_SMALL If multiple keys are associated with the attribute(s), and the + KeyValue buffer does not contain enough structures + (KeyDescriptorCount) to contain all the key data, then + the available structures will be filled and + KeyDescriptorCount will be updated to indicate the + number of keys which could not be processed. + @retval EFI_ACCESS_DENIED Access was denied by the device or the key server; OR a + ClientId is required by the server and either none or an + invalid id was provided. + @retval EFI_DEVICE_ERROR Device or key server error. Check individual key attribute + request(s) (i.e. key attribute status for each) to see which ones + may have been processed. + @retval EFI_INVALID_PARAMETER This is NULL, ClientId is required but it is NULL, + KeyDescriptorCount is NULL, or + KeyDescriptors is NULL or KeyAttributes is + NULL, or KeyAttributesCount is NULL. + @retval EFI_NOT_FOUND One or more EFI_KMS_KEY_ATTRIBUTE structures could + not be processed properly. KeyAttributeCount contains + the number of structures which were successfully processed. + Individual structures will reflect the status of the processing for + that structure. + @retval EFI_UNSUPPORTED The implementation/KMS does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_KMS_GET_KEY_BY_ATTRIBUTES) ( + IN EFI_KMS_PROTOCOL *This, + IN EFI_KMS_CLIENT_INFO *Client, + IN OUT UINTN *KeyAttributeCount, + IN OUT EFI_KMS_KEY_ATTRIBUTE *KeyAttributes, + IN OUT UINTN *KeyDescriptorCount, + IN OUT EFI_KMS_KEY_DESCRIPTOR *KeyDescriptors, + IN OUT UINTN *ClientDataSize OPTIONAL, + IN OUT VOID **ClientData OPTIONAL + ); + +/// +/// The Key Management Service (KMS) protocol provides services to generate, store, retrieve, +/// and manage cryptographic keys. +/// +struct _EFI_KMS_PROTOCOL { + /// + /// Get the current status of the key management service. If the implementation has not yet + /// connected to the KMS, then a call to this function will initiate a connection. This is the + /// only function that is valid for use prior to the service being marked available. + /// + EFI_KMS_GET_SERVICE_STATUS GetServiceStatus; + /// + /// Register a specific client with the KMS. + /// + EFI_KMS_REGISTER_CLIENT RegisterClient; + /// + /// Request the generation of a new key and retrieve it. + /// + EFI_KMS_CREATE_KEY CreateKey; + /// + /// Retrieve an existing key. + /// + EFI_KMS_GET_KEY GetKey; + /// + /// Add a local key to KMS database. If there is an existing key with this key identifier in the + /// KMS database, it will be replaced with the new key. + /// + EFI_KMS_ADD_KEY AddKey; + /// + /// Delete an existing key from the KMS database. + /// + EFI_KMS_DELETE_KEY DeleteKey; + /// + /// Get attributes for an existing key in the KMS database. + /// + EFI_KMS_GET_KEY_ATTRIBUTES GetKeyAttributes; + /// + /// Add attributes to an existing key in the KMS database. + /// + EFI_KMS_ADD_KEY_ATTRIBUTES AddKeyAttributes; + /// + /// Delete attributes for an existing key in the KMS database. + /// + EFI_KMS_DELETE_KEY_ATTRIBUTES DeleteKeyAttributes; + /// + /// Get existing key(s) with the specified attributes. + /// + EFI_KMS_GET_KEY_BY_ATTRIBUTES GetKeyByAttributes; + /// + /// The version of this EFI_KMS_PROTOCOL structure. This must be set to 0x00020040 for + /// the initial version of this protocol. + /// + UINT32 ProtocolVersion; + /// + /// Optional GUID used to identify a specific KMS. This GUID may be supplied by the provider, + /// by the implementation, or may be null. If is null, then the ServiceName must not be null. + /// + EFI_GUID ServiceId; + /// + /// Optional pointer to a unicode string which may be used to identify the KMS or provide + /// other information about the supplier. + /// + CHAR16 *ServiceName; + /// + /// Optional 32-bit value which may be used to indicate the version of the KMS provided by + /// the supplier. + /// + UINT32 ServiceVersion; + /// + /// TRUE if and only if the service is active and available for use. To avoid unnecessary + /// delays in POST, this protocol may be installed without connecting to the service. In this + /// case, the first call to the GetServiceStatus () function will cause the implementation to + /// connect to the supported service and mark it as available. The capabilities of this service + /// as defined in the reminder of this protocol are not guaranteed to be valid until the service + /// has been marked available. + /// + BOOLEAN ServiceAvailable; + /// + /// TRUE if and only if the service supports client identifiers. Client identifiers may be used + /// for auditing, access control or any other purpose specific to the implementation. + /// + BOOLEAN ClientIdSupported; + /// + /// TRUE if and only if the service requires a client identifier in order to process key requests. + /// FALSE otherwise. + /// + BOOLEAN ClientIdRequired; + /// + /// The maximum size in bytes for the client identifier. + /// + UINT16 ClientIdMaxSize; + /// + /// The client name string type(s) supported by the KMS service. If client names are not + /// supported, this field will be set the EFI_KMS_DATA_TYPE_NONE. Otherwise, it will be set + /// to the inclusive 'OR' of all client name formats supported. Client names may be used for + /// auditing, access control or any other purpose specific to the implementation. + /// + UINT8 ClientNameStringTypes; + /// + /// TRUE if only if the KMS requires a client name to be supplied to the service. + /// FALSE otherwise. + /// + BOOLEAN ClientNameRequired; + /// + /// The maximum number of characters allowed for the client name. + /// + UINT16 ClientNameMaxCount; + /// + /// TRUE if and only if the service supports arbitrary client data requests. The use of client + /// data requires the caller to have specific knowledge of the individual KMS service and + /// should be used only if absolutely necessary. + /// FALSE otherwise. + /// + BOOLEAN ClientDataSupported; + /// + /// The maximum size in bytes for the client data. If the maximum data size is not specified + /// by the KMS or it is not known, then this field must be filled with all ones. + /// + UINTN ClientDataMaxSize; + /// + /// TRUE if variable length key identifiers are supported. + /// FALSE if a fixed length key identifier is supported. + /// + BOOLEAN KeyIdVariableLenSupported; + /// + /// If KeyIdVariableLenSupported is TRUE, this is the maximum supported key identifier length + /// in bytes. Otherwise this is the fixed length of key identifier supported. Key ids shorter + /// than the fixed length will be padded on the right with blanks. + /// + UINTN KeyIdMaxSize; + /// + /// The number of key format/size GUIDs returned in the KeyFormats field. + /// + UINTN KeyFormatsCount; + /// + /// A pointer to an array of EFI_GUID values which specify key formats/sizes supported by + /// this KMS. Each format/size pair will be specified by a separate EFI_GUID. At least one + /// key format/size must be supported. All formats/sizes with the same hashing algorithm + /// must be contiguous in the array, and for each hashing algorithm, the key sizes must be in + /// ascending order. See "Related Definitions" for GUIDs which identify supported key formats/sizes. + /// This list of GUIDs supported by the KMS is not required to be exhaustive, and the KMS + /// may provide support for additional key formats/sizes. Users may request key information + /// using an arbitrary GUID, but any GUID not recognized by the implementation or not + /// supported by the KMS will return an error code of EFI_UNSUPPORTED + /// + EFI_GUID *KeyFormats; + /// + /// TRUE if key attributes are supported. + /// FALSE if key attributes are not supported. + /// + BOOLEAN KeyAttributesSupported; + /// + /// The key attribute identifier string type(s) supported by the KMS service. If key attributes + /// are not supported, this field will be set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it will + /// be set to the inclusive 'OR' of all key attribute identifier string types supported. + /// EFI_KMS_DATA_TYPE_BINARY is not valid for this field. + /// + UINT8 KeyAttributeIdStringTypes; + UINT16 KeyAttributeIdMaxCount; + /// + /// The number of predefined KeyAttributes structures returned in the KeyAttributes + /// parameter. If the KMS does not support predefined key attributes, or if it does not + /// provide a method to obtain predefined key attributes data, then this field must be zero. + /// + UINTN KeyAttributesCount; + /// + /// A pointer to an array of KeyAttributes structures which contains the predefined + /// attributes supported by this KMS. Each structure must contain a valid key attribute + /// identifier and should provide any other information as appropriate for the attribute, + /// including a default value if one exists. This variable must be set to NULL if the + /// KeyAttributesCount variable is zero. It must point to a valid buffer if the + /// KeyAttributesCount variable is non-zero. + /// This list of predefined attributes is not required to be exhaustive, and the KMS may + /// provide additional predefined attributes not enumerated in this list. The implementation + /// does not distinguish between predefined and used defined attributes, and therefore, + /// predefined attributes not enumerated will still be processed to the KMS. + /// + EFI_KMS_KEY_ATTRIBUTE *KeyAttributes; +}; + +extern EFI_GUID gEfiKmsFormatGeneric128Guid; +extern EFI_GUID gEfiKmsFormatGeneric160Guid; +extern EFI_GUID gEfiKmsFormatGeneric256Guid; +extern EFI_GUID gEfiKmsFormatGeneric512Guid; +extern EFI_GUID gEfiKmsFormatGeneric1024Guid; +extern EFI_GUID gEfiKmsFormatGeneric2048Guid; +extern EFI_GUID gEfiKmsFormatGeneric3072Guid; +extern EFI_GUID gEfiKmsFormatMd2128Guid; +extern EFI_GUID gEfiKmsFormatMdc2128Guid; +extern EFI_GUID gEfiKmsFormatMd4128Guid; +extern EFI_GUID gEfiKmsFormatMdc4128Guid; +extern EFI_GUID gEfiKmsFormatMd5128Guid; +extern EFI_GUID gEfiKmsFormatMd5sha128Guid; +extern EFI_GUID gEfiKmsFormatSha1160Guid; +extern EFI_GUID gEfiKmsFormatSha256256Guid; +extern EFI_GUID gEfiKmsFormatSha512512Guid; +extern EFI_GUID gEfiKmsFormatAesxts128Guid; +extern EFI_GUID gEfiKmsFormatAesxts256Guid; +extern EFI_GUID gEfiKmsFormatAescbc128Guid; +extern EFI_GUID gEfiKmsFormatAescbc256Guid; +extern EFI_GUID gEfiKmsFormatRsasha11024Guid; +extern EFI_GUID gEfiKmsFormatRsasha12048Guid; +extern EFI_GUID gEfiKmsFormatRsasha2562048Guid; +extern EFI_GUID gEfiKmsFormatRsasha2563072Guid; +extern EFI_GUID gEfiKmsProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacyRegion2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacyRegion2.h new file mode 100644 index 0000000000..4a21784ce3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacyRegion2.h @@ -0,0 +1,233 @@ +/** @file + The Legacy Region Protocol controls the read, write and boot-lock attributes for + the region 0xC0000 to 0xFFFFF. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef __LEGACY_REGION2_H__ +#define __LEGACY_REGION2_H__ + + +#define EFI_LEGACY_REGION2_PROTOCOL_GUID \ +{ \ + 0x70101eaf, 0x85, 0x440c, {0xb3, 0x56, 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } \ +} + +typedef struct _EFI_LEGACY_REGION2_PROTOCOL EFI_LEGACY_REGION2_PROTOCOL; + +/** + Modify the hardware to allow (decode) or disallow (not decode) memory reads in a region. + + If the On parameter evaluates to TRUE, this function enables memory reads in the address range + Start to (Start + Length - 1). + If the On parameter evaluates to FALSE, this function disables memory reads in the address range + Start to (Start + Length - 1). + + @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance. + @param Start[in] The beginning of the physical address of the region whose attributes + should be modified. + @param Length[in] The number of bytes of memory whose attributes should be modified. + The actual number of bytes modified may be greater than the number + specified. + @param Granularity[out] The number of bytes in the last region affected. This may be less + than the total number of bytes affected if the starting address + was not aligned to a region's starting address or if the length + was greater than the number of bytes in the first region. + @param On[in] Decode / Non-Decode flag. + + @retval EFI_SUCCESS The region's attributes were successfully modified. + @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_REGION2_DECODE)( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity, + IN BOOLEAN *On + ); + + +/** + Modify the hardware to disallow memory writes in a region. + + This function changes the attributes of a memory range to not allow writes. + + @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance. + @param Start[in] The beginning of the physical address of the region whose + attributes should be modified. + @param Length[in] The number of bytes of memory whose attributes should be modified. + The actual number of bytes modified may be greater than the number + specified. + @param Granularity[out] The number of bytes in the last region affected. This may be less + than the total number of bytes affected if the starting address was + not aligned to a region's starting address or if the length was + greater than the number of bytes in the first region. + + @retval EFI_SUCCESS The region's attributes were successfully modified. + @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_REGION2_LOCK)( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity + ); + + +/** + Modify the hardware to disallow memory attribute changes in a region. + + This function makes the attributes of a region read only. Once a region is boot-locked with this + function, the read and write attributes of that region cannot be changed until a power cycle has + reset the boot-lock attribute. Calls to Decode(), Lock() and Unlock() will have no effect. + + @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance. + @param Start[in] The beginning of the physical address of the region whose + attributes should be modified. + @param Length[in] The number of bytes of memory whose attributes should be modified. + The actual number of bytes modified may be greater than the number + specified. + @param Granularity[out] The number of bytes in the last region affected. This may be less + than the total number of bytes affected if the starting address was + not aligned to a region's starting address or if the length was + greater than the number of bytes in the first region. + + @retval EFI_SUCCESS The region's attributes were successfully modified. + @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region. + @retval EFI_UNSUPPORTED The chipset does not support locking the configuration registers in + a way that will not affect memory regions outside the legacy memory + region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_REGION2_BOOT_LOCK)( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL + ); + + +/** + Modify the hardware to allow memory writes in a region. + + This function changes the attributes of a memory range to allow writes. + + @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance. + @param Start[in] The beginning of the physical address of the region whose + attributes should be modified. + @param Length[in] The number of bytes of memory whose attributes should be modified. + The actual number of bytes modified may be greater than the number + specified. + @param Granularity[out] The number of bytes in the last region affected. This may be less + than the total number of bytes affected if the starting address was + not aligned to a region's starting address or if the length was + greater than the number of bytes in the first region. + + @retval EFI_SUCCESS The region's attributes were successfully modified. + @retval EFI_INVALID_PARAMETER If Start or Length describe an address not in the Legacy Region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_REGION2_UNLOCK)( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity + ); + + +typedef enum { + LegacyRegionDecoded, ///< This region is currently set to allow reads. + LegacyRegionNotDecoded, ///< This region is currently set to not allow reads. + LegacyRegionWriteEnabled, ///< This region is currently set to allow writes. + LegacyRegionWriteDisabled, ///< This region is currently set to write protected. + LegacyRegionBootLocked, ///< This region's attributes are locked, cannot be modified until + ///< after a power cycle. + LegacyRegionNotLocked ///< This region's attributes are not locked. +} EFI_LEGACY_REGION_ATTRIBUTE; + + +typedef struct { + /// + /// The beginning of the physical address of this + /// region. + /// + UINT32 Start; + /// + /// The number of bytes in this region. + /// + UINT32 Length; + /// + /// Attribute of the Legacy Region Descriptor that + /// describes the capabilities for that memory region. + /// + EFI_LEGACY_REGION_ATTRIBUTE Attribute; + /// + /// Describes the byte length programmability + /// associated with the Start address and the specified + /// Attribute setting. + UINT32 Granularity; +} EFI_LEGACY_REGION_DESCRIPTOR; + + +/** + Get region information for the attributes of the Legacy Region. + + This function is used to discover the granularity of the attributes for the memory in the legacy + region. Each attribute may have a different granularity and the granularity may not be the same + for all memory ranges in the legacy region. + + @param This[in] Indicates the EFI_LEGACY_REGION2_PROTOCOL instance. + @param DescriptorCount[out] The number of region descriptor entries returned in the Descriptor + buffer. + @param Descriptor[out] A pointer to a pointer used to return a buffer where the legacy + region information is deposited. This buffer will contain a list of + DescriptorCount number of region descriptors. This function will + provide the memory for the buffer. + + @retval EFI_SUCCESS The information structure was returned. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_REGION_GET_INFO)( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + OUT UINT32 *DescriptorCount, + OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor + ); + + +/// +/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory +/// attributes of the Option ROM shadowing region, 0xC0000 to 0xFFFFF. +/// There are three memory attributes that can be modified through this protocol: read, write and +/// boot-lock. These protocols may be set in any combination. +/// +struct _EFI_LEGACY_REGION2_PROTOCOL { + EFI_LEGACY_REGION2_DECODE Decode; + EFI_LEGACY_REGION2_LOCK Lock; + EFI_LEGACY_REGION2_BOOT_LOCK BootLock; + EFI_LEGACY_REGION2_UNLOCK UnLock; + EFI_LEGACY_REGION_GET_INFO GetInfo; +}; + +extern EFI_GUID gEfiLegacyRegion2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiController.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiController.h new file mode 100644 index 0000000000..d08741d5ed --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiController.h @@ -0,0 +1,259 @@ +/** @file + This file defines the Legacy SPI Controller Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__ +#define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__ + +/// +/// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID +/// definition. This definition assumes it was supposed to be '1'. +/// +/// Global ID for the Legacy SPI Controller Protocol +/// +#define EFI_LEGACY_SPI_CONTROLLER_GUID \ + { 0x39136fc7, 0x1a11, 0x49de, \ + { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }} + +typedef +struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL +EFI_LEGACY_SPI_CONTROLLER_PROTOCOL; + +/** + Set the erase block opcode. + + This routine must be called at or below TPL_NOTIFY. + The menu table contains SPI transaction opcodes which are accessible after + the legacy SPI flash controller's configuration is locked. The board layer + specifies the erase block size for the SPI NOR flash part. The SPI NOR flash + peripheral driver selects the erase block opcode which matches the erase + block size and uses this API to load the opcode into the opcode menu table. + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL + structure. + @param[in] EraseBlockOpcode Erase block opcode to be placed into the opcode + menu table. + + @retval EFI_SUCCESS The opcode menu table was updated + @retval EFI_ACCESS_ERROR The SPI controller is locked + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This, + IN UINT8 EraseBlockOpcode + ); + +/** + Set the write status prefix opcode. + + This routine must be called at or below TPL_NOTIFY. + The prefix table contains SPI transaction write prefix opcodes which are + accessible after the legacy SPI flash controller's configuration is locked. + The board layer specifies the write status prefix opcode for the SPI NOR + flash part. The SPI NOR flash peripheral driver uses this API to load the + opcode into the prefix table. + + @param[in] This Pointer to an + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure. + @param[in] WriteStatusPrefix Prefix opcode for the write status command. + + @retval EFI_SUCCESS The prefix table was updated + @retval EFI_ACCESS_ERROR The SPI controller is locked + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This, + IN UINT8 WriteStatusPrefix + ); + +/** + Set the BIOS base address. + + This routine must be called at or below TPL_NOTIFY. + The BIOS base address works with the protect range registers to protect + portions of the SPI NOR flash from erase and write operat ions. The BIOS + calls this API prior to passing control to the OS loader. + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL + structure. + @param[in] BiosBaseAddress The BIOS base address. + + @retval EFI_SUCCESS The BIOS base address was properly set + @retval EFI_ACCESS_ERROR The SPI controller is locked + @retval EFI_INVALID_PARAMETER The BIOS base address is greater than + This->Maxi.mumOffset + @retval EFI_UNSUPPORTED The BIOS base address was already set + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This, + IN UINT32 BiosBaseAddress + ); + +/** + Clear the SPI protect range registers. + + This routine must be called at or below TPL_NOTIFY. + The BIOS uses this routine to set an initial condition on the SPI protect + range registers. + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure. + + @retval EFI_SUCCESS The registers were successfully cleared + @retval EFI_ACCESS_ERROR The SPI controller is locked + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This + ); + +/** + Determine if the SPI range is protected. + + This routine must be called at or below TPL_NOTIFY. + The BIOS uses this routine to verify a range in the SPI is protected. + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL + structure. + @param[in] BiosAddress Address within a 4 KiB block to start protecting. + @param[in] BytesToProtect The number of 4 KiB blocks to protect. + + @retval TRUE The range is protected + @retval FALSE The range is not protected + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This, + IN UINT32 BiosAddress, + IN UINT32 BlocksToProtect + ); + +/** + Set the next protect range register. + + This routine must be called at or below TPL_NOTIFY. + The BIOS sets the protect range register to prevent write and erase + operations to a portion of the SPI NOR flash device. + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL + structure. + @param[in] BiosAddress Address within a 4 KiB block to start protecting. + @param[in] BlocksToProtect The number of 4 KiB blocks to protect. + + @retval EFI_SUCCESS The register was successfully updated + @retval EFI_ACCESS_ERROR The SPI controller is locked + @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or + BlocksToProtect * 4 KiB + > This->MaximumRangeBytes, or + BiosAddress - This->BiosBaseAddress + + (BlocksToProtect * 4 KiB) + > This->MaximumRangeBytes + @retval EFI_OUT_OF_RESOURCES No protect range register available + @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS base + address is not set + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This, + IN UINT32 BiosAddress, + IN UINT32 BlocksToProtect + ); + +/** + Lock the SPI controller configuration. + + This routine must be called at or below TPL_NOTIFY. + This routine locks the SPI controller's configuration so that the software + is no longer able to update: + * Prefix table + * Opcode menu + * Opcode type table + * BIOS base address + * Protect range registers + + @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure. + + @retval EFI_SUCCESS The SPI controller was successfully locked + @retval EFI_ALREADY_STARTED The SPI controller was already locked + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER) ( + IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This + ); + +/// +/// Support the extra features of the legacy SPI flash controller. +/// +struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL { + /// + /// Maximum offset from the BIOS base address that is able to be protected. + /// + UINT32 MaximumOffset; + + /// + /// Maximum number of bytes that can be protected by one range register. + /// + UINT32 MaximumRangeBytes; + + /// + /// The number of registers available for protecting the BIOS. + /// + UINT32 RangeRegisterCount; + + /// + /// Set the erase block opcode. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode; + + /// + /// Set the write status prefix opcode. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix; + + /// + /// Set the BIOS base address. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress; + + /// + /// Clear the SPI protect range registers. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect; + + /// + /// Determine if the SPI range is protected. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected; + + /// + /// Set the next protect range register. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange; + + /// + /// Lock the SPI controller configuration. + /// + EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController; +}; + +extern EFI_GUID gEfiLegacySpiControllerProtocolGuid; + +#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiFlash.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiFlash.h new file mode 100644 index 0000000000..539ecedb26 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiFlash.h @@ -0,0 +1,195 @@ +/** @file + This file defines the Legacy SPI Flash Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __LEGACY_SPI_FLASH_PROTOCOL_H__ +#define __LEGACY_SPI_FLASH_PROTOCOL_H__ + +#include + +/// +/// Global ID for the Legacy SPI Flash Protocol +/// +#define EFI_LEGACY_SPI_FLASH_PROTOCOL_GUID \ + { 0xf01bed57, 0x04bc, 0x4f3f, \ + { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }} + +typedef struct _EFI_LEGACY_SPI_FLASH_PROTOCOL EFI_LEGACY_SPI_FLASH_PROTOCOL; + +/** + Set the BIOS base address. + + This routine must be called at or below TPL_NOTIFY. + The BIOS base address works with the protect range registers to protect + portions of the SPI NOR flash from erase and write operat ions. + The BIOS calls this API prior to passing control to the OS loader. + + @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data + structure. + @param[in] BiosBaseAddress The BIOS base address. + + @retval EFI_SUCCESS The BIOS base address was properly set + @retval EFI_ACCESS_ERROR The SPI controller is locked + @retval EFI_INVALID_PARAMETER BiosBaseAddress > This->MaximumOffset + @retval EFI_UNSUPPORTED The BIOS base address was already set or not a + legacy SPI host controller + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS) ( + IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This, + IN UINT32 BiosBaseAddress + ); + +/** + Clear the SPI protect range registers. + + This routine must be called at or below TPL_NOTIFY. + The BIOS uses this routine to set an initial condition on the SPI protect + range registers. + + @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure. + + @retval EFI_SUCCESS The registers were successfully cleared + @retval EFI_ACCESS_ERROR The SPI controller is locked + @retval EFI_UNSUPPORTED Not a legacy SPI host controller + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT) ( + IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This + ); + +/** + Determine if the SPI range is protected. + + This routine must be called at or below TPL_NOTIFY. + The BIOS uses this routine to verify a range in the SPI is protected. + + @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data + structure. + @param[in] BiosAddress Address within a 4 KiB block to start protecting. + @param[in] BlocksToProtect The number of 4 KiB blocks to protect. + + @retval TRUE The range is protected + @retval FALSE The range is not protected + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED) ( + IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This, + IN UINT32 BiosAddress, + IN UINT32 BlocksToProtect + ); + +/** + Set the next protect range register. + + This routine must be called at or below TPL_NOTIFY. + The BIOS sets the protect range register to prevent write and erase + operations to a portion of the SPI NOR flash device. + + @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data + structure. + @param[in] BiosAddress Address within a 4 KiB block to start protecting. + @param[in] BlocksToProtect The number of 4 KiB blocks to protect. + + @retval EFI_SUCCESS The register was successfully updated + @retval EFI_ACCESS_ERROR The SPI controller is locked + @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or + @retval EFI_INVALID_PARAMETER BlocksToProtect * 4 KiB + > This->MaximumRangeBytes, or + BiosAddress - This->BiosBaseAddress + + (BlocksToProtect * 4 KiB) + > This->MaximumRangeBytes + @retval EFI_OUT_OF_RESOURCES No protect range register available + @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS + base address is not set Not a legacy SPI host + controller + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE) ( + IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This, + IN UINT32 BiosAddress, + IN UINT32 BlocksToProtect + ); + +/** + Lock the SPI controller configuration. + + This routine must be called at or below TPL_NOTIFY. + This routine locks the SPI controller's configuration so that the software is + no longer able to update: + * Prefix table + * Opcode menu + * Opcode type table + * BIOS base address + * Protect range registers + + @param[in] This Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure. + + @retval EFI_SUCCESS The SPI controller was successfully locked + @retval EFI_ALREADY_STARTED The SPI controller was already locked + @retval EFI_UNSUPPORTED Not a legacy SPI host controller +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER) ( + IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This + ); + +/// +/// The EFI_LEGACY_SPI_FLASH_PROTOCOL extends the EFI_SPI_NOR_FLASH_PROTOCOL +/// with APls to support the legacy SPI flash controller. +/// +struct _EFI_LEGACY_SPI_FLASH_PROTOCOL { + /// + /// This protocol manipulates the SPI NOR flash parts using a common set of + /// commands. + /// + EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol; + + // + // Legacy flash (SPI host) controller support + // + + /// + /// Set the BIOS base address. + /// + EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress; + + /// + /// Clear the SPI protect range registers. + /// + EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect; + + /// + /// Determine if the SPI range is protected. + /// + EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected; + + /// + /// Set the next protect range register. + /// + EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange; + + /// + /// Lock the SPI controller configuration. + /// + EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController; +}; + +extern EFI_GUID gEfiLegacySpiFlashProtocolGuid; + +#endif // __LEGACY_SPI_FLASH_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmController.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmController.h new file mode 100644 index 0000000000..e4fa7d9672 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmController.h @@ -0,0 +1,30 @@ +/** @file + This file defines the Legacy SPI SMM Controler Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__ +#define __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__ + +#include + +/// +/// Global ID for the Legacy SPI SMM Controller Protocol +/// +#define EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_GUID \ + { 0x62331b78, 0xd8d0, 0x4c8c, \ + { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }} + +typedef +struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL +EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL; + +extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid; + +#endif // __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmFlash.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmFlash.h new file mode 100644 index 0000000000..6e3f234065 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LegacySpiSmmFlash.h @@ -0,0 +1,30 @@ +/** @file + This file defines the Legacy SPI SMM Flash Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__ +#define __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__ + +#include + +/// +/// Global ID for the Legacy SPI SMM Flash Protocol +/// +#define EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL_GUID \ + { 0x5e3848d4, 0x0db5, 0x4fc0, \ + { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }} + +typedef +struct _EFI_LEGACY_SPI_FLASH_PROTOCOL +EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL; + +extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid; + +#endif // __SPI_SMM_FLASH_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile.h new file mode 100644 index 0000000000..1c2890feae --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile.h @@ -0,0 +1,82 @@ +/** @file + Load File protocol as defined in the UEFI 2.0 specification. + + The load file protocol exists to supports the addition of new boot devices, + and to support booting from devices that do not map well to file system. + Network boot is done via a LoadFile protocol. + + UEFI 2.0 can boot from any device that produces a LoadFile protocol. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_LOAD_FILE_PROTOCOL_H__ +#define __EFI_LOAD_FILE_PROTOCOL_H__ + +#define EFI_LOAD_FILE_PROTOCOL_GUID \ + { \ + 0x56EC3091, 0x954C, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B } \ + } + +/// +/// Protocol Guid defined by EFI1.1. +/// +#define LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL_GUID + +typedef struct _EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL; + +/// +/// Backward-compatible with EFI1.1 +/// +typedef EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_INTERFACE; + +/** + Causes the driver to load a specified file. + + @param This Protocol instance pointer. + @param FilePath The device specific path of the file to load. + @param BootPolicy If TRUE, indicates that the request originates from the + boot manager is attempting to load FilePath as a boot + selection. If FALSE, then FilePath must match as exact file + to be loaded. + @param BufferSize On input the size of Buffer in bytes. On output with a return + code of EFI_SUCCESS, the amount of data transferred to + Buffer. On output with a return code of EFI_BUFFER_TOO_SMALL, + the size of Buffer required to retrieve the requested file. + @param Buffer The memory buffer to transfer the file to. IF Buffer is NULL, + then the size of the requested file is returned in + BufferSize. + + @retval EFI_SUCCESS The file was loaded. + @retval EFI_UNSUPPORTED The device does not support the provided BootPolicy + @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or + BufferSize is NULL. + @retval EFI_NO_MEDIA No medium was present to load the file. + @retval EFI_DEVICE_ERROR The file was not loaded due to a device error. + @retval EFI_NO_RESPONSE The remote system did not respond. + @retval EFI_NOT_FOUND The file was not found. + @retval EFI_ABORTED The file load process was manually cancelled. + @retval EFI_WARN_FILE_SYSTEM The resulting Buffer contains UEFI-compliant file system. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOAD_FILE)( + IN EFI_LOAD_FILE_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *FilePath, + IN BOOLEAN BootPolicy, + IN OUT UINTN *BufferSize, + IN VOID *Buffer OPTIONAL + ); + +/// +/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices. +/// +struct _EFI_LOAD_FILE_PROTOCOL { + EFI_LOAD_FILE LoadFile; +}; + +extern EFI_GUID gEfiLoadFileProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile2.h new file mode 100644 index 0000000000..52105a1bfb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadFile2.h @@ -0,0 +1,79 @@ +/** @file + Load File protocol as defined in the UEFI 2.0 specification. + + Load file protocol exists to supports the addition of new boot devices, + and to support booting from devices that do not map well to file system. + Network boot is done via a LoadFile protocol. + + UEFI 2.0 can boot from any device that produces a LoadFile protocol. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_LOAD_FILE2_PROTOCOL_H__ +#define __EFI_LOAD_FILE2_PROTOCOL_H__ + +#define EFI_LOAD_FILE2_PROTOCOL_GUID \ + { \ + 0x4006c0c1, 0xfcb3, 0x403e, {0x99, 0x6d, 0x4a, 0x6c, 0x87, 0x24, 0xe0, 0x6d } \ + } + +/// +/// Protocol Guid defined by UEFI2.1. +/// +#define LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL_GUID + +typedef struct _EFI_LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL; + + +/** + Causes the driver to load a specified file. + + @param This Protocol instance pointer. + @param FilePath The device specific path of the file to load. + @param BootPolicy Should always be FALSE. + @param BufferSize On input the size of Buffer in bytes. On output with a return + code of EFI_SUCCESS, the amount of data transferred to + Buffer. On output with a return code of EFI_BUFFER_TOO_SMALL, + the size of Buffer required to retrieve the requested file. + @param Buffer The memory buffer to transfer the file to. IF Buffer is NULL, + then no the size of the requested file is returned in + BufferSize. + + @retval EFI_SUCCESS The file was loaded. + @retval EFI_UNSUPPORTED BootPolicy is TRUE. + @retval EFI_INVALID_PARAMETER FilePath is not a valid device path, or + BufferSize is NULL. + @retval EFI_NO_MEDIA No medium was present to load the file. + @retval EFI_DEVICE_ERROR The file was not loaded due to a device error. + @retval EFI_NO_RESPONSE The remote system did not respond. + @retval EFI_NOT_FOUND The file was not found + @retval EFI_ABORTED The file load process was manually canceled. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current + directory entry. BufferSize has been updated with + the size needed to complete the request. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOAD_FILE2)( + IN EFI_LOAD_FILE2_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *FilePath, + IN BOOLEAN BootPolicy, + IN OUT UINTN *BufferSize, + IN VOID *Buffer OPTIONAL + ); + +/// +/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices. +/// +struct _EFI_LOAD_FILE2_PROTOCOL { + EFI_LOAD_FILE2 LoadFile; +}; + +extern EFI_GUID gEfiLoadFile2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadedImage.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadedImage.h new file mode 100644 index 0000000000..6b4aee651a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/LoadedImage.h @@ -0,0 +1,82 @@ +/** @file + UEFI 2.0 Loaded image protocol definition. + + Every EFI driver and application is passed an image handle when it is loaded. + This image handle will contain a Loaded Image Protocol. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __LOADED_IMAGE_PROTOCOL_H__ +#define __LOADED_IMAGE_PROTOCOL_H__ + +#define EFI_LOADED_IMAGE_PROTOCOL_GUID \ + { \ + 0x5B1B31A1, 0x9562, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B } \ + } + +#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \ + { \ + 0xbc62157e, 0x3e33, 0x4fec, {0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf } \ + } + +/// +/// Protocol GUID defined in EFI1.1. +/// +#define LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE_PROTOCOL_GUID + +/// +/// EFI_SYSTEM_TABLE & EFI_IMAGE_UNLOAD are defined in EfiApi.h +/// +#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000 + +/// +/// Revision defined in EFI1.1. +/// +#define EFI_LOADED_IMAGE_INFORMATION_REVISION EFI_LOADED_IMAGE_PROTOCOL_REVISION + +/// +/// Can be used on any image handle to obtain information about the loaded image. +/// +typedef struct { + UINT32 Revision; ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure. + ///< All future revisions will be backward compatible to the current revision. + EFI_HANDLE ParentHandle; ///< Parent image's image handle. NULL if the image is loaded directly from + ///< the firmware's boot manager. + EFI_SYSTEM_TABLE *SystemTable; ///< the image's EFI system table pointer. + + // + // Source location of image + // + EFI_HANDLE DeviceHandle; ///< The device handle that the EFI Image was loaded from. + EFI_DEVICE_PATH_PROTOCOL *FilePath; ///< A pointer to the file path portion specific to DeviceHandle + ///< that the EFI Image was loaded from. + VOID *Reserved; ///< Reserved. DO NOT USE. + + // + // Images load options + // + UINT32 LoadOptionsSize;///< The size in bytes of LoadOptions. + VOID *LoadOptions; ///< A pointer to the image's binary load options. + + // + // Location of where image was loaded + // + VOID *ImageBase; ///< The base address at which the image was loaded. + UINT64 ImageSize; ///< The size in bytes of the loaded image. + EFI_MEMORY_TYPE ImageCodeType; ///< The memory type that the code sections were loaded as. + EFI_MEMORY_TYPE ImageDataType; ///< The memory type that the data sections were loaded as. + EFI_IMAGE_UNLOAD Unload; +} EFI_LOADED_IMAGE_PROTOCOL; + +// +// For backward-compatible with EFI1.1. +// +typedef EFI_LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE; + +extern EFI_GUID gEfiLoadedImageProtocolGuid; +extern EFI_GUID gEfiLoadedImageDevicePathProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ManagedNetwork.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ManagedNetwork.h new file mode 100644 index 0000000000..4617afbc18 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ManagedNetwork.h @@ -0,0 +1,366 @@ +/** @file + EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0. + EFI_MANAGED_NETWORK_PROTOCOL as defined in UEFI 2.0. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0 + +**/ + +#ifndef __EFI_MANAGED_NETWORK_PROTOCOL_H__ +#define __EFI_MANAGED_NETWORK_PROTOCOL_H__ + +#include + +#define EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xf36ff770, 0xa7e1, 0x42cf, {0x9e, 0xd2, 0x56, 0xf0, 0xf2, 0x71, 0xf4, 0x4c } \ + } + +#define EFI_MANAGED_NETWORK_PROTOCOL_GUID \ + { \ + 0x7ab33a91, 0xace5, 0x4326, { 0xb5, 0x72, 0xe7, 0xee, 0x33, 0xd3, 0x9f, 0x16 } \ + } + +typedef struct _EFI_MANAGED_NETWORK_PROTOCOL EFI_MANAGED_NETWORK_PROTOCOL; + +typedef struct { + /// + /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed + /// from the MNP receive queue will be dropped if its receive timeout expires. + /// + UINT32 ReceivedQueueTimeoutValue; + /// + /// Timeout value for a UEFI one-shot timer event. A packet that has not been removed + /// from the MNP transmit queue will be dropped if its receive timeout expires. + /// + UINT32 TransmitQueueTimeoutValue; + /// + /// Ethernet type II 16-bit protocol type in host byte order. Valid + /// values are zero and 1,500 to 65,535. + /// + UINT16 ProtocolTypeFilter; + /// + /// Set to TRUE to receive packets that are sent to the network + /// device MAC address. The startup default value is FALSE. + /// + BOOLEAN EnableUnicastReceive; + /// + /// Set to TRUE to receive packets that are sent to any of the + /// active multicast groups. The startup default value is FALSE. + /// + BOOLEAN EnableMulticastReceive; + /// + /// Set to TRUE to receive packets that are sent to the network + /// device broadcast address. The startup default value is FALSE. + /// + BOOLEAN EnableBroadcastReceive; + /// + /// Set to TRUE to receive packets that are sent to any MAC address. + /// The startup default value is FALSE. + /// + BOOLEAN EnablePromiscuousReceive; + /// + /// Set to TRUE to drop queued packets when the configuration + /// is changed. The startup default value is FALSE. + /// + BOOLEAN FlushQueuesOnReset; + /// + /// Set to TRUE to timestamp all packets when they are received + /// by the MNP. Note that timestamps may be unsupported in some + /// MNP implementations. The startup default value is FALSE. + /// + BOOLEAN EnableReceiveTimestamps; + /// + /// Set to TRUE to disable background polling in this MNP + /// instance. Note that background polling may not be supported in + /// all MNP implementations. The startup default value is FALSE, + /// unless background polling is not supported. + /// + BOOLEAN DisableBackgroundPolling; +} EFI_MANAGED_NETWORK_CONFIG_DATA; + +typedef struct { + EFI_TIME Timestamp; + EFI_EVENT RecycleEvent; + UINT32 PacketLength; + UINT32 HeaderLength; + UINT32 AddressLength; + UINT32 DataLength; + BOOLEAN BroadcastFlag; + BOOLEAN MulticastFlag; + BOOLEAN PromiscuousFlag; + UINT16 ProtocolType; + VOID *DestinationAddress; + VOID *SourceAddress; + VOID *MediaHeader; + VOID *PacketData; +} EFI_MANAGED_NETWORK_RECEIVE_DATA; + +typedef struct { + UINT32 FragmentLength; + VOID *FragmentBuffer; +} EFI_MANAGED_NETWORK_FRAGMENT_DATA; + +typedef struct { + EFI_MAC_ADDRESS *DestinationAddress; //OPTIONAL + EFI_MAC_ADDRESS *SourceAddress; //OPTIONAL + UINT16 ProtocolType; //OPTIONAL + UINT32 DataLength; + UINT16 HeaderLength; //OPTIONAL + UINT16 FragmentCount; + EFI_MANAGED_NETWORK_FRAGMENT_DATA FragmentTable[1]; +} EFI_MANAGED_NETWORK_TRANSMIT_DATA; + + +typedef struct { + /// + /// This Event will be signaled after the Status field is updated + /// by the MNP. The type of Event must be + /// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// + EFI_EVENT Event; + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// + EFI_STATUS Status; + union { + /// + /// When this token is used for receiving, RxData is a pointer to the EFI_MANAGED_NETWORK_RECEIVE_DATA. + /// + EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to the EFI_MANAGED_NETWORK_TRANSMIT_DATA. + /// + EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData; + } Packet; +} EFI_MANAGED_NETWORK_COMPLETION_TOKEN; + +/** + Returns the operational parameters for the current MNP child driver. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param MnpConfigData The pointer to storage for MNP operational parameters. + @param SnpModeData The pointer to storage for SNP operational parameters. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. The default + values are returned in MnpConfigData if it is not NULL. + @retval Other The mode data could not be read. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_GET_MODE_DATA)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + +/** + Sets or clears the operational parameters for the MNP child driver. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param MnpConfigData The pointer to configuration data that will be assigned to the MNP + child driver instance. If NULL, the MNP child driver instance is + reset to startup defaults and all pending transmit and receive + requests are flushed. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Required system resources (usually memory) could not be + allocated. + @retval EFI_UNSUPPORTED The requested feature is unsupported in this [MNP] + implementation. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval Other The MNP child driver instance has been reset to startup defaults. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_CONFIGURE)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL + ); + +/** + Translates an IP multicast address to a hardware (MAC) multicast address. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param Ipv6Flag Set to TRUE to if IpAddress is an IPv6 multicast address. + Set to FALSE if IpAddress is an IPv4 multicast address. + @param IpAddress The pointer to the multicast IP address (in network byte order) to convert. + @param MacAddress The pointer to the resulting multicast MAC address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One of the following conditions is TRUE: + - This is NULL. + - IpAddress is NULL. + - *IpAddress is not a valid multicast IP address. + - MacAddress is NULL. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval Other The address could not be converted. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN BOOLEAN Ipv6Flag, + IN EFI_IP_ADDRESS *IpAddress, + OUT EFI_MAC_ADDRESS *MacAddress + ); + +/** + Enables and disables receive filters for multicast address. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param JoinFlag Set to TRUE to join this multicast group. + Set to FALSE to leave this multicast group. + @param MacAddress The pointer to the multicast MAC group (address) to join or leave. + + @retval EFI_SUCCESS The requested operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - JoinFlag is TRUE and MacAddress is NULL. + - *MacAddress is not a valid multicast MAC address. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_ALREADY_STARTED The supplied multicast group is already joined. + @retval EFI_NOT_FOUND The supplied multicast group is not joined. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_UNSUPPORTED The requested feature is unsupported in this MNP implementation. + @retval Other The requested operation could not be completed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_GROUPS)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN BOOLEAN JoinFlag, + IN EFI_MAC_ADDRESS *MacAddress OPTIONAL + ); + +/** + Places asynchronous outgoing data packets into the transmit queue. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param Token The pointer to a token associated with the transmit data descriptor. + + @retval EFI_SUCCESS The transmit completion token was cached. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_ACCESS_DENIED The transmit completion token is already in the transmit queue. + @retval EFI_OUT_OF_RESOURCES The transmit data could not be queued due to a lack of system resources + (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY The transmit request could not be queued because the transmit queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_TRANSMIT)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token + ); + +/** + Places an asynchronous receiving request into the receiving queue. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param Token The pointer to a token associated with the receive data descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The transmit data could not be queued due to a lack of system resources + (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_ACCESS_DENIED The receive completion token was already in the receive queue. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_RECEIVE)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token + ); + + +/** + Aborts an asynchronous transmit or receive request. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + @param Token The pointer to a token that has been issued by + EFI_MANAGED_NETWORK_PROTOCOL.Transmit() or + EFI_MANAGED_NETWORK_PROTOCOL.Receive(). If + NULL, all pending tokens are aborted. + + @retval EFI_SUCCESS The asynchronous I/O request was aborted and Token.Event + was signaled. When Token is NULL, all pending requests were + aborted and their events were signaled. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was + not found in the transmit or receive queue. It has either completed + or was not issued by Transmit() and Receive(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_CANCEL)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This, + IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token OPTIONAL + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + @param This The pointer to the EFI_MANAGED_NETWORK_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This MNP child driver instance has not been configured. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY No incoming or outgoing data was processed. Consider increasing + the polling rate. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MANAGED_NETWORK_POLL)( + IN EFI_MANAGED_NETWORK_PROTOCOL *This + ); + +/// +/// The MNP is used by network applications (and drivers) to +/// perform raw (unformatted) asynchronous network packet I/O. +/// +struct _EFI_MANAGED_NETWORK_PROTOCOL { + EFI_MANAGED_NETWORK_GET_MODE_DATA GetModeData; + EFI_MANAGED_NETWORK_CONFIGURE Configure; + EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC McastIpToMac; + EFI_MANAGED_NETWORK_GROUPS Groups; + EFI_MANAGED_NETWORK_TRANSMIT Transmit; + EFI_MANAGED_NETWORK_RECEIVE Receive; + EFI_MANAGED_NETWORK_CANCEL Cancel; + EFI_MANAGED_NETWORK_POLL Poll; +}; + +extern EFI_GUID gEfiManagedNetworkServiceBindingProtocolGuid; +extern EFI_GUID gEfiManagedNetworkProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Metronome.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Metronome.h new file mode 100644 index 0000000000..624c387c58 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Metronome.h @@ -0,0 +1,74 @@ +/** @file + Metronome Architectural Protocol as defined in PI SPEC VOLUME 2 DXE + + This code abstracts the DXE core to provide delay services. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_METRONOME_H__ +#define __ARCH_PROTOCOL_METRONOME_H__ + +/// +/// Global ID for the Metronome Architectural Protocol +/// +#define EFI_METRONOME_ARCH_PROTOCOL_GUID \ + { 0x26baccb2, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } + +/// +/// Declare forward reference for the Metronome Architectural Protocol +/// +typedef struct _EFI_METRONOME_ARCH_PROTOCOL EFI_METRONOME_ARCH_PROTOCOL; + +/** + The WaitForTick() function waits for the number of ticks specified by + TickNumber from a known time source in the platform. If TickNumber of + ticks are detected, then EFI_SUCCESS is returned. The actual time passed + between entry of this function and the first tick is between 0 and + TickPeriod 100 nS units. If you want to guarantee that at least TickPeriod + time has elapsed, wait for two ticks. This function waits for a hardware + event to determine when a tick occurs. It is possible for interrupt + processing, or exception processing to interrupt the execution of the + WaitForTick() function. Depending on the hardware source for the ticks, it + is possible for a tick to be missed. This function cannot guarantee that + ticks will not be missed. If a timeout occurs waiting for the specified + number of ticks, then EFI_TIMEOUT is returned. + + @param This The EFI_METRONOME_ARCH_PROTOCOL instance. + @param TickNumber Number of ticks to wait. + + @retval EFI_SUCCESS The wait for the number of ticks specified by TickNumber + succeeded. + @retval EFI_TIMEOUT A timeout occurred waiting for the specified number of ticks. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_METRONOME_WAIT_FOR_TICK)( + IN EFI_METRONOME_ARCH_PROTOCOL *This, + IN UINT32 TickNumber + ); + +/// +/// This protocol provides access to a known time source in the platform to the +/// core. The core uses this known time source to produce core services that +/// require calibrated delays. +/// +struct _EFI_METRONOME_ARCH_PROTOCOL { + EFI_METRONOME_WAIT_FOR_TICK WaitForTick; + + /// + /// The period of platform's known time source in 100 nS units. + /// This value on any platform must be at least 10 uS, and must not + /// exceed 200 uS. The value in this field is a constant that must + /// not be modified after the Metronome architectural protocol is + /// installed. All consumers must treat this as a read-only field. + /// + UINT32 TickPeriod; +}; + +extern EFI_GUID gEfiMetronomeArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmAccess.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmAccess.h new file mode 100644 index 0000000000..39c3795603 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmAccess.h @@ -0,0 +1,127 @@ +/** @file + EFI MM Access Protocol as defined in the PI 1.5 specification. + + This protocol is used to control the visibility of the MMRAM on the platform. + It abstracts the location and characteristics of MMRAM. The expectation is + that the north bridge or memory controller would publish this protocol. + + The principal functionality found in the memory controller includes the following: + - Exposing the MMRAM to all non-MM agents, or the "open" state + - Shrouding the MMRAM to all but the MM agents, or the "closed" state + - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be + perturbed by either boot service or runtime agents + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_ACCESS_H_ +#define _MM_ACCESS_H_ + +#define EFI_MM_ACCESS_PROTOCOL_GUID \ + { \ + 0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac } \ + } + + +typedef struct _EFI_MM_ACCESS_PROTOCOL EFI_MM_ACCESS_PROTOCOL; + +/** + Opens the MMRAM area to be accessible by a boot-service driver. + + This function "opens" MMRAM so that it is visible while not inside of MM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function + should return EFI_DEVICE_ERROR if the MMRAM configuration is locked. + + @param[in] This The EFI_MM_ACCESS_PROTOCOL instance. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM. + @retval EFI_DEVICE_ERROR MMRAM cannot be opened, perhaps because it is locked. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_OPEN)( + IN EFI_MM_ACCESS_PROTOCOL *This + ); + +/** + Inhibits access to the MMRAM. + + This function "closes" MMRAM so that it is not visible while outside of MM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. + + @param[in] This The EFI_MM_ACCESS_PROTOCOL instance. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_UNSUPPORTED The system does not support opening and closing of MMRAM. + @retval EFI_DEVICE_ERROR MMRAM cannot be closed. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_CLOSE)( + IN EFI_MM_ACCESS_PROTOCOL *This + ); + +/** + Inhibits access to the MMRAM. + + This function prohibits access to the MMRAM region. This function is usually implemented such + that it is a write-once operation. + + @param[in] This The EFI_MM_ACCESS_PROTOCOL instance. + + @retval EFI_SUCCESS The device was successfully locked. + @retval EFI_UNSUPPORTED The system does not support locking of MMRAM. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_LOCK)( + IN EFI_MM_ACCESS_PROTOCOL *This + ); + +/** + Queries the memory controller for the possible regions that will support MMRAM. + + @param[in] This The EFI_MM_ACCESS_PROTOCOL instance. + @param[in,out] MmramMapSize A pointer to the size, in bytes, of the MmramMemoryMap buffer. + @param[in,out] MmramMap A pointer to the buffer in which firmware places the current memory map. + + @retval EFI_SUCCESS The chipset supported the given resource. + @retval EFI_BUFFER_TOO_SMALL The MmramMap parameter was too small. The current buffer size + needed to hold the memory map is returned in MmramMapSize. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_CAPABILITIES)( + IN CONST EFI_MM_ACCESS_PROTOCOL *This, + IN OUT UINTN *MmramMapSize, + IN OUT EFI_MMRAM_DESCRIPTOR *MmramMap + ); + +/// +/// EFI MM Access Protocol is used to control the visibility of the MMRAM on the platform. +/// It abstracts the location and characteristics of MMRAM. The platform should report all +/// MMRAM via EFI_MM_ACCESS_PROTOCOL. The expectation is that the north bridge or memory +/// controller would publish this protocol. +/// +struct _EFI_MM_ACCESS_PROTOCOL { + EFI_MM_OPEN Open; + EFI_MM_CLOSE Close; + EFI_MM_LOCK Lock; + EFI_MM_CAPABILITIES GetCapabilities; + /// + /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is locked. + /// + BOOLEAN LockState; + /// + /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is open. + /// + BOOLEAN OpenState; +}; + +extern EFI_GUID gEfiMmAccessProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmBase.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmBase.h new file mode 100644 index 0000000000..3a8f3e69bb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmBase.h @@ -0,0 +1,81 @@ +/** @file + EFI MM Base Protocol as defined in the PI 1.5 specification. + + This protocol is utilized by all MM drivers to locate the MM infrastructure services and determine + whether the driver is being invoked inside MMRAM or outside of MMRAM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_BASE_H_ +#define _MM_BASE_H_ + +#include + +#define EFI_MM_BASE_PROTOCOL_GUID \ + { \ + 0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 } \ + } + +typedef struct _EFI_MM_BASE_PROTOCOL EFI_MM_BASE_PROTOCOL; + +/** + Service to indicate whether the driver is currently executing in the MM Initialization phase. + + This service is used to indicate whether the driver is currently executing in the MM Initialization + phase. For MM drivers, this will return TRUE in InMmram while inside the driver's entry point and + otherwise FALSE. For combination MM/DXE drivers, this will return FALSE in the DXE launch. For the + MM launch, it behaves as an MM driver. + + @param[in] This The EFI_MM_BASE_PROTOCOL instance. + @param[out] InMmram Pointer to a Boolean which, on return, indicates that the driver is + currently executing inside of MMRAM (TRUE) or outside of MMRAM (FALSE). + + @retval EFI_SUCCESS The call returned successfully. + @retval EFI_INVALID_PARAMETER InMmram was NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_INSIDE_OUT)( + IN CONST EFI_MM_BASE_PROTOCOL *This, + OUT BOOLEAN *InMmram + ) +; + +/** + Returns the location of the Management Mode Service Table (MMST). + + This function returns the location of the Management Mode Service Table (MMST). The use of the + API is such that a driver can discover the location of the MMST in its entry point and then cache it in + some driver global variable so that the MMST can be invoked in subsequent handlers. + + @param[in] This The EFI_MM_BASE_PROTOCOL instance. + @param[in,out] Mmst On return, points to a pointer to the Management Mode Service Table (MMST). + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_INVALID_PARAMETER Mmst was invalid. + @retval EFI_UNSUPPORTED Not in MM. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_GET_MMST_LOCATION)( + IN CONST EFI_MM_BASE_PROTOCOL *This, + IN OUT EFI_MM_SYSTEM_TABLE **Mmst + ) +; + +/// +/// EFI MM Base Protocol is utilized by all MM drivers to locate the MM infrastructure +/// services and determine whether the driver is being invoked inside MMRAM or outside of MMRAM. +/// +struct _EFI_MM_BASE_PROTOCOL { + EFI_MM_INSIDE_OUT InMm; + EFI_MM_GET_MMST_LOCATION GetMmstLocation; +}; + +extern EFI_GUID gEfiMmBaseProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication.h new file mode 100644 index 0000000000..f6e2a6f43f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication.h @@ -0,0 +1,87 @@ +/** @file + EFI MM Communication Protocol as defined in the PI 1.5 specification. + + This protocol provides a means of communicating between drivers outside of MM and MMI + handlers inside of MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_COMMUNICATION_H_ +#define _MM_COMMUNICATION_H_ + +#pragma pack(1) + +/// +/// To avoid confusion in interpreting frames, the communication buffer should always +/// begin with EFI_MM_COMMUNICATE_HEADER +/// +typedef struct { + /// + /// Allows for disambiguation of the message format. + /// + EFI_GUID HeaderGuid; + /// + /// Describes the size of Data (in bytes) and does not include the size of the header. + /// + UINTN MessageLength; + /// + /// Designates an array of bytes that is MessageLength in size. + /// + UINT8 Data[1]; +} EFI_MM_COMMUNICATE_HEADER; + +#pragma pack() + +#define EFI_MM_COMMUNICATION_PROTOCOL_GUID \ + { \ + 0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 } \ + } + +typedef struct _EFI_MM_COMMUNICATION_PROTOCOL EFI_MM_COMMUNICATION_PROTOCOL; + +/** + Communicates with a registered handler. + + This function provides a service to send and receive messages from a registered UEFI service. + + @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance. + @param[in] CommBuffer A pointer to the buffer to convey into MMRAM. + @param[in] CommSize The size of the data buffer being passed in. On exit, the size of data + being returned. Zero if the handler does not wish to reply with any data. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. + @retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation. + If this error is returned, the MessageLength field + in the CommBuffer header or the integer pointed by + CommSize, are updated to reflect the maximum payload + size the implementation can accommodate. + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter, + if not omitted, are in address range that cannot be + accessed by the MM environment. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_COMMUNICATE)( + IN CONST EFI_MM_COMMUNICATION_PROTOCOL *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ); + +/// +/// EFI MM Communication Protocol provides runtime services for communicating +/// between DXE drivers and a registered MMI handler. +/// +struct _EFI_MM_COMMUNICATION_PROTOCOL { + EFI_MM_COMMUNICATE Communicate; +}; + +extern EFI_GUID gEfiMmCommunicationProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication2.h new file mode 100644 index 0000000000..2e02dbc452 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCommunication2.h @@ -0,0 +1,69 @@ +/** @file + EFI MM Communication Protocol 2 as defined in the PI 1.7 errata A specification. + + This protocol provides a means of communicating between drivers outside of MM and MMI + handlers inside of MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2019, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_COMMUNICATION2_H_ +#define _MM_COMMUNICATION2_H_ + +#include + +#define EFI_MM_COMMUNICATION2_PROTOCOL_GUID \ + { \ + 0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 } \ + } + +typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL EFI_MM_COMMUNICATION2_PROTOCOL; + +/** + Communicates with a registered handler. + + This function provides a service to send and receive messages from a registered UEFI service. + + @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance. + @param[in] CommBufferPhysical Physical address of the MM communication buffer + @param[in] CommBufferVirtual Virtual address of the MM communication buffer + @param[in] CommSize The size of the data buffer being passed in. On exit, the size of data + being returned. Zero if the handler does not wish to reply with any data. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER CommBufferPhysical was NULL or CommBufferVirtual was NULL. + @retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation. + If this error is returned, the MessageLength field + in the CommBuffer header or the integer pointed by + CommSize, are updated to reflect the maximum payload + size the implementation can accommodate. + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter, + if not omitted, are in address range that cannot be + accessed by the MM environment. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_COMMUNICATE2)( + IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This, + IN OUT VOID *CommBufferPhysical, + IN OUT VOID *CommBufferVirtual, + IN OUT UINTN *CommSize OPTIONAL + ); + +/// +/// EFI MM Communication Protocol provides runtime services for communicating +/// between DXE drivers and a registered MMI handler. +/// +struct _EFI_MM_COMMUNICATION2_PROTOCOL { + EFI_MM_COMMUNICATE2 Communicate; +}; + +extern EFI_GUID gEfiMmCommunication2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmConfiguration.h new file mode 100644 index 0000000000..485c317196 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmConfiguration.h @@ -0,0 +1,64 @@ +/** @file + EFI MM Configuration Protocol as defined in the PI 1.5 specification. + + This protocol is used to: + 1) report the portions of MMRAM regions which cannot be used for the MMRAM heap. + 2) register the MM Foundation entry point with the processor code. The entry + point will be invoked by the MM processor entry code. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_CONFIGURATION_H_ +#define _MM_CONFIGURATION_H_ + +#include + +#define EFI_MM_CONFIGURATION_PROTOCOL_GUID \ + { \ + 0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 } \ + } + +typedef struct _EFI_MM_CONFIGURATION_PROTOCOL EFI_MM_CONFIGURATION_PROTOCOL; + +/** + Register the MM Foundation entry point. + + This function registers the MM Foundation entry point with the processor code. This entry point + will be invoked by the MM Processor entry code. + + @param[in] This The EFI_MM_CONFIGURATION_PROTOCOL instance. + @param[in] MmEntryPoint MM Foundation entry point. + + @retval EFI_SUCCESS Success to register MM Entry Point. + @retval EFI_INVALID_PARAMETER MmEntryPoint is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_REGISTER_MM_ENTRY)( + IN CONST EFI_MM_CONFIGURATION_PROTOCOL *This, + IN EFI_MM_ENTRY_POINT MmEntryPoint + ); + +/// +/// The EFI MM Configuration Protocol is a mandatory protocol published by a DXE CPU driver to +/// indicate which areas within MMRAM are reserved for use by the CPU for any purpose, +/// such as stack, save state or MM entry point. +/// +/// The RegistermmEntry() function allows the MM IPL DXE driver to register the MM +/// Foundation entry point with the MM entry vector code. +/// +struct _EFI_MM_CONFIGURATION_PROTOCOL { + /// + /// A pointer to an array MMRAM ranges used by the initial MM entry code. + /// + EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions; + EFI_MM_REGISTER_MM_ENTRY RegisterMmEntry; +}; + +extern EFI_GUID gEfiMmConfigurationProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmControl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmControl.h new file mode 100644 index 0000000000..92a5b10efb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmControl.h @@ -0,0 +1,100 @@ +/** @file + EFI MM Control Protocol as defined in the PI 1.5 specification. + + This protocol is used initiate synchronous MMI activations. This protocol could be published by a + processor driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the + APM port. Because of the possibility of performing MMI IPI transactions, the ability to generate this + event from a platform chipset agent is an optional capability for both IA-32 and x64-based systems. + + The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides an + abstraction of the platform hardware that generates an MMI. There are often I/O ports that, when + accessed, will generate the MMI. Also, the hardware optionally supports the periodic generation of + these signals. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_CONTROL_H_ +#define _MM_CONTROL_H_ + +#include + +#define EFI_MM_CONTROL_PROTOCOL_GUID \ + { \ + 0x843dc720, 0xab1e, 0x42cb, {0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b} \ + } + +typedef struct _EFI_MM_CONTROL_PROTOCOL EFI_MM_CONTROL_PROTOCOL; +typedef UINTN EFI_MM_PERIOD; + +/** + Invokes MMI activation from either the preboot or runtime environment. + + This function generates an MMI. + + @param[in] This The EFI_MM_CONTROL_PROTOCOL instance. + @param[in,out] CommandPort The value written to the command port. + @param[in,out] DataPort The value written to the data port. + @param[in] Periodic Optional mechanism to engender a periodic stream. + @param[in] ActivationInterval Optional parameter to repeat at this period one + time or, if the Periodic Boolean is set, periodically. + + @retval EFI_SUCCESS The MMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The timing is unsupported. + @retval EFI_INVALID_PARAMETER The activation period is unsupported. + @retval EFI_INVALID_PARAMETER The last periodic activation has not been cleared. + @retval EFI_NOT_STARTED The MM base service has not been initialized. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_ACTIVATE)( + IN CONST EFI_MM_CONTROL_PROTOCOL *This, + IN OUT UINT8 *CommandPort OPTIONAL, + IN OUT UINT8 *DataPort OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + Clears any system state that was created in response to the Trigger() call. + + This function acknowledges and causes the deassertion of the MMI activation source. + + @param[in] This The EFI_MM_CONTROL_PROTOCOL instance. + @param[in] Periodic Optional parameter to repeat at this period one time + + @retval EFI_SUCCESS The MMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The source could not be cleared. + @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_DEACTIVATE)( + IN CONST EFI_MM_CONTROL_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL + ); + +/// +/// The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides an +/// abstraction of the platform hardware that generates an MMI. There are often I/O ports that, when +/// accessed, will generate the MMI. Also, the hardware optionally supports the periodic generation of +/// these signals. +/// +struct _EFI_MM_CONTROL_PROTOCOL { + EFI_MM_ACTIVATE Trigger; + EFI_MM_DEACTIVATE Clear; + /// + /// Minimum interval at which the platform can set the period. A maximum is not + /// specified in that the MM infrastructure code can emulate a maximum interval that is + /// greater than the hardware capabilities by using software emulation in the MM + /// infrastructure code. + /// + EFI_MM_PERIOD MinimumTriggerPeriod; +}; + +extern EFI_GUID gEfiMmControlProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpu.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpu.h new file mode 100644 index 0000000000..37df7a5fb7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpu.h @@ -0,0 +1,241 @@ +/** @file + EFI MM CPU Protocol as defined in the PI 1.5 specification. + + This protocol allows MM drivers to access architecture-standard registers from any of the CPU + save state areas. In some cases, difference processors provide the same information in the save state, + but not in the same format. These so-called pseudo-registers provide this information in a standard + format. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_CPU_H_ +#define _MM_CPU_H_ + +#define EFI_MM_CPU_PROTOCOL_GUID \ + { \ + 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \ + } + +/// +/// Save State register index +/// +typedef enum { + /// + /// x86/X64 standard registers + /// + EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4, + EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5, + EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6, + EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7, + EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8, + EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9, + EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10, + EFI_MM_SAVE_STATE_REGISTER_ES = 20, + EFI_MM_SAVE_STATE_REGISTER_CS = 21, + EFI_MM_SAVE_STATE_REGISTER_SS = 22, + EFI_MM_SAVE_STATE_REGISTER_DS = 23, + EFI_MM_SAVE_STATE_REGISTER_FS = 24, + EFI_MM_SAVE_STATE_REGISTER_GS = 25, + EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26, + EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27, + EFI_MM_SAVE_STATE_REGISTER_DR7 = 28, + EFI_MM_SAVE_STATE_REGISTER_DR6 = 29, + EFI_MM_SAVE_STATE_REGISTER_R8 = 30, + EFI_MM_SAVE_STATE_REGISTER_R9 = 31, + EFI_MM_SAVE_STATE_REGISTER_R10 = 32, + EFI_MM_SAVE_STATE_REGISTER_R11 = 33, + EFI_MM_SAVE_STATE_REGISTER_R12 = 34, + EFI_MM_SAVE_STATE_REGISTER_R13 = 35, + EFI_MM_SAVE_STATE_REGISTER_R14 = 36, + EFI_MM_SAVE_STATE_REGISTER_R15 = 37, + EFI_MM_SAVE_STATE_REGISTER_RAX = 38, + EFI_MM_SAVE_STATE_REGISTER_RBX = 39, + EFI_MM_SAVE_STATE_REGISTER_RCX = 40, + EFI_MM_SAVE_STATE_REGISTER_RDX = 41, + EFI_MM_SAVE_STATE_REGISTER_RSP = 42, + EFI_MM_SAVE_STATE_REGISTER_RBP = 43, + EFI_MM_SAVE_STATE_REGISTER_RSI = 44, + EFI_MM_SAVE_STATE_REGISTER_RDI = 45, + EFI_MM_SAVE_STATE_REGISTER_RIP = 46, + EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51, + EFI_MM_SAVE_STATE_REGISTER_CR0 = 52, + EFI_MM_SAVE_STATE_REGISTER_CR3 = 53, + EFI_MM_SAVE_STATE_REGISTER_CR4 = 54, + EFI_MM_SAVE_STATE_REGISTER_FCW = 256, + EFI_MM_SAVE_STATE_REGISTER_FSW = 257, + EFI_MM_SAVE_STATE_REGISTER_FTW = 258, + EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259, + EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260, + EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261, + EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262, + EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263, + EFI_MM_SAVE_STATE_REGISTER_MM0 = 264, + EFI_MM_SAVE_STATE_REGISTER_MM1 = 265, + EFI_MM_SAVE_STATE_REGISTER_MM2 = 266, + EFI_MM_SAVE_STATE_REGISTER_MM3 = 267, + EFI_MM_SAVE_STATE_REGISTER_MM4 = 268, + EFI_MM_SAVE_STATE_REGISTER_MM5 = 269, + EFI_MM_SAVE_STATE_REGISTER_MM6 = 270, + EFI_MM_SAVE_STATE_REGISTER_MM7 = 271, + EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272, + EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273, + EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274, + EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275, + EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276, + EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277, + EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278, + EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279, + EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280, + EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281, + EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282, + EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283, + EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284, + EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285, + EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286, + EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287, + /// + /// Pseudo-Registers + /// + EFI_MM_SAVE_STATE_REGISTER_IO = 512, + EFI_MM_SAVE_STATE_REGISTER_LMA = 513, + EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514 +} EFI_MM_SAVE_STATE_REGISTER; + +/// +/// The EFI_MM_SAVE_STATE_REGISTER_LMA pseudo-register values +/// If the processor acts in 32-bit mode at the time the MMI occurred, the pseudo register value +/// EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, +/// EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer. +/// +#define EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT 32 +#define EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT 64 + +/// +/// Size width of I/O instruction +/// +typedef enum { + EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0, + EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1, + EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2, + EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3 +} EFI_MM_SAVE_STATE_IO_WIDTH; + +/// +/// Types of I/O instruction +/// +typedef enum { + EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1, + EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2, + EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4, + EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8 +} EFI_MM_SAVE_STATE_IO_TYPE; + +/// +/// Structure of the data which is returned when ReadSaveState() is called with +/// EFI_MM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will +/// return EFI_NOT_FOUND. +/// +/// This structure describes the I/O operation which was in process when the MMI was generated. +/// +typedef struct _EFI_MM_SAVE_STATE_IO_INFO { + /// + /// For input instruction (IN, INS), this is data read before the MMI occurred. For output + /// instructions (OUT, OUTS) this is data that was written before the MMI occurred. The + /// width of the data is specified by IoWidth. + /// + UINT64 IoData; + /// + /// The I/O port that was being accessed when the MMI was triggered. + /// + UINT16 IoPort; + /// + /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData. + /// + EFI_MM_SAVE_STATE_IO_WIDTH IoWidth; + /// + /// Defines type of I/O instruction. + /// + EFI_MM_SAVE_STATE_IO_TYPE IoType; +} EFI_MM_SAVE_STATE_IO_INFO; + +typedef struct _EFI_MM_CPU_PROTOCOL EFI_MM_CPU_PROTOCOL; + +/** + Read data from the CPU save state. + + This function is used to read the specified number of bytes of the specified register from the CPU + save state of the specified CPU and place the value into the buffer. If the CPU does not support the + specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not + support the specified register width Width, then EFI_INVALID_PARAMETER is returned. + + @param[in] This The EFI_MM_CPU_PROTOCOL instance. + @param[in] Width The number of bytes to read from the CPU save state. + @param[in] Register Specifies the CPU register to read form the save state. + @param[in] CpuIndex Specifies the zero-based index of the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor. + @retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width + is not correct.This or Buffer is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_READ_SAVE_STATE)( + IN CONST EFI_MM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + OUT VOID *Buffer + ); + + +/** + Write data to the CPU save state. + + This function is used to write the specified number of bytes of the specified register to the CPU save + state of the specified CPU and place the value into the buffer. If the CPU does not support the + specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not + support the specified register width Width, then EFI_INVALID_PARAMETER is returned. + + @param[in] This The EFI_MM_CPU_PROTOCOL instance. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Register Specifies the CPU register to write to the save state. + @param[in] CpuIndex Specifies the zero-based index of the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor. + @retval EFI_INVALID_PARAMETER Input parameters are not valid. For example: + ProcessorIndex or Width is not correct. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_WRITE_SAVE_STATE)( + IN CONST EFI_MM_CPU_PROTOCOL *This, + IN UINTN Width, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN CpuIndex, + IN CONST VOID *Buffer + ); + +/// +/// EFI MM CPU Protocol provides access to CPU-related information while in MM. +/// +/// This protocol allows MM drivers to access architecture-standard registers from any of the CPU +/// save state areas. In some cases, difference processors provide the same information in the save state, +/// but not in the same format. These so-called pseudo-registers provide this information in a standard +/// format. +/// +struct _EFI_MM_CPU_PROTOCOL { + EFI_MM_READ_SAVE_STATE ReadSaveState; + EFI_MM_WRITE_SAVE_STATE WriteSaveState; +}; + +extern EFI_GUID gEfiMmCpuProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpuIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpuIo.h new file mode 100644 index 0000000000..f0e7ec6e87 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmCpuIo.h @@ -0,0 +1,90 @@ +/** @file + MM CPU I/O 2 protocol as defined in the PI 1.5 specification. + + This protocol provides CPU I/O and memory access within MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_CPU_IO_H_ +#define _MM_CPU_IO_H_ + +#define EFI_MM_CPU_IO_PROTOCOL_GUID \ + { \ + 0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \ + } + +typedef struct _EFI_MM_CPU_IO_PROTOCOL EFI_MM_CPU_IO_PROTOCOL; + +/// +/// Width of the MM CPU I/O operations +/// +typedef enum { + MM_IO_UINT8 = 0, + MM_IO_UINT16 = 1, + MM_IO_UINT32 = 2, + MM_IO_UINT64 = 3 +} EFI_MM_IO_WIDTH; + +/** + Provides the basic memory and I/O interfaces used toabstract accesses to devices. + + The I/O operations are carried out exactly as requested. The caller is + responsible for any alignment and I/O width issues that the bus, device, + platform, or type of I/O might require. + + @param[in] This The EFI_MM_CPU_IO_PROTOCOL instance. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller is + responsible for aligning the Address if required. + @param[in] Count The number of I/O operations to perform. + @param[in,out] Buffer For read operations, the destination buffer to store + the results. For write operations, the source buffer + from which to write data. + + @retval EFI_SUCCESS The data was read from or written to the device. + @retval EFI_UNSUPPORTED The Address is not valid for this system. + @retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack + of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_CPU_IO)( + IN CONST EFI_MM_CPU_IO_PROTOCOL *This, + IN EFI_MM_IO_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +typedef struct { + /// + /// This service provides the various modalities of memory and I/O read. + /// + EFI_MM_CPU_IO Read; + /// + /// This service provides the various modalities of memory and I/O write. + /// + EFI_MM_CPU_IO Write; +} EFI_MM_IO_ACCESS; + +/// +/// MM CPU I/O Protocol provides CPU I/O and memory access within MM. +/// +struct _EFI_MM_CPU_IO_PROTOCOL { + /// + /// Allows reads and writes to memory-mapped I/O space. + /// + EFI_MM_IO_ACCESS Mem; + /// + /// Allows reads and writes to I/O space. + /// + EFI_MM_IO_ACCESS Io; +}; + +extern EFI_GUID gEfiMmCpuIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmEndOfDxe.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmEndOfDxe.h new file mode 100644 index 0000000000..74f8427efe --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmEndOfDxe.h @@ -0,0 +1,24 @@ +/** @file + MM End Of Dxe protocol introduced in the PI 1.5 specification. + + This protocol is a mandatory protocol published by MM Foundation code. + This protocol is an MM counterpart of the End of DXE Event. + This protocol prorogates End of DXE notification into MM environment. + This protocol is installed prior to installation of the MM Ready to Lock Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_END_OF_DXE_H_ +#define _MM_END_OF_DXE_H_ + +#define EFI_MM_END_OF_DXE_PROTOCOL_GUID \ + { \ + 0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d } \ + } + +extern EFI_GUID gEfiMmEndOfDxeProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmGpiDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmGpiDispatch.h new file mode 100644 index 0000000000..877c0e2a24 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmGpiDispatch.h @@ -0,0 +1,119 @@ +/** @file + MM General Purpose Input (GPI) Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides the parent dispatch service for the General Purpose Input + (GPI) MMI source generator. + + The EFI_MM_GPI_DISPATCH_PROTOCOL provides the ability to install child handlers for the + given event types. Several inputs can be enabled. This purpose of this interface is to generate an + MMI in response to any of these inputs having a true value provided. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_GPI_DISPATCH_H_ +#define _MM_GPI_DISPATCH_H_ + +#include + +#define EFI_MM_GPI_DISPATCH_PROTOCOL_GUID \ + { \ + 0x25566b03, 0xb577, 0x4cbf, {0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 } \ + } + +/// +/// The dispatch function's context. +/// +typedef struct { + /// + /// A number from one of 2^64 possible GPIs that can generate an MMI. A + /// 0 corresponds to logical GPI[0]; 1 corresponds to logical GPI[1]; and + /// GpiNum of N corresponds to GPI[N], where N can span from 0 to 2^64-1. + /// + UINT64 GpiNum; +} EFI_MM_GPI_REGISTER_CONTEXT; + +typedef struct _EFI_MM_GPI_DISPATCH_PROTOCOL EFI_MM_GPI_DISPATCH_PROTOCOL; + +/** + Registers a child MMI source dispatch function with a parent MM driver. + + This service registers a function (DispatchFunction) which will be called when an MMI is + generated because of one or more of the GPIs specified by RegisterContext. On return, + DispatchHandle contains a unique handle which may be used later to unregister the function + using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer pointing to another instance of + EFI_MM_GPI_REGISTER_CONTEXT describing the GPIs which actually caused the MMI and + CommBufferSize pointing to the size of the structure. + + @param[in] This Pointer to the EFI_MM_GPI_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when the specified GPI causes an MMI. + @param[in] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the GPI(s) for which the dispatch function + should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The GPI input value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_GPI_REGISTER)( + IN CONST EFI_MM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN CONST EFI_MM_GPI_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a General Purpose Input (GPI) service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the GPI triggers an MMI. + + @param[in] This Pointer to the EFI_MM_GPI_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS Handle of the service to remove. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_GPI_UNREGISTER)( + IN CONST EFI_MM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM GPI MMI Dispatch Protocol +/// +/// The MM GPI MMI Dispatch Protocol provides the parent dispatch service +/// for the General Purpose Input (GPI) MMI source generator. +/// +struct _EFI_MM_GPI_DISPATCH_PROTOCOL { + EFI_MM_GPI_REGISTER Register; + EFI_MM_GPI_UNREGISTER UnRegister; + /// + /// Denotes the maximum value of inputs that can have handlers attached. + /// + UINTN NumSupportedGpis; +}; + +extern EFI_GUID gEfiMmGpiDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmIoTrapDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmIoTrapDispatch.h new file mode 100644 index 0000000000..4434645035 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmIoTrapDispatch.h @@ -0,0 +1,130 @@ +/** @file + MM IO Trap Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides a parent dispatch service for IO trap MMI sources. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_IO_TRAP_DISPATCH_H_ +#define _MM_IO_TRAP_DISPATCH_H_ + +#include + +#define EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID \ + { \ + 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 } \ + } + +/// +/// IO Trap valid types +/// +typedef enum { + WriteTrap, + ReadTrap, + ReadWriteTrap, + IoTrapTypeMaximum +} EFI_MM_IO_TRAP_DISPATCH_TYPE; + +/// +/// IO Trap context structure containing information about the +/// IO trap event that should invoke the handler +/// +typedef struct { + UINT16 Address; + UINT16 Length; + EFI_MM_IO_TRAP_DISPATCH_TYPE Type; +} EFI_MM_IO_TRAP_REGISTER_CONTEXT; + +/// +/// IO Trap context structure containing information about the IO trap that occurred +/// +typedef struct { + UINT32 WriteData; +} EFI_MM_IO_TRAP_CONTEXT; + +typedef struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_MM_IO_TRAP_DISPATCH_PROTOCOL; + +/** + Register an IO trap MMI child handler for a specified MMI. + + This service registers a function (DispatchFunction) which will be called when an MMI is + generated because of an access to an I/O port specified by RegisterContext. On return, + DispatchHandle contains a unique handle which may be used later to unregister the function + using UnRegister(). If the base of the I/O range specified is zero, then an I/O range with the + specified length and characteristics will be allocated and the Address field in RegisterContext + updated. If no range could be allocated, then EFI_OUT_OF_RESOURCES will be returned. + + The service will not perform GCD allocation if the base address is non-zero or + EFI_MM_READY_TO_LOCK has been installed. In this case, the caller is responsible for the + existence and allocation of the specific IO range. + An error may be returned if some or all of the requested resources conflict with an existing IO trap + child handler. + + It is not required that implementations will allow multiple children for a single IO trap MMI source. + Some implementations may support multiple children. + The DispatchFunction will be called with Context updated to contain information + concerning the I/O action that actually happened and is passed in RegisterContext, with + CommBuffer pointing to the data actually written and CommBufferSize pointing to the size of + the data in CommBuffer. + + @param[in] This Pointer to the EFI_MM_IO_TRAP_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when I/O trap location is accessed. + @param[in] RegisterContext Pointer to the dispatch function's context. The caller fills this + context in before calling the register function to indicate to the register + function the IO trap MMI source for which the dispatch function should be invoked. + @param[out] DispatchHandle Handle of the dispatch function, for when interfacing with the parent MM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully registered. + @retval EFI_DEVICE_ERROR The driver was unable to complete due to hardware error. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available to fulfill the IO trap range request. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The input value is not within a valid range. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_REGISTER)( + IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN OUT EFI_MM_IO_TRAP_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child MMI source dispatch function with a parent MM driver. + + This service removes a previously installed child dispatch handler. This does not guarantee that the + system resources will be freed from the GCD. + + @param[in] This Pointer to the EFI_MM_IO_TRAP_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to remove. + + @retval EFI_SUCCESS The dispatch function has been successfully unregistered. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_UNREGISTER)( + IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM IO Trap Dispatch Protocol. +/// +/// This protocol provides a parent dispatch service for IO trap MMI sources. +/// +struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL { + EFI_MM_IO_TRAP_DISPATCH_REGISTER Register; + EFI_MM_IO_TRAP_DISPATCH_UNREGISTER UnRegister; +}; + +extern EFI_GUID gEfiMmIoTrapDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmMp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmMp.h new file mode 100644 index 0000000000..4f67ffcf30 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmMp.h @@ -0,0 +1,333 @@ +/** @file + EFI MM MP Protocol is defined in the PI 1.5 specification. + + The MM MP protocol provides a set of functions to allow execution of procedures on processors that + have entered MM. This protocol has the following properties: + 1. The caller can only invoke execution of a procedure on a processor, other than the caller, that + has also entered MM. + 2. It is possible to invoke a procedure on multiple processors. Supports blocking and non-blocking + modes of operation. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_MP_H_ +#define _MM_MP_H_ + +#include + +#define EFI_MM_MP_PROTOCOL_GUID \ + { \ + 0x5d5450d7, 0x990c, 0x4180, {0xa8, 0x3, 0x8e, 0x63, 0xf0, 0x60, 0x83, 0x7 } \ + } + +// +// Revision definition. +// +#define EFI_MM_MP_PROTOCOL_REVISION 0x00 + +// +// Attribute flags +// +#define EFI_MM_MP_TIMEOUT_SUPPORTED 0x01 + +// +// Completion token +// +typedef VOID* MM_COMPLETION; + +typedef struct { + MM_COMPLETION Completion; + EFI_STATUS Status; +} MM_DISPATCH_COMPLETION_TOKEN; + +typedef struct _EFI_MM_MP_PROTOCOL EFI_MM_MP_PROTOCOL; + +/** + Service to retrieves the number of logical processor in the platform. + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[out] NumberOfProcessors Pointer to the total number of logical processors in the system, + including the BSP and all APs. + + @retval EFI_SUCCESS The number of processors was retrieved successfully + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_GET_NUMBER_OF_PROCESSORS) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + OUT UINTN *NumberOfProcessors +); + + +/** + This service allows the caller to invoke a procedure one of the application processors (AP). This + function uses an optional token parameter to support blocking and non-blocking modes. If the token + is passed into the call, the function will operate in a non-blocking fashion and the caller can + check for completion with CheckOnProcedure or WaitForProcedure. + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[in] Procedure A pointer to the procedure to be run on the designated target + AP of the system. Type EFI_AP_PROCEDURE2 is defined below in + related definitions. + @param[in] CpuNumber The zero-based index of the processor number of the target + AP, on which the code stream is supposed to run. If the number + points to the calling processor then it will not run the + supplied code. + @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for this AP to + finish execution of Procedure, either for blocking or + non-blocking mode. Zero means infinity. If the timeout + expires before this AP returns from Procedure, then Procedure + on the AP is terminated. If the timeout expires in blocking + mode, the call returns EFI_TIMEOUT. If the timeout expires + in non-blocking mode, the timeout determined can be through + CheckOnProcedure or WaitForProcedure. + Note that timeout support is optional. Whether an + implementation supports this feature, can be determined via + the Attributes data member. + @param[in,out] ProcedureArguments Allows the caller to pass a list of parameters to the code + that is run by the AP. It is an optional common mailbox + between APs and the caller to share information. + @param[in,out] Token This is parameter is broken into two components: + 1.Token->Completion is an optional parameter that allows the + caller to execute the procedure in a blocking or non-blocking + fashion. If it is NULL the call is blocking, and the call will + not return until the AP has completed the procedure. If the + token is not NULL, the call will return immediately. The caller + can check whether the procedure has completed with + CheckOnProcedure or WaitForProcedure. + 2.Token->Status The implementation updates the address pointed + at by this variable with the status code returned by Procedure + when it completes execution on the target AP, or with EFI_TIMEOUT + if the Procedure fails to complete within the optional timeout. + The implementation will update this variable with EFI_NOT_READY + prior to starting Procedure on the target AP. + @param[in,out] CPUStatus This optional pointer may be used to get the status code returned + by Procedure when it completes execution on the target AP, or with + EFI_TIMEOUT if the Procedure fails to complete within the optional + timeout. The implementation will update this variable with + EFI_NOT_READY prior to starting Procedure on the target AP. + + @retval EFI_SUCCESS In the blocking case, this indicates that Procedure has completed + execution on the target AP. + In the non-blocking case this indicates that the procedure has + been successfully scheduled for execution on the target AP. + @retval EFI_INVALID_PARAMETER The input arguments are out of range. Either the target AP is the + caller of the function, or the Procedure or Token is NULL + @retval EFI_NOT_READY If the target AP is busy executing another procedure + @retval EFI_ALREADY_STARTED Token is already in use for another procedure + @retval EFI_TIMEOUT In blocking mode, the timeout expired before the specified AP + has finished +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_DISPATCH_PROCEDURE) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN CpuNumber, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus +); + +/** + This service allows the caller to invoke a procedure on all running application processors (AP) + except the caller. This function uses an optional token parameter to support blocking and + nonblocking modes. If the token is passed into the call, the function will operate in a non-blocking + fashion and the caller can check for completion with CheckOnProcedure or WaitForProcedure. + + It is not necessary for the implementation to run the procedure on every processor on the platform. + Processors that are powered down in such a way that they cannot respond to interrupts, may be + excluded from the broadcast. + + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[in] Procedure A pointer to the code stream to be run on the APs that have + entered MM. Type EFI_AP_PROCEDURE is defined below in related + definitions. + @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for the APs to finish + execution of Procedure, either for blocking or non-blocking mode. + Zero means infinity. If the timeout expires before all APs return + from Procedure, then Procedure on the failed APs is terminated. If + the timeout expires in blocking mode, the call returns EFI_TIMEOUT. + If the timeout expires in non-blocking mode, the timeout determined + can be through CheckOnProcedure or WaitForProcedure. + Note that timeout support is optional. Whether an implementation + supports this feature can be determined via the Attributes data + member. + @param[in,out] ProcedureArguments Allows the caller to pass a list of parameters to the code + that is run by the AP. It is an optional common mailbox + between APs and the caller to share information. + @param[in,out] Token This is parameter is broken into two components: + 1.Token->Completion is an optional parameter that allows the + caller to execute the procedure in a blocking or non-blocking + fashion. If it is NULL the call is blocking, and the call will + not return until the AP has completed the procedure. If the + token is not NULL, the call will return immediately. The caller + can check whether the procedure has completed with + CheckOnProcedure or WaitForProcedure. + 2.Token->Status The implementation updates the address pointed + at by this variable with the status code returned by Procedure + when it completes execution on the target AP, or with EFI_TIMEOUT + if the Procedure fails to complete within the optional timeout. + The implementation will update this variable with EFI_NOT_READY + prior to starting Procedure on the target AP + @param[in,out] CPUStatus This optional pointer may be used to get the individual status + returned by every AP that participated in the broadcast. This + parameter if used provides the base address of an array to hold + the EFI_STATUS value of each AP in the system. The size of the + array can be ascertained by the GetNumberOfProcessors function. + As mentioned above, the broadcast may not include every processor + in the system. Some implementations may exclude processors that + have been powered down in such a way that they are not responsive + to interrupts. Additionally the broadcast excludes the processor + which is making the BroadcastProcedure call. For every excluded + processor, the array entry must contain a value of EFI_NOT_STARTED + + @retval EFI_SUCCESS In the blocking case, this indicates that Procedure has completed + execution on the APs. In the non-blocking case this indicates that + the procedure has been successfully scheduled for execution on the + APs. + @retval EFI_INVALID_PARAMETER Procedure or Token is NULL. + @retval EFI_NOT_READY If a target AP is busy executing another procedure. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before all enabled APs have + finished. + @retval EFI_ALREADY_STARTED Before the AP procedure associated with the Token is finished, the + same Token cannot be used to dispatch or broadcast another procedure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_BROADCAST_PROCEDURE) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE2 Procedure, + IN UINTN TimeoutInMicroseconds, + IN OUT VOID *ProcedureArguments OPTIONAL, + IN OUT MM_COMPLETION *Token, + IN OUT EFI_STATUS *CPUStatus +); + + +/** + This service allows the caller to set a startup procedure that will be executed when an AP powers + up from a state where core configuration and context is lost. The procedure is execution has the + following properties: + 1. The procedure executes before the processor is handed over to the operating system. + 2. All processors execute the same startup procedure. + 3. The procedure may run in parallel with other procedures invoked through the functions in this + protocol, or with processors that are executing an MM handler or running in the operating system. + + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[in] Procedure A pointer to the code stream to be run on the designated target AP + of the system. Type EFI_AP_PROCEDURE is defined below in Volume 2 + with the related definitions of + EFI_MP_SERVICES_PROTOCOL.StartupAllAPs. + If caller may pass a value of NULL to deregister any existing + startup procedure. + @param[in,out] ProcedureArguments Allows the caller to pass a list of parameters to the code that is + run by the AP. It is an optional common mailbox between APs and + the caller to share information + + @retval EFI_SUCCESS The Procedure has been set successfully. + @retval EFI_INVALID_PARAMETER The Procedure is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_SET_STARTUP_PROCEDURE) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + IN EFI_AP_PROCEDURE Procedure, + IN OUT VOID *ProcedureArguments OPTIONAL +); + +/** + When non-blocking execution of a procedure on an AP is invoked with DispatchProcedure, + via the use of a token, this function can be used to check for completion of the procedure on the AP. + The function takes the token that was passed into the DispatchProcedure call. If the procedure + is complete, and therefore it is now possible to run another procedure on the same AP, this function + returns EFI_SUCESS. In this case the status returned by the procedure that executed on the AP is + returned in the token's Status field. If the procedure has not yet completed, then this function + returns EFI_NOT_READY. + + When a non-blocking execution of a procedure is invoked with BroadcastProcedure, via the + use of a token, this function can be used to check for completion of the procedure on all the + broadcast APs. The function takes the token that was passed into the BroadcastProcedure + call. If the procedure is complete on all broadcast APs this function returns EFI_SUCESS. In this + case the Status field in the token passed into the function reflects the overall result of the + invocation, which may be EFI_SUCCESS, if all executions succeeded, or the first observed failure. + If the procedure has not yet completed on the broadcast APs, the function returns + EFI_NOT_READY. + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[in] Token This parameter describes the token that was passed into + DispatchProcedure or BroadcastProcedure. + + @retval EFI_SUCCESS Procedure has completed. + @retval EFI_NOT_READY The Procedure has not completed. + @retval EFI_INVALID_PARAMETER Token or Token->Completion is NULL + @retval EFI_NOT_FOUND Token is not currently in use for a non-blocking call + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CHECK_FOR_PROCEDURE) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token +); + +/** + When a non-blocking execution of a procedure on an AP is invoked via DispatchProcedure, + this function will block the caller until the remote procedure has completed on the designated AP. + The non-blocking procedure invocation is identified by the Token parameter, which must match the + token that used when DispatchProcedure was called. Upon completion the status returned by + the procedure that executed on the AP is used to update the token's Status field. + + When a non-blocking execution of a procedure on an AP is invoked via BroadcastProcedure + this function will block the caller until the remote procedure has completed on all of the APs that + entered MM. The non-blocking procedure invocation is identified by the Token parameter, which + must match the token that used when BroadcastProcedure was called. Upon completion the + overall status returned by the procedures that executed on the broadcast AP is used to update the + token's Status field. The overall status may be EFI_SUCCESS, if all executions succeeded, or the + first observed failure. + + + @param[in] This The EFI_MM_MP_PROTOCOL instance. + @param[in] Token This parameter describes the token that was passed into + DispatchProcedure or BroadcastProcedure. + + @retval EFI_SUCCESS Procedure has completed. + @retval EFI_INVALID_PARAMETER Token or Token->Completion is NULL + @retval EFI_NOT_FOUND Token is not currently in use for a non-blocking call + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WAIT_FOR_PROCEDURE) ( + IN CONST EFI_MM_MP_PROTOCOL *This, + IN MM_COMPLETION Token +); + + + +/// +/// The MM MP protocol provides a set of functions to allow execution of procedures on processors that +/// have entered MM. +/// +struct _EFI_MM_MP_PROTOCOL { + UINT32 Revision; + UINT32 Attributes; + EFI_MM_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; + EFI_MM_DISPATCH_PROCEDURE DispatchProcedure; + EFI_MM_BROADCAST_PROCEDURE BroadcastProcedure; + EFI_MM_SET_STARTUP_PROCEDURE SetStartupProcedure; + EFI_CHECK_FOR_PROCEDURE CheckForProcedure; + EFI_WAIT_FOR_PROCEDURE WaitForProcedure; +}; + +extern EFI_GUID gEfiMmMpProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPciRootBridgeIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPciRootBridgeIo.h new file mode 100644 index 0000000000..cb5f569eec --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPciRootBridgeIo.h @@ -0,0 +1,31 @@ +/** @file + MM PCI Root Bridge IO protocol as defined in the PI 1.5 specification. + + This protocol provides PCI I/O and memory access within MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_PCI_ROOT_BRIDGE_IO_H_ +#define _MM_PCI_ROOT_BRIDGE_IO_H_ + +#include + +#define EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \ + { \ + 0x8bc1714d, 0xffcb, 0x41c3, { 0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea } \ + } + +/// +/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the +/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return +/// EFI_UNSUPPORTED. +/// +typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL; + +extern EFI_GUID gEfiMmPciRootBridgeIoProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h new file mode 100644 index 0000000000..74b6c00620 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h @@ -0,0 +1,164 @@ +/** @file + MM Periodic Timer Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides the parent dispatch service for the periodical timer MMI source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_PERIODIC_TIMER_DISPATCH_H_ +#define _MM_PERIODIC_TIMER_DISPATCH_H_ + +#include + +#define EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID \ + { \ + 0x4cec368e, 0x8e8e, 0x4d71, {0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53 } \ + } + +/// +/// Example: A chipset supports periodic MMIs on every 64ms or 2 seconds. +/// A child wishes schedule a period MMI to fire on a period of 3 seconds, there +/// are several ways to approach the problem: +/// 1. The child may accept a 4 second periodic rate, in which case it registers with +/// Period = 40000 +/// MmiTickInterval = 20000 +/// The resulting MMI will occur every 2 seconds with the child called back on +/// every 2nd MMI. +/// NOTE: the same result would occur if the child set MmiTickInterval = 0. +/// 2. The child may choose the finer granularity MMI (64ms): +/// Period = 30000 +/// MmiTickInterval = 640 +/// The resulting MMI will occur every 64ms with the child called back on +/// every 47th MMI. +/// NOTE: the child driver should be aware that this will result in more +/// MMIs occuring during system runtime which can negatively impact system +/// performance. +/// +typedef struct { + /// + /// The minimum period of time in 100 nanosecond units that the child gets called. The + /// child will be called back after a time greater than the time Period. + /// + UINT64 Period; + /// + /// The period of time interval between MMIs. Children of this interface should use this + /// field when registering for periodic timer intervals when a finer granularity periodic + /// MMI is desired. + /// + UINT64 MmiTickInterval; +} EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT; + +/// +/// The DispatchFunction will be called with Context set to the same value as was passed into +/// Register() in RegisterContext and with CommBuffer pointing to an instance of +/// EFI_MM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size. +/// +typedef struct { + /// + /// ElapsedTime is the actual time in 100 nanosecond units elapsed since last called, a + /// value of 0 indicates an unknown amount of time. + /// + UINT64 ElapsedTime; +} EFI_MM_PERIODIC_TIMER_CONTEXT; + +typedef struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL; + +/** + Register a child MMI source dispatch function for MM periodic timer. + + This service registers a function (DispatchFunction) which will be called when at least the + amount of time specified by RegisterContext has elapsed. On return, DispatchHandle + contains a unique handle which may be used later to unregister the function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer pointing to an instance of + EFI_MM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size. + + @param[in] This Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when at least the specified amount + of time has elapsed. + @param[in] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the period at which the dispatch function + should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The period input value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_PERIODIC_TIMER_REGISTER)( + IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN CONST EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a periodic timer service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the time has elapsed. + + @param[in] This Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The service has been successfully removed. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_PERIODIC_TIMER_UNREGISTER)( + IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Returns the next MMI tick period supported by the chipset. + + The order returned is from longest to shortest interval period. + + @param[in] This Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance. + @param[in,out] MmiTickInterval Pointer to pointer of next shorter MMI interval + period supported by the child. This parameter works as a get-first, + get-next field.The first time this function is called, *MmiTickInterval + should be set to NULL to get the longest MMI interval.The returned + *MmiTickInterval should be passed in on subsequent calls to get the + next shorter interval period until *MmiTickInterval = NULL. + + @retval EFI_SUCCESS The service returned successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_PERIODIC_TIMER_INTERVAL)( + IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN OUT UINT64 **MmiTickInterval + ); + +/// +/// Interface structure for the MM Periodic Timer Dispatch Protocol +/// +/// This protocol provides the parent dispatch service for the periodical timer MMI source generator. +/// +struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL { + EFI_MM_PERIODIC_TIMER_REGISTER Register; + EFI_MM_PERIODIC_TIMER_UNREGISTER UnRegister; + EFI_MM_PERIODIC_TIMER_INTERVAL GetNextShorterInterval; +}; + +extern EFI_GUID gEfiMmPeriodicTimerDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPowerButtonDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPowerButtonDispatch.h new file mode 100644 index 0000000000..f46501dc1c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmPowerButtonDispatch.h @@ -0,0 +1,111 @@ +/** @file + MM Power Button Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides the parent dispatch service for the power button MMI source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_POWER_BUTTON_DISPATCH_H_ +#define _MM_POWER_BUTTON_DISPATCH_H_ + +#include + +#define EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID \ + { \ + 0x1b1183fa, 0x1823, 0x46a7, {0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d } \ + } + +/// +/// Power Button phases. +/// +typedef enum { + EfiPowerButtonEntry, + EfiPowerButtonExit, + EfiPowerButtonMax +} EFI_POWER_BUTTON_PHASE; + +/// +/// The dispatch function's context. +/// +typedef struct { + /// + /// Designates whether this handler should be invoked upon entry or exit. + /// + EFI_POWER_BUTTON_PHASE Phase; +} EFI_MM_POWER_BUTTON_REGISTER_CONTEXT; + +typedef struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL; + +/** + Provides the parent dispatch service for a power button event. + + This service registers a function (DispatchFunction) which will be called when an MMI is + generated because the power button was pressed or released, as specified by RegisterContext. + On return, DispatchHandle contains a unique handle which may be used later to unregister the + function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL. + + @param[in] This Pointer to the EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when power button is pressed or released. + @param[in] RegisterContext Pointer to the dispatch function's context. The caller fills in this context + before calling the Register() function to indicate to the Register() function + the power button MMI phase for which the dispatch function should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The power button input value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_POWER_BUTTON_REGISTER)( + IN CONST EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN EFI_MM_POWER_BUTTON_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a power-button service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the standby button is pressed or released. + + @param[in] This Pointer to the EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The service has been successfully removed. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_POWER_BUTTON_UNREGISTER)( + IN CONST EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM Power Button Dispatch Protocol. +/// +/// This protocol provides the parent dispatch service for the power button MMI source generator. +/// +struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL { + EFI_MM_POWER_BUTTON_REGISTER Register; + EFI_MM_POWER_BUTTON_UNREGISTER UnRegister; +}; + +extern EFI_GUID gEfiMmPowerButtonDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReadyToLock.h new file mode 100644 index 0000000000..092fcfdcc0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReadyToLock.h @@ -0,0 +1,26 @@ +/** @file + MM Ready To Lock protocol introduced in the PI 1.5 specification. + + This protocol is a mandatory protocol published by the MM Foundation + code when the system is preparing to lock certain resources and interfaces + in anticipation of the invocation of 3rd party extensible modules. + This protocol is an MM counterpart of the DXE MM Ready to Lock Protocol. + This protocol prorogates resource locking notification into MM environment. + This protocol is installed after installation of the MM End of DXE Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_READY_TO_LOCK_H_ +#define _MM_READY_TO_LOCK_H_ + +#define EFI_MM_READY_TO_LOCK_PROTOCOL_GUID \ + { \ + 0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 } \ + } + +extern EFI_GUID gEfiMmReadyToLockProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h new file mode 100644 index 0000000000..f8e67ac4e3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h @@ -0,0 +1,78 @@ +/** @file + This protocol provides registering and unregistering services to status code consumers while in DXE MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.1. + +**/ + +#ifndef __MM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ +#define __MM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ + +#define EFI_MM_RSC_HANDLER_PROTOCOL_GUID \ + { \ + 0x2ff29fa7, 0x5e80, 0x4ed9, {0xb3, 0x80, 0x1, 0x7d, 0x3c, 0x55, 0x4f, 0xf4} \ + } + +typedef +EFI_STATUS +(EFIAPI *EFI_MM_RSC_HANDLER_CALLBACK)( + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN EFI_GUID *CallerId, + IN EFI_STATUS_CODE_DATA *Data +); + +/** + Register the callback function for ReportStatusCode() notification. + + When this function is called the function pointer is added to an internal list and any future calls to + ReportStatusCode() will be forwarded to the Callback function. + + @param[in] Callback A pointer to a function of type EFI_MM_RSC_HANDLER_CALLBACK that is + called when a call to ReportStatusCode() occurs. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No more functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It can't be registered again. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_RSC_HANDLER_REGISTER)( + IN EFI_MM_RSC_HANDLER_CALLBACK Callback +); + +/** + Remove a previously registered callback function from the notification list. + + A callback function must be unregistered before it is deallocated. It is important that any registered + callbacks that are not runtime complaint be unregistered when ExitBootServices() is called. + + @param[in] Callback A pointer to a function of type EFI_MM_RSC_HANDLER_CALLBACK that is to be + unregistered. + + @retval EFI_SUCCESS The function was successfully unregistered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_NOT_FOUND The callback function was not found to be unregistered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_RSC_HANDLER_UNREGISTER)( + IN EFI_MM_RSC_HANDLER_CALLBACK Callback +); + +typedef struct _EFI_MM_RSC_HANDLER_PROTOCOL { + EFI_MM_RSC_HANDLER_REGISTER Register; + EFI_MM_RSC_HANDLER_UNREGISTER Unregister; +} EFI_MM_RSC_HANDLER_PROTOCOL; + +extern EFI_GUID gEfiMmRscHandlerProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h new file mode 100644 index 0000000000..430237862a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h @@ -0,0 +1,113 @@ +/** @file + MM Standby Button Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides the parent dispatch service for the standby button MMI source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_STANDBY_BUTTON_DISPATCH_H_ +#define _MM_STANDBY_BUTTON_DISPATCH_H_ + +#include + +#define EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID \ + { \ + 0x7300c4a1, 0x43f2, 0x4017, {0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b } \ + } + +/// +/// Standby Button phases +/// +typedef enum { + EfiStandbyButtonEntry, + EfiStandbyButtonExit, + EfiStandbyButtonMax +} EFI_STANDBY_BUTTON_PHASE; + +/// +/// The dispatch function's context. +/// +typedef struct { + /// + /// Describes whether the child handler should be invoked upon the entry to the button + /// activation or upon exit. + /// + EFI_STANDBY_BUTTON_PHASE Phase; +} EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT; + +typedef struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL; + +/** + Provides the parent dispatch service for a standby button event. + + This service registers a function (DispatchFunction) which will be called when an MMI is + generated because the standby button was pressed or released, as specified by + RegisterContext. On return, DispatchHandle contains a unique handle which may be used + later to unregister the function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL. + + @param[in] This Pointer to the EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when the standby button is pressed or released. + @param[in] RegisterContext Pointer to the dispatch function's context. The caller fills in this context + before calling the register function to indicate to the register function the + standby button MMI source for which the dispatch function should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The standby button input value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_STANDBY_BUTTON_REGISTER)( + IN CONST EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a child MMI source dispatch function with a parent MM driver. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the standby button is pressed or released. + + @param[in] This Pointer to the EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The service has been successfully removed. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_STANDBY_BUTTON_UNREGISTER)( + IN CONST EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM Standby Button Dispatch Protocol. +/// +/// This protocol provides the parent dispatch service for the standby +/// button MMI source generator. +/// +struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL { + EFI_MM_STANDBY_BUTTON_REGISTER Register; + EFI_MM_STANDBY_BUTTON_UNREGISTER UnRegister; +}; + +extern EFI_GUID gEfiMmStandbyButtonDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStatusCode.h new file mode 100644 index 0000000000..3ff1a31aa4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmStatusCode.h @@ -0,0 +1,59 @@ +/** @file + EFI MM Status Code Protocol as defined in the PI 1.5 specification. + + This protocol provides the basic status code services while in MM. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_STATUS_CODE_H__ +#define _MM_STATUS_CODE_H__ + + +#define EFI_MM_STATUS_CODE_PROTOCOL_GUID \ + { \ + 0x6afd2b77, 0x98c1, 0x4acd, {0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1} \ + } + +typedef struct _EFI_MM_STATUS_CODE_PROTOCOL EFI_MM_STATUS_CODE_PROTOCOL; + +/** + Service to emit the status code in MM. + + The EFI_MM_STATUS_CODE_PROTOCOL.ReportStatusCode() function enables a driver + to emit a status code while in MM. The reason that there is a separate protocol definition from the + DXE variant of this service is that the publisher of this protocol will provide a service that is + capability of coexisting with a foreground operational environment, such as an operating system + after the termination of boot services. + + @param[in] This Points to this instance of the EFI_MM_STATUS_CODE_PROTOCOL. + @param[in] CodeType DIndicates the type of status code being reported. + @param[in] Value Describes the current status of a hardware or software entity. + @param[in] Instance The enumeration of a hardware or software entity within the system. + @param[in] CallerId This optional parameter may be used to identify the caller. + @param[in] Data This optional parameter may be used to pass additional data. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The function should not be completed due to a device error. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_REPORT_STATUS_CODE)( + IN CONST EFI_MM_STATUS_CODE_PROTOCOL *This, + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN CONST EFI_GUID *CallerId, + IN EFI_STATUS_CODE_DATA *Data OPTIONAL + ); + +struct _EFI_MM_STATUS_CODE_PROTOCOL { + EFI_MM_REPORT_STATUS_CODE ReportStatusCode; +}; + +extern EFI_GUID gEfiMmStatusCodeProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSwDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSwDispatch.h new file mode 100644 index 0000000000..49957de656 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSwDispatch.h @@ -0,0 +1,130 @@ +/** @file + MM Software Dispatch Protocol introduced from PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + This protocol provides the parent dispatch service for a given MMI source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_SW_DISPATCH_H_ +#define _MM_SW_DISPATCH_H_ + +#include + +#define EFI_MM_SW_DISPATCH_PROTOCOL_GUID \ + { \ + 0x18a3c6dc, 0x5eea, 0x48c8, {0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99 } \ + } + +/// +/// A particular chipset may not support all possible software MMI input values. +/// For example, the ICH supports only values 00h to 0FFh. The parent only allows a single +/// child registration for each SwMmiInputValue. +/// +typedef struct { + UINTN SwMmiInputValue; +} EFI_MM_SW_REGISTER_CONTEXT; + +/// +/// The DispatchFunction will be called with Context set to the same value as was passed into +/// this function in RegisterContext and with CommBuffer (and CommBufferSize) pointing +/// to an instance of EFI_MM_SW_CONTEXT indicating the index of the CPU which generated the +/// software MMI. +/// +typedef struct { + /// + /// The 0-based index of the CPU which generated the software MMI. + /// + UINTN SwMmiCpuIndex; + /// + /// This value corresponds directly to the CommandPort parameter used in the call to Trigger(). + /// + UINT8 CommandPort; + /// + /// This value corresponds directly to the DataPort parameter used in the call to Trigger(). + /// + UINT8 DataPort; +} EFI_MM_SW_CONTEXT; + +typedef struct _EFI_MM_SW_DISPATCH_PROTOCOL EFI_MM_SW_DISPATCH_PROTOCOL; + +/** + Register a child MMI source dispatch function for the specified software MMI. + + This service registers a function (DispatchFunction) which will be called when the software + MMI source specified by RegisterContext->SwMmiCpuIndex is detected. On return, + DispatchHandle contains a unique handle which may be used later to unregister the function + using UnRegister(). + + @param[in] This Pointer to the EFI_MM_SW_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when the specified software + MMI is generated. + @param[in, out] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function which Software MMI input value the + dispatch function should be invoked for. + @param[out] DispatchHandle Handle generated by the dispatcher to track the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW MMI input value + is not within a valid range or is already in use. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this + child. + @retval EFI_OUT_OF_RESOURCES A unique software MMI value could not be assigned + for this dispatch. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_SW_REGISTER)( + IN CONST EFI_MM_SW_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN OUT EFI_MM_SW_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child MMI source dispatch function for the specified software MMI. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called in response to a software MMI. + + @param[in] This Pointer to the EFI_MM_SW_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully unregistered. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_SW_UNREGISTER)( + IN CONST EFI_MM_SW_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle +); + +/// +/// Interface structure for the MM Software MMI Dispatch Protocol. +/// +/// The EFI_MM_SW_DISPATCH_PROTOCOL provides the ability to install child handlers for the +/// given software. These handlers will respond to software interrupts, and the maximum software +/// interrupt in the EFI_MM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue. +/// +struct _EFI_MM_SW_DISPATCH_PROTOCOL { + EFI_MM_SW_REGISTER Register; + EFI_MM_SW_UNREGISTER UnRegister; + /// + /// A read-only field that describes the maximum value that can be used in the + /// EFI_MM_SW_DISPATCH_PROTOCOL.Register() service. + /// + UINTN MaximumSwiValue; +}; + +extern EFI_GUID gEfiMmSwDispatchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSxDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSxDispatch.h new file mode 100644 index 0000000000..db008e96fa --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmSxDispatch.h @@ -0,0 +1,129 @@ +/** @file + MM Sx Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + Provides the parent dispatch service for a given Sx-state source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_SX_DISPATCH_H_ +#define _MM_SX_DISPATCH_H_ + +#include + +#define EFI_MM_SX_DISPATCH_PROTOCOL_GUID \ + { \ + 0x456d2859, 0xa84b, 0x4e47, {0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d } \ + } + +/// +/// Sleep states S0-S5 +/// +typedef enum { + SxS0, + SxS1, + SxS2, + SxS3, + SxS4, + SxS5, + EfiMaximumSleepType +} EFI_SLEEP_TYPE; + +/// +/// Sleep state phase: entry or exit +/// +typedef enum { + SxEntry, + SxExit, + EfiMaximumPhase +} EFI_SLEEP_PHASE; + +/// +/// The dispatch function's context +/// +typedef struct { + EFI_SLEEP_TYPE Type; + EFI_SLEEP_PHASE Phase; +} EFI_MM_SX_REGISTER_CONTEXT; + +typedef struct _EFI_MM_SX_DISPATCH_PROTOCOL EFI_MM_SX_DISPATCH_PROTOCOL; + +/** + Provides the parent dispatch service for a given Sx source generator. + + This service registers a function (DispatchFunction) which will be called when the sleep state + event specified by RegisterContext is detected. On return, DispatchHandle contains a + unique handle which may be used later to unregister the function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer and CommBufferSize set to + NULL and 0 respectively. + + @param[in] This Pointer to the EFI_MM_SX_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when the specified sleep state event occurs. + @param[in] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function which Sx state type and phase the caller + wishes to be called back on. For this intertace, + the Sx driver will call the registered handlers for + all Sx type and phases, so the Sx state handler(s) + must check the Type and Phase field of the Dispatch + context and act accordingly. + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent Sx state MM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_UNSUPPORTED The Sx driver or hardware does not support that + Sx Type/Phase. + @retval EFI_DEVICE_ERROR The Sx driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. Type & Phase are not + within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this + child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_SX_REGISTER)( + IN CONST EFI_MM_SX_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN CONST EFI_MM_SX_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters an Sx-state service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called in response to sleep event. + + @param[in] This Pointer to the EFI_MM_SX_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The service has been successfully removed. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_SX_UNREGISTER)( + IN CONST EFI_MM_SX_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM Sx Dispatch Protocol +/// +/// The EFI_MM_SX_DISPATCH_PROTOCOL provides the ability to install child handlers to +/// respond to sleep state related events. +/// +struct _EFI_MM_SX_DISPATCH_PROTOCOL { + EFI_MM_SX_REGISTER Register; + EFI_MM_SX_UNREGISTER UnRegister; +}; + +extern EFI_GUID gEfiMmSxDispatchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmUsbDispatch.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmUsbDispatch.h new file mode 100644 index 0000000000..75abb270b1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MmUsbDispatch.h @@ -0,0 +1,124 @@ +/** @file + MM USB Dispatch Protocol as defined in PI 1.5 Specification + Volume 4 Management Mode Core Interface. + + Provides the parent dispatch service for the USB MMI source generator. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.5. + +**/ + +#ifndef _MM_USB_DISPATCH_H_ +#define _MM_USB_DISPATCH_H_ + +#include + +#define EFI_MM_USB_DISPATCH_PROTOCOL_GUID \ + { \ + 0xee9b8d90, 0xc5a6, 0x40a2, {0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 } \ + } + +/// +/// USB MMI event types +/// +typedef enum { + UsbLegacy, + UsbWake +} EFI_USB_MMI_TYPE; + +/// +/// The dispatch function's context. +/// +typedef struct { + /// + /// Describes whether this child handler will be invoked in response to a USB legacy + /// emulation event, such as port-trap on the PS/2* keyboard control registers, or to a + /// USB wake event, such as resumption from a sleep state. + /// + EFI_USB_MMI_TYPE Type; + /// + /// The device path is part of the context structure and describes the location of the + /// particular USB host controller in the system for which this register event will occur. + /// This location is important because of the possible integration of several USB host + /// controllers in a system. + /// + EFI_DEVICE_PATH_PROTOCOL *Device; +} EFI_MM_USB_REGISTER_CONTEXT; + +typedef struct _EFI_MM_USB_DISPATCH_PROTOCOL EFI_MM_USB_DISPATCH_PROTOCOL; + +/** + Provides the parent dispatch service for the USB MMI source generator. + + This service registers a function (DispatchFunction) which will be called when the USB- + related MMI specified by RegisterContext has occurred. On return, DispatchHandle + contains a unique handle which may be used later to unregister the function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer containing NULL and + CommBufferSize containing zero. + + @param[in] This Pointer to the EFI_MM_USB_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when a USB-related MMI occurs. + @param[in] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the USB MMI types for which the dispatch + function should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the MMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the MMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The USB MMI type + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or MM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_USB_REGISTER)( + IN CONST EFI_MM_USB_DISPATCH_PROTOCOL *This, + IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction, + IN CONST EFI_MM_USB_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a USB service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the USB event occurs. + + @param[in] This Pointer to the EFI_MM_USB_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the MMI source has been disabled + if there are no other registered child dispatch + functions for this MMI source. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MM_USB_UNREGISTER)( + IN CONST EFI_MM_USB_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the MM USB MMI Dispatch Protocol +/// +/// This protocol provides the parent dispatch service for the USB MMI source generator. +/// +struct _EFI_MM_USB_DISPATCH_PROTOCOL { + EFI_MM_USB_REGISTER Register; + EFI_MM_USB_UNREGISTER UnRegister; +}; + +extern EFI_GUID gEfiMmUsbDispatchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MonotonicCounter.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MonotonicCounter.h new file mode 100644 index 0000000000..5d56ca788f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MonotonicCounter.h @@ -0,0 +1,22 @@ +/** @file + Monotonic Counter Architectural Protocol as defined in PI SPEC VOLUME 2 DXE + + This code provides the services required to access the system's monotonic counter + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_MONTONIC_COUNTER_H__ +#define __ARCH_PROTOCOL_MONTONIC_COUNTER_H__ + +/// +/// Global ID for the Monotonic Counter Architectural Protocol. +/// +#define EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID \ + {0x1da97072, 0xbddc, 0x4b30, {0x99, 0xf1, 0x72, 0xa0, 0xb5, 0x6f, 0xff, 0x2a} } + +extern EFI_GUID gEfiMonotonicCounterArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MpService.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MpService.h new file mode 100644 index 0000000000..697d99ebe5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/MpService.h @@ -0,0 +1,676 @@ +/** @file + When installed, the MP Services Protocol produces a collection of services + that are needed for MP management. + + The MP Services Protocol provides a generalized way of performing following tasks: + - Retrieving information of multi-processor environment and MP-related status of + specific processors. + - Dispatching user-provided function to APs. + - Maintain MP-related processor status. + + The MP Services Protocol must be produced on any system with more than one logical + processor. + + The Protocol is available only during boot time. + + MP Services Protocol is hardware-independent. Most of the logic of this protocol + is architecturally neutral. It abstracts the multi-processor environment and + status of processors, and provides interfaces to retrieve information, maintain, + and dispatch. + + MP Services Protocol may be consumed by ACPI module. The ACPI module may use this + protocol to retrieve data that are needed for an MP platform and report them to OS. + MP Services Protocol may also be used to program and configure processors, such + as MTRR synchronization for memory space attributes setting in DXE Services. + MP Services Protocol may be used by non-CPU DXE drivers to speed up platform boot + by taking advantage of the processing capabilities of the APs, for example, using + APs to help test system memory in parallel with other device initialization. + Diagnostics applications may also use this protocol for multi-processor. + +Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in the UEFI Platform Initialization Specification 1.2, + Volume 2:Driver Execution Environment Core Interface. + +**/ + +#ifndef _MP_SERVICE_PROTOCOL_H_ +#define _MP_SERVICE_PROTOCOL_H_ + +/// +/// Global ID for the EFI_MP_SERVICES_PROTOCOL. +/// +#define EFI_MP_SERVICES_PROTOCOL_GUID \ + { \ + 0x3fdda605, 0xa76e, 0x4f46, {0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08} \ + } + +/// +/// Value used in the NumberProcessors parameter of the GetProcessorInfo function +/// +#define CPU_V2_EXTENDED_TOPOLOGY BIT24 + +/// +/// Forward declaration for the EFI_MP_SERVICES_PROTOCOL. +/// +typedef struct _EFI_MP_SERVICES_PROTOCOL EFI_MP_SERVICES_PROTOCOL; + +/// +/// Terminator for a list of failed CPUs returned by StartAllAPs(). +/// +#define END_OF_CPU_LIST 0xffffffff + +/// +/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and +/// indicates whether the processor is playing the role of BSP. If the bit is 1, +/// then the processor is BSP. Otherwise, it is AP. +/// +#define PROCESSOR_AS_BSP_BIT 0x00000001 + +/// +/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and +/// indicates whether the processor is enabled. If the bit is 1, then the +/// processor is enabled. Otherwise, it is disabled. +/// +#define PROCESSOR_ENABLED_BIT 0x00000002 + +/// +/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and +/// indicates whether the processor is healthy. If the bit is 1, then the +/// processor is healthy. Otherwise, some fault has been detected for the processor. +/// +#define PROCESSOR_HEALTH_STATUS_BIT 0x00000004 + +/// +/// Structure that describes the pyhiscal location of a logical CPU. +/// +typedef struct { + /// + /// Zero-based physical package number that identifies the cartridge of the processor. + /// + UINT32 Package; + /// + /// Zero-based physical core number within package of the processor. + /// + UINT32 Core; + /// + /// Zero-based logical thread number within core of the processor. + /// + UINT32 Thread; +} EFI_CPU_PHYSICAL_LOCATION; + +/// +/// Structure that defines the 6-level physical location of the processor +/// +typedef struct { +/// +/// Package Zero-based physical package number that identifies the cartridge of the processor. +/// +UINT32 Package; +/// +/// Module Zero-based physical module number within package of the processor. +/// +UINT32 Module; +/// +/// Tile Zero-based physical tile number within module of the processor. +/// +UINT32 Tile; +/// +/// Die Zero-based physical die number within tile of the processor. +/// +UINT32 Die; +/// +/// Core Zero-based physical core number within die of the processor. +/// +UINT32 Core; +/// +/// Thread Zero-based logical thread number within core of the processor. +/// +UINT32 Thread; +} EFI_CPU_PHYSICAL_LOCATION2; + + +typedef union { + /// The 6-level physical location of the processor, including the + /// physical package number that identifies the cartridge, the physical + /// module number within package, the physical tile number within the module, + /// the physical die number within the tile, the physical core number within + /// package, and logical thread number within core. + EFI_CPU_PHYSICAL_LOCATION2 Location2; +} EXTENDED_PROCESSOR_INFORMATION; + + +/// +/// Structure that describes information about a logical CPU. +/// +typedef struct { + /// + /// The unique processor ID determined by system hardware. For IA32 and X64, + /// the processor ID is the same as the Local APIC ID. Only the lower 8 bits + /// are used, and higher bits are reserved. For IPF, the lower 16 bits contains + /// id/eid, and higher bits are reserved. + /// + UINT64 ProcessorId; + /// + /// Flags indicating if the processor is BSP or AP, if the processor is enabled + /// or disabled, and if the processor is healthy. Bits 3..31 are reserved and + /// must be 0. + /// + /// 
+  /// BSP  ENABLED  HEALTH  Description
+  /// ===  =======  ======  ===================================================
+  ///  0      0       0     Unhealthy Disabled AP.
+  ///  0      0       1     Healthy Disabled AP.
+  ///  0      1       0     Unhealthy Enabled AP.
+  ///  0      1       1     Healthy Enabled AP.
+  ///  1      0       0     Invalid. The BSP can never be in the disabled state.
+  ///  1      0       1     Invalid. The BSP can never be in the disabled state.
+  ///  1      1       0     Unhealthy Enabled BSP.
+  ///  1      1       1     Healthy Enabled BSP.
+  ///
+ /// + UINT32 StatusFlag; + /// + /// The physical location of the processor, including the physical package number + /// that identifies the cartridge, the physical core number within package, and + /// logical thread number within core. + /// + EFI_CPU_PHYSICAL_LOCATION Location; + /// + /// The extended information of the processor. This field is filled only when + /// CPU_V2_EXTENDED_TOPOLOGY is set in parameter ProcessorNumber. + EXTENDED_PROCESSOR_INFORMATION ExtendedInformation; +} EFI_PROCESSOR_INFORMATION; + +/** + This service retrieves the number of logical processor in the platform + and the number of those logical processors that are enabled on this boot. + This service may only be called from the BSP. + + This function is used to retrieve the following information: + - The number of logical processors that are present in the system. + - The number of enabled logical processors in the system at the instant + this call is made. + + Because MP Service Protocol provides services to enable and disable processors + dynamically, the number of enabled logical processors may vary during the + course of a boot session. + + If this service is called from an AP, then EFI_DEVICE_ERROR is returned. + If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then + EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors + is returned in NumberOfProcessors, the number of currently enabled processor + is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL + instance. + @param[out] NumberOfProcessors Pointer to the total number of logical + processors in the system, including the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled logical + processors that exist in system, including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and enabled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL. + @retval EFI_INVALID_PARAMETER NumberOfEnabledProcessors is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)( + IN EFI_MP_SERVICES_PROTOCOL *This, + OUT UINTN *NumberOfProcessors, + OUT UINTN *NumberOfEnabledProcessors + ); + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + This service retrieves detailed MP-related information about any processor + on the platform. Note the following: + - The processor information may change during the course of a boot session. + - The information presented here is entirely MP related. + + Information regarding the number of caches and their sizes, frequency of operation, + slot numbers is all considered platform-related information and is not provided + by this service. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL + instance. + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where information for + the requested processor is deposited. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist in the platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_GET_PROCESSOR_INFO)( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer + ); + +/** + This service executes a caller provided function on all enabled APs. APs can + run either simultaneously or one at a time in sequence. This service supports + both blocking and non-blocking requests. The non-blocking requests use EFI + events so the BSP can detect when the APs have finished. This service may only + be called from the BSP. + + This function is used to dispatch all the enabled APs to the function specified + by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned + immediately and Procedure is not started on any AP. + + If SingleThread is TRUE, all the enabled APs execute the function specified by + Procedure one by one, in ascending order of processor handle number. Otherwise, + all the enabled APs execute the function specified by Procedure simultaneously. + + If WaitEvent is NULL, execution is in blocking mode. The BSP waits until all + APs finish or TimeoutInMicroSecs expires. Otherwise, execution is in non-blocking + mode, and the BSP returns from this service without waiting for APs. If a + non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT + is signaled, then EFI_UNSUPPORTED must be returned. + + If the timeout specified by TimeoutInMicroseconds expires before all APs return + from Procedure, then Procedure on the failed APs is terminated. All enabled APs + are always available for further calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() + and EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NULL, its + content points to the list of processor handle numbers in which Procedure was + terminated. + + Note: It is the responsibility of the consumer of the EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() + to make sure that the nature of the code that is executed on the BSP and the + dispatched APs is well controlled. The MP Services Protocol does not guarantee + that the Procedure function is MP-safe. Hence, the tasks that can be run in + parallel are limited to certain independent tasks and well-controlled exclusive + code. EFI services and protocols may not be called by APs unless otherwise + specified. + + In blocking execution mode, BSP waits until all APs finish or + TimeoutInMicroSeconds expires. + + In non-blocking execution mode, BSP is freed to return to the caller and then + proceed to the next task without having to wait for APs. The following + sequence needs to occur in a non-blocking execution mode: + + -# The caller that intends to use this MP Services Protocol in non-blocking + mode creates WaitEvent by calling the EFI CreateEvent() service. The caller + invokes EFI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter WaitEvent + is not NULL, then StartupAllAPs() executes in non-blocking mode. It requests + the function specified by Procedure to be started on all the enabled APs, + and releases the BSP to continue with other tasks. + -# The caller can use the CheckEvent() and WaitForEvent() services to check + the state of the WaitEvent created in step 1. + -# When the APs complete their task or TimeoutInMicroSecondss expires, the MP + Service signals WaitEvent by calling the EFI SignalEvent() function. If + FailedCpuList is not NULL, its content is available when WaitEvent is + signaled. If all APs returned from Procedure prior to the timeout, then + FailedCpuList is set to NULL. If not all APs return from Procedure before + the timeout, then FailedCpuList is filled in with the list of the failed + APs. The buffer is allocated by MP Service Protocol using AllocatePool(). + It is the caller's responsibility to free the buffer with FreePool() service. + -# This invocation of SignalEvent() function informs the caller that invoked + EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs completed + the specified task or a timeout occurred. The contents of FailedCpuList + can be examined to determine which APs did not complete the specified task + prior to the timeout. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL + instance. + @param[in] Procedure A pointer to the function to be run on + enabled APs of the system. See type + EFI_AP_PROCEDURE. + @param[in] SingleThread If TRUE, then all the enabled APs execute + the function specified by Procedure one by + one, in ascending order of processor handle + number. If FALSE, then all the enabled APs + execute the function specified by Procedure + simultaneously. + @param[in] WaitEvent The event created by the caller with CreateEvent() + service. If it is NULL, then execute in + blocking mode. BSP waits until all APs finish + or TimeoutInMicroSeconds expires. If it's + not NULL, then execute in non-blocking mode. + BSP requests the function specified by + Procedure to be started on all the enabled + APs, and go on executing immediately. If + all return from Procedure, or TimeoutInMicroSeconds + expires, this event is signaled. The BSP + can use the CheckEvent() or WaitForEvent() + services to check the state of event. Type + EFI_EVENT is defined in CreateEvent() in + the Unified Extensible Firmware Interface + Specification. + @param[in] TimeoutInMicrosecsond Indicates the time limit in microseconds for + APs to return from Procedure, either for + blocking or non-blocking mode. Zero means + infinity. If the timeout expires before + all APs return from Procedure, then Procedure + on the failed APs is terminated. All enabled + APs are available for next function assigned + by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() + or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). + If the timeout expires in blocking mode, + BSP returns EFI_TIMEOUT. If the timeout + expires in non-blocking mode, WaitEvent + is signaled with SignalEvent(). + @param[in] ProcedureArgument The parameter passed into Procedure for + all APs. + @param[out] FailedCpuList If NULL, this parameter is ignored. Otherwise, + if all APs finish successfully, then its + content is set to NULL. If not all APs + finish before timeout expires, then its + content is set to address of the buffer + holding handle numbers of the failed APs. + The buffer is allocated by MP Service Protocol, + and it's the caller's responsibility to + free the buffer with FreePool() service. + In blocking mode, it is ready for consumption + when the call returns. In non-blocking mode, + it is ready when WaitEvent is signaled. The + list of failed CPU is terminated by + END_OF_CPU_LIST. + + @retval EFI_SUCCESS In blocking mode, all APs have finished before + the timeout expired. + @retval EFI_SUCCESS In non-blocking mode, function has been dispatched + to all enabled APs. + @retval EFI_UNSUPPORTED A non-blocking mode request was made after the + UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was + signaled. + @retval EFI_DEVICE_ERROR Caller processor is AP. + @retval EFI_NOT_STARTED No enabled APs exist in the system. + @retval EFI_NOT_READY Any enabled APs are busy. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before + all enabled APs have finished. + @retval EFI_INVALID_PARAMETER Procedure is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_STARTUP_ALL_APS)( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN EFI_AP_PROCEDURE Procedure, + IN BOOLEAN SingleThread, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroSeconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT UINTN **FailedCpuList OPTIONAL + ); + +/** + This service lets the caller get one enabled AP to execute a caller-provided + function. The caller can request the BSP to either wait for the completion + of the AP or just proceed with the next task by using the EFI event mechanism. + See EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking + execution support. This service may only be called from the BSP. + + This function is used to dispatch one enabled AP to the function specified by + Procedure passing in the argument specified by ProcedureArgument. If WaitEvent + is NULL, execution is in blocking mode. The BSP waits until the AP finishes or + TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. + BSP proceeds to the next task without waiting for the AP. If a non-blocking mode + is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, + then EFI_UNSUPPORTED must be returned. + + If the timeout specified by TimeoutInMicroseconds expires before the AP returns + from Procedure, then execution of Procedure by the AP is terminated. The AP is + available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and + EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL + instance. + @param[in] Procedure A pointer to the function to be run on the + designated AP of the system. See type + EFI_AP_PROCEDURE. + @param[in] ProcessorNumber The handle number of the AP. The range is + from 0 to the total number of logical + processors minus 1. The total number of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). + @param[in] WaitEvent The event created by the caller with CreateEvent() + service. If it is NULL, then execute in + blocking mode. BSP waits until this AP finish + or TimeoutInMicroSeconds expires. If it's + not NULL, then execute in non-blocking mode. + BSP requests the function specified by + Procedure to be started on this AP, + and go on executing immediately. If this AP + return from Procedure or TimeoutInMicroSeconds + expires, this event is signaled. The BSP + can use the CheckEvent() or WaitForEvent() + services to check the state of event. Type + EFI_EVENT is defined in CreateEvent() in + the Unified Extensible Firmware Interface + Specification. + @param[in] TimeoutInMicrosecsond Indicates the time limit in microseconds for + this AP to finish this Procedure, either for + blocking or non-blocking mode. Zero means + infinity. If the timeout expires before + this AP returns from Procedure, then Procedure + on the AP is terminated. The + AP is available for next function assigned + by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() + or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). + If the timeout expires in blocking mode, + BSP returns EFI_TIMEOUT. If the timeout + expires in non-blocking mode, WaitEvent + is signaled with SignalEvent(). + @param[in] ProcedureArgument The parameter passed into Procedure on the + specified AP. + @param[out] Finished If NULL, this parameter is ignored. In + blocking mode, this parameter is ignored. + In non-blocking mode, if AP returns from + Procedure before the timeout expires, its + content is set to TRUE. Otherwise, the + value is set to FALSE. The caller can + determine if the AP returned from Procedure + by evaluating this value. + + @retval EFI_SUCCESS In blocking mode, specified AP finished before + the timeout expires. + @retval EFI_SUCCESS In non-blocking mode, the function has been + dispatched to specified AP. + @retval EFI_UNSUPPORTED A non-blocking mode request was made after the + UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was + signaled. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_TIMEOUT In blocking mode, the timeout expired before + the specified AP has finished. + @retval EFI_NOT_READY The specified AP is busy. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP. + @retval EFI_INVALID_PARAMETER Procedure is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_STARTUP_THIS_AP)( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN EFI_AP_PROCEDURE Procedure, + IN UINTN ProcessorNumber, + IN EFI_EVENT WaitEvent OPTIONAL, + IN UINTN TimeoutInMicroseconds, + IN VOID *ProcedureArgument OPTIONAL, + OUT BOOLEAN *Finished OPTIONAL + ); + +/** + This service switches the requested AP to be the BSP from that point onward. + This service changes the BSP for all purposes. This call can only be performed + by the current BSP. + + This service switches the requested AP to be the BSP from that point onward. + This service changes the BSP for all purposes. The new BSP can take over the + execution of the old BSP and continue seamlessly from where the old one left + off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT + is signaled. + + If the BSP cannot be switched prior to the return from this service, then + EFI_UNSUPPORTED must be returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL instance. + @param[in] ProcessorNumber The handle number of AP that is to become the new + BSP. The range is from 0 to the total number of + logical processors minus 1. The total number of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). + @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an + enabled AP. Otherwise, it will be disabled. + + @retval EFI_SUCCESS BSP successfully switched. + @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to + this service returning. + @retval EFI_UNSUPPORTED Switching the BSP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND The processor with the handle specified by + ProcessorNumber does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or + a disabled AP. + @retval EFI_NOT_READY The specified AP is busy. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_SWITCH_BSP)( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableOldBSP + ); + +/** + This service lets the caller enable or disable an AP from this point onward. + This service may only be called from the BSP. + + This service allows the caller enable or disable an AP from this point onward. + The caller can optionally specify the health status of the AP by Health. If + an AP is being disabled, then the state of the disabled AP is implementation + dependent. If an AP is enabled, then the implementation must guarantee that a + complete initialization sequence is performed on the AP, so the AP is in a state + that is compatible with an MP operating system. This service may not be supported + after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled. + + If the enable or disable AP operation cannot be completed prior to the return + from this service, then EFI_UNSUPPORTED must be returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL instance. + @param[in] ProcessorNumber The handle number of AP. + The range is from 0 to the total number of + logical processors minus 1. The total number of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). + @param[in] EnableAP Specifies the new state for the processor for + enabled, FALSE for disabled. + @param[in] HealthFlag If not NULL, a pointer to a value that specifies + the new health status of the AP. This flag + corresponds to StatusFlag defined in + EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only + the PROCESSOR_HEALTH_STATUS_BIT is used. All other + bits are ignored. If it is NULL, this parameter + is ignored. + + @retval EFI_SUCCESS The specified AP was enabled or disabled successfully. + @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed + prior to this service returning. + @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber + does not exist. + @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_ENABLEDISABLEAP)( + IN EFI_MP_SERVICES_PROTOCOL *This, + IN UINTN ProcessorNumber, + IN BOOLEAN EnableAP, + IN UINT32 *HealthFlag OPTIONAL + ); + +/** + This return the handle number for the calling processor. This service may be + called from the BSP and APs. + + This service returns the processor handle number for the calling processor. + The returned value is in the range from 0 to the total number of logical + processors minus 1. The total number of logical processors can be retrieved + with EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be + called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER + is returned. Otherwise, the current processors handle number is returned in + ProcessorNumber, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_MP_SERVICES_PROTOCOL instance. + @param[in] ProcessorNumber Pointer to the handle number of AP. + The range is from 0 to the total number of + logical processors minus 1. The total number of + logical processors can be retrieved by + EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). + + @retval EFI_SUCCESS The current processor handle number was returned + in ProcessorNumber. + @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MP_SERVICES_WHOAMI)( + IN EFI_MP_SERVICES_PROTOCOL *This, + OUT UINTN *ProcessorNumber + ); + +/// +/// When installed, the MP Services Protocol produces a collection of services +/// that are needed for MP management. +/// +/// Before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the module +/// that produces this protocol is required to place all APs into an idle state +/// whenever the APs are disabled or the APs are not executing code as requested +/// through the StartupAllAPs() or StartupThisAP() services. The idle state of +/// an AP before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled is +/// implementation dependent. +/// +/// After the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, all the APs +/// must be placed in the OS compatible CPU state as defined by the UEFI +/// Specification. Implementations of this protocol may use the UEFI event +/// EFI_EVENT_GROUP_READY_TO_BOOT to force APs into the OS compatible state as +/// defined by the UEFI Specification. Modules that use this protocol must +/// guarantee that all non-blocking mode requests on all APs have been completed +/// before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled. Since the +/// order that event notification functions in the same event group are executed +/// is not deterministic, an event of type EFI_EVENT_GROUP_READY_TO_BOOT cannot +/// be used to guarantee that APs have completed their non-blocking mode requests. +/// +/// When the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the StartAllAPs() +/// and StartupThisAp() services must no longer support non-blocking mode requests. +/// The support for SwitchBSP() and EnableDisableAP() may no longer be supported +/// after this event is signaled. Since UEFI Applications and UEFI OS Loaders +/// execute after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, these +/// UEFI images must be aware that the functionality of this protocol may be reduced. +/// +struct _EFI_MP_SERVICES_PROTOCOL { + EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; + EFI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; + EFI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; + EFI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; + EFI_MP_SERVICES_SWITCH_BSP SwitchBSP; + EFI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; + EFI_MP_SERVICES_WHOAMI WhoAmI; +}; + +extern EFI_GUID gEfiMpServiceProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp4.h new file mode 100644 index 0000000000..ce7e940229 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp4.h @@ -0,0 +1,587 @@ +/** @file + EFI Multicast Trivial File Transfer Protocol Definition + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0 + +**/ + +#ifndef __EFI_MTFTP4_PROTOCOL_H__ +#define __EFI_MTFTP4_PROTOCOL_H__ + +#define EFI_MTFTP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x2FE800BE, 0x8F01, 0x4aa6, {0x94, 0x6B, 0xD7, 0x13, 0x88, 0xE1, 0x83, 0x3F } \ + } + +#define EFI_MTFTP4_PROTOCOL_GUID \ + { \ + 0x78247c57, 0x63db, 0x4708, {0x99, 0xc2, 0xa8, 0xb4, 0xa9, 0xa6, 0x1f, 0x6b } \ + } + +typedef struct _EFI_MTFTP4_PROTOCOL EFI_MTFTP4_PROTOCOL; +typedef struct _EFI_MTFTP4_TOKEN EFI_MTFTP4_TOKEN; + +// +//MTFTP4 packet opcode definition +// +#define EFI_MTFTP4_OPCODE_RRQ 1 +#define EFI_MTFTP4_OPCODE_WRQ 2 +#define EFI_MTFTP4_OPCODE_DATA 3 +#define EFI_MTFTP4_OPCODE_ACK 4 +#define EFI_MTFTP4_OPCODE_ERROR 5 +#define EFI_MTFTP4_OPCODE_OACK 6 +#define EFI_MTFTP4_OPCODE_DIR 7 +#define EFI_MTFTP4_OPCODE_DATA8 8 +#define EFI_MTFTP4_OPCODE_ACK8 9 + +// +// MTFTP4 error code definition +// +#define EFI_MTFTP4_ERRORCODE_NOT_DEFINED 0 +#define EFI_MTFTP4_ERRORCODE_FILE_NOT_FOUND 1 +#define EFI_MTFTP4_ERRORCODE_ACCESS_VIOLATION 2 +#define EFI_MTFTP4_ERRORCODE_DISK_FULL 3 +#define EFI_MTFTP4_ERRORCODE_ILLEGAL_OPERATION 4 +#define EFI_MTFTP4_ERRORCODE_UNKNOWN_TRANSFER_ID 5 +#define EFI_MTFTP4_ERRORCODE_FILE_ALREADY_EXISTS 6 +#define EFI_MTFTP4_ERRORCODE_NO_SUCH_USER 7 +#define EFI_MTFTP4_ERRORCODE_REQUEST_DENIED 8 + +// +// MTFTP4 pacekt definitions +// +#pragma pack(1) + +typedef struct { + UINT16 OpCode; + UINT8 Filename[1]; +} EFI_MTFTP4_REQ_HEADER; + +typedef struct { + UINT16 OpCode; + UINT8 Data[1]; +} EFI_MTFTP4_OACK_HEADER; + +typedef struct { + UINT16 OpCode; + UINT16 Block; + UINT8 Data[1]; +} EFI_MTFTP4_DATA_HEADER; + +typedef struct { + UINT16 OpCode; + UINT16 Block[1]; +} EFI_MTFTP4_ACK_HEADER; + +typedef struct { + UINT16 OpCode; + UINT64 Block; + UINT8 Data[1]; +} EFI_MTFTP4_DATA8_HEADER; + +typedef struct { + UINT16 OpCode; + UINT64 Block[1]; +} EFI_MTFTP4_ACK8_HEADER; + +typedef struct { + UINT16 OpCode; + UINT16 ErrorCode; + UINT8 ErrorMessage[1]; +} EFI_MTFTP4_ERROR_HEADER; + +typedef union { + /// + /// Type of packets as defined by the MTFTPv4 packet opcodes. + /// + UINT16 OpCode; + /// + /// Read request packet header. + /// + EFI_MTFTP4_REQ_HEADER Rrq; + /// + /// Write request packet header. + /// + EFI_MTFTP4_REQ_HEADER Wrq; + /// + /// Option acknowledge packet header. + /// + EFI_MTFTP4_OACK_HEADER Oack; + /// + /// Data packet header. + /// + EFI_MTFTP4_DATA_HEADER Data; + /// + /// Acknowledgement packet header. + /// + EFI_MTFTP4_ACK_HEADER Ack; + /// + /// Data packet header with big block number. + /// + EFI_MTFTP4_DATA8_HEADER Data8; + /// + /// Acknowledgement header with big block num. + /// + EFI_MTFTP4_ACK8_HEADER Ack8; + /// + /// Error packet header. + /// + EFI_MTFTP4_ERROR_HEADER Error; +} EFI_MTFTP4_PACKET; + +#pragma pack() + +/// +/// MTFTP4 option definition. +/// +typedef struct { + UINT8 *OptionStr; + UINT8 *ValueStr; +} EFI_MTFTP4_OPTION; + + +typedef struct { + BOOLEAN UseDefaultSetting; + EFI_IPv4_ADDRESS StationIp; + EFI_IPv4_ADDRESS SubnetMask; + UINT16 LocalPort; + EFI_IPv4_ADDRESS GatewayIp; + EFI_IPv4_ADDRESS ServerIp; + UINT16 InitialServerPort; + UINT16 TryCount; + UINT16 TimeoutValue; +} EFI_MTFTP4_CONFIG_DATA; + + +typedef struct { + EFI_MTFTP4_CONFIG_DATA ConfigData; + UINT8 SupportedOptionCount; + UINT8 **SupportedOptoins; + UINT8 UnsupportedOptionCount; + UINT8 **UnsupportedOptoins; +} EFI_MTFTP4_MODE_DATA; + + +typedef struct { + EFI_IPv4_ADDRESS GatewayIp; + EFI_IPv4_ADDRESS ServerIp; + UINT16 ServerPort; + UINT16 TryCount; + UINT16 TimeoutValue; +} EFI_MTFTP4_OVERRIDE_DATA; + +// +// Protocol interfaces definition +// + +/** + A callback function that is provided by the caller to intercept + the EFI_MTFTP4_OPCODE_DATA or EFI_MTFTP4_OPCODE_DATA8 packets processed in the + EFI_MTFTP4_PROTOCOL.ReadFile() function, and alternatively to intercept + EFI_MTFTP4_OPCODE_OACK or EFI_MTFTP4_OPCODE_ERROR packets during a call to + EFI_MTFTP4_PROTOCOL.ReadFile(), WriteFile() or ReadDirectory(). + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The token that the caller provided in the + EFI_MTFTP4_PROTOCOL.ReadFile(), WriteFile() + or ReadDirectory() function. + @param PacketLen Indicates the length of the packet. + @param Packet The pointer to an MTFTPv4 packet. + + @retval EFI_SUCCESS The operation was successful. + @retval Others Aborts the transfer process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_CHECK_PACKET)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token, + IN UINT16 PacketLen, + IN EFI_MTFTP4_PACKET *Paket + ); + +/** + Timeout callback function. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The token that is provided in the + EFI_MTFTP4_PROTOCOL.ReadFile() or + EFI_MTFTP4_PROTOCOL.WriteFile() or + EFI_MTFTP4_PROTOCOL.ReadDirectory() functions + by the caller. + + @retval EFI_SUCCESS The operation was successful. + @retval Others Aborts download process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_TIMEOUT_CALLBACK)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token + ); + +/** + A callback function that the caller provides to feed data to the + EFI_MTFTP4_PROTOCOL.WriteFile() function. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The token provided in the + EFI_MTFTP4_PROTOCOL.WriteFile() by the caller. + @param Length Indicates the length of the raw data wanted on input, and the + length the data available on output. + @param Buffer The pointer to the buffer where the data is stored. + + @retval EFI_SUCCESS The operation was successful. + @retval Others Aborts session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_PACKET_NEEDED)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token, + IN OUT UINT16 *Length, + OUT VOID **Buffer + ); + + +/** + Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param ModeData The pointer to storage for the EFI MTFTPv4 Protocol driver mode data. + + @retval EFI_SUCCESS The configuration data was successfully returned. + @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated. + @retval EFI_INVALID_PARAMETER This is NULL or ModeData is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_GET_MODE_DATA)( + IN EFI_MTFTP4_PROTOCOL *This, + OUT EFI_MTFTP4_MODE_DATA *ModeData + ); + + +/** + Initializes, changes, or resets the default operational setting for this + EFI MTFTPv4 Protocol driver instance. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param MtftpConfigData The pointer to the configuration data structure. + + @retval EFI_SUCCESS The EFI MTFTPv4 Protocol driver was configured successfully. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_ACCESS_DENIED The EFI configuration could not be changed at this time because + there is one MTFTP background operation in progress. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) has not finished yet. + @retval EFI_UNSUPPORTED A configuration protocol (DHCP, BOOTP, RARP, etc.) could not + be located when clients choose to use the default address + settings. + @retval EFI_OUT_OF_RESOURCES The EFI MTFTPv4 Protocol driver instance data could not be + allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI + MTFTPv4 Protocol driver instance is not configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_CONFIGURE)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_CONFIG_DATA *MtftpConfigData OPTIONAL + ); + + +/** + Gets information about a file from an MTFTPv4 server. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param OverrideData Data that is used to override the existing parameters. If NULL, + the default parameters that were set in the + EFI_MTFTP4_PROTOCOL.Configure() function are used. + @param Filename The pointer to null-terminated ASCII file name string. + @param ModeStr The pointer to null-terminated ASCII mode string. If NULL, "octet" will be used. + @param OptionCount Number of option/value string pairs in OptionList. + @param OptionList The pointer to array of option/value string pairs. Ignored if + OptionCount is zero. + @param PacketLength The number of bytes in the returned packet. + @param Packet The pointer to the received packet. This buffer must be freed by + the caller. + + @retval EFI_SUCCESS An MTFTPv4 OACK packet was received and is in the Packet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Filename is NULL. + - OptionCount is not zero and OptionList is NULL. + - One or more options in OptionList have wrong format. + - PacketLength is NULL. + - One or more IPv4 addresses in OverrideData are not valid + unicast IPv4 addresses if OverrideData is not NULL. + @retval EFI_UNSUPPORTED One or more options in the OptionList are in the + unsupported list of structure EFI_MTFTP4_MODE_DATA. + @retval EFI_NOT_STARTED The EFI MTFTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) has not finished yet. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_TFTP_ERROR An MTFTPv4 ERROR packet was received and is in the Packet. + @retval EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received and the Packet is set to NULL. + @retval EFI_HOST_UNREACHABLE An ICMP host unreachable error packet was received and the Packet is set to NULL. + @retval EFI_PROTOCOL_UNREACHABLE An ICMP protocol unreachable error packet was received and the Packet is set to NULL. + @retval EFI_PORT_UNREACHABLE An ICMP port unreachable error packet was received and the Packet is set to NULL. + @retval EFI_ICMP_ERROR Some other ICMP ERROR packet was received and is in the Buffer. + @retval EFI_PROTOCOL_ERROR An unexpected MTFTPv4 packet was received and is in the Packet. + @retval EFI_TIMEOUT No responses were received from the MTFTPv4 server. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_GET_INFO)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_OVERRIDE_DATA *OverrideData OPTIONAL, + IN UINT8 *Filename, + IN UINT8 *ModeStr OPTIONAL, + IN UINT8 OptionCount, + IN EFI_MTFTP4_OPTION *OptionList, + OUT UINT32 *PacketLength, + OUT EFI_MTFTP4_PACKET **Packet OPTIONAL + ); + +/** + Parses the options in an MTFTPv4 OACK packet. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param PacketLen Length of the OACK packet to be parsed. + @param Packet The pointer to the OACK packet to be parsed. + @param OptionCount The pointer to the number of options in following OptionList. + @param OptionList The pointer to EFI_MTFTP4_OPTION storage. Call the EFI Boot + Service FreePool() to release the OptionList if the options + in this OptionList are not needed any more. + + @retval EFI_SUCCESS The OACK packet was valid and the OptionCount and + OptionList parameters have been updated. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - PacketLen is 0. + - Packet is NULL or Packet is not a valid MTFTPv4 packet. + - OptionCount is NULL. + @retval EFI_NOT_FOUND No options were found in the OACK packet. + @retval EFI_OUT_OF_RESOURCES Storage for the OptionList array cannot be allocated. + @retval EFI_PROTOCOL_ERROR One or more of the option fields is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_PARSE_OPTIONS)( + IN EFI_MTFTP4_PROTOCOL *This, + IN UINT32 PacketLen, + IN EFI_MTFTP4_PACKET *Packet, + OUT UINT32 *OptionCount, + OUT EFI_MTFTP4_OPTION **OptionList OPTIONAL + ); + + +/** + Downloads a file from an MTFTPv4 server. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The data file has been transferred successfully. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_BUFFER_TOO_SMALL BufferSize is not zero but not large enough to hold the + downloaded data in downloading process. + @retval EFI_ABORTED Current operation is aborted by user. + @retval EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received. + @retval EFI_HOST_UNREACHABLE An ICMP host unreachable error packet was received. + @retval EFI_PROTOCOL_UNREACHABLE An ICMP protocol unreachable error packet was received. + @retval EFI_PORT_UNREACHABLE An ICMP port unreachable error packet was received. + @retval EFI_ICMP_ERROR Some other ICMP ERROR packet was received. + @retval EFI_TIMEOUT No responses were received from the MTFTPv4 server. + @retval EFI_TFTP_ERROR An MTFTPv4 ERROR packet was received. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_READ_FILE)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token + ); + + + +/** + Sends a file to an MTFTPv4 server. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The upload session has started. + @retval EFI_UNSUPPORTED The operation is not supported by this implementation. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_UNSUPPORTED One or more options in the Token.OptionList are in + the unsupported list of structure EFI_MTFTP4_MODE_DATA. + @retval EFI_NOT_STARTED The EFI MTFTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_ALREADY_STARTED This Token is already being used in another MTFTPv4 session. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_WRITE_FILE)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token + ); + + +/** + Downloads a data file "directory" from an MTFTPv4 server. May be unsupported in some EFI + implementations. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + @param Token The pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The MTFTPv4 related file "directory" has been downloaded. + @retval EFI_UNSUPPORTED The operation is not supported by this implementation. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_UNSUPPORTED One or more options in the Token.OptionList are in + the unsupported list of structure EFI_MTFTP4_MODE_DATA. + @retval EFI_NOT_STARTED The EFI MTFTPv4 Protocol driver has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_ALREADY_STARTED This Token is already being used in another MTFTPv4 session. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_READ_DIRECTORY)( + IN EFI_MTFTP4_PROTOCOL *This, + IN EFI_MTFTP4_TOKEN *Token + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + @param This The pointer to the EFI_MTFTP4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI MTFTPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP4_POLL)( + IN EFI_MTFTP4_PROTOCOL *This + ); + +/// +/// The EFI_MTFTP4_PROTOCOL is designed to be used by UEFI drivers and applications +/// to transmit and receive data files. The EFI MTFTPv4 Protocol driver uses +/// the underlying EFI UDPv4 Protocol driver and EFI IPv4 Protocol driver. +/// +struct _EFI_MTFTP4_PROTOCOL { + EFI_MTFTP4_GET_MODE_DATA GetModeData; + EFI_MTFTP4_CONFIGURE Configure; + EFI_MTFTP4_GET_INFO GetInfo; + EFI_MTFTP4_PARSE_OPTIONS ParseOptions; + EFI_MTFTP4_READ_FILE ReadFile; + EFI_MTFTP4_WRITE_FILE WriteFile; + EFI_MTFTP4_READ_DIRECTORY ReadDirectory; + EFI_MTFTP4_POLL Poll; +}; + +struct _EFI_MTFTP4_TOKEN { + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// + EFI_STATUS Status; + /// + /// The event that will be signaled when the operation completes. If + /// set to NULL, the corresponding function will wait until the read or + /// write operation finishes. The type of Event must be + /// EVT_NOTIFY_SIGNAL. The Task Priority Level (TPL) of + /// Event must be lower than or equal to TPL_CALLBACK. + /// + EFI_EVENT Event; + /// + /// If not NULL, the data that will be used to override the existing configure data. + /// + EFI_MTFTP4_OVERRIDE_DATA *OverrideData; + /// + /// The pointer to the null-terminated ASCII file name string. + /// + UINT8 *Filename; + /// + /// The pointer to the null-terminated ASCII mode string. If NULL, "octet" is used. + /// + UINT8 *ModeStr; + /// + /// Number of option/value string pairs. + /// + UINT32 OptionCount; + /// + /// The pointer to an array of option/value string pairs. Ignored if OptionCount is zero. + /// + EFI_MTFTP4_OPTION *OptionList; + /// + /// The size of the data buffer. + /// + UINT64 BufferSize; + /// + /// The pointer to the data buffer. Data that is downloaded from the + /// MTFTPv4 server is stored here. Data that is uploaded to the + /// MTFTPv4 server is read from here. Ignored if BufferSize is zero. + /// + VOID *Buffer; + /// + /// The pointer to the context that will be used by CheckPacket, + /// TimeoutCallback and PacketNeeded. + /// + VOID *Context; + /// + /// The pointer to the callback function to check the contents of the received packet. + /// + EFI_MTFTP4_CHECK_PACKET CheckPacket; + /// + /// The pointer to the function to be called when a timeout occurs. + /// + EFI_MTFTP4_TIMEOUT_CALLBACK TimeoutCallback; + /// + /// The pointer to the function to provide the needed packet contents. + /// + EFI_MTFTP4_PACKET_NEEDED PacketNeeded; +}; + +extern EFI_GUID gEfiMtftp4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiMtftp4ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp6.h new file mode 100644 index 0000000000..c15d45fcfd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Mtftp6.h @@ -0,0 +1,820 @@ +/** @file + UEFI Multicast Trivial File Transfer Protocol v6 Definition, which is built upon + the EFI UDPv6 Protocol and provides basic services for client-side unicast and/or + multicast TFTP operations. + + Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_MTFTP6_PROTOCOL_H__ +#define __EFI_MTFTP6_PROTOCOL_H__ + + +#define EFI_MTFTP6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xd9760ff3, 0x3cca, 0x4267, {0x80, 0xf9, 0x75, 0x27, 0xfa, 0xfa, 0x42, 0x23 } \ + } + +#define EFI_MTFTP6_PROTOCOL_GUID \ + { \ + 0xbf0a78ba, 0xec29, 0x49cf, {0xa1, 0xc9, 0x7a, 0xe5, 0x4e, 0xab, 0x6a, 0x51 } \ + } + +typedef struct _EFI_MTFTP6_PROTOCOL EFI_MTFTP6_PROTOCOL; +typedef struct _EFI_MTFTP6_TOKEN EFI_MTFTP6_TOKEN; + +/// +/// MTFTP Packet OpCodes +///@{ +#define EFI_MTFTP6_OPCODE_RRQ 1 ///< The MTFTPv6 packet is a read request. +#define EFI_MTFTP6_OPCODE_WRQ 2 ///< The MTFTPv6 packet is a write request. +#define EFI_MTFTP6_OPCODE_DATA 3 ///< The MTFTPv6 packet is a data packet. +#define EFI_MTFTP6_OPCODE_ACK 4 ///< The MTFTPv6 packet is an acknowledgement packet. +#define EFI_MTFTP6_OPCODE_ERROR 5 ///< The MTFTPv6 packet is an error packet. +#define EFI_MTFTP6_OPCODE_OACK 6 ///< The MTFTPv6 packet is an option acknowledgement packet. +#define EFI_MTFTP6_OPCODE_DIR 7 ///< The MTFTPv6 packet is a directory query packet. +#define EFI_MTFTP6_OPCODE_DATA8 8 ///< The MTFTPv6 packet is a data packet with a big block number. +#define EFI_MTFTP6_OPCODE_ACK8 9 ///< The MTFTPv6 packet is an acknowledgement packet with a big block number. +///@} + +/// +/// MTFTP ERROR Packet ErrorCodes +///@{ +/// +/// The error code is not defined. See the error message in the packet (if any) for details. +/// +#define EFI_MTFTP6_ERRORCODE_NOT_DEFINED 0 +/// +/// The file was not found. +/// +#define EFI_MTFTP6_ERRORCODE_FILE_NOT_FOUND 1 +/// +/// There was an access violation. +/// +#define EFI_MTFTP6_ERRORCODE_ACCESS_VIOLATION 2 +/// +/// The disk was full or its allocation was exceeded. +/// +#define EFI_MTFTP6_ERRORCODE_DISK_FULL 3 +/// +/// The MTFTPv6 operation was illegal. +/// +#define EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION 4 +/// +/// The transfer ID is unknown. +/// +#define EFI_MTFTP6_ERRORCODE_UNKNOWN_TRANSFER_ID 5 +/// +/// The file already exists. +/// +#define EFI_MTFTP6_ERRORCODE_FILE_ALREADY_EXISTS 6 +/// +/// There is no such user. +/// +#define EFI_MTFTP6_ERRORCODE_NO_SUCH_USER 7 +/// +/// The request has been denied due to option negotiation. +/// +#define EFI_MTFTP6_ERRORCODE_REQUEST_DENIED 8 +///@} + +#pragma pack(1) + +/// +/// EFI_MTFTP6_REQ_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_RRQ for a read request + /// or OpCode = EFI_MTFTP6_OPCODE_WRQ for a write request. + /// + UINT16 OpCode; + /// + /// The file name to be downloaded or uploaded. + /// + UINT8 Filename[1]; +} EFI_MTFTP6_REQ_HEADER; + +/// +/// EFI_MTFTP6_OACK_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_OACK. + /// + UINT16 OpCode; + /// + /// The option strings in the option acknowledgement packet. + /// + UINT8 Data[1]; +} EFI_MTFTP6_OACK_HEADER; + +/// +/// EFI_MTFTP6_DATA_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_DATA. + /// + UINT16 OpCode; + /// + /// Block number of this data packet. + /// + UINT16 Block; + /// + /// The content of this data packet. + /// + UINT8 Data[1]; +} EFI_MTFTP6_DATA_HEADER; + +/// +/// EFI_MTFTP6_ACK_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_ACK. + /// + UINT16 OpCode; + /// + /// The block number of the data packet that is being acknowledged. + /// + UINT16 Block[1]; +} EFI_MTFTP6_ACK_HEADER; + +/// +/// EFI_MTFTP6_DATA8_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_DATA8. + /// + UINT16 OpCode; + /// + /// The block number of data packet. + /// + UINT64 Block; + /// + /// The content of this data packet. + /// + UINT8 Data[1]; +} EFI_MTFTP6_DATA8_HEADER; + +/// +/// EFI_MTFTP6_ACK8_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_ACK8. + /// + UINT16 OpCode; + /// + /// The block number of the data packet that is being acknowledged. + /// + UINT64 Block[1]; +} EFI_MTFTP6_ACK8_HEADER; + +/// +/// EFI_MTFTP6_ERROR_HEADER +/// +typedef struct { + /// + /// For this packet type, OpCode = EFI_MTFTP6_OPCODE_ERROR. + /// + UINT16 OpCode; + /// + /// The error number as defined by the MTFTPv6 packet error codes. + /// + UINT16 ErrorCode; + /// + /// Error message string. + /// + UINT8 ErrorMessage[1]; +} EFI_MTFTP6_ERROR_HEADER; + +/// +/// EFI_MTFTP6_PACKET +/// +typedef union { + UINT16 OpCode; ///< Type of packets as defined by the MTFTPv6 packet opcodes. + EFI_MTFTP6_REQ_HEADER Rrq; ///< Read request packet header. + EFI_MTFTP6_REQ_HEADER Wrq; ///< write request packet header. + EFI_MTFTP6_OACK_HEADER Oack; ///< Option acknowledge packet header. + EFI_MTFTP6_DATA_HEADER Data; ///< Data packet header. + EFI_MTFTP6_ACK_HEADER Ack; ///< Acknowledgement packet header. + EFI_MTFTP6_DATA8_HEADER Data8; ///< Data packet header with big block number. + EFI_MTFTP6_ACK8_HEADER Ack8; ///< Acknowledgement header with big block number. + EFI_MTFTP6_ERROR_HEADER Error; ///< Error packet header. +} EFI_MTFTP6_PACKET; + +#pragma pack() + +/// +/// EFI_MTFTP6_CONFIG_DATA +/// +typedef struct { + /// + /// The local IP address to use. Set to zero to let the underlying IPv6 + /// driver choose a source address. If not zero it must be one of the + /// configured IP addresses in the underlying IPv6 driver. + /// + EFI_IPv6_ADDRESS StationIp; + /// + /// Local port number. Set to zero to use the automatically assigned port number. + /// + UINT16 LocalPort; + /// + /// The IP address of the MTFTPv6 server. + /// + EFI_IPv6_ADDRESS ServerIp; + /// + /// The initial MTFTPv6 server port number. Request packets are + /// sent to this port. This number is almost always 69 and using zero + /// defaults to 69. + UINT16 InitialServerPort; + /// + /// The number of times to transmit MTFTPv6 request packets and wait for a response. + /// + UINT16 TryCount; + /// + /// The number of seconds to wait for a response after sending the MTFTPv6 request packet. + /// + UINT16 TimeoutValue; +} EFI_MTFTP6_CONFIG_DATA; + +/// +/// EFI_MTFTP6_MODE_DATA +/// +typedef struct { + /// + /// The configuration data of this instance. + /// + EFI_MTFTP6_CONFIG_DATA ConfigData; + /// + /// The number of option strings in the following SupportedOptions array. + /// + UINT8 SupportedOptionCount; + /// + /// An array of null-terminated ASCII option strings that are recognized and supported by + /// this EFI MTFTPv6 Protocol driver implementation. The buffer is + /// read only to the caller and the caller should NOT free the buffer. + /// + UINT8 **SupportedOptions; +} EFI_MTFTP6_MODE_DATA; + +/// +/// EFI_MTFTP_OVERRIDE_DATA +/// +typedef struct { + /// + /// IP address of the MTFTPv6 server. If set to all zero, the value that + /// was set by the EFI_MTFTP6_PROTOCOL.Configure() function will be used. + /// + EFI_IPv6_ADDRESS ServerIp; + /// + /// MTFTPv6 server port number. If set to zero, it will use the value + /// that was set by the EFI_MTFTP6_PROTOCOL.Configure() function. + /// + UINT16 ServerPort; + /// + /// Number of times to transmit MTFTPv6 request packets and wait + /// for a response. If set to zero, the value that was set by + /// theEFI_MTFTP6_PROTOCOL.Configure() function will be used. + /// + UINT16 TryCount; + /// + /// Number of seconds to wait for a response after sending the + /// MTFTPv6 request packet. If set to zero, the value that was set by + /// the EFI_MTFTP6_PROTOCOL.Configure() function will be used. + /// + UINT16 TimeoutValue; +} EFI_MTFTP6_OVERRIDE_DATA; + +/// +/// EFI_MTFTP6_OPTION +/// +typedef struct { + UINT8 *OptionStr; ///< Pointer to the null-terminated ASCII MTFTPv6 option string. + UINT8 *ValueStr; ///< Pointer to the null-terminated ASCII MTFTPv6 value string. +} EFI_MTFTP6_OPTION; + +/** + EFI_MTFTP6_TIMEOUT_CALLBACK is a callback function that the caller provides to capture the + timeout event in the EFI_MTFTP6_PROTOCOL.ReadFile(), EFI_MTFTP6_PROTOCOL.WriteFile() or + EFI_MTFTP6_PROTOCOL.ReadDirectory() functions. + + Whenever a timeout occurs, the EFI MTFTPv6 Protocol driver will call the EFI_MTFTP6_TIMEOUT_CALLBACK + function to notify the caller of the timeout event. Any status code other than EFI_SUCCESS + that is returned from this function will abort the current download process. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token The token that the caller provided in the EFI_MTFTP6_PROTOCOl.ReadFile(), + WriteFile() or ReadDirectory() function. + @param[in] PacketLen Indicates the length of the packet. + @param[in] Packet Pointer to an MTFTPv6 packet. + + @retval EFI_SUCCESS Operation success. + @retval Others Aborts session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_CHECK_PACKET)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token, + IN UINT16 PacketLen, + IN EFI_MTFTP6_PACKET *Packet + ); + +/** + EFI_MTFTP6_TIMEOUT_CALLBACK is a callback function that the caller provides to capture the + timeout event in the EFI_MTFTP6_PROTOCOL.ReadFile(), EFI_MTFTP6_PROTOCOL.WriteFile() or + EFI_MTFTP6_PROTOCOL.ReadDirectory() functions. + + Whenever a timeout occurs, the EFI MTFTPv6 Protocol driver will call the EFI_MTFTP6_TIMEOUT_CALLBACK + function to notify the caller of the timeout event. Any status code other than EFI_SUCCESS + that is returned from this function will abort the current download process. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token The token that is provided in the EFI_MTFTP6_PROTOCOL.ReadFile() or + EFI_MTFTP6_PROTOCOL.WriteFile() or EFI_MTFTP6_PROTOCOL.ReadDirectory() + functions by the caller. + + @retval EFI_SUCCESS Operation success. + @retval Others Aborts session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_TIMEOUT_CALLBACK)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token + ); + +/** + EFI_MTFTP6_PACKET_NEEDED is a callback function that the caller provides to feed data to the + EFI_MTFTP6_PROTOCOL.WriteFile() function. + + EFI_MTFTP6_PACKET_NEEDED provides another mechanism for the caller to provide data to upload + other than a static buffer. The EFI MTFTP6 Protocol driver always calls EFI_MTFTP6_PACKET_NEEDED + to get packet data from the caller if no static buffer was given in the initial call to + EFI_MTFTP6_PROTOCOL.WriteFile() function. Setting *Length to zero signals the end of the session. + Returning a status code other than EFI_SUCCESS aborts the session. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token The token provided in the EFI_MTFTP6_PROTOCOL.WriteFile() by the caller. + @param[in, out] Length Indicates the length of the raw data wanted on input, and the + length the data available on output. + @param[out] Buffer Pointer to the buffer where the data is stored. + + @retval EFI_SUCCESS Operation success. + @retval Others Aborts session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_PACKET_NEEDED)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token, + IN OUT UINT16 *Length, + OUT VOID **Buffer + ); + +struct _EFI_MTFTP6_TOKEN { + /// + /// The status that is returned to the caller at the end of the operation + /// to indicate whether this operation completed successfully. + /// Defined Status values are listed below. + /// + EFI_STATUS Status; + /// + /// The event that will be signaled when the operation completes. If + /// set to NULL, the corresponding function will wait until the read or + /// write operation finishes. The type of Event must be EVT_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// If not NULL, the data that will be used to override the existing + /// configure data. + /// + EFI_MTFTP6_OVERRIDE_DATA *OverrideData; + /// + /// Pointer to the null-terminated ASCII file name string. + /// + UINT8 *Filename; + /// + /// Pointer to the null-terminated ASCII mode string. If NULL, octet is used. + /// + UINT8 *ModeStr; + /// + /// Number of option/value string pairs. + /// + UINT32 OptionCount; + /// + /// Pointer to an array of option/value string pairs. Ignored if + /// OptionCount is zero. Both a remote server and this driver + /// implementation should support these options. If one or more + /// options are unrecognized by this implementation, it is sent to the + /// remote server without being changed. + /// + EFI_MTFTP6_OPTION *OptionList; + /// + /// On input, the size, in bytes, of Buffer. On output, the number + /// of bytes transferred. + /// + UINT64 BufferSize; + /// + /// Pointer to the data buffer. Data that is downloaded from the + /// MTFTPv6 server is stored here. Data that is uploaded to the + /// MTFTPv6 server is read from here. Ignored if BufferSize is zero. + /// + VOID *Buffer; + /// + /// Pointer to the context that will be used by CheckPacket, + /// TimeoutCallback and PacketNeeded. + /// + VOID *Context; + /// + /// Pointer to the callback function to check the contents of the + /// received packet. + /// + EFI_MTFTP6_CHECK_PACKET CheckPacket; + /// + /// Pointer to the function to be called when a timeout occurs. + /// + EFI_MTFTP6_TIMEOUT_CALLBACK TimeoutCallback; + /// + /// Pointer to the function to provide the needed packet contents. + /// Only used in WriteFile() operation. + /// + EFI_MTFTP6_PACKET_NEEDED PacketNeeded; +}; + +/** + Read the current operational settings. + + The GetModeData() function reads the current operational settings of this EFI MTFTPv6 + Protocol driver instance. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[out] ModeData The buffer in which the EFI MTFTPv6 Protocol driver mode + data is returned. + + @retval EFI_SUCCESS The configuration data was successfully returned. + @retval EFI_OUT_OF_RESOURCES The required mode data could not be allocated. + @retval EFI_INVALID_PARAMETER This is NULL or ModeData is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_GET_MODE_DATA)( + IN EFI_MTFTP6_PROTOCOL *This, + OUT EFI_MTFTP6_MODE_DATA *ModeData + ); + +/** + Initializes, changes, or resets the default operational setting for this EFI MTFTPv6 + Protocol driver instance. + + The Configure() function is used to set and change the configuration data for this EFI + MTFTPv6 Protocol driver instance. The configuration data can be reset to startup defaults by calling + Configure() with MtftpConfigData set to NULL. Whenever the instance is reset, any + pending operation is aborted. By changing the EFI MTFTPv6 Protocol driver instance configuration + data, the client can connect to different MTFTPv6 servers. The configuration parameters in + MtftpConfigData are used as the default parameters in later MTFTPv6 operations and can be + overridden in later operations. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] MtftpConfigData Pointer to the configuration data structure. + + @retval EFI_SUCCESS The EFI MTFTPv6 Protocol instance was configured successfully. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + - This is NULL. + - MtftpConfigData.StationIp is neither zero nor one + of the configured IP addresses in the underlying IPv6 driver. + - MtftpCofigData.ServerIp is not a valid IPv6 unicast address. + @retval EFI_ACCESS_DENIED - The configuration could not be changed at this time because there + is some MTFTP background operation in progress. + - MtftpCofigData.LocalPort is already in use. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_OUT_OF_RESOURCES The EFI MTFTPv6 Protocol driver instance data could not be + allocated. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI + MTFTPv6 Protocol driver instance is not configured. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_CONFIGURE)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_CONFIG_DATA *MtftpConfigData OPTIONAL +); + +/** + Get information about a file from an MTFTPv6 server. + + The GetInfo() function assembles an MTFTPv6 request packet with options, sends it to the + MTFTPv6 server, and may return an MTFTPv6 OACK, MTFTPv6 ERROR, or ICMP ERROR packet. + Retries occur only if no response packets are received from the MTFTPv6 server before the + timeout expires. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] OverrideData Data that is used to override the existing parameters. If NULL, the + default parameters that were set in the EFI_MTFTP6_PROTOCOL.Configure() + function are used. + @param[in] Filename Pointer to null-terminated ASCII file name string. + @param[in] ModeStr Pointer to null-terminated ASCII mode string. If NULL, octet will be used + @param[in] OptionCount Number of option/value string pairs in OptionList. + @param[in] OptionList Pointer to array of option/value string pairs. Ignored if + OptionCount is zero. + @param[out] PacketLength The number of bytes in the returned packet. + @param[out] Packet The pointer to the received packet. This buffer must be freed by + the caller. + + @retval EFI_SUCCESS An MTFTPv6 OACK packet was received and is in the Packet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Filename is NULL + - OptionCount is not zero and OptionList is NULL. + - One or more options in OptionList have wrong format. + - PacketLength is NULL. + - OverrideData.ServerIp is not valid unicast IPv6 addresses. + @retval EFI_UNSUPPORTED One or more options in the OptionList are unsupported by + this implementation. + @retval EFI_NOT_STARTED The EFI MTFTPv6 Protocol driver has not been started. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_TFTP_ERROR An MTFTPv6 ERROR packet was received and is in the Packet. + @retval EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received and the Packet is set to NULL. + @retval EFI_HOST_UNREACHABLE An ICMP host unreachable error packet was received and the Packet is set to NULL. + @retval EFI_PROTOCOL_UNREACHABLE An ICMP protocol unreachable error packet was received and the Packet is set to NULL. + @retval EFI_PORT_UNREACHABLE An ICMP port unreachable error packet was received and the Packet is set to NULL. + @retval EFI_ICMP_ERROR Some other ICMP ERROR packet was received and the Packet is set to NULL. + @retval EFI_PROTOCOL_ERROR An unexpected MTFTPv6 packet was received and is in the Packet. + @retval EFI_TIMEOUT No responses were received from the MTFTPv6 server. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_GET_INFO)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_OVERRIDE_DATA *OverrideData OPTIONAL, + IN UINT8 *Filename, + IN UINT8 *ModeStr OPTIONAL, + IN UINT8 OptionCount, + IN EFI_MTFTP6_OPTION *OptionList OPTIONAL, + OUT UINT32 *PacketLength, + OUT EFI_MTFTP6_PACKET **Packet OPTIONAL +); + +/** + Parse the options in an MTFTPv6 OACK packet. + + The ParseOptions() function parses the option fields in an MTFTPv6 OACK packet and + returns the number of options that were found and optionally a list of pointers to + the options in the packet. + If one or more of the option fields are not valid, then EFI_PROTOCOL_ERROR is returned + and *OptionCount and *OptionList stop at the last valid option. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] PacketLen Length of the OACK packet to be parsed. + @param[in] Packet Pointer to the OACK packet to be parsed. + @param[out] OptionCount Pointer to the number of options in the following OptionList. + @param[out] OptionList Pointer to EFI_MTFTP6_OPTION storage. Each pointer in the + OptionList points to the corresponding MTFTP option buffer + in the Packet. Call the EFI Boot Service FreePool() to + release the OptionList if the options in this OptionList + are not needed any more. + + @retval EFI_SUCCESS The OACK packet was valid and the OptionCount and + OptionList parameters have been updated. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - PacketLen is 0. + - Packet is NULL or Packet is not a valid MTFTPv6 packet. + - OptionCount is NULL. + @retval EFI_NOT_FOUND No options were found in the OACK packet. + @retval EFI_OUT_OF_RESOURCES Storage for the OptionList array can not be allocated. + @retval EFI_PROTOCOL_ERROR One or more of the option fields is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_PARSE_OPTIONS)( + IN EFI_MTFTP6_PROTOCOL *This, + IN UINT32 PacketLen, + IN EFI_MTFTP6_PACKET *Packet, + OUT UINT32 *OptionCount, + OUT EFI_MTFTP6_OPTION **OptionList OPTIONAL + ); + +/** + Download a file from an MTFTPv6 server. + + The ReadFile() function is used to initialize and start an MTFTPv6 download process and + optionally wait for completion. When the download operation completes, whether successfully or + not, the Token.Status field is updated by the EFI MTFTPv6 Protocol driver and then + Token.Event is signaled if it is not NULL. + + Data can be downloaded from the MTFTPv6 server into either of the following locations: + - A fixed buffer that is pointed to by Token.Buffer + - A download service function that is pointed to by Token.CheckPacket + + If both Token.Buffer and Token.CheckPacket are used, then Token.CheckPacket + will be called first. If the call is successful, the packet will be stored in Token.Buffer. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The data file has been transferred successfully. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_BUFFER_TOO_SMALL BufferSize is not zero but not large enough to hold the + downloaded data in downloading process. + @retval EFI_ABORTED Current operation is aborted by user. + @retval EFI_NETWORK_UNREACHABLE An ICMP network unreachable error packet was received. + @retval EFI_HOST_UNREACHABLE An ICMP host unreachable error packet was received. + @retval EFI_PROTOCOL_UNREACHABLE An ICMP protocol unreachable error packet was received. + @retval EFI_PORT_UNREACHABLE An ICMP port unreachable error packet was received. + @retval EFI_ICMP_ERROR An ICMP ERROR packet was received. + @retval EFI_TIMEOUT No responses were received from the MTFTPv6 server. + @retval EFI_TFTP_ERROR An MTFTPv6 ERROR packet was received. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + @retval EFI_NO_MEDIA There was a media error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_READ_FILE)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token + ); + +/** + Send a file to an MTFTPv6 server. May be unsupported in some implementations. + + The WriteFile() function is used to initialize an uploading operation with the given option list + and optionally wait for completion. If one or more of the options is not supported by the server, the + unsupported options are ignored and a standard TFTP process starts instead. When the upload + process completes, whether successfully or not, Token.Event is signaled, and the EFI MTFTPv6 + Protocol driver updates Token.Status. + + The caller can supply the data to be uploaded in the following two modes: + - Through the user-provided buffer + - Through a callback function + + With the user-provided buffer, the Token.BufferSize field indicates the length of the buffer, + and the driver will upload the data in the buffer. With an EFI_MTFTP6_PACKET_NEEDED + callback function, the driver will call this callback function to get more data from the user to upload. + See the definition of EFI_MTFTP6_PACKET_NEEDED for more information. These two modes + cannot be used at the same time. The callback function will be ignored if the user provides the + buffer. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The upload session has started. + @retval EFI_UNSUPPORTED The operation is not supported by this implementation. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token.Filename is NULL. + - Token.OptionCount is not zero and Token.OptionList is NULL. + - One or more options in Token.OptionList have wrong format. + - Token.Buffer and Token.PacketNeeded are both NULL. + - Token.OverrideData.ServerIp is not valid unicast IPv6 addresses. + @retval EFI_UNSUPPORTED One or more options in the Token.OptionList are not + supported by this implementation. + @retval EFI_NOT_STARTED The EFI MTFTPv6 Protocol driver has not been started. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_ALREADY_STARTED This Token is already being used in another MTFTPv6 session. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_WRITE_FILE)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token + ); + +/** + Download a data file directory from an MTFTPv6 server. May be unsupported in some implementations. + + The ReadDirectory() function is used to return a list of files on the MTFTPv6 server that are + logically (or operationally) related to Token.Filename. The directory request packet that is sent + to the server is built with the option list that was provided by caller, if present. + + The file information that the server returns is put into either of the following locations: + - A fixed buffer that is pointed to by Token.Buffer + - A download service function that is pointed to by Token.CheckPacket + + If both Token.Buffer and Token.CheckPacket are used, then Token.CheckPacket + will be called first. If the call is successful, the packet will be stored in Token.Buffer. + + The returned directory listing in the Token.Buffer or EFI_MTFTP6_PACKET consists of a list + of two or three variable-length ASCII strings, each terminated by a null character, for each file in the + directory. If the multicast option is involved, the first field of each directory entry is the static + multicast IP address and UDP port number that is associated with the file name. The format of the + field is ip:ip:ip:ip:port. If the multicast option is not involved, this field and its terminating + null character are not present. + + The next field of each directory entry is the file name and the last field is the file information string. + The information string contains the file size and the create/modify timestamp. The format of the + information string is filesize yyyy-mm-dd hh:mm:ss:ffff. The timestamp is + Coordinated Universal Time (UTC; also known as Greenwich Mean Time [GMT]). + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + @param[in] Token Pointer to the token structure to provide the parameters that are + used in this operation. + + @retval EFI_SUCCESS The MTFTPv6 related file "directory" has been downloaded. + @retval EFI_UNSUPPORTED The EFI MTFTPv6 Protocol driver does not support this function. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token.Filename is NULL. + - Token.OptionCount is not zero and Token.OptionList is NULL. + - One or more options in Token.OptionList have wrong format. + - Token.Buffer and Token.CheckPacket are both NULL. + - Token.OverrideData.ServerIp is not valid unicast IPv6 addresses. + @retval EFI_UNSUPPORTED One or more options in the Token.OptionList are not + supported by this implementation. + @retval EFI_NOT_STARTED The EFI MTFTPv6 Protocol driver has not been started. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_ALREADY_STARTED This Token is already being used in another MTFTPv6 session. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + @retval EFI_ACCESS_DENIED The previous operation has not completed yet. + @retval EFI_DEVICE_ERROR An unexpected network error or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_READ_DIRECTORY)( + IN EFI_MTFTP6_PROTOCOL *This, + IN EFI_MTFTP6_TOKEN *Token +); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase the rate that data + packets are moved between the communications device and the transmit and receive queues. + In some systems, the periodic timer event in the managed network driver may not poll the + underlying communications device fast enough to transmit and/or receive all data packets without + missing incoming packets or dropping outgoing packets. Drivers and applications that are + experiencing packet loss should try calling the Poll() function more often. + + @param[in] This Pointer to the EFI_MTFTP6_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_NOT_STARTED This EFI MTFTPv6 Protocol instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_MTFTP6_POLL)( + IN EFI_MTFTP6_PROTOCOL *This + ); + +/// +/// The EFI_MTFTP6_PROTOCOL is designed to be used by UEFI drivers and applications to transmit +/// and receive data files. The EFI MTFTPv6 Protocol driver uses the underlying EFI UDPv6 Protocol +/// driver and EFI IPv6 Protocol driver. +/// +struct _EFI_MTFTP6_PROTOCOL { + EFI_MTFTP6_GET_MODE_DATA GetModeData; + EFI_MTFTP6_CONFIGURE Configure; + EFI_MTFTP6_GET_INFO GetInfo; + EFI_MTFTP6_PARSE_OPTIONS ParseOptions; + EFI_MTFTP6_READ_FILE ReadFile; + EFI_MTFTP6_WRITE_FILE WriteFile; + EFI_MTFTP6_READ_DIRECTORY ReadDirectory; + EFI_MTFTP6_POLL Poll; +}; + +extern EFI_GUID gEfiMtftp6ServiceBindingProtocolGuid; +extern EFI_GUID gEfiMtftp6ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h new file mode 100644 index 0000000000..f80374a076 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h @@ -0,0 +1,112 @@ +/** @file + EFI Network Interface Identifier Protocol. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in EFI Specification 1.10. + +**/ + +#ifndef __EFI_NETWORK_INTERFACE_IDENTIFER_H__ +#define __EFI_NETWORK_INTERFACE_IDENTIFER_H__ + +// +// GUID retired from UEFI Specification 2.1b +// +#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_GUID \ + { \ + 0xE18541CD, 0xF755, 0x4f73, {0x92, 0x8D, 0x64, 0x3C, 0x8A, 0x79, 0xB2, 0x29 } \ + } + +// +// GUID intruduced in UEFI Specification 2.1b +// +#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_GUID_31 \ + { \ + 0x1ACED566, 0x76ED, 0x4218, {0xBC, 0x81, 0x76, 0x7F, 0x1F, 0x97, 0x7A, 0x89 } \ + } + +// +// Revision defined in UEFI Specification 2.4 +// +#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION 0x00020000 + + +/// +/// Revision defined in EFI1.1. +/// +#define EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE_REVISION EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION + +/// +/// Forward reference for pure ANSI compatability. +/// +typedef struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL; + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE; + +/// +/// An optional protocol that is used to describe details about the software +/// layer that is used to produce the Simple Network Protocol. +/// +struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL { + UINT64 Revision; ///< The revision of the EFI_NETWORK_INTERFACE_IDENTIFIER protocol. + UINT64 Id; ///< The address of the first byte of the identifying structure for this network + ///< interface. This is only valid when the network interface is started + ///< (see Start()). When the network interface is not started, this field is set to zero. + UINT64 ImageAddr; ///< The address of the first byte of the identifying structure for this + ///< network interface. This is set to zero if there is no structure. + UINT32 ImageSize; ///< The size of unrelocated network interface image. + CHAR8 StringId[4];///< A four-character ASCII string that is sent in the class identifier field of + ///< option 60 in DHCP. For a Type of EfiNetworkInterfaceUndi, this field is UNDI. + UINT8 Type; ///< Network interface type. This will be set to one of the values + ///< in EFI_NETWORK_INTERFACE_TYPE. + UINT8 MajorVer; ///< Major version number. + UINT8 MinorVer; ///< Minor version number. + BOOLEAN Ipv6Supported; ///< TRUE if the network interface supports IPv6; otherwise FALSE. + UINT16 IfNum; ///< The network interface number that is being identified by this Network + ///< Interface Identifier Protocol. This field must be less than or + ///< equal to the (IFcnt | IFcntExt <<8 ) fields in the !PXE structure. + +}; + +/// +///******************************************************* +/// EFI_NETWORK_INTERFACE_TYPE +///******************************************************* +/// +typedef enum { + EfiNetworkInterfaceUndi = 1 +} EFI_NETWORK_INTERFACE_TYPE; + +/// +/// Forward reference for pure ANSI compatability. +/// +typedef struct undiconfig_table UNDI_CONFIG_TABLE; + +/// +/// The format of the configuration table for UNDI +/// +struct undiconfig_table { + UINT32 NumberOfInterfaces; ///< The number of NIC devices + ///< that this UNDI controls. + UINT32 reserved; + UNDI_CONFIG_TABLE *nextlink; ///< A pointer to the next UNDI + ///< configuration table. + /// + /// The length of this array is given in the NumberOfInterfaces field. + /// + struct { + VOID *NII_InterfacePointer; ///< Pointer to the NII interface structure. + VOID *DevicePathPointer; ///< Pointer to the device path for this NIC. + } NII_entry[1]; +}; + +extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid; +extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid_31; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvdimmLabel.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvdimmLabel.h new file mode 100644 index 0000000000..c9b5642bc3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvdimmLabel.h @@ -0,0 +1,345 @@ +/** @file + EFI NVDIMM Label Protocol Definition + + The EFI NVDIMM Label Protocol is used to Provides services that allow management + of labels contained in a Label Storage Area that are associated with a specific + NVDIMM Device Path. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.7. + +**/ + +#ifndef __EFI_NVDIMM_LABEL_PROTOCOL_H__ +#define __EFI_NVDIMM_LABEL_PROTOCOL_H__ + +#define EFI_NVDIMM_LABEL_PROTOCOL_GUID \ + { \ + 0xd40b6b80, 0x97d5, 0x4282, {0xbb, 0x1d, 0x22, 0x3a, 0x16, 0x91, 0x80, 0x58 } \ + } + +typedef struct _EFI_NVDIMM_LABEL_PROTOCOL EFI_NVDIMM_LABEL_PROTOCOL; + +#define EFI_NVDIMM_LABEL_INDEX_SIG_LEN 16 +#define EFI_NVDIMM_LABEL_INDEX_ALIGN 256 +typedef struct { + /// + /// Signature of the Index Block data structure. Must be "NAMESPACE_INDEX\0". + /// + CHAR8 Sig[EFI_NVDIMM_LABEL_INDEX_SIG_LEN]; + + /// + /// Attributes of this Label Storage Area. + /// + UINT8 Flags[3]; + + /// + /// Size of each label in bytes, 128 bytes << LabelSize. + /// 1 means 256 bytes, 2 means 512 bytes, etc. Shall be 1 or greater. + /// + UINT8 LabelSize; + + /// + /// Sequence number used to identify which of the two Index Blocks is current. + /// + UINT32 Seq; + + /// + /// The offset of this Index Block in the Label Storage Area. + /// + UINT64 MyOff; + + /// + /// The size of this Index Block in bytes. + /// This field must be a multiple of the EFI_NVDIMM_LABEL_INDEX_ALIGN. + /// + UINT64 MySize; + + /// + /// The offset of the other Index Block paired with this one. + /// + UINT64 OtherOff; + + /// + /// The offset of the first slot where labels are stored in this Label Storage Area. + /// + UINT64 LabelOff; + + /// + /// The total number of slots for storing labels in this Label Storage Area. + /// + UINT32 NSlot; + + /// + /// Major version number. Value shall be 1. + /// + UINT16 Major; + + /// + /// Minor version number. Value shall be 2. + /// + UINT16 Minor; + + /// + /// 64-bit Fletcher64 checksum of all fields in this Index Block. + /// + UINT64 Checksum; + + /// + /// Array of unsigned bytes implementing a bitmask that tracks which label slots are free. + /// A bit value of 0 indicates in use, 1 indicates free. + /// The size of this field is the number of bytes required to hold the bitmask with NSlot bits, + /// padded with additional zero bytes to make the Index Block size a multiple of EFI_NVDIMM_LABEL_INDEX_ALIGN. + /// Any bits allocated beyond NSlot bits must be zero. + /// + UINT8 Free[]; +} EFI_NVDIMM_LABEL_INDEX_BLOCK; + +#define EFI_NVDIMM_LABEL_NAME_LEN 64 + +/// +/// The label is read-only. +/// +#define EFI_NVDIMM_LABEL_FLAGS_ROLABEL 0x00000001 + +/// +/// When set, the complete label set is local to a single NVDIMM Label Storage Area. +/// When clear, the complete label set is contained on multiple NVDIMM Label Storage Areas. +/// +#define EFI_NVDIMM_LABEL_FLAGS_LOCAL 0x00000002 + +/// +/// This reserved flag is utilized on older implementations and has been deprecated. +/// Do not use. +// +#define EFI_NVDIMM_LABEL_FLAGS_RESERVED 0x00000004 + +/// +/// When set, the label set is being updated. +/// +#define EFI_NVDIMM_LABEL_FLAGS_UPDATING 0x00000008 + +typedef struct { + /// + /// Unique Label Identifier UUID per RFC 4122. + /// + EFI_GUID Uuid; + + /// + /// NULL-terminated string using UTF-8 character formatting. + /// + CHAR8 Name[EFI_NVDIMM_LABEL_NAME_LEN]; + + /// + /// Attributes of this namespace. + /// + UINT32 Flags; + + /// + /// Total number of labels describing this namespace. + /// + UINT16 NLabel; + + /// + /// Position of this label in list of labels for this namespace. + /// + UINT16 Position; + + /// + /// The SetCookie is utilized by SW to perform consistency checks on the Interleave Set to verify the current + /// physical device configuration matches the original physical configuration when the labels were created + /// for the set.The label is considered invalid if the actual label set cookie doesn't match the cookie stored here. + /// + UINT64 SetCookie; + + /// + /// This is the default logical block size in bytes and may be superseded by a block size that is specified + /// in the AbstractionGuid. + /// + UINT64 LbaSize; + + /// + /// The DPA is the DIMM Physical address where the NVM contributing to this namespace begins on this NVDIMM. + /// + UINT64 Dpa; + + /// + /// The extent of the DPA contributed by this label. + /// + UINT64 RawSize; + + /// + /// Current slot in the Label Storage Area where this label is stored. + /// + UINT32 Slot; + + /// + /// Alignment hint used to advertise the preferred alignment of the data from within the namespace defined by this label. + /// + UINT8 Alignment; + + /// + /// Shall be 0. + /// + UINT8 Reserved[3]; + + /// + /// Range Type GUID that describes the access mechanism for the specified DPA range. + /// + EFI_GUID TypeGuid; + + /// + /// Identifies the address abstraction mechanism for this namespace. A value of 0 indicates no mechanism used. + /// + EFI_GUID AddressAbstractionGuid; + + /// + /// Shall be 0. + /// + UINT8 Reserved1[88]; + + /// + /// 64-bit Fletcher64 checksum of all fields in this Label. + /// This field is considered zero when the checksum is computed. + /// + UINT64 Checksum; +} EFI_NVDIMM_LABEL; + +typedef struct { + /// + /// The Region Offset field from the ACPI NFIT NVDIMM Region Mapping Structure for a given entry. + /// + UINT64 RegionOffset; + + /// + /// The serial number of the NVDIMM, assigned by the module vendor. + /// + UINT32 SerialNumber; + + /// + /// The identifier indicating the vendor of the NVDIMM. + /// + UINT16 VendorId; + + /// + /// The manufacturing date of the NVDIMM, assigned by the module vendor. + /// + UINT16 ManufacturingDate; + + /// + /// The manufacturing location from for the NVDIMM, assigned by the module vendor. + /// + UINT8 ManufacturingLocation; + + /// + /// Shall be 0. + /// + UINT8 Reserved[31]; +} EFI_NVDIMM_LABEL_SET_COOKIE_MAP; + +typedef struct { + /// + /// Array size is 1 if EFI_NVDIMM_LABEL_FLAGS_LOCAL is set indicating a Local Namespaces. + /// + EFI_NVDIMM_LABEL_SET_COOKIE_MAP Mapping[0]; +} EFI_NVDIMM_LABEL_SET_COOKIE_INFO; + +/** + Retrieves the Label Storage Area size and the maximum transfer size for the LabelStorageRead and + LabelStorageWrite methods. + + @param This A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance. + @param SizeOfLabelStorageArea The size of the Label Storage Area for the NVDIMM in bytes. + @param MaxTransferLength The maximum number of bytes that can be transferred in a single call to + LabelStorageRead or LabelStorageWrite. + + @retval EFI_SUCCESS The size of theLabel Storage Area and maximum transfer size returned are valid. + @retval EFI_ACCESS_DENIED The Label Storage Area for the NVDIMM device is not currently accessible. + @retval EFI_DEVICE_ERROR A physical device error occurred and the data transfer failed to complete. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_INFORMATION) ( + IN EFI_NVDIMM_LABEL_PROTOCOL *This, + OUT UINT32 *SizeOfLabelStorageArea, + OUT UINT32 *MaxTransferLength + ); + +/** + Retrieves the label data for the requested offset and length from within the Label Storage Area for + the NVDIMM. + + @param This A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance. + @param Offset The byte offset within the Label Storage Area to read from. + @param TransferLength Number of bytes to read from the Label Storage Area beginning at the byte + Offset specified. A TransferLength of 0 reads no data. + @param LabelData The return label data read at the requested offset and length from within + the Label Storage Area. + + @retval EFI_SUCCESS The label data from the Label Storage Area for the NVDIMM was read successfully + at the specified Offset and TransferLength and LabelData contains valid data. + @retval EFI_INVALID_PARAMETER Any of the following are true: + - Offset > SizeOfLabelStorageArea reported in the LabelStorageInformation return data. + - Offset + TransferLength is > SizeOfLabelStorageArea reported in the + LabelStorageInformation return data. + - TransferLength is > MaxTransferLength reported in the LabelStorageInformation return + data. + @retval EFI_ACCESS_DENIED The Label Storage Area for the NVDIMM device is not currently accessible and labels + cannot be read at this time. + @retval EFI_DEVICE_ERROR A physical device error occurred and the data transfer failed to complete. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_READ) ( + IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This, + IN UINT32 Offset, + IN UINT32 TransferLength, + OUT UINT8 *LabelData + ); + +/** + Writes the label data for the requested offset and length in to the Label Storage Area for the NVDIMM. + + @param This A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance. + @param Offset The byte offset within the Label Storage Area to write to. + @param TransferLength Number of bytes to write to the Label Storage Area beginning at the byte + Offset specified. A TransferLength of 0 writes no data. + @param LabelData The return label data write at the requested offset and length from within + the Label Storage Area. + + @retval EFI_SUCCESS The label data from the Label Storage Area for the NVDIMM written read successfully + at the specified Offset and TransferLength. + @retval EFI_INVALID_PARAMETER Any of the following are true: + - Offset > SizeOfLabelStorageArea reported in the LabelStorageInformation return data. + - Offset + TransferLength is > SizeOfLabelStorageArea reported in the + LabelStorageInformation return data. + - TransferLength is > MaxTransferLength reported in the LabelStorageInformation return + data. + @retval EFI_ACCESS_DENIED The Label Storage Area for the NVDIMM device is not currently accessible and labels + cannot be written at this time. + @retval EFI_DEVICE_ERROR A physical device error occurred and the data transfer failed to complete. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_WRITE) ( + IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This, + IN UINT32 Offset, + IN UINT32 TransferLength, + IN UINT8 *LabelData + ); + +/// +/// Provides services that allow management of labels contained in a Label Storage Area. +/// +struct _EFI_NVDIMM_LABEL_PROTOCOL { + EFI_NVDIMM_LABEL_STORAGE_INFORMATION LabelStorageInformation; + EFI_NVDIMM_LABEL_STORAGE_READ LabelStorageRead; + EFI_NVDIMM_LABEL_STORAGE_WRITE LabelStorageWrite; +}; + +extern EFI_GUID gEfiNvdimmLabelProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvmExpressPassthru.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvmExpressPassthru.h new file mode 100644 index 0000000000..f804d0f88d --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/NvmExpressPassthru.h @@ -0,0 +1,283 @@ +/** @file + This protocol provides services that allow NVM Express commands to be sent to an + NVM Express controller or to a specific namespace in a NVM Express controller. + This protocol interface is optimized for storage. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + +**/ + +#ifndef _UEFI_NVM_EXPRESS_PASS_THRU_H_ +#define _UEFI_NVM_EXPRESS_PASS_THRU_H_ + +#define EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL_GUID \ + { \ + 0x52c78312, 0x8edc, 0x4233, { 0x98, 0xf2, 0x1a, 0x1a, 0xa5, 0xe3, 0x88, 0xa5 } \ + } + +typedef struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL; + +typedef struct { + UINT32 Attributes; + UINT32 IoAlign; + UINT32 NvmeVersion; +} EFI_NVM_EXPRESS_PASS_THRU_MODE; + +// +// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is +// for directly addressable namespaces. +// +#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001 +// +// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is +// for a single volume logical namespace comprised of multiple namespaces. +// +#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002 +// +// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface +// supports non-blocking I/O. +// +#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004 +// +// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface +// supports NVM command set. +// +#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008 + +// +// FusedOperation +// +#define NORMAL_CMD 0x00 +#define FUSED_FIRST_CMD 0x01 +#define FUSED_SECOND_CMD 0x02 + +typedef struct { + UINT32 Opcode:8; + UINT32 FusedOperation:2; + UINT32 Reserved:22; +} NVME_CDW0; + +// +// Flags +// +#define CDW2_VALID 0x01 +#define CDW3_VALID 0x02 +#define CDW10_VALID 0x04 +#define CDW11_VALID 0x08 +#define CDW12_VALID 0x10 +#define CDW13_VALID 0x20 +#define CDW14_VALID 0x40 +#define CDW15_VALID 0x80 + +// +// Queue Type +// +#define NVME_ADMIN_QUEUE 0x00 +#define NVME_IO_QUEUE 0x01 + +typedef struct { + NVME_CDW0 Cdw0; + UINT8 Flags; + UINT32 Nsid; + UINT32 Cdw2; + UINT32 Cdw3; + UINT32 Cdw10; + UINT32 Cdw11; + UINT32 Cdw12; + UINT32 Cdw13; + UINT32 Cdw14; + UINT32 Cdw15; +} EFI_NVM_EXPRESS_COMMAND; + +typedef struct { + UINT32 DW0; + UINT32 DW1; + UINT32 DW2; + UINT32 DW3; +} EFI_NVM_EXPRESS_COMPLETION; + +typedef struct { + UINT64 CommandTimeout; + VOID *TransferBuffer; + UINT32 TransferLength; + VOID *MetadataBuffer; + UINT32 MetadataLength; + UINT8 QueueType; + EFI_NVM_EXPRESS_COMMAND *NvmeCmd; + EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion; +} EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET; + +// +// Protocol function prototypes +// +/** + Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports + both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking + I/O functionality is optional. + + + @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance. + @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command + Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's + (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to + all valid namespaces. + @param[in,out] Packet A pointer to the NVM Express Command Packet. + @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed. + If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O + is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM + Express Command Packet completes. + + @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred + to, or from DataBuffer. + @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred + is returned in TransferLength. + @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller + may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet. + @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM + Express Command Packet was not sent, so no additional status information is available. + @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express + controller. The NVM Express Command Packet was not sent so no additional status information + is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU)( + IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This, + IN UINT32 NamespaceId, + IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/** + Used to retrieve the next namespace ID for this NVM Express controller. + + The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid + namespace ID on this NVM Express controller. + + If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace + ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId + and a status of EFI_SUCCESS is returned. + + If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF, + then EFI_INVALID_PARAMETER is returned. + + If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid + namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId, + and EFI_SUCCESS is returned. + + If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM + Express controller, then EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance. + @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express + namespace present on the NVM Express controller. On output, a + pointer to the next NamespaceId of an NVM Express namespace on + an NVM Express controller. An input value of 0xFFFFFFFF retrieves + the first NamespaceId for an NVM Express namespace present on an + NVM Express controller. + + @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned. + @retval EFI_NOT_FOUND There are no more namespaces defined on this controller. + @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE)( + IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This, + IN OUT UINT32 *NamespaceId + ); + +/** + Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller. + + The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device + path node for the NVM Express namespace specified by NamespaceId. + + If the NamespaceId is not valid, then EFI_NOT_FOUND is returned. + + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. + + If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are + initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance. + @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be + allocated and built. Caller must set the NamespaceId to zero if the + device path node will contain a valid UUID. + @param[out] DevicePath A pointer to a single device path node that describes the NVM Express + namespace specified by NamespaceId. This function is responsible for + allocating the buffer DevicePath with the boot service AllocatePool(). + It is the caller's responsibility to free DevicePath when the caller + is finished with DevicePath. + @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified + by NamespaceId was allocated and returned in DevicePath. + @retval EFI_NOT_FOUND The NamespaceId is not valid. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH)( + IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This, + IN UINT32 NamespaceId, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Used to translate a device path node to a namespace ID. + + The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the + namespace described by DevicePath. + + If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express + Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID. + + If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned + + @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance. + @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on + the NVM Express controller. + @param[out] NamespaceId The NVM Express namespace ID contained in the device path node. + + @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId. + @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned. + @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver + supports, then EFI_UNSUPPORTED is returned. + @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver + supports, but there is not a valid translation from DevicePath to a namespace ID, + then EFI_NOT_FOUND is returned. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE)( + IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT32 *NamespaceId + ); + +// +// Protocol Interface Structure +// +struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL { + EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode; + EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru; + EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace; + EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath; + EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace; +}; + +extern EFI_GUID gEfiNvmExpressPassThruProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PartitionInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PartitionInfo.h new file mode 100644 index 0000000000..cabf140eb3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PartitionInfo.h @@ -0,0 +1,68 @@ +/** @file + This file defines the EFI Partition Information Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __PARTITION_INFO_PROTOCOL_H__ +#define __PARTITION_INFO_PROTOCOL_H__ + +#include +#include + +// +// EFI Partition Information Protocol GUID value +// +#define EFI_PARTITION_INFO_PROTOCOL_GUID \ + { 0x8cf2f62c, 0xbc9b, 0x4821, { 0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0 }}; + + +#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000 +#define PARTITION_TYPE_OTHER 0x00 +#define PARTITION_TYPE_MBR 0x01 +#define PARTITION_TYPE_GPT 0x02 + +#pragma pack(1) + +/// +/// Partition Information Protocol structure. +/// +typedef struct { + // + // Set to EFI_PARTITION_INFO_PROTOCOL_REVISION. + // + UINT32 Revision; + // + // Partition info type (PARTITION_TYPE_MBR, PARTITION_TYPE_GPT, or PARTITION_TYPE_OTHER). + // + UINT32 Type; + // + // If 1, partition describes an EFI System Partition. + // + UINT8 System; + UINT8 Reserved[7]; + union { + /// + /// MBR data + /// + MBR_PARTITION_RECORD Mbr; + /// + /// GPT data + /// + EFI_PARTITION_ENTRY Gpt; + } Info; +} EFI_PARTITION_INFO_PROTOCOL; + +#pragma pack() + +/// +/// Partition Information Protocol GUID variable. +/// +extern EFI_GUID gEfiPartitionInfoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pcd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pcd.h new file mode 100644 index 0000000000..e0eb679e74 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pcd.h @@ -0,0 +1,861 @@ +/** @file + Native Platform Configuration Database (PCD) Protocol + + Different with the EFI_PCD_PROTOCOL defined in PI 1.2 specification, the native + PCD protocol provide interfaces for dynamic and dynamic-ex type PCD. + The interfaces in dynamic type PCD do not require the token space guid as parameter, + but interfaces in dynamic-ex type PCD require token space guid as parameter. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.2. + +**/ + +#ifndef __PCD_H__ +#define __PCD_H__ + +extern EFI_GUID gPcdProtocolGuid; + +#define PCD_PROTOCOL_GUID \ + { 0x11b34006, 0xd85b, 0x4d0a, { 0xa2, 0x90, 0xd5, 0xa5, 0x71, 0x31, 0xe, 0xf7 } } + +#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0) + + +/** + Sets the SKU value for subsequent calls to set or get PCD token values. + + SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. + SetSku() is normally called only once by the system. + + For each item (token), the database can hold a single value that applies to all SKUs, + or multiple values, where each value is associated with a specific SKU Id. Items with multiple, + SKU-specific values are called SKU enabled. + + The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255. + For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the + single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the + last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token, + the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been + set for that Id, the results are unpredictable. + + @param[in] SkuId The SKU value that will be used when the PCD service will retrieve and + set values associated with a PCD token. + + +**/ +typedef +VOID +(EFIAPI *PCD_PROTOCOL_SET_SKU)( + IN UINTN SkuId + ); + + + +/** + Retrieves an 8-bit value for a given PCD token. + + Retrieves the current byte-sized value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT8 value. + +**/ +typedef +UINT8 +(EFIAPI *PCD_PROTOCOL_GET8)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 16-bit value for a given PCD token. + + Retrieves the current 16-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT16 value. + +**/ +typedef +UINT16 +(EFIAPI *PCD_PROTOCOL_GET16)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 32-bit value for a given PCD token. + + Retrieves the current 32-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT32 value. + +**/ +typedef +UINT32 +(EFIAPI *PCD_PROTOCOL_GET32)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 64-bit value for a given PCD token. + + Retrieves the current 64-bit value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The UINT64 value. + +**/ +typedef +UINT64 +(EFIAPI *PCD_PROTOCOL_GET64)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a pointer to a value for a given PCD token. + + Retrieves the current pointer to the buffer for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The pointer to the buffer to be retrived. + +**/ +typedef +VOID * +(EFIAPI *PCD_PROTOCOL_GET_POINTER)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves a Boolean value for a given PCD token. + + Retrieves the current boolean value for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The Boolean value. + +**/ +typedef +BOOLEAN +(EFIAPI *PCD_PROTOCOL_GET_BOOLEAN)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves the size of the value for a given PCD token. + + Retrieves the current size of a particular PCD token. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] TokenNumber The PCD token number. + + @return The size of the value for the PCD token. + +**/ +typedef +UINTN +(EFIAPI *PCD_PROTOCOL_GET_SIZE)( + IN UINTN TokenNumber + ); + + + +/** + Retrieves an 8-bit value for a given PCD token. + + Retrieves the 8-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 8-bit value for the PCD token. + +**/ +typedef +UINT8 +(EFIAPI *PCD_PROTOCOL_GET_EX_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 16-bit value for a given PCD token. + + Retrieves the 16-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 16-bit value for the PCD token. + +**/ +typedef +UINT16 +(EFIAPI *PCD_PROTOCOL_GET_EX_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a 32-bit value for a given PCD token. + + Retrieves the 32-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 32-bit value for the PCD token. + +**/ +typedef +UINT32 +(EFIAPI *PCD_PROTOCOL_GET_EX_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves an 64-bit value for a given PCD token. + + Retrieves the 64-bit value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size 64-bit value for the PCD token. + +**/ +typedef +UINT64 +(EFIAPI *PCD_PROTOCOL_GET_EX_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a pointer to a value for a given PCD token. + + Retrieves the current pointer to the buffer for a PCD token number. + Do not make any assumptions about the alignment of the pointer that + is returned by this function call. If the TokenNumber is invalid, + the results are unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The pointer to the buffer to be retrieved. + +**/ +typedef +VOID * +(EFIAPI *PCD_PROTOCOL_GET_EX_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves a Boolean value for a given PCD token. + + Retrieves the Boolean value of a particular PCD token. + If the TokenNumber is invalid or the token space + specified by Guid does not exist, the results are + unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size Boolean value for the PCD token. + +**/ +typedef +BOOLEAN +(EFIAPI *PCD_PROTOCOL_GET_EX_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Retrieves the size of the value for a given PCD token. + + Retrieves the current size of a particular PCD token. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The token space for the token number. + @param[in] TokenNumber The PCD token number. + + @return The size of the value for the PCD token. + +**/ +typedef +UINTN +(EFIAPI *PCD_PROTOCOL_GET_EX_SIZE)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber + ); + + + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET8)( + IN UINTN TokenNumber, + IN UINT8 Value + ); + + + +/** + Sets a 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET16)( + IN UINTN TokenNumber, + IN UINT16 Value + ); + + + +/** + Sets a 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET32)( + IN UINTN TokenNumber, + IN UINT32 Value + ); + + + +/** + Sets a 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET64)( + IN UINTN TokenNumber, + IN UINT64 Value + ); + + + +/** + Sets a value of a specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token. + On input, if the SizeOfValue is greater than the maximum size supported + for this TokenNumber then the output value of SizeOfValue will reflect + the maximum size supported for this TokenNumber. + @param[in] Buffer The buffer to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_POINTER)( + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfBuffer, + IN VOID *Buffer + ); + + + +/** + Sets a Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_BOOLEAN)( + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + + + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT8 Value + ); + + + +/** + Sets an 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT16 Value + ); + + + +/** + Sets a 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT32 Value + ); + + + +/** + Sets a 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT64 Value + ); + + + +/** + Sets a value of a specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token. + On input, if the SizeOfValue is greater than the maximum size supported + for this TokenNumber then the output value of SizeOfValue will reflect + the maximum size supported for this TokenNumber. + @param[in] Buffer The buffer to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfBuffer, + IN VOID *Buffer + ); + + + +/** + Sets a Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the + size of the value being set is compatible with the Token's existing definition. + If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The procedure returned successfully. + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data + being set was incompatible with a call to this function. + Use GetSize() to retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_SET_EX_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN BOOLEAN Value + ); + + + +/** + Callback on SET function prototype definition. + + This notification function serves two purposes. + Firstly, it notifies the module which did the registration that the value + of this PCD token has been set. Secondly, it provides a mechanism for the + module that did the registration to intercept the set operation and override + the value that has been set, if necessary. After the invocation of the callback function, + TokenData will be used by PCD service DXE driver to modify the internal data in + PCD database. + + @param[in] CallBackGuid The PCD token GUID being set. + @param[in] CallBackToken The PCD token number being set. + @param[in, out] TokenData A pointer to the token data being set. + @param[in] TokenDataSize The size, in bytes, of the data being set. + + @retval VOID + +**/ +typedef +VOID +(EFIAPI *PCD_PROTOCOL_CALLBACK)( + IN CONST EFI_GUID *CallBackGuid, OPTIONAL + IN UINTN CallBackToken, + IN OUT VOID *TokenData, + IN UINTN TokenDataSize + ); + + + +/** + Specifies a function to be called anytime the value of a designated token is changed. + + @param[in] TokenNumber The PCD token number. + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event + for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_CALLBACK_ONSET)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_PROTOCOL_CALLBACK CallBackFunction + ); + + + +/** + Cancels a previously set callback function for a particular PCD token number. + + @param[in] TokenNumber The PCD token number. + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event + for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_CANCEL_CALLBACK)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN UINTN TokenNumber, + IN PCD_PROTOCOL_CALLBACK CallBackFunction + ); + + + +/** + Retrieves the next valid token number in a given namespace. + + This is useful since the PCD infrastructure contains a sparse list of token numbers, + and one cannot a priori know what token numbers are valid in the database. + + If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned. + If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned. + If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned. + If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned. + The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid. + If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned. + If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned. + If TokenNumber is not present in the token space specified by Guid, then EFI_NOT_FOUND is returned. + + + @param[in] Guid The 128-bit unique value that designates the namespace from which to retrieve the next token. + This is an optional parameter that may be NULL. If this parameter is NULL, then a request is + being made to retrieve tokens from the default token space. + @param[in,out] TokenNumber + A pointer to the PCD token number to use to find the subsequent token number. + + @retval EFI_SUCCESS The PCD service has retrieved the next valid token number. + @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_GET_NEXT_TOKEN)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN OUT UINTN *TokenNumber + ); + + + +/** + Retrieves the next valid PCD token namespace for a given namespace. + + Gets the next valid token namespace for a given namespace. This is useful to traverse the valid + token namespaces on a platform. + + @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token namespace + from which the search will start. On output, it designates the next valid token + namespace on the platform. If *Guid is NULL, then the GUID of the first token + space of the current platform is returned. If the search cannot locate the next valid + token namespace, an error is returned and the value of *Guid is undefined. + + @retval EFI_SUCCESS The PCD service retrieved the value requested. + @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace. + +**/ +typedef +EFI_STATUS +(EFIAPI *PCD_PROTOCOL_GET_NEXT_TOKENSPACE)( + IN OUT CONST EFI_GUID **Guid + ); + +/// +/// This service abstracts the ability to set/get Platform Configuration Database (PCD). +/// +typedef struct { + PCD_PROTOCOL_SET_SKU SetSku; + + PCD_PROTOCOL_GET8 Get8; + PCD_PROTOCOL_GET16 Get16; + PCD_PROTOCOL_GET32 Get32; + PCD_PROTOCOL_GET64 Get64; + PCD_PROTOCOL_GET_POINTER GetPtr; + PCD_PROTOCOL_GET_BOOLEAN GetBool; + PCD_PROTOCOL_GET_SIZE GetSize; + + PCD_PROTOCOL_GET_EX_8 Get8Ex; + PCD_PROTOCOL_GET_EX_16 Get16Ex; + PCD_PROTOCOL_GET_EX_32 Get32Ex; + PCD_PROTOCOL_GET_EX_64 Get64Ex; + PCD_PROTOCOL_GET_EX_POINTER GetPtrEx; + PCD_PROTOCOL_GET_EX_BOOLEAN GetBoolEx; + PCD_PROTOCOL_GET_EX_SIZE GetSizeEx; + + PCD_PROTOCOL_SET8 Set8; + PCD_PROTOCOL_SET16 Set16; + PCD_PROTOCOL_SET32 Set32; + PCD_PROTOCOL_SET64 Set64; + PCD_PROTOCOL_SET_POINTER SetPtr; + PCD_PROTOCOL_SET_BOOLEAN SetBool; + + PCD_PROTOCOL_SET_EX_8 Set8Ex; + PCD_PROTOCOL_SET_EX_16 Set16Ex; + PCD_PROTOCOL_SET_EX_32 Set32Ex; + PCD_PROTOCOL_SET_EX_64 Set64Ex; + PCD_PROTOCOL_SET_EX_POINTER SetPtrEx; + PCD_PROTOCOL_SET_EX_BOOLEAN SetBoolEx; + + PCD_PROTOCOL_CALLBACK_ONSET CallbackOnSet; + PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback; + PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken; + PCD_PROTOCOL_GET_NEXT_TOKENSPACE GetNextTokenSpace; +} PCD_PROTOCOL; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PcdInfo.h new file mode 100644 index 0000000000..3f461b978a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PcdInfo.h @@ -0,0 +1,102 @@ +/** @file + Native Platform Configuration Database (PCD) INFO PROTOCOL. + + The protocol that provides additional information about items that reside in the PCD database. + + Different with the EFI_GET_PCD_INFO_PROTOCOL defined in PI 1.2.1 specification, + the native PCD INFO PROTOCOL provide interfaces for dynamic and dynamic-ex type PCD. + The interfaces for dynamic type PCD do not require the token space guid as parameter, + but interfaces for dynamic-ex type PCD require token space guid as parameter. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.2. + +**/ + +#ifndef __PCD_INFO_H__ +#define __PCD_INFO_H__ + +extern EFI_GUID gGetPcdInfoProtocolGuid; + +#define GET_PCD_INFO_PROTOCOL_GUID \ + { 0x5be40f57, 0xfa68, 0x4610, { 0xbb, 0xbf, 0xe9, 0xc5, 0xfc, 0xda, 0xd3, 0x65 } } + +/// +/// The forward declaration for GET_PCD_INFO_PROTOCOL. +/// +typedef struct _GET_PCD_INFO_PROTOCOL GET_PCD_INFO_PROTOCOL; + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO) ( + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO_EX) ( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve the currently set SKU Id. + + @return The currently set SKU Id. If the platform has not set at a SKU Id, then the + default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU + Id is returned. +**/ +typedef +UINTN +(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_SKU) ( + VOID +); + +/// +/// This is the PCD service to use when querying for some additional data that can be contained in the +/// PCD database. +/// +struct _GET_PCD_INFO_PROTOCOL { + /// + /// Retrieve additional information associated with a PCD. + /// + GET_PCD_INFO_PROTOCOL_GET_INFO GetInfo; + GET_PCD_INFO_PROTOCOL_GET_INFO_EX GetInfoEx; + /// + /// Retrieve the currently set SKU Id. + /// + GET_PCD_INFO_PROTOCOL_GET_SKU GetSku; +}; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciEnumerationComplete.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciEnumerationComplete.h new file mode 100644 index 0000000000..8054c48b6a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciEnumerationComplete.h @@ -0,0 +1,24 @@ +/** @file + PCI Enumeration Complete Protocol as defined in the PI 1.1 specification. + This protocol indicates that pci enumeration complete + + Copyright (c) 2009, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef _PCI_ENUMERATION_COMPLETE_H_ +#define _PCI_ENUMERATION_COMPLETE_H_ + +#define EFI_PCI_ENUMERATION_COMPLETE_GUID \ + { \ + 0x30cfe3e7, 0x3de1, 0x4586, { 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93 } \ + } + +extern EFI_GUID gEfiPciEnumerationCompleteProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h new file mode 100644 index 0000000000..744c47aaac --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h @@ -0,0 +1,422 @@ +/** @file + This file declares PCI Host Bridge Resource Allocation Protocol which + provides the basic interfaces to abstract a PCI host bridge resource allocation. + This protocol is mandatory if the system includes PCI devices. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards. + +**/ + +#ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_ +#define _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_ + +// +// This file must be included because EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL +// uses EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS +// +#include + +/// +/// Global ID for the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL. +/// +#define EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GUID \ + { \ + 0xCF8034BE, 0x6768, 0x4d8b, {0xB7,0x39,0x7C,0xCE,0x68,0x3A,0x9F,0xBE } \ + } + +/// +/// Forward declaration for EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL. +/// +typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL; + +/// If this bit is set, then the PCI Root Bridge does not +/// support separate windows for Non-prefetchable and Prefetchable +/// memory. A PCI bus driver needs to include requests for Prefetchable +/// memory in the Non-prefetchable memory pool. +/// +#define EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM 1 + +/// +/// If this bit is set, then the PCI Root Bridge supports +/// 64 bit memory windows. If this bit is not set, +/// the PCI bus driver needs to include requests for 64 bit +/// memory address in the corresponding 32 bit memory pool. +/// +#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2 + +/// +/// A UINT64 value that contains the status of a PCI resource requested +/// in the Configuration parameter returned by GetProposedResources() +/// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED +/// +typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS; + +/// +/// The request of this resource type could be fulfilled. Used in the +/// Configuration parameter returned by GetProposedResources() to identify +/// a PCI resources request that can be satisfied. +/// +#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL + +/// +/// The request of this resource type could not be fulfilled for its +/// absence in the host bridge resource pool. Used in the Configuration parameter +/// returned by GetProposedResources() to identify a PCI resources request that +/// can not be satisfied. +/// +#define EFI_RESOURCE_NOT_SATISFIED 0xFFFFFFFFFFFFFFFFULL + +/// +/// This enum is used to specify the phase of the PCI enumaeration process. +/// +typedef enum { + /// + /// Reset the host bridge PCI apertures and internal data structures. + /// PCI enumerator should issue this notification before starting fresh + /// enumeration process. Enumeration cannot be restarted after sending + /// any other notification such as EfiPciHostBridgeBeginBusAllocation. + /// + EfiPciHostBridgeBeginEnumeration, + + /// + /// The bus allocation phase is about to begin. No specific action + /// is required here. This notification can be used to perform any + /// chipset specific programming. + /// + EfiPciHostBridgeBeginBusAllocation, + + /// + /// The bus allocation and bus programming phase is complete. No specific + /// action is required here. This notification can be used to perform any + /// chipset specific programming. + /// + EfiPciHostBridgeEndBusAllocation, + + /// + /// The resource allocation phase is about to begin.No specific action is + /// required here. This notification can be used to perform any chipset specific programming. + /// + EfiPciHostBridgeBeginResourceAllocation, + + /// + /// Allocate resources per previously submitted requests for all the PCI Root + /// Bridges. These resource settings are returned on the next call to + /// GetProposedResources(). + /// + EfiPciHostBridgeAllocateResources, + + /// + /// Program the Host Bridge hardware to decode previously allocated resources + /// (proposed resources) for all the PCI Root Bridges. + /// + EfiPciHostBridgeSetResources, + + /// + /// De-allocate previously allocated resources previously for all the PCI + /// Root Bridges and reset the I/O and memory apertures to initial state. + /// + EfiPciHostBridgeFreeResources, + + /// + /// The resource allocation phase is completed. No specific action is required + /// here. This notification can be used to perform any chipset specific programming. + /// + EfiPciHostBridgeEndResourceAllocation, + + /// + /// The Host Bridge Enumeration is completed. No specific action is required here. + /// This notification can be used to perform any chipset specific programming. + /// + EfiPciHostBridgeEndEnumeration, + EfiMaxPciHostBridgeEnumerationPhase +} EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE; + +/// +/// Definitions of 2 notification points. +/// +typedef enum { + /// + /// This notification is only applicable to PCI-PCI bridges and + /// indicates that the PCI enumerator is about to begin enumerating + /// the bus behind the PCI-PCI Bridge. This notification is sent after + /// the primary bus number, the secondary bus number and the subordinate + /// bus number registers in the PCI-PCI Bridge are programmed to valid + /// (not necessary final) values + /// + EfiPciBeforeChildBusEnumeration, + + /// + /// This notification is sent before the PCI enumerator probes BAR registers + /// for every valid PCI function. + /// + EfiPciBeforeResourceCollection +} EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE; + +/** + These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI + enumeration process. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] Phase The phase during enumeration. + + @retval EFI_SUCCESS The notification was accepted without any errors. + @retval EFI_INVALID_PARAMETER The Phase is invalid. + @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error + is valid for a Phase of EfiPciHostBridgeAllocateResources if + SubmitResources() has not been called for one or more + PCI root bridges before this call. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid for + a Phase of EfiPciHostBridgeSetResources. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + This error is valid for a Phase of EfiPciHostBridgeAllocateResources + if the previously submitted resource requests cannot be fulfilled or were only + partially fulfilled + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ); + +/** + Returns the device handle of the next PCI root bridge that is associated with this host bridge. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in,out] RootBridgeHandle Returns the device handle of the next PCI root bridge. On input, it holds the + RootBridgeHandle that was returned by the most recent call to + GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle + for the first PCI root bridge is returned. + + @retval EFI_SUCCESS The requested attribute information was returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was returned + on a previous call to GetNextRootBridge(). + @retval EFI_NOT_FOUND There are no more PCI root bridge device handles. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle + ); + +/** + Returns the allocation attributes of a PCI root bridge. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. + @param[out] Attribute The pointer to attributes of the PCI root bridge. + + @retval EFI_SUCCESS The requested attribute information was returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_INVALID_PARAMETER Attributes is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ); + +/** + Sets up the specified PCI root bridge for the bus enumeration process. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge to be set up. + @param[out] Configuration The pointer to the pointer to the PCI bus resource descriptor. + + @retval EFI_SUCCESS The PCI root bridge was set up and the bus range was returned in + Configuration. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + Programs the PCI root bridge hardware so that it decodes the specified PCI bus range. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge whose bus range is to be programmed. + @param[in] Configuration The pointer to the PCI bus resource descriptor. + + @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_INVALID_PARAMETER Configuration is NULL + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) + resource descriptor. + @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource + descriptor. + @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI (2.0 & 3.0) resource + descriptors other than bus descriptors. + @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource + descriptors. + @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge. + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + Submits the I/O and memory resource requirements for the specified PCI root bridge. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being + submitted. + @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor. + + @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were + accepted. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_INVALID_PARAMETER Configuration is NULL. + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI (2.0 & 3.0) + resource descriptor. + @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource + types that are not supported by this PCI root bridge. This error will + happen if the caller did not combine resources according to + Attributes that were returned by GetAllocAttributes(). + @retval EFI_INVALID_PARAMETER "Address Range Maximum" is invalid. + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + Returns the proposed resource settings for the specified PCI root bridge. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge handle. + @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor. + + @retval EFI_SUCCESS The requested parameters were returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various + stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual + PCI controllers before enumeration. + + @param[in] This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. + @param[in] RootBridgeHandle The associated PCI root bridge handle. + @param[in] PciAddress The address of the PCI device on the PCI bus. + @param[in] Phase The phase of the PCI device enumeration. + + @retval EFI_SUCCESS The requested parameters were returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. + @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in + EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator + should not enumerate this device, including its child devices if it is + a PCI-to-PCI bridge. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER)( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ); + +/// +/// Provides the basic interfaces to abstract a PCI host bridge resource allocation. +/// +struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL { + /// + /// The notification from the PCI bus enumerator that it is about to enter + /// a certain phase during the enumeration process. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase; + + /// + /// Retrieves the device handle for the next PCI root bridge that is produced by the + /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge; + + /// + /// Retrieves the allocation-related attributes of a PCI root bridge. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes; + + /// + /// Sets up a PCI root bridge for bus enumeration. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration; + + /// + /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers; + + /// + /// Submits the resource requirements for the specified PCI root bridge. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources; + + /// + /// Returns the proposed resource assignment for the specified PCI root bridges. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources; + + /// + /// Provides hooks from the PCI bus driver to every PCI controller + /// (device/function) at various stages of the PCI enumeration process that + /// allow the host bridge driver to preinitialize individual PCI controllers + /// before enumeration. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController; +}; + +extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugInit.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugInit.h new file mode 100644 index 0000000000..9cf91479ad --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugInit.h @@ -0,0 +1,272 @@ +/** @file + This file declares EFI PCI Hot Plug Init Protocol. + + This protocol provides the necessary functionality to initialize the Hot Plug + Controllers (HPCs) and the buses that they control. This protocol also provides + information regarding resource padding. + + @par Note: + This protocol is required only on platforms that support one or more PCI Hot + Plug* slots or CardBus sockets. + + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator + to properly initialize the HPCs and CardBus sockets that require initialization. + The HPC initialization takes place before the PCI enumeration process is complete. + There cannot be more than one instance of this protocol in a system. This protocol + is installed on its own separate handle. + + Because the system may include multiple HPCs, one instance of this protocol + should represent all of them. The protocol functions use the device path of + the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc() + is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC + and continue the enumeration process. If the HPC is not initialized, the devices + that it controls may not be initialized, and no resource padding will be provided. + + From the standpoint of the PCI bus enumerator, HPCs are divided into the following + two classes: + + - Root HPC: + These HPCs must be initialized by calling InitializeRootHpc() during the + enumeration process. These HPCs will also require resource padding. The + platform code must have a priori knowledge of these devices and must know + how to initialize them. There may not be any way to access their PCI + configuration space before the PCI enumerator programs all the upstream + bridges and thus enables the path to these devices. The PCI bus enumerator + is responsible for determining the PCI bus address of the HPC before it + calls InitializeRootHpc(). + - Nonroot HPC: + These HPCs will not need explicit initialization during enumeration process. + These HPCs will require resource padding. The platform code does not have + to have a priori knowledge of these devices. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef _EFI_PCI_HOT_PLUG_INIT_H_ +#define _EFI_PCI_HOT_PLUG_INIT_H_ + +/// +/// Global ID for the EFI_PCI_HOT_PLUG_INIT_PROTOCOL +/// +#define EFI_PCI_HOT_PLUG_INIT_PROTOCOL_GUID \ + { \ + 0xaa0e8bc1, 0xdabc, 0x46b0, {0xa8, 0x44, 0x37, 0xb8, 0x16, 0x9b, 0x2b, 0xea } \ + } + +/// +/// Forward declaration for EFI_PCI_HOT_PLUG_INIT_PROTOCOL +/// +typedef struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL EFI_PCI_HOT_PLUG_INIT_PROTOCOL; + +/// +/// Describes the current state of an HPC +/// +typedef UINT16 EFI_HPC_STATE; + +/// +/// The HPC initialization function was called and the HPC completed +/// initialization, but it was not enabled for some reason. The HPC may be +/// disabled in hardware, or it may be disabled due to user preferences, +/// hardware failure, or other reasons. No resource padding is required. +/// +#define EFI_HPC_STATE_INITIALIZED 0x01 + +/// +/// The HPC initialization function was called, the HPC completed +/// initialization, and it was enabled. Resource padding is required. +/// +#define EFI_HPC_STATE_ENABLED 0x02 + +/// +/// Location definition for PCI Hot Plug Controller +/// +typedef struct{ + /// + /// + /// The device path to the root HPC. An HPC cannot control its parent buses. + /// The PCI bus driver requires this information so that it can pass the + /// correct HpcPciAddress to the InitializeRootHpc() and GetResourcePadding() + /// functions. + /// + EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath; + /// + /// The device path to the Hot Plug Bus (HPB) that is controlled by the root + /// HPC. The PCI bus driver uses this information to check if a particular PCI + /// bus has hot-plug slots. The device path of a PCI bus is the same as the + /// device path of its parent. For Standard(PCI) Hot Plug Controllers (SHPCs) + /// and PCI Express*, HpbDevicePath is the same as HpcDevicePath. + /// + EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath; +} EFI_HPC_LOCATION; + +/// +/// Describes how resource padding should be applied +/// +typedef enum { + /// + /// Apply the padding at a PCI bus level. In other words, the resources + /// that are allocated to the bus containing hot-plug slots are padded by + /// the specified amount. If the hot-plug bus is behind a PCI-to-PCI + /// bridge, the PCI-to-PCI bridge apertures will indicate the padding + /// + EfiPaddingPciBus, + /// + /// Apply the padding at a PCI root bridge level. If a PCI root bridge + /// includes more than one hot-plug bus, the resource padding requests + /// for these buses are added together and the resources that are + /// allocated to the root bridge are padded by the specified amount. This + /// strategy may reduce the total amount of padding, but requires + /// reprogramming of PCI-to-PCI bridges in a hot-add event. If the hotplug + /// bus is behind a PCI-to-PCI bridge, the PCI-to-PCI bridge + /// apertures do not indicate the padding for that bus. + /// + EfiPaddingPciRootBridge +} EFI_HPC_PADDING_ATTRIBUTES; + +/** + Returns a list of root Hot Plug Controllers (HPCs) that require initialization + during the boot process. + + This procedure returns a list of root HPCs. The PCI bus driver must initialize + these controllers during the boot process. The PCI bus driver may or may not be + able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it + can be included in this list if it requires initialization. The HpcList must be + self consistent. An HPC cannot control any of its parent buses. Only one HPC can + control a PCI bus. Because this list includes only root HPCs, no HPC in the list + can be a child of another HPC. This policy must be enforced by the + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for such + invalid conditions. The callee allocates the buffer HpcList + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[out] HpcCount The number of root HPCs that were returned. + @param[out] HpcList The list of root HPCs. HpcCount defines the number of + elements in this list. + + @retval EFI_SUCCESS HpcList was returned. + @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_ROOT_HPC_LIST)( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ); + +/** + Initializes one root Hot Plug Controller (HPC). This process may causes + initialization of its subordinate buses. + + This function initializes the specified HPC. At the end of initialization, + the hot-plug slots or sockets (controlled by this HPC) are powered and are + connected to the bus. All the necessary registers in the HPC are set up. For + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set + up are defined in the PCI Standard Hot Plug Controller and Subsystem + Specification. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC that is being initialized. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[in] Event The event that should be signaled when the HPC + initialization is complete. Set to NULL if the + caller wants to wait until the entire initialization + process is complete. + @param[out] HpcState The state of the HPC hardware. The state is + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED. + + @retval EFI_SUCCESS If Event is NULL, the specific HPC was successfully + initialized. If Event is not NULL, Event will be + signaled at a later time when initialization is complete. + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient + resources. + @retval EFI_INVALID_PARAMETER HpcState is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INITIALIZE_ROOT_HPC)( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ); + +/** + Returns the resource padding that is required by the PCI bus that is controlled + by the specified Hot Plug Controller (HPC). + + This function returns the resource padding that is required by the PCI bus that + is controlled by the specified HPC. This member function is called for all the + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This + function will be called before PCI resource allocation is completed. This function + must be called after all the root HPCs, with the possible exception of a + PCI-to-CardBus bridge, have completed initialization. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance. + @param[in] HpcDevicePath The device path to the HPC. + @param[in] HpcPciAddress The address of the HPC function on the PCI bus. + @param[in] HpcState The state of the HPC hardware. + @param[out] Padding The amount of resource padding that is required by the + PCI bus under the control of the specified HPC. + @param[out] Attributes Describes how padding is accounted for. The padding + is returned in the form of ACPI 2.0 resource descriptors. + + @retval EFI_SUCCESS The resource padding was successfully returned. + @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL + does not support the specified HPC. + @retval EFI_NOT_READY This function was called before HPC initialization + is complete. + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL. + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding + cannot be allocated due to insufficient resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_HOT_PLUG_PADDING)( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ); + +/// +/// This protocol provides the necessary functionality to initialize the +/// Hot Plug Controllers (HPCs) and the buses that they control. This protocol +/// also provides information regarding resource padding. +/// +struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL { + /// + /// Returns a list of root HPCs and the buses that they control. + /// + EFI_GET_ROOT_HPC_LIST GetRootHpcList; + + /// + /// Initializes the specified root HPC. + /// + EFI_INITIALIZE_ROOT_HPC InitializeRootHpc; + + /// + /// Returns the resource padding that is required by the HPC. + /// + EFI_GET_HOT_PLUG_PADDING GetResourcePadding; +}; + +extern EFI_GUID gEfiPciHotPlugInitProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugRequest.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugRequest.h new file mode 100644 index 0000000000..dff7f6e980 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciHotPlugRequest.h @@ -0,0 +1,164 @@ +/** @file + Provides services to notify the PCI bus driver that some events have happened + in a hot-plug controller (such as a PC Card socket, or PHPC), and to ask the + PCI bus driver to create or destroy handles for PCI-like devices. + + A hot-plug capable PCI bus driver should produce the EFI PCI Hot Plug Request + protocol. When a PCI device or a PCI-like device (for example, 32-bit PC Card) + is installed after PCI bus does the enumeration, the PCI bus driver can be + notified through this protocol. For example, when a 32-bit PC Card is inserted + into the PC Card socket, the PC Card bus driver can call interface of this + protocol to notify PCI bus driver to allocate resource and create handles for + this PC Card. + + The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL is installed by the PCI bus driver on a + separate handle when PCI bus driver starts up. There is only one instance in + the system. Any driver that wants to use this protocol must locate it globally. + The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL allows the driver of hot-plug controller, + for example, PC Card Bus driver, to notify PCI bus driver that an event has + happened in the hot-plug controller, and the PCI bus driver is requested to + create (add) or destroy (remove) handles for the specified PCI-like devices. + For example, when a 32-bit PC Card is inserted, this protocol interface will + be called with an add operation, and the PCI bus driver will enumerate and + start the devices inserted; when a 32-bit PC Card is removed, this protocol + interface will be called with a remove operation, and the PCI bus driver will + stop the devices and destroy their handles. The existence of this protocol + represents the capability of the PCI bus driver. If this protocol exists in + system, it means PCI bus driver is hot-plug capable, thus together with the + effort of PC Card bus driver, hot-plug of PC Card can be supported. Otherwise, + the hot-plug capability is not provided. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef __PCI_HOTPLUG_REQUEST_H_ +#define __PCI_HOTPLUG_REQUEST_H_ + +/// +/// Global ID for EFI_PCI_HOTPLUG_REQUEST_PROTOCOL +/// +#define EFI_PCI_HOTPLUG_REQUEST_PROTOCOL_GUID \ + { \ + 0x19cb87ab, 0x2cb9, 0x4665, {0x83, 0x60, 0xdd, 0xcf, 0x60, 0x54, 0xf7, 0x9d} \ + } + +/// +/// Forward declaration for EFI_PCI_HOTPLUG_REQUEST_PROTOCOL +/// +typedef struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL EFI_PCI_HOTPLUG_REQUEST_PROTOCOL; + +/// +/// Enumeration of PCI hot plug operations +/// +typedef enum { + /// + /// The PCI bus driver is requested to create handles for the specified devices. + /// An array of EFI_HANDLE is returned, with a NULL element marking the end of + /// the array. + /// + EfiPciHotPlugRequestAdd, + + /// + /// The PCI bus driver is requested to destroy handles for the specified devices. + /// + EfiPciHotplugRequestRemove +} EFI_PCI_HOTPLUG_OPERATION; + +/** + This function is used to notify PCI bus driver that some events happened in a + hot-plug controller, and the PCI bus driver is requested to start or stop + specified PCI-like devices. + + This function allows the PCI bus driver to be notified to act as requested when + a hot-plug event has happened on the hot-plug controller. Currently, the + operations include add operation and remove operation. If it is a add operation, + the PCI bus driver will enumerate, allocate resources for devices behind the + hot-plug controller, and create handle for the device specified by RemainingDevicePath. + The RemainingDevicePath is an optional parameter. If it is not NULL, only the + specified device is started; if it is NULL, all devices behind the hot-plug + controller are started. The newly created handles of PC Card functions are + returned in the ChildHandleBuffer, together with the number of child handle in + NumberOfChildren. If it is a remove operation, when NumberOfChildren contains + a non-zero value, child handles specified in ChildHandleBuffer are stopped and + destroyed; otherwise, PCI bus driver is notified to stop managing the controller + handle. + + @param[in] This A pointer to the EFI_PCI_HOTPLUG_REQUEST_PROTOCOL + instance. + @param[in] Operation The operation the PCI bus driver is requested + to make. + @param[in] Controller The handle of the hot-plug controller. + @param[in] RemainingDevicePath The remaining device path for the PCI-like + hot-plug device. It only contains device + path nodes behind the hot-plug controller. + It is an optional parameter and only valid + when the Operation is a add operation. If + it is NULL, all devices behind the PC Card + socket are started. + @param[in,out] NumberOfChildren The number of child handles. For an add + operation, it is an output parameter. For + a remove operation, it's an input parameter. + When it contains a non-zero value, children + handles specified in ChildHandleBuffer are + destroyed. Otherwise, PCI bus driver is + notified to stop managing the controller + handle. + @param[in,out] ChildHandleBuffer The buffer which contains the child handles. + For an add operation, it is an output + parameter and contains all newly created + child handles. For a remove operation, it + contains child handles to be destroyed when + NumberOfChildren contains a non-zero value. + It can be NULL when NumberOfChildren is 0. + It's the caller's responsibility to allocate + and free memory for this buffer. + + @retval EFI_SUCCESS The handles for the specified device have been + created or destroyed as requested, and for an + add operation, the new handles are returned in + ChildHandleBuffer. + @retval EFI_INVALID_PARAMETER Operation is not a legal value. + @retval EFI_INVALID_PARAMETER Controller is NULL or not a valid handle. + @retval EFI_INVALID_PARAMETER NumberOfChildren is NULL. + @retval EFI_INVALID_PARAMETER ChildHandleBuffer is NULL while Operation is + remove and NumberOfChildren contains a non-zero + value. + @retval EFI_INVALID_PARAMETER ChildHandleBuffer is NULL while Operation is add. + @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the + devices. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOTPLUG_REQUEST_NOTIFY)( + IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL *This, + IN EFI_PCI_HOTPLUG_OPERATION Operation, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL, + IN OUT UINT8 *NumberOfChildren, + IN OUT EFI_HANDLE *ChildHandleBuffer + ); + +/// +/// Provides services to notify PCI bus driver that some events have happened in +/// a hot-plug controller (for example, PC Card socket, or PHPC), and ask PCI bus +/// driver to create or destroy handles for the PCI-like devices. +/// +struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL { + /// + /// Notify the PCI bus driver that some events have happened in a hot-plug + /// controller (for example, PC Card socket, or PHPC), and ask PCI bus driver + /// to create or destroy handles for the PCI-like devices. See Section 0 for + /// a detailed description. + /// + EFI_PCI_HOTPLUG_REQUEST_NOTIFY Notify; +}; + +extern EFI_GUID gEfiPciHotPlugRequestProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciIo.h new file mode 100644 index 0000000000..420b8cba6f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciIo.h @@ -0,0 +1,551 @@ +/** @file + EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, + and DMA interfaces that a driver uses to access its PCI controller. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_IO_H__ +#define __PCI_IO_H__ + +/// +/// Global ID for the PCI I/O Protocol +/// +#define EFI_PCI_IO_PROTOCOL_GUID \ + { \ + 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \ + } + +typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL; + +/// +/// ******************************************************* +/// EFI_PCI_IO_PROTOCOL_WIDTH +/// ******************************************************* +/// +typedef enum { + EfiPciIoWidthUint8 = 0, + EfiPciIoWidthUint16, + EfiPciIoWidthUint32, + EfiPciIoWidthUint64, + EfiPciIoWidthFifoUint8, + EfiPciIoWidthFifoUint16, + EfiPciIoWidthFifoUint32, + EfiPciIoWidthFifoUint64, + EfiPciIoWidthFillUint8, + EfiPciIoWidthFillUint16, + EfiPciIoWidthFillUint32, + EfiPciIoWidthFillUint64, + EfiPciIoWidthMaximum +} EFI_PCI_IO_PROTOCOL_WIDTH; + +// +// Complete PCI address generater +// +#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged +#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles +#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined +#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header +#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header +#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header +#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached +#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range +#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device +#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR +#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC +#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode) +#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode) + +#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) +#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO) + +/// +/// ******************************************************* +/// EFI_PCI_IO_PROTOCOL_OPERATION +/// ******************************************************* +/// +typedef enum { + /// + /// A read operation from system memory by a bus master. + /// + EfiPciIoOperationBusMasterRead, + /// + /// A write operation from system memory by a bus master. + /// + EfiPciIoOperationBusMasterWrite, + /// + /// Provides both read and write access to system memory by both the processor and a + /// bus master. The buffer is coherent from both the processor's and the bus master's point of view. + /// + EfiPciIoOperationBusMasterCommonBuffer, + EfiPciIoOperationMaximum +} EFI_PCI_IO_PROTOCOL_OPERATION; + +/// +/// ******************************************************* +/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION +/// ******************************************************* +/// +typedef enum { + /// + /// Retrieve the PCI controller's current attributes, and return them in Result. + /// + EfiPciIoAttributeOperationGet, + /// + /// Set the PCI controller's current attributes to Attributes. + /// + EfiPciIoAttributeOperationSet, + /// + /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller. + /// + EfiPciIoAttributeOperationEnable, + /// + /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller. + /// + EfiPciIoAttributeOperationDisable, + /// + /// Retrieve the PCI controller's supported attributes, and return them in Result. + /// + EfiPciIoAttributeOperationSupported, + EfiPciIoAttributeOperationMaximum +} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION; + +/** + Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is + satisfied or after a defined duration. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Width Signifies the width of the memory or I/O operations. + @param BarIndex The BAR index of the standard PCI Configuration header to use as the + base address for the memory operation to perform. + @param Offset The offset within the selected BAR to start the memory operation. + @param Mask Mask used for the polling criteria. + @param Value The comparison value used for the polling exit criteria. + @param Delay The number of 100 ns units to poll. + @param Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. + @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +/** + Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Width Signifies the width of the memory or I/O operations. + @param BarIndex The BAR index of the standard PCI Configuration header to use as the + base address for the memory or I/O operation to perform. + @param Offset The offset within the selected BAR to start the memory or I/O operation. + @param Count The number of memory or I/O operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI controller. + @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI BAR specified by BarIndex. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +typedef struct { + /// + /// Read PCI controller registers in the PCI memory or I/O space. + /// + EFI_PCI_IO_PROTOCOL_IO_MEM Read; + /// + /// Write PCI controller registers in the PCI memory or I/O space. + /// + EFI_PCI_IO_PROTOCOL_IO_MEM Write; +} EFI_PCI_IO_PROTOCOL_ACCESS; + +/** + Enable a PCI driver to access PCI controller registers in PCI configuration space. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Width Signifies the width of the memory operations. + @param Offset The offset within the PCI configuration space for the PCI controller. + @param Count The number of PCI configuration operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + + @retval EFI_SUCCESS The data was read from or written to the PCI controller. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +typedef struct { + /// + /// Read PCI controller registers in PCI configuration space. + /// + EFI_PCI_IO_PROTOCOL_CONFIG Read; + /// + /// Write PCI controller registers in PCI configuration space. + /// + EFI_PCI_IO_PROTOCOL_CONFIG Write; +} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; + +/** + Enables a PCI driver to copy one region of PCI memory space to another region of PCI + memory space. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Width Signifies the width of the memory operations. + @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the + base address for the memory operation to perform. + @param DestOffset The destination offset within the BAR specified by DestBarIndex to + start the memory writes for the copy operation. + @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the + base address for the memory operation to perform. + @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start + the memory reads for the copy operation. + @param Count The number of memory operations to perform. Bytes moved is Width + size * Count, starting at DestOffset and SrcOffset. + + @retval EFI_SUCCESS The data was copied from one memory region to another memory region. + @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller. + @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller. + @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count + is not valid for the PCI BAR specified by DestBarIndex. + @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is + not valid for the PCI BAR specified by SrcBarIndex. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 DestBarIndex, + IN UINT64 DestOffset, + IN UINT8 SrcBarIndex, + IN UINT64 SrcOffset, + IN UINTN Count + ); + +/** + Provides the PCI controller-specific addresses needed to access system memory. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Operation Indicates if the bus master is going to read or write to system memory. + @param HostAddress The system memory address to map to the PCI controller. + @param NumberOfBytes On input the number of bytes to map. On output the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus master PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)( + IN EFI_PCI_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer + or EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages + was not allocated with AllocateBuffer(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ); + +/** + Flushes all PCI posted write transactions from a PCI host bridge to system memory. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host + bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI + host bridge due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)( + IN EFI_PCI_IO_PROTOCOL *This + ); + +/** + Retrieves this PCI controller's current PCI bus number, device number, and function number. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param SegmentNumber The PCI controller's current PCI segment number. + @param BusNumber The PCI controller's current PCI bus number. + @param DeviceNumber The PCI controller's current PCI device number. + @param FunctionNumber The PCI controller's current PCI function number. + + @retval EFI_SUCCESS The PCI controller location was returned. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)( + IN EFI_PCI_IO_PROTOCOL *This, + OUT UINTN *SegmentNumber, + OUT UINTN *BusNumber, + OUT UINTN *DeviceNumber, + OUT UINTN *FunctionNumber + ); + +/** + Performs an operation on the attributes that this PCI controller supports. The operations include + getting the set of supported attributes, retrieving the current attributes, setting the current + attributes, enabling attributes, and disabling attributes. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Operation The operation to perform on the attributes for this PCI controller. + @param Attributes The mask of attributes that are used for Set, Enable, and Disable + operations. + @param Result A pointer to the result mask of attributes that are returned for the Get + and Supported operations. + + @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_UNSUPPORTED one or more of the bits set in + Attributes are not supported by this PCI controller or one of + its parent bridges when Operation is Set, Enable or Disable. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, + IN UINT64 Attributes, + OUT UINT64 *Result OPTIONAL + ); + +/** + Gets the attributes that this PCI controller supports setting on a BAR using + SetBarAttributes(), and retrieves the list of resource descriptors for a BAR. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param BarIndex The BAR index of the standard PCI Configuration header to use as the + base address for resource range. The legal range for this field is 0..5. + @param Supports A pointer to the mask of attributes that this PCI controller supports + setting for this BAR with SetBarAttributes(). + @param Resources A pointer to the resource descriptors that describe the current + configuration of this BAR of the PCI controller. + + @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI + controller supports are returned in Supports. If Resources + is not NULL, then the resource descriptors that the PCI + controller is currently using are returned in Resources. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. + @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate + Resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT8 BarIndex, + OUT UINT64 *Supports, OPTIONAL + OUT VOID **Resources OPTIONAL + ); + +/** + Sets the attributes for a range of a BAR on a PCI controller. + + @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param Attributes The mask of attributes to set for the resource range specified by + BarIndex, Offset, and Length. + @param BarIndex The BAR index of the standard PCI Configuration header to use as the + base address for resource range. The legal range for this field is 0..5. + @param Offset A pointer to the BAR relative base address of the resource range to be + modified by the attributes specified by Attributes. + @param Length A pointer to the length of the resource range to be modified by the + attributes specified by Attributes. + + @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource + range specified by BarIndex, Offset, and Length were + set on the PCI controller, and the actual resource range is returned + in Offset and Length. + @retval EFI_INVALID_PARAMETER Offset or Length is NULL. + @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the + resource range specified by BarIndex, Offset, and + Length. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN UINT8 BarIndex, + IN OUT UINT64 *Offset, + IN OUT UINT64 *Length + ); + +/// +/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, +/// and DMA interfaces used to abstract accesses to PCI controllers. +/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. +/// A device driver that wishes to manage a PCI controller in a system will have to +/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. +/// +struct _EFI_PCI_IO_PROTOCOL { + EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem; + EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo; + EFI_PCI_IO_PROTOCOL_ACCESS Mem; + EFI_PCI_IO_PROTOCOL_ACCESS Io; + EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; + EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem; + EFI_PCI_IO_PROTOCOL_MAP Map; + EFI_PCI_IO_PROTOCOL_UNMAP Unmap; + EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer; + EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer; + EFI_PCI_IO_PROTOCOL_FLUSH Flush; + EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation; + EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes; + EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes; + EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes; + + /// + /// The size, in bytes, of the ROM image. + /// + UINT64 RomSize; + + /// + /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible + /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. + /// The contents of this buffer are either from the PCI option ROM that can be accessed + /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. + /// The Attributes() function can be used to determine from which of these two sources + /// the RomImage buffer was initialized. + /// + VOID *RomImage; +}; + +extern EFI_GUID gEfiPciIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciOverride.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciOverride.h new file mode 100644 index 0000000000..e5b797177f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciOverride.h @@ -0,0 +1,40 @@ +/** @file + This file declares EFI PCI Override protocol which provides the interface between + the PCI bus driver/PCI Host Bridge Resource Allocation driver and an implementation's + driver to describe the unique features of a platform. + This protocol is optional. + + Copyright (c) 2009, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef _PCI_OVERRIDE_H_ +#define _PCI_OVERRIDE_H_ + +/// +/// EFI_PCI_OVERRIDE_PROTOCOL has the same structure with EFI_PCI_PLATFORM_PROTOCOL +/// +#include + +/// +/// Global ID for the EFI_PCI_OVERRIDE_PROTOCOL +/// +#define EFI_PCI_OVERRIDE_GUID \ + { \ + 0xb5b35764, 0x460c, 0x4a06, {0x99, 0xfc, 0x77, 0xa1, 0x7c, 0x1b, 0x5c, 0xeb} \ + } + +/// +/// Declaration for EFI_PCI_OVERRIDE_PROTOCOL +/// +typedef EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_OVERRIDE_PROTOCOL; + + +extern EFI_GUID gEfiPciOverrideProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciPlatform.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciPlatform.h new file mode 100644 index 0000000000..1f514e2d77 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciPlatform.h @@ -0,0 +1,338 @@ +/** @file + This file declares PlatfromOpRom protocols that provide the interface between + the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific + driver to describe the unique features of a platform. + This protocol is optional. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1.2 + Volume 5: Standards + +**/ + +#ifndef _PCI_PLATFORM_H_ +#define _PCI_PLATFORM_H_ + +/// +/// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL uses +/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE. +/// +#include + +/// +/// Global ID for the EFI_PCI_PLATFORM_PROTOCOL. +/// +#define EFI_PCI_PLATFORM_PROTOCOL_GUID \ + { \ + 0x7d75280, 0x27d4, 0x4d69, {0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41} \ + } + +/// +/// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL. +/// +typedef struct _EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_PLATFORM_PROTOCOL; + +/// +/// EFI_PCI_PLATFORM_POLICY that is a bitmask with the following legal combinations: +/// - EFI_RESERVE_NONE_IO_ALIAS:
+/// Does not set aside either ISA or VGA I/O resources during PCI +/// enumeration. By using this selection, the platform indicates that it does +/// not want to support a PCI device that requires ISA or legacy VGA +/// resources. If a PCI device driver asks for these resources, the request +/// will be turned down. +/// - EFI_RESERVE_ISA_IO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:
+/// Sets aside the ISA I/O range and all the aliases during PCI +/// enumeration. VGA I/O ranges and aliases are included in ISA alias +/// ranges. In this scheme, seventy-five percent of the I/O space remains unused. +/// By using this selection, the platform indicates that it wants to support +/// PCI devices that require the following, at the cost of wasted I/O space: +/// ISA range and its aliases +/// Legacy VGA range and its aliases +/// The PCI bus driver will not allocate I/O addresses out of the ISA I/O +/// range and its aliases. The following are the ISA I/O ranges: +/// - n100..n3FF +/// - n500..n7FF +/// - n900..nBFF +/// - nD00..nFFF +/// +/// In this case, the PCI bus driver will ask the PCI host bridge driver for +/// larger I/O ranges. The PCI host bridge driver is not aware of the ISA +/// aliasing policy and merely attempts to allocate the requested ranges. +/// The first device that requests the legacy VGA range will get all the +/// legacy VGA range plus its aliased addresses forwarded to it. The first +/// device that requests the legacy ISA range will get all the legacy ISA +/// range, plus its aliased addresses, forwarded to it. +/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_ALIAS:
+/// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration +/// and the aliases of the VGA I/O ranges. By using this selection, the +/// platform indicates that it will support VGA devices that require VGA +/// ranges, including those that require VGA aliases. The platform further +/// wants to support non-VGA devices that ask for the ISA range (0x100 - +/// 3FF), but not if it also asks for the ISA aliases. The PCI bus driver will +/// not allocate I/O addresses out of the legacy ISA I/O range (0x100 - +/// 0x3FF) range or the aliases of the VGA I/O range. If a PCI device +/// driver asks for the ISA I/O ranges, including aliases, the request will be +/// turned down. The first device that requests the legacy VGA range will +/// get all the legacy VGA range plus its aliased addresses forwarded to +/// it. When the legacy VGA device asks for legacy VGA ranges and its +/// aliases, all the upstream PCI-to-PCI bridges must be set up to perform +/// 10-bit decode on legacy VGA ranges. To prevent two bridges from +/// positively decoding the same address, all PCI-to-PCI bridges that are +/// peers to this bridge will have to be set up to not decode ISA aliased +/// ranges. In that case, all the devices behind the peer bridges can +/// occupy only I/O addresses that are not ISA aliases. This is a limitation +/// of PCI-to-PCI bridges and is described in the white paper PCI-to-PCI +/// Bridges and Card Bus Controllers on Windows 2000, Windows XP, +/// and Windows Server 2003. The PCI enumeration process must be +/// cognizant of this restriction. +/// - EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS:
+/// Sets aside the ISA I/O range (0x100 - 0x3FF) during PCI enumeration. +/// VGA I/O ranges are included in the ISA range. By using this selection, +/// the platform indicates that it wants to support PCI devices that require +/// the ISA range and legacy VGA range, but it does not want to support +/// devices that require ISA alias ranges or VGA alias ranges. The PCI +/// bus driver will not allocate I/O addresses out of the legacy ISA I/O +/// range (0x100-0x3FF). If a PCI device driver asks for the ISA I/O +/// ranges, including aliases, the request will be turned down. By using +/// this selection, the platform indicates that it will support VGA devices +/// that require VGA ranges, but it will not support VGA devices that +/// require VGA aliases. To truly support 16-bit VGA decode, all the PCIto- +/// PCI bridges that are upstream to a VGA device, as well as +/// upstream to the parent PCI root bridge, must support 16-bit VGA I/O +/// decode. See the PCI-to-PCI Bridge Architecture Specification for +/// information regarding the 16-bit VGA decode support. This +/// requirement must hold true for every VGA device in the system. If any +/// of these bridges does not support 16-bit VGA decode, it will positively +/// decode all the aliases of the VGA I/O ranges and this selection must +/// be treated like EFI_RESERVE_ISA_IO_NO_ALIAS | +/// EFI_RESERVE_VGA_IO_ALIAS. +/// +typedef UINT32 EFI_PCI_PLATFORM_POLICY; + +/// +/// Does not set aside either ISA or VGA I/O resources during PCI +/// enumeration. +/// +#define EFI_RESERVE_NONE_IO_ALIAS 0x0000 + +/// +/// Sets aside ISA I/O range and all aliases: +/// - n100..n3FF +/// - n500..n7FF +/// - n900..nBFF +/// - nD00..nFFF. +/// +#define EFI_RESERVE_ISA_IO_ALIAS 0x0001 + +/// +/// Sets aside ISA I/O range 0x100-0x3FF. +/// +#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002 + +/// +/// Sets aside VGA I/O ranges and all aliases. +/// +#define EFI_RESERVE_VGA_IO_ALIAS 0x0004 + +/// +/// Sets aside VGA I/O ranges +/// +#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008 + +/// +/// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute +/// platform-specific code. +/// +typedef enum { + /// + /// The phase that indicates the entry point to the PCI Bus Notify phase. This + /// platform hook is called before the PCI bus driver calls the + /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver. + /// + BeforePciHostBridge = 0, + /// + /// The phase that indicates the entry point to the PCI Bus Notify phase. This + /// platform hook is called before the PCI bus driver calls the + /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL driver. + /// + ChipsetEntry = 0, + /// + /// The phase that indicates the exit point to the Chipset Notify phase before + /// returning to the PCI Bus Driver Notify phase. This platform hook is called after + /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + /// driver. + /// + AfterPciHostBridge = 1, + /// + /// The phase that indicates the exit point to the Chipset Notify phase before + /// returning to the PCI Bus Driver Notify phase. This platform hook is called after + /// the PCI bus driver calls the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + /// driver. + /// + ChipsetExit = 1, + MaximumChipsetPhase +} EFI_PCI_EXECUTION_PHASE; + +typedef EFI_PCI_EXECUTION_PHASE EFI_PCI_CHIPSET_EXECUTION_PHASE; + +/** + The notification from the PCI bus enumerator to the platform that it is + about to enter a certain phase during the enumeration process. + + The PlatformNotify() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Eight notification points are defined at this time. More synchronization points + may be added as required in the future. The PCI bus driver calls the platform driver + twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol + driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol + driver has been notified. + This member function may not perform any error checking on the input parameters. It + also does not return any error codes. If this member function detects any error condition, + it needs to handle those errors on its own because there is no way to surface any + errors to the caller. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY)( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + The notification from the PCI bus enumerator to the platform for each PCI + controller at several predefined points during PCI controller initialization. + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param[in] HostBridge The associated PCI host bridge handle. + @param[in] RootBridge The associated PCI root bridge handle. + @param[in] PciAddress The address of the PCI device on the PCI bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER)( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + Retrieves the platform policy regarding enumeration. + + The GetPlatformPolicy() function retrieves the platform policy regarding PCI + enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol + driver can call this member function to retrieve the policy. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param[out] PciPolicy The platform policy with respect to VGA and ISA aliasing. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER PciPolicy is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY)( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +/** + Gets the PCI device's option ROM from a platform-specific location. + + The GetPciRom() function gets the PCI device's option ROM from a platform-specific location. + The option ROM will be loaded into memory. This member function is used to return an image + that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option + ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return + option ROM images for embedded controllers. Option ROMs for embedded controllers are typically + stored in platform-specific storage, and this member function can retrieve it from that storage + and return it to the PCI bus driver. The PCI bus driver will call this member function before + scanning the ROM that is attached to any controller, which allows a platform to specify a ROM + image that is different from the ROM image on a PCI card. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param[in] PciHandle The handle of the PCI device. + @param[out] RomImage If the call succeeds, the pointer to the pointer to the option ROM image. + Otherwise, this field is undefined. The memory for RomImage is allocated + by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using the EFI Boot Service AllocatePool(). + It is the caller's responsibility to free the memory using the EFI Boot Service + FreePool(), when the caller is done with the option ROM. + @param[out] RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise, + this field is undefined. + + @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this device. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM)( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ); + +/// +/// This protocol provides the interface between the PCI bus driver/PCI Host +/// Bridge Resource Allocation driver and a platform-specific driver to describe +/// the unique features of a platform. +/// +struct _EFI_PCI_PLATFORM_PROTOCOL { + /// + /// The notification from the PCI bus enumerator to the platform that it is about to + /// enter a certain phase during the enumeration process. + /// + EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify; + /// + /// The notification from the PCI bus enumerator to the platform for each PCI + /// controller at several predefined points during PCI controller initialization. + /// + EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController; + /// + /// Retrieves the platform policy regarding enumeration. + /// + EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy; + /// + /// Gets the PCI device's option ROM from a platform-specific location. + /// + EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom; +}; + +extern EFI_GUID gEfiPciPlatformProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciRootBridgeIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciRootBridgeIo.h new file mode 100644 index 0000000000..dffb8a9dee --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PciRootBridgeIo.h @@ -0,0 +1,436 @@ +/** @file + PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification. + + PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, + and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform + defferent types of bus mastering DMA. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PCI_ROOT_BRIDGE_IO_H__ +#define __PCI_ROOT_BRIDGE_IO_H__ + +#include + +#define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \ + { \ + 0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL; + +/// +/// ******************************************************* +/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH +/// ******************************************************* +/// +typedef enum { + EfiPciWidthUint8, + EfiPciWidthUint16, + EfiPciWidthUint32, + EfiPciWidthUint64, + EfiPciWidthFifoUint8, + EfiPciWidthFifoUint16, + EfiPciWidthFifoUint32, + EfiPciWidthFifoUint64, + EfiPciWidthFillUint8, + EfiPciWidthFillUint16, + EfiPciWidthFillUint32, + EfiPciWidthFillUint64, + EfiPciWidthMaximum +} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH; + +/// +/// ******************************************************* +/// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION +/// ******************************************************* +/// +typedef enum { + /// + /// A read operation from system memory by a bus master that is not capable of producing + /// PCI dual address cycles. + /// + EfiPciOperationBusMasterRead, + /// + /// A write operation from system memory by a bus master that is not capable of producing + /// PCI dual address cycles. + /// + EfiPciOperationBusMasterWrite, + /// + /// Provides both read and write access to system memory by both the processor and a bus + /// master that is not capable of producing PCI dual address cycles. + /// + EfiPciOperationBusMasterCommonBuffer, + /// + /// A read operation from system memory by a bus master that is capable of producing PCI + /// dual address cycles. + /// + EfiPciOperationBusMasterRead64, + /// + /// A write operation to system memory by a bus master that is capable of producing PCI + /// dual address cycles. + /// + EfiPciOperationBusMasterWrite64, + /// + /// Provides both read and write access to system memory by both the processor and a bus + /// master that is capable of producing PCI dual address cycles. + /// + EfiPciOperationBusMasterCommonBuffer64, + EfiPciOperationMaximum +} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION; + +#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 +#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002 +#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004 +#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008 +#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010 +#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 +#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 +#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 +#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800 +#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000 +#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 +#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000 +#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 +#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000 + +#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) + +#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER) + +#define EFI_PCI_ADDRESS(bus, dev, func, reg) \ + (UINT64) ( \ + (((UINTN) bus) << 24) | \ + (((UINTN) dev) << 16) | \ + (((UINTN) func) << 8) | \ + (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32)))) + +typedef struct { + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT32 ExtendedRegister; +} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS; + +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is + satisfied or after a defined duration. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory or I/O operations. + @param Address The base address of the memory or I/O operations. + @param Mask Mask used for the polling criteria. + @param Value The comparison value used for the polling exit criteria. + @param Delay The number of 100 ns units to poll. + @param Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +typedef struct { + /// + /// Read PCI controller registers in the PCI root bridge memory space. + /// + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read; + /// + /// Write PCI controller registers in the PCI root bridge memory space. + /// + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write; +} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS; + +/** + Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI + root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param Width Signifies the width of the memory operations. + @param DestAddress The destination address of the memory operation. + @param SrcAddress The source address of the memory operation. + @param Count The number of memory operations to perform. + + @retval EFI_SUCCESS The data was copied from one memory region to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +/** + Provides the PCI controller-specific addresses required to access system memory from a + DMA bus master. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Operation Indicates if the bus master is going to read or write to system memory. + @param HostAddress The system memory address to map to the PCI controller. + @param NumberOfBytes On input the number of bytes to map. On output the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus master PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or + EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are + MEMORY_WRITE_COMBINE and MEMORY_CACHED. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages + was not allocated with AllocateBuffer(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ); + +/** + Flushes all PCI posted write transactions from a PCI host bridge to system memory. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host + bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI + host bridge due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +/** + Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the + attributes that a PCI root bridge is currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supports A pointer to the mask of attributes that this PCI root bridge supports + setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root bridge is currently + using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root + bridge supports is returned in Supports. If Attributes is + not NULL, then the attributes that the PCI root bridge is currently + using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supports, + OUT UINT64 *Attributes + ); + +/** + Sets attributes for a resource range on a PCI root bridge. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Attributes The mask of attributes to set. + @param ResourceBase A pointer to the base address of the resource range to be modified by the + attributes specified by Attributes. + @param ResourceLength A pointer to the length of the resource range to be modified by the + attributes specified by Attributes. + + @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource + range specified by ResourceBase and ResourceLength + were set on the PCI root bridge, and the actual resource range is + returned in ResuourceBase and ResourceLength. + @retval EFI_UNSUPPORTED A bit is set in Attributes that is not supported by the PCI Root + Bridge. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the + resource range specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +/** + Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI + resource descriptors. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Resources A pointer to the resource descriptors that describe the current + configuration of this PCI root bridge. + + @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in + Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be + retrieved. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +/// +/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are +/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. +/// +struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL { + /// + /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member. + /// + EFI_HANDLE ParentHandle; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration; + + /// + /// The segment number that this PCI root bridge resides. + /// + UINT32 SegmentNumber; +}; + +extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcd.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcd.h new file mode 100644 index 0000000000..b409ba614f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcd.h @@ -0,0 +1,418 @@ +/** @file + Platform Configuration Database (PCD) Protocol defined in PI 1.2 Vol3 + + A platform database that contains a variety of current platform settings or + directives that can be accessed by a driver or application. + PI PCD protocol only provide the accessing interfaces for Dynamic-Ex type PCD. + + Callers to this protocol must be at a TPL_APPLICATION task priority level. + This is the base PCD service API that provides an abstraction for accessing configuration content in + the platform. It a seamless mechanism for extracting information regardless of where the + information is stored (such as in Read-only data, or an EFI Variable). + This protocol allows access to data through size-granular APIs and provides a mechanism for a + firmware component to monitor specific settings and be alerted when a setting is changed. + + Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.2 Vol 3. +**/ + +#ifndef __PI_PCD_H__ +#define __PI_PCD_H__ + +extern EFI_GUID gEfiPcdProtocolGuid; + +#define EFI_PCD_PROTOCOL_GUID \ + { 0x13a3f0f6, 0x264a, 0x3ef0, { 0xf2, 0xe0, 0xde, 0xc5, 0x12, 0x34, 0x2f, 0x34 } } + +#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0) + +/** + SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. SetSku() is + normally called only once by the system. + For each item (token), the database can hold a single value that applies to all SKUs, or multiple + values, where each value is associated with a specific SKU Id. Items with multiple, SKU-specific + values are called SKU enabled. + The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255. For tokens that are + not SKU enabled, the system ignores any set SKU Id and works with the single value for that token. + For SKU-enabled tokens, the system will use the SKU Id set by the last call to SetSku(). If no SKU + Id is set or the currently set SKU Id isn't valid for the specified token, the system uses the default + SKU Id. If the system attempts to use the default SKU Id and no value has been set for that Id, the + results are unpredictable. + + @param[in] SkuId The SKU value to set. +**/ +typedef +VOID +(EFIAPI *EFI_PCD_PROTOCOL_SET_SKU)( + IN UINTN SkuId +); + +/** + Retrieves an 8-bit value for a given PCD token. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return 8-bit value for a given PCD token. +**/ +typedef +UINT8 +(EFIAPI *EFI_PCD_PROTOCOL_GET_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current word-sized value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return word-sized value for a given PCD token. +**/ +typedef +UINT16 +(EFIAPI *EFI_PCD_PROTOCOL_GET_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current 32-bit sized value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return 32-bit value for a given PCD token. +**/ +typedef +UINT32 +(EFIAPI *EFI_PCD_PROTOCOL_GET_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the 64-bit sized value for a PCD token number. + If the TokenNumber is invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return 64-bit value for a given PCD token. + +**/ +typedef +UINT64 +(EFIAPI *EFI_PCD_PROTOCOL_GET_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current pointer to the value for a PCD token number. Do not make any assumptions + about the alignment of the pointer that is returned by this function call. If the TokenNumber is + invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return pointer to a value for a given PCD token. +**/ +typedef +VOID * +(EFIAPI *EFI_PCD_PROTOCOL_GET_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current BOOLEAN-sized value for a PCD token number. If the TokenNumber is + invalid, the results are unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return Boolean value for a given PCD token. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_PCD_PROTOCOL_GET_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are + unpredictable. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + + @return the size of the value for a given PCD token. +**/ +typedef +UINTN +(EFIAPI *EFI_PCD_PROTOCOL_GET_SIZE)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber +); + +/** + Sets an 8-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_8)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT8 Value +); + +/** + Sets an 16-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_16)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT16 Value +); + +/** + Sets an 32-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_32)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT32 Value +); + +/** + Sets an 64-bit value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_64)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN UINT64 Value +); + +/** + Sets a value of a specified size for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] SizeOfValue The length of the value being set for the PCD token. If too large of a length is + specified, upon return from this function the value of SizeOfValue will + reflect the maximum size for the PCD token. + @param[in] Buffer A pointer to the buffer containing the value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_POINTER)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN OUT UINTN *SizeOfValue, + IN VOID *Buffer +); + +/** + Sets a Boolean value for a given PCD token. + + When the PCD service sets a value, it will check to ensure that the size of the value being set is + compatible with the Token's existing definition. If it is not, an error will be returned. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[in] Value The value to set for the PCD token. + + @retval EFI_SUCCESS The PCD service has set the value requested + @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data being set was + incompatible with a call to this function. Use GetSizeEx() to + retrieve the size of the target data. + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_SET_BOOLEAN)( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + IN BOOLEAN Value +); + +typedef +VOID +(EFIAPI *EFI_PCD_PROTOCOL_CALLBACK)( + IN EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN OUT VOID *TokenData, + IN UINTN TokenDataSize +); + +/** + Specifies a function to be called anytime the value of a designated token is changed. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackToken The PCD token number to monitor. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_CALLBACK_ON_SET)( + IN CONST EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN EFI_PCD_PROTOCOL_CALLBACK CallBackFunction +); + +/** + Cancels a callback function that was set through a previous call to the CallBackOnSet function. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] CallBackToken The PCD token number to monitor. + @param[in] CallBackFunction The function prototype called when the value associated with the CallBackToken is set. + + @retval EFI_SUCCESS The PCD service has successfully established a call event for the CallBackToken requested. + @retval EFI_NOT_FOUND The PCD service could not find the referenced token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_CANCEL_CALLBACK)( + IN CONST EFI_GUID *Guid OPTIONAL, + IN UINTN CallBackToken, + IN EFI_PCD_PROTOCOL_CALLBACK CallBackFunction +); + +/** + Gets the next valid token number in a given namespace. This is useful since the PCD infrastructure + contains a sparse list of token numbers, and one cannot a priori know what token numbers are valid + in the database. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to retrieve the next token. + @param[in] TokenNumber A pointer to the PCD token number to use to find the subsequent token number. To + retrieve the "first" token, have the pointer reference a TokenNumber value of 0. + @retval EFI_SUCCESS The PCD service has retrieved the value requested + @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN)( + IN CONST EFI_GUID *Guid, OPTIONAL + IN UINTN *TokenNumber +); + +/** + Gets the next valid token namespace for a given namespace. This is useful to traverse the valid + token namespaces on a platform. + + @param[in, out] Guid An indirect pointer to EFI_GUID. On input it designates a known token namespace + from which the search will start. On output, it designates the next valid token + namespace on the platform. If *Guid is NULL, then the GUID of the first token + space of the current platform is returned. If the search cannot locate the next valid + token namespace, an error is returned and the value of *Guid is undefined. + + @retval EFI_SUCCESS The PCD service retrieved the value requested. + @retval EFI_NOT_FOUND The PCD service could not find the next valid token namespace. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE)( + IN OUT CONST EFI_GUID **Guid +); + +typedef struct _EFI_PCD_PROTOCOL { + EFI_PCD_PROTOCOL_SET_SKU SetSku; + EFI_PCD_PROTOCOL_GET_8 Get8; + EFI_PCD_PROTOCOL_GET_16 Get16; + EFI_PCD_PROTOCOL_GET_32 Get32; + EFI_PCD_PROTOCOL_GET_64 Get64; + EFI_PCD_PROTOCOL_GET_POINTER GetPtr; + EFI_PCD_PROTOCOL_GET_BOOLEAN GetBool; + EFI_PCD_PROTOCOL_GET_SIZE GetSize; + EFI_PCD_PROTOCOL_SET_8 Set8; + EFI_PCD_PROTOCOL_SET_16 Set16; + EFI_PCD_PROTOCOL_SET_32 Set32; + EFI_PCD_PROTOCOL_SET_64 Set64; + EFI_PCD_PROTOCOL_SET_POINTER SetPtr; + EFI_PCD_PROTOCOL_SET_BOOLEAN SetBool; + EFI_PCD_PROTOCOL_CALLBACK_ON_SET CallbackOnSet; + EFI_PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback; + EFI_PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken; + EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE GetNextTokenSpace; +} EFI_PCD_PROTOCOL; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcdInfo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcdInfo.h new file mode 100644 index 0000000000..b8c3133122 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PiPcdInfo.h @@ -0,0 +1,77 @@ +/** @file + Platform Configuration Database (PCD) Info Protocol defined in PI 1.2.1 Vol3. + + The protocol that provides additional information about items that reside in the PCD database. + + Copyright (c) 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + PI Version 1.2.1 Vol 3. +**/ + +#ifndef __PI_PCD_INFO_H__ +#define __PI_PCD_INFO_H__ + +extern EFI_GUID gEfiGetPcdInfoProtocolGuid; + +#define EFI_GET_PCD_INFO_PROTOCOL_GUID \ + { 0xfd0f4478, 0xefd, 0x461d, { 0xba, 0x2d, 0xe5, 0x8c, 0x45, 0xfd, 0x5f, 0x5e } } + +/// +/// The forward declaration for EFI_GET_PCD_INFO_PROTOCOL. +/// +typedef struct _EFI_GET_PCD_INFO_PROTOCOL EFI_GET_PCD_INFO_PROTOCOL; + +/** + Retrieve additional information associated with a PCD token. + + This includes information such as the type of value the TokenNumber is associated with as well as possible + human readable name that is associated with the token. + + @param[in] Guid The 128-bit unique value that designates the namespace from which to extract the value. + @param[in] TokenNumber The PCD token number. + @param[out] PcdInfo The returned information associated with the requested TokenNumber. + + @retval EFI_SUCCESS The PCD information was returned successfully + @retval EFI_NOT_FOUND The PCD service could not find the requested token number. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_INFO) ( + IN CONST EFI_GUID *Guid, + IN UINTN TokenNumber, + OUT EFI_PCD_INFO *PcdInfo +); + +/** + Retrieve the currently set SKU Id. + + @return The currently set SKU Id. If the platform has not set at a SKU Id, then the + default SKU Id value of 0 is returned. If the platform has set a SKU Id, then the currently set SKU + Id is returned. +**/ +typedef +UINTN +(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_SKU) ( + VOID +); + +/// +/// Callers to this protocol must be at a TPL_APPLICATION task priority level. +/// This is the PCD service to use when querying for some additional data that can be contained in the +/// PCD database. +/// +struct _EFI_GET_PCD_INFO_PROTOCOL { + /// + /// Retrieve additional information associated with a PCD. + /// + EFI_GET_PCD_INFO_PROTOCOL_GET_INFO GetInfo; + /// + /// Retrieve the currently set SKU Id. + /// + EFI_GET_PCD_INFO_PROTOCOL_GET_SKU GetSku; +}; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pkcs7Verify.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pkcs7Verify.h new file mode 100644 index 0000000000..5cf1ffda13 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Pkcs7Verify.h @@ -0,0 +1,223 @@ +/** @file + EFI_PKCS7_VERIFY_PROTOCOL as defined in UEFI 2.5. + The EFI_PKCS7_VERIFY_PROTOCOL is used to verify data signed using PKCS#7 + formatted authentication. The PKCS#7 data to be verified must be binary + DER encoded. + PKCS#7 is a general-purpose cryptographic standard (defined by RFC2315, + available at http://tools.ietf.org/html/rfc2315). + +Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_PKCS7_VERIFY_PROTOCOL_H__ +#define __EFI_PKCS7_VERIFY_PROTOCOL_H__ + +#include + +/// +/// Global ID for the PKCS7 Verification Protocol +/// +#define EFI_PKCS7_VERIFY_PROTOCOL_GUID \ + { \ + 0x47889fb2, 0xd671, 0x4fab, {0xa0, 0xca, 0xdf, 0x0e, 0x44, 0xdf, 0x70, 0xd6 } \ + } + +typedef struct _EFI_PKCS7_VERIFY_PROTOCOL EFI_PKCS7_VERIFY_PROTOCOL; + + +/** + Processes a buffer containing binary DER-encoded PKCS7 signature. + The signed data content may be embedded within the buffer or separated. Funtion + verifies the signature of the content is valid and signing certificate was not + revoked and is contained within a list of trusted signers. + + @param[in] This Pointer to EFI_PKCS7_VERIFY_PROTOCOL instance. + @param[in] SignedData Points to buffer containing ASN.1 DER-encoded PKCS7 + signature. + @param[in] SignedDataSize The size of SignedData buffer in bytes. + @param[in] InData In case of detached signature, InData points to + buffer containing the raw message data previously + signed and to be verified by function. In case of + SignedData containing embedded data, InData must be + NULL. + @param[in] InDataSize When InData is used, the size of InData buffer in + bytes. When InData is NULL. This parameter must be + 0. + @param[in] AllowedDb Pointer to a list of pointers to EFI_SIGNATURE_LIST + structures. The list is terminated by a null + pointer. The EFI_SIGNATURE_LIST structures contain + lists of X.509 certificates of approved signers. + Function recognizes signer certificates of type + EFI_CERT_X509_GUID. Any hash certificate in AllowedDb + list is ignored by this function. Function returns + success if signer of the buffer is within this list + (and not within RevokedDb). This parameter is + required. + @param[in] RevokedDb Optional pointer to a list of pointers to + EFI_SIGNATURE_LIST structures. The list is terminated + by a null pointer. List of X.509 certificates of + revoked signers and revoked file hashes. Except as + noted in description of TimeStampDb signature + verification will always fail if the signer of the + file or the hash of the data component of the buffer + is in RevokedDb list. This list is optional and + caller may pass Null or pointer to NULL if not + required. + @param[in] TimeStampDb Optional pointer to a list of pointers to + EFI_SIGNATURE_LIST structures. The list is terminated + by a null pointer. This parameter can be used to pass + a list of X.509 certificates of trusted time stamp + signers. This list is optional and caller must pass + Null or pointer to NULL if not required. + @param[out] Content On input, points to an optional caller-allocated + buffer into which the function will copy the content + portion of the file after verification succeeds. + This parameter is optional and if NULL, no copy of + content from file is performed. + @param[in,out] ContentSize On input, points to the size in bytes of the optional + buffer Content previously allocated by caller. On + output, if the verification succeeds, the value + referenced by ContentSize will contain the actual + size of the content from signed file. If ContentSize + indicates the caller-allocated buffer is too small + to contain content, an error is returned, and + ContentSize will be updated with the required size. + This parameter must be 0 if Content is Null. + + @retval EFI_SUCCESS Content signature was verified against hash of + content, the signer's certificate was not found in + RevokedDb, and was found in AllowedDb or if in signer + is found in both AllowedDb and RevokedDb, the + signing was allowed by reference to TimeStampDb as + described above, and no hash matching content hash + was found in RevokedDb. + @retval EFI_SECURITY_VIOLATION The SignedData buffer was correctly formatted but + signer was in RevokedDb or not in AllowedDb. Also + returned if matching content hash found in RevokedDb. + @retval EFI_COMPROMISED_DATA Calculated hash differs from signed hash. + @retval EFI_INVALID_PARAMETER SignedData is NULL or SignedDataSize is zero. + AllowedDb is NULL. + @retval EFI_INVALID_PARAMETER Content is not NULL and ContentSize is NULL. + @retval EFI_ABORTED Unsupported or invalid format in TimeStampDb, + RevokedDb or AllowedDb list contents was detected. + @retval EFI_NOT_FOUND Content not found because InData is NULL and no + content embedded in SignedData. + @retval EFI_UNSUPPORTED The SignedData buffer was not correctly formatted + for processing by the function. + @retval EFI_UNSUPPORTED Signed data embedded in SignedData but InData is not + NULL. + @retval EFI_BUFFER_TOO_SMALL The size of buffer indicated by ContentSize is too + small to hold the content. ContentSize updated to + required size. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PKCS7_VERIFY_BUFFER) ( + IN EFI_PKCS7_VERIFY_PROTOCOL *This, + IN VOID *SignedData, + IN UINTN SignedDataSize, + IN VOID *InData OPTIONAL, + IN UINTN InDataSize, + IN EFI_SIGNATURE_LIST **AllowedDb, + IN EFI_SIGNATURE_LIST **RevokedDb OPTIONAL, + IN EFI_SIGNATURE_LIST **TimeStampDb OPTIONAL, + OUT VOID *Content OPTIONAL, + IN OUT UINTN *ContentSize + ); + +/** + Processes a buffer containing binary DER-encoded detached PKCS7 signature. + The hash of the signed data content is calculated and passed by the caller. Function + verifies the signature of the content is valid and signing certificate was not revoked + and is contained within a list of trusted signers. + + Note: because this function uses hashes and the specification contains a variety of + hash choices, you should be aware that the check against the RevokedDb list + will improperly succeed if the signature is revoked using a different hash + algorithm. For this reason, you should either cycle through all UEFI supported + hashes to see if one is forbidden, or rely on a single hash choice only if the + UEFI signature authority only signs and revokes with a single hash (at time + of writing, this hash choice is SHA256). + + @param[in] This Pointer to EFI_PKCS7_VERIFY_PROTOCOL instance. + @param[in] Signature Points to buffer containing ASN.1 DER-encoded PKCS + detached signature. + @param[in] SignatureSize The size of Signature buffer in bytes. + @param[in] InHash InHash points to buffer containing the caller + calculated hash of the data. The parameter may not + be NULL. + @param[in] InHashSize The size in bytes of InHash buffer. + @param[in] AllowedDb Pointer to a list of pointers to EFI_SIGNATURE_LIST + structures. The list is terminated by a null + pointer. The EFI_SIGNATURE_LIST structures contain + lists of X.509 certificates of approved signers. + Function recognizes signer certificates of type + EFI_CERT_X509_GUID. Any hash certificate in AllowedDb + list is ignored by this function. Function returns + success if signer of the buffer is within this list + (and not within RevokedDb). This parameter is + required. + @param[in] RevokedDb Optional pointer to a list of pointers to + EFI_SIGNATURE_LIST structures. The list is terminated + by a null pointer. List of X.509 certificates of + revoked signers and revoked file hashes. Signature + verification will always fail if the signer of the + file or the hash of the data component of the buffer + is in RevokedDb list. This parameter is optional + and caller may pass Null if not required. + @param[in] TimeStampDb Optional pointer to a list of pointers to + EFI_SIGNATURE_LIST structures. The list is terminated + by a null pointer. This parameter can be used to pass + a list of X.509 certificates of trusted time stamp + counter-signers. + + @retval EFI_SUCCESS Signed hash was verified against caller-provided + hash of content, the signer's certificate was not + found in RevokedDb, and was found in AllowedDb or + if in signer is found in both AllowedDb and + RevokedDb, the signing was allowed by reference to + TimeStampDb as described above, and no hash matching + content hash was found in RevokedDb. + @retval EFI_SECURITY_VIOLATION The SignedData buffer was correctly formatted but + signer was in RevokedDb or not in AllowedDb. Also + returned if matching content hash found in RevokedDb. + @retval EFI_COMPROMISED_DATA Caller provided hash differs from signed hash. Or, + caller and encrypted hash are different sizes. + @retval EFI_INVALID_PARAMETER Signature is NULL or SignatureSize is zero. InHash + is NULL or InHashSize is zero. AllowedDb is NULL. + @retval EFI_ABORTED Unsupported or invalid format in TimeStampDb, + RevokedDb or AllowedDb list contents was detected. + @retval EFI_UNSUPPORTED The Signature buffer was not correctly formatted + for processing by the function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PKCS7_VERIFY_SIGNATURE) ( + IN EFI_PKCS7_VERIFY_PROTOCOL *This, + IN VOID *Signature, + IN UINTN SignatureSize, + IN VOID *InHash, + IN UINTN InHashSize, + IN EFI_SIGNATURE_LIST **AllowedDb, + IN EFI_SIGNATURE_LIST **RevokedDb OPTIONAL, + IN EFI_SIGNATURE_LIST **TimeStampDb OPTIONAL + ); + +/// +/// The EFI_PKCS7_VERIFY_PROTOCOL is used to verify data signed using PKCS7 +/// structure. The PKCS7 data to be verified must be ASN.1 (DER) encoded. +/// SHA256 must be supported as digest algorithm with RSA digest encryption. +/// Support of other hash algorithms is optional. +/// +struct _EFI_PKCS7_VERIFY_PROTOCOL { + EFI_PKCS7_VERIFY_BUFFER VerifyBuffer; + EFI_PKCS7_VERIFY_SIGNATURE VerifySignature; +}; + +extern EFI_GUID gEfiPkcs7VerifyProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformDriverOverride.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformDriverOverride.h new file mode 100644 index 0000000000..e60ca5a82a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformDriverOverride.h @@ -0,0 +1,134 @@ +/** @file + Platform Driver Override protocol as defined in the UEFI 2.1 specification. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL_H__ +#define __EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL_H__ + +/// +/// Global ID for the Platform Driver Override Protocol +/// +#define EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL_GUID \ + { \ + 0x6b30c738, 0xa391, 0x11d4, {0x9a, 0x3b, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL; + +// +// Prototypes for the Platform Driver Override Protocol +// + +/** + Retrieves the image handle of the platform override driver for a controller in the system. + + @param This A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_ + PROTOCOL instance. + @param ControllerHandle The device handle of the controller to check if a driver override + exists. + @param DriverImageHandle On input, a pointer to the previous driver image handle returned + by GetDriver(). On output, a pointer to the next driver + image handle. + + @retval EFI_SUCCESS The driver override for ControllerHandle was returned in + DriverImageHandle. + @retval EFI_NOT_FOUND A driver override for ControllerHandle was not found. + @retval EFI_INVALID_PARAMETER The handle specified by ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a + previous call to GetDriver(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER)( + IN EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN OUT EFI_HANDLE *DriverImageHandle + ); + +/** + Retrieves the device path of the platform override driver for a controller in the system. + + @param This A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL instance. + @param ControllerHandle The device handle of the controller to check if a driver override + exists. + @param DriverImagePath On input, a pointer to the previous driver device path returned by + GetDriverPath(). On output, a pointer to the next driver + device path. Passing in a pointer to NULL will return the first + driver device path for ControllerHandle. + + @retval EFI_SUCCESS The driver override for ControllerHandle was returned in + DriverImageHandle. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_NOT_FOUND A driver override for ControllerHandle was not found. + @retval EFI_INVALID_PARAMETER The handle specified by ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER DriverImagePath is not a device path that was returned on a + previous call to GetDriverPath(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH)( + IN EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DriverImagePath + ); + +/** + Used to associate a driver image handle with a device path that was returned on a prior call to the + GetDriverPath() service. This driver image handle will then be available through the + GetDriver() service. + + @param This A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_ + PROTOCOL instance. + @param ControllerHandle The device handle of the controller. + @param DriverImagePath A pointer to the driver device path that was returned in a prior + call to GetDriverPath(). + @param DriverImageHandle The driver image handle that was returned by LoadImage() + when the driver specified by DriverImagePath was loaded + into memory. + + @retval EFI_SUCCESS The association between DriverImagePath and + DriverImageHandle was established for the controller specified + by ControllerHandle. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_NOT_FOUND DriverImagePath is not a device path that was returned on a prior + call to GetDriverPath() for the controller specified by + ControllerHandle. + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + @retval EFI_INVALID_PARAMETER DriverImagePath is not a valid device path. + @retval EFI_INVALID_PARAMETER DriverImageHandle is not a valid image handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED)( + IN EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *DriverImagePath, + IN EFI_HANDLE DriverImageHandle + ); + +/// +/// This protocol matches one or more drivers to a controller. A platform driver +/// produces this protocol, and it is installed on a separate handle. This protocol +/// is used by the ConnectController() boot service to select the best driver +/// for a controller. All of the drivers returned by this protocol have a higher +/// precedence than drivers found from an EFI Bus Specific Driver Override Protocol +/// or drivers found from the general UEFI driver Binding search algorithm. If more +/// than one driver is returned by this protocol, then the drivers are returned in +/// order from highest precedence to lowest precedence. +/// +struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL { + EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER GetDriver; + EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH GetDriverPath; + EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED DriverLoaded; +}; + +extern EFI_GUID gEfiPlatformDriverOverrideProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h new file mode 100644 index 0000000000..55d1962d61 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h @@ -0,0 +1,349 @@ +/** @file + UEFI Platform to Driver Configuration Protocol is defined in UEFI specification. + + This is a protocol that is optionally produced by the platform and optionally consumed + by a UEFI Driver in its Start() function. This protocol allows the driver to receive + configuration information as part of being started. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLATFORM_TO_DRIVER_CONFIGUARTION_H__ +#define __PLATFORM_TO_DRIVER_CONFIGUARTION_H__ + +#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL_GUID \ + { 0x642cd590, 0x8059, 0x4c0a, { 0xa9, 0x58, 0xc5, 0xec, 0x7, 0xd2, 0x3c, 0x4b } } + + +typedef struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL; + + +/** + The UEFI driver must call Query early in the Start() function + before any time consuming operations are performed. If + ChildHandle is NULL the driver is requesting information from + the platform about the ControllerHandle that is being started. + Information returned from Query may lead to the drivers Start() + function failing. + If the UEFI driver is a bus driver and producing a ChildHandle, + the driver must call Query after the child handle has been created + and an EFI_DEVICE_PATH_PROTOCOL has been placed on that handle, + but before any time consuming operation is performed. If information + return by Query may lead the driver to decide to not create the + ChildHandle. The driver must then cleanup and remove the ChildHandle + from the system. + The UEFI driver repeatedly calls Query, processes the information + returned by the platform, and calls Response passing in the + arguments returned from Query. The Instance value passed into + Response must be the same value passed into the corresponding + call to Query. The UEFI driver must continuously call Query and + Response until EFI_NOT_FOUND is returned by Query. + If the UEFI driver does not recognize the ParameterTypeGuid, it + calls Response with a ConfigurationAction of + EfiPlatformConfigurationActionUnsupportedGuid. The UEFI driver + must then continue calling Query and Response until EFI_NOT_FOUND + is returned by Query. This gives the platform an opportunity to + pass additional configuration settings using a different + ParameterTypeGuid that may be supported by the driver. + An Instance value of zero means return the first ParameterBlock + in the set of unprocessed parameter blocks. The driver should + increment the Instance value by one for each successive call to Query. + + @param This A pointer to the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL instance. + + @param ControllerHandle The handle the platform will return + configuration information about. + + @param ChildHandle The handle of the child controller to + return information on. This is an optional + parameter that may be NULL. It will be + NULL for device drivers and for bus + drivers that attempt to get options for + the bus controller. It will not be NULL + for a bus driver that attempts to get + options for one of its child controllers. + + + @param Instance Pointer to the Instance value. Zero means + return the first query data. The caller should + increment this value by one each time to retrieve + successive data. + + @param ParameterTypeGuid An EFI_GUID that defines the contents + of ParameterBlock. UEFI drivers must + use the ParameterTypeGuid to determine + how to parse the ParameterBlock. The caller + should not attempt to free ParameterTypeGuid. + + @param ParameterBlock The platform returns a pointer to the + ParameterBlock structure which + contains details about the + configuration parameters specific to + the ParameterTypeGuid. This structure + is defined based on the protocol and + may be different for different + protocols. UEFI driver decodes this + structure and its contents based on + ParameterTypeGuid. ParameterBlock is + allocated by the platform and the + platform is responsible for freeing + the ParameterBlock after Result is + called. + + @param ParameterBlockSize The platform returns the size of + the ParameterBlock in bytes. + + + @retval EFI_SUCCESS The platform return parameter + information for ControllerHandle. + + @retval EFI_NOT_FOUND No more unread Instance exists. + + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + + @retval EFI_INVALID_PARAMETER Instance is NULL. + + @retval EFI_DEVICE_ERROR A device error occurred while + attempting to return parameter block + information for the controller + specified by ControllerHandle and + ChildHandle. + + @retval EFI_OUT_RESOURCES There are not enough resources + available to set the configuration + options for the controller specified + by ControllerHandle and ChildHandle. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY)( + IN CONST EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL *This, + IN CONST EFI_HANDLE ControllerHandle, + IN CONST EFI_HANDLE ChildHandle OPTIONAL, + IN CONST UINTN *Instance, + OUT EFI_GUID **ParameterTypeGuid, + OUT VOID **ParameterBlock, + OUT UINTN *ParameterBlockSize +); + +typedef enum { + /// + /// The controller specified by ControllerHandle is still + /// in a usable state, and its configuration has been updated + /// via parsing the ParameterBlock. If required by the + /// parameter block, and the module supports an NVRAM store, + /// the configuration information from PB was successfully + /// saved to the NVRAM. No actions are required before + /// this controller can be used again with the updated + /// configuration settings. + /// + EfiPlatformConfigurationActionNone = 0, + + /// + /// The driver has detected that the controller specified + /// by ControllerHandle is not in a usable state and + /// needs to be stopped. The calling agent can use the + /// DisconnectControservice to perform this operation, and + /// it should be performed as soon as possible. + /// + EfiPlatformConfigurationActionStopController = 1, + + /// + /// This controller specified by ControllerHandle needs to + /// be stopped and restarted before it can be used again. + /// The calling agent can use the DisconnectController() + /// and ConnectController() services to perform this + /// operation. The restart operation can be delayed until + /// all of the configuration options have been set. + /// + EfiPlatformConfigurationActionRestartController = 2, + + /// + /// A configuration change has been made that requires the + /// platform to be restarted before the controller + /// specified by ControllerHandle can be used again. The + /// calling agent can use the ResetSystem() services to + /// perform this operation. The restart operation can be + /// delayed until all of the configuration options have + /// been set. + /// + EfiPlatformConfigurationActionRestartPlatform = 3, + + /// + /// The controller specified by ControllerHandle is still + /// in a usable state; its configuration has been updated + /// via parsing the ParameterBlock. The driver tried to + /// update the driver's private NVRAM store with + /// information from ParameterBlock and failed. No actions + /// are required before this controller can be used again + /// with the updated configuration settings, but these + /// configuration settings are not guaranteed to persist + /// after ControllerHandle is stopped. + /// + EfiPlatformConfigurationActionNvramFailed = 4, + + /// + /// The controller specified by ControllerHandle is still + /// in a usable state; its configuration has not been updated + /// via parsing the ParameterBlock. The driver did not support + /// the ParameterBlock format identified by ParameterTypeGuid. + /// No actions are required before this controller can be used + /// again. On additional Query calls from this ControllerHandle, + /// the platform should stop returning a ParameterBlock + /// qualified by this same ParameterTypeGuid. If no other + /// ParameterTypeGuid is supported by the platform, Query + /// should return EFI_NOT_FOUND. + /// + EfiPlatformConfigurationActionUnsupportedGuid = 5, + EfiPlatformConfigurationActionMaximum +} EFI_PLATFORM_CONFIGURATION_ACTION; + + +/** + The UEFI driver repeatedly calls Query, processes the + information returned by the platform, and calls Response passing + in the arguments returned from Query. The UEFI driver must + continuously call Query until EFI_NOT_FOUND is returned. For + every call to Query that returns EFI_SUCCESS a corrisponding + call to Response is required passing in the same + ContollerHandle, ChildHandle, Instance, ParameterTypeGuid, + ParameterBlock, and ParameterBlockSize. The UEFI driver may + update values in ParameterBlock based on rules defined by + ParameterTypeGuid. The platform is responsible for freeing + ParameterBlock and the UEFI driver must not try to free it. + + @param This A pointer to the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL instance. + + @param ControllerHandle The handle the driver is returning + configuration information about. + + @param ChildHandle The handle of the child controller to + return information on. This is an optional + parameter that may be NULL. It will be + NULL for device drivers, and for bus + drivers that attempt to get options for + the bus controller. It will not be NULL + for a bus driver that attempts to get + options for one of its child controllers. + Instance Instance data returned from + Query(). + + @param Instance Instance data passed to Query(). + + @param ParameterTypeGuid ParameterTypeGuid returned from Query. + + @param ParameterBlock ParameterBlock returned from Query. + + @param ParameterBlockSize The ParameterBlock size returned from Query. + + @param ConfigurationAction The driver tells the platform what + action is required for ParameterBlock to + take effect. + + + @retval EFI_SUCCESS The platform return parameter information + for ControllerHandle. + + @retval EFI_NOT_FOUND Instance was not found. + + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + + @retval EFI_INVALID_PARAMETER Instance is zero. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE)( + IN CONST EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL *This, + IN CONST EFI_HANDLE ControllerHandle, + IN CONST EFI_HANDLE ChildHandle OPTIONAL, + IN CONST UINTN *Instance, + IN CONST EFI_GUID *ParameterTypeGuid, + IN CONST VOID *ParameterBlock, + IN CONST UINTN ParameterBlockSize , + IN CONST EFI_PLATFORM_CONFIGURATION_ACTION ConfigurationAction +); + + +/// +/// The EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL is used by the +/// UEFI driver to query the platform for configuration information. +/// The UEFI driver calls Query() multiple times to get +/// configuration information from the platform. For every call to +/// Query() there must be a matching call to Response() so the +/// UEFI driver can inform the platform how it used the +/// information passed in from Query(). It's legal for a UEFI +/// driver to use Response() to inform the platform it does not +/// understand the data returned via Query() and thus no action was +/// taken. +/// +struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL { + EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY Query; + EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE Response; +}; + + + +#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_CLP_GUID \ + {0x345ecc0e, 0xcb6, 0x4b75, { 0xbb, 0x57, 0x1b, 0x12, 0x9c, 0x47, 0x33,0x3e } } + +/** + + ParameterTypeGuid provides the support for parameters + communicated through the DMTF SM CLP Specification 1.0 Final + Standard to be used to configure the UEFI driver. In this + section the producer of the + EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL is platform + firmware and the consumer is the UEFI driver. Note: if future + versions of the DMTF SM CLP Specification require changes to the + parameter block definition, a newer ParameterTypeGuid will be + used. +**/ +typedef struct { + CHAR8 *CLPCommand; ///< A pointer to the null-terminated UTF-8 string that specifies the DMTF SM CLP command + ///< line that the driver is required to parse and process when this function is called. + ///< See the DMTF SM CLP Specification 1.0 Final Standard for details on the + ///< format and syntax of the CLP command line string. CLPCommand buffer + ///< is allocated by the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOOL. + UINT32 CLPCommandLength; ///< The length of the CLP Command in bytes. + CHAR8 *CLPReturnString; ///< A pointer to the null-terminated UTF-8 string that indicates the CLP return status + ///< that the driver is required to provide to the calling agent. + ///< The calling agent may parse and/ or pass + ///< this for processing and user feedback. The SM CLP Command Response string + ///< buffer is filled in by the UEFI driver in the "keyword=value" format + ///< described in the SM CLP Specification, unless otherwise requested via the SM + ///< CLP Coutput option in the Command Line string buffer. UEFI driver's support + ///< for this default "keyword=value" output format is required if the UEFI + ///< driver supports this protocol, while support for other SM CLP output + ///< formats is optional (the UEFI Driver should return an EFI_UNSUPPORTED if + ///< the SM CLP Coutput option requested by the caller is not supported by the + ///< UEFI Driver). CLPReturnString buffer is allocated by the consumer of the + ///< EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to + ///< Response(). + UINT32 CLPReturnStringLength; ///< The length of the CLP return status string in bytes. + UINT8 CLPCmdStatus; ///< SM CLP Command Status (see DMTF SM CLP Specification 1.0 Final Standard - + ///< Table 4) CLPErrorValue SM CLP Processing Error Value (see DMTF SM + ///< CLP Specification 1.0 Final Standard - Table 6). This field is filled in by + ///< the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC + ///< OL and undefined prior to the call to Response(). + UINT8 CLPErrorValue; ///< SM CLP Processing Error Value (see DMTF SM CLP Specification 1.0 Final Standard - Table 6). + ///< This field is filled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL and undefined prior to the call to Response(). + UINT16 CLPMsgCode; ///< Bit 15: OEM Message Code Flag 0 = Message Code is an SM CLP Probable + ///< Cause Value. (see SM CLP Specification Table 11) 1 = Message Code is OEM + ///< Specific Bits 14-0: Message Code This field is filled in by the consumer of + ///< the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to + ///< Response(). + +} EFI_CONFIGURE_CLP_PARAMETER_BLK; + + + +extern EFI_GUID gEfiPlatformToDriverConfigurationClpGuid; + +extern EFI_GUID gEfiPlatformToDriverConfigurationProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCode.h new file mode 100644 index 0000000000..388a83a090 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCode.h @@ -0,0 +1,930 @@ +/** @file + EFI PXE Base Code Protocol definitions, which is used to access PXE-compatible + devices for network access and network booting. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in EFI Specification 1.10. + +**/ +#ifndef __PXE_BASE_CODE_PROTOCOL_H__ +#define __PXE_BASE_CODE_PROTOCOL_H__ + +/// +/// PXE Base Code protocol. +/// +#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \ + { \ + 0x03c4e603, 0xac28, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE_PROTOCOL; + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE; + +/// +/// Default IP TTL and ToS. +/// +#define DEFAULT_TTL 16 +#define DEFAULT_ToS 0 + +/// +/// ICMP error format. +/// +typedef struct { + UINT8 Type; + UINT8 Code; + UINT16 Checksum; + union { + UINT32 reserved; + UINT32 Mtu; + UINT32 Pointer; + struct { + UINT16 Identifier; + UINT16 Sequence; + } Echo; + } u; + UINT8 Data[494]; +} EFI_PXE_BASE_CODE_ICMP_ERROR; + +/// +/// TFTP error format. +/// +typedef struct { + UINT8 ErrorCode; + CHAR8 ErrorString[127]; +} EFI_PXE_BASE_CODE_TFTP_ERROR; + +/// +/// IP Receive Filter definitions. +/// +#define EFI_PXE_BASE_CODE_MAX_IPCNT 8 + +/// +/// IP Receive Filter structure. +/// +typedef struct { + UINT8 Filters; + UINT8 IpCnt; + UINT16 reserved; + EFI_IP_ADDRESS IpList[EFI_PXE_BASE_CODE_MAX_IPCNT]; +} EFI_PXE_BASE_CODE_IP_FILTER; + +#define EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP 0x0001 +#define EFI_PXE_BASE_CODE_IP_FILTER_BROADCAST 0x0002 +#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS 0x0004 +#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS_MULTICAST 0x0008 + +/// +/// ARP cache entries. +/// +typedef struct { + EFI_IP_ADDRESS IpAddr; + EFI_MAC_ADDRESS MacAddr; +} EFI_PXE_BASE_CODE_ARP_ENTRY; + +/// +/// ARP route table entries. +/// +typedef struct { + EFI_IP_ADDRESS IpAddr; + EFI_IP_ADDRESS SubnetMask; + EFI_IP_ADDRESS GwAddr; +} EFI_PXE_BASE_CODE_ROUTE_ENTRY; + +// +// UDP definitions +// +typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; + +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_IP 0x0001 +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_PORT 0x0002 +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_IP 0x0004 +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_PORT 0x0008 +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_USE_FILTER 0x0010 +#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_MAY_FRAGMENT 0x0020 + +// +// Discover() definitions +// +#define EFI_PXE_BASE_CODE_BOOT_TYPE_BOOTSTRAP 0 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_MS_WINNT_RIS 1 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_INTEL_LCM 2 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_DOSUNDI 3 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_NEC_ESMPRO 4 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_IBM_WSoD 5 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_IBM_LCCM 6 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_CA_UNICENTER_TNG 7 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_HP_OPENVIEW 8 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_9 9 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_10 10 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_ALTIRIS_11 11 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_NOT_USED_12 12 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_REDHAT_INSTALL 13 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_REDHAT_BOOT 14 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_REMBO 15 +#define EFI_PXE_BASE_CODE_BOOT_TYPE_BEOBOOT 16 +// +// 17 through 32767 are reserved +// 32768 through 65279 are for vendor use +// 65280 through 65534 are reserved +// +#define EFI_PXE_BASE_CODE_BOOT_TYPE_PXETEST 65535 + +#define EFI_PXE_BASE_CODE_BOOT_LAYER_MASK 0x7FFF +#define EFI_PXE_BASE_CODE_BOOT_LAYER_INITIAL 0x0000 + +// +// PXE Tag definition that identifies the processor +// and programming environment of the client system. +// These identifiers are defined by IETF: +// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml +// +#if defined (MDE_CPU_IA32) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006 +#elif defined (MDE_CPU_X64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007 +#elif defined (MDE_CPU_ARM) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A +#elif defined (MDE_CPU_AARCH64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B +#elif defined (MDE_CPU_RISCV64) +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B +#endif + + +/// +/// Discover() server list structure. +/// +typedef struct { + UINT16 Type; + BOOLEAN AcceptAnyResponse; + UINT8 Reserved; + EFI_IP_ADDRESS IpAddr; +} EFI_PXE_BASE_CODE_SRVLIST; + +/// +/// Discover() information override structure. +/// +typedef struct { + BOOLEAN UseMCast; + BOOLEAN UseBCast; + BOOLEAN UseUCast; + BOOLEAN MustUseList; + EFI_IP_ADDRESS ServerMCastIp; + UINT16 IpCnt; + EFI_PXE_BASE_CODE_SRVLIST SrvList[1]; +} EFI_PXE_BASE_CODE_DISCOVER_INFO; + +/// +/// TFTP opcode definitions. +/// +typedef enum { + EFI_PXE_BASE_CODE_TFTP_FIRST, + EFI_PXE_BASE_CODE_TFTP_GET_FILE_SIZE, + EFI_PXE_BASE_CODE_TFTP_READ_FILE, + EFI_PXE_BASE_CODE_TFTP_WRITE_FILE, + EFI_PXE_BASE_CODE_TFTP_READ_DIRECTORY, + EFI_PXE_BASE_CODE_MTFTP_GET_FILE_SIZE, + EFI_PXE_BASE_CODE_MTFTP_READ_FILE, + EFI_PXE_BASE_CODE_MTFTP_READ_DIRECTORY, + EFI_PXE_BASE_CODE_MTFTP_LAST +} EFI_PXE_BASE_CODE_TFTP_OPCODE; + +/// +/// MTFTP information. This information is required +/// to start or join a multicast TFTP session. It is also required to +/// perform the "get file size" and "read directory" operations of MTFTP. +/// +typedef struct { + EFI_IP_ADDRESS MCastIp; + EFI_PXE_BASE_CODE_UDP_PORT CPort; + EFI_PXE_BASE_CODE_UDP_PORT SPort; + UINT16 ListenTimeout; + UINT16 TransmitTimeout; +} EFI_PXE_BASE_CODE_MTFTP_INFO; + +/// +/// DHCPV4 Packet structure. +/// +typedef struct { + UINT8 BootpOpcode; + UINT8 BootpHwType; + UINT8 BootpHwAddrLen; + UINT8 BootpGateHops; + UINT32 BootpIdent; + UINT16 BootpSeconds; + UINT16 BootpFlags; + UINT8 BootpCiAddr[4]; + UINT8 BootpYiAddr[4]; + UINT8 BootpSiAddr[4]; + UINT8 BootpGiAddr[4]; + UINT8 BootpHwAddr[16]; + UINT8 BootpSrvName[64]; + UINT8 BootpBootFile[128]; + UINT32 DhcpMagik; + UINT8 DhcpOptions[56]; +} EFI_PXE_BASE_CODE_DHCPV4_PACKET; + +/// +/// DHCPV6 Packet structure. +/// +typedef struct { + UINT32 MessageType:8; + UINT32 TransactionId:24; + UINT8 DhcpOptions[1024]; +} EFI_PXE_BASE_CODE_DHCPV6_PACKET; + +/// +/// Packet structure. +/// +typedef union { + UINT8 Raw[1472]; + EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4; + EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6; +} EFI_PXE_BASE_CODE_PACKET; + +// +// PXE Base Code Mode structure +// +#define EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES 8 +#define EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES 8 + +/// +/// EFI_PXE_BASE_CODE_MODE. +/// The data values in this structure are read-only and +/// are updated by the code that produces the +/// EFI_PXE_BASE_CODE_PROTOCOL functions. +/// +typedef struct { + BOOLEAN Started; + BOOLEAN Ipv6Available; + BOOLEAN Ipv6Supported; + BOOLEAN UsingIpv6; + BOOLEAN BisSupported; + BOOLEAN BisDetected; + BOOLEAN AutoArp; + BOOLEAN SendGUID; + BOOLEAN DhcpDiscoverValid; + BOOLEAN DhcpAckReceived; + BOOLEAN ProxyOfferReceived; + BOOLEAN PxeDiscoverValid; + BOOLEAN PxeReplyReceived; + BOOLEAN PxeBisReplyReceived; + BOOLEAN IcmpErrorReceived; + BOOLEAN TftpErrorReceived; + BOOLEAN MakeCallbacks; + UINT8 TTL; + UINT8 ToS; + EFI_IP_ADDRESS StationIp; + EFI_IP_ADDRESS SubnetMask; + EFI_PXE_BASE_CODE_PACKET DhcpDiscover; + EFI_PXE_BASE_CODE_PACKET DhcpAck; + EFI_PXE_BASE_CODE_PACKET ProxyOffer; + EFI_PXE_BASE_CODE_PACKET PxeDiscover; + EFI_PXE_BASE_CODE_PACKET PxeReply; + EFI_PXE_BASE_CODE_PACKET PxeBisReply; + EFI_PXE_BASE_CODE_IP_FILTER IpFilter; + UINT32 ArpCacheEntries; + EFI_PXE_BASE_CODE_ARP_ENTRY ArpCache[EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES]; + UINT32 RouteTableEntries; + EFI_PXE_BASE_CODE_ROUTE_ENTRY RouteTable[EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES]; + EFI_PXE_BASE_CODE_ICMP_ERROR IcmpError; + EFI_PXE_BASE_CODE_TFTP_ERROR TftpError; +} EFI_PXE_BASE_CODE_MODE; + +// +// PXE Base Code Interface Function definitions +// + +/** + Enables the use of the PXE Base Code Protocol functions. + + This function enables the use of the PXE Base Code Protocol functions. If the + Started field of the EFI_PXE_BASE_CODE_MODE structure is already TRUE, then + EFI_ALREADY_STARTED will be returned. If UseIpv6 is TRUE, then IPv6 formatted + addresses will be used in this session. If UseIpv6 is FALSE, then IPv4 formatted + addresses will be used in this session. If UseIpv6 is TRUE, and the Ipv6Supported + field of the EFI_PXE_BASE_CODE_MODE structure is FALSE, then EFI_UNSUPPORTED will + be returned. If there is not enough memory or other resources to start the PXE + Base Code Protocol, then EFI_OUT_OF_RESOURCES will be returned. Otherwise, the + PXE Base Code Protocol will be started, and all of the fields of the EFI_PXE_BASE_CODE_MODE + structure will be initialized as follows: + StartedSet to TRUE. + Ipv6SupportedUnchanged. + Ipv6AvailableUnchanged. + UsingIpv6Set to UseIpv6. + BisSupportedUnchanged. + BisDetectedUnchanged. + AutoArpSet to TRUE. + SendGUIDSet to FALSE. + TTLSet to DEFAULT_TTL. + ToSSet to DEFAULT_ToS. + DhcpCompletedSet to FALSE. + ProxyOfferReceivedSet to FALSE. + StationIpSet to an address of all zeros. + SubnetMaskSet to a subnet mask of all zeros. + DhcpDiscoverZero-filled. + DhcpAckZero-filled. + ProxyOfferZero-filled. + PxeDiscoverValidSet to FALSE. + PxeDiscoverZero-filled. + PxeReplyValidSet to FALSE. + PxeReplyZero-filled. + PxeBisReplyValidSet to FALSE. + PxeBisReplyZero-filled. + IpFilterSet the Filters field to 0 and the IpCnt field to 0. + ArpCacheEntriesSet to 0. + ArpCacheZero-filled. + RouteTableEntriesSet to 0. + RouteTableZero-filled. + IcmpErrorReceivedSet to FALSE. + IcmpErrorZero-filled. + TftpErroReceivedSet to FALSE. + TftpErrorZero-filled. + MakeCallbacksSet to TRUE if the PXE Base Code Callback Protocol is available. + Set to FALSE if the PXE Base Code Callback Protocol is not available. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param UseIpv6 Specifies the type of IP addresses that are to be used during the session + that is being started. Set to TRUE for IPv6 addresses, and FALSE for + IPv4 addresses. + + @retval EFI_SUCCESS The PXE Base Code Protocol was started. + @retval EFI_DEVICE_ERROR The network device encountered an error during this oper + @retval EFI_UNSUPPORTED UseIpv6 is TRUE, but the Ipv6Supported field of the + EFI_PXE_BASE_CODE_MODE structure is FALSE. + @retval EFI_ALREADY_STARTED The PXE Base Code Protocol is already in the started state. + @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid + EFI_PXE_BASE_CODE_PROTOCOL structure. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough memory or other resources to start the + PXE Base Code Protocol. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_START)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN BOOLEAN UseIpv6 + ); + +/** + Disables the use of the PXE Base Code Protocol functions. + + This function stops all activity on the network device. All the resources allocated + in Start() are released, the Started field of the EFI_PXE_BASE_CODE_MODE structure is + set to FALSE and EFI_SUCCESS is returned. If the Started field of the EFI_PXE_BASE_CODE_MODE + structure is already FALSE, then EFI_NOT_STARTED will be returned. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + + @retval EFI_SUCCESS The PXE Base Code Protocol was stopped. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is already in the stopped state. + @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid + EFI_PXE_BASE_CODE_PROTOCOL structure. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_STOP)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This + ); + +/** + Attempts to complete a DHCPv4 D.O.R.A. (discover / offer / request / acknowledge) or DHCPv6 + S.A.R.R (solicit / advertise / request / reply) sequence. + + This function attempts to complete the DHCP sequence. If this sequence is completed, + then EFI_SUCCESS is returned, and the DhcpCompleted, ProxyOfferReceived, StationIp, + SubnetMask, DhcpDiscover, DhcpAck, and ProxyOffer fields of the EFI_PXE_BASE_CODE_MODE + structure are filled in. + If SortOffers is TRUE, then the cached DHCP offer packets will be sorted before + they are tried. If SortOffers is FALSE, then the cached DHCP offer packets will + be tried in the order in which they are received. Please see the Preboot Execution + Environment (PXE) Specification for additional details on the implementation of DHCP. + This function can take at least 31 seconds to timeout and return control to the + caller. If the DHCP sequence does not complete, then EFI_TIMEOUT will be returned. + If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, + then the DHCP sequence will be stopped and EFI_ABORTED will be returned. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param SortOffers TRUE if the offers received should be sorted. Set to FALSE to try the + offers in the order that they are received. + + @retval EFI_SUCCESS Valid DHCP has completed. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid + EFI_PXE_BASE_CODE_PROTOCOL structure. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough memory to complete the DHCP Protocol. + @retval EFI_ABORTED The callback function aborted the DHCP Protocol. + @retval EFI_TIMEOUT The DHCP Protocol timed out. + @retval EFI_ICMP_ERROR An ICMP error packet was received during the DHCP session. + @retval EFI_NO_RESPONSE Valid PXE offer was not received. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_DHCP)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN BOOLEAN SortOffers + ); + +/** + Attempts to complete the PXE Boot Server and/or boot image discovery sequence. + + This function attempts to complete the PXE Boot Server and/or boot image discovery + sequence. If this sequence is completed, then EFI_SUCCESS is returned, and the + PxeDiscoverValid, PxeDiscover, PxeReplyReceived, and PxeReply fields of the + EFI_PXE_BASE_CODE_MODE structure are filled in. If UseBis is TRUE, then the + PxeBisReplyReceived and PxeBisReply fields of the EFI_PXE_BASE_CODE_MODE structure + will also be filled in. If UseBis is FALSE, then PxeBisReplyValid will be set to FALSE. + In the structure referenced by parameter Info, the PXE Boot Server list, SrvList[], + has two uses: It is the Boot Server IP address list used for unicast discovery + (if the UseUCast field is TRUE), and it is the list used for Boot Server verification + (if the MustUseList field is TRUE). Also, if the MustUseList field in that structure + is TRUE and the AcceptAnyResponse field in the SrvList[] array is TRUE, any Boot + Server reply of that type will be accepted. If the AcceptAnyResponse field is + FALSE, only responses from Boot Servers with matching IP addresses will be accepted. + This function can take at least 10 seconds to timeout and return control to the + caller. If the Discovery sequence does not complete, then EFI_TIMEOUT will be + returned. Please see the Preboot Execution Environment (PXE) Specification for + additional details on the implementation of the Discovery sequence. + If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, + then the Discovery sequence is stopped and EFI_ABORTED will be returned. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param Type The type of bootstrap to perform. + @param Layer The pointer to the boot server layer number to discover, which must be + PXE_BOOT_LAYER_INITIAL when a new server type is being + discovered. + @param UseBis TRUE if Boot Integrity Services are to be used. FALSE otherwise. + @param Info The pointer to a data structure that contains additional information on the + type of discovery operation that is to be performed. + + @retval EFI_SUCCESS The Discovery sequence has been completed. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough memory to complete Discovery. + @retval EFI_ABORTED The callback function aborted the Discovery sequence. + @retval EFI_TIMEOUT The Discovery sequence timed out. + @retval EFI_ICMP_ERROR An ICMP error packet was received during the PXE discovery + session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_DISCOVER)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN UINT16 Type, + IN UINT16 *Layer, + IN BOOLEAN UseBis, + IN EFI_PXE_BASE_CODE_DISCOVER_INFO *Info OPTIONAL + ); + +/** + Used to perform TFTP and MTFTP services. + + This function is used to perform TFTP and MTFTP services. This includes the + TFTP operations to get the size of a file, read a directory, read a file, and + write a file. It also includes the MTFTP operations to get the size of a file, + read a directory, and read a file. The type of operation is specified by Operation. + If the callback function that is invoked during the TFTP/MTFTP operation does + not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED will + be returned. + For read operations, the return data will be placed in the buffer specified by + BufferPtr. If BufferSize is too small to contain the entire downloaded file, + then EFI_BUFFER_TOO_SMALL will be returned and BufferSize will be set to zero + or the size of the requested file (the size of the requested file is only returned + if the TFTP server supports TFTP options). If BufferSize is large enough for the + read operation, then BufferSize will be set to the size of the downloaded file, + and EFI_SUCCESS will be returned. Applications using the PxeBc.Mtftp() services + should use the get-file-size operations to determine the size of the downloaded + file prior to using the read-file operations--especially when downloading large + (greater than 64 MB) files--instead of making two calls to the read-file operation. + Following this recommendation will save time if the file is larger than expected + and the TFTP server does not support TFTP option extensions. Without TFTP option + extension support, the client has to download the entire file, counting and discarding + the received packets, to determine the file size. + For write operations, the data to be sent is in the buffer specified by BufferPtr. + BufferSize specifies the number of bytes to send. If the write operation completes + successfully, then EFI_SUCCESS will be returned. + For TFTP "get file size" operations, the size of the requested file or directory + is returned in BufferSize, and EFI_SUCCESS will be returned. If the TFTP server + does not support options, the file will be downloaded into a bit bucket and the + length of the downloaded file will be returned. For MTFTP "get file size" operations, + if the MTFTP server does not support the "get file size" option, EFI_UNSUPPORTED + will be returned. + This function can take up to 10 seconds to timeout and return control to the caller. + If the TFTP sequence does not complete, EFI_TIMEOUT will be returned. + If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, + then the TFTP sequence is stopped and EFI_ABORTED will be returned. + The format of the data returned from a TFTP read directory operation is a null-terminated + filename followed by a null-terminated information string, of the form + "size year-month-day hour:minute:second" (i.e. %d %d-%d-%d %d:%d:%f - note that + the seconds field can be a decimal number), where the date and time are UTC. For + an MTFTP read directory command, there is additionally a null-terminated multicast + IP address preceding the filename of the form %d.%d.%d.%d for IP v4. The final + entry is itself null-terminated, so that the final information string is terminated + with two null octets. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param Operation The type of operation to perform. + @param BufferPtr A pointer to the data buffer. + @param Overwrite Only used on write file operations. TRUE if a file on a remote server can + be overwritten. + @param BufferSize For get-file-size operations, *BufferSize returns the size of the + requested file. + @param BlockSize The requested block size to be used during a TFTP transfer. + @param ServerIp The TFTP / MTFTP server IP address. + @param Filename A Null-terminated ASCII string that specifies a directory name or a file + name. + @param Info The pointer to the MTFTP information. + @param DontUseBuffer Set to FALSE for normal TFTP and MTFTP read file operation. + + @retval EFI_SUCCESS The TFTP/MTFTP operation was completed. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + @retval EFI_BUFFER_TOO_SMALL The buffer is not large enough to complete the read operation. + @retval EFI_ABORTED The callback function aborted the TFTP/MTFTP operation. + @retval EFI_TIMEOUT The TFTP/MTFTP operation timed out. + @retval EFI_ICMP_ERROR An ICMP error packet was received during the MTFTP session. + @retval EFI_TFTP_ERROR A TFTP error packet was received during the MTFTP session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_MTFTP)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN EFI_PXE_BASE_CODE_TFTP_OPCODE Operation, + IN OUT VOID *BufferPtr OPTIONAL, + IN BOOLEAN Overwrite, + IN OUT UINT64 *BufferSize, + IN UINTN *BlockSize OPTIONAL, + IN EFI_IP_ADDRESS *ServerIp, + IN UINT8 *Filename OPTIONAL, + IN EFI_PXE_BASE_CODE_MTFTP_INFO *Info OPTIONAL, + IN BOOLEAN DontUseBuffer + ); + +/** + Writes a UDP packet to the network interface. + + This function writes a UDP packet specified by the (optional HeaderPtr and) + BufferPtr parameters to the network interface. The UDP header is automatically + built by this routine. It uses the parameters OpFlags, DestIp, DestPort, GatewayIp, + SrcIp, and SrcPort to build this header. If the packet is successfully built and + transmitted through the network interface, then EFI_SUCCESS will be returned. + If a timeout occurs during the transmission of the packet, then EFI_TIMEOUT will + be returned. If an ICMP error occurs during the transmission of the packet, then + the IcmpErrorReceived field is set to TRUE, the IcmpError field is filled in and + EFI_ICMP_ERROR will be returned. If the Callback Protocol does not return + EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED will be returned. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param OpFlags The UDP operation flags. + @param DestIp The destination IP address. + @param DestPort The destination UDP port number. + @param GatewayIp The gateway IP address. + @param SrcIp The source IP address. + @param SrcPort The source UDP port number. + @param HeaderSize An optional field which may be set to the length of a header at + HeaderPtr to be prefixed to the data at BufferPtr. + @param HeaderPtr If HeaderSize is not NULL, a pointer to a header to be prefixed to the + data at BufferPtr. + @param BufferSize A pointer to the size of the data at BufferPtr. + @param BufferPtr A pointer to the data to be written. + + @retval EFI_SUCCESS The UDP Write operation was completed. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_BAD_BUFFER_SIZE The buffer is too long to be transmitted. + @retval EFI_ABORTED The callback function aborted the UDP Write operation. + @retval EFI_TIMEOUT The UDP Write operation timed out. + @retval EFI_ICMP_ERROR An ICMP error packet was received during the UDP write session. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_UDP_WRITE)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN UINT16 OpFlags, + IN EFI_IP_ADDRESS *DestIp, + IN EFI_PXE_BASE_CODE_UDP_PORT *DestPort, + IN EFI_IP_ADDRESS *GatewayIp, OPTIONAL + IN EFI_IP_ADDRESS *SrcIp, OPTIONAL + IN OUT EFI_PXE_BASE_CODE_UDP_PORT *SrcPort, OPTIONAL + IN UINTN *HeaderSize, OPTIONAL + IN VOID *HeaderPtr, OPTIONAL + IN UINTN *BufferSize, + IN VOID *BufferPtr + ); + +/** + Reads a UDP packet from the network interface. + + This function reads a UDP packet from a network interface. The data contents + are returned in (the optional HeaderPtr and) BufferPtr, and the size of the + buffer received is returned in BufferSize. If the input BufferSize is smaller + than the UDP packet received (less optional HeaderSize), it will be set to the + required size, and EFI_BUFFER_TOO_SMALL will be returned. In this case, the + contents of BufferPtr are undefined, and the packet is lost. If a UDP packet is + successfully received, then EFI_SUCCESS will be returned, and the information + from the UDP header will be returned in DestIp, DestPort, SrcIp, and SrcPort if + they are not NULL. + Depending on the values of OpFlags and the DestIp, DestPort, SrcIp, and SrcPort + input values, different types of UDP packet receive filtering will be performed. + The following tables summarize these receive filter operations. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param OpFlags The UDP operation flags. + @param DestIp The destination IP address. + @param DestPort The destination UDP port number. + @param SrcIp The source IP address. + @param SrcPort The source UDP port number. + @param HeaderSize An optional field which may be set to the length of a header at + HeaderPtr to be prefixed to the data at BufferPtr. + @param HeaderPtr If HeaderSize is not NULL, a pointer to a header to be prefixed to the + data at BufferPtr. + @param BufferSize A pointer to the size of the data at BufferPtr. + @param BufferPtr A pointer to the data to be read. + + @retval EFI_SUCCESS The UDP Read operation was completed. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + @retval EFI_BUFFER_TOO_SMALL The packet is larger than Buffer can hold. + @retval EFI_ABORTED The callback function aborted the UDP Read operation. + @retval EFI_TIMEOUT The UDP Read operation timed out. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_UDP_READ)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN UINT16 OpFlags, + IN OUT EFI_IP_ADDRESS *DestIp, OPTIONAL + IN OUT EFI_PXE_BASE_CODE_UDP_PORT *DestPort, OPTIONAL + IN OUT EFI_IP_ADDRESS *SrcIp, OPTIONAL + IN OUT EFI_PXE_BASE_CODE_UDP_PORT *SrcPort, OPTIONAL + IN UINTN *HeaderSize, OPTIONAL + IN VOID *HeaderPtr, OPTIONAL + IN OUT UINTN *BufferSize, + IN VOID *BufferPtr + ); + +/** + Updates the IP receive filters of a network device and enables software filtering. + + The NewFilter field is used to modify the network device's current IP receive + filter settings and to enable a software filter. This function updates the IpFilter + field of the EFI_PXE_BASE_CODE_MODE structure with the contents of NewIpFilter. + The software filter is used when the USE_FILTER in OpFlags is set to UdpRead(). + The current hardware filter remains in effect no matter what the settings of OpFlags + are, so that the meaning of ANY_DEST_IP set in OpFlags to UdpRead() is from those + packets whose reception is enabled in hardware - physical NIC address (unicast), + broadcast address, logical address or addresses (multicast), or all (promiscuous). + UdpRead() does not modify the IP filter settings. + Dhcp(), Discover(), and Mtftp() set the IP filter, and return with the IP receive + filter list emptied and the filter set to EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP. + If an application or driver wishes to preserve the IP receive filter settings, + it will have to preserve the IP receive filter settings before these calls, and + use SetIpFilter() to restore them after the calls. If incompatible filtering is + requested (for example, PROMISCUOUS with anything else), or if the device does not + support a requested filter setting and it cannot be accommodated in software + (for example, PROMISCUOUS not supported), EFI_INVALID_PARAMETER will be returned. + The IPlist field is used to enable IPs other than the StationIP. They may be + multicast or unicast. If IPcnt is set as well as EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP, + then both the StationIP and the IPs from the IPlist will be used. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param NewFilter The pointer to the new set of IP receive filters. + + @retval EFI_SUCCESS The IP receive filter settings were updated. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_SET_IP_FILTER)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN EFI_PXE_BASE_CODE_IP_FILTER *NewFilter + ); + +/** + Uses the ARP protocol to resolve a MAC address. + + This function uses the ARP protocol to resolve a MAC address. The UsingIpv6 field + of the EFI_PXE_BASE_CODE_MODE structure is used to determine if IPv4 or IPv6 + addresses are being used. The IP address specified by IpAddr is used to resolve + a MAC address. If the ARP protocol succeeds in resolving the specified address, + then the ArpCacheEntries and ArpCache fields of the EFI_PXE_BASE_CODE_MODE structure + are updated, and EFI_SUCCESS is returned. If MacAddr is not NULL, the resolved + MAC address is placed there as well. + If the PXE Base Code protocol is in the stopped state, then EFI_NOT_STARTED is + returned. If the ARP protocol encounters a timeout condition while attempting + to resolve an address, then EFI_TIMEOUT is returned. If the Callback Protocol + does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED is + returned. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param IpAddr The pointer to the IP address that is used to resolve a MAC address. + @param MacAddr If not NULL, a pointer to the MAC address that was resolved with the + ARP protocol. + + @retval EFI_SUCCESS The IP or MAC address was resolved. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_DEVICE_ERROR The network device encountered an error during this operation. + @retval EFI_ABORTED The callback function aborted the ARP Protocol. + @retval EFI_TIMEOUT The ARP Protocol encountered a timeout condition. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_ARP)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN EFI_IP_ADDRESS *IpAddr, + IN EFI_MAC_ADDRESS *MacAddr OPTIONAL + ); + +/** + Updates the parameters that affect the operation of the PXE Base Code Protocol. + + This function sets parameters that affect the operation of the PXE Base Code Protocol. + The parameter specified by NewAutoArp is used to control the generation of ARP + protocol packets. If NewAutoArp is TRUE, then ARP Protocol packets will be generated + as required by the PXE Base Code Protocol. If NewAutoArp is FALSE, then no ARP + Protocol packets will be generated. In this case, the only mappings that are + available are those stored in the ArpCache of the EFI_PXE_BASE_CODE_MODE structure. + If there are not enough mappings in the ArpCache to perform a PXE Base Code Protocol + service, then the service will fail. This function updates the AutoArp field of + the EFI_PXE_BASE_CODE_MODE structure to NewAutoArp. + The SetParameters() call must be invoked after a Callback Protocol is installed + to enable the use of callbacks. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param NewAutoArp If not NULL, a pointer to a value that specifies whether to replace the + current value of AutoARP. + @param NewSendGUID If not NULL, a pointer to a value that specifies whether to replace the + current value of SendGUID. + @param NewTTL If not NULL, a pointer to be used in place of the current value of TTL, + the "time to live" field of the IP header. + @param NewToS If not NULL, a pointer to be used in place of the current value of ToS, + the "type of service" field of the IP header. + @param NewMakeCallback If not NULL, a pointer to a value that specifies whether to replace the + current value of the MakeCallback field of the Mode structure. + + @retval EFI_SUCCESS The new parameters values were updated. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_SET_PARAMETERS)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN BOOLEAN *NewAutoArp, OPTIONAL + IN BOOLEAN *NewSendGUID, OPTIONAL + IN UINT8 *NewTTL, OPTIONAL + IN UINT8 *NewToS, OPTIONAL + IN BOOLEAN *NewMakeCallback OPTIONAL + ); + +/** + Updates the station IP address and/or subnet mask values of a network device. + + This function updates the station IP address and/or subnet mask values of a network + device. + The NewStationIp field is used to modify the network device's current IP address. + If NewStationIP is NULL, then the current IP address will not be modified. Otherwise, + this function updates the StationIp field of the EFI_PXE_BASE_CODE_MODE structure + with NewStationIp. + The NewSubnetMask field is used to modify the network device's current subnet + mask. If NewSubnetMask is NULL, then the current subnet mask will not be modified. + Otherwise, this function updates the SubnetMask field of the EFI_PXE_BASE_CODE_MODE + structure with NewSubnetMask. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param NewStationIp The pointer to the new IP address to be used by the network device. + @param NewSubnetMask The pointer to the new subnet mask to be used by the network device. + + @retval EFI_SUCCESS The new station IP address and/or subnet mask were updated. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_SET_STATION_IP)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + IN EFI_IP_ADDRESS *NewStationIp, OPTIONAL + IN EFI_IP_ADDRESS *NewSubnetMask OPTIONAL + ); + +/** + Updates the contents of the cached DHCP and Discover packets. + + The pointers to the new packets are used to update the contents of the cached + packets in the EFI_PXE_BASE_CODE_MODE structure. + + @param This The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance. + @param NewDhcpDiscoverValid The pointer to a value that will replace the current + DhcpDiscoverValid field. + @param NewDhcpAckReceived The pointer to a value that will replace the current + DhcpAckReceived field. + @param NewProxyOfferReceived The pointer to a value that will replace the current + ProxyOfferReceived field. + @param NewPxeDiscoverValid The pointer to a value that will replace the current + ProxyOfferReceived field. + @param NewPxeReplyReceived The pointer to a value that will replace the current + PxeReplyReceived field. + @param NewPxeBisReplyReceived The pointer to a value that will replace the current + PxeBisReplyReceived field. + @param NewDhcpDiscover The pointer to the new cached DHCP Discover packet contents. + @param NewDhcpAck The pointer to the new cached DHCP Ack packet contents. + @param NewProxyOffer The pointer to the new cached Proxy Offer packet contents. + @param NewPxeDiscover The pointer to the new cached PXE Discover packet contents. + @param NewPxeReply The pointer to the new cached PXE Reply packet contents. + @param NewPxeBisReply The pointer to the new cached PXE BIS Reply packet contents. + + @retval EFI_SUCCESS The cached packet contents were updated. + @retval EFI_NOT_STARTED The PXE Base Code Protocol is in the stopped state. + @retval EFI_INVALID_PARAMETER This is NULL or not point to a valid EFI_PXE_BASE_CODE_PROTOCOL structure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PXE_BASE_CODE_SET_PACKETS)( + IN EFI_PXE_BASE_CODE_PROTOCOL *This, + BOOLEAN *NewDhcpDiscoverValid, OPTIONAL + BOOLEAN *NewDhcpAckReceived, OPTIONAL + BOOLEAN *NewProxyOfferReceived, OPTIONAL + BOOLEAN *NewPxeDiscoverValid, OPTIONAL + BOOLEAN *NewPxeReplyReceived, OPTIONAL + BOOLEAN *NewPxeBisReplyReceived, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewDhcpDiscover, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewDhcpAck, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewProxyOffer, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewPxeDiscover, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewPxeReply, OPTIONAL + IN EFI_PXE_BASE_CODE_PACKET *NewPxeBisReply OPTIONAL + ); + +// +// PXE Base Code Protocol structure +// +#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000 + +// +// Revision defined in EFI1.1 +// +#define EFI_PXE_BASE_CODE_INTERFACE_REVISION EFI_PXE_BASE_CODE_PROTOCOL_REVISION + +/// +/// The EFI_PXE_BASE_CODE_PROTOCOL is used to control PXE-compatible devices. +/// An EFI_PXE_BASE_CODE_PROTOCOL will be layered on top of an +/// EFI_MANAGED_NETWORK_PROTOCOL protocol in order to perform packet level transactions. +/// The EFI_PXE_BASE_CODE_PROTOCOL handle also supports the +/// EFI_LOAD_FILE_PROTOCOL protocol. This provides a clean way to obtain control from the +/// boot manager if the boot path is from the remote device. +/// +struct _EFI_PXE_BASE_CODE_PROTOCOL { + /// + /// The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must + /// be backwards compatible. If a future version is not backwards compatible + /// it is not the same GUID. + /// + UINT64 Revision; + EFI_PXE_BASE_CODE_START Start; + EFI_PXE_BASE_CODE_STOP Stop; + EFI_PXE_BASE_CODE_DHCP Dhcp; + EFI_PXE_BASE_CODE_DISCOVER Discover; + EFI_PXE_BASE_CODE_MTFTP Mtftp; + EFI_PXE_BASE_CODE_UDP_WRITE UdpWrite; + EFI_PXE_BASE_CODE_UDP_READ UdpRead; + EFI_PXE_BASE_CODE_SET_IP_FILTER SetIpFilter; + EFI_PXE_BASE_CODE_ARP Arp; + EFI_PXE_BASE_CODE_SET_PARAMETERS SetParameters; + EFI_PXE_BASE_CODE_SET_STATION_IP SetStationIp; + EFI_PXE_BASE_CODE_SET_PACKETS SetPackets; + /// + /// The pointer to the EFI_PXE_BASE_CODE_MODE data for this device. + /// + EFI_PXE_BASE_CODE_MODE *Mode; +}; + +extern EFI_GUID gEfiPxeBaseCodeProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h new file mode 100644 index 0000000000..2640a1c2ba --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h @@ -0,0 +1,124 @@ +/** @file + It is invoked when the PXE Base Code Protocol is about to transmit, has received, + or is waiting to receive a packet. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in EFI Specification 1.10 + +**/ + +#ifndef _PXE_BASE_CODE_CALLBACK_H_ +#define _PXE_BASE_CODE_CALLBACK_H_ + +/// +/// Call Back Definitions. +/// +#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_GUID \ + { \ + 0x245dca21, 0xfb7b, 0x11d3, {0x8f, 0x01, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +/// +/// UEFI Revision Number Definition. +/// +#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION 0x00010000 + +/// +/// EFI 1.1 Revision Number defintion. +/// +#define EFI_PXE_BASE_CODE_CALLBACK_INTERFACE_REVISION \ + EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION + +/// +/// UEFI Protocol name. +/// +typedef struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL; + +/// +/// EFI1.1 Protocol name. +/// +typedef EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK; + +/// +/// Event type list for PXE Base Code Protocol function. +/// +typedef enum { + EFI_PXE_BASE_CODE_FUNCTION_FIRST, + EFI_PXE_BASE_CODE_FUNCTION_DHCP, + EFI_PXE_BASE_CODE_FUNCTION_DISCOVER, + EFI_PXE_BASE_CODE_FUNCTION_MTFTP, + EFI_PXE_BASE_CODE_FUNCTION_UDP_WRITE, + EFI_PXE_BASE_CODE_FUNCTION_UDP_READ, + EFI_PXE_BASE_CODE_FUNCTION_ARP, + EFI_PXE_BASE_CODE_FUNCTION_IGMP, + EFI_PXE_BASE_CODE_PXE_FUNCTION_LAST +} EFI_PXE_BASE_CODE_FUNCTION; + +/// +/// Callback status type. +/// +typedef enum { + EFI_PXE_BASE_CODE_CALLBACK_STATUS_FIRST, + EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, + EFI_PXE_BASE_CODE_CALLBACK_STATUS_ABORT, + EFI_PXE_BASE_CODE_CALLBACK_STATUS_LAST +} EFI_PXE_BASE_CODE_CALLBACK_STATUS; + +/** + Callback function that is invoked when the PXE Base Code Protocol is about to transmit, has + received, or is waiting to receive a packet. + + This function is invoked when the PXE Base Code Protocol is about to transmit, has received, + or is waiting to receive a packet. Parameters Function and Received specify the type of event. + Parameters PacketLen and Packet specify the packet that generated the event. If these fields + are zero and NULL respectively, then this is a status update callback. If the operation specified + by Function is to continue, then CALLBACK_STATUS_CONTINUE should be returned. If the operation + specified by Function should be aborted, then CALLBACK_STATUS_ABORT should be returned. Due to + the polling nature of UEFI device drivers, a callback function should not execute for more than 5 ms. + The SetParameters() function must be called after a Callback Protocol is installed to enable the + use of callbacks. + + @param This The pointer to the EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL instance. + @param Function The PXE Base Code Protocol function that is waiting for an event. + @param Received TRUE if the callback is being invoked due to a receive event. FALSE if + the callback is being invoked due to a transmit event. + @param PacketLen The length, in bytes, of Packet. This field will have a value of zero if + this is a wait for receive event. + @param Packet If Received is TRUE, a pointer to the packet that was just received; + otherwise a pointer to the packet that is about to be transmitted. + + @retval EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE if Function specifies a continue operation + @retval EFI_PXE_BASE_CODE_CALLBACK_STATUS_ABORT if Function specifies an abort operation + +**/ +typedef +EFI_PXE_BASE_CODE_CALLBACK_STATUS +(EFIAPI *EFI_PXE_CALLBACK)( + IN EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL *This, + IN EFI_PXE_BASE_CODE_FUNCTION Function, + IN BOOLEAN Received, + IN UINT32 PacketLen, + IN EFI_PXE_BASE_CODE_PACKET *Packet OPTIONAL + ); + +/// +/// Protocol that is invoked when the PXE Base Code Protocol is about +/// to transmit, has received, or is waiting to receive a packet. +/// +struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL { + /// + /// The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must + /// be backwards compatible. If a future version is not backwards compatible + /// it is not the same GUID. + /// + UINT64 Revision; + EFI_PXE_CALLBACK Callback; +}; + +extern EFI_GUID gEfiPxeBaseCodeCallbackProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RamDisk.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RamDisk.h new file mode 100644 index 0000000000..9861ec64e6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RamDisk.h @@ -0,0 +1,100 @@ +/** @file + This file defines the EFI RAM Disk Protocol. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.6 + +**/ + +#ifndef __RAM_DISK_PROTOCOL_H__ +#define __RAM_DISK_PROTOCOL_H__ + +// +// EFI RAM Disk Protocol GUID value +// +#define EFI_RAM_DISK_PROTOCOL_GUID \ + { 0xab38a0df, 0x6873, 0x44a9, { 0x87, 0xe6, 0xd4, 0xeb, 0x56, 0x14, 0x84, 0x49 }}; + +// +// Forward reference for pure ANSI compatability +// +typedef struct _EFI_RAM_DISK_PROTOCOL EFI_RAM_DISK_PROTOCOL; + +/** + Register a RAM disk with specified address, size and type. + + @param[in] RamDiskBase The base address of registered RAM disk. + @param[in] RamDiskSize The size of registered RAM disk. + @param[in] RamDiskType The type of registered RAM disk. The GUID can be + any of the values defined in section 9.3.6.9, or a + vendor defined GUID. + @param[in] ParentDevicePath + Pointer to the parent device path. If there is no + parent device path then ParentDevicePath is NULL. + @param[out] DevicePath On return, points to a pointer to the device path + of the RAM disk device. + If ParentDevicePath is not NULL, the returned + DevicePath is created by appending a RAM disk node + to the parent device path. If ParentDevicePath is + NULL, the returned DevicePath is a RAM disk device + path without appending. This function is + responsible for allocating the buffer DevicePath + with the boot service AllocatePool(). + + @retval EFI_SUCCESS The RAM disk is registered successfully. + @retval EFI_INVALID_PARAMETER DevicePath or RamDiskType is NULL. + RamDiskSize is 0. + @retval EFI_ALREADY_STARTED A Device Path Protocol instance to be created + is already present in the handle database. + @retval EFI_OUT_OF_RESOURCES The RAM disk register operation fails due to + resource limitation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RAM_DISK_REGISTER_RAMDISK) ( + IN UINT64 RamDiskBase, + IN UINT64 RamDiskSize, + IN EFI_GUID *RamDiskType, + IN EFI_DEVICE_PATH *ParentDevicePath OPTIONAL, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Unregister a RAM disk specified by DevicePath. + + @param[in] DevicePath A pointer to the device path that describes a RAM + Disk device. + + @retval EFI_SUCCESS The RAM disk is unregistered successfully. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_UNSUPPORTED The device specified by DevicePath is not a + valid ramdisk device path and not supported + by the driver. + @retval EFI_NOT_FOUND The RAM disk pointed by DevicePath doesn't + exist. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RAM_DISK_UNREGISTER_RAMDISK) ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ); + +/// +/// RAM Disk Protocol structure. +/// +struct _EFI_RAM_DISK_PROTOCOL { + EFI_RAM_DISK_REGISTER_RAMDISK Register; + EFI_RAM_DISK_UNREGISTER_RAMDISK Unregister; +}; + +/// +/// RAM Disk Protocol GUID variable. +/// +extern EFI_GUID gEfiRamDiskProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RealTimeClock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RealTimeClock.h new file mode 100644 index 0000000000..a80ffc3058 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RealTimeClock.h @@ -0,0 +1,30 @@ +/** @file + Real Time clock Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + This code abstracts time and data functions. Used to provide + Time and date related EFI runtime services. + + The GetTime (), SetTime (), GetWakeupTime (), and SetWakeupTime () UEFI 2.0 + services are added to the EFI system table and the + EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID protocol is registered with a NULL + pointer. + + No CRC of the EFI system table is required, since that is done in the DXE core. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_REAL_TIME_CLOCK_H__ +#define __ARCH_PROTOCOL_REAL_TIME_CLOCK_H__ + +/// +/// Global ID for the Real Time Clock Architectural Protocol +/// +#define EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID \ + { 0x27CFAC87, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } } + +extern EFI_GUID gEfiRealTimeClockArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RedfishDiscover.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RedfishDiscover.h new file mode 100644 index 0000000000..284e4a3b01 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RedfishDiscover.h @@ -0,0 +1,193 @@ +/** @file + This file defines the EFI Redfish Discover Protocol interface. + + (C) Copyright 2021 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Some corrections and revises are added to UEFI Specification 2.9. + - This Protocol is introduced in UEFI Specification 2.8. + +**/ + +#ifndef EFI_REDFISH_DISCOVER_PROTOCOL_H_ +#define EFI_REDFISH_DISCOVER_PROTOCOL_H_ + +// +// GUID definitions +// +#define EFI_REDFISH_DISCOVER_PROTOCOL_GUID \ + { \ + 0x5db12509, 0x4550, 0x4347, { 0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f } \ + } + +#define REDFISH_DISCOVER_TOKEN_SIGNATURE SIGNATURE_32 ('R', 'F', 'T', 'S') + +typedef UINT32 EFI_REDFISH_DISCOVER_FLAG; +#define EFI_REDFISH_DISCOVER_HOST_INTERFACE 0x00000001 ///< Discover Redfish server reported in SMBIOS 42h. +#define EFI_REDFISH_DISCOVER_SSDP 0x00000002 ///< Discover Redfish server using UPnP Http search method. +#define EFI_REDFISH_DISCOVER_SSDP_UDP6 0x00000004 ///< Use UDP version 6. +#define EFI_REDFISH_DISCOVER_KEEP_ALIVE 0x00000008 ///< Keep to send UPnP Search in the duration indicated in + ///< EFI_REDFISH_DISCOVER_DURATION_MASK. +#define EFI_REDFISH_DISCOVER_RENEW 0x00000010 ///< Set this bit to indicate this function to notify the caller + ///< a list of all Redfish servers it found. Otherwise, this fucntion + ///< just notify the caller new found Redfish servers. + ///< +#define EFI_REDFISH_DISCOVER_VALIDATION 0x80000000 ///< Validate Redfish service for host interface instance. +#define EFI_REDFISH_DISCOVER_DURATION_MASK 0x0f000000 ///< 2 to the Power of Duration. The valid value of duration is between + ///< 3 to 15. The corresponding duration is 8 to 2^15 seconds. + ///< Duration is only valid when EFI_REDFISH_DISCOVER_KEEP_ALIVE + ///< is set to 1. +typedef struct _EFI_REDFISH_DISCOVER_PROTOCOL EFI_REDFISH_DISCOVER_PROTOCOL; + +typedef struct { + EFI_HANDLE RedfishRestExHandle; ///< REST EX EFI handle associated with this Redfish service. + BOOLEAN IsUdp6; ///< Indicates it's IP versino 6. + EFI_IP_ADDRESS RedfishHostIpAddress; ///< IP address of Redfish service. + UINTN RedfishVersion; ///< Redfish service version. + CHAR16 *Location; ///< Redfish service location. + CHAR16 *Uuid; ///< Redfish service UUID. + CHAR16 *Os; ///< Redfish service OS. + CHAR16 *OsVersion; ///< Redfish service OS version. + CHAR16 *Product; ///< Redfish service product name. + CHAR16 *ProductVer; ///< Redfish service product version. + BOOLEAN UseHttps; ///< Using HTTPS. +} EFI_REDFISH_DISCOVERED_INFORMATION; + +typedef struct { + EFI_STATUS Status; ///< Status of Redfish service discovery. + EFI_REDFISH_DISCOVERED_INFORMATION Information; ///< Redfish service discovered. +} EFI_REDFISH_DISCOVERED_INSTANCE; + +typedef struct { + UINTN NumberOfServiceFound; ///< Must be 0 when pass to Acquire (). + EFI_REDFISH_DISCOVERED_INSTANCE *RedfishInstances; ///< Must be NULL when pass to Acquire (). +} EFI_REDFISH_DISCOVERED_LIST; + +typedef struct { + EFI_MAC_ADDRESS MacAddress; ///< MAC address of network interfase to discover Redfish service. + BOOLEAN IsIpv6; ///< Indicates it's IP versino 6. + EFI_IP_ADDRESS SubnetId; ///< Subnet ID. + UINT8 SubnetPrefixLength; ///< Subnet prefix-length for IPv4 and IPv6. + UINT16 VlanId; ///< VLAN ID. +} EFI_REDFISH_DISCOVER_NETWORK_INTERFACE; + +typedef struct { + UINT32 Signature; ///< Token signature. + EFI_REDFISH_DISCOVERED_LIST DiscoverList; ///< The memory of EFI_REDFISH_DISCOVERED_LIST is + ///< allocated by Acquire() and freed when caller invoke Release(). + EFI_EVENT Event; ///< The TPL_CALLBACK event to be notified when Redfish services + ///< are discovered or any errors occurred during discovery. + UINTN Timeout; ///< The timeout value declared in EFI_REDFISH_DISCOVERED_TOKEN + ///< determines the seconds to drop discover process. + ///< Basically, the nearby Redfish services must response in >=1 + ///< and <= 5 seconds. The valid timeout value used to have + ///< asynchronous discovery is >= 1 and <= 5 seconds. Set the + ///< timeout to zero means to discover Redfish service synchronously. + ///< Event in token is created by caller to listen the Reefish services + ///< found by Acquire(). +} EFI_REDFISH_DISCOVERED_TOKEN; + +/** + This function gets the NIC list which Redfish discover protocol + can discover Redfish service on it. + + @param[in] This EFI_REDFISH_DISCOVER_PROTOCOL instance. + @param[in] ImageHandle EFI Image handle request the NIC list, + @param[out] NumberOfNetworkInterfaces Number of NICs can do Redfish service discovery. + @param[out] NetworkInterfaces NIC instances. It's an array of instance. The number of entries + in array is indicated by NumberOfNetworkInterfaces. + Caller has to release the memory + allocated by Redfish discover protocol. + + @retval EFI_SUCCESS REST EX instances of discovered Redfish are released. + @retval Others Fail to remove the entry + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REDFISH_DISCOVER_NETWORK_LIST)( + IN EFI_REDFISH_DISCOVER_PROTOCOL *This, + IN EFI_HANDLE ImageHandle, + OUT UINTN *NumberOfNetworkInterfaces, + OUT EFI_REDFISH_DISCOVER_NETWORK_INTERFACE **NetworkInterfaces +); + +/** + This function acquires Redfish services by discovering static Redfish setting + according to Redfish Host Interface or through SSDP. Returns a list of EFI + handles in EFI_REDFISH_DISCOVERED_LIST. Each of EFI handle has cooresponding + EFI REST EX instance installed on it. Each REST EX isntance is a child instance which + created through EFI REST EX serivce protoocl for communicating with specific + Redfish service. + + @param[in] This EFI_REDFISH_DISCOVER_PROTOCOL instance. + @param[in] ImageHandle EFI image owns these Redfish service instances. + @param[in] TargetNetworkInterface Target NIC to do the discovery. + NULL means discover Redfish service on all NICs on platform. + @param[in] Flags Redfish service discover flags. + @param[in] Token EFI_REDFISH_DISCOVERED_TOKEN instance. + The memory of EFI_REDFISH_DISCOVERED_LIST and the strings in + EFI_REDFISH_DISCOVERED_INFORMATION are all allocated by Acquire() + and must be freed when caller invoke Release(). + + @retval EFI_SUCCESS REST EX instance of discovered Redfish services are returned. + @retval EFI_INVALID_PARAMETERS ImageHandle == NULL, Flags == 0, Token == NULL, Token->Timeout > 5, + or Token->Event == NULL. + @retval Others Fail acquire Redfish services. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE)( + IN EFI_REDFISH_DISCOVER_PROTOCOL *This, + IN EFI_HANDLE ImageHandle, + IN EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL, + IN EFI_REDFISH_DISCOVER_FLAG Flags, + IN EFI_REDFISH_DISCOVERED_TOKEN *Token +); + +/** + This function aborts Redfish service discovery on the given network interface. + + @param[in] This EFI_REDFISH_DISCOVER_PROTOCOL instance. + @param[in] TargetNetworkInterface Target NIC to do the discovery. + + @retval EFI_SUCCESS REST EX instance of discovered Redfish services are returned. + @retval Others Fail to abort Redfish service discovery. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REDFISH_DISCOVER_ABORT_ACQUIRE)( + IN EFI_REDFISH_DISCOVER_PROTOCOL *This, + IN EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL +); + +/** + This function releases Redfish services found by RedfishServiceAcquire(). + + @param[in] This EFI_REDFISH_DISCOVER_PROTOCOL instance. + @param[in] List The Redfish service to release. + + @retval EFI_SUCCESS REST EX instances of discovered Redfish are released. + @retval Others Fail to remove the entry + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REDFISH_DISCOVER_RELEASE_SERVICE)( + IN EFI_REDFISH_DISCOVER_PROTOCOL *This, + IN EFI_REDFISH_DISCOVERED_LIST *List +); + +struct _EFI_REDFISH_DISCOVER_PROTOCOL { + EFI_REDFISH_DISCOVER_NETWORK_LIST GetNetworkInterfaceList; + EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE AcquireRedfishService; + EFI_REDFISH_DISCOVER_ABORT_ACQUIRE AbortAcquireRedfishService; + EFI_REDFISH_DISCOVER_RELEASE_SERVICE ReleaseRedfishService; +}; + +extern EFI_GUID gEfiRedfishDiscoverProtocolGuid; +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RegularExpressionProtocol.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RegularExpressionProtocol.h new file mode 100644 index 0000000000..4baf644b8b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RegularExpressionProtocol.h @@ -0,0 +1,175 @@ +/** @file + This section defines the Regular Expression Protocol. This protocol isused to match + Unicode strings against Regular Expression patterns. + +Copyright (c) 2015-2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + +**/ + +#ifndef __REGULAR_EXPRESSION_PROTOCOL_H__ +#define __REGULAR_EXPRESSION_PROTOCOL_H__ + +#define EFI_REGULAR_EXPRESSION_PROTOCOL_GUID \ + { \ + 0xB3F79D9A, 0x436C, 0xDC11, {0xB0, 0x52, 0xCD, 0x85, 0xDF, 0x52, 0x4C, 0xE6 } \ + } + +#define EFI_REGEX_SYNTAX_TYPE_POSIX_EXTENDED_GUID \ + { \ + 0x5F05B20F, 0x4A56, 0xC231, {0xFA, 0x0B, 0xA7, 0xB1, 0xF1, 0x10, 0x04, 0x1D } \ + } + +#define EFI_REGEX_SYNTAX_TYPE_PERL_GUID \ + { \ + 0x63E60A51, 0x497D, 0xD427, {0xC4, 0xA5, 0xB8, 0xAB, 0xDC, 0x3A, 0xAE, 0xB6 } \ + } + +#define EFI_REGEX_SYNTAX_TYPE_ECMA_262_GUID \ + { \ + 0x9A473A4A, 0x4CEB, 0xB95A, {0x41, 0x5E, 0x5B, 0xA0, 0xBC, 0x63, 0x9B, 0x2E } \ + } + +typedef struct _EFI_REGULAR_EXPRESSION_PROTOCOL EFI_REGULAR_EXPRESSION_PROTOCOL; + + +typedef struct { + CONST CHAR16 *CapturePtr; // Pointer to the start of the captured sub-expression + // within matched String. + + UINTN Length; // Length of captured sub-expression. +} EFI_REGEX_CAPTURE; + +typedef EFI_GUID EFI_REGEX_SYNTAX_TYPE; + +// +// Protocol member functions +// +/** + Returns information about the regular expression syntax types supported + by the implementation. + + This A pointer to the EFI_REGULAR_EXPRESSION_PROTOCOL + instance. + + RegExSyntaxTypeListSize On input, the size in bytes of RegExSyntaxTypeList. + On output with a return code of EFI_SUCCESS, the + size in bytes of the data returned in + RegExSyntaxTypeList. On output with a return code + of EFI_BUFFER_TOO_SMALL, the size of + RegExSyntaxTypeListrequired to obtain the list. + + RegExSyntaxTypeList A caller-allocated memory buffer filled by the + driver with one EFI_REGEX_SYNTAX_TYPEelement + for each supported Regular expression syntax + type. The list must not change across multiple + calls to the same driver. The first syntax + type in the list is the default type for the + driver. + + @retval EFI_SUCCESS The regular expression syntax types list + was returned successfully. + @retval EFI_UNSUPPORTED The service is not supported by this driver. + @retval EFI_DEVICE_ERROR The list of syntax types could not be + retrieved due to a hardware or firmware error. + @retval EFI_BUFFER_TOO_SMALL The buffer RegExSyntaxTypeList is too small + to hold the result. + @retval EFI_INVALID_PARAMETER RegExSyntaxTypeListSize is NULL + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGULAR_EXPRESSION_GET_INFO) ( + IN EFI_REGULAR_EXPRESSION_PROTOCOL *This, + IN OUT UINTN *RegExSyntaxTypeListSize, + OUT EFI_REGEX_SYNTAX_TYPE *RegExSyntaxTypeList + ); + +/** + Checks if the input string matches to the regular expression pattern. + + This A pointer to the EFI_REGULAR_EXPRESSION_PROTOCOL instance. + Type EFI_REGULAR_EXPRESSION_PROTOCOL is defined in Section + XYZ. + + String A pointer to a NULL terminated string to match against the + regular expression string specified by Pattern. + + Pattern A pointer to a NULL terminated string that represents the + regular expression. + + SyntaxType A pointer to the EFI_REGEX_SYNTAX_TYPE that identifies the + regular expression syntax type to use. May be NULL in which + case the function will use its default regular expression + syntax type. + + Result On return, points to TRUE if String fully matches against + the regular expression Pattern using the regular expression + SyntaxType. Otherwise, points to FALSE. + + Captures A Pointer to an array of EFI_REGEX_CAPTURE objects to receive + the captured groups in the event of a match. The full + sub-string match is put in Captures[0], and the results of N + capturing groups are put in Captures[1:N]. If Captures is + NULL, then this function doesn't allocate the memory for the + array and does not build up the elements. It only returns the + number of matching patterns in CapturesCount. If Captures is + not NULL, this function returns a pointer to an array and + builds up the elements in the array. CapturesCount is also + updated to the number of matching patterns found. It is the + caller's responsibility to free the memory pool in Captures + and in each CapturePtr in the array elements. + + CapturesCount On output, CapturesCount is the number of matching patterns + found in String. Zero means no matching patterns were found + in the string. + + @retval EFI_SUCCESS The regular expression string matching + completed successfully. + @retval EFI_UNSUPPORTED The regular expression syntax specified by + SyntaxTypeis not supported by this driver. + @retval EFI_DEVICE_ERROR The regular expression string matching + failed due to a hardware or firmware error. + @retval EFI_INVALID_PARAMETER String, Pattern, Result, or CapturesCountis + NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGULAR_EXPRESSION_MATCH) ( + IN EFI_REGULAR_EXPRESSION_PROTOCOL *This, + IN CHAR16 *String, + IN CHAR16 *Pattern, + IN EFI_REGEX_SYNTAX_TYPE *SyntaxType, OPTIONAL + OUT BOOLEAN *Result, + OUT EFI_REGEX_CAPTURE **Captures, OPTIONAL + OUT UINTN *CapturesCount + ); + +struct _EFI_REGULAR_EXPRESSION_PROTOCOL { + EFI_REGULAR_EXPRESSION_MATCH MatchString; + EFI_REGULAR_EXPRESSION_GET_INFO GetInfo; +} ; + +extern EFI_GUID gEfiRegularExpressionProtocolGuid; + +// +// For regular expression rules specified in the POSIX Extended Regular +// Expression (ERE) Syntax: +// +extern EFI_GUID gEfiRegexSyntaxTypePosixExtendedGuid; + +// +// For regular expression rules specifiedin the ECMA 262 Specification +// +extern EFI_GUID gEfiRegexSyntaxTypeEcma262Guid; + +// +// For regular expression rules specified in the Perl standard: +// +extern EFI_GUID gEfiRegexSyntaxTypePerlGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ReportStatusCodeHandler.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ReportStatusCodeHandler.h new file mode 100644 index 0000000000..7d2fceed55 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ReportStatusCodeHandler.h @@ -0,0 +1,91 @@ +/** @file + This protocol provide registering and unregistering services to status code + consumers while in DXE. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.2. + +**/ + +#ifndef __REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ +#define __REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ + +#define EFI_RSC_HANDLER_PROTOCOL_GUID \ + { \ + 0x86212936, 0xe76, 0x41c8, {0xa0, 0x3a, 0x2a, 0xf2, 0xfc, 0x1c, 0x39, 0xe2} \ + } + +typedef +EFI_STATUS +(EFIAPI *EFI_RSC_HANDLER_CALLBACK)( + IN EFI_STATUS_CODE_TYPE CodeType, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN EFI_GUID *CallerId, + IN EFI_STATUS_CODE_DATA *Data +); + +/** + Register the callback function for ReportStatusCode() notification. + + When this function is called the function pointer is added to an internal list and any future calls to + ReportStatusCode() will be forwarded to the Callback function. During the bootservices, + this is the callback for which this service can be invoked. The report status code router + will create an event such that the callback function is only invoked at the TPL for which it was + registered. The entity that registers for the callback should also register for an event upon + generation of exit boot services and invoke the unregister service. + If the handler does not have a TPL dependency, it should register for a callback at TPL high. The + router infrastructure will support making callbacks at runtime, but the caller for runtime invocation + must meet the following criteria: + 1. must be a runtime driver type so that its memory is not reclaimed + 2. not unregister at exit boot services so that the router will still have its callback address + 3. the caller must be self-contained (eg. Not call out into any boot-service interfaces) and be + runtime safe, in general. + + @param[in] Callback A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is called when + a call to ReportStatusCode() occurs. + @param[in] Tpl TPL at which callback can be safely invoked. + + @retval EFI_SUCCESS Function was successfully registered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_OUT_OF_RESOURCES The internal buffer ran out of space. No more functions can be + registered. + @retval EFI_ALREADY_STARTED The function was already registered. It can't be registered again. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RSC_HANDLER_REGISTER)( + IN EFI_RSC_HANDLER_CALLBACK Callback, + IN EFI_TPL Tpl +); + +/** + Remove a previously registered callback function from the notification list. + + A callback function must be unregistered before it is deallocated. It is important that any registered + callbacks that are not runtime complaint be unregistered when ExitBootServices() is called. + + @param[in] Callback A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is to be + unregistered. + + @retval EFI_SUCCESS The function was successfully unregistered. + @retval EFI_INVALID_PARAMETER The callback function was NULL. + @retval EFI_NOT_FOUND The callback function was not found to be unregistered. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RSC_HANDLER_UNREGISTER)( + IN EFI_RSC_HANDLER_CALLBACK Callback +); + +typedef struct { + EFI_RSC_HANDLER_REGISTER Register; + EFI_RSC_HANDLER_UNREGISTER Unregister; +} EFI_RSC_HANDLER_PROTOCOL; + +extern EFI_GUID gEfiRscHandlerProtocolGuid; + +#endif // __REPORT_STATUS_CODE_HANDLER_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Reset.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Reset.h new file mode 100644 index 0000000000..6b96b20f72 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Reset.h @@ -0,0 +1,25 @@ +/** @file + Reset Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + Used to provide ResetSystem runtime services + + The ResetSystem () UEFI 2.0 service is added to the EFI system table and the + EFI_RESET_ARCH_PROTOCOL_GUID protocol is registered with a NULL pointer. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_RESET_H__ +#define __ARCH_PROTOCOL_RESET_H__ + +/// +/// Global ID for the Reset Architectural Protocol +/// +#define EFI_RESET_ARCH_PROTOCOL_GUID \ + { 0x27CFAC88, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } } + +extern EFI_GUID gEfiResetArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ResetNotification.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ResetNotification.h new file mode 100644 index 0000000000..171fca8042 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ResetNotification.h @@ -0,0 +1,80 @@ +/** @file + EFI Reset Notification Protocol as defined in UEFI 2.7. + This protocol provides services to register for a notification when ResetSystem is called. + + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __EFI_RESET_NOTIFICATION_H__ +#define __EFI_RESET_NOTIFICATION_H__ + +#define EFI_RESET_NOTIFICATION_PROTOCOL_GUID \ + { 0x9da34ae0, 0xeaf9, 0x4bbf, { 0x8e, 0xc3, 0xfd, 0x60, 0x22, 0x6c, 0x44, 0xbe } } + +typedef struct _EFI_RESET_NOTIFICATION_PROTOCOL EFI_RESET_NOTIFICATION_PROTOCOL; + +/** + Register a notification function to be called when ResetSystem() is called. + + The RegisterResetNotify() function registers a notification function that is called when + ResetSystem()is called and prior to completing the reset of the platform. + The registered functions must not perform a platform reset themselves. These + notifications are intended only for the notification of components which may need some + special-purpose maintenance prior to the platform resetting. + The list of registered reset notification functions are processed if ResetSystem()is called + before ExitBootServices(). The list of registered reset notification functions is ignored if + ResetSystem()is called after ExitBootServices(). + + @param[in] This A pointer to the EFI_RESET_NOTIFICATION_PROTOCOL instance. + @param[in] ResetFunction Points to the function to be called when a ResetSystem() is executed. + + @retval EFI_SUCCESS The reset notification function was successfully registered. + @retval EFI_INVALID_PARAMETER ResetFunction is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register the reset notification function. + @retval EFI_ALREADY_STARTED The reset notification function specified by ResetFunction has already been registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_RESET_NOTIFY) ( + IN EFI_RESET_NOTIFICATION_PROTOCOL *This, + IN EFI_RESET_SYSTEM ResetFunction +); + +/** + Unregister a notification function. + + The UnregisterResetNotify() function removes the previously registered + notification using RegisterResetNotify(). + + @param[in] This A pointer to the EFI_RESET_NOTIFICATION_PROTOCOL instance. + @param[in] ResetFunction The pointer to the ResetFunction being unregistered. + + @retval EFI_SUCCESS The reset notification function was unregistered. + @retval EFI_INVALID_PARAMETER ResetFunction is NULL. + @retval EFI_INVALID_PARAMETER The reset notification function specified by ResetFunction was not previously + registered using RegisterResetNotify(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UNREGISTER_RESET_NOTIFY) ( + IN EFI_RESET_NOTIFICATION_PROTOCOL *This, + IN EFI_RESET_SYSTEM ResetFunction +); + +struct _EFI_RESET_NOTIFICATION_PROTOCOL { + EFI_REGISTER_RESET_NOTIFY RegisterResetNotify; + EFI_UNREGISTER_RESET_NOTIFY UnregisterResetNotify; +}; + + +extern EFI_GUID gEfiResetNotificationProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rest.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rest.h new file mode 100644 index 0000000000..57ab880667 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rest.h @@ -0,0 +1,88 @@ +/** @file + This file defines the EFI REST Protocol interface. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_REST_PROTOCOL_H__ +#define __EFI_REST_PROTOCOL_H__ + +#include + +#define EFI_REST_PROTOCOL_GUID \ + { \ + 0x0db48a36, 0x4e54, 0xea9c, {0x9b, 0x09, 0x1e, 0xa5, 0xbe, 0x3a, 0x66, 0x0b } \ + } + +typedef struct _EFI_REST_PROTOCOL EFI_REST_PROTOCOL; + +/** + Provides a simple HTTP-like interface to send and receive resources from a REST + service. + + The SendReceive() function sends an HTTP request to this REST service, and returns a + response when the data is retrieved from the service. RequestMessage contains the HTTP + request to the REST resource identified by RequestMessage.Request.Url. The + ResponseMessage is the returned HTTP response for that request, including any HTTP + status. + + @param[in] This Pointer to EFI_REST_PROTOCOL instance for a particular + REST service. + @param[in] RequestMessage Pointer to the HTTP request data for this resource. + @param[out] ResponseMessage Pointer to the HTTP response data obtained for this + requested. + + @retval EFI_SUCCESS Operation succeeded. + @retval EFI_INVALID_PARAMETER This, RequestMessage, or ResponseMessage are NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_SEND_RECEIVE) ( + IN EFI_REST_PROTOCOL *This, + IN EFI_HTTP_MESSAGE *RequestMessage, + OUT EFI_HTTP_MESSAGE *ResponseMessage + ); + +/** + The GetServiceTime() function is an optional interface to obtain the current time from + this REST service instance. If this REST service does not support retrieving the time, + this function returns EFI_UNSUPPORTED. + + @param[in] This Pointer to EFI_REST_PROTOCOL instance. + @param[out] Time A pointer to storage to receive a snapshot of the + current time of the REST service. + + @retval EFI_SUCCESS Operation succeeded + @retval EFI_INVALID_PARAMETER This or Time are NULL. + @retval EFI_UNSUPPORTED The RESTful service does not support returning the + time. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_GET_TIME) ( + IN EFI_REST_PROTOCOL *This, + OUT EFI_TIME *Time + ); + +/// +/// The EFI REST protocol is designed to be used by EFI drivers and applications to send +/// and receive resources from a RESTful service. This protocol abstracts REST +/// (Representational State Transfer) client functionality. This EFI protocol could be +/// implemented to use an underlying EFI HTTP protocol, or it could rely on other +/// interfaces that abstract HTTP access to the resources. +/// +struct _EFI_REST_PROTOCOL { + EFI_REST_SEND_RECEIVE SendReceive; + EFI_REST_GET_TIME GetServiceTime; +}; + +extern EFI_GUID gEfiRestProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestEx.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestEx.h new file mode 100644 index 0000000000..c0cdde3cb0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestEx.h @@ -0,0 +1,390 @@ +/** @file + This file defines the EFI REST EX Protocol interface. It is + split into the following two main sections. + + - REST EX Service Binding Protocol + - REST EX Protocol + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ (C) Copyright 2020 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.8 + +**/ + +#ifndef EFI_REST_EX_PROTOCOL_H_ +#define EFI_REST_EX_PROTOCOL_H_ + +#include + +// +//GUID definitions +// +#define EFI_REST_EX_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x456bbe01, 0x99d0, 0x45ea, {0xbb, 0x5f, 0x16, 0xd8, 0x4b, 0xed, 0xc5, 0x59 } \ + } + +#define EFI_REST_EX_PROTOCOL_GUID \ + { \ + 0x55648b91, 0xe7d, 0x40a3, {0xa9, 0xb3, 0xa8, 0x15, 0xd7, 0xea, 0xdf, 0x97 } \ + } + +typedef struct _EFI_REST_EX_PROTOCOL EFI_REST_EX_PROTOCOL; + +//******************************************************* +//EFI_REST_EX_SERVICE_INFO_VER +//******************************************************* +typedef struct { + UINT8 Major; + UINT8 Minor; +} EFI_REST_EX_SERVICE_INFO_VER; + +//******************************************************* +//EFI_REST_EX_SERVICE_INFO_HEADER +//******************************************************* +typedef struct { + UINT32 Length; + EFI_REST_EX_SERVICE_INFO_VER RestServiceInfoVer; +} EFI_REST_EX_SERVICE_INFO_HEADER; + +//******************************************************* +// EFI_REST_EX_SERVICE_TYPE +//******************************************************* +typedef enum { + EfiRestExServiceUnspecific = 1, + EfiRestExServiceRedfish, + EfiRestExServiceOdata, + EfiRestExServiceVendorSpecific = 0xff, + EfiRestExServiceTypeMax +} EFI_REST_EX_SERVICE_TYPE; + +//******************************************************* +// EFI_REST_EX_SERVICE_ACCESS_MODE +//******************************************************* +typedef enum { + EfiRestExServiceInBandAccess = 1, + EfiRestExServiceOutOfBandAccess = 2, + EfiRestExServiceModeMax +} EFI_REST_EX_SERVICE_ACCESS_MODE; + +//******************************************************* +// EFI_REST_EX_CONFIG_TYPE +//******************************************************* +typedef enum { + EfiRestExConfigHttp, + EfiRestExConfigUnspecific, + EfiRestExConfigTypeMax +} EFI_REST_EX_CONFIG_TYPE; + +//******************************************************* +//EFI_REST_EX_SERVICE_INFO v1.0 +//******************************************************* +typedef struct { + EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader; + EFI_REST_EX_SERVICE_TYPE RestServiceType; + EFI_REST_EX_SERVICE_ACCESS_MODE RestServiceAccessMode; + EFI_GUID VendorRestServiceName; + UINT32 VendorSpecificDataLength; + UINT8 *VendorSpecifcData; + EFI_REST_EX_CONFIG_TYPE RestExConfigType; + UINT8 RestExConfigDataLength; +} EFI_REST_EX_SERVICE_INFO_V_1_0; + +//******************************************************* +//EFI_REST_EX_SERVICE_INFO +//******************************************************* +typedef union { + EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader; + EFI_REST_EX_SERVICE_INFO_V_1_0 EfiRestExServiceInfoV10; +} EFI_REST_EX_SERVICE_INFO; + +//******************************************************* +// EFI_REST_EX_HTTP_CONFIG_DATA +//******************************************************* +typedef struct { + EFI_HTTP_CONFIG_DATA HttpConfigData; + UINT32 SendReceiveTimeout; +} EFI_REST_EX_HTTP_CONFIG_DATA; + +//******************************************************* +//EFI_REST_EX_CONFIG_DATA +//******************************************************* +typedef UINT8 *EFI_REST_EX_CONFIG_DATA; + +//******************************************************* +//EFI_REST_EX_TOKEN +//******************************************************* +typedef struct { + EFI_EVENT Event; + EFI_STATUS Status; + EFI_HTTP_MESSAGE *ResponseMessage; +} EFI_REST_EX_TOKEN; + +/** + Provides a simple HTTP-like interface to send and receive resources from a REST service. + + The SendReceive() function sends an HTTP request to this REST service, and returns a + response when the data is retrieved from the service. RequestMessage contains the HTTP + request to the REST resource identified by RequestMessage.Request.Url. The + ResponseMessage is the returned HTTP response for that request, including any HTTP + status. + + @param[in] This Pointer to EFI_REST_EX_PROTOCOL instance for a particular + REST service. + @param[in] RequestMessage Pointer to the HTTP request data for this resource + @param[out] ResponseMessage Pointer to the HTTP response data obtained for this requested. + + @retval EFI_SUCCESS operation succeeded. + @retval EFI_INVALID_PARAMETER This, RequestMessage, or ResponseMessage are NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_SEND_RECEIVE)( + IN EFI_REST_EX_PROTOCOL *This, + IN EFI_HTTP_MESSAGE *RequestMessage, + OUT EFI_HTTP_MESSAGE *ResponseMessage + ); + +/** + Obtain the current time from this REST service instance. + + The GetServiceTime() function is an optional interface to obtain the current time from + this REST service instance. If this REST service does not support to retrieve the time, + this function returns EFI_UNSUPPORTED. This function must returns EFI_UNSUPPORTED if + EFI_REST_EX_SERVICE_TYPE returned in EFI_REST_EX_SERVICE_INFO from GetService() is + EFI_REST_EX_SERVICE_UNSPECIFIC. + + @param[in] This Pointer to EFI_REST_EX_PROTOCOL instance for a particular + REST service. + @param[out] Time A pointer to storage to receive a snapshot of the current time of + the REST service. + + @retval EFI_SUCCESS operation succeeded. + @retval EFI_INVALID_PARAMETER This or Time are NULL. + @retval EFI_UNSUPPORTED The RESTful service does not support returning the time. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY The configuration of this instance is not set yet. Configure() must + be executed and returns successfully prior to invoke this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_GET_TIME)( + IN EFI_REST_EX_PROTOCOL *This, + OUT EFI_TIME *Time + ); + +/** + This function returns the information of REST service provided by this EFI REST EX driver instance. + + The information such as the type of REST service and the access mode of REST EX driver instance + (In-band or Out-of-band) are described in EFI_REST_EX_SERVICE_INFO structure. For the vendor-specific + REST service, vendor-specific REST service information is returned in VendorSpecifcData. + REST EX driver designer is well know what REST service this REST EX driver instance intends to + communicate with. The designer also well know this driver instance is used to talk to BMC through + specific platform mechanism or talk to REST server through UEFI HTTP protocol. REST EX driver is + responsible to fill up the correct information in EFI_REST_EX_SERVICE_INFO. EFI_REST_EX_SERVICE_INFO + is referred by EFI REST clients to pickup the proper EFI REST EX driver instance to get and set resource. + GetService() is a basic and mandatory function which must be able to use even Configure() is not invoked + in previously. + + @param[in] This Pointer to EFI_REST_EX_PROTOCOL instance for a particular + REST service. + @param[out] RestExServiceInfo Pointer to receive a pointer to EFI_REST_EX_SERVICE_INFO structure. The + format of EFI_REST_EX_SERVICE_INFO is version controlled for the future + extension. The version of EFI_REST_EX_SERVICE_INFO structure is returned + in the header within this structure. EFI REST client refers to the correct + format of structure according to the version number. The pointer to + EFI_REST_EX_SERVICE_INFO is a memory block allocated by EFI REST EX driver + instance. That is caller's responsibility to free this memory when this + structure is no longer needed. Refer to Related Definitions below for the + definitions of EFI_REST_EX_SERVICE_INFO structure. + + @retval EFI_SUCCESS EFI_REST_EX_SERVICE_INFO is returned in RestExServiceInfo. This function + is not supported in this REST EX Protocol driver instance. + @retval EFI_UNSUPPORTED This function is not supported in this REST EX Protocol driver instance. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_EX_GET_SERVICE)( + IN EFI_REST_EX_PROTOCOL *This, + OUT EFI_REST_EX_SERVICE_INFO **RestExServiceInfo + ); + +/** + This function returns operational configuration of current EFI REST EX child instance. + + This function returns the current configuration of EFI REST EX child instance. The format of + operational configuration depends on the implementation of EFI REST EX driver instance. For + example, HTTP-aware EFI REST EX driver instance uses EFI HTTP protocol as the undying protocol + to communicate with REST service. In this case, the type of configuration is + EFI_REST_EX_CONFIG_TYPE_HTTP returned from GetService(). EFI_HTTP_CONFIG_DATA is used as EFI REST + EX configuration format and returned to EFI REST client. User has to type cast RestExConfigData + to EFI_HTTP_CONFIG_DATA. For those non HTTP-aware REST EX driver instances, the type of configuration + is EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC returned from GetService(). In this case, the format of + returning data could be non industrial. Instead, the format of configuration data is system/platform + specific definition such as BMC mechanism used in EFI REST EX driver instance. EFI REST client and + EFI REST EX driver instance have to refer to the specific system /platform spec which is out of UEFI scope. + + @param[in] This This is the EFI_REST_EX_PROTOCOL instance. + @param[out] RestExConfigData Pointer to receive a pointer to EFI_REST_EX_CONFIG_DATA. + The memory allocated for configuration data should be freed + by caller. See Related Definitions for the details. + + @retval EFI_SUCCESS EFI_REST_EX_CONFIG_DATA is returned in successfully. + @retval EFI_UNSUPPORTED This function is not supported in this REST EX Protocol driver instance. + @retval EFI_NOT_READY The configuration of this instance is not set yet. Configure() must be + executed and returns successfully prior to invoke this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_EX_GET_MODE_DATA)( + IN EFI_REST_EX_PROTOCOL *This, + OUT EFI_REST_EX_CONFIG_DATA *RestExConfigData + ); + +/** + This function is used to configure EFI REST EX child instance. + + This function is used to configure the setting of underlying protocol of REST EX child + instance. The type of configuration is according to the implementation of EFI REST EX + driver instance. For example, HTTP-aware EFI REST EX driver instance uses EFI HTTP protocol + as the undying protocol to communicate with REST service. The type of configuration is + EFI_REST_EX_CONFIG_TYPE_HTTP and RestExConfigData is the same format with EFI_HTTP_CONFIG_DATA. + Akin to HTTP configuration, REST EX child instance can be configure to use different HTTP + local access point for the data transmission. Multiple REST clients may use different + configuration of HTTP to distinguish themselves, such as to use the different TCP port. + For those non HTTP-aware REST EX driver instance, the type of configuration is + EFI_REST_EX_CONFIG_TYPE_UNSPECIFIC. RestExConfigData refers to the non industrial standard. + Instead, the format of configuration data is system/platform specific definition such as BMC. + In this case, EFI REST client and EFI REST EX driver instance have to refer to the specific + system/platform spec which is out of the UEFI scope. Besides GetService()function, no other + EFI REST EX functions can be executed by this instance until Configure()is executed and returns + successfully. All other functions must returns EFI_NOT_READY if this instance is not configured + yet. Set RestExConfigData to NULL means to put EFI REST EX child instance into the unconfigured + state. + + @param[in] This This is the EFI_REST_EX_PROTOCOL instance. + @param[in] RestExConfigData Pointer to EFI_REST_EX_CONFIG_DATA. See Related Definitions in + GetModeData() protocol interface. + + @retval EFI_SUCCESS EFI_REST_EX_CONFIG_DATA is set in successfully. + @retval EFI_DEVICE_ERROR Configuration for this REST EX child instance is failed with the given + EFI_REST_EX_CONFIG_DATA. + @retval EFI_UNSUPPORTED This function is not supported in this REST EX Protocol driver instance. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_EX_CONFIGURE)( + IN EFI_REST_EX_PROTOCOL *This, + IN EFI_REST_EX_CONFIG_DATA RestExConfigData + ); + +/** + This function sends REST request to REST service and signal caller's event asynchronously when + the final response is received by REST EX Protocol driver instance. + + The essential design of this function is to handle asynchronous send/receive implicitly according + to REST service asynchronous request mechanism. Caller will get the notification once the response + is returned from REST service. + + @param[in] This This is the EFI_REST_EX_PROTOCOL instance. + @param[in] RequestMessage This is the HTTP request message sent to REST service. Set RequestMessage + to NULL to cancel the previous asynchronous request associated with the + corresponding RestExToken. See descriptions for the details. + @param[in] RestExToken REST EX token which REST EX Protocol instance uses to notify REST client + the status of response of asynchronous REST request. See related definition + of EFI_REST_EX_TOKEN. + @param[in] TimeOutInMilliSeconds The pointer to the timeout in milliseconds which REST EX Protocol driver + instance refers as the duration to drop asynchronous REST request. NULL + pointer means no timeout for this REST request. REST EX Protocol driver + signals caller's event with EFI_STATUS set to EFI_TIMEOUT in RestExToken + if REST EX Protocol can't get the response from REST service within + TimeOutInMilliSeconds. + + @retval EFI_SUCCESS Asynchronous REST request is established. + @retval EFI_UNSUPPORTED This REST EX Protocol driver instance doesn't support asynchronous request. + @retval EFI_TIMEOUT Asynchronous REST request is not established and timeout is expired. + @retval EFI_ABORT Previous asynchronous REST request has been canceled. + @retval EFI_DEVICE_ERROR Otherwise, returns EFI_DEVICE_ERROR for other errors according to HTTP Status Code. + @retval EFI_NOT_READY The configuration of this instance is not set yet. Configure() must be executed + and returns successfully prior to invoke this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_EX_ASYNC_SEND_RECEIVE)( + IN EFI_REST_EX_PROTOCOL *This, + IN EFI_HTTP_MESSAGE *RequestMessage OPTIONAL, + IN EFI_REST_EX_TOKEN *RestExToken, + IN UINTN *TimeOutInMilliSeconds OPTIONAL + ); + +/** + This function sends REST request to a REST Event service and signals caller's event + token asynchronously when the URI resource change event is received by REST EX + Protocol driver instance. + + The essential design of this function is to monitor event implicitly according to + REST service event service mechanism. Caller will get the notification if certain + resource is changed. + + @param[in] This This is the EFI_REST_EX_PROTOCOL instance. + @param[in] RequestMessage This is the HTTP request message sent to REST service. Set RequestMessage + to NULL to cancel the previous event service associated with the corresponding + RestExToken. See descriptions for the details. + @param[in] RestExToken REST EX token which REST EX Protocol driver instance uses to notify REST client + the URI resource which monitored by REST client has been changed. See the related + definition of EFI_REST_EX_TOKEN in EFI_REST_EX_PROTOCOL.AsyncSendReceive(). + + @retval EFI_SUCCESS Asynchronous REST request is established. + @retval EFI_UNSUPPORTED This REST EX Protocol driver instance doesn't support asynchronous request. + @retval EFI_ABORT Previous asynchronous REST request has been canceled or event subscription has been + delete from service. + @retval EFI_DEVICE_ERROR Otherwise, returns EFI_DEVICE_ERROR for other errors according to HTTP Status Code. + @retval EFI_NOT_READY The configuration of this instance is not set yet. Configure() must be executed + and returns successfully prior to invoke this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_EX_EVENT_SERVICE)( + IN EFI_REST_EX_PROTOCOL *This, + IN EFI_HTTP_MESSAGE *RequestMessage OPTIONAL, + IN EFI_REST_EX_TOKEN *RestExToken +); + +/// +/// EFI REST(EX) protocols are designed to support REST communication between EFI REST client +/// applications/drivers and REST services. EFI REST client tool uses EFI REST(EX) protocols +/// to send/receive resources to/from REST service to manage systems, configure systems or +/// manipulate resources on REST service. Due to HTTP protocol is commonly used to communicate +/// with REST service in practice, EFI REST(EX) protocols adopt HTTP as the message format to +/// send and receive REST service resource. EFI REST(EX) driver instance abstracts EFI REST +/// client functionality and provides underlying interface to communicate with REST service. +/// EFI REST(EX) driver instance knows how to communicate with REST service through certain +/// interface after the corresponding configuration is initialized. +/// +struct _EFI_REST_EX_PROTOCOL { + EFI_REST_SEND_RECEIVE SendReceive; + EFI_REST_GET_TIME GetServiceTime; + EFI_REST_EX_GET_SERVICE GetService; + EFI_REST_EX_GET_MODE_DATA GetModeData; + EFI_REST_EX_CONFIGURE Configure; + EFI_REST_EX_ASYNC_SEND_RECEIVE AyncSendReceive; + EFI_REST_EX_EVENT_SERVICE EventService; +}; + +extern EFI_GUID gEfiRestExServiceBindingProtocolGuid; +extern EFI_GUID gEfiRestExProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestJsonStructure.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestJsonStructure.h new file mode 100644 index 0000000000..7d37489b41 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/RestJsonStructure.h @@ -0,0 +1,161 @@ +/** @file + This file defines the EFI REST JSON Structure Protocol interface. + + (C) Copyright 2020 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.8 + +**/ + +#ifndef EFI_REST_JSON_STRUCTURE_PROTOCOL_H_ +#define EFI_REST_JSON_STRUCTURE_PROTOCOL_H_ + +/// +/// GUID definitions +/// +#define EFI_REST_JSON_STRUCTURE_PROTOCOL_GUID \ + { \ + 0xa9a048f6, 0x48a0, 0x4714, {0xb7, 0xda, 0xa9, 0xad,0x87, 0xd4, 0xda, 0xc9 } \ + } + +typedef struct _EFI_REST_JSON_STRUCTURE_PROTOCOL EFI_REST_JSON_STRUCTURE_PROTOCOL; +typedef CHAR8 * EFI_REST_JSON_RESOURCE_TYPE_DATATYPE; + +/// +/// Structure defintions of resource name space. +/// +/// The fields declared in this structure define the +/// name and revision of payload delievered throught +/// REST API. +/// +typedef struct _EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE { + CHAR8 *ResourceTypeName; ///< Resource type name + CHAR8 *MajorVersion; ///< Resource major version + CHAR8 *MinorVersion; ///< Resource minor version + CHAR8 *ErrataVersion; ///< Resource errata version +} EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE; + +/// +/// REST resource type identifier +/// +/// REST resource type consists of name space and data type. +/// +typedef struct _EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER { + EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE NameSpace; ///< Namespace of this resource type. + EFI_REST_JSON_RESOURCE_TYPE_DATATYPE DataType; ///< Name of data type declared in this + ///< resource type. +} EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER; + +/// +/// List of JSON to C structure conversions which this convertor supports. +/// +typedef struct _EFI_REST_JSON_STRUCTURE_SUPPORTED { + LIST_ENTRY NextSupportedRsrcInterp; ///< Linklist to next supported conversion. + EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER RestResourceInterp; ///< JSON resource type this convertor supports. +} EFI_REST_JSON_STRUCTURE_SUPPORTED; + +/// +/// The header file of JSON C structure +/// +typedef struct _EFI_REST_JSON_STRUCTURE_HEADER { + EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER JsonRsrcIdentifier; ///< Resource identifier which use to + ///< choice the proper interpreter. + ///< Follow by a pointer points to JSON structure, the content in the + ///< JSON structure is implementation-specific according to converter producer. + VOID *JsonStructurePointer; +} EFI_REST_JSON_STRUCTURE_HEADER; + +/** + JSON-IN C Structure-OUT function. Convert the given REST JSON resource into structure. + + @param[in] This This is the EFI_REST_JSON_STRUCTURE_PROTOCOL instance. + @param[in] JsonRsrcIdentifier This indicates the resource type and version is given in + ResourceJsonText. + @param[in] ResourceJsonText REST JSON resource in text format. + @param[out] JsonStructure Pointer to receive the pointer to EFI_REST_JSON_STRUCTURE_HEADER + + @retval EFI_SUCCESS + @retval Others +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_JSON_STRUCTURE_TO_STRUCTURE)( + IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This, + IN EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER *JsonRsrcIdentifier OPTIONAL, + IN CHAR8 *ResourceJsonText, + OUT EFI_REST_JSON_STRUCTURE_HEADER **JsonStructure +); + +/** + Convert the given REST JSON structure into JSON text. + + @param[in] This This is the EFI_REST_JSON_STRUCTURE_PROTOCOL instance. + @param[in] JsonStructureHeader The point to EFI_REST_JSON_STRUCTURE_HEADER structure. + @param[out] ResourceJsonText Pointer to receive REST JSON resource in text format. + + @retval EFI_SUCCESS + @retval Others + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_JSON_STRUCTURE_TO_JSON)( + IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This, + IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader, + OUT CHAR8 **ResourceJsonText +); + +/** + This function destroys the REST JSON structure. + + @param[in] This This is the EFI_REST_JSON_STRUCTURE_PROTOCOL instance. + @param[in] JsonStructureHeader JSON structure to destroy. + + @retval EFI_SUCCESS + @retval Others + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE)( + IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This, + IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader +); +/** + This function provides REST JSON resource to structure converter registration. + + @param[in] This This is the EFI_REST_JSON_STRUCTURE_PROTOCOL instance. + @param[in] JsonStructureSupported The type and version of REST JSON resource which this converter + supports. + @param[in] ToStructure The function to convert REST JSON resource to structure. + @param[in] ToJson The function to convert REST JSON structure to JSON in text format. + @param[in] DestroyStructure Destroy REST JSON structure returned in ToStructure() function. + + @retval EFI_SUCCESS Register successfully. + @retval Others Fail to register. + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_REST_JSON_STRUCTURE_REGISTER)( + IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This, + IN EFI_REST_JSON_STRUCTURE_SUPPORTED *JsonStructureSupported, + IN EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure, + IN EFI_REST_JSON_STRUCTURE_TO_JSON ToJson, + IN EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestroyStructure +); + +/// +/// EFI REST JSON to C structure protocol definition. +/// +struct _EFI_REST_JSON_STRUCTURE_PROTOCOL { + EFI_REST_JSON_STRUCTURE_REGISTER Register; ///< Register JSON to C structure convertor + EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure; ///< The function to convert JSON to C structure + EFI_REST_JSON_STRUCTURE_TO_JSON ToJson; ///< The function to convert C structure to JSON + EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestoryStructure; ///< Destory C structure. +}; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rng.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rng.h new file mode 100644 index 0000000000..2db8e9fdc5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Rng.h @@ -0,0 +1,150 @@ +/** @file + EFI_RNG_PROTOCOL as defined in UEFI 2.4. + The UEFI Random Number Generator Protocol is used to provide random bits for use + in applications, or entropy for seeding other random number generators. + +Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_RNG_PROTOCOL_H__ +#define __EFI_RNG_PROTOCOL_H__ + +/// +/// Global ID for the Random Number Generator Protocol +/// +#define EFI_RNG_PROTOCOL_GUID \ + { \ + 0x3152bca5, 0xeade, 0x433d, {0x86, 0x2e, 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44 } \ + } + +typedef struct _EFI_RNG_PROTOCOL EFI_RNG_PROTOCOL; + +/// +/// A selection of EFI_RNG_PROTOCOL algorithms. +/// The algorithms listed are optional, not meant to be exhaustive and be argmented by +/// vendors or other industry standards. +/// + +typedef EFI_GUID EFI_RNG_ALGORITHM; + +/// +/// The algorithms corresponds to SP800-90 as defined in +/// NIST SP 800-90, "Recommendation for Random Number Generation Using Deterministic Random +/// Bit Generators", March 2007. +/// +#define EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID \ + { \ + 0xa7af67cb, 0x603b, 0x4d42, {0xba, 0x21, 0x70, 0xbf, 0xb6, 0x29, 0x3f, 0x96 } \ + } +#define EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID \ + { \ + 0xc5149b43, 0xae85, 0x4f53, {0x99, 0x82, 0xb9, 0x43, 0x35, 0xd3, 0xa9, 0xe7 } \ + } +#define EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID \ + { \ + 0x44f0de6e, 0x4d8c, 0x4045, {0xa8, 0xc7, 0x4d, 0xd1, 0x68, 0x85, 0x6b, 0x9e } \ + } +/// +/// The algorithms correspond to X9.31 as defined in +/// NIST, "Recommended Random Number Generator Based on ANSI X9.31 Appendix A.2.4 Using +/// the 3-Key Triple DES and AES Algorithm", January 2005. +/// +#define EFI_RNG_ALGORITHM_X9_31_3DES_GUID \ + { \ + 0x63c4785a, 0xca34, 0x4012, {0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46 } \ + } +#define EFI_RNG_ALGORITHM_X9_31_AES_GUID \ + { \ + 0xacd03321, 0x777e, 0x4d3d, {0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9 } \ + } +/// +/// The "raw" algorithm, when supported, is intended to provide entropy directly from +/// the source, without it going through some deterministic random bit generator. +/// +#define EFI_RNG_ALGORITHM_RAW \ + { \ + 0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 } \ + } + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList. + On output with a return code of EFI_SUCCESS, the size + in bytes of the data returned in RNGAlgorithmList. On output + with a return code of EFI_BUFFER_TOO_SMALL, + the size of RNGAlgorithmList required to obtain the list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver + with one EFI_RNG_ALGORITHM element for each supported + RNG algorithm. The list must not change across multiple + calls to the same driver. The first algorithm in the list + is the default algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned successfully. + @retval EFI_UNSUPPORTED The services is not supported by this driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be retrieved due to a + hardware or firmware error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RNG_GET_INFO) ( + IN EFI_RNG_PROTOCOL *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ); + +/** + Produces and returns an RNG value using either the default or specified RNG algorithm. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG + algorithm to use. May be NULL in which case the function will + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by + RNGValue. The driver shall return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the + resulting RNG value. + + @retval EFI_SUCCESS The RNG value was returned successfully. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by + this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or + firmware error. + @retval EFI_NOT_READY There is not enough random data available to satisfy the length + requested by RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RNG_GET_RNG) ( + IN EFI_RNG_PROTOCOL *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ); + +/// +/// The Random Number Generator (RNG) protocol provides random bits for use in +/// applications, or entropy for seeding other random number generators. +/// +struct _EFI_RNG_PROTOCOL { + EFI_RNG_GET_INFO GetInfo; + EFI_RNG_GET_RNG GetRNG; +}; + +extern EFI_GUID gEfiRngProtocolGuid; +extern EFI_GUID gEfiRngAlgorithmSp80090Hash256Guid; +extern EFI_GUID gEfiRngAlgorithmSp80090Hmac256Guid; +extern EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid; +extern EFI_GUID gEfiRngAlgorithmX9313DesGuid; +extern EFI_GUID gEfiRngAlgorithmX931AesGuid; +extern EFI_GUID gEfiRngAlgorithmRaw; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Runtime.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Runtime.h new file mode 100644 index 0000000000..4986a39795 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Runtime.h @@ -0,0 +1,122 @@ +/** @file + Runtime Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + Allows the runtime functionality of the DXE Foundation to be contained + in a separate driver. It also provides hooks for the DXE Foundation to + export information that is needed at runtime. As such, this protocol allows + services to the DXE Foundation to manage runtime drivers and events. + This protocol also implies that the runtime services required to transition + to virtual mode, SetVirtualAddressMap() and ConvertPointer(), have been + registered into the UEFI Runtime Table in the UEFI System Table. This protocol + must be produced by a runtime DXE driver and may only be consumed by the DXE Foundation. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_RUNTIME_H__ +#define __ARCH_PROTOCOL_RUNTIME_H__ + +/// +/// Global ID for the Runtime Architectural Protocol +/// +#define EFI_RUNTIME_ARCH_PROTOCOL_GUID \ + { 0xb7dfb4e1, 0x52f, 0x449f, {0x87, 0xbe, 0x98, 0x18, 0xfc, 0x91, 0xb7, 0x33 } } + +typedef struct _EFI_RUNTIME_ARCH_PROTOCOL EFI_RUNTIME_ARCH_PROTOCOL; + +/// +/// LIST_ENTRY from BaseType +/// +typedef LIST_ENTRY EFI_LIST_ENTRY; + +typedef struct _EFI_RUNTIME_IMAGE_ENTRY EFI_RUNTIME_IMAGE_ENTRY; + +/// +/// EFI_RUNTIME_IMAGE_ENTRY +/// +struct _EFI_RUNTIME_IMAGE_ENTRY { + /// + /// Start of image that has been loaded in memory. It is a pointer + /// to either the DOS header or PE header of the image. + /// + VOID *ImageBase; + /// + /// Size in bytes of the image represented by ImageBase. + /// + UINT64 ImageSize; + /// + /// Information about the fix-ups that were performed on ImageBase when it was + /// loaded into memory. + /// + VOID *RelocationData; + /// + /// The ImageHandle passed into ImageBase when it was loaded. + /// + EFI_HANDLE Handle; + /// + /// Entry for this node in the EFI_RUNTIME_ARCHITECTURE_PROTOCOL.ImageHead list. + /// + EFI_LIST_ENTRY Link; +}; + +typedef struct _EFI_RUNTIME_EVENT_ENTRY EFI_RUNTIME_EVENT_ENTRY; + +/// +/// EFI_RUNTIME_EVENT_ENTRY +/// +struct _EFI_RUNTIME_EVENT_ENTRY { + /// + /// The same as Type passed into CreateEvent(). + /// + UINT32 Type; + /// + /// The same as NotifyTpl passed into CreateEvent(). + /// + EFI_TPL NotifyTpl; + /// + /// The same as NotifyFunction passed into CreateEvent(). + /// + EFI_EVENT_NOTIFY NotifyFunction; + /// + /// The same as NotifyContext passed into CreateEvent(). + /// + VOID *NotifyContext; + /// + /// The EFI_EVENT returned by CreateEvent(). Event must be in runtime memory. + /// + EFI_EVENT *Event; + /// + /// Entry for this node in the + /// EFI_RUNTIME_ARCHITECTURE_PROTOCOL.EventHead list. + /// + EFI_LIST_ENTRY Link; +}; + +/// +/// Allows the runtime functionality of the DXE Foundation to be contained in a +/// separate driver. It also provides hooks for the DXE Foundation to export +/// information that is needed at runtime. As such, this protocol allows the DXE +/// Foundation to manage runtime drivers and events. This protocol also implies +/// that the runtime services required to transition to virtual mode, +/// SetVirtualAddressMap() and ConvertPointer(), have been registered into the +/// EFI Runtime Table in the EFI System Partition. This protocol must be produced +/// by a runtime DXE driver and may only be consumed by the DXE Foundation. +/// +struct _EFI_RUNTIME_ARCH_PROTOCOL { + EFI_LIST_ENTRY ImageHead; ///< A list of type EFI_RUNTIME_IMAGE_ENTRY. + EFI_LIST_ENTRY EventHead; ///< A list of type EFI_RUNTIME_EVENT_ENTRY. + UINTN MemoryDescriptorSize; ///< Size of a memory descriptor that is returned by GetMemoryMap(). + UINT32 MemoryDesciptorVersion; ///< Version of a memory descriptor that is returned by GetMemoryMap(). + UINTN MemoryMapSize;///< Size of the memory map in bytes contained in MemoryMapPhysical and MemoryMapVirtual. + EFI_MEMORY_DESCRIPTOR *MemoryMapPhysical; ///< Pointer to a runtime buffer that contains a copy of + ///< the memory map returned via GetMemoryMap(). + EFI_MEMORY_DESCRIPTOR *MemoryMapVirtual; ///< Pointer to MemoryMapPhysical that is updated to virtual mode after SetVirtualAddressMap(). + BOOLEAN VirtualMode; ///< Boolean that is TRUE if SetVirtualAddressMap() has been called. + BOOLEAN AtRuntime; ///< Boolean that is TRUE if ExitBootServices () has been called. +}; + +extern EFI_GUID gEfiRuntimeArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SaveState.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SaveState.h new file mode 100644 index 0000000000..7e7d5cadfd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SaveState.h @@ -0,0 +1,170 @@ +/** @file + S3 Save State Protocol as defined in PI 1.6(Errata A) Specification VOLUME 5 Standard. + + This protocol is used by DXE PI module to store or record various IO operations + to be replayed during an S3 resume. + This protocol is not required for all platforms. + + Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: + Standards + +**/ + +#ifndef __S3_SAVE_STATE_H__ +#define __S3_SAVE_STATE_H__ + +#define EFI_S3_SAVE_STATE_PROTOCOL_GUID \ + { 0xe857caf6, 0xc046, 0x45dc, { 0xbe, 0x3f, 0xee, 0x7, 0x65, 0xfb, 0xa8, 0x87 }} + + +typedef VOID *EFI_S3_BOOT_SCRIPT_POSITION; + +typedef struct _EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL; + +/** + Record operations that need to be replayed during an S3 resume. + + This function is used to store an OpCode to be replayed as part of the S3 resume boot path. It is + assumed this protocol has platform specific mechanism to store the OpCode set and replay them + during the S3 resume. + + @param[in] This A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance. + @param[in] OpCode The operation code (opcode) number. + @param[in] ... Argument list that is specific to each opcode. See the following subsections for the + definition of each opcode. + + @retval EFI_SUCCESS The operation succeeded. A record was added into the specified + script table. + @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported. + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_S3_SAVE_STATE_WRITE)( + IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This, + IN UINTN OpCode, + ... +); + +/** + Record operations that need to be replayed during an S3 resume. + + This function is used to store an OpCode to be replayed as part of the S3 resume boot path. It is + assumed this protocol has platform specific mechanism to store the OpCode set and replay them + during the S3 resume. + The opcode is inserted before or after the specified position in the boot script table. If Position is + NULL then that position is after the last opcode in the table (BeforeOrAfter is TRUE) or before + the first opcode in the table (BeforeOrAfter is FALSE). The position which is pointed to by + Position upon return can be used for subsequent insertions. + + This function has a variable parameter list. The exact parameter list depends on the OpCode that is + passed into the function. If an unsupported OpCode or illegal parameter list is passed in, this + function returns EFI_INVALID_PARAMETER. + If there are not enough resources available for storing more scripts, this function returns + EFI_OUT_OF_RESOURCES. + OpCode values of 0x80 - 0xFE are reserved for implementation specific functions. + + @param[in] This A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance. + @param[in] BeforeOrAfter Specifies whether the opcode is stored before (TRUE) or after (FALSE) the position + in the boot script table specified by Position. If Position is NULL or points to + NULL then the new opcode is inserted at the beginning of the table (if TRUE) or end + of the table (if FALSE). + @param[in, out] Position On entry, specifies the position in the boot script table where the opcode will be + inserted, either before or after, depending on BeforeOrAfter. On exit, specifies + the position of the inserted opcode in the boot script table. + @param[in] OpCode The operation code (opcode) number. See "Related Definitions" in Write() for the + defined opcode types. + @param[in] ... Argument list that is specific to each opcode. See the following subsections for the + definition of each opcode. + + @retval EFI_SUCCESS The operation succeeded. An opcode was added into the script. + @retval EFI_INVALID_PARAMETER The Opcode is an invalid opcode value. + @retval EFI_INVALID_PARAMETER The Position is not a valid position in the boot script table. + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script table. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_S3_SAVE_STATE_INSERT)( + IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This, + IN BOOLEAN BeforeOrAfter, + IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL, + IN UINTN OpCode, + ... +); + +/** + Find a label within the boot script table and, if not present, optionally create it. + + If the label Label is already exists in the boot script table, then no new label is created, the + position of the Label is returned in *Position and EFI_SUCCESS is returned. + If the label Label does not already exist and CreateIfNotFound is TRUE, then it will be + created before or after the specified position and EFI_SUCCESS is returned. + If the label Label does not already exist and CreateIfNotFound is FALSE, then + EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance. + @param[in] BeforeOrAfter Specifies whether the label is stored before (TRUE) or after (FALSE) the position in + the boot script table specified by Position. If Position is NULL or points to + NULL then the new label is inserted at the beginning of the table (if TRUE) or end of + the table (if FALSE). + @param[in] CreateIfNotFound Specifies whether the label will be created if the label does not exists (TRUE) or not (FALSE). + @param[in, out] Position On entry, specifies the position in the boot script table where the label will be inserted, + either before or after, depending on BeforeOrAfter. On exit, specifies the position + of the inserted label in the boot script table. + @param[in] Label Points to the label which will be inserted in the boot script table. + + @retval EFI_SUCCESS The label already exists or was inserted. + @retval EFI_NOT_FOUND The label did not already exist and CreateifNotFound was FALSE. + @retval EFI_INVALID_PARAMETER The Label is NULL or points to an empty string. + @retval EFI_INVALID_PARAMETER The Position is not a valid position in the boot script table. + @retval EFI_OUT_OF_RESOURCES There is insufficient memory to store the boot script. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_S3_SAVE_STATE_LABEL)( + IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This, + IN BOOLEAN BeforeOrAfter, + IN BOOLEAN CreateIfNotFound, + IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL, + IN CONST CHAR8 *Label +); + +/** + Compare two positions in the boot script table and return their relative position. + + This function compares two positions in the boot script table and returns their relative positions. If + Position1 is before Position2, then -1 is returned. If Position1 is equal to Position2, + then 0 is returned. If Position1 is after Position2, then 1 is returned. + + @param[in] This A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance. + @param[in] Position1 The positions in the boot script table to compare. + @param[in] Position2 The positions in the boot script table to compare. + @param[out] RelativePosition On return, points to the result of the comparison. + + @retval EFI_SUCCESS The operation succeeded. + @retval EFI_INVALID_PARAMETER The Position1 or Position2 is not a valid position in the boot script table. + @retval EFI_INVALID_PARAMETER The RelativePosition is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_S3_SAVE_STATE_COMPARE)( + IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This, + IN EFI_S3_BOOT_SCRIPT_POSITION Position1, + IN EFI_S3_BOOT_SCRIPT_POSITION Position2, + OUT UINTN *RelativePosition +); + +struct _EFI_S3_SAVE_STATE_PROTOCOL { + EFI_S3_SAVE_STATE_WRITE Write; + EFI_S3_SAVE_STATE_INSERT Insert; + EFI_S3_SAVE_STATE_LABEL Label; + EFI_S3_SAVE_STATE_COMPARE Compare; +}; + +extern EFI_GUID gEfiS3SaveStateProtocolGuid; + +#endif // __S3_SAVE_STATE_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SmmSaveState.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SmmSaveState.h new file mode 100644 index 0000000000..07f82db050 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/S3SmmSaveState.h @@ -0,0 +1,40 @@ +/** @file + S3 SMM Save State Protocol as defined in PI1.2 Specification VOLUME 5 Standard. + + The EFI_S3_SMM_SAVE_STATE_PROTOCOL publishes the PI SMMboot script abstractions + On an S3 resume boot path the data stored via this protocol is replayed in the order it was stored. + The order of replay is the order either of the S3 Save State Protocol or S3 SMM Save State Protocol + Write() functions were called during the boot process. Insert(), Label(), and + Compare() operations are ordered relative other S3 SMM Save State Protocol write() operations + and the order relative to S3 State Save Write() operations is not defined. Due to these ordering + restrictions it is recommended that the S3 State Save Protocol be used during the DXE phase when + every possible. + The EFI_S3_SMM_SAVE_STATE_PROTOCOL can be called at runtime and + EFI_OUT_OF_RESOURCES may be returned from a runtime call. It is the responsibility of the + platform to ensure enough memory resource exists to save the system state. It is recommended that + runtime calls be minimized by the caller. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: + Standards + +**/ + +#ifndef __S3_SMM_SAVE_STATE_H__ +#define __S3_SMM_SAVE_STATE_H__ + +#include + +#define EFI_S3_SMM_SAVE_STATE_PROTOCOL_GUID \ + {0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, 0xf4, 0xaf, 0x1, 0x4c }} + + +typedef EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SMM_SAVE_STATE_PROTOCOL; + +extern EFI_GUID gEfiS3SmmSaveStateProtocolGuid; + +#endif // __S3_SMM_SAVE_STATE_H__ + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiIo.h new file mode 100644 index 0000000000..d3db297a97 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiIo.h @@ -0,0 +1,311 @@ +/** @file + EFI_SCSI_IO_PROTOCOL as defined in UEFI 2.0. + This protocol is used by code, typically drivers, running in the EFI boot + services environment to access SCSI devices. In particular, functions for + managing devices on SCSI buses are defined here. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SCSI_IO_PROTOCOL_H__ +#define __EFI_SCSI_IO_PROTOCOL_H__ + +#define EFI_SCSI_IO_PROTOCOL_GUID \ + { \ + 0x932f47e6, 0x2362, 0x4002, {0x80, 0x3e, 0x3c, 0xd5, 0x4b, 0x13, 0x8f, 0x85 } \ + } + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_SCSI_IO_PROTOCOL EFI_SCSI_IO_PROTOCOL; + +// +// SCSI Device type information, defined in the SCSI Primary Commands standard (e.g., SPC-4) +// +#define EFI_SCSI_IO_TYPE_DISK 0x00 ///< Disk device +#define EFI_SCSI_IO_TYPE_TAPE 0x01 ///< Tape device +#define EFI_SCSI_IO_TYPE_PRINTER 0x02 ///< Printer +#define EFI_SCSI_IO_TYPE_PROCESSOR 0x03 ///< Processor +#define EFI_SCSI_IO_TYPE_WORM 0x04 ///< Write-once read-multiple +#define EFI_SCSI_IO_TYPE_CDROM 0x05 ///< CD or DVD device +#define EFI_SCSI_IO_TYPE_SCANNER 0x06 ///< Scanner device +#define EFI_SCSI_IO_TYPE_OPTICAL 0x07 ///< Optical memory device +#define EFI_SCSI_IO_TYPE_MEDIUMCHANGER 0x08 ///< Medium Changer device +#define EFI_SCSI_IO_TYPE_COMMUNICATION 0x09 ///< Communications device +#define MFI_SCSI_IO_TYPE_A 0x0A ///< Obsolete +#define MFI_SCSI_IO_TYPE_B 0x0B ///< Obsolete +#define MFI_SCSI_IO_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID) +#define MFI_SCSI_IO_TYPE_SES 0x0D ///< Enclosure services device +#define MFI_SCSI_IO_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk) +#define MFI_SCSI_IO_TYPE_OCRW 0x0F ///< Optical card reader/writer device +#define MFI_SCSI_IO_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands +#define MFI_SCSI_IO_TYPE_OSD 0x11 ///< Object-based Storage Device +#define EFI_SCSI_IO_TYPE_RESERVED_LOW 0x12 ///< Reserved (low) +#define EFI_SCSI_IO_TYPE_RESERVED_HIGH 0x1E ///< Reserved (high) +#define EFI_SCSI_IO_TYPE_UNKNOWN 0x1F ///< Unknown no device type + +// +// SCSI Data Direction definition +// +#define EFI_SCSI_IO_DATA_DIRECTION_READ 0 +#define EFI_SCSI_IO_DATA_DIRECTION_WRITE 1 +#define EFI_SCSI_IO_DATA_DIRECTION_BIDIRECTIONAL 2 + +// +// SCSI Host Adapter Status definition +// +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OK 0x00 +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09 ///< timeout when processing the command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_TIMEOUT 0x0b ///< timeout when waiting for the command processing +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d ///< a message reject was received when processing command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_RESET 0x0e ///< a bus reset was detected +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10 ///< the adapter failed in issuing request sense command +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11 ///< selection timeout +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12 ///< data overrun or data underrun +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_BUS_FREE 0x13 ///< Unexepected bus free +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 ///< Target bus phase sequence failure +#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OTHER 0x7f + + +// +// SCSI Target Status definition +// +#define EFI_SCSI_IO_STATUS_TARGET_GOOD 0x00 +#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02 ///< check condition +#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04 ///< condition met +#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08 ///< busy +#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10 ///< intermediate +#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 ///< intermediate-condition met +#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18 ///< reservation conflict +#define EFI_SCSI_IO_STATUS_TARGET_COMMOND_TERMINATED 0x22 ///< command terminated +#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28 ///< queue full + +typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI Request + /// Packet is greater than Timeout. + /// + UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for SCSI READ command + /// + VOID *InDataBuffer; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for SCSI WRITE command. + /// + VOID *OutDataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// + VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device. + /// + VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// + UINT32 InTransferLength; + /// + /// On Input, the size, in bytes of OutDataBuffer. On Output, the + /// Number of bytes transferred between SCSI Controller and the SCSI device. + /// + UINT32 OutTransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are + /// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// + UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// + UINT8 DataDirection; + /// + /// The status of the SCSI Host Controller that produces the SCSI + /// bus where the SCSI device attached when the SCSI Request + /// Packet was executed on the SCSI Controller. + /// + UINT8 HostAdapterStatus; + /// + /// The status returned by the SCSI device when the SCSI Request + /// Packet was executed. + /// + UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// + UINT8 SenseDataLength; +} EFI_SCSI_IO_SCSI_REQUEST_PACKET; + +/** + Retrieves the device type information of the SCSI Controller. + + @param This Protocol instance pointer. + @param DeviceType A pointer to the device type information + retrieved from the SCSI Controller. + + @retval EFI_SUCCESS Retrieved the device type information successfully. + @retval EFI_INVALID_PARAMETER The DeviceType is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE)( + IN EFI_SCSI_IO_PROTOCOL *This, + OUT UINT8 *DeviceType + ); + +/** + Retrieves the device location in the SCSI channel. + + @param This Protocol instance pointer. + @param Target A pointer to the Target ID of a SCSI device + on the SCSI channel. + @param Lun A pointer to the LUN of the SCSI device on + the SCSI channel. + + @retval EFI_SUCCESS Retrieves the device location successfully. + @retval EFI_INVALID_PARAMETER The Target or Lun is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION)( + IN EFI_SCSI_IO_PROTOCOL *This, + IN OUT UINT8 **Target, + OUT UINT64 *Lun + ); + +/** + Resets the SCSI Bus that the SCSI Controller is attached to. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The SCSI bus is reset successfully. + @retval EFI_DEVICE_ERROR Errors encountered when resetting the SCSI bus. + @retval EFI_UNSUPPORTED The bus reset operation is not supported by the + SCSI Host Controller. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset + the SCSI bus. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_IO_PROTOCOL_RESET_BUS)( + IN EFI_SCSI_IO_PROTOCOL *This + ); + +/** + Resets the SCSI Controller that the device handle specifies. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS Reset the SCSI controller successfully. + @retval EFI_DEVICE_ERROR Errors were encountered when resetting the + SCSI Controller. + @retval EFI_UNSUPPORTED The SCSI bus does not support a device + reset operation. + @retval EFI_TIMEOUT A timeout occurred while attempting to + reset the SCSI Controller. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_IO_PROTOCOL_RESET_DEVICE)( + IN EFI_SCSI_IO_PROTOCOL *This + ); + + +/** + Sends a SCSI Request Packet to the SCSI Controller for execution. + + @param This Protocol instance pointer. + @param Packet The SCSI request packet to send to the SCSI + Controller specified by the device handle. + @param Event If the SCSI bus to which the SCSI device is attached + does not support non-blocking I/O, then Event is + ignored, and blocking I/O is performed. + If Event is NULL, then blocking I/O is performed. + If Event is not NULL and non-blocking I/O is + supported, then non-blocking I/O is performed, + and Event will be signaled when the SCSI Request + Packet completes. + + @retval EFI_SUCCESS The SCSI Request Packet was sent by the host + successfully, and TransferLength bytes were + transferred to/from DataBuffer. See + HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order + for additional status information. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, + but the entire DataBuffer could not be transferred. + The actual number of bytes transferred is returned + in TransferLength. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Command Packets already + queued.The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + the SCSI Request Packet. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + @retval EFI_INVALID_PARAMETER The contents of CommandPacket are invalid. + The SCSI Request Packet was not sent, so no + additional status information is available. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the SCSI initiator(i.e., SCSI + Host Controller). The SCSI Request Packet was not + sent, so no additional status information is + available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI + Request Packet to execute. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND)( + IN EFI_SCSI_IO_PROTOCOL *This, + IN OUT EFI_SCSI_IO_SCSI_REQUEST_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/// +/// Provides services to manage and communicate with SCSI devices. +/// +struct _EFI_SCSI_IO_PROTOCOL { + EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE GetDeviceType; + EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION GetDeviceLocation; + EFI_SCSI_IO_PROTOCOL_RESET_BUS ResetBus; + EFI_SCSI_IO_PROTOCOL_RESET_DEVICE ResetDevice; + EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND ExecuteScsiCommand; + + /// + /// Supplies the alignment requirement for any buffer used in a data transfer. + /// IoAlign values of 0 and 1 mean that the buffer can be placed anywhere in memory. + /// Otherwise, IoAlign must be a power of 2, and the requirement is that the + /// start address of a buffer must be evenly divisible by IoAlign with no remainder. + /// + UINT32 IoAlign; +}; + +extern EFI_GUID gEfiScsiIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThru.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThru.h new file mode 100644 index 0000000000..1666b248e7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThru.h @@ -0,0 +1,377 @@ +/** @file + SCSI Pass Through protocol as defined in EFI 1.1. + This protocol allows information about a SCSI channel to be collected, + and allows SCSI Request Packets to be sent to any SCSI devices on a SCSI + channel even if those devices are not boot devices. This protocol is attached + to the device handle of each SCSI channel in a system that the protocol + supports, and can be used for diagnostics. It may also be used to build + a Block I/O driver for SCSI hard drives and SCSI CD-ROM or DVD drives to + allow those devices to become boot devices. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SCSI_PASS_THROUGH_H__ +#define __SCSI_PASS_THROUGH_H__ + +#define EFI_SCSI_PASS_THRU_PROTOCOL_GUID \ + { \ + 0xa59e8fcf, 0xbda0, 0x43bb, {0x90, 0xb1, 0xd3, 0x73, 0x2e, 0xca, 0xa8, 0x77 } \ + } + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_SCSI_PASS_THRU_PROTOCOL EFI_SCSI_PASS_THRU_PROTOCOL; + +#define EFI_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001 +#define EFI_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002 +#define EFI_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004 + +// +// SCSI Host Adapter Status definition +// +#define EFI_SCSI_STATUS_HOST_ADAPTER_OK 0x00 +#define EFI_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09 // timeout when processing the command +#define EFI_SCSI_STATUS_HOST_ADAPTER_TIMEOUT 0x0b // timeout when waiting for the command processing +#define EFI_SCSI_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d // a message reject was received when processing command +#define EFI_SCSI_STATUS_HOST_ADAPTER_BUS_RESET 0x0e // a bus reset was detected +#define EFI_SCSI_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f +#define EFI_SCSI_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10 // the adapter failed in issuing request sense command +#define EFI_SCSI_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11 // selection timeout +#define EFI_SCSI_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12 // data overrun or data underrun +#define EFI_SCSI_STATUS_HOST_ADAPTER_BUS_FREE 0x13 // Unexepected bus free +#define EFI_SCSI_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 // Target bus phase sequence failure +#define EFI_SCSI_STATUS_HOST_ADAPTER_OTHER 0x7f + +// +// SCSI Target Status definition +// +#define EFI_SCSI_STATUS_TARGET_GOOD 0x00 +#define EFI_SCSI_STATUS_TARGET_CHECK_CONDITION 0x02 // check condition +#define EFI_SCSI_STATUS_TARGET_CONDITION_MET 0x04 // condition met +#define EFI_SCSI_STATUS_TARGET_BUSY 0x08 // busy +#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE 0x10 // intermediate +#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 // intermediate-condition met +#define EFI_SCSI_STATUS_TARGET_RESERVATION_CONFLICT 0x18 // reservation conflict +#define EFI_SCSI_STATUS_TARGET_COMMOND_TERMINATED 0x22 // command terminated +#define EFI_SCSI_STATUS_TARGET_QUEUE_FULL 0x28 // queue full + +typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI Request + /// Packet is greater than Timeout. + /// + UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device. Must be aligned to the boundary + /// specified in the IoAlign field of the + /// EFI_SCSI_PASS_THRU_MODE structure. + /// + VOID *DataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// + VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device. + /// + VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// + UINT32 TransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are + /// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// + UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// + UINT8 DataDirection; + /// + /// The status of the SCSI Host Controller that produces the SCSI + /// bus where the SCSI device attached when the SCSI Request + /// Packet was executed on the SCSI Controller. + /// + UINT8 HostAdapterStatus; + /// + /// The status returned by the SCSI device when the SCSI Request + /// Packet was executed. + /// + UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// + UINT8 SenseDataLength; +} EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET; + +typedef struct { + /// + /// A Null-terminated Unicode string that represents the printable name of the SCSI controller. + /// + CHAR16 *ControllerName; + /// + /// A Null-terminated Unicode string that represents the printable name of the SCSI channel. + /// + CHAR16 *ChannelName; + /// + /// The Target ID of the host adapter on the SCSI channel. + /// + UINT32 AdapterId; + /// + /// Additional information on the attributes of the SCSI channel. + /// + UINT32 Attributes; + /// + /// Supplies the alignment requirement for any buffer used in a data transfer. + /// + UINT32 IoAlign; +} EFI_SCSI_PASS_THRU_MODE; + +/** + Sends a SCSI Request Packet to a SCSI device that is attached to + the SCSI channel. This function supports both blocking I/O and + non-blocking I/O. The blocking I/O functionality is required, + and the non-blocking I/O functionality is optional. + + @param This Protocol instance pointer. + @param Target The Target ID of the SCSI device to + send the SCSI Request Packet. + @param Lun The LUN of the SCSI device to send the + SCSI Request Packet. + @param Packet A pointer to the SCSI Request Packet to send + to the SCSI device specified by Target and Lun. + @param Event If non-blocking I/O is not supported then Event + is ignored, and blocking I/O is performed. + If Event is NULL, then blocking I/O is performed. + If Event is not NULL and non blocking I/O is + supported, then non-blocking I/O is performed, + and Event will be signaled when the SCSI Request + Packet completes + + @retval EFI_SUCCESS The SCSI Request Packet was sent by the host, and + TransferLength bytes were transferred to/from + DataBuffer. See HostAdapterStatus, TargetStatus, + SenseDataLength, and SenseData in that order + for additional status information. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was executed, but the + entire DataBuffer could not be transferred. + The actual number of bytes transferred is returned + in TransferLength. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because + there are too many SCSI Request Packets already + queued. The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + the SCSI Request Packet. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + @retval EFI_INVALID_PARAMETER Target, Lun, or the contents of ScsiRequestPacket + are invalid. The SCSI Request Packet was not sent, + so no additional status information is available. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet + is not supported by the host adapter. The SCSI + Request Packet was not sent, so no additional + status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI + Request Packet to execute. See HostAdapterStatus, + TargetStatus, SenseDataLength, and SenseData in + that order for additional status information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_PASSTHRU)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT32 Target, + IN UINT64 Lun, + IN OUT EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/** + Used to retrieve the list of legal Target IDs for SCSI devices + on a SCSI channel. + + @param This Protocol instance pointer. + @param Target On input, a pointer to the Target ID of a + SCSI device present on the SCSI channel. + On output, a pointer to the Target ID of + the next SCSI device present on a SCSI channel. + An input value of 0xFFFFFFFF retrieves the + Target ID of the first SCSI device present on + a SCSI channel. + @param Lun On input, a pointer to the LUN of a SCSI device + present on the SCSI channel. On output, a pointer + to the LUN of the next SCSI device present on a + SCSI channel. + + @retval EFI_SUCCESS The Target ID of the next SCSI device on the SCSI + channel was returned in Target and Lun. + @retval EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel. + @retval EFI_INVALID_PARAMETER Target is not 0xFFFFFFFF, and Target and Lun were + not returned on a previous call to GetNextDevice(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_GET_NEXT_DEVICE)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This, + IN OUT UINT32 *Target, + IN OUT UINT64 *Lun + ); + +/** + Used to allocate and build a device path node for a SCSI device + on a SCSI channel. + + @param This Protocol instance pointer. + @param Target The Target ID of the SCSI device for which + a device path node is to be allocated and built. + @param Lun The LUN of the SCSI device for which a device + path node is to be allocated and built. + @param DevicePath A pointer to a single device path node that + describes the SCSI device specified by + Target and Lun. This function is responsible + for allocating the buffer DevicePath with the boot + service AllocatePool(). It is the caller's + responsibility to free DevicePath when the caller + is finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SCSI device + specified by Target and Lun was allocated and + returned in DevicePath. + @retval EFI_NOT_FOUND The SCSI devices specified by Target and Lun does + not exist on the SCSI channel. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate + DevicePath. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_BUILD_DEVICE_PATH)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT32 Target, + IN UINT64 Lun, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Used to translate a device path node to a Target ID and LUN. + + @param This Protocol instance pointer. + @param DevicePath A pointer to the device path node that + describes a SCSI device on the SCSI channel. + @param Target A pointer to the Target ID of a SCSI device + on the SCSI channel. + @param Lun A pointer to the LUN of a SCSI device on + the SCSI channel. + + @retval EFI_SUCCESS DevicePath was successfully translated to a + Target ID and LUN, and they were returned + in Target and Lun. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_INVALID_PARAMETER Target is NULL. + @retval EFI_INVALID_PARAMETER Lun is NULL. + @retval EFI_UNSUPPORTED This driver does not support the device path + node type in DevicePath. + @retval EFI_NOT_FOUND A valid translation from DevicePath to a + Target ID and LUN does not exist. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_GET_TARGET_LUN)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT32 *Target, + OUT UINT64 *Lun + ); + +/** + Resets a SCSI channel.This operation resets all the + SCSI devices connected to the SCSI channel. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The SCSI channel was reset. + @retval EFI_UNSUPPORTED The SCSI channel does not support + a channel reset operation. + @retval EFI_DEVICE_ERROR A device error occurred while + attempting to reset the SCSI channel. + @retval EFI_TIMEOUT A timeout occurred while attempting + to reset the SCSI channel. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_RESET_CHANNEL)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This + ); + +/** + Resets a SCSI device that is connected to a SCSI channel. + + @param This Protocol instance pointer. + @param Target The Target ID of the SCSI device to reset. + @param Lun The LUN of the SCSI device to reset. + + @retval EFI_SUCCESS The SCSI device specified by Target and + Lun was reset. + @retval EFI_UNSUPPORTED The SCSI channel does not support a target + reset operation. + @retval EFI_INVALID_PARAMETER Target or Lun are invalid. + @retval EFI_DEVICE_ERROR A device error occurred while attempting + to reset the SCSI device specified by Target + and Lun. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset + the SCSI device specified by Target and Lun. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SCSI_PASS_THRU_RESET_TARGET)( + IN EFI_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT32 Target, + IN UINT64 Lun + ); + +/// +/// The EFI_SCSI_PASS_THRU_PROTOCOL provides information about a SCSI channel and +/// the ability to send SCSI Request Packets to any SCSI device attached to that SCSI channel. The +/// information includes the Target ID of the host controller on the SCSI channel, the attributes of +/// the SCSI channel, the printable name for the SCSI controller, and the printable name of the +/// SCSI channel. +/// +struct _EFI_SCSI_PASS_THRU_PROTOCOL { + /// + /// A pointer to the EFI_SCSI_PASS_THRU_MODE data for this SCSI channel. + /// + EFI_SCSI_PASS_THRU_MODE *Mode; + EFI_SCSI_PASS_THRU_PASSTHRU PassThru; + EFI_SCSI_PASS_THRU_GET_NEXT_DEVICE GetNextDevice; + EFI_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath; + EFI_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun; + EFI_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel; + EFI_SCSI_PASS_THRU_RESET_TARGET ResetTarget; +}; + +extern EFI_GUID gEfiScsiPassThruProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThruExt.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThruExt.h new file mode 100644 index 0000000000..49e16feb1a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ScsiPassThruExt.h @@ -0,0 +1,388 @@ +/** @file + EFI_EXT_SCSI_PASS_THRU_PROTOCOL as defined in UEFI 2.0. + This protocol provides services that allow SCSI Pass Thru commands + to be sent to SCSI devices attached to a SCSI channel. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EXT_SCSI_PASS_THROUGH_PROTOCOL_H__ +#define __EXT_SCSI_PASS_THROUGH_PROTOCOL_H__ + +#define EFI_EXT_SCSI_PASS_THRU_PROTOCOL_GUID \ + { \ + 0x143b7632, 0xb81b, 0x4cb7, {0xab, 0xd3, 0xb6, 0x25, 0xa5, 0xb9, 0xbf, 0xfe } \ + } + +typedef struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL EFI_EXT_SCSI_PASS_THRU_PROTOCOL; + +#define TARGET_MAX_BYTES 0x10 + +#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001 +#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002 +#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004 + +// +// DataDirection +// +#define EFI_EXT_SCSI_DATA_DIRECTION_READ 0 +#define EFI_EXT_SCSI_DATA_DIRECTION_WRITE 1 +#define EFI_EXT_SCSI_DATA_DIRECTION_BIDIRECTIONAL 2 +// +// HostAdapterStatus +// +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OK 0x00 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT 0x0b +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_RESET 0x0e +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_FREE 0x13 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 +#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OTHER 0x7f +// +// TargetStatus +// +#define EFI_EXT_SCSI_STATUS_TARGET_GOOD 0x00 +#define EFI_EXT_SCSI_STATUS_TARGET_CHECK_CONDITION 0x02 +#define EFI_EXT_SCSI_STATUS_TARGET_CONDITION_MET 0x04 +#define EFI_EXT_SCSI_STATUS_TARGET_BUSY 0x08 +#define EFI_EXT_SCSI_STATUS_TARGET_INTERMEDIATE 0x10 +#define EFI_EXT_SCSI_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 +#define EFI_EXT_SCSI_STATUS_TARGET_RESERVATION_CONFLICT 0x18 +#define EFI_EXT_SCSI_STATUS_TARGET_TASK_SET_FULL 0x28 +#define EFI_EXT_SCSI_STATUS_TARGET_ACA_ACTIVE 0x30 +#define EFI_EXT_SCSI_STATUS_TARGET_TASK_ABORTED 0x40 + +typedef struct { + /// + /// The Target ID of the host adapter on the SCSI channel. + /// + UINT32 AdapterId; + /// + /// Additional information on the attributes of the SCSI channel. + /// + UINT32 Attributes; + /// + /// Supplies the alignment requirement for any buffer used in a data transfer. + /// + UINT32 IoAlign; +} EFI_EXT_SCSI_PASS_THRU_MODE; + +typedef struct { + /// + /// The timeout, in 100 ns units, to use for the execution of this SCSI + /// Request Packet. A Timeout value of 0 means that this function + /// will wait indefinitely for the SCSI Request Packet to execute. If + /// Timeout is greater than zero, then this function will return + /// EFI_TIMEOUT if the time required to execute the SCSI + /// Request Packet is greater than Timeout. + /// + UINT64 Timeout; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for read and bidirectional commands. + /// + VOID *InDataBuffer; + /// + /// A pointer to the data buffer to transfer between the SCSI + /// controller and the SCSI device for write or bidirectional commands. + /// + VOID *OutDataBuffer; + /// + /// A pointer to the sense data that was generated by the execution of + /// the SCSI Request Packet. + /// + VOID *SenseData; + /// + /// A pointer to buffer that contains the Command Data Block to + /// send to the SCSI device specified by Target and Lun. + /// + VOID *Cdb; + /// + /// On Input, the size, in bytes, of InDataBuffer. On output, the + /// number of bytes transferred between the SCSI controller and the SCSI device. + /// + UINT32 InTransferLength; + /// + /// On Input, the size, in bytes of OutDataBuffer. On Output, the + /// Number of bytes transferred between SCSI Controller and the SCSI device. + /// + UINT32 OutTransferLength; + /// + /// The length, in bytes, of the buffer Cdb. The standard values are 6, + /// 10, 12, and 16, but other values are possible if a variable length CDB is used. + /// + UINT8 CdbLength; + /// + /// The direction of the data transfer. 0 for reads, 1 for writes. A + /// value of 2 is Reserved for Bi-Directional SCSI commands. + /// + UINT8 DataDirection; + /// + /// The status of the host adapter specified by This when the SCSI + /// Request Packet was executed on the target device. + /// + UINT8 HostAdapterStatus; + /// + /// The status returned by the device specified by Target and Lun + /// when the SCSI Request Packet was executed. + /// + UINT8 TargetStatus; + /// + /// On input, the length in bytes of the SenseData buffer. On + /// output, the number of bytes written to the SenseData buffer. + /// + UINT8 SenseDataLength; +} EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET; + +/** + Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI channel. This function + supports both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the + nonblocking I/O functionality is optional. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param Target The Target is an array of size TARGET_MAX_BYTES and it represents + the id of the SCSI device to send the SCSI Request Packet. Each + transport driver may choose to utilize a subset of this size to suit the needs + of transport target representation. For example, a Fibre Channel driver + may use only 8 bytes (WWN) to represent an FC target. + @param Lun The LUN of the SCSI device to send the SCSI Request Packet. + @param Packet A pointer to the SCSI Request Packet to send to the SCSI device + specified by Target and Lun. + @param Event If nonblocking I/O is not supported then Event is ignored, and blocking + I/O is performed. If Event is NULL, then blocking I/O is performed. If + Event is not NULL and non blocking I/O is supported, then + nonblocking I/O is performed, and Event will be signaled when the + SCSI Request Packet completes. + + @retval EFI_SUCCESS The SCSI Request Packet was sent by the host. For bi-directional + commands, InTransferLength bytes were transferred from + InDataBuffer. For write and bi-directional commands, + OutTransferLength bytes were transferred by + OutDataBuffer. + @retval EFI_BAD_BUFFER_SIZE The SCSI Request Packet was not executed. The number of bytes that + could be transferred is returned in InTransferLength. For write + and bi-directional commands, OutTransferLength bytes were + transferred by OutDataBuffer. + @retval EFI_NOT_READY The SCSI Request Packet could not be sent because there are too many + SCSI Request Packets already queued. The caller may retry again later. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SCSI Request + Packet. + @retval EFI_INVALID_PARAMETER Target, Lun, or the contents of ScsiRequestPacket are invalid. + @retval EFI_UNSUPPORTED The command described by the SCSI Request Packet is not supported + by the host adapter. This includes the case of Bi-directional SCSI + commands not supported by the implementation. The SCSI Request + Packet was not sent, so no additional status information is available. + @retval EFI_TIMEOUT A timeout occurred while waiting for the SCSI Request Packet to execute. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_PASSTHRU)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun, + IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/** + Used to retrieve the list of legal Target IDs and LUNs for SCSI devices on a SCSI channel. These + can either be the list SCSI devices that are actually present on the SCSI channel, or the list of legal + Target Ids and LUNs for the SCSI channel. Regardless, the caller of this function must probe the + Target ID and LUN returned to see if a SCSI device is actually present at that location on the SCSI + channel. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param Target On input, a pointer to the Target ID (an array of size + TARGET_MAX_BYTES) of a SCSI device present on the SCSI channel. + On output, a pointer to the Target ID (an array of + TARGET_MAX_BYTES) of the next SCSI device present on a SCSI + channel. An input value of 0xF(all bytes in the array are 0xF) in the + Target array retrieves the Target ID of the first SCSI device present on a + SCSI channel. + @param Lun On input, a pointer to the LUN of a SCSI device present on the SCSI + channel. On output, a pointer to the LUN of the next SCSI device present + on a SCSI channel. + + @retval EFI_SUCCESS The Target ID and LUN of the next SCSI device on the SCSI + channel was returned in Target and Lun. + @retval EFI_INVALID_PARAMETER Target array is not all 0xF, and Target and Lun were + not returned on a previous call to GetNextTargetLun(). + @retval EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 **Target, + IN OUT UINT64 *Lun + ); + +/** + Used to allocate and build a device path node for a SCSI device on a SCSI channel. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param Target The Target is an array of size TARGET_MAX_BYTES and it specifies the + Target ID of the SCSI device for which a device path node is to be + allocated and built. Transport drivers may chose to utilize a subset of + this size to suit the representation of targets. For example, a Fibre + Channel driver may use only 8 bytes (WWN) in the array to represent a + FC target. + @param Lun The LUN of the SCSI device for which a device path node is to be + allocated and built. + @param DevicePath A pointer to a single device path node that describes the SCSI device + specified by Target and Lun. This function is responsible for + allocating the buffer DevicePath with the boot service + AllocatePool(). It is the caller's responsibility to free + DevicePath when the caller is finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SCSI device specified by + Target and Lun was allocated and returned in + DevicePath. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_NOT_FOUND The SCSI devices specified by Target and Lun does not exist + on the SCSI channel. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Used to translate a device path node to a Target ID and LUN. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param DevicePath A pointer to a single device path node that describes the SCSI device + on the SCSI channel. + @param Target A pointer to the Target Array which represents the ID of a SCSI device + on the SCSI channel. + @param Lun A pointer to the LUN of a SCSI device on the SCSI channel. + + @retval EFI_SUCCESS DevicePath was successfully translated to a Target ID and + LUN, and they were returned in Target and Lun. + @retval EFI_INVALID_PARAMETER DevicePath or Target or Lun is NULL. + @retval EFI_NOT_FOUND A valid translation from DevicePath to a Target ID and LUN + does not exist. + @retval EFI_UNSUPPORTED This driver does not support the device path node type in + DevicePath. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 **Target, + OUT UINT64 *Lun + ); + +/** + Resets a SCSI channel. This operation resets all the SCSI devices connected to the SCSI channel. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + + @retval EFI_SUCCESS The SCSI channel was reset. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI channel. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI channel. + @retval EFI_UNSUPPORTED The SCSI channel does not support a channel reset operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This + ); + +/** + Resets a SCSI logical unit that is connected to a SCSI channel. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param Target The Target is an array of size TARGET_MAX_BYTE and it represents the + target port ID of the SCSI device containing the SCSI logical unit to + reset. Transport drivers may chose to utilize a subset of this array to suit + the representation of their targets. + @param Lun The LUN of the SCSI device to reset. + + @retval EFI_SUCCESS The SCSI device specified by Target and Lun was reset. + @retval EFI_INVALID_PARAMETER Target or Lun is NULL. + @retval EFI_TIMEOUT A timeout occurred while attempting to reset the SCSI device + specified by Target and Lun. + @retval EFI_UNSUPPORTED The SCSI channel does not support a target reset operation. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the SCSI device + specified by Target and Lun. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun + ); + +/** + Used to retrieve the list of legal Target IDs for SCSI devices on a SCSI channel. These can either + be the list SCSI devices that are actually present on the SCSI channel, or the list of legal Target IDs + for the SCSI channel. Regardless, the caller of this function must probe the Target ID returned to + see if a SCSI device is actually present at that location on the SCSI channel. + + @param This A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance. + @param Target (TARGET_MAX_BYTES) of a SCSI device present on the SCSI channel. + On output, a pointer to the Target ID (an array of + TARGET_MAX_BYTES) of the next SCSI device present on a SCSI + channel. An input value of 0xF(all bytes in the array are 0xF) in the + Target array retrieves the Target ID of the first SCSI device present on a + SCSI channel. + + @retval EFI_SUCCESS The Target ID of the next SCSI device on the SCSI + channel was returned in Target. + @retval EFI_INVALID_PARAMETER Target or Lun is NULL. + @retval EFI_TIMEOUT Target array is not all 0xF, and Target was not + returned on a previous call to GetNextTarget(). + @retval EFI_NOT_FOUND There are no more SCSI devices on this SCSI channel. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET)( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 **Target + ); + +/// +/// The EFI_EXT_SCSI_PASS_THRU_PROTOCOL provides information about a SCSI channel +/// and the ability to send SCI Request Packets to any SCSI device attached to +/// that SCSI channel. The information includes the Target ID of the host controller +/// on the SCSI channel and the attributes of the SCSI channel. +/// +struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL { + /// + /// A pointer to the EFI_EXT_SCSI_PASS_THRU_MODE data for this SCSI channel. + /// + EFI_EXT_SCSI_PASS_THRU_MODE *Mode; + EFI_EXT_SCSI_PASS_THRU_PASSTHRU PassThru; + EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN GetNextTargetLun; + EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath; + EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun; + EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel; + EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN ResetTargetLun; + EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET GetNextTarget; +}; + +extern EFI_GUID gEfiExtScsiPassThruProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SdMmcPassThru.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SdMmcPassThru.h new file mode 100644 index 0000000000..4135a3ba9e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SdMmcPassThru.h @@ -0,0 +1,258 @@ +/** @file + The EFI_SD_MMC_PASS_THRU_PROTOCOL provides the ability to send SD/MMC Commands + to any SD/MMC device attached to the SD compatible pci host controller. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SD_MMC_PASS_THRU_H__ +#define __SD_MMC_PASS_THRU_H__ + +#define EFI_SD_MMC_PASS_THRU_PROTOCOL_GUID \ + { \ + 0x716ef0d9, 0xff83, 0x4f69, {0x81, 0xe9, 0x51, 0x8b, 0xd3, 0x9a, 0x8e, 0x70 } \ + } + +typedef struct _EFI_SD_MMC_PASS_THRU_PROTOCOL EFI_SD_MMC_PASS_THRU_PROTOCOL; + +typedef enum { + SdMmcCommandTypeBc, // Broadcast commands, no response + SdMmcCommandTypeBcr, // Broadcast commands with response + SdMmcCommandTypeAc, // Addressed(point-to-point) commands + SdMmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands +} EFI_SD_MMC_COMMAND_TYPE; + +typedef enum { + SdMmcResponseTypeR1, + SdMmcResponseTypeR1b, + SdMmcResponseTypeR2, + SdMmcResponseTypeR3, + SdMmcResponseTypeR4, + SdMmcResponseTypeR5, + SdMmcResponseTypeR5b, + SdMmcResponseTypeR6, + SdMmcResponseTypeR7 +} EFI_SD_MMC_RESPONSE_TYPE; + +typedef struct _EFI_SD_MMC_COMMAND_BLOCK { + UINT16 CommandIndex; + UINT32 CommandArgument; + UINT32 CommandType; // One of the EFI_SD_MMC_COMMAND_TYPE values + UINT32 ResponseType; // One of the EFI_SD_MMC_RESPONSE_TYPE values +} EFI_SD_MMC_COMMAND_BLOCK; + +typedef struct _EFI_SD_MMC_STATUS_BLOCK { + UINT32 Resp0; + UINT32 Resp1; + UINT32 Resp2; + UINT32 Resp3; +} EFI_SD_MMC_STATUS_BLOCK; + +typedef struct _EFI_SD_MMC_PASS_THRU_COMMAND_PACKET { + UINT64 Timeout; + EFI_SD_MMC_COMMAND_BLOCK *SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK *SdMmcStatusBlk; + VOID *InDataBuffer; + VOID *OutDataBuffer; + UINT32 InTransferLength; + UINT32 OutTransferLength; + EFI_STATUS TransactionStatus; +} EFI_SD_MMC_PASS_THRU_COMMAND_PACKET; + +/** + Sends SD command to an SD card that is attached to the SD controller. + + The PassThru() function sends the SD command specified by Packet to the SD card + specified by Slot. + + If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned. + + If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned. + + If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER + is returned. + + If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL, + EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in,out] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. If Event is + not NULL, then nonblocking I/O is performed, and Event + will be signaled when the Packet completes. + + @retval EFI_SUCCESS The SD Command Packet was sent by the host. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD + command Packet. + @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid. + @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and + OutDataBuffer are NULL. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not + supported by the host controller. + @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the + limit supported by SD card ( i.e. if the number of bytes + exceed the Last LBA). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_MMC_PASS_THRU_PASSTHRU) ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL +); + +/** + Used to retrieve next slot numbers supported by the SD controller. The function + returns information about all available slots (populated or not-populated). + + The GetNextSlot() function retrieves the next slot number on an SD controller. + If on input Slot is 0xFF, then the slot number of the first slot on the SD controller + is returned. + + If Slot is a slot number that was returned on a previous call to GetNextSlot(), then + the slot number of the next slot on the SD controller is returned. + + If Slot is not 0xFF and Slot was not returned on a previous call to GetNextSlot(), + EFI_INVALID_PARAMETER is returned. + + If Slot is the slot number of the last slot on the SD controller, then EFI_NOT_FOUND + is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance. + @param[in,out] Slot On input, a pointer to a slot number on the SD controller. + On output, a pointer to the next slot number on the SD controller. + An input value of 0xFF retrieves the first slot number on the SD + controller. + + @retval EFI_SUCCESS The next slot number on the SD controller was returned in Slot. + @retval EFI_NOT_FOUND There are no more slots on this SD controller. + @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a previous call + to GetNextSlot(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT) ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 *Slot +); + +/** + Used to allocate and build a device path node for an SD card on the SD controller. + + The BuildDevicePath() function allocates and builds a single device node for the SD + card specified by Slot. + + If the SD card specified by Slot is not present on the SD controller, then EFI_NOT_FOUND + is returned. + + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. + + If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES + is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of + DevicePath are initialized to describe the SD card specified by Slot, and EFI_SUCCESS is + returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot Specifies the slot number of the SD card for which a device + path node is to be allocated and built. + @param[out] DevicePath A pointer to a single device path node that describes the SD + card specified by Slot. This function is responsible for + allocating the buffer DevicePath with the boot service + AllocatePool(). It is the caller's responsibility to free + DevicePath when the caller is finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SD card specified by + Slot was allocated and returned in DevicePath. + @retval EFI_NOT_FOUND The SD card specified by Slot does not exist on the SD controller. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate DevicePath. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH) ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath +); + +/** + This function retrieves an SD card slot number based on the input device path. + + The GetSlotNumber() function retrieves slot number for the SD card specified by + the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is returned. + + If DevicePath is not a device path node type that the SD Pass Thru driver supports, + EFI_UNSUPPORTED is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] DevicePath A pointer to the device path node that describes a SD + card on the SD controller. + @param[out] Slot On return, points to the slot number of an SD card on + the SD controller. + + @retval EFI_SUCCESS SD card slot number is returned in Slot. + @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL. + @retval EFI_UNSUPPORTED DevicePath is not a device path node type that the SD + Pass Thru driver supports. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER) ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 *Slot +); + +/** + Resets an SD card that is connected to the SD controller. + + The ResetDevice() function resets the SD card specified by Slot. + + If this SD controller does not support a device reset operation, EFI_UNSUPPORTED is + returned. + + If Slot is not in a valid slot number for this SD controller, EFI_INVALID_PARAMETER + is returned. + + If the device reset operation is completed, EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance. + @param[in] Slot Specifies the slot number of the SD card to be reset. + + @retval EFI_SUCCESS The SD card specified by Slot was reset. + @retval EFI_UNSUPPORTED The SD controller does not support a device reset operation. + @retval EFI_INVALID_PARAMETER Slot number is invalid. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_DEVICE_ERROR The reset command failed due to a device error + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_MMC_PASS_THRU_RESET_DEVICE) ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot +); + +struct _EFI_SD_MMC_PASS_THRU_PROTOCOL { + UINT32 IoAlign; + EFI_SD_MMC_PASS_THRU_PASSTHRU PassThru; + EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT GetNextSlot; + EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath; + EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER GetSlotNumber; + EFI_SD_MMC_PASS_THRU_RESET_DEVICE ResetDevice; +}; + +extern EFI_GUID gEfiSdMmcPassThruProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security.h new file mode 100644 index 0000000000..392db311ae --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security.h @@ -0,0 +1,97 @@ +/** @file + Security Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + Used to provide Security services. Specifically, dependening upon the + authentication state of a discovered driver in a Firmware Volume, the + portable DXE Core Dispatcher will call into the Security Architectural + Protocol (SAP) with the authentication state of the driver. + + This call-out allows for OEM-specific policy decisions to be made, such + as event logging for attested boots, locking flash in response to discovering + an unsigned driver or failed signature check, or other exception response. + + The SAP can also change system behavior by having the DXE core put a driver + in the Schedule-On-Request (SOR) state. This will allow for later disposition + of the driver by platform agent, such as Platform BDS. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_SECURITY_H__ +#define __ARCH_PROTOCOL_SECURITY_H__ + +/// +/// Global ID for the Security Code Architectural Protocol +/// +#define EFI_SECURITY_ARCH_PROTOCOL_GUID \ + { 0xA46423E3, 0x4617, 0x49f1, {0xB9, 0xFF, 0xD1, 0xBF, 0xA9, 0x11, 0x58, 0x39 } } + +typedef struct _EFI_SECURITY_ARCH_PROTOCOL EFI_SECURITY_ARCH_PROTOCOL; + +/** + The EFI_SECURITY_ARCH_PROTOCOL (SAP) is used to abstract platform-specific + policy from the DXE core response to an attempt to use a file that returns a + given status for the authentication check from the section extraction protocol. + + The possible responses in a given SAP implementation may include locking + flash upon failure to authenticate, attestation logging for all signed drivers, + and other exception operations. The File parameter allows for possible logging + within the SAP of the driver. + + If File is NULL, then EFI_INVALID_PARAMETER is returned. + + If the file specified by File with an authentication status specified by + AuthenticationStatus is safe for the DXE Core to use, then EFI_SUCCESS is returned. + + If the file specified by File with an authentication status specified by + AuthenticationStatus is not safe for the DXE Core to use under any circumstances, + then EFI_ACCESS_DENIED is returned. + + If the file specified by File with an authentication status specified by + AuthenticationStatus is not safe for the DXE Core to use right now, but it + might be possible to use it at a future time, then EFI_SECURITY_VIOLATION is + returned. + + @param This The EFI_SECURITY_ARCH_PROTOCOL instance. + @param AuthenticationStatus + This is the authentication type returned from the Section + Extraction protocol. See the Section Extraction Protocol + Specification for details on this type. + @param File This is a pointer to the device path of the file that is + being dispatched. This will optionally be used for logging. + + @retval EFI_SUCCESS The file specified by File did authenticate, and the + platform policy dictates that the DXE Core may use File. + @retval EFI_INVALID_PARAMETER Driver is NULL. + @retval EFI_SECURITY_VIOLATION The file specified by File did not authenticate, and + the platform policy dictates that File should be placed + in the untrusted state. A file may be promoted from + the untrusted to the trusted state at a future time + with a call to the Trust() DXE Service. + @retval EFI_ACCESS_DENIED The file specified by File did not authenticate, and + the platform policy dictates that File should not be + used for any purpose. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SECURITY_FILE_AUTHENTICATION_STATE)( + IN CONST EFI_SECURITY_ARCH_PROTOCOL *This, + IN UINT32 AuthenticationStatus, + IN CONST EFI_DEVICE_PATH_PROTOCOL *File + ); + +/// +/// The EFI_SECURITY_ARCH_PROTOCOL is used to abstract platform-specific policy +/// from the DXE core. This includes locking flash upon failure to authenticate, +/// attestation logging, and other exception operations. +/// +struct _EFI_SECURITY_ARCH_PROTOCOL { + EFI_SECURITY_FILE_AUTHENTICATION_STATE FileAuthenticationState; +}; + +extern EFI_GUID gEfiSecurityArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security2.h new file mode 100644 index 0000000000..95c5dc1b3a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Security2.h @@ -0,0 +1,101 @@ +/** @file + Security2 Architectural Protocol as defined in PI Specification1.2.1 VOLUME 2 DXE + + Abstracts security-specific functions from the DXE Foundation of UEFI Image Verification, + Trusted Computing Group (TCG) measured boot, and User Identity policy for image loading and + consoles. This protocol must be produced by a boot service or runtime DXE driver. + + This protocol is optional and must be published prior to the EFI_SECURITY_ARCH_PROTOCOL. + As a result, the same driver must publish both of these interfaces. + + When both Security and Security2 Architectural Protocols are published, LoadImage must use + them in accordance with the following rules: + The Security2 protocol must be used on every image being loaded. + The Security protocol must be used after the Securiy2 protocol and only on images that + have been read using Firmware Volume protocol. + + When only Security architectural protocol is published, LoadImage must use it on every image + being loaded. + + Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_SECURITY2_H__ +#define __ARCH_PROTOCOL_SECURITY2_H__ + +/// +/// Global ID for the Security2 Code Architectural Protocol +/// +#define EFI_SECURITY2_ARCH_PROTOCOL_GUID \ + { 0x94ab2f58, 0x1438, 0x4ef1, {0x91, 0x52, 0x18, 0x94, 0x1a, 0x3a, 0x0e, 0x68 } } + +typedef struct _EFI_SECURITY2_ARCH_PROTOCOL EFI_SECURITY2_ARCH_PROTOCOL; + +/** + The DXE Foundation uses this service to measure and/or verify a UEFI image. + + This service abstracts the invocation of Trusted Computing Group (TCG) measured boot, UEFI + Secure boot, and UEFI User Identity infrastructure. For the former two, the DXE Foundation + invokes the FileAuthentication() with a DevicePath and corresponding image in + FileBuffer memory. The TCG measurement code will record the FileBuffer contents into the + appropriate PCR. The image verification logic will confirm the integrity and provenance of the + image in FileBuffer of length FileSize . The origin of the image will be DevicePath in + these cases. + If the FileBuffer is NULL, the interface will determine if the DevicePath can be connected + in order to support the User Identification policy. + + @param This The EFI_SECURITY2_ARCH_PROTOCOL instance. + @param File A pointer to the device path of the file that is + being dispatched. This will optionally be used for logging. + @param FileBuffer A pointer to the buffer with the UEFI file image. + @param FileSize The size of the file. + @param BootPolicy A boot policy that was used to call LoadImage() UEFI service. If + FileAuthentication() is invoked not from the LoadImage(), + BootPolicy must be set to FALSE. + + @retval EFI_SUCCESS The file specified by DevicePath and non-NULL + FileBuffer did authenticate, and the platform policy dictates + that the DXE Foundation may use the file. + @retval EFI_SUCCESS The device path specified by NULL device path DevicePath + and non-NULL FileBuffer did authenticate, and the platform + policy dictates that the DXE Foundation may execute the image in + FileBuffer. + @retval EFI_SUCCESS FileBuffer is NULL and current user has permission to start + UEFI device drivers on the device path specified by DevicePath. + @retval EFI_SECURITY_VIOLATION The file specified by DevicePath and FileBuffer did not + authenticate, and the platform policy dictates that the file should be + placed in the untrusted state. The image has been added to the file + execution table. + @retval EFI_ACCESS_DENIED The file specified by File and FileBuffer did not + authenticate, and the platform policy dictates that the DXE + Foundation may not use File. + @retval EFI_SECURITY_VIOLATION FileBuffer is NULL and the user has no + permission to start UEFI device drivers on the device path specified + by DevicePath. + @retval EFI_SECURITY_VIOLATION FileBuffer is not NULL and the user has no permission to load + drivers from the device path specified by DevicePath. The + image has been added into the list of the deferred images. +**/ +typedef EFI_STATUS (EFIAPI *EFI_SECURITY2_FILE_AUTHENTICATION) ( + IN CONST EFI_SECURITY2_ARCH_PROTOCOL *This, + IN CONST EFI_DEVICE_PATH_PROTOCOL *File, OPTIONAL + IN VOID *FileBuffer, + IN UINTN FileSize, + IN BOOLEAN BootPolicy +); + +/// +/// The EFI_SECURITY2_ARCH_PROTOCOL is used to abstract platform-specific policy from the +/// DXE Foundation. This includes measuring the PE/COFF image prior to invoking, comparing the +/// image against a policy (whether a white-list/black-list of public image verification keys +/// or registered hashes). +/// +struct _EFI_SECURITY2_ARCH_PROTOCOL { + EFI_SECURITY2_FILE_AUTHENTICATION FileAuthentication; +}; + +extern EFI_GUID gEfiSecurity2ArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SecurityPolicy.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SecurityPolicy.h new file mode 100644 index 0000000000..d36e588d87 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SecurityPolicy.h @@ -0,0 +1,20 @@ +/** @file + Security Policy protocol as defined in PI Specification VOLUME 2 DXE + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SECURITY_POLICY_H_ +#define _SECURITY_POLICY_H_ + +/// +/// Security policy protocol GUID definition +/// +#define EFI_SECURITY_POLICY_PROTOCOL_GUID \ + {0x78E4D245, 0xCD4D, 0x4a05, {0xA2, 0xBA, 0x47, 0x43, 0xE8, 0x6C, 0xFC, 0xAB} } + +extern EFI_GUID gEfiSecurityPolicyProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SerialIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SerialIo.h new file mode 100644 index 0000000000..3a72653733 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SerialIo.h @@ -0,0 +1,309 @@ +/** @file + Serial IO protocol as defined in the UEFI 2.0 specification. + + Abstraction of a basic serial device. Targeted at 16550 UART, but + could be much more generic. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SERIAL_IO_PROTOCOL_H__ +#define __SERIAL_IO_PROTOCOL_H__ + +#define EFI_SERIAL_IO_PROTOCOL_GUID \ + { \ + 0xBB25CF6F, 0xF1D4, 0x11D2, {0x9A, 0x0C, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0xFD } \ + } + +#define EFI_SERIAL_TERMINAL_DEVICE_TYPE_GUID \ + { \ + 0X6AD9A60F, 0X5815, 0X4C7C, { 0X8A, 0X10, 0X50, 0X53, 0XD2, 0XBF, 0X7A, 0X1B } \ + } + +/// +/// Protocol GUID defined in EFI1.1. +/// +#define SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL_GUID + +typedef struct _EFI_SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL; + + +/// +/// Backward-compatible with EFI1.1. +/// +typedef EFI_SERIAL_IO_PROTOCOL SERIAL_IO_INTERFACE; + +/// +/// Parity type that is computed or checked as each character is transmitted or received. If the +/// device does not support parity, the value is the default parity value. +/// +typedef enum { + DefaultParity, + NoParity, + EvenParity, + OddParity, + MarkParity, + SpaceParity +} EFI_PARITY_TYPE; + +/// +/// Stop bits type +/// +typedef enum { + DefaultStopBits, + OneStopBit, + OneFiveStopBits, + TwoStopBits +} EFI_STOP_BITS_TYPE; + +// +// define for Control bits, grouped by read only, write only, and read write +// +// +// Read Only +// +#define EFI_SERIAL_CLEAR_TO_SEND 0x00000010 +#define EFI_SERIAL_DATA_SET_READY 0x00000020 +#define EFI_SERIAL_RING_INDICATE 0x00000040 +#define EFI_SERIAL_CARRIER_DETECT 0x00000080 +#define EFI_SERIAL_INPUT_BUFFER_EMPTY 0x00000100 +#define EFI_SERIAL_OUTPUT_BUFFER_EMPTY 0x00000200 + +// +// Write Only +// +#define EFI_SERIAL_REQUEST_TO_SEND 0x00000002 +#define EFI_SERIAL_DATA_TERMINAL_READY 0x00000001 + +// +// Read Write +// +#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x00001000 +#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x00002000 +#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x00004000 + +// +// Serial IO Member Functions +// +/** + Reset the serial device. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The serial device could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_RESET)( + IN EFI_SERIAL_IO_PROTOCOL *This + ); + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param This Protocol instance pointer. + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_INVALID_PARAMETER One or more attributes has an unsupported value. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_SET_ATTRIBUTES)( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT64 BaudRate, + IN UINT32 ReceiveFifoDepth, + IN UINT32 Timeout, + IN EFI_PARITY_TYPE Parity, + IN UINT8 DataBits, + IN EFI_STOP_BITS_TYPE StopBits + ); + +/** + Set the control bits on a serial device + + @param This Protocol instance pointer. + @param Control Set the bits of Control that are settable. + + @retval EFI_SUCCESS The new control bits were set on the serial device. + @retval EFI_UNSUPPORTED The serial device does not support this operation. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_SET_CONTROL_BITS)( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT32 Control + ); + +/** + Retrieves the status of thecontrol bits on a serial device + + @param This Protocol instance pointer. + @param Control A pointer to return the current Control signals from the serial device. + + @retval EFI_SUCCESS The control bits were read from the serial device. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_GET_CONTROL_BITS)( + IN EFI_SERIAL_IO_PROTOCOL *This, + OUT UINT32 *Control + ); + +/** + Writes data to a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data actually written. + @param Buffer The buffer of data to write + + @retval EFI_SUCCESS The data was written. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_WRITE)( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Writes data to a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data returned in Buffer. + @param Buffer The buffer to return the data into. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_READ)( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + @par Data Structure Description: + The data values in SERIAL_IO_MODE are read-only and are updated by the code + that produces the SERIAL_IO_PROTOCOL member functions. + + @param ControlMask + A mask for the Control bits that the device supports. The device + must always support the Input Buffer Empty control bit. + + @param TimeOut + If applicable, the number of microseconds to wait before timing out + a Read or Write operation. + + @param BaudRate + If applicable, the current baud rate setting of the device; otherwise, + baud rate has the value of zero to indicate that device runs at the + device's designed speed. + + @param ReceiveFifoDepth + The number of characters the device will buffer on input + + @param DataBits + The number of characters the device will buffer on input + + @param Parity + If applicable, this is the EFI_PARITY_TYPE that is computed or + checked as each character is transmitted or reveived. If the device + does not support parity the value is the default parity value. + + @param StopBits + If applicable, the EFI_STOP_BITS_TYPE number of stop bits per + character. If the device does not support stop bits the value is + the default stop bit values. + +**/ +typedef struct { + UINT32 ControlMask; + + // + // current Attributes + // + UINT32 Timeout; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + UINT32 DataBits; + UINT32 Parity; + UINT32 StopBits; +} EFI_SERIAL_IO_MODE; + +#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000 +#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001 +#define SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION + +/// +/// The Serial I/O protocol is used to communicate with UART-style serial devices. +/// These can be standard UART serial ports in PC-AT systems, serial ports attached +/// to a USB interface, or potentially any character-based I/O device. +/// +struct _EFI_SERIAL_IO_PROTOCOL { + /// + /// The revision to which the EFI_SERIAL_IO_PROTOCOL adheres. All future revisions + /// must be backwards compatible. If a future version is not backwards compatible, + /// it is not the same GUID. + /// + UINT32 Revision; + EFI_SERIAL_RESET Reset; + EFI_SERIAL_SET_ATTRIBUTES SetAttributes; + EFI_SERIAL_SET_CONTROL_BITS SetControl; + EFI_SERIAL_GET_CONTROL_BITS GetControl; + EFI_SERIAL_WRITE Write; + EFI_SERIAL_READ Read; + /// + /// Pointer to SERIAL_IO_MODE data. + /// + EFI_SERIAL_IO_MODE *Mode; + /// + /// Pointer to a GUID identifying the device connected to the serial port. + /// This field is NULL when the protocol is installed by the serial port + /// driver and may be populated by a platform driver for a serial port + /// with a known device attached. The field will remain NULL if there is + /// no platform serial device identification information available. + /// + CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1 +}; + +extern EFI_GUID gEfiSerialIoProtocolGuid; +extern EFI_GUID gEfiSerialTerminalDeviceTypeGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ServiceBinding.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ServiceBinding.h new file mode 100644 index 0000000000..37f44c554c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ServiceBinding.h @@ -0,0 +1,88 @@ +/** @file + UEFI Service Binding Protocol is defined in UEFI specification. + + The file defines the generic Service Binding Protocol functions. + It provides services that are required to create and destroy child + handles that support a given set of protocols. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SERVICE_BINDING_H__ +#define __EFI_SERVICE_BINDING_H__ + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_SERVICE_BINDING_PROTOCOL EFI_SERVICE_BINDING_PROTOCOL; + +/** + Creates a child handle and installs a protocol. + + The CreateChild() function installs a protocol on ChildHandle. + If ChildHandle is a pointer to NULL, then a new handle is created and returned in ChildHandle. + If ChildHandle is not a pointer to NULL, then the protocol installs on the existing ChildHandle. + + @param This Pointer to the EFI_SERVICE_BINDING_PROTOCOL instance. + @param ChildHandle Pointer to the handle of the child to create. If it is NULL, + then a new handle is created. If it is a pointer to an existing UEFI handle, + then the protocol is added to the existing UEFI handle. + + @retval EFI_SUCCES The protocol was added to ChildHandle. + @retval EFI_INVALID_PARAMETER ChildHandle is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to create + the child + @retval other The child handle was not created + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERVICE_BINDING_CREATE_CHILD)( + IN EFI_SERVICE_BINDING_PROTOCOL *This, + IN OUT EFI_HANDLE *ChildHandle + ); + +/** + Destroys a child handle with a protocol installed on it. + + The DestroyChild() function does the opposite of CreateChild(). It removes a protocol + that was installed by CreateChild() from ChildHandle. If the removed protocol is the + last protocol on ChildHandle, then ChildHandle is destroyed. + + @param This Pointer to the EFI_SERVICE_BINDING_PROTOCOL instance. + @param ChildHandle Handle of the child to destroy + + @retval EFI_SUCCES The protocol was removed from ChildHandle. + @retval EFI_UNSUPPORTED ChildHandle does not support the protocol that is being removed. + @retval EFI_INVALID_PARAMETER Child handle is NULL. + @retval EFI_ACCESS_DENIED The protocol could not be removed from the ChildHandle + because its services are being used. + @retval other The child handle was not destroyed + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERVICE_BINDING_DESTROY_CHILD)( + IN EFI_SERVICE_BINDING_PROTOCOL *This, + IN EFI_HANDLE ChildHandle + ); + +/// +/// The EFI_SERVICE_BINDING_PROTOCOL provides member functions to create and destroy +/// child handles. A driver is responsible for adding protocols to the child handle +/// in CreateChild() and removing protocols in DestroyChild(). It is also required +/// that the CreateChild() function opens the parent protocol BY_CHILD_CONTROLLER +/// to establish the parent-child relationship, and closes the protocol in DestroyChild(). +/// The pseudo code for CreateChild() and DestroyChild() is provided to specify the +/// required behavior, not to specify the required implementation. Each consumer of +/// a software protocol is responsible for calling CreateChild() when it requires the +/// protocol and calling DestroyChild() when it is finished with that protocol. +/// +struct _EFI_SERVICE_BINDING_PROTOCOL { + EFI_SERVICE_BINDING_CREATE_CHILD CreateChild; + EFI_SERVICE_BINDING_DESTROY_CHILD DestroyChild; +}; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Shell.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Shell.h new file mode 100644 index 0000000000..9047060ae3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Shell.h @@ -0,0 +1,1262 @@ +/** @file + EFI Shell protocol as defined in the UEFI Shell 2.0 specification including errata. + + (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SHELL_PROTOCOL_H__ +#define __EFI_SHELL_PROTOCOL_H__ + +#include + +#define EFI_SHELL_PROTOCOL_GUID \ + { \ + 0x6302d008, 0x7f9b, 0x4f30, { 0x87, 0xac, 0x60, 0xc9, 0xfe, 0xf5, 0xda, 0x4e } \ + } +typedef VOID *SHELL_FILE_HANDLE; + +typedef enum { + /// + /// The operation completed successfully. + /// + SHELL_SUCCESS = 0, + + /// + /// The image failed to load. + /// + SHELL_LOAD_ERROR = 1, + + /// + /// The parameter was incorrect. + /// + SHELL_INVALID_PARAMETER = 2, + + /// + /// The operation is not supported. + /// + SHELL_UNSUPPORTED = 3, + + /// + /// The buffer was not the proper size for the request. + /// + SHELL_BAD_BUFFER_SIZE = 4, + + /// + /// The buffer was not large enough to hold the requested data. + /// The required buffer size is returned in the appropriate + /// parameter when this error occurs. + /// + SHELL_BUFFER_TOO_SMALL = 5, + + /// + /// There is no data pending upon return. + /// + SHELL_NOT_READY = 6, + + /// + /// The physical device reported an error while attempting the + /// operation. + /// + SHELL_DEVICE_ERROR = 7, + + /// + /// The device cannot be written to. + /// + SHELL_WRITE_PROTECTED = 8, + + /// + /// The resource has run out. + /// + SHELL_OUT_OF_RESOURCES = 9, + + /// + /// An inconsistency was detected on the file system causing the + /// operation to fail. + /// + SHELL_VOLUME_CORRUPTED = 10, + + /// + /// There is no more space on the file system. + /// + SHELL_VOLUME_FULL = 11, + + /// + /// The device does not contain any medium to perform the + /// operation. + /// + SHELL_NO_MEDIA = 12, + + /// + /// The medium in the device has changed since the last + /// access. + /// + SHELL_MEDIA_CHANGED = 13, + + /// + /// The item was not found. + /// + SHELL_NOT_FOUND = 14, + + /// + /// Access was denied. + /// + SHELL_ACCESS_DENIED = 15, + + // note the skipping of 16 and 17 + + /// + /// A timeout time expired. + /// + SHELL_TIMEOUT = 18, + + /// + /// The protocol has not been started. + /// + SHELL_NOT_STARTED = 19, + + /// + /// The protocol has already been started. + /// + SHELL_ALREADY_STARTED = 20, + + /// + /// The operation was aborted. + /// + SHELL_ABORTED = 21, + + // note the skipping of 22, 23, and 24 + + /// + /// A function encountered an internal version that was + /// incompatible with a version requested by the caller. + /// + SHELL_INCOMPATIBLE_VERSION = 25, + + /// + /// The function was not performed due to a security violation. + /// + SHELL_SECURITY_VIOLATION = 26, + + /// + /// The function was performed and resulted in an unequal + /// comparison.. + /// + SHELL_NOT_EQUAL = 27 +} SHELL_STATUS; + + +// replaced EFI_LIST_ENTRY with LIST_ENTRY for simplicity. +// they are identical outside of the name. +typedef struct { + LIST_ENTRY Link; ///< Linked list members. + EFI_STATUS Status; ///< Status of opening the file. Valid only if Handle != NULL. + CONST CHAR16 *FullName; ///< Fully qualified filename. + CONST CHAR16 *FileName; ///< name of this file. + SHELL_FILE_HANDLE Handle; ///< Handle for interacting with the opened file or NULL if closed. + EFI_FILE_INFO *Info; ///< Pointer to the FileInfo struct for this file or NULL. +} EFI_SHELL_FILE_INFO; + +/** + Returns whether any script files are currently being processed. + + @retval TRUE There is at least one script file active. + @retval FALSE No script files are active now. + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_SHELL_BATCH_IS_ACTIVE) ( + VOID + ); + +/** + Closes the file handle. + + This function closes a specified file handle. All 'dirty' cached file data is + flushed to the device, and the file is closed. In all cases, the handle is + closed. + + @param[in] FileHandle The file handle to be closed. + + @retval EFI_SUCCESS The file closed sucessfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_CLOSE_FILE)( + IN SHELL_FILE_HANDLE FileHandle + ); + +/** + Creates a file or directory by name. + + This function creates an empty new file or directory with the specified attributes and + returns the new file's handle. If the file already exists and is read-only, then + EFI_INVALID_PARAMETER will be returned. + + If the file already existed, it is truncated and its attributes updated. If the file is + created successfully, the FileHandle is the file's handle, else, the FileHandle is NULL. + + If the file name begins with >v, then the file handle which is returned refers to the + shell environment variable with the specified name. If the shell environment variable + already exists and is non-volatile then EFI_INVALID_PARAMETER is returned. + + @param[in] FileName Pointer to NULL-terminated file path. + @param[in] FileAttribs The new file's attrbiutes. The different attributes are + described in EFI_FILE_PROTOCOL.Open(). + @param[out] FileHandle On return, points to the created file handle or directory's handle. + + @retval EFI_SUCCESS The file was opened. FileHandle points to the new file's handle. + @retval EFI_INVALID_PARAMETER One of the parameters has an invalid value. + @retval EFI_UNSUPPORTED The file path could not be opened. + @retval EFI_NOT_FOUND The specified file could not be found on the device, or could not + file the file system on the device. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no + longer supported. + @retval EFI_DEVICE_ERROR The device reported an error or can't get the file path according + the DirName. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a file for write + when the media is write-protected. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. + @retval EFI_VOLUME_FULL The volume is full. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_CREATE_FILE)( + IN CONST CHAR16 *FileName, + IN UINT64 FileAttribs, + OUT SHELL_FILE_HANDLE *FileHandle + ); + +/** + Deletes the file specified by the file handle. + + This function closes and deletes a file. In all cases, the file handle is closed. If the file + cannot be deleted, the warning code EFI_WARN_DELETE_FAILURE is returned, but the + handle is still closed. + + @param[in] FileHandle The file handle to delete. + + @retval EFI_SUCCESS The file was closed and deleted and the handle was closed. + @retval EFI_WARN_DELETE_FAILURE The handle was closed but the file was not deleted. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_DELETE_FILE)( + IN SHELL_FILE_HANDLE FileHandle + ); + +/** + Deletes the file specified by the file name. + + This function deletes a file. + + @param[in] FileName Points to the NULL-terminated file name. + + @retval EFI_SUCCESS The file was deleted. + @retval EFI_WARN_DELETE_FAILURE The handle was closed but the file was not deleted. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_DELETE_FILE_BY_NAME)( + IN CONST CHAR16 *FileName + ); + +/** + Disables the page break output mode. +**/ +typedef +VOID +(EFIAPI *EFI_SHELL_DISABLE_PAGE_BREAK) ( + VOID + ); + +/** + Enables the page break output mode. +**/ +typedef +VOID +(EFIAPI *EFI_SHELL_ENABLE_PAGE_BREAK) ( + VOID + ); + +/** + Execute the command line. + + This function creates a nested instance of the shell and executes the specified + command (CommandLine) with the specified environment (Environment). Upon return, + the status code returned by the specified command is placed in StatusCode. + + If Environment is NULL, then the current environment is used and all changes made + by the commands executed will be reflected in the current environment. If the + Environment is non-NULL, then the changes made will be discarded. + + The CommandLine is executed from the current working directory on the current + device. + + @param[in] ParentImageHandle A handle of the image that is executing the specified + command line. + @param[in] CommandLine Points to the NULL-terminated UCS-2 encoded string + containing the command line. If NULL then the command- + line will be empty. + @param[in] Environment Points to a NULL-terminated array of environment + variables with the format 'x=y', where x is the + environment variable name and y is the value. If this + is NULL, then the current shell environment is used. + @param[out] ErrorCode Points to the status code returned by the command. + + @retval EFI_SUCCESS The command executed successfully. The status code + returned by the command is pointed to by StatusCode. + @retval EFI_INVALID_PARAMETER The parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Out of resources. + @retval EFI_UNSUPPORTED Nested shell invocations are not allowed. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_EXECUTE) ( + IN EFI_HANDLE *ParentImageHandle, + IN CHAR16 *CommandLine OPTIONAL, + IN CHAR16 **Environment OPTIONAL, + OUT EFI_STATUS *StatusCode OPTIONAL + ); + +/** + Find files that match a specified pattern. + + This function searches for all files and directories that match the specified + FilePattern. The FilePattern can contain wild-card characters. The resulting file + information is placed in the file list FileList. + + The files in the file list are not opened. The OpenMode field is set to 0 and the FileInfo + field is set to NULL. + + @param[in] FilePattern Points to a NULL-terminated shell file path, including wildcards. + @param[out] FileList On return, points to the start of a file list containing the names + of all matching files or else points to NULL if no matching files + were found. + + @retval EFI_SUCCESS Files found. + @retval EFI_NOT_FOUND No files found. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_FIND_FILES)( + IN CONST CHAR16 *FilePattern, + OUT EFI_SHELL_FILE_INFO **FileList + ); + +/** + Find all files in a specified directory. + + @param[in] FileDirHandle Handle of the directory to search. + @param[out] FileList On return, points to the list of files in the directory + or NULL if there are no files in the directory. + + @retval EFI_SUCCESS File information was returned successfully. + @retval EFI_VOLUME_CORRUPTED The file system structures have been corrupted. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_NO_MEDIA The device media is not present. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_FIND_FILES_IN_DIR)( +IN SHELL_FILE_HANDLE FileDirHandle, +OUT EFI_SHELL_FILE_INFO **FileList +); + +/** + Flushes data back to a device. + + This function flushes all modified data associated with a file to a device. + + @param[in] FileHandle The handle of the file to flush. + + @retval EFI_SUCCESS The data was flushed. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read-only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_FLUSH_FILE)( + IN SHELL_FILE_HANDLE FileHandle + ); + +/** + Frees the file list. + + This function cleans up the file list and any related data structures. It has no + impact on the files themselves. + + @param[in] FileList The file list to free. Type EFI_SHELL_FILE_INFO is + defined in OpenFileList(). + + @retval EFI_SUCCESS Free the file list successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_FREE_FILE_LIST) ( + IN EFI_SHELL_FILE_INFO **FileList + ); + +/** + Returns the current directory on the specified device. + + If FileSystemMapping is NULL, it returns the current working directory. If the + FileSystemMapping is not NULL, it returns the current directory associated with the + FileSystemMapping. In both cases, the returned name includes the file system + mapping (i.e. fs0:\current-dir). + + Note that the current directory string should exclude the tailing backslash character. + + @param[in] FileSystemMapping A pointer to the file system mapping. If NULL, + then the current working directory is returned. + + @retval !=NULL The current directory. + @retval NULL Current directory does not exist. +**/ +typedef +CONST CHAR16 * +(EFIAPI *EFI_SHELL_GET_CUR_DIR) ( + IN CONST CHAR16 *FileSystemMapping OPTIONAL + ); + +typedef UINT32 EFI_SHELL_DEVICE_NAME_FLAGS; +#define EFI_DEVICE_NAME_USE_COMPONENT_NAME 0x00000001 +#define EFI_DEVICE_NAME_USE_DEVICE_PATH 0x00000002 + +/** + Gets the name of the device specified by the device handle. + + This function gets the user-readable name of the device specified by the device + handle. If no user-readable name could be generated, then *BestDeviceName will be + NULL and EFI_NOT_FOUND will be returned. + + If EFI_DEVICE_NAME_USE_COMPONENT_NAME is set, then the function will return the + device's name using the EFI_COMPONENT_NAME2_PROTOCOL, if present on + DeviceHandle. + + If EFI_DEVICE_NAME_USE_DEVICE_PATH is set, then the function will return the + device's name using the EFI_DEVICE_PATH_PROTOCOL, if present on DeviceHandle. + If both EFI_DEVICE_NAME_USE_COMPONENT_NAME and + EFI_DEVICE_NAME_USE_DEVICE_PATH are set, then + EFI_DEVICE_NAME_USE_COMPONENT_NAME will have higher priority. + + @param[in] DeviceHandle The handle of the device. + @param[in] Flags Determines the possible sources of component names. + @param[in] Language A pointer to the language specified for the device + name, in the same format as described in the UEFI + specification, Appendix M. + @param[out] BestDeviceName On return, points to the callee-allocated NULL- + terminated name of the device. If no device name + could be found, points to NULL. The name must be + freed by the caller... + + @retval EFI_SUCCESS Get the name successfully. + @retval EFI_NOT_FOUND Fail to get the device name. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_DEVICE_NAME) ( + IN EFI_HANDLE DeviceHandle, + IN EFI_SHELL_DEVICE_NAME_FLAGS Flags, + IN CHAR8 *Language, + OUT CHAR16 **BestDeviceName + ); + +/** + Gets the device path from the mapping. + + This function gets the device path associated with a mapping. + + @param[in] Mapping A pointer to the mapping + + @retval !=NULL Pointer to the device path that corresponds to the + device mapping. The returned pointer does not need + to be freed. + @retval NULL There is no device path associated with the + specified mapping. +**/ +typedef +CONST EFI_DEVICE_PATH_PROTOCOL * +(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_MAP) ( + IN CONST CHAR16 *Mapping + ); + +/** + Converts a file system style name to a device path. + + This function converts a file system style name to a device path, by replacing any + mapping references to the associated device path. + + @param[in] Path The pointer to the path. + + @return The pointer of the file path. The file path is callee + allocated and should be freed by the caller. +**/ +typedef +EFI_DEVICE_PATH_PROTOCOL * +(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH) ( + IN CONST CHAR16 *Path + ); + +/** + Gets either a single or list of environment variables. + + If name is not NULL then this function returns the current value of the specified + environment variable. + + If Name is NULL than a list of all environment variable names is returned. Each a + NULL terminated string with a double NULL terminating the list. + + @param[in] Name A pointer to the environment variable name. If + Name is NULL, then the function will return all + of the defined shell environment variables. In + the case where multiple environment variables are + being returned, each variable will be terminated by + a NULL, and the list will be terminated by a double + NULL. + + @return A pointer to the returned string. + The returned pointer does not need to be freed by the caller. + + @retval NULL The environment variable doesn't exist or there are + no environment variables. +**/ +typedef +CONST CHAR16 * +(EFIAPI *EFI_SHELL_GET_ENV) ( + IN CONST CHAR16 *Name OPTIONAL + ); + +/** + Gets the environment variable and Attributes, or list of environment variables. Can be + used instead of GetEnv(). + + This function returns the current value of the specified environment variable and + the Attributes. If no variable name was specified, then all of the known + variables will be returned. + + @param[in] Name A pointer to the environment variable name. If Name is NULL, + then the function will return all of the defined shell + environment variables. In the case where multiple environment + variables are being returned, each variable will be terminated + by a NULL, and the list will be terminated by a double NULL. + @param[out] Attributes If not NULL, a pointer to the returned attributes bitmask for + the environment variable. In the case where Name is NULL, and + multiple environment variables are being returned, Attributes + is undefined. + + @retval NULL The environment variable doesn't exist. + @return The environment variable's value. The returned pointer does not + need to be freed by the caller. +**/ +typedef +CONST CHAR16 * +(EFIAPI *EFI_SHELL_GET_ENV_EX) ( + IN CONST CHAR16 *Name, + OUT UINT32 *Attributes OPTIONAL + ); + +/** + Gets the file information from an open file handle. + + This function allocates a buffer to store the file's information. It's the caller's + responsibility to free the buffer. + + @param[in] FileHandle A File Handle. + + @retval NULL Cannot get the file info. + @return A pointer to a buffer with file information. +**/ +typedef +EFI_FILE_INFO * +(EFIAPI *EFI_SHELL_GET_FILE_INFO)( + IN SHELL_FILE_HANDLE FileHandle + ); + +/** + Converts a device path to a file system-style path. + + This function converts a device path to a file system path by replacing part, or all, of + the device path with the file-system mapping. If there are more than one application + file system mappings, the one that most closely matches Path will be used. + + @param[in] Path The pointer to the device path. + + @return The pointer of the NULL-terminated file path. The path + is callee-allocated and should be freed by the caller. +**/ +typedef +CHAR16 * +(EFIAPI *EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH) ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *Path + ); + +/** + Gets a file's current position. + + This function returns the current file position for the file handle. For directories, the + current file position has no meaning outside of the file system driver and as such, the + operation is not supported. + + @param[in] FileHandle The file handle on which to get the current position. + @param[out] Position Byte position from the start of the file. + + @retval EFI_SUCCESS Data was accessed. + @retval EFI_UNSUPPORTED The request is not valid on open directories. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_FILE_POSITION)( + IN SHELL_FILE_HANDLE FileHandle, + OUT UINT64 *Position + ); + +/** + Gets the size of a file. + + This function returns the size of the file specified by FileHandle. + + @param[in] FileHandle The handle of the file. + @param[out] Size The size of this file. + + @retval EFI_SUCCESS Get the file's size. + @retval EFI_DEVICE_ERROR Can't access the file. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_FILE_SIZE)( + IN SHELL_FILE_HANDLE FileHandle, + OUT UINT64 *Size + ); + +/** + Get the GUID value from a human readable name. + + If GuidName is a known GUID name, then update Guid to have the correct value for + that GUID. + + This function is only available when the major and minor versions in the + EfiShellProtocol are greater than or equal to 2 and 1, respectively. + + @param[in] GuidName A pointer to the localized name for the GUID being queried. + @param[out] Guid A pointer to the GUID structure to be filled in. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_INVALID_PARAMETER Guid was NULL. + @retval EFI_INVALID_PARAMETER GuidName was NULL. + @retval EFI_NOT_FOUND GuidName is not a known GUID Name. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_GUID_FROM_NAME)( + IN CONST CHAR16 *GuidName, + OUT EFI_GUID *Guid + ); + +/** + Get the human readable name for a GUID from the value. + + If Guid is assigned a name, then update *GuidName to point to the name. The callee + should not modify the value. + + This function is only available when the major and minor versions in the + EfiShellProtocol are greater than or equal to 2 and 1, respectively. + + @param[in] Guid A pointer to the GUID being queried. + @param[out] GuidName A pointer to a pointer the localized to name for the GUID being requested + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_INVALID_PARAMETER Guid was NULL. + @retval EFI_INVALID_PARAMETER GuidName was NULL. + @retval EFI_NOT_FOUND Guid is not assigned a name. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_GUID_NAME)( + IN CONST EFI_GUID *Guid, + OUT CONST CHAR16 **GuidName + ); + +/** + Return help information about a specific command. + + This function returns the help information for the specified command. The help text + can be internal to the shell or can be from a UEFI Shell manual page. + + If Sections is specified, then each section name listed will be compared in a casesensitive + manner, to the section names described in Appendix B. If the section exists, + it will be appended to the returned help text. If the section does not exist, no + information will be returned. If Sections is NULL, then all help text information + available will be returned. + + @param[in] Command Points to the NULL-terminated UEFI Shell command name. + @param[in] Sections Points to the NULL-terminated comma-delimited + section names to return. If NULL, then all + sections will be returned. + @param[out] HelpText On return, points to a callee-allocated buffer + containing all specified help text. + + @retval EFI_SUCCESS The help text was returned. + @retval EFI_OUT_OF_RESOURCES The necessary buffer could not be allocated to hold the + returned help text. + @retval EFI_INVALID_PARAMETER HelpText is NULL. + @retval EFI_NOT_FOUND There is no help text available for Command. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_GET_HELP_TEXT) ( + IN CONST CHAR16 *Command, + IN CONST CHAR16 *Sections OPTIONAL, + OUT CHAR16 **HelpText + ); + +/** + Gets the mapping(s) that most closely matches the device path. + + This function gets the mapping which corresponds to the device path *DevicePath. If + there is no exact match, then the mapping which most closely matches *DevicePath + is returned, and *DevicePath is updated to point to the remaining portion of the + device path. If there is an exact match, the mapping is returned and *DevicePath + points to the end-of-device-path node. + + If there are multiple map names they will be semi-colon seperated in the + NULL-terminated string. + + @param[in, out] DevicePath On entry, points to a device path pointer. On + exit, updates the pointer to point to the + portion of the device path after the mapping. + + @retval NULL No mapping was found. + @retval !=NULL Pointer to NULL-terminated mapping. The buffer + is callee allocated and should be freed by the caller. +**/ +typedef +CONST CHAR16 * +(EFIAPI *EFI_SHELL_GET_MAP_FROM_DEVICE_PATH) ( + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + Gets the enable status of the page break output mode. + + User can use this function to determine current page break mode. + + @retval TRUE The page break output mode is enabled. + @retval FALSE The page break output mode is disabled. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_SHELL_GET_PAGE_BREAK) ( + VOID + ); + +/** + Judges whether the active shell is the root shell. + + This function makes the user to know that whether the active Shell is the root shell. + + @retval TRUE The active Shell is the root Shell. + @retval FALSE The active Shell is NOT the root Shell. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_SHELL_IS_ROOT_SHELL) ( +VOID +); + +/** + Opens a file or a directory by file name. + + This function opens the specified file in the specified OpenMode and returns a file + handle. + If the file name begins with '>v', then the file handle which is returned refers to the + shell environment variable with the specified name. If the shell environment variable + exists, is non-volatile and the OpenMode indicates EFI_FILE_MODE_WRITE, then + EFI_INVALID_PARAMETER is returned. + + If the file name is '>i', then the file handle which is returned refers to the standard + input. If the OpenMode indicates EFI_FILE_MODE_WRITE, then EFI_INVALID_PARAMETER + is returned. + + If the file name is '>o', then the file handle which is returned refers to the standard + output. If the OpenMode indicates EFI_FILE_MODE_READ, then EFI_INVALID_PARAMETER + is returned. + + If the file name is '>e', then the file handle which is returned refers to the standard + error. If the OpenMode indicates EFI_FILE_MODE_READ, then EFI_INVALID_PARAMETER + is returned. + + If the file name is 'NUL', then the file handle that is returned refers to the standard NUL + file. If the OpenMode indicates EFI_FILE_MODE_READ, then EFI_INVALID_PARAMETER is + returned. + + If return EFI_SUCCESS, the FileHandle is the opened file's handle, else, the + FileHandle is NULL. + + @param[in] FileName Points to the NULL-terminated UCS-2 encoded file name. + @param[out] FileHandle On return, points to the file handle. + @param[in] OpenMode File open mode. Either EFI_FILE_MODE_READ or + EFI_FILE_MODE_WRITE from section 12.4 of the UEFI + Specification. + @retval EFI_SUCCESS The file was opened. FileHandle has the opened file's handle. + @retval EFI_INVALID_PARAMETER One of the parameters has an invalid value. FileHandle is NULL. + @retval EFI_UNSUPPORTED Could not open the file path. FileHandle is NULL. + @retval EFI_NOT_FOUND The specified file could not be found on the device or the file + system could not be found on the device. FileHandle is NULL. + @retval EFI_NO_MEDIA The device has no medium. FileHandle is NULL. + @retval EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no + longer supported. FileHandle is NULL. + @retval EFI_DEVICE_ERROR The device reported an error or can't get the file path according + the FileName. FileHandle is NULL. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. FileHandle is NULL. + @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a file for write + when the media is write-protected. FileHandle is NULL. + @retval EFI_ACCESS_DENIED The service denied access to the file. FileHandle is NULL. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. FileHandle + is NULL. + @retval EFI_VOLUME_FULL The volume is full. FileHandle is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_OPEN_FILE_BY_NAME) ( + IN CONST CHAR16 *FileName, + OUT SHELL_FILE_HANDLE *FileHandle, + IN UINT64 OpenMode + ); + +/** + Opens the files that match the path specified. + + This function opens all of the files specified by Path. Wildcards are processed + according to the rules specified in UEFI Shell 2.0 spec section 3.7.1. Each + matching file has an EFI_SHELL_FILE_INFO structure created in a linked list. + + @param[in] Path A pointer to the path string. + @param[in] OpenMode Specifies the mode used to open each file, EFI_FILE_MODE_READ or + EFI_FILE_MODE_WRITE. + @param[in, out] FileList Points to the start of a list of files opened. + + @retval EFI_SUCCESS Create the file list successfully. + @return Can't create the file list. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_OPEN_FILE_LIST) ( + IN CHAR16 *Path, + IN UINT64 OpenMode, + IN OUT EFI_SHELL_FILE_INFO **FileList + ); + +/** + Opens the root directory of a device. + + This function opens the root directory of a device and returns a file handle to it. + + @param[in] DevicePath Points to the device path corresponding to the device where the + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL is installed. + @param[out] FileHandle On exit, points to the file handle corresponding to the root directory on the + device. + + @retval EFI_SUCCESS Root opened successfully. + @retval EFI_NOT_FOUND EFI_SIMPLE_FILE_SYSTEM could not be found or the root directory + could not be opened. + @retval EFI_VOLUME_CORRUPTED The data structures in the volume were corrupted. + @retval EFI_DEVICE_ERROR The device had an error. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_OPEN_ROOT)( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT SHELL_FILE_HANDLE *FileHandle + ); + +/** + Opens the root directory of a device on a handle. + + This function opens the root directory of a device and returns a file handle to it. + + @param[in] DeviceHandle The handle of the device that contains the volume. + @param[out] FileHandle On exit, points to the file handle corresponding to the root directory on the + device. + + @retval EFI_SUCCESS Root opened successfully. + @retval EFI_NOT_FOUND EFI_SIMPLE_FILE_SYSTEM could not be found or the root directory + could not be opened. + @retval EFI_VOLUME_CORRUPTED The data structures in the volume were corrupted. + @retval EFI_DEVICE_ERROR The device had an error. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_OPEN_ROOT_BY_HANDLE)( + IN EFI_HANDLE DeviceHandle, + OUT SHELL_FILE_HANDLE *FileHandle + ); + +/** + Reads data from the file. + + If FileHandle is not a directory, the function reads the requested number of bytes + from the file at the file's current position and returns them in Buffer. If the read goes + beyond the end of the file, the read length is truncated to the end of the file. The file's + current position is increased by the number of bytes returned. + If FileHandle is a directory, then an error is returned. + + @param[in] FileHandle The opened file handle for read. + @param[in] ReadSize On input, the size of Buffer, in bytes. On output, the amount of data read. + @param[in, out] Buffer The buffer in which data is read. + + @retval EFI_SUCCESS Data was read. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TO_SMALL Buffer is too small. ReadSize contains required size. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_READ_FILE) ( + IN SHELL_FILE_HANDLE FileHandle, + IN OUT UINTN *ReadSize, + IN OUT VOID *Buffer + ); + +/** + Register a GUID and a localized human readable name for it. + + If Guid is not assigned a name, then assign GuidName to Guid. This list of GUID + names must be used whenever a shell command outputs GUID information. + + This function is only available when the major and minor versions in the + EfiShellProtocol are greater than or equal to 2 and 1, respectively. + + @param[in] Guid A pointer to the GUID being registered. + @param[in] GuidName A pointer to the localized name for the GUID being registered. + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_INVALID_PARAMETER Guid was NULL. + @retval EFI_INVALID_PARAMETER GuidName was NULL. + @retval EFI_ACCESS_DENIED Guid already is assigned a name. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_REGISTER_GUID_NAME)( + IN CONST EFI_GUID *Guid, + IN CONST CHAR16 *GuidName + ); + +/** + Deletes the duplicate file names files in the given file list. + + @param[in] FileList A pointer to the first entry in the file list. + + @retval EFI_SUCCESS Always success. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_REMOVE_DUP_IN_FILE_LIST) ( + IN EFI_SHELL_FILE_INFO **FileList + ); + +/** + Changes a shell command alias. + + This function creates an alias for a shell command. + + @param[in] Command Points to the NULL-terminated shell command or existing alias. + @param[in] Alias Points to the NULL-terminated alias for the shell command. If this is NULL, and + Command refers to an alias, that alias will be deleted. + @param[in] Replace If TRUE and the alias already exists, then the existing alias will be replaced. If + FALSE and the alias already exists, then the existing alias is unchanged and + EFI_ACCESS_DENIED is returned. + @param[in] Volatile if TRUE the Alias being set will be stored in a volatile fashion. if FALSE the + Alias being set will be stored in a non-volatile fashion. + + @retval EFI_SUCCESS Alias created or deleted successfully. + @retval EFI_ACCESS_DENIED The alias is a built-in alias or already existed and Replace was set to + FALSE. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_ALIAS)( + IN CONST CHAR16 *Command, + IN CONST CHAR16 *Alias, + IN BOOLEAN Replace, + IN BOOLEAN Volatile + ); + +/** + This function returns the command associated with a alias or a list of all + alias'. + + @param[in] Alias Points to the NULL-terminated shell alias. + If this parameter is NULL, then all + aliases will be returned in ReturnedData. + @param[out] Volatile Upon return of a single command if TRUE indicates + this is stored in a volatile fashion. FALSE otherwise. + @return If Alias is not NULL, it will return a pointer to + the NULL-terminated command for that alias. + If Alias is NULL, ReturnedData points to a ';' + delimited list of alias (e.g. + ReturnedData = "dir;del;copy;mfp") that is NULL-terminated. + @retval NULL An error ocurred. + @retval NULL Alias was not a valid Alias. +**/ +typedef +CONST CHAR16 * +(EFIAPI *EFI_SHELL_GET_ALIAS)( + IN CONST CHAR16 *Alias, + OUT BOOLEAN *Volatile OPTIONAL + ); + +/** + Changes the current directory on the specified device. + + If the FileSystem is NULL, and the directory Dir does not contain a file system's + mapped name, this function changes the current working directory. If FileSystem is + NULL and the directory Dir contains a mapped name, then the current file system and + the current directory on that file system are changed. + + If FileSystem is not NULL, and Dir is NULL, then this changes the current working file + system. + + If FileSystem is not NULL and Dir is not NULL, then this function changes the current + directory on the specified file system. + + If the current working directory or the current working file system is changed then the + %cwd% environment variable will be updated. + + @param[in] FileSystem A pointer to the file system's mapped name. If NULL, then the current working + directory is changed. + @param[in] Dir Points to the NULL-terminated directory on the device specified by FileSystem. + + @retval NULL Current directory does not exist. + @return The current directory. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_CUR_DIR) ( + IN CONST CHAR16 *FileSystem OPTIONAL, + IN CONST CHAR16 *Dir + ); + +/** + Sets the environment variable. + + This function changes the current value of the specified environment variable. If the + environment variable exists and the Value is an empty string, then the environment + variable is deleted. If the environment variable exists and the Value is not an empty + string, then the value of the environment variable is changed. If the environment + variable does not exist and the Value is an empty string, there is no action. If the + environment variable does not exist and the Value is a non-empty string, then the + environment variable is created and assigned the specified value. + + For a description of volatile and non-volatile environment variables, see UEFI Shell + 2.0 specification section 3.6.1. + + @param[in] Name Points to the NULL-terminated environment variable name. + @param[in] Value Points to the NULL-terminated environment variable value. If the value is an + empty string then the environment variable is deleted. + @param[in] Volatile Indicates whether the variable is non-volatile (FALSE) or volatile (TRUE). + + @retval EFI_SUCCESS The environment variable was successfully updated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_ENV) ( + IN CONST CHAR16 *Name, + IN CONST CHAR16 *Value, + IN BOOLEAN Volatile + ); + +/** + Sets the file information to an opened file handle. + + This function changes file information. All file information in the EFI_FILE_INFO + struct will be updated to the passed in data. + + @param[in] FileHandle A file handle. + @param[in] FileInfo Points to new file information. + + @retval EFI_SUCCESS The information was set. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read-only. + @retval EFI_VOLUME_FULL The volume is full. + @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size of EFI_FILE_INFO. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_FILE_INFO)( + IN SHELL_FILE_HANDLE FileHandle, + IN CONST EFI_FILE_INFO *FileInfo + ); + +/** + Sets a file's current position. + + This function sets the current file position for the handle to the position supplied. With + the exception of seeking to position 0xFFFFFFFFFFFFFFFF, only absolute positioning is + supported, and seeking past the end of the file is allowed (a subsequent write would + grow the file). Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position + to be set to the end of the file. + + @param[in] FileHandle The file handle on which requested position will be set. + @param[in] Position Byte position from the start of the file. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open directories. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_FILE_POSITION)( + IN SHELL_FILE_HANDLE FileHandle, + IN UINT64 Position + ); + +/** + This function creates a mapping for a device path. + + @param[in] DevicePath Points to the device path. If this is NULL and Mapping points to a valid mapping, + then the mapping will be deleted. + @param[in] Mapping Points to the NULL-terminated mapping for the device path. + + @retval EFI_SUCCESS Mapping created or deleted successfully. + @retval EFI_NO_MAPPING There is no handle that corresponds exactly to DevicePath. See the + boot service function LocateDevicePath(). + @retval EFI_ACCESS_DENIED The mapping is a built-in alias. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_SET_MAP)( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN CONST CHAR16 *Mapping + ); + +/** + Writes data to the file. + + This function writes the specified number of bytes to the file at the current file position. + The current file position is advanced the actual number of bytes written, which is + returned in BufferSize. Partial writes only occur when there has been a data error + during the write attempt (such as "volume space full"). The file automatically grows to + hold the data, if required. + + Direct writes to opened directories are not supported. + + @param[in] FileHandle The opened file handle for writing. + @param[in, out] BufferSize On input, size of Buffer. + @param[in] Buffer The buffer in which data to write. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to open directory are not supported. + @retval EFI_NO_MEDIA The device has no media. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The device is write-protected. + @retval EFI_ACCESS_DENIED The file was open for read only. + @retval EFI_VOLUME_FULL The volume is full. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SHELL_WRITE_FILE)( + IN SHELL_FILE_HANDLE FileHandle, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +// +// EFI_SHELL_PROTOCOL has been updated since UEFI Shell Spec 2.0 +// Usage of this protocol will require version checking before attempting +// to use any new members. There is no need to check the version for +// members that existed in UEFI Shell Spec 2.0. +// +// Update below for any future UEFI Shell spec changes to this protocol. +// +// Check EFI_SHELL_PROTOCOL MajorVersion and MinorVersion: +// if ((2 == gEfiShellProtocol->MajorVersion) && +// (0 == gEfiShellProtocol->MinorVersion)) { +// // +// // Cannot call: +// // RegisterGuidName - UEFI Shell 2.1 +// // GetGuidName - UEFI Shell 2.1 +// // GetGuidFromName - UEFI Shell 2.1 +// // GetEnvEx - UEFI Shell 2.1 +// // +// } else { +// // +// // Can use all members +// // +// } +// +typedef struct _EFI_SHELL_PROTOCOL { + EFI_SHELL_EXECUTE Execute; + EFI_SHELL_GET_ENV GetEnv; + EFI_SHELL_SET_ENV SetEnv; + EFI_SHELL_GET_ALIAS GetAlias; + EFI_SHELL_SET_ALIAS SetAlias; + EFI_SHELL_GET_HELP_TEXT GetHelpText; + EFI_SHELL_GET_DEVICE_PATH_FROM_MAP GetDevicePathFromMap; + EFI_SHELL_GET_MAP_FROM_DEVICE_PATH GetMapFromDevicePath; + EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH GetDevicePathFromFilePath; + EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH GetFilePathFromDevicePath; + EFI_SHELL_SET_MAP SetMap; + EFI_SHELL_GET_CUR_DIR GetCurDir; + EFI_SHELL_SET_CUR_DIR SetCurDir; + EFI_SHELL_OPEN_FILE_LIST OpenFileList; + EFI_SHELL_FREE_FILE_LIST FreeFileList; + EFI_SHELL_REMOVE_DUP_IN_FILE_LIST RemoveDupInFileList; + EFI_SHELL_BATCH_IS_ACTIVE BatchIsActive; + EFI_SHELL_IS_ROOT_SHELL IsRootShell; + EFI_SHELL_ENABLE_PAGE_BREAK EnablePageBreak; + EFI_SHELL_DISABLE_PAGE_BREAK DisablePageBreak; + EFI_SHELL_GET_PAGE_BREAK GetPageBreak; + EFI_SHELL_GET_DEVICE_NAME GetDeviceName; + EFI_SHELL_GET_FILE_INFO GetFileInfo; + EFI_SHELL_SET_FILE_INFO SetFileInfo; + EFI_SHELL_OPEN_FILE_BY_NAME OpenFileByName; + EFI_SHELL_CLOSE_FILE CloseFile; + EFI_SHELL_CREATE_FILE CreateFile; + EFI_SHELL_READ_FILE ReadFile; + EFI_SHELL_WRITE_FILE WriteFile; + EFI_SHELL_DELETE_FILE DeleteFile; + EFI_SHELL_DELETE_FILE_BY_NAME DeleteFileByName; + EFI_SHELL_GET_FILE_POSITION GetFilePosition; + EFI_SHELL_SET_FILE_POSITION SetFilePosition; + EFI_SHELL_FLUSH_FILE FlushFile; + EFI_SHELL_FIND_FILES FindFiles; + EFI_SHELL_FIND_FILES_IN_DIR FindFilesInDir; + EFI_SHELL_GET_FILE_SIZE GetFileSize; + EFI_SHELL_OPEN_ROOT OpenRoot; + EFI_SHELL_OPEN_ROOT_BY_HANDLE OpenRootByHandle; + EFI_EVENT ExecutionBreak; + UINT32 MajorVersion; + UINT32 MinorVersion; + // Added for Shell 2.1 + EFI_SHELL_REGISTER_GUID_NAME RegisterGuidName; + EFI_SHELL_GET_GUID_NAME GetGuidName; + EFI_SHELL_GET_GUID_FROM_NAME GetGuidFromName; + EFI_SHELL_GET_ENV_EX GetEnvEx; +} EFI_SHELL_PROTOCOL; + +extern EFI_GUID gEfiShellProtocolGuid; + +enum ShellVersion { + SHELL_MAJOR_VERSION = 2, + SHELL_MINOR_VERSION = 2 +}; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellDynamicCommand.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellDynamicCommand.h new file mode 100644 index 0000000000..58ae0b8447 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellDynamicCommand.h @@ -0,0 +1,79 @@ +/** @file + EFI Shell Dynamic Command registration protocol + + (C) Copyright 2012-2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL_H__ +#define __EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL_H__ + +#include +#include + +// {3C7200E9-005F-4EA4-87DE-A3DFAC8A27C3} +#define EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL_GUID \ + { \ + 0x3c7200e9, 0x005f, 0x4ea4, { 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 } \ + } + + +// +// Define for forward reference. +// +typedef struct _EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL; + + +/** + This is the shell command handler function pointer callback type. This + function handles the command when it is invoked in the shell. + + @param[in] This The instance of the EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL. + @param[in] SystemTable The pointer to the system table. + @param[in] ShellParameters The parameters associated with the command. + @param[in] Shell The instance of the shell protocol used in the context + of processing this command. + + @return EFI_SUCCESS the operation was sucessful + @return other the operation failed. +**/ +typedef +SHELL_STATUS +(EFIAPI * SHELL_COMMAND_HANDLER)( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN EFI_SYSTEM_TABLE *SystemTable, + IN EFI_SHELL_PARAMETERS_PROTOCOL *ShellParameters, + IN EFI_SHELL_PROTOCOL *Shell + ); + +/** + This is the command help handler function pointer callback type. This + function is responsible for displaying help information for the associated + command. + + @param[in] This The instance of the EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL. + @param[in] Language The pointer to the language string to use. + + @return string Pool allocated help string, must be freed by caller +**/ +typedef +CHAR16* +(EFIAPI * SHELL_COMMAND_GETHELP)( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN CONST CHAR8 *Language + ); + +/// EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL protocol structure. +struct _EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL { + + CONST CHAR16 *CommandName; + SHELL_COMMAND_HANDLER Handler; + SHELL_COMMAND_GETHELP GetHelp; + +}; + +extern EFI_GUID gEfiShellDynamicCommandProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellParameters.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellParameters.h new file mode 100644 index 0000000000..20091a1537 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/ShellParameters.h @@ -0,0 +1,54 @@ +/** @file + EFI Shell protocol as defined in the UEFI Shell 2.0 specification. + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SHELL_PARAMETERS_PROTOCOL_H__ +#define __EFI_SHELL_PARAMETERS_PROTOCOL_H__ + +#include + +#define EFI_SHELL_PARAMETERS_PROTOCOL_GUID \ + { \ + 0x752f3136, 0x4e16, 0x4fdc, { 0xa2, 0x2a, 0xe5, 0xf4, 0x68, 0x12, 0xf4, 0xca } \ + } + +typedef struct _EFI_SHELL_PARAMETERS_PROTOCOL { + /// + /// Points to an Argc-element array of points to NULL-terminated strings containing + /// the command-line parameters. The first entry in the array is always the full file + /// path of the executable. Any quotation marks that were used to preserve + /// whitespace have been removed. + /// + CHAR16 **Argv; + + /// + /// The number of elements in the Argv array. + /// + UINTN Argc; + + /// + /// The file handle for the standard input for this executable. This may be different + /// from the ConInHandle in EFI_SYSTEM_TABLE. + /// + SHELL_FILE_HANDLE StdIn; + + /// + /// The file handle for the standard output for this executable. This may be different + /// from the ConOutHandle in EFI_SYSTEM_TABLE. + /// + SHELL_FILE_HANDLE StdOut; + + /// + /// The file handle for the standard error output for this executable. This may be + /// different from the StdErrHandle in EFI_SYSTEM_TABLE. + /// + SHELL_FILE_HANDLE StdErr; +} EFI_SHELL_PARAMETERS_PROTOCOL; + +extern EFI_GUID gEfiShellParametersProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleFileSystem.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleFileSystem.h new file mode 100644 index 0000000000..7762d34ac2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleFileSystem.h @@ -0,0 +1,556 @@ +/** @file + SimpleFileSystem protocol as defined in the UEFI 2.0 specification. + + The SimpleFileSystem protocol is the programmatic access to the FAT (12,16,32) + file system specified in UEFI 2.0. It can also be used to abstract a file + system other than FAT. + + UEFI 2.0 can boot from any valid EFI image contained in a SimpleFileSystem. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SIMPLE_FILE_SYSTEM_H__ +#define __SIMPLE_FILE_SYSTEM_H__ + +#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \ + { \ + 0x964e5b22, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL; + +typedef struct _EFI_FILE_PROTOCOL EFI_FILE_PROTOCOL; +typedef struct _EFI_FILE_PROTOCOL *EFI_FILE_HANDLE; + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID + +/// +/// Protocol name defined in EFI1.1. +/// +typedef EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_FILE_IO_INTERFACE; +typedef EFI_FILE_PROTOCOL EFI_FILE; + +/** + Open the root directory on a volume. + + @param This A pointer to the volume to open the root directory. + @param Root A pointer to the location to return the opened file handle for the + root directory. + + @retval EFI_SUCCESS The device was opened. + @retval EFI_UNSUPPORTED This volume does not support the requested file system type. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES The volume was not opened due to lack of resources. + @retval EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no + longer supported. Any existing file handles for this volume are + no longer valid. To access the files on the new medium, the + volume must be reopened with OpenVolume(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME)( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **Root + ); + +#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000 + +/// +/// Revision defined in EFI1.1 +/// +#define EFI_FILE_IO_INTERFACE_REVISION EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION + +struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL { + /// + /// The version of the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. The version + /// specified by this specification is 0x00010000. All future revisions + /// must be backwards compatible. + /// + UINT64 Revision; + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME OpenVolume; +}; + +/** + Opens a new file relative to the source file's location. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to the source location. This would typically be an open + handle to a directory. + @param NewHandle A pointer to the location to return the opened handle for the new + file. + @param FileName The Null-terminated string of the name of the file to be opened. + The file name may contain the following path modifiers: "\", ".", + and "..". + @param OpenMode The mode to open the file. The only valid combinations that the + file may be opened with are: Read, Read/Write, or Create/Read/Write. + @param Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the + attribute bits for the newly created file. + + @retval EFI_SUCCESS The file was opened. + @retval EFI_NOT_FOUND The specified file could not be found on the device. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no + longer supported. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a file for write + when the media is write-protected. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_OPEN)( + IN EFI_FILE_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes + ); + +// +// Open modes +// +#define EFI_FILE_MODE_READ 0x0000000000000001ULL +#define EFI_FILE_MODE_WRITE 0x0000000000000002ULL +#define EFI_FILE_MODE_CREATE 0x8000000000000000ULL + +// +// File attributes +// +#define EFI_FILE_READ_ONLY 0x0000000000000001ULL +#define EFI_FILE_HIDDEN 0x0000000000000002ULL +#define EFI_FILE_SYSTEM 0x0000000000000004ULL +#define EFI_FILE_RESERVED 0x0000000000000008ULL +#define EFI_FILE_DIRECTORY 0x0000000000000010ULL +#define EFI_FILE_ARCHIVE 0x0000000000000020ULL +#define EFI_FILE_VALID_ATTR 0x0000000000000037ULL + +/** + Closes a specified file handle. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to close. + + @retval EFI_SUCCESS The file was closed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_CLOSE)( + IN EFI_FILE_PROTOCOL *This + ); + +/** + Close and delete the file handle. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the + handle to the file to delete. + + @retval EFI_SUCCESS The file was closed and deleted, and the handle was closed. + @retval EFI_WARN_DELETE_FAILURE The handle was closed, but the file was not deleted. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_DELETE)( + IN EFI_FILE_PROTOCOL *This + ); + +/** + Reads data from a file. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to read data from. + @param BufferSize On input, the size of the Buffer. On output, the amount of data + returned in Buffer. In both cases, the size is measured in bytes. + @param Buffer The buffer into which the data is read. + + @retval EFI_SUCCESS Data was read. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_DEVICE_ERROR An attempt was made to read from a deleted file. + @retval EFI_DEVICE_ERROR On entry, the current file position is beyond the end of the file. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory + entry. BufferSize has been updated with the size + needed to complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_READ)( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Writes data to a file. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to write data to. + @param BufferSize On input, the size of the Buffer. On output, the amount of data + actually written. In both cases, the size is measured in bytes. + @param Buffer The buffer of data to write. + + @retval EFI_SUCCESS Data was written. + @retval EFI_UNSUPPORTED Writes to open directory files are not supported. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_DEVICE_ERROR An attempt was made to write to a deleted file. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read only. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_WRITE)( + IN EFI_FILE_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +/** + Sets a file's current position. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the + file handle to set the requested position on. + @param Position The byte position from the start of the file to set. + + @retval EFI_SUCCESS The position was set. + @retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open + directories. + @retval EFI_DEVICE_ERROR An attempt was made to set the position of a deleted file. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_SET_POSITION)( + IN EFI_FILE_PROTOCOL *This, + IN UINT64 Position + ); + +/** + Returns a file's current position. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to get the current position on. + @param Position The address to return the file's current position value. + + @retval EFI_SUCCESS The position was returned. + @retval EFI_UNSUPPORTED The request is not valid on open directories. + @retval EFI_DEVICE_ERROR An attempt was made to get the position from a deleted file. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_GET_POSITION)( + IN EFI_FILE_PROTOCOL *This, + OUT UINT64 *Position + ); + +/** + Returns information about a file. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle the requested information is for. + @param InformationType The type identifier for the information being requested. + @param BufferSize On input, the size of Buffer. On output, the amount of data + returned in Buffer. In both cases, the size is measured in bytes. + @param Buffer A pointer to the data buffer to return. The buffer's type is + indicated by InformationType. + + @retval EFI_SUCCESS The information was returned. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small to read the current directory entry. + BufferSize has been updated with the size needed to complete + the request. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_GET_INFO)( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Sets information about a file. + + @param File A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle the information is for. + @param InformationType The type identifier for the information being set. + @param BufferSize The size, in bytes, of Buffer. + @param Buffer A pointer to the data buffer to write. The buffer's type is + indicated by InformationType. + + @retval EFI_SUCCESS The information was set. + @retval EFI_UNSUPPORTED The InformationType is not known. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED InformationType is EFI_FILE_INFO_ID and the media is + read-only. + @retval EFI_WRITE_PROTECTED InformationType is EFI_FILE_PROTOCOL_SYSTEM_INFO_ID + and the media is read only. + @retval EFI_WRITE_PROTECTED InformationType is EFI_FILE_SYSTEM_VOLUME_LABEL_ID + and the media is read-only. + @retval EFI_ACCESS_DENIED An attempt is made to change the name of a file to a + file that is already present. + @retval EFI_ACCESS_DENIED An attempt is being made to change the EFI_FILE_DIRECTORY + Attribute. + @retval EFI_ACCESS_DENIED An attempt is being made to change the size of a directory. + @retval EFI_ACCESS_DENIED InformationType is EFI_FILE_INFO_ID and the file was opened + read-only and an attempt is being made to modify a field + other than Attribute. + @retval EFI_VOLUME_FULL The volume is full. + @retval EFI_BAD_BUFFER_SIZE BufferSize is smaller than the size of the type indicated + by InformationType. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_SET_INFO)( + IN EFI_FILE_PROTOCOL *This, + IN EFI_GUID *InformationType, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flushes all modified data associated with a file to a device. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to flush. + + @retval EFI_SUCCESS The data was flushed. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read-only. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_FLUSH)( + IN EFI_FILE_PROTOCOL *This + ); + +typedef struct { + // + // If Event is NULL, then blocking I/O is performed. + // If Event is not NULL and non-blocking I/O is supported, then non-blocking I/O is performed, + // and Event will be signaled when the read request is completed. + // The caller must be prepared to handle the case where the callback associated with Event + // occurs before the original asynchronous I/O request call returns. + // + EFI_EVENT Event; + + // + // Defines whether or not the signaled event encountered an error. + // + EFI_STATUS Status; + + // + // For OpenEx(): Not Used, ignored. + // For ReadEx(): On input, the size of the Buffer. On output, the amount of data returned in Buffer. + // In both cases, the size is measured in bytes. + // For WriteEx(): On input, the size of the Buffer. On output, the amount of data actually written. + // In both cases, the size is measured in bytes. + // For FlushEx(): Not used, ignored. + // + UINTN BufferSize; + + // + // For OpenEx(): Not Used, ignored. + // For ReadEx(): The buffer into which the data is read. + // For WriteEx(): The buffer of data to write. + // For FlushEx(): Not Used, ignored. + // + VOID *Buffer; +} EFI_FILE_IO_TOKEN; + +/** + Opens a new file relative to the source directory's location. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to the source location. + @param NewHandle A pointer to the location to return the opened handle for the new + file. + @param FileName The Null-terminated string of the name of the file to be opened. + The file name may contain the following path modifiers: "\", ".", + and "..". + @param OpenMode The mode to open the file. The only valid combinations that the + file may be opened with are: Read, Read/Write, or Create/Read/Write. + @param Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the + attribute bits for the newly created file. + @param Token A pointer to the token associated with the transaction. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read successfully. + If Event is not NULL (asynchronous I/O): The request was successfully + queued for processing. + @retval EFI_NOT_FOUND The specified file could not be found on the device. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_MEDIA_CHANGED The device has a different medium in it or the medium is no + longer supported. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED An attempt was made to create a file, or open a file for write + when the media is write-protected. + @retval EFI_ACCESS_DENIED The service denied access to the file. + @retval EFI_OUT_OF_RESOURCES Not enough resources were available to open the file. + @retval EFI_VOLUME_FULL The volume is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_OPEN_EX)( + IN EFI_FILE_PROTOCOL *This, + OUT EFI_FILE_PROTOCOL **NewHandle, + IN CHAR16 *FileName, + IN UINT64 OpenMode, + IN UINT64 Attributes, + IN OUT EFI_FILE_IO_TOKEN *Token + ); + + +/** + Reads data from a file. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file handle to read data from. + @param Token A pointer to the token associated with the transaction. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read successfully. + If Event is not NULL (asynchronous I/O): The request was successfully + queued for processing. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_DEVICE_ERROR An attempt was made to read from a deleted file. + @retval EFI_DEVICE_ERROR On entry, the current file position is beyond the end of the file. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_OUT_OF_RESOURCES Unable to queue the request due to lack of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_READ_EX) ( + IN EFI_FILE_PROTOCOL *This, + IN OUT EFI_FILE_IO_TOKEN *Token +); + + +/** + Writes data to a file. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file handle to write data to. + @param Token A pointer to the token associated with the transaction. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read successfully. + If Event is not NULL (asynchronous I/O): The request was successfully + queued for processing. + @retval EFI_UNSUPPORTED Writes to open directory files are not supported. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_DEVICE_ERROR An attempt was made to write to a deleted file. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read only. + @retval EFI_VOLUME_FULL The volume is full. + @retval EFI_OUT_OF_RESOURCES Unable to queue the request due to lack of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_WRITE_EX) ( + IN EFI_FILE_PROTOCOL *This, + IN OUT EFI_FILE_IO_TOKEN *Token +); + +/** + Flushes all modified data associated with a file to a device. + + @param This A pointer to the EFI_FILE_PROTOCOL instance that is the file + handle to flush. + @param Token A pointer to the token associated with the transaction. + + @retval EFI_SUCCESS If Event is NULL (blocking I/O): The data was read successfully. + If Event is not NULL (asynchronous I/O): The request was successfully + queued for processing. + @retval EFI_NO_MEDIA The device has no medium. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_VOLUME_CORRUPTED The file system structures are corrupted. + @retval EFI_WRITE_PROTECTED The file or medium is write-protected. + @retval EFI_ACCESS_DENIED The file was opened read-only. + @retval EFI_VOLUME_FULL The volume is full. + @retval EFI_OUT_OF_RESOURCES Unable to queue the request due to lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FILE_FLUSH_EX) ( + IN EFI_FILE_PROTOCOL *This, + IN OUT EFI_FILE_IO_TOKEN *Token + ); + +#define EFI_FILE_PROTOCOL_REVISION 0x00010000 +#define EFI_FILE_PROTOCOL_REVISION2 0x00020000 +#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2 + +// +// Revision defined in EFI1.1. +// +#define EFI_FILE_REVISION EFI_FILE_PROTOCOL_REVISION + +/// +/// The EFI_FILE_PROTOCOL provides file IO access to supported file systems. +/// An EFI_FILE_PROTOCOL provides access to a file's or directory's contents, +/// and is also a reference to a location in the directory tree of the file system +/// in which the file resides. With any given file handle, other files may be opened +/// relative to this file's location, yielding new file handles. +/// +struct _EFI_FILE_PROTOCOL { + /// + /// The version of the EFI_FILE_PROTOCOL interface. The version specified + /// by this specification is EFI_FILE_PROTOCOL_LATEST_REVISION. + /// Future versions are required to be backward compatible to version 1.0. + /// + UINT64 Revision; + EFI_FILE_OPEN Open; + EFI_FILE_CLOSE Close; + EFI_FILE_DELETE Delete; + EFI_FILE_READ Read; + EFI_FILE_WRITE Write; + EFI_FILE_GET_POSITION GetPosition; + EFI_FILE_SET_POSITION SetPosition; + EFI_FILE_GET_INFO GetInfo; + EFI_FILE_SET_INFO SetInfo; + EFI_FILE_FLUSH Flush; + EFI_FILE_OPEN_EX OpenEx; + EFI_FILE_READ_EX ReadEx; + EFI_FILE_WRITE_EX WriteEx; + EFI_FILE_FLUSH_EX FlushEx; +}; + + +extern EFI_GUID gEfiSimpleFileSystemProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleNetwork.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleNetwork.h new file mode 100644 index 0000000000..a367fa2e31 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleNetwork.h @@ -0,0 +1,675 @@ +/** @file + The EFI_SIMPLE_NETWORK_PROTOCOL provides services to initialize a network interface, + transmit packets, receive packets, and close a network interface. + + Basic network device abstraction. + + Rx - Received + Tx - Transmit + MCast - MultiCast + ... + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in EFI Specification 1.10. + +**/ + +#ifndef __SIMPLE_NETWORK_H__ +#define __SIMPLE_NETWORK_H__ + +#define EFI_SIMPLE_NETWORK_PROTOCOL_GUID \ + { \ + 0xA19832B9, 0xAC25, 0x11D3, {0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \ + } + +typedef struct _EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK_PROTOCOL; + + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK; + +/// +/// Simple Network Protocol data structures. +/// +typedef struct { + /// + /// Total number of frames received. Includes frames with errors and + /// dropped frames. + /// + UINT64 RxTotalFrames; + + /// + /// Number of valid frames received and copied into receive buffers. + /// + UINT64 RxGoodFrames; + + /// + /// Number of frames below the minimum length for the media. + /// This would be <64 for ethernet. + /// + UINT64 RxUndersizeFrames; + + /// + /// Number of frames longer than the maxminum length for the + /// media. This would be >1500 for ethernet. + /// + UINT64 RxOversizeFrames; + + /// + /// Valid frames that were dropped because receive buffers were full. + /// + UINT64 RxDroppedFrames; + + /// + /// Number of valid unicast frames received and not dropped. + /// + UINT64 RxUnicastFrames; + + /// + /// Number of valid broadcast frames received and not dropped. + /// + UINT64 RxBroadcastFrames; + + /// + /// Number of valid mutlicast frames received and not dropped. + /// + UINT64 RxMulticastFrames; + + /// + /// Number of frames w/ CRC or alignment errors. + /// + UINT64 RxCrcErrorFrames; + + /// + /// Total number of bytes received. Includes frames with errors + /// and dropped frames. + // + UINT64 RxTotalBytes; + + /// + /// Transmit statistics. + /// + UINT64 TxTotalFrames; + UINT64 TxGoodFrames; + UINT64 TxUndersizeFrames; + UINT64 TxOversizeFrames; + UINT64 TxDroppedFrames; + UINT64 TxUnicastFrames; + UINT64 TxBroadcastFrames; + UINT64 TxMulticastFrames; + UINT64 TxCrcErrorFrames; + UINT64 TxTotalBytes; + + /// + /// Number of collisions detection on this subnet. + /// + UINT64 Collisions; + + /// + /// Number of frames destined for unsupported protocol. + /// + UINT64 UnsupportedProtocol; + + /// + /// Number of valid frames received that were duplicated. + /// + UINT64 RxDuplicatedFrames; + + /// + /// Number of encrypted frames received that failed to decrypt. + /// + UINT64 RxDecryptErrorFrames; + + /// + /// Number of frames that failed to transmit after exceeding the retry limit. + /// + UINT64 TxErrorFrames; + + /// + /// Number of frames transmitted successfully after more than one attempt. + /// + UINT64 TxRetryFrames; +} EFI_NETWORK_STATISTICS; + +/// +/// The state of the network interface. +/// When an EFI_SIMPLE_NETWORK_PROTOCOL driver initializes a +/// network interface, the network interface is left in the EfiSimpleNetworkStopped state. +/// +typedef enum { + EfiSimpleNetworkStopped, + EfiSimpleNetworkStarted, + EfiSimpleNetworkInitialized, + EfiSimpleNetworkMaxState +} EFI_SIMPLE_NETWORK_STATE; + +#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST 0x01 +#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST 0x02 +#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST 0x04 +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08 +#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10 + +#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT 0x01 +#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT 0x02 +#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT 0x04 +#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT 0x08 + +#define MAX_MCAST_FILTER_CNT 16 +typedef struct { + /// + /// Reports the current state of the network interface. + /// + UINT32 State; + /// + /// The size, in bytes, of the network interface's HW address. + /// + UINT32 HwAddressSize; + /// + /// The size, in bytes, of the network interface's media header. + /// + UINT32 MediaHeaderSize; + /// + /// The maximum size, in bytes, of the packets supported by the network interface. + /// + UINT32 MaxPacketSize; + /// + /// The size, in bytes, of the NVRAM device attached to the network interface. + /// + UINT32 NvRamSize; + /// + /// The size that must be used for all NVRAM reads and writes. The + /// start address for NVRAM read and write operations and the total + /// length of those operations, must be a multiple of this value. The + /// legal values for this field are 0, 1, 2, 4, and 8. + /// + UINT32 NvRamAccessSize; + /// + /// The multicast receive filter settings supported by the network interface. + /// + UINT32 ReceiveFilterMask; + /// + /// The current multicast receive filter settings. + /// + UINT32 ReceiveFilterSetting; + /// + /// The maximum number of multicast address receive filters supported by the driver. + /// + UINT32 MaxMCastFilterCount; + /// + /// The current number of multicast address receive filters. + /// + UINT32 MCastFilterCount; + /// + /// Array containing the addresses of the current multicast address receive filters. + /// + EFI_MAC_ADDRESS MCastFilter[MAX_MCAST_FILTER_CNT]; + /// + /// The current HW MAC address for the network interface. + /// + EFI_MAC_ADDRESS CurrentAddress; + /// + /// The current HW MAC address for broadcast packets. + /// + EFI_MAC_ADDRESS BroadcastAddress; + /// + /// The permanent HW MAC address for the network interface. + /// + EFI_MAC_ADDRESS PermanentAddress; + /// + /// The interface type of the network interface. + /// + UINT8 IfType; + /// + /// TRUE if the HW MAC address can be changed. + /// + BOOLEAN MacAddressChangeable; + /// + /// TRUE if the network interface can transmit more than one packet at a time. + /// + BOOLEAN MultipleTxSupported; + /// + /// TRUE if the presence of media can be determined; otherwise FALSE. + /// + BOOLEAN MediaPresentSupported; + /// + /// TRUE if media are connected to the network interface; otherwise FALSE. + /// + BOOLEAN MediaPresent; +} EFI_SIMPLE_NETWORK_MODE; + +// +// Protocol Member Functions +// +/** + Changes the state of a network interface from "stopped" to "started". + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was started. + @retval EFI_ALREADY_STARTED The network interface is already in the started state. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_START)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This + ); + +/** + Changes the state of a network interface from "started" to "stopped". + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was stopped. + @retval EFI_ALREADY_STARTED The network interface is already in the stopped state. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_STOP)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This + ); + +/** + Resets a network adapter and allocates the transmit and receive buffers + required by the network interface; optionally, also requests allocation + of additional transmit and receive buffers. + + @param This The protocol instance pointer. + @param ExtraRxBufferSize The size, in bytes, of the extra receive buffer space + that the driver should allocate for the network interface. + Some network interfaces will not be able to use the extra + buffer, and the caller will not know if it is actually + being used. + @param ExtraTxBufferSize The size, in bytes, of the extra transmit buffer space + that the driver should allocate for the network interface. + Some network interfaces will not be able to use the extra + buffer, and the caller will not know if it is actually + being used. + + @retval EFI_SUCCESS The network interface was initialized. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_OUT_OF_RESOURCES There was not enough memory for the transmit and + receive buffers. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_INITIALIZE)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN UINTN ExtraRxBufferSize OPTIONAL, + IN UINTN ExtraTxBufferSize OPTIONAL + ); + +/** + Resets a network adapter and re-initializes it with the parameters that were + provided in the previous call to Initialize(). + + @param This The protocol instance pointer. + @param ExtendedVerification Indicates that the driver may perform a more + exhaustive verification operation of the device + during reset. + + @retval EFI_SUCCESS The network interface was reset. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_RESET)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Resets a network adapter and leaves it in a state that is safe for + another driver to initialize. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The network interface was shutdown. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_SHUTDOWN)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This + ); + +/** + Manages the multicast receive filters of a network interface. + + @param This The protocol instance pointer. + @param Enable A bit mask of receive filters to enable on the network interface. + @param Disable A bit mask of receive filters to disable on the network interface. + @param ResetMCastFilter Set to TRUE to reset the contents of the multicast receive + filters on the network interface to their default values. + @param McastFilterCnt Number of multicast HW MAC addresses in the new + MCastFilter list. This value must be less than or equal to + the MCastFilterCnt field of EFI_SIMPLE_NETWORK_MODE. This + field is optional if ResetMCastFilter is TRUE. + @param MCastFilter A pointer to a list of new multicast receive filter HW MAC + addresses. This list will replace any existing multicast + HW MAC address list. This field is optional if + ResetMCastFilter is TRUE. + + @retval EFI_SUCCESS The multicast receive filter list was updated. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_RECEIVE_FILTERS)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN UINT32 Enable, + IN UINT32 Disable, + IN BOOLEAN ResetMCastFilter, + IN UINTN MCastFilterCnt OPTIONAL, + IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL + ); + +/** + Modifies or resets the current station address, if supported. + + @param This The protocol instance pointer. + @param Reset Flag used to reset the station address to the network interfaces + permanent address. + @param New The new station address to be used for the network interface. + + @retval EFI_SUCCESS The network interfaces station address was updated. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_STATION_ADDRESS)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN BOOLEAN Reset, + IN EFI_MAC_ADDRESS *New OPTIONAL + ); + +/** + Resets or collects the statistics on a network interface. + + @param This Protocol instance pointer. + @param Reset Set to TRUE to reset the statistics for the network interface. + @param StatisticsSize On input the size, in bytes, of StatisticsTable. On + output the size, in bytes, of the resulting table of + statistics. + @param StatisticsTable A pointer to the EFI_NETWORK_STATISTICS structure that + contains the statistics. + + @retval EFI_SUCCESS The statistics were collected from the network interface. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_BUFFER_TOO_SMALL The Statistics buffer was too small. The current buffer + size needed to hold the statistics is returned in + StatisticsSize. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_STATISTICS)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN BOOLEAN Reset, + IN OUT UINTN *StatisticsSize OPTIONAL, + OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL + ); + +/** + Converts a multicast IP address to a multicast HW MAC address. + + @param This The protocol instance pointer. + @param IPv6 Set to TRUE if the multicast IP address is IPv6 [RFC 2460]. Set + to FALSE if the multicast IP address is IPv4 [RFC 791]. + @param IP The multicast IP address that is to be converted to a multicast + HW MAC address. + @param MAC The multicast HW MAC address that is to be generated from IP. + + @retval EFI_SUCCESS The multicast IP address was mapped to the multicast + HW MAC address. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_BUFFER_TOO_SMALL The Statistics buffer was too small. The current buffer + size needed to hold the statistics is returned in + StatisticsSize. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN BOOLEAN IPv6, + IN EFI_IP_ADDRESS *IP, + OUT EFI_MAC_ADDRESS *MAC + ); + +/** + Performs read and write operations on the NVRAM device attached to a + network interface. + + @param This The protocol instance pointer. + @param ReadWrite TRUE for read operations, FALSE for write operations. + @param Offset Byte offset in the NVRAM device at which to start the read or + write operation. This must be a multiple of NvRamAccessSize and + less than NvRamSize. + @param BufferSize The number of bytes to read or write from the NVRAM device. + This must also be a multiple of NvramAccessSize. + @param Buffer A pointer to the data buffer. + + @retval EFI_SUCCESS The NVRAM access was performed. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_NVDATA)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN BOOLEAN ReadWrite, + IN UINTN Offset, + IN UINTN BufferSize, + IN OUT VOID *Buffer + ); + +/** + Reads the current interrupt status and recycled transmit buffer status from + a network interface. + + @param This The protocol instance pointer. + @param InterruptStatus A pointer to the bit mask of the currently active interrupts + If this is NULL, the interrupt status will not be read from + the device. If this is not NULL, the interrupt status will + be read from the device. When the interrupt status is read, + it will also be cleared. Clearing the transmit interrupt + does not empty the recycled transmit buffer array. + @param TxBuf Recycled transmit buffer address. The network interface will + not transmit if its internal recycled transmit buffer array + is full. Reading the transmit buffer does not clear the + transmit interrupt. If this is NULL, then the transmit buffer + status will not be read. If there are no transmit buffers to + recycle and TxBuf is not NULL, * TxBuf will be set to NULL. + + @retval EFI_SUCCESS The status of the network interface was retrieved. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_GET_STATUS)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + OUT UINT32 *InterruptStatus OPTIONAL, + OUT VOID **TxBuf OPTIONAL + ); + +/** + Places a packet in the transmit queue of a network interface. + + @param This The protocol instance pointer. + @param HeaderSize The size, in bytes, of the media header to be filled in by + the Transmit() function. If HeaderSize is non-zero, then it + must be equal to This->Mode->MediaHeaderSize and the DestAddr + and Protocol parameters must not be NULL. + @param BufferSize The size, in bytes, of the entire packet (media header and + data) to be transmitted through the network interface. + @param Buffer A pointer to the packet (media header followed by data) to be + transmitted. This parameter cannot be NULL. If HeaderSize is zero, + then the media header in Buffer must already be filled in by the + caller. If HeaderSize is non-zero, then the media header will be + filled in by the Transmit() function. + @param SrcAddr The source HW MAC address. If HeaderSize is zero, then this parameter + is ignored. If HeaderSize is non-zero and SrcAddr is NULL, then + This->Mode->CurrentAddress is used for the source HW MAC address. + @param DestAddr The destination HW MAC address. If HeaderSize is zero, then this + parameter is ignored. + @param Protocol The type of header to build. If HeaderSize is zero, then this + parameter is ignored. See RFC 1700, section "Ether Types", for + examples. + + @retval EFI_SUCCESS The packet was placed on the transmit queue. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_NOT_READY The network interface is too busy to accept this transmit request. + @retval EFI_BUFFER_TOO_SMALL The BufferSize parameter is too small. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_TRANSMIT)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + IN UINTN HeaderSize, + IN UINTN BufferSize, + IN VOID *Buffer, + IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + IN EFI_MAC_ADDRESS *DestAddr OPTIONAL, + IN UINT16 *Protocol OPTIONAL + ); + +/** + Receives a packet from a network interface. + + @param This The protocol instance pointer. + @param HeaderSize The size, in bytes, of the media header received on the network + interface. If this parameter is NULL, then the media header size + will not be returned. + @param BufferSize On entry, the size, in bytes, of Buffer. On exit, the size, in + bytes, of the packet that was received on the network interface. + @param Buffer A pointer to the data buffer to receive both the media header and + the data. + @param SrcAddr The source HW MAC address. If this parameter is NULL, the + HW MAC source address will not be extracted from the media + header. + @param DestAddr The destination HW MAC address. If this parameter is NULL, + the HW MAC destination address will not be extracted from the + media header. + @param Protocol The media header type. If this parameter is NULL, then the + protocol will not be extracted from the media header. See + RFC 1700 section "Ether Types" for examples. + + @retval EFI_SUCCESS The received data was stored in Buffer, and BufferSize has + been updated to the number of bytes received. + @retval EFI_NOT_STARTED The network interface has not been started. + @retval EFI_NOT_READY The network interface is too busy to accept this transmit + request. + @retval EFI_BUFFER_TOO_SMALL The BufferSize parameter is too small. + @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value. + @retval EFI_DEVICE_ERROR The command could not be sent to the network interface. + @retval EFI_UNSUPPORTED This function is not supported by the network interface. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_NETWORK_RECEIVE)( + IN EFI_SIMPLE_NETWORK_PROTOCOL *This, + OUT UINTN *HeaderSize OPTIONAL, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer, + OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + OUT EFI_MAC_ADDRESS *DestAddr OPTIONAL, + OUT UINT16 *Protocol OPTIONAL + ); + +#define EFI_SIMPLE_NETWORK_PROTOCOL_REVISION 0x00010000 + +// +// Revision defined in EFI1.1 +// +#define EFI_SIMPLE_NETWORK_INTERFACE_REVISION EFI_SIMPLE_NETWORK_PROTOCOL_REVISION + +/// +/// The EFI_SIMPLE_NETWORK_PROTOCOL protocol is used to initialize access +/// to a network adapter. Once the network adapter initializes, +/// the EFI_SIMPLE_NETWORK_PROTOCOL protocol provides services that +/// allow packets to be transmitted and received. +/// +struct _EFI_SIMPLE_NETWORK_PROTOCOL { + /// + /// Revision of the EFI_SIMPLE_NETWORK_PROTOCOL. All future revisions must + /// be backwards compatible. If a future version is not backwards compatible + /// it is not the same GUID. + /// + UINT64 Revision; + EFI_SIMPLE_NETWORK_START Start; + EFI_SIMPLE_NETWORK_STOP Stop; + EFI_SIMPLE_NETWORK_INITIALIZE Initialize; + EFI_SIMPLE_NETWORK_RESET Reset; + EFI_SIMPLE_NETWORK_SHUTDOWN Shutdown; + EFI_SIMPLE_NETWORK_RECEIVE_FILTERS ReceiveFilters; + EFI_SIMPLE_NETWORK_STATION_ADDRESS StationAddress; + EFI_SIMPLE_NETWORK_STATISTICS Statistics; + EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC MCastIpToMac; + EFI_SIMPLE_NETWORK_NVDATA NvData; + EFI_SIMPLE_NETWORK_GET_STATUS GetStatus; + EFI_SIMPLE_NETWORK_TRANSMIT Transmit; + EFI_SIMPLE_NETWORK_RECEIVE Receive; + /// + /// Event used with WaitForEvent() to wait for a packet to be received. + /// + EFI_EVENT WaitForPacket; + /// + /// Pointer to the EFI_SIMPLE_NETWORK_MODE data for the device. + /// + EFI_SIMPLE_NETWORK_MODE *Mode; +}; + +extern EFI_GUID gEfiSimpleNetworkProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimplePointer.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimplePointer.h new file mode 100644 index 0000000000..cb52ad9ddf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimplePointer.h @@ -0,0 +1,137 @@ +/** @file + Simple Pointer protocol from the UEFI 2.0 specification. + + Abstraction of a very simple pointer device like a mouse or trackball. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SIMPLE_POINTER_H__ +#define __SIMPLE_POINTER_H__ + +#define EFI_SIMPLE_POINTER_PROTOCOL_GUID \ + { \ + 0x31878c87, 0xb75, 0x11d5, {0x9a, 0x4f, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +typedef struct _EFI_SIMPLE_POINTER_PROTOCOL EFI_SIMPLE_POINTER_PROTOCOL; + +// +// Data structures +// +typedef struct { + /// + /// The signed distance in counts that the pointer device has been moved along the x-axis. + /// + INT32 RelativeMovementX; + /// + /// The signed distance in counts that the pointer device has been moved along the y-axis. + /// + INT32 RelativeMovementY; + /// + /// The signed distance in counts that the pointer device has been moved along the z-axis. + /// + INT32 RelativeMovementZ; + /// + /// If TRUE, then the left button of the pointer device is being + /// pressed. If FALSE, then the left button of the pointer device is not being pressed. + /// + BOOLEAN LeftButton; + /// + /// If TRUE, then the right button of the pointer device is being + /// pressed. If FALSE, then the right button of the pointer device is not being pressed. + /// + BOOLEAN RightButton; +} EFI_SIMPLE_POINTER_STATE; + +typedef struct { + /// + /// The resolution of the pointer device on the x-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// + UINT64 ResolutionX; + /// + /// The resolution of the pointer device on the y-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// + UINT64 ResolutionY; + /// + /// The resolution of the pointer device on the z-axis in counts/mm. + /// If 0, then the pointer device does not support an x-axis. + /// + UINT64 ResolutionZ; + /// + /// TRUE if a left button is present on the pointer device. Otherwise FALSE. + /// + BOOLEAN LeftButton; + /// + /// TRUE if a right button is present on the pointer device. Otherwise FALSE. + /// + BOOLEAN RightButton; +} EFI_SIMPLE_POINTER_MODE; + +/** + Resets the pointer device hardware. + + @param This A pointer to the EFI_SIMPLE_POINTER_PROTOCOL + instance. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning correctly and could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_POINTER_RESET)( + IN EFI_SIMPLE_POINTER_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Retrieves the current state of a pointer device. + + @param This A pointer to the EFI_SIMPLE_POINTER_PROTOCOL + instance. + @param State A pointer to the state information on the pointer device. + + @retval EFI_SUCCESS The state of the pointer device was returned in State. + @retval EFI_NOT_READY The state of the pointer device has not changed since the last call to + GetState(). + @retval EFI_DEVICE_ERROR A device error occurred while attempting to retrieve the pointer device's + current state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIMPLE_POINTER_GET_STATE)( + IN EFI_SIMPLE_POINTER_PROTOCOL *This, + OUT EFI_SIMPLE_POINTER_STATE *State + ); + +/// +/// The EFI_SIMPLE_POINTER_PROTOCOL provides a set of services for a pointer +/// device that can use used as an input device from an application written +/// to this specification. The services include the ability to reset the +/// pointer device, retrieve get the state of the pointer device, and +/// retrieve the capabilities of the pointer device. +/// +struct _EFI_SIMPLE_POINTER_PROTOCOL { + EFI_SIMPLE_POINTER_RESET Reset; + EFI_SIMPLE_POINTER_GET_STATE GetState; + /// + /// Event to use with WaitForEvent() to wait for input from the pointer device. + /// + EFI_EVENT WaitForInput; + /// + /// Pointer to EFI_SIMPLE_POINTER_MODE data. + /// + EFI_SIMPLE_POINTER_MODE *Mode; +}; + +extern EFI_GUID gEfiSimplePointerProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextIn.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextIn.h new file mode 100644 index 0000000000..e6884d89c1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextIn.h @@ -0,0 +1,127 @@ +/** @file + Simple Text Input protocol from the UEFI 2.0 specification. + + Abstraction of a very simple input device like a keyboard or serial + terminal. + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SIMPLE_TEXT_IN_PROTOCOL_H__ +#define __SIMPLE_TEXT_IN_PROTOCOL_H__ + +#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \ + { \ + 0x387477c1, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL; + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define SIMPLE_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID + +/// +/// Protocol name in EFI1.1 for backward-compatible. +/// +typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL SIMPLE_INPUT_INTERFACE; + +/// +/// The keystroke information for the key that was pressed. +/// +typedef struct { + UINT16 ScanCode; + CHAR16 UnicodeChar; +} EFI_INPUT_KEY; + +// +// Required unicode control chars +// +#define CHAR_BACKSPACE 0x0008 +#define CHAR_TAB 0x0009 +#define CHAR_LINEFEED 0x000A +#define CHAR_CARRIAGE_RETURN 0x000D + +// +// EFI Scan codes +// +#define SCAN_NULL 0x0000 +#define SCAN_UP 0x0001 +#define SCAN_DOWN 0x0002 +#define SCAN_RIGHT 0x0003 +#define SCAN_LEFT 0x0004 +#define SCAN_HOME 0x0005 +#define SCAN_END 0x0006 +#define SCAN_INSERT 0x0007 +#define SCAN_DELETE 0x0008 +#define SCAN_PAGE_UP 0x0009 +#define SCAN_PAGE_DOWN 0x000A +#define SCAN_F1 0x000B +#define SCAN_F2 0x000C +#define SCAN_F3 0x000D +#define SCAN_F4 0x000E +#define SCAN_F5 0x000F +#define SCAN_F6 0x0010 +#define SCAN_F7 0x0011 +#define SCAN_F8 0x0012 +#define SCAN_F9 0x0013 +#define SCAN_F10 0x0014 +#define SCAN_ESC 0x0017 + +/** + Reset the input device and optionally run diagnostics + + @param This Protocol instance pointer. + @param ExtendedVerification Driver may perform diagnostics on reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning properly and could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INPUT_RESET)( + IN EFI_SIMPLE_TEXT_INPUT_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Reads the next keystroke from the input device. The WaitForKey Event can + be used to test for existence of a keystroke via WaitForEvent () call. + + @param This Protocol instance pointer. + @param Key A pointer to a buffer that is filled in with the keystroke + information for the key that was pressed. + + @retval EFI_SUCCESS The keystroke information was returned. + @retval EFI_NOT_READY There was no keystroke data available. + @retval EFI_DEVICE_ERROR The keystroke information was not returned due to + hardware errors. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INPUT_READ_KEY)( + IN EFI_SIMPLE_TEXT_INPUT_PROTOCOL *This, + OUT EFI_INPUT_KEY *Key + ); + +/// +/// The EFI_SIMPLE_TEXT_INPUT_PROTOCOL is used on the ConsoleIn device. +/// It is the minimum required protocol for ConsoleIn. +/// +struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL { + EFI_INPUT_RESET Reset; + EFI_INPUT_READ_KEY ReadKeyStroke; + /// + /// Event to use with WaitForEvent() to wait for a key to be available + /// + EFI_EVENT WaitForKey; +}; + +extern EFI_GUID gEfiSimpleTextInProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextInEx.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextInEx.h new file mode 100644 index 0000000000..f6a80e7c4f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextInEx.h @@ -0,0 +1,317 @@ +/** @file + Simple Text Input Ex protocol from the UEFI 2.0 specification. + + This protocol defines an extension to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL + which exposes much more state and modifier information from the input device, + also allows one to register a notification for a particular keystroke. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SIMPLE_TEXT_IN_EX_H__ +#define __SIMPLE_TEXT_IN_EX_H__ + +#include + +#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \ + {0xdd9e7534, 0x7762, 0x4698, { 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa } } + + +typedef struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL; + +/** + The Reset() function resets the input device hardware. As part + of initialization process, the firmware/device will make a quick + but reasonable attempt to verify that the device is functioning. + If the ExtendedVerification flag is TRUE the firmware may take + an extended amount of time to verify the device is operating on + reset. Otherwise the reset operation is to occur as quickly as + possible. The hardware verification process is not defined by + this specification and is left up to the platform firmware or + driver to implement. + + @param This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. + + @param ExtendedVerification Indicates that the driver may + perform a more exhaustive + verification operation of the + device during reset. + + + @retval EFI_SUCCESS The device was reset. + + @retval EFI_DEVICE_ERROR The device is not functioning + correctly and could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INPUT_RESET_EX)( + IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +); + + +/// +/// EFI_KEY_TOGGLE_STATE. The toggle states are defined. +/// They are: EFI_TOGGLE_STATE_VALID, EFI_SCROLL_LOCK_ACTIVE +/// EFI_NUM_LOCK_ACTIVE, EFI_CAPS_LOCK_ACTIVE +/// +typedef UINT8 EFI_KEY_TOGGLE_STATE; + +typedef struct _EFI_KEY_STATE { + /// + /// Reflects the currently pressed shift + /// modifiers for the input device. The + /// returned value is valid only if the high + /// order bit has been set. + /// + UINT32 KeyShiftState; + /// + /// Reflects the current internal state of + /// various toggled attributes. The returned + /// value is valid only if the high order + /// bit has been set. + /// + EFI_KEY_TOGGLE_STATE KeyToggleState; +} EFI_KEY_STATE; + +typedef struct { + /// + /// The EFI scan code and Unicode value returned from the input device. + /// + EFI_INPUT_KEY Key; + /// + /// The current state of various toggled attributes as well as input modifier values. + /// + EFI_KEY_STATE KeyState; +} EFI_KEY_DATA; + +// +// Any Shift or Toggle State that is valid should have +// high order bit set. +// +// Shift state +// +#define EFI_SHIFT_STATE_VALID 0x80000000 +#define EFI_RIGHT_SHIFT_PRESSED 0x00000001 +#define EFI_LEFT_SHIFT_PRESSED 0x00000002 +#define EFI_RIGHT_CONTROL_PRESSED 0x00000004 +#define EFI_LEFT_CONTROL_PRESSED 0x00000008 +#define EFI_RIGHT_ALT_PRESSED 0x00000010 +#define EFI_LEFT_ALT_PRESSED 0x00000020 +#define EFI_RIGHT_LOGO_PRESSED 0x00000040 +#define EFI_LEFT_LOGO_PRESSED 0x00000080 +#define EFI_MENU_KEY_PRESSED 0x00000100 +#define EFI_SYS_REQ_PRESSED 0x00000200 + +// +// Toggle state +// +#define EFI_TOGGLE_STATE_VALID 0x80 +#define EFI_KEY_STATE_EXPOSED 0x40 +#define EFI_SCROLL_LOCK_ACTIVE 0x01 +#define EFI_NUM_LOCK_ACTIVE 0x02 +#define EFI_CAPS_LOCK_ACTIVE 0x04 + +// +// EFI Scan codes +// +#define SCAN_F11 0x0015 +#define SCAN_F12 0x0016 +#define SCAN_PAUSE 0x0048 +#define SCAN_F13 0x0068 +#define SCAN_F14 0x0069 +#define SCAN_F15 0x006A +#define SCAN_F16 0x006B +#define SCAN_F17 0x006C +#define SCAN_F18 0x006D +#define SCAN_F19 0x006E +#define SCAN_F20 0x006F +#define SCAN_F21 0x0070 +#define SCAN_F22 0x0071 +#define SCAN_F23 0x0072 +#define SCAN_F24 0x0073 +#define SCAN_MUTE 0x007F +#define SCAN_VOLUME_UP 0x0080 +#define SCAN_VOLUME_DOWN 0x0081 +#define SCAN_BRIGHTNESS_UP 0x0100 +#define SCAN_BRIGHTNESS_DOWN 0x0101 +#define SCAN_SUSPEND 0x0102 +#define SCAN_HIBERNATE 0x0103 +#define SCAN_TOGGLE_DISPLAY 0x0104 +#define SCAN_RECOVERY 0x0105 +#define SCAN_EJECT 0x0106 + +/** + The function reads the next keystroke from the input device. If + there is no pending keystroke the function returns + EFI_NOT_READY. If there is a pending keystroke, then + KeyData.Key.ScanCode is the EFI scan code defined in Error! + Reference source not found. The KeyData.Key.UnicodeChar is the + actual printable character or is zero if the key does not + represent a printable character (control key, function key, + etc.). The KeyData.KeyState is shift state for the character + reflected in KeyData.Key.UnicodeChar or KeyData.Key.ScanCode . + When interpreting the data from this function, it should be + noted that if a class of printable characters that are + normally adjusted by shift modifiers (e.g. Shift Key + "f" + key) would be presented solely as a KeyData.Key.UnicodeChar + without the associated shift state. So in the previous example + of a Shift Key + "f" key being pressed, the only pertinent + data returned would be KeyData.Key.UnicodeChar with the value + of "F". This of course would not typically be the case for + non-printable characters such as the pressing of the Right + Shift Key + F10 key since the corresponding returned data + would be reflected both in the KeyData.KeyState.KeyShiftState + and KeyData.Key.ScanCode values. UEFI drivers which implement + the EFI_SIMPLE_TEXT_INPUT_EX protocol are required to return + KeyData.Key and KeyData.KeyState values. These drivers must + always return the most current state of + KeyData.KeyState.KeyShiftState and + KeyData.KeyState.KeyToggleState. It should also be noted that + certain input devices may not be able to produce shift or toggle + state information, and in those cases the high order bit in the + respective Toggle and Shift state fields should not be active. + + + @param This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. + + @param KeyData A pointer to a buffer that is filled in with + the keystroke state data for the key that was + pressed. + + + @retval EFI_SUCCESS The keystroke information was returned. + @retval EFI_NOT_READY There was no keystroke data available. + @retval EFI_DEVICE_ERROR The keystroke information was not returned due to + hardware errors. + + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INPUT_READ_KEY_EX)( + IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This, + OUT EFI_KEY_DATA *KeyData +); + +/** + The SetState() function allows the input device hardware to + have state settings adjusted. + + @param This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. + + @param KeyToggleState Pointer to the EFI_KEY_TOGGLE_STATE to + set the state for the input device. + + + @retval EFI_SUCCESS The device state was set appropriately. + + @retval EFI_DEVICE_ERROR The device is not functioning + correctly and could not have the + setting adjusted. + + @retval EFI_UNSUPPORTED The device does not support the + ability to have its state set. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_STATE)( + IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This, + IN EFI_KEY_TOGGLE_STATE *KeyToggleState +); + +/// +/// The function will be called when the key sequence is typed specified by KeyData. +/// +typedef +EFI_STATUS +(EFIAPI *EFI_KEY_NOTIFY_FUNCTION)( + IN EFI_KEY_DATA *KeyData +); + +/** + The RegisterKeystrokeNotify() function registers a function + which will be called when a specified keystroke will occur. + + @param This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. + + @param KeyData A pointer to a buffer that is filled in with + the keystroke information for the key that was + pressed. If KeyData.Key, KeyData.KeyState.KeyToggleState + and KeyData.KeyState.KeyShiftState are 0, then any incomplete + keystroke will trigger a notification of the KeyNotificationFunction. + + @param KeyNotificationFunction Points to the function to be called when the key sequence + is typed specified by KeyData. This notification function + should be called at <=TPL_CALLBACK. + + + @param NotifyHandle Points to the unique handle assigned to + the registered notification. + + @retval EFI_SUCCESS Key notify was registered successfully. + + @retval EFI_OUT_OF_RESOURCES Unable to allocate necessary + data structures. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_KEYSTROKE_NOTIFY)( + IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This, + IN EFI_KEY_DATA *KeyData, + IN EFI_KEY_NOTIFY_FUNCTION KeyNotificationFunction, + OUT VOID **NotifyHandle +); + +/** + The UnregisterKeystrokeNotify() function removes the + notification which was previously registered. + + @param This A pointer to the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL instance. + + @param NotificationHandle The handle of the notification + function being unregistered. + + @retval EFI_SUCCESS Key notify was unregistered successfully. + + @retval EFI_INVALID_PARAMETER The NotificationHandle is + invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UNREGISTER_KEYSTROKE_NOTIFY)( + IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This, + IN VOID *NotificationHandle +); + + +/// +/// The EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL is used on the ConsoleIn +/// device. It is an extension to the Simple Text Input protocol +/// which allows a variety of extended shift state information to be +/// returned. +/// +struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL{ + EFI_INPUT_RESET_EX Reset; + EFI_INPUT_READ_KEY_EX ReadKeyStrokeEx; + /// + /// Event to use with WaitForEvent() to wait for a key to be available. + /// + EFI_EVENT WaitForKeyEx; + EFI_SET_STATE SetState; + EFI_REGISTER_KEYSTROKE_NOTIFY RegisterKeyNotify; + EFI_UNREGISTER_KEYSTROKE_NOTIFY UnregisterKeyNotify; +}; + + +extern EFI_GUID gEfiSimpleTextInputExProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextOut.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextOut.h new file mode 100644 index 0000000000..0653bc199a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SimpleTextOut.h @@ -0,0 +1,409 @@ +/** @file + Simple Text Out protocol from the UEFI 2.0 specification. + + Abstraction of a very simple text based output device like VGA text mode or + a serial terminal. The Simple Text Out protocol instance can represent + a single hardware device or a virtual device that is an aggregation + of multiple physical devices. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SIMPLE_TEXT_OUT_H__ +#define __SIMPLE_TEXT_OUT_H__ + +#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \ + { \ + 0x387477c2, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ + } + +/// +/// Protocol GUID defined in EFI1.1. +/// +#define SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID + +typedef struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL; + +/// +/// Backward-compatible with EFI1.1. +/// +typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL SIMPLE_TEXT_OUTPUT_INTERFACE; + +// +// Defines for required EFI Unicode Box Draw characters +// +#define BOXDRAW_HORIZONTAL 0x2500 +#define BOXDRAW_VERTICAL 0x2502 +#define BOXDRAW_DOWN_RIGHT 0x250c +#define BOXDRAW_DOWN_LEFT 0x2510 +#define BOXDRAW_UP_RIGHT 0x2514 +#define BOXDRAW_UP_LEFT 0x2518 +#define BOXDRAW_VERTICAL_RIGHT 0x251c +#define BOXDRAW_VERTICAL_LEFT 0x2524 +#define BOXDRAW_DOWN_HORIZONTAL 0x252c +#define BOXDRAW_UP_HORIZONTAL 0x2534 +#define BOXDRAW_VERTICAL_HORIZONTAL 0x253c +#define BOXDRAW_DOUBLE_HORIZONTAL 0x2550 +#define BOXDRAW_DOUBLE_VERTICAL 0x2551 +#define BOXDRAW_DOWN_RIGHT_DOUBLE 0x2552 +#define BOXDRAW_DOWN_DOUBLE_RIGHT 0x2553 +#define BOXDRAW_DOUBLE_DOWN_RIGHT 0x2554 +#define BOXDRAW_DOWN_LEFT_DOUBLE 0x2555 +#define BOXDRAW_DOWN_DOUBLE_LEFT 0x2556 +#define BOXDRAW_DOUBLE_DOWN_LEFT 0x2557 +#define BOXDRAW_UP_RIGHT_DOUBLE 0x2558 +#define BOXDRAW_UP_DOUBLE_RIGHT 0x2559 +#define BOXDRAW_DOUBLE_UP_RIGHT 0x255a +#define BOXDRAW_UP_LEFT_DOUBLE 0x255b +#define BOXDRAW_UP_DOUBLE_LEFT 0x255c +#define BOXDRAW_DOUBLE_UP_LEFT 0x255d +#define BOXDRAW_VERTICAL_RIGHT_DOUBLE 0x255e +#define BOXDRAW_VERTICAL_DOUBLE_RIGHT 0x255f +#define BOXDRAW_DOUBLE_VERTICAL_RIGHT 0x2560 +#define BOXDRAW_VERTICAL_LEFT_DOUBLE 0x2561 +#define BOXDRAW_VERTICAL_DOUBLE_LEFT 0x2562 +#define BOXDRAW_DOUBLE_VERTICAL_LEFT 0x2563 +#define BOXDRAW_DOWN_HORIZONTAL_DOUBLE 0x2564 +#define BOXDRAW_DOWN_DOUBLE_HORIZONTAL 0x2565 +#define BOXDRAW_DOUBLE_DOWN_HORIZONTAL 0x2566 +#define BOXDRAW_UP_HORIZONTAL_DOUBLE 0x2567 +#define BOXDRAW_UP_DOUBLE_HORIZONTAL 0x2568 +#define BOXDRAW_DOUBLE_UP_HORIZONTAL 0x2569 +#define BOXDRAW_VERTICAL_HORIZONTAL_DOUBLE 0x256a +#define BOXDRAW_VERTICAL_DOUBLE_HORIZONTAL 0x256b +#define BOXDRAW_DOUBLE_VERTICAL_HORIZONTAL 0x256c + +// +// EFI Required Block Elements Code Chart +// +#define BLOCKELEMENT_FULL_BLOCK 0x2588 +#define BLOCKELEMENT_LIGHT_SHADE 0x2591 + +// +// EFI Required Geometric Shapes Code Chart +// +#define GEOMETRICSHAPE_UP_TRIANGLE 0x25b2 +#define GEOMETRICSHAPE_RIGHT_TRIANGLE 0x25ba +#define GEOMETRICSHAPE_DOWN_TRIANGLE 0x25bc +#define GEOMETRICSHAPE_LEFT_TRIANGLE 0x25c4 + +// +// EFI Required Arrow shapes +// +#define ARROW_LEFT 0x2190 +#define ARROW_UP 0x2191 +#define ARROW_RIGHT 0x2192 +#define ARROW_DOWN 0x2193 + +// +// EFI Console Colours +// +#define EFI_BLACK 0x00 +#define EFI_BLUE 0x01 +#define EFI_GREEN 0x02 +#define EFI_CYAN (EFI_BLUE | EFI_GREEN) +#define EFI_RED 0x04 +#define EFI_MAGENTA (EFI_BLUE | EFI_RED) +#define EFI_BROWN (EFI_GREEN | EFI_RED) +#define EFI_LIGHTGRAY (EFI_BLUE | EFI_GREEN | EFI_RED) +#define EFI_BRIGHT 0x08 +#define EFI_DARKGRAY (EFI_BLACK | EFI_BRIGHT) +#define EFI_LIGHTBLUE (EFI_BLUE | EFI_BRIGHT) +#define EFI_LIGHTGREEN (EFI_GREEN | EFI_BRIGHT) +#define EFI_LIGHTCYAN (EFI_CYAN | EFI_BRIGHT) +#define EFI_LIGHTRED (EFI_RED | EFI_BRIGHT) +#define EFI_LIGHTMAGENTA (EFI_MAGENTA | EFI_BRIGHT) +#define EFI_YELLOW (EFI_BROWN | EFI_BRIGHT) +#define EFI_WHITE (EFI_BLUE | EFI_GREEN | EFI_RED | EFI_BRIGHT) + +// +// Macro to accept color values in their raw form to create +// a value that represents both a foreground and background +// color in a single byte. +// For Foreground, and EFI_* value is valid from EFI_BLACK(0x00) to +// EFI_WHITE (0x0F). +// For Background, only EFI_BLACK, EFI_BLUE, EFI_GREEN, EFI_CYAN, +// EFI_RED, EFI_MAGENTA, EFI_BROWN, and EFI_LIGHTGRAY are acceptable +// +// Do not use EFI_BACKGROUND_xxx values with this macro. +// +#define EFI_TEXT_ATTR(Foreground,Background) ((Foreground) | ((Background) << 4)) + +#define EFI_BACKGROUND_BLACK 0x00 +#define EFI_BACKGROUND_BLUE 0x10 +#define EFI_BACKGROUND_GREEN 0x20 +#define EFI_BACKGROUND_CYAN (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_GREEN) +#define EFI_BACKGROUND_RED 0x40 +#define EFI_BACKGROUND_MAGENTA (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_RED) +#define EFI_BACKGROUND_BROWN (EFI_BACKGROUND_GREEN | EFI_BACKGROUND_RED) +#define EFI_BACKGROUND_LIGHTGRAY (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_GREEN | EFI_BACKGROUND_RED) + +// +// We currently define attributes from 0 - 7F for color manipulations +// To internally handle the local display characteristics for a particular character, +// Bit 7 signifies the local glyph representation for a character. If turned on, glyphs will be +// pulled from the wide glyph database and will display locally as a wide character (16 X 19 versus 8 X 19) +// If bit 7 is off, the narrow glyph database will be used. This does NOT affect information that is sent to +// non-local displays, such as serial or LAN consoles. +// +#define EFI_WIDE_ATTRIBUTE 0x80 + +/** + Reset the text output device hardware and optionally run diagnostics + + @param This The protocol instance pointer. + @param ExtendedVerification Driver may perform more exhaustive verification + operation of the device during reset. + + @retval EFI_SUCCESS The text output device was reset. + @retval EFI_DEVICE_ERROR The text output device is not functioning correctly and + could not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_RESET)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Write a string to the output device. + + @param This The protocol instance pointer. + @param String The NULL-terminated string to be displayed on the output + device(s). All output devices must also support the Unicode + drawing character codes defined in this file. + + @retval EFI_SUCCESS The string was output to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to output + the text. + @retval EFI_UNSUPPORTED The output device's mode is not currently in a + defined text mode. + @retval EFI_WARN_UNKNOWN_GLYPH This warning code indicates that some of the + characters in the string could not be + rendered and were skipped. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_STRING)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN CHAR16 *String + ); + +/** + Verifies that all characters in a string can be output to the + target device. + + @param This The protocol instance pointer. + @param String The NULL-terminated string to be examined for the output + device(s). + + @retval EFI_SUCCESS The device(s) are capable of rendering the output string. + @retval EFI_UNSUPPORTED Some of the characters in the string cannot be + rendered by one or more of the output devices mapped + by the EFI handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_TEST_STRING)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN CHAR16 *String + ); + +/** + Returns information for an available text mode that the output device(s) + supports. + + @param This The protocol instance pointer. + @param ModeNumber The mode number to return information on. + @param Columns Returns the geometry of the text output device for the + requested ModeNumber. + @param Rows Returns the geometry of the text output device for the + requested ModeNumber. + + @retval EFI_SUCCESS The requested mode information was returned. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED The mode number was not valid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_QUERY_MODE)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN UINTN ModeNumber, + OUT UINTN *Columns, + OUT UINTN *Rows + ); + +/** + Sets the output device(s) to a specified mode. + + @param This The protocol instance pointer. + @param ModeNumber The mode number to set. + + @retval EFI_SUCCESS The requested text mode was set. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED The mode number was not valid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_SET_MODE)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN UINTN ModeNumber + ); + +/** + Sets the background and foreground colors for the OutputString () and + ClearScreen () functions. + + @param This The protocol instance pointer. + @param Attribute The attribute to set. Bits 0..3 are the foreground color, and + bits 4..6 are the background color. All other bits are undefined + and must be zero. The valid Attributes are defined in this file. + + @retval EFI_SUCCESS The attribute was set. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED The attribute requested is not defined. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_SET_ATTRIBUTE)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN UINTN Attribute + ); + +/** + Clears the output device(s) display to the currently selected background + color. + + @param This The protocol instance pointer. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED The output device is not in a valid text mode. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_CLEAR_SCREEN)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This + ); + +/** + Sets the current coordinates of the cursor position + + @param This The protocol instance pointer. + @param Column The position to set the cursor to. Must be greater than or + equal to zero and less than the number of columns and rows + by QueryMode (). + @param Row The position to set the cursor to. Must be greater than or + equal to zero and less than the number of columns and rows + by QueryMode (). + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + @retval EFI_UNSUPPORTED The output device is not in a valid text mode, or the + cursor position is invalid for the current mode. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_SET_CURSOR_POSITION)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN UINTN Column, + IN UINTN Row + ); + +/** + Makes the cursor visible or invisible + + @param This The protocol instance pointer. + @param Visible If TRUE, the cursor is set to be visible. If FALSE, the cursor is + set to be invisible. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the + request, or the device does not support changing + the cursor mode. + @retval EFI_UNSUPPORTED The output device is not in a valid text mode. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TEXT_ENABLE_CURSOR)( + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *This, + IN BOOLEAN Visible + ); + +/** + @par Data Structure Description: + Mode Structure pointed to by Simple Text Out protocol. +**/ +typedef struct { + /// + /// The number of modes supported by QueryMode () and SetMode (). + /// + INT32 MaxMode; + + // + // current settings + // + + /// + /// The text mode of the output device(s). + /// + INT32 Mode; + /// + /// The current character output attribute. + /// + INT32 Attribute; + /// + /// The cursor's column. + /// + INT32 CursorColumn; + /// + /// The cursor's row. + /// + INT32 CursorRow; + /// + /// The cursor is currently visible or not. + /// + BOOLEAN CursorVisible; +} EFI_SIMPLE_TEXT_OUTPUT_MODE; + +/// +/// The SIMPLE_TEXT_OUTPUT protocol is used to control text-based output devices. +/// It is the minimum required protocol for any handle supplied as the ConsoleOut +/// or StandardError device. In addition, the minimum supported text mode of such +/// devices is at least 80 x 25 characters. +/// +struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL { + EFI_TEXT_RESET Reset; + + EFI_TEXT_STRING OutputString; + EFI_TEXT_TEST_STRING TestString; + + EFI_TEXT_QUERY_MODE QueryMode; + EFI_TEXT_SET_MODE SetMode; + EFI_TEXT_SET_ATTRIBUTE SetAttribute; + + EFI_TEXT_CLEAR_SCREEN ClearScreen; + EFI_TEXT_SET_CURSOR_POSITION SetCursorPosition; + EFI_TEXT_ENABLE_CURSOR EnableCursor; + + /// + /// Pointer to SIMPLE_TEXT_OUTPUT_MODE data. + /// + EFI_SIMPLE_TEXT_OUTPUT_MODE *Mode; +}; + +extern EFI_GUID gEfiSimpleTextOutProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardEdge.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardEdge.h new file mode 100644 index 0000000000..3107070ee9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardEdge.h @@ -0,0 +1,736 @@ +/** @file + The Smart Card Edge Protocol provides an abstraction for device to provide Smart + Card support. + + This protocol allows UEFI applications to interface with a Smart Card during + boot process for authentication or data signing/decryption, especially if the + application has to make use of PKI. + + Copyright (c) 2015-2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + +**/ + +#ifndef __SMART_CARD_EDGE_H__ +#define __SMART_CARD_EDGE_H__ + +#define EFI_SMART_CARD_EDGE_PROTOCOL_GUID \ + { \ + 0xd317f29b, 0xa325, 0x4712, {0x9b, 0xf1, 0xc6, 0x19, 0x54, 0xdc, 0x19, 0x8c} \ + } + +typedef struct _EFI_SMART_CARD_EDGE_PROTOCOL EFI_SMART_CARD_EDGE_PROTOCOL; + +// +// Maximum size for a Smart Card AID (Application IDentifier) +// +#define SCARD_AID_MAXSIZE 0x0010 +// +// Size of CSN (Card Serial Number) +// +#define SCARD_CSN_SIZE 0x0010 +// +// Current specification version 1.00 +// +#define SMART_CARD_EDGE_PROTOCOL_VERSION_1 0x00000100 +// +// Parameters type definition +// +typedef UINT8 SMART_CARD_AID[SCARD_AID_MAXSIZE]; +typedef UINT8 SMART_CARD_CSN[SCARD_CSN_SIZE]; + +// +// Type of data elements in credentials list +// +// value of tag field for header, the number of containers +// +#define SC_EDGE_TAG_HEADER 0x0000 +// +// value of tag field for certificate +// +#define SC_EDGE_TAG_CERT 0x0001 +// +// value of tag field for key index associated with certificate +// +#define SC_EDGE_TAG_KEY_ID 0x0002 +// +// value of tag field for key type +// +#define SC_EDGE_TAG_KEY_TYPE 0x0003 +// +// value of tag field for key size +// +#define SC_EDGE_TAG_KEY_SIZE 0x0004 + +// +// Length of L fields of TLV items +// +// +// size of L field for header +// +#define SC_EDGE_L_SIZE_HEADER 1 +// +// size of L field for certificate (big endian) +// +#define SC_EDGE_L_SIZE_CERT 2 +// +// size of L field for key index +// +#define SC_EDGE_L_SIZE_KEY_ID 1 +// +// size of L field for key type +// +#define SC_EDGE_L_SIZE_KEY_TYPE 1 +// +// size of L field for key size (big endian) +// +#define SC_EDGE_L_SIZE_KEY_SIZE 2 + +// +// Some TLV items have a fixed value for L field +// +// value of L field for header +// +#define SC_EDGE_L_VALUE_HEADER 1 +// +// value of L field for key index +// +#define SC_EDGE_L_VALUE_KEY_ID 1 +// +// value of L field for key type +// +#define SC_EDGE_L_VALUE_KEY_TYPE 1 +// +// value of L field for key size +// +#define SC_EDGE_L_VALUE_KEY_SIZE 2 + +// +// Possible values for key type +// +// +// RSA decryption +// +#define SC_EDGE_RSA_EXCHANGE 0x01 +// +// RSA signature +// +#define SC_EDGE_RSA_SIGNATURE 0x02 +// +// ECDSA signature +// +#define SC_EDGE_ECDSA_256 0x03 +// +// ECDSA signature +// +#define SC_EDGE_ECDSA_384 0x04 +// +// ECDSA signature +// +#define SC_EDGE_ECDSA_521 0x05 +// +// ECDH agreement +// +#define SC_EDGE_ECDH_256 0x06 +// +// ECDH agreement +// +#define SC_EDGE_ECDH_384 0x07 +// +// ECDH agreement +// +#define SC_EDGE_ECDH_521 0x08 + +// +// Padding methods GUIDs for signature +// +// +// RSASSA- PKCS#1-V1.5 padding method, for signature +// +#define EFI_PADDING_RSASSA_PKCS1V1P5_GUID \ + { \ + 0x9317ec24, 0x7cb0, 0x4d0e, {0x8b, 0x32, 0x2e, 0xd9, 0x20, 0x9c, 0xd8, 0xaf} \ + } + +extern EFI_GUID gEfiPaddingRsassaPkcs1V1P5Guid; + +// +// RSASSA-PSS padding method, for signature +// +#define EFI_PADDING_RSASSA_PSS_GUID \ + { \ + 0x7b2349e0, 0x522d, 0x4f8e, {0xb9, 0x27, 0x69, 0xd9, 0x7c, 0x9e, 0x79, 0x5f} \ + } + +extern EFI_GUID gEfiPaddingRsassaPssGuid; + +// +// Padding methods GUIDs for decryption +// +// +// No padding, for decryption +// +#define EFI_PADDING_NONE_GUID \ + { \ + 0x3629ddb1, 0x228c, 0x452e, {0xb6, 0x16, 0x09, 0xed, 0x31, 0x6a, 0x97, 0x00} \ + } + +extern EFI_GUID gEfiPaddingNoneGuid; + +// +// RSAES-PKCS#1-V1.5 padding, for decryption +// +#define EFI_PADDING_RSAES_PKCS1V1P5_GUID \ + { \ + 0xe1c1d0a9, 0x40b1, 0x4632, {0xbd, 0xcc, 0xd9, 0xd6, 0xe5, 0x29, 0x56, 0x31} \ + } + +extern EFI_GUID gEfiPaddingRsaesPkcs1V1P5Guid; + +// +// RSAES-OAEP padding, for decryption +// +#define EFI_PADDING_RSAES_OAEP_GUID \ + { \ + 0xc1e63ac4, 0xd0cf, 0x4ce6, {0x83, 0x5b, 0xee, 0xd0, 0xe6, 0xa8, 0xa4, 0x5b} \ + } + +extern EFI_GUID gEfiPaddingRsaesOaepGuid; + +/** + This function retrieves the context driver. + + The GetContextfunction returns the context of the protocol, the application + identifiers supported by the protocol and the number and the CSN unique identifier + of Smart Cards that are present and supported by protocol. + + If AidTableSize, AidTable, CsnTableSize, CsnTable or VersionProtocol is NULL, + the function does not fail but does not fill in such variables. + + In case AidTableSize indicates a buffer too small to hold all the protocol AID table, + only the first AidTableSize items of the table are returned in AidTable. + + In case CsnTableSize indicates a buffer too small to hold the entire table of + Smart Card CSN present, only the first CsnTableSize items of the table are returned + in CsnTable. + + VersionScEdgeProtocol returns the version of the EFI_SMART_CARD_EDGE_PROTOCOL this + driver uses. For this protocol specification value is SMART_CARD_EDGE_PROTOCOL_VERSION_1. + + In case of Smart Card removal the internal CSN list is immediately updated, even if + a connection is opened with that Smart Card. + + @param[in] This Indicates a pointer to the calling context. + @param[out] NumberAidSupported Number of AIDs this protocol supports. + @param[in, out] AidTableSize On input, number of items allocated for the + AID table. On output, number of items returned + by protocol. + @param[out] AidTable Table of the AIDs supported by the protocol. + @param[out] NumberSCPresent Number of currently present Smart Cards that + are supported by protocol. + @param[in, out] CsnTableSize On input, the number of items the buffer CSN + table can contain. On output, the number of + items returned by the protocol. + @param[out] CsnTable Table of the CSN of the Smart Card present and + supported by protocol. + @param[out] VersionScEdgeProtocol EFI_SMART_CARD_EDGE_PROTOCOL version. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER NumberSCPresent is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_CONTEXT) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + OUT UINTN *NumberAidSupported, + IN OUT UINTN *AidTableSize OPTIONAL, + OUT SMART_CARD_AID *AidTable OPTIONAL, + OUT UINTN *NumberSCPresent, + IN OUT UINTN *CsnTableSize OPTIONAL, + OUT SMART_CARD_CSN *CsnTable OPTIONAL, + OUT UINT32 *VersionScEdgeProtocol OPTIONAL + ); + +/** + This function establish a connection with a Smart Card the protocol support. + + In case of success the SCardHandle can be used. + + If the ScardCsn is NULL the connection is established with the first Smart Card + the protocol finds in its table of Smart Card present and supported. Else it + establish context with the Smart Card whose CSN given by ScardCsn. + + If ScardAid is not NULL the function returns the Smart Card AID the protocol supports. + After a successful connect the SCardHandle will remain existing even in case Smart Card + removed from Smart Card reader, but all function invoking this SCardHandle will fail. + SCardHandle is released only on Disconnect. + + @param[in] This Indicates a pointer to the calling context. + @param[out] SCardHandle Handle on Smart Card connection. + @param[in] ScardCsn CSN of the Smart Card the connection has to be + established. + @param[out] ScardAid AID of the Smart Card the connection has been + established. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER SCardHandle is NULL. + @retval EFI_NO_MEDIA No Smart Card supported by protocol is present, + Smart Card with CSN ScardCsn or Reader has been + removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_CONNECT) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + OUT EFI_HANDLE *SCardHandle, + IN UINT8 *ScardCsn OPTIONAL, + OUT UINT8 *ScardAid OPTIONAL + ); + +/** + This function releases a connection previously established by Connect. + + The Disconnect function releases the connection previously established by + a Connect. In case the Smart Card or the Smart Card reader has been removed + before this call, this function returns EFI_SUCCESS. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection to release. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_DISCONNECT) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle + ); + +/** + This function returns the Smart Card serial number. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[out] Csn The Card Serial number, 16 bytes array. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_CSN) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + OUT UINT8 Csn[SCARD_CSN_SIZE] + ); + +/** + This function returns the name of the Smart Card reader used for this connection. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in, out] ReaderNameLength On input, a pointer to the variable that holds + the maximal size, in bytes, of ReaderName. + On output, the required size, in bytes, for ReaderName. + @param[out] ReaderName A pointer to a NULL terminated string that will + contain the reader name. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER ReaderNameLength is NULL. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_READER_NAME) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN OUT UINTN *ReaderNameLength, + OUT CHAR16 *ReaderName OPTIONAL + ); + +/** + This function authenticates a Smart Card user by presenting a PIN code. + + The VerifyPinfunction presents a PIN code to the Smart Card. + + If Smart Card found the PIN code correct the user is considered authenticated + to current application, and the function returns TRUE. + + Negative or null PinSize value rejected if PinCodeis not NULL. + + A NULL PinCodebuffer means the application didn't know the PIN, in that case: + - If PinSize value is negative the caller only wants to know if the current + chain of the elements Smart Card Edge protocol, Smart Card Reader protocol + and Smart Card Reader supports the Secure Pin Entry PCSC V2 functionality. + - If PinSize value is positive or null the caller ask to perform the verify + PIN using the Secure PIN Entry functionality. + + In PinCode buffer, the PIN value is always given in plaintext, in case of secure + messaging the SMART_CARD_EDGE_PROTOCOL will be in charge of all intermediate + treatments to build the correct Smart Card APDU. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in] PinSize PIN code buffer size. + @param[in] PinCode PIN code to present to the Smart Card. + @param[out] PinResult Result of PIN code presentation to the Smart Card. + TRUE when Smard Card founds the PIN code correct. + @param[out] RemainingAttempts Number of attempts still possible. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_UNSUPPORTED Pinsize < 0 and Secure PIN Entry functionality not + supported. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER Bad value for PinSize: value not supported by Smart + Card or, negative with PinCode not null. + @retval EFI_INVALID_PARAMETER PinResult is NULL. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_VERIFY_PIN) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN INT32 PinSize, + IN UINT8 *PinCode, + OUT BOOLEAN *PinResult, + OUT UINT32 *RemainingAttempts OPTIONAL + ); + +/** + This function gives the remaining number of attempts for PIN code presentation. + + The number of attempts to present a correct PIN is limited and depends on Smart + Card and on PIN. + + This function will retrieve the number of remaining possible attempts. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[out] RemainingAttempts Number of attempts still possible. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER RemainingAttempts is NULL. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_PIN_REMAINING) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + OUT UINT32 *RemainingAttempts + ); + +/** + This function returns a specific data from Smart Card. + + The function is generic for any kind of data, but driver and application must + share an EFI_GUID that identify the data. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in] DataId The type identifier of the data to get. + @param[in, out] DataSize On input, in bytes, the size of Data. On output, + in bytes, the size of buffer required to store + the specified data. + @param[out] Data The data buffer in which the data is returned. + The type of the data buffer is associated with + the DataId. Ignored if *DataSize is 0. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER DataId is NULL. + @retval EFI_INVALID_PARAMETER DataSize is NULL. + @retval EFI_INVALID_PARAMETER Data is NULL, and *DataSize is not zero. + @retval EFI_NOT_FOUND DataId unknown for this driver. + @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the specified + data and the required size is returned in DataSize. + @retval EFI_ACCESS_DENIED Operation not performed, conditions not fulfilled. + PIN not verified. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_DATA) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN EFI_GUID *DataId, + IN OUT UINTN *DataSize, + OUT VOID *Data OPTIONAL + ); + +/** + This function retrieve credentials store into the Smart Card. + + The function returns a series of items in TLV (Tag Length Value) format. + + First TLV item is the header item that gives the number of following + containers (0x00, 0x01, Nb containers). + + All these containers are a series of 4 TLV items: + - The certificate item (0x01, certificate size, certificate) + - The Key identifier item (0x02, 0x01, key index) + - The key type item (0x03, 0x01, key type) + - The key size item (0x04, 0x02, key size), key size in number of bits. + Numeric multi-bytes values are on big endian format, most significant byte first: + - The L field value for certificate (2 bytes) + - The L field value for key size (2 bytes) + - The value field for key size (2 bytes) + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in, out] CredentialSize On input, in bytes, the size of buffer to store + the list of credential. + On output, in bytes, the size of buffer required + to store the entire list of credentials. + + @param[out] CredentialList List of credentials stored into the Smart Card. + A list of TLV (Tag Length Value) elements organized + in containers array. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER CredentialSize is NULL. + @retval EFI_INVALID_PARAMETER CredentialList is NULL, if CredentialSize is not zero. + @retval EFI_BUFFER_TOO_SMALL The size of CredentialList is too small for the + specified data and the required size is returned in + CredentialSize. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_GET_CREDENTIAL) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN OUT UINTN *CredentialSize, + OUT UINT8 *CredentialList OPTIONAL + ); + +/** + This function signs an already hashed data with a Smart Card private key. + + This function signs data, actually it is the hash of these data that is given + to the function. + + SignatureData buffer shall be big enough for signature. Signature size is + function key size and key type. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in] KeyId Identifier of the key container, retrieved + in a key index item of credentials. + @param[in] KeyType The key type, retrieved in a key type item of + credentials. + + @param[in] HashAlgorithm Hash algorithm used to hash the, one of: + - EFI_HASH_ALGORITHM_SHA1_GUID + - EFI_HASH_ALGORITHM_SHA256_GUID + - EFI_HASH_ALGORITHM_SHA384_GUID + - EFI_HASH_ALGORITHM_SHA512_GUID + @param[in] PaddingMethod Padding method used jointly with hash algorithm, + one of: + - EFI_PADDING_RSASSA_PKCS1V1P5_GUID + - EFI_PADDING_RSASSA_PSS_GUID + @param[in] HashedData Hash of the data to sign. Size is function of the + HashAlgorithm. + + @param[out] SignatureData Resulting signature with private key KeyId. Size + is function of the KeyType and key size retrieved + in the associated key size item of credentials. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER KeyId is not valid. + @retval EFI_INVALID_PARAMETER KeyType is not valid or not corresponding to KeyId. + @retval EFI_INVALID_PARAMETER HashAlgorithm is NULL. + @retval EFI_INVALID_PARAMETER HashAlgorithm is not valid. + @retval EFI_INVALID_PARAMETER PaddingMethod is NULL. + @retval EFI_INVALID_PARAMETER PaddingMethod is not valid. + @retval EFI_INVALID_PARAMETER HashedData is NULL. + @retval EFI_INVALID_PARAMETER SignatureData is NULL. + @retval EFI_ACCESS_DENIED Operation not performed, conditions not fulfilled. + PIN not verified. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_SIGN_DATA) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN UINTN KeyId, + IN UINTN KeyType, + IN EFI_GUID *HashAlgorithm, + IN EFI_GUID *PaddingMethod, + IN UINT8 *HashedData, + OUT UINT8 *SignatureData + ); + +/** + This function decrypts data with a PKI/RSA Smart Card private key. + + The function decrypts some PKI/RSA encrypted data with private key securely + stored into the Smart Card. + + The KeyId must reference a key of type SC_EDGE_RSA_EXCHANGE. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in] KeyId Identifier of the key container, retrieved + in a key index item of credentials. + @param[in] HashAlgorithm Hash algorithm used to hash the, one of: + - EFI_HASH_ALGORITHM_SHA1_GUID + - EFI_HASH_ALGORITHM_SHA256_GUID + - EFI_HASH_ALGORITHM_SHA384_GUID + - EFI_HASH_ALGORITHM_SHA512_GUID + @param[in] PaddingMethod Padding method used jointly with hash algorithm, + one of: + - EFI_PADDING_NONE_GUID + - EFI_PADDING_RSAES_PKCS1V1P5_GUID + - EFI_PADDING_RSAES_OAEP_GUID + @param[in] EncryptedSize Size of data to decrypt. + @param[in] EncryptedData Data to decrypt + @param[in, out] PlaintextSize On input, in bytes, the size of buffer to store + the decrypted data. + On output, in bytes, the size of buffer required + to store the decrypted data. + @param[out] PlaintextData Buffer for decrypted data, padding removed. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER KeyId is not valid or associated key not of type + SC_EDGE_RSA_EXCHANGE. + @retval EFI_INVALID_PARAMETER HashAlgorithm is NULL. + @retval EFI_INVALID_PARAMETER HashAlgorithm is not valid. + @retval EFI_INVALID_PARAMETER PaddingMethod is NULL. + @retval EFI_INVALID_PARAMETER PaddingMethod is not valid. + @retval EFI_INVALID_PARAMETER EncryptedSize is 0. + @retval EFI_INVALID_PARAMETER EncryptedData is NULL. + @retval EFI_INVALID_PARAMETER PlaintextSize is NULL. + @retval EFI_INVALID_PARAMETER PlaintextData is NULL. + @retval EFI_ACCESS_DENIED Operation not performed, conditions not fulfilled. + PIN not verified. + @retval EFI_BUFFER_TOO_SMALL PlaintextSize is too small for the plaintext data + and the required size is returned in PlaintextSize. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_DECRYPT_DATA) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN UINTN KeyId, + IN EFI_GUID *HashAlgorithm, + IN EFI_GUID *PaddingMethod, + IN UINTN EncryptedSize, + IN UINT8 *EncryptedData, + IN OUT UINTN *PlaintextSize, + OUT UINT8 *PlaintextData + ); + +/** + This function performs a secret Diffie Hellman agreement calculation that would + be used to derive a symmetric encryption / decryption key. + + The function compute a DH agreement that should be diversified togenerate a symmetric + key to proceed encryption or decryption. + + The application and the Smart Card shall agree on the diversification process. + + The KeyId must reference a key of one of the types: SC_EDGE_ECDH_256, SC_EDGE_ECDH_384 + or SC_EDGE_ECDH_521. + + @param[in] This Indicates a pointer to the calling context. + @param[in] SCardHandle Handle on Smart Card connection. + @param[in] KeyId Identifier of the key container, retrieved + in a key index item of credentials. + @param[in] dataQx Public key x coordinate. Size is the same as + key size for KeyId. Stored in big endian format. + @param[in] dataQy Public key y coordinate. Size is the same as + key size for KeyId. Stored in big endian format. + @param[out] DHAgreement Buffer for DH agreement computed. Size must be + bigger or equal to key size for KeyId. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER No connection for SCardHandle value. + @retval EFI_INVALID_PARAMETER KeyId is not valid. + @retval EFI_INVALID_PARAMETER dataQx is NULL. + @retval EFI_INVALID_PARAMETER dataQy is NULL. + @retval EFI_INVALID_PARAMETER DHAgreement is NULL. + @retval EFI_ACCESS_DENIED Operation not performed, conditions not fulfilled. + PIN not verified. + @retval EFI_NO_MEDIA Smart Card or Reader of SCardHandle connection + has been removed. A Disconnect should be performed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT) ( + IN EFI_SMART_CARD_EDGE_PROTOCOL *This, + IN EFI_HANDLE SCardHandle, + IN UINTN KeyId, + IN UINT8 *dataQx, + IN UINT8 *dataQy, + OUT UINT8 *DHAgreement + ); + +/// +/// Smart card aware application invokes this protocol to get access to an inserted +/// smart card in the reader or to the reader itself. +/// +struct _EFI_SMART_CARD_EDGE_PROTOCOL { + EFI_SMART_CARD_EDGE_GET_CONTEXT GetContext; + EFI_SMART_CARD_EDGE_CONNECT Connect; + EFI_SMART_CARD_EDGE_DISCONNECT Disconnect; + EFI_SMART_CARD_EDGE_GET_CSN GetCsn; + EFI_SMART_CARD_EDGE_GET_READER_NAME GetReaderName; + EFI_SMART_CARD_EDGE_VERIFY_PIN VerifyPin; + EFI_SMART_CARD_EDGE_GET_PIN_REMAINING GetPinRemaining; + EFI_SMART_CARD_EDGE_GET_DATA GetData; + EFI_SMART_CARD_EDGE_GET_CREDENTIAL GetCredential; + EFI_SMART_CARD_EDGE_SIGN_DATA SignData; + EFI_SMART_CARD_EDGE_DECRYPT_DATA DecryptData; + EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT BuildDHAgreement; +}; + +extern EFI_GUID gEfiSmartCardEdgeProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardReader.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardReader.h new file mode 100644 index 0000000000..e1344902fb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmartCardReader.h @@ -0,0 +1,319 @@ +/** @file + The UEFI Smart Card Reader Protocol provides an abstraction for device to provide + smart card reader support. This protocol is very close to Part 5 of PC/SC workgroup + specifications and provides an API to applications willing to communicate with a + smart card or a smart card reader. + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMART_CARD_READER_H__ +#define __SMART_CARD_READER_H__ + +#define EFI_SMART_CARD_READER_PROTOCOL_GUID \ + { \ + 0x2a4d1adf, 0x21dc, 0x4b81, {0xa4, 0x2f, 0x8b, 0x8e, 0xe2, 0x38, 0x00, 0x60} \ + } + +typedef struct _EFI_SMART_CARD_READER_PROTOCOL EFI_SMART_CARD_READER_PROTOCOL; + +// +// Codes for access mode +// +#define SCARD_AM_READER 0x0001 // Exclusive access to reader +#define SCARD_AM_CARD 0x0002 // Exclusive access to card +// +// Codes for card action +// +#define SCARD_CA_NORESET 0x0000 // Don't reset card +#define SCARD_CA_COLDRESET 0x0001 // Perform a cold reset +#define SCARD_CA_WARMRESET 0x0002 // Perform a warm reset +#define SCARD_CA_UNPOWER 0x0003 // Power off the card +#define SCARD_CA_EJECT 0x0004 // Eject the card +// +// Protocol types +// +#define SCARD_PROTOCOL_UNDEFINED 0x0000 +#define SCARD_PROTOCOL_T0 0x0001 +#define SCARD_PROTOCOL_T1 0x0002 +#define SCARD_PROTOCOL_RAW 0x0004 +// +// Codes for state type +// +#define SCARD_UNKNOWN 0x0000 /* state is unknown */ +#define SCARD_ABSENT 0x0001 /* Card is absent */ +#define SCARD_INACTIVE 0x0002 /* Card is present and not powered*/ +#define SCARD_ACTIVE 0x0003 /* Card is present and powered */ +// +// Macro to generate a ControlCode & PC/SC part 10 control code +// +#define SCARD_CTL_CODE(code) (0x42000000 + (code)) +#define CM_IOCTL_GET_FEATURE_REQUEST SCARD_CTL_CODE(3400) + +/** + This function requests connection to the smart card or the reader, using the + appropriate reset type and protocol. + + The SCardConnectfunction requests access to the smart card or the reader. Upon + success, it is then possible to call SCardTransmit. + + If AccessMode is set to SCARD_AM_READER, PreferredProtocols must be set to + SCARD_PROTOCOL_UNDEFINED and CardAction to SCARD_CA_NORESET else function + fails with EFI_INVALID_PARAMETER. + + @param[in] This Indicates a pointer to the calling context. + @param[in] AccessMode Codes of access mode. + @param[in] CardAction SCARD_CA_NORESET, SCARD_CA_COLDRESET or + SCARD_CA_WARMRESET. + @param[in] PreferredProtocols Bitmask of acceptable protocols. + @param[out] ActiveProtocol A flag that indicates the active protocol. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL + @retval EFI_INVALID_PARAMETER AccessMode is not valid. + @retval EFI_INVALID_PARAMETER CardAction is not valid. + @retval EFI_INVALID_PARAMETER Invalid combination of AccessMode/CardAction/ + PreferredProtocols. + @retval EFI_NOT_READY A smart card is inserted but failed to return an ATR. + @retval EFI_UNSUPPORTED PreferredProtocols does not contain an available + protocol to use. + @retval EFI_NO_MEDIA AccessMode is set to SCARD_AM_CARD but there is + no smart card inserted. + @retval EFI_ACCESS_DENIED Access is already locked by a previous SCardConnectcall. + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_CONNECT) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + IN UINT32 AccessMode, + IN UINT32 CardAction, + IN UINT32 PreferredProtocols, + OUT UINT32 *ActiveProtocol + ); + +/** + This function releases a connection previously taken by SCardConnect. + + The SCardDisconnect function releases the lock previously taken by SCardConnect. + In case the smart card has been removed before this call, thisfunction + returns EFI_SUCCESS. If there is no previous call to SCardConnect, this + function returns EFI_SUCCESS. + + @param[in] This Indicates a pointer to the calling context. + @param[in] CardAction Codes for card action. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL + @retval EFI_INVALID_PARAMETER CardAction value is unknown. + @retval EFI_UNSUPPORTED Reader does not support Eject card feature + (disconnect was not performed). + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_DISCONNECT) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + IN UINT32 CardAction + ); + +/** + This function retrieves some basic information about the smart card and reader. + + The SCardStatusfunction retrieves basic reader and card information. + + If ReaderName, State, CardProtocolor Atris NULL, the function does not fail but + does not fill in such variables. + + If EFI_SUCCESS is not returned, ReaderName and Atr contents shall not be considered + as valid. + + @param[in] This Indicates a pointer to the calling context. + @param[out] ReaderName A pointer to a NULL terminated string that will + contain the reader name. + @param[in, out] ReaderNameLength On input, a pointer to the variablethat holds the + maximal size, in bytes,of ReaderName. + On output, the required size, in bytes, for ReaderName. + @param[out] State Current state of the smart card reader. + @param[out] CardProtocol Current protocol used to communicate with the smart card. + @param[out] Atr A pointer to retrieve the ATR of the smart card. + @param[in, out] AtrLength On input, a pointer to hold the maximum size, in bytes, + of Atr(usually 33). + On output, the required size, inbytes, for the smart + card ATR. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL + @retval EFI_INVALID_PARAMETER ReaderName is not NULL but ReaderNameLength is NULL + @retval EFI_INVALID_PARAMETER Atr is not NULL but AtrLength is NULL + @retval EFI_BUFFER_TOO_SMALL ReaderNameLength is not big enough to hold the reader name. + ReaderNameLength has been updated to the required value. + @retval EFI_BUFFER_TOO_SMALL AtrLength is not big enough to hold the ATR. + AtrLength has been updated to the required value. + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_STATUS) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + OUT CHAR16 *ReaderName OPTIONAL, + IN OUT UINTN *ReaderNameLength OPTIONAL, + OUT UINT32 *State OPTIONAL, + OUT UINT32 *CardProtocol OPTIONAL, + OUT UINT8 *Atr OPTIONAL, + IN OUT UINTN *AtrLength OPTIONAL + ); + +/** + This function sends a command to the card or reader and returns its response. + + The protocol to use to communicate with the smart card has been selected through + SCardConnectcall. + + In case RAPDULength indicates a buffer too small to holdthe response APDU, the + function fails with EFI_BUFFER_TOO_SMALL. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOLinstance. + @param[in] CAPDU A pointer to a byte array thatcontains the Command + APDU to send to the smart card or reader. + @param[in] CAPDULength Command APDU size, in bytes. + @param[out] RAPDU A pointer to a byte array that will contain the + Response APDU. + @param[in, out] RAPDULength On input, the maximum size, inbytes, of the Response + APDU. + On output, the size, in bytes, of the Response APDU. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER CAPDU is NULL or CAPDULength is 0. + @retval EFI_BUFFER_TOO_SMALL RAPDULength is not big enough to hold the response APDU. + RAPDULength has been updated to the required value. + @retval EFI_NO_MEDIA There is no card in the reader. + @retval EFI_NOT_READY Card is not powered. + @retval EFI_PROTOCOL_ERROR A protocol error has occurred. + @retval EFI_TIMEOUT The reader did not respond. + @retval EFI_ACCESS_DENIED A communication with the reader/card is already pending. + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_TRANSMIT) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + IN UINT8 *CAPDU, + IN UINTN CAPDULength, + OUT UINT8 *RAPDU, + IN OUT UINTN *RAPDULength + ); + +/** + This function provides direct access to the reader. + + This function gives direct control to send commands to the driver or the reader. + The ControlCode to use is vendor dependant; the only standard code defined is + the one to get PC/SC part 10 features. + + InBuffer and Outbuffer may be NULL when ControlCode operation does not require + them. + + @param[in] This Indicates a pointer to the calling context. + @param[in] ControlCode The control code for the operation to perform. + @param[in] InBuffer A pointer to the input parameters. + @param[in] InBufferLength Size, in bytes, of input parameters. + @param[out] OutBuffer A pointer to the output parameters. + @param[in, out] OutBufferLength On input, maximal size, in bytes, to store output + parameters. + On output, the size, in bytes, of output parameters. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER ControlCode requires input parameters but: + InBuffer is NULL or InBufferLenth is NULL or + InBuffer is not NULL but InBufferLenth is less than + expected. + @retval EFI_INVALID_PARAMETER OutBuffer is not NULL but OutBufferLength is NULL. + @retval EFI_UNSUPPORTED ControlCode is not supported. + @retval EFI_BUFFER_TOO_SMALL OutBufferLength is not big enough to hold the output + parameters. + OutBufferLength has been updated to the required value. + @retval EFI_NO_MEDIA There is no card in the reader and the control code + specified requires one. + @retval EFI_NOT_READY ControlCode requires a powered card to operate. + @retval EFI_PROTOCOL_ERROR A protocol error has occurred. + @retval EFI_TIMEOUT The reader did not respond. + @retval EFI_ACCESS_DENIED A communication with the reader/card is already pending. + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_CONTROL) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + IN UINT32 ControlCode, + IN UINT8 *InBuffer OPTIONAL, + IN UINTN InBufferLength OPTIONAL, + OUT UINT8 *OutBuffer OPTIONAL, + IN OUT UINTN *OutBufferLength OPTIONAL + ); + +/** + This function retrieves a reader or smart card attribute. + + Possibly supported attrib values are listed in "PC/SC specification, Part 3: + Requirements for PC-Connected Interface Devices". + + @param[in] This Indicates a pointer to the calling context. + @param[in] Attrib Identifier for the attribute to retrieve. + @param[out] OutBuffer A pointer to a buffer that will contain + attribute data. + @param[in, out] OutBufferLength On input, maximal size, in bytes, to store + attribute data. + On output, the size, in bytes, of attribute + data. + + @retval EFI_SUCCESS The requested command completed successfully. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER OutBuffer is NULL or OutBufferLength is 0. + @retval EFI_BUFFER_TOO_SMALL OutBufferLength is not big enough to hold the output + parameters. + OutBufferLength has been updated to the required value. + @retval EFI_UNSUPPORTED Attribis not supported + @retval EFI_NO_MEDIA There is no card in the reader and Attrib value + requires one. + @retval EFI_NOT_READY Attrib requires a powered card to operate. + @retval EFI_PROTOCOL_ERROR A protocol error has occurred. + @retval EFI_TIMEOUT The reader did not respond. + @retval EFI_DEVICE_ERROR Any other error condition, typically a reader removal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMART_CARD_READER_GET_ATTRIB) ( + IN EFI_SMART_CARD_READER_PROTOCOL *This, + IN UINT32 Attrib, + OUT UINT8 *OutBuffer, + IN OUT UINTN *OutBufferLength + ); + +/// +/// Smart card aware application invokes this protocol to get access to an inserted +/// smart card in the reader or to the reader itself. +/// +struct _EFI_SMART_CARD_READER_PROTOCOL { + EFI_SMART_CARD_READER_CONNECT SCardConnect; + EFI_SMART_CARD_READER_DISCONNECT SCardDisconnect; + EFI_SMART_CARD_READER_STATUS SCardStatus; + EFI_SMART_CARD_READER_TRANSMIT SCardTransmit; + EFI_SMART_CARD_READER_CONTROL SCardControl; + EFI_SMART_CARD_READER_GET_ATTRIB SCardGetAttrib; +}; + +extern EFI_GUID gEfiSmartCardReaderProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Smbios.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Smbios.h new file mode 100644 index 0000000000..1ef57a665a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Smbios.h @@ -0,0 +1,207 @@ +/** @file + SMBIOS Protocol as defined in PI1.2 Specification VOLUME 5 Standard. + + SMBIOS protocol allows consumers to log SMBIOS data records, and enables the producer + to create the SMBIOS tables for a platform. + + This protocol provides an interface to add, remove or discover SMBIOS records. The driver which + produces this protocol is responsible for creating the SMBIOS data tables and installing the pointer + to the tables in the EFI System Configuration Table. + The caller is responsible for only adding SMBIOS records that are valid for the SMBIOS + MajorVersion and MinorVersion. When an enumerated SMBIOS field's values are + controlled by the DMTF, new values can be used as soon as they are defined by the DMTF without + requiring an update to MajorVersion and MinorVersion. + The SMBIOS protocol can only be called a TPL < TPL_NOTIFY. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SMBIOS_PROTOCOL_H__ +#define __SMBIOS_PROTOCOL_H__ + +#include + +#define EFI_SMBIOS_PROTOCOL_GUID \ + { 0x3583ff6, 0xcb36, 0x4940, { 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7 }} + +#define EFI_SMBIOS_TYPE_BIOS_INFORMATION SMBIOS_TYPE_BIOS_INFORMATION +#define EFI_SMBIOS_TYPE_SYSTEM_INFORMATION SMBIOS_TYPE_SYSTEM_INFORMATION +#define EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION SMBIOS_TYPE_BASEBOARD_INFORMATION +#define EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE SMBIOS_TYPE_SYSTEM_ENCLOSURE +#define EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION SMBIOS_TYPE_PROCESSOR_INFORMATION +#define EFI_SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION +#define EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON SMBIOS_TYPE_MEMORY_MODULE_INFORMATON +#define EFI_SMBIOS_TYPE_CACHE_INFORMATION SMBIOS_TYPE_CACHE_INFORMATION +#define EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION +#define EFI_SMBIOS_TYPE_SYSTEM_SLOTS SMBIOS_TYPE_SYSTEM_SLOTS +#define EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION +#define EFI_SMBIOS_TYPE_OEM_STRINGS SMBIOS_TYPE_OEM_STRINGS +#define EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS +#define EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION +#define EFI_SMBIOS_TYPE_GROUP_ASSOCIATIONS SMBIOS_TYPE_GROUP_ASSOCIATIONS +#define EFI_SMBIOS_TYPE_SYSTEM_EVENT_LOG SMBIOS_TYPE_SYSTEM_EVENT_LOG +#define EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY +#define EFI_SMBIOS_TYPE_MEMORY_DEVICE SMBIOS_TYPE_MEMORY_DEVICE +#define EFI_SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION +#define EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS +#define EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS +#define EFI_SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE +#define EFI_SMBIOS_TYPE_PORTABLE_BATTERY SMBIOS_TYPE_PORTABLE_BATTERY +#define EFI_SMBIOS_TYPE_SYSTEM_RESET SMBIOS_TYPE_SYSTEM_RESET +#define EFI_SMBIOS_TYPE_HARDWARE_SECURITY SMBIOS_TYPE_HARDWARE_SECURITY +#define EFI_SMBIOS_TYPE_SYSTEM_POWER_CONTROLS SMBIOS_TYPE_SYSTEM_POWER_CONTROLS +#define EFI_SMBIOS_TYPE_VOLTAGE_PROBE SMBIOS_TYPE_VOLTAGE_PROBE +#define EFI_SMBIOS_TYPE_COOLING_DEVICE SMBIOS_TYPE_COOLING_DEVICE +#define EFI_SMBIOS_TYPE_TEMPERATURE_PROBE SMBIOS_TYPE_TEMPERATURE_PROBE +#define EFI_SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE +#define EFI_SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS +#define EFI_SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE +#define EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION +#define EFI_SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION +#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE SMBIOS_TYPE_MANAGEMENT_DEVICE +#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT +#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA +#define EFI_SMBIOS_TYPE_MEMORY_CHANNEL SMBIOS_TYPE_MEMORY_CHANNEL +#define EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION SMBIOS_TYPE_IPMI_DEVICE_INFORMATION +#define EFI_SMBIOS_TYPE_SYSTEM_POWER_SUPPLY SMBIOS_TYPE_SYSTEM_POWER_SUPPLY +#define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION SMBIOS_TYPE_ADDITIONAL_INFORMATION +#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION +#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE +#define EFI_SMBIOS_TYPE_INACTIVE SMBIOS_TYPE_INACTIVE +#define EFI_SMBIOS_TYPE_END_OF_TABLE SMBIOS_TYPE_END_OF_TABLE +#define EFI_SMBIOS_OEM_BEGIN SMBIOS_OEM_BEGIN +#define EFI_SMBIOS_OEM_END SMBIOS_OEM_END + +typedef SMBIOS_TABLE_STRING EFI_SMBIOS_STRING; +typedef SMBIOS_TYPE EFI_SMBIOS_TYPE; +typedef SMBIOS_HANDLE EFI_SMBIOS_HANDLE; +typedef SMBIOS_STRUCTURE EFI_SMBIOS_TABLE_HEADER; + +typedef struct _EFI_SMBIOS_PROTOCOL EFI_SMBIOS_PROTOCOL; + +/** + Add an SMBIOS record. + + This function allows any agent to add SMBIOS records. The caller is responsible for ensuring + Record is formatted in a way that matches the version of the SMBIOS specification as defined in + the MajorRevision and MinorRevision fields of the EFI_SMBIOS_PROTOCOL. + Record must follow the SMBIOS structure evolution and usage guidelines in the SMBIOS + specification. Record starts with the formatted area of the SMBIOS structure and the length is + defined by EFI_SMBIOS_TABLE_HEADER.Length. Each SMBIOS structure is terminated by a + double-null (0x0000), either directly following the formatted area (if no strings are present) or + directly following the last string. The number of optional strings is not defined by the formatted area, + but is fixed by the call to Add(). A string can be a place holder, but it must not be a NULL string as + two NULL strings look like the double-null that terminates the structure. + + @param[in] This The EFI_SMBIOS_PROTOCOL instance. + @param[in] ProducerHandle The handle of the controller or driver associated with the SMBIOS information. NULL means no handle. + @param[in, out] SmbiosHandle On entry, the handle of the SMBIOS record to add. If FFFEh, then a unique handle + will be assigned to the SMBIOS record. If the SMBIOS handle is already in use, + EFI_ALREADY_STARTED is returned and the SMBIOS record is not updated. + @param[in] Record The data for the fixed portion of the SMBIOS record. The format of the record is + determined by EFI_SMBIOS_TABLE_HEADER.Type. The size of the formatted + area is defined by EFI_SMBIOS_TABLE_HEADER.Length and either followed + by a double-null (0x0000) or a set of null terminated strings and a null. + + @retval EFI_SUCCESS Record was added. + @retval EFI_OUT_OF_RESOURCES Record was not added. + @retval EFI_ALREADY_STARTED The SmbiosHandle passed in was already in use. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBIOS_ADD)( + IN CONST EFI_SMBIOS_PROTOCOL *This, + IN EFI_HANDLE ProducerHandle OPTIONAL, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle, + IN EFI_SMBIOS_TABLE_HEADER *Record +); + +/** + Update the string associated with an existing SMBIOS record. + + This function allows the update of specific SMBIOS strings. The number of valid strings for any + SMBIOS record is defined by how many strings were present when Add() was called. + + @param[in] This The EFI_SMBIOS_PROTOCOL instance. + @param[in] SmbiosHandle SMBIOS Handle of structure that will have its string updated. + @param[in] StringNumber The non-zero string number of the string to update. + @param[in] String Update the StringNumber string with String. + + @retval EFI_SUCCESS SmbiosHandle had its StringNumber String updated. + @retval EFI_INVALID_PARAMETER SmbiosHandle does not exist. + @retval EFI_UNSUPPORTED String was not added because it is longer than the SMBIOS Table supports. + @retval EFI_NOT_FOUND The StringNumber.is not valid for this SMBIOS record. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBIOS_UPDATE_STRING)( + IN CONST EFI_SMBIOS_PROTOCOL *This, + IN EFI_SMBIOS_HANDLE *SmbiosHandle, + IN UINTN *StringNumber, + IN CHAR8 *String +); + +/** + Remove an SMBIOS record. + + This function removes an SMBIOS record using the handle specified by SmbiosHandle. + + @param[in] This The EFI_SMBIOS_PROTOCOL instance. + @param[in] SmbiosHandle The handle of the SMBIOS record to remove. + + @retval EFI_SUCCESS SMBIOS record was removed. + @retval EFI_INVALID_PARAMETER SmbiosHandle does not specify a valid SMBIOS record. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBIOS_REMOVE)( + IN CONST EFI_SMBIOS_PROTOCOL *This, + IN EFI_SMBIOS_HANDLE SmbiosHandle +); + +/** + Allow the caller to discover all or some of the SMBIOS records. + + This function allows all of the SMBIOS records to be discovered. It's possible to find + only the SMBIOS records that match the optional Type argument. + + @param[in] This The EFI_SMBIOS_PROTOCOL instance. + @param[in, out] SmbiosHandle On entry, points to the previous handle of the SMBIOS record. On exit, points to the + next SMBIOS record handle. If it is FFFEh on entry, then the first SMBIOS record + handle will be returned. If it returns FFFEh on exit, then there are no more SMBIOS records. + @param[in] Type On entry, it points to the type of the next SMBIOS record to return. If NULL, it + indicates that the next record of any type will be returned. Type is not + modified by the this function. + @param[out] Record On exit, points to a pointer to the the SMBIOS Record consisting of the formatted area + followed by the unformatted area. The unformatted area optionally contains text strings. + @param[out] ProducerHandle On exit, points to the ProducerHandle registered by Add(). If no + ProducerHandle was passed into Add() NULL is returned. If a NULL pointer is + passed in no data will be returned. + @retval EFI_SUCCESS SMBIOS record information was successfully returned in Record. + SmbiosHandle is the handle of the current SMBIOS record + @retval EFI_NOT_FOUND The SMBIOS record with SmbiosHandle was the last available record. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBIOS_GET_NEXT)( + IN CONST EFI_SMBIOS_PROTOCOL *This, + IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle, + IN EFI_SMBIOS_TYPE *Type OPTIONAL, + OUT EFI_SMBIOS_TABLE_HEADER **Record, + OUT EFI_HANDLE *ProducerHandle OPTIONAL +); + +struct _EFI_SMBIOS_PROTOCOL { + EFI_SMBIOS_ADD Add; + EFI_SMBIOS_UPDATE_STRING UpdateString; + EFI_SMBIOS_REMOVE Remove; + EFI_SMBIOS_GET_NEXT GetNext; + UINT8 MajorVersion; ///< The major revision of the SMBIOS specification supported. + UINT8 MinorVersion; ///< The minor revision of the SMBIOS specification supported. +}; + +extern EFI_GUID gEfiSmbiosProtocolGuid; + +#endif // __SMBIOS_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmbusHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmbusHc.h new file mode 100644 index 0000000000..219a5cbe0c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmbusHc.h @@ -0,0 +1,289 @@ +/** @file + The file provides basic SMBus host controller management + and basic data transactions over the SMBus. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: PI + Version 1.00. + +**/ + +#ifndef __SMBUS_HC_H__ +#define __SMBUS_HC_H__ + +#include + +#define EFI_SMBUS_HC_PROTOCOL_GUID \ + {0xe49d33ed, 0x513d, 0x4634, { 0xb6, 0x98, 0x6f, 0x55, 0xaa, 0x75, 0x1c, 0x1b} } + +typedef struct _EFI_SMBUS_HC_PROTOCOL EFI_SMBUS_HC_PROTOCOL; + +/** + + The Execute() function provides a standard way to execute an + operation as defined in the System Management Bus (SMBus) + Specification. The resulting transaction will be either that + the SMBus slave devices accept this transaction or that this + function returns with error. + + @param This A pointer to the EFI_SMBUS_HC_PROTOCOL instance. + SlaveAddress The SMBus slave address of the device + with which to communicate. Type + EFI_SMBUS_DEVICE_ADDRESS is defined in + EFI_PEI_SMBUS_PPI.Execute() in the Platform + Initialization SMBus PPI Specification. + + @param Command This command is transmitted by the SMBus host + controller to the SMBus slave device and the + interpretation is SMBus slave device specific. + It can mean the offset to a list of functions + inside an SMBus slave device. Not all + operations or slave devices support this + command's registers. Type + EFI_SMBUS_DEVICE_COMMAND is defined in + EFI_PEI_SMBUS_PPI.Execute() in the Platform + Initialization SMBus PPI Specification. + + @param Operation Signifies the particular SMBus + hardware protocol instance it will use to + execute the SMBus transactions. This SMBus + hardware protocol is defined by the SMBus + Specification and is not related to PI + Architecture. Type EFI_SMBUS_OPERATION is + defined in EFI_PEI_SMBUS_PPI.Execute() in the + Platform Initialization SMBus PPI + Specification. + + @param PecCheck Defines if Packet Error Code (PEC) checking + is required for this operation. SMBus Host + Controller Code Definitions Version 1.0 + August 21, 2006 13 + + @param Length Signifies the number of bytes that this operation will do. + The maximum number of bytes can be revision + specific and operation specific. This field + will contain the actual number of bytes that + are executed for this operation. Not all + operations require this argument. + + @param Buffer Contains the value of data to execute to the + SMBus slave device. Not all operations require + this argument. The length of this buffer is + identified by Length. + + + @retval EFI_SUCCESS The last data that was returned from the + access matched the poll exit criteria. + + @retval EFI_CRC_ERROR Checksum is not correct (PEC is incorrect). + + @retval EFI_TIMEOUT Timeout expired before the operation was + completed. Timeout is determined by the + SMBus host controller device. + + @retval EFI_OUT_OF_RESOURCES The request could not be + completed due to a lack of + resources. + + @retval EFI_DEVICE_ERROR The request was not completed + because a failure that was reflected + in the Host Status Register bit. + Device errors are a result of a + transaction collision, illegal + command field, unclaimed cycle (host + initiated), or bus errors + (collisions). + + @retval EFI_INVALID_PARAMETER Operation is not defined in + EFI_SMBUS_OPERATION. + + @retval EFI_INVALID_PARAMETER Length/Buffer is NULL for + operations except for + EfiSmbusQuickRead and + EfiSmbusQuickWrite. Length is + outside the range of valid + values. + + @retval EFI_UNSUPPORTED The SMBus operation or PEC is not + supported. + + @retval EFI_BUFFER_TOO_SMALL Buffer is not sufficient for + this operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBUS_HC_EXECUTE_OPERATION)( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +); + + + +/** + + The ArpDevice() function provides a standard way for a device driver to + enumerate the entire SMBus or specific devices on the bus. + + @param This A pointer to the EFI_SMBUS_HC_PROTOCOL instance. + + @param ArpAll A Boolean expression that indicates if the + host drivers need to enumerate all the devices + or enumerate only the device that is + identified by SmbusUdid. If ArpAll is TRUE, + SmbusUdid and SlaveAddress are optional. If + ArpAll is FALSE, ArpDevice will enumerate + SmbusUdid and the address will be at + SlaveAddress. + + @param SmbusUdid The Unique Device Identifier (UDID) that is + associated with this device. Type + EFI_SMBUS_UDID is defined in + EFI_PEI_SMBUS_PPI.ArpDevice() in the + Platform Initialization SMBus PPI + Specification. + + @param SlaveAddress The SMBus slave address that is + associated with an SMBus UDID. + + @retval EFI_SUCCESS The last data that was returned from the + access matched the poll exit criteria. + + @retval EFI_CRC_ERROR Checksum is not correct (PEC is + incorrect). + + @retval EFI_TIMEOUT Timeout expired before the operation was + completed. Timeout is determined by the + SMBus host controller device. + + @retval EFI_OUT_OF_RESOURCES The request could not be + completed due to a lack of + resources. + + @retval EFI_DEVICE_ERROR The request was not completed + because a failure was reflected in + the Host Status Register bit. Device + Errors are a result of a transaction + collision, illegal command field, + unclaimed cycle (host initiated), or + bus errors (collisions). + + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are + not implemented by this driver. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE)( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +); + + +/** + The GetArpMap() function returns the mapping of all the SMBus devices + that were enumerated by the SMBus host driver. + + @param This A pointer to the EFI_SMBUS_HC_PROTOCOL instance. + + @param Length Size of the buffer that contains the SMBus + device map. + + @param SmbusDeviceMap The pointer to the device map as + enumerated by the SMBus controller + driver. + + @retval EFI_SUCCESS The SMBus returned the current device map. + + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are + not implemented by this driver. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP)( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +); + +/** + The notify function does some actions. + + @param SlaveAddress + The SMBUS hardware address to which the SMBUS device is preassigned or allocated. + + @param Data + Data of the SMBus host notify command that the caller wants to be called. + + @return EFI_STATUS +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBUS_NOTIFY_FUNCTION)( + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data +); + + +/** + + The Notify() function registers all the callback functions to + allow the bus driver to call these functions when the + SlaveAddress/Data pair happens. + + @param This A pointer to the EFI_SMBUS_HC_PROTOCOL instance. + + @param SlaveAddress Address that the host controller detects + as sending a message and calls all the registered function. + + @param Data Data that the host controller detects as sending + message and calls all the registered function. + + + @param NotifyFunction The function to call when the bus + driver detects the SlaveAddress and + Data pair. + + @retval EFI_SUCCESS NotifyFunction was registered. + + @retval EFI_UNSUPPORTED ArpDevice, GetArpMap, and Notify are + not implemented by this driver. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMBUS_HC_PROTOCOL_NOTIFY)( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction +); + + +/// +/// The EFI_SMBUS_HC_PROTOCOL provides SMBus host controller management and basic data +/// transactions over SMBus. There is one EFI_SMBUS_HC_PROTOCOL instance for each SMBus +/// host controller. +/// +struct _EFI_SMBUS_HC_PROTOCOL { + EFI_SMBUS_HC_EXECUTE_OPERATION Execute; + EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE ArpDevice; + EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP GetArpMap; + EFI_SMBUS_HC_PROTOCOL_NOTIFY Notify; +}; + + +extern EFI_GUID gEfiSmbusHcProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmAccess2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmAccess2.h new file mode 100644 index 0000000000..06475e1722 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmAccess2.h @@ -0,0 +1,38 @@ +/** @file + EFI SMM Access2 Protocol as defined in the PI 1.2 specification. + + This protocol is used to control the visibility of the SMRAM on the platform. + It abstracts the location and characteristics of SMRAM. The expectation is + that the north bridge or memory controller would publish this protocol. + + The principal functionality found in the memory controller includes the following: + - Exposing the SMRAM to all non-SMM agents, or the "open" state + - Shrouding the SMRAM to all but the SMM agents, or the "closed" state + - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be + perturbed by either boot service or runtime agents + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_ACCESS2_H_ +#define _SMM_ACCESS2_H_ + +#include + +#define EFI_SMM_ACCESS2_PROTOCOL_GUID EFI_MM_ACCESS_PROTOCOL_GUID + +typedef EFI_MM_ACCESS_PROTOCOL EFI_SMM_ACCESS2_PROTOCOL; + +typedef EFI_MM_OPEN EFI_SMM_OPEN2; + +typedef EFI_MM_CLOSE EFI_SMM_CLOSE2; + +typedef EFI_MM_LOCK EFI_SMM_LOCK2; + +typedef EFI_MM_CAPABILITIES EFI_SMM_CAPABILITIES2; +extern EFI_GUID gEfiSmmAccess2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmBase2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmBase2.h new file mode 100644 index 0000000000..492f400122 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmBase2.h @@ -0,0 +1,79 @@ +/** @file + EFI SMM Base2 Protocol as defined in the PI 1.2 specification. + + This protocol is utilized by all SMM drivers to locate the SMM infrastructure services and determine + whether the driver is being invoked inside SMRAM or outside of SMRAM. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_BASE2_H_ +#define _SMM_BASE2_H_ + +#include +#include + +#define EFI_SMM_BASE2_PROTOCOL_GUID EFI_MM_BASE_PROTOCOL_GUID + +typedef struct _EFI_SMM_BASE2_PROTOCOL EFI_SMM_BASE2_PROTOCOL; + +/** + Service to indicate whether the driver is currently executing in the SMM Initialization phase. + + This service is used to indicate whether the driver is currently executing in the SMM Initialization + phase. For SMM drivers, this will return TRUE in InSmram while inside the driver's entry point and + otherwise FALSE. For combination SMM/DXE drivers, this will return FALSE in the DXE launch. For the + SMM launch, it behaves as an SMM driver. + + @param[in] This The EFI_SMM_BASE2_PROTOCOL instance. + @param[out] InSmram Pointer to a Boolean which, on return, indicates that the driver is + currently executing inside of SMRAM (TRUE) or outside of SMRAM (FALSE). + + @retval EFI_SUCCESS The call returned successfully. + @retval EFI_INVALID_PARAMETER InSmram was NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_INSIDE_OUT2)( + IN CONST EFI_SMM_BASE2_PROTOCOL *This, + OUT BOOLEAN *InSmram + ) +; + +/** + Returns the location of the System Management Service Table (SMST). + + This function returns the location of the System Management Service Table (SMST). The use of the + API is such that a driver can discover the location of the SMST in its entry point and then cache it in + some driver global variable so that the SMST can be invoked in subsequent handlers. + + @param[in] This The EFI_SMM_BASE2_PROTOCOL instance. + @param[in,out] Smst On return, points to a pointer to the System Management Service Table (SMST). + + @retval EFI_SUCCESS The operation was successful. + @retval EFI_INVALID_PARAMETER Smst was invalid. + @retval EFI_UNSUPPORTED Not in SMM. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_GET_SMST_LOCATION2)( + IN CONST EFI_SMM_BASE2_PROTOCOL *This, + IN OUT EFI_SMM_SYSTEM_TABLE2 **Smst + ) +; + +/// +/// EFI SMM Base2 Protocol is utilized by all SMM drivers to locate the SMM infrastructure +/// services and determine whether the driver is being invoked inside SMRAM or outside of SMRAM. +/// +struct _EFI_SMM_BASE2_PROTOCOL { + EFI_SMM_INSIDE_OUT2 InSmm; + EFI_SMM_GET_SMST_LOCATION2 GetSmstLocation; +}; + +extern EFI_GUID gEfiSmmBase2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCommunication.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCommunication.h new file mode 100644 index 0000000000..13b0d29e4b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCommunication.h @@ -0,0 +1,27 @@ +/** @file + EFI SMM Communication Protocol as defined in the PI 1.2 specification. + + This protocol provides a means of communicating between drivers outside of SMM and SMI + handlers inside of SMM. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_COMMUNICATION_H_ +#define _SMM_COMMUNICATION_H_ + +#include + + +typedef EFI_MM_COMMUNICATE_HEADER EFI_SMM_COMMUNICATE_HEADER; + +#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID EFI_MM_COMMUNICATION_PROTOCOL_GUID + +typedef EFI_MM_COMMUNICATION_PROTOCOL EFI_SMM_COMMUNICATION_PROTOCOL; + +extern EFI_GUID gEfiSmmCommunicationProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmConfiguration.h new file mode 100644 index 0000000000..af6d380947 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmConfiguration.h @@ -0,0 +1,78 @@ +/** @file + EFI SMM Configuration Protocol as defined in the PI 1.2 specification. + + This protocol is used to: + 1) report the portions of SMRAM regions which cannot be used for the SMRAM heap. + 2) register the SMM Foundation entry point with the processor code. The entry + point will be invoked by the SMM processor entry code. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_CONFIGURATION_H_ +#define _SMM_CONFIGURATION_H_ + +#include +#include + +#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID EFI_MM_CONFIGURATION_PROTOCOL_GUID + +/// +/// Structure describing a SMRAM region which cannot be used for the SMRAM heap. +/// +typedef struct _EFI_SMM_RESERVED_SMRAM_REGION { + /// + /// Starting address of the reserved SMRAM area, as it appears while SMRAM is open. + /// Ignored if SmramReservedSize is 0. + /// + EFI_PHYSICAL_ADDRESS SmramReservedStart; + /// + /// Number of bytes occupied by the reserved SMRAM area. A size of zero indicates the + /// last SMRAM area. + /// + UINT64 SmramReservedSize; +} EFI_SMM_RESERVED_SMRAM_REGION; + +typedef struct _EFI_SMM_CONFIGURATION_PROTOCOL EFI_SMM_CONFIGURATION_PROTOCOL; + +/** + Register the SMM Foundation entry point. + + This function registers the SMM Foundation entry point with the processor code. This entry point + will be invoked by the SMM Processor entry code. + + @param[in] This The EFI_SMM_CONFIGURATION_PROTOCOL instance. + @param[in] SmmEntryPoint SMM Foundation entry point. + + @retval EFI_SUCCESS Success to register SMM Entry Point. + @retval EFI_INVALID_PARAMETER SmmEntryPoint is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_REGISTER_SMM_ENTRY)( + IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This, + IN EFI_SMM_ENTRY_POINT SmmEntryPoint + ); + +/// +/// The EFI SMM Configuration Protocol is a mandatory protocol published by a DXE CPU driver to +/// indicate which areas within SMRAM are reserved for use by the CPU for any purpose, +/// such as stack, save state or SMM entry point. +/// +/// The RegisterSmmEntry() function allows the SMM IPL DXE driver to register the SMM +/// Foundation entry point with the SMM entry vector code. +/// +struct _EFI_SMM_CONFIGURATION_PROTOCOL { + /// + /// A pointer to an array SMRAM ranges used by the initial SMM entry code. + /// + EFI_SMM_RESERVED_SMRAM_REGION *SmramReservedRegions; + EFI_SMM_REGISTER_SMM_ENTRY RegisterSmmEntry; +}; + +extern EFI_GUID gEfiSmmConfigurationProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmControl2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmControl2.h new file mode 100644 index 0000000000..d75efeed42 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmControl2.h @@ -0,0 +1,35 @@ +/** @file + EFI SMM Control2 Protocol as defined in the PI 1.2 specification. + + This protocol is used initiate synchronous SMI activations. This protocol could be published by a + processor driver to abstract the SMI IPI or a driver which abstracts the ASIC that is supporting the + APM port. Because of the possibility of performing SMI IPI transactions, the ability to generate this + event from a platform chipset agent is an optional capability for both IA-32 and x64-based systems. + + The EFI_SMM_CONTROL2_PROTOCOL is produced by a runtime driver. It provides an + abstraction of the platform hardware that generates an SMI. There are often I/O ports that, when + accessed, will generate the SMI. Also, the hardware optionally supports the periodic generation of + these signals. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_CONTROL2_H_ +#define _SMM_CONTROL2_H_ + +#include + +#define EFI_SMM_CONTROL2_PROTOCOL_GUID EFI_MM_CONTROL_PROTOCOL_GUID + +typedef EFI_MM_CONTROL_PROTOCOL EFI_SMM_CONTROL2_PROTOCOL; +typedef EFI_MM_PERIOD EFI_SMM_PERIOD; + +typedef EFI_MM_ACTIVATE EFI_SMM_ACTIVATE2; + +typedef EFI_MM_DEACTIVATE EFI_SMM_DEACTIVATE2; +extern EFI_GUID gEfiSmmControl2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpu.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpu.h new file mode 100644 index 0000000000..62144fd55f --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpu.h @@ -0,0 +1,130 @@ +/** @file + EFI SMM CPU Protocol as defined in the PI 1.2 specification. + + This protocol allows SMM drivers to access architecture-standard registers from any of the CPU + save state areas. In some cases, difference processors provide the same information in the save state, + but not in the same format. These so-called pseudo-registers provide this information in a standard + format. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_CPU_H_ +#define _SMM_CPU_H_ + +#include + +#define EFI_SMM_CPU_PROTOCOL_GUID EFI_MM_CPU_PROTOCOL_GUID + +#define EFI_SMM_SAVE_STATE_REGISTER_GDTBASE EFI_MM_SAVE_STATE_REGISTER_GDTBASE +#define EFI_SMM_SAVE_STATE_REGISTER_IDTBASE EFI_MM_SAVE_STATE_REGISTER_IDTBASE +#define EFI_SMM_SAVE_STATE_REGISTER_LDTBASE EFI_MM_SAVE_STATE_REGISTER_LDTBASE +#define EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT +#define EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT +#define EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT +#define EFI_SMM_SAVE_STATE_REGISTER_LDTINFO EFI_MM_SAVE_STATE_REGISTER_LDTINFO +#define EFI_SMM_SAVE_STATE_REGISTER_ES EFI_MM_SAVE_STATE_REGISTER_ES +#define EFI_SMM_SAVE_STATE_REGISTER_CS EFI_MM_SAVE_STATE_REGISTER_CS +#define EFI_SMM_SAVE_STATE_REGISTER_SS EFI_MM_SAVE_STATE_REGISTER_SS +#define EFI_SMM_SAVE_STATE_REGISTER_DS EFI_MM_SAVE_STATE_REGISTER_DS +#define EFI_SMM_SAVE_STATE_REGISTER_FS EFI_MM_SAVE_STATE_REGISTER_FS +#define EFI_SMM_SAVE_STATE_REGISTER_GS EFI_MM_SAVE_STATE_REGISTER_GS +#define EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL +#define EFI_SMM_SAVE_STATE_REGISTER_TR_SEL EFI_MM_SAVE_STATE_REGISTER_TR_SEL +#define EFI_SMM_SAVE_STATE_REGISTER_DR7 EFI_MM_SAVE_STATE_REGISTER_DR7 +#define EFI_SMM_SAVE_STATE_REGISTER_DR6 EFI_MM_SAVE_STATE_REGISTER_DR6 +#define EFI_SMM_SAVE_STATE_REGISTER_R8 EFI_MM_SAVE_STATE_REGISTER_R8 +#define EFI_SMM_SAVE_STATE_REGISTER_R9 EFI_MM_SAVE_STATE_REGISTER_R9 +#define EFI_SMM_SAVE_STATE_REGISTER_R10 EFI_MM_SAVE_STATE_REGISTER_R10 +#define EFI_SMM_SAVE_STATE_REGISTER_R11 EFI_MM_SAVE_STATE_REGISTER_R11 +#define EFI_SMM_SAVE_STATE_REGISTER_R12 EFI_MM_SAVE_STATE_REGISTER_R12 +#define EFI_SMM_SAVE_STATE_REGISTER_R13 EFI_MM_SAVE_STATE_REGISTER_R13 +#define EFI_SMM_SAVE_STATE_REGISTER_R14 EFI_MM_SAVE_STATE_REGISTER_R14 +#define EFI_SMM_SAVE_STATE_REGISTER_R15 EFI_MM_SAVE_STATE_REGISTER_R15 +#define EFI_SMM_SAVE_STATE_REGISTER_RAX EFI_MM_SAVE_STATE_REGISTER_RAX +#define EFI_SMM_SAVE_STATE_REGISTER_RBX EFI_MM_SAVE_STATE_REGISTER_RBX +#define EFI_SMM_SAVE_STATE_REGISTER_RCX EFI_MM_SAVE_STATE_REGISTER_RCX +#define EFI_SMM_SAVE_STATE_REGISTER_RDX EFI_MM_SAVE_STATE_REGISTER_RDX +#define EFI_SMM_SAVE_STATE_REGISTER_RSP EFI_MM_SAVE_STATE_REGISTER_RSP +#define EFI_SMM_SAVE_STATE_REGISTER_RBP EFI_MM_SAVE_STATE_REGISTER_RBP +#define EFI_SMM_SAVE_STATE_REGISTER_RSI EFI_MM_SAVE_STATE_REGISTER_RSI +#define EFI_SMM_SAVE_STATE_REGISTER_RDI EFI_MM_SAVE_STATE_REGISTER_RDI +#define EFI_SMM_SAVE_STATE_REGISTER_RIP EFI_MM_SAVE_STATE_REGISTER_RIP +#define EFI_SMM_SAVE_STATE_REGISTER_RFLAGS EFI_MM_SAVE_STATE_REGISTER_RFLAGS +#define EFI_SMM_SAVE_STATE_REGISTER_CR0 EFI_MM_SAVE_STATE_REGISTER_CR0 +#define EFI_SMM_SAVE_STATE_REGISTER_CR3 EFI_MM_SAVE_STATE_REGISTER_CR3 +#define EFI_SMM_SAVE_STATE_REGISTER_CR4 EFI_MM_SAVE_STATE_REGISTER_CR4 +#define EFI_SMM_SAVE_STATE_REGISTER_FCW EFI_MM_SAVE_STATE_REGISTER_FCW +#define EFI_SMM_SAVE_STATE_REGISTER_FSW EFI_MM_SAVE_STATE_REGISTER_FSW +#define EFI_SMM_SAVE_STATE_REGISTER_FTW EFI_MM_SAVE_STATE_REGISTER_FTW +#define EFI_SMM_SAVE_STATE_REGISTER_OPCODE EFI_MM_SAVE_STATE_REGISTER_OPCODE +#define EFI_SMM_SAVE_STATE_REGISTER_FP_EIP EFI_MM_SAVE_STATE_REGISTER_FP_EIP +#define EFI_SMM_SAVE_STATE_REGISTER_FP_CS EFI_MM_SAVE_STATE_REGISTER_FP_CS +#define EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET +#define EFI_SMM_SAVE_STATE_REGISTER_FP_DS EFI_MM_SAVE_STATE_REGISTER_FP_DS +#define EFI_SMM_SAVE_STATE_REGISTER_MM0 EFI_MM_SAVE_STATE_REGISTER_MM0 +#define EFI_SMM_SAVE_STATE_REGISTER_MM1 EFI_MM_SAVE_STATE_REGISTER_MM1 +#define EFI_SMM_SAVE_STATE_REGISTER_MM2 EFI_MM_SAVE_STATE_REGISTER_MM2 +#define EFI_SMM_SAVE_STATE_REGISTER_MM3 EFI_MM_SAVE_STATE_REGISTER_MM3 +#define EFI_SMM_SAVE_STATE_REGISTER_MM4 EFI_MM_SAVE_STATE_REGISTER_MM4 +#define EFI_SMM_SAVE_STATE_REGISTER_MM5 EFI_MM_SAVE_STATE_REGISTER_MM5 +#define EFI_SMM_SAVE_STATE_REGISTER_MM6 EFI_MM_SAVE_STATE_REGISTER_MM6 +#define EFI_SMM_SAVE_STATE_REGISTER_MM7 EFI_MM_SAVE_STATE_REGISTER_MM7 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM0 EFI_MM_SAVE_STATE_REGISTER_XMM0 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM1 EFI_MM_SAVE_STATE_REGISTER_XMM1 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM2 EFI_MM_SAVE_STATE_REGISTER_XMM2 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM3 EFI_MM_SAVE_STATE_REGISTER_XMM3 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM4 EFI_MM_SAVE_STATE_REGISTER_XMM4 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM5 EFI_MM_SAVE_STATE_REGISTER_XMM5 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM6 EFI_MM_SAVE_STATE_REGISTER_XMM6 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM7 EFI_MM_SAVE_STATE_REGISTER_XMM7 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM8 EFI_MM_SAVE_STATE_REGISTER_XMM8 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM9 EFI_MM_SAVE_STATE_REGISTER_XMM9 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM10 EFI_MM_SAVE_STATE_REGISTER_XMM10 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM11 EFI_MM_SAVE_STATE_REGISTER_XMM11 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM12 EFI_MM_SAVE_STATE_REGISTER_XMM12 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM13 EFI_MM_SAVE_STATE_REGISTER_XMM13 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM14 EFI_MM_SAVE_STATE_REGISTER_XMM14 +#define EFI_SMM_SAVE_STATE_REGISTER_XMM15 EFI_MM_SAVE_STATE_REGISTER_XMM15 +#define EFI_SMM_SAVE_STATE_REGISTER_IO EFI_MM_SAVE_STATE_REGISTER_IO +#define EFI_SMM_SAVE_STATE_REGISTER_LMA EFI_MM_SAVE_STATE_REGISTER_LMA +#define EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID + +typedef EFI_MM_SAVE_STATE_REGISTER EFI_SMM_SAVE_STATE_REGISTER; + + +#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT +#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT + + +/// +/// Size width of I/O instruction +/// +#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 +#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 +#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 +#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 +typedef EFI_MM_SAVE_STATE_IO_WIDTH EFI_SMM_SAVE_STATE_IO_WIDTH; + +/// +/// Types of I/O instruction +/// +#define EFI_SMM_SAVE_STATE_IO_TYPE_INPUT EFI_MM_SAVE_STATE_IO_TYPE_INPUT +#define EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT +#define EFI_SMM_SAVE_STATE_IO_TYPE_STRING EFI_MM_SAVE_STATE_IO_TYPE_STRING +#define EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX +typedef EFI_MM_SAVE_STATE_IO_TYPE EFI_SMM_SAVE_STATE_IO_TYPE; + +typedef EFI_MM_SAVE_STATE_IO_INFO EFI_SMM_SAVE_STATE_IO_INFO; + +typedef EFI_MM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL; + +typedef EFI_MM_READ_SAVE_STATE EFI_SMM_READ_SAVE_STATE; + +typedef EFI_MM_WRITE_SAVE_STATE EFI_SMM_WRITE_SAVE_STATE; +extern EFI_GUID gEfiSmmCpuProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpuIo2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpuIo2.h new file mode 100644 index 0000000000..b9d12bca74 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmCpuIo2.h @@ -0,0 +1,35 @@ +/** @file + SMM CPU I/O 2 protocol as defined in the PI 1.2 specification. + + This protocol provides CPU I/O and memory access within SMM. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_CPU_IO2_H_ +#define _SMM_CPU_IO2_H_ + +#include + +#define EFI_SMM_CPU_IO2_PROTOCOL_GUID EFI_MM_CPU_IO_PROTOCOL_GUID + +typedef EFI_MM_CPU_IO_PROTOCOL EFI_SMM_CPU_IO2_PROTOCOL; + +/// +/// Width of the SMM CPU I/O operations +/// +#define SMM_IO_UINT8 MM_IO_UINT8 +#define SMM_IO_UINT16 MM_IO_UINT16 +#define SMM_IO_UINT32 MM_IO_UINT32 +#define SMM_IO_UINT64 MM_IO_UINT64 + +typedef EFI_MM_IO_WIDTH EFI_SMM_IO_WIDTH; +typedef EFI_MM_CPU_IO EFI_SMM_CPU_IO2; + +typedef EFI_MM_IO_ACCESS EFI_SMM_IO_ACCESS2; + +extern EFI_GUID gEfiSmmCpuIo2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmEndOfDxe.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmEndOfDxe.h new file mode 100644 index 0000000000..aa693ef3eb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmEndOfDxe.h @@ -0,0 +1,26 @@ +/** @file + SMM End Of Dxe protocol introduced in the PI 1.2.1 specification. + + According to PI 1.4a specification, this protocol indicates end of the + execution phase when all of the components are under the authority of + the platform manufacturer. + This protocol is a mandatory protocol published by SMM Foundation code. + This protocol is an SMM counterpart of the End of DXE Event. + This protocol prorogates End of DXE notification into SMM environment. + This protocol is installed prior to installation of the SMM Ready to Lock Protocol. + + Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_END_OF_DXE_H_ +#define _SMM_END_OF_DXE_H_ + +#include + +#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID EFI_MM_END_OF_DXE_PROTOCOL_GUID + +extern EFI_GUID gEfiSmmEndOfDxeProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmGpiDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmGpiDispatch2.h new file mode 100644 index 0000000000..2faec309f1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmGpiDispatch2.h @@ -0,0 +1,43 @@ +/** @file + SMM General Purpose Input (GPI) Dispatch2 Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides the parent dispatch service for the General Purpose Input + (GPI) SMI source generator. + + The EFI_SMM_GPI_DISPATCH2_PROTOCOL provides the ability to install child handlers for the + given event types. Several inputs can be enabled. This purpose of this interface is to generate an + SMI in response to any of these inputs having a true value provided. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_GPI_DISPATCH2_H_ +#define _SMM_GPI_DISPATCH2_H_ + +#include +#include + +#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID EFI_MM_GPI_DISPATCH_PROTOCOL_GUID +/// +/// The dispatch function's context. +/// +typedef EFI_MM_GPI_REGISTER_CONTEXT EFI_SMM_GPI_REGISTER_CONTEXT; + +typedef EFI_MM_GPI_REGISTER EFI_SMM_GPI_REGISTER2; + +typedef EFI_MM_GPI_UNREGISTER EFI_SMM_GPI_UNREGISTER2; + +typedef EFI_MM_GPI_DISPATCH_PROTOCOL EFI_SMM_GPI_DISPATCH2_PROTOCOL; + + + +extern EFI_GUID gEfiSmmGpiDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h new file mode 100644 index 0000000000..a4aea7c657 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h @@ -0,0 +1,47 @@ +/** @file + SMM IO Trap Dispatch2 Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides a parent dispatch service for IO trap SMI sources. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_IO_TRAP_DISPATCH2_H_ +#define _SMM_IO_TRAP_DISPATCH2_H_ + +#include + +#define EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL_GUID EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID + +/// +/// IO Trap valid types +/// +typedef EFI_MM_IO_TRAP_DISPATCH_TYPE EFI_SMM_IO_TRAP_DISPATCH_TYPE; + +/// +/// IO Trap context structure containing information about the +/// IO trap event that should invoke the handler +/// +typedef EFI_MM_IO_TRAP_REGISTER_CONTEXT EFI_SMM_IO_TRAP_REGISTER_CONTEXT; + +/// +/// IO Trap context structure containing information about the IO trap that occurred +/// +typedef EFI_MM_IO_TRAP_CONTEXT EFI_SMM_IO_TRAP_CONTEXT; + +typedef EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL; + +typedef EFI_MM_IO_TRAP_DISPATCH_REGISTER EFI_SMM_IO_TRAP_DISPATCH2_REGISTER; + +typedef EFI_MM_IO_TRAP_DISPATCH_UNREGISTER EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER; + +extern EFI_GUID gEfiSmmIoTrapDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h new file mode 100644 index 0000000000..02109f8fd1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h @@ -0,0 +1,28 @@ +/** @file + SMM PCI Root Bridge IO protocol as defined in the PI 1.2 specification. + + This protocol provides PCI I/O and memory access within SMM. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_PCI_ROOT_BRIDGE_IO_H_ +#define _SMM_PCI_ROOT_BRIDGE_IO_H_ + +#include + +#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID + +/// +/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the +/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return +/// EFI_UNSUPPORTED. +/// +typedef EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL; + +extern EFI_GUID gEfiSmmPciRootBridgeIoProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h new file mode 100644 index 0000000000..a82ef42761 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h @@ -0,0 +1,156 @@ +/** @file + SMM Periodic Timer Dispatch Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides the parent dispatch service for the periodical timer SMI source generator. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_PERIODIC_TIMER_DISPATCH2_H_ +#define _SMM_PERIODIC_TIMER_DISPATCH2_H_ + +#include +#include + +#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID + +/// +/// Example: A chipset supports periodic SMIs on every 64ms or 2 seconds. +/// A child wishes schedule a period SMI to fire on a period of 3 seconds, there +/// are several ways to approach the problem: +/// 1. The child may accept a 4 second periodic rate, in which case it registers with +/// Period = 40000 +/// SmiTickInterval = 20000 +/// The resulting SMI will occur every 2 seconds with the child called back on +/// every 2nd SMI. +/// NOTE: the same result would occur if the child set SmiTickInterval = 0. +/// 2. The child may choose the finer granularity SMI (64ms): +/// Period = 30000 +/// SmiTickInterval = 640 +/// The resulting SMI will occur every 64ms with the child called back on +/// every 47th SMI. +/// NOTE: the child driver should be aware that this will result in more +/// SMIs occuring during system runtime which can negatively impact system +/// performance. +/// +typedef struct { + /// + /// The minimum period of time in 100 nanosecond units that the child gets called. The + /// child will be called back after a time greater than the time Period. + /// + UINT64 Period; + /// + /// The period of time interval between SMIs. Children of this interface should use this + /// field when registering for periodic timer intervals when a finer granularity periodic + /// SMI is desired. + /// + UINT64 SmiTickInterval; +} EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT; + +/// +/// The DispatchFunction will be called with Context set to the same value as was passed into +/// Register() in RegisterContext and with CommBuffer pointing to an instance of +/// EFI_SMM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size. +/// +typedef EFI_MM_PERIODIC_TIMER_CONTEXT EFI_SMM_PERIODIC_TIMER_CONTEXT; + +typedef struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL; + +/** + Register a child SMI source dispatch function for SMM periodic timer. + + This service registers a function (DispatchFunction) which will be called when at least the + amount of time specified by RegisterContext has elapsed. On return, DispatchHandle + contains a unique handle which may be used later to unregister the function using UnRegister(). + The DispatchFunction will be called with Context set to the same value as was passed into + this function in RegisterContext and with CommBuffer pointing to an instance of + EFI_SMM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size. + + @param[in] This Pointer to the EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when at least the specified amount + of time has elapsed. + @param[in] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the period at which the dispatch function + should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to track the function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The period input value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM) to manage this child. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_PERIODIC_TIMER_REGISTER2)( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN CONST EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregisters a periodic timer service. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called when the time has elapsed. + + @param[in] This Pointer to the EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL instance. + @param[in] DispatchHandle Handle of the service to remove. + + @retval EFI_SUCCESS The service has been successfully removed. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_PERIODIC_TIMER_UNREGISTER2)( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Returns the next SMI tick period supported by the chipset. + + The order returned is from longest to shortest interval period. + + @param[in] This Pointer to the EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL instance. + @param[in,out] SmiTickInterval Pointer to pointer of next shorter SMI interval + period supported by the child. This parameter works as a get-first, + get-next field.The first time this function is called, *SmiTickInterval + should be set to NULL to get the longest SMI interval.The returned + *SmiTickInterval should be passed in on subsequent calls to get the + next shorter interval period until *SmiTickInterval = NULL. + + @retval EFI_SUCCESS The service returned successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_PERIODIC_TIMER_INTERVAL2)( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval + ); + +/// +/// Interface structure for the SMM Periodic Timer Dispatch Protocol +/// +/// This protocol provides the parent dispatch service for the periodical timer SMI source generator. +/// +struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL { + EFI_SMM_PERIODIC_TIMER_REGISTER2 Register; + EFI_SMM_PERIODIC_TIMER_UNREGISTER2 UnRegister; + EFI_SMM_PERIODIC_TIMER_INTERVAL2 GetNextShorterInterval; +}; + +extern EFI_GUID gEfiSmmPeriodicTimerDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h new file mode 100644 index 0000000000..5fe84b00f2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h @@ -0,0 +1,36 @@ +/** @file + SMM Power Button Dispatch2 Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides the parent dispatch service for the power button SMI source generator. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_POWER_BUTTON_DISPATCH2_H_ +#define _SMM_POWER_BUTTON_DISPATCH2_H_ + +#include + +#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID + +/// +/// The dispatch function's context. +/// +typedef EFI_MM_POWER_BUTTON_REGISTER_CONTEXT EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT; + +typedef EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL; + +typedef EFI_MM_POWER_BUTTON_REGISTER EFI_SMM_POWER_BUTTON_REGISTER2; + +typedef EFI_MM_POWER_BUTTON_UNREGISTER EFI_SMM_POWER_BUTTON_UNREGISTER2; + +extern EFI_GUID gEfiSmmPowerButtonDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReadyToLock.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReadyToLock.h new file mode 100644 index 0000000000..f2661397c3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReadyToLock.h @@ -0,0 +1,28 @@ +/** @file + SMM Ready To Lock protocol introduced in the PI 1.2 specification. + + According to PI 1.4a specification, this SMM protocol indicates that + SMM resources and services that should not be used by the third party + code are about to be locked. + This protocol is a mandatory protocol published by the SMM Foundation + code when the system is preparing to lock certain resources and interfaces + in anticipation of the invocation of 3rd party extensible modules. + This protocol is an SMM counterpart of the DXE SMM Ready to Lock Protocol. + This protocol prorogates resource locking notification into SMM environment. + This protocol is installed after installation of the SMM End of DXE Protocol. + + Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_READY_TO_LOCK_H_ +#define _SMM_READY_TO_LOCK_H_ + +#include + +#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_MM_READY_TO_LOCK_PROTOCOL_GUID + +extern EFI_GUID gEfiSmmReadyToLockProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h new file mode 100644 index 0000000000..008d8c9bc8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h @@ -0,0 +1,29 @@ +/** @file + This protocol provides registering and unregistering services to status code consumers while in DXE SMM. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in PI Specification 1.1. + +**/ + +#ifndef __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ +#define __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ + +#include + +#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID EFI_MM_RSC_HANDLER_PROTOCOL_GUID + +typedef EFI_MM_RSC_HANDLER_CALLBACK EFI_SMM_RSC_HANDLER_CALLBACK; + +typedef EFI_MM_RSC_HANDLER_REGISTER EFI_SMM_RSC_HANDLER_REGISTER; + +typedef EFI_MM_RSC_HANDLER_UNREGISTER EFI_SMM_RSC_HANDLER_UNREGISTER; + +typedef EFI_MM_RSC_HANDLER_PROTOCOL EFI_SMM_RSC_HANDLER_PROTOCOL; + +extern EFI_GUID gEfiSmmRscHandlerProtocolGuid; + +#endif // __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h new file mode 100644 index 0000000000..dfe9305fc2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h @@ -0,0 +1,36 @@ +/** @file + SMM Standby Button Dispatch2 Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides the parent dispatch service for the standby button SMI source generator. + + Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_STANDBY_BUTTON_DISPATCH2_H_ +#define _SMM_STANDBY_BUTTON_DISPATCH2_H_ + +#include + +#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID + +/// +/// The dispatch function's context. +/// +typedef EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT; + +typedef EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL; + +typedef EFI_MM_STANDBY_BUTTON_REGISTER EFI_SMM_STANDBY_BUTTON_REGISTER2; + +typedef EFI_MM_STANDBY_BUTTON_UNREGISTER EFI_SMM_STANDBY_BUTTON_UNREGISTER2; + +extern EFI_GUID gEfiSmmStandbyButtonDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStatusCode.h new file mode 100644 index 0000000000..da396cc115 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmStatusCode.h @@ -0,0 +1,25 @@ +/** @file + EFI SMM Status Code Protocol as defined in the PI 1.2 specification. + + This protocol provides the basic status code services while in SMM. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_STATUS_CODE_H__ +#define _SMM_STATUS_CODE_H__ + +#include + +#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID EFI_MM_STATUS_CODE_PROTOCOL_GUID + +typedef EFI_MM_STATUS_CODE_PROTOCOL EFI_SMM_STATUS_CODE_PROTOCOL; + +typedef EFI_MM_REPORT_STATUS_CODE EFI_SMM_REPORT_STATUS_CODE; + +extern EFI_GUID gEfiSmmStatusCodeProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSwDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSwDispatch2.h new file mode 100644 index 0000000000..95e7db4048 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSwDispatch2.h @@ -0,0 +1,128 @@ +/** @file + SMM Software Dispatch Protocol introduced from PI 1.2 Specification + Volume 4 System Management Mode Core Interface. + + This protocol provides the parent dispatch service for a given SMI source generator. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_SW_DISPATCH2_H_ +#define _SMM_SW_DISPATCH2_H_ + +#include +#include + +#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID EFI_MM_SW_DISPATCH_PROTOCOL_GUID + +/// +/// A particular chipset may not support all possible software SMI input values. +/// For example, the ICH supports only values 00h to 0FFh. The parent only allows a single +/// child registration for each SwSmiInputValue. +/// +typedef struct { + UINTN SwSmiInputValue; +} EFI_SMM_SW_REGISTER_CONTEXT; + +/// +/// The DispatchFunction will be called with Context set to the same value as was passed into +/// this function in RegisterContext and with CommBuffer (and CommBufferSize) pointing +/// to an instance of EFI_SMM_SW_CONTEXT indicating the index of the CPU which generated the +/// software SMI. +/// +typedef struct { + /// + /// The 0-based index of the CPU which generated the software SMI. + /// + UINTN SwSmiCpuIndex; + /// + /// This value corresponds directly to the CommandPort parameter used in the call to Trigger(). + /// + UINT8 CommandPort; + /// + /// This value corresponds directly to the DataPort parameter used in the call to Trigger(). + /// + UINT8 DataPort; +} EFI_SMM_SW_CONTEXT; + +typedef struct _EFI_SMM_SW_DISPATCH2_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL; + +/** + Register a child SMI source dispatch function for the specified software SMI. + + This service registers a function (DispatchFunction) which will be called when the software + SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return, + DispatchHandle contains a unique handle which may be used later to unregister the function + using UnRegister(). + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance. + @param[in] DispatchFunction Function to register for handler when the specified software + SMI is generated. + @param[in, out] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function which Software SMI input value the + dispatch function should be invoked for. + @param[out] DispatchHandle Handle generated by the dispatcher to track the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the SMI source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI input value + is not within a valid range or is already in use. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM) to manage this + child. + @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not be assigned + for this dispatch. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_SW_REGISTER2)( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN OUT EFI_SMM_SW_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function for the specified software SMI. + + This service removes the handler associated with DispatchHandle so that it will no longer be + called in response to a software SMI. + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully unregistered. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_SW_UNREGISTER2)( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle +); + +/// +/// Interface structure for the SMM Software SMI Dispatch Protocol. +/// +/// The EFI_SMM_SW_DISPATCH2_PROTOCOL provides the ability to install child handlers for the +/// given software. These handlers will respond to software interrupts, and the maximum software +/// interrupt in the EFI_SMM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue. +/// +struct _EFI_SMM_SW_DISPATCH2_PROTOCOL { + EFI_SMM_SW_REGISTER2 Register; + EFI_SMM_SW_UNREGISTER2 UnRegister; + /// + /// A read-only field that describes the maximum value that can be used in the + /// EFI_SMM_SW_DISPATCH2_PROTOCOL.Register() service. + /// + UINTN MaximumSwiValue; +}; + +extern EFI_GUID gEfiSmmSwDispatch2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSxDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSxDispatch2.h new file mode 100644 index 0000000000..d4e3020bd1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmSxDispatch2.h @@ -0,0 +1,32 @@ +/** @file + SMM Sx Dispatch Protocol as defined in PI 1.2 Specification + Volume 4 System Management Mode Core Interface. + + Provides the parent dispatch service for a given Sx-state source generator. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMM_SX_DISPATCH2_H_ +#define _SMM_SX_DISPATCH2_H_ + +#include + +#define EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID EFI_MM_SX_DISPATCH_PROTOCOL_GUID + +/// +/// The dispatch function's context +/// +typedef EFI_MM_SX_REGISTER_CONTEXT EFI_SMM_SX_REGISTER_CONTEXT; + +typedef EFI_MM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL; + +typedef EFI_MM_SX_REGISTER EFI_SMM_SX_REGISTER2; + +typedef EFI_MM_SX_UNREGISTER EFI_SMM_SX_UNREGISTER2; + +extern EFI_GUID gEfiSmmSxDispatch2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmUsbDispatch2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmUsbDispatch2.h new file mode 100644 index 0000000000..8ac127a8bb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SmmUsbDispatch2.h @@ -0,0 +1,41 @@ +/** @file + SMM USB Dispatch2 Protocol as defined in PI 1.1 Specification + Volume 4 System Management Mode Core Interface. + + Provides the parent dispatch service for the USB SMI source generator. + + Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.1. + +**/ + +#ifndef _SMM_USB_DISPATCH2_H_ +#define _SMM_USB_DISPATCH2_H_ + +#include + +#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID EFI_MM_USB_DISPATCH_PROTOCOL_GUID + +/// +/// USB SMI event types +/// +typedef EFI_USB_MMI_TYPE EFI_USB_SMI_TYPE; + +/// +/// The dispatch function's context. +/// +typedef EFI_MM_USB_REGISTER_CONTEXT EFI_SMM_USB_REGISTER_CONTEXT; + +typedef EFI_MM_USB_DISPATCH_PROTOCOL EFI_SMM_USB_DISPATCH2_PROTOCOL; + +typedef EFI_MM_USB_REGISTER EFI_SMM_USB_REGISTER2; + +typedef EFI_MM_USB_UNREGISTER EFI_SMM_USB_UNREGISTER2; + +extern EFI_GUID gEfiSmmUsbDispatch2ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiConfiguration.h new file mode 100644 index 0000000000..c09784b735 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiConfiguration.h @@ -0,0 +1,287 @@ +/** @file + This file defines the SPI Configuration Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_CONFIGURATION_PROTOCOL_H__ +#define __SPI_CONFIGURATION_PROTOCOL_H__ + +/// +/// Global ID for the SPI Configuration Protocol +/// +#define EFI_SPI_CONFIGURATION_GUID \ + { 0x85a6d3e6, 0xb65b, 0x4afc, \ + { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }} + +/// +/// Macros to easily specify frequencies in hertz, kilohertz and megahertz. +/// +#define Hz(Frequency) (Frequency) +#define KHz(Frequency) (1000 * Hz (Frequency)) +#define MHz(Frequency) (1000 * KHz (Frequency)) + +typedef struct _EFI_SPI_PERIPHERAL EFI_SPI_PERIPHERAL; + +/** + Manipulate the chip select for a SPI device. + + This routine must be called at or below TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. + The SPI bus layer calls this routine either in the board layer or in the SPI + controller to manipulate the chip select pin at the start and end of a SPI + transaction. + + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operation. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set successfully + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The SpiPeripheral->ChipSelectParameter value + is invalid + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_CHIP_SELECT) ( + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine must be called at or below TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The clock + generator will choose a supported clock frequency + which is less then or equal to this value. + Specify zero to turn the clock generator off. + The actual clock frequency supported by the clock + generator will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by CLockHz + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_CLOCK) ( + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/// +/// The EFI_SPI_PART data structure provides a description of a SPI part which +/// is independent of the use on the board. This data is available directly +/// from the part's datasheet and may be provided by the vendor. +/// +typedef struct _EFI_SPI_PART { + /// + /// A Unicode string specifying the SPI chip vendor. + /// + CONST CHAR16 *Vendor; + + /// + /// A Unicode string specifying the SPI chip part number. + /// + CONST CHAR16 *PartNumber; + + /// + /// The minimum SPI bus clock frequency used to access this chip. This value + /// may be specified in the chip's datasheet. If not, use the value of zero. + /// + UINT32 MinClockHz; + + /// + /// The maximum SPI bus clock frequency used to access this chip. This value + /// is found in the chip's datasheet. + /// + UINT32 MaxClockHz; + + /// + /// Specify the polarity of the chip select pin. This value can be found in + /// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select + ///and FALSE when a zero asserts the chip select. + /// + BOOLEAN ChipSelectPolarity; +} EFI_SPI_PART; + +/// +/// The EFI_SPI_BUS data structure provides the connection details between the +/// physical SPI bus and the EFI_SPI_HC_PROTOCOL instance which controls that +/// SPI bus. This data structure also describes the details of how the clock is +/// generated for that SPI bus. Finally this data structure provides the list +/// of physical SPI devices which are attached to the SPI bus. +/// +typedef struct _EFI_SPI_BUS { + /// + /// A Unicode string describing the SPI bus + /// + CONST CHAR16 *FriendlyName; + + /// + /// Address of the first EFI_SPI_PERIPHERAL data structure connected to this + /// bus. Specify NULL if there are no SPI peripherals connected to this bus. + /// + CONST EFI_SPI_PERIPHERAL *Peripherallist; + + /// + /// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely + /// describes the SPI controller. + /// + CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath; + + /// + /// Address of the routine which controls the clock used by the SPI bus for + /// this SPI peripheral. The SPI host co ntroller's clock routine is called + /// when this value is set to NULL. + /// + EFI_SPI_CLOCK Clock; + + /// + /// Address of a data structure containing the additional values which + /// describe the necessary control for the clock. When Clock is NULL, + /// the declaration for this data structure is provided by the vendor of the + /// host's SPI controller driver. When Clock is not NULL, the declaration for + /// this data structure is provided by the board layer. + /// + VOID *ClockParameter; +} EFI_SPI_BUS; + +/// +/// The EFI_SPI_PERIPHERAL data structure describes how a specific block of +/// logic which is connected to the SPI bus. This data structure also selects +/// which upper level driver is used to manipulate this SPI device. +/// The SpiPeripheraLDriverGuid is available from the vendor of the SPI +/// peripheral driver. +/// +struct _EFI_SPI_PERIPHERAL { + /// + /// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if + /// the current data structure is the last one on the SPI bus. + /// + CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral; + + /// + /// A unicode string describing the function of the SPI part. + /// + CONST CHAR16 *FriendlyName; + + /// + /// Address of a GUID provided by the vendor of the SPI peripheral driver. + /// Instead of using a " EFI_SPI_IO_PROTOCOL" GUID, the SPI bus driver uses + /// this GUID to identify an EFI_SPI_IO_PROTOCOL data structure and to + /// provide the connection points for the SPI peripheral drivers. + /// This reduces the comparison logic in the SPI peripheral driver's + /// Supported routine. + /// + CONST GUID *SpiPeripheralDriverGuid; + + /// + /// The address of an EFI_SPI_PART data structure which describes this chip. + /// + CONST EFI_SPI_PART *SpiPart; + + /// + /// The maximum clock frequency is specified in the EFI_SPI_P ART. When this + /// this value is non-zero and less than the value in the EFI_SPI_PART then + /// this value is used for the maximum clock frequency for the SPI part. + /// + UINT32 MaxClockHz; + + /// + /// Specify the idle value of the clock as found in the datasheet. + /// Use zero (0) if the clock'S idle value is low or one (1) if the the + /// clock's idle value is high. + /// + BOOLEAN ClockPolarity; + + /// + /// Specify the clock delay after chip select. Specify zero (0) to delay an + /// entire clock cycle or one (1) to delay only half a clock cycle. + /// + BOOLEAN ClockPhase; + + /// + /// SPI peripheral attributes, select zero or more of: + /// * SPI_PART_SUPPORTS_2_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to + /// support a 2-bit data bus + /// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to + /// support a 4-bit data bus + /// + UINT32 Attributes; + + /// + /// Address of a vendor specific data structure containing additional board + /// configuration details related to the SPI chip. The SPI peripheral layer + /// uses this data structure when configuring the chip. + /// + CONST VOID *ConfigurationData; + + /// + /// The address of an EFI_SPI_BUS data structure which describes the SPI bus + /// to which this chip is connected. + /// + CONST EFI_SPI_BUS *SpiBus; + + /// + /// Address of the routine which controls the chip select pin for this SPI + /// peripheral. Call the SPI host controller's chip select routine when this + /// value is set to NULL. + /// + EFI_SPI_CHIP_SELECT ChipSelect; + + /// + /// Address of a data structure containing the additional values which + /// describe the necessary control for the chip select. When ChipSelect is + /// NULL, the declaration for this data structure is provided by the vendor + /// of the host's SPI controller driver. The vendor's documentation specifies + /// the necessary values to use for the chip select pin selection and + /// control. When Chipselect is not NULL, the declaration for this data + /// structure is provided by the board layer. + /// + VOID *ChipSelectParameter; +}; + +/// +/// Describe the details of the board's SPI busses to the SPI driver stack. +/// The board layer uses the EFI_SPI_CONFIGURATION_PROTOCOL to expose the data +/// tables which describe the board's SPI busses, The SPI bus layer uses these +/// tables to configure the clock, chip select and manage the SPI transactions +/// on the SPI controllers. +/// +typedef struct _EFI_SPI_CONFIGURATION_PROTOCOL { + /// + /// The number of SPI busses on the board. + /// + UINT32 BusCount; + + /// + /// The address of an array of EFI_SPI_BUS data structure addresses. + /// + CONST EFI_SPI_BUS *CONST *CONST Buslist; +} EFI_SPI_CONFIGURATION_PROTOCOL; + +extern EFI_GUID gEfiSpiConfigurationProtocolGuid; + +#endif // __SPI_CONFIGURATION_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiHc.h new file mode 100644 index 0000000000..f875bc706b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiHc.h @@ -0,0 +1,188 @@ +/** @file + This file defines the SPI Host Controller Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_HC_PROTOCOL_H__ +#define __SPI_HC_PROTOCOL_H__ + +#include +#include + +/// +/// Global ID for the SPI Host Controller Protocol +/// +#define EFI_SPI_HOST_GUID \ + { 0xc74e5db2, 0xfa96, 0x4ae2, \ + { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }} + +/// +/// EDK2-style name +/// +#define EFI_SPI_HC_PROTOCOL_GUID EFI_SPI_HOST_GUID + +typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL; + +/** + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSeLect value or its contents are + invalid + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ); + +/** + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ); + +/** + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ); + +/// +/// Support a SPI data transaction between the SPI controller and a SPI chip. +/// +struct _EFI_SPI_HC_PROTOCOL { + /// + /// Host control attributes, may have zero or more of the following set: + /// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS + /// * HC_SUPPORTS_READ_ONLY_OPERATIONS + /// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS + /// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS + /// - The SPI host controller requires the transmit frame to be in most + /// significant bits instead of least significant bits.The host driver + /// will adjust the frames if necessary. + /// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS + /// - The SPI host controller places the receive frame to be in most + /// significant bits instead of least significant bits.The host driver + /// will adjust the frames to be in the least significant bits if + /// necessary. + /// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH + /// - The SPI controller supports a 2 - bit data bus + /// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH + /// - The SPI controller supports a 4 - bit data bus + /// * HC_TRANSFER_SIZE_INCLUDES_OPCODE + /// - Transfer size includes the opcode byte + /// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS + /// - Transfer size includes the 3 address bytes + /// The SPI host controller must support full - duplex (receive while + /// sending) operation.The SPI host controller must support a 1 - bit bus + /// width. + /// + UINT32 Attributes; + + /// + /// Mask of frame sizes which the SPI host controller supports. Frame size of + /// N-bits is supported when bit N-1 is set. The host controller must support + /// a frame size of 8-bits. + /// + UINT32 FrameSizeSupportMask; + + /// + /// Maximum transfer size in bytes: 1 - Oxffffffff + /// + UINT32 MaximumTransferBytes; + + /// + /// Assert or deassert the SPI chip select. + /// + EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect; + + /// + /// Set up the clock generator to produce the correct clock frequency, phase + /// and polarity for a SPI chip. + /// + EFI_SPI_HC_PROTOCOL_CLOCK Clock; + + /// + /// Perform the SPI transaction on the SPI peripheral using the SPI host + /// controller. + /// + EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction; +}; + +extern EFI_GUID gEfiSpiHcProtocolGuid; + +#endif // __SPI_HC_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiIo.h new file mode 100644 index 0000000000..449707e098 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiIo.h @@ -0,0 +1,286 @@ +/** @file + This file defines the SPI I/O Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_IO_PROTOCOL_H__ +#define __SPI_IO_PROTOCOL_H__ + +#include +#include + +typedef struct _EFI_SPI_IO_PROTOCOL EFI_SPI_IO_PROTOCOL; + +/// +/// Note: The UEFI PI 1.6 specification does not specify values for the +/// members below. The order matches the specification. +/// +typedef enum { + /// + /// Data flowing in both direction between the host and + /// SPI peripheral.ReadBytes must equal WriteBytes and both ReadBuffer and + /// WriteBuffer must be provided. + /// + SPI_TRANSACTION_FULL_DUPLEX, + + /// + /// Data flowing from the host to the SPI peripheral.ReadBytes must be + /// zero.WriteBytes must be non - zero and WriteBuffer must be provided. + /// + SPI_TRANSACTION_WRITE_ONLY, + + /// + /// Data flowing from the SPI peripheral to the host.WriteBytes must be + /// zero.ReadBytes must be non - zero and ReadBuffer must be provided. + /// + SPI_TRANSACTION_READ_ONLY, + + /// + /// Data first flowing from the host to the SPI peripheral and then data + /// flows from the SPI peripheral to the host.These types of operations get + /// used for SPI flash devices when control data (opcode, address) must be + /// passed to the SPI peripheral to specify the data to be read. + /// + SPI_TRANSACTION_WRITE_THEN_READ +} EFI_SPI_TRANSACTION_TYPE; + +/** + Initiate a SPI transaction between the host and a SPI peripheral. + + This routine must be called at or below TPL_NOTIFY. + This routine works with the SPI bus layer to pass the SPI transaction to the + SPI controller for execution on the SPI bus. There are four types of + supported transactions supported by this routine: + * Full Duplex: WriteBuffer and ReadBuffer are the same size. + * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0 + * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0 + * Write Then Read: WriteBuffer contains control data to write to SPI + peripheral before data is placed into the ReadBuffer. + Both WriteBytes and ReadBytes must be non-zero. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] TransactionType Type of SPI transaction. + @param[in] DebugTransaction Set TRUE only when debugging is desired. + Debugging may be turned on for a single SPI + transaction. Only this transaction will display + debugging messages. All other transactions with + this value set to FALSE will not display any + debugging messages. + @param[in] ClockHz Specify the ClockHz value as zero (0) to use + the maximum clock frequency supported by the + SPI controller and part. Specify a non-zero + value only when a specific SPI transaction + requires a reduced clock rate. + @param[in] BusWidth Width of the SPI bus in bits: 1, 2, 4 + @param[in] FrameSize Frame size in bits, range: 1 - 32 + @param[in] WriteBytes The length of the WriteBuffer in bytes. + Specify zero for read-only operations. + @param[in] WriteBuffer The buffer containing data to be sent from the + host to the SPI chip. Specify NULL for read + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The transmit frame is in the least + significant N bits. + @param[in] ReadBytes The length of the ReadBuffer in bytes. + Specify zero for write-only operations. + @param[out] ReadBuffer The buffer to receeive data from the SPI chip + during the transaction. Specify NULL for write + only operations. + * Frame sizes 1-8 bits: UINT8 (one byte) per + frame + * Frame sizes 7-16 bits: UINT16 (two bytes) per + frame + * Frame sizes 17-32 bits: UINT32 (four bytes) + per frame The received frame is in the least + significant N bits. + + @retval EFI_SUCCESS The SPI transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The writeBytes value was invalid + @retval EFI_BAD_BUFFER_SIZE The ReadBytes value was invalid + @retval EFI_INVALID_PARAMETER TransactionType is not valid, + or BusWidth not supported by SPI peripheral or + SPI host controller, + or WriteBytes non-zero and WriteBuffer is + NULL, + or ReadBytes non-zero and ReadBuffer is NULL, + or ReadBuffer != WriteBuffer for full-duplex + type, + or WriteBuffer was NULL, + or TPL is too high + @retval EFI_OUT_OF_RESOURCES Insufficient memory for SPI transaction + @retval EFI_UNSUPPORTED The FrameSize is not supported by the SPI bus + layer or the SPI host controller + @retval EFI_UNSUPPORTED The SPI controller was not able to support + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN EFI_SPI_TRANSACTION_TYPE TransactionType, + IN BOOLEAN DebugTransaction, + IN UINT32 ClockHz OPTIONAL, + IN UINT32 BusWidth, + IN UINT32 FrameSize, + IN UINT32 WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT32 ReadBytes, + OUT UINT8 *ReadBuffer + ); + +/** + Update the SPI peripheral associated with this SPI 10 instance. + + Support socketed SPI parts by allowing the SPI peripheral driver to replace + the SPI peripheral after the connection is made. An example use is socketed + SPI NOR flash parts, where the size and parameters change depending upon + device is in the socket. + + @param[in] This Pointer to an EFI_SPI_IO_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to an EFI_SPI_PERIPHERAL structure. + + @retval EFI_SUCCESS The SPI peripheral was updated successfully + @retval EFI_INVALID_PARAMETER The SpiPeripheral value is NULL, + or the SpiPeripheral->SpiBus is NULL, + or the SpiP eripheral - >SpiBus pointing at + wrong bus, + or the SpiP eripheral - >SpiPart is NULL + +**/ +typedef EFI_STATUS +(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) ( + IN CONST EFI_SPI_IO_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral + ); + +/// +/// The EFI_SPI_BUS_ TRANSACTION data structure contains the description of the +/// SPI transaction to perform on the host controller. +/// +typedef struct _EFI_SPI_BUS_TRANSACTION { + /// + /// Pointer to the SPI peripheral being manipulated. + /// + CONST EFI_SPI_PERIPHERAL *SpiPeripheral; + + /// + /// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE + /// values. + /// + EFI_SPI_TRANSACTION_TYPE TransactionType; + + /// + /// TRUE if the transaction is being debugged. Debugging may be turned on for + /// a single SPI transaction. Only this transaction will display debugging + /// messages. All other transactions with this value set to FALSE will not + /// display any debugging messages. + /// + BOOLEAN DebugTransaction; + + /// + /// SPI bus width in bits: 1, 2, 4 + /// + UINT32 BusWidth; + + /// + /// Frame size in bits, range: 1 - 32 + /// + UINT32 FrameSize; + + /// + /// Length of the write buffer in bytes + /// + UINT32 WriteBytes; + + /// + /// Buffer containing data to send to the SPI peripheral + /// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame + /// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame + /// + UINT8 *WriteBuffer; + + /// + /// Length of the read buffer in bytes + /// + UINT32 ReadBytes; + + /// + /// Buffer to receive the data from the SPI peripheral + /// * Frame sizes 1 - 8 bits: UINT8 (one byte) per frame + /// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame + /// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame + /// + UINT8 *ReadBuffer; +} EFI_SPI_BUS_TRANSACTION; + +/// +/// Support managed SPI data transactions between the SPI controller and a SPI +/// chip. +/// +struct _EFI_SPI_IO_PROTOCOL { + /// + /// Address of an EFI_SPI_PERIPHERAL data structure associated with this + /// protocol instance. + /// + CONST EFI_SPI_PERIPHERAL *SpiPeripheral; + + /// + /// Address of the original EFI_SPI_PERIPHERAL data structure associated with + /// this protocol instance. + /// + CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral; + + /// + /// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits + /// is supported when bit N-1 is set. The host controller must support a + /// frame size of 8-bits. Frame sizes of 16, 24 and 32-bits are converted to + /// 8-bit frame sizes by the SPI bus layer if the frame size is not supported + /// by the SPI host controller. + /// + UINT32 FrameSizeSupportMask; + + /// + /// Maximum transfer size in bytes: 1 - Oxffffffff + /// + UINT32 MaximumTransferBytes; + + /// + /// Transaction attributes: One or more from: + /// * SPI_10_SUPPORTS_2_B1T_DATA_BUS_W1DTH + /// - The SPI host and peripheral supports a 2-bit data bus + /// * SPI_IO_SUPPORTS_4_BIT_DATA_BUS_W1DTH + /// - The SPI host and peripheral supports a 4-bit data bus + /// * SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE + /// - Transfer size includes the opcode byte + /// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS + /// - Transfer size includes the 3 address bytes + /// + UINT32 Attributes; + + /// + /// Pointer to legacy SPI controller protocol + /// + CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol; + + /// + /// Initiate a SPI transaction between the host and a SPI peripheral. + /// + EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction; + + /// + /// Update the SPI peripheral associated with this SPI 10 instance. + /// + EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral; +}; + +#endif // __SPI_IO_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiNorFlash.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiNorFlash.h new file mode 100644 index 0000000000..0c9dca79e6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiNorFlash.h @@ -0,0 +1,256 @@ +/** @file + This file defines the SPI NOR Flash Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_NOR_FLASH_PROTOCOL_H__ +#define __SPI_NOR_FLASH_PROTOCOL_H__ + +#include + +/// +/// Global ID for the SPI NOR Flash Protocol +/// +#define EFI_SPI_NOR_FLASH_PROTOCOL_GUID \ + { 0xb57ec3fe, 0xf833, 0x4ba6, \ + { 0x85, 0x78, 0x2a, 0x7d, 0x6a, 0x87, 0x44, 0x4b }} + +typedef struct _EFI_SPI_NOR_FLASH_PROTOCOL EFI_SPI_NOR_FLASH_PROTOCOL; + +/** + Read the 3 byte manufacture and device ID from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the 3 byte manufacture and device ID from the flash part + filling the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure. + @param[out] Buffer Pointer to a 3 byte buffer to receive the manufacture and + device ID. + + + + @retval EFI_SUCCESS The manufacture and device ID was read + successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL + @retval EFI_DEVICE_ERROR Invalid data received from SPI flash part. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + OUT UINT8 *Buffer + ); + +/** + Read data from the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine reads data from the SPI part in the buffer provided. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start reading + @param[in] LengthInBytes Read length in bytes + @param[out] Buffer Address of a buffer to receive the data + + @retval EFI_SUCCESS The data was read successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + OUT UINT8 *Buffer + ); + +/** + Read the flash status register. + + This routine must be called at or below TPL_NOTIFY. + This routine reads the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to read. + @param[out] FlashStatus Pointer to a buffer to receive the flash status. + + @retval EFI_SUCCESS The status register was read successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + OUT UINT8 *FlashStatus + ); + +/** + Write the flash status register. + + This routine must be called at or below TPL_N OTIFY. + This routine writes the flash part status register. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] LengthInBytes Number of status bytes to write. + @param[in] FlashStatus Pointer to a buffer containing the new status. + + @retval EFI_SUCCESS The status write was successful. + @retval EFI_OUT_OF_RESOURCES Failed to allocate the write buffer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 LengthInBytes, + IN UINT8 *FlashStatus + ); + +/** + Write data to the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine breaks up the write operation as necessary to write the data to + the SPI part. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address in the flash to start writing + @param[in] LengthInBytes Write length in bytes + @param[in] Buffer Address of a buffer containing the data + + @retval EFI_SUCCESS The data was written successfully. + @retval EFI_INVALID_PARAMETER Buffer is NULL, or + FlashAddress >= This->FlashSize, or + LengthInBytes > This->FlashSize - FlashAddress + @retval EFI_OUT_OF_RESOURCES Insufficient memory to copy buffer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 LengthInBytes, + IN UINT8 *Buffer + ); + +/** + Efficiently erases one or more 4KiB regions in the SPI flash. + + This routine must be called at or below TPL_NOTIFY. + This routine uses a combination of 4 KiB and larger blocks to erase the + specified area. + + @param[in] This Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data + structure. + @param[in] FlashAddress Address within a 4 KiB block to start erasing + @param[in] BlockCount Number of 4 KiB blocks to erase + + @retval EFI_SUCCESS The erase was completed successfully. + @retval EFI_INVALID_PARAMETER FlashAddress >= This->FlashSize, or + BlockCount * 4 KiB + > This->FlashSize - FlashAddress + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE) ( + IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This, + IN UINT32 FlashAddress, + IN UINT32 BlockCount + ); + +/// +/// The EFI_SPI_NOR_FLASH_PROTOCOL exists in the SPI peripheral layer. +/// This protocol manipulates the SPI NOR flash parts using a common set of +/// commands. The board layer provides the interconnection and configuration +/// details for the SPI NOR flash part. The SPI NOR flash driver uses this +/// configuration data to expose a generic interface which provides the +/// following APls: +/// * Read manufacture and device ID +/// * Read data +/// * Read data using low frequency +/// * Read status +/// * Write data +/// * Erase 4 KiB blocks +/// * Erase 32 or 64 KiB blocks +/// * Write status +/// The EFI_SPI_NOR_FLASH_PROTOCOL also exposes some APls to set the security +/// features on the legacy SPI flash controller. +/// +struct _EFI_SPI_NOR_FLASH_PROTOCOL { + /// + /// Pointer to an EFI_SPI_PERIPHERAL data structure + /// + CONST EFI_SPI_PERIPHERAL *SpiPeripheral; + + /// + /// Flash size in bytes + /// + UINT32 FlashSize; + + /// + /// Manufacture and Device ID + /// + UINT8 Deviceid[3]; + + /// + /// Erase block size in bytes + /// + UINT32 EraseBlockBytes; + + /// + /// Read the 3 byte manufacture and device ID from the SPI flash. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashid; + + /// + /// Read data from the SPI flash. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA ReadData; + + /// + /// Low frequency read data from the SPI flash. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA LfReadData; + + /// + /// Read the flash status register. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS ReadStatus; + + /// + /// Write the flash status register. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus; + + /// + /// Write data to the SPI flash. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA WriteData; + + /// + /// Efficiently erases one or more 4KiB regions in the SPI flash. + /// + EFI_SPI_NOR_FLASH_PROTOCOL_ERASE Erase; +}; + +extern EFI_GUID gEfiSpiNorFlashProtocolGuid; + +#endif // __SPI_NOR_FLASH_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmConfiguration.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmConfiguration.h new file mode 100644 index 0000000000..8bb713c80e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmConfiguration.h @@ -0,0 +1,30 @@ +/** @file + This file defines the SPI SMM Configuration Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_SMM_CONFIGURATION_PROTOCOL_H__ +#define __SPI_SMM_CONFIGURATION_PROTOCOL_H__ + +#include + +/// +/// Global ID for the SPI SMM Configuration Protocol +/// +#define EFI_SPI_SMM_CONFIGURATION_PROTOCOL_GUID \ + { 0x995c6eca, 0x171b, 0x45fd, \ + { 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }} + +typedef +struct _EFI_SPI_CONFIGURATION_PROTOCOL +EFI_SPI_SMM_CONFIGURATION_PROTOCOL; + +extern EFI_GUID gEfiSpiSmmConfigurationProtocolGuid; + +#endif // __SPI_SMM_CONFIGURATION_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmHc.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmHc.h new file mode 100644 index 0000000000..fb7a259571 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmHc.h @@ -0,0 +1,30 @@ +/** @file + This file defines the SPI SMM Host Controller Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_SMM_HC_H__ +#define __SPI_SMM_HC_H__ + +#include + +/// +/// Global ID for the SPI SMM Host Controller Protocol +/// +#define EFI_SPI_SMM_HC_PROTOCOL_GUID \ + { 0xe9f02217, 0x2093, 0x4470, \ + { 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }} + +typedef +struct _EFI_SPI_HC_PROTOCOL +EFI_SPI_SMM_HC_PROTOCOL; + +extern EFI_GUID gEfiSpiSmmHcProtocolGuid; + +#endif // __SPI_SMM_HC_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmNorFlash.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmNorFlash.h new file mode 100644 index 0000000000..dfb61f359e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SpiSmmNorFlash.h @@ -0,0 +1,30 @@ +/** @file + This file defines the SPI SMM NOR Flash Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI PI Specification 1.6. + +**/ + +#ifndef __SPI_SMM_NOR_FLASH_PROTOCOL_H__ +#define __SPI_SMM_NOR_FLASH_PROTOCOL_H__ + +#include + +/// +/// Global ID for the SPI SMM NOR Flash Protocol +/// +#define EFI_SPI_SMM_NOR_FLASH_PROTOCOL_GUID \ + { 0xaab18f19, 0xfe14, 0x4666, \ + { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a } } + +typedef +struct _EFI_SPI_NOR_FLASH_PROTOCOL +EFI_SPI_SMM_NOR_FLASH_PROTOCOL; + +extern EFI_GUID gEfiSpiSmmNorFlashProtocolGuid; + +#endif // __SPI_SMM_NOR_FLASH_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StatusCode.h new file mode 100644 index 0000000000..90b1f63d3b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StatusCode.h @@ -0,0 +1,53 @@ +/** @file + Status code Runtime Protocol as defined in PI Specification 1.4a VOLUME 2 DXE + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __STATUS_CODE_RUNTIME_PROTOCOL_H__ +#define __STATUS_CODE_RUNTIME_PROTOCOL_H__ + +#define EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID \ +{ 0xd2b2b828, 0x826, 0x48a7, { 0xb3, 0xdf, 0x98, 0x3c, 0x0, 0x60, 0x24, 0xf0 } } + +/** + Provides an interface that a software module can call to report a status code. + + @param Type Indicates the type of status code being reported. + @param Value Describes the current status of a hardware or software entity. + This included information about the class and subclass that is used to + classify the entity as well as an operation. + @param Instance The enumeration of a hardware or software entity within + the system. Valid instance numbers start with 1. + @param CallerId This optional parameter may be used to identify the caller. + This parameter allows the status code driver to apply different rules to + different callers. + @param Data This optional parameter may be used to pass additional data. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_DEVICE_ERROR The function should not be completed due to a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REPORT_STATUS_CODE)( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN EFI_GUID *CallerId OPTIONAL, + IN EFI_STATUS_CODE_DATA *Data OPTIONAL + ); + +/// +/// Provides the service required to report a status code to the platform firmware. +/// This protocol must be produced by a runtime DXE driver. +/// +typedef struct _EFI_STATUS_CODE_PROTOCOL { + EFI_REPORT_STATUS_CODE ReportStatusCode; +} EFI_STATUS_CODE_PROTOCOL; + +extern EFI_GUID gEfiStatusCodeRuntimeProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StorageSecurityCommand.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StorageSecurityCommand.h new file mode 100644 index 0000000000..db38fb491e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/StorageSecurityCommand.h @@ -0,0 +1,206 @@ +/** @file + EFI Storage Security Command Protocol as defined in UEFI 2.3.1 specification. + This protocol is used to abstract mass storage devices to allow code running in + the EFI boot services environment to send security protocol commands to mass + storage devices without specific knowledge of the type of device or controller + that manages the device. + + Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __STORAGE_SECURITY_COMMAND_H__ +#define __STORAGE_SECURITY_COMMAND_H__ + +#define EFI_STORAGE_SECURITY_COMMAND_PROTOCOL_GUID \ + { \ + 0xC88B0B6D, 0x0DFC, 0x49A7, {0x9C, 0xB4, 0x49, 0x07, 0x4B, 0x4C, 0x3A, 0x78 } \ + } + +typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL EFI_STORAGE_SECURITY_COMMAND_PROTOCOL; + +/** + Send a security protocol command to a device that receives data and/or the result + of one or more commands sent by SendData. + + The ReceiveData function sends a security protocol command to the given MediaId. + The security protocol command sent is defined by SecurityProtocolId and contains + the security protocol specific data SecurityProtocolSpecificData. The function + returns the data from the security protocol command in PayloadBuffer. + + For devices supporting the SCSI command set, the security protocol command is sent + using the SECURITY PROTOCOL IN command defined in SPC-4. + + For devices supporting the ATA command set, the security protocol command is sent + using one of the TRUSTED RECEIVE commands defined in ATA8-ACS if PayloadBufferSize + is non-zero. + + If the PayloadBufferSize is zero, the security protocol command is sent using the + Trusted Non-Data command defined in ATA8-ACS. + + If PayloadBufferSize is too small to store the available data from the security + protocol command, the function shall copy PayloadBufferSize bytes into the + PayloadBuffer and return EFI_WARN_BUFFER_TOO_SMALL. + + If PayloadBuffer or PayloadTransferSize is NULL and PayloadBufferSize is non-zero, + the function shall return EFI_INVALID_PARAMETER. + + If the given MediaId does not support security protocol commands, the function shall + return EFI_UNSUPPORTED. If there is no media in the device, the function returns + EFI_NO_MEDIA. If the MediaId is not the ID for the current media in the device, + the function returns EFI_MEDIA_CHANGED. + + If the security protocol fails to complete within the Timeout period, the function + shall return EFI_TIMEOUT. + + If the security protocol command completes without an error, the function shall + return EFI_SUCCESS. If the security protocol command completes with an error, the + function shall return EFI_DEVICE_ERROR. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to receive data from. + @param Timeout The timeout, in 100ns units, to use for the execution + of the security protocol command. A Timeout value of 0 + means that this function will wait indefinitely for the + security protocol command to execute. If Timeout is greater + than zero, then this function will return EFI_TIMEOUT if the + time required to execute the receive data command is greater than Timeout. + @param SecurityProtocolId The value of the "Security Protocol" parameter of + the security protocol command to be sent. + @param SecurityProtocolSpecificData The value of the "Security Protocol Specific" parameter + of the security protocol command to be sent. + @param PayloadBufferSize Size in bytes of the payload data buffer. + @param PayloadBuffer A pointer to a destination buffer to store the security + protocol command specific payload data for the security + protocol command. The caller is responsible for having + either implicit or explicit ownership of the buffer. + @param PayloadTransferSize A pointer to a buffer to store the size in bytes of the + data written to the payload data buffer. + + @retval EFI_SUCCESS The security protocol command completed successfully. + @retval EFI_WARN_BUFFER_TOO_SMALL The PayloadBufferSize was too small to store the available + data from the device. The PayloadBuffer contains the truncated data. + @retval EFI_UNSUPPORTED The given MediaId does not support security protocol commands. + @retval EFI_DEVICE_ERROR The security protocol command completed with an error. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_INVALID_PARAMETER The PayloadBuffer or PayloadTransferSize is NULL and + PayloadBufferSize is non-zero. + @retval EFI_TIMEOUT A timeout occurred while waiting for the security + protocol command to execute. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_STORAGE_SECURITY_RECEIVE_DATA)( + IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Timeout, + IN UINT8 SecurityProtocolId, + IN UINT16 SecurityProtocolSpecificData, + IN UINTN PayloadBufferSize, + OUT VOID *PayloadBuffer, + OUT UINTN *PayloadTransferSize + ); + +/** + Send a security protocol command to a device. + + The SendData function sends a security protocol command containing the payload + PayloadBuffer to the given MediaId. The security protocol command sent is + defined by SecurityProtocolId and contains the security protocol specific data + SecurityProtocolSpecificData. If the underlying protocol command requires a + specific padding for the command payload, the SendData function shall add padding + bytes to the command payload to satisfy the padding requirements. + + For devices supporting the SCSI command set, the security protocol command is sent + using the SECURITY PROTOCOL OUT command defined in SPC-4. + + For devices supporting the ATA command set, the security protocol command is sent + using one of the TRUSTED SEND commands defined in ATA8-ACS if PayloadBufferSize + is non-zero. If the PayloadBufferSize is zero, the security protocol command is + sent using the Trusted Non-Data command defined in ATA8-ACS. + + If PayloadBuffer is NULL and PayloadBufferSize is non-zero, the function shall + return EFI_INVALID_PARAMETER. + + If the given MediaId does not support security protocol commands, the function + shall return EFI_UNSUPPORTED. If there is no media in the device, the function + returns EFI_NO_MEDIA. If the MediaId is not the ID for the current media in the + device, the function returns EFI_MEDIA_CHANGED. + + If the security protocol fails to complete within the Timeout period, the function + shall return EFI_TIMEOUT. + + If the security protocol command completes without an error, the function shall return + EFI_SUCCESS. If the security protocol command completes with an error, the function + shall return EFI_DEVICE_ERROR. + + @param This Indicates a pointer to the calling context. + @param MediaId ID of the medium to receive data from. + @param Timeout The timeout, in 100ns units, to use for the execution + of the security protocol command. A Timeout value of 0 + means that this function will wait indefinitely for the + security protocol command to execute. If Timeout is greater + than zero, then this function will return EFI_TIMEOUT if the + time required to execute the receive data command is greater than Timeout. + @param SecurityProtocolId The value of the "Security Protocol" parameter of + the security protocol command to be sent. + @param SecurityProtocolSpecificData The value of the "Security Protocol Specific" parameter + of the security protocol command to be sent. + @param PayloadBufferSize Size in bytes of the payload data buffer. + @param PayloadBuffer A pointer to a destination buffer to store the security + protocol command specific payload data for the security + protocol command. + + @retval EFI_SUCCESS The security protocol command completed successfully. + @retval EFI_UNSUPPORTED The given MediaId does not support security protocol commands. + @retval EFI_DEVICE_ERROR The security protocol command completed with an error. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_INVALID_PARAMETER The PayloadBuffer is NULL and PayloadBufferSize is non-zero. + @retval EFI_TIMEOUT A timeout occurred while waiting for the security + protocol command to execute. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA) ( + IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This, + IN UINT32 MediaId, + IN UINT64 Timeout, + IN UINT8 SecurityProtocolId, + IN UINT16 SecurityProtocolSpecificData, + IN UINTN PayloadBufferSize, + IN VOID *PayloadBuffer +); + +/// +/// The EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is used to send security protocol +/// commands to a mass storage device. Two types of security protocol commands +/// are supported. SendData sends a command with data to a device. ReceiveData +/// sends a command that receives data and/or the result of one or more commands +/// sent by SendData. +/// +/// The security protocol command formats supported shall be based on the definition +/// of the SECURITY PROTOCOL IN and SECURITY PROTOCOL OUT commands defined in SPC-4. +/// If the device uses the SCSI command set, no translation is needed in the firmware +/// and the firmware can package the parameters into a SECURITY PROTOCOL IN or SECURITY +/// PROTOCOL OUT command and send the command to the device. If the device uses a +/// non-SCSI command set, the firmware shall map the command and data payload to the +/// corresponding command and payload format defined in the non-SCSI command set +/// (for example, TRUSTED RECEIVE and TRUSTED SEND in ATA8-ACS). +/// +/// The firmware shall automatically add an EFI_STORAGE_SECURITY_COMMAND_PROTOCOL +/// for any storage devices detected during system boot that support SPC-4, ATA8-ACS +/// or their successors. +/// +struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL { + EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData; + EFI_STORAGE_SECURITY_SEND_DATA SendData; +}; + +extern EFI_GUID gEfiStorageSecurityCommandProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIo.h new file mode 100644 index 0000000000..fb5ea855c9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIo.h @@ -0,0 +1,169 @@ +/** @file + The Super I/O Protocol is installed by the Super I/O driver. The Super I/O driver is a UEFI driver + model compliant driver. In the Start() routine of the Super I/O driver, a handle with an instance + of EFI_SIO_PROTOCOL is created for each device within the Super I/O. The device within the + Super I/O is powered up, enabled, and assigned with the default set of resources. In the Stop() + routine of the Super I/O driver, the device is disabled and Super I/O protocol is uninstalled. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_SUPER_IO_PROTOCOL_H__ +#define __EFI_SUPER_IO_PROTOCOL_H__ +#include + +#define EFI_SIO_PROTOCOL_GUID \ + { 0x215fdd18, 0xbd50, 0x4feb, { 0x89, 0xb, 0x58, 0xca, 0xb, 0x47, 0x39, 0xe9 } } + +typedef union { + ACPI_SMALL_RESOURCE_HEADER *SmallHeader; + ACPI_LARGE_RESOURCE_HEADER *LargeHeader; +} ACPI_RESOURCE_HEADER_PTR; + +typedef struct { + UINT8 Register; ///< Register number. + UINT8 AndMask; ///< Bitwise AND mask. + UINT8 OrMask; ///< Bitwise OR mask. +} EFI_SIO_REGISTER_MODIFY; + +typedef struct _EFI_SIO_PROTOCOL EFI_SIO_PROTOCOL; + +/** + Provides a low level access to the registers for the Super I/O. + + @param[in] This Indicates a pointer to the calling context. + @param[in] Write Specifies the type of the register operation. If this parameter is TRUE, Value is + interpreted as an input parameter and the operation is a register write. If this parameter + is FALSE, Value is interpreted as an output parameter and the operation is a register + read. + @param[in] ExitCfgMode Exit Configuration Mode Indicator. If this parameter is set to TRUE, the Super I/O + driver will turn off configuration mode of the Super I/O prior to returning from this + function. If this parameter is set to FALSE, the Super I/O driver will leave Super I/O + in the configuration mode. + The Super I/O driver must track the current state of the Super I/O and enable the + configuration mode of Super I/O if necessary prior to register access. + @param[in] Register Register number. + @param[in, out] Value If Write is TRUE, Value is a pointer to the buffer containing the byte of data to be + written to the Super I/O register. If Write is FALSE, Value is a pointer to the + destination buffer for the byte of data to be read from the Super I/O register. + + @retval EFI_SUCCESS The operation completed successfully + @retval EFI_INVALID_PARAMETER The Value is NULL + @retval EFI_INVALID_PARAMETER Invalid Register number + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_REGISTER_ACCESS)( + IN CONST EFI_SIO_PROTOCOL *This, + IN BOOLEAN Write, + IN BOOLEAN ExitCfgMode, + IN UINT8 Register, + IN OUT UINT8 *Value +); + +/** + Provides an interface to get a list of the current resources consumed by the device in the ACPI + Resource Descriptor format. + + GetResources() returns a list of resources currently consumed by the device. The + ResourceList is a pointer to the buffer containing resource descriptors for the device. The + descriptors are in the format of Small or Large ACPI resource descriptor as defined by ACPI + specification (2.0 & 3.0). The buffer of resource descriptors is terminated with the 'End tag' + resource descriptor. + + @param[in] This Indicates a pointer to the calling context. + @param[out] ResourceList A pointer to an ACPI resource descriptor list that defines the current resources used by + the device. Type ACPI_RESOURCE_HEADER_PTR is defined in the "Related + Definitions" below. + + @retval EFI_SUCCESS The operation completed successfully + @retval EFI_INVALID_PARAMETER ResourceList is NULL + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_GET_RESOURCES)( + IN CONST EFI_SIO_PROTOCOL *This, + OUT ACPI_RESOURCE_HEADER_PTR *ResourceList +); + +/** + Sets the resources for the device. + + @param[in] This Indicates a pointer to the calling context. + @param[in] ResourceList Pointer to the ACPI resource descriptor list. Type ACPI_RESOURCE_HEADER_PTR + is defined in the "Related Definitions" section of + EFI_SIO_PROTOCOL.GetResources(). + + @retval EFI_SUCCESS The operation completed successfully + @retval EFI_INVALID_PARAMETER ResourceList is invalid + @retval EFI_ACCESS_DENIED Some of the resources in ResourceList are in use + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_SET_RESOURCES)( + IN CONST EFI_SIO_PROTOCOL *This, + IN ACPI_RESOURCE_HEADER_PTR ResourceList +); + +/** + Provides a collection of resource descriptor lists. Each resource descriptor list in the collection + defines a combination of resources that can potentially be used by the device. + + @param[in] This Indicates a pointer to the calling context. + @param[out] ResourceCollection Collection of the resource descriptor lists. + + @retval EFI_SUCCESS The operation completed successfully + @retval EFI_INVALID_PARAMETER ResourceCollection is NULL +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_POSSIBLE_RESOURCES)( + IN CONST EFI_SIO_PROTOCOL *This, + OUT ACPI_RESOURCE_HEADER_PTR *ResourceCollection +); + +/** + Provides an interface for a table based programming of the Super I/O registers. + + The Modify() function provides an interface for table based programming of the Super I/O + registers. This function can be used to perform programming of multiple Super I/O registers with a + single function call. For each table entry, the Register is read, its content is bitwise ANDed with + AndMask, and then ORed with OrMask before being written back to the Register. The Super + I/O driver must track the current state of the Super I/O and enable the configuration mode of Super I/ + O if necessary prior to table processing. Once the table is processed, the Super I/O device has to be + returned to the original state. + + @param[in] This Indicates a pointer to the calling context. + @param[in] Command A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY + structures. Each structure specifies a single Super I/O register modify operation. Type + EFI_SIO_REGISTER_MODIFY is defined in the "Related Definitions" below. + @param[in] NumberOfCommands Number of elements in the Command array. + + @retval EFI_SUCCESS The operation completed successfully + @retval EFI_INVALID_PARAMETER Command is NULL + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_MODIFY)( + IN CONST EFI_SIO_PROTOCOL *This, + IN CONST EFI_SIO_REGISTER_MODIFY *Command, + IN UINTN NumberOfCommands +); + +struct _EFI_SIO_PROTOCOL { + EFI_SIO_REGISTER_ACCESS RegisterAccess; + EFI_SIO_GET_RESOURCES GetResources; + EFI_SIO_SET_RESOURCES SetResources; + EFI_SIO_POSSIBLE_RESOURCES PossibleResources; + EFI_SIO_MODIFY Modify; +}; + +extern EFI_GUID gEfiSioProtocolGuid; + +#endif // __EFI_SUPER_IO_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIoControl.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIoControl.h new file mode 100644 index 0000000000..1f2f62345a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/SuperIoControl.h @@ -0,0 +1,86 @@ +/** @file + The Super I/O Control Protocol is installed by the Super I/O driver. It provides + the low-level services for SIO devices that enable them to be used in the UEFI + driver model. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This protocol is from PI Version 1.2.1. + +**/ + +#ifndef __EFI_SUPER_IO_CONTROL_PROTOCOL_H__ +#define __EFI_SUPER_IO_CONTROL_PROTOCOL_H__ + +#define EFI_SIO_CONTROL_PROTOCOL_GUID \ + { \ + 0xb91978df, 0x9fc1, 0x427d, { 0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27 } \ + } + +typedef struct _EFI_SIO_CONTROL_PROTOCOL EFI_SIO_CONTROL_PROTOCOL; +typedef struct _EFI_SIO_CONTROL_PROTOCOL *PEFI_SIO_CONTROL_PROTOCOL; + +/** + Enable an ISA-style device. + + This function enables a logical ISA device and, if necessary, configures it + to default settings, including memory, I/O, DMA and IRQ resources. + + @param This A pointer to this instance of the EFI_SIO_CONTROL_PROTOCOL. + + @retval EFI_SUCCESS The device is enabled successfully. + @retval EFI_OUT_OF_RESOURCES The device could not be enabled because there + were insufficient resources either for the device + itself or for the records needed to track the device. + @retval EFI_ALREADY_STARTED The device is already enabled. + @retval EFI_UNSUPPORTED The device cannot be enabled. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_CONTROL_ENABLE)( + IN CONST EFI_SIO_CONTROL_PROTOCOL *This + ); + +/** + Disable a logical ISA device. + + This function disables a logical ISA device so that it no longer consumes + system resources, such as memory, I/O, DMA and IRQ resources. Enough information + must be available so that subsequent Enable() calls would properly reconfigure + the device. + + @param This A pointer to this instance of the EFI_SIO_CONTROL_PROTOCOL. + + @retval EFI_SUCCESS The device is disabled successfully. + @retval EFI_OUT_OF_RESOURCES The device could not be disabled because there + were insufficient resources either for the device + itself or for the records needed to track the device. + @retval EFI_ALREADY_STARTED The device is already disabled. + @retval EFI_UNSUPPORTED The device cannot be disabled. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIO_CONTROL_DISABLE)( + IN CONST EFI_SIO_CONTROL_PROTOCOL *This + ); + +struct _EFI_SIO_CONTROL_PROTOCOL { + /// + /// The version of this protocol. + /// + UINT32 Version; + /// + /// Enable a device. + /// + EFI_SIO_CONTROL_ENABLE EnableDevice; + /// + /// Disable a device. + /// + EFI_SIO_CONTROL_DISABLE DisableDevice; +}; + +extern EFI_GUID gEfiSioControlProtocolGuid; + +#endif // __EFI_SUPER_IO_CONTROL_PROTOCOL_H__ diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Supplicant.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Supplicant.h new file mode 100644 index 0000000000..d7cfc2ad26 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Supplicant.h @@ -0,0 +1,458 @@ +/** @file + This file defines the EFI Supplicant Protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.6 + +**/ + +#ifndef __EFI_SUPPLICANT_PROTOCOL_H__ +#define __EFI_SUPPLICANT_PROTOCOL_H__ + +#include + +/// +/// The EFI Supplicant Service Binding Protocol is used to locate EFI +/// Supplicant Protocol drivers to create and destroy child of the driver to +/// communicate with other host using Supplicant protocol. +/// +#define EFI_SUPPLICANT_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x45bcd98e, 0x59ad, 0x4174, { 0x95, 0x46, 0x34, 0x4a, 0x7, 0x48, 0x58, 0x98 } \ + } + +/// +/// The EFI Supplicant protocol provides services to process authentication and +/// data encryption/decryption for security management. +/// +#define EFI_SUPPLICANT_PROTOCOL_GUID \ + { \ + 0x54fcc43e, 0xaa89, 0x4333, { 0x9a, 0x85, 0xcd, 0xea, 0x24, 0x5, 0x1e, 0x9e } \ + } + +typedef struct _EFI_SUPPLICANT_PROTOCOL EFI_SUPPLICANT_PROTOCOL; + +/// +/// EFI_SUPPLICANT_CRYPT_MODE +/// +typedef enum { + // + // Encrypt data provided in the fragment buffers. + // + EfiSupplicantEncrypt, + // + // Decrypt data provided in the fragment buffers. + // + EfiSupplicantDecrypt, +} EFI_SUPPLICANT_CRYPT_MODE; + +/// +/// EFI_SUPPLICANT_DATA_TYPE +/// +typedef enum { + // + // Session Configuration + // + + // + // Current authentication type in use. The corresponding Data is of type + // EFI_80211_AKM_SUITE_SELECTOR. + // + EfiSupplicant80211AKMSuite, + // + // Group data encryption type in use. The corresponding Data is of type + // EFI_SUPPLICANT_CIPHER_SUITE_SELECTOR. + // + EfiSupplicant80211GroupDataCipherSuite, + // + // Pairwise encryption type in use. The corresponding Data is of type + // EFI_80211_CIPHER_SUITE_SELECTOR. + // + EfiSupplicant80211PairwiseCipherSuite, + // + // PSK password. The corresponding Data is a NULL-terminated ASCII string. + // + EfiSupplicant80211PskPassword, + // + // Target SSID name. The corresponding Data is of type EFI_80211_SSID. + // + EfiSupplicant80211TargetSSIDName, + // + // Station MAC address. The corresponding Data is of type + // EFI_80211_MAC_ADDRESS. + // + EfiSupplicant80211StationMac, + // + // Target SSID MAC address. The corresponding Data is 6 bytes MAC address. + // + EfiSupplicant80211TargetSSIDMac, + + // + // Session Information + // + + // + // 802.11 PTK. The corresponding Data is of type EFI_SUPPLICANT_KEY. + // + EfiSupplicant80211PTK, + // + // 802.11 GTK. The corresponding Data is of type EFI_SUPPLICANT_GTK_LIST. + // + EfiSupplicant80211GTK, + // + // Supplicant state. The corresponding Data is + // EFI_EAPOL_SUPPLICANT_PAE_STATE. + // + EfiSupplicantState, + // + // 802.11 link state. The corresponding Data is EFI_80211_LINK_STATE. + // + EfiSupplicant80211LinkState, + // + // Flag indicates key is refreshed. The corresponding Data is + // EFI_SUPPLICANT_KEY_REFRESH. + // + EfiSupplicantKeyRefresh, + + // + // Session Configuration + // + + // + // Supported authentication types. The corresponding Data is of type + // EFI_80211_AKM_SUITE_SELECTOR. + // + EfiSupplicant80211SupportedAKMSuites, + // + // Supported software encryption types provided by supplicant driver. The + // corresponding Data is of type EFI_80211_CIPHER_SUITE_SELECTOR. + // + EfiSupplicant80211SupportedSoftwareCipherSuites, + // + // Supported hardware encryption types provided by wireless UNDI driver. The + // corresponding Data is of type EFI_80211_CIPHER_SUITE_SELECTOR. + // + EfiSupplicant80211SupportedHardwareCipherSuites, + + // + // Session Information + // + + // + // 802.11 Integrity GTK. The corresponding Data is of type + // EFI_SUPPLICANT_GTK_LIST. + // + EfiSupplicant80211IGTK, + // + // 802.11 PMK. The corresponding Data is 32 bytes pairwise master key. + // + EfiSupplicant80211PMK, + EfiSupplicantDataTypeMaximum +} EFI_SUPPLICANT_DATA_TYPE; + +/// +/// EFI_80211_LINK_STATE +/// +typedef enum { + // + // Indicates initial start state, unauthenticated, unassociated. + // + Ieee80211UnauthenticatedUnassociated, + // + // Indicates authenticated, unassociated. + // + Ieee80211AuthenticatedUnassociated, + // + // Indicates authenticated and associated, but pending RSN authentication. + // + Ieee80211PendingRSNAuthentication, + // + // Indicates authenticated and associated. + // + Ieee80211AuthenticatedAssociated +} EFI_80211_LINK_STATE; + +/// +/// EFI_SUPPLICANT_KEY_TYPE (IEEE Std 802.11 Section 6.3.19.1.2) +/// +typedef enum { + Group, + Pairwise, + PeerKey, + IGTK +} EFI_SUPPLICANT_KEY_TYPE; + +/// +/// EFI_SUPPLICANT_KEY_DIRECTION (IEEE Std 802.11 Section 6.3.19.1.2) +/// +typedef enum { + // + // Indicates that the keys are being installed for the receive direction. + // + Receive, + // + // Indicates that the keys are being installed for the transmit direction. + // + Transmit, + // + // Indicates that the keys are being installed for both the receive and + // transmit directions. + // + Both +} EFI_SUPPLICANT_KEY_DIRECTION; + +/// +/// EFI_SUPPLICANT_KEY_REFRESH +/// +typedef struct { + // + // If TRUE, indicates GTK is just refreshed after a successful call to + // EFI_SUPPLICANT_PROTOCOL.BuildResponsePacket(). + // + BOOLEAN GTKRefresh; +} EFI_SUPPLICANT_KEY_REFRESH; + +#define EFI_MAX_KEY_LEN 64 + +/// +/// EFI_SUPPLICANT_KEY +/// +typedef struct { + // + // The key value. + // + UINT8 Key[EFI_MAX_KEY_LEN]; + // + // Length in bytes of the Key. Should be up to EFI_MAX_KEY_LEN. + // + UINT8 KeyLen; + // + // The key identifier. + // + UINT8 KeyId; + // + // Defines whether this key is a group key, pairwise key, PeerKey, or + // Integrity Group. + // + EFI_SUPPLICANT_KEY_TYPE KeyType; + // + // The value is set according to the KeyType. + // + EFI_80211_MAC_ADDRESS Addr; + // + // The Receive Sequence Count value. + // + UINT8 Rsc[8]; + // + // Length in bytes of the Rsc. Should be up to 8. + // + UINT8 RscLen; + // + // Indicates whether the key is configured by the Authenticator or + // Supplicant. The value true indicates Authenticator. + // + BOOLEAN IsAuthenticator; + // + // The cipher suite required for this association. + // + EFI_80211_SUITE_SELECTOR CipherSuite; + // + // Indicates the direction for which the keys are to be installed. + // + EFI_SUPPLICANT_KEY_DIRECTION Direction; +} EFI_SUPPLICANT_KEY; + +/// +/// EFI_SUPPLICANT_GTK_LIST +/// +typedef struct { + // + // Indicates the number of GTKs that are contained in GTKList. + // + UINT8 GTKCount; + // + // A variable-length array of GTKs of type EFI_SUPPLICANT_KEY. The number of + // entries is specified by GTKCount. + // + EFI_SUPPLICANT_KEY GTKList[1]; +} EFI_SUPPLICANT_GTK_LIST; + +/// +/// EFI_SUPPLICANT_FRAGMENT_DATA +/// +typedef struct { + // + // Length of data buffer in the fragment. + // + UINT32 FragmentLength; + // + // Pointer to the data buffer in the fragment. + // + VOID *FragmentBuffer; +} EFI_SUPPLICANT_FRAGMENT_DATA; + +/** + BuildResponsePacket() is called during STA and AP authentication is in + progress. Supplicant derives the PTK or session keys depend on type of + authentication is being employed. + + @param[in] This Pointer to the EFI_SUPPLICANT_PROTOCOL + instance. + @param[in] RequestBuffer Pointer to the most recently received EAPOL + packet. NULL means the supplicant need + initiate the EAP authentication session and + send EAPOL-Start message. + @param[in] RequestBufferSize + Packet size in bytes for the most recently + received EAPOL packet. 0 is only valid when + RequestBuffer is NULL. + @param[out] Buffer Pointer to the buffer to hold the built + packet. + @param[in, out] BufferSize Pointer to the buffer size in bytes. On + input, it is the buffer size provided by the + caller. On output, it is the buffer size in + fact needed to contain the packet. + + @retval EFI_SUCCESS The required EAPOL packet is built + successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + RequestBuffer is NULL, but RequestSize is + NOT 0. + RequestBufferSize is 0. + Buffer is NULL, but RequestBuffer is NOT 0. + BufferSize is NULL. + @retval EFI_BUFFER_TOO_SMALL BufferSize is too small to hold the response + packet. + @retval EFI_NOT_READY Current EAPOL session state is NOT ready to + build ResponsePacket. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SUPPLICANT_BUILD_RESPONSE_PACKET) ( + IN EFI_SUPPLICANT_PROTOCOL *This, + IN UINT8 *RequestBuffer, OPTIONAL + IN UINTN RequestBufferSize, OPTIONAL + OUT UINT8 *Buffer, + IN OUT UINTN *BufferSize + ); + +/** + ProcessPacket() is called to Supplicant driver to encrypt or decrypt the data + depending type of authentication type. + + @param[in] This Pointer to the EFI_SUPPLICANT_PROTOCOL + instance. + @param[in, out] FragmentTable Pointer to a list of fragment. The caller + will take responsible to handle the original + FragmentTable while it may be reallocated in + Supplicant driver. + @param[in] FragmentCount Number of fragment. + @param[in] CryptMode Crypt mode. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + FragmentTable is NULL. + FragmentCount is NULL. + CryptMode is invalid. + @retval EFI_NOT_READY Current supplicant state is NOT Authenticated. + @retval EFI_ABORTED Something wrong decryption the message. + @retval EFI_UNSUPPORTED This API is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SUPPLICANT_PROCESS_PACKET) ( + IN EFI_SUPPLICANT_PROTOCOL *This, + IN OUT EFI_SUPPLICANT_FRAGMENT_DATA **FragmentTable, + IN UINT32 *FragmentCount, + IN EFI_SUPPLICANT_CRYPT_MODE CryptMode + ); + +/** + Set Supplicant configuration data. + + @param[in] This Pointer to the EFI_SUPPLICANT_PROTOCOL + instance. + @param[in] DataType The type of data. + @param[in] Data Pointer to the buffer to hold the data. + @param[in] DataSize Pointer to the buffer size in bytes. + + @retval EFI_SUCCESS The Supplicant configuration data is set + successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + Data is NULL. + DataSize is 0. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SUPPLICANT_SET_DATA) ( + IN EFI_SUPPLICANT_PROTOCOL *This, + IN EFI_SUPPLICANT_DATA_TYPE DataType, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get Supplicant configuration data. + + @param[in] This Pointer to the EFI_SUPPLICANT_PROTOCOL + instance. + @param[in] DataType The type of data. + @param[out] Data Pointer to the buffer to hold the data. + Ignored if DataSize is 0. + @param[in, out] DataSize Pointer to the buffer size in bytes. On + input, it is the buffer size provided by the + caller. On output, it is the buffer size in + fact needed to contain the packet. + + @retval EFI_SUCCESS The Supplicant configuration data is got + successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + This is NULL. + DataSize is NULL. + Data is NULL if *DataSize is not zero. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The Supplicant configuration data is not + found. + @retval EFI_BUFFER_TOO_SMALL The size of Data is too small for the + specified configuration data and the required + size is returned in DataSize. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SUPPLICANT_GET_DATA) ( + IN EFI_SUPPLICANT_PROTOCOL *This, + IN EFI_SUPPLICANT_DATA_TYPE DataType, + OUT UINT8 *Data, OPTIONAL + IN OUT UINTN *DataSize + ); + +/// +/// The EFI_SUPPLICANT_PROTOCOL is designed to provide unified place for WIFI +/// and EAP security management. Both PSK authentication and 802.1X EAP +/// authentication can be managed via this protocol and driver or application +/// as a consumer can only focus on about packet transmitting or receiving. +/// +struct _EFI_SUPPLICANT_PROTOCOL { + EFI_SUPPLICANT_BUILD_RESPONSE_PACKET BuildResponsePacket; + EFI_SUPPLICANT_PROCESS_PACKET ProcessPacket; + EFI_SUPPLICANT_SET_DATA SetData; + EFI_SUPPLICANT_GET_DATA GetData; +}; + +extern EFI_GUID gEfiSupplicantServiceBindingProtocolGuid; +extern EFI_GUID gEfiSupplicantProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TapeIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TapeIo.h new file mode 100644 index 0000000000..1eac48c2d7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TapeIo.h @@ -0,0 +1,231 @@ +/** @file + EFI_TAPE_IO_PROTOCOL as defined in the UEFI 2.0. + Provide services to control and access a tape device. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __EFI_TAPE_IO_PROTOCOL_H__ +#define __EFI_TAPE_IO_PROTOCOL_H__ + +#define EFI_TAPE_IO_PROTOCOL_GUID \ + { \ + 0x1e93e633, 0xd65a, 0x459e, {0xab, 0x84, 0x93, 0xd9, 0xec, 0x26, 0x6d, 0x18 } \ + } + +typedef struct _EFI_TAPE_IO_PROTOCOL EFI_TAPE_IO_PROTOCOL; + +typedef struct _EFI_TAPE_HEADER { + UINT64 Signature; + UINT32 Revision; + UINT32 BootDescSize; + UINT32 BootDescCRC; + EFI_GUID TapeGUID; + EFI_GUID TapeType; + EFI_GUID TapeUnique; + UINT32 BLLocation; + UINT32 BLBlocksize; + UINT32 BLFilesize; + CHAR8 OSVersion[40]; + CHAR8 AppVersion[40]; + CHAR8 CreationDate[10]; + CHAR8 CreationTime[10]; + CHAR8 SystemName[256]; // UTF-8 + CHAR8 TapeTitle[120]; // UTF-8 + CHAR8 pad[468]; // pad to 1024 +} EFI_TAPE_HEADER; + +/** + Reads from the tape. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + @param BufferSize The size of the buffer in bytes pointed to by Buffer. + @param Buffer The pointer to the buffer for data to be read into. + + @retval EFI_SUCCESS Data was successfully transferred from the media. + @retval EFI_END_OF_FILE A filemark was encountered which limited the data + transferred by the read operation or the head is positioned + just after a filemark. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY The transfer failed since the device was not ready (e.g. not + online). The transfer may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of transfer. + @retval EFI_TIMEOUT The transfer failed to complete within the timeout specified. + @retval EFI_MEDIA_CHANGED The media in the device was changed since the last access. + The transfer was aborted since the current position of the + media may be incorrect. + @retval EFI_INVALID_PARAMETER A NULL Buffer was specified with a non-zero + BufferSize, or the device is operating in fixed block + size mode and the BufferSize was not a multiple of + device's fixed block size + @retval EFI_DEVICE_ERROR A device error occurred while attempting to transfer data + from the media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_READ)( + IN EFI_TAPE_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Writes to the tape. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + @param BufferSize Size of the buffer in bytes pointed to by Buffer. + @param Buffer The pointer to the buffer for data to be written from. + + @retval EFI_SUCCESS Data was successfully transferred to the media. + @retval EFI_END_OF_MEDIA The logical end of media has been reached. Data may have + been successfully transferred to the media. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY The transfer failed since the device was not ready (e.g. not + online). The transfer may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of transfer. + @retval EFI_TIMEOUT The transfer failed to complete within the timeout specified. + @retval EFI_MEDIA_CHANGED The media in the device was changed since the last access. + The transfer was aborted since the current position of the + media may be incorrect. + @retval EFI_WRITE_PROTECTED The media in the device is write-protected. The transfer + was aborted since a write cannot be completed. + @retval EFI_INVALID_PARAMETER A NULL Buffer was specified with a non-zero + BufferSize, or the device is operating in fixed block + size mode and the BufferSize was not a multiple of + device's fixed block size + @retval EFI_DEVICE_ERROR A device error occurred while attempting to transfer data + from the media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_WRITE)( + IN EFI_TAPE_IO_PROTOCOL *This, + IN UINTN *BufferSize, + IN VOID *Buffer + ); + + +/** + Rewinds the tape. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + + @retval EFI_SUCCESS The media was successfully repositioned. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY Repositioning the media failed since the device was not + ready (e.g. not online). The transfer may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of media repositioning. + @retval EFI_TIMEOUT Repositioning of the media did not complete within the timeout specified. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reposition the media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_REWIND)( + IN EFI_TAPE_IO_PROTOCOL *This + ); + + +/** + Positions the tape. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + @param Direction Direction and number of data blocks or filemarks to space over on media. + @param Type Type of mark to space over on media. + The following Type marks are mandatory: + BLOCK type : 0 + FILEMARK type : 1 + + @retval EFI_SUCCESS The media was successfully repositioned. + @retval EFI_END_OF_MEDIA Beginning or end of media was reached before the + indicated number of data blocks or filemarks were found. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY The reposition failed since the device was not ready (e.g. not + online). The reposition may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of repositioning. + @retval EFI_TIMEOUT The repositioning failed to complete within the timeout specified. + @retval EFI_MEDIA_CHANGED The media in the device was changed since the last access. + Repositioning the media was aborted since the current + position of the media may be incorrect. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reposition the media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_SPACE)( + IN EFI_TAPE_IO_PROTOCOL *This, + IN INTN Direction, + IN UINTN Type + ); + + +/** + Writes filemarks to the media. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + @param Count Number of filemarks to write to the media. + + @retval EFI_SUCCESS Data was successfully transferred from the media. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY The transfer failed since the device was not ready (e.g. not + online). The transfer may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of repositioning. + @retval EFI_TIMEOUT The transfer failed to complete within the timeout specified. + @retval EFI_MEDIA_CHANGED The media in the device was changed since the last access. + The transfer was aborted since the current position of the + media may be incorrect. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to transfer data from the media. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_WRITEFM)( + IN EFI_TAPE_IO_PROTOCOL *This, + IN UINTN Count + ); + + +/** + Resets the tape device. + + @param This A pointer to the EFI_TAPE_IO_PROTOCOL instance. + @param ExtendedVerification Indicates whether the parent bus should also be reset. + + @retval EFI_SUCCESS The bus and/or device were successfully reset. + @retval EFI_NO_MEDIA No media is loaded in the device. + @retval EFI_NOT_READY The reset failed since the device and/or bus was not ready. + The reset may be retried at a later time. + @retval EFI_UNSUPPORTED The device does not support this type of reset. + @retval EFI_TIMEOUT The reset did not complete within the timeout allowed. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to reset the bus and/or device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TAPE_RESET)( + IN EFI_TAPE_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/// +/// The EFI_TAPE_IO_PROTOCOL provides basic sequential operations for tape devices. +/// These include read, write, rewind, space, write filemarks and reset functions. +/// Per this specification, a boot application uses the services of this protocol +/// to load the bootloader image from tape. +/// +struct _EFI_TAPE_IO_PROTOCOL { + EFI_TAPE_READ TapeRead; + EFI_TAPE_WRITE TapeWrite; + EFI_TAPE_REWIND TapeRewind; + EFI_TAPE_SPACE TapeSpace; + EFI_TAPE_WRITEFM TapeWriteFM; + EFI_TAPE_RESET TapeReset; +}; + +extern EFI_GUID gEfiTapeIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcg2Protocol.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcg2Protocol.h new file mode 100644 index 0000000000..04a209cfdf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcg2Protocol.h @@ -0,0 +1,335 @@ +/** @file + TPM2 Protocol as defined in TCG PC Client Platform EFI Protocol Specification Family "2.0". + See http://trustedcomputinggroup.org for the latest specification + +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __TCG2_PROTOCOL_H__ +#define __TCG2_PROTOCOL_H__ + +#include +#include + +#define EFI_TCG2_PROTOCOL_GUID \ + {0x607f766c, 0x7455, 0x42be, { 0x93, 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f }} + +typedef struct tdEFI_TCG2_PROTOCOL EFI_TCG2_PROTOCOL; + +typedef struct tdEFI_TCG2_VERSION { + UINT8 Major; + UINT8 Minor; +} EFI_TCG2_VERSION; + +typedef UINT32 EFI_TCG2_EVENT_LOG_BITMAP; +typedef UINT32 EFI_TCG2_EVENT_LOG_FORMAT; +typedef UINT32 EFI_TCG2_EVENT_ALGORITHM_BITMAP; + +#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 0x00000001 +#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002 + +typedef struct tdEFI_TCG2_BOOT_SERVICE_CAPABILITY { + // + // Allocated size of the structure + // + UINT8 Size; + // + // Version of the EFI_TCG2_BOOT_SERVICE_CAPABILITY structure itself. + // For this version of the protocol, the Major version shall be set to 1 + // and the Minor version shall be set to 1. + // + EFI_TCG2_VERSION StructureVersion; + // + // Version of the EFI TCG2 protocol. + // For this version of the protocol, the Major version shall be set to 1 + // and the Minor version shall be set to 1. + // + EFI_TCG2_VERSION ProtocolVersion; + // + // Supported hash algorithms (this bitmap is determined by the supported PCR + // banks in the TPM and the hashing algorithms supported by the firmware) + // + EFI_TCG2_EVENT_ALGORITHM_BITMAP HashAlgorithmBitmap; + // + // Bitmap of supported event log formats + // + EFI_TCG2_EVENT_LOG_BITMAP SupportedEventLogs; + // + // False = TPM not present + // + BOOLEAN TPMPresentFlag; + // + // Max size (in bytes) of a command that can be sent to the TPM + // + UINT16 MaxCommandSize; + // + // Max size (in bytes) of a response that can be provided by the TPM + // + UINT16 MaxResponseSize; + // + // 4-byte Vendor ID + // (see TCG Vendor ID registry, Section "TPM Capabilities Vendor ID") + // + UINT32 ManufacturerID; + // + // Maximum number of PCR banks (hashing algorithms) supported. + // No granularity is provided to support a specific set of algorithms. + // Minimum value is 1. + // + UINT32 NumberOfPCRBanks; + // + // A bitmap of currently active PCR banks (hashing algorithms). + // This is a subset of the supported hashing algorithms reported in HashAlgorithmBitMap. + // NumberOfPcrBanks defines the number of bits that are set. + // + EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrBanks; +} EFI_TCG2_BOOT_SERVICE_CAPABILITY; + +#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001 +#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002 +#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004 +#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008 +#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 + +// +// This bit is shall be set when an event shall be extended but not logged. +// +#define EFI_TCG2_EXTEND_ONLY 0x0000000000000001 +// +// This bit shall be set when the intent is to measure a PE/COFF image. +// +#define PE_COFF_IMAGE 0x0000000000000010 + +#define MAX_PCR_INDEX 23 + +#pragma pack(1) + +#define EFI_TCG2_EVENT_HEADER_VERSION 1 + +typedef struct { + // + // Size of the event header itself (sizeof(EFI_TCG2_EVENT_HEADER)). + // + UINT32 HeaderSize; + // + // Header version. For this version of this specification, the value shall be 1. + // + UINT16 HeaderVersion; + // + // Index of the PCR that shall be extended (0 - 23). + // + TCG_PCRINDEX PCRIndex; + // + // Type of the event that shall be extended (and optionally logged). + // + TCG_EVENTTYPE EventType; +} EFI_TCG2_EVENT_HEADER; + +typedef struct tdEFI_TCG2_EVENT { + // + // Total size of the event including the Size component, the header and the Event data. + // + UINT32 Size; + EFI_TCG2_EVENT_HEADER Header; + UINT8 Event[1]; +} EFI_TCG2_EVENT; + +#pragma pack() + +/** + The EFI_TCG2_PROTOCOL GetCapability function call provides protocol + capability information and state information. + + @param[in] This Indicates the calling context + @param[in, out] ProtocolCapability The caller allocates memory for a EFI_TCG2_BOOT_SERVICE_CAPABILITY + structure and sets the size field to the size of the structure allocated. + The callee fills in the fields with the EFI protocol capability information + and the current EFI TCG2 state information up to the number of fields which + fit within the size of the structure passed in. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + The ProtocolCapability variable will not be populated. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + The ProtocolCapability variable will not be populated. + @retval EFI_BUFFER_TOO_SMALL The ProtocolCapability variable is too small to hold the full response. + It will be partially populated (required Size field will be set). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_GET_CAPABILITY) ( + IN EFI_TCG2_PROTOCOL *This, + IN OUT EFI_TCG2_BOOT_SERVICE_CAPABILITY *ProtocolCapability + ); + +/** + The EFI_TCG2_PROTOCOL Get Event Log function call allows a caller to + retrieve the address of a given event log and its last entry. + + @param[in] This Indicates the calling context + @param[in] EventLogFormat The type of the event log for which the information is requested. + @param[out] EventLogLocation A pointer to the memory address of the event log. + @param[out] EventLogLastEntry If the Event Log contains more than one entry, this is a pointer to the + address of the start of the last entry in the event log in memory. + @param[out] EventLogTruncated If the Event Log is missing at least one entry because an event would + have exceeded the area allocated for events, this value is set to TRUE. + Otherwise, the value will be FALSE and the Event Log will be complete. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect + (e.g. asking for an event log whose format is not supported). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_GET_EVENT_LOG) ( + IN EFI_TCG2_PROTOCOL *This, + IN EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat, + OUT EFI_PHYSICAL_ADDRESS *EventLogLocation, + OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry, + OUT BOOLEAN *EventLogTruncated + ); + +/** + The EFI_TCG2_PROTOCOL HashLogExtendEvent function call provides callers with + an opportunity to extend and optionally log events without requiring + knowledge of actual TPM commands. + The extend operation will occur even if this function cannot create an event + log entry (e.g. due to the event log being full). + + @param[in] This Indicates the calling context + @param[in] Flags Bitmap providing additional information. + @param[in] DataToHash Physical address of the start of the data buffer to be hashed. + @param[in] DataToHashLen The length in bytes of the buffer referenced by DataToHash. + @param[in] EfiTcgEvent Pointer to data buffer containing information about the event. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + @retval EFI_VOLUME_FULL The extend operation occurred, but the event could not be written to one or more event logs. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_UNSUPPORTED The PE/COFF image type is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_TCG2_HASH_LOG_EXTEND_EVENT) ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT64 Flags, + IN EFI_PHYSICAL_ADDRESS DataToHash, + IN UINT64 DataToHashLen, + IN EFI_TCG2_EVENT *EfiTcgEvent + ); + +/** + This service enables the sending of commands to the TPM. + + @param[in] This Indicates the calling context + @param[in] InputParameterBlockSize Size of the TPM input parameter block. + @param[in] InputParameterBlock Pointer to the TPM input parameter block. + @param[in] OutputParameterBlockSize Size of the TPM output parameter block. + @param[in] OutputParameterBlock Pointer to the TPM output parameter block. + + @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received. + @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_SUBMIT_COMMAND) ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT32 InputParameterBlockSize, + IN UINT8 *InputParameterBlock, + IN UINT32 OutputParameterBlockSize, + IN UINT8 *OutputParameterBlock + ); + +/** + This service returns the currently active PCR banks. + + @param[in] This Indicates the calling context + @param[out] ActivePcrBanks Pointer to the variable receiving the bitmap of currently active PCR banks. + + @retval EFI_SUCCESS The bitmap of active PCR banks was stored in the ActivePcrBanks parameter. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_GET_ACTIVE_PCR_BANKS) ( + IN EFI_TCG2_PROTOCOL *This, + OUT UINT32 *ActivePcrBanks + ); + +/** + This service sets the currently active PCR banks. + + @param[in] This Indicates the calling context + @param[in] ActivePcrBanks Bitmap of the requested active PCR banks. At least one bit SHALL be set. + + @retval EFI_SUCCESS The bitmap in ActivePcrBank parameter is already active. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_SET_ACTIVE_PCR_BANKS) ( + IN EFI_TCG2_PROTOCOL *This, + IN UINT32 ActivePcrBanks + ); + +/** + This service retrieves the result of a previous invocation of SetActivePcrBanks. + + @param[in] This Indicates the calling context + @param[out] OperationPresent Non-zero value to indicate a SetActivePcrBank operation was invoked during the last boot. + @param[out] Response The response from the SetActivePcrBank request. + + @retval EFI_SUCCESS The result value could be returned. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS) ( + IN EFI_TCG2_PROTOCOL *This, + OUT UINT32 *OperationPresent, + OUT UINT32 *Response + ); + +struct tdEFI_TCG2_PROTOCOL { + EFI_TCG2_GET_CAPABILITY GetCapability; + EFI_TCG2_GET_EVENT_LOG GetEventLog; + EFI_TCG2_HASH_LOG_EXTEND_EVENT HashLogExtendEvent; + EFI_TCG2_SUBMIT_COMMAND SubmitCommand; + EFI_TCG2_GET_ACTIVE_PCR_BANKS GetActivePcrBanks; + EFI_TCG2_SET_ACTIVE_PCR_BANKS SetActivePcrBanks; + EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS GetResultOfSetActivePcrBanks; +}; + +extern EFI_GUID gEfiTcg2ProtocolGuid; + +// +// Log entries after Get Event Log service +// + +#define EFI_TCG2_FINAL_EVENTS_TABLE_GUID \ + {0x1e2ed096, 0x30e2, 0x4254, { 0xbd, 0x89, 0x86, 0x3b, 0xbe, 0xf8, 0x23, 0x25 }} + +extern EFI_GUID gEfiTcg2FinalEventsTableGuid; + +typedef struct tdEFI_TCG2_FINAL_EVENTS_TABLE { + // + // The version of this structure. + // + UINT64 Version; + // + // Number of events recorded after invocation of GetEventLog API + // + UINT64 NumberOfEvents; + // + // List of events of type TCG_PCR_EVENT2. + // +//TCG_PCR_EVENT2 Event[1]; +} EFI_TCG2_FINAL_EVENTS_TABLE; + +#define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TcgService.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TcgService.h new file mode 100644 index 0000000000..937bd12f24 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TcgService.h @@ -0,0 +1,195 @@ +/** @file + TCG Service Protocol as defined in TCG_EFI_Protocol_1_22_Final + See http://trustedcomputinggroup.org for the latest specification + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TCG_SERVICE_PROTOCOL_H_ +#define _TCG_SERVICE_PROTOCOL_H_ + +#include + +#define EFI_TCG_PROTOCOL_GUID \ + {0xf541796d, 0xa62e, 0x4954, { 0xa7, 0x75, 0x95, 0x84, 0xf6, 0x1b, 0x9c, 0xdd } } + +typedef struct _EFI_TCG_PROTOCOL EFI_TCG_PROTOCOL; + +typedef struct { + UINT8 Major; + UINT8 Minor; + UINT8 RevMajor; + UINT8 RevMinor; +} TCG_VERSION; + +typedef struct _TCG_EFI_BOOT_SERVICE_CAPABILITY { + UINT8 Size; /// Size of this structure. + TCG_VERSION StructureVersion; + TCG_VERSION ProtocolSpecVersion; + UINT8 HashAlgorithmBitmap; /// Hash algorithms . + /// This protocol is capable of : 01=SHA-1. + BOOLEAN TPMPresentFlag; /// 00h = TPM not present. + BOOLEAN TPMDeactivatedFlag; /// 01h = TPM currently deactivated. +} TCG_EFI_BOOT_SERVICE_CAPABILITY; + +typedef UINT32 TCG_ALGORITHM_ID; + +/** + This service provides EFI protocol capability information, state information + about the TPM, and Event Log state information. + + @param This Indicates the calling context + @param ProtocolCapability The callee allocates memory for a TCG_BOOT_SERVICE_CAPABILITY + structure and fills in the fields with the EFI protocol + capability information and the current TPM state information. + @param TCGFeatureFlags This is a pointer to the feature flags. No feature + flags are currently defined so this parameter + MUST be set to 0. However, in the future, + feature flags may be defined that, for example, + enable hash algorithm agility. + @param EventLogLocation This is a pointer to the address of the event log in memory. + @param EventLogLastEntry If the Event Log contains more than one entry, + this is a pointer to the address of the start of + the last entry in the event log in memory. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER ProtocolCapability does not match TCG capability. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG_STATUS_CHECK)( + IN EFI_TCG_PROTOCOL *This, + OUT TCG_EFI_BOOT_SERVICE_CAPABILITY + *ProtocolCapability, + OUT UINT32 *TCGFeatureFlags, + OUT EFI_PHYSICAL_ADDRESS *EventLogLocation, + OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry + ); + +/** + This service abstracts the capability to do a hash operation on a data buffer. + + @param This Indicates the calling context. + @param HashData The pointer to the data buffer to be hashed. + @param HashDataLen The length of the data buffer to be hashed. + @param AlgorithmId Identification of the Algorithm to use for the hashing operation. + @param HashedDataLen Resultant length of the hashed data. + @param HashedDataResult Resultant buffer of the hashed data. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER HashDataLen is NULL. + @retval EFI_INVALID_PARAMETER HashDataLenResult is NULL. + @retval EFI_OUT_OF_RESOURCES Cannot allocate buffer of size *HashedDataLen. + @retval EFI_UNSUPPORTED AlgorithmId not supported. + @retval EFI_BUFFER_TOO_SMALL *HashedDataLen < sizeof (TCG_DIGEST). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG_HASH_ALL)( + IN EFI_TCG_PROTOCOL *This, + IN UINT8 *HashData, + IN UINT64 HashDataLen, + IN TCG_ALGORITHM_ID AlgorithmId, + IN OUT UINT64 *HashedDataLen, + IN OUT UINT8 **HashedDataResult + ); + +/** + This service abstracts the capability to add an entry to the Event Log. + + @param This Indicates the calling context + @param TCGLogData The pointer to the start of the data buffer containing + the TCG_PCR_EVENT data structure. All fields in + this structure are properly filled by the caller. + @param EventNumber The event number of the event just logged. + @param Flags Indicates additional flags. Only one flag has been + defined at this time, which is 0x01 and means the + extend operation should not be performed. All + other bits are reserved. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_OUT_OF_RESOURCES Insufficient memory in the event log to complete this action. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG_LOG_EVENT)( + IN EFI_TCG_PROTOCOL *This, + IN TCG_PCR_EVENT *TCGLogData, + IN OUT UINT32 *EventNumber, + IN UINT32 Flags + ); + +/** + This service is a proxy for commands to the TPM. + + @param This Indicates the calling context. + @param TpmInputParameterBlockSize Size of the TPM input parameter block. + @param TpmInputParameterBlock The pointer to the TPM input parameter block. + @param TpmOutputParameterBlockSize Size of the TPM output parameter block. + @param TpmOutputParameterBlock The pointer to the TPM output parameter block. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Invalid ordinal. + @retval EFI_UNSUPPORTED Current Task Priority Level >= EFI_TPL_CALLBACK. + @retval EFI_TIMEOUT The TIS timed-out. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG_PASS_THROUGH_TO_TPM)( + IN EFI_TCG_PROTOCOL *This, + IN UINT32 TpmInputParameterBlockSize, + IN UINT8 *TpmInputParameterBlock, + IN UINT32 TpmOutputParameterBlockSize, + IN UINT8 *TpmOutputParameterBlock + ); + +/** + This service abstracts the capability to do a hash operation on a data buffer, extend a specific TPM PCR with the hash result, and add an entry to the Event Log + + @param This Indicates the calling context + @param HashData The physical address of the start of the data buffer + to be hashed, extended, and logged. + @param HashDataLen The length, in bytes, of the buffer referenced by HashData + @param AlgorithmId Identification of the Algorithm to use for the hashing operation + @param TCGLogData The physical address of the start of the data + buffer containing the TCG_PCR_EVENT data structure. + @param EventNumber The event number of the event just logged. + @param EventLogLastEntry The physical address of the first byte of the entry + just placed in the Event Log. If the Event Log was + empty when this function was called then this physical + address will be the same as the physical address of + the start of the Event Log. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_UNSUPPORTED AlgorithmId != TPM_ALG_SHA. + @retval EFI_UNSUPPORTED Current TPL >= EFI_TPL_CALLBACK. + @retval EFI_DEVICE_ERROR The command was unsuccessful. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCG_HASH_LOG_EXTEND_EVENT)( + IN EFI_TCG_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS HashData, + IN UINT64 HashDataLen, + IN TCG_ALGORITHM_ID AlgorithmId, + IN OUT TCG_PCR_EVENT *TCGLogData, + IN OUT UINT32 *EventNumber, + OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry + ); + +/// +/// The EFI_TCG Protocol abstracts TCG activity. +/// +struct _EFI_TCG_PROTOCOL { + EFI_TCG_STATUS_CHECK StatusCheck; + EFI_TCG_HASH_ALL HashAll; + EFI_TCG_LOG_EVENT LogEvent; + EFI_TCG_PASS_THROUGH_TO_TPM PassThroughToTpm; + EFI_TCG_HASH_LOG_EXTEND_EVENT HashLogExtendEvent; +}; + +extern EFI_GUID gEfiTcgProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp4.h new file mode 100644 index 0000000000..d1fef270f6 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp4.h @@ -0,0 +1,571 @@ +/** @file + EFI TCPv4(Transmission Control Protocol version 4) Protocol Definition + The EFI TCPv4 Service Binding Protocol is used to locate EFI TCPv4 Protocol drivers to create + and destroy child of the driver to communicate with other host using TCP protocol. + The EFI TCPv4 Protocol provides services to send and receive data stream. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0. + +**/ + +#ifndef __EFI_TCP4_PROTOCOL_H__ +#define __EFI_TCP4_PROTOCOL_H__ + +#include + +#define EFI_TCP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x00720665, 0x67EB, 0x4a99, {0xBA, 0xF7, 0xD3, 0xC3, 0x3A, 0x1C, 0x7C, 0xC9 } \ + } + +#define EFI_TCP4_PROTOCOL_GUID \ + { \ + 0x65530BC7, 0xA359, 0x410f, {0xB0, 0x10, 0x5A, 0xAD, 0xC7, 0xEC, 0x2B, 0x62 } \ + } + +typedef struct _EFI_TCP4_PROTOCOL EFI_TCP4_PROTOCOL; + +/// +/// EFI_TCP4_SERVICE_POINT is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE InstanceHandle; + EFI_IPv4_ADDRESS LocalAddress; + UINT16 LocalPort; + EFI_IPv4_ADDRESS RemoteAddress; + UINT16 RemotePort; +} EFI_TCP4_SERVICE_POINT; + +/// +/// EFI_TCP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE DriverHandle; + UINT32 ServiceCount; + EFI_TCP4_SERVICE_POINT Services[1]; +} EFI_TCP4_VARIABLE_DATA; + +typedef struct { + BOOLEAN UseDefaultAddress; + EFI_IPv4_ADDRESS StationAddress; + EFI_IPv4_ADDRESS SubnetMask; + UINT16 StationPort; + EFI_IPv4_ADDRESS RemoteAddress; + UINT16 RemotePort; + BOOLEAN ActiveFlag; +} EFI_TCP4_ACCESS_POINT; + +typedef struct { + UINT32 ReceiveBufferSize; + UINT32 SendBufferSize; + UINT32 MaxSynBackLog; + UINT32 ConnectionTimeout; + UINT32 DataRetries; + UINT32 FinTimeout; + UINT32 TimeWaitTimeout; + UINT32 KeepAliveProbes; + UINT32 KeepAliveTime; + UINT32 KeepAliveInterval; + BOOLEAN EnableNagle; + BOOLEAN EnableTimeStamp; + BOOLEAN EnableWindowScaling; + BOOLEAN EnableSelectiveAck; + BOOLEAN EnablePathMtuDiscovery; +} EFI_TCP4_OPTION; + +typedef struct { + // + // I/O parameters + // + UINT8 TypeOfService; + UINT8 TimeToLive; + + // + // Access Point + // + EFI_TCP4_ACCESS_POINT AccessPoint; + + // + // TCP Control Options + // + EFI_TCP4_OPTION *ControlOption; +} EFI_TCP4_CONFIG_DATA; + +/// +/// TCP4 connnection state +/// +typedef enum { + Tcp4StateClosed = 0, + Tcp4StateListen = 1, + Tcp4StateSynSent = 2, + Tcp4StateSynReceived = 3, + Tcp4StateEstablished = 4, + Tcp4StateFinWait1 = 5, + Tcp4StateFinWait2 = 6, + Tcp4StateClosing = 7, + Tcp4StateTimeWait = 8, + Tcp4StateCloseWait = 9, + Tcp4StateLastAck = 10 +} EFI_TCP4_CONNECTION_STATE; + +typedef struct { + EFI_EVENT Event; + EFI_STATUS Status; +} EFI_TCP4_COMPLETION_TOKEN; + +typedef struct { + /// + /// The Status in the CompletionToken will be set to one of + /// the following values if the active open succeeds or an unexpected + /// error happens: + /// EFI_SUCCESS: The active open succeeds and the instance's + /// state is Tcp4StateEstablished. + /// EFI_CONNECTION_RESET: The connect fails because the connection is reset + /// either by instance itself or the communication peer. + /// EFI_CONNECTION_REFUSED: The connect fails because this connection is initiated with + /// an active open and the connection is refused. + /// EFI_ABORTED: The active open is aborted. + /// EFI_TIMEOUT: The connection establishment timer expires and + /// no more specific information is available. + /// EFI_NETWORK_UNREACHABLE: The active open fails because + /// an ICMP network unreachable error is received. + /// EFI_HOST_UNREACHABLE: The active open fails because an + /// ICMP host unreachable error is received. + /// EFI_PROTOCOL_UNREACHABLE: The active open fails + /// because an ICMP protocol unreachable error is received. + /// EFI_PORT_UNREACHABLE: The connection establishment + /// timer times out and an ICMP port unreachable error is received. + /// EFI_ICMP_ERROR: The connection establishment timer timeout and some other ICMP + /// error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_TCP4_COMPLETION_TOKEN CompletionToken; +} EFI_TCP4_CONNECTION_TOKEN; + +typedef struct { + EFI_TCP4_COMPLETION_TOKEN CompletionToken; + EFI_HANDLE NewChildHandle; +} EFI_TCP4_LISTEN_TOKEN; + +typedef struct { + UINT32 FragmentLength; + VOID *FragmentBuffer; +} EFI_TCP4_FRAGMENT_DATA; + +typedef struct { + BOOLEAN UrgentFlag; + UINT32 DataLength; + UINT32 FragmentCount; + EFI_TCP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_TCP4_RECEIVE_DATA; + +typedef struct { + BOOLEAN Push; + BOOLEAN Urgent; + UINT32 DataLength; + UINT32 FragmentCount; + EFI_TCP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_TCP4_TRANSMIT_DATA; + +typedef struct { + /// + /// When transmission finishes or meets any unexpected error it will + /// be set to one of the following values: + /// EFI_SUCCESS: The receiving or transmission operation + /// completes successfully. + /// EFI_CONNECTION_FIN: The receiving operation fails because the communication peer + /// has closed the connection and there is no more data in the + /// receive buffer of the instance. + /// EFI_CONNECTION_RESET: The receiving or transmission operation fails + /// because this connection is reset either by instance + /// itself or the communication peer. + /// EFI_ABORTED: The receiving or transmission is aborted. + /// EFI_TIMEOUT: The transmission timer expires and no more + /// specific information is available. + /// EFI_NETWORK_UNREACHABLE: The transmission fails + /// because an ICMP network unreachable error is received. + /// EFI_HOST_UNREACHABLE: The transmission fails because an + /// ICMP host unreachable error is received. + /// EFI_PROTOCOL_UNREACHABLE: The transmission fails + /// because an ICMP protocol unreachable error is received. + /// EFI_PORT_UNREACHABLE: The transmission fails and an + /// ICMP port unreachable error is received. + /// EFI_ICMP_ERROR: The transmission fails and some other + /// ICMP error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurs. + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_TCP4_COMPLETION_TOKEN CompletionToken; + union { + /// + /// When this token is used for receiving, RxData is a pointer to EFI_TCP4_RECEIVE_DATA. + /// + EFI_TCP4_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to EFI_TCP4_TRANSMIT_DATA. + /// + EFI_TCP4_TRANSMIT_DATA *TxData; + } Packet; +} EFI_TCP4_IO_TOKEN; + +typedef struct { + EFI_TCP4_COMPLETION_TOKEN CompletionToken; + BOOLEAN AbortOnClose; +} EFI_TCP4_CLOSE_TOKEN; + +// +// Interface definition for TCP4 protocol +// + +/** + Get the current operational status. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param Tcp4State The pointer to the buffer to receive the current TCP state. + @param Tcp4ConfigData The pointer to the buffer to receive the current TCP configuration. + @param Ip4ModeData The pointer to the buffer to receive the current IPv4 configuration + data used by the TCPv4 instance. + @param MnpConfigData The pointer to the buffer to receive the current MNP configuration + data used indirectly by the TCPv4 instance. + @param SnpModeData The pointer to the buffer to receive the current SNP configuration + data used indirectly by the TCPv4 instance. + + @retval EFI_SUCCESS The mode data was read. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED No configuration data is available because this instance hasn't + been started. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_GET_MODE_DATA)( + IN EFI_TCP4_PROTOCOL *This, + OUT EFI_TCP4_CONNECTION_STATE *Tcp4State OPTIONAL, + OUT EFI_TCP4_CONFIG_DATA *Tcp4ConfigData OPTIONAL, + OUT EFI_IP4_MODE_DATA *Ip4ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + +/** + Initialize or brutally reset the operational parameters for this EFI TCPv4 instance. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param Tcp4ConfigData The pointer to the configure data to configure the instance. + + @retval EFI_SUCCESS The operational settings are set, changed, or reset + successfully. + @retval EFI_INVALID_PARAMETER Some parameter is invalid. + @retval EFI_NO_MAPPING When using a default address, configuration (through + DHCP, BOOTP, RARP, etc.) is not finished yet. + @retval EFI_ACCESS_DENIED Configuring TCP instance when it is configured without + calling Configure() with NULL to reset it. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + @retval EFI_UNSUPPORTED One or more of the control options are not supported in + the implementation. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources when + executing Configure(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_CONFIGURE)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_CONFIG_DATA *TcpConfigData OPTIONAL + ); + + +/** + Add or delete a route entry to the route table + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param DeleteRoute Set it to TRUE to delete this route from the routing table. Set it to + FALSE to add this route to the routing table. + DestinationAddress and SubnetMask are used as the + keywords to search route entry. + @param SubnetAddress The destination network. + @param SubnetMask The subnet mask of the destination network. + @param GatewayAddress The gateway address for this route. It must be on the same + subnet with the station address unless a direct route is specified. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The EFI TCPv4 Protocol instance has not been configured. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - SubnetAddress is NULL. + - SubnetMask is NULL. + - GatewayAddress is NULL. + - *SubnetAddress is not NULL a valid subnet address. + - *SubnetMask is not a valid subnet mask. + - *GatewayAddress is not a valid unicast IP address or it + is not in the same subnet. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resources to add the entry to the + routing table. + @retval EFI_NOT_FOUND This route is not in the routing table. + @retval EFI_ACCESS_DENIED The route is already defined in the routing table. + @retval EFI_UNSUPPORTED The TCP driver does not support this operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_ROUTES)( + IN EFI_TCP4_PROTOCOL *This, + IN BOOLEAN DeleteRoute, + IN EFI_IPv4_ADDRESS *SubnetAddress, + IN EFI_IPv4_ADDRESS *SubnetMask, + IN EFI_IPv4_ADDRESS *GatewayAddress + ); + +/** + Initiate a nonblocking TCP connection request for an active TCP instance. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param ConnectionToken The pointer to the connection token to return when the TCP three + way handshake finishes. + + @retval EFI_SUCCESS The connection request is successfully initiated and the state + of this TCPv4 instance has been changed to Tcp4StateSynSent. + @retval EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following conditions are TRUE: + - This instance is not configured as an active one. + - This instance is not in Tcp4StateClosed state. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - ConnectionToken is NULL. + - ConnectionToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The driver can't allocate enough resource to initiate the activ eopen. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_CONNECT)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_CONNECTION_TOKEN *ConnectionToken + ); + + +/** + Listen on the passive instance to accept an incoming connection request. This is a nonblocking operation. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param ListenToken The pointer to the listen token to return when operation finishes. + + @retval EFI_SUCCESS The listen token has been queued successfully. + @retval EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following are TRUE: + - This instance is not a passive instance. + - This instance is not in Tcp4StateListen state. + - The same listen token has already existed in the listen + token queue of this TCP instance. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - ListenToken is NULL. + - ListentToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR Any unexpected and not belonged to above category error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_ACCEPT)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_LISTEN_TOKEN *ListenToken + ); + +/** + Queues outgoing data into the transmit queue. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param Token The pointer to the completion token to queue to the transmit queue. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been configured. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - Token is NULL. + - Token->CompletionToken.Event is NULL. + - Token->Packet.TxData is NULL L. + - Token->Packet.FragmentCount is zero. + - Token->Packet.DataLength is not equal to the sum of fragment lengths. + @retval EFI_ACCESS_DENIED One or more of the following conditions is TRUE: + - A transmit completion token with the same Token->CompletionToken.Event + was already in the transmission queue. + - The current instance is in Tcp4StateClosed state. + - The current instance is a passive one and it is in + Tcp4StateListen state. + - User has called Close() to disconnect this connection. + @retval EFI_NOT_READY The completion token could not be queued because the + transmit queue is full. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data because of resource + shortage. + @retval EFI_NETWORK_UNREACHABLE There is no route to the destination network or address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_TRANSMIT)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_IO_TOKEN *Token + ); + + +/** + Places an asynchronous receive request into the receiving queue. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param Token The pointer to a token that is associated with the receive data + descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been configured. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, RARP, + etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token->CompletionToken.Event is NULL. + - Token->Packet.RxData is NULL. + - Token->Packet.RxData->DataLength is 0. + - The Token->Packet.RxData->DataLength is not + the sum of all FragmentBuffer length in FragmentTable. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of + system resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_ACCESS_DENIED One or more of the following conditions is TRUE: + - A receive completion token with the same Token- + >CompletionToken.Event was already in the receive + queue. + - The current instance is in Tcp4StateClosed state. + - The current instance is a passive one and it is in + Tcp4StateListen state. + - User has called Close() to disconnect this connection. + @retval EFI_CONNECTION_FIN The communication peer has closed the connection and there is + no any buffered data in the receive buffer of this instance. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_RECEIVE)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_IO_TOKEN *Token + ); + +/** + Disconnecting a TCP connection gracefully or reset a TCP connection. This function is a + nonblocking operation. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param CloseToken The pointer to the close token to return when operation finishes. + + @retval EFI_SUCCESS The Close() is called successfully. + @retval EFI_NOT_STARTED This EFI TCPv4 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following are TRUE: + - Configure() has been called with + TcpConfigData set to NULL and this function has + not returned. + - Previous Close() call on this instance has not + finished. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - CloseToken is NULL. + - CloseToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR Any unexpected and not belonged to above category error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_CLOSE)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_CLOSE_TOKEN *CloseToken + ); + +/** + Abort an asynchronous connection, listen, transmission or receive request. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + @param Token The pointer to a token that has been issued by + EFI_TCP4_PROTOCOL.Connect(), + EFI_TCP4_PROTOCOL.Accept(), + EFI_TCP4_PROTOCOL.Transmit() or + EFI_TCP4_PROTOCOL.Receive(). If NULL, all pending + tokens issued by above four functions will be aborted. Type + EFI_TCP4_COMPLETION_TOKEN is defined in + EFI_TCP4_PROTOCOL.Connect(). + + @retval EFI_SUCCESS The asynchronous I/O request is aborted and Token->Event + is signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance hasn't been configured. + @retval EFI_NO_MAPPING When using the default address, configuration + (DHCP, BOOTP,RARP, etc.) hasn't finished yet. + @retval EFI_NOT_FOUND The asynchronous I/O request isn't found in the + transmission or receive queue. It has either + completed or wasn't issued by Transmit() and Receive(). + @retval EFI_UNSUPPORTED The implementation does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_CANCEL)( + IN EFI_TCP4_PROTOCOL *This, + IN EFI_TCP4_COMPLETION_TOKEN *Token OPTIONAL + ); + + +/** + Poll to receive incoming data and transmit outgoing segments. + + @param This The pointer to the EFI_TCP4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY No incoming or outgoing data is processed. + @retval EFI_TIMEOUT Data was dropped out of the transmission or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP4_POLL)( + IN EFI_TCP4_PROTOCOL *This + ); + +/// +/// The EFI_TCP4_PROTOCOL defines the EFI TCPv4 Protocol child to be used by +/// any network drivers or applications to send or receive data stream. +/// It can either listen on a specified port as a service or actively connected +/// to remote peer as a client. Each instance has its own independent settings, +/// such as the routing table. +/// +struct _EFI_TCP4_PROTOCOL { + EFI_TCP4_GET_MODE_DATA GetModeData; + EFI_TCP4_CONFIGURE Configure; + EFI_TCP4_ROUTES Routes; + EFI_TCP4_CONNECT Connect; + EFI_TCP4_ACCEPT Accept; + EFI_TCP4_TRANSMIT Transmit; + EFI_TCP4_RECEIVE Receive; + EFI_TCP4_CLOSE Close; + EFI_TCP4_CANCEL Cancel; + EFI_TCP4_POLL Poll; +}; + +extern EFI_GUID gEfiTcp4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiTcp4ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp6.h new file mode 100644 index 0000000000..4b3e471b44 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tcp6.h @@ -0,0 +1,858 @@ +/** @file + EFI TCPv6(Transmission Control Protocol version 6) Protocol Definition + The EFI TCPv6 Service Binding Protocol is used to locate EFI TCPv6 Protocol drivers to create + and destroy child of the driver to communicate with other host using TCP protocol. + The EFI TCPv6 Protocol provides services to send and receive data stream. + + Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_TCP6_PROTOCOL_H__ +#define __EFI_TCP6_PROTOCOL_H__ + +#include +#include + +#define EFI_TCP6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0xec20eb79, 0x6c1a, 0x4664, {0x9a, 0x0d, 0xd2, 0xe4, 0xcc, 0x16, 0xd6, 0x64 } \ + } + +#define EFI_TCP6_PROTOCOL_GUID \ + { \ + 0x46e44855, 0xbd60, 0x4ab7, {0xab, 0x0d, 0xa6, 0x79, 0xb9, 0x44, 0x7d, 0x77 } \ + } + + +typedef struct _EFI_TCP6_PROTOCOL EFI_TCP6_PROTOCOL; + +/// +/// EFI_TCP6_SERVICE_POINT is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + /// + /// The EFI TCPv6 Protocol instance handle that is using this + /// address/port pair. + /// + EFI_HANDLE InstanceHandle; + /// + /// The local IPv6 address to which this TCP instance is bound. Set + /// to 0::/128, if this TCP instance is configured to listen on all + /// available source addresses. + /// + EFI_IPv6_ADDRESS LocalAddress; + /// + /// The local port number in host byte order. + /// + UINT16 LocalPort; + /// + /// The remote IPv6 address. It may be 0::/128 if this TCP instance is + /// not connected to any remote host. + /// + EFI_IPv6_ADDRESS RemoteAddress; + /// + /// The remote port number in host byte order. It may be zero if this + /// TCP instance is not connected to any remote host. + /// + UINT16 RemotePort; +} EFI_TCP6_SERVICE_POINT; + +/// +/// EFI_TCP6_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE DriverHandle; ///< The handle of the driver that creates this entry. + UINT32 ServiceCount; ///< The number of address/port pairs following this data structure. + EFI_TCP6_SERVICE_POINT Services[1]; ///< List of address/port pairs that are currently in use. +} EFI_TCP6_VARIABLE_DATA; + +/// +/// EFI_TCP6_ACCESS_POINT +/// +typedef struct { + /// + /// The local IP address assigned to this TCP instance. The EFI + /// TCPv6 driver will only deliver incoming packets whose + /// destination addresses exactly match the IP address. Set to zero to + /// let the underlying IPv6 driver choose a source address. If not zero + /// it must be one of the configured IP addresses in the underlying + /// IPv6 driver. + /// + EFI_IPv6_ADDRESS StationAddress; + /// + /// The local port number to which this EFI TCPv6 Protocol instance + /// is bound. If the instance doesn't care the local port number, set + /// StationPort to zero to use an ephemeral port. + /// + UINT16 StationPort; + /// + /// The remote IP address to which this EFI TCPv6 Protocol instance + /// is connected. If ActiveFlag is FALSE (i.e. a passive TCPv6 + /// instance), the instance only accepts connections from the + /// RemoteAddress. If ActiveFlag is TRUE the instance will + /// connect to the RemoteAddress, i.e., outgoing segments will be + /// sent to this address and only segments from this address will be + /// delivered to the application. When ActiveFlag is FALSE, it + /// can be set to zero and means that incoming connection requests + /// from any address will be accepted. + /// + EFI_IPv6_ADDRESS RemoteAddress; + /// + /// The remote port to which this EFI TCPv6 Protocol instance + /// connects or from which connection request will be accepted by + /// this EFI TCPv6 Protocol instance. If ActiveFlag is FALSE it + /// can be zero and means that incoming connection request from + /// any port will be accepted. Its value can not be zero when + /// ActiveFlag is TRUE. + /// + UINT16 RemotePort; + /// + /// Set it to TRUE to initiate an active open. Set it to FALSE to + /// initiate a passive open to act as a server. + /// + BOOLEAN ActiveFlag; +} EFI_TCP6_ACCESS_POINT; + +/// +/// EFI_TCP6_OPTION +/// +typedef struct { + /// + /// The size of the TCP receive buffer. + /// + UINT32 ReceiveBufferSize; + /// + /// The size of the TCP send buffer. + /// + UINT32 SendBufferSize; + /// + /// The length of incoming connect request queue for a passive + /// instance. When set to zero, the value is implementation specific. + /// + UINT32 MaxSynBackLog; + /// + /// The maximum seconds a TCP instance will wait for before a TCP + /// connection established. When set to zero, the value is + /// implementation specific. + /// + UINT32 ConnectionTimeout; + /// + ///The number of times TCP will attempt to retransmit a packet on + ///an established connection. When set to zero, the value is + ///implementation specific. + /// + UINT32 DataRetries; + /// + /// How many seconds to wait in the FIN_WAIT_2 states for a final + /// FIN flag before the TCP instance is closed. This timeout is in + /// effective only if the application has called Close() to + /// disconnect the connection completely. It is also called + /// FIN_WAIT_2 timer in other implementations. When set to zero, + /// it should be disabled because the FIN_WAIT_2 timer itself is + /// against the standard. The default value is 60. + /// + UINT32 FinTimeout; + /// + /// How many seconds to wait in TIME_WAIT state before the TCP + /// instance is closed. The timer is disabled completely to provide a + /// method to close the TCP connection quickly if it is set to zero. It + /// is against the related RFC documents. + /// + UINT32 TimeWaitTimeout; + /// + /// The maximum number of TCP keep-alive probes to send before + /// giving up and resetting the connection if no response from the + /// other end. Set to zero to disable keep-alive probe. + /// + UINT32 KeepAliveProbes; + /// + /// The number of seconds a connection needs to be idle before TCP + /// sends out periodical keep-alive probes. When set to zero, the + /// value is implementation specific. It should be ignored if keep- + /// alive probe is disabled. + /// + UINT32 KeepAliveTime; + /// + /// The number of seconds between TCP keep-alive probes after the + /// periodical keep-alive probe if no response. When set to zero, the + /// value is implementation specific. It should be ignored if keep- + /// alive probe is disabled. + /// + UINT32 KeepAliveInterval; + /// + /// Set it to TRUE to enable the Nagle algorithm as defined in + /// RFC896. Set it to FALSE to disable it. + /// + BOOLEAN EnableNagle; + /// + /// Set it to TRUE to enable TCP timestamps option as defined in + /// RFC1323. Set to FALSE to disable it. + /// + BOOLEAN EnableTimeStamp; + /// + /// Set it to TRUE to enable TCP window scale option as defined in + /// RFC1323. Set it to FALSE to disable it. + /// + BOOLEAN EnableWindowScaling; + /// + /// Set it to TRUE to enable selective acknowledge mechanism + /// described in RFC 2018. Set it to FALSE to disable it. + /// Implementation that supports SACK can optionally support + /// DSAK as defined in RFC 2883. + /// + BOOLEAN EnableSelectiveAck; + /// + /// Set it to TRUE to enable path MTU discovery as defined in + /// RFC 1191. Set to FALSE to disable it. + /// + BOOLEAN EnablePathMtuDiscovery; +} EFI_TCP6_OPTION; + +/// +/// EFI_TCP6_CONFIG_DATA +/// +typedef struct { + /// + /// TrafficClass field in transmitted IPv6 packets. + /// + UINT8 TrafficClass; + /// + /// HopLimit field in transmitted IPv6 packets. + /// + UINT8 HopLimit; + /// + /// Used to specify TCP communication end settings for a TCP instance. + /// + EFI_TCP6_ACCESS_POINT AccessPoint; + /// + /// Used to configure the advance TCP option for a connection. If set + /// to NULL, implementation specific options for TCP connection will be used. + /// + EFI_TCP6_OPTION *ControlOption; +} EFI_TCP6_CONFIG_DATA; + +/// +/// EFI_TCP6_CONNECTION_STATE +/// +typedef enum { + Tcp6StateClosed = 0, + Tcp6StateListen = 1, + Tcp6StateSynSent = 2, + Tcp6StateSynReceived = 3, + Tcp6StateEstablished = 4, + Tcp6StateFinWait1 = 5, + Tcp6StateFinWait2 = 6, + Tcp6StateClosing = 7, + Tcp6StateTimeWait = 8, + Tcp6StateCloseWait = 9, + Tcp6StateLastAck = 10 +} EFI_TCP6_CONNECTION_STATE; + +/// +/// EFI_TCP6_COMPLETION_TOKEN +/// is used as a common header for various asynchronous tokens. +/// +typedef struct { + /// + /// The Event to signal after request is finished and Status field is + /// updated by the EFI TCPv6 Protocol driver. + /// + EFI_EVENT Event; + /// + /// The result of the completed operation. + /// + EFI_STATUS Status; +} EFI_TCP6_COMPLETION_TOKEN; + +/// +/// EFI_TCP6_CONNECTION_TOKEN +/// will be set if the active open succeeds or an unexpected +/// error happens. +/// +typedef struct { + /// + /// The Status in the CompletionToken will be set to one of + /// the following values if the active open succeeds or an unexpected + /// error happens: + /// EFI_SUCCESS: The active open succeeds and the instance's + /// state is Tcp6StateEstablished. + /// EFI_CONNECTION_RESET: The connect fails because the connection is reset + /// either by instance itself or the communication peer. + /// EFI_CONNECTION_REFUSED: The receiving or transmission operation fails because this + /// connection is refused. + /// EFI_ABORTED: The active open is aborted. + /// EFI_TIMEOUT: The connection establishment timer expires and + /// no more specific information is available. + /// EFI_NETWORK_UNREACHABLE: The active open fails because + /// an ICMP network unreachable error is received. + /// EFI_HOST_UNREACHABLE: The active open fails because an + /// ICMP host unreachable error is received. + /// EFI_PROTOCOL_UNREACHABLE: The active open fails + /// because an ICMP protocol unreachable error is received. + /// EFI_PORT_UNREACHABLE: The connection establishment + /// timer times out and an ICMP port unreachable error is received. + /// EFI_ICMP_ERROR: The connection establishment timer times + /// out and some other ICMP error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// EFI_SECURITY_VIOLATION: The active open was failed because of IPSec policy check. + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_TCP6_COMPLETION_TOKEN CompletionToken; +} EFI_TCP6_CONNECTION_TOKEN; + +/// +/// EFI_TCP6_LISTEN_TOKEN +/// returns when list operation finishes. +/// +typedef struct { + /// + /// The Status in CompletionToken will be set to the + /// following value if accept finishes: + /// EFI_SUCCESS: A remote peer has successfully established a + /// connection to this instance. A new TCP instance has also been + /// created for the connection. + /// EFI_CONNECTION_RESET: The accept fails because the connection is reset either + /// by instance itself or communication peer. + /// EFI_ABORTED: The accept request has been aborted. + /// EFI_SECURITY_VIOLATION: The accept operation was failed because of IPSec policy check. + /// + EFI_TCP6_COMPLETION_TOKEN CompletionToken; + EFI_HANDLE NewChildHandle; +} EFI_TCP6_LISTEN_TOKEN; + +/// +/// EFI_TCP6_FRAGMENT_DATA +/// allows multiple receive or transmit buffers to be specified. The +/// purpose of this structure is to provide scattered read and write. +/// +typedef struct { + UINT32 FragmentLength; ///< Length of data buffer in the fragment. + VOID *FragmentBuffer; ///< Pointer to the data buffer in the fragment. +} EFI_TCP6_FRAGMENT_DATA; + +/// +/// EFI_TCP6_RECEIVE_DATA +/// When TCPv6 driver wants to deliver received data to the application, +/// it will pick up the first queued receiving token, update its +/// Token->Packet.RxData then signal the Token->CompletionToken.Event. +/// +typedef struct { + /// + /// Whether the data is urgent. When this flag is set, the instance is in + /// urgent mode. + /// + BOOLEAN UrgentFlag; + /// + /// When calling Receive() function, it is the byte counts of all + /// Fragmentbuffer in FragmentTable allocated by user. + /// When the token is signaled by TCPv6 driver it is the length of + /// received data in the fragments. + /// + UINT32 DataLength; + /// + /// Number of fragments. + /// + UINT32 FragmentCount; + /// + /// An array of fragment descriptors. + /// + EFI_TCP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_TCP6_RECEIVE_DATA; + +/// +/// EFI_TCP6_TRANSMIT_DATA +/// The EFI TCPv6 Protocol user must fill this data structure before sending a packet. +/// The packet may contain multiple buffers in non-continuous memory locations. +/// +typedef struct { + /// + /// Push If TRUE, data must be transmitted promptly, and the PUSH bit in + /// the last TCP segment created will be set. If FALSE, data + /// transmission may be delayed to combine with data from + /// subsequent Transmit()s for efficiency. + /// + BOOLEAN Push; + /// + /// The data in the fragment table are urgent and urgent point is in + /// effect if TRUE. Otherwise those data are NOT considered urgent. + /// + BOOLEAN Urgent; + /// + /// Length of the data in the fragments. + /// + UINT32 DataLength; + /// + /// Number of fragments. + /// + UINT32 FragmentCount; + /// + /// An array of fragment descriptors. + /// + EFI_TCP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_TCP6_TRANSMIT_DATA; + +/// +/// EFI_TCP6_IO_TOKEN +/// returns When transmission finishes or meets any unexpected error. +/// +typedef struct { + /// + /// When transmission finishes or meets any unexpected error it will + /// be set to one of the following values: + /// EFI_SUCCESS: The receiving or transmission operation + /// completes successfully. + /// EFI_CONNECTION_FIN: The receiving operation fails because the communication peer + /// has closed the connection and there is no more data in the + /// receive buffer of the instance. + /// EFI_CONNECTION_RESET: The receiving or transmission operation fails + /// because this connection is reset either by instance + /// itself or the communication peer. + /// EFI_ABORTED: The receiving or transmission is aborted. + /// EFI_TIMEOUT: The transmission timer expires and no more + /// specific information is available. + /// EFI_NETWORK_UNREACHABLE: The transmission fails + /// because an ICMP network unreachable error is received. + /// EFI_HOST_UNREACHABLE: The transmission fails because an + /// ICMP host unreachable error is received. + /// EFI_PROTOCOL_UNREACHABLE: The transmission fails + /// because an ICMP protocol unreachable error is received. + /// EFI_PORT_UNREACHABLE: The transmission fails and an + /// ICMP port unreachable error is received. + /// EFI_ICMP_ERROR: The transmission fails and some other + /// ICMP error is received. + /// EFI_DEVICE_ERROR: An unexpected system or network error occurs. + /// EFI_SECURITY_VIOLATION: The receiving or transmission + /// operation was failed because of IPSec policy check + /// EFI_NO_MEDIA: There was a media error. + /// + EFI_TCP6_COMPLETION_TOKEN CompletionToken; + union { + /// + /// When this token is used for receiving, RxData is a pointer to + /// EFI_TCP6_RECEIVE_DATA. + /// + EFI_TCP6_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to + /// EFI_TCP6_TRANSMIT_DATA. + /// + EFI_TCP6_TRANSMIT_DATA *TxData; + } Packet; +} EFI_TCP6_IO_TOKEN; + +/// +/// EFI_TCP6_CLOSE_TOKEN +/// returns when close operation finishes. +/// +typedef struct { + /// + /// When close finishes or meets any unexpected error it will be set + /// to one of the following values: + /// EFI_SUCCESS: The close operation completes successfully. + /// EFI_ABORTED: User called configure with NULL without close stopping. + /// EFI_SECURITY_VIOLATION: The close operation was failed because of IPSec policy check. + /// + EFI_TCP6_COMPLETION_TOKEN CompletionToken; + /// + /// Abort the TCP connection on close instead of the standard TCP + /// close process when it is set to TRUE. This option can be used to + /// satisfy a fast disconnect. + /// + BOOLEAN AbortOnClose; +} EFI_TCP6_CLOSE_TOKEN; + +/** + Get the current operational status. + + The GetModeData() function copies the current operational settings of this EFI TCPv6 + Protocol instance into user-supplied buffers. This function can also be used to retrieve + the operational setting of underlying drivers such as IPv6, MNP, or SNP. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[out] Tcp6State The buffer in which the current TCP state is returned. + @param[out] Tcp6ConfigData The buffer in which the current TCP configuration is returned. + @param[out] Ip6ModeData The buffer in which the current IPv6 configuration data used by + the TCP instance is returned. + @param[out] MnpConfigData The buffer in which the current MNP configuration data used + indirectly by the TCP instance is returned. + @param[out] SnpModeData The buffer in which the current SNP mode data used indirectly by + the TCP instance is returned. + + @retval EFI_SUCCESS The mode data was read. + @retval EFI_NOT_STARTED No configuration data is available because this instance hasn't + been started. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_GET_MODE_DATA)( + IN EFI_TCP6_PROTOCOL *This, + OUT EFI_TCP6_CONNECTION_STATE *Tcp6State OPTIONAL, + OUT EFI_TCP6_CONFIG_DATA *Tcp6ConfigData OPTIONAL, + OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + +/** + Initialize or brutally reset the operational parameters for this EFI TCPv6 instance. + + The Configure() function does the following: + - Initialize this TCP instance, i.e., initialize the communication end settings and + specify active open or passive open for an instance. + - Reset this TCP instance brutally, i.e., cancel all pending asynchronous tokens, flush + transmission and receiving buffer directly without informing the communication peer. + + No other TCPv6 Protocol operation except Poll() can be executed by this instance until + it is configured properly. For an active TCP instance, after a proper configuration it + may call Connect() to initiates the three-way handshake. For a passive TCP instance, + its state will transit to Tcp6StateListen after configuration, and Accept() may be + called to listen the incoming TCP connection requests. If Tcp6ConfigData is set to NULL, + the instance is reset. Resetting process will be done brutally, the state machine will + be set to Tcp6StateClosed directly, the receive queue and transmit queue will be flushed, + and no traffic is allowed through this instance. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] Tcp6ConfigData Pointer to the configure data to configure the instance. + If Tcp6ConfigData is set to NULL, the instance is reset. + + @retval EFI_SUCCESS The operational settings are set, changed, or reset + successfully. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for + use. + @retval EFI_INVALID_PARAMETER One or more of the following conditions are TRUE: + - This is NULL. + - Tcp6ConfigData->AccessPoint.StationAddress is neither zero nor + one of the configured IP addresses in the underlying IPv6 driver. + - Tcp6ConfigData->AccessPoint.RemoteAddress isn't a valid unicast + IPv6 address. + - Tcp6ConfigData->AccessPoint.RemoteAddress is zero or + Tcp6ConfigData->AccessPoint.RemotePort is zero when + Tcp6ConfigData->AccessPoint.ActiveFlag is TRUE. + - A same access point has been configured in other TCP + instance properly. + @retval EFI_ACCESS_DENIED Configuring TCP instance when it is configured without + calling Configure() with NULL to reset it. + @retval EFI_UNSUPPORTED One or more of the control options are not supported in + the implementation. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough system resources when + executing Configure(). + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_CONFIGURE)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_CONFIG_DATA *Tcp6ConfigData OPTIONAL + ); + +/** + Initiate a nonblocking TCP connection request for an active TCP instance. + + The Connect() function will initiate an active open to the remote peer configured + in current TCP instance if it is configured active. If the connection succeeds or + fails due to any error, the ConnectionToken->CompletionToken.Event will be signaled + and ConnectionToken->CompletionToken.Status will be updated accordingly. This + function can only be called for the TCP instance in Tcp6StateClosed state. The + instance will transfer into Tcp6StateSynSent if the function returns EFI_SUCCESS. + If TCP three-way handshake succeeds, its state will become Tcp6StateEstablished, + otherwise, the state will return to Tcp6StateClosed. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] ConnectionToken Pointer to the connection token to return when the TCP three + way handshake finishes. + + @retval EFI_SUCCESS The connection request is successfully initiated and the state of + this TCP instance has been changed to Tcp6StateSynSent. + @retval EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following conditions are TRUE: + - This instance is not configured as an active one. + - This instance is not in Tcp6StateClosed state. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - ConnectionToken is NULL. + - ConnectionToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The driver can't allocate enough resource to initiate the active open. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_CONNECT)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_CONNECTION_TOKEN *ConnectionToken + ); + +/** + Listen on the passive instance to accept an incoming connection request. This is a + nonblocking operation. + + The Accept() function initiates an asynchronous accept request to wait for an incoming + connection on the passive TCP instance. If a remote peer successfully establishes a + connection with this instance, a new TCP instance will be created and its handle will + be returned in ListenToken->NewChildHandle. The newly created instance is configured + by inheriting the passive instance's configuration and is ready for use upon return. + The new instance is in the Tcp6StateEstablished state. + + The ListenToken->CompletionToken.Event will be signaled when a new connection is + accepted, user aborts the listen or connection is reset. + + This function only can be called when current TCP instance is in Tcp6StateListen state. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] ListenToken Pointer to the listen token to return when operation finishes. + + + @retval EFI_SUCCESS The listen token has been queued successfully. + @retval EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following are TRUE: + - This instance is not a passive instance. + - This instance is not in Tcp6StateListen state. + - The same listen token has already existed in the listen + token queue of this TCP instance. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - ListenToken is NULL. + - ListentToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR Any unexpected and not belonged to above category error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_ACCEPT)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_LISTEN_TOKEN *ListenToken + ); + +/** + Queues outgoing data into the transmit queue. + + The Transmit() function queues a sending request to this TCP instance along with the + user data. The status of the token is updated and the event in the token will be + signaled once the data is sent out or some error occurs. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] Token Pointer to the completion token to queue to the transmit queue. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been configured. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a + source address for this instance, but no source address was + available for use. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - Token is NULL. + - Token->CompletionToken.Event is NULL. + - Token->Packet.TxData is NULL. + - Token->Packet.FragmentCount is zero. + - Token->Packet.DataLength is not equal to the sum of fragment lengths. + @retval EFI_ACCESS_DENIED One or more of the following conditions are TRUE: + - A transmit completion token with the same Token-> + CompletionToken.Event was already in the + transmission queue. + - The current instance is in Tcp6StateClosed state. + - The current instance is a passive one and it is in + Tcp6StateListen state. + - User has called Close() to disconnect this connection. + @retval EFI_NOT_READY The completion token could not be queued because the + transmit queue is full. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data because of resource + shortage. + @retval EFI_NETWORK_UNREACHABLE There is no route to the destination network or address. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_TRANSMIT)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_IO_TOKEN *Token + ); + +/** + Places an asynchronous receive request into the receiving queue. + + The Receive() function places a completion token into the receive packet queue. This + function is always asynchronous. The caller must allocate the Token->CompletionToken.Event + and the FragmentBuffer used to receive data. The caller also must fill the DataLength which + represents the whole length of all FragmentBuffer. When the receive operation completes, the + EFI TCPv6 Protocol driver updates the Token->CompletionToken.Status and Token->Packet.RxData + fields and the Token->CompletionToken.Event is signaled. If got data the data and its length + will be copied into the FragmentTable, at the same time the full length of received data will + be recorded in the DataLength fields. Providing a proper notification function and context + for the event will enable the user to receive the notification and receiving status. That + notification function is guaranteed to not be re-entered. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] Token Pointer to a token that is associated with the receive data + descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been configured. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - Token is NULL. + - Token->CompletionToken.Event is NULL. + - Token->Packet.RxData is NULL. + - Token->Packet.RxData->DataLength is 0. + - The Token->Packet.RxData->DataLength is not the + sum of all FragmentBuffer length in FragmentTable. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of + system resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + The EFI TCPv6 Protocol instance has been reset to startup defaults. + @retval EFI_ACCESS_DENIED One or more of the following conditions is TRUE: + - A receive completion token with the same Token->CompletionToken.Event + was already in the receive queue. + - The current instance is in Tcp6StateClosed state. + - The current instance is a passive one and it is in + Tcp6StateListen state. + - User has called Close() to disconnect this connection. + @retval EFI_CONNECTION_FIN The communication peer has closed the connection and there is no + any buffered data in the receive buffer of this instance + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_RECEIVE)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_IO_TOKEN *Token + ); + +/** + Disconnecting a TCP connection gracefully or reset a TCP connection. This function is a + nonblocking operation. + + Initiate an asynchronous close token to TCP driver. After Close() is called, any buffered + transmission data will be sent by TCP driver and the current instance will have a graceful close + working flow described as RFC 793 if AbortOnClose is set to FALSE, otherwise, a rest packet + will be sent by TCP driver to fast disconnect this connection. When the close operation completes + successfully the TCP instance is in Tcp6StateClosed state, all pending asynchronous + operations are signaled and any buffers used for TCP network traffic are flushed. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] CloseToken Pointer to the close token to return when operation finishes. + + @retval EFI_SUCCESS The Close() is called successfully. + @retval EFI_NOT_STARTED This EFI TCPv6 Protocol instance has not been configured. + @retval EFI_ACCESS_DENIED One or more of the following are TRUE: + - CloseToken or CloseToken->CompletionToken.Event is already in use. + - Previous Close() call on this instance has not finished. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - CloseToken is NULL. + - CloseToken->CompletionToken.Event is NULL. + @retval EFI_OUT_OF_RESOURCES Could not allocate enough resource to finish the operation. + @retval EFI_DEVICE_ERROR Any unexpected and not belonged to above category error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_CLOSE)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_CLOSE_TOKEN *CloseToken + ); + +/** + Abort an asynchronous connection, listen, transmission or receive request. + + The Cancel() function aborts a pending connection, listen, transmit or + receive request. + + If Token is not NULL and the token is in the connection, listen, transmission + or receive queue when it is being cancelled, its Token->Status will be set + to EFI_ABORTED and then Token->Event will be signaled. + + If the token is not in one of the queues, which usually means that the + asynchronous operation has completed, EFI_NOT_FOUND is returned. + + If Token is NULL all asynchronous token issued by Connect(), Accept(), + Transmit() and Receive() will be aborted. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + @param[in] Token Pointer to a token that has been issued by + EFI_TCP6_PROTOCOL.Connect(), + EFI_TCP6_PROTOCOL.Accept(), + EFI_TCP6_PROTOCOL.Transmit() or + EFI_TCP6_PROTOCOL.Receive(). If NULL, all pending + tokens issued by above four functions will be aborted. Type + EFI_TCP6_COMPLETION_TOKEN is defined in + EFI_TCP_PROTOCOL.Connect(). + + @retval EFI_SUCCESS The asynchronous I/O request is aborted and Token->Event + is signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance hasn't been configured. + @retval EFI_NOT_FOUND The asynchronous I/O request isn't found in the transmission or + receive queue. It has either completed or wasn't issued by + Transmit() and Receive(). + @retval EFI_UNSUPPORTED The implementation does not support this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_CANCEL)( + IN EFI_TCP6_PROTOCOL *This, + IN EFI_TCP6_COMPLETION_TOKEN *Token OPTIONAL + ); + +/** + Poll to receive incoming data and transmit outgoing segments. + + The Poll() function increases the rate that data is moved between the network + and application and can be called when the TCP instance is created successfully. + Its use is optional. + + @param[in] This Pointer to the EFI_TCP6_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_NOT_READY No incoming or outgoing data is processed. + @retval EFI_TIMEOUT Data was dropped out of the transmission or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TCP6_POLL)( + IN EFI_TCP6_PROTOCOL *This + ); + +/// +/// EFI_TCP6_PROTOCOL +/// defines the EFI TCPv6 Protocol child to be used by any network drivers or +/// applications to send or receive data stream. It can either listen on a +/// specified port as a service or actively connect to remote peer as a client. +/// Each instance has its own independent settings. +/// +struct _EFI_TCP6_PROTOCOL { + EFI_TCP6_GET_MODE_DATA GetModeData; + EFI_TCP6_CONFIGURE Configure; + EFI_TCP6_CONNECT Connect; + EFI_TCP6_ACCEPT Accept; + EFI_TCP6_TRANSMIT Transmit; + EFI_TCP6_RECEIVE Receive; + EFI_TCP6_CLOSE Close; + EFI_TCP6_CANCEL Cancel; + EFI_TCP6_POLL Poll; +}; + +extern EFI_GUID gEfiTcp6ServiceBindingProtocolGuid; +extern EFI_GUID gEfiTcp6ProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timer.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timer.h new file mode 100644 index 0000000000..38c0ffe1d9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timer.h @@ -0,0 +1,174 @@ +/** @file + Timer Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + This code is used to provide the timer tick for the DXE core. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_TIMER_H__ +#define __ARCH_PROTOCOL_TIMER_H__ + +/// +/// Global ID for the Timer Architectural Protocol +/// +#define EFI_TIMER_ARCH_PROTOCOL_GUID \ + { 0x26baccb3, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } + +/// +/// Declare forward reference for the Timer Architectural Protocol +/// +typedef struct _EFI_TIMER_ARCH_PROTOCOL EFI_TIMER_ARCH_PROTOCOL; + +/** + This function of this type is called when a timer interrupt fires. This + function executes at TPL_HIGH_LEVEL. The DXE Core will register a function + of this type to be called for the timer interrupt, so it can know how much + time has passed. This information is used to signal timer based events. + + @param Time Time since the last timer interrupt in 100 ns units. This will + typically be TimerPeriod, but if a timer interrupt is missed, and the + EFI_TIMER_ARCH_PROTOCOL driver can detect missed interrupts, then Time + will contain the actual amount of time since the last interrupt. + + None. + +**/ +typedef +VOID +(EFIAPI *EFI_TIMER_NOTIFY)( + IN UINT64 Time + ); + +/** + This function registers the handler NotifyFunction so it is called every time + the timer interrupt fires. It also passes the amount of time since the last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS is + returned. If the CPU does not support registering a timer interrupt handler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler + when a handler is already registered, then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not registered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fires. This + function executes at TPL_HIGH_LEVEL. The DXE Core will + register a handler for the timer interrupt, so it can know + how much time has passed. This information is used to + signal timer based events. NULL will unregister the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support timer interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TIMER_REGISTER_HANDLER)( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction +); + +/** + This function adjusts the period of timer interrupts to the value specified + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust the + interrupt controller so that a CPU interrupt is not generated when the timer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is + returned. If the timer is programmable, then the timer period + will be rounded up to the nearest timer period that is supported + by the timer hardware. If TimerPeriod is set to 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TIMER_SET_TIMER_PERIOD)( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ); + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If + 0 is returned, then the timer is currently disabled. + + @retval EFI_SUCCESS The timer period was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TIMER_GET_TIMER_PERIOD)( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ); + +/** + This function generates a soft timer interrupt. If the platform does not support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() + service, then a soft timer interrupt will be generated. If the timer interrupt is + enabled when this service is called, then the registered handler will be invoked. The + registered handler should not be able to distinguish a hardware-generated timer + interrupt from a software-generated timer interrupt. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TIMER_GENERATE_SOFT_INTERRUPT)( + IN EFI_TIMER_ARCH_PROTOCOL *This + ); + + +/// +/// This protocol provides the services to initialize a periodic timer +/// interrupt, and to register a handler that is called each time the timer +/// interrupt fires. It may also provide a service to adjust the rate of the +/// periodic timer interrupt. When a timer interrupt occurs, the handler is +/// passed the amount of time that has passed since the previous timer +/// interrupt. +/// +struct _EFI_TIMER_ARCH_PROTOCOL { + EFI_TIMER_REGISTER_HANDLER RegisterHandler; + EFI_TIMER_SET_TIMER_PERIOD SetTimerPeriod; + EFI_TIMER_GET_TIMER_PERIOD GetTimerPeriod; + EFI_TIMER_GENERATE_SOFT_INTERRUPT GenerateSoftInterrupt; +}; + +extern EFI_GUID gEfiTimerArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timestamp.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timestamp.h new file mode 100644 index 0000000000..38f60bc876 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Timestamp.h @@ -0,0 +1,95 @@ +/** @file + EFI Timestamp Protocol as defined in UEFI2.4 Specification. + Used to provide a platform independent interface for retrieving a high resolution timestamp counter. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.4 + +**/ + +#ifndef __EFI_TIME_STAMP_PROTOCOL_H__ +#define __EFI_TIME_STAMP_PROTOCOL_H__ + + +#define EFI_TIMESTAMP_PROTOCOL_GUID \ + { 0xafbfde41, 0x2e6e, 0x4262, {0xba, 0x65, 0x62, 0xb9, 0x23, 0x6e, 0x54, 0x95 } } + +/// +/// Declare forward reference for the Time Stamp Protocol +/// +typedef struct _EFI_TIMESTAMP_PROTOCOL EFI_TIMESTAMP_PROTOCOL; + +/// +/// EFI_TIMESTAMP_PROPERTIES +/// +typedef struct { + /// + /// The frequency of the timestamp counter in Hz. + /// + UINT64 Frequency; + /// + /// The value that the timestamp counter ends with immediately before it rolls over. + /// For example, a 64-bit free running counter would have an EndValue of 0xFFFFFFFFFFFFFFFF. + /// A 24-bit free running counter would have an EndValue of 0xFFFFFF. + /// + UINT64 EndValue; +} EFI_TIMESTAMP_PROPERTIES; + +/** + Retrieves the current value of a 64-bit free running timestamp counter. + + The counter shall count up in proportion to the amount of time that has passed. The counter value + will always roll over to zero. The properties of the counter can be retrieved from GetProperties(). + The caller should be prepared for the function to return the same value twice across successive calls. + The counter value will not go backwards other than when wrapping, as defined by EndValue in GetProperties(). + The frequency of the returned timestamp counter value must remain constant. Power management operations that + affect clocking must not change the returned counter frequency. The quantization of counter value updates may + vary as long as the value reflecting time passed remains consistent. + + @param None. + + @retval The current value of the free running timestamp counter. + +**/ +typedef +UINT64 +(EFIAPI *TIMESTAMP_GET)( + VOID + ); + +/** + Obtains timestamp counter properties including frequency and value limits. + + @param[out] Properties The properties of the timestamp counter. + + @retval EFI_SUCCESS The properties were successfully retrieved. + @retval EFI_DEVICE_ERROR An error occurred trying to retrieve the properties of the timestamp + counter subsystem. Properties is not pedated. + @retval EFI_INVALID_PARAMETER Properties is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *TIMESTAMP_GET_PROPERTIES)( + OUT EFI_TIMESTAMP_PROPERTIES *Properties + ); + + + +/// +/// EFI_TIMESTAMP_PROTOCOL +/// The protocol provides a platform independent interface for retrieving a high resolution +/// timestamp counter. +/// +struct _EFI_TIMESTAMP_PROTOCOL { + TIMESTAMP_GET GetTimestamp; + TIMESTAMP_GET_PROPERTIES GetProperties; +}; + +extern EFI_GUID gEfiTimestampProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tls.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tls.h new file mode 100644 index 0000000000..954918ea53 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Tls.h @@ -0,0 +1,511 @@ +/** @file + EFI TLS Protocols as defined in UEFI 2.5. + + The EFI TLS Service Binding Protocol is used to locate EFI TLS Protocol drivers + to create and destroy child of the driver to communicate with other host using + TLS protocol. + The EFI TLS Protocol provides the ability to manage TLS session. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_TLS_PROTOCOL_H__ +#define __EFI_TLS_PROTOCOL_H__ + +/// +/// The EFI TLS Service Binding Protocol is used to locate EFI TLS Protocol drivers to +/// create and destroy child of the driver to communicate with other host using TLS +/// protocol. +/// +#define EFI_TLS_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x952cb795, 0xff36, 0x48cf, {0xa2, 0x49, 0x4d, 0xf4, 0x86, 0xd6, 0xab, 0x8d } \ + } + +/// +/// The EFI TLS protocol provides the ability to manage TLS session. +/// +#define EFI_TLS_PROTOCOL_GUID \ + { \ + 0xca959f, 0x6cfa, 0x4db1, {0x95, 0xbc, 0xe4, 0x6c, 0x47, 0x51, 0x43, 0x90 } \ + } + +typedef struct _EFI_TLS_PROTOCOL EFI_TLS_PROTOCOL; + +/// +/// EFI_TLS_SESSION_DATA_TYPE +/// +typedef enum { + /// + /// TLS session Version. The corresponding Data is of type EFI_TLS_VERSION. + /// + EfiTlsVersion, + /// + /// TLS session as client or as server. The corresponding Data is of + /// EFI_TLS_CONNECTION_END. + /// + EfiTlsConnectionEnd, + /// + /// A priority list of preferred algorithms for the TLS session. + /// The corresponding Data is a list of EFI_TLS_CIPHER. + /// + EfiTlsCipherList, + /// + /// TLS session compression method. + /// The corresponding Data is of type EFI_TLS_COMPRESSION. + /// + EfiTlsCompressionMethod, + /// + /// TLS session extension data. + /// The corresponding Data is a list of type EFI_TLS_EXTENSION . + /// + EfiTlsExtensionData, + /// + /// TLS session verify method. + /// The corresponding Data is of type EFI_TLS_VERIFY. + /// + EfiTlsVerifyMethod, + /// + /// TLS session data session ID. + /// For SetSessionData(), it is TLS session ID used for session resumption. + /// For GetSessionData(), it is the TLS session ID used for current session. + /// The corresponding Data is of type EFI_TLS_SESSION_ID. + /// + EfiTlsSessionID, + /// + /// TLS session data session state. + /// The corresponding Data is of type EFI_TLS_SESSION_STATE. + /// + EfiTlsSessionState, + /// + /// TLS session data client random. + /// The corresponding Data is of type EFI_TLS_RANDOM. + /// + EfiTlsClientRandom, + /// + /// TLS session data server random. + /// The corresponding Data is of type EFI_TLS_RANDOM. + /// + EfiTlsServerRandom, + /// + /// TLS session data key material. + /// The corresponding Data is of type EFI_TLS_MASTER_SECRET. + /// + EfiTlsKeyMaterial, + /// + /// TLS session hostname for validation which is used to verify whether the name + /// within the peer certificate matches a given host name. + /// This parameter is invalid when EfiTlsVerifyMethod is EFI_TLS_VERIFY_NONE. + /// The corresponding Data is of type EFI_TLS_VERIFY_HOST. + /// + EfiTlsVerifyHost, + + EfiTlsSessionDataTypeMaximum +} EFI_TLS_SESSION_DATA_TYPE; + +/// +/// EFI_TLS_VERSION +/// Note: The TLS version definition is from SSL3.0 to the latest TLS (e.g. 1.2). +/// SSL2.0 is obsolete and should not be used. +/// +typedef struct { + UINT8 Major; + UINT8 Minor; +} EFI_TLS_VERSION; + +/// +/// EFI_TLS_CONNECTION_END to define TLS session as client or server. +/// +typedef enum { + EfiTlsClient, + EfiTlsServer, +} EFI_TLS_CONNECTION_END; + +/// +/// EFI_TLS_CIPHER +/// Note: The definition of EFI_TLS_CIPHER definition is from "RFC 5246, A.4.1. +/// Hello Messages". The value of EFI_TLS_CIPHER is from TLS Cipher +/// Suite Registry of IANA. +/// +#pragma pack (1) +typedef struct { + UINT8 Data1; + UINT8 Data2; +} EFI_TLS_CIPHER; +#pragma pack () + +/// +/// EFI_TLS_COMPRESSION +/// Note: The value of EFI_TLS_COMPRESSION definition is from "RFC 3749". +/// +typedef UINT8 EFI_TLS_COMPRESSION; + +/// +/// EFI_TLS_EXTENSION +/// Note: The definition of EFI_TLS_EXTENSION if from "RFC 5246 A.4.1. +/// Hello Messages". +/// +#pragma pack (1) +typedef struct { + UINT16 ExtensionType; + UINT16 Length; + UINT8 Data[1]; +} EFI_TLS_EXTENSION; +#pragma pack () + +/// +/// EFI_TLS_VERIFY +/// Use either EFI_TLS_VERIFY_NONE or EFI_TLS_VERIFY_PEER, the last two options +/// are 'ORed' with EFI_TLS_VERIFY_PEER if they are desired. +/// +typedef UINT32 EFI_TLS_VERIFY; +/// +/// No certificates will be sent or the TLS/SSL handshake will be continued regardless +/// of the certificate verification result. +/// +#define EFI_TLS_VERIFY_NONE 0x0 +/// +/// The TLS/SSL handshake is immediately terminated with an alert message containing +/// the reason for the certificate verification failure. +/// +#define EFI_TLS_VERIFY_PEER 0x1 +/// +/// EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT is only meaningful in the server mode. +/// TLS session will fail if client certificate is absent. +/// +#define EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT 0x2 +/// +/// TLS session only verify client once, and doesn't request certificate during +/// re-negotiation. +/// +#define EFI_TLS_VERIFY_CLIENT_ONCE 0x4 + +/// +/// EFI_TLS_VERIFY_HOST_FLAG +/// +typedef UINT32 EFI_TLS_VERIFY_HOST_FLAG; +/// +/// There is no additional flags set for hostname validation. +/// Wildcards are supported and they match only in the left-most label. +/// +#define EFI_TLS_VERIFY_FLAG_NONE 0x00 +/// +/// Always check the Subject Distinguished Name (DN) in the peer certificate even if the +/// certificate contains Subject Alternative Name (SAN). +/// +#define EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT 0x01 +/// +/// Disable the match of all wildcards. +/// +#define EFI_TLS_VERIFY_FLAG_NO_WILDCARDS 0x02 +/// +/// Disable the "*" as wildcard in labels that have a prefix or suffix (e.g. "www*" or "*www"). +/// +#define EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS 0x04 +/// +/// Allow the "*" to match more than one labels. Otherwise, only matches a single label. +/// +#define EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS 0x08 +/// +/// Restrict to only match direct child sub-domains which start with ".". +/// For example, a name of ".example.com" would match "www.example.com" with this flag, +/// but would not match "www.sub.example.com". +/// +#define EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS 0x10 +/// +/// Never check the Subject Distinguished Name (DN) even there is no +/// Subject Alternative Name (SAN) in the certificate. +/// +#define EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT 0x20 + +/// +/// EFI_TLS_VERIFY_HOST +/// +#pragma pack (1) +typedef struct { + EFI_TLS_VERIFY_HOST_FLAG Flags; + CHAR8 *HostName; +} EFI_TLS_VERIFY_HOST; +#pragma pack () + +/// +/// EFI_TLS_RANDOM +/// Note: The definition of EFI_TLS_RANDOM is from "RFC 5246 A.4.1. +/// Hello Messages". +/// +#pragma pack (1) +typedef struct { + UINT32 GmtUnixTime; + UINT8 RandomBytes[28]; +} EFI_TLS_RANDOM; +#pragma pack () + +/// +/// EFI_TLS_MASTER_SECRET +/// Note: The definition of EFI_TLS_MASTER_SECRET is from "RFC 5246 8.1. +/// Computing the Master Secret". +/// +#pragma pack (1) +typedef struct { + UINT8 Data[48]; +} EFI_TLS_MASTER_SECRET; +#pragma pack () + +/// +/// EFI_TLS_SESSION_ID +/// Note: The definition of EFI_TLS_SESSION_ID is from "RFC 5246 A.4.1. Hello Messages". +/// +#define MAX_TLS_SESSION_ID_LENGTH 32 +#pragma pack (1) +typedef struct { + UINT16 Length; + UINT8 Data[MAX_TLS_SESSION_ID_LENGTH]; +} EFI_TLS_SESSION_ID; +#pragma pack () + +/// +/// EFI_TLS_SESSION_STATE +/// +typedef enum { + /// + /// When a new child of TLS protocol is created, the initial state of TLS session + /// is EfiTlsSessionNotStarted. + /// + EfiTlsSessionNotStarted, + /// + /// The consumer can call BuildResponsePacket() with NULL to get ClientHello to + /// start the TLS session. Then the status is EfiTlsSessionHandShaking. + /// + EfiTlsSessionHandShaking, + /// + /// During handshake, the consumer need call BuildResponsePacket() with input + /// data from peer, then get response packet and send to peer. After handshake + /// finish, the TLS session status becomes EfiTlsSessionDataTransferring, and + /// consumer can use ProcessPacket() for data transferring. + /// + EfiTlsSessionDataTransferring, + /// + /// Finally, if consumer wants to active close TLS session, consumer need + /// call SetSessionData to set TLS session state to EfiTlsSessionClosing, and + /// call BuildResponsePacket() with NULL to get CloseNotify alert message, + /// and sent it out. + /// + EfiTlsSessionClosing, + /// + /// If any error happen during parsing ApplicationData content type, EFI_ABORT + /// will be returned by ProcessPacket(), and TLS session state will become + /// EfiTlsSessionError. Then consumer need call BuildResponsePacket() with + /// NULL to get alert message and sent it out. + /// + EfiTlsSessionError, + + EfiTlsSessionStateMaximum + +} EFI_TLS_SESSION_STATE; + +/// +/// EFI_TLS_FRAGMENT_DATA +/// +typedef struct { + /// + /// Length of data buffer in the fragment. + /// + UINT32 FragmentLength; + /// + /// Pointer to the data buffer in the fragment. + /// + VOID *FragmentBuffer; +} EFI_TLS_FRAGMENT_DATA; + +/// +/// EFI_TLS_CRYPT_MODE +/// +typedef enum { + /// + /// Encrypt data provided in the fragment buffers. + /// + EfiTlsEncrypt, + /// + /// Decrypt data provided in the fragment buffers. + /// + EfiTlsDecrypt, +} EFI_TLS_CRYPT_MODE; + +/** + Set TLS session data. + + The SetSessionData() function set data for a new TLS session. All session data should + be set before BuildResponsePacket() invoked. + + @param[in] This Pointer to the EFI_TLS_PROTOCOL instance. + @param[in] DataType TLS session data type. + @param[in] Data Pointer to session data. + @param[in] DataSize Total size of session data. + + @retval EFI_SUCCESS The TLS session data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + DataSize is 0. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_ACCESS_DENIED If the DataType is one of below: + EfiTlsClientRandom + EfiTlsServerRandom + EfiTlsKeyMaterial + @retval EFI_NOT_READY Current TLS session state is NOT + EfiTlsSessionStateNotStarted. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_SET_SESSION_DATA) ( + IN EFI_TLS_PROTOCOL *This, + IN EFI_TLS_SESSION_DATA_TYPE DataType, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get TLS session data. + + The GetSessionData() function return the TLS session information. + + @param[in] This Pointer to the EFI_TLS_PROTOCOL instance. + @param[in] DataType TLS session data type. + @param[in, out] Data Pointer to session data. + @param[in, out] DataSize Total size of session data. On input, it means + the size of Data buffer. On output, it means the size + of copied Data buffer if EFI_SUCCESS, and means the + size of desired Data buffer if EFI_BUFFER_TOO_SMALL. + + @retval EFI_SUCCESS The TLS session data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + DataSize is NULL. + Data is NULL if *DataSize is not zero. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The TLS session data is not found. + @retval EFI_NOT_READY The DataType is not ready in current session state. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the data. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_GET_SESSION_DATA) ( + IN EFI_TLS_PROTOCOL *This, + IN EFI_TLS_SESSION_DATA_TYPE DataType, + IN OUT VOID *Data, OPTIONAL + IN OUT UINTN *DataSize + ); + +/** + Build response packet according to TLS state machine. This function is only valid for + alert, handshake and change_cipher_spec content type. + + The BuildResponsePacket() function builds TLS response packet in response to the TLS + request packet specified by RequestBuffer and RequestSize. If RequestBuffer is NULL and + RequestSize is 0, and TLS session status is EfiTlsSessionNotStarted, the TLS session + will be initiated and the response packet needs to be ClientHello. If RequestBuffer is + NULL and RequestSize is 0, and TLS session status is EfiTlsSessionClosing, the TLS + session will be closed and response packet needs to be CloseNotify. If RequestBuffer is + NULL and RequestSize is 0, and TLS session status is EfiTlsSessionError, the TLS + session has errors and the response packet needs to be Alert message based on error + type. + + @param[in] This Pointer to the EFI_TLS_PROTOCOL instance. + @param[in] RequestBuffer Pointer to the most recently received TLS packet. NULL + means TLS need initiate the TLS session and response + packet need to be ClientHello. + @param[in] RequestSize Packet size in bytes for the most recently received TLS + packet. 0 is only valid when RequestBuffer is NULL. + @param[out] Buffer Pointer to the buffer to hold the built packet. + @param[in, out] BufferSize Pointer to the buffer size in bytes. On input, it is + the buffer size provided by the caller. On output, it + is the buffer size in fact needed to contain the + packet. + + @retval EFI_SUCCESS The required TLS packet is built successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + RequestBuffer is NULL but RequestSize is NOT 0. + RequestSize is 0 but RequestBuffer is NOT NULL. + BufferSize is NULL. + Buffer is NULL if *BufferSize is not zero. + @retval EFI_BUFFER_TOO_SMALL BufferSize is too small to hold the response packet. + @retval EFI_NOT_READY Current TLS session state is NOT ready to build + ResponsePacket. + @retval EFI_ABORTED Something wrong build response packet. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_BUILD_RESPONSE_PACKET) ( + IN EFI_TLS_PROTOCOL *This, + IN UINT8 *RequestBuffer, OPTIONAL + IN UINTN RequestSize, OPTIONAL + OUT UINT8 *Buffer, OPTIONAL + IN OUT UINTN *BufferSize + ); + +/** + Decrypt or encrypt TLS packet during session. This function is only valid after + session connected and for application_data content type. + + The ProcessPacket () function process each inbound or outbound TLS APP packet. + + @param[in] This Pointer to the EFI_TLS_PROTOCOL instance. + @param[in, out] FragmentTable Pointer to a list of fragment. The caller will take + responsible to handle the original FragmentTable while + it may be reallocated in TLS driver. If CryptMode is + EfiTlsEncrypt, on input these fragments contain the TLS + header and plain text TLS APP payload; on output these + fragments contain the TLS header and cipher text TLS + APP payload. If CryptMode is EfiTlsDecrypt, on input + these fragments contain the TLS header and cipher text + TLS APP payload; on output these fragments contain the + TLS header and plain text TLS APP payload. + @param[in] FragmentCount Number of fragment. + @param[in] CryptMode Crypt mode. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + FragmentTable is NULL. + FragmentCount is NULL. + CryptoMode is invalid. + @retval EFI_NOT_READY Current TLS session state is NOT + EfiTlsSessionDataTransferring. + @retval EFI_ABORTED Something wrong decryption the message. TLS session + status will become EfiTlsSessionError. The caller need + call BuildResponsePacket() to generate Error Alert + message and send it out. + @retval EFI_OUT_OF_RESOURCES No enough resource to finish the operation. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_PROCESS_PACKET) ( + IN EFI_TLS_PROTOCOL *This, + IN OUT EFI_TLS_FRAGMENT_DATA **FragmentTable, + IN UINT32 *FragmentCount, + IN EFI_TLS_CRYPT_MODE CryptMode + ); + +/// +/// The EFI_TLS_PROTOCOL is used to create, destroy and manage TLS session. +/// For detail of TLS, please refer to TLS related RFC. +/// +struct _EFI_TLS_PROTOCOL { + EFI_TLS_SET_SESSION_DATA SetSessionData; + EFI_TLS_GET_SESSION_DATA GetSessionData; + EFI_TLS_BUILD_RESPONSE_PACKET BuildResponsePacket; + EFI_TLS_PROCESS_PACKET ProcessPacket; +}; + +extern EFI_GUID gEfiTlsServiceBindingProtocolGuid; +extern EFI_GUID gEfiTlsProtocolGuid; + +#endif // __EFI_TLS_PROTOCOL_H__ + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TlsConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TlsConfig.h new file mode 100644 index 0000000000..367a13751c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TlsConfig.h @@ -0,0 +1,127 @@ +/** @file + EFI TLS Configuration Protocol as defined in UEFI 2.5. + The EFI TLS Configuration Protocol provides a way to set and get TLS configuration. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ +#ifndef __EFI_TLS_CONFIGURATION_PROTOCOL_H__ +#define __EFI_TLS_CONFIGURATION_PROTOCOL_H__ + +/// +/// The EFI Configuration protocol provides a way to set and get TLS configuration. +/// +#define EFI_TLS_CONFIGURATION_PROTOCOL_GUID \ + { \ + 0x1682fe44, 0xbd7a, 0x4407, { 0xb7, 0xc7, 0xdc, 0xa3, 0x7c, 0xa3, 0x92, 0x2d } \ + } + +typedef struct _EFI_TLS_CONFIGURATION_PROTOCOL EFI_TLS_CONFIGURATION_PROTOCOL; + +/// +/// EFI_TLS_CONFIG_DATA_TYPE +/// +typedef enum { + /// + /// Local host configuration data: public certificate data. + /// This data should be DER-encoded binary X.509 certificate + /// or PEM-encoded X.509 certificate. + /// + EfiTlsConfigDataTypeHostPublicCert, + /// + /// Local host configuration data: private key data. + /// + EfiTlsConfigDataTypeHostPrivateKey, + /// + /// CA certificate to verify peer. This data should be PEM-encoded + /// RSA or PKCS#8 private key. + /// + EfiTlsConfigDataTypeCACertificate, + /// + /// CA-supplied Certificate Revocation List data. This data should + /// be DER-encoded CRL data. + /// + EfiTlsConfigDataTypeCertRevocationList, + + EfiTlsConfigDataTypeMaximum + +} EFI_TLS_CONFIG_DATA_TYPE; + +/** + Set TLS configuration data. + + The SetData() function sets TLS configuration to non-volatile storage or volatile + storage. + + @param[in] This Pointer to the EFI_TLS_CONFIGURATION_PROTOCOL instance. + @param[in] DataType Configuration data type. + @param[in] Data Pointer to configuration data. + @param[in] DataSize Total size of configuration data. + + @retval EFI_SUCCESS The TLS configuration data is set successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + DataSize is 0. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_CONFIGURATION_SET_DATA)( + IN EFI_TLS_CONFIGURATION_PROTOCOL *This, + IN EFI_TLS_CONFIG_DATA_TYPE DataType, + IN VOID *Data, + IN UINTN DataSize + ); + +/** + Get TLS configuration data. + + The GetData() function gets TLS configuration. + + @param[in] This Pointer to the EFI_TLS_CONFIGURATION_PROTOCOL instance. + @param[in] DataType Configuration data type. + @param[in, out] Data Pointer to configuration data. + @param[in, out] DataSize Total size of configuration data. On input, it means + the size of Data buffer. On output, it means the size + of copied Data buffer if EFI_SUCCESS, and means the + size of desired Data buffer if EFI_BUFFER_TOO_SMALL. + + @retval EFI_SUCCESS The TLS configuration data is got successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + DataSize is NULL. + Data is NULL if *DataSize is not zero. + @retval EFI_UNSUPPORTED The DataType is unsupported. + @retval EFI_NOT_FOUND The TLS configuration data is not found. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the data. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TLS_CONFIGURATION_GET_DATA)( + IN EFI_TLS_CONFIGURATION_PROTOCOL *This, + IN EFI_TLS_CONFIG_DATA_TYPE DataType, + IN OUT VOID *Data, OPTIONAL + IN OUT UINTN *DataSize + ); + +/// +/// The EFI_TLS_CONFIGURATION_PROTOCOL is designed to provide a way to set and get +/// TLS configuration, such as Certificate, private key data. +/// +struct _EFI_TLS_CONFIGURATION_PROTOCOL { + EFI_TLS_CONFIGURATION_SET_DATA SetData; + EFI_TLS_CONFIGURATION_GET_DATA GetData; +}; + +extern EFI_GUID gEfiTlsConfigurationProtocolGuid; + +#endif //__EFI_TLS_CONFIGURATION_PROTOCOL_H__ + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TrEEProtocol.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TrEEProtocol.h new file mode 100644 index 0000000000..db86c1cdc2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/TrEEProtocol.h @@ -0,0 +1,243 @@ +/** @file + This protocol is defined to abstract TPM2 hardware access in boot phase. + +Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __TREE_H__ +#define __TREE_H__ + +#include +#include + +#define EFI_TREE_PROTOCOL_GUID \ + {0x607f766c, 0x7455, 0x42be, 0x93, 0x0b, 0xe4, 0xd7, 0x6d, 0xb2, 0x72, 0x0f} + +typedef struct _EFI_TREE_PROTOCOL EFI_TREE_PROTOCOL; + +typedef struct _TREE_VERSION { + UINT8 Major; + UINT8 Minor; +} TREE_VERSION; + +typedef UINT32 TREE_EVENT_LOG_BITMAP; +typedef UINT32 TREE_EVENT_LOG_FORMAT; + +#define TREE_EVENT_LOG_FORMAT_TCG_1_2 0x00000001 + +typedef struct _TREE_BOOT_SERVICE_CAPABILITY { + // + // Allocated size of the structure passed in + // + UINT8 Size; + // + // Version of the TREE_BOOT_SERVICE_CAPABILITY structure itself. + // For this version of the protocol, the Major version shall be set to 1 + // and the Minor version shall be set to 0. + // + TREE_VERSION StructureVersion; + // + // Version of the TrEE protocol. + // For this version of the protocol, the Major version shall be set to 1 + // and the Minor version shall be set to 0. + // + TREE_VERSION ProtocolVersion; + // + // Supported hash algorithms + // + UINT32 HashAlgorithmBitmap; + // + // Bitmap of supported event log formats + // + TREE_EVENT_LOG_BITMAP SupportedEventLogs; + // + // False = TrEE not present + // + BOOLEAN TrEEPresentFlag; + // + // Max size (in bytes) of a command that can be sent to the TrEE + // + UINT16 MaxCommandSize; + // + // Max size (in bytes) of a response that can be provided by the TrEE + // + UINT16 MaxResponseSize; + // + // 4-byte Vendor ID (see Trusted Computing Group, "TCG Vendor ID Registry," + // Version 1.0, Revision 0.1, August 31, 2007, "TPM Capabilities Vendor ID" section) + // + UINT32 ManufacturerID; +} TREE_BOOT_SERVICE_CAPABILITY_1_0; + +typedef TREE_BOOT_SERVICE_CAPABILITY_1_0 TREE_BOOT_SERVICE_CAPABILITY; + +#define TREE_BOOT_HASH_ALG_SHA1 0x00000001 +#define TREE_BOOT_HASH_ALG_SHA256 0x00000002 +#define TREE_BOOT_HASH_ALG_SHA384 0x00000004 +#define TREE_BOOT_HASH_ALG_SHA512 0x00000008 + +// +// This bit is shall be set when an event shall be extended but not logged. +// +#define TREE_EXTEND_ONLY 0x0000000000000001 +// +// This bit shall be set when the intent is to measure a PE/COFF image. +// +#define PE_COFF_IMAGE 0x0000000000000010 + +typedef UINT32 TrEE_PCRINDEX; +typedef UINT32 TrEE_EVENTTYPE; + +#define MAX_PCR_INDEX 23 +#define TREE_EVENT_HEADER_VERSION 1 + +#pragma pack(1) + +typedef struct { + // + // Size of the event header itself (sizeof(TrEE_EVENT_HEADER)). + // + UINT32 HeaderSize; + // + // Header version. For this version of this specification, the value shall be 1. + // + UINT16 HeaderVersion; + // + // Index of the PCR that shall be extended (0 - 23). + // + TrEE_PCRINDEX PCRIndex; + // + // Type of the event that shall be extended (and optionally logged). + // + TrEE_EVENTTYPE EventType; +} TrEE_EVENT_HEADER; + +typedef struct { + // + // Total size of the event including the Size component, the header and the Event data. + // + UINT32 Size; + TrEE_EVENT_HEADER Header; + UINT8 Event[1]; +} TrEE_EVENT; + +#pragma pack() + +/** + The EFI_TREE_PROTOCOL GetCapability function call provides protocol + capability information and state information about the TrEE. + + @param[in] This Indicates the calling context + @param[out] ProtocolCapability The caller allocates memory for a TREE_BOOT_SERVICE_CAPABILITY + structure and sets the size field to the size of the structure allocated. + The callee fills in the fields with the EFI protocol capability information + and the current TrEE state information up to the number of fields which + fit within the size of the structure passed in. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + The ProtocolCapability variable will not be populated. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + The ProtocolCapability variable will not be populated. + @retval EFI_BUFFER_TOO_SMALL The ProtocolCapability variable is too small to hold the full response. + It will be partially populated (required Size field will be set). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TREE_GET_CAPABILITY) ( + IN EFI_TREE_PROTOCOL *This, + IN OUT TREE_BOOT_SERVICE_CAPABILITY *ProtocolCapability + ); + +/** + The EFI_TREE_PROTOCOL Get Event Log function call allows a caller to + retrieve the address of a given event log and its last entry. + + @param[in] This Indicates the calling context + @param[in] EventLogFormat The type of the event log for which the information is requested. + @param[out] EventLogLocation A pointer to the memory address of the event log. + @param[out] EventLogLastEntry If the Event Log contains more than one entry, this is a pointer to the + address of the start of the last entry in the event log in memory. + @param[out] EventLogTruncated If the Event Log is missing at least one entry because an event would + have exceeded the area allocated for events, this value is set to TRUE. + Otherwise, the value will be FALSE and the Event Log will be complete. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect + (e.g. asking for an event log whose format is not supported). +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TREE_GET_EVENT_LOG) ( + IN EFI_TREE_PROTOCOL *This, + IN TREE_EVENT_LOG_FORMAT EventLogFormat, + OUT EFI_PHYSICAL_ADDRESS *EventLogLocation, + OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry, + OUT BOOLEAN *EventLogTruncated + ); + +/** + The EFI_TREE_PROTOCOL HashLogExtendEvent function call provides callers with + an opportunity to extend and optionally log events without requiring + knowledge of actual TPM commands. + The extend operation will occur even if this function cannot create an event + log entry (e.g. due to the event log being full). + + @param[in] This Indicates the calling context + @param[in] Flags Bitmap providing additional information. + @param[in] DataToHash Physical address of the start of the data buffer to be hashed. + @param[in] DataToHashLen The length in bytes of the buffer referenced by DataToHash. + @param[in] Event Pointer to data buffer containing information about the event. + + @retval EFI_SUCCESS Operation completed successfully. + @retval EFI_DEVICE_ERROR The command was unsuccessful. + @retval EFI_VOLUME_FULL The extend operation occurred, but the event could not be written to one or more event logs. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_UNSUPPORTED The PE/COFF image type is not supported. +**/ +typedef +EFI_STATUS +(EFIAPI * EFI_TREE_HASH_LOG_EXTEND_EVENT) ( + IN EFI_TREE_PROTOCOL *This, + IN UINT64 Flags, + IN EFI_PHYSICAL_ADDRESS DataToHash, + IN UINT64 DataToHashLen, + IN TrEE_EVENT *Event + ); + +/** + This service enables the sending of commands to the TrEE. + + @param[in] This Indicates the calling context + @param[in] InputParameterBlockSize Size of the TrEE input parameter block. + @param[in] InputParameterBlock Pointer to the TrEE input parameter block. + @param[in] OutputParameterBlockSize Size of the TrEE output parameter block. + @param[in] OutputParameterBlock Pointer to the TrEE output parameter block. + + @retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received. + @retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_TREE_SUBMIT_COMMAND) ( + IN EFI_TREE_PROTOCOL *This, + IN UINT32 InputParameterBlockSize, + IN UINT8 *InputParameterBlock, + IN UINT32 OutputParameterBlockSize, + IN UINT8 *OutputParameterBlock + ); + +struct _EFI_TREE_PROTOCOL { + EFI_TREE_GET_CAPABILITY GetCapability; + EFI_TREE_GET_EVENT_LOG GetEventLog; + EFI_TREE_HASH_LOG_EXTEND_EVENT HashLogExtendEvent; + EFI_TREE_SUBMIT_COMMAND SubmitCommand; +}; + +extern EFI_GUID gEfiTrEEProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp4.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp4.h new file mode 100644 index 0000000000..7a3bc418cb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp4.h @@ -0,0 +1,439 @@ +/** @file + UDP4 Service Binding Protocol as defined in UEFI specification. + + The EFI UDPv4 Protocol provides simple packet-oriented services + to transmit and receive UDP packets. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.0. + +**/ + +#ifndef __EFI_UDP4_PROTOCOL_H__ +#define __EFI_UDP4_PROTOCOL_H__ + +#include +// +//GUID definitions +// +#define EFI_UDP4_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x83f01464, 0x99bd, 0x45e5, {0xb3, 0x83, 0xaf, 0x63, 0x05, 0xd8, 0xe9, 0xe6 } \ + } + +#define EFI_UDP4_PROTOCOL_GUID \ + { \ + 0x3ad9df29, 0x4501, 0x478d, {0xb1, 0xf8, 0x7f, 0x7f, 0xe7, 0x0e, 0x50, 0xf3 } \ + } + +typedef struct _EFI_UDP4_PROTOCOL EFI_UDP4_PROTOCOL; + +/// +/// EFI_UDP4_SERVICE_POINT is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE InstanceHandle; + EFI_IPv4_ADDRESS LocalAddress; + UINT16 LocalPort; + EFI_IPv4_ADDRESS RemoteAddress; + UINT16 RemotePort; +} EFI_UDP4_SERVICE_POINT; + +/// +/// EFI_UDP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + EFI_HANDLE DriverHandle; + UINT32 ServiceCount; + EFI_UDP4_SERVICE_POINT Services[1]; +} EFI_UDP4_VARIABLE_DATA; + +typedef struct { + UINT32 FragmentLength; + VOID *FragmentBuffer; +} EFI_UDP4_FRAGMENT_DATA; + +typedef struct { + EFI_IPv4_ADDRESS SourceAddress; + UINT16 SourcePort; + EFI_IPv4_ADDRESS DestinationAddress; + UINT16 DestinationPort; +} EFI_UDP4_SESSION_DATA; +typedef struct { + // + // Receiving Filters + // + BOOLEAN AcceptBroadcast; + BOOLEAN AcceptPromiscuous; + BOOLEAN AcceptAnyPort; + BOOLEAN AllowDuplicatePort; + // + // I/O parameters + // + UINT8 TypeOfService; + UINT8 TimeToLive; + BOOLEAN DoNotFragment; + UINT32 ReceiveTimeout; + UINT32 TransmitTimeout; + // + // Access Point + // + BOOLEAN UseDefaultAddress; + EFI_IPv4_ADDRESS StationAddress; + EFI_IPv4_ADDRESS SubnetMask; + UINT16 StationPort; + EFI_IPv4_ADDRESS RemoteAddress; + UINT16 RemotePort; +} EFI_UDP4_CONFIG_DATA; + +typedef struct { + EFI_UDP4_SESSION_DATA *UdpSessionData; //OPTIONAL + EFI_IPv4_ADDRESS *GatewayAddress; //OPTIONAL + UINT32 DataLength; + UINT32 FragmentCount; + EFI_UDP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_UDP4_TRANSMIT_DATA; + +typedef struct { + EFI_TIME TimeStamp; + EFI_EVENT RecycleSignal; + EFI_UDP4_SESSION_DATA UdpSession; + UINT32 DataLength; + UINT32 FragmentCount; + EFI_UDP4_FRAGMENT_DATA FragmentTable[1]; +} EFI_UDP4_RECEIVE_DATA; + + +typedef struct { + EFI_EVENT Event; + EFI_STATUS Status; + union { + EFI_UDP4_RECEIVE_DATA *RxData; + EFI_UDP4_TRANSMIT_DATA *TxData; + } Packet; +} EFI_UDP4_COMPLETION_TOKEN; + +/** + Reads the current operational settings. + + The GetModeData() function copies the current operational settings of this EFI + UDPv4 Protocol instance into user-supplied buffers. This function is used + optionally to retrieve the operational mode data of underlying networks or + drivers. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param Udp4ConfigData The pointer to the buffer to receive the current configuration data. + @param Ip4ModeData The pointer to the EFI IPv4 Protocol mode data structure. + @param MnpConfigData The pointer to the managed network configuration data structure. + @param SnpModeData The pointer to the simple network mode data structure. + + @retval EFI_SUCCESS The mode data was read. + @retval EFI_NOT_STARTED When Udp4ConfigData is queried, no configuration data is + available because this instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_GET_MODE_DATA)( + IN EFI_UDP4_PROTOCOL *This, + OUT EFI_UDP4_CONFIG_DATA *Udp4ConfigData OPTIONAL, + OUT EFI_IP4_MODE_DATA *Ip4ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL + ); + + +/** + Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv4 + Protocol. + + The Configure() function is used to do the following: + * Initialize and start this instance of the EFI UDPv4 Protocol. + * Change the filtering rules and operational parameters. + * Reset this instance of the EFI UDPv4 Protocol. + Until these parameters are initialized, no network traffic can be sent or + received by this instance. This instance can be also reset by calling Configure() + with UdpConfigData set to NULL. Once reset, the receiving queue and transmitting + queue are flushed and no traffic is allowed through this instance. + With different parameters in UdpConfigData, Configure() can be used to bind + this instance to specified port. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param Udp4ConfigData The pointer to the buffer to receive the current configuration data. + + @retval EFI_SUCCESS The configuration settings were set, changed, or reset successfully. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER UdpConfigData.StationAddress is not a valid unicast IPv4 address. + @retval EFI_INVALID_PARAMETER UdpConfigData.SubnetMask is not a valid IPv4 address mask. The subnet + mask must be contiguous. + @retval EFI_INVALID_PARAMETER UdpConfigData.RemoteAddress is not a valid unicast IPv4 address if it + is not zero. + @retval EFI_ALREADY_STARTED The EFI UDPv4 Protocol instance is already started/configured + and must be stopped/reset before it can be reconfigured. + @retval EFI_ACCESS_DENIED UdpConfigData. AllowDuplicatePort is FALSE + and UdpConfigData.StationPort is already used by + other instance. + @retval EFI_OUT_OF_RESOURCES The EFI UDPv4 Protocol driver cannot allocate memory for this + EFI UDPv4 Protocol instance. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred and this instance + was not opened. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_CONFIGURE)( + IN EFI_UDP4_PROTOCOL *This, + IN EFI_UDP4_CONFIG_DATA *UdpConfigData OPTIONAL + ); + +/** + Joins and leaves multicast groups. + + The Groups() function is used to enable and disable the multicast group + filtering. If the JoinFlag is FALSE and the MulticastAddress is NULL, then all + currently joined groups are left. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param JoinFlag Set to TRUE to join a multicast group. Set to FALSE to leave one + or all multicast groups. + @param MulticastAddress The pointer to multicast group address to join or leave. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The EFI UDPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_OUT_OF_RESOURCES Could not allocate resources to join the group. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - JoinFlag is TRUE and MulticastAddress is NULL. + - JoinFlag is TRUE and *MulticastAddress is not + a valid multicast address. + @retval EFI_ALREADY_STARTED The group address is already in the group table (when + JoinFlag is TRUE). + @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is + FALSE). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_GROUPS)( + IN EFI_UDP4_PROTOCOL *This, + IN BOOLEAN JoinFlag, + IN EFI_IPv4_ADDRESS *MulticastAddress OPTIONAL + ); + +/** + Adds and deletes routing table entries. + + The Routes() function adds a route to or deletes a route from the routing table. + Routes are determined by comparing the SubnetAddress with the destination IP + address and arithmetically AND-ing it with the SubnetMask. The gateway address + must be on the same subnet as the configured station address. + The default route is added with SubnetAddress and SubnetMask both set to 0.0.0.0. + The default route matches all destination IP addresses that do not match any + other routes. + A zero GatewayAddress is a nonroute. Packets are sent to the destination IP + address if it can be found in the Address Resolution Protocol (ARP) cache or + on the local subnet. One automatic nonroute entry will be inserted into the + routing table for outgoing packets that are addressed to a local subnet + (gateway address of 0.0.0.0). + Each instance of the EFI UDPv4 Protocol has its own independent routing table. + Instances of the EFI UDPv4 Protocol that use the default IP address will also + have copies of the routing table provided by the EFI_IP4_CONFIG_PROTOCOL. These + copies will be updated automatically whenever the IP driver reconfigures its + instances; as a result, the previous modification to these copies will be lost. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param DeleteRoute Set to TRUE to delete this route from the routing table. + Set to FALSE to add this route to the routing table. + @param SubnetAddress The destination network address that needs to be routed. + @param SubnetMask The subnet mask of SubnetAddress. + @param GatewayAddress The gateway IP address for this route. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The EFI UDPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + - RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Could not add the entry to the routing table. + @retval EFI_NOT_FOUND This route is not in the routing table. + @retval EFI_ACCESS_DENIED The route is already defined in the routing table. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_ROUTES)( + IN EFI_UDP4_PROTOCOL *This, + IN BOOLEAN DeleteRoute, + IN EFI_IPv4_ADDRESS *SubnetAddress, + IN EFI_IPv4_ADDRESS *SubnetMask, + IN EFI_IPv4_ADDRESS *GatewayAddress + ); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase + the rate that data packets are moved between the communications device and the + transmit and receive queues. + In some systems, the periodic timer event in the managed network driver may not + poll the underlying communications device fast enough to transmit and/or receive + all data packets without missing incoming packets or dropping outgoing packets. + Drivers and applications that are experiencing packet loss should try calling + the Poll() function more often. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_POLL)( + IN EFI_UDP4_PROTOCOL *This + ); + +/** + Places an asynchronous receive request into the receiving queue. + + The Receive() function places a completion token into the receive packet queue. + This function is always asynchronous. + The caller must fill in the Token.Event field in the completion token, and this + field cannot be NULL. When the receive operation completes, the EFI UDPv4 Protocol + driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event + is signaled. Providing a proper notification function and context for the event + will enable the user to receive the notification and receiving status. That + notification function is guaranteed to not be re-entered. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param Token The pointer to a token that is associated with the receive data + descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI UDPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, RARP, etc.) + is not finished yet. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_INVALID_PARAMETER Token is NULL. + @retval EFI_INVALID_PARAMETER Token.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system + resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_ACCESS_DENIED A receive completion token with the same Token.Event was already in + the receive queue. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_RECEIVE)( + IN EFI_UDP4_PROTOCOL *This, + IN EFI_UDP4_COMPLETION_TOKEN *Token + ); + +/** + Queues outgoing data packets into the transmit queue. + + The Transmit() function places a sending request to this instance of the EFI + UDPv4 Protocol, alongside the transmit data that was filled by the user. Whenever + the packet in the token is sent out or some errors occur, the Token.Event will + be signaled and Token.Status is updated. Providing a proper notification function + and context for the event will enable the user to receive the notification and + transmitting status. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param Token The pointer to the completion token that will be placed into the + transmit queue. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This EFI UDPv4 Protocol instance has not been started. + @retval EFI_NO_MAPPING When using a default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_ACCESS_DENIED The transmit completion token with the same + Token.Event was already in the transmit queue. + @retval EFI_NOT_READY The completion token could not be queued because the + transmit queue is full. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data. + @retval EFI_NOT_FOUND There is no route to the destination network or address. + @retval EFI_BAD_BUFFER_SIZE The data length is greater than the maximum UDP packet + size. Or the length of the IP header + UDP header + data + length is greater than MTU if DoNotFragment is TRUE. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_TRANSMIT)( + IN EFI_UDP4_PROTOCOL *This, + IN EFI_UDP4_COMPLETION_TOKEN *Token + ); + +/** + Aborts an asynchronous transmit or receive request. + + The Cancel() function is used to abort a pending transmit or receive request. + If the token is in the transmit or receive request queues, after calling this + function, Token.Status will be set to EFI_ABORTED and then Token.Event will be + signaled. If the token is not in one of the queues, which usually means that + the asynchronous operation has completed, this function will not signal the + token and EFI_NOT_FOUND is returned. + + @param This The pointer to the EFI_UDP4_PROTOCOL instance. + @param Token The pointer to a token that has been issued by + EFI_UDP4_PROTOCOL.Transmit() or + EFI_UDP4_PROTOCOL.Receive().If NULL, all pending + tokens are aborted. + + @retval EFI_SUCCESS The asynchronous I/O request was aborted and Token.Event + was signaled. When Token is NULL, all pending requests are + aborted and their events are signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NO_MAPPING When using the default address, configuration (DHCP, BOOTP, + RARP, etc.) is not finished yet. + @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was + not found in the transmit or receive queue. It has either completed + or was not issued by Transmit() and Receive(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP4_CANCEL)( + IN EFI_UDP4_PROTOCOL *This, + IN EFI_UDP4_COMPLETION_TOKEN *Token OPTIONAL + ); + +/// +/// The EFI_UDP4_PROTOCOL defines an EFI UDPv4 Protocol session that can be used +/// by any network drivers, applications, or daemons to transmit or receive UDP packets. +/// This protocol instance can either be bound to a specified port as a service or +/// connected to some remote peer as an active client. Each instance has its own settings, +/// such as the routing table and group table, which are independent from each other. +/// +struct _EFI_UDP4_PROTOCOL { + EFI_UDP4_GET_MODE_DATA GetModeData; + EFI_UDP4_CONFIGURE Configure; + EFI_UDP4_GROUPS Groups; + EFI_UDP4_ROUTES Routes; + EFI_UDP4_TRANSMIT Transmit; + EFI_UDP4_RECEIVE Receive; + EFI_UDP4_CANCEL Cancel; + EFI_UDP4_POLL Poll; +}; + +extern EFI_GUID gEfiUdp4ServiceBindingProtocolGuid; +extern EFI_GUID gEfiUdp4ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp6.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp6.h new file mode 100644 index 0000000000..276392e14e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Udp6.h @@ -0,0 +1,574 @@ +/** @file + The EFI UDPv6 (User Datagram Protocol version 6) Protocol Definition, which is built upon + the EFI IPv6 Protocol and provides simple packet-oriented services to transmit and receive + UDP packets. + + Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_UDP6_PROTOCOL_H__ +#define __EFI_UDP6_PROTOCOL_H__ + +#include + +#define EFI_UDP6_SERVICE_BINDING_PROTOCOL_GUID \ + { \ + 0x66ed4721, 0x3c98, 0x4d3e, {0x81, 0xe3, 0xd0, 0x3d, 0xd3, 0x9a, 0x72, 0x54 } \ + } + +#define EFI_UDP6_PROTOCOL_GUID \ + { \ + 0x4f948815, 0xb4b9, 0x43cb, {0x8a, 0x33, 0x90, 0xe0, 0x60, 0xb3, 0x49, 0x55 } \ + } + +/// +/// EFI_UDP6_SERVICE_POINT is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + /// + /// The EFI UDPv6 Protocol instance handle that is using this address/port pair. + /// + EFI_HANDLE InstanceHandle; + /// + /// The IPv6 address to which this instance of the EFI UDPv6 Protocol is bound. + /// Set to 0::/128, if this instance is used to listen all packets from any + /// source address. + /// + EFI_IPv6_ADDRESS LocalAddress; + /// + /// The port number in host byte order on which the service is listening. + /// + UINT16 LocalPort; + /// + /// The IPv6 address of the remote host. May be 0::/128 if it is not connected + /// to any remote host or connected with more than one remote host. + /// + EFI_IPv6_ADDRESS RemoteAddress; + /// + /// The port number in host byte order on which the remote host is + /// listening. Maybe zero if it is not connected to any remote host. + /// + UINT16 RemotePort; +} EFI_UDP6_SERVICE_POINT; + +/// +/// EFI_UDP6_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more. +/// The definition in here is only present to provide backwards compatability. +/// +typedef struct { + /// + /// The handle of the driver that creates this entry. + /// + EFI_HANDLE DriverHandle; + /// + /// The number of address/port pairs that follow this data structure. + /// + UINT32 ServiceCount; + /// + /// List of address/port pairs that are currently in use. + /// + EFI_UDP6_SERVICE_POINT Services[1]; +} EFI_UDP6_VARIABLE_DATA; + +typedef struct _EFI_UDP6_PROTOCOL EFI_UDP6_PROTOCOL; + +/// +/// EFI_UDP6_FRAGMENT_DATA allows multiple receive or transmit buffers to be specified. +/// The purpose of this structure is to avoid copying the same packet multiple times. +/// +typedef struct { + UINT32 FragmentLength; ///< Length of the fragment data buffer. + VOID *FragmentBuffer; ///< Pointer to the fragment data buffer. +} EFI_UDP6_FRAGMENT_DATA; + +/// +/// The EFI_UDP6_SESSION_DATA is used to retrieve the settings when receiving packets or +/// to override the existing settings (only DestinationAddress and DestinationPort can +/// be overridden) of this EFI UDPv6 Protocol instance when sending packets. +/// +typedef struct { + /// + /// Address from which this packet is sent. This field should not be used when + /// sending packets. + /// + EFI_IPv6_ADDRESS SourceAddress; + /// + /// Port from which this packet is sent. It is in host byte order. This field should + /// not be used when sending packets. + /// + UINT16 SourcePort; + /// + /// Address to which this packet is sent. When sending packet, it'll be ignored + /// if it is zero. + /// + EFI_IPv6_ADDRESS DestinationAddress; + /// + /// Port to which this packet is sent. When sending packet, it'll be + /// ignored if it is zero. + /// + UINT16 DestinationPort; +} EFI_UDP6_SESSION_DATA; + +typedef struct { + /// + /// Set to TRUE to accept UDP packets that are sent to any address. + /// + BOOLEAN AcceptPromiscuous; + /// + /// Set to TRUE to accept UDP packets that are sent to any port. + /// + BOOLEAN AcceptAnyPort; + /// + /// Set to TRUE to allow this EFI UDPv6 Protocol child instance to open a port number + /// that is already being used by another EFI UDPv6 Protocol child instance. + /// + BOOLEAN AllowDuplicatePort; + /// + /// TrafficClass field in transmitted IPv6 packets. + /// + UINT8 TrafficClass; + /// + /// HopLimit field in transmitted IPv6 packets. + /// + UINT8 HopLimit; + /// + /// The receive timeout value (number of microseconds) to be associated with each + /// incoming packet. Zero means do not drop incoming packets. + /// + UINT32 ReceiveTimeout; + /// + /// The transmit timeout value (number of microseconds) to be associated with each + /// outgoing packet. Zero means do not drop outgoing packets. + /// + UINT32 TransmitTimeout; + /// + /// The station IP address that will be assigned to this EFI UDPv6 Protocol instance. + /// The EFI UDPv6 and EFI IPv6 Protocol drivers will only deliver incoming packets + /// whose destination matches this IP address exactly. Address 0::/128 is also accepted + /// as a special case. Under this situation, underlying IPv6 driver is responsible for + /// binding a source address to this EFI IPv6 protocol instance according to source + /// address selection algorithm. Only incoming packet from the selected source address + /// is delivered. This field can be set and changed only when the EFI IPv6 driver is + /// transitioning from the stopped to the started states. If no address is available + /// for selecting, the EFI IPv6 Protocol driver will use EFI_IP6_CONFIG_PROTOCOL to + /// retrieve the IPv6 address. + EFI_IPv6_ADDRESS StationAddress; + /// + /// The port number to which this EFI UDPv6 Protocol instance is bound. If a client + /// of the EFI UDPv6 Protocol does not care about the port number, set StationPort + /// to zero. The EFI UDPv6 Protocol driver will assign a random port number to transmitted + /// UDP packets. Ignored it if AcceptAnyPort is TRUE. + /// + UINT16 StationPort; + /// + /// The IP address of remote host to which this EFI UDPv6 Protocol instance is connecting. + /// If RemoteAddress is not 0::/128, this EFI UDPv6 Protocol instance will be connected to + /// RemoteAddress; i.e., outgoing packets of this EFI UDPv6 Protocol instance will be sent + /// to this address by default and only incoming packets from this address will be delivered + /// to client. Ignored for incoming filtering if AcceptPromiscuous is TRUE. + EFI_IPv6_ADDRESS RemoteAddress; + /// + /// The port number of the remote host to which this EFI UDPv6 Protocol instance is connecting. + /// If it is not zero, outgoing packets of this EFI UDPv6 Protocol instance will be sent to + /// this port number by default and only incoming packets from this port will be delivered + /// to client. Ignored if RemoteAddress is 0::/128 and ignored for incoming filtering if + /// AcceptPromiscuous is TRUE. + UINT16 RemotePort; +} EFI_UDP6_CONFIG_DATA; + +/// +/// The EFI UDPv6 Protocol client must fill this data structure before sending a packet. +/// The packet may contain multiple buffers that may be not in a continuous memory location. +/// +typedef struct { + /// + /// If not NULL, the data that is used to override the transmitting settings.Only the two + /// filed UdpSessionData.DestinationAddress and UdpSessionData.DestionPort can be used as + /// the transmitting setting filed. + /// + EFI_UDP6_SESSION_DATA *UdpSessionData; + /// + /// Sum of the fragment data length. Must not exceed the maximum UDP packet size. + /// + UINT32 DataLength; + /// + /// Number of fragments. + /// + UINT32 FragmentCount; + /// + /// Array of fragment descriptors. + /// + EFI_UDP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_UDP6_TRANSMIT_DATA; + +/// +/// EFI_UDP6_RECEIVE_DATA is filled by the EFI UDPv6 Protocol driver when this EFI UDPv6 +/// Protocol instance receives an incoming packet. If there is a waiting token for incoming +/// packets, the CompletionToken.Packet.RxData field is updated to this incoming packet and +/// the CompletionToken.Event is signaled. The EFI UDPv6 Protocol client must signal the +/// RecycleSignal after processing the packet. +/// FragmentTable could contain multiple buffers that are not in the continuous memory locations. +/// The EFI UDPv6 Protocol client might need to combine two or more buffers in FragmentTable to +/// form their own protocol header. +/// +typedef struct { + /// + /// Time when the EFI UDPv6 Protocol accepted the packet. + /// + EFI_TIME TimeStamp; + /// + /// Indicates the event to signal when the received data has been processed. + /// + EFI_EVENT RecycleSignal; + /// + /// The UDP session data including SourceAddress, SourcePort, DestinationAddress, + /// and DestinationPort. + /// + EFI_UDP6_SESSION_DATA UdpSession; + /// + /// The sum of the fragment data length. + /// + UINT32 DataLength; + /// + /// Number of fragments. Maybe zero. + /// + UINT32 FragmentCount; + /// + /// Array of fragment descriptors. Maybe zero. + /// + EFI_UDP6_FRAGMENT_DATA FragmentTable[1]; +} EFI_UDP6_RECEIVE_DATA; + +/// +/// The EFI_UDP6_COMPLETION_TOKEN structures are used for both transmit and receive operations. +/// When used for transmitting, the Event and TxData fields must be filled in by the EFI UDPv6 +/// Protocol client. After the transmit operation completes, the Status field is updated by the +/// EFI UDPv6 Protocol and the Event is signaled. +/// When used for receiving, only the Event field must be filled in by the EFI UDPv6 Protocol +/// client. After a packet is received, RxData and Status are filled in by the EFI UDPv6 Protocol +/// and the Event is signaled. +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI UDPv6 Protocol + /// driver. The type of Event must be EVT_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// - EFI_SUCCESS: The receive or transmit operation completed successfully. + /// - EFI_ABORTED: The receive or transmit was aborted. + /// - EFI_TIMEOUT: The transmit timeout expired. + /// - EFI_NETWORK_UNREACHABLE: The destination network is unreachable. RxData is set to + /// NULL in this situation. + /// - EFI_HOST_UNREACHABLE: The destination host is unreachable. RxData is set to NULL in + /// this situation. + /// - EFI_PROTOCOL_UNREACHABLE: The UDP protocol is unsupported in the remote system. + /// RxData is set to NULL in this situation. + /// - EFI_PORT_UNREACHABLE: No service is listening on the remote port. RxData is set to + /// NULL in this situation. + /// - EFI_ICMP_ERROR: Some other Internet Control Message Protocol (ICMP) error report was + /// received. For example, packets are being sent too fast for the destination to receive them + /// and the destination sent an ICMP source quench report. RxData is set to NULL in this situation. + /// - EFI_DEVICE_ERROR: An unexpected system or network error occurred. + /// - EFI_SECURITY_VIOLATION: The transmit or receive was failed because of IPsec policy check. + /// - EFI_NO_MEDIA: There was a media error. + /// + EFI_STATUS Status; + union { + /// + /// When this token is used for receiving, RxData is a pointer to EFI_UDP6_RECEIVE_DATA. + /// + EFI_UDP6_RECEIVE_DATA *RxData; + /// + /// When this token is used for transmitting, TxData is a pointer to EFI_UDP6_TRANSMIT_DATA. + /// + EFI_UDP6_TRANSMIT_DATA *TxData; + } Packet; +} EFI_UDP6_COMPLETION_TOKEN; + +/** + Read the current operational settings. + + The GetModeData() function copies the current operational settings of this EFI UDPv6 Protocol + instance into user-supplied buffers. This function is used optionally to retrieve the operational + mode data of underlying networks or drivers. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[out] Udp6ConfigData The buffer in which the current UDP configuration data is returned. + @param[out] Ip6ModeData The buffer in which the current EFI IPv6 Protocol mode data is returned. + @param[out] MnpConfigData The buffer in which the current managed network configuration data is + returned. + @param[out] SnpModeData The buffer in which the simple network mode data is returned. + + @retval EFI_SUCCESS The mode data was read. + @retval EFI_NOT_STARTED When Udp6ConfigData is queried, no configuration data is available + because this instance has not been started. + @retval EFI_INVALID_PARAMETER This is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_GET_MODE_DATA)( + IN EFI_UDP6_PROTOCOL *This, + OUT EFI_UDP6_CONFIG_DATA *Udp6ConfigData OPTIONAL, + OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL, + OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL, + OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL +); + +/** + Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv6 + Protocol. + + The Configure() function is used to do the following: + - Initialize and start this instance of the EFI UDPv6 Protocol. + - Change the filtering rules and operational parameters. + - Reset this instance of the EFI UDPv6 Protocol. + + Until these parameters are initialized, no network traffic can be sent or received by this instance. + This instance can be also reset by calling Configure() with UdpConfigData set to NULL. + Once reset, the receiving queue and transmitting queue are flushed and no traffic is allowed through + this instance. + + With different parameters in UdpConfigData, Configure() can be used to bind this instance to specified + port. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[in] UdpConfigData Pointer to the buffer contained the configuration data. + + @retval EFI_SUCCESS The configuration settings were set, changed, or reset successfully. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available for use. + @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE: + - This is NULL. + - UdpConfigData.StationAddress neither zero nor one of the configured IP + addresses in the underlying IPv6 driver. + - UdpConfigData.RemoteAddress is not a valid unicast IPv6 address if it + is not zero. + @retval EFI_ALREADY_STARTED The EFI UDPv6 Protocol instance is already started/configured and must be + stopped/reset before it can be reconfigured. Only TrafficClass, HopLimit, + ReceiveTimeout, and TransmitTimeout can be reconfigured without stopping + the current instance of the EFI UDPv6 Protocol. + @retval EFI_ACCESS_DENIED UdpConfigData.AllowDuplicatePort is FALSE and UdpConfigData.StationPort + is already used by other instance. + @retval EFI_OUT_OF_RESOURCES The EFI UDPv6 Protocol driver cannot allocate memory for this EFI UDPv6 + Protocol instance. + @retval EFI_DEVICE_ERROR An unexpected network or system error occurred and this instance was not + opened. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_CONFIGURE)( + IN EFI_UDP6_PROTOCOL *This, + IN EFI_UDP6_CONFIG_DATA *UdpConfigData OPTIONAL +); + +/** + Joins and leaves multicast groups. + + The Groups() function is used to join or leave one or more multicast group. + If the JoinFlag is FALSE and the MulticastAddress is NULL, then all currently joined groups are left. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[in] JoinFlag Set to TRUE to join a multicast group. Set to FALSE to leave one + or all multicast groups. + @param[in] MulticastAddress Pointer to multicast group address to join or leave. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_STARTED The EFI UDPv6 Protocol instance has not been started. + @retval EFI_OUT_OF_RESOURCES Could not allocate resources to join the group. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + - This is NULL. + - JoinFlag is TRUE and MulticastAddress is NULL. + - JoinFlag is TRUE and *MulticastAddress is not a valid multicast address. + @retval EFI_ALREADY_STARTED The group address is already in the group table (when JoinFlag is TRUE). + @retval EFI_NOT_FOUND The group address is not in the group table (when JoinFlag is FALSE). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_GROUPS)( + IN EFI_UDP6_PROTOCOL *This, + IN BOOLEAN JoinFlag, + IN EFI_IPv6_ADDRESS *MulticastAddress OPTIONAL +); + +/** + Queues outgoing data packets into the transmit queue. + + The Transmit() function places a sending request to this instance of the EFI UDPv6 Protocol, + alongside the transmit data that was filled by the user. Whenever the packet in the token is + sent out or some errors occur, the Token.Event will be signaled and Token.Status is updated. + Providing a proper notification function and context for the event will enable the user to + receive the notification and transmitting status. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[in] Token Pointer to the completion token that will be placed into the + transmit queue. + + @retval EFI_SUCCESS The data has been queued for transmission. + @retval EFI_NOT_STARTED This EFI UDPv6 Protocol instance has not been started. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available + for use. + @retval EFI_INVALID_PARAMETER One or more of the following are TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + - Token.Packet.TxData is NULL. + - Token.Packet.TxData.FragmentCount is zero. + - Token.Packet.TxData.DataLength is not equal to the sum of fragment + lengths. + - One or more of the Token.Packet.TxData.FragmentTable[].FragmentLength + fields is zero. + - One or more of the Token.Packet.TxData.FragmentTable[].FragmentBuffer + fields is NULL. + - Token.Packet.TxData.UdpSessionData.DestinationAddress is not zero + and is not valid unicast Ipv6 address if UdpSessionData is not NULL. + - Token.Packet.TxData.UdpSessionData is NULL and this instance's + UdpConfigData.RemoteAddress is unspecified. + - Token.Packet.TxData.UdpSessionData.DestinationAddress is non-zero + when DestinationAddress is configured as non-zero when doing Configure() + for this EFI Udp6 protocol instance. + - Token.Packet.TxData.UdpSesionData.DestinationAddress is zero when + DestinationAddress is unspecified when doing Configure() for this + EFI Udp6 protocol instance. + @retval EFI_ACCESS_DENIED The transmit completion token with the same Token.Event was already + in the transmit queue. + @retval EFI_NOT_READY The completion token could not be queued because the transmit queue + is full. + @retval EFI_OUT_OF_RESOURCES Could not queue the transmit data. + @retval EFI_NOT_FOUND There is no route to the destination network or address. + @retval EFI_BAD_BUFFER_SIZE The data length is greater than the maximum UDP packet size. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_TRANSMIT)( + IN EFI_UDP6_PROTOCOL *This, + IN EFI_UDP6_COMPLETION_TOKEN *Token +); + +/** + Places an asynchronous receive request into the receiving queue. + + The Receive() function places a completion token into the receive packet queue. This function is + always asynchronous. + The caller must fill in the Token.Event field in the completion token, and this field cannot be + NULL. When the receive operation completes, the EFI UDPv6 Protocol driver updates the Token.Status + and Token.Packet.RxData fields and the Token.Event is signaled. + Providing a proper notification function and context for the event will enable the user to receive + the notification and receiving status. That notification function is guaranteed to not be re-entered. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[in] Token Pointer to a token that is associated with the receive data descriptor. + + @retval EFI_SUCCESS The receive completion token was cached. + @retval EFI_NOT_STARTED This EFI UDPv6 Protocol instance has not been started. + @retval EFI_NO_MAPPING The underlying IPv6 driver was responsible for choosing a source + address for this instance, but no source address was available + for use. + @retval EFI_INVALID_PARAMETER One or more of the following is TRUE: + - This is NULL. + - Token is NULL. + - Token.Event is NULL. + @retval EFI_OUT_OF_RESOURCES The receive completion token could not be queued due to a lack of system + resources (usually memory). + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. The EFI UDPv6 Protocol + instance has been reset to startup defaults. + @retval EFI_ACCESS_DENIED A receive completion token with the same Token.Event was already in + the receive queue. + @retval EFI_NOT_READY The receive request could not be queued because the receive queue is full. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_RECEIVE)( + IN EFI_UDP6_PROTOCOL *This, + IN EFI_UDP6_COMPLETION_TOKEN *Token +); + +/** + Aborts an asynchronous transmit or receive request. + + The Cancel() function is used to abort a pending transmit or receive request. If the token is in the + transmit or receive request queues, after calling this function, Token.Status will be set to + EFI_ABORTED and then Token.Event will be signaled. If the token is not in one of the queues, + which usually means that the asynchronous operation has completed, this function will not signal the + token and EFI_NOT_FOUND is returned. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + @param[in] Token Pointer to a token that has been issued by EFI_UDP6_PROTOCOL.Transmit() + or EFI_UDP6_PROTOCOL.Receive().If NULL, all pending tokens are aborted. + + @retval EFI_SUCCESS The asynchronous I/O request was aborted and Token.Event was signaled. + When Token is NULL, all pending requests are aborted and their events + are signaled. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_NOT_STARTED This instance has not been started. + @retval EFI_NOT_FOUND When Token is not NULL, the asynchronous I/O request was not found in + the transmit or receive queue. It has either completed or was not issued + by Transmit() and Receive(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_CANCEL)( + IN EFI_UDP6_PROTOCOL *This, + IN EFI_UDP6_COMPLETION_TOKEN *Token OPTIONAL +); + +/** + Polls for incoming data packets and processes outgoing data packets. + + The Poll() function can be used by network drivers and applications to increase the rate that data + packets are moved between the communications device and the transmit and receive queues. + In some systems, the periodic timer event in the managed network driver may not poll the underlying + communications device fast enough to transmit and/or receive all data packets without missing incoming + packets or dropping outgoing packets. Drivers and applications that are experiencing packet loss should + try calling the Poll() function more often. + + @param[in] This Pointer to the EFI_UDP6_PROTOCOL instance. + + @retval EFI_SUCCESS Incoming or outgoing data was processed. + @retval EFI_INVALID_PARAMETER This is NULL. + @retval EFI_DEVICE_ERROR An unexpected system or network error occurred. + @retval EFI_TIMEOUT Data was dropped out of the transmit and/or receive queue. + Consider increasing the polling rate. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UDP6_POLL)( + IN EFI_UDP6_PROTOCOL *This +); + +/// +/// The EFI_UDP6_PROTOCOL defines an EFI UDPv6 Protocol session that can be used by any network drivers, +/// applications, or daemons to transmit or receive UDP packets. This protocol instance can either be +/// bound to a specified port as a service or connected to some remote peer as an active client. +/// Each instance has its own settings, such as group table, that are independent from each other. +/// +struct _EFI_UDP6_PROTOCOL { + EFI_UDP6_GET_MODE_DATA GetModeData; + EFI_UDP6_CONFIGURE Configure; + EFI_UDP6_GROUPS Groups; + EFI_UDP6_TRANSMIT Transmit; + EFI_UDP6_RECEIVE Receive; + EFI_UDP6_CANCEL Cancel; + EFI_UDP6_POLL Poll; +}; + +extern EFI_GUID gEfiUdp6ServiceBindingProtocolGuid; +extern EFI_GUID gEfiUdp6ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UfsDeviceConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UfsDeviceConfig.h new file mode 100644 index 0000000000..33ba120866 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UfsDeviceConfig.h @@ -0,0 +1,137 @@ +/** @file + This file defines the EFI UFS Device Config Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.7 + +**/ + +#ifndef __UFS_DEVICE_CONFIG_PROTOCOL_H__ +#define __UFS_DEVICE_CONFIG_PROTOCOL_H__ + +// +// EFI UFS Device Config Protocol GUID value +// +#define EFI_UFS_DEVICE_CONFIG_GUID \ + { 0xb81bfab0, 0xeb3, 0x4cf9, { 0x84, 0x65, 0x7f, 0xa9, 0x86, 0x36, 0x16, 0x64 }}; + +// +// Forward reference for pure ANSI compatability +// +typedef struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL EFI_UFS_DEVICE_CONFIG_PROTOCOL; + +/** + Read or write specified device descriptor of a UFS device. + + The service is used to read/write UFS device descriptors. The consumer of this API is responsible + for allocating the data buffer pointed by Descriptor. + + @param[in] This The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance. + @param[in] Read The boolean variable to show r/w direction. + @param[in] DescId The ID of device descriptor. + @param[in] Index The Index of device descriptor. + @param[in] Selector The Selector of device descriptor. + @param[in, out] Descriptor The buffer of device descriptor to be read or written. + @param[in, out] DescSize The size of device descriptor buffer. On input, the size, in bytes, + of the data buffer specified by Descriptor. On output, the number + of bytes that were actually transferred. + + @retval EFI_SUCCESS The device descriptor is read/written successfully. + @retval EFI_INVALID_PARAMETER This is NULL or Descriptor is NULL or DescSize is NULL. + DescId, Index and Selector are invalid combination to point to a + type of UFS device descriptor. + @retval EFI_DEVICE_ERROR The device descriptor is not read/written successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR) ( + IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This, + IN BOOLEAN Read, + IN UINT8 DescId, + IN UINT8 Index, + IN UINT8 Selector, + IN OUT UINT8 *Descriptor, + IN OUT UINT32 *DescSize + ); + +/** + Read or write specified flag of a UFS device. + + The service is used to read/write UFS flag descriptors. The consumer of this API is responsible + for allocating the buffer pointed by Flag. The buffer size is 1 byte as UFS flag descriptor is + just a single Boolean value that represents a TRUE or FALSE, '0' or '1', ON or OFF type of value. + + @param[in] This The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance. + @param[in] Read The boolean variable to show r/w direction. + @param[in] FlagId The ID of flag to be read or written. + @param[in, out] Flag The buffer to set or clear flag. + + @retval EFI_SUCCESS The flag descriptor is set/clear successfully. + @retval EFI_INVALID_PARAMETER This is NULL or Flag is NULL. + FlagId is an invalid UFS flag ID. + @retval EFI_DEVICE_ERROR The flag is not set/clear successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_FLAG) ( + IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This, + IN BOOLEAN Read, + IN UINT8 FlagId, + IN OUT UINT8 *Flag + ); + +/** + Read or write specified attribute of a UFS device. + + The service is used to read/write UFS attributes. The consumer of this API is responsible for + allocating the data buffer pointed by Attribute. + + @param[in] This The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance. + @param[in] Read The boolean variable to show r/w direction. + @param[in] AttrId The ID of Attribute. + @param[in] Index The Index of Attribute. + @param[in] Selector The Selector of Attribute. + @param[in, out] Attribute The buffer of Attribute to be read or written. + @param[in, out] AttrSize The size of Attribute buffer. On input, the size, in bytes, of the + data buffer specified by Attribute. On output, the number of bytes + that were actually transferred. + + @retval EFI_SUCCESS The attribute is read/written successfully. + @retval EFI_INVALID_PARAMETER This is NULL or Attribute is NULL or AttrSize is NULL. + AttrId, Index and Selector are invalid combination to point to a + type of UFS attribute. + @retval EFI_DEVICE_ERROR The attribute is not read/written successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE) ( + IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This, + IN BOOLEAN Read, + IN UINT8 AttrId, + IN UINT8 Index, + IN UINT8 Selector, + IN OUT UINT8 *Attribute, + IN OUT UINT32 *AttrSize + ); + +/// +/// UFS Device Config Protocol structure. +/// +struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL { + EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR RwUfsDescriptor; + EFI_UFS_DEVICE_CONFIG_RW_FLAG RwUfsFlag; + EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE RwUfsAttribute; +}; + +/// +/// UFS Device Config Protocol GUID variable. +/// +extern EFI_GUID gEfiUfsDeviceConfigProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaDraw.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaDraw.h new file mode 100644 index 0000000000..472ceeaaf0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaDraw.h @@ -0,0 +1,160 @@ +/** @file + UGA Draw protocol from the EFI 1.10 specification. + + Abstraction of a very simple graphics device. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UGA_DRAW_H__ +#define __UGA_DRAW_H__ + + +#define EFI_UGA_DRAW_PROTOCOL_GUID \ + { \ + 0x982c298b, 0xf4fa, 0x41cb, {0xb8, 0x38, 0x77, 0xaa, 0x68, 0x8f, 0xb8, 0x39 } \ + } + +typedef struct _EFI_UGA_DRAW_PROTOCOL EFI_UGA_DRAW_PROTOCOL; + +/** + Return the current video mode information. + + @param This The EFI_UGA_DRAW_PROTOCOL instance. + @param HorizontalResolution The size of video screen in pixels in the X dimension. + @param VerticalResolution The size of video screen in pixels in the Y dimension. + @param ColorDepth Number of bits per pixel, currently defined to be 32. + @param RefreshRate The refresh rate of the monitor in Hertz. + + @retval EFI_SUCCESS Mode information returned. + @retval EFI_NOT_STARTED Video display is not initialized. Call SetMode () + @retval EFI_INVALID_PARAMETER One of the input args was NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UGA_DRAW_PROTOCOL_GET_MODE)( + IN EFI_UGA_DRAW_PROTOCOL *This, + OUT UINT32 *HorizontalResolution, + OUT UINT32 *VerticalResolution, + OUT UINT32 *ColorDepth, + OUT UINT32 *RefreshRate + ); + +/** + Set the current video mode information. + + @param This The EFI_UGA_DRAW_PROTOCOL instance. + @param HorizontalResolution The size of video screen in pixels in the X dimension. + @param VerticalResolution The size of video screen in pixels in the Y dimension. + @param ColorDepth Number of bits per pixel, currently defined to be 32. + @param RefreshRate The refresh rate of the monitor in Hertz. + + @retval EFI_SUCCESS Mode information returned. + @retval EFI_NOT_STARTED Video display is not initialized. Call SetMode () + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UGA_DRAW_PROTOCOL_SET_MODE)( + IN EFI_UGA_DRAW_PROTOCOL *This, + IN UINT32 HorizontalResolution, + IN UINT32 VerticalResolution, + IN UINT32 ColorDepth, + IN UINT32 RefreshRate + ); + +typedef struct { + UINT8 Blue; + UINT8 Green; + UINT8 Red; + UINT8 Reserved; +} EFI_UGA_PIXEL; + +typedef union { + EFI_UGA_PIXEL Pixel; + UINT32 Raw; +} EFI_UGA_PIXEL_UNION; + +/// +/// Enumration value for actions of Blt operations. +/// +typedef enum { + EfiUgaVideoFill, ///< Write data from the BltBuffer pixel (SourceX, SourceY) + ///< directly to every pixel of the video display rectangle + ///< (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). + ///< Only one pixel will be used from the BltBuffer. Delta is NOT used. + + EfiUgaVideoToBltBuffer, ///< Read data from the video display rectangle + ///< (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in + ///< the BltBuffer rectangle (DestinationX, DestinationY ) + ///< (DestinationX + Width, DestinationY + Height). If DestinationX or + ///< DestinationY is not zero then Delta must be set to the length in bytes + ///< of a row in the BltBuffer. + + EfiUgaBltBufferToVideo, ///< Write data from the BltBuffer rectangle + ///< (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the + ///< video display rectangle (DestinationX, DestinationY) + ///< (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is + ///< not zero then Delta must be set to the length in bytes of a row in the + ///< BltBuffer. + + EfiUgaVideoToVideo, ///< Copy from the video display rectangle (SourceX, SourceY) + ///< (SourceX + Width, SourceY + Height) .to the video display rectangle + ///< (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). + ///< The BltBuffer and Delta are not used in this mode. + + EfiUgaBltMax ///< Maxmimum value for enumration value of Blt operation. If a Blt operation + ///< larger or equal to this enumration value, it is invalid. +} EFI_UGA_BLT_OPERATION; + +/** + Blt a rectangle of pixels on the graphics screen. + + @param[in] This - Protocol instance pointer. + @param[in] BltBuffer - Buffer containing data to blit into video buffer. This + buffer has a size of Width*Height*sizeof(EFI_UGA_PIXEL) + @param[in] BltOperation - Operation to perform on BlitBuffer and video memory + @param[in] SourceX - X coordinate of source for the BltBuffer. + @param[in] SourceY - Y coordinate of source for the BltBuffer. + @param[in] DestinationX - X coordinate of destination for the BltBuffer. + @param[in] DestinationY - Y coordinate of destination for the BltBuffer. + @param[in] Width - Width of rectangle in BltBuffer in pixels. + @param[in] Height - Hight of rectangle in BltBuffer in pixels. + @param[in] Delta - OPTIONAL + + @retval EFI_SUCCESS - The Blt operation completed. + @retval EFI_INVALID_PARAMETER - BltOperation is not valid. + @retval EFI_DEVICE_ERROR - A hardware error occurred writting to the video buffer. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UGA_DRAW_PROTOCOL_BLT)( + IN EFI_UGA_DRAW_PROTOCOL * This, + IN EFI_UGA_PIXEL * BltBuffer, OPTIONAL + IN EFI_UGA_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL + ); + +/// +/// This protocol provides a basic abstraction to set video modes and +/// copy pixels to and from the graphics controller's frame buffer. +/// +struct _EFI_UGA_DRAW_PROTOCOL { + EFI_UGA_DRAW_PROTOCOL_GET_MODE GetMode; + EFI_UGA_DRAW_PROTOCOL_SET_MODE SetMode; + EFI_UGA_DRAW_PROTOCOL_BLT Blt; +}; + +extern EFI_GUID gEfiUgaDrawProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaIo.h new file mode 100644 index 0000000000..9bfe596831 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UgaIo.h @@ -0,0 +1,191 @@ +/** @file + UGA IO protocol from the EFI 1.10 specification. + + Abstraction of a very simple graphics device. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UGA_IO_H__ +#define __UGA_IO_H__ + +#define EFI_UGA_IO_PROTOCOL_GUID \ + { 0x61a4d49e, 0x6f68, 0x4f1b, { 0xb9, 0x22, 0xa8, 0x6e, 0xed, 0xb, 0x7, 0xa2 } } + +typedef struct _EFI_UGA_IO_PROTOCOL EFI_UGA_IO_PROTOCOL; + +typedef UINT32 UGA_STATUS; + +typedef enum { + UgaDtParentBus = 1, + UgaDtGraphicsController, + UgaDtOutputController, + UgaDtOutputPort, + UgaDtOther +} UGA_DEVICE_TYPE, *PUGA_DEVICE_TYPE; + +typedef UINT32 UGA_DEVICE_ID, *PUGA_DEVICE_ID; + +typedef struct { + UGA_DEVICE_TYPE deviceType; + UGA_DEVICE_ID deviceId; + UINT32 ui32DeviceContextSize; + UINT32 ui32SharedContextSize; +} UGA_DEVICE_DATA, *PUGA_DEVICE_DATA; + +typedef struct _UGA_DEVICE { + VOID *pvDeviceContext; + VOID *pvSharedContext; + VOID *pvRunTimeContext; + struct _UGA_DEVICE *pParentDevice; + VOID *pvBusIoServices; + VOID *pvStdIoServices; + UGA_DEVICE_DATA deviceData; +} UGA_DEVICE, *PUGA_DEVICE; + +typedef enum { + UgaIoGetVersion = 1, + UgaIoGetChildDevice, + UgaIoStartDevice, + UgaIoStopDevice, + UgaIoFlushDevice, + UgaIoResetDevice, + UgaIoGetDeviceState, + UgaIoSetDeviceState, + UgaIoSetPowerState, + UgaIoGetMemoryConfiguration, + UgaIoSetVideoMode, + UgaIoCopyRectangle, + UgaIoGetEdidSegment, + UgaIoDeviceChannelOpen, + UgaIoDeviceChannelClose, + UgaIoDeviceChannelRead, + UgaIoDeviceChannelWrite, + UgaIoGetPersistentDataSize, + UgaIoGetPersistentData, + UgaIoSetPersistentData, + UgaIoGetDevicePropertySize, + UgaIoGetDeviceProperty, + UgaIoBtPrivateInterface +} UGA_IO_REQUEST_CODE, *PUGA_IO_REQUEST_CODE; + +typedef struct { + IN UGA_IO_REQUEST_CODE ioRequestCode; + IN VOID *pvInBuffer; + IN UINT64 ui64InBufferSize; + OUT VOID *pvOutBuffer; + IN UINT64 ui64OutBufferSize; + OUT UINT64 ui64BytesReturned; +} UGA_IO_REQUEST, *PUGA_IO_REQUEST; + + +/** + Dynamically allocate storage for a child UGA_DEVICE. + + @param[in] This The EFI_UGA_IO_PROTOCOL instance. + @param[in] ParentDevice ParentDevice specifies a pointer to the parent device of Device. + @param[in] DeviceData A pointer to UGA_DEVICE_DATA returned from a call to DispatchService() + with a UGA_DEVICE of Parent and an IoRequest of type UgaIoGetChildDevice. + @param[in] RunTimeContext Context to associate with Device. + @param[out] Device The Device returns a dynamically allocated child UGA_DEVICE object + for ParentDevice. The caller is responsible for deleting Device. + + + @retval EFI_SUCCESS Device was returned. + @retval EFI_INVALID_PARAMETER One of the arguments was not valid. + @retval EFI_DEVICE_ERROR The device had an error and could not complete the request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UGA_IO_PROTOCOL_CREATE_DEVICE)( + IN EFI_UGA_IO_PROTOCOL *This, + IN UGA_DEVICE *ParentDevice, + IN UGA_DEVICE_DATA *DeviceData, + IN VOID *RunTimeContext, + OUT UGA_DEVICE **Device + ); + + +/** + Delete a dynamically allocated child UGA_DEVICE object that was allocated via CreateDevice(). + + @param[in] This The EFI_UGA_IO_PROTOCOL instance. Type EFI_UGA_IO_PROTOCOL is + defined in Section 10.7. + @param[in] Device The Device points to a UGA_DEVICE object that was dynamically + allocated via a CreateDevice() call. + + + @retval EFI_SUCCESS Device was returned. + @retval EFI_INVALID_PARAMETER The Device was not allocated via CreateDevice(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UGA_IO_PROTOCOL_DELETE_DEVICE)( + IN EFI_UGA_IO_PROTOCOL * This, + IN UGA_DEVICE * Device + ); + +/** + This is the main UGA service dispatch routine for all UGA_IO_REQUEST s. + + @param pDevice pDevice specifies a pointer to a device object associated with a + device enumerated by a pIoRequest->ioRequestCode of type + UgaIoGetChildDevice. The root device for the EFI_UGA_IO_PROTOCOL + is represented by pDevice being set to NULL. + + @param pIoRequest + pIoRequest points to a caller allocated buffer that contains data + defined by pIoRequest->ioRequestCode. See Related Definitions for + a definition of UGA_IO_REQUEST_CODE s and their associated data + structures. + + @return UGA_STATUS + +**/ +typedef UGA_STATUS +(EFIAPI *PUGA_FW_SERVICE_DISPATCH)( + IN PUGA_DEVICE pDevice, + IN OUT PUGA_IO_REQUEST pIoRequest + ); + +/// +/// Provides a basic abstraction to send I/O requests to the graphics device and any of its children. +/// +struct _EFI_UGA_IO_PROTOCOL { + EFI_UGA_IO_PROTOCOL_CREATE_DEVICE CreateDevice; + EFI_UGA_IO_PROTOCOL_DELETE_DEVICE DeleteDevice; + PUGA_FW_SERVICE_DISPATCH DispatchService; +}; + +extern EFI_GUID gEfiUgaIoProtocolGuid; + +// +// Data structure that is stored in the EFI Configuration Table with the +// EFI_UGA_IO_PROTOCOL_GUID. The option ROMs listed in this table may have +// EBC UGA drivers. +// +typedef struct { + UINT32 Version; + UINT32 HeaderSize; + UINT32 SizeOfEntries; + UINT32 NumberOfEntries; +} EFI_DRIVER_OS_HANDOFF_HEADER; + +typedef enum { + EfiUgaDriverFromPciRom, + EfiUgaDriverFromSystem, + EfiDriverHandoffMax +} EFI_DRIVER_HANOFF_ENUM; + +typedef struct { + EFI_DRIVER_HANOFF_ENUM Type; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *PciRomImage; + UINT64 PciRomSize; +} EFI_DRIVER_OS_HANDOFF; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UnicodeCollation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UnicodeCollation.h new file mode 100644 index 0000000000..a18c36c55b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UnicodeCollation.h @@ -0,0 +1,186 @@ +/** @file + Unicode Collation protocol that follows the UEFI 2.0 specification. + This protocol is used to allow code running in the boot services environment + to perform lexical comparison functions on Unicode strings for given languages. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UNICODE_COLLATION_H__ +#define __UNICODE_COLLATION_H__ + +#define EFI_UNICODE_COLLATION_PROTOCOL_GUID \ + { \ + 0x1d85cd7f, 0xf43d, 0x11d2, {0x9a, 0xc, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ + } + +#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \ + { \ + 0xa4c751fc, 0x23ae, 0x4c3e, {0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49 } \ + } + +typedef struct _EFI_UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL; + + +/// +/// Protocol GUID name defined in EFI1.1. +/// +#define UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL_GUID + +/// +/// Protocol defined in EFI1.1. +/// +typedef EFI_UNICODE_COLLATION_PROTOCOL UNICODE_COLLATION_INTERFACE; + +/// +/// Protocol data structures and defines +/// +#define EFI_UNICODE_BYTE_ORDER_MARK (CHAR16) (0xfeff) + +// +// Protocol member functions +// +/** + Performs a case-insensitive comparison of two Null-terminated strings. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param Str1 A pointer to a Null-terminated string. + @param Str2 A pointer to a Null-terminated string. + + @retval 0 Str1 is equivalent to Str2. + @retval >0 Str1 is lexically greater than Str2. + @retval <0 Str1 is lexically less than Str2. + +**/ +typedef +INTN +(EFIAPI *EFI_UNICODE_COLLATION_STRICOLL)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN CHAR16 *Str1, + IN CHAR16 *Str2 + ); + +/** + Performs a case-insensitive comparison of a Null-terminated + pattern string and a Null-terminated string. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param String A pointer to a Null-terminated string. + @param Pattern A pointer to a Null-terminated pattern string. + + @retval TRUE Pattern was found in String. + @retval FALSE Pattern was not found in String. + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_UNICODE_COLLATION_METAIMATCH)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN CHAR16 *String, + IN CHAR16 *Pattern + ); + +/** + Converts all the characters in a Null-terminated string to + lower case characters. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param String A pointer to a Null-terminated string. + +**/ +typedef +VOID +(EFIAPI *EFI_UNICODE_COLLATION_STRLWR)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN OUT CHAR16 *Str + ); + +/** + Converts all the characters in a Null-terminated string to upper + case characters. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param String A pointer to a Null-terminated string. + +**/ +typedef +VOID +(EFIAPI *EFI_UNICODE_COLLATION_STRUPR)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN OUT CHAR16 *Str + ); + +/** + Converts an 8.3 FAT file name in an OEM character set to a Null-terminated + string. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param FatSize The size of the string Fat in bytes. + @param Fat A pointer to a Null-terminated string that contains an 8.3 file + name using an 8-bit OEM character set. + @param String A pointer to a Null-terminated string. The string must + be allocated in advance to hold FatSize characters. + +**/ +typedef +VOID +(EFIAPI *EFI_UNICODE_COLLATION_FATTOSTR)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN UINTN FatSize, + IN CHAR8 *Fat, + OUT CHAR16 *String + ); + +/** + Converts a Null-terminated string to legal characters in a FAT + filename using an OEM character set. + + @param This A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance. + @param String A pointer to a Null-terminated string. + @param FatSize The size of the string Fat in bytes. + @param Fat A pointer to a string that contains the converted version of + String using legal FAT characters from an OEM character set. + + @retval TRUE One or more conversions failed and were substituted with '_' + @retval FALSE None of the conversions failed. + +**/ +typedef +BOOLEAN +(EFIAPI *EFI_UNICODE_COLLATION_STRTOFAT)( + IN EFI_UNICODE_COLLATION_PROTOCOL *This, + IN CHAR16 *String, + IN UINTN FatSize, + OUT CHAR8 *Fat + ); + +/// +/// The EFI_UNICODE_COLLATION_PROTOCOL is used to perform case-insensitive +/// comparisons of strings. +/// +struct _EFI_UNICODE_COLLATION_PROTOCOL { + EFI_UNICODE_COLLATION_STRICOLL StriColl; + EFI_UNICODE_COLLATION_METAIMATCH MetaiMatch; + EFI_UNICODE_COLLATION_STRLWR StrLwr; + EFI_UNICODE_COLLATION_STRUPR StrUpr; + + // + // for supporting fat volumes + // + EFI_UNICODE_COLLATION_FATTOSTR FatToStr; + EFI_UNICODE_COLLATION_STRTOFAT StrToFat; + + /// + /// A Null-terminated ASCII string array that contains one or more language codes. + /// When this field is used for UnicodeCollation2, it is specified in RFC 4646 format. + /// When it is used for UnicodeCollation, it is specified in ISO 639-2 format. + /// + CHAR8 *SupportedLanguages; +}; + +extern EFI_GUID gEfiUnicodeCollationProtocolGuid; +extern EFI_GUID gEfiUnicodeCollation2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Usb2HostController.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Usb2HostController.h new file mode 100644 index 0000000000..01538095c4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Usb2HostController.h @@ -0,0 +1,658 @@ +/** @file + EFI_USB2_HC_PROTOCOL as defined in UEFI 2.0. + The USB Host Controller Protocol is used by code, typically USB bus drivers, + running in the EFI boot services environment, to perform data transactions over + a USB bus. In addition, it provides an abstraction for the root hub of the USB bus. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _USB2_HOSTCONTROLLER_H_ +#define _USB2_HOSTCONTROLLER_H_ + +#include + +#define EFI_USB2_HC_PROTOCOL_GUID \ + { \ + 0x3e745226, 0x9818, 0x45b6, {0xa2, 0xac, 0xd7, 0xcd, 0xe, 0x8b, 0xa2, 0xbc } \ + } + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_USB2_HC_PROTOCOL EFI_USB2_HC_PROTOCOL; + + +typedef struct { + UINT16 PortStatus; ///< Contains current port status bitmap. + UINT16 PortChangeStatus; ///< Contains current port status change bitmap. +} EFI_USB_PORT_STATUS; + +/// +/// EFI_USB_PORT_STATUS.PortStatus bit definition +/// +#define USB_PORT_STAT_CONNECTION 0x0001 +#define USB_PORT_STAT_ENABLE 0x0002 +#define USB_PORT_STAT_SUSPEND 0x0004 +#define USB_PORT_STAT_OVERCURRENT 0x0008 +#define USB_PORT_STAT_RESET 0x0010 +#define USB_PORT_STAT_POWER 0x0100 +#define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 +#define USB_PORT_STAT_SUPER_SPEED 0x0800 +#define USB_PORT_STAT_OWNER 0x2000 + +/// +/// EFI_USB_PORT_STATUS.PortChangeStatus bit definition +/// +#define USB_PORT_STAT_C_CONNECTION 0x0001 +#define USB_PORT_STAT_C_ENABLE 0x0002 +#define USB_PORT_STAT_C_SUSPEND 0x0004 +#define USB_PORT_STAT_C_OVERCURRENT 0x0008 +#define USB_PORT_STAT_C_RESET 0x0010 + + +/// +/// Usb port features value +/// Each value indicates its bit index in the port status and status change bitmaps, +/// if combines these two bitmaps into a 32-bit bitmap. +/// +typedef enum { + EfiUsbPortEnable = 1, + EfiUsbPortSuspend = 2, + EfiUsbPortReset = 4, + EfiUsbPortPower = 8, + EfiUsbPortOwner = 13, + EfiUsbPortConnectChange = 16, + EfiUsbPortEnableChange = 17, + EfiUsbPortSuspendChange = 18, + EfiUsbPortOverCurrentChange = 19, + EfiUsbPortResetChange = 20 +} EFI_USB_PORT_FEATURE; + +#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC. +#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC. +#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC. +#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC. + +typedef struct { + UINT8 TranslatorHubAddress; ///< device address + UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to. +} EFI_USB2_HC_TRANSACTION_TRANSLATOR; + +// +// Protocol definitions +// + +/** + Retrieves the Host Controller capabilities. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param MaxSpeed Host controller data transfer speed. + @param PortNumber Number of the root hub ports. + @param Is64BitCapable TRUE if controller supports 64-bit memory addressing, + FALSE otherwise. + + @retval EFI_SUCCESS The host controller capabilities were retrieved successfully. + @retval EFI_INVALID_PARAMETER One of the input args was NULL. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to + retrieve the capabilities. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_CAPABILITY)( + IN EFI_USB2_HC_PROTOCOL *This, + OUT UINT8 *MaxSpeed, + OUT UINT8 *PortNumber, + OUT UINT8 *Is64BitCapable + ); + +#define EFI_USB_HC_RESET_GLOBAL 0x0001 +#define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002 +#define EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG 0x0004 +#define EFI_USB_HC_RESET_HOST_WITH_DEBUG 0x0008 +/** + Provides software reset for the USB host controller. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param Attributes A bit mask of the reset operation to perform. + + @retval EFI_SUCCESS The reset operation succeeded. + @retval EFI_INVALID_PARAMETER Attributes is not valid. + @retval EFI_UNSUPPORTED The type of reset specified by Attributes is not currently + supported by the host controller hardware. + @retval EFI_ACCESS_DENIED Reset operation is rejected due to the debug port being configured + and active; only EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG or + EFI_USB_HC_RESET_HOST_WITH_DEBUG reset Attributes can be used to + perform reset operation for this host controller. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to + retrieve the capabilities. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_RESET)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT16 Attributes + ); + +/** + Enumration value for status of USB HC. +**/ +typedef enum { + EfiUsbHcStateHalt, ///< The host controller is in halt + ///< state. No USB transactions can occur + ///< while in this state. The host + ///< controller can enter this state for + ///< three reasons: 1) After host + ///< controller hardware reset. 2) + ///< Explicitly set by software. 3) + ///< Triggered by a fatal error such as + ///< consistency check failure. + + EfiUsbHcStateOperational, ///< The host controller is in an + ///< operational state. When in + ///< this state, the host + ///< controller can execute bus + ///< traffic. This state must be + ///< explicitly set to enable the + ///< USB bus traffic. + + EfiUsbHcStateSuspend, ///< The host controller is in the + ///< suspend state. No USB + ///< transactions can occur while in + ///< this state. The host controller + ///< enters this state for the + ///< following reasons: 1) Explicitly + ///< set by software. 2) Triggered + ///< when there is no bus traffic for + ///< 3 microseconds. + + EfiUsbHcStateMaximum ///< Maximum value for enumration value of HC status. +} EFI_USB_HC_STATE; + +/** + Retrieves current state of the USB host controller. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param State A pointer to the EFI_USB_HC_STATE data structure that + indicates current state of the USB host controller. + + @retval EFI_SUCCESS The state information of the host controller was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to retrieve the + host controller's current state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_STATE)( + IN EFI_USB2_HC_PROTOCOL *This, + OUT EFI_USB_HC_STATE *State +); + +/** + Sets the USB host controller to a specific state. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param State Indicates the state of the host controller that will be set. + + @retval EFI_SUCCESS The USB host controller was successfully placed in the state + specified by State. + @retval EFI_INVALID_PARAMETER State is not valid. + @retval EFI_DEVICE_ERROR Failed to set the state specified by State due to device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_SET_STATE)( + IN EFI_USB2_HC_PROTOCOL *This, + IN EFI_USB_HC_STATE State + ); + +/** + Submits control transfer to a target USB device. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param DeviceSpeed Indicates device speed. + @param MaximumPacketLength Indicates the maximum packet size that the default control transfer + endpoint is capable of sending or receiving. + @param Request A pointer to the USB device request that will be sent to the USB device. + @param TransferDirection Specifies the data direction for the transfer. There are three values + available, EfiUsbDataIn, EfiUsbDataOut and EfiUsbNoData. + @param Data A pointer to the buffer of data that will be transmitted to USB device or + received from USB device. + @param DataLength On input, indicates the size, in bytes, of the data buffer specified by Data. + On output, indicates the amount of data actually transferred. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer is + allowed to complete. + @param Translator A pointer to the transaction translator data. + @param TransferResult A pointer to the detailed result information generated by this control + transfer. + + @retval EFI_SUCCESS The control transfer was completed successfully. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The control transfer could not be completed due to a lack of resources. + @retval EFI_TIMEOUT The control transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The control transfer failed due to host controller or device error. + Caller should check TransferResult for detailed error information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaximumPacketLength, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION TransferDirection, + IN OUT VOID *Data OPTIONAL, + IN OUT UINTN *DataLength OPTIONAL, + IN UINTN TimeOut, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator, + OUT UINT32 *TransferResult + ); + +#define EFI_USB_MAX_BULK_BUFFER_NUM 10 + +/** + Submits bulk transfer to a bulk endpoint of a USB device. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param EndPointAddress The combination of an endpoint number and an endpoint direction of the + target USB device. + @param DeviceSpeed Indicates device speed. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of + sending or receiving. + @param DataBuffersNumber Number of data buffers prepared for the transfer. + @param Data Array of pointers to the buffers of data that will be transmitted to USB + device or received from USB device. + @param DataLength When input, indicates the size, in bytes, of the data buffers specified by + Data. When output, indicates the actually transferred data size. + @param DataToggle A pointer to the data toggle value. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer is + allowed to complete. + @param Translator A pointer to the transaction translator data. + @param TransferResult A pointer to the detailed result information of the bulk transfer. + + @retval EFI_SUCCESS The bulk transfer was completed successfully. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The bulk transfer could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The bulk transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. + Caller should check TransferResult for detailed error information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_BULK_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaximumPacketLength, + IN UINT8 DataBuffersNumber, + IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM], + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator, + OUT UINT32 *TransferResult + ); + +/** + Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. + Translator parameter doesn't exist in UEFI2.0 spec, but it will be updated in the following specification version. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param EndPointAddress The combination of an endpoint number and an endpoint direction of the + target USB device. + @param DeviceSpeed Indicates device speed. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of + sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between the host and the + target interrupt endpoint. If FALSE, the specified asynchronous interrupt + pipe is canceled. If TRUE, and an interrupt transfer exists for the target + end point, then EFI_INVALID_PARAMETER is returned. + @param DataToggle A pointer to the data toggle value. + @param PollingInterval Indicates the interval, in milliseconds, that the asynchronous interrupt + transfer is polled. + @param DataLength Indicates the length of data to be received at the rate specified by + PollingInterval from the target asynchronous interrupt endpoint. + @param Translator A pointr to the transaction translator data. + @param CallBackFunction The Callback function. This function is called at the rate specified by + PollingInterval. + @param Context The context that is passed to the CallBackFunction. This is an + optional parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaxiumPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle, + IN UINTN PollingInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL + ); + +/** + Submits synchronous interrupt transfer to an interrupt endpoint of a USB device. + Translator parameter doesn't exist in UEFI2.0 spec, but it will be updated in the following specification version. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param EndPointAddress The combination of an endpoint number and an endpoint direction of the + target USB device. + @param DeviceSpeed Indicates device speed. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of + sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted to USB device or + received from USB device. + @param DataLength On input, the size, in bytes, of the data buffer specified by Data. On + output, the number of bytes transferred. + @param DataToggle A pointer to the data toggle value. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer is + allowed to complete. + @param Translator A pointr to the transaction translator data. + @param TransferResult A pointer to the detailed result information from the synchronous + interrupt transfer. + + @retval EFI_SUCCESS The synchronous interrupt transfer was completed successfully. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The synchronous interrupt transfer could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The synchronous interrupt transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The synchronous interrupt transfer failed due to host controller or device error. + Caller should check TransferResult for detailed error information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator, + OUT UINT32 *TransferResult + ); + +#define EFI_USB_MAX_ISO_BUFFER_NUM 7 +#define EFI_USB_MAX_ISO_BUFFER_NUM1 2 + +/** + Submits isochronous transfer to an isochronous endpoint of a USB device. + + This function is used to submit isochronous transfer to a target endpoint of a USB device. + The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers are + used when working with isochronous date. It provides periodic, continuous communication between + the host and a device. Isochronous transfers can beused only by full-speed, high-speed, and + super-speed devices. + + High-speed isochronous transfers can be performed using multiple data buffers. The number of + buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For + full-speed isochronous transfers this value is ignored. + + Data represents a list of pointers to the data buffers. For full-speed isochronous transfers + only the data pointed by Data[0]shall be used. For high-speed isochronous transfers and for + the split transactions depending on DataLengththere several data buffers canbe used. For the + high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM. + + For split transactions performed on full-speed device by high-speed host controller the total + number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1. + If the isochronous transfer is successful, then EFI_SUCCESSis returned. The isochronous transfer + is designed to be completed within one USB frame time, if it cannot be completed, EFI_TIMEOUT + is returned. If an error other than timeout occurs during the USB transfer, then EFI_DEVICE_ERROR + is returned and the detailed status code will be returned in TransferResult. + + EFI_INVALID_PARAMETERis returned if one of the following conditionsis satisfied: + - Data is NULL. + - DataLength is 0. + - DeviceSpeed is not one of the supported values listed above. + - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed devices, + and 1024 or less for high-speed and super-speed devices. + - TransferResult is NULL. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param EndPointAddress The combination of an endpoint number and an endpoint direction of the + target USB device. + @param DeviceSpeed Indicates device speed. The supported values are EFI_USB_SPEED_FULL, + EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of + sending or receiving. + @param DataBuffersNumber Number of data buffers prepared for the transfer. + @param Data Array of pointers to the buffers of data that will be transmitted to USB + device or received from USB device. + @param DataLength Specifies the length, in bytes, of the data to be sent to or received from + the USB device. + @param Translator A pointer to the transaction translator data. + @param TransferResult A pointer to the detailed result information of the isochronous transfer. + + @retval EFI_SUCCESS The isochronous transfer was completed successfully. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The isochronous transfer could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The isochronous transfer cannot be completed within the one USB frame time. + @retval EFI_DEVICE_ERROR The isochronous transfer failed due to host controller or device error. + Caller should check TransferResult for detailed error information. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaximumPacketLength, + IN UINT8 DataBuffersNumber, + IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM], + IN UINTN DataLength, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator, + OUT UINT32 *TransferResult + ); + +/** + Submits nonblocking isochronous transfer to an isochronous endpoint of a USB device. + + This is an asynchronous type of USB isochronous transfer. If the caller submits a USB + isochronous transfer request through this function, this function will return immediately. + + When the isochronous transfer completes, the IsochronousCallbackfunction will be triggered, + the caller can know the transfer results. If the transfer is successful, the caller can get + the data received or sent in this callback function. + + The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers + are used when working with isochronous date. It provides periodic, continuous communication + between the host and a device. Isochronous transfers can be used only by full-speed, high-speed, + and super-speed devices. + + High-speed isochronous transfers can be performed using multiple data buffers. The number of + buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For + full-speed isochronous transfers this value is ignored. + + Data represents a list of pointers to the data buffers. For full-speed isochronous transfers + only the data pointed by Data[0] shall be used. For high-speed isochronous transfers and for + the split transactions depending on DataLength there several data buffers can be used. For + the high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM. + + For split transactions performed on full-speed device by high-speed host controller the total + number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1. + + EFI_INVALID_PARAMETER is returned if one of the following conditionsis satisfied: + - Data is NULL. + - DataLength is 0. + - DeviceSpeed is not one of the supported values listed above. + - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed + devices and 1024 or less for high-speed and super-speed devices. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB. + @param EndPointAddress The combination of an endpoint number and an endpoint direction of the + target USB device. + @param DeviceSpeed Indicates device speed. The supported values are EFI_USB_SPEED_FULL, + EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of + sending or receiving. + @param DataBuffersNumber Number of data buffers prepared for the transfer. + @param Data Array of pointers to the buffers of data that will be transmitted to USB + device or received from USB device. + @param DataLength Specifies the length, in bytes, of the data to be sent to or received from + the USB device. + @param Translator A pointer to the transaction translator data. + @param IsochronousCallback The Callback function. This function is called if the requested + isochronous transfer is completed. + @param Context Data passed to the IsochronousCallback function. This is an + optional parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous isochronous transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The asynchronous isochronous transfer could not be submitted due to + a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 DeviceSpeed, + IN UINTN MaximumPacketLength, + IN UINT8 DataBuffersNumber, + IN OUT VOID *Data[EFI_USB_MAX_ISO_BUFFER_NUM], + IN UINTN DataLength, + IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ); + +/** + Retrieves the current status of a USB root hub port. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port from which the status is to be retrieved. + This value is zero based. + @param PortStatus A pointer to the current port status bits and port status change bits. + + @retval EFI_SUCCESS The status of the USB root hub port specified by PortNumber + was returned in PortStatus. + @retval EFI_INVALID_PARAMETER PortNumber is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 PortNumber, + OUT EFI_USB_PORT_STATUS *PortStatus + ); + +/** + Sets a feature for the specified root hub port. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port whose feature is requested to be set. This + value is zero based. + @param PortFeature Indicates the feature selector associated with the feature set request. + + @retval EFI_SUCCESS The feature specified by PortFeature was set for the USB + root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); + +/** + Clears a feature for the specified root hub port. + + @param This A pointer to the EFI_USB2_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port whose feature is requested to be cleared. This + value is zero based. + @param PortFeature Indicates the feature selector associated with the feature clear request. + + @retval EFI_SUCCESS The feature specified by PortFeature was cleared for the USB + root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE)( + IN EFI_USB2_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); + +/// +/// The EFI_USB2_HC_PROTOCOL provides USB host controller management, basic +/// data transactions over a USB bus, and USB root hub access. A device driver +/// that wishes to manage a USB bus in a system retrieves the EFI_USB2_HC_PROTOCOL +/// instance that is associated with the USB bus to be managed. A device handle +/// for a USB host controller will minimally contain an EFI_DEVICE_PATH_PROTOCOL +/// instance, and an EFI_USB2_HC_PROTOCOL instance. +/// +struct _EFI_USB2_HC_PROTOCOL { + EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability; + EFI_USB2_HC_PROTOCOL_RESET Reset; + EFI_USB2_HC_PROTOCOL_GET_STATE GetState; + EFI_USB2_HC_PROTOCOL_SET_STATE SetState; + EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer; + EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer; + EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer; + EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer; + EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer; + EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer; + EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus; + EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature; + EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature; + + /// + /// The major revision number of the USB host controller. The revision information + /// indicates the release of the Universal Serial Bus Specification with which the + /// host controller is compliant. + /// + UINT16 MajorRevision; + + /// + /// The minor revision number of the USB host controller. The revision information + /// indicates the release of the Universal Serial Bus Specification with which the + /// host controller is compliant. + /// + UINT16 MinorRevision; +}; + +extern EFI_GUID gEfiUsb2HcProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbFunctionIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbFunctionIo.h new file mode 100644 index 0000000000..3461bfa7fb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbFunctionIo.h @@ -0,0 +1,684 @@ +/** @file + The USB Function Protocol provides an I/O abstraction for a USB Controller + operating in Function mode (also commonly referred to as Device, Peripheral, + or Target mode) and the mechanisms by which the USB Function can communicate + with the USB Host. It is used by other UEFI drivers or applications to + perform data transactions and basic USB controller management over a USB + Function port. + + This simple protocol only supports USB 2.0 bulk transfers on systems with a + single configuration and a single interface. It does not support isochronous + or interrupt transfers, alternate interfaces, or USB 3.0 functionality. + Future revisions of this protocol may support these or additional features. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol was introduced in UEFI Specification 2.5. + +**/ + +#ifndef __USB_FUNCTION_IO_H__ +#define __USB_FUNCTION_IO_H__ + +#include + +#define EFI_USBFN_IO_PROTOCOL_GUID \ + { \ + 0x32d2963a, 0xfe5d, 0x4f30, {0xb6, 0x33, 0x6e, 0x5d, 0xc5, 0x58, 0x3, 0xcc} \ + } + +typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL; + +#define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001 + +typedef enum _EFI_USBFN_PORT_TYPE { + EfiUsbUnknownPort = 0, + EfiUsbStandardDownstreamPort, + EfiUsbChargingDownstreamPort, + EfiUsbDedicatedChargingPort, + EfiUsbInvalidDedicatedChargingPort +} EFI_USBFN_PORT_TYPE; + +typedef struct { + EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor; + EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable; +} EFI_USB_INTERFACE_INFO; + +typedef struct { + EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor; + EFI_USB_INTERFACE_INFO **InterfaceInfoTable; +} EFI_USB_CONFIG_INFO; + +typedef struct { + EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor; + EFI_USB_CONFIG_INFO **ConfigInfoTable; +} EFI_USB_DEVICE_INFO; + +typedef enum _EFI_USB_ENDPOINT_TYPE { + UsbEndpointControl = 0x00, + //UsbEndpointIsochronous = 0x01, + UsbEndpointBulk = 0x02, + //UsbEndpointInterrupt = 0x03 +} EFI_USB_ENDPOINT_TYPE; + +typedef enum _EFI_USBFN_DEVICE_INFO_ID { + EfiUsbDeviceInfoUnknown = 0, + EfiUsbDeviceInfoSerialNumber, + EfiUsbDeviceInfoManufacturerName, + EfiUsbDeviceInfoProductName +} EFI_USBFN_DEVICE_INFO_ID; + +typedef enum _EFI_USBFN_ENDPOINT_DIRECTION { + EfiUsbEndpointDirectionHostOut = 0, + EfiUsbEndpointDirectionHostIn, + EfiUsbEndpointDirectionDeviceTx = EfiUsbEndpointDirectionHostIn, + EfiUsbEndpointDirectionDeviceRx = EfiUsbEndpointDirectionHostOut +} EFI_USBFN_ENDPOINT_DIRECTION; + +typedef enum _EFI_USBFN_MESSAGE { + // + // Nothing + // + EfiUsbMsgNone = 0, + // + // SETUP packet is received, returned Buffer contains + // EFI_USB_DEVICE_REQUEST struct + // + EfiUsbMsgSetupPacket, + // + // Indicates that some of the requested data has been received from the + // host. It is the responsibility of the class driver to determine if it + // needs to wait for any remaining data. Returned Buffer contains + // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer + // status and count of bytes received. + // + EfiUsbMsgEndpointStatusChangedRx, + // + // Indicates that some of the requested data has been transmitted to the + // host. It is the responsibility of the class driver to determine if any + // remaining data needs to be resent. Returned Buffer contains + // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer + // status and count of bytes sent. + // + EfiUsbMsgEndpointStatusChangedTx, + // + // DETACH bus event signaled + // + EfiUsbMsgBusEventDetach, + // + // ATTACH bus event signaled + // + EfiUsbMsgBusEventAttach, + // + // RESET bus event signaled + // + EfiUsbMsgBusEventReset, + // + // SUSPEND bus event signaled + // + EfiUsbMsgBusEventSuspend, + // + // RESUME bus event signaled + // + EfiUsbMsgBusEventResume, + // + // Bus speed updated, returned buffer indicated bus speed using + // following enumeration named EFI_USB_BUS_SPEED + // + EfiUsbMsgBusEventSpeed +} EFI_USBFN_MESSAGE; + +typedef enum _EFI_USBFN_TRANSFER_STATUS { + UsbTransferStatusUnknown = 0, + UsbTransferStatusComplete, + UsbTransferStatusAborted, + UsbTransferStatusActive, + UsbTransferStatusNone +} EFI_USBFN_TRANSFER_STATUS; + +typedef struct _EFI_USBFN_TRANSFER_RESULT { + UINTN BytesTransferred; + EFI_USBFN_TRANSFER_STATUS TransferStatus; + UINT8 EndpointIndex; + EFI_USBFN_ENDPOINT_DIRECTION Direction; + VOID *Buffer; +} EFI_USBFN_TRANSFER_RESULT; + +typedef enum _EFI_USB_BUS_SPEED { + UsbBusSpeedUnknown = 0, + UsbBusSpeedLow, + UsbBusSpeedFull, + UsbBusSpeedHigh, + UsbBusSpeedSuper, + UsbBusSpeedMaximum = UsbBusSpeedSuper +} EFI_USB_BUS_SPEED; + +typedef union _EFI_USBFN_MESSAGE_PAYLOAD { + EFI_USB_DEVICE_REQUEST udr; + EFI_USBFN_TRANSFER_RESULT utr; + EFI_USB_BUS_SPEED ubs; +} EFI_USBFN_MESSAGE_PAYLOAD; + +typedef enum _EFI_USBFN_POLICY_TYPE { + EfiUsbPolicyUndefined = 0, + EfiUsbPolicyMaxTransactionSize, + EfiUsbPolicyZeroLengthTerminationSupport, + EfiUsbPolicyZeroLengthTermination +} EFI_USBFN_POLICY_TYPE; + +/** + Returns information about what USB port type was attached. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[out] PortType Returns the USB port type. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to + process this request or there is no USB port + attached to the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_DETECT_PORT) ( + IN EFI_USBFN_IO_PROTOCOL *This, + OUT EFI_USBFN_PORT_TYPE *PortType + ); + +/** + Configures endpoints based on supplied device and configuration descriptors. + + Assuming that the hardware has already been initialized, this function configures + the endpoints using the device information supplied by DeviceInfo, activates the + port, and starts receiving USB events. + + This function must ignore the bMaxPacketSize0field of the Standard Device Descriptor + and the wMaxPacketSize field of the Standard Endpoint Descriptor that are made + available through DeviceInfo. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[out] DeviceInfo A pointer to EFI_USBFN_DEVICE_INFO instance. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of + resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) ( + IN EFI_USBFN_IO_PROTOCOL *This, + OUT EFI_USB_DEVICE_INFO *DeviceInfo + ); + +/** + Returns the maximum packet size of the specified endpoint type for the supplied + bus speed. + + If the BusSpeed is UsbBusSpeedUnknown, the maximum speed the underlying controller + supports is assumed. + + This protocol currently does not support isochronous or interrupt transfers. Future + revisions of this protocol may eventually support it. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOLinstance. + @param[in] EndpointType Endpoint type as defined as EFI_USB_ENDPOINT_TYPE. + @param[in] BusSpeed Bus speed as defined as EFI_USB_BUS_SPEED. + @param[out] MaxPacketSize The maximum packet size, in bytes, of the specified + endpoint type. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN EFI_USB_ENDPOINT_TYPE EndpointType, + IN EFI_USB_BUS_SPEED BusSpeed, + OUT UINT16 *MaxPacketSize + ); + +/** + Returns device specific information based on the supplied identifier as a Unicode string. + + If the supplied Buffer isn't large enough, or is NULL, the method fails with + EFI_BUFFER_TOO_SMALL and the required size is returned through BufferSize. All returned + strings are in Unicode format. + + An Id of EfiUsbDeviceInfoUnknown is treated as an invalid parameter. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOLinstance. + @param[in] Id The requested information id. + + + @param[in] BufferSize On input, the size of the Buffer in bytes. On output, the + amount of data returned in Buffer in bytes. + @param[out] Buffer A pointer to a buffer to returnthe requested information + as a Unicode string. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + BufferSize is NULL. + *BufferSize is not 0 and Buffer is NULL. + Id in invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_BUFFER_TOO_SMALL The buffer is too small to hold the buffer. + *BufferSize has been updated with the size needed to hold the request string. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_DEVICE_INFO) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN EFI_USBFN_DEVICE_INFO_ID Id, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer OPTIONAL +); + +/** + Returns the vendor-id and product-id of the device. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[out] Vid Returned vendor-id of the device. + @param[out] Pid Returned product-id of the device. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND Unable to return the vendor-id or the product-id. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) ( + IN EFI_USBFN_IO_PROTOCOL *This, + OUT UINT16 *Vid, + OUT UINT16 *Pid +); + +/** + Aborts the transfer on the specified endpoint. + + This function should fail with EFI_INVALID_PARAMETER if the specified direction + is incorrect for the endpoint. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the endpoint on which the ongoing transfer + needs to be canceled. + @param[in] Direction Direction of the endpoint. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_ABORT_TRANSFER) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction +); + +/** + Returns the stall state on the specified endpoint. + + This function should fail with EFI_INVALID_PARAMETER if the specified direction + is incorrect for the endpoint. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the endpoint. + @param[in] Direction Direction of the endpoint. + @param[in, out] State Boolean, true value indicates that the endpoint + is in a stalled state, false otherwise. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction, + IN OUT BOOLEAN *State +); + +/** + Sets or clears the stall state on the specified endpoint. + + This function should fail with EFI_INVALID_PARAMETER if the specified direction + is incorrect for the endpoint. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the endpoint. + @param[in] Direction Direction of the endpoint. + @param[in] State Requested stall state on the specified endpoint. + True value causes the endpoint to stall; false + value clears an existing stall. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction, + IN OUT BOOLEAN *State +); + +/** + This function is called repeatedly to get information on USB bus states, + receive-completion and transmit-completion events on the endpoints, and + notification on setup packet on endpoint 0. + + A class driver must call EFI_USBFN_IO_PROTOCOL.EventHandler()repeatedly + to receive updates on the transfer status and number of bytes transferred + on various endpoints. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[out] Message Indicates the event that initiated this notification. + @param[in, out] PayloadSize On input, the size of the memory pointed by + Payload. On output, the amount ofdata returned + in Payload. + @param[out] Payload A pointer to EFI_USBFN_MESSAGE_PAYLOAD instance + to return additional payload for current message. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + @retval EFI_BUFFER_TOO_SMALL The Supplied buffer is not large enough to hold + the message payload. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_EVENTHANDLER) ( + IN EFI_USBFN_IO_PROTOCOL *This, + OUT EFI_USBFN_MESSAGE *Message, + IN OUT UINTN *PayloadSize, + OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload +); + +/** + This function handles transferring data to or from the host on the specified + endpoint, depending on the direction specified. + + A class driver must call EFI_USBFN_IO_PROTOCOL.EventHandler() repeatedly to + receive updates on the transfer status and the number of bytes transferred on + various endpoints. Upon an update of the transfer status, the Buffer field of + the EFI_USBFN_TRANSFER_RESULT structure (as described in the function description + for EFI_USBFN_IO_PROTOCOL.EventHandler()) must be initialized with the Buffer + pointer that was supplied to this method. + + The overview of the call sequence is illustrated in the Figure 54. + + This function should fail with EFI_INVALID_PARAMETER if the specified direction + is incorrect for the endpoint. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the endpoint on which TX or RX transfer + needs to take place. + @param[in] Direction Direction of the endpoint. + @param[in, out] BufferSize If Direction is EfiUsbEndpointDirectionDeviceRx: + On input, the size of the Bufferin bytes. + On output, the amount of data returned in Buffer + in bytes. + If Direction is EfiUsbEndpointDirectionDeviceTx: + On input, the size of the Bufferin bytes. + On output, the amount of data transmitted in bytes. + @param[in, out] Buffer If Direction is EfiUsbEndpointDirectionDeviceRx: + The Buffer to return the received data. + If Directionis EfiUsbEndpointDirectionDeviceTx: + The Buffer that contains the data to be transmitted. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_TRANSFER) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction, + IN OUT UINTN *BufferSize, + IN OUT VOID *Buffer +); + +/** + Returns the maximum supported transfer size. + + Returns the maximum number of bytes that the underlying controller can accommodate + in a single transfer. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[out] MaxTransferSize The maximum supported transfer size, in bytes. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_NOT_READY The physical device is busy or not ready to process + this request. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) ( + IN EFI_USBFN_IO_PROTOCOL *This, + OUT UINTN *MaxTransferSize + ); + +/** + Allocates a transfer buffer of the specified sizethat satisfies the controller + requirements. + + The AllocateTransferBuffer() function allocates a memory region of Size bytes and + returns the address of the allocated memory that satisfies the underlying controller + requirements in the location referenced by Buffer. + + The allocated transfer buffer must be freed using a matching call to + EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer()function. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] Size The number of bytes to allocate for the transfer buffer. + @param[out] Buffer A pointer to a pointer to the allocated buffer if the + call succeeds; undefined otherwise. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_OUT_OF_RESOURCES The requested transfer buffer could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINTN Size, + OUT VOID **Buffer + ); + +/** + Deallocates the memory allocated for the transfer buffer by the + EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer() function. + + The EFI_USBFN_IO_PROTOCOL.FreeTransferBuffer() function deallocates the + memory specified by Buffer. The Buffer that is freed must have been allocated + by EFI_USBFN_IO_PROTOCOL.AllocateTransferBuffer(). + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] Buffer A pointer to the transfer buffer to deallocate. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_FREE_TRANSFER_BUFFER) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN VOID *Buffer + ); + +/** + This function supplies power to the USB controller if needed and initializes + the hardware and the internal data structures. The port must not be activated + by this function. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_START_CONTROLLER) ( + IN EFI_USBFN_IO_PROTOCOL *This + ); + +/** + This function stops the USB hardware device. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_STOP_CONTROLLER) ( + IN EFI_USBFN_IO_PROTOCOL *This + ); + +/** + This function sets the configuration policy for the specified non-control + endpoint. + + This function can only be called before EFI_USBFN_IO_PROTOCOL.StartController() + or after EFI_USBFN_IO_PROTOCOL.StopController() has been called. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the non-control endpoint for which the + policy needs to be set. + @param[in] Direction Direction of the endpoint. + @param[in] PolicyType Policy type the user is trying to set for the + specified non-control endpoint. + @param[in] BufferSize The size of the Bufferin bytes. + @param[in] Buffer The new value for the policy parameter that + PolicyType specifies. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The physical device reported an error. + @retval EFI_UNSUPPORTED Changing this policy value is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_POLICY) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction, + IN EFI_USBFN_POLICY_TYPE PolicyType, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + This function sets the configuration policy for the specified non-control + endpoint. + + This function can only be called before EFI_USBFN_IO_PROTOCOL.StartController() + or after EFI_USBFN_IO_PROTOCOL.StopController() has been called. + + @param[in] This A pointer to the EFI_USBFN_IO_PROTOCOL instance. + @param[in] EndpointIndex Indicates the non-control endpoint for which the + policy needs to be set. + @param[in] Direction Direction of the endpoint. + @param[in] PolicyType Policy type the user is trying to retrieve for + the specified non-control endpoint. + @param[in, out] BufferSize On input, the size of Bufferin bytes. On output, + the amount of data returned in Bufferin bytes. + @param[in, out] Buffer A pointer to a buffer to return requested endpoint + policy value. + + @retval EFI_SUCCESS The function returned successfully. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_DEVICE_ERROR The specified policy value is not supported. + @retval EFI_BUFFER_TOO_SMALL Supplied buffer is not large enough to hold requested + policy value. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_POLICY) ( + IN EFI_USBFN_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + IN EFI_USBFN_ENDPOINT_DIRECTION Direction, + IN EFI_USBFN_POLICY_TYPE PolicyType, + IN OUT UINTN *BufferSize, + IN OUT VOID *Buffer + ); + +/// +/// The EFI_USBFN_IO_PROTOCOL provides basic data transactions and basic USB +/// controller management for a USB Function port. +/// +struct _EFI_USBFN_IO_PROTOCOL { + UINT32 Revision; + EFI_USBFN_IO_DETECT_PORT DetectPort; + EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints; + EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize; + EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo; + EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId; + EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer; + EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState; + EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState; + EFI_USBFN_IO_EVENTHANDLER EventHandler; + EFI_USBFN_IO_TRANSFER Transfer; + EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize; + EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer; + EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer; + EFI_USBFN_IO_START_CONTROLLER StartController; + EFI_USBFN_IO_STOP_CONTROLLER StopController; + EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy; + EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy; +}; + +extern EFI_GUID gEfiUsbFunctionIoProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbHostController.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbHostController.h new file mode 100644 index 0000000000..184d2de450 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbHostController.h @@ -0,0 +1,502 @@ +/** @file + EFI_USB_HC_PROTOCOL as defined in EFI 1.10. + + The USB Host Controller Protocol is used by code, typically USB bus drivers, + running in the EFI boot services environment, to perform data transactions + over a USB bus. In addition, it provides an abstraction for the root hub of the USB bus. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _USB_HOSTCONTROLLER_H_ +#define _USB_HOSTCONTROLLER_H_ + +#include + +#define EFI_USB_HC_PROTOCOL_GUID \ + { \ + 0xf5089266, 0x1aa0, 0x4953, {0x97, 0xd8, 0x56, 0x2f, 0x8a, 0x73, 0xb5, 0x19 } \ + } + +/// +/// Forward reference for pure ANSI compatability +/// +typedef struct _EFI_USB_HC_PROTOCOL EFI_USB_HC_PROTOCOL; + +// +// Protocol definitions +// + +/** + Provides software reset for the USB host controller. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param Attributes A bit mask of the reset operation to perform. + + @retval EFI_SUCCESS The reset operation succeeded. + @retval EFI_UNSUPPORTED The type of reset specified by Attributes is not currently supported + by the host controller hardware. + @retval EFI_INVALID_PARAMETER Attributes is not valid. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to perform the reset operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_RESET)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT16 Attributes + ); + +/** + Retrieves current state of the USB host controller. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param State A pointer to the EFI_USB_HC_STATE data structure that + indicates current state of the USB host controller. + + @retval EFI_SUCCESS The state information of the host controller was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to retrieve the host controller's + current state. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_GET_STATE)( + IN EFI_USB_HC_PROTOCOL *This, + OUT EFI_USB_HC_STATE *State + ); + +/** + Sets the USB host controller to a specific state. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param State Indicates the state of the host controller that will be set. + + @retval EFI_SUCCESS The USB host controller was successfully placed in the state specified by + State. + @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_DEVICE_ERROR Failed to set the state specified by State due to device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_SET_STATE)( + IN EFI_USB_HC_PROTOCOL *This, + IN EFI_USB_HC_STATE State + ); + +/** + Submits control transfer to a target USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param IsSlowDevice Indicates whether the target device is slow device or full-speed + device. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. + @param Request A pointer to the USB device request that will be sent to the USB + device. + @param TransferDirection Specifies the data direction for the transfer. There are three + values available, EfiUsbDataIn, EfiUsbDataOut and EfiUsbNoData. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength On input, indicates the size, in bytes, of the data buffer specified + by Data. On output, indicates the amount of data actually + transferred. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer + is allowed to complete. + @param TransferResult A pointer to the detailed result information generated by this + control transfer. + + @retval EFI_SUCCESS The control transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The control transfer could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The control transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The control transfer failed due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_CONTROL_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaximumPacketLength, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION TransferDirection, + IN OUT VOID *Data OPTIONAL, + IN OUT UINTN *DataLength OPTIONAL, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); + +/** + Submits bulk transfer to a bulk endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the control + endpoint (whose default endpoint address is 0). It is the + caller's responsibility to make sure that the EndPointAddress + represents a bulk endpoint. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength On input, indicates the size, in bytes, of the data buffer specified + by Data. On output, indicates the amount of data actually + transferred. + @param DataToggle A pointer to the data toggle value. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer + is allowed to complete. + @param TransferResult A pointer to the detailed result information of the bulk transfer. + + @retval EFI_SUCCESS The bulk transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The bulk transfer could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The bulk transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_BULK_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); + +/** + Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the control + endpoint (whose default endpoint address is zero). It is the + caller's responsibility to make sure that the + EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device or full-speed + device. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between the host + and the target interrupt endpoint. If FALSE, the specified asynchronous + interrupt pipe is canceled. If TRUE, and an interrupt transfer exists + for the target end point, then EFI_INVALID_PARAMETER is returned. + @param DataToggle A pointer to the data toggle value. On input, it is valid when + IsNewTransfer is TRUE, and it indicates the initial data toggle + value the asynchronous interrupt transfer should adopt. On output, + it is valid when IsNewTransfer is FALSE, and it is updated to indicate + the data toggle value of the subsequent asynchronous interrupt transfer. + @param PollingInterval Indicates the interval, in milliseconds, that the asynchronous + interrupt transfer is polled. + @param DataLength Indicates the length of data to be received at the rate specified by + PollingInterval from the target asynchronous interrupt + endpoint. This parameter is only required when IsNewTransfer is TRUE. + @param CallBackFunction The Callback function. This function is called at the rate specified by + PollingInterval. This parameter is only required when IsNewTransfer is TRUE. + @param Context The context that is passed to the CallBackFunction. + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The bulk transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxiumPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle, + IN UINTN PollingInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL + ); + +/** + Submits synchronous interrupt transfer to an interrupt endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the control + endpoint (whose default endpoint address is zero). It is the + caller's responsibility to make sure that the + EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device or full-speed + device. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. asynchronous interrupt pipe is canceled. + @param DataLength On input, the size, in bytes, of the data buffer specified by Data. + On output, the number of bytes transferred. + @param DataToggle A pointer to the data toggle value. On input, it indicates the initial + data toggle value the synchronous interrupt transfer should adopt; + on output, it is updated to indicate the data toggle value of the + subsequent synchronous interrupt transfer. + @param TimeOut Indicates the maximum time, in milliseconds, which the transfer + is allowed to complete. + @param TransferResult A pointer to the detailed result information from the synchronous + interrupt transfer. + + @retval EFI_SUCCESS The synchronous interrupt transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The synchronous interrupt transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The synchronous interrupt transfer failed due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); + +/** + Submits isochronous transfer to an isochronous endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the control + endpoint (whose default endpoint address is 0). It is the caller's + responsibility to make sure that the EndPointAddress + represents an isochronous endpoint. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. asynchronous interrupt pipe is canceled. + @param DataLength Specifies the length, in bytes, of the data to be sent to or received + from the USB device. + @param TransferResult A pointer to the detailed result information from the isochronous + transfer. + + @retval EFI_SUCCESS The isochronous transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The isochronous could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The isochronous transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The isochronous transfer failed due to host controller or device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_ISOCHRONOUS_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN UINTN DataLength, + OUT UINT32 *TransferResult + ); + +/** + Submits nonblocking isochronous transfer to an isochronous endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, which is + assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the control + endpoint (whose default endpoint address is zero). It is the + caller's responsibility to make sure that the + EndPointAddress represents an isochronous endpoint. + @param MaximumPacketLength Indicates the maximum packet size that the default control + transfer endpoint is capable of sending or receiving. For isochronous + endpoints, this value is used to reserve the bus time in the schedule, + required for the perframe data payloads. The pipe may, on an ongoing basis, + actually use less bandwidth than that reserved. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. asynchronous interrupt pipe is canceled. + @param DataLength Specifies the length, in bytes, of the data to be sent to or received + from the USB device. + @param IsochronousCallback The Callback function.This function is called if the requested + isochronous transfer is completed. + @param Context Data passed to the IsochronousCallback function. This is + an optional parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous isochronous transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The asynchronous isochronous could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN UINTN DataLength, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ); + +/** + Retrieves the number of root hub ports. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber A pointer to the number of the root hub ports. + + @retval EFI_SUCCESS The port number was retrieved successfully. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to retrieve the port number. + @retval EFI_INVALID_PARAMETER PortNumber is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_NUMBER)( + IN EFI_USB_HC_PROTOCOL *This, + OUT UINT8 *PortNumber + ); + +/** + Retrieves the current status of a USB root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port from which the status is to be retrieved. + This value is zero based. For example, if a root hub has two ports, + then the first port is numbered 0, and the second port is + numbered 1. + @param PortStatus A pointer to the current port status bits and port status change bits. + + @retval EFI_SUCCESS The status of the USB root hub port specified by PortNumber + was returned in PortStatus. + @retval EFI_INVALID_PARAMETER PortNumber is invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + OUT EFI_USB_PORT_STATUS *PortStatus + ); + +/** + Sets a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port from which the status is to be retrieved. + This value is zero based. For example, if a root hub has two ports, + then the first port is numbered 0, and the second port is + numbered 1. + @param PortFeature Indicates the feature selector associated with the feature set + request. + + @retval EFI_SUCCESS The feature specified by PortFeature was set for the USB + root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); + +/** + Clears a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port from which the status is to be retrieved. + This value is zero based. For example, if a root hub has two ports, + then the first port is numbered 0, and the second port is + numbered 1. + @param PortFeature Indicates the feature selector associated with the feature clear + request. + + @retval EFI_SUCCESS The feature specified by PortFeature was cleared for the USB + root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE)( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); + + +/// +/// The EFI_USB_HC_PROTOCOL provides USB host controller management, basic data transactions +/// over a USB bus, and USB root hub access. A device driver that wishes to manage a USB bus in a +/// system retrieves the EFI_USB_HC_PROTOCOL instance that is associated with the USB bus to be +/// managed. A device handle for a USB host controller will minimally contain an +/// EFI_DEVICE_PATH_PROTOCOL instance, and an EFI_USB_HC_PROTOCOL instance. +/// +struct _EFI_USB_HC_PROTOCOL { + EFI_USB_HC_PROTOCOL_RESET Reset; + EFI_USB_HC_PROTOCOL_GET_STATE GetState; + EFI_USB_HC_PROTOCOL_SET_STATE SetState; + EFI_USB_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer; + EFI_USB_HC_PROTOCOL_BULK_TRANSFER BulkTransfer; + EFI_USB_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer; + EFI_USB_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer; + EFI_USB_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer; + EFI_USB_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer; + EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_NUMBER GetRootHubPortNumber; + EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus; + EFI_USB_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature; + EFI_USB_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature; + /// + /// The major revision number of the USB host controller. The revision information + /// indicates the release of the Universal Serial Bus Specification with which the + /// host controller is compliant. + /// + UINT16 MajorRevision; + /// + /// The minor revision number of the USB host controller. The revision information + /// indicates the release of the Universal Serial Bus Specification with which the + /// host controller is compliant. + /// + UINT16 MinorRevision; +}; + +extern EFI_GUID gEfiUsbHcProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbIo.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbIo.h new file mode 100644 index 0000000000..dec2465211 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UsbIo.h @@ -0,0 +1,506 @@ +/** @file + EFI Usb I/O Protocol as defined in UEFI specification. + This protocol is used by code, typically drivers, running in the EFI + boot services environment to access USB devices like USB keyboards, + mice and mass storage devices. In particular, functions for managing devices + on USB buses are defined here. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USB_IO_H__ +#define __USB_IO_H__ + +#include + +// +// Global ID for the USB I/O Protocol +// +#define EFI_USB_IO_PROTOCOL_GUID \ + { \ + 0x2B2F68D6, 0x0CD2, 0x44cf, {0x8E, 0x8B, 0xBB, 0xA2, 0x0B, 0x1B, 0x5B, 0x75 } \ + } + +typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL; + +// +// Related Definition for EFI USB I/O protocol +// + +// +// USB standard descriptors and reqeust +// +typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST; +typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR; +typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR; +typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR; +typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR; + +/// +/// USB data transfer direction +/// +typedef enum { + EfiUsbDataIn, + EfiUsbDataOut, + EfiUsbNoData +} EFI_USB_DATA_DIRECTION; + +// +// USB Transfer Results +// +#define EFI_USB_NOERROR 0x00 +#define EFI_USB_ERR_NOTEXECUTE 0x01 +#define EFI_USB_ERR_STALL 0x02 +#define EFI_USB_ERR_BUFFER 0x04 +#define EFI_USB_ERR_BABBLE 0x08 +#define EFI_USB_ERR_NAK 0x10 +#define EFI_USB_ERR_CRC 0x20 +#define EFI_USB_ERR_TIMEOUT 0x40 +#define EFI_USB_ERR_BITSTUFF 0x80 +#define EFI_USB_ERR_SYSTEM 0x100 + +/** + Async USB transfer callback routine. + + @param Data Data received or sent via the USB Asynchronous Transfer, if the + transfer completed successfully. + @param DataLength The length of Data received or sent via the Asynchronous + Transfer, if transfer successfully completes. + @param Context Data passed from UsbAsyncInterruptTransfer() request. + @param Status Indicates the result of the asynchronous transfer. + + @retval EFI_SUCCESS The asynchronous USB transfer request has been successfully executed. + @retval EFI_DEVICE_ERROR The asynchronous USB transfer request failed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ASYNC_USB_TRANSFER_CALLBACK)( + IN VOID *Data, + IN UINTN DataLength, + IN VOID *Context, + IN UINT32 Status + ); + +// +// Prototype for EFI USB I/O protocol +// + + +/** + This function is used to manage a USB device with a control transfer pipe. A control transfer is + typically used to perform device initialization and configuration. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param Request A pointer to the USB device request that will be sent to the USB + device. + @param Direction Indicates the data direction. + @param Timeout Indicating the transfer should be completed within this time frame. + The units are in milliseconds. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength The size, in bytes, of the data buffer specified by Data. + @param Status A pointer to the result of the USB transfer. + + @retval EFI_SUCCESS The control transfer has been successfully executed. + @retval EFI_DEVICE_ERROR The transfer failed. The transfer status is returned in Status. + @retval EFI_INVALID_PARAMETE One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_TIMEOUT The control transfer fails due to timeout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_CONTROL_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION Direction, + IN UINT32 Timeout, + IN OUT VOID *Data OPTIONAL, + IN UINTN DataLength OPTIONAL, + OUT UINT32 *Status + ); + +/** + This function is used to manage a USB device with the bulk transfer pipe. Bulk Transfers are + typically used to transfer large amounts of data to/from USB devices. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceEndpoint The destination USB device endpoint to which the + device request is being sent. DeviceEndpoint must + be between 0x01 and 0x0F or between 0x81 and 0x8F, + otherwise EFI_INVALID_PARAMETER is returned. If + the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER + is returned. The MSB of this parameter indicates + the endpoint direction. The number "1" stands for + an IN endpoint, and "0" stands for an OUT endpoint. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength The size, in bytes, of the data buffer specified by Data. + On input, the size, in bytes, of the data buffer specified by Data. + On output, the number of bytes that were actually transferred. + @param Timeout Indicating the transfer should be completed within this time frame. + The units are in milliseconds. If Timeout is 0, then the + caller must wait for the function to be completed until + EFI_SUCCESS or EFI_DEVICE_ERROR is returned. + @param Status This parameter indicates the USB transfer status. + + @retval EFI_SUCCESS The bulk transfer has been successfully executed. + @retval EFI_DEVICE_ERROR The transfer failed. The transfer status is returned in Status. + @retval EFI_INVALID_PARAMETE One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The control transfer fails due to timeout. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_BULK_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN UINTN Timeout, + OUT UINT32 *Status + ); + +/** + This function is used to manage a USB device with an interrupt transfer pipe. An Asynchronous + Interrupt Transfer is typically used to query a device's status at a fixed rate. For example, + keyboard, mouse, and hub devices use this type of transfer to query their interrupt endpoints at + a fixed rate. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceEndpoint The destination USB device endpoint to which the + device request is being sent. DeviceEndpoint must + be between 0x01 and 0x0F or between 0x81 and 0x8F, + otherwise EFI_INVALID_PARAMETER is returned. If + the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER + is returned. The MSB of this parameter indicates + the endpoint direction. The number "1" stands for + an IN endpoint, and "0" stands for an OUT endpoint. + @param IsNewTransfer If TRUE, a new transfer will be submitted to USB controller. If + FALSE, the interrupt transfer is deleted from the device's interrupt + transfer queue. + @param PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be + executed.This parameter is required when IsNewTransfer is TRUE. The + value must be between 1 to 255, otherwise EFI_INVALID_PARAMETER is returned. + The units are in milliseconds. + @param DataLength Specifies the length, in bytes, of the data to be received from the + USB device. This parameter is only required when IsNewTransfer is TRUE. + @param InterruptCallback The Callback function. This function is called if the asynchronous + interrupt transfer is completed. This parameter is required + when IsNewTransfer is TRUE. + @param Context Data passed to the InterruptCallback function. This is an optional + parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous USB transfer request transfer has been successfully executed. + @retval EFI_DEVICE_ERROR The asynchronous USB transfer request failed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN BOOLEAN IsNewTransfer, + IN UINTN PollingInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack OPTIONAL, + IN VOID *Context OPTIONAL + ); + +/** + This function is used to manage a USB device with an interrupt transfer pipe. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceEndpoint The destination USB device endpoint to which the + device request is being sent. DeviceEndpoint must + be between 0x01 and 0x0F or between 0x81 and 0x8F, + otherwise EFI_INVALID_PARAMETER is returned. If + the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER + is returned. The MSB of this parameter indicates + the endpoint direction. The number "1" stands for + an IN endpoint, and "0" stands for an OUT endpoint. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength On input, then size, in bytes, of the buffer Data. On output, the + amount of data actually transferred. + @param Timeout The time out, in seconds, for this transfer. If Timeout is 0, + then the caller must wait for the function to be completed + until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. If the + transfer is not completed in this time frame, then EFI_TIMEOUT is returned. + @param Status This parameter indicates the USB transfer status. + + @retval EFI_SUCCESS The sync interrupt transfer has been successfully executed. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_DEVICE_ERROR The sync interrupt transfer request failed. + @retval EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The transfer fails due to timeout. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_SYNC_INTERRUPT_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN UINTN Timeout, + OUT UINT32 *Status + ); + +/** + This function is used to manage a USB device with an isochronous transfer pipe. An Isochronous + transfer is typically used to transfer streaming data. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceEndpoint The destination USB device endpoint to which the + device request is being sent. DeviceEndpoint must + be between 0x01 and 0x0F or between 0x81 and 0x8F, + otherwise EFI_INVALID_PARAMETER is returned. If + the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER + is returned. The MSB of this parameter indicates + the endpoint direction. The number "1" stands for + an IN endpoint, and "0" stands for an OUT endpoint. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength The size, in bytes, of the data buffer specified by Data. + @param Status This parameter indicates the USB transfer status. + + @retval EFI_SUCCESS The isochronous transfer has been successfully executed. + @retval EFI_INVALID_PARAMETER The parameter DeviceEndpoint is not valid. + @retval EFI_DEVICE_ERROR The transfer failed due to the reason other than timeout, The error status + is returned in Status. + @retval EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources. + @retval EFI_TIMEOUT The transfer fails due to timeout. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_ISOCHRONOUS_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN UINTN DataLength, + OUT UINT32 *Status + ); + +/** + This function is used to manage a USB device with an isochronous transfer pipe. An Isochronous + transfer is typically used to transfer streaming data. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceEndpoint The destination USB device endpoint to which the + device request is being sent. DeviceEndpoint must + be between 0x01 and 0x0F or between 0x81 and 0x8F, + otherwise EFI_INVALID_PARAMETER is returned. If + the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER + is returned. The MSB of this parameter indicates + the endpoint direction. The number "1" stands for + an IN endpoint, and "0" stands for an OUT endpoint. + @param Data A pointer to the buffer of data that will be transmitted to USB + device or received from USB device. + @param DataLength The size, in bytes, of the data buffer specified by Data. + This is an optional parameter and may be NULL. + @param IsochronousCallback The IsochronousCallback() function.This function is + called if the requested isochronous transfer is completed. + @param Context Data passed to the IsochronousCallback() function. + + @retval EFI_SUCCESS The asynchronous isochronous transfer has been successfully submitted + to the system. + @retval EFI_INVALID_PARAMETER The parameter DeviceEndpoint is not valid. + @retval EFI_OUT_OF_RESOURCES The request could not be submitted due to a lack of resources. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 DeviceEndpoint, + IN OUT VOID *Data, + IN UINTN DataLength, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ); + +/** + Resets and reconfigures the USB controller. This function will work for all USB devices except + USB Hub Controllers. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + + @retval EFI_SUCCESS The USB controller was reset. + @retval EFI_INVALID_PARAMETER If the controller specified by This is a USB hub. + @retval EFI_DEVICE_ERROR An error occurred during the reconfiguration process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_PORT_RESET)( + IN EFI_USB_IO_PROTOCOL *This + ); + +/** + Retrieves the USB Device Descriptor. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param DeviceDescriptor A pointer to the caller allocated USB Device Descriptor. + + @retval EFI_SUCCESS The device descriptor was retrieved successfully. + @retval EFI_INVALID_PARAMETER DeviceDescriptor is NULL. + @retval EFI_NOT_FOUND The device descriptor was not found. The device may not be configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_DEVICE_DESCRIPTOR)( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor + ); + +/** + Retrieves the USB Device Descriptor. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param ConfigurationDescriptor A pointer to the caller allocated USB Active Configuration + Descriptor. + @retval EFI_SUCCESS The active configuration descriptor was retrieved successfully. + @retval EFI_INVALID_PARAMETER ConfigurationDescriptor is NULL. + @retval EFI_NOT_FOUND An active configuration descriptor cannot be found. The device may not + be configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_CONFIG_DESCRIPTOR)( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_CONFIG_DESCRIPTOR *ConfigurationDescriptor + ); + +/** + Retrieves the Interface Descriptor for a USB Device Controller. As stated earlier, an interface + within a USB device is equivalently to a USB Controller within the current configuration. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param InterfaceDescriptor A pointer to the caller allocated USB Interface Descriptor within + the configuration setting. + @retval EFI_SUCCESS The interface descriptor retrieved successfully. + @retval EFI_INVALID_PARAMETER InterfaceDescriptor is NULL. + @retval EFI_NOT_FOUND The interface descriptor cannot be found. The device may not be + correctly configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_INTERFACE_DESCRIPTOR)( + IN EFI_USB_IO_PROTOCOL *This, + OUT EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor + ); + +/** + Retrieves an Endpoint Descriptor within a USB Controller. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param EndpointIndex Indicates which endpoint descriptor to retrieve. + @param EndpointDescriptor A pointer to the caller allocated USB Endpoint Descriptor of + a USB controller. + + @retval EFI_SUCCESS The endpoint descriptor was retrieved successfully. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_NOT_FOUND The endpoint descriptor cannot be found. The device may not be + correctly configured. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT8 EndpointIndex, + OUT EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDescriptor + ); + +/** + Retrieves a string stored in a USB Device. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param LangID The Language ID for the string being retrieved. + @param StringID The ID of the string being retrieved. + @param String A pointer to a buffer allocated by this function with + AllocatePool() to store the string.If this function + returns EFI_SUCCESS, it stores the string the caller + wants to get. The caller should release the string + buffer with FreePool() after the string is not used any more. + + @retval EFI_SUCCESS The string was retrieved successfully. + @retval EFI_NOT_FOUND The string specified by LangID and StringID was not found. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the return buffer String. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_STRING_DESCRIPTOR)( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 LangID, + IN UINT8 StringID, + OUT CHAR16 **String + ); + +/** + Retrieves all the language ID codes that the USB device supports. + + @param This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param LangIDTable Language ID for the string the caller wants to get. + This is a 16-bit ID defined by Microsoft. This + buffer pointer is allocated and maintained by + the USB Bus Driver, the caller should not modify + its contents. + @param TableSize The size, in bytes, of the table LangIDTable. + + @retval EFI_SUCCESS The support languages were retrieved successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USB_IO_GET_SUPPORTED_LANGUAGE)( + IN EFI_USB_IO_PROTOCOL *This, + OUT UINT16 **LangIDTable, + OUT UINT16 *TableSize + ); + +/// +/// The EFI_USB_IO_PROTOCOL provides four basic transfers types described +/// in the USB 1.1 Specification. These include control transfer, interrupt +/// transfer, bulk transfer and isochronous transfer. The EFI_USB_IO_PROTOCOL +/// also provides some basic USB device/controller management and configuration +/// interfaces. A USB device driver uses the services of this protocol to manage USB devices. +/// +struct _EFI_USB_IO_PROTOCOL { + // + // IO transfer + // + EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer; + EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer; + EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer; + EFI_USB_IO_SYNC_INTERRUPT_TRANSFER UsbSyncInterruptTransfer; + EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer; + EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer; + + // + // Common device request + // + EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor; + EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor; + EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor; + EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor; + EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor; + EFI_USB_IO_GET_SUPPORTED_LANGUAGE UsbGetSupportedLanguages; + + // + // Reset controller's parent port + // + EFI_USB_IO_PORT_RESET UsbPortReset; +}; + +extern EFI_GUID gEfiUsbIoProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential.h new file mode 100644 index 0000000000..d572f97b77 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential.h @@ -0,0 +1,286 @@ +/** @file + UEFI 2.2 User Credential Protocol definition.It has been removed from UEFI 2.3.1 and replaced + by EFI_USER_CREDENTIAL2_PROTOCOL. + + Attached to a device handle, this protocol identifies a single means of identifying the user. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USER_CREDENTIAL_H__ +#define __USER_CREDENTIAL_H__ + +#include + +#define EFI_USER_CREDENTIAL_PROTOCOL_GUID \ + { \ + 0x71ee5e94, 0x65b9, 0x45d5, { 0x82, 0x1a, 0x3a, 0x4d, 0x86, 0xcf, 0xe6, 0xbe } \ + } + +typedef struct _EFI_USER_CREDENTIAL_PROTOCOL EFI_USER_CREDENTIAL_PROTOCOL; + +/** + Enroll a user on a credential provider. + + This function enrolls and deletes a user profile using this credential provider. If a user profile + is successfully enrolled, it calls the User Manager Protocol function Notify() to notify the user + manager driver that credential information has changed. If an enrolled user does exist, delete the + user on the credential provider. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[in] User The user profile to enroll. + + @retval EFI_SUCCESS User profile was successfully enrolled. + @retval EFI_ACCESS_DENIED Current user profile does not permit enrollment on the user profile + handle. Either the user profile cannot enroll on any user profile or + cannot enroll on a user profile other than the current user profile. + @retval EFI_UNSUPPORTED This credential provider does not support enrollment in the pre-OS. + @retval EFI_DEVICE_ERROR The new credential could not be created because of a device error. + @retval EFI_INVALID_PARAMETER User does not refer to a valid user profile handle. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_ENROLL)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User + ); + +/** + Returns the user interface information used during user identification. + + This function returns information about the form used when interacting with the user during user + identification. The form is the first enabled form in the form-set class + EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If + the user credential provider does not require a form to identify the user, then this function should + return EFI_NOT_FOUND. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[out] Hii On return, holds the HII database handle. + @param[out] FormSetId On return, holds the identifier of the form set which contains + the form used during user identification. + @param[out] FormId On return, holds the identifier of the form used during user + identification. + + @retval EFI_SUCCESS Form returned successfully. + @retval EFI_NOT_FOUND Form not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or FormSetId is NULL or FormId is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_FORM)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_GUID *FormSetId, + OUT EFI_FORM_ID *FormId + ); + +/** + Returns bitmap used to describe the credential provider type. + + This optional function returns a bitmap which is less than or equal to the number of pixels specified + by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[in, out] Width On entry, points to the desired bitmap width. If NULL then no bitmap + information will be returned. On exit, points to the width of the + bitmap returned. + @param[in, out] Height On entry, points to the desired bitmap height. If NULL then no bitmap + information will be returned. On exit, points to the height of the + bitmap returned + @param[out] Hii On return, holds the HII database handle. + @param[out] Image On return, holds the HII image identifier. + + @retval EFI_SUCCESS Image identifier returned successfully. + @retval EFI_NOT_FOUND Image identifier not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or Image is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_TILE)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + IN OUT UINTN *Width, + IN OUT UINTN *Height, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_IMAGE_ID *Image + ); + +/** + Returns string used to describe the credential provider type. + + This function returns a string which describes the credential provider. If no such string exists, then + EFI_NOT_FOUND is returned. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[out] Hii On return, holds the HII database handle. + @param[out] String On return, holds the HII string identifier. + + @retval EFI_SUCCESS String identifier returned successfully. + @retval EFI_NOT_FOUND String identifier not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or String is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_TITLE)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_STRING_ID *String + ); + +/** + Return the user identifier associated with the currently authenticated user. + + This function returns the user identifier of the user authenticated by this credential provider. This + function is called after the credential-related information has been submitted on a form OR after a + call to Default() has returned that this credential is ready to log on. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[in] User The user profile handle of the user profile currently being considered + by the user identity manager. If NULL, then no user profile is currently + under consideration. + @param[out] Identifier On return, points to the user identifier. + + @retval EFI_SUCCESS User identifier returned successfully. + @retval EFI_NOT_READY No user identifier can be returned. + @retval EFI_ACCESS_DENIED The user has been locked out of this user credential. + @retval EFI_NOT_FOUND User is not NULL, and the specified user handle can't be found in user + profile database + @retval EFI_INVALID_PARAMETER Identifier is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_USER)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + OUT EFI_USER_INFO_IDENTIFIER *Identifier + ); + +/** + Indicate that user interface interaction has begun for the specified credential. + + This function is called when a credential provider is selected by the user. If AutoLogon returns + FALSE, then the user interface will be constructed by the User Identity Manager. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[out] AutoLogon On return, points to the credential provider's capabilities after + the credential provider has been selected by the user. + + @retval EFI_SUCCESS Credential provider successfully selected. + @retval EFI_INVALID_PARAMETER AutoLogon is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_SELECT)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + OUT EFI_CREDENTIAL_LOGON_FLAGS *AutoLogon + ); + +/** + Indicate that user interface interaction has ended for the specified credential. + + This function is called when a credential provider is deselected by the user. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + + @retval EFI_SUCCESS Credential provider successfully deselected. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_DESELECT)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This + ); + +/** + Return the default logon behavior for this user credential. + + This function reports the default login behavior regarding this credential provider. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[out] AutoLogon On return, holds whether the credential provider should be + used by default to automatically log on the user. + + @retval EFI_SUCCESS Default information successfully returned. + @retval EFI_INVALID_PARAMETER AutoLogon is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_DEFAULT)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + OUT EFI_CREDENTIAL_LOGON_FLAGS *AutoLogon + ); + +/** + Return information attached to the credential provider. + + This function returns user information. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[in] UserInfo Handle of the user information data record. + @param[out] Info On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user + information. If the buffer is too small to hold the information, then + EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the + number of bytes actually required. + @param[in,out] InfoSize On entry, points to the size of Info. On return, points to the size of the user + information. + + @retval EFI_SUCCESS Information returned successfully. + @retval EFI_BUFFER_TOO_SMALL The size specified by InfoSize is too small to hold all of the user + information. The size required is returned in *InfoSize. + @retval EFI_NOT_FOUND The specified UserInfo does not refer to a valid user info handle. + @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_GET_INFO)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + IN EFI_USER_INFO_HANDLE UserInfo, + OUT EFI_USER_INFO *Info, + IN OUT UINTN *InfoSize + ); + +/** + Enumerate all of the user information records on the credential provider. + + This function returns the next user information record. To retrieve the first user information record + handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information + record handle until there are no more, at which point UserInfo will point to NULL. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL. + @param[in,out] UserInfo On entry, points to the previous user information handle or NULL to + start enumeration. On exit, points to the next user information handle + or NULL if there is no more user information. + + @retval EFI_SUCCESS User information returned. + @retval EFI_NOT_FOUND No more user information found. + @retval EFI_INVALID_PARAMETER UserInfo is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL_GET_NEXT_INFO)( + IN CONST EFI_USER_CREDENTIAL_PROTOCOL *This, + IN OUT EFI_USER_INFO_HANDLE *UserInfo + ); + +/// +/// This protocol provides support for a single class of credentials +/// +struct _EFI_USER_CREDENTIAL_PROTOCOL { + EFI_GUID Identifier; ///< Uniquely identifies this credential provider. + EFI_GUID Type; ///< Identifies this class of User Credential Provider. + EFI_CREDENTIAL_ENROLL Enroll; + EFI_CREDENTIAL_FORM Form; + EFI_CREDENTIAL_TILE Tile; + EFI_CREDENTIAL_TITLE Title; + EFI_CREDENTIAL_USER User; + EFI_CREDENTIAL_SELECT Select; + EFI_CREDENTIAL_DESELECT Deselect; + EFI_CREDENTIAL_DEFAULT Default; + EFI_CREDENTIAL_GET_INFO GetInfo; + EFI_CREDENTIAL_GET_NEXT_INFO GetNextInfo; + EFI_CREDENTIAL_CAPABILITIES Capabilities; +}; + +extern EFI_GUID gEfiUserCredentialProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential2.h new file mode 100644 index 0000000000..e5adb66276 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserCredential2.h @@ -0,0 +1,308 @@ +/** @file + UEFI 2.3.1 User Credential Protocol definition. + + Attached to a device handle, this protocol identifies a single means of identifying the user. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USER_CREDENTIAL2_H__ +#define __USER_CREDENTIAL2_H__ + +#include + +#define EFI_USER_CREDENTIAL2_PROTOCOL_GUID \ + { \ + 0xe98adb03, 0xb8b9, 0x4af8, { 0xba, 0x20, 0x26, 0xe9, 0x11, 0x4c, 0xbc, 0xe5 } \ + } + +typedef struct _EFI_USER_CREDENTIAL2_PROTOCOL EFI_USER_CREDENTIAL2_PROTOCOL; + +/** + Enroll a user on a credential provider. + + This function enrolls a user on this credential provider. If the user exists on this credential + provider, update the user information on this credential provider; otherwise add the user information + on credential provider. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in] User The user profile to enroll. + + @retval EFI_SUCCESS User profile was successfully enrolled. + @retval EFI_ACCESS_DENIED Current user profile does not permit enrollment on the user profile + handle. Either the user profile cannot enroll on any user profile or + cannot enroll on a user profile other than the current user profile. + @retval EFI_UNSUPPORTED This credential provider does not support enrollment in the pre-OS. + @retval EFI_DEVICE_ERROR The new credential could not be created because of a device error. + @retval EFI_INVALID_PARAMETER User does not refer to a valid user profile handle. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_ENROLL)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User + ); + +/** + Returns the user interface information used during user identification. + + This function returns information about the form used when interacting with the user during user + identification. The form is the first enabled form in the form-set class + EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If + the user credential provider does not require a form to identify the user, then this function should + return EFI_NOT_FOUND. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[out] Hii On return, holds the HII database handle. + @param[out] FormSetId On return, holds the identifier of the form set which contains + the form used during user identification. + @param[out] FormId On return, holds the identifier of the form used during user + identification. + + @retval EFI_SUCCESS Form returned successfully. + @retval EFI_NOT_FOUND Form not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or FormSetId is NULL or FormId is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_FORM)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_GUID *FormSetId, + OUT EFI_FORM_ID *FormId + ); + +/** + Returns bitmap used to describe the credential provider type. + + This optional function returns a bitmap which is less than or equal to the number of pixels specified + by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in, out] Width On entry, points to the desired bitmap width. If NULL then no bitmap + information will be returned. On exit, points to the width of the + bitmap returned. + @param[in, out] Height On entry, points to the desired bitmap height. If NULL then no bitmap + information will be returned. On exit, points to the height of the + bitmap returned + @param[out] Hii On return, holds the HII database handle. + @param[out] Image On return, holds the HII image identifier. + + @retval EFI_SUCCESS Image identifier returned successfully. + @retval EFI_NOT_FOUND Image identifier not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or Image is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_TILE)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN OUT UINTN *Width, + IN OUT UINTN *Height, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_IMAGE_ID *Image + ); + +/** + Returns string used to describe the credential provider type. + + This function returns a string which describes the credential provider. If no such string exists, then + EFI_NOT_FOUND is returned. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[out] Hii On return, holds the HII database handle. + @param[out] String On return, holds the HII string identifier. + + @retval EFI_SUCCESS String identifier returned successfully. + @retval EFI_NOT_FOUND String identifier not returned. + @retval EFI_INVALID_PARAMETER Hii is NULL or String is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_TITLE)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + OUT EFI_HII_HANDLE *Hii, + OUT EFI_STRING_ID *String + ); + +/** + Return the user identifier associated with the currently authenticated user. + + This function returns the user identifier of the user authenticated by this credential provider. This + function is called after the credential-related information has been submitted on a form OR after a + call to Default() has returned that this credential is ready to log on. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in] User The user profile handle of the user profile currently being considered + by the user identity manager. If NULL, then no user profile is currently + under consideration. + @param[out] Identifier On return, points to the user identifier. + + @retval EFI_SUCCESS User identifier returned successfully. + @retval EFI_NOT_READY No user identifier can be returned. + @retval EFI_ACCESS_DENIED The user has been locked out of this user credential. + @retval EFI_NOT_FOUND User is not NULL, and the specified user handle can't be found in user + profile database + @retval EFI_INVALID_PARAMETER Identifier is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_USER)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + OUT EFI_USER_INFO_IDENTIFIER *Identifier + ); + +/** + Indicate that user interface interaction has begun for the specified credential. + + This function is called when a credential provider is selected by the user. If AutoLogon returns + FALSE, then the user interface will be constructed by the User Identity Manager. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[out] AutoLogon On return, points to the credential provider's capabilities after + the credential provider has been selected by the user. + + @retval EFI_SUCCESS Credential provider successfully selected. + @retval EFI_INVALID_PARAMETER AutoLogon is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_SELECT)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + OUT EFI_CREDENTIAL_LOGON_FLAGS *AutoLogon + ); + +/** + Indicate that user interface interaction has ended for the specified credential. + + This function is called when a credential provider is deselected by the user. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + + @retval EFI_SUCCESS Credential provider successfully deselected. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_DESELECT)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This + ); + +/** + Return the default logon behavior for this user credential. + + This function reports the default login behavior regarding this credential provider. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[out] AutoLogon On return, holds whether the credential provider should be + used by default to automatically log on the user. + + @retval EFI_SUCCESS Default information successfully returned. + @retval EFI_INVALID_PARAMETER AutoLogon is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_DEFAULT)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + OUT EFI_CREDENTIAL_LOGON_FLAGS *AutoLogon + ); + +/** + Return information attached to the credential provider. + + This function returns user information. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in] UserInfo Handle of the user information data record. + @param[out] Info On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user + information. If the buffer is too small to hold the information, then + EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the + number of bytes actually required. + @param[in,out] InfoSize On entry, points to the size of Info. On return, points to the size of the user + information. + + @retval EFI_SUCCESS Information returned successfully. + @retval EFI_BUFFER_TOO_SMALL The size specified by InfoSize is too small to hold all of the user + information. The size required is returned in *InfoSize. + @retval EFI_NOT_FOUND The specified UserInfo does not refer to a valid user info handle. + @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_GET_INFO)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN EFI_USER_INFO_HANDLE UserInfo, + OUT EFI_USER_INFO *Info, + IN OUT UINTN *InfoSize + ); + +/** + Enumerate all of the user information records on the credential provider. + + This function returns the next user information record. To retrieve the first user information record + handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information + record handle until there are no more, at which point UserInfo will point to NULL. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in,out] UserInfo On entry, points to the previous user information handle or NULL to + start enumeration. On exit, points to the next user information handle + or NULL if there is no more user information. + + @retval EFI_SUCCESS User information returned. + @retval EFI_NOT_FOUND No more user information found. + @retval EFI_INVALID_PARAMETER UserInfo is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_GET_NEXT_INFO)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN OUT EFI_USER_INFO_HANDLE *UserInfo + ); + +/** + Delete a user on this credential provider. + + This function deletes a user on this credential provider. + + @param[in] This Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL. + @param[in] User The user profile handle to delete. + + @retval EFI_SUCCESS User profile was successfully deleted. + @retval EFI_ACCESS_DENIED Current user profile does not permit deletion on the user profile handle. + Either the user profile cannot delete on any user profile or cannot delete + on a user profile other than the current user profile. + @retval EFI_UNSUPPORTED This credential provider does not support deletion in the pre-OS. + @retval EFI_DEVICE_ERROR The new credential could not be deleted because of a device error. + @retval EFI_INVALID_PARAMETER User does not refer to a valid user profile handle. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREDENTIAL2_DELETE)( + IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User +); + +/// +/// This protocol provides support for a single class of credentials +/// +struct _EFI_USER_CREDENTIAL2_PROTOCOL { + EFI_GUID Identifier; ///< Uniquely identifies this credential provider. + EFI_GUID Type; ///< Identifies this class of User Credential Provider. + EFI_CREDENTIAL2_ENROLL Enroll; + EFI_CREDENTIAL2_FORM Form; + EFI_CREDENTIAL2_TILE Tile; + EFI_CREDENTIAL2_TITLE Title; + EFI_CREDENTIAL2_USER User; + EFI_CREDENTIAL2_SELECT Select; + EFI_CREDENTIAL2_DESELECT Deselect; + EFI_CREDENTIAL2_DEFAULT Default; + EFI_CREDENTIAL2_GET_INFO GetInfo; + EFI_CREDENTIAL2_GET_NEXT_INFO GetNextInfo; + EFI_CREDENTIAL_CAPABILITIES Capabilities; + EFI_CREDENTIAL2_DELETE Delete; +}; + +extern EFI_GUID gEfiUserCredential2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserManager.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserManager.h new file mode 100644 index 0000000000..0496af7695 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/UserManager.h @@ -0,0 +1,618 @@ +/** @file + UEFI User Manager Protocol definition. + + This protocol manages user profiles. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __USER_MANAGER_H__ +#define __USER_MANAGER_H__ + +/// +/// Global ID for the User Manager Protocol +/// +#define EFI_USER_MANAGER_PROTOCOL_GUID \ + { \ + 0x6fd5b00c, 0xd426, 0x4283, { 0x98, 0x87, 0x6c, 0xf5, 0xcf, 0x1c, 0xb1, 0xfe } \ + } + +#define EFI_EVENT_GROUP_USER_PROFILE_CHANGED \ + { \ + 0xbaf1e6de, 0x209e, 0x4adb, { 0x8d, 0x96, 0xfd, 0x8b, 0x71, 0xf3, 0xf6, 0x83 } \ + } + +typedef VOID *EFI_USER_PROFILE_HANDLE; +typedef VOID *EFI_USER_INFO_HANDLE; + +/// +/// The attributes of the user profile information. +/// +typedef UINT16 EFI_USER_INFO_ATTRIBS; +#define EFI_USER_INFO_STORAGE 0x000F +#define EFI_USER_INFO_STORAGE_VOLATILE 0x0000 +#define EFI_USER_INFO_STORAGE_CREDENTIAL_NV 0x0001 +#define EFI_USER_INFO_STORAGE_PLATFORM_NV 0x0002 + +#define EFI_USER_INFO_ACCESS 0x0070 +#define EFI_USER_INFO_PUBLIC 0x0010 +#define EFI_USER_INFO_PRIVATE 0x0020 +#define EFI_USER_INFO_PROTECTED 0x0030 +#define EFI_USER_INFO_EXCLUSIVE 0x0080 + +/// +/// User information structure +/// +typedef struct { + /// + /// The user credential identifier associated with this user information or else Nil if the + /// information is not associated with any specific credential. + /// + EFI_GUID Credential; + /// + /// The type of user information. + /// + UINT8 InfoType; + /// + /// Must be set to 0. + /// + UINT8 Reserved1; + /// + /// The attributes of the user profile information. + /// + EFI_USER_INFO_ATTRIBS InfoAttribs; + /// + /// The size of the user information, in bytes, including this header. + /// + UINT32 InfoSize; +} EFI_USER_INFO; + +/// +/// User credential class GUIDs +/// +#define EFI_USER_CREDENTIAL_CLASS_UNKNOWN \ + { 0x5cf32e68, 0x7660, 0x449b, { 0x80, 0xe6, 0x7e, 0xa3, 0x6e, 0x3, 0xf6, 0xa8 } } +#define EFI_USER_CREDENTIAL_CLASS_PASSWORD \ + { 0xf8e5058c, 0xccb6, 0x4714, { 0xb2, 0x20, 0x3f, 0x7e, 0x3a, 0x64, 0xb, 0xd1 } } +#define EFI_USER_CREDENTIAL_CLASS_SMART_CARD \ + { 0x5f03ba33, 0x8c6b, 0x4c24, { 0xaa, 0x2e, 0x14, 0xa2, 0x65, 0x7b, 0xd4, 0x54 } } +#define EFI_USER_CREDENTIAL_CLASS_FINGERPRINT \ + { 0x32cba21f, 0xf308, 0x4cbc, { 0x9a, 0xb5, 0xf5, 0xa3, 0x69, 0x9f, 0x4, 0x4a } } +#define EFI_USER_CREDENTIAL_CLASS_HANDPRINT \ + { 0x5917ef16, 0xf723, 0x4bb9, { 0xa6, 0x4b, 0xd8, 0xc5, 0x32, 0xf4, 0xd8, 0xb5 } } +#define EFI_USER_CREDENTIAL_CLASS_SECURE_CARD \ + { 0x8a6b4a83, 0x42fe, 0x45d2, { 0xa2, 0xef, 0x46, 0xf0, 0x6c, 0x7d, 0x98, 0x52 } } + +typedef UINT64 EFI_CREDENTIAL_CAPABILITIES; +#define EFI_CREDENTIAL_CAPABILITIES_ENROLL 0x0000000000000001 + +/// +/// Credential logon flags +/// +typedef UINT32 EFI_CREDENTIAL_LOGON_FLAGS; +#define EFI_CREDENTIAL_LOGON_FLAG_AUTO 0x00000001 +#define EFI_CREDENTIAL_LOGON_FLAG_DEFAULT 0x00000002 + +/// +/// User information record types +/// + +/// +/// No information. +/// +#define EFI_USER_INFO_EMPTY_RECORD 0x00 +/// +/// Provide the user's name for the enrolled user. +/// +#define EFI_USER_INFO_NAME_RECORD 0x01 +typedef CHAR16 *EFI_USER_INFO_NAME; +/// +/// Provides the date and time when the user profile was created. +/// +#define EFI_USER_INFO_CREATE_DATE_RECORD 0x02 +typedef EFI_TIME EFI_USER_INFO_CREATE_DATE; +/// +/// Provides the date and time when the user profile was selected. +/// +#define EFI_USER_INFO_USAGE_DATE_RECORD 0x03 +typedef EFI_TIME EFI_USER_INFO_USAGE_DATE; +/// +/// Provides the number of times that the user profile has been selected. +/// +#define EFI_USER_INFO_USAGE_COUNT_RECORD 0x04 +typedef UINT64 EFI_USER_INFO_USAGE_COUNT; +/// +/// Provides a unique non-volatile user identifier for each enrolled user. +/// +#define EFI_USER_INFO_IDENTIFIER_RECORD 0x05 +typedef UINT8 EFI_USER_INFO_IDENTIFIER[16]; +/// +/// Specifies the type of a particular credential associated with the user profile. +/// +#define EFI_USER_INFO_CREDENTIAL_TYPE_RECORD 0x06 +typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_TYPE; +/// +/// Specifies the user-readable name of a particular credential type. +/// +#define EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD 0x07 +typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_TYPE_NAME; +/// +/// Specifies the credential provider. +/// +#define EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD 0x08 +typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_PROVIDER; +/// +/// Specifies the user-readable name of a particular credential's provider. +/// +#define EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD 0x09 +typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME; +/// +/// Provides PKCS#11 credential information from a smart card. +/// +#define EFI_USER_INFO_PKCS11_RECORD 0x0A +/// +/// Provides standard biometric information in the format specified by the ISO 19785 (Common +/// Biometric Exchange Formats Framework) specification. +/// +#define EFI_USER_INFO_CBEFF_RECORD 0x0B +typedef VOID *EFI_USER_INFO_CBEFF; +/// +/// Indicates how close of a match the fingerprint must be in order to be considered a match. +/// +#define EFI_USER_INFO_FAR_RECORD 0x0C +typedef UINT8 EFI_USER_INFO_FAR; +/// +/// Indicates how many attempts the user has to with a particular credential before the system prevents +/// further attempts. +/// +#define EFI_USER_INFO_RETRY_RECORD 0x0D +typedef UINT8 EFI_USER_INFO_RETRY; +/// +/// Provides the user's pre-OS access rights. +/// +#define EFI_USER_INFO_ACCESS_POLICY_RECORD 0x0E + +typedef struct { + UINT32 Type; ///< Specifies the type of user access control. + UINT32 Size; ///< Specifies the size of the user access control record, in bytes, including this header. +} EFI_USER_INFO_ACCESS_CONTROL; + +typedef EFI_USER_INFO_ACCESS_CONTROL EFI_USER_INFO_ACCESS_POLICY; + +/// +/// User Information access types +/// + +/// +/// Forbids the user from booting or loading executables from the specified device path or any child +/// device paths. +/// +#define EFI_USER_INFO_ACCESS_FORBID_LOAD 0x00000001 +/// +/// Permits the user from booting or loading executables from the specified device path or any child +/// device paths. +/// Note: in-consistency between code and the UEFI 2.3 specification here. +/// The definition EFI_USER_INFO_ACCESS_PERMIT_BOOT in the specification should be typo and wait for +/// spec update. +/// +#define EFI_USER_INFO_ACCESS_PERMIT_LOAD 0x00000002 +/// +/// Presence of this record indicates that a user can update enrollment information. +/// +#define EFI_USER_INFO_ACCESS_ENROLL_SELF 0x00000003 +/// +/// Presence of this record indicates that a user can enroll new users. +/// +#define EFI_USER_INFO_ACCESS_ENROLL_OTHERS 0x00000004 +/// +/// Presence of this record indicates that a user can update the user information of any user. +/// +#define EFI_USER_INFO_ACCESS_MANAGE 0x00000005 +/// +/// Describes permissions usable when configuring the platform. +/// +#define EFI_USER_INFO_ACCESS_SETUP 0x00000006 +/// +/// Standard GUIDs for access to configure the platform. +/// +#define EFI_USER_INFO_ACCESS_SETUP_ADMIN_GUID \ + { 0x85b75607, 0xf7ce, 0x471e, { 0xb7, 0xe4, 0x2a, 0xea, 0x5f, 0x72, 0x32, 0xee } } +#define EFI_USER_INFO_ACCESS_SETUP_NORMAL_GUID \ + { 0x1db29ae0, 0x9dcb, 0x43bc, { 0x8d, 0x87, 0x5d, 0xa1, 0x49, 0x64, 0xdd, 0xe2 } } +#define EFI_USER_INFO_ACCESS_SETUP_RESTRICTED_GUID \ + { 0xbdb38125, 0x4d63, 0x49f4, { 0x82, 0x12, 0x61, 0xcf, 0x5a, 0x19, 0xa, 0xf8 } } + +/// +/// Forbids UEFI drivers from being started from the specified device path(s) or any child device paths. +/// +#define EFI_USER_INFO_ACCESS_FORBID_CONNECT 0x00000007 +/// +/// Permits UEFI drivers to be started on the specified device path(s) or any child device paths. +/// +#define EFI_USER_INFO_ACCESS_PERMIT_CONNECT 0x00000008 +/// +/// Modifies the boot order. +/// +#define EFI_USER_INFO_ACCESS_BOOT_ORDER 0x00000009 +typedef UINT32 EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR; + +#define EFI_USER_INFO_ACCESS_BOOT_ORDER_MASK 0x0000000F +/// +/// Insert new boot options at the beginning of the boot order. +/// +#define EFI_USER_INFO_ACCESS_BOOT_ORDER_INSERT 0x00000000 +/// +/// Append new boot options to the end of the boot order. +/// +#define EFI_USER_INFO_ACCESS_BOOT_ORDER_APPEND 0x00000001 +/// +/// Replace the entire boot order. +/// +#define EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE 0x00000002 +/// +/// The Boot Manager will not attempt find a default boot device +/// when the default boot order is does not lead to a bootable device. +/// +#define EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT 0x00000010 + +/// +/// Provides the expression which determines which credentials are required to assert user identity. +/// +#define EFI_USER_INFO_IDENTITY_POLICY_RECORD 0x0F + +typedef struct { + UINT32 Type; ///< Specifies either an operator or a data item. + UINT32 Length; ///< The length of this block, in bytes, including this header. +} EFI_USER_INFO_IDENTITY_POLICY; + +/// +/// User identity policy expression operators. +/// +#define EFI_USER_INFO_IDENTITY_FALSE 0x00 +#define EFI_USER_INFO_IDENTITY_TRUE 0x01 +#define EFI_USER_INFO_IDENTITY_CREDENTIAL_TYPE 0x02 +#define EFI_USER_INFO_IDENTITY_CREDENTIAL_PROVIDER 0x03 +#define EFI_USER_INFO_IDENTITY_NOT 0x10 +#define EFI_USER_INFO_IDENTITY_AND 0x11 +#define EFI_USER_INFO_IDENTITY_OR 0x12 + +/// +/// Provides placeholder for additional user profile information identified by a GUID. +/// +#define EFI_USER_INFO_GUID_RECORD 0xFF +typedef EFI_GUID EFI_USER_INFO_GUID; + +/// +/// User information table +/// A collection of EFI_USER_INFO records, prefixed with this header. +/// +typedef struct { + UINT64 Size; ///< Total size of the user information table, in bytes. +} EFI_USER_INFO_TABLE; + +typedef struct _EFI_USER_MANAGER_PROTOCOL EFI_USER_MANAGER_PROTOCOL; + +/** + Create a new user profile. + + This function creates a new user profile with only a new user identifier attached and returns its + handle. The user profile is non-volatile, but the handle User can change across reboots. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[out] User On return, points to the new user profile handle. + The user profile handle is unique only during this boot. + + @retval EFI_SUCCESS User profile was successfully created. + @retval EFI_ACCESS_DENIED Current user does not have sufficient permissions to create a user profile. + @retval EFI_UNSUPPORTED Creation of new user profiles is not supported. + @retval EFI_INVALID_PARAMETER The User parameter is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_CREATE)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + OUT EFI_USER_PROFILE_HANDLE *User + ); + +/** + Delete an existing user profile. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] User User profile handle. + + @retval EFI_SUCCESS User profile was successfully deleted. + @retval EFI_ACCESS_DENIED Current user does not have sufficient permissions to delete a user + profile or there is only one user profile. + @retval EFI_UNSUPPORTED Deletion of new user profiles is not supported. + @retval EFI_INVALID_PARAMETER User does not refer to a valid user profile. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_DELETE)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User + ); + +/** + Enumerate all of the enrolled users on the platform. + + This function returns the next enrolled user profile. To retrieve the first user profile handle, point + User at a NULL. Each subsequent call will retrieve another user profile handle until there are no + more, at which point User will point to NULL. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in,out] User On entry, points to the previous user profile handle or NULL to + start enumeration. On exit, points to the next user profile handle + or NULL if there are no more user profiles. + + @retval EFI_SUCCESS Next enrolled user profile successfully returned. + @retval EFI_ACCESS_DENIED Next enrolled user profile was not successfully returned. + @retval EFI_INVALID_PARAMETER The User parameter is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_GET_NEXT)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN OUT EFI_USER_PROFILE_HANDLE *User + ); + +/** + Return the current user profile handle. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[out] CurrentUser On return, points to the current user profile handle. + + @retval EFI_SUCCESS Current user profile handle returned successfully. + @retval EFI_INVALID_PARAMETER The CurrentUser parameter is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_CURRENT)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + OUT EFI_USER_PROFILE_HANDLE *CurrentUser + ); + +/** + Identify a user. + + Identify the user and, if authenticated, returns the user handle and changes the current user profile. + All user information marked as private in a previously selected profile is no longer available for + inspection. + Whenever the current user profile is changed then the an event with the GUID + EFI_EVENT_GROUP_USER_PROFILE_CHANGED is signaled. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[out] User On return, points to the user profile handle for the current user profile. + + @retval EFI_SUCCESS User was successfully identified. + @retval EFI_ACCESS_DENIED User was not successfully identified. + @retval EFI_INVALID_PARAMETER The User parameter is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_IDENTIFY)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + OUT EFI_USER_PROFILE_HANDLE *User + ); + +/** + Find a user using a user information record. + + This function searches all user profiles for the specified user information record. The search starts + with the user information record handle following UserInfo and continues until either the + information is found or there are no more user profiles. + A match occurs when the Info.InfoType field matches the user information record type and the + user information record data matches the portion of Info. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in,out] User On entry, points to the previously returned user profile handle or NULL to start + searching with the first user profile. On return, points to the user profile handle or + NULL if not found. + @param[in,out] UserInfo On entry, points to the previously returned user information handle or NULL to start + searching with the first. On return, points to the user information handle of the user + information record or NULL if not found. Can be NULL, in which case only one user + information record per user can be returned. + @param[in] Info Points to the buffer containing the user information to be compared to the user + information record. If the user information record data is empty, then only the user + information record type is compared. + If InfoSize is 0, then the user information record must be empty. + + @param[in] InfoSize The size of Info, in bytes. + + @retval EFI_SUCCESS User information was found. User points to the user profile handle and UserInfo + points to the user information handle. + @retval EFI_NOT_FOUND User information was not found. User points to NULL and UserInfo points to NULL. + @retval EFI_INVALID_PARAMETER User is NULL. Or Info is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_FIND)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN OUT EFI_USER_PROFILE_HANDLE *User, + IN OUT EFI_USER_INFO_HANDLE *UserInfo OPTIONAL, + IN CONST EFI_USER_INFO *Info, + IN UINTN InfoSize + ); + +/** + Called by credential provider to notify of information change. + + This function allows the credential provider to notify the User Identity Manager when user status + has changed. + If the User Identity Manager doesn't support asynchronous changes in credentials, then this function + should return EFI_UNSUPPORTED. + If current user does not exist, and the credential provider can identify a user, then make the user + to be current user and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event. + If current user already exists, and the credential provider can identify another user, then switch + current user to the newly identified user, and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event. + If current user was identified by this credential provider and now the credential provider cannot identify + current user, then logout current user and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] Changed Handle on which is installed an instance of the + EFI_USER_CREDENTIAL_PROTOCOL where the user has changed. + + @retval EFI_SUCCESS The User Identity Manager has handled the notification. + @retval EFI_NOT_READY The function was called while the specified credential provider was not selected. + @retval EFI_UNSUPPORTED The User Identity Manager doesn't support asynchronous notifications. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_NOTIFY)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_HANDLE Changed + ); + +/** + Return information attached to the user. + + This function returns user information. The format of the information is described in User + Information. The function may return EFI_ACCESS_DENIED if the information is marked private + and the handle specified by User is not the current user profile. The function may return + EFI_ACCESS_DENIED if the information is marked protected and the information is associated + with a credential provider for which the user has not been authenticated. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] User Handle of the user whose profile will be retrieved. + @param[in] UserInfo Handle of the user information data record. + @param[out] Info On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user + information. If the buffer is too small to hold the information, then + EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the + number of bytes actually required. + @param[in,out] InfoSize On entry, points to the size of Info. On return, points to the size of the user + information. + + @retval EFI_SUCCESS Information returned successfully. + @retval EFI_ACCESS_DENIED The information about the specified user cannot be accessed by the current user. + @retval EFI_BUFFER_TOO_SMALL The number of bytes specified by *InfoSize is too small to hold + the returned data. The actual size required is returned in *InfoSize. + @retval EFI_NOT_FOUND User does not refer to a valid user profile or UserInfo does not refer to a valid + user info handle. + @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_GET_INFO)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + IN EFI_USER_INFO_HANDLE UserInfo, + OUT EFI_USER_INFO *Info, + IN OUT UINTN *InfoSize + ); + +/** + Add or update user information. + + This function changes user information. If NULL is pointed to by UserInfo, then a new user + information record is created and its handle is returned in UserInfo. Otherwise, the existing one is + replaced. + If EFI_USER_INFO_IDENTITY_POLICY_RECORD is changed, it is the caller's responsibility to keep it to + be synced with the information on credential providers. + If EFI_USER_INFO_EXCLUSIVE is specified in Info and a user information record of the same + type already exists in the user profile, then EFI_ACCESS_DENIED will be returned and + UserInfo will point to the handle of the existing record. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] User Handle of the user whose profile will be retrieved. + @param[in,out] UserInfo Handle of the user information data record. + @param[in] Info On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user + information. If the buffer is too small to hold the information, then + EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the + number of bytes actually required. + @param[in] InfoSize On entry, points to the size of Info. On return, points to the size of the user + information. + + @retval EFI_SUCCESS Information returned successfully. + @retval EFI_ACCESS_DENIED The record is exclusive. + @retval EFI_SECURITY_VIOLATION The current user does not have permission to change the specified + user profile or user information record. + @retval EFI_NOT_FOUND User does not refer to a valid user profile or UserInfo does not refer to a valid + user info handle. + @retval EFI_INVALID_PARAMETER UserInfo is NULL or Info is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_SET_INFO)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + IN OUT EFI_USER_INFO_HANDLE *UserInfo, + IN CONST EFI_USER_INFO *Info, + IN UINTN InfoSize + ); + +/** + Delete user information. + + Delete the user information attached to the user profile specified by the UserInfo. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] User Handle of the user whose information will be deleted. + @param[in] UserInfo Handle of the user information to remove. + + @retval EFI_SUCCESS User information deleted successfully. + @retval EFI_NOT_FOUND User information record UserInfo does not exist in the user profile. + @retval EFI_ACCESS_DENIED The current user does not have permission to delete this user information. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_DELETE_INFO)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + IN EFI_USER_INFO_HANDLE UserInfo + ); + +/** + Enumerate user information of all the enrolled users on the platform. + + This function returns the next user information record. To retrieve the first user information record + handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information + record handle until there are no more, at which point UserInfo will point to NULL. + + @param[in] This Points to this instance of the EFI_USER_MANAGER_PROTOCOL. + @param[in] User Handle of the user whose information will be deleted. + @param[in,out] UserInfo Handle of the user information to remove. + + @retval EFI_SUCCESS User information returned. + @retval EFI_NOT_FOUND No more user information found. + @retval EFI_INVALID_PARAMETER UserInfo is NULL. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_USER_PROFILE_GET_NEXT_INFO)( + IN CONST EFI_USER_MANAGER_PROTOCOL *This, + IN EFI_USER_PROFILE_HANDLE User, + IN OUT EFI_USER_INFO_HANDLE *UserInfo + ); + +/// +/// This protocol provides the services used to manage user profiles. +/// +struct _EFI_USER_MANAGER_PROTOCOL { + EFI_USER_PROFILE_CREATE Create; + EFI_USER_PROFILE_DELETE Delete; + EFI_USER_PROFILE_GET_NEXT GetNext; + EFI_USER_PROFILE_CURRENT Current; + EFI_USER_PROFILE_IDENTIFY Identify; + EFI_USER_PROFILE_FIND Find; + EFI_USER_PROFILE_NOTIFY Notify; + EFI_USER_PROFILE_GET_INFO GetInfo; + EFI_USER_PROFILE_SET_INFO SetInfo; + EFI_USER_PROFILE_DELETE_INFO DeleteInfo; + EFI_USER_PROFILE_GET_NEXT_INFO GetNextInfo; +}; + +extern EFI_GUID gEfiUserManagerProtocolGuid; +extern EFI_GUID gEfiEventUserProfileChangedGuid; +extern EFI_GUID gEfiUserCredentialClassUnknownGuid; +extern EFI_GUID gEfiUserCredentialClassPasswordGuid; +extern EFI_GUID gEfiUserCredentialClassSmartCardGuid; +extern EFI_GUID gEfiUserCredentialClassFingerprintGuid; +extern EFI_GUID gEfiUserCredentialClassHandprintGuid; +extern EFI_GUID gEfiUserCredentialClassSecureCardGuid; +extern EFI_GUID gEfiUserInfoAccessSetupAdminGuid; +extern EFI_GUID gEfiUserInfoAccessSetupNormalGuid; +extern EFI_GUID gEfiUserInfoAccessSetupRestrictedGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Variable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Variable.h new file mode 100644 index 0000000000..c209344712 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/Variable.h @@ -0,0 +1,39 @@ +/** @file + Variable Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + This provides the services required to get and set environment variables. This + protocol must be produced by a runtime DXE driver and may be consumed only by + the DXE Foundation. The DXE driver that produces this protocol must be a runtime + driver. This driver is responsible for initializing the GetVariable(), + GetNextVariableName(), and SetVariable() fields of the UEFI Runtime Services Table. + + After the three fields of the UEFI Runtime Services Table have been initialized, + the driver must install the EFI_VARIABLE_ARCH_PROTOCOL_GUID on a new handle with + a NULL interface pointer. The installation of this protocol informs the DXE Foundation + that the read-only and the volatile environment variable related services are + now available and that the DXE Foundation must update the 32-bit CRC of the UEFI + Runtime Services Table. The full complement of environment variable services are + not available until both this protocol and EFI_VARIABLE_WRITE_ARCH_PROTOCOL are + installed. DXE drivers that require read-only access or read/write access to volatile + environment variables must have this architectural protocol in their dependency + expressions. DXE drivers that require write access to nonvolatile environment + variables must have the EFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency + expressions. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_VARIABLE_ARCH_H__ +#define __ARCH_PROTOCOL_VARIABLE_ARCH_H__ + +/// +/// Global ID for the Variable Architectural Protocol +/// +#define EFI_VARIABLE_ARCH_PROTOCOL_GUID \ + { 0x1e5668e2, 0x8481, 0x11d4, {0xbc, 0xf1, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } + +extern EFI_GUID gEfiVariableArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VariableWrite.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VariableWrite.h new file mode 100644 index 0000000000..9131e1945e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VariableWrite.h @@ -0,0 +1,39 @@ +/** @file + Variable Write Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + This provides the services required to set nonvolatile environment variables. + This protocol must be produced by a runtime DXE driver and may be consumed only + by the DXE Foundation. + + The DXE driver that produces this protocol must be a runtime driver. This driver + may update the SetVariable() field of the UEFI Runtime Services Table. + + After the UEFI Runtime Services Table has been initialized, the driver must + install the EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID on a new handle with a NULL + interface pointer. The installation of this protocol informs the DXE Foundation + that the write services for nonvolatile environment variables are now available + and that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services + Table. The full complement of environment variable services are not available + until both this protocol and EFI_VARIABLE_ARCH_PROTOCOL are installed. DXE drivers + that require read-only access or read/write access to volatile environment variables + must have the EFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency expressions. + DXE drivers that require write access to nonvolatile environment variables must + have this architectural protocol in their dependency expressions. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ARCH_PROTOCOL_VARIABLE_WRITE_ARCH_H__ +#define __ARCH_PROTOCOL_VARIABLE_WRITE_ARCH_H__ + +/// +/// Global ID for the Variable Write Architectural Protocol +/// +#define EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID \ + { 0x6441f818, 0x6362, 0x4e44, {0xb5, 0x70, 0x7d, 0xba, 0x31, 0xdd, 0x24, 0x53 } } + +extern EFI_GUID gEfiVariableWriteArchProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VlanConfig.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VlanConfig.h new file mode 100644 index 0000000000..ae53d9aac7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/VlanConfig.h @@ -0,0 +1,137 @@ +/** @file + EFI VLAN Config protocol is to provide manageability interface for VLAN configuration. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.2 + +**/ + +#ifndef __EFI_VLANCONFIG_PROTOCOL_H__ +#define __EFI_VLANCONFIG_PROTOCOL_H__ + + +#define EFI_VLAN_CONFIG_PROTOCOL_GUID \ + { \ + 0x9e23d768, 0xd2f3, 0x4366, {0x9f, 0xc3, 0x3a, 0x7a, 0xba, 0x86, 0x43, 0x74 } \ + } + +typedef struct _EFI_VLAN_CONFIG_PROTOCOL EFI_VLAN_CONFIG_PROTOCOL; + + +/// +/// EFI_VLAN_FIND_DATA +/// +typedef struct { + UINT16 VlanId; ///< Vlan Identifier. + UINT8 Priority; ///< Priority of this VLAN. +} EFI_VLAN_FIND_DATA; + + +/** + Create a VLAN device or modify the configuration parameter of an + already-configured VLAN. + + The Set() function is used to create a new VLAN device or change the VLAN + configuration parameters. If the VlanId hasn't been configured in the + physical Ethernet device, a new VLAN device will be created. If a VLAN with + this VlanId is already configured, then related configuration will be updated + as the input parameters. + + If VlanId is zero, the VLAN device will send and receive untagged frames. + Otherwise, the VLAN device will send and receive VLAN-tagged frames containing the VlanId. + If VlanId is out of scope of (0-4094), EFI_INVALID_PARAMETER is returned. + If Priority is out of the scope of (0-7), then EFI_INVALID_PARAMETER is returned. + If there is not enough system memory to perform the registration, then + EFI_OUT_OF_RESOURCES is returned. + + @param[in] This Points to the EFI_VLAN_CONFIG_PROTOCOL. + @param[in] VlanId A unique identifier (1-4094) of the VLAN which is being created + or modified, or zero (0). + @param[in] Priority 3 bit priority in VLAN header. Priority 0 is default value. If + VlanId is zero (0), Priority is ignored. + + @retval EFI_SUCCESS The VLAN is successfully configured. + @retval EFI_INVALID_PARAMETER One or more of following conditions is TRUE: + - This is NULL. + - VlanId is an invalid VLAN Identifier. + - Priority is invalid. + @retval EFI_OUT_OF_RESOURCES There is not enough system memory to perform the registration. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_VLAN_CONFIG_SET)( + IN EFI_VLAN_CONFIG_PROTOCOL *This, + IN UINT16 VlanId, + IN UINT8 Priority + ); + +/** + Find configuration information for specified VLAN or all configured VLANs. + + The Find() function is used to find the configuration information for matching + VLAN and allocate a buffer into which those entries are copied. + + @param[in] This Points to the EFI_VLAN_CONFIG_PROTOCOL. + @param[in] VlanId Pointer to VLAN identifier. Set to NULL to find all + configured VLANs. + @param[out] NumberOfVlan The number of VLANs which is found by the specified criteria. + @param[out] Entries The buffer which receive the VLAN configuration. + + @retval EFI_SUCCESS The VLAN is successfully found. + @retval EFI_INVALID_PARAMETER One or more of following conditions is TRUE: + - This is NULL. + - Specified VlanId is invalid. + @retval EFI_NOT_FOUND No matching VLAN is found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_VLAN_CONFIG_FIND)( + IN EFI_VLAN_CONFIG_PROTOCOL *This, + IN UINT16 *VlanId OPTIONAL, + OUT UINT16 *NumberOfVlan, + OUT EFI_VLAN_FIND_DATA **Entries + ); + +/** + Remove the configured VLAN device. + + The Remove() function is used to remove the specified VLAN device. + If the VlanId is out of the scope of (0-4094), EFI_INVALID_PARAMETER is returned. + If specified VLAN hasn't been previously configured, EFI_NOT_FOUND is returned. + + @param[in] This Points to the EFI_VLAN_CONFIG_PROTOCOL. + @param[in] VlanId Identifier (0-4094) of the VLAN to be removed. + + @retval EFI_SUCCESS The VLAN is successfully removed. + @retval EFI_INVALID_PARAMETER One or more of following conditions is TRUE: + - This is NULL. + - VlanId is an invalid parameter. + @retval EFI_NOT_FOUND The to-be-removed VLAN does not exist. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_VLAN_CONFIG_REMOVE)( + IN EFI_VLAN_CONFIG_PROTOCOL *This, + IN UINT16 VlanId + ); + +/// +/// EFI_VLAN_CONFIG_PROTOCOL +/// provide manageability interface for VLAN setting. The intended +/// VLAN tagging implementation is IEEE802.1Q. +/// +struct _EFI_VLAN_CONFIG_PROTOCOL { + EFI_VLAN_CONFIG_SET Set; + EFI_VLAN_CONFIG_FIND Find; + EFI_VLAN_CONFIG_REMOVE Remove; +}; + +extern EFI_GUID gEfiVlanConfigProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WatchdogTimer.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WatchdogTimer.h new file mode 100644 index 0000000000..94fa0e3ef1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WatchdogTimer.h @@ -0,0 +1,138 @@ +/** @file + Watchdog Timer Architectural Protocol as defined in PI Specification VOLUME 2 DXE + + Used to provide system watchdog timer services + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __ARCH_PROTOCOL_WATCHDOG_TIMER_H__ +#define __ARCH_PROTOCOL_WATCHDOG_TIMER_H__ + +/// +/// Global ID for the Watchdog Timer Architectural Protocol +/// +#define EFI_WATCHDOG_TIMER_ARCH_PROTOCOL_GUID \ + { 0x665E3FF5, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } } + +/// +/// Declare forward reference for the Timer Architectural Protocol +/// +typedef struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL EFI_WATCHDOG_TIMER_ARCH_PROTOCOL; + +/** + A function of this type is called when the watchdog timer fires if a + handler has been registered. + + @param Time The time in 100 ns units that has passed since the watchdog + timer was armed. For the notify function to be called, this + must be greater than TimerPeriod. + + @return None. + +**/ +typedef +VOID +(EFIAPI *EFI_WATCHDOG_TIMER_NOTIFY)( + IN UINT64 Time + ); + +/** + This function registers a handler that is to be invoked when the watchdog + timer fires. By default, the EFI_WATCHDOG_TIMER protocol will call the + Runtime Service ResetSystem() when the watchdog timer fires. If a + NotifyFunction is registered, then the NotifyFunction will be called before + the Runtime Service ResetSystem() is called. If NotifyFunction is NULL, then + the watchdog handler is unregistered. If a watchdog handler is registered, + then EFI_SUCCESS is returned. If an attempt is made to register a handler + when a handler is already registered, then EFI_ALREADY_STARTED is returned. + If an attempt is made to uninstall a handler when a handler is not installed, + then return EFI_INVALID_PARAMETER. + + @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when the watchdog timer fires. If this + is NULL, then the handler will be unregistered. + + @retval EFI_SUCCESS The watchdog timer handler was registered or + unregistered. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_TIMER_REGISTER_HANDLER)( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction + ); + +/** + This function sets the amount of time to wait before firing the watchdog + timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog + timer is disabled. + + @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The amount of time in 100 nS units to wait before the watchdog + timer is fired. If TimerPeriod is zero, then the watchdog + timer is disabled. + + @retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time + 100 nS units. + @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD)( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ); + +/** + This function retrieves the amount of time the system will wait before firing + the watchdog timer. This period is returned in TimerPeriod, and EFI_SUCCESS + is returned. If TimerPeriod is NULL, then EFI_INVALID_PARAMETER is returned. + + @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the amount of time in 100 nS units that the system + will wait before the watchdog timer is fired. If TimerPeriod of + zero is returned, then the watchdog timer is disabled. + + @retval EFI_SUCCESS The amount of time that the system will wait before + firing the watchdog timer was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD)( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ); + + +/// +/// This protocol provides the services required to implement the Boot Service +/// SetWatchdogTimer(). It provides a service to set the amount of time to wait +/// before firing the watchdog timer, and it also provides a service to register +/// a handler that is invoked when the watchdog timer fires. This protocol can +/// implement the watchdog timer by using the event and timer Boot Services, or +/// it can make use of custom hardware. When the watchdog timer fires, control +/// will be passed to a handler if one has been registered. If no handler has +/// been registered, or the registered handler returns, then the system will be +/// reset by calling the Runtime Service ResetSystem(). +/// +struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL { + EFI_WATCHDOG_TIMER_REGISTER_HANDLER RegisterHandler; + EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD SetTimerPeriod; + EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD GetTimerPeriod; +}; + +extern EFI_GUID gEfiWatchdogTimerArchProtocolGuid; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi.h new file mode 100644 index 0000000000..58c248d1ee --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi.h @@ -0,0 +1,1123 @@ +/** @file + This file provides management service interfaces of 802.11 MAC layer. It is used by + network applications (and drivers) to establish wireless connection with an access + point (AP). + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.5 + +**/ + +#ifndef __EFI_WIFI_PROTOCOL_H__ +#define __EFI_WIFI_PROTOCOL_H__ + +#include + +#define EFI_WIRELESS_MAC_CONNECTION_PROTOCOL_GUID \ + { \ + 0xda55bc9, 0x45f8, 0x4bb4, {0x87, 0x19, 0x52, 0x24, 0xf1, 0x8a, 0x4d, 0x45 } \ + } + +typedef struct _EFI_WIRELESS_MAC_CONNECTION_PROTOCOL EFI_WIRELESS_MAC_CONNECTION_PROTOCOL; + +/// +/// EFI_80211_ACC_NET_TYPE +/// +typedef enum { + IeeePrivate = 0, + IeeePrivatewithGuest = 1, + IeeeChargeablePublic = 2, + IeeeFreePublic = 3, + IeeePersonal = 4, + IeeeEmergencyServOnly = 5, + IeeeTestOrExp = 14, + IeeeWildcard = 15 +} EFI_80211_ACC_NET_TYPE; + +/// +/// EFI_80211_ASSOCIATE_RESULT_CODE +/// +typedef enum { + AssociateSuccess, + AssociateRefusedReasonUnspecified, + AssociateRefusedCapsMismatch, + AssociateRefusedExtReason, + AssociateRefusedAPOutOfMemory, + AssociateRefusedBasicRatesMismatch, + AssociateRejectedEmergencyServicesNotSupported, + AssociateRefusedTemporarily +} EFI_80211_ASSOCIATE_RESULT_CODE; + +/// +/// EFI_80211_SCAN_RESULT_CODE +/// +typedef enum { + /// + /// The scan operation finished successfully. + /// + ScanSuccess, + /// + /// The scan operation is not supported in current implementation. + /// + ScanNotSupported +} EFI_80211_SCAN_RESULT_CODE; + +/// +/// EFI_80211_REASON_CODE +/// +typedef enum { + Ieee80211UnspecifiedReason = 1, + Ieee80211PreviousAuthenticateInvalid = 2, + Ieee80211DeauthenticatedSinceLeaving = 3, + Ieee80211DisassociatedDueToInactive = 4, + Ieee80211DisassociatedSinceApUnable = 5, + Ieee80211Class2FrameNonauthenticated = 6, + Ieee80211Class3FrameNonassociated = 7, + Ieee80211DisassociatedSinceLeaving = 8, + // ... +} EFI_80211_REASON_CODE; + +/// +/// EFI_80211_DISASSOCIATE_RESULT_CODE +/// +typedef enum { + /// + /// Disassociation process completed successfully. + /// + DisassociateSuccess, + /// + /// Disassociation failed due to any input parameter is invalid. + /// + DisassociateInvalidParameters +} EFI_80211_DISASSOCIATE_RESULT_CODE; + +/// +/// EFI_80211_AUTHENTICATION_TYPE +/// +typedef enum { + /// + /// Open system authentication, admits any STA to the DS. + /// + OpenSystem, + /// + /// Shared Key authentication relies on WEP to demonstrate knowledge of a WEP + /// encryption key. + /// + SharedKey, + /// + /// FT authentication relies on keys derived during the initial mobility domain + /// association to authenticate the stations. + /// + FastBSSTransition, + /// + /// SAE authentication uses finite field cryptography to prove knowledge of a shared + /// password. + /// + SAE +} EFI_80211_AUTHENTICATION_TYPE; + +/// +/// EFI_80211_AUTHENTICATION_RESULT_CODE +/// +typedef enum { + AuthenticateSuccess, + AuthenticateRefused, + AuthenticateAnticLoggingTokenRequired, + AuthenticateFiniteCyclicGroupNotSupported, + AuthenticationRejected, + AuthenticateInvalidParameter +} EFI_80211_AUTHENTICATE_RESULT_CODE; + +/// +/// EFI_80211_ELEMENT_HEADER +/// +typedef struct { + /// + /// A unique element ID defined in IEEE 802.11 specification. + /// + UINT8 ElementID; + /// + /// Specifies the number of octets in the element body. + /// + UINT8 Length; +} EFI_80211_ELEMENT_HEADER; + +/// +/// EFI_80211_ELEMENT_REQ +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Start of elements that are requested to be included in the Probe Response frame. + /// The elements are listed in order of increasing element ID. + /// + UINT8 RequestIDs[1]; +} EFI_80211_ELEMENT_REQ; + +/// +/// EFI_80211_ELEMENT_SSID +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Service set identifier. If Hdr.Length is zero, this field is ignored. + /// + UINT8 SSId[32]; +} EFI_80211_ELEMENT_SSID; + +/// +/// EFI_80211_SCAN_DATA +/// +typedef struct { + /// + /// Determines whether infrastructure BSS, IBSS, MBSS, or all, are included in the + /// scan. + /// + EFI_80211_BSS_TYPE BSSType; + /// + /// Indicates a specific or wildcard BSSID. Use all binary 1s to represent all SSIDs. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Length in bytes of the SSId. If zero, ignore SSId field. + /// + UINT8 SSIdLen; + /// + /// Specifies the desired SSID or the wildcard SSID. Use NULL to represent all SSIDs. + /// + UINT8 *SSId; + /// + /// Indicates passive scanning if TRUE. + /// + BOOLEAN PassiveMode; + /// + /// The delay in microseconds to be used prior to transmitting a Probe frame during + /// active scanning. If zero, the value can be overridden by an + /// implementation-dependent default value. + /// + UINT32 ProbeDelay; + /// + /// Specifies a list of channels that are examined when scanning for a BSS. If set to + /// NULL, all valid channels will be scanned. + /// + UINT32 *ChannelList; + /// + /// Indicates the minimum time in TU to spend on each channel when scanning. If zero, + /// the value can be overridden by an implementation-dependent default value. + /// + UINT32 MinChannelTime; + /// + /// Indicates the maximum time in TU to spend on each channel when scanning. If zero, + /// the value can be overridden by an implementation-dependent default value. + /// + UINT32 MaxChannelTime; + /// + /// Points to an optionally present element. This is an optional parameter and may be + /// NULL. + /// + EFI_80211_ELEMENT_REQ *RequestInformation; + /// + /// Indicates one or more SSID elements that are optionally present. This is an + /// optional parameter and may be NULL. + /// + EFI_80211_ELEMENT_SSID *SSIDList; + /// + /// Specifies a desired specific access network type or the wildcard access network + /// type. Use 15 as wildcard access network type. + /// + EFI_80211_ACC_NET_TYPE AccessNetworkType; + /// + /// Specifies zero or more elements. This is an optional parameter and may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_SCAN_DATA; + +/// +/// EFI_80211_COUNTRY_TRIPLET_SUBBAND +/// +typedef struct { + /// + /// Indicates the lowest channel number in the subband. It has a positive integer + /// value less than 201. + /// + UINT8 FirstChannelNum; + /// + /// Indicates the number of channels in the subband. + /// + UINT8 NumOfChannels; + /// + /// Indicates the maximum power in dBm allowed to be transmitted. + /// + UINT8 MaxTxPowerLevel; +} EFI_80211_COUNTRY_TRIPLET_SUBBAND; + +/// +/// EFI_80211_COUNTRY_TRIPLET_OPERATE +/// +typedef struct { + /// + /// Indicates the operating extension identifier. It has a positive integer value of + /// 201 or greater. + /// + UINT8 OperatingExtId; + /// + /// Index into a set of values for radio equipment set of rules. + /// + UINT8 OperatingClass; + /// + /// Specifies aAirPropagationTime characteristics used in BSS operation. Refer the + /// definition of aAirPropagationTime in IEEE 802.11 specification. + /// + UINT8 CoverageClass; +} EFI_80211_COUNTRY_TRIPLET_OPERATE; + +/// +/// EFI_80211_COUNTRY_TRIPLET +/// +typedef union { + /// + /// The subband triplet. + /// + EFI_80211_COUNTRY_TRIPLET_SUBBAND Subband; + /// + /// The operating triplet. + /// + EFI_80211_COUNTRY_TRIPLET_OPERATE Operating; +} EFI_80211_COUNTRY_TRIPLET; + +/// +/// EFI_80211_ELEMENT_COUNTRY +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Specifies country strings in 3 octets. + /// + UINT8 CountryStr[3]; + /// + /// Indicates a triplet that repeated in country element. The number of triplets is + /// determined by the Hdr.Length field. + /// + EFI_80211_COUNTRY_TRIPLET CountryTriplet[1]; +} EFI_80211_ELEMENT_COUNTRY; + +/// +/// EFI_80211_ELEMENT_DATA_RSN +/// +typedef struct { + /// + /// Indicates the version number of the RSNA protocol. Value 1 is defined in current + /// IEEE 802.11 specification. + /// + UINT16 Version; + /// + /// Specifies the cipher suite selector used by the BSS to protect group address frames. + /// + UINT32 GroupDataCipherSuite; + /// + /// Indicates the number of pairwise cipher suite selectors that are contained in + /// PairwiseCipherSuiteList. + /// +//UINT16 PairwiseCipherSuiteCount; + /// + /// Contains a series of cipher suite selectors that indicate the pairwise cipher + /// suites contained in this element. + /// +//UINT32 PairwiseCipherSuiteList[PairwiseCipherSuiteCount]; + /// + /// Indicates the number of AKM suite selectors that are contained in AKMSuiteList. + /// +//UINT16 AKMSuiteCount; + /// + /// Contains a series of AKM suite selectors that indicate the AKM suites contained in + /// this element. + /// +//UINT32 AKMSuiteList[AKMSuiteCount]; + /// + /// Indicates requested or advertised capabilities. + /// +//UINT16 RSNCapabilities; + /// + /// Indicates the number of PKMIDs in the PMKIDList. + /// +//UINT16 PMKIDCount; + /// + /// Contains zero or more PKMIDs that the STA believes to be valid for the destination + /// AP. +//UINT8 PMKIDList[PMKIDCount][16]; + /// + /// Specifies the cipher suite selector used by the BSS to protect group addressed + /// robust management frames. + /// +//UINT32 GroupManagementCipherSuite; +} EFI_80211_ELEMENT_DATA_RSN; + +/// +/// EFI_80211_ELEMENT_RSN +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Points to RSN element. The size of a RSN element is limited to 255 octets. + /// + EFI_80211_ELEMENT_DATA_RSN *Data; +} EFI_80211_ELEMENT_RSN; + +/// +/// EFI_80211_ELEMENT_EXT_CAP +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Indicates the capabilities being advertised by the STA transmitting the element. + /// This is a bit field with variable length. Refer to IEEE 802.11 specification for + /// bit value. + /// + UINT8 Capabilities[1]; +} EFI_80211_ELEMENT_EXT_CAP; + +/// +/// EFI_80211_BSS_DESCRIPTION +/// +typedef struct { + /// + /// Indicates a specific BSSID of the found BSS. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the SSID of the found BSS. If NULL, ignore SSIdLen field. + /// + UINT8 *SSId; + /// + /// Specifies the SSID of the found BSS. If NULL, ignore SSIdLen field. + /// + UINT8 SSIdLen; + /// + /// Specifies the type of the found BSS. + /// + EFI_80211_BSS_TYPE BSSType; + /// + /// The beacon period in TU of the found BSS. + /// + UINT16 BeaconPeriod; + /// + /// The timestamp of the received frame from the found BSS. + /// + UINT64 Timestamp; + /// + /// The advertised capabilities of the BSS. + /// + UINT16 CapabilityInfo; + /// + /// The set of data rates that shall be supported by all STAs that desire to join this + /// BSS. + /// + UINT8 *BSSBasicRateSet; + /// + /// The set of data rates that the peer STA desires to use for communication within + /// the BSS. + /// + UINT8 *OperationalRateSet; + /// + /// The information required to identify the regulatory domain in which the peer STA + /// is located. + /// + EFI_80211_ELEMENT_COUNTRY *Country; + /// + /// The cipher suites and AKM suites supported in the BSS. + /// + EFI_80211_ELEMENT_RSN RSN; + /// + /// Specifies the RSSI of the received frame. + /// + UINT8 RSSI; + /// + /// Specifies the RCPI of the received frame. + /// + UINT8 RCPIMeasurement; + /// + /// Specifies the RSNI of the received frame. + /// + UINT8 RSNIMeasurement; + /// + /// Specifies the elements requested by the request element of the Probe Request frame. + /// This is an optional parameter and may be NULL. + /// + UINT8 *RequestedElements; + /// + /// Specifies the BSS membership selectors that represent the set of features that + /// shall be supported by all STAs to join this BSS. + /// + UINT8 *BSSMembershipSelectorSet; + /// + /// Specifies the parameters within the Extended Capabilities element that are + /// supported by the MAC entity. This is an optional parameter and may be NULL. + /// + EFI_80211_ELEMENT_EXT_CAP *ExtCapElement; +} EFI_80211_BSS_DESCRIPTION; + +/// +/// EFI_80211_SUBELEMENT_INFO +/// +typedef struct { + /// + /// Indicates the unique identifier within the containing element or sub-element. + /// + UINT8 SubElementID; + /// + /// Specifies the number of octets in the Data field. + /// + UINT8 Length; + /// + /// A variable length data buffer. + /// + UINT8 Data[1]; +} EFI_80211_SUBELEMENT_INFO; + +/// +/// EFI_80211_MULTIPLE_BSSID +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Indicates the maximum number of BSSIDs in the multiple BSSID set. When Indicator + /// is set to n, 2n is the maximum number. + /// + UINT8 Indicator; + /// + /// Contains zero or more sub-elements. + /// + EFI_80211_SUBELEMENT_INFO SubElement[1]; +} EFI_80211_MULTIPLE_BSSID; + +/// +/// EFI_80211_BSS_DESP_PILOT +/// +typedef struct { + /// + /// Indicates a specific BSSID of the found BSS. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the type of the found BSS. + /// + EFI_80211_BSS_TYPE BSSType; + /// + /// One octet field to report condensed capability information. + /// + UINT8 ConCapInfo; + /// + /// Two octet's field to report condensed country string. + /// + UINT8 ConCountryStr[2]; + /// + /// Indicates the operating class value for the operating channel. + /// + UINT8 OperatingClass; + /// + /// Indicates the operating channel. + /// + UINT8 Channel; + /// + /// Indicates the measurement pilot interval in TU. + /// + UINT8 Interval; + /// + /// Indicates that the BSS is within a multiple BSSID set. + /// + EFI_80211_MULTIPLE_BSSID *MultipleBSSID; + /// + /// Specifies the RCPI of the received frame. + /// + UINT8 RCPIMeasurement; + /// + /// Specifies the RSNI of the received frame. + /// + UINT8 RSNIMeasurement; +} EFI_80211_BSS_DESP_PILOT; + +/// +/// EFI_80211_SCAN_RESULT +/// +typedef struct { + /// + /// The number of EFI_80211_BSS_DESCRIPTION in BSSDespSet. If zero, BSSDespSet should + /// be ignored. + /// + UINTN NumOfBSSDesp; + /// + /// Points to zero or more instances of EFI_80211_BSS_DESCRIPTION. + /// + EFI_80211_BSS_DESCRIPTION **BSSDespSet; + /// + /// The number of EFI_80211_BSS_DESP_PILOT in BSSDespFromPilotSet. If zero, + /// BSSDespFromPilotSet should be ignored. + /// + UINTN NumofBSSDespFromPilot; + /// + /// Points to zero or more instances of EFI_80211_BSS_DESP_PILOT. + /// + EFI_80211_BSS_DESP_PILOT **BSSDespFromPilotSet; + /// + /// Specifies zero or more elements. This is an optional parameter and may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_SCAN_RESULT; + +/// +/// EFI_80211_SCAN_DATA_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI Wireless + /// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: Scan operation completed successfully. + /// EFI_NOT_FOUND: Failed to find available BSS. + /// EFI_DEVICE_ERROR: An unexpected network or system error occurred. + /// EFI_ACCESS_DENIED: The scan operation is not completed due to some underlying + /// hardware or software state. + /// EFI_NOT_READY: The scan operation is started but not yet completed. + EFI_STATUS Status; + /// + /// Pointer to the scan data. + /// + EFI_80211_SCAN_DATA *Data; + /// + /// Indicates the scan state. + /// + EFI_80211_SCAN_RESULT_CODE ResultCode; + /// + /// Indicates the scan result. It is caller's responsibility to free this buffer. + /// + EFI_80211_SCAN_RESULT *Result; +} EFI_80211_SCAN_DATA_TOKEN; + +/// +/// EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE +/// +typedef struct { + /// + /// The first channel number in a subband of supported channels. + /// + UINT8 FirstChannelNumber; + /// + /// The number of channels in a subband of supported channels. + /// + UINT8 NumberOfChannels; +} EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE; + +/// +/// EFI_80211_ELEMENT_SUPP_CHANNEL +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Indicates one or more tuples of (first channel, number of channels). + /// + EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE Subband[1]; +} EFI_80211_ELEMENT_SUPP_CHANNEL; + +/// +/// EFI_80211_ASSOCIATE_DATA +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity to associate with. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the requested operational capabilities to the AP in 2 octets. + /// + UINT16 CapabilityInfo; + /// + /// Specifies a time limit in TU, after which the associate procedure is terminated. + /// + UINT32 FailureTimeout; + /// + /// Specifies if in power save mode, how often the STA awakes and listens for the next + /// beacon frame in TU. + /// + UINT32 ListenInterval; + /// + /// Indicates a list of channels in which the STA is capable of operating. + /// + EFI_80211_ELEMENT_SUPP_CHANNEL *Channels; + /// + /// The cipher suites and AKM suites selected by the STA. + /// + EFI_80211_ELEMENT_RSN RSN; + /// + /// Specifies the parameters within the Extended Capabilities element that are + /// supported by the MAC entity. This is an optional parameter and may be NULL. + /// + EFI_80211_ELEMENT_EXT_CAP *ExtCapElement; + /// + /// Specifies zero or more elements. This is an optional parameter and may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_ASSOCIATE_DATA; + +/// +/// EFI_80211_ELEMENT_TIMEOUT_VAL +/// +typedef struct { + /// + /// Common header of an element. + /// + EFI_80211_ELEMENT_HEADER Hdr; + /// + /// Specifies the timeout interval type. + /// + UINT8 Type; + /// + /// Specifies the timeout interval value. + /// + UINT32 Value; +} EFI_80211_ELEMENT_TIMEOUT_VAL; + +/// +/// EFI_80211_ASSOCIATE_RESULT +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity from which the association request + /// was received. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the operational capabilities advertised by the AP. + /// + UINT16 CapabilityInfo; + /// + /// Specifies the association ID value assigned by the AP. + /// + UINT16 AssociationID; + /// + /// Indicates the measured RCPI of the corresponding association request frame. It is + /// an optional parameter and is set to zero if unavailable. + /// + UINT8 RCPIValue; + /// + /// Indicates the measured RSNI at the time the corresponding association request + /// frame was received. It is an optional parameter and is set to zero if unavailable. + /// + UINT8 RSNIValue; + /// + /// Specifies the parameters within the Extended Capabilities element that are + /// supported by the MAC entity. This is an optional parameter and may be NULL. + /// + EFI_80211_ELEMENT_EXT_CAP *ExtCapElement; + /// + /// Specifies the timeout interval when the result code is AssociateRefusedTemporarily. + /// + EFI_80211_ELEMENT_TIMEOUT_VAL TimeoutInterval; + /// + /// Specifies zero or more elements. This is an optional parameter and may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_ASSOCIATE_RESULT; + +/// +/// EFI_80211_ASSOCIATE_DATA_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI Wireless + /// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: Association operation completed successfully. + /// EFI_DEVICE_ERROR: An unexpected network or system error occurred. + /// + EFI_STATUS Status; + /// + /// Pointer to the association data. + /// + EFI_80211_ASSOCIATE_DATA *Data; + /// + /// Indicates the association state. + /// + EFI_80211_ASSOCIATE_RESULT_CODE ResultCode; + /// + /// Indicates the association result. It is caller's responsibility to free this + /// buffer. + /// + EFI_80211_ASSOCIATE_RESULT *Result; +} EFI_80211_ASSOCIATE_DATA_TOKEN; + +/// +/// EFI_80211_DISASSOCIATE_DATA +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity with which to perform the + /// disassociation process. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the reason for initiating the disassociation process. + /// + EFI_80211_REASON_CODE ReasonCode; + /// + /// Zero or more elements, may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_DISASSOCIATE_DATA; + +/// +/// EFI_80211_DISASSOCIATE_DATA_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI Wireless + /// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: Disassociation operation completed successfully. + /// EFI_DEVICE_ERROR: An unexpected network or system error occurred. + /// EFI_ACCESS_DENIED: The disassociation operation is not completed due to some + /// underlying hardware or software state. + /// EFI_NOT_READY: The disassociation operation is started but not yet completed. + /// + EFI_STATUS Status; + /// + /// Pointer to the disassociation data. + /// + EFI_80211_DISASSOCIATE_DATA *Data; + /// + /// Indicates the disassociation state. + /// + EFI_80211_DISASSOCIATE_RESULT_CODE ResultCode; +} EFI_80211_DISASSOCIATE_DATA_TOKEN; + +/// +/// EFI_80211_AUTHENTICATION_DATA +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity with which to perform the + /// authentication process. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the type of authentication algorithm to use during the authentication + /// process. + /// + EFI_80211_AUTHENTICATION_TYPE AuthType; + /// + /// Specifies a time limit in TU after which the authentication procedure is + /// terminated. + /// + UINT32 FailureTimeout; + /// + /// Specifies the set of elements to be included in the first message of the FT + /// authentication sequence, may be NULL. + /// + UINT8 *FTContent; + /// + /// Specifies the set of elements to be included in the SAE Commit Message or SAE + /// Confirm Message, may be NULL. + /// + UINT8 *SAEContent; + /// + /// Zero or more elements, may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_AUTHENTICATE_DATA; + +/// +/// EFI_80211_AUTHENTICATION_RESULT +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity from which the authentication request + /// was received. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the set of elements to be included in the second message of the FT + /// authentication sequence, may be NULL. + /// + UINT8 *FTContent; + /// + /// Specifies the set of elements to be included in the SAE Commit Message or SAE + /// Confirm Message, may be NULL. + /// + UINT8 *SAEContent; + /// + /// Zero or more elements, may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_AUTHENTICATE_RESULT; + +/// +/// EFI_80211_AUTHENTICATE_DATA_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI Wireless + /// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: Authentication operation completed successfully. + /// EFI_PROTOCOL_ERROR: Peer MAC entity rejects the authentication. + /// EFI_NO_RESPONSE: Peer MAC entity does not response the authentication request. + /// EFI_DEVICE_ERROR: An unexpected network or system error occurred. + /// EFI_ACCESS_DENIED: The authentication operation is not completed due to some + /// underlying hardware or software state. + /// EFI_NOT_READY: The authentication operation is started but not yet completed. + /// + EFI_STATUS Status; + /// + /// Pointer to the authentication data. + /// + EFI_80211_AUTHENTICATE_DATA *Data; + /// + /// Indicates the association state. + /// + EFI_80211_AUTHENTICATE_RESULT_CODE ResultCode; + /// + /// Indicates the association result. It is caller's responsibility to free this + /// buffer. + /// + EFI_80211_AUTHENTICATE_RESULT *Result; +} EFI_80211_AUTHENTICATE_DATA_TOKEN; + +/// +/// EFI_80211_DEAUTHENTICATE_DATA +/// +typedef struct { + /// + /// Specifies the address of the peer MAC entity with which to perform the + /// deauthentication process. + /// + EFI_80211_MAC_ADDRESS BSSId; + /// + /// Specifies the reason for initiating the deauthentication process. + /// + EFI_80211_REASON_CODE ReasonCode; + /// + /// Zero or more elements, may be NULL. + /// + UINT8 *VendorSpecificInfo; +} EFI_80211_DEAUTHENTICATE_DATA; + +/// +/// EFI_80211_DEAUTHENTICATE_DATA_TOKEN +/// +typedef struct { + /// + /// This Event will be signaled after the Status field is updated by the EFI Wireless + /// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. + /// + EFI_EVENT Event; + /// + /// Will be set to one of the following values: + /// EFI_SUCCESS: Deauthentication operation completed successfully. + /// EFI_DEVICE_ERROR: An unexpected network or system error occurred. + /// EFI_ACCESS_DENIED: The deauthentication operation is not completed due to some + /// underlying hardware or software state. + /// EFI_NOT_READY: The deauthentication operation is started but not yet + /// completed. + /// + EFI_STATUS Status; + /// + /// Pointer to the deauthentication data. + /// + EFI_80211_DEAUTHENTICATE_DATA *Data; +} EFI_80211_DEAUTHENTICATE_DATA_TOKEN; + +/** + Request a survey of potential BSSs that administrator can later elect to try to join. + + The Scan() function returns the description of the set of BSSs detected by the scan + process. Passive scan operation is performed by default. + + @param[in] This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL + instance. + @param[in] Data Pointer to the scan token. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + Data->Data is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters are not supported + by this implementation. + @retval EFI_ALREADY_STARTED The scan operation is already started. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_SCAN)( + IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This, + IN EFI_80211_SCAN_DATA_TOKEN *Data + ); + +/** + Request an association with a specified peer MAC entity that is within an AP. + + The Associate() function provides the capability for MAC layer to become associated + with an AP. + + @param[in] This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL + instance. + @param[in] Data Pointer to the association token. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + Data->Data is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters are not supported + by this implementation. + @retval EFI_ALREADY_STARTED The association process is already started. + @retval EFI_NOT_READY Authentication is not performed before this association + process. + @retval EFI_NOT_FOUND The specified peer MAC entity is not found. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE)( + IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This, + IN EFI_80211_ASSOCIATE_DATA_TOKEN *Data + ); + +/** + Request a disassociation with a specified peer MAC entity. + + The Disassociate() function is invoked to terminate an existing association. + Disassociation is a notification and cannot be refused by the receiving peer except + when management frame protection is negotiated and the message integrity check fails. + + @param[in] This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL + instance. + @param[in] Data Pointer to the disassociation token. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + @retval EFI_ALREADY_STARTED The disassociation process is already started. + @retval EFI_NOT_READY The disassociation service is invoked to a + nonexistent association relationship. + @retval EFI_NOT_FOUND The specified peer MAC entity is not found. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE)( + IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This, + IN EFI_80211_DISASSOCIATE_DATA_TOKEN *Data + ); + +/** + Request the process of establishing an authentication relationship with a peer MAC + entity. + + The Authenticate() function requests authentication with a specified peer MAC entity. + This service might be time-consuming thus is designed to be invoked independently of + the association service. + + @param[in] This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL + instance. + @param[in] Data Pointer to the authentication token. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + Data.Data is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters are not supported + by this implementation. + @retval EFI_ALREADY_STARTED The authentication process is already started. + @retval EFI_NOT_FOUND The specified peer MAC entity is not found. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE)( + IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This, + IN EFI_80211_AUTHENTICATE_DATA_TOKEN *Data + ); + +/** + Invalidate the authentication relationship with a peer MAC entity. + + The Deauthenticate() function requests that the authentication relationship with a + specified peer MAC entity be invalidated. Deauthentication is a notification and when + it is sent out the association at the transmitting station is terminated. + + @param[in] This Pointer to the EFI_WIRELESS_MAC_CONNECTION_PROTOCOL + instance. + @param[in] Data Pointer to the deauthentication token. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE: + This is NULL. + Data is NULL. + Data.Data is NULL. + @retval EFI_ALREADY_STARTED The deauthentication process is already started. + @retval EFI_NOT_READY The deauthentication service is invoked to a + nonexistent association or authentication relationship. + @retval EFI_NOT_FOUND The specified peer MAC entity is not found. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be allocated. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE)( + IN EFI_WIRELESS_MAC_CONNECTION_PROTOCOL *This, + IN EFI_80211_DEAUTHENTICATE_DATA_TOKEN *Data + ); + +/// +/// The EFI_WIRELESS_MAC_CONNECTION_PROTOCOL is designed to provide management service +/// interfaces for the EFI wireless network stack to establish wireless connection with +/// AP. An EFI Wireless MAC Connection Protocol instance will be installed on each +/// communication device that the EFI wireless network stack runs on. +/// +struct _EFI_WIRELESS_MAC_CONNECTION_PROTOCOL { + EFI_WIRELESS_MAC_CONNECTION_SCAN Scan; + EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE Associate; + EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE Disassociate; + EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE Authenticate; + EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE Deauthenticate; +}; + +extern EFI_GUID gEfiWiFiProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi2.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi2.h new file mode 100644 index 0000000000..2fb1790f3a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Protocol/WiFi2.h @@ -0,0 +1,407 @@ +/** @file + This file defines the EFI Wireless MAC Connection II Protocol. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is introduced in UEFI Specification 2.6 + +**/ + +#ifndef __EFI_WIFI2_PROTOCOL_H__ +#define __EFI_WIFI2_PROTOCOL_H__ + +#define EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL_GUID \ + { \ + 0x1b0fb9bf, 0x699d, 0x4fdd, { 0xa7, 0xc3, 0x25, 0x46, 0x68, 0x1b, 0xf6, 0x3b } \ + } + +typedef struct _EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL; + +/// +/// EFI_80211_BSS_TYPE +/// +typedef enum { + IeeeInfrastructureBSS, + IeeeIndependentBSS, + IeeeMeshBSS, + IeeeAnyBss +} EFI_80211_BSS_TYPE; + +/// +/// EFI_80211_CONNECT_NETWORK_RESULT_CODE +/// +typedef enum { + // + // The connection establishment operation finished successfully. + // + ConnectSuccess, + // + // The connection was refused by the Network. + // + ConnectRefused, + // + // The connection establishment operation failed (i.e, Network is not + // detected). + // + ConnectFailed, + // + // The connection establishment operation was terminated on timeout. + // + ConnectFailureTimeout, + // + // The connection establishment operation failed on other reason. + // + ConnectFailedReasonUnspecified +} EFI_80211_CONNECT_NETWORK_RESULT_CODE; + +/// +/// EFI_80211_MAC_ADDRESS +/// +typedef struct { + UINT8 Addr[6]; +} EFI_80211_MAC_ADDRESS; + +#define EFI_MAX_SSID_LEN 32 + +/// +/// EFI_80211_SSID +/// +typedef struct { + // + // Length in bytes of the SSId. If zero, ignore SSId field. + // + UINT8 SSIdLen; + // + // Specifies the service set identifier. + // + UINT8 SSId[EFI_MAX_SSID_LEN]; +} EFI_80211_SSID; + +/// +/// EFI_80211_GET_NETWORKS_DATA +/// +typedef struct { + // + // The number of EFI_80211_SSID in SSIDList. If zero, SSIDList should be + // ignored. + // + UINT32 NumOfSSID; + // + // The SSIDList is a pointer to an array of EFI_80211_SSID instances. The + // number of entries is specified by NumOfSSID. The array should only include + // SSIDs of hidden networks. It is suggested that the caller inputs less than + // 10 elements in the SSIDList. It is the caller's responsibility to free + // this buffer. + // + EFI_80211_SSID SSIDList[1]; +} EFI_80211_GET_NETWORKS_DATA; + +/// +/// EFI_80211_SUITE_SELECTOR +/// +typedef struct { + // + // Organization Unique Identifier, as defined in IEEE 802.11 standard, + // usually set to 00-0F-AC. + // + UINT8 Oui[3]; + // + // Suites types, as defined in IEEE 802.11 standard. + // + UINT8 SuiteType; +} EFI_80211_SUITE_SELECTOR; + +/// +/// EFI_80211_AKM_SUITE_SELECTOR +/// +typedef struct { + // + // Indicates the number of AKM suite selectors that are contained in + // AKMSuiteList. If zero, the AKMSuiteList is ignored. + // + UINT16 AKMSuiteCount; + // + // A variable-length array of AKM suites, as defined in IEEE 802.11 standard, + // Table 8-101. The number of entries is specified by AKMSuiteCount. + // + EFI_80211_SUITE_SELECTOR AKMSuiteList[1]; +} EFI_80211_AKM_SUITE_SELECTOR; + +/// +/// EFI_80211_CIPHER_SUITE_SELECTOR +/// +typedef struct { + // + // Indicates the number of cipher suites that are contained in + // CipherSuiteList. If zero, the CipherSuiteList is ignored. + // + UINT16 CipherSuiteCount; + // + // A variable-length array of cipher suites, as defined in IEEE 802.11 + // standard, Table 8-99. The number of entries is specified by + // CipherSuiteCount. + // + EFI_80211_SUITE_SELECTOR CipherSuiteList[1]; +} EFI_80211_CIPHER_SUITE_SELECTOR; + +/// +/// EFI_80211_NETWORK +/// +typedef struct { + // + // Specifies the type of the BSS. + // + EFI_80211_BSS_TYPE BSSType; + // + // Specifies the SSID of the BSS. + // + EFI_80211_SSID SSId; + // + // Pointer to the AKM suites supported in the wireless network. + // + EFI_80211_AKM_SUITE_SELECTOR *AKMSuite; + // + // Pointer to the cipher suites supported in the wireless network. + // + EFI_80211_CIPHER_SUITE_SELECTOR *CipherSuite; +} EFI_80211_NETWORK; + +/// +/// EFI_80211_NETWORK_DESCRIPTION +/// +typedef struct { + // + // Specifies the found wireless network. + // + EFI_80211_NETWORK Network; + // + // Indicates the network quality as a value between 0 to 100, where 100 + // indicates the highest network quality. + // + UINT8 NetworkQuality; +} EFI_80211_NETWORK_DESCRIPTION; + +/// +/// EFI_80211_GET_NETWORKS_RESULT +/// +typedef struct { + // + // The number of EFI_80211_NETWORK_DESCRIPTION in NetworkDesc. If zero, + // NetworkDesc should be ignored. + // + UINT8 NumOfNetworkDesc; + // + // The NetworkDesc is a pointer to an array of EFI_80211_NETWORK_DESCRIPTION + // instances. It is caller's responsibility to free this buffer. + // + EFI_80211_NETWORK_DESCRIPTION NetworkDesc[1]; +} EFI_80211_GET_NETWORKS_RESULT; + +/// +/// EFI_80211_GET_NETWORKS_TOKEN +/// +typedef struct { + // + // If the status code returned by GetNetworks() is EFI_SUCCESS, then this + // Event will be signaled after the Status field is updated by the EFI + // Wireless MAC Connection Protocol II driver. The type of Event must be + // EFI_NOTIFY_SIGNAL. + // + EFI_EVENT Event; + // + // Will be set to one of the following values: + // EFI_SUCCESS: The operation completed successfully. + // EFI_NOT_FOUND: Failed to find available wireless networks. + // EFI_DEVICE_ERROR: An unexpected network or system error occurred. + // EFI_ACCESS_DENIED: The operation is not completed due to some underlying + // hardware or software state. + // EFI_NOT_READY: The operation is started but not yet completed. + // + EFI_STATUS Status; + // + // Pointer to the input data for getting networks. + // + EFI_80211_GET_NETWORKS_DATA *Data; + // + // Indicates the scan result. It is caller's responsibility to free this + // buffer. + // + EFI_80211_GET_NETWORKS_RESULT *Result; +} EFI_80211_GET_NETWORKS_TOKEN; + +/// +/// EFI_80211_CONNECT_NETWORK_DATA +/// +typedef struct { + // + // Specifies the wireless network to connect to. + // + EFI_80211_NETWORK *Network; + // + // Specifies a time limit in seconds that is optionally present, after which + // the connection establishment procedure is terminated by the UNDI driver. + // This is an optional parameter and may be 0. Values of 5 seconds or higher + // are recommended. + // + UINT32 FailureTimeout; +} EFI_80211_CONNECT_NETWORK_DATA; + +/// +/// EFI_80211_CONNECT_NETWORK_TOKEN +/// +typedef struct { + // + // If the status code returned by ConnectNetwork() is EFI_SUCCESS, then this + // Event will be signaled after the Status field is updated by the EFI + // Wireless MAC Connection Protocol II driver. The type of Event must be + // EFI_NOTIFY_SIGNAL. + // + EFI_EVENT Event; + // + // Will be set to one of the following values: + // EFI_SUCCESS: The operation completed successfully. + // EFI_DEVICE_ERROR: An unexpected network or system error occurred. + // EFI_ACCESS_DENIED: The operation is not completed due to some underlying + // hardware or software state. + // EFI_NOT_READY: The operation is started but not yet completed. + // + EFI_STATUS Status; + // + // Pointer to the connection data. + // + EFI_80211_CONNECT_NETWORK_DATA *Data; + // + // Indicates the connection state. + // + EFI_80211_CONNECT_NETWORK_RESULT_CODE ResultCode; +} EFI_80211_CONNECT_NETWORK_TOKEN; + +/// +/// EFI_80211_DISCONNECT_NETWORK_TOKEN +/// +typedef struct { + // + // If the status code returned by DisconnectNetwork() is EFI_SUCCESS, then + // this Event will be signaled after the Status field is updated by the EFI + // Wireless MAC Connection Protocol II driver. The type of Event must be + // EFI_NOTIFY_SIGNAL. + // + EFI_EVENT Event; + // + // Will be set to one of the following values: + // EFI_SUCCESS: The operation completed successfully + // EFI_DEVICE_ERROR: An unexpected network or system error occurred. + // EFI_ACCESS_DENIED: The operation is not completed due to some underlying + // hardware or software state. + // + EFI_STATUS Status; +} EFI_80211_DISCONNECT_NETWORK_TOKEN; + +/** + Request a survey of potential wireless networks that administrator can later + elect to try to join. + + @param[in] This Pointer to the + EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL + instance. + @param[in] Token Pointer to the token for getting wireless + network. + + @retval EFI_SUCCESS The operation started, and an event will + eventually be raised for the caller. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + This is NULL. + Token is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters is not + supported by this implementation. + @retval EFI_ALREADY_STARTED The operation of getting wireless network is + already started. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be + allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS) ( + IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This, + IN EFI_80211_GET_NETWORKS_TOKEN *Token + ); + +/** + Connect a wireless network specified by a particular SSID, BSS type and + Security type. + + @param[in] This Pointer to the + EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL + instance. + @param[in] Token Pointer to the token for connecting wireless + network. + + @retval EFI_SUCCESS The operation started successfully. Results + will be notified eventually. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + This is NULL. + Token is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters are not + supported by this implementation. + @retval EFI_ALREADY_STARTED The connection process is already started. + @retval EFI_NOT_FOUND The specified wireless network is not found. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be + allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK) ( + IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This, + IN EFI_80211_CONNECT_NETWORK_TOKEN *Token + ); + +/** + Request a disconnection with current connected wireless network. + + @param[in] This Pointer to the + EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL + instance. + @param[in] Token Pointer to the token for disconnecting + wireless network. + + @retval EFI_SUCCESS The operation started successfully. Results + will be notified eventually. + @retval EFI_INVALID_PARAMETER One or more of the following conditions is + TRUE: + This is NULL. + Token is NULL. + @retval EFI_UNSUPPORTED One or more of the input parameters are not + supported by this implementation. + @retval EFI_NOT_FOUND Not connected to a wireless network. + @retval EFI_OUT_OF_RESOURCES Required system resources could not be + allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK) ( + IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This, + IN EFI_80211_DISCONNECT_NETWORK_TOKEN *Token + ); + +/// +/// The EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL provides network management +/// service interfaces for 802.11 network stack. It is used by network +/// applications (and drivers) to establish wireless connection with a wireless +/// network. +/// +struct _EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL { + EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS GetNetworks; + EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK ConnectNetwork; + EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK DisconnectNetwork; +}; + +extern EFI_GUID gEfiWiFi2ProtocolGuid; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Cpuid.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Cpuid.h new file mode 100644 index 0000000000..09aebd9894 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Cpuid.h @@ -0,0 +1,737 @@ +/** @file + CPUID leaf definitions. + + Provides defines for CPUID leaf indexes. Data structures are provided for + registers returned by a CPUID leaf that contain one or more bit fields. + If a register returned is a single 32-bit value, then a data structure is + not provided for that register. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __AMD_CPUID_H__ +#define __AMD_CPUID_H__ + +/** +CPUID Signature Information + +@param EAX CPUID_SIGNATURE (0x00) + +@retval EAX Returns the highest value the CPUID instruction recognizes for + returning basic processor information. The value is returned is + processor specific. +@retval EBX First 4 characters of a vendor identification string. +@retval ECX Last 4 characters of a vendor identification string. +@retval EDX Middle 4 characters of a vendor identification string. + +**/ + +/// +/// @{ CPUID signature values returned by AMD processors +/// +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') +#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') +/// +/// @} +/// + + +/** + CPUID Extended Processor Signature and Features + + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX Extended Family, Model, Stepping Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. + @retval EBX Brand Identifier + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. + @retval ECX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. +**/ + +/** + CPUID Extended Processor Signature and Features EAX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Stepping. + /// + UINT32 Stepping:4; + /// + /// [Bits 7:4] Base Model. + /// + UINT32 BaseModel:4; + /// + /// [Bits 11:8] Base Family. + /// + UINT32 BaseFamily:4; + /// + /// [Bit 15:12] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 19:16] Extended Model. + /// + UINT32 ExtModel:4; + /// + /// [Bits 27:20] Extended Family. + /// + UINT32 ExtFamily:8; + /// + /// [Bit 31:28] Reserved. + /// + UINT32 Reserved2:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EAX; + +/** + CPUID Extended Processor Signature and Features EBX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 27:0] Reserved. + /// + UINT32 Reserved:28; + /// + /// [Bit 31:28] Package Type. + /// + UINT32 PkgType:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EBX; + +/** + CPUID Extended Processor Signature and Features ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF:1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy:1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM:1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace:1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8:1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT:1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A:1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse:1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW:1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW:1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS:1; + /// + /// [Bit 11] Extended Operation Support. + /// + UINT32 XOP:1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT:1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT:1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP:1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4:1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE:1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2:4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions:1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore:1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3:2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension:1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc:1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3:1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended:1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4:2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Features EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 floating point unit on-chip. + /// + UINT32 FPU:1; + /// + /// [Bit 1] Virtual-mode enhancements. + /// + UINT32 VME:1; + /// + /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. + /// + UINT32 DE:1; + /// + /// [Bit 3] Page-size extensions (4 MB pages). + /// + UINT32 PSE:1; + /// + /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. + /// + UINT32 TSC:1; + /// + /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. + /// + UINT32 MSR:1; + /// + /// [Bit 6] Physical-address extensions (PAE). + /// + UINT32 PAE:1; + /// + /// [Bit 7] Machine check exception, CR4.MCE. + /// + UINT32 MCE:1; + /// + /// [Bit 8] CMPXCHG8B instruction. + /// + UINT32 CMPXCHG8B:1; + /// + /// [Bit 9] APIC exists and is enabled. + /// + UINT32 APIC:1; + /// + /// [Bit 10] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 11] SYSCALL and SYSRET instructions. + /// + UINT32 SYSCALL_SYSRET:1; + /// + /// [Bit 12] Memory-type range registers. + /// + UINT32 MTRR:1; + /// + /// [Bit 13] Page global extension, CR4.PGE. + /// + UINT32 PGE:1; + /// + /// [Bit 14] Machine check architecture, MCG_CAP. + /// + UINT32 MCA:1; + /// + /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. + /// + UINT32 CMOV:1; + /// + /// [Bit 16] Page attribute table. + /// + UINT32 PAT:1; + /// + /// [Bit 17] Page-size extensions. + /// + UINT32 PSE36 : 1; + /// + /// [Bit 19:18] Reserved. + /// + UINT32 Reserved2:2; + /// + /// [Bit 20] No-execute page protection. + /// + UINT32 NX:1; + /// + /// [Bit 21] Reserved. + /// + UINT32 Reserved3:1; + /// + /// [Bit 22] AMD Extensions to MMX instructions. + /// + UINT32 MmxExt:1; + /// + /// [Bit 23] MMX instructions. + /// + UINT32 MMX:1; + /// + /// [Bit 24] FXSAVE and FXRSTOR instructions. + /// + UINT32 FFSR:1; + /// + /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. + /// + UINT32 FFXSR:1; + /// + /// [Bit 26] 1-GByte large page support. + /// + UINT32 Page1GB:1; + /// + /// [Bit 27] RDTSCP instructions. + /// + UINT32 RDTSCP:1; + /// + /// [Bit 28] Reserved. + /// + UINT32 Reserved4:1; + /// + /// [Bit 29] Long Mode. + /// + UINT32 LM:1; + /// + /// [Bit 30] 3DNow! instructions. + /// + UINT32 ThreeDNow:1; + /// + /// [Bit 31] AMD Extensions to 3DNow! instructions. + /// + UINT32 ThreeDNowExt:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EDX; + + +/** +CPUID Linear Physical Address Size + +@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + +@retval EAX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. +@retval EBX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. +@retval ECX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. +@retval EDX Reserved. +**/ + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Maximum physical byte address size in bits. + /// + UINT32 PhysicalAddressBits:8; + /// + /// [Bits 15:8] Maximum linear byte address size in bits. + /// + UINT32 LinearAddressBits:8; + /// + /// [Bits 23:16] Maximum guest physical byte address size in bits. + /// + UINT32 GuestPhysAddrSize:8; + /// + /// [Bit 31:24] Reserved. + /// + UINT32 Reserved:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; + +/** + CPUID Linear Physical Address Size EBX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Clear Zero Instruction. + /// + UINT32 CLZERO:1; + /// + /// [Bits 1] Instructions retired count support. + /// + UINT32 IRPerf:1; + /// + /// [Bits 2] Restore error pointers for XSave instructions. + /// + UINT32 XSaveErPtr:1; + /// + /// [Bit 31:3] Reserved. + /// + UINT32 Reserved:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; + +/** + CPUID Linear Physical Address Size ECX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of threads - 1. + /// + UINT32 NC:8; + /// + /// [Bit 11:8] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 15:12] APIC ID size. + /// + UINT32 ApicIdCoreIdSize:4; + /// + /// [Bits 17:16] Performance time-stamp counter size. + /// + UINT32 PerfTscSize:2; + /// + /// [Bit 31:18] Reserved. + /// + UINT32 Reserved2:14; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; + + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. + @retval EBX Core Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. + @retval ECX Node Identifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. + @retval EDX Reserved. +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId:8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore:8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId:8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor:3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + + +/** + CPUID Memory Encryption Information + + @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) + + @retval EAX Returns the memory encryption feature support status. + @retval EBX If memory encryption feature is present then return + the page table bit number used to enable memory encryption support + and reducing of physical address space in bits. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ + +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F + +/** + CPUID Memory Encryption support information EAX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Memory Encryption (Sme) Support + /// + UINT32 SmeBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support + /// + UINT32 SevBit:1; + + /// + /// [Bit 2] Page flush MSR support + /// + UINT32 PageFlushMsrBit:1; + + /// + /// [Bit 3] Encrypted state support + /// + UINT32 SevEsBit:1; + + /// + /// [Bit 31:4] Reserved + /// + UINT32 ReservedBits:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; + +/** + CPUID Memory Encryption support information EBX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 5:0] Page table bit number used to enable memory encryption + /// + UINT32 PtePosBits:6; + + /// + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled + /// + UINT32 ReducedPhysBits:5; + + /// + /// [Bit 31:12] Reserved + /// + UINT32 ReservedBits:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; + +/** + CPUID Memory Encryption support information ECX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Number of encrypted guest supported simultaneously + /// + UINT32 NumGuests; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_ECX; + +/** + CPUID Memory Encryption support information EDX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID + /// + UINT32 MinAsid; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EDX; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Fam17Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Fam17Msr.h new file mode 100644 index 0000000000..67fea3dbdb --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -0,0 +1,136 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __FAM17_MSR_H__ +#define __FAM17_MSR_H__ + +/** + Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register + +**/ +#define MSR_SEV_ES_GHCB 0xc0010130 + +/** + MSR information returned for #MSR_SEV_ES_GHCB +**/ +typedef union { + struct { + UINT32 Function:12; + UINT32 Reserved1:20; + UINT32 Reserved2:32; + } GhcbInfo; + + struct { + UINT8 Reserved[3]; + UINT8 SevEncryptionBitPos; + UINT16 SevEsProtocolMin; + UINT16 SevEsProtocolMax; + } GhcbProtocol; + + struct { + UINT32 Function:12; + UINT32 ReasonCodeSet:4; + UINT32 ReasonCode:8; + UINT32 Reserved1:8; + UINT32 Reserved2:32; + } GhcbTerminate; + + struct { + UINT64 Function:12; + UINT64 Features:52; + } GhcbHypervisorFeatures; + + struct { + UINT64 Function:12; + UINT64 GuestFrameNumber:52; + } GhcbGpaRegister; + + struct { + UINT64 Function:12; + UINT64 GuestFrameNumber:40; + UINT64 Operation:4; + UINT64 Reserved:8; + } SnpPageStateChangeRequest; + + struct { + UINT32 Function:12; + UINT32 Reserved:20; + UINT32 ErrorCode; + } SnpPageStateChangeResponse; + + VOID *Ghcb; + + UINT64 GhcbPhysicalAddress; +} MSR_SEV_ES_GHCB_REGISTER; + +#define GHCB_INFO_SEV_INFO 1 +#define GHCB_INFO_SEV_INFO_GET 2 +#define GHCB_INFO_CPUID_REQUEST 4 +#define GHCB_INFO_CPUID_RESPONSE 5 +#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18 +#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE 19 +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20 +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE 21 +#define GHCB_HYPERVISOR_FEATURES_REQUEST 128 +#define GHCB_HYPERVISOR_FEATURES_RESPONSE 129 +#define GHCB_INFO_TERMINATE_REQUEST 256 + +#define GHCB_TERMINATE_GHCB 0 +#define GHCB_TERMINATE_GHCB_GENERAL 0 +#define GHCB_TERMINATE_GHCB_PROTOCOL 1 + +/** + Secure Encrypted Virtualization (SEV) status register + +**/ +#define MSR_SEV_STATUS 0xc0010131 + +/** + MSR information returned for #MSR_SEV_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled + /// + UINT32 SevBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled + /// + UINT32 SevEsBit:1; + + /// + /// [Bit 2] Secure Nested Paging (SevSnp) is enabled + /// + UINT32 SevSnpBit:1; + + UINT32 Reserved2:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SEV_STATUS_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Ghcb.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Ghcb.h new file mode 100644 index 0000000000..84f79808ab --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Ghcb.h @@ -0,0 +1,282 @@ +/** @file + Guest-Hypervisor Communication Block (GHCB) Definition. + + Provides data types allowing an SEV-ES guest to interact with the hypervisor + using the GHCB protocol. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SEV-ES Guest-Hypervisor Communication Block Standardization + +**/ + +#ifndef __GHCB_H__ +#define __GHCB_H__ + +#include +#include +#include + +#define UD_EXCEPTION 6 +#define GP_EXCEPTION 13 +#define VC_EXCEPTION 29 + +#define GHCB_VERSION_MIN 1 +#define GHCB_VERSION_MAX 1 + +#define GHCB_STANDARD_USAGE 0 + +// +// SVM Exit Codes +// +#define SVM_EXIT_DR7_READ 0x27ULL +#define SVM_EXIT_DR7_WRITE 0x37ULL +#define SVM_EXIT_RDTSC 0x6EULL +#define SVM_EXIT_RDPMC 0x6FULL +#define SVM_EXIT_CPUID 0x72ULL +#define SVM_EXIT_INVD 0x76ULL +#define SVM_EXIT_IOIO_PROT 0x7BULL +#define SVM_EXIT_MSR 0x7CULL +#define SVM_EXIT_VMMCALL 0x81ULL +#define SVM_EXIT_RDTSCP 0x87ULL +#define SVM_EXIT_WBINVD 0x89ULL +#define SVM_EXIT_MONITOR 0x8AULL +#define SVM_EXIT_MWAIT 0x8BULL +#define SVM_EXIT_NPF 0x400ULL + +// +// VMG Special Exit Codes +// +#define SVM_EXIT_MMIO_READ 0x80000001ULL +#define SVM_EXIT_MMIO_WRITE 0x80000002ULL +#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL +#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL +#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL +#define SVM_EXIT_SNP_PAGE_STATE_CHANGE 0x80000010ULL +#define SVM_EXIT_SNP_AP_CREATION 0x80000013ULL +#define SVM_EXIT_HYPERVISOR_FEATURES 0x8000FFFDULL +#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL + +// +// IOIO Exit Information +// +#define IOIO_TYPE_STR BIT2 +#define IOIO_TYPE_IN 1 +#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) +#define IOIO_TYPE_OUT 0 +#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR) + +#define IOIO_REP BIT3 + +#define IOIO_ADDR_64 BIT9 +#define IOIO_ADDR_32 BIT8 +#define IOIO_ADDR_16 BIT7 + +#define IOIO_DATA_32 BIT6 +#define IOIO_DATA_16 BIT5 +#define IOIO_DATA_8 BIT4 +#define IOIO_DATA_MASK (BIT6 | BIT5 | BIT4) +#define IOIO_DATA_OFFSET 4 +#define IOIO_DATA_BYTES(x) (((x) & IOIO_DATA_MASK) >> IOIO_DATA_OFFSET) + +#define IOIO_SEG_ES 0 +#define IOIO_SEG_DS (BIT11 | BIT10) + +// +// AP Creation Information +// +#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT 0 +#define SVM_VMGEXIT_SNP_AP_CREATE 1 +#define SVM_VMGEXIT_SNP_AP_DESTROY 2 + +typedef PACKED struct { + UINT8 Reserved1[203]; + UINT8 Cpl; + UINT8 Reserved8[300]; + UINT64 Rax; + UINT8 Reserved4[264]; + UINT64 Rcx; + UINT64 Rdx; + UINT64 Rbx; + UINT8 Reserved5[112]; + UINT64 SwExitCode; + UINT64 SwExitInfo1; + UINT64 SwExitInfo2; + UINT64 SwScratch; + UINT8 Reserved6[56]; + UINT64 XCr0; + UINT8 ValidBitmap[16]; + UINT64 X87StateGpa; + UINT8 Reserved7[1016]; +} GHCB_SAVE_AREA; + +typedef PACKED struct { + GHCB_SAVE_AREA SaveArea; + UINT8 SharedBuffer[2032]; + UINT8 Reserved1[10]; + UINT16 ProtocolVersion; + UINT32 GhcbUsage; +} GHCB; + +#define GHCB_SAVE_AREA_QWORD_OFFSET(RegisterField) \ + (OFFSET_OF (GHCB, SaveArea.RegisterField) / sizeof (UINT64)) + +typedef enum { + GhcbCpl = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl), + GhcbRax = GHCB_SAVE_AREA_QWORD_OFFSET (Rax), + GhcbRbx = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx), + GhcbRcx = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx), + GhcbRdx = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx), + GhcbXCr0 = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0), + GhcbSwExitCode = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode), + GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1), + GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2), + GhcbSwScratch = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch), +} GHCB_REGISTER; + +typedef union { + struct { + UINT32 Lower32Bits; + UINT32 Upper32Bits; + } Elements; + + UINT64 Uint64; +} GHCB_EXIT_INFO; + +typedef union { + struct { + UINT32 Vector:8; + UINT32 Type:3; + UINT32 ErrorCodeValid:1; + UINT32 Rsvd:19; + UINT32 Valid:1; + UINT32 ErrorCode; + } Elements; + + UINT64 Uint64; +} GHCB_EVENT_INJECTION; + +#define GHCB_EVENT_INJECTION_TYPE_INT 0 +#define GHCB_EVENT_INJECTION_TYPE_NMI 2 +#define GHCB_EVENT_INJECTION_TYPE_EXCEPTION 3 +#define GHCB_EVENT_INJECTION_TYPE_SOFT_INT 4 + +// +// Hypervisor features +// +#define GHCB_HV_FEATURES_SNP BIT0 +#define GHCB_HV_FEATURES_SNP_AP_CREATE (GHCB_HV_FEATURES_SNP | BIT1) +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2) +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3) + +// +// SNP Page State Change. +// +// Note that the PSMASH and UNSMASH operations are not supported when using the MSR protocol. +// +#define SNP_PAGE_STATE_PRIVATE 1 +#define SNP_PAGE_STATE_SHARED 2 +#define SNP_PAGE_STATE_PSMASH 3 +#define SNP_PAGE_STATE_UNSMASH 4 + +typedef struct { + UINT64 CurrentPage:12; + UINT64 GuestFrameNumber:40; + UINT64 Operation:4; + UINT64 PageSize:1; + UINT64 Reserved:7; +} SNP_PAGE_STATE_ENTRY; + +typedef struct { + UINT16 CurrentEntry; + UINT16 EndEntry; + UINT32 Reserved; +} SNP_PAGE_STATE_HEADER; + +#define SNP_PAGE_STATE_MAX_ENTRY 253 + +typedef struct { + SNP_PAGE_STATE_HEADER Header; + SNP_PAGE_STATE_ENTRY Entry[SNP_PAGE_STATE_MAX_ENTRY]; +} SNP_PAGE_STATE_CHANGE_INFO; + +// +// SEV-ES save area mapping structures used for SEV-SNP AP Creation. +// Only the fields required to be set to a non-zero value are defined. +// +// The segment register definition is defined for processor reset/real mode +// (as when an INIT of the vCPU is requested). Should other modes (long mode, +// etc.) be required, then the definitions can be enhanced. +// + +// +// Segment types at processor reset, See AMD APM Volume 2, Table 14-2. +// +#define SEV_ES_RESET_CODE_SEGMENT_TYPE 0xA +#define SEV_ES_RESET_DATA_SEGMENT_TYPE 0x2 + +#define SEV_ES_RESET_LDT_TYPE 0x2 +#define SEV_ES_RESET_TSS_TYPE 0x3 + +#pragma pack (1) +typedef union { + struct { + UINT16 Type:4; + UINT16 Sbit:1; + UINT16 Dpl:2; + UINT16 Present:1; + UINT16 Avl:1; + UINT16 Reserved1:1; + UINT16 Db:1; + UINT16 Granularity:1; + } Bits; + UINT16 Uint16; +} SEV_ES_SEGMENT_REGISTER_ATTRIBUTES; + +typedef struct { + UINT16 Selector; + SEV_ES_SEGMENT_REGISTER_ATTRIBUTES Attributes; + UINT32 Limit; + UINT64 Base; +} SEV_ES_SEGMENT_REGISTER; + +typedef struct { + SEV_ES_SEGMENT_REGISTER Es; + SEV_ES_SEGMENT_REGISTER Cs; + SEV_ES_SEGMENT_REGISTER Ss; + SEV_ES_SEGMENT_REGISTER Ds; + SEV_ES_SEGMENT_REGISTER Fs; + SEV_ES_SEGMENT_REGISTER Gs; + SEV_ES_SEGMENT_REGISTER Gdtr; + SEV_ES_SEGMENT_REGISTER Ldtr; + SEV_ES_SEGMENT_REGISTER Idtr; + SEV_ES_SEGMENT_REGISTER Tr; + UINT8 Reserved1[42]; + UINT8 Vmpl; + UINT8 Reserved2[5]; + UINT64 Efer; + UINT8 Reserved3[112]; + UINT64 Cr4; + UINT8 Reserved4[8]; + UINT64 Cr0; + UINT64 Dr7; + UINT64 Dr6; + UINT64 Rflags; + UINT64 Rip; + UINT8 Reserved5[232]; + UINT64 GPat; + UINT8 Reserved6[320]; + UINT64 SevFeatures; + UINT8 Reserved7[48]; + UINT64 XCr0; + UINT8 Reserved8[24]; + UINT32 Mxcsr; + UINT16 X87Ftw; + UINT8 Reserved9[2]; + UINT16 X87Fcw; +} SEV_ES_SAVE_AREA; +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Msr.h new file mode 100644 index 0000000000..024d5aa6de --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Amd/Msr.h @@ -0,0 +1,23 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2017 - 2019, Advanced Micro Devices. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 + +**/ + +#ifndef __AMD_MSR_H__ +#define __AMD_MSR_H__ + +#include +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/ArchitecturalMsr.h new file mode 100644 index 0000000000..22b9ec36f4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -0,0 +1,6572 @@ +/** @file + Intel Architectural MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __INTEL_ARCHITECTURAL_MSR_H__ +#define __INTEL_ARCHITECTURAL_MSR_H__ + +/** + See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H). + + @param ECX MSR_IA32_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR); + AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr); + @endcode + @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM. +**/ +#define MSR_IA32_P5_MC_ADDR 0x00000000 + + +/** + See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H. + + @param ECX MSR_IA32_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE); + AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr); + @endcode + @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM. +**/ +#define MSR_IA32_P5_MC_TYPE 0x00000001 + + +/** + See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced + at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE); + AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr); + @endcode + @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM. +**/ +#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006 + + +/** + See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family / + Display Model 05_01H. + + @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER); + AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr); + @endcode + @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM. +**/ +#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010 + + +/** + Platform ID (RO) The operating system can use this MSR to determine "slot" + information for the processor and the proper microcode update to load. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_IA32_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + @endcode + @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. +**/ +#define MSR_IA32_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_IA32_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:18; + /// + /// [Bits 52:50] Platform Id (RO) Contains information concerning the + /// intended platform for the processor. + /// 52 51 50 + /// -- -- -- + /// 0 0 0 Processor Flag 0. + /// 0 0 1 Processor Flag 1 + /// 0 1 0 Processor Flag 2 + /// 0 1 1 Processor Flag 3 + /// 1 0 0 Processor Flag 4 + /// 1 0 1 Processor Flag 5 + /// 1 1 0 Processor Flag 6 + /// 1 1 1 Processor Flag 7 + /// + UINT32 PlatformId:3; + UINT32 Reserved3:11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PLATFORM_ID_REGISTER; + + +/** + 06_01H. + + @param ECX MSR_IA32_APIC_BASE (0x0000001B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_APIC_BASE_REGISTER. + + Example usage + @code + MSR_IA32_APIC_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64); + @endcode + @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM. +**/ +#define MSR_IA32_APIC_BASE 0x0000001B + +/** + MSR information returned for MSR index #MSR_IA32_APIC_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bit 8] BSP flag (R/W). + /// + UINT32 BSP:1; + UINT32 Reserved2:1; + /// + /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display + /// Model 06_1AH. + /// + UINT32 EXTD:1; + /// + /// [Bit 11] APIC Global Enable (R/W). + /// + UINT32 EN:1; + /// + /// [Bits 31:12] APIC Base (R/W). + /// + UINT32 ApicBase:20; + /// + /// [Bits 63:32] APIC Base (R/W). + /// + UINT32 ApicBaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_APIC_BASE_REGISTER; + + +/** + Control Features in Intel 64 Processor (R/W). If any one enumeration + condition for defined bit field holds. + + @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_IA32_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. +**/ +#define MSR_IA32_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from + /// being written, writes to this bit will result in GP(0). Note: Once the + /// Lock bit is set, the contents of this register cannot be modified. + /// Therefore the lock bit must be set after configuring support for Intel + /// Virtualization Technology and prior to transferring control to an + /// option ROM or the OS. Hence, once the Lock bit is set, the entire + /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD + /// is not deasserted. If any one enumeration condition for defined bit + /// field position greater than bit 0 holds. + /// + UINT32 Lock:1; + /// + /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a + /// system executive to use VMX in conjunction with SMX to support + /// Intel(R) Trusted Execution Technology. BIOS must set this bit only + /// when the CPUID function 1 returns VMX feature flag and SMX feature + /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 EnableVmxInsideSmx:1; + /// + /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX + /// for system executive that do not require SMX. BIOS must set this bit + /// only when the CPUID function 1 returns VMX feature flag set (ECX bit + /// 5). If CPUID.01H:ECX[5] = 1. + /// + UINT32 EnableVmxOutsideSmx:1; + UINT32 Reserved1:5; + /// + /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit + /// in the field represents an enable control for a corresponding SENTER + /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If + /// CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterLocalFunctionEnables:7; + /// + /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable + /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit + /// 6] is set. If CPUID.01H:ECX[6] = 1. + /// + UINT32 SenterGlobalEnable:1; + UINT32 Reserved2:1; + /// + /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to + /// enable runtime reconfiguration of SGX Launch Control via + /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1. + /// + UINT32 SgxLaunchControlEnable:1; + /// + /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX + /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1. + /// + UINT32 SgxEnable:1; + UINT32 Reserved3:1; + /// + /// [Bit 20] LMCE On (R/WL): When set, system software can program the + /// MSRs associated with LMCE to configure delivery of some machine check + /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1. + /// + UINT32 LmceOn:1; + UINT32 Reserved4:11; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FEATURE_CONTROL_REGISTER; + + +/** + Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H, + ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for + a logical processor. Reset value is Zero. A write to IA32_TSC will modify + the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does + not affect the internal invariant TSC hardware. + + @param ECX MSR_IA32_TSC_ADJUST (0x0000003B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST); + AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr); + @endcode + @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM. +**/ +#define MSR_IA32_TSC_ADJUST 0x0000003B + + +/** + BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a + microcode update to be loaded into the processor. See Section 9.11.6, + "Microcode Update Loader." A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr); + @endcode + @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM. +**/ +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 + + +/** + BIOS Update Signature (RO) Returns the microcode update signature following + the execution of CPUID.01H. A processor may prevent writing to this MSR when + loading guest states on VM entries or saving guest states on VM exits. + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER. + + Example usage + @code + MSR_IA32_BIOS_SIGN_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID); + @endcode + @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM. +**/ +#define MSR_IA32_BIOS_SIGN_ID 0x0000008B + +/** + MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:32; + /// + /// [Bits 63:32] Microcode update signature. This field contains the + /// signature of the currently loaded microcode update when read following + /// the execution of the CPUID instruction, function 1. It is required + /// that this register field be pre-loaded with zero prior to executing + /// the CPUID, function 1. If the field remains equal to zero, then there + /// is no microcode update loaded. Another nonzero value will be the + /// signature. + /// + UINT32 MicrocodeUpdateSignature:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_BIOS_SIGN_ID_REGISTER; + + +/** + IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the + SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the + default value is the digest of Intel's signing key. Read permitted If + CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H): + EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1. + + @param ECX MSR_IA32_SGXLEPUBKEYHASHn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn); + AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr); + @endcode + @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM. + MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM. + MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM. + MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM. + @{ +**/ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F +/// @} + + +/** + SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] = + 1. + + @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER. + + Example usage + @code + MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL); + AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM. +**/ +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B + +/** + MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this + /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment + /// (see Section 34.15.6), the dual-monitor treatment cannot be activated + /// if the bit is 0. This bit is cleared when the logical processor is + /// reset. + /// + UINT32 Valid:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If + /// IA32_VMX_MISC[28]. + /// + UINT32 BlockSmi:1; + UINT32 Reserved2:9; + /// + /// [Bits 31:12] MSEG Base (R/W). + /// + UINT32 MsegBase:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMM_MONITOR_CTL_REGISTER; + +/** + MSEG header that is located at the physical address specified by the MsegBase + field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. +**/ +typedef struct { + /// + /// Different processors may use different MSEG revision identifiers. These + /// identifiers enable software to avoid using an MSEG header formatted for + /// one processor on a processor that uses a different format. Software can + /// discover the MSEG revision identifier that a processor uses by reading + /// the VMX capability MSR IA32_VMX_MISC. + // + UINT32 MsegHeaderRevision; + /// + /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field + /// is the IA-32e mode SMM feature bit. It indicates whether the logical + /// processor will be in IA-32e mode after the STM is activated. + /// + UINT32 MonitorFeatures; + UINT32 GdtrLimit; + UINT32 GdtrBaseOffset; + UINT32 CsSelector; + UINT32 EipOffset; + UINT32 EspOffset; + UINT32 Cr3Offset; + /// + /// Pad header so total size is 2KB + /// + UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; +} MSEG_HEADER; + +/// +/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER +/// +#define STM_FEATURES_IA32E 0x1 +/// +/// @} +/// + +/** + Base address of the logical processor's SMRAM image (RO, SMM only). If + IA32_VMX_MISC[15]. + + @param ECX MSR_IA32_SMBASE (0x0000009E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SMBASE); + @endcode + @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM. +**/ +#define MSR_IA32_SMBASE 0x0000009E + + +/** + General Performance Counters (R/W). + MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PMCn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PMC0); + AsmWriteMsr64 (MSR_IA32_PMC0, Msr); + @endcode + @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM. + MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM. + MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM. + MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM. + MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM. + MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM. + MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM. + MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM. + @{ +**/ +#define MSR_IA32_PMC0 0x000000C1 +#define MSR_IA32_PMC1 0x000000C2 +#define MSR_IA32_PMC2 0x000000C3 +#define MSR_IA32_PMC3 0x000000C4 +#define MSR_IA32_PMC4 0x000000C5 +#define MSR_IA32_PMC5 0x000000C6 +#define MSR_IA32_PMC6 0x000000C7 +#define MSR_IA32_PMC7 0x000000C8 +/// @} + + +/** + TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1. + C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative + to TSC freq.) when the logical processor is in C0. Cleared upon overflow / + wrap-around of IA32_APERF. + + @param ECX MSR_IA32_MPERF (0x000000E7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MPERF); + AsmWriteMsr64 (MSR_IA32_MPERF, Msr); + @endcode + @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM. +**/ +#define MSR_IA32_MPERF 0x000000E7 + + +/** + Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = + 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at + the coordinated clock frequency, when the logical processor is in C0. + Cleared upon overflow / wrap-around of IA32_MPERF. + + @param ECX MSR_IA32_APERF (0x000000E8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_APERF); + AsmWriteMsr64 (MSR_IA32_APERF, Msr); + @endcode + @note MSR_IA32_APERF is defined as IA32_APERF in SDM. +**/ +#define MSR_IA32_APERF 0x000000E8 + + +/** + MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.". + Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_MTRRCAP (0x000000FE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRRCAP_REGISTER. + + Example usage + @code + MSR_IA32_MTRRCAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP); + @endcode + @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM. +**/ +#define MSR_IA32_MTRRCAP 0x000000FE + +/** + MSR information returned for MSR index #MSR_IA32_MTRRCAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] VCNT: The number of variable memory type ranges in the + /// processor. + /// + UINT32 VCNT:8; + /// + /// [Bit 8] Fixed range MTRRs are supported when set. + /// + UINT32 FIX:1; + UINT32 Reserved1:1; + /// + /// [Bit 10] WC Supported when set. + /// + UINT32 WC:1; + /// + /// [Bit 11] SMRR Supported when set. + /// + UINT32 SMRR:1; + UINT32 Reserved2:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRRCAP_REGISTER; + + +/** + SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_CS (0x00000174) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SYSENTER_CS_REGISTER. + + Example usage + @code + MSR_IA32_SYSENTER_CS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS); + AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64); + @endcode + @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM. +**/ +#define MSR_IA32_SYSENTER_CS 0x00000174 + +/** + MSR information returned for MSR index #MSR_IA32_SYSENTER_CS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] CS Selector. + /// + UINT32 CS:16; + UINT32 Reserved1:16; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SYSENTER_CS_REGISTER; + + +/** + SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_ESP (0x00000175) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr); + @endcode + @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM. +**/ +#define MSR_IA32_SYSENTER_ESP 0x00000175 + + +/** + SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H. + + @param ECX MSR_IA32_SYSENTER_EIP (0x00000176) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP); + AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr); + @endcode + @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM. +**/ +#define MSR_IA32_SYSENTER_EIP 0x00000176 + + +/** + Global Machine Check Capability (RO). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); + @endcode + @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. +**/ +#define MSR_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count: Number of reporting banks. + /// + UINT32 Count:8; + /// + /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set. + /// + UINT32 MCG_CTL_P:1; + /// + /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present + /// if this bit is set. + /// + UINT32 MCG_EXT_P:1; + /// + /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. + /// Introduced at Display Family / Display Model 06_01H. + /// + UINT32 MCP_CMCI_P:1; + /// + /// [Bit 11] MCG_TES_P: Threshold-based error status register are present + /// if this bit is set. + /// + UINT32 MCG_TES_P:1; + UINT32 Reserved1:4; + /// + /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state + /// registers present. + /// + UINT32 MCG_EXT_CNT:8; + /// + /// [Bit 24] MCG_SER_P: The processor supports software error recovery if + /// this bit is set. + /// + UINT32 MCG_SER_P:1; + UINT32 Reserved2:1; + /// + /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform + /// firmware to be invoked when an error is detected so that it may + /// provide additional platform specific information in an ACPI format + /// "Generic Error Data Entry" that augments the data included in machine + /// check bank registers. Introduced at Display Family / Display Model + /// 06_3EH. + /// + UINT32 MCG_ELOG_P:1; + /// + /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended + /// state in IA32_MCG_STATUS and associated MSR necessary to configure + /// Local Machine Check Exception (LMCE). Introduced at Display Family / + /// Display Model 06_3EH. + /// + UINT32 MCG_LMCE_P:1; + UINT32 Reserved3:4; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_CAP_REGISTER; + + +/** + Global Machine Check Status (R/W0). Introduced at Display Family / Display + Model 06_01H. + + @param ECX MSR_IA32_MCG_STATUS (0x0000017A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_MCG_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); + AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64); + @endcode + @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM. +**/ +#define MSR_IA32_MCG_STATUS 0x0000017A + +/** + MSR information returned for MSR index #MSR_IA32_MCG_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 RIPV:1; + /// + /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display + /// Model 06_01H. + /// + UINT32 EIPV:1; + /// + /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family + /// / Display Model 06_01H. + /// + UINT32 MCIP:1; + /// + /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1. + /// + UINT32 LMCE_S:1; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_STATUS_REGISTER; + + +/** + Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1. + + @param ECX MSR_IA32_MCG_CTL (0x0000017B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL); + AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr); + @endcode + @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM. +**/ +#define MSR_IA32_MCG_CTL 0x0000017B + + +/** + Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n. + + @param ECX MSR_IA32_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERFEVTSEL_REGISTER. + + Example usage + @code + MSR_IA32_PERFEVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0); + AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64); + @endcode + @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. + MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. + MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. + MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_IA32_PERFEVTSEL0 0x00000186 +#define MSR_IA32_PERFEVTSEL1 0x00000187 +#define MSR_IA32_PERFEVTSEL2 0x00000188 +#define MSR_IA32_PERFEVTSEL3 0x00000189 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to + #MSR_IA32_PERFEVTSEL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select: Selects a performance event logic unit. + /// + UINT32 EventSelect:8; + /// + /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to + /// detect on the selected event logic. + /// + UINT32 UMASK:8; + /// + /// [Bit 16] USR: Counts while in privilege level is not ring 0. + /// + UINT32 USR:1; + /// + /// [Bit 17] OS: Counts while in privilege level is ring 0. + /// + UINT32 OS:1; + /// + /// [Bit 18] Edge: Enables edge detection if set. + /// + UINT32 E:1; + /// + /// [Bit 19] PC: enables pin control. + /// + UINT32 PC:1; + /// + /// [Bit 20] INT: enables interrupt on counter overflow. + /// + UINT32 INT:1; + /// + /// [Bit 21] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. + /// + UINT32 ANY:1; + /// + /// [Bit 22] EN: enables the corresponding performance counter to commence + /// counting when this bit is set. + /// + UINT32 EN:1; + /// + /// [Bit 23] INV: invert the CMASK. + /// + UINT32 INV:1; + /// + /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding + /// performance counter increments each cycle if the event count is + /// greater than or equal to the CMASK. + /// + UINT32 CMASK:8; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERFEVTSEL_REGISTER; + + +/** + Current performance state(P-State) operating point (RO). Introduced at + Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS); + @endcode + @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM. +**/ +#define MSR_IA32_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Current performance State Value. + /// + UINT32 State:16; + UINT32 Reserved1:16; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_STATUS_REGISTER; + + +/** + (R/W). Introduced at Display Family / Display Model 0F_03H. + + @param ECX MSR_IA32_PERF_CTL (0x00000199) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CTL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL); + AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM. +**/ +#define MSR_IA32_PERF_CTL 0x00000199 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Target performance State Value. + /// + UINT32 TargetState:16; + UINT32 Reserved1:16; + /// + /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH + /// (Mobile only). + /// + UINT32 IDA:1; + UINT32 Reserved2:31; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CTL_REGISTER; + + +/** + Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled + Clock Modulation.". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER. + + Example usage + @code + MSR_IA32_CLOCK_MODULATION_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); + AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64); + @endcode + @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. +**/ +#define MSR_IA32_CLOCK_MODULATION 0x0000019A + +/** + MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If + /// CPUID.06H:EAX[5] = 1. + /// + UINT32 ExtendedOnDemandClockModulationDutyCycle:1; + /// + /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded + /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationDutyCycle:3; + /// + /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 OnDemandClockModulationEnable:1; + UINT32 Reserved1:27; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_CLOCK_MODULATION_REGISTER; + + +/** + Thermal Interrupt Control (R/W) Enables and disables the generation of an + interrupt on temperature transitions detected with the processor's thermal + sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.". + If CPUID.01H:EDX[22] = 1 + + @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_THERM_INTERRUPT 0x0000019B + +/** + MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 HighTempEnable:1; + /// + /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 LowTempEnable:1; + /// + /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_Enable:1; + /// + /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 FORCEPR_Enable:1; + /// + /// [Bit 4] Critical Temperature Interrupt Enable. + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempEnable:1; + UINT32 Reserved1:3; + /// + /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1:7; + /// + /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold1Enable:1; + /// + /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2:7; + /// + /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1. + /// + UINT32 Threshold2Enable:1; + /// + /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitNotificationEnable:1; + UINT32 Reserved2:7; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_INTERRUPT_REGISTER; + + +/** + Thermal Status Information (RO) Contains status information about the + processor's thermal sensor and automatic thermal monitoring facilities. See + Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1. + + @param ECX MSR_IA32_THERM_STATUS (0x0000019C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS); + @endcode + @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM. +**/ +#define MSR_IA32_THERM_STATUS 0x0000019C + +/** + MSR information returned for MSR index #MSR_IA32_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatus:1; + /// + /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1. + /// + UINT32 ThermalStatusLog:1; + /// + /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Event:1; + /// + /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1. + /// + UINT32 PROCHOT_FORCEPR_Log:1; + /// + /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatus:1; + /// + /// [Bit 5] Critical Temperature Status log (R/WC0). + /// If CPUID.01H:EDX[22] = 1. + /// + UINT32 CriticalTempStatusLog:1; + /// + /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Status:1; + /// + /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold1Log:1; + /// + /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Status:1; + /// + /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1. + /// + UINT32 ThermalThreshold2Log:1; + /// + /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitStatus:1; + /// + /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1. + /// + UINT32 PowerLimitLog:1; + /// + /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitStatus:1; + /// + /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CurrentLimitLog:1; + /// + /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitStatus:1; + /// + /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1. + /// + UINT32 CrossDomainLimitLog:1; + /// + /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 DigitalReadout:7; + UINT32 Reserved1:4; + /// + /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = + /// 1. + /// + UINT32 ResolutionInDegreesCelsius:4; + /// + /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1. + /// + UINT32 ReadingValid:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_THERM_STATUS_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for + /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings + /// are disabled. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting + /// this bit enables the thermal control circuit (TCC) portion of the + /// Intel Thermal Monitor feature. This allows the processor to + /// automatically reduce power consumption in response to TCC activation. + /// 0 = Disabled. Note: In some products clearing this bit might be + /// ignored in critical thermal conditions, and TM1, TM2 and adaptive + /// thermal throttling will still be activated. The default value of this + /// field varies with product. See respective tables where default value is + /// listed. Introduced at Display Family / Display Model 0F_0H. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Performance Monitoring Available (R) 1 = Performance + /// monitoring enabled 0 = Performance monitoring disabled. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:3; + /// + /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't + /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at + /// Display Family / Display Model 0F_0H. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = + /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display + /// Family / Display Model 06_0FH. + /// + UINT32 PEBS:1; + UINT32 Reserved4:3; + /// + /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced + /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep + /// Technology enabled. If CPUID.01H: ECX[7] =1. + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the + /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This + /// indicates that MONITOR/MWAIT are not supported. Software attempts to + /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit + /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit + /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit + /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it + /// in the default state. Writing this bit when the SSE3 feature flag is + /// set to 0 may generate a #GP exception. Introduced at Display Family / + /// Display Model 0F_03H. + /// + UINT32 MONITOR:1; + UINT32 Reserved6:3; + /// + /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H + /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup + /// question that allows users to specify when the installed OS does not + /// support CPUID functions greater than 2. Before setting this bit, BIOS + /// must execute the CPUID.0H and examine the maximum value returned in + /// EAX[7:0]. If the maximum value is greater than 2, this bit is + /// supported. Otherwise, this bit is not supported. Setting this bit when + /// the maximum value is not greater than 2 may generate a #GP exception. + /// Setting this bit may cause unexpected behavior in software that + /// depends on the availability of CPUID leaves greater than 2. Introduced + /// at Display Family / Display Model 0F_03H. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are + /// disabled. xTPR messages are optional messages that allow the processor + /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit + /// feature (XD Bit) is disabled and the XD Bit extended feature flag will + /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the + /// Execute Disable Bit feature (if available) allows the OS to enable PAE + /// paging and take advantage of data only pages. BIOS must not alter the + /// contents of this bit location, if XD bit is not supported. Writing + /// this bit to 1 when the XD Bit extended feature flag is set to 0 may + /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1. + /// + UINT32 XD:1; + UINT32 Reserved9:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MISC_ENABLE_REGISTER; + + +/** + Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1. + + @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER. + + Example usage + @code + MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS); + AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64); + @endcode + @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. +**/ +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0 + +/** + MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest + /// performance. 15 indicates preference to maximize energy saving. + /// + UINT32 PowerPolicyPreference:4; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_ENERGY_PERF_BIAS_REGISTER; + + +/** + Package Thermal Status Information (RO) Contains status information about + the package's thermal sensor. See Section 14.8, "Package Level Thermal + Management.". If CPUID.06H: EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS); + @endcode + @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg Thermal Status (RO):. + /// + UINT32 ThermalStatus:1; + /// + /// [Bit 1] Pkg Thermal Status Log (R/W):. + /// + UINT32 ThermalStatusLog:1; + /// + /// [Bit 2] Pkg PROCHOT # event (RO). + /// + UINT32 PROCHOT_Event:1; + /// + /// [Bit 3] Pkg PROCHOT # log (R/WC0). + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 4] Pkg Critical Temperature Status (RO). + /// + UINT32 CriticalTempStatus:1; + /// + /// [Bit 5] Pkg Critical Temperature Status log (R/WC0). + /// + UINT32 CriticalTempStatusLog:1; + /// + /// [Bit 6] Pkg Thermal Threshold #1 Status (RO). + /// + UINT32 ThermalThreshold1Status:1; + /// + /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold1Log:1; + /// + /// [Bit 8] Pkg Thermal Threshold #2 Status (RO). + /// + UINT32 ThermalThreshold2Status:1; + /// + /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0). + /// + UINT32 ThermalThreshold2Log:1; + /// + /// [Bit 10] Pkg Power Limitation Status (RO). + /// + UINT32 PowerLimitStatus:1; + /// + /// [Bit 11] Pkg Power Limitation log (R/WC0). + /// + UINT32 PowerLimitLog:1; + UINT32 Reserved1:4; + /// + /// [Bits 22:16] Pkg Digital Readout (RO). + /// + UINT32 DigitalReadout:7; + UINT32 Reserved2:9; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER; + + +/** + Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of + an interrupt on temperature transitions detected with the package's thermal + sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H: + EAX[6] = 1. + + @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM. +**/ +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2 + +/** + MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Pkg High-Temperature Interrupt Enable. + /// + UINT32 HighTempEnable:1; + /// + /// [Bit 1] Pkg Low-Temperature Interrupt Enable. + /// + UINT32 LowTempEnable:1; + /// + /// [Bit 2] Pkg PROCHOT# Interrupt Enable. + /// + UINT32 PROCHOT_Enable:1; + UINT32 Reserved1:1; + /// + /// [Bit 4] Pkg Overheat Interrupt Enable. + /// + UINT32 OverheatEnable:1; + UINT32 Reserved2:3; + /// + /// [Bits 14:8] Pkg Threshold #1 Value. + /// + UINT32 Threshold1:7; + /// + /// [Bit 15] Pkg Threshold #1 Interrupt Enable. + /// + UINT32 Threshold1Enable:1; + /// + /// [Bits 22:16] Pkg Threshold #2 Value. + /// + UINT32 Threshold2:7; + /// + /// [Bit 23] Pkg Threshold #2 Interrupt Enable. + /// + UINT32 Threshold2Enable:1; + /// + /// [Bit 24] Pkg Power Limit Notification Enable. + /// + UINT32 PowerLimitNotificationEnable:1; + UINT32 Reserved3:7; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER; + + +/** + Trace/Profile Resource Control (R/W). Introduced at Display Family / Display + Model 06_0EH. + + @param ECX MSR_IA32_DEBUGCTL (0x000001D9) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DEBUGCTL_REGISTER. + + Example usage + @code + MSR_IA32_DEBUGCTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL); + AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64); + @endcode + @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM. +**/ +#define MSR_IA32_DEBUGCTL 0x000001D9 + +/** + MSR information returned for MSR index #MSR_IA32_DEBUGCTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a + /// running trace of the most recent branches taken by the processor in + /// the LBR stack. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 LBR:1; + /// + /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat + /// EFLAGS.TF as single-step on branches instead of single-step on + /// instructions. Introduced at Display Family / Display Model 06_01H. + /// + UINT32 BTF:1; + UINT32 Reserved1:4; + /// + /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be + /// sent. Introduced at Display Family / Display Model 06_0EH. + /// + UINT32 TR:1; + /// + /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to + /// be logged in a BTS buffer. Introduced at Display Family / Display + /// Model 06_0EH. + /// + UINT32 BTS:1; + /// + /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular + /// fashion. When this bit is set, an interrupt is generated by the BTS + /// facility when the BTS buffer is full. Introduced at Display Family / + /// Display Model 06_0EH. + /// + UINT32 BTINT:1; + /// + /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_OS:1; + /// + /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. + /// Introduced at Display Family / Display Model 06_0FH. + /// + UINT32 BTS_OFF_USR:1; + /// + /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a + /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_LBRS_ON_PMI:1; + /// + /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the + /// global counter control MSR are frozen (address 38FH) on a PMI request. + /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 FREEZE_PERFMON_ON_PMI:1; + /// + /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to + /// receive and generate PMI on behalf of the uncore. Introduced at + /// Display Family / Display Model 06_1AH. + /// + UINT32 ENABLE_UNCORE_PMI:1; + /// + /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace + /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1. + /// + UINT32 FREEZE_WHILE_SMM:1; + /// + /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If + /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1). + /// + UINT32 RTM_DEBUG:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DEBUGCTL_REGISTER; + + +/** + SMRR Base Address (Writeable only in SMM) Base address of SMM memory range. + If IA32_MTRRCAP.SMRR[11] = 1. + + @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM. +**/ +#define MSR_IA32_SMRR_PHYSBASE 0x000001F2 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type:8; + UINT32 Reserved1:4; + /// + /// [Bits 31:12] PhysBase. SMRR physical Base Address. + /// + UINT32 PhysBase:20; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSBASE_REGISTER; + + +/** + SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If + IA32_MTRRCAP[SMRR] = 1. + + @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_SMRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK); + AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64); + @endcode + @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM. +**/ +#define MSR_IA32_SMRR_PHYSMASK 0x000001F3 + +/** + MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 Valid:1; + /// + /// [Bits 31:12] PhysMask SMRR address range mask. + /// + UINT32 PhysMask:20; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SMRR_PHYSMASK_REGISTER; + + +/** + DCA Capability (R). If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP); + @endcode + @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM. +**/ +#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8 + + +/** + If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP); + AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr); + @endcode + @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM. +**/ +#define MSR_IA32_CPU_DCA_CAP 0x000001F9 + + +/** + DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1. + + @param ECX MSR_IA32_DCA_0_CAP (0x000001FA) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DCA_0_CAP_REGISTER. + + Example usage + @code + MSR_IA32_DCA_0_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP); + AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64); + @endcode + @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM. +**/ +#define MSR_IA32_DCA_0_CAP 0x000001FA + +/** + MSR information returned for MSR index #MSR_IA32_DCA_0_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no + /// defeatures are set. + /// + UINT32 DCA_ACTIVE:1; + /// + /// [Bits 2:1] TRANSACTION. + /// + UINT32 TRANSACTION:2; + /// + /// [Bits 6:3] DCA_TYPE. + /// + UINT32 DCA_TYPE:4; + /// + /// [Bits 10:7] DCA_QUEUE_SIZE. + /// + UINT32 DCA_QUEUE_SIZE:4; + UINT32 Reserved1:2; + /// + /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW + /// side-effect. + /// + UINT32 DCA_DELAY:4; + UINT32 Reserved2:7; + /// + /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit. + /// + UINT32 SW_BLOCK:1; + UINT32 Reserved3:1; + /// + /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1). + /// + UINT32 HW_BLOCK:1; + UINT32 Reserved4:5; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DCA_0_CAP_REGISTER; + + +/** + MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSBASEn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM. + MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM. + MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM. + MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM. + MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM. + MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM. + MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM. + MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM. + MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM. + MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSBASE0 0x00000200 +#define MSR_IA32_MTRR_PHYSBASE1 0x00000202 +#define MSR_IA32_MTRR_PHYSBASE2 0x00000204 +#define MSR_IA32_MTRR_PHYSBASE3 0x00000206 +#define MSR_IA32_MTRR_PHYSBASE4 0x00000208 +#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A +#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C +#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E +#define MSR_IA32_MTRR_PHYSBASE8 0x00000210 +#define MSR_IA32_MTRR_PHYSBASE9 0x00000212 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to + #MSR_IA32_MTRR_PHYSBASE9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Type. Specifies memory type of the range. + /// + UINT32 Type:8; + UINT32 Reserved1:4; + /// + /// [Bits 31:12] PhysBase. MTRR physical Base Address. + /// + UINT32 PhysBase:20; + /// + /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysBaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSBASE_REGISTER; + + +/** + MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs". + If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n. + + @param ECX MSR_IA32_MTRR_PHYSMASKn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0); + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM. + MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM. + MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM. + MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM. + MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM. + MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM. + MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM. + MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM. + MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM. + MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM. + @{ +**/ +#define MSR_IA32_MTRR_PHYSMASK0 0x00000201 +#define MSR_IA32_MTRR_PHYSMASK1 0x00000203 +#define MSR_IA32_MTRR_PHYSMASK2 0x00000205 +#define MSR_IA32_MTRR_PHYSMASK3 0x00000207 +#define MSR_IA32_MTRR_PHYSMASK4 0x00000209 +#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B +#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D +#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F +#define MSR_IA32_MTRR_PHYSMASK8 0x00000211 +#define MSR_IA32_MTRR_PHYSMASK9 0x00000213 +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to + #MSR_IA32_MTRR_PHYSMASK9 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:11; + /// + /// [Bit 11] Valid Enable range mask. + /// + UINT32 V:1; + /// + /// [Bits 31:12] PhysMask. MTRR address range mask. + /// + UINT32 PhysMask:20; + /// + /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. + /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the + /// maximum physical address range supported by the processor. It is + /// reported by CPUID leaf function 80000008H. If CPUID does not support + /// leaf 80000008H, the processor supports 36-bit physical address size, + /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved. + /// + UINT32 PhysMaskHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_PHYSMASK_REGISTER; + + +/** + MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX64K_00000 0x00000250 + + +/** + MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_80000 0x00000258 + + +/** + MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259 + + +/** + See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268 + + +/** + MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269 + + +/** + MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A + + +/** + MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B + + +/** + MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C + + +/** + MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D + + +/** + MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E + + +/** + MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000); + AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr); + @endcode + @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM. +**/ +#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F + + +/** + IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1. + + @param ECX MSR_IA32_PAT (0x00000277) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PAT_REGISTER. + + Example usage + @code + MSR_IA32_PAT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT); + AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64); + @endcode + @note MSR_IA32_PAT is defined as IA32_PAT in SDM. +**/ +#define MSR_IA32_PAT 0x00000277 + +/** + MSR information returned for MSR index #MSR_IA32_PAT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] PA0. + /// + UINT32 PA0:3; + UINT32 Reserved1:5; + /// + /// [Bits 10:8] PA1. + /// + UINT32 PA1:3; + UINT32 Reserved2:5; + /// + /// [Bits 18:16] PA2. + /// + UINT32 PA2:3; + UINT32 Reserved3:5; + /// + /// [Bits 26:24] PA3. + /// + UINT32 PA3:3; + UINT32 Reserved4:5; + /// + /// [Bits 34:32] PA4. + /// + UINT32 PA4:3; + UINT32 Reserved5:5; + /// + /// [Bits 42:40] PA5. + /// + UINT32 PA5:3; + UINT32 Reserved6:5; + /// + /// [Bits 50:48] PA6. + /// + UINT32 PA6:3; + UINT32 Reserved7:5; + /// + /// [Bits 58:56] PA7. + /// + UINT32 PA7:3; + UINT32 Reserved8:5; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PAT_REGISTER; + + +/** + Provides the programming interface to use corrected MC error signaling + capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n. + + @param ECX MSR_IA32_MCn_CTL2 + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MC_CTL2_REGISTER. + + Example usage + @code + MSR_IA32_MC_CTL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2); + AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64); + @endcode + @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM. + MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM. + MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM. + MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM. + MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. + MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM. + MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM. + MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM. + MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM. + MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM. + MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM. + MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM. + MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM. + MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM. + MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM. + MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM. + MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM. + MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM. + MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM. + MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM. + MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM. + MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM. + MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM. + MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM. + MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM. + MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM. + MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM. + MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM. + MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM. + MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM. + MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM. + MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL2 0x00000280 +#define MSR_IA32_MC1_CTL2 0x00000281 +#define MSR_IA32_MC2_CTL2 0x00000282 +#define MSR_IA32_MC3_CTL2 0x00000283 +#define MSR_IA32_MC4_CTL2 0x00000284 +#define MSR_IA32_MC5_CTL2 0x00000285 +#define MSR_IA32_MC6_CTL2 0x00000286 +#define MSR_IA32_MC7_CTL2 0x00000287 +#define MSR_IA32_MC8_CTL2 0x00000288 +#define MSR_IA32_MC9_CTL2 0x00000289 +#define MSR_IA32_MC10_CTL2 0x0000028A +#define MSR_IA32_MC11_CTL2 0x0000028B +#define MSR_IA32_MC12_CTL2 0x0000028C +#define MSR_IA32_MC13_CTL2 0x0000028D +#define MSR_IA32_MC14_CTL2 0x0000028E +#define MSR_IA32_MC15_CTL2 0x0000028F +#define MSR_IA32_MC16_CTL2 0x00000290 +#define MSR_IA32_MC17_CTL2 0x00000291 +#define MSR_IA32_MC18_CTL2 0x00000292 +#define MSR_IA32_MC19_CTL2 0x00000293 +#define MSR_IA32_MC20_CTL2 0x00000294 +#define MSR_IA32_MC21_CTL2 0x00000295 +#define MSR_IA32_MC22_CTL2 0x00000296 +#define MSR_IA32_MC23_CTL2 0x00000297 +#define MSR_IA32_MC24_CTL2 0x00000298 +#define MSR_IA32_MC25_CTL2 0x00000299 +#define MSR_IA32_MC26_CTL2 0x0000029A +#define MSR_IA32_MC27_CTL2 0x0000029B +#define MSR_IA32_MC28_CTL2 0x0000029C +#define MSR_IA32_MC29_CTL2 0x0000029D +#define MSR_IA32_MC30_CTL2 0x0000029E +#define MSR_IA32_MC31_CTL2 0x0000029F +/// @} + +/** + MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 + to #MSR_IA32_MC31_CTL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Corrected error count threshold. + /// + UINT32 CorrectedErrorCountThreshold:15; + UINT32 Reserved1:15; + /// + /// [Bit 30] CMCI_EN. + /// + UINT32 CMCI_EN:1; + UINT32 Reserved2:1; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MC_CTL2_REGISTER; + + +/** + MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1. + + @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER. + + Example usage + @code + MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64); + @endcode + @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM. +**/ +#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF + +/** + MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Default Memory Type. + /// + UINT32 Type:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] Fixed Range MTRR Enable. + /// + UINT32 FE:1; + /// + /// [Bit 11] MTRR Enable. + /// + UINT32 E:1; + UINT32 Reserved2:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MTRR_DEF_TYPE_REGISTER; + + +/** + Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If + CPUID.0AH: EDX[4:0] > 0. + + @param ECX MSR_IA32_FIXED_CTR0 (0x00000309) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr); + @endcode + @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM. +**/ +#define MSR_IA32_FIXED_CTR0 0x00000309 + + +/** + Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If + CPUID.0AH: EDX[4:0] > 1. + + @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr); + @endcode + @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM. +**/ +#define MSR_IA32_FIXED_CTR1 0x0000030A + + +/** + Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If + CPUID.0AH: EDX[4:0] > 2. + + @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr); + @endcode + @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM. +**/ +#define MSR_IA32_FIXED_CTR2 0x0000030B + + +/** + RO. If CPUID.01H: ECX[15] = 1. + + @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER. + + Example usage + @code + MSR_IA32_PERF_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES); + AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM. +**/ +#define MSR_IA32_PERF_CAPABILITIES 0x00000345 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 5:0] LBR format. + /// + UINT32 LBR_FMT:6; + /// + /// [Bit 6] PEBS Trap. + /// + UINT32 PEBS_TRAP:1; + /// + /// [Bit 7] PEBSSaveArchRegs. + /// + UINT32 PEBS_ARCH_REG:1; + /// + /// [Bits 11:8] PEBS Record Format. + /// + UINT32 PEBS_REC_FMT:4; + /// + /// [Bit 12] 1: Freeze while SMM is supported. + /// + UINT32 SMM_FREEZE:1; + /// + /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx. + /// + UINT32 FW_WRITE:1; + UINT32 Reserved1:18; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_CAPABILITIES_REGISTER; + + +/** + Fixed-Function Performance Counter Control (R/W) Counter increments while + the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with + the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0] + > 1. + + @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL); + AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM. +**/ +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D + +/** + MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0. + /// + UINT32 EN0_OS:1; + /// + /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0. + /// + UINT32 EN0_Usr:1; + /// + /// [Bit 2] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread0:1; + /// + /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows. + /// + UINT32 EN0_PMI:1; + /// + /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0. + /// + UINT32 EN1_OS:1; + /// + /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0. + /// + UINT32 EN1_Usr:1; + /// + /// [Bit 6] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread1:1; + /// + /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows. + /// + UINT32 EN1_PMI:1; + /// + /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0. + /// + UINT32 EN2_OS:1; + /// + /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0. + /// + UINT32 EN2_Usr:1; + /// + /// [Bit 10] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2. + /// + UINT32 AnyThread2:1; + /// + /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows. + /// + UINT32 EN2_PMI:1; + UINT32 Reserved1:20; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_FIXED_CTR_CTRL_REGISTER; + + +/** + Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: + /// EAX[15:8] > 0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: + /// EAX[15:8] > 1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: + /// EAX[15:8] > 2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: + /// EAX[15:8] > 3. + /// + UINT32 Ovf_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If + /// CPUID.0AH: EAX[7:0] > 1. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory + /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) + /// && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] LBR_Frz: LBRs are frozen due to - + /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If + /// CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due + /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU + /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] ASCI: Data in the performance counters in the core PMU may + /// include contributions from the direct or indirect operation intel SGX + /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: + /// EAX[7:0] > 2. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: + /// EAX[7:0] > 0. + /// + UINT32 OvfBuf:1; + /// + /// [Bit 63] CondChgd: status bits of this register has changed. If + /// CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Global Performance Counter Control (R/W) Counter increments while the result + of ANDing respective enable bit in this MSR with the corresponding OS or USR + bits in the general-purpose or fixed counter control MSR is true. If + CPUID.0AH: EAX[7:0] > 0. + + @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields +/// + struct { + /// + /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits n..31 are reserved. + /// + UINT32 EN_PMCn:32; + /// + /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. + /// Enable bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 EN_FIXED_CTRn:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER; + + +/** + Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] > + 0 && CPUID.0AH: EAX[7:0] <= 3. + + @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn:32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn:23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved2:5; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf:1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; + + +/** + Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn:32; + /// + /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. + /// If CPUID.0AH: EDX[4:0] > n. + /// Clear bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn:23; + /// + /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, + /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved2:2; + /// + /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / + /// Display Model 06_2EH. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 OvfBuf:1; + /// + /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; + + +/** + Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH: + EAX[7:0] > 3. + + @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET); + AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); + @endcode + @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 Ovf_PMCn:32; + /// + /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. + /// If CPUID.0AH: EAX[7:0] > n. + /// Set bitmask. Only the first n-1 bits are valid. + /// Bits 22:n are reserved. + /// + UINT32 Ovf_FIXED_CTRn:23; + /// + /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved2:2; + /// + /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3. + /// + UINT32 OvfBuf:1; + UINT32 Reserved3:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; + + +/** + Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] > + 3. + + @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER. + + Example usage + @code + MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE); + @endcode + @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM. +**/ +#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392 + +/** + MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 31:n are reserved. + /// + UINT32 IA32_PERFEVTSELn:32; + /// + /// [Bits 62:32] IA32_FIXED_CTRn in use. + /// If CPUID.0AH: EAX[7:0] > n. + /// Status bitmask. Only the first n-1 bits are valid. + /// Bits 30:n are reserved. + /// + UINT32 IA32_FIXED_CTRn:31; + /// + /// [Bit 63] PMI in use. + /// + UINT32 PMI:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER; + + +/** + PEBS Control (R/W). + + @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE); + AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM. +**/ +#define MSR_IA32_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / + /// Display Model 06_0FH. + /// + UINT32 Enable:1; + /// + /// [Bits 3:1] Reserved or Model specific. + /// + UINT32 Reserved1:3; + UINT32 Reserved2:28; + /// + /// [Bits 35:32] Reserved or Model specific. + /// + UINT32 Reserved3:4; + UINT32 Reserved4:28; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PEBS_ENABLE_REGISTER; + + +/** + MCn_CTL. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_CTL + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL); + AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr); + @endcode + @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM. + MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM. + MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM. + MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM. + MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. + MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM. + MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM. + MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM. + MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM. + MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM. + MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM. + MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM. + MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM. + MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM. + MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM. + MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM. + MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM. + MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM. + MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM. + MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM. + MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM. + MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM. + MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM. + MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM. + MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM. + MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM. + MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM. + MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM. + MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM. + @{ +**/ +#define MSR_IA32_MC0_CTL 0x00000400 +#define MSR_IA32_MC1_CTL 0x00000404 +#define MSR_IA32_MC2_CTL 0x00000408 +#define MSR_IA32_MC3_CTL 0x0000040C +#define MSR_IA32_MC4_CTL 0x00000410 +#define MSR_IA32_MC5_CTL 0x00000414 +#define MSR_IA32_MC6_CTL 0x00000418 +#define MSR_IA32_MC7_CTL 0x0000041C +#define MSR_IA32_MC8_CTL 0x00000420 +#define MSR_IA32_MC9_CTL 0x00000424 +#define MSR_IA32_MC10_CTL 0x00000428 +#define MSR_IA32_MC11_CTL 0x0000042C +#define MSR_IA32_MC12_CTL 0x00000430 +#define MSR_IA32_MC13_CTL 0x00000434 +#define MSR_IA32_MC14_CTL 0x00000438 +#define MSR_IA32_MC15_CTL 0x0000043C +#define MSR_IA32_MC16_CTL 0x00000440 +#define MSR_IA32_MC17_CTL 0x00000444 +#define MSR_IA32_MC18_CTL 0x00000448 +#define MSR_IA32_MC19_CTL 0x0000044C +#define MSR_IA32_MC20_CTL 0x00000450 +#define MSR_IA32_MC21_CTL 0x00000454 +#define MSR_IA32_MC22_CTL 0x00000458 +#define MSR_IA32_MC23_CTL 0x0000045C +#define MSR_IA32_MC24_CTL 0x00000460 +#define MSR_IA32_MC25_CTL 0x00000464 +#define MSR_IA32_MC26_CTL 0x00000468 +#define MSR_IA32_MC27_CTL 0x0000046C +#define MSR_IA32_MC28_CTL 0x00000470 +/// @} + + +/** + MCn_STATUS. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_STATUS + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS); + AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr); + @endcode + @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM. + MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM. + MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM. + MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM. + MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM. + MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM. + MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM. + MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM. + MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM. + MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM. + MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM. + MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM. + MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM. + MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM. + MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM. + MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM. + MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM. + MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM. + MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM. + MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM. + MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM. + MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM. + MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM. + MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM. + MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM. + MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM. + MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM. + MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM. + MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM. + @{ +**/ +#define MSR_IA32_MC0_STATUS 0x00000401 +#define MSR_IA32_MC1_STATUS 0x00000405 +#define MSR_IA32_MC2_STATUS 0x00000409 +#define MSR_IA32_MC3_STATUS 0x0000040D +#define MSR_IA32_MC4_STATUS 0x00000411 +#define MSR_IA32_MC5_STATUS 0x00000415 +#define MSR_IA32_MC6_STATUS 0x00000419 +#define MSR_IA32_MC7_STATUS 0x0000041D +#define MSR_IA32_MC8_STATUS 0x00000421 +#define MSR_IA32_MC9_STATUS 0x00000425 +#define MSR_IA32_MC10_STATUS 0x00000429 +#define MSR_IA32_MC11_STATUS 0x0000042D +#define MSR_IA32_MC12_STATUS 0x00000431 +#define MSR_IA32_MC13_STATUS 0x00000435 +#define MSR_IA32_MC14_STATUS 0x00000439 +#define MSR_IA32_MC15_STATUS 0x0000043D +#define MSR_IA32_MC16_STATUS 0x00000441 +#define MSR_IA32_MC17_STATUS 0x00000445 +#define MSR_IA32_MC18_STATUS 0x00000449 +#define MSR_IA32_MC19_STATUS 0x0000044D +#define MSR_IA32_MC20_STATUS 0x00000451 +#define MSR_IA32_MC21_STATUS 0x00000455 +#define MSR_IA32_MC22_STATUS 0x00000459 +#define MSR_IA32_MC23_STATUS 0x0000045D +#define MSR_IA32_MC24_STATUS 0x00000461 +#define MSR_IA32_MC25_STATUS 0x00000465 +#define MSR_IA32_MC26_STATUS 0x00000469 +#define MSR_IA32_MC27_STATUS 0x0000046D +#define MSR_IA32_MC28_STATUS 0x00000471 +/// @} + + +/** + MCn_ADDR. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_ADDR + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR); + AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr); + @endcode + @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM. + MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM. + MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM. + MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM. + MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM. + MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM. + MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM. + MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM. + MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM. + MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM. + MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM. + MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM. + MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM. + MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM. + MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM. + MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM. + MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM. + MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM. + MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM. + MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM. + MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM. + MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM. + MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM. + MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM. + MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM. + MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM. + MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM. + MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM. + MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM. + @{ +**/ +#define MSR_IA32_MC0_ADDR 0x00000402 +#define MSR_IA32_MC1_ADDR 0x00000406 +#define MSR_IA32_MC2_ADDR 0x0000040A +#define MSR_IA32_MC3_ADDR 0x0000040E +#define MSR_IA32_MC4_ADDR 0x00000412 +#define MSR_IA32_MC5_ADDR 0x00000416 +#define MSR_IA32_MC6_ADDR 0x0000041A +#define MSR_IA32_MC7_ADDR 0x0000041E +#define MSR_IA32_MC8_ADDR 0x00000422 +#define MSR_IA32_MC9_ADDR 0x00000426 +#define MSR_IA32_MC10_ADDR 0x0000042A +#define MSR_IA32_MC11_ADDR 0x0000042E +#define MSR_IA32_MC12_ADDR 0x00000432 +#define MSR_IA32_MC13_ADDR 0x00000436 +#define MSR_IA32_MC14_ADDR 0x0000043A +#define MSR_IA32_MC15_ADDR 0x0000043E +#define MSR_IA32_MC16_ADDR 0x00000442 +#define MSR_IA32_MC17_ADDR 0x00000446 +#define MSR_IA32_MC18_ADDR 0x0000044A +#define MSR_IA32_MC19_ADDR 0x0000044E +#define MSR_IA32_MC20_ADDR 0x00000452 +#define MSR_IA32_MC21_ADDR 0x00000456 +#define MSR_IA32_MC22_ADDR 0x0000045A +#define MSR_IA32_MC23_ADDR 0x0000045E +#define MSR_IA32_MC24_ADDR 0x00000462 +#define MSR_IA32_MC25_ADDR 0x00000466 +#define MSR_IA32_MC26_ADDR 0x0000046A +#define MSR_IA32_MC27_ADDR 0x0000046E +#define MSR_IA32_MC28_ADDR 0x00000472 +/// @} + + +/** + MCn_MISC. If IA32_MCG_CAP.CNT > n. + + @param ECX MSR_IA32_MCn_MISC + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC); + AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr); + @endcode + @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM. + MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM. + MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM. + MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM. + MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM. + MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM. + MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. + MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM. + MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM. + MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM. + MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM. + MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM. + MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM. + MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM. + MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM. + MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM. + MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM. + MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM. + MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM. + MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM. + MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM. + MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM. + MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM. + MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM. + MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM. + MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM. + MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM. + MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM. + MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM. + @{ +**/ +#define MSR_IA32_MC0_MISC 0x00000403 +#define MSR_IA32_MC1_MISC 0x00000407 +#define MSR_IA32_MC2_MISC 0x0000040B +#define MSR_IA32_MC3_MISC 0x0000040F +#define MSR_IA32_MC4_MISC 0x00000413 +#define MSR_IA32_MC5_MISC 0x00000417 +#define MSR_IA32_MC6_MISC 0x0000041B +#define MSR_IA32_MC7_MISC 0x0000041F +#define MSR_IA32_MC8_MISC 0x00000423 +#define MSR_IA32_MC9_MISC 0x00000427 +#define MSR_IA32_MC10_MISC 0x0000042B +#define MSR_IA32_MC11_MISC 0x0000042F +#define MSR_IA32_MC12_MISC 0x00000433 +#define MSR_IA32_MC13_MISC 0x00000437 +#define MSR_IA32_MC14_MISC 0x0000043B +#define MSR_IA32_MC15_MISC 0x0000043F +#define MSR_IA32_MC16_MISC 0x00000443 +#define MSR_IA32_MC17_MISC 0x00000447 +#define MSR_IA32_MC18_MISC 0x0000044B +#define MSR_IA32_MC19_MISC 0x0000044F +#define MSR_IA32_MC20_MISC 0x00000453 +#define MSR_IA32_MC21_MISC 0x00000457 +#define MSR_IA32_MC22_MISC 0x0000045B +#define MSR_IA32_MC23_MISC 0x0000045F +#define MSR_IA32_MC24_MISC 0x00000463 +#define MSR_IA32_MC25_MISC 0x00000467 +#define MSR_IA32_MC26_MISC 0x0000046B +#define MSR_IA32_MC27_MISC 0x0000046F +#define MSR_IA32_MC28_MISC 0x00000473 +/// @} + + +/** + Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic + VMX Information.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_BASIC (0x00000480) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + MSR_IA32_VMX_BASIC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC); + @endcode + @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. +**/ +#define MSR_IA32_VMX_BASIC 0x00000480 + +/** + MSR information returned for MSR index #MSR_IA32_VMX_BASIC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 30:0] VMCS revision identifier used by the processor. Processors + /// that use the same VMCS revision identifier use the same size for VMCS + /// regions (see subsequent item on bits 44:32). + /// + /// @note Earlier versions of this manual specified that the VMCS revision + /// identifier was a 32-bit field in bits 31:0 of this MSR. For all + /// processors produced prior to this change, bit 31 of this MSR was read + /// as 0. + /// + UINT32 VmcsRevisonId:31; + UINT32 MustBeZero:1; + /// + /// [Bit 44:32] Reports the number of bytes that software should allocate + /// for the VMXON region and any VMCS region. It is a value greater than + /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear). + /// + UINT32 VmcsSize:13; + UINT32 Reserved1:3; + /// + /// [Bit 48] Indicates the width of the physical addresses that may be used + /// for the VMXON region, each VMCS, and data structures referenced by + /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX + /// transitions). If the bit is 0, these addresses are limited to the + /// processor's physical-address width. If the bit is 1, these addresses + /// are limited to 32 bits. This bit is always 0 for processors that + /// support Intel 64 architecture. + /// + /// @note On processors that support Intel 64 architecture, the pointer + /// must not set bits beyond the processor's physical address width. + /// + UINT32 VmcsAddressWidth:1; + /// + /// [Bit 49] If bit 49 is read as 1, the logical processor supports the + /// dual-monitor treatment of system-management interrupts and + /// system-management mode. See Section 34.15 for details of this treatment. + /// + UINT32 DualMonitor:1; + /// + /// [Bit 53:50] report the memory type that should be used for the VMCS, + /// for data structures referenced by pointers in the VMCS (I/O bitmaps, + /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG + /// header. If software needs to access these data structures (e.g., to + /// modify the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported bits + /// 53:50 in this MSR. + /// + /// As of this writing, all processors that support VMX operation indicate + /// the write-back type. + /// + /// If software needs to access these data structures (e.g., to modify + /// the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does so, + /// it should establish mappings that use the memory type reported in this + /// MSR. + /// + /// @note Alternatively, software may map any of these regions or + /// structures with the UC memory type. (This may be necessary for the MSEG + /// header.) Doing so is discouraged unless necessary as it will cause the + /// performance of software accesses to those structures to suffer. + /// + /// + UINT32 MemoryType:4; + /// + /// [Bit 54] If bit 54 is read as 1, the processor reports information in + /// the VM-exit instruction-information field on VM exitsdue to execution + /// of the INS and OUTS instructions (see Section 27.2.4). This reporting + /// is done only if this bit is read as 1. + /// + UINT32 InsOutsReporting:1; + /// + /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may + /// be cleared to 0. See Appendix A.2 for details. It also reports support + /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, + /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and + /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, + /// Appendix A.4, and Appendix A.5 for details. + /// + UINT32 VmxControls:1; + UINT32 Reserved2:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_VMX_BASIC_REGISTER; + +/// +/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType +/// +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 +/// +/// @} +/// + + +/** + Capability Reporting Register of Pinbased VM-execution Controls (R/O) See + Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 + + +/** + Capability Reporting Register of Primary Processor-based VM-execution + Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution + Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS); + @endcode + @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 + + +/** + Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, + "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS); + @endcode + @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM. +**/ +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 + + +/** + Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5, + "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS); + @endcode + @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM. +**/ +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 + + +/** + Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, + "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_MISC (0x00000485) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + IA32_VMX_MISC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC); + @endcode + @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. +**/ +#define MSR_IA32_VMX_MISC 0x00000485 + +/** + MSR information returned for MSR index #IA32_VMX_MISC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Reports a value X that specifies the relationship between the + /// rate of the VMX-preemption timer and that of the timestamp counter (TSC). + /// Specifically, the VMX-preemption timer (if it is active) counts down by + /// 1 every time bit X in the TSC changes due to a TSC increment. + /// + UINT32 VmxTimerRatio:5; + /// + /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA + /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more + /// details. This bit is read as 1 on any logical processor that supports + /// the 1-setting of the "unrestricted guest" VM-execution control. + /// + UINT32 VmExitEferLma:1; + /// + /// [Bit 6] reports (if set) the support for activity state 1 (HLT). + /// + UINT32 HltActivityStateSupported:1; + /// + /// [Bit 7] reports (if set) the support for activity state 2 (shutdown). + /// + UINT32 ShutdownActivityStateSupported:1; + /// + /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI). + /// + UINT32 WaitForSipiActivityStateSupported:1; + UINT32 Reserved1:5; + /// + /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used + /// in VMX operation. If the processor supports Intel PT but does not allow + /// it to be used in VMX operation, execution of VMXON clears + /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); + /// any attempt to set that bit while in VMX operation (including VMX root + /// operation) using the WRMSR instruction causes a general-protection + /// exception. + /// + UINT32 ProcessorTraceSupported:1; + /// + /// [Bit 15] If read as 1, the RDMSR instruction can be used in system- + /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). + /// See Section 34.15.6.3. + /// + UINT32 SmBaseMsrSupported:1; + /// + /// [Bits 24:16] Indicate the number of CR3-target values supported by the + /// processor. This number is a value between 0 and 256, inclusive (bit 24 + /// is set if and only if bits 23:16 are clear). + /// + UINT32 NumberOfCr3TargetValues:9; + /// + /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum + /// number of MSRs that should appear in the VM-exit MSR-store list, the + /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if + /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the + /// recommended maximum number of MSRs to be included in each list. If the + /// limit is exceeded, undefined processor behavior may result (including a + /// machine check during the VMX transition). + /// + UINT32 MsrStoreListMaximum:3; + /// + /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set + /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 + /// (see Section 34.14.4). + /// + UINT32 BlockSmiSupported:1; + /// + /// [Bit 29] read as 1, software can use VMWRITE to write to any supported + /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit + /// information fields. + /// + UINT32 VmWriteSupported:1; + /// + /// [Bit 30] If read as 1, VM entry allows injection of a software + /// interrupt, software exception, or privileged software exception with an + /// instruction length of 0. + /// + UINT32 VmInjectSupported:1; + UINT32 Reserved2:1; + /// + /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the + /// processor. + /// + UINT32 MsegRevisionIdentifier:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_VMX_MISC_REGISTER; + + +/** + Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0); + @endcode + @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 + + +/** + Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, + "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1); + @endcode + @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM. +**/ +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 + + +/** + Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, + "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0); + @endcode + @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM. +**/ +#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 + + +/** + Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, + "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1); + @endcode + @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM. +**/ +#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 + + +/** + Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix + A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1. + + @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM); + @endcode + @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM. +**/ +#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A + + +/** + Capability Reporting Register of Secondary Processor-based VM-execution + Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution + Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]). + + @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2); + @endcode + @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM. +**/ +#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B + + +/** + Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10, + "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C + TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ). + + @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP); + @endcode + @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM. +**/ +#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C + + +/** + Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O) + See Appendix A.3.1, "Pin-Based VMExecution Controls.". If ( + CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). + + @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS); + @endcode + @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D + + +/** + Capability Reporting Register of Primary Processor-based VM-execution Flex + Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution + Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). + + @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS); + @endcode + @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM. +**/ +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E + + +/** + Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix + A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). + + @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS); + @endcode + @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM. +**/ +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F + + +/** + Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix + A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). + + @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS); + @endcode + @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM. +**/ +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 + + +/** + Capability Reporting Register of VMfunction Controls (R/O). If( + CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ). + + @param ECX MSR_IA32_VMX_VMFUNC (0x00000491) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC); + @endcode + @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM. +**/ +#define MSR_IA32_VMX_VMFUNC 0x00000491 + + +/** + Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) && + IA32_PERF_CAPABILITIES[ 13] = 1. + + @param ECX MSR_IA32_A_PMCn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_A_PMC0); + AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr); + @endcode + @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM. + MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM. + MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM. + MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM. + MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM. + MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM. + MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM. + MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM. + @{ +**/ +#define MSR_IA32_A_PMC0 0x000004C1 +#define MSR_IA32_A_PMC1 0x000004C2 +#define MSR_IA32_A_PMC2 0x000004C3 +#define MSR_IA32_A_PMC3 0x000004C4 +#define MSR_IA32_A_PMC4 0x000004C5 +#define MSR_IA32_A_PMC5 0x000004C6 +#define MSR_IA32_A_PMC6 0x000004C7 +#define MSR_IA32_A_PMC7 0x000004C8 +/// @} + + +/** + (R/W). If IA32_MCG_CAP.LMCE_P =1. + + @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER. + + Example usage + @code + MSR_IA32_MCG_EXT_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); + AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM. +**/ +#define MSR_IA32_MCG_EXT_CTL 0x000004D0 + +/** + MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LMCE_EN. + /// + UINT32 LMCE_EN:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_MCG_EXT_CTL_REGISTER; + + +/** + Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H, + ECX=0H): EBX[2] = 1. + + @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_SGX_SVN_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS); + @endcode + @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM. +**/ +#define MSR_IA32_SGX_SVN_STATUS 0x00000500 + +/** + MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated + /// Code Modules (ACMs)". + /// + UINT32 Lock:1; + UINT32 Reserved1:15; + /// + /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with + /// Authenticated Code Modules (ACMs)". + /// + UINT32 SGX_SVN_SINIT:8; + UINT32 Reserved2:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_SGX_SVN_STATUS_REGISTER; + + +/** + Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1) + && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) + ) ). + + @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); + AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM. +**/ +#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:7; + /// + /// [Bits 31:7] Base physical address. + /// + UINT32 Base:25; + /// + /// [Bits 63:32] Base physical address. + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER; + + +/** + Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H, + ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) + (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ). + + @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); + AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM. +**/ +#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:7; + /// + /// [Bits 31:7] MaskOrTableOffset. + /// + UINT32 MaskOrTableOffset:25; + /// + /// [Bits 63:32] Output Offset. + /// + UINT32 OutputOffset:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER; + +/** + Format of ToPA table entries. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 END:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 INT:1; + UINT32 Reserved2:1; + /// + /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 STOP:1; + UINT32 Reserved3:1; + /// + /// [Bit 6:9] Indicates the size of the associated output region. See Section + /// 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Size:4; + UINT32 Reserved4:2; + /// + /// [Bit 12:31] Output Region Base Physical Address low part. + /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match. + /// ATTENTION: The size of the address field is determined by the processor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 Base:20; + /// + /// [Bit 32:63] Output Region Base Physical Address high part. + /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match. + /// ATTENTION: The size of the address field is determined by the processor's + /// physical-address width (MAXPHYADDR) in bits, as reported in + /// CPUID.80000008H:EAX[7:0]. the above part of address reserved. + /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. + /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)". + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} RTIT_TOPA_TABLE_ENTRY; + +/// +/// The size of the associated output region usd by Topa. +/// +typedef enum { + RtitTopaMemorySize4K = 0, + RtitTopaMemorySize8K, + RtitTopaMemorySize16K, + RtitTopaMemorySize32K, + RtitTopaMemorySize64K, + RtitTopaMemorySize128K, + RtitTopaMemorySize256K, + RtitTopaMemorySize512K, + RtitTopaMemorySize1M, + RtitTopaMemorySize2M, + RtitTopaMemorySize4M, + RtitTopaMemorySize8M, + RtitTopaMemorySize16M, + RtitTopaMemorySize32M, + RtitTopaMemorySize64M, + RtitTopaMemorySize128M +} RTIT_TOPA_MEMORY_SIZE; + +/** + Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). + + @param ECX MSR_IA32_RTIT_CTL (0x00000570) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_CTL_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); + AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM. +**/ +#define MSR_IA32_RTIT_CTL 0x00000570 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] TraceEn. + /// + UINT32 TraceEn:1; + /// + /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). + /// + UINT32 CYCEn:1; + /// + /// [Bit 2] OS. + /// + UINT32 OS:1; + /// + /// [Bit 3] User. + /// + UINT32 User:1; + /// + /// [Bit 4] PwrEvtEn. + /// + UINT32 PwrEvtEn:1; + /// + /// [Bit 5] FUPonPTW. + /// + UINT32 FUPonPTW:1; + /// + /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1). + /// + UINT32 FabricEn:1; + /// + /// [Bit 7] CR3 filter. + /// + UINT32 CR3:1; + /// + /// [Bit 8] ToPA. + /// + UINT32 ToPA:1; + /// + /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). + /// + UINT32 MTCEn:1; + /// + /// [Bit 10] TSCEn. + /// + UINT32 TSCEn:1; + /// + /// [Bit 11] DisRETC. + /// + UINT32 DisRETC:1; + /// + /// [Bit 12] PTWEn. + /// + UINT32 PTWEn:1; + /// + /// [Bit 13] BranchEn. + /// + UINT32 BranchEn:1; + /// + /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). + /// + UINT32 MTCFreq:4; + UINT32 Reserved3:1; + /// + /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). + /// + UINT32 CYCThresh:4; + UINT32 Reserved4:1; + /// + /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). + /// + UINT32 PSBFreq:4; + UINT32 Reserved5:4; + /// + /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0). + /// + UINT32 ADDR0_CFG:4; + /// + /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1). + /// + UINT32 ADDR1_CFG:4; + /// + /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2). + /// + UINT32 ADDR2_CFG:4; + /// + /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3). + /// + UINT32 ADDR3_CFG:4; + UINT32 Reserved6:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_CTL_REGISTER; + + +/** + Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). + + @param ECX MSR_IA32_RTIT_STATUS (0x00000571) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS); + AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM. +**/ +#define MSR_IA32_RTIT_STATUS 0x00000571 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] FilterEn, (writes ignored). + /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1). + /// + UINT32 FilterEn:1; + /// + /// [Bit 1] ContexEn, (writes ignored). + /// + UINT32 ContexEn:1; + /// + /// [Bit 2] TriggerEn, (writes ignored). + /// + UINT32 TriggerEn:1; + UINT32 Reserved1:1; + /// + /// [Bit 4] Error. + /// + UINT32 Error:1; + /// + /// [Bit 5] Stopped. + /// + UINT32 Stopped:1; + UINT32 Reserved2:26; + /// + /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3). + /// + UINT32 PacketByteCnt:17; + UINT32 Reserved3:15; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_STATUS_REGISTER; + + +/** + Trace Filter CR3 Match Register (R/W). + If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1). + + @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH); + AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM. +**/ +#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:5; + /// + /// [Bits 31:5] CR3[63:5] value to match. + /// + UINT32 Cr3:27; + /// + /// [Bits 63:32] CR3[63:5] value to match. + /// + UINT32 Cr3Hi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_CR3_MATCH_REGISTER; + + +/** + Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). + + @param ECX MSR_IA32_RTIT_ADDRn_A + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_ADDR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_ADDR_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_ADDR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A); + AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM. + MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM. + MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM. + MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM. + @{ +**/ +#define MSR_IA32_RTIT_ADDR0_A 0x00000580 +#define MSR_IA32_RTIT_ADDR1_A 0x00000582 +#define MSR_IA32_RTIT_ADDR2_A 0x00000584 +#define MSR_IA32_RTIT_ADDR3_A 0x00000586 +/// @} + + +/** + Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n). + + @param ECX MSR_IA32_RTIT_ADDRn_B + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_ADDR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_RTIT_ADDR_REGISTER. + + Example usage + @code + MSR_IA32_RTIT_ADDR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B); + AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64); + @endcode + @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM. + MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM. + MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM. + MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM. + @{ +**/ +#define MSR_IA32_RTIT_ADDR0_B 0x00000581 +#define MSR_IA32_RTIT_ADDR1_B 0x00000583 +#define MSR_IA32_RTIT_ADDR2_B 0x00000585 +#define MSR_IA32_RTIT_ADDR3_B 0x00000587 +/// @} + + +/** + MSR information returned for MSR indexes + #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and + #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Virtual Address. + /// + UINT32 VirtualAddress:32; + /// + /// [Bits 47:32] Virtual Address. + /// + UINT32 VirtualAddressHi:16; + /// + /// [Bits 63:48] SignExt_VA. + /// + UINT32 SignExt_VA:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_RTIT_ADDR_REGISTER; + + +/** + DS Save Area (R/W) Points to the linear address of the first byte of the DS + buffer management area, which is used to manage the BTS and PEBS buffers. + See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If( + CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS + buffer management area, if IA-32e mode is active. + + @param ECX MSR_IA32_DS_AREA (0x00000600) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DS_AREA_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DS_AREA_REGISTER. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_DS_AREA); + AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr); + @endcode + @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM. +**/ +#define MSR_IA32_DS_AREA 0x00000600 + + +/** + TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] = + 1. + + @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE); + AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr); + @endcode + @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM. +**/ +#define MSR_IA32_TSC_DEADLINE 0x000006E0 + + +/** + Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1. + + @param ECX MSR_IA32_PM_ENABLE (0x00000770) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PM_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PM_ENABLE_REGISTER. + + Example usage + @code + MSR_IA32_PM_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE); + AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64); + @endcode + @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM. +**/ +#define MSR_IA32_PM_ENABLE 0x00000770 + +/** + MSR information returned for MSR index #MSR_IA32_PM_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If + /// CPUID.06H:EAX.[7] = 1. + /// + UINT32 HWP_ENABLE:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PM_ENABLE_REGISTER; + + +/** + HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1. + + @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER. + + Example usage + @code + MSR_IA32_HWP_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES); + @endcode + @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM. +**/ +#define MSR_IA32_HWP_CAPABILITIES 0x00000771 + +/** + MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance + /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Highest_Performance:8; + /// + /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP + /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Guaranteed_Performance:8; + /// + /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP + /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Most_Efficient_Performance:8; + /// + /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance + /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Lowest_Performance:8; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_HWP_CAPABILITIES_REGISTER; + + +/** + Power Management Control Hints for All Logical Processors in a Package + (R/W). If CPUID.06H:EAX.[11] = 1. + + @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER. + + Example usage + @code + MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG); + AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64); + @endcode + @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM. +**/ +#define MSR_IA32_HWP_REQUEST_PKG 0x00000772 + +/** + MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[11] = 1. + /// + UINT32 Minimum_Performance:8; + /// + /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[11] = 1. + /// + UINT32 Maximum_Performance:8; + /// + /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". + /// If CPUID.06H:EAX.[11] = 1. + /// + UINT32 Desired_Performance:8; + /// + /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, + /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1. + /// + UINT32 Energy_Performance_Preference:8; + /// + /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1. + /// + UINT32 Activity_Window:10; + UINT32 Reserved:22; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_HWP_REQUEST_PKG_REGISTER; + + +/** + Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1. + + @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER. + + Example usage + @code + MSR_IA32_HWP_INTERRUPT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT); + AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64); + @endcode + @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM. +**/ +#define MSR_IA32_HWP_INTERRUPT 0x00000773 + +/** + MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP + /// Notifications". If CPUID.06H:EAX.[8] = 1. + /// + UINT32 EN_Guaranteed_Performance_Change:1; + /// + /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications". + /// If CPUID.06H:EAX.[8] = 1. + /// + UINT32 EN_Excursion_Minimum:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_HWP_INTERRUPT_REGISTER; + + +/** + Power Management Control Hints to a Logical Processor (R/W). If + CPUID.06H:EAX.[7] = 1. + + @param ECX MSR_IA32_HWP_REQUEST (0x00000774) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_HWP_REQUEST_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_HWP_REQUEST_REGISTER. + + Example usage + @code + MSR_IA32_HWP_REQUEST_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST); + AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64); + @endcode + @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM. +**/ +#define MSR_IA32_HWP_REQUEST 0x00000774 + +/** + MSR information returned for MSR index #MSR_IA32_HWP_REQUEST +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[7] = 1. + /// + UINT32 Minimum_Performance:8; + /// + /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[7] = 1. + /// + UINT32 Maximum_Performance:8; + /// + /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". + /// If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Desired_Performance:8; + /// + /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4, + /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1. + /// + UINT32 Energy_Performance_Preference:8; + /// + /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1. + /// + UINT32 Activity_Window:10; + /// + /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If + /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1. + /// + UINT32 Package_Control:1; + UINT32 Reserved:21; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_HWP_REQUEST_REGISTER; + + +/** + Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If + CPUID.06H:EAX.[7] = 1. + + @param ECX MSR_IA32_HWP_STATUS (0x00000777) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_HWP_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_HWP_STATUS_REGISTER. + + Example usage + @code + MSR_IA32_HWP_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS); + AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64); + @endcode + @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM. +**/ +#define MSR_IA32_HWP_STATUS 0x00000777 + +/** + MSR information returned for MSR index #MSR_IA32_HWP_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5, + /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Guaranteed_Performance_Change:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP + /// Feedback". If CPUID.06H:EAX.[7] = 1. + /// + UINT32 Excursion_To_Minimum:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_HWP_STATUS_REGISTER; + + +/** + x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1 + && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_APICID (0x00000802) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID); + @endcode + @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM. +**/ +#define MSR_IA32_X2APIC_APICID 0x00000802 + + +/** + x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_VERSION (0x00000803) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION); + @endcode + @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM. +**/ +#define MSR_IA32_X2APIC_VERSION 0x00000803 + + +/** + x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_TPR (0x00000808) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR); + AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr); + @endcode + @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM. +**/ +#define MSR_IA32_X2APIC_TPR 0x00000808 + + +/** + x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_PPR (0x0000080A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR); + @endcode + @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM. +**/ +#define MSR_IA32_X2APIC_PPR 0x0000080A + + +/** + x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] + = 1. + + @param ECX MSR_IA32_X2APIC_EOI (0x0000080B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr); + @endcode + @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM. +**/ +#define MSR_IA32_X2APIC_EOI 0x0000080B + + +/** + x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LDR (0x0000080D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR); + @endcode + @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM. +**/ +#define MSR_IA32_X2APIC_LDR 0x0000080D + + +/** + x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1 + && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR); + AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr); + @endcode + @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM. +**/ +#define MSR_IA32_X2APIC_SIVR 0x0000080F + + +/** + x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O). + If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_ISRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0); + @endcode + @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM. + MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM. + MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM. + MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM. + MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM. + MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM. + MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM. + MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM. + @{ +**/ +#define MSR_IA32_X2APIC_ISR0 0x00000810 +#define MSR_IA32_X2APIC_ISR1 0x00000811 +#define MSR_IA32_X2APIC_ISR2 0x00000812 +#define MSR_IA32_X2APIC_ISR3 0x00000813 +#define MSR_IA32_X2APIC_ISR4 0x00000814 +#define MSR_IA32_X2APIC_ISR5 0x00000815 +#define MSR_IA32_X2APIC_ISR6 0x00000816 +#define MSR_IA32_X2APIC_ISR7 0x00000817 +/// @} + + +/** + x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O). + If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_TMRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0); + @endcode + @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM. + MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM. + MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM. + MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM. + MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM. + MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM. + MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM. + MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM. + @{ +**/ +#define MSR_IA32_X2APIC_TMR0 0x00000818 +#define MSR_IA32_X2APIC_TMR1 0x00000819 +#define MSR_IA32_X2APIC_TMR2 0x0000081A +#define MSR_IA32_X2APIC_TMR3 0x0000081B +#define MSR_IA32_X2APIC_TMR4 0x0000081C +#define MSR_IA32_X2APIC_TMR5 0x0000081D +#define MSR_IA32_X2APIC_TMR6 0x0000081E +#define MSR_IA32_X2APIC_TMR7 0x0000081F +/// @} + + +/** + x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O). + If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_IRRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0); + @endcode + @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM. + MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM. + MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM. + MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM. + MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM. + MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM. + MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM. + MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM. + @{ +**/ +#define MSR_IA32_X2APIC_IRR0 0x00000820 +#define MSR_IA32_X2APIC_IRR1 0x00000821 +#define MSR_IA32_X2APIC_IRR2 0x00000822 +#define MSR_IA32_X2APIC_IRR3 0x00000823 +#define MSR_IA32_X2APIC_IRR4 0x00000824 +#define MSR_IA32_X2APIC_IRR5 0x00000825 +#define MSR_IA32_X2APIC_IRR6 0x00000826 +#define MSR_IA32_X2APIC_IRR7 0x00000827 +/// @} + + +/** + x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_ESR (0x00000828) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR); + AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr); + @endcode + @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM. +**/ +#define MSR_IA32_X2APIC_ESR 0x00000828 + + +/** + x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If + CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F + + +/** + x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_ICR (0x00000830) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR); + AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr); + @endcode + @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM. +**/ +#define MSR_IA32_X2APIC_ICR 0x00000830 + + +/** + x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832 + + +/** + x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] = + 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833 + + +/** + x2APIC LVT Performance Monitor Interrupt Register (R/W). If + CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_PMI 0x00000834 + + +/** + x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835 + + +/** + x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836 + + +/** + x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR); + AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr); + @endcode + @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM. +**/ +#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837 + + +/** + x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT); + AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr); + @endcode + @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM. +**/ +#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838 + + +/** + x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT); + @endcode + @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM. +**/ +#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839 + + +/** + x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF); + AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr); + @endcode + @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM. +**/ +#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E + + +/** + x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 && + IA32_APIC_BASE.[10] = 1. + + @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr); + @endcode + @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM. +**/ +#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F + + +/** + Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1. + + @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER. + + Example usage + @code + MSR_IA32_DEBUG_INTERFACE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE); + AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64); + @endcode + @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM. +**/ +#define MSR_IA32_DEBUG_INTERFACE 0x00000C80 + +/** + MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features. + /// Default is 0. If CPUID.01H:ECX.[11] = 1. + /// + UINT32 Enable:1; + UINT32 Reserved1:29; + /// + /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The + /// lock bit is set automatically on the first SMI assertion even if not + /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1. + /// + UINT32 Lock:1; + /// + /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to + /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1. + /// + UINT32 DebugOccurred:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_DEBUG_INTERFACE_REGISTER; + + +/** + L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ). + + @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_L3_QOS_CFG_REGISTER. + + Example usage + @code + MSR_IA32_L3_QOS_CFG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG); + AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64); + @endcode + @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. +**/ +#define MSR_IA32_L3_QOS_CFG 0x00000C81 + +/** + MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate + /// in Code and Data Prioritization (CDP) mode. + /// + UINT32 Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_L3_QOS_CFG_REGISTER; + +/** + L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ). + + @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_L2_QOS_CFG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_L2_QOS_CFG_REGISTER. + + Example usage + @code + MSR_IA32_L2_QOS_CFG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG); + AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64); + @endcode + @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM. +**/ +#define MSR_IA32_L2_QOS_CFG 0x00000C82 + +/** + MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate + /// in Code and Data Prioritization (CDP) mode. + /// + UINT32 Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_L2_QOS_CFG_REGISTER; + +/** + Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] + = 1 ). + + @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_QM_EVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_QM_EVTSEL_REGISTER. + + Example usage + @code + MSR_IA32_QM_EVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL); + AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64); + @endcode + @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. +**/ +#define MSR_IA32_QM_EVTSEL 0x00000C8D + +/** + MSR information returned for MSR index #MSR_IA32_QM_EVTSEL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via + /// IA32_QM_CTR. + /// + UINT32 EventID:8; + UINT32 Reserved:24; + /// + /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to + /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` ( + /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). + /// + UINT32 ResourceMonitoringID:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_QM_EVTSEL_REGISTER; + + +/** + Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1 + ). + + @param ECX MSR_IA32_QM_CTR (0x00000C8E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_QM_CTR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_QM_CTR_REGISTER. + + Example usage + @code + MSR_IA32_QM_CTR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR); + @endcode + @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM. +**/ +#define MSR_IA32_QM_CTR 0x00000C8E + +/** + MSR information returned for MSR index #MSR_IA32_QM_CTR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Resource Monitored Data. + /// + UINT32 ResourceMonitoredData:32; + /// + /// [Bits 61:32] Resource Monitored Data. + /// + UINT32 ResourceMonitoredDataHi:30; + /// + /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not + /// available or not monitored for this resource or RMID. + /// + UINT32 Unavailable:1; + /// + /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was + /// written to IA32_PQR_QM_EVTSEL. + /// + UINT32 Error:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_QM_CTR_REGISTER; + + +/** + Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12] + =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ). + + @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PQR_ASSOC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PQR_ASSOC_REGISTER. + + Example usage + @code + MSR_IA32_PQR_ASSOC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC); + AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64); + @endcode + @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. +**/ +#define MSR_IA32_PQR_ASSOC 0x00000C8F + +/** + MSR information returned for MSR index #MSR_IA32_PQR_ASSOC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware + /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2` + /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)). + /// + UINT32 ResourceMonitoringID:32; + /// + /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on + /// writes); returns the current COS when read. If ( CPUID.(EAX=07H, + /// ECX=0):EBX.[15] = 1 ). + /// + UINT32 COS:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PQR_ASSOC_REGISTER; + + +/** + Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H, + ECX=0H):EBX[14] = 1). + + @param ECX MSR_IA32_BNDCFGS (0x00000D90) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_BNDCFGS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_BNDCFGS_REGISTER. + + Example usage + @code + MSR_IA32_BNDCFGS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS); + AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64); + @endcode + @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM. +**/ +#define MSR_IA32_BNDCFGS 0x00000D90 + +/** + MSR information returned for MSR index #MSR_IA32_BNDCFGS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EN: Enable Intel MPX in supervisor mode. + /// + UINT32 EN:1; + /// + /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch + /// instructions in the absence of the BND prefix. + /// + UINT32 BNDPRESERVE:1; + UINT32 Reserved:10; + /// + /// [Bits 31:12] Base Address of Bound Directory. + /// + UINT32 Base:20; + /// + /// [Bits 63:32] Base Address of Bound Directory. + /// + UINT32 BaseHi:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_BNDCFGS_REGISTER; + + +/** + Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1. + + @param ECX MSR_IA32_XSS (0x00000DA0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_XSS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_XSS_REGISTER. + + Example usage + @code + MSR_IA32_XSS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS); + AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64); + @endcode + @note MSR_IA32_XSS is defined as IA32_XSS in SDM. +**/ +#define MSR_IA32_XSS 0x00000DA0 + +/** + MSR information returned for MSR index #MSR_IA32_XSS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bit 8] Trace Packet Configuration State (R/W). + /// + UINT32 TracePacketConfigurationState:1; + UINT32 Reserved2:23; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_XSS_REGISTER; + + +/** + Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1. + + @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER. + + Example usage + @code + MSR_IA32_PKG_HDC_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL); + AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64); + @endcode + @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM. +**/ +#define MSR_IA32_PKG_HDC_CTL 0x00000DB0 + +/** + MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled + /// logical processors in the package. See Section 14.5.2, "Package level + /// Enabling HDC". If CPUID.06H:EAX.[13] = 1. + /// + UINT32 HDC_Pkg_Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PKG_HDC_CTL_REGISTER; + + +/** + Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1. + + @param ECX MSR_IA32_PM_CTL1 (0x00000DB1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_PM_CTL1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_PM_CTL1_REGISTER. + + Example usage + @code + MSR_IA32_PM_CTL1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1); + AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64); + @endcode + @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM. +**/ +#define MSR_IA32_PM_CTL1 0x00000DB1 + +/** + MSR information returned for MSR index #MSR_IA32_PM_CTL1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for + /// package level HDC control. See Section 14.5.3. + /// If CPUID.06H:EAX.[13] = 1. + /// + UINT32 HDC_Allow_Block:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_PM_CTL1_REGISTER; + + +/** + Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1. + Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical + processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1. + + @param ECX MSR_IA32_THREAD_STALL (0x00000DB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL); + @endcode + @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM. +**/ +#define MSR_IA32_THREAD_STALL 0x00000DB2 + + +/** + Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0] + CPUID.80000001H:EDX.[2 9]). + + @param ECX MSR_IA32_EFER (0xC0000080) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_EFER_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_EFER_REGISTER. + + Example usage + @code + MSR_IA32_EFER_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); + AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64); + @endcode + @note MSR_IA32_EFER is defined as IA32_EFER in SDM. +**/ +#define MSR_IA32_EFER 0xC0000080 + +/** + MSR information returned for MSR index #MSR_IA32_EFER +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET + /// instructions in 64-bit mode. + /// + UINT32 SCE:1; + UINT32 Reserved1:7; + /// + /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode + /// operation. + /// + UINT32 LME:1; + UINT32 Reserved2:1; + /// + /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode + /// is active when set. + /// + UINT32 LMA:1; + /// + /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W). + /// + UINT32 NXE:1; + UINT32 Reserved3:20; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_EFER_REGISTER; + + +/** + System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_STAR (0xC0000081) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_STAR); + AsmWriteMsr64 (MSR_IA32_STAR, Msr); + @endcode + @note MSR_IA32_STAR is defined as IA32_STAR in SDM. +**/ +#define MSR_IA32_STAR 0xC0000081 + + +/** + IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_LSTAR (0xC0000082) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_LSTAR); + AsmWriteMsr64 (MSR_IA32_LSTAR, Msr); + @endcode + @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM. +**/ +#define MSR_IA32_LSTAR 0xC0000082 + +/** + IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL + instruction is not recognized in compatibility mode. If + CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_CSTAR (0xC0000083) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_CSTAR); + AsmWriteMsr64 (MSR_IA32_CSTAR, Msr); + @endcode + @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM. +**/ +#define MSR_IA32_CSTAR 0xC0000083 + +/** + System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_FMASK (0xC0000084) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FMASK); + AsmWriteMsr64 (MSR_IA32_FMASK, Msr); + @endcode + @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM. +**/ +#define MSR_IA32_FMASK 0xC0000084 + + +/** + Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_FS_BASE (0xC0000100) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_FS_BASE); + AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr); + @endcode + @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM. +**/ +#define MSR_IA32_FS_BASE 0xC0000100 + + +/** + Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_GS_BASE (0xC0000101) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_GS_BASE); + AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr); + @endcode + @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM. +**/ +#define MSR_IA32_GS_BASE 0xC0000101 + + +/** + Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1. + + @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE); + AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr); + @endcode + @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM. +**/ +#define MSR_IA32_KERNEL_GS_BASE 0xC0000102 + + +/** + Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1. + + @param ECX MSR_IA32_TSC_AUX (0xC0000103) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IA32_TSC_AUX_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IA32_TSC_AUX_REGISTER. + + Example usage + @code + MSR_IA32_TSC_AUX_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX); + AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64); + @endcode + @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM. +**/ +#define MSR_IA32_TSC_AUX 0xC0000103 + +/** + MSR information returned for MSR index #MSR_IA32_TSC_AUX +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] AUX: Auxiliary signature of TSC. + /// + UINT32 AUX:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_TSC_AUX_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Cpuid.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Cpuid.h new file mode 100644 index 0000000000..10c79963d2 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Cpuid.h @@ -0,0 +1,4075 @@ +/** @file + Intel CPUID leaf definitions. + + Provides defines for CPUID leaf indexes. Data structures are provided for + registers returned by a CPUID leaf that contain one or more bit fields. + If a register returned is a single 32-bit value, then a data structure is + not provided for that register. + + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, + November 2018, CPUID instruction. + +**/ + +#ifndef __INTEL_CPUID_H__ +#define __INTEL_CPUID_H__ + +/** + CPUID Signature Information + + @param EAX CPUID_SIGNATURE (0x00) + + @retval EAX Returns the highest value the CPUID instruction recognizes for + returning basic processor information. The value is returned is + processor specific. + @retval EBX First 4 characters of a vendor identification string. + @retval ECX Last 4 characters of a vendor identification string. + @retval EDX Middle 4 characters of a vendor identification string. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ +#define CPUID_SIGNATURE 0x00 + +/// +/// @{ CPUID signature values returned by Intel processors +/// +#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u') +#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I') +#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l') +/// +/// @} +/// + + +/** + CPUID Version Information + + @param EAX CPUID_VERSION_INFO (0x01) + + @retval EAX Returns Model, Family, Stepping Information described by the + type CPUID_VERSION_INFO_EAX. + @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by + the type CPUID_VERSION_INFO_EBX. + @retval ECX CPU Feature Information described by the type + CPUID_VERSION_INFO_ECX. + @retval EDX CPU Feature Information described by the type + CPUID_VERSION_INFO_EDX. + + Example usage + @code + CPUID_VERSION_INFO_EAX Eax; + CPUID_VERSION_INFO_EBX Ebx; + CPUID_VERSION_INFO_ECX Ecx; + CPUID_VERSION_INFO_EDX Edx; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_VERSION_INFO 0x01 + +/** + CPUID Version Information returned in EAX for CPUID leaf + #CPUID_VERSION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID + UINT32 Model:4; ///< [Bits 7:4] Model + UINT32 FamilyId:4; ///< [Bits 11:8] Family + UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type + UINT32 Reserved1:2; ///< [Bits 15:14] Reserved + UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID + UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID + UINT32 Reserved2:4; ///< Reserved + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_VERSION_INFO_EAX; + +/// +/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType +/// +#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00 +#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01 +#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02 +/// +/// @} +/// + +/** + CPUID Version Information returned in EBX for CPUID leaf + #CPUID_VERSION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Provides an entry into a brand string table that contains + /// brand strings for IA-32 processors. + /// + UINT32 BrandIndex:8; + /// + /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH + /// and CLFLUSHOPT instructions in 8-byte increments. This field was + /// introduced in the Pentium 4 processor. + /// + UINT32 CacheLineSize:8; + /// + /// [Bits 23:16] Maximum number of addressable IDs for logical processors + /// in this physical package. + /// + /// @note + /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is + /// the number of unique initial APICIDs reserved for addressing different + /// logical processors in a physical package. This field is only valid if + /// CPUID.1.EDX.HTT[bit 28]= 1. + /// + UINT32 MaximumAddressableIdsForLogicalProcessors:8; + /// + /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the + /// processor during power up. This field was introduced in the Pentium 4 + /// processor. + /// + UINT32 InitialLocalApicId:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_VERSION_INFO_EBX; + +/** + CPUID Version Information returned in ECX for CPUID leaf + #CPUID_VERSION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the + /// processor supports this technology + /// + UINT32 SSE3:1; + /// + /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ + /// instruction. Carryless Multiplication + /// + UINT32 PCLMULQDQ:1; + /// + /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports + /// DS area using 64-bit layout. + /// + UINT32 DTES64:1; + /// + /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports + /// this feature. + /// + UINT32 MONITOR:1; + /// + /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor + /// supports the extensions to the Debug Store feature to allow for branch + /// message storage qualified by CPL + /// + UINT32 DS_CPL:1; + /// + /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the + /// processor supports this technology. + /// + UINT32 VMX:1; + /// + /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor + /// supports this technology + /// + UINT32 SMX:1; + /// + /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates + /// that the processor supports this technology + /// + UINT32 EIST:1; + /// + /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor + /// supports this technology + /// + UINT32 TM2:1; + /// + /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming + /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction + /// extensions are not present in the processor. + /// + UINT32 SSSE3:1; + /// + /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode + /// can be set to either adaptive mode or shared mode. A value of 0 indicates + /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR + /// Bit 24 (L1 Data Cache Context Mode) for details + /// + UINT32 CNXT_ID:1; + /// + /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE + /// MSR for silicon debug + /// + UINT32 SDBG:1; + /// + /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple + /// Add) extensions using YMM state. + /// + UINT32 FMA:1; + /// + /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature + /// is available. + /// + UINT32 CMPXCHG16B:1; + /// + /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor + /// supports changing IA32_MISC_ENABLE[Bit 23]. + /// + UINT32 xTPR_Update_Control:1; + /// + /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the + /// processor supports the performance and debug feature indication MSR + /// IA32_PERF_CAPABILITIES. + /// + UINT32 PDCM:1; + UINT32 Reserved:1; + /// + /// [Bit 17] Process-context identifiers. A value of 1 indicates that the + /// processor supports PCIDs and that software may set CR4.PCIDE to 1. + /// + UINT32 PCID:1; + /// + /// [Bit 18] A value of 1 indicates the processor supports the ability to + /// prefetch data from a memory mapped device. Direct Cache Access. + /// + UINT32 DCA:1; + /// + /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1. + /// + UINT32 SSE4_1:1; + /// + /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2. + /// + UINT32 SSE4_2:1; + /// + /// [Bit 21] A value of 1 indicates that the processor supports x2APIC + /// feature. + /// + UINT32 x2APIC:1; + /// + /// [Bit 22] A value of 1 indicates that the processor supports MOVBE + /// instruction. + /// + UINT32 MOVBE:1; + /// + /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT + /// instruction. + /// + UINT32 POPCNT:1; + /// + /// [Bit 24] A value of 1 indicates that the processor's local APIC timer + /// supports one-shot operation using a TSC deadline value. + /// + UINT32 TSC_Deadline:1; + /// + /// [Bit 25] A value of 1 indicates that the processor supports the AESNI + /// instruction extensions. + /// + UINT32 AESNI:1; + /// + /// [Bit 26] A value of 1 indicates that the processor supports the + /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV + /// instructions, and XCR0. + /// + UINT32 XSAVE:1; + /// + /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18] + /// to enable XSETBV/XGETBV instructions to access XCR0 and to support + /// processor extended state management using XSAVE/XRSTOR. + /// + UINT32 OSXSAVE:1; + /// + /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction + /// extensions. + /// + UINT32 AVX:1; + /// + /// [Bit 29] A value of 1 indicates that processor supports 16-bit + /// floating-point conversion instructions. + /// + UINT32 F16C:1; + /// + /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction. + /// + UINT32 RDRAND:1; + /// + /// [Bit 31] Always returns 0. + /// + UINT32 NotUsed:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_VERSION_INFO_ECX; + +/** + CPUID Version Information returned in EDX for CPUID leaf + #CPUID_VERSION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU. + /// + UINT32 FPU:1; + /// + /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, + /// including CR4.VME for controlling the feature, CR4.PVI for protected + /// mode virtual interrupts, software interrupt indirection, expansion of + /// the TSS with the software indirection bitmap, and EFLAGS.VIF and + /// EFLAGS.VIP flags. + /// + UINT32 VME:1; + /// + /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including + /// CR4.DE for controlling the feature, and optional trapping of accesses to + /// DR4 and DR5. + /// + UINT32 DE:1; + /// + /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported, + /// including CR4.PSE for controlling the feature, the defined dirty bit in + /// PDE (Page Directory Entries), optional reserved bit trapping in CR3, + /// PDEs, and PTEs. + /// + UINT32 PSE:1; + /// + /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported, + /// including CR4.TSD for controlling privilege. + /// + UINT32 TSC:1; + /// + /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The + /// RDMSR and WRMSR instructions are supported. Some of the MSRs are + /// implementation dependent. + /// + UINT32 MSR:1; + /// + /// [Bit 6] Physical Address Extension. Physical addresses greater than 32 + /// bits are supported: extended page table entry formats, an extra level in + /// the page translation tables is defined, 2-MByte pages are supported + /// instead of 4 Mbyte pages if PAE bit is 1. + /// + UINT32 PAE:1; + /// + /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine + /// Checks, including CR4.MCE for controlling the feature. This feature does + /// not define the model-specific implementations of machine-check error + /// logging, reporting, and processor shutdowns. Machine Check exception + /// handlers may have to depend on processor version to do model specific + /// processing of the exception, or test for the presence of the Machine + /// Check feature. + /// + UINT32 MCE:1; + /// + /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits) + /// instruction is supported (implicitly locked and atomic). + /// + UINT32 CX8:1; + /// + /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable + /// Interrupt Controller (APIC), responding to memory mapped commands in the + /// physical address range FFFE0000H to FFFE0FFFH (by default - some + /// processors permit the APIC to be relocated). + /// + UINT32 APIC:1; + UINT32 Reserved1:1; + /// + /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT + /// and associated MSRs are supported. + /// + UINT32 SEP:1; + /// + /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap + /// MSR contains feature bits that describe what memory types are supported, + /// how many variable MTRRs are supported, and whether fixed MTRRs are + /// supported. + /// + UINT32 MTRR:1; + /// + /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure + /// entries that map a page, indicating TLB entries that are common to + /// different processes and need not be flushed. The CR4.PGE bit controls + /// this feature. + /// + UINT32 PGE:1; + /// + /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine + /// Check Architecture of reporting machine errors is supported. The MCG_CAP + /// MSR contains feature bits describing how many banks of error reporting + /// MSRs are supported. + /// + UINT32 MCA:1; + /// + /// [Bit 15] Conditional Move Instructions. The conditional move instruction + /// CMOV is supported. In addition, if x87 FPU is present as indicated by the + /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported. + /// + UINT32 CMOV:1; + /// + /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This + /// feature augments the Memory Type Range Registers (MTRRs), allowing an + /// operating system to specify attributes of memory accessed through a + /// linear address on a 4KB granularity. + /// + UINT32 PAT:1; + /// + /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical + /// memory beyond 4 GBytes are supported with 32-bit paging. This feature + /// indicates that upper bits of the physical address of a 4-MByte page are + /// encoded in bits 20:13 of the page-directory entry. Such physical + /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size. + /// + UINT32 PSE_36:1; + /// + /// [Bit 18] Processor Serial Number. The processor supports the 96-bit + /// processor identification number feature and the feature is enabled. + /// + UINT32 PSN:1; + /// + /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported. + /// + UINT32 CLFSH:1; + UINT32 Reserved2:1; + /// + /// [Bit 21] Debug Store. The processor supports the ability to write debug + /// information into a memory resident buffer. This feature is used by the + /// branch trace store (BTS) and precise event-based sampling (PEBS) + /// facilities. + /// + UINT32 DS:1; + /// + /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The + /// processor implements internal MSRs that allow processor temperature to + /// be monitored and processor performance to be modulated in predefined + /// duty cycles under software control. + /// + UINT32 ACPI:1; + /// + /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX + /// technology. + /// + UINT32 MMX:1; + /// + /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR + /// instructions are supported for fast save and restore of the floating + /// point context. Presence of this bit also indicates that CR4.OSFXSR is + /// available for an operating system to indicate that it supports the + /// FXSAVE and FXRSTOR instructions. + /// + UINT32 FXSR:1; + /// + /// [Bit 25] SSE. The processor supports the SSE extensions. + /// + UINT32 SSE:1; + /// + /// [Bit 26] SSE2. The processor supports the SSE2 extensions. + /// + UINT32 SSE2:1; + /// + /// [Bit 27] Self Snoop. The processor supports the management of + /// conflicting memory types by performing a snoop of its own cache + /// structure for transactions issued to the bus. + /// + UINT32 SS:1; + /// + /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT + /// indicates there is only a single logical processor in the package and + /// software should assume only a single APIC ID is reserved. A value of 1 + /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of + /// addressable IDs for logical processors in this package) is valid for the + /// package. + /// + UINT32 HTT:1; + /// + /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor + /// automatic thermal control circuitry (TCC). + /// + UINT32 TM:1; + UINT32 Reserved3:1; + /// + /// [Bit 31] Pending Break Enable. The processor supports the use of the + /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is + /// asserted) to signal the processor that an interrupt is pending and that + /// the processor should return to normal operation to handle the interrupt. + /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability. + /// + UINT32 PBE:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_VERSION_INFO_EDX; + + +/** + CPUID Cache and TLB Information + + @param EAX CPUID_CACHE_INFO (0x02) + + @retval EAX Cache and TLB Information described by the type + CPUID_CACHE_INFO_CACHE_TLB. + CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns + 0x01 and must be ignored. Only valid if + CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. + @retval EBX Cache and TLB Information described by the type + CPUID_CACHE_INFO_CACHE_TLB. Only valid if + CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. + @retval ECX Cache and TLB Information described by the type + CPUID_CACHE_INFO_CACHE_TLB. Only valid if + CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. + @retval EDX Cache and TLB Information described by the type + CPUID_CACHE_INFO_CACHE_TLB. Only valid if + CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear. + + Example usage + @code + CPUID_CACHE_INFO_CACHE_TLB Eax; + CPUID_CACHE_INFO_CACHE_TLB Ebx; + CPUID_CACHE_INFO_CACHE_TLB Ecx; + CPUID_CACHE_INFO_CACHE_TLB Edx; + + AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode + + Cache Descriptor values + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Type Description
0x00 General Null descriptor, this byte contains no information
0x01 TLB Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
0x02 TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries
0x03 TLB Data TLB: 4 KByte pages, 4-way set associative, 64 entries
0x04 TLB Data TLB: 4 MByte pages, 4-way set associative, 8 entries
0x05 TLB Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
0x06 Cache 1st-level instruction cache: 8 KBytes, 4-way set associative, + 32 byte line size
0x08 Cache 1st-level instruction cache: 16 KBytes, 4-way set associative, + 32 byte line size
0x09 Cache 1st-level instruction cache: 32KBytes, 4-way set associative, + 64 byte line size
0x0A Cache 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0x0B TLB Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0x0C Cache 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0x0D Cache 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
0x0E Cache 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
0x1D Cache 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
0x21 Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
0x22 Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, + 2 lines per sector
0x23 Cache 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector
0x24 Cache 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
0x25 Cache 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector
0x29 Cache 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector
0x2C Cache 1st-level data cache: 32 KBytes, 8-way set associative, + 64 byte line size
0x30 Cache 1st-level instruction cache: 32 KBytes, 8-way set associative, + 64 byte line size
0x40 Cache No 2nd-level cache or, if processor contains a valid 2nd-level cache, + no 3rd-level cache
0x41 Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
0x42 Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
0x43 Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
0x44 Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
0x45 Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
0x46 Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
0x47 Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
0x48 Cache 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
0x49 Cache 3rd-level cache: 4MB, 16-way set associative, 64-byte line size + (Intel Xeon processor MP, Family 0FH, Model 06H)
+ 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
0x4A Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
0x4B Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
0x4C Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
0x4D Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
0x4E Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
0x4F TLB Instruction TLB: 4 KByte pages, 32 entries
0x50 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
0x51 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
0x52 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
0x55 TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
0x56 TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
0x57 TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries
0x59 TLB Data TLB0: 4 KByte pages, fully associative, 16 entries
0x5A TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
0x5B TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries
0x5C TLB Data TLB: 4 KByte and 4 MByte pages,128 entries
0x5D TLB Data TLB: 4 KByte and 4 MByte pages,256 entries
0x60 Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
0x61 TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries
0x63 TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, + 32 entries and a separate array with 1 GByte pages, 4-way set associative, + 4 entries
0x64 TLB Data TLB: 4 KByte pages, 4-way set associative, 512 entries
0x66 Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
0x67 Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
0x68 Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
0x6A Cache uTLB: 4 KByte pages, 8-way set associative, 64 entries
0x6B Cache DTLB: 4 KByte pages, 8-way set associative, 256 entries
0x6C Cache DTLB: 2M/4M pages, 8-way set associative, 128 entries
0x6D Cache DTLB: 1 GByte pages, fully associative, 16 entries
0x70 Cache Trace cache: 12 K-uop, 8-way set associative
0x71 Cache Trace cache: 16 K-uop, 8-way set associative
0x72 Cache Trace cache: 32 K-uop, 8-way set associative
0x76 TLB Instruction TLB: 2M/4M pages, fully associative, 8 entries
0x78 Cache 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
0x79 Cache 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector
0x7A Cache 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector
0x7B Cache 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector
0x7C Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, + 2 lines per sector
0x7D Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
0x7F Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
0x80 Cache 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
0x82 Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
0x83 Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
0x84 Cache 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
0x85 Cache 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
0x86 Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
0x87 Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
0xA0 DTLB DTLB: 4k pages, fully associative, 32 entries
0xB0 TLB Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
0xB1 TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
0xB2 TLB Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
0xB3 TLB Data TLB: 4 KByte pages, 4-way set associative, 128 entries
0xB4 TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries
0xB5 TLB Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
0xB6 TLB Instruction TLB: 4KByte pages, 8-way set associative, + 128 entries
0xBA TLB Data TLB1: 4 KByte pages, 4-way associative, 64 entries
0xC0 TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
0xC1 STLB Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, + 1024 entries
0xC2 DTLB DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries
0xC3 STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, + 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.
0xC4 DTLB DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
0xCA STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
0xD0 Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size
0xD1 Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size
0xD2 Cache 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size
0xD6 Cache 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size
0xD7 Cache 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size
0xD8 Cache 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size
0xDC Cache 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size
0xDD Cache 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size
0xDE Cache 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size
0xE2 Cache 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size
0xE3 Cache 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size
0xE4 Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
0xEA Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
0xEB Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
0xEC Cache 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
0xF0 Prefetch 64-Byte prefetching
0xF1 Prefetch 128-Byte prefetching
0xFE General CPUID leaf 2 does not report TLB descriptor information; use CPUID + leaf 18H to query TLB and other address translation parameters.
0xFF General CPUID leaf 2 does not report cache descriptor information, + use CPUID leaf 4 to query cache parameters
+**/ +#define CPUID_CACHE_INFO 0x02 + +/** + CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID + leaf #CPUID_CACHE_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:31; + /// + /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid. + /// if 1, then none of the cache descriptor bytes in the register are valid. + /// + UINT32 NotValid:1; + } Bits; + /// + /// Array of Cache and TLB descriptor bytes + /// + UINT8 CacheDescriptor[4]; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_CACHE_INFO_CACHE_TLB; + + +/** + CPUID Processor Serial Number + + Processor serial number (PSN) is not supported in the Pentium 4 processor + or later. On all models, use the PSN flag (returned using CPUID) to check + for PSN support before accessing the feature. + + @param EAX CPUID_SERIAL_NUMBER (0x03) + + @retval EAX Reserved. + @retval EBX Reserved. + @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in + Pentium III processor only; otherwise, the value in this + register is reserved.) + @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in + Pentium III processor only; otherwise, the value in this + register is reserved.) + + Example usage + @code + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx); + @endcode +**/ +#define CPUID_SERIAL_NUMBER 0x03 + + +/** + CPUID Cache Parameters + + @param EAX CPUID_CACHE_PARAMS (0x04) + @param ECX Cache Level. Valid values start at 0. Software can enumerate + the deterministic cache parameters for each level of the cache + hierarchy starting with an index value of 0, until the + parameters report the value associated with the CacheType + field in CPUID_CACHE_PARAMS_EAX is 0. + + @retval EAX Returns cache type information described by the type + CPUID_CACHE_PARAMS_EAX. + @retval EBX Returns cache line and associativity information described by + the type CPUID_CACHE_PARAMS_EBX. + @retval ECX Returns the number of sets in the cache. + @retval EDX Returns cache WINVD/INVD behavior described by the type + CPUID_CACHE_PARAMS_EDX. + + Example usage + @code + UINT32 CacheLevel; + CPUID_CACHE_PARAMS_EAX Eax; + CPUID_CACHE_PARAMS_EBX Ebx; + UINT32 Ecx; + CPUID_CACHE_PARAMS_EDX Edx; + + CacheLevel = 0; + do { + AsmCpuidEx ( + CPUID_CACHE_PARAMS, CacheLevel, + &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 + ); + CacheLevel++; + } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); + @endcode +**/ +#define CPUID_CACHE_PARAMS 0x04 + +/** + CPUID Cache Parameters Information returned in EAX for CPUID leaf + #CPUID_CACHE_PARAMS. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, + /// then there is no information for the requested cache level. + /// + UINT32 CacheType:5; + /// + /// [Bits 7:5] Cache level (Starts at 1). + /// + UINT32 CacheLevel:3; + /// + /// [Bit 8] Self Initializing cache level (does not need SW initialization). + /// + UINT32 SelfInitializingCache:1; + /// + /// [Bit 9] Fully Associative cache. + /// + UINT32 FullyAssociativeCache:1; + /// + /// [Bits 13:10] Reserved. + /// + UINT32 Reserved:4; + /// + /// [Bits 25:14] Maximum number of addressable IDs for logical processors + /// sharing this cache. + /// + /// Add one to the return value to get the result. + /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) + /// is the number of unique initial APIC IDs reserved for addressing + /// different logical processors sharing this cache. + /// + UINT32 MaximumAddressableIdsForLogicalProcessors:12; + /// + /// [Bits 31:26] Maximum number of addressable IDs for processor cores in + /// the physical package. + /// + /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) + /// is the number of unique Core_IDs reserved for addressing different + /// processor cores in a physical package. Core ID is a subset of bits of + /// the initial APIC ID. + /// The returned value is constant for valid initial values in ECX. Valid + /// ECX values start from 0. + /// + UINT32 MaximumAddressableIdsForProcessorCores:6; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_CACHE_PARAMS_EAX; + +/// +/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType +/// +#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00 +#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01 +#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02 +#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03 +/// +/// @} +/// + +/** + CPUID Cache Parameters Information returned in EBX for CPUID leaf + #CPUID_CACHE_PARAMS. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 11:0] System Coherency Line Size. Add one to the return value to + /// get the result. + /// + UINT32 LineSize:12; + /// + /// [Bits 21:12] Physical Line Partitions. Add one to the return value to + /// get the result. + /// + UINT32 LinePartitions:10; + /// + /// [Bits 31:22] Ways of associativity. Add one to the return value to get + /// the result. + /// + UINT32 Ways:10; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_CACHE_PARAMS_EBX; + +/** + CPUID Cache Parameters Information returned in EDX for CPUID leaf + #CPUID_CACHE_PARAMS. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Write-Back Invalidate/Invalidate. + /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level + /// caches for threads sharing this cache. + /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of + /// non-originating threads sharing this cache. + /// + UINT32 Invalidate:1; + /// + /// [Bit 1] Cache Inclusiveness. + /// 0 = Cache is not inclusive of lower cache levels. + /// 1 = Cache is inclusive of lower cache levels. + /// + UINT32 CacheInclusiveness:1; + /// + /// [Bit 2] Complex Cache Indexing. + /// 0 = Direct mapped cache. + /// 1 = A complex function is used to index the cache, potentially using all + /// address bits. + /// + UINT32 ComplexCacheIndexing:1; + UINT32 Reserved:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_CACHE_PARAMS_EDX; + + +/** + CPUID MONITOR/MWAIT Information + + @param EAX CPUID_MONITOR_MWAIT (0x05) + + @retval EAX Smallest monitor-line size in bytes described by the type + CPUID_MONITOR_MWAIT_EAX. + @retval EBX Largest monitor-line size in bytes described by the type + CPUID_MONITOR_MWAIT_EBX. + @retval ECX Enumeration of Monitor-Mwait extensions support described by + the type CPUID_MONITOR_MWAIT_ECX. + @retval EDX Sub C-states supported described by the type + CPUID_MONITOR_MWAIT_EDX. + + Example usage + @code + CPUID_MONITOR_MWAIT_EAX Eax; + CPUID_MONITOR_MWAIT_EBX Ebx; + CPUID_MONITOR_MWAIT_ECX Ecx; + CPUID_MONITOR_MWAIT_EDX Edx; + + AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_MONITOR_MWAIT 0x05 + +/** + CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf + #CPUID_MONITOR_MWAIT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's + /// monitor granularity). + /// + UINT32 SmallestMonitorLineSize:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MONITOR_MWAIT_EAX; + +/** + CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf + #CPUID_MONITOR_MWAIT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's + /// monitor granularity). + /// + UINT32 LargestMonitorLineSize:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MONITOR_MWAIT_EBX; + +/** + CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf + #CPUID_MONITOR_MWAIT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX, + /// and EDX are valid. + /// + UINT32 ExtensionsSupported:1; + /// + /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when + /// interrupts disabled. + /// + UINT32 InterruptAsBreak:1; + UINT32 Reserved:30; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MONITOR_MWAIT_ECX; + +/** + CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf + #CPUID_MONITOR_MWAIT. + + @note + The definition of C0 through C7 states for MWAIT extension are + processor-specific C-states, not ACPI C-states. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT. + /// + UINT32 C0States:4; + /// + /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT. + /// + UINT32 C1States:4; + /// + /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT. + /// + UINT32 C2States:4; + /// + /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT. + /// + UINT32 C3States:4; + /// + /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT. + /// + UINT32 C4States:4; + /// + /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT. + /// + UINT32 C5States:4; + /// + /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT. + /// + UINT32 C6States:4; + /// + /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT. + /// + UINT32 C7States:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MONITOR_MWAIT_EDX; + + +/** + CPUID Thermal and Power Management + + @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06) + + @retval EAX Thermal and power management features described by the type + CPUID_THERMAL_POWER_MANAGEMENT_EAX. + @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor + described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX. + @retval ECX Performance features described by the type + CPUID_THERMAL_POWER_MANAGEMENT_ECX. + @retval EDX Reserved. + + Example usage + @code + CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax; + CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx; + CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx; + + AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); + @endcode +**/ +#define CPUID_THERMAL_POWER_MANAGEMENT 0x06 + +/** + CPUID Thermal and Power Management Information returned in EAX for CPUID leaf + #CPUID_THERMAL_POWER_MANAGEMENT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Digital temperature sensor is supported if set. + /// + UINT32 DigitalTemperatureSensor:1; + /// + /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]). + /// + UINT32 TurboBoostTechnology:1; + /// + /// [Bit 2] APIC-Timer-always-running feature is supported if set. + /// + UINT32 ARAT:1; + UINT32 Reserved1:1; + /// + /// [Bit 4] Power limit notification controls are supported if set. + /// + UINT32 PLN:1; + /// + /// [Bit 5] Clock modulation duty cycle extension is supported if set. + /// + UINT32 ECMD:1; + /// + /// [Bit 6] Package thermal management is supported if set. + /// + UINT32 PTM:1; + /// + /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES, + /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set. + /// + UINT32 HWP:1; + /// + /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set. + /// + UINT32 HWP_Notification:1; + /// + /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set. + /// + UINT32 HWP_Activity_Window:1; + /// + /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set. + /// + UINT32 HWP_Energy_Performance_Preference:1; + /// + /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set. + /// + UINT32 HWP_Package_Level_Request:1; + UINT32 Reserved2:1; + /// + /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, + /// IA32_THREAD_STALL MSRs are supported if set. + /// + UINT32 HDC:1; + /// + /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available. + /// + UINT32 TurboBoostMaxTechnology30:1; + /// + /// [Bit 15] HWP Capabilities. + /// Highest Performance change is supported if set. + /// + UINT32 HWPCapabilities:1; + /// + /// [Bit 16] HWP PECI override is supported if set. + /// + UINT32 HWPPECIOverride:1; + /// + /// [Bit 17] Flexible HWP is supported if set. + /// + UINT32 FlexibleHWP:1; + /// + /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set. + /// + UINT32 FastAccessMode:1; + UINT32 Reserved4:1; + /// + /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set. + /// + UINT32 IgnoringIdleLogicalProcessorHWPRequest:1; + UINT32 Reserved5:11; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_THERMAL_POWER_MANAGEMENT_EAX; + +/** + CPUID Thermal and Power Management Information returned in EBX for CPUID leaf + #CPUID_THERMAL_POWER_MANAGEMENT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor. + /// + UINT32 InterruptThresholds:4; + UINT32 Reserved:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_THERMAL_POWER_MANAGEMENT_EBX; + +/** + CPUID Thermal and Power Management Information returned in ECX for CPUID leaf + #CPUID_THERMAL_POWER_MANAGEMENT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF + /// and IA32_APERF). The capability to provide a measure of delivered + /// processor performance (since last reset of the counters), as a percentage + /// of the expected processor performance when running at the TSC frequency. + /// + UINT32 HardwareCoordinationFeedback:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] If this bit is set, then the processor supports performance-energy + /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS + /// (1B0H). + /// + UINT32 PerformanceEnergyBias:1; + UINT32 Reserved2:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_THERMAL_POWER_MANAGEMENT_ECX; + + +/** + CPUID Structured Extended Feature Flags Enumeration + + @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) + @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00). + + @note + If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf + index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. + + @retval EAX The maximum input value for ECX to retrieve sub-leaf information. + @retval EBX Structured Extended Feature Flags described by the type + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX. + @retval ECX Structured Extended Feature Flags described by the type + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx; + UINT32 SubLeaf; + + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + &Eax, NULL, NULL, NULL + ); + for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + SubLeaf, + NULL, &Ebx.Uint32, &Ecx.Uint32, NULL + ); + } + @endcode +**/ +#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 + +/// +/// CPUID Structured Extended Feature Flags Enumeration sub-leaf +/// +#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00 + +/** + CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. + /// + UINT32 FSGSBASE:1; + /// + /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1. + /// + UINT32 IA32_TSC_ADJUST:1; + /// + /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT + /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS". + /// + UINT32 SGX:1; + /// + /// [Bit 3] If 1 indicates the processor supports the first group of advanced + /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT) + /// + UINT32 BMI1:1; + /// + /// [Bit 4] Hardware Lock Elision + /// + UINT32 HLE:1; + /// + /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions. + /// + UINT32 AVX2:1; + /// + /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1. + /// + UINT32 FDP_EXCPTN_ONLY:1; + /// + /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1. + /// + UINT32 SMEP:1; + /// + /// [Bit 8] If 1 indicates the processor supports the second group of + /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, + /// SARX, SHLX, SHRX) + /// + UINT32 BMI2:1; + /// + /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1. + /// + UINT32 EnhancedRepMovsbStosb:1; + /// + /// [Bit 10] If 1, supports INVPCID instruction for system software that + /// manages process-context identifiers. + /// + UINT32 INVPCID:1; + /// + /// [Bit 11] Restricted Transactional Memory + /// + UINT32 RTM:1; + /// + /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) + /// Monitoring capability if 1. + /// + UINT32 RDT_M:1; + /// + /// [Bit 13] Deprecates FPU CS and FPU DS values if 1. + /// + UINT32 DeprecateFpuCsDs:1; + /// + /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1. + /// + UINT32 MPX:1; + /// + /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) + /// Allocation capability if 1. + /// + UINT32 RDT_A:1; + /// + /// [Bit 16] AVX512F. + /// + UINT32 AVX512F:1; + /// + /// [Bit 17] AVX512DQ. + /// + UINT32 AVX512DQ:1; + /// + /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction. + /// + UINT32 RDSEED:1; + /// + /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX + /// instructions. + /// + UINT32 ADX:1; + /// + /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC + /// instructions) if 1. + /// + UINT32 SMAP:1; + /// + /// [Bit 21] AVX512_IFMA. + /// + UINT32 AVX512_IFMA:1; + UINT32 Reserved6:1; + /// + /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction. + /// + UINT32 CLFLUSHOPT:1; + /// + /// [Bit 24] If 1 indicates the processor supports the CLWB instruction. + /// + UINT32 CLWB:1; + /// + /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace + /// extensions. + /// + UINT32 IntelProcessorTrace:1; + /// + /// [Bit 26] AVX512PF. (Intel Xeon Phi only.). + /// + UINT32 AVX512PF:1; + /// + /// [Bit 27] AVX512ER. (Intel Xeon Phi only.). + /// + UINT32 AVX512ER:1; + /// + /// [Bit 28] AVX512CD. + /// + UINT32 AVX512CD:1; + /// + /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) + /// SHA Extensions) if 1. + /// + UINT32 SHA:1; + /// + /// [Bit 30] AVX512BW. + /// + UINT32 AVX512BW:1; + /// + /// [Bit 31] AVX512VL. + /// + UINT32 AVX512VL:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX; + +/** + CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction. + /// (Intel Xeon Phi only.) + /// + UINT32 PREFETCHWT1:1; + /// + /// [Bit 1] AVX512_VBMI. + /// + UINT32 AVX512_VBMI:1; + /// + /// [Bit 2] Supports user-mode instruction prevention if 1. + /// + UINT32 UMIP:1; + /// + /// [Bit 3] Supports protection keys for user-mode pages if 1. + /// + UINT32 PKU:1; + /// + /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the + /// RDPKRU/WRPKRU instructions). + /// + UINT32 OSPKE:1; + UINT32 Reserved5:9; + /// + /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.). + /// + UINT32 AVX512_VPOPCNTDQ:1; + UINT32 Reserved7:1; + /// + /// [Bits 16] Supports 5-level paging if 1. + /// + UINT32 FiveLevelPage:1; + /// + /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions + /// in 64-bit mode. + /// + UINT32 MAWAU:5; + /// + /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1. + /// + UINT32 RDPID:1; + UINT32 Reserved3:7; + /// + /// [Bit 30] Supports SGX Launch Configuration if 1. + /// + UINT32 SGX_LC:1; + UINT32 Reserved4:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX; + +/** + CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf + #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 1:0] Reserved. + /// + UINT32 Reserved1:2; + /// + /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.) + /// + UINT32 AVX512_4VNNIW:1; + /// + /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.) + /// + UINT32 AVX512_4FMAPS:1; + /// + /// [Bit 14:4] Reserved. + /// + UINT32 Reserved4:11; + /// + /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part. + /// + UINT32 Hybrid:1; + /// + /// [Bit 25:16] Reserved. + /// + UINT32 Reserved5:10; + /// + /// [Bit 26] Enumerates support for indirect branch restricted speculation + /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors + /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD + /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and + /// IA32_PRED_CMD[0] (IBPB). + /// + UINT32 EnumeratesSupportForIBRSAndIBPB:1; + /// + /// [Bit 27] Enumerates support for single thread indirect branch + /// predictors (STIBP). Processors that set this bit support the + /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1] + /// (STIBP). + /// + UINT32 EnumeratesSupportForSTIBP:1; + /// + /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit + /// support the IA32_FLUSH_CMD MSR. They allow software to set + /// IA32_FLUSH_CMD[0] (L1D_FLUSH). + /// + UINT32 EnumeratesSupportForL1D_FLUSH:1; + /// + /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR. + /// + UINT32 EnumeratesSupportForCapability:1; + /// + /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR. + /// + UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1; + /// + /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD). + /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow + /// software to set IA32_SPEC_CTRL[2] (SSBD). + /// + UINT32 EnumeratesSupportForSSBD:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX; + +/** + CPUID Direct Cache Access Information + + @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09) + + @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H). + @retval EBX Reserved. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + + AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL); + @endcode +**/ +#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09 + + +/** + CPUID Architectural Performance Monitoring + + @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A) + + @retval EAX Architectural Performance Monitoring information described by + the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX. + @retval EBX Architectural Performance Monitoring information described by + the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX. + @retval ECX Reserved. + @retval EDX Architectural Performance Monitoring information described by + the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX. + + Example usage + @code + CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax; + CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx; + CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx; + + AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32); + @endcode +**/ +#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A + +/** + CPUID Architectural Performance Monitoring EAX for CPUID leaf + #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 7:0] Version ID of architectural performance monitoring. + /// + UINT32 ArchPerfMonVerID:8; + /// + /// [Bits 15:8] Number of general-purpose performance monitoring counter + /// per logical processor. + /// + /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous + /// block of MSR address space. Each performance event select register is + /// paired with a corresponding performance counter in the 0C1H address + /// block. + /// + UINT32 PerformanceMonitorCounters:8; + /// + /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter. + /// + /// The bit width of an IA32_PMCx MSR. This the number of valid bits for + /// read operation. On write operations, the lower-order 32 bits of the MSR + /// may be written with any value, and the high-order bits are sign-extended + /// from the value of bit 31. + /// + UINT32 PerformanceMonitorCounterWidth:8; + /// + /// [Bits 31:24] Length of EBX bit vector to enumerate architectural + /// performance monitoring events. + /// + UINT32 EbxBitVectorLength:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX; + +/** + CPUID Architectural Performance Monitoring EBX for CPUID leaf + #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core cycle event not available if 1. + /// + UINT32 UnhaltedCoreCycles:1; + /// + /// [Bit 1] Instruction retired event not available if 1. + /// + UINT32 InstructionsRetired:1; + /// + /// [Bit 2] Reference cycles event not available if 1. + /// + UINT32 UnhaltedReferenceCycles:1; + /// + /// [Bit 3] Last-level cache reference event not available if 1. + /// + UINT32 LastLevelCacheReferences:1; + /// + /// [Bit 4] Last-level cache misses event not available if 1. + /// + UINT32 LastLevelCacheMisses:1; + /// + /// [Bit 5] Branch instruction retired event not available if 1. + /// + UINT32 BranchInstructionsRetired:1; + /// + /// [Bit 6] Branch mispredict retired event not available if 1. + /// + UINT32 AllBranchMispredictRetired:1; + UINT32 Reserved:25; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX; + +/** + CPUID Architectural Performance Monitoring EDX for CPUID leaf + #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Number of fixed-function performance counters + /// (if Version ID > 1). + /// + UINT32 FixedFunctionPerformanceCounters:5; + /// + /// [Bits 12:5] Bit width of fixed-function performance counters + /// (if Version ID > 1). + /// + UINT32 FixedFunctionPerformanceCounterWidth:8; + UINT32 Reserved1:2; + /// + /// [Bits 15] AnyThread deprecation. + /// + UINT32 AnyThreadDeprecation:1; + UINT32 Reserved2:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX; + + +/** + CPUID Extended Topology Information + + @note + CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first + checking for the existence of Leaf 1FH before using leaf 0BH. + Most of Leaf 0BH output depends on the initial value in ECX. The EDX output + of leaf 0BH is always valid and does not vary with input value in ECX. Output + value in ECX[7:0] always equals input value in ECX[7:0]. + Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index + enumerates a higher-level topological entity in hierarchical order. + For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and + EBX will return 0. + If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], + other input values with ECX > n also return 0 in ECX[15:8]. + + @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B) + @param ECX Level number + + @retval EAX Extended topology information described by the type + CPUID_EXTENDED_TOPOLOGY_EAX. + @retval EBX Extended topology information described by the type + CPUID_EXTENDED_TOPOLOGY_EBX. + @retval ECX Extended topology information described by the type + CPUID_EXTENDED_TOPOLOGY_ECX. + @retval EDX x2APIC ID the current logical processor. + + Example usage + @code + CPUID_EXTENDED_TOPOLOGY_EAX Eax; + CPUID_EXTENDED_TOPOLOGY_EBX Ebx; + CPUID_EXTENDED_TOPOLOGY_ECX Ecx; + UINT32 Edx; + UINT32 LevelNumber; + + LevelNumber = 0; + do { + AsmCpuidEx ( + CPUID_EXTENDED_TOPOLOGY, LevelNumber, + &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx + ); + LevelNumber++; + } while (Eax.Bits.ApicIdShift != 0); + @endcode +**/ +#define CPUID_EXTENDED_TOPOLOGY 0x0B + +/** + CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique + /// topology ID of the next level type. All logical processors with the + /// same next level ID share current level. + /// + /// @note + /// Software should use this field (EAX[4:0]) to enumerate processor + /// topology of the system. + /// + UINT32 ApicIdShift:5; + UINT32 Reserved:27; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_TOPOLOGY_EAX; + +/** + CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Number of logical processors at this level type. The number + /// reflects configuration as shipped by Intel. + /// + /// @note + /// Software must not use EBX[15:0] to enumerate processor topology of the + /// system. This value in this field (EBX[15:0]) is only intended for + /// display/diagnostic purposes. The actual number of logical processors + /// available to BIOS/OS/Applications may be different from the value of + /// EBX[15:0], depending on software and platform hardware configurations. + /// + UINT32 LogicalProcessors:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_TOPOLOGY_EBX; + +/** + CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Level number. Same value in ECX input. + /// + UINT32 LevelNumber:8; + /// + /// [Bits 15:8] Level type. + /// + /// @note + /// The value of the "level type" field is not related to level numbers in + /// any way, higher "level type" values do not mean higher levels. + /// + UINT32 LevelType:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_TOPOLOGY_ECX; + +/// +/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType +/// +#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00 +#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01 +#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02 +/// +/// @} +/// + + +/** + CPUID Extended State Information + + @param EAX CPUID_EXTENDED_STATE (0x0D) + @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00). + CPUID_EXTENDED_STATE_SUB_LEAF (0x01). + CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). + Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR. +**/ +#define CPUID_EXTENDED_STATE 0x0D + +/** + CPUID Extended State Information Main Leaf + + @param EAX CPUID_EXTENDED_STATE (0x0D) + @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00) + + @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] + can be set to 1 only if EAX[n] is 1. The format of the extended + state main leaf is described by the type + CPUID_EXTENDED_STATE_MAIN_LEAF_EAX. + @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save + area) required by enabled features in XCR0. May be different than + ECX if some features at the end of the XSAVE save area are not + enabled. + @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save + area) of the XSAVE/XRSTOR save area required by all supported + features in the processor, i.e., all the valid bit fields in XCR0. + @retval EDX Reports the supported bits of the upper 32 bits of XCR0. + XCR0[n+32] can be set to 1 only if EDX[n] is 1. + + Example usage + @code + CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuidEx ( + CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, + &Eax.Uint32, &Ebx, &Ecx, &Edx + ); + @endcode +**/ +#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00 + +/** + CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, + sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 state. + /// + UINT32 x87:1; + /// + /// [Bit 1] SSE state. + /// + UINT32 SSE:1; + /// + /// [Bit 2] AVX state. + /// + UINT32 AVX:1; + /// + /// [Bits 4:3] MPX state. + /// + UINT32 MPX:2; + /// + /// [Bits 7:5] AVX-512 state. + /// + UINT32 AVX_512:3; + /// + /// [Bit 8] Used for IA32_XSS. + /// + UINT32 IA32_XSS:1; + /// + /// [Bit 9] PKRU state. + /// + UINT32 PKRU:1; + UINT32 Reserved1:3; + /// + /// [Bit 13] Used for IA32_XSS, part 2. + /// + UINT32 IA32_XSS_2:1; + UINT32 Reserved2:18; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX; + +/** + CPUID Extended State Information Sub Leaf + + @param EAX CPUID_EXTENDED_STATE (0x0D) + @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01) + + @retval EAX The format of the extended state sub-leaf is described by the + type CPUID_EXTENDED_STATE_SUB_LEAF_EAX. + @retval EBX The size in bytes of the XSAVE area containing all states + enabled by XCRO | IA32_XSS. + @retval ECX The format of the extended state sub-leaf is described by the + type CPUID_EXTENDED_STATE_SUB_LEAF_ECX. + @retval EDX Reports the supported bits of the upper 32 bits of the + IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1. + + Example usage + @code + CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx; + UINT32 Edx; + + AsmCpuidEx ( + CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, + &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx + ); + @endcode +**/ +#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01 + +/** + CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, + sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] XSAVEOPT is available. + /// + UINT32 XSAVEOPT:1; + /// + /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set. + /// + UINT32 XSAVEC:1; + /// + /// [Bit 2] Supports XGETBV with ECX = 1 if set. + /// + UINT32 XGETBV:1; + /// + /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set. + /// + UINT32 XSAVES:1; + UINT32 Reserved:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_STATE_SUB_LEAF_EAX; + +/** + CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, + sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Used for XCR0. + /// + UINT32 XCR0:1; + /// + /// [Bit 8] PT STate. + /// + UINT32 PT:1; + /// + /// [Bit 9] Used for XCR0. + /// + UINT32 XCR0_1:1; + UINT32 Reserved1:3; + /// + /// [Bit 13] HWP state. + /// + UINT32 HWPState:1; + UINT32 Reserved8:18; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_STATE_SUB_LEAF_ECX; + +/** + CPUID Extended State Information Size and Offset Sub Leaf + + @note + Leaf 0DH output depends on the initial value in ECX. + Each sub-leaf index (starting at position 2) is supported if it corresponds to + a supported bit in either the XCR0 register or the IA32_XSS MSR. + If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf + n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 + returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0 + returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32]. + + @param EAX CPUID_EXTENDED_STATE (0x0D) + @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based + on supported bits in XCR0 or IA32_XSS_MSR. + + @retval EAX The size in bytes (from the offset specified in EBX) of the save + area for an extended state feature associated with a valid + sub-leaf index, n. + @retval EBX The offset in bytes of this extended state component's save area + from the beginning of the XSAVE/XRSTOR area. This field reports + 0 if the sub-leaf index, n, does not map to a valid bit in the + XCR0 register. + @retval ECX The format of the extended state components's save area as + described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX. + This field reports 0 if the sub-leaf index, n, is invalid. + @retval EDX This field reports 0 if the sub-leaf index, n, is invalid; + otherwise it is reserved. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx; + UINT32 Edx; + UINTN SubLeaf; + + for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { + AsmCpuidEx ( + CPUID_EXTENDED_STATE, SubLeaf, + &Eax, &Ebx, &Ecx.Uint32, &Edx + ); + } + @endcode +**/ +#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02 + +/** + CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, + sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is + /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported + /// in XCR0. + /// + UINT32 XSS:1; + /// + /// [Bit 1] is set if, when the compacted format of an XSAVE area is used, + /// this extended state component located on the next 64-byte boundary + /// following the preceding state component (otherwise, it is located + /// immediately following the preceding state component). + /// + UINT32 Compacted:1; + UINT32 Reserved:30; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX; + + +/** + CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information + + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01). + +**/ +#define CPUID_INTEL_RDT_MONITORING 0x0F + +/** + CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information + Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00) + + @retval EAX Reserved. + @retval EBX Maximum range (zero-based) of RMID within this physical + processor of all types. + @retval ECX Reserved. + @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by + the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX. + + Example usage + @code + UINT32 Ebx; + CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, + NULL, &Ebx, NULL, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00 + +/** + CPUID Intel RDT Monitoring Information EDX for CPUID leaf + #CPUID_INTEL_RDT_MONITORING, sub-leaf + #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1. + /// + UINT32 L3CacheRDT_M:1; + UINT32 Reserved2:30; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX; + +/** + CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01) + + @retval EAX Reserved. + @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). + @retval ECX Maximum range (zero-based) of RMID of this resource type. + @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the + type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX. + + Example usage + @code + UINT32 Ebx; + UINT32 Ecx; + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, + NULL, &Ebx, &Ecx, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01 + +/** + CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf + #CPUID_INTEL_RDT_MONITORING, sub-leaf + #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Supports L3 occupancy monitoring if 1. + /// + UINT32 L3CacheOccupancyMonitoring:1; + /// + /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1. + /// + UINT32 L3CacheTotalBandwidthMonitoring:1; + /// + /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1. + /// + UINT32 L3CacheLocalBandwidthMonitoring:1; + UINT32 Reserved:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX; + + +/** + CPUID Intel Resource Director Technology (Intel RDT) Allocation Information + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10). + @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02). +**/ +#define CPUID_INTEL_RDT_ALLOCATION 0x10 + +/** + Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). + + @retval EAX Reserved. + @retval EBX L3 and L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, + NULL, &Ebx.Uint32, NULL, NULL + ); + @endcode +**/ +#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00 + +/** + CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Supports L3 Cache Allocation Technology if 1. + /// + UINT32 L3CacheAllocation:1; + /// + /// [Bit 2] Supports L2 Cache Allocation Technology if 1. + /// + UINT32 L2CacheAllocation:1; + /// + /// [Bit 3] Supports Memory Bandwidth Allocation if 1. + /// + UINT32 MemoryBandwidth:1; + UINT32 Reserved3:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX; + + +/** + L3 Cache Allocation Technology Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01) + + @retval EAX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX. + @retval EBX Bit-granular map of isolation/contention of allocation units. + @retval ECX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX. + @retval EDX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, + &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 + +/** + CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID + /// using minus-one notation. + /// + UINT32 CapacityLength:5; + UINT32 Reserved:27; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX; + +/** + CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved3:2; + /// + /// [Bit 2] Code and Data Prioritization Technology supported if 1. + /// + UINT32 CodeDataPrioritization:1; + UINT32 Reserved2:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX; + +/** + CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Highest COS number supported for this ResID. + /// + UINT32 HighestCosNumber:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX; + +/** + L2 Cache Allocation Technology Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02) + + @retval EAX RESID L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX. + @retval EBX Bit-granular map of isolation/contention of allocation units. + @retval ECX Reserved. + @retval EDX RESID L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, + &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02 + +/** + CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID + /// using minus-one notation. + /// + UINT32 CapacityLength:5; + UINT32 Reserved:27; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX; + +/** + CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Highest COS number supported for this ResID. + /// + UINT32 HighestCosNumber:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX; + +/** + Memory Bandwidth Allocation Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03) + + @retval EAX RESID memory bandwidth Allocation Technology information + described by the type + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX. + @retval EBX Reserved. + @retval ECX RESID memory bandwidth Allocation Technology information + described by the type + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX. + @retval EDX RESID memory bandwidth Allocation Technology information + described by the type + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx; + CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; + + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, + &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 + +/** + CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 11:0] Reports the maximum MBA throttling value supported for + /// the corresponding ResID using minus-one notation. + /// + UINT32 MaximumMBAThrottling:12; + UINT32 Reserved:20; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX; + +/** + CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] Reserved. + /// + UINT32 Reserved1:2; + /// + /// [Bits 3] Reports whether the response of the delay values is linear. + /// + UINT32 Liner:1; + UINT32 Reserved2:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX; + +/** + CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Highest COS number supported for this ResID. + /// + UINT32 HighestCosNumber:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX; + +/** + Intel SGX resource capability and configuration. + See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves". + + If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying + CPUID with EAX=12H on Intel SGX resource capability and configuration. + + @param EAX CPUID_INTEL_SGX (0x12) + @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00). + CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01). + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02). + Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0]) + until the sub-leaf type is invalid. + +**/ +#define CPUID_INTEL_SGX 0x12 + +/** + Sub-Leaf 0 Enumeration of Intel SGX Capabilities. + Enumerates Intel SGX capability, including enclave instruction opcode support. + + @param EAX CPUID_INTEL_SGX (0x12) + @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00) + + @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is + described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX. + @retval EBX MISCSELECT: Reports the bit vector of supported extended features + that can be written to the MISC region of the SSA. + @retval ECX Reserved. + @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is + described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, + &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00 + +/** + Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX, + sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported. + /// + UINT32 SGX1:1; + /// + /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported. + /// + UINT32 SGX2:1; + UINT32 Reserved1:3; + /// + /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves + /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT. + /// + UINT32 ENCLV:1; + /// + /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC, + /// ERDINFO, ELDBC, and ELDUC. + /// + UINT32 ENCLS:1; + UINT32 Reserved2:25; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX; + +/** + Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX, + sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes + /// when not in 64-bit mode. + /// + UINT32 MaxEnclaveSize_Not64:8; + /// + /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes + /// when operating in 64-bit mode. + /// + UINT32 MaxEnclaveSize_64:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX; + + +/** + Sub-Leaf 1 Enumeration of Intel SGX Capabilities. + Enumerates Intel SGX capability of processor state configuration and enclave + configuration in the SECS structure. + + @param EAX CPUID_INTEL_SGX (0x12) + @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01) + + @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can + set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE + only if EAX[n] is 1, where n < 32. + @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can + set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE + only if EBX[n] is 1, where n < 32. + @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can + set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE + only if ECX[n] is 1, where n < 32. + @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can + set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE + only if EDX[n] is 1, where n < 32. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuidEx ( + CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, + &Eax, &Ebx, &Ecx, &Edx + ); + @endcode +**/ +#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01 + + +/** + Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources. + Enumerates available EPC resources. + + @param EAX CPUID_INTEL_SGX (0x12) + @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02) + + @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX + Resources is described by the type + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX. + @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX + Resources is described by the type + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX. + @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX + Resources is described by the type + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX. + @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX + Resources is described by the type + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax; + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx; + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx; + CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF, + &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02 + +/** + Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID + leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 3:0] Sub-leaf-type encoding. + /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0. + /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC) + /// in EBX:EAX and EDX:ECX. + /// All other encoding are reserved. + /// + UINT32 SubLeafType:4; + UINT32 Reserved:8; + /// + /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of + /// the base of the EPC section. + /// + UINT32 LowAddressOfEpcSection:20; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX; + +/** + Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID + leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of + /// the base of the EPC section. + /// + UINT32 HighAddressOfEpcSection:20; + UINT32 Reserved:12; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX; + +/** + Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID + leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 3:0] The EPC section encoding. + /// 0000b: Not valid. + /// 0001b: The EPC section is confidentiality, integrity and replay protected. + /// All other encoding are reserved. + /// + UINT32 EpcSection:4; + UINT32 Reserved:8; + /// + /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the + /// corresponding EPC section within the Processor Reserved Memory. + /// + UINT32 LowSizeOfEpcSection:20; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX; + +/** + Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID + leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the + /// corresponding EPC section within the Processor Reserved Memory. + /// + UINT32 HighSizeOfEpcSection:20; + UINT32 Reserved:12; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX; + + +/** + CPUID Intel Processor Trace Information + + @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14) + @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00). + CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01). + +**/ +#define CPUID_INTEL_PROCESSOR_TRACE 0x14 + +/** + CPUID Intel Processor Trace Information Main Leaf + + @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) + @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00) + + @retval EAX Reports the maximum sub-leaf supported in leaf 14H. + @retval EBX Returns Intel processor trace information described by the + type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX. + @retval ECX Returns Intel processor trace information described by the + type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx; + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; + + AsmCpuidEx ( + CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, + &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL + ); + @endcode +**/ +#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00 + +/** + CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, + sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, + /// and that IA32_RTIT_CR3_MATCH MSR can be accessed. + /// + UINT32 Cr3Filter:1; + /// + /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate + /// Mode. + /// + UINT32 ConfigurablePsb:1; + /// + /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, + /// and preservation of Intel PT MSRs across warm reset. + /// + UINT32 IpTraceStopFiltering:1; + /// + /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of + /// COFI-based packets. + /// + UINT32 Mtc:1; + /// + /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set + /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE + /// can generate packets. + /// + UINT32 PTWrite:1; + /// + /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set + /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet + /// generation. + /// + UINT32 PowerEventTrace:1; + UINT32 Reserved:26; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX; + +/** + CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, + sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence + /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and + /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed. + /// + UINT32 RTIT:1; + /// + /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to + /// the maximum allowed by the MaskOrTableOffset field of + /// IA32_RTIT_OUTPUT_MASK_PTRS. + /// + UINT32 ToPA:1; + /// + /// [Bit 2] If 1, indicates support of Single-Range Output scheme. + /// + UINT32 SingleRangeOutput:1; + /// + /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem. + /// + UINT32 TraceTransportSubsystem:1; + UINT32 Reserved:27; + /// + /// [Bit 31] If 1, generated packets which contain IP payloads have LIP + /// values, which include the CS base component. + /// + UINT32 LIP:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX; + + +/** + CPUID Intel Processor Trace Information Sub-leaf + + @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14) + @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01) + + @retval EAX Returns Intel processor trace information described by the + type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX. + @retval EBX Returns Intel processor trace information described by the + type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + UINT32 MaximumSubLeaf; + UINT32 SubLeaf; + CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax; + CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx; + + AsmCpuidEx ( + CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, + &MaximumSubLeaf, NULL, NULL, NULL + ); + + for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { + AsmCpuidEx ( + CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, + &Eax.Uint32, &Ebx.Uint32, NULL, NULL + ); + } + @endcode +**/ +#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01 + +/** + CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, + sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Number of configurable Address Ranges for filtering. + /// + UINT32 ConfigurableAddressRanges:3; + UINT32 Reserved:13; + /// + /// [Bits 31:16] Bitmap of supported MTC period encodings + /// + UINT32 MtcPeriodEncodings:16; + + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX; + +/** + CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, + sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings. + /// + UINT32 CycleThresholdEncodings:16; + /// + /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings. + /// + UINT32 PsbFrequencyEncodings:16; + + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX; + + +/** + CPUID Time Stamp Counter and Nominal Core Crystal Clock Information + + @note + If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. + EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core + crystal clock frequency. + If ECX is 0, the nominal core crystal clock frequency is not enumerated. + "TSC frequency" = "core crystal clock frequency" * EBX/EAX. + The core crystal clock may differ from the reference clock, bus clock, or core + clock frequencies. + + @param EAX CPUID_TIME_STAMP_COUNTER (0x15) + + @retval EAX An unsigned integer which is the denominator of the + TSC/"core crystal clock" ratio + @retval EBX An unsigned integer which is the numerator of the + TSC/"core crystal clock" ratio. + @retval ECX An unsigned integer which is the nominal frequency + of the core crystal clock in Hz. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + + AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); + @endcode +**/ +#define CPUID_TIME_STAMP_COUNTER 0x15 + + +/** + CPUID Processor Frequency Information + + @note + Data is returned from this interface in accordance with the processor's + specification and does not reflect actual values. Suitable use of this data + includes the display of processor information in like manner to the processor + brand string and for determining the appropriate range to use when displaying + processor information e.g. frequency history graphs. The returned information + should not be used for any other purpose as the returned information does not + accurately correlate to information / counters returned by other processor + interfaces. While a processor may support the Processor Frequency Information + leaf, fields that return a value of zero are not supported. + + @param EAX CPUID_TIME_STAMP_COUNTER (0x16) + + @retval EAX Returns processor base frequency information described by the + type CPUID_PROCESSOR_FREQUENCY_EAX. + @retval EBX Returns maximum frequency information described by the type + CPUID_PROCESSOR_FREQUENCY_EBX. + @retval ECX Returns bus frequency information described by the type + CPUID_PROCESSOR_FREQUENCY_ECX. + @retval EDX Reserved. + + Example usage + @code + CPUID_PROCESSOR_FREQUENCY_EAX Eax; + CPUID_PROCESSOR_FREQUENCY_EBX Ebx; + CPUID_PROCESSOR_FREQUENCY_ECX Ecx; + + AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL); + @endcode +**/ +#define CPUID_PROCESSOR_FREQUENCY 0x16 + +/** + CPUID Processor Frequency Information EAX for CPUID leaf + #CPUID_PROCESSOR_FREQUENCY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Processor Base Frequency (in MHz). + /// + UINT32 ProcessorBaseFrequency:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_PROCESSOR_FREQUENCY_EAX; + +/** + CPUID Processor Frequency Information EBX for CPUID leaf + #CPUID_PROCESSOR_FREQUENCY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Maximum Frequency (in MHz). + /// + UINT32 MaximumFrequency:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_PROCESSOR_FREQUENCY_EBX; + +/** + CPUID Processor Frequency Information ECX for CPUID leaf + #CPUID_PROCESSOR_FREQUENCY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Bus (Reference) Frequency (in MHz). + /// + UINT32 BusFrequency:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_PROCESSOR_FREQUENCY_ECX; + + +/** + CPUID SoC Vendor Information + + @param EAX CPUID_SOC_VENDOR (0x17) + @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) + CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) + CPUID_SOC_VENDOR_BRAND_STRING1 (0x02) + CPUID_SOC_VENDOR_BRAND_STRING1 (0x03) + + @note + Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String + is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC + Vendor Brand String is constructed by concatenating in ascending order of + EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3. + +**/ +#define CPUID_SOC_VENDOR 0x17 + +/** + CPUID SoC Vendor Information + + @param EAX CPUID_SOC_VENDOR (0x17) + @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00) + + @retval EAX MaxSOCID_Index. Reports the maximum input value of supported + sub-leaf in leaf 17H. + @retval EBX Returns SoC Vendor information described by the type + CPUID_SOC_VENDOR_MAIN_LEAF_EBX. + @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC + projects. + @retval EDX Stepping ID. A unique number within an SOC project that an SOC + vendor assigns. + + Example usage + @code + UINT32 Eax; + CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuidEx ( + CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, + &Eax, &Ebx.Uint32, &Ecx, &Edx + ); + @endcode +**/ +#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00 + +/** + CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf + #CPUID_SOC_VENDOR_MAIN_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] SOC Vendor ID. + /// + UINT32 SocVendorId:16; + /// + /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry + /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is + /// assigned by Intel. + /// + UINT32 IsVendorScheme:1; + UINT32 Reserved:15; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_SOC_VENDOR_MAIN_LEAF_EBX; + +/** + CPUID SoC Vendor Information + + @param EAX CPUID_SOC_VENDOR (0x17) + @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) + + @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + + Example usage + @code + CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; + + AsmCpuidEx ( + CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, + &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01 + +/** + CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1, + #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3. +**/ +typedef union { + /// + /// 4 UTF-8 characters of Soc Vendor Brand String + /// + CHAR8 BrandString[4]; + /// + /// All fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_SOC_VENDOR_BRAND_STRING_DATA; + +/** + CPUID SoC Vendor Information + + @param EAX CPUID_SOC_VENDOR (0x17) + @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02) + + @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + + Example usage + @code + CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; + + AsmCpuidEx ( + CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, + &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02 + +/** + CPUID SoC Vendor Information + + @param EAX CPUID_SOC_VENDOR (0x17) + @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03) + + @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type + CPUID_SOC_VENDOR_BRAND_STRING_DATA. + + Example usage + @code + CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx; + CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx; + + AsmCpuidEx ( + CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, + &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03 + +/** + CPUID Deterministic Address Translation Parameters + + @note + Each sub-leaf enumerates a different address translation structure. + If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf + index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A + sub-leaf index is also invalid if EDX[4:0] returns 0. + Valid sub-leaves do not need to be contiguous or in any particular order. A + valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or + than a valid sub-leaf of a higher or lower-level structure. + * Some unified TLBs will allow a single TLB entry to satisfy data read/write + and instruction fetches. Others will require separate entries (e.g., one + loaded on data read/write and another loaded on an instruction fetch). + Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual + for details of a particular product. + ** Add one to the return value to get the result. + + @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) + @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) + CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*) + +**/ +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 + +/** + CPUID Deterministic Address Translation Parameters + + @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18) + @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) + + @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H. + @retval EBX Returns Deterministic Address Translation Parameters described by + the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX. + @retval ECX Number of Sets. + @retval EDX Returns Deterministic Address Translation Parameters described by + the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX. + + Example usage + @code + UINT32 Eax; + CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx; + UINT32 Ecx; + CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx; + + AsmCpuidEx ( + CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, + CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, + &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00 + +/** + CPUID Deterministic Address Translation Parameters EBX for CPUID leafs. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] 4K page size entries supported by this structure. + /// + UINT32 Page4K:1; + /// + /// [Bits 1] 2MB page size entries supported by this structure. + /// + UINT32 Page2M:1; + /// + /// [Bits 2] 4MB page size entries supported by this structure. + /// + UINT32 Page4M:1; + /// + /// [Bits 3] 1 GB page size entries supported by this structure. + /// + UINT32 Page1G:1; + /// + /// [Bits 7:4] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical + /// processors sharing this structure) + /// + UINT32 Partitioning:3; + /// + /// [Bits 15:11] Reserved. + /// + UINT32 Reserved2:5; + /// + /// [Bits 31:16] W = Ways of associativity. + /// + UINT32 Way:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX; + +/** + CPUID Deterministic Address Translation Parameters EDX for CPUID leafs. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Translation cache type field. + /// + UINT32 TranslationCacheType:5; + /// + /// [Bits 7:5] Translation cache level (starts at 1). + /// + UINT32 TranslationCacheLevel:3; + /// + /// [Bits 8] Fully associative structure. + /// + UINT32 FullyAssociative:1; + /// + /// [Bits 13:9] Reserved. + /// + UINT32 Reserved1:5; + /// + /// [Bits 25:14] Maximum number of addressable IDs for logical + /// processors sharing this translation cache. + /// + UINT32 MaximumNum:12; + /// + /// [Bits 31:26] Reserved. + /// + UINT32 Reserved2:6; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX; + +/// +/// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType +/// +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00 +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01 +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02 +#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03 +/// +/// @} +/// + + +/** + CPUID Hybrid Information Enumeration Leaf + + @param EAX CPUID_HYBRID_INFORMATION (0x1A) + @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00). + + @retval EAX Enumerates the native model ID and core type described + by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX + @retval EBX Reserved. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax; + + AsmCpuidEx ( + CPUID_HYBRID_INFORMATION, + CPUID_HYBRID_INFORMATION_MAIN_LEAF, + &Eax, NULL, NULL, NULL + ); + @endcode + +**/ +#define CPUID_HYBRID_INFORMATION 0x1A + +/// +/// CPUID Hybrid Information Enumeration main leaf +/// +#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00 + +/** + CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION, + main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 23:0] Native model ID of the core. + /// + /// The core-type and native mode ID can be used to uniquely identify + /// the microarchitecture of the core.This native model ID is not unique + /// across core types, and not related to the model ID reported in CPUID + /// leaf 01H, and does not identify the SOC. + /// + UINT32 NativeModelId:24; + /// + /// [Bit 31:24] Core type + /// + UINT32 CoreType:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX; + +/// +/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType +/// +#define CPUID_CORE_TYPE_INTEL_ATOM 0x20 +#define CPUID_CORE_TYPE_INTEL_CORE 0x40 +/// +/// @} +/// + + +/** + CPUID V2 Extended Topology Enumeration Leaf + + @note + CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking + for the existence of Leaf 1FH and using this if available. + Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf + 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] + always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each + subsequent higher sub-leaf index enumerates a higher-level topological entity in + hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; + EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of + 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8]. + + Software should use this field (EAX[4:0]) to enumerate processor topology of the system. + Software must not use EBX[15:0] to enumerate processor topology of the system. This value + in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual + number of logical processors available to BIOS/OS/Applications may be different from the + value of EBX[15:0], depending on software and platform hardware configurations. + + @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F) + @param ECX Level number + +**/ +#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F + +/// +/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType +/// The value of the "level type" field is not related to level numbers in +/// any way, higher "level type" values do not mean higher levels. +/// +#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03 +#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04 +#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05 +/// +/// @} +/// + +/** + CPUID Extended Function + + @param EAX CPUID_EXTENDED_FUNCTION (0x80000000) + + @retval EAX Maximum Input Value for Extended Function CPUID Information. + @retval EBX Reserved. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + + AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); + @endcode +**/ +#define CPUID_EXTENDED_FUNCTION 0x80000000 + + +/** + CPUID Extended Processor Signature and Feature Bits + + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX CPUID_EXTENDED_CPU_SIG. + @retval EBX Reserved. + @retval ECX Extended Processor Signature and Feature Bits information + described by the type CPUID_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Processor Signature and Feature Bits information + described by the type CPUID_EXTENDED_CPU_SIG_EDX. + + Example usage + @code + UINT32 Eax; + CPUID_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_EXTENDED_CPU_SIG_EDX Edx; + + AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_EXTENDED_CPU_SIG 0x80000001 + +/** + CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF:1; + UINT32 Reserved1:4; + /// + /// [Bit 5] LZCNT. + /// + UINT32 LZCNT:1; + UINT32 Reserved2:2; + /// + /// [Bit 8] PREFETCHW. + /// + UINT32 PREFETCHW:1; + UINT32 Reserved3:23; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:11; + /// + /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode. + /// + UINT32 SYSCALL_SYSRET:1; + UINT32 Reserved2:8; + /// + /// [Bit 20] Execute Disable Bit available. + /// + UINT32 NX:1; + UINT32 Reserved3:5; + /// + /// [Bit 26] 1-GByte pages are available if 1. + /// + UINT32 Page1GB:1; + /// + /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1. + /// + UINT32 RDTSCP:1; + UINT32 Reserved4:1; + /// + /// [Bit 29] Intel(R) 64 Architecture available if 1. + /// + UINT32 LM:1; + UINT32 Reserved5:2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_CPU_SIG_EDX; + + +/** + CPUID Processor Brand String + + @param EAX CPUID_BRAND_STRING1 (0x80000002) + + @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA. + @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + + Example usage + @code + CPUID_BRAND_STRING_DATA Eax; + CPUID_BRAND_STRING_DATA Ebx; + CPUID_BRAND_STRING_DATA Ecx; + CPUID_BRAND_STRING_DATA Edx; + + AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_BRAND_STRING1 0x80000002 + +/** + CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1, + #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3. +**/ +typedef union { + /// + /// 4 ASCII characters of Processor Brand String + /// + CHAR8 BrandString[4]; + /// + /// All fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_BRAND_STRING_DATA; + +/** + CPUID Processor Brand String + + @param EAX CPUID_BRAND_STRING2 (0x80000003) + + @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + + Example usage + @code + CPUID_BRAND_STRING_DATA Eax; + CPUID_BRAND_STRING_DATA Ebx; + CPUID_BRAND_STRING_DATA Ecx; + CPUID_BRAND_STRING_DATA Edx; + + AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_BRAND_STRING2 0x80000003 + +/** + CPUID Processor Brand String + + @param EAX CPUID_BRAND_STRING3 (0x80000004) + + @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA. + + Example usage + @code + CPUID_BRAND_STRING_DATA Eax; + CPUID_BRAND_STRING_DATA Ebx; + CPUID_BRAND_STRING_DATA Ecx; + CPUID_BRAND_STRING_DATA Edx; + + AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ +#define CPUID_BRAND_STRING3 0x80000004 + + +/** + CPUID Extended Cache information + + @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006) + + @retval EAX Reserved. + @retval EBX Reserved. + @retval ECX Extended cache information described by the type + CPUID_EXTENDED_CACHE_INFO_ECX. + @retval EDX Reserved. + + Example usage + @code + CPUID_EXTENDED_CACHE_INFO_ECX Ecx; + + AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL); + @endcode +**/ +#define CPUID_EXTENDED_CACHE_INFO 0x80000006 + +/** + CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Cache line size in bytes. + /// + UINT32 CacheLineSize:8; + UINT32 Reserved:4; + /// + /// [Bits 15:12] L2 Associativity field. Supported values are in the range + /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to + /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL + /// + UINT32 L2Associativity:4; + /// + /// [Bits 31:16] Cache size in 1K units. + /// + UINT32 CacheSize:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_CACHE_INFO_ECX; + +/// +/// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity +/// +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08 +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E +#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F +/// +/// @} +/// + +/** + CPUID Extended Time Stamp Counter information + + @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007) + + @retval EAX Reserved. + @retval EBX Reserved. + @retval ECX Reserved. + @retval EDX Extended time stamp counter (TSC) information described by the + type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX. + + Example usage + @code + CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx; + + AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32); + @endcode +**/ +#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007 + +/** + CPUID Extended Time Stamp Counter information EDX for CPUID leaf + #CPUID_EXTENDED_TIME_STAMP_COUNTER. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bit 8] Invariant TSC available if 1. + /// + UINT32 InvariantTsc:1; + UINT32 Reserved2:23; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX; + + +/** + CPUID Linear Physical Address Size + + @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + + @retval EAX Linear/Physical Address Size described by the type + CPUID_VIR_PHY_ADDRESS_SIZE_EAX. + @retval EBX Reserved. + @retval ECX Reserved. + @retval EDX Reserved. + + Example usage + @code + CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax; + + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL); + @endcode +**/ +#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of physical address bits. + /// + /// @note + /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address + /// number supported should come from this field. + /// + UINT32 PhysicalAddressBits:8; + /// + /// [Bits 15:8] Number of linear address bits. + /// + UINT32 LinearAddressBits:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_VIR_PHY_ADDRESS_SIZE_EAX; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/LocalApic.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/LocalApic.h new file mode 100644 index 0000000000..5bc7f4149a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/LocalApic.h @@ -0,0 +1,183 @@ +/** @file + IA32 Local APIC Definitions. + + Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INTEL_LOCAL_APIC_H__ +#define __INTEL_LOCAL_APIC_H__ + +// +// Definition for Local APIC registers and related values +// +#define XAPIC_ID_OFFSET 0x20 +#define XAPIC_VERSION_OFFSET 0x30 +#define XAPIC_EOI_OFFSET 0x0b0 +#define XAPIC_ICR_DFR_OFFSET 0x0e0 +#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0 +#define XAPIC_ICR_LOW_OFFSET 0x300 +#define XAPIC_ICR_HIGH_OFFSET 0x310 +#define XAPIC_LVT_TIMER_OFFSET 0x320 +#define XAPIC_LVT_LINT0_OFFSET 0x350 +#define XAPIC_LVT_LINT1_OFFSET 0x360 +#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380 +#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390 +#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0 + +#define X2APIC_MSR_BASE_ADDRESS 0x800 +#define X2APIC_MSR_ICR_ADDRESS 0x830 + +#define LOCAL_APIC_DELIVERY_MODE_FIXED 0 +#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1 +#define LOCAL_APIC_DELIVERY_MODE_SMI 2 +#define LOCAL_APIC_DELIVERY_MODE_NMI 4 +#define LOCAL_APIC_DELIVERY_MODE_INIT 5 +#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6 +#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7 + +#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0 +#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1 +#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2 +#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3 + +// +// Local APIC Version Register. +// +typedef union { + struct { + UINT32 Version:8; ///< The version numbers of the local APIC. + UINT32 Reserved0:8; ///< Reserved. + UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1. + UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported. + UINT32 Reserved1:7; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_VERSION; + +// +// Low half of Interrupt Command Register (ICR). +// +typedef union { + struct { + UINT32 Vector:8; ///< The vector number of the interrupt being sent. + UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent. + UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode. + UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode. + UINT32 Reserved0:1; ///< Reserved. + UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1. + UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode. + UINT32 Reserved1:2; ///< Reserved. + UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt. + UINT32 Reserved2:12; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_ICR_LOW; + +// +// High half of Interrupt Command Register (ICR) +// +typedef union { + struct { + UINT32 Reserved0:24; ///< Reserved. + UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode. + } Bits; + UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode. +} LOCAL_APIC_ICR_HIGH; + +// +// Spurious-Interrupt Vector Register (SVR) +// +typedef union { + struct { + UINT32 SpuriousVector:8; ///< Spurious Vector. + UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable. + UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking. + UINT32 Reserved0:2; ///< Reserved. + UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression. + UINT32 Reserved1:19; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_SVR; + +// +// Divide Configuration Register (DCR) +// +typedef union { + struct { + UINT32 DivideValue1:2; ///< Low 2 bits of the divide value. + UINT32 Reserved0:1; ///< Always 0. + UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value. + UINT32 Reserved1:28; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_DCR; + +// +// LVT Timer Register +// +typedef union { + struct { + UINT32 Vector:8; ///< The vector number of the interrupt being sent. + UINT32 Reserved0:4; ///< Reserved. + UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. + UINT32 Reserved1:3; ///< Reserved. + UINT32 Mask:1; ///< 0: Not masked, 1: Masked. + UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic. + UINT32 Reserved2:14; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_LVT_TIMER; + +// +// LVT LINT0/LINT1 Register +// +typedef union { + struct { + UINT32 Vector:8; ///< The vector number of the interrupt being sent. + UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. + UINT32 Reserved0:1; ///< Reserved. + UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. + UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity. + UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received. + UINT32 TriggerMode:1; ///< 0:edge, 1:level. + UINT32 Mask:1; ///< 0: Not masked, 1: Masked. + UINT32 Reserved1:15; ///< Reserved. + } Bits; + UINT32 Uint32; +} LOCAL_APIC_LVT_LINT; + +// +// MSI Address Register +// +typedef union { + struct { + UINT32 Reserved0:2; ///< Reserved + UINT32 DestinationMode:1; ///< Specifies the Destination Mode. + UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint. + UINT32 Reserved1:8; ///< Reserved. + UINT32 DestinationId:8; ///< Specifies the Destination ID. + UINT32 BaseAddress:12; ///< Must be 0FEEH + } Bits; + UINT32 Uint32; +} LOCAL_APIC_MSI_ADDRESS; + +// +// MSI Address Register +// +typedef union { + struct { + UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH + UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. + UINT32 Reserved0:3; ///< Reserved. + UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts. + UINT32 TriggerMode:1; ///< 0:Edge, 1:Level. + UINT32 Reserved1:16; ///< Reserved. + UINT32 Reserved2:32; ///< Reserved. + } Bits; + UINT64 Uint64; +} LOCAL_APIC_MSI_DATA; + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Microcode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Microcode.h new file mode 100644 index 0000000000..3834fe64e8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Microcode.h @@ -0,0 +1,194 @@ +/** @file + Microcode Definitions. + + Microcode Definitions based on contents of the + Intel(R) 64 and IA-32 Architectures Software Developer's Manual + Volume 3A, Section 9.11 Microcode Definitions + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, + June 2016, Chapter 9 Processor Management and Initialization, Section 9-11. + +**/ + +#ifndef __INTEL_MICROCODE_H__ +#define __INTEL_MICROCODE_H__ + +/// +/// CPU Microcode Date in BCD format +/// +typedef union { + struct { + UINT32 Year:16; + UINT32 Day:8; + UINT32 Month:8; + } Bits; + UINT32 Uint32; +} CPU_MICROCODE_DATE; + +/// +/// CPU Microcode Processor Signature format +/// +typedef union { + struct { + UINT32 Stepping:4; + UINT32 Model:4; + UINT32 Family:4; + UINT32 Type:2; + UINT32 Reserved1:2; + UINT32 ExtendedModel:4; + UINT32 ExtendedFamily:8; + UINT32 Reserved2:4; + } Bits; + UINT32 Uint32; +} CPU_MICROCODE_PROCESSOR_SIGNATURE; + +#pragma pack (1) + +/// +/// Microcode Update Format definition +/// +typedef struct { + /// + /// Version number of the update header + /// + UINT32 HeaderVersion; + /// + /// Unique version number for the update, the basis for the update + /// signature provided by the processor to indicate the current update + /// functioning within the processor. Used by the BIOS to authenticate + /// the update and verify that the processor loads successfully. The + /// value in this field cannot be used for processor stepping identification + /// alone. This is a signed 32-bit number. + /// + UINT32 UpdateRevision; + /// + /// Date of the update creation in binary format: mmddyyyy (e.g. + /// 07/18/98 is 07181998H). + /// + CPU_MICROCODE_DATE Date; + /// + /// Extended family, extended model, type, family, model, and stepping + /// of processor that requires this particular update revision (e.g., + /// 00000650H). Each microcode update is designed specifically for a + /// given extended family, extended model, type, family, model, and + /// stepping of the processor. + /// The BIOS uses the processor signature field in conjunction with the + /// CPUID instruction to determine whether or not an update is + /// appropriate to load on a processor. The information encoded within + /// this field exactly corresponds to the bit representations returned by + /// the CPUID instruction. + /// + CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature; + /// + /// Checksum of Update Data and Header. Used to verify the integrity of + /// the update header and data. Checksum is correct when the + /// summation of all the DWORDs (including the extended Processor + /// Signature Table) that comprise the microcode update result in + /// 00000000H. + /// + UINT32 Checksum; + /// + /// Version number of the loader program needed to correctly load this + /// update. The initial version is 00000001H + /// + UINT32 LoaderRevision; + /// + /// Platform type information is encoded in the lower 8 bits of this 4- + /// byte field. Each bit represents a particular platform type for a given + /// CPUID. The BIOS uses the processor flags field in conjunction with + /// the platform Id bits in MSR (17H) to determine whether or not an + /// update is appropriate to load on a processor. Multiple bits may be set + /// representing support for multiple platform IDs. + /// + UINT32 ProcessorFlags; + /// + /// Specifies the size of the encrypted data in bytes, and must be a + /// multiple of DWORDs. If this value is 00000000H, then the microcode + /// update encrypted data is 2000 bytes (or 500 DWORDs). + /// + UINT32 DataSize; + /// + /// Specifies the total size of the microcode update in bytes. It is the + /// summation of the header size, the encrypted data size and the size of + /// the optional extended signature table. This value is always a multiple + /// of 1024. + /// + UINT32 TotalSize; + /// + /// Reserved fields for future expansion. + /// + UINT8 Reserved[12]; +} CPU_MICROCODE_HEADER; + +/// +/// Extended Signature Table Header Field Definitions +/// +typedef struct { + /// + /// Specifies the number of extended signature structures (Processor + /// Signature[n], processor flags[n] and checksum[n]) that exist in this + /// microcode update + /// + UINT32 ExtendedSignatureCount; + /// + /// Checksum of update extended processor signature table. Used to + /// verify the integrity of the extended processor signature table. + /// Checksum is correct when the summation of the DWORDs that + /// comprise the extended processor signature table results in + /// 00000000H. + /// + UINT32 ExtendedChecksum; + /// + /// Reserved fields. + /// + UINT8 Reserved[12]; +} CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +/// +/// Extended Signature Table Field Definitions +/// +typedef struct { + /// + /// Extended family, extended model, type, family, model, and stepping + /// of processor that requires this particular update revision (e.g., + /// 00000650H). Each microcode update is designed specifically for a + /// given extended family, extended model, type, family, model, and + /// stepping of the processor. + /// The BIOS uses the processor signature field in conjunction with the + /// CPUID instruction to determine whether or not an update is + /// appropriate to load on a processor. The information encoded within + /// this field exactly corresponds to the bit representations returned by + /// the CPUID instruction. + /// + CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature; + /// + /// Platform type information is encoded in the lower 8 bits of this 4- + /// byte field. Each bit represents a particular platform type for a given + /// CPUID. The BIOS uses the processor flags field in conjunction with + /// the platform Id bits in MSR (17H) to determine whether or not an + /// update is appropriate to load on a processor. Multiple bits may be set + /// representing support for multiple platform IDs. + /// + UINT32 ProcessorFlag; + /// + /// Used by utility software to decompose a microcode update into + /// multiple microcode updates where each of the new updates is + /// constructed without the optional Extended Processor Signature + /// Table. + /// To calculate the Checksum, substitute the Primary Processor + /// Signature entry and the Processor Flags entry with the + /// corresponding Extended Patch entry. Delete the Extended Processor + /// Signature Table entries. The Checksum is correct when the + /// summation of all DWORDs that comprise the created Extended + /// Processor Patch results in 00000000H. + /// + UINT32 Checksum; +} CPU_MICROCODE_EXTENDED_TABLE; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr.h new file mode 100644 index 0000000000..4f6172a16e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr.h @@ -0,0 +1,44 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 ~ 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __INTEL_MSR_H__ +#define __INTEL_MSR_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/AtomMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/AtomMsr.h new file mode 100644 index 0000000000..20bfd1fe6c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/AtomMsr.h @@ -0,0 +1,784 @@ +/** @file + MSR Definitions for the Intel(R) Atom(TM) Processor Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __ATOM_MSR_H__ +#define __ATOM_MSR_H__ + +#include + +/** + Is Intel(R) Atom(TM) Processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x1C || \ + DisplayModel == 0x26 || \ + DisplayModel == 0x27 || \ + DisplayModel == 0x35 || \ + DisplayModel == 0x36 \ + ) \ + ) + +/** + Shared. Model Specific Platform ID (R). + + @param ECX MSR_ATOM_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_ATOM_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID); + @endcode + @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. +**/ +#define MSR_ATOM_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. + /// + UINT32 MaximumQualifiedRatio:5; + UINT32 Reserved2:19; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_PLATFORM_ID_REGISTER; + + +/** + Shared. Processor Hard Power-On Configuration (R/W) Enables and disables + processor features; (R) indicates current processor configuration. + + @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_ATOM_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. +**/ +#define MSR_ATOM_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Always 0. + /// + UINT32 DataErrorCheckingEnable:1; + /// + /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Always 0. + /// + UINT32 ResponseErrorCheckingEnable:1; + /// + /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. + /// + UINT32 AERR_DriveEnable:1; + /// + /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 = + /// Disabled Always 0. + /// + UINT32 BERR_Enable:1; + UINT32 Reserved2:1; + UINT32 Reserved3:1; + /// + /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0. + /// + UINT32 BINIT_DriverEnable:1; + UINT32 Reserved4:1; + /// + /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled + /// Always 0. + /// + UINT32 AERR_ObservationEnabled:1; + UINT32 Reserved5:1; + /// + /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled + /// Always 0. + /// + UINT32 BINIT_ObservationEnabled:1; + UINT32 Reserved6:1; + /// + /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes. + /// + UINT32 ResetVector:1; + UINT32 Reserved7:1; + /// + /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B. + /// + UINT32 APICClusterID:2; + UINT32 Reserved8:2; + /// + /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B. + /// + UINT32 SymmetricArbitrationID:2; + /// + /// [Bits 26:22] Integer Bus Frequency Ratio (R/O). + /// + UINT32 IntegerBusFrequencyRatio:5; + UINT32 Reserved9:5; + UINT32 Reserved10:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_EBL_CR_POWERON_REGISTER; + + +/** + Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch + record registers on the last branch record stack. The From_IP part of the + stack contains pointers to the source instruction . See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.5. + + @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + @{ +**/ +#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040 +#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041 +#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042 +#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043 +#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044 +#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045 +#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046 +#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047 +/// @} + + +/** + Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch + record registers on the last branch record stack. The To_IP part of the + stack contains pointers to the destination instruction. + + @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + @{ +**/ +#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060 +#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061 +#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062 +#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063 +#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064 +#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065 +#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066 +#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067 +/// @} + + +/** + Shared. Scalable Bus Speed(RO) This field indicates the intended scalable + bus clock speed for processors based on Intel Atom microarchitecture:. + + @param ECX MSR_ATOM_FSB_FREQ (0x000000CD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_FSB_FREQ_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_FSB_FREQ_REGISTER. + + Example usage + @code + MSR_ATOM_FSB_FREQ_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ); + @endcode + @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. +**/ +#define MSR_ATOM_FSB_FREQ 0x000000CD + +/** + MSR information returned for MSR index #MSR_ATOM_FSB_FREQ +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] - Scalable Bus Speed + /// + /// Atom Processor Family + /// --------------------- + /// 111B: 083 MHz (FSB 333) + /// 101B: 100 MHz (FSB 400) + /// 001B: 133 MHz (FSB 533) + /// 011B: 167 MHz (FSB 667) + /// + /// 133.33 MHz should be utilized if performing calculation with + /// System Bus Speed when encoding is 001B. + /// 166.67 MHz should be utilized if performing calculation with + /// System Bus Speed when + /// encoding is 011B. + /// + UINT32 ScalableBusSpeed:3; + UINT32 Reserved1:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_FSB_FREQ_REGISTER; + + +/** + Shared. + + @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. + + Example usage + @code + MSR_ATOM_BBL_CR_CTL3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3); + AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64); + @endcode + @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. +**/ +#define MSR_ATOM_BBL_CR_CTL3 0x0000011E + +/** + MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = + /// Indicates if the L2 is hardware-disabled. + /// + UINT32 L2HardwareEnabled:1; + UINT32 Reserved1:7; + /// + /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = + /// Disabled (default) Until this bit is set the processor will not + /// respond to the WBINVD instruction or the assertion of the FLUSH# input. + /// + UINT32 L2Enabled:1; + UINT32 Reserved2:14; + /// + /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. + /// + UINT32 L2NotPresent:1; + UINT32 Reserved3:8; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_BBL_CR_CTL3_REGISTER; + + +/** + Shared. + + @param ECX MSR_ATOM_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_ATOM_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS); + AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64); + @endcode + @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. +**/ +#define MSR_ATOM_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_ATOM_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Current Performance State Value. + /// + UINT32 CurrentPerformanceStateValue:16; + UINT32 Reserved1:16; + UINT32 Reserved2:8; + /// + /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio + /// configured for the processor. + /// + UINT32 MaximumBusRatio:5; + UINT32 Reserved3:19; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_PERF_STATUS_REGISTER; + + +/** + Shared. + + @param ECX MSR_ATOM_THERM2_CTL (0x0000019D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_THERM2_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_THERM2_CTL_REGISTER. + + Example usage + @code + MSR_ATOM_THERM2_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL); + AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64); + @endcode + @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. +**/ +#define MSR_ATOM_THERM2_CTL 0x0000019D + +/** + MSR information returned for MSR index #MSR_ATOM_THERM2_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = + /// Thermal Monitor 1 (thermally-initiated on-die modulation of the + /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated + /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is + /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. + /// + UINT32 TM_SELECT:1; + UINT32 Reserved2:15; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_THERM2_CTL_REGISTER; + + +/** + Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. Default value is 0. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:1; + UINT32 Reserved4:1; + /// + /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by + /// the processor to indicate a pending break event within the processor 0 + /// = Indicates compatible FERR# signaling behavior This bit must be set + /// to 1 to support XAPIC interrupt model usage. + /// + UINT32 FERR:1; + /// + /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + /// + /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the + /// thermal sensor indicates that the die temperature is at the + /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. + /// TM2 will reduce the bus to core ratio and voltage according to the + /// value last written to MSR_THERM2_CTL bits 15:0. + /// When this bit is clear (0, default), the processor does not change + /// the VID signals or the bus to core ratio when the processor enters a + /// thermally managed state. The BIOS must enable this feature if the + /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is + /// not set, this feature is not supported and BIOS must not alter the + /// contents of the TM2 bit location. The processor is operating out of + /// specification if both this bit and the TM1 bit are set to 0. + /// + UINT32 TM2:1; + UINT32 Reserved5:2; + /// + /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved6:1; + /// + /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved7:1; + /// + /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock + /// (R/WO) When set, this bit causes the following bits to become + /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this + /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must + /// be set before an Enhanced Intel SpeedStep Technology transition is + /// requested. This bit is cleared on reset. + /// + UINT32 EISTLock:1; + UINT32 Reserved8:1; + /// + /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved9:8; + UINT32 Reserved10:2; + /// + /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved11:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_IA32_MISC_ENABLE_REGISTER; + + +/** + Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) + that points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP (at 40H). + + @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9 + + +/** + Unique. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP); + @endcode + @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_ATOM_LER_FROM_LIP 0x000001DD + + +/** + Unique. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP); + @endcode + @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_ATOM_LER_TO_LIP 0x000001DE + + +/** + Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling + (PEBS).". + + @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_ATOM_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE); + AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_ATOM_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). + /// + UINT32 Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_ATOM_PEBS_ENABLE_REGISTER; + + +/** + Package. Package C2 Residency Note: C-state values are processor specific + C-state code names, unrelated to MWAIT extension C-state parameters or ACPI + C-States. Package. Package C2 Residency Counter. (R/O) Time that this + package is in processor-specific C2 states since last reset. Counts at 1 Mhz + frequency. + + @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY); + AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr); + @endcode + @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. +**/ +#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8 + + +/** + Package. Package C4 Residency Note: C-state values are processor specific + C-state code names, unrelated to MWAIT extension C-state parameters or ACPI + C-States. Package. Package C4 Residency Counter. (R/O) Time that this + package is in processor-specific C4 states since last reset. Counts at 1 Mhz + frequency. + + @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY); + AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr); + @endcode + @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM. +**/ +#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9 + + +/** + Package. Package C6 Residency Note: C-state values are processor specific + C-state code names, unrelated to MWAIT extension C-state parameters or ACPI + C-States. Package. Package C6 Residency Counter. (R/O) Time that this + package is in processor-specific C6 states since last reset. Counts at 1 Mhz + frequency. + + @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h new file mode 100644 index 0000000000..f4de39c4df --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h @@ -0,0 +1,354 @@ +/** @file + MSR Definitions for Intel processors based on the Broadwell microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __BROADWELL_MSR_H__ +#define __BROADWELL_MSR_H__ + +#include + +/** + Is Intel processors based on the Broadwell microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x3D || \ + DisplayModel == 0x47 || \ + DisplayModel == 0x4F || \ + DisplayModel == 0x56 \ + ) \ + ) + +/** + Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control + Facilities.". + + @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical + /// Addresses (ToPA).". + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:5; + /// + /// [Bit 61] Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Ovf_BufDSSAVE. + /// + UINT32 OvfBuf:1; + /// + /// [Bit 63] CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI C-states. `See http://biosbits.org. `__. + + @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 0000b: + /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 + /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10. + /// + UINT32 Limit:4; + UINT32 Reserved1:6; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + /// + /// [Bit 29] Enable Package C-State Auto-demotion (R/W). + /// + UINT32 CStateAutoDemotion:1; + /// + /// [Bit 30] Enable Package C-State Undemotion (R/W). + /// + UINT32 CStateUndemotion:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT); + @endcode + @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6core active. + /// + UINT32 Maximum6C:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio + fields represent the widest possible range of uncore frequencies. Writing to + these fields allows software to control the minimum and the maximum + frequency that hardware will select. + + @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT); + AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 MAX_RATIO:7; + UINT32 Reserved2:1; + /// + /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 MIN_RATIO:7; + UINT32 Reserved3:17; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER; + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS); + @endcode + @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Core2Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Core2Msr.h new file mode 100644 index 0000000000..617daaaff8 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Core2Msr.h @@ -0,0 +1,1068 @@ +/** @file + MSR Definitions for the Intel(R) Core(TM) 2 Processor Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __CORE2_MSR_H__ +#define __CORE2_MSR_H__ + +#include + +/** + Is Intel(R) Core(TM) 2 Processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x0F || \ + DisplayModel == 0x17 \ + ) \ + ) + +/** + Shared. Model Specific Platform ID (R). + + @param ECX MSR_CORE2_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_CORE2_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID); + @endcode + @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. +**/ +#define MSR_CORE2_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. + /// + UINT32 MaximumQualifiedRatio:5; + UINT32 Reserved2:19; + UINT32 Reserved3:18; + /// + /// [Bits 52:50] See Table 2-2. + /// + UINT32 PlatformId:3; + UINT32 Reserved4:11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_PLATFORM_ID_REGISTER; + + +/** + Shared. Processor Hard Power-On Configuration (R/W) Enables and disables + processor features; (R) indicates current processor configuration. + + @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_CORE2_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. +**/ +#define MSR_CORE2_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Note: Not all processor implements R/W. + /// + UINT32 DataErrorCheckingEnable:1; + /// + /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Note: Not all processor implements R/W. + /// + UINT32 ResponseErrorCheckingEnable:1; + /// + /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not + /// all processor implements R/W. + /// + UINT32 MCERR_DriveEnable:1; + /// + /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: + /// Not all processor implements R/W. + /// + UINT32 AddressParityEnable:1; + UINT32 Reserved2:1; + UINT32 Reserved3:1; + /// + /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not + /// all processor implements R/W. + /// + UINT32 BINIT_DriverEnable:1; + /// + /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 OutputTriStateEnable:1; + /// + /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 MCERR_ObservationEnabled:1; + /// + /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present. + /// + UINT32 IntelTXTCapableChipset:1; + /// + /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 BINIT_ObservationEnabled:1; + UINT32 Reserved4:1; + /// + /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes. + /// + UINT32 ResetVector:1; + UINT32 Reserved5:1; + /// + /// [Bits 17:16] APIC Cluster ID (R/O). + /// + UINT32 APICClusterID:2; + /// + /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 = + /// Non-integer ratio. + /// + UINT32 NonIntegerBusRatio:1; + UINT32 Reserved6:1; + /// + /// [Bits 21:20] Symmetric Arbitration ID (R/O). + /// + UINT32 SymmetricArbitrationID:2; + /// + /// [Bits 26:22] Integer Bus Frequency Ratio (R/O). + /// + UINT32 IntegerBusFrequencyRatio:5; + UINT32 Reserved7:5; + UINT32 Reserved8:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_EBL_CR_POWERON_REGISTER; + + +/** + Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2. + + @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_CORE2_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM. +**/ +#define MSR_CORE2_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:3; + /// + /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock + /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read + /// visible and writeable while in SMM. + /// + UINT32 SMRREnable:1; + UINT32 Reserved2:28; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_FEATURE_CONTROL_REGISTER; + + +/** + Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch + record registers on the last branch record stack. The From_IP part of the + stack contains pointers to the source instruction. See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.5. + + @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + @{ +**/ +#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040 +#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041 +#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042 +#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043 +/// @} + + +/** + Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch + record registers on the last branch record stack. This To_IP part of the + stack contains pointers to the destination instruction. + + @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + @{ +**/ +#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060 +#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061 +#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062 +#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063 +/// @} + + +/** + Unique. System Management Mode Base Address register (WO in SMM) + Model-specific implementation of SMRR-like interface, read visible and write + only in SMM. + + @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER. + + Example usage + @code + MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr; + + Msr.Uint64 = 0; + AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64); + @endcode + @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM. +**/ +#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0 + +/** + MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:12; + /// + /// [Bits 31:12] PhysBase. SMRR physical Base Address. + /// + UINT32 PhysBase:20; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_SMRR_PHYSBASE_REGISTER; + + +/** + Unique. System Management Mode Physical Address Mask register (WO in SMM) + Model-specific implementation of SMRR-like interface, read visible and write + only in SMM. + + @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER. + + Example usage + @code + MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr; + + Msr.Uint64 = 0; + AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64); + @endcode + @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM. +**/ +#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1 + +/** + MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:11; + /// + /// [Bit 11] Valid. Physical address base and range mask are valid. + /// + UINT32 Valid:1; + /// + /// [Bits 31:12] PhysMask. SMRR physical address range mask. + /// + UINT32 PhysMask:20; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_SMRR_PHYSMASK_REGISTER; + + +/** + Shared. Scalable Bus Speed(RO) This field indicates the intended scalable + bus clock speed for processors based on Intel Core microarchitecture:. + + @param ECX MSR_CORE2_FSB_FREQ (0x000000CD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_FSB_FREQ_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_FSB_FREQ_REGISTER. + + Example usage + @code + MSR_CORE2_FSB_FREQ_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ); + @endcode + @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. +**/ +#define MSR_CORE2_FSB_FREQ 0x000000CD + +/** + MSR information returned for MSR index #MSR_CORE2_FSB_FREQ +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] - Scalable Bus Speed + /// 101B: 100 MHz (FSB 400) + /// 001B: 133 MHz (FSB 533) + /// 011B: 167 MHz (FSB 667) + /// 010B: 200 MHz (FSB 800) + /// 000B: 267 MHz (FSB 1067) + /// 100B: 333 MHz (FSB 1333) + /// + /// 133.33 MHz should be utilized if performing calculation with System + /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if + /// performing calculation with System Bus Speed when encoding is 011B. + /// 266.67 MHz should be utilized if performing calculation with System + /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if + /// performing calculation with System Bus Speed when encoding is 100B. + /// + UINT32 ScalableBusSpeed:3; + UINT32 Reserved1:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_FSB_FREQ_REGISTER; + +/** + Shared. + + @param ECX MSR_CORE2_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_CORE2_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS); + AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64); + @endcode + @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. +**/ +#define MSR_CORE2_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_CORE2_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Current Performance State Value. + /// + UINT32 CurrentPerformanceStateValue:16; + UINT32 Reserved1:15; + /// + /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default + /// is cleared. + /// + UINT32 XEOperation:1; + UINT32 Reserved2:8; + /// + /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio + /// configured for the processor. + /// + UINT32 MaximumBusRatio:5; + UINT32 Reserved3:1; + /// + /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio + /// is enabled. Applies processors based on Enhanced Intel Core + /// microarchitecture. + /// + UINT32 NonIntegerBusRatio:1; + UINT32 Reserved4:17; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_PERF_STATUS_REGISTER; + + +/** + Unique. + + @param ECX MSR_CORE2_THERM2_CTL (0x0000019D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_THERM2_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_THERM2_CTL_REGISTER. + + Example usage + @code + MSR_CORE2_THERM2_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL); + AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64); + @endcode + @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. +**/ +#define MSR_CORE2_THERM2_CTL 0x0000019D + +/** + MSR information returned for MSR index #MSR_CORE2_THERM2_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = + /// Thermal Monitor 1 (thermally-initiated on-die modulation of the + /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated + /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is + /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled. + /// + UINT32 TM_SELECT:1; + UINT32 Reserved2:15; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_THERM2_CTL_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:1; + /// + /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the + /// hardware prefetcher operation on streams of data. When clear + /// (default), enables the prefetch queue. Disabling of the hardware + /// prefetcher may impact processor performance. + /// + UINT32 HardwarePrefetcherDisable:1; + /// + /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by + /// the processor to indicate a pending break event within the processor 0 + /// = Indicates compatible FERR# signaling behavior This bit must be set + /// to 1 to support XAPIC interrupt model usage. + /// + UINT32 FERR:1; + /// + /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + /// + /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the + /// thermal sensor indicates that the die temperature is at the + /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. + /// TM2 will reduce the bus to core ratio and voltage according to the + /// value last written to MSR_THERM2_CTL bits 15:0. + /// When this bit is clear (0, default), the processor does not change + /// the VID signals or the bus to core ratio when the processor enters a + /// thermally managed state. The BIOS must enable this feature if the + /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is + /// not set, this feature is not supported and BIOS must not alter the + /// contents of the TM2 bit location. The processor is operating out of + /// specification if both this bit and the TM1 bit are set to 0. + /// + UINT32 TM2:1; + UINT32 Reserved4:2; + /// + /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + /// + /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set + /// to 1, the processor fetches the cache line that contains data + /// currently required by the processor. When set to 0, the processor + /// fetches cache lines that comprise a cache line pair (128 bytes). + /// Single processor platforms should not set this bit. Server platforms + /// should set or clear this bit based on platform performance observed in + /// validation and testing. BIOS may contain a setup option that controls + /// the setting of this bit. + /// + UINT32 AdjacentCacheLinePrefetchDisable:1; + /// + /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock + /// (R/WO) When set, this bit causes the following bits to become + /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this + /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must + /// be set before an Enhanced Intel SpeedStep Technology transition is + /// requested. This bit is cleared on reset. + /// + UINT32 EISTLock:1; + UINT32 Reserved6:1; + /// + /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved9:2; + /// + /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU + /// L1 data cache prefetcher is disabled. The default value after reset is + /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is + /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple + /// loads from the same line done within a time limit, the DCU prefetcher + /// assumes the next line will be required. The next line is prefetched in + /// to the L1 data cache from memory or L2. + /// + UINT32 DCUPrefetcherDisable:1; + /// + /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that + /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled + /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). + /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] + /// reports the processor's support of IDA is enabled. Note: the power-on + /// default value is used by BIOS to detect hardware support of IDA. If + /// power-on default value is 1, IDA is available in the processor. If + /// power-on default value is 0, IDA is not available. + /// + UINT32 IDADisable:1; + /// + /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP + /// prefetcher is disabled. The default value after reset is 0. BIOS may + /// write '1' to disable this feature. The IP prefetcher is an L1 data + /// cache prefetcher. The IP prefetcher looks for sequential load history + /// to determine whether to prefetch the next expected data into the L1 + /// cache from memory or L2. + /// + UINT32 IPPrefetcherDisable:1; + UINT32 Reserved10:24; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_IA32_MISC_ENABLE_REGISTER; + + +/** + Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) + that points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP (at 40H). + + @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9 + + +/** + Unique. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP); + @endcode + @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_CORE2_LER_FROM_LIP 0x000001DD + + +/** + Unique. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP); + @endcode + @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_CORE2_LER_TO_LIP 0x000001DE + + +/** + Unique. Fixed-Function Performance Counter Register n (R/W). + + @param ECX MSR_CORE2_PERF_FIXED_CTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0); + AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr); + @endcode + @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM. + MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM. + MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM. + @{ +**/ +#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309 +#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A +#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B +/// @} + + +/** + Unique. RO. This applies to processors that do not support architectural + perfmon version 2. + + @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER. + + Example usage + @code + MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES); + AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64); + @endcode + @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM. +**/ +#define MSR_CORE2_PERF_CAPABILITIES 0x00000345 + +/** + MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 5:0] LBR Format. See Table 2-2. + /// + UINT32 LBR_FMT:6; + /// + /// [Bit 6] PEBS Record Format. + /// + UINT32 PEBS_FMT:1; + /// + /// [Bit 7] PEBSSaveArchRegs. See Table 2-2. + /// + UINT32 PEBS_ARCH_REG:1; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_PERF_CAPABILITIES_REGISTER; + + +/** + Unique. Fixed-Function-Counter Control Register (R/W). + + @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL); + AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr); + @endcode + @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM. +**/ +#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D + + +/** + Unique. See Section 18.6.2.2, "Global Counter Control Facilities.". + + @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr); + @endcode + @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E + + +/** + Unique. See Section 18.6.2.2, "Global Counter Control Facilities.". + + @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr); + @endcode + @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F + + +/** + Unique. See Section 18.6.2.2, "Global Counter Control Facilities.". + + @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr); + @endcode + @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390 + + +/** + Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling + (PEBS).". + + @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_CORE2_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE); + AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_CORE2_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). + /// + UINT32 Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE2_PEBS_ENABLE_REGISTER; + + +/** + Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon + processor 7400 series (processor signature 06_1D) only. See Section 17.2.2. + + @param ECX MSR_CORE2_EMON_L3_CTR_CTLn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0); + AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr); + @endcode + @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. + MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM. + @{ +**/ +#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC +#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD +#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE +#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF +#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0 +#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1 +#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2 +#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3 +/// @} + + +/** + Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor + 7400 series (processor signature 06_1D) only. See Section 17.2.2. + + @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL); + AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr); + @endcode + @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM. +**/ +#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/CoreMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/CoreMsr.h new file mode 100644 index 0000000000..a000ab7184 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/CoreMsr.h @@ -0,0 +1,1056 @@ +/** @file + MSR Definitions for Intel Core Solo and Intel Core Duo Processors. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __CORE_MSR_H__ +#define __CORE_MSR_H__ + +#include + +/** + Is Intel Core Solo and Intel Core Duo Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x0E \ + ) \ + ) + +/** + Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2. + + @param ECX MSR_CORE_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR); + AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr); + @endcode + @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. +**/ +#define MSR_CORE_P5_MC_ADDR 0x00000000 + + +/** + Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2. + + @param ECX MSR_CORE_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE); + AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr); + @endcode + @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. +**/ +#define MSR_CORE_P5_MC_TYPE 0x00000001 + + +/** + Shared. Processor Hard Power-On Configuration (R/W) Enables and disables + processor features; (R) indicates current processor configuration. + + @param ECX MSR_CORE_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_CORE_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. +**/ +#define MSR_CORE_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Note: Not all processor implements R/W. + /// + UINT32 DataErrorCheckingEnable:1; + /// + /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled + /// Note: Not all processor implements R/W. + /// + UINT32 ResponseErrorCheckingEnable:1; + /// + /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not + /// all processor implements R/W. + /// + UINT32 MCERR_DriveEnable:1; + /// + /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: + /// Not all processor implements R/W. + /// + UINT32 AddressParityEnable:1; + UINT32 Reserved2:2; + /// + /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not + /// all processor implements R/W. + /// + UINT32 BINIT_DriverEnable:1; + /// + /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 OutputTriStateEnable:1; + /// + /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 MCERR_ObservationEnabled:1; + UINT32 Reserved3:1; + /// + /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 BINIT_ObservationEnabled:1; + UINT32 Reserved4:1; + /// + /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes. + /// + UINT32 ResetVector:1; + UINT32 Reserved5:1; + /// + /// [Bits 17:16] APIC Cluster ID (R/O). + /// + UINT32 APICClusterID:2; + /// + /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved. + /// + UINT32 SystemBusFrequency:1; + UINT32 Reserved6:1; + /// + /// [Bits 21:20] Symmetric Arbitration ID (R/O). + /// + UINT32 SymmetricArbitrationID:2; + /// + /// [Bits 26:22] Clock Frequency Ratio (R/O). + /// + UINT32 ClockFrequencyRatio:5; + UINT32 Reserved7:5; + UINT32 Reserved8:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_EBL_CR_POWERON_REGISTER; + + +/** + Unique. Last Branch Record n (R/W) One of 8 last branch record registers on + the last branch record stack: bits 31-0 hold the 'from' address and bits + 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at + 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording + (Pentium M Processors).". + + @param ECX MSR_CORE_LASTBRANCH_n + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0); + AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr); + @endcode + @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. + MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. + MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. + MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. + MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. + MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. + MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. + MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM. + @{ +**/ +#define MSR_CORE_LASTBRANCH_0 0x00000040 +#define MSR_CORE_LASTBRANCH_1 0x00000041 +#define MSR_CORE_LASTBRANCH_2 0x00000042 +#define MSR_CORE_LASTBRANCH_3 0x00000043 +#define MSR_CORE_LASTBRANCH_4 0x00000044 +#define MSR_CORE_LASTBRANCH_5 0x00000045 +#define MSR_CORE_LASTBRANCH_6 0x00000046 +#define MSR_CORE_LASTBRANCH_7 0x00000047 +/// @} + + +/** + Shared. Scalable Bus Speed (RO) This field indicates the scalable bus + clock speed:. + + @param ECX MSR_CORE_FSB_FREQ (0x000000CD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_FSB_FREQ_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_FSB_FREQ_REGISTER. + + Example usage + @code + MSR_CORE_FSB_FREQ_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ); + @endcode + @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. +**/ +#define MSR_CORE_FSB_FREQ 0x000000CD + +/** + MSR information returned for MSR index #MSR_CORE_FSB_FREQ +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] - Scalable Bus Speed + /// 101B: 100 MHz (FSB 400) + /// 001B: 133 MHz (FSB 533) + /// 011B: 167 MHz (FSB 667) + /// + /// 133.33 MHz should be utilized if performing calculation with System Bus + /// Speed when encoding is 101B. 166.67 MHz should be utilized if + /// performing calculation with System Bus Speed when encoding is 001B. + /// + UINT32 ScalableBusSpeed:3; + UINT32 Reserved1:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_FSB_FREQ_REGISTER; + + +/** + Shared. + + @param ECX MSR_CORE_BBL_CR_CTL3 (0x0000011E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER. + + Example usage + @code + MSR_CORE_BBL_CR_CTL3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3); + AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64); + @endcode + @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. +**/ +#define MSR_CORE_BBL_CR_CTL3 0x0000011E + +/** + MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = + /// Indicates if the L2 is hardware-disabled. + /// + UINT32 L2HardwareEnabled:1; + UINT32 Reserved1:7; + /// + /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = + /// Disabled (default) Until this bit is set the processor will not + /// respond to the WBINVD instruction or the assertion of the FLUSH# input. + /// + UINT32 L2Enabled:1; + UINT32 Reserved2:14; + /// + /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. + /// + UINT32 L2NotPresent:1; + UINT32 Reserved3:8; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_BBL_CR_CTL3_REGISTER; + + +/** + Unique. + + @param ECX MSR_CORE_THERM2_CTL (0x0000019D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_THERM2_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_THERM2_CTL_REGISTER. + + Example usage + @code + MSR_CORE_THERM2_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL); + AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64); + @endcode + @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. +**/ +#define MSR_CORE_THERM2_CTL 0x0000019D + +/** + MSR information returned for MSR index #MSR_CORE_THERM2_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = + /// Thermal Monitor 1 (thermally-initiated on-die modulation of the + /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated + /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is + /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled. + /// + UINT32 TM_SELECT:1; + UINT32 Reserved2:15; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_THERM2_CTL_REGISTER; + + +/** + Enable Miscellaneous Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_CORE_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_CORE_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:3; + /// + /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:2; + /// + /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by + /// the processor to indicate a pending break event within the processor 0 + /// = Indicates compatible FERR# signaling behavior This bit must be set + /// to 1 to support XAPIC interrupt model usage. + /// + UINT32 FERR:1; + /// + /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + UINT32 Reserved4:1; + /// + /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the + /// thermal sensor indicates that the die temperature is at the + /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. + /// TM2 will reduce the bus to core ratio and voltage according to the + /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear + /// (0, default), the processor does not change the VID signals or the bus + /// to core ratio when the processor enters a thermal managed state. If + /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID + /// with EAX = 1, then this feature is not supported and BIOS must not + /// alter the contents of this bit location. The processor is operating + /// out of spec if both this bit and the TM1 bit are set to disabled + /// states. + /// + UINT32 TM2:1; + UINT32 Reserved5:2; + /// + /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 = + /// Enhanced Intel SpeedStep Technology enabled. + /// + UINT32 EIST:1; + UINT32 Reserved6:1; + /// + /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved7:1; + UINT32 Reserved8:2; + /// + /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this + /// bit may cause behavior in software that depends on the availability of + /// CPUID leaves greater than 2. + /// + UINT32 LimitCpuidMaxval:1; + UINT32 Reserved9:9; + UINT32 Reserved10:2; + /// + /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved11:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_IA32_MISC_ENABLE_REGISTER; + + +/** + Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) + that points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP (at 40H). + + @param ECX MSR_CORE_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_CORE_LASTBRANCH_TOS 0x000001C9 + + +/** + Unique. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_CORE_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP); + @endcode + @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_CORE_LER_FROM_LIP 0x000001DD + + +/** + Unique. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_CORE_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP); + @endcode + @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_CORE_LER_TO_LIP 0x000001DE + +/** + Unique. + + @param ECX MSR_CORE_MTRRPHYSBASEn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0); + AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr); + @endcode + @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. + MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. + MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. + MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. + MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. + MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. + MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. + MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM. + @{ +**/ +#define MSR_CORE_MTRRPHYSBASE0 0x00000200 +#define MSR_CORE_MTRRPHYSBASE1 0x00000202 +#define MSR_CORE_MTRRPHYSBASE2 0x00000204 +#define MSR_CORE_MTRRPHYSBASE3 0x00000206 +#define MSR_CORE_MTRRPHYSBASE4 0x00000208 +#define MSR_CORE_MTRRPHYSBASE5 0x0000020A +#define MSR_CORE_MTRRPHYSMASK6 0x0000020D +#define MSR_CORE_MTRRPHYSMASK7 0x0000020F +/// @} + + +/** + Unique. + + @param ECX MSR_CORE_MTRRPHYSMASKn (0x00000201) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0); + AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr); + @endcode + @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. + MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. + MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. + MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. + MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. + MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. + MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. + MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM. + @{ +**/ +#define MSR_CORE_MTRRPHYSMASK0 0x00000201 +#define MSR_CORE_MTRRPHYSMASK1 0x00000203 +#define MSR_CORE_MTRRPHYSMASK2 0x00000205 +#define MSR_CORE_MTRRPHYSMASK3 0x00000207 +#define MSR_CORE_MTRRPHYSMASK4 0x00000209 +#define MSR_CORE_MTRRPHYSMASK5 0x0000020B +#define MSR_CORE_MTRRPHYSBASE6 0x0000020C +#define MSR_CORE_MTRRPHYSBASE7 0x0000020E +/// @} + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX64K_00000 (0x00000250) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr); + @endcode + @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM. +**/ +#define MSR_CORE_MTRRFIX64K_00000 0x00000250 + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX16K_80000 (0x00000258) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr); + @endcode + @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM. +**/ +#define MSR_CORE_MTRRFIX16K_80000 0x00000258 + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX16K_A0000 (0x00000259) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr); + @endcode + @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM. +**/ +#define MSR_CORE_MTRRFIX16K_A0000 0x00000259 + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_C0000 (0x00000268) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_C0000 0x00000268 + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_C8000 (0x00000269) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_C8000 0x00000269 + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_D0000 (0x0000026A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_D8000 (0x0000026B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_E0000 (0x0000026C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_E8000 (0x0000026D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_F0000 (0x0000026E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E + + +/** + Unique. + + @param ECX MSR_CORE_MTRRFIX4K_F8000 (0x0000026F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000); + AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr); + @endcode + @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM. +**/ +#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F + + +/** + Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". + + @param ECX MSR_CORE_MC4_CTL (0x0000040C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL); + AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr); + @endcode + @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM. +**/ +#define MSR_CORE_MC4_CTL 0x0000040C + + +/** + Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.". + + @param ECX MSR_CORE_MC4_STATUS (0x0000040D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS); + AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr); + @endcode + @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM. +**/ +#define MSR_CORE_MC4_STATUS 0x0000040D + + +/** + Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR + register is either not implemented or contains no address if the ADDRV flag + in the MSR_MC4_STATUS register is clear. When not implemented in the + processor, all reads and writes to this MSR will cause a general-protection + exception. + + @param ECX MSR_CORE_MC4_ADDR (0x0000040E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR); + AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr); + @endcode + @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM. +**/ +#define MSR_CORE_MC4_ADDR 0x0000040E + + +/** + Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR + register is either not implemented or contains no address if the ADDRV flag + in the MSR_MC3_STATUS register is clear. When not implemented in the + processor, all reads and writes to this MSR will cause a general-protection + exception. + + @param ECX MSR_CORE_MC3_ADDR (0x00000412) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR); + AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr); + @endcode + @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM. +**/ +#define MSR_CORE_MC3_ADDR 0x00000412 + + +/** + Unique. + + @param ECX MSR_CORE_MC3_MISC (0x00000413) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC); + AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr); + @endcode + @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM. +**/ +#define MSR_CORE_MC3_MISC 0x00000413 + + +/** + Unique. + + @param ECX MSR_CORE_MC5_CTL (0x00000414) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL); + AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr); + @endcode + @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM. +**/ +#define MSR_CORE_MC5_CTL 0x00000414 + + +/** + Unique. + + @param ECX MSR_CORE_MC5_STATUS (0x00000415) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS); + AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr); + @endcode + @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM. +**/ +#define MSR_CORE_MC5_STATUS 0x00000415 + + +/** + Unique. + + @param ECX MSR_CORE_MC5_ADDR (0x00000416) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR); + AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr); + @endcode + @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM. +**/ +#define MSR_CORE_MC5_ADDR 0x00000416 + + +/** + Unique. + + @param ECX MSR_CORE_MC5_MISC (0x00000417) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC); + AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr); + @endcode + @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM. +**/ +#define MSR_CORE_MC5_MISC 0x00000417 + + +/** + Unique. See Table 2-2. + + @param ECX MSR_CORE_IA32_EFER (0xC0000080) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_CORE_IA32_EFER_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_CORE_IA32_EFER_REGISTER. + + Example usage + @code + MSR_CORE_IA32_EFER_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER); + AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64); + @endcode + @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM. +**/ +#define MSR_CORE_IA32_EFER 0xC0000080 + +/** + MSR information returned for MSR index #MSR_CORE_IA32_EFER +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:11; + /// + /// [Bit 11] Execute Disable Bit Enable. + /// + UINT32 NXE:1; + UINT32 Reserved2:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_CORE_IA32_EFER_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h new file mode 100644 index 0000000000..a8da54c394 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h @@ -0,0 +1,2539 @@ +/** @file + MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __GOLDMONT_MSR_H__ +#define __GOLDMONT_MSR_H__ + +#include + +/** + Is Intel Atom processors based on the Goldmont microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x5C \ + ) \ + ) + +/** + Core. Control Features in Intel 64Processor (R/W). + + @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. +**/ +#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock bit (R/WL) + /// + UINT32 Lock:1; + /// + /// [Bit 1] Enable VMX inside SMX operation (R/WL) + /// + UINT32 EnableVmxInsideSmx:1; + /// + /// [Bit 2] Enable VMX outside SMX operation (R/WL) + /// + UINT32 EnableVmxOutsideSmx:1; + UINT32 Reserved1:5; + /// + /// [Bits 14:8] SENTER local function enables (R/WL) + /// + UINT32 SenterLocalFunctionEnables:7; + /// + /// [Bit 15] SENTER global functions enable (R/WL) + /// + UINT32 SenterGlobalEnable:1; + UINT32 Reserved2:2; + /// + /// [Bit 18] SGX global functions enable (R/WL) + /// + UINT32 SgxEnable:1; + UINT32 Reserved3:13; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER; + + +/** + Package. See http://biosbits.org. + + @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO); + AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + /// + /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, + /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to + /// specify an temperature offset. + /// + UINT32 TJOFFSET:1; + UINT32 Reserved3:1; + UINT32 Reserved4:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved5:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. See http://biosbits.org. + + @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type + MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type + MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power). for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 0000b: + /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8 + /// 0111b: C9 1000b: C10. + /// + UINT32 Limit:4; + UINT32 Reserved1:6; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map + /// IO_read instructions sent to IO register specified by + /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register + /// until next reset. + /// + UINT32 CFGLock:1; + UINT32 Reserved3:16; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. + Accessible only while in SMM. + + @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. +**/ +#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:26; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and the + /// MSR_SMM_FEATURE_CONTROL is supported. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is + /// supported. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. Default value is 1. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:3; + /// + /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + UINT32 Reserved4:3; + /// + /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved6:3; + /// + /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved9:3; + /// + /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors + /// that support Intel Turbo Boost Technology, the turbo mode feature is + /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: + /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: + /// EAX[1] reports the processor's support of turbo mode is enabled. Note: + /// the power-on default value is used by BIOS to detect hardware support + /// of turbo mode. If power-on default value is 1, turbo mode is available + /// in the processor. If power-on default value is 0, turbo mode is not + /// available. + /// + UINT32 TurboModeDisable:1; + UINT32 Reserved10:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER; + + +/** + Miscellaneous Feature Control (R/W). + + @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. +**/ +#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the + /// L2 hardware prefetcher, which fetches additional lines of code or data + /// into the L2 cache. + /// + UINT32 L2HardwarePrefetcherDisable:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables + /// the L1 data cache prefetcher, which fetches the next cache line into + /// L1 data cache. + /// + UINT32 DCUHardwarePrefetcherDisable:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER; + + +/** + Package. See http://biosbits.org. + + @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER. + + Example usage + @code + MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT); + AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. +**/ +#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA + +/** + MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables + /// hardware coordination of Enhanced Intel Speedstep Technology request + /// from processor cores; When 1, disables hardware coordination of + /// Enhanced Intel Speedstep Technology requests. + /// + UINT32 EISTHardwareCoordinationDisable:1; + UINT32 Reserved1:21; + /// + /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then + /// thermal interrupt on one core is routed to all cores. + /// + UINT32 ThermalInterruptCoordinationEnable:1; + UINT32 Reserved2:9; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies + Maximum Ratio Limit for each Core Group. Max ratio for groups with more + cores must decrease monotonically. For groups with less than 4 cores, the + max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must + be 22 or less. For groups with more than 5 cores, the max ratio must be 16 + or less.. + + @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT); + AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 0 threshold. + /// + UINT32 MaxRatioLimitGroup0:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 1 threshold and greater than Group 0 threshold. + /// + UINT32 MaxRatioLimitGroup1:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 2 threshold and greater than Group 1 threshold. + /// + UINT32 MaxRatioLimitGroup2:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 3 threshold and greater than Group 2 threshold. + /// + UINT32 MaxRatioLimitGroup3:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 4 threshold and greater than Group 3 threshold. + /// + UINT32 MaxRatioLimitGroup4:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 5 threshold and greater than Group 4 threshold. + /// + UINT32 MaxRatioLimitGroup5:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 6 threshold and greater than Group 5 threshold. + /// + UINT32 MaxRatioLimitGroup6:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7 + /// Maximum turbo ratio limit when number of active cores is less or equal + /// to Group 7 threshold and greater than Group 6 threshold. + /// + UINT32 MaxRatioLimitGroup7:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of + 0 threshold is ignored. + + @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER. + + Example usage + @code + MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT); + AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM. +**/ +#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE + +/** + MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of + /// active cores to operate under Group 0 Max Turbo Ratio limit. + /// + UINT32 CoreCountThresholdGroup0:8; + /// + /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of + /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be + /// greater than Group 0 Core Count. + /// + UINT32 CoreCountThresholdGroup1:8; + /// + /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of + /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be + /// greater than Group 1 Core Count. + /// + UINT32 CoreCountThresholdGroup2:8; + /// + /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of + /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be + /// greater than Group 2 Core Count. + /// + UINT32 CoreCountThresholdGroup3:8; + /// + /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of + /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be + /// greater than Group 3 Core Count. + /// + UINT32 CoreCountThresholdGroup4:8; + /// + /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of + /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be + /// greater than Group 4 Core Count. + /// + UINT32 CoreCountThresholdGroup5:8; + /// + /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of + /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be + /// greater than Group 5 Core Count. + /// + UINT32 CoreCountThresholdGroup6:8; + /// + /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of + /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be + /// greater than Group 6 Core Count and not less than the total number of + /// processor cores in the package. E.g. specify 255. + /// + UINT32 CoreCountThresholdGroup7:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER; + + +/** + Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, + "Filtering of Last Branch Records.". + + @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER. + + Example usage + @code + MSR_GOLDMONT_LBR_SELECT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT); + AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_GOLDMONT_LBR_SELECT 0x000001C8 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + /// + /// [Bit 9] EN_CALL_STACK. + /// + UINT32 EN_CALL_STACK:1; + UINT32 Reserved1:22; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_LBR_SELECT_REGISTER; + + +/** + Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that + points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP. + + @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9 + + +/** + Core. Power Control Register. See http://biosbits.org. + + @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_POWER_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL); + AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM. +**/ +#define MSR_GOLDMONT_POWER_CTL 0x000001FC + +/** + MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the + /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology + /// operating point when all execution cores enter MWAIT (C1). + /// + UINT32 C1EEnable:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_POWER_CTL_REGISTER; + + +/** + Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update + CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in + the package. Lower 64 bits of an 128-bit external entropy value for key + derivation of an enclave. + + @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0); + @endcode + @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM. +**/ +#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300 + + +// +// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM. +// +#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0 + + +/** + Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of + an 128-bit external entropy value for key derivation of an enclave. + + @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1); + @endcode + @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM. +**/ +#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301 + + +// +// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM. +// +#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1 + + +/** + Core. See Table 2-2. See Section 18.2.4, "Architectural Performance + Monitoring Version 4.". + + @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. +**/ +#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 + +/** + MSR information returned for MSR index + #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Set 1 to clear Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Set 1 to clear Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Set 1 to clear Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Set 1 to clear Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Set 1 to clear Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Set 1 to clear Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Set 1 to clear Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Set 1 to clear Trace_ToPA_PMI. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] Set 1 to clear LBR_Frz. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Set 1 to clear CTR_Frz. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Set 1 to clear ASCI. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Set 1 to clear Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + /// + /// [Bit 63] Set 1 to clear CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; + + +/** + Core. See Table 2-2. See Section 18.2.4, "Architectural Performance + Monitoring Version 4.". + + @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. +**/ +#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 + +/** + MSR information returned for MSR index + #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1. + /// + UINT32 Ovf_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] Set 1 to cause LBR_Frz = 1. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Set 1 to cause CTR_Frz = 1. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Set 1 to cause ASCI = 1. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Set 1 to cause Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + UINT32 Reserved4:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; + + +/** + Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling + (PEBS).". + + @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE); + AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS trigger and recording for the programmed event + /// (precise or otherwise) on IA32_PMC0. (R/W). + /// + UINT32 Enable:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PEBS_ENABLE_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr); + @endcode + @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. +**/ +#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C6 states. Count at the same frequency as the TSC. + + @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9 + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY); + AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr); + @endcode + @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. +**/ +#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC + + +/** + Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM. +**/ +#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from + /// further changes. + /// + UINT32 Lock:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if + /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the + /// logical processors are prevented from executing SMM code outside the + /// ranges defined by the SMRR. When set to '1' any logical processor in + /// the package that attempts to execute SMM code not within the ranges + /// defined by the SMRR will assert an unrecoverable MCE. + /// + UINT32 SMM_Code_Chk_En:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER; + + +/** + Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical + processors in the package. Available only while in SMM and + MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. + + @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER. + + Example usage + @code + MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED); + AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM. +**/ +#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2 + + +/** + Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical + processors in the package. Available only while in SMM. + + @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER. + + Example usage + @code + MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED); + AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM. +**/ +#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3 + + +/** + Core. Trace Control Register (R/W). + + @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM. +**/ +#define MSR_IA32_RTIT_CTL 0x00000570 + +/** + MSR information returned for MSR index #MSR_IA32_RTIT_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] TraceEn. + /// + UINT32 TraceEn:1; + /// + /// [Bit 1] CYCEn. + /// + UINT32 CYCEn:1; + /// + /// [Bit 2] OS. + /// + UINT32 OS:1; + /// + /// [Bit 3] User. + /// + UINT32 User:1; + UINT32 Reserved1:3; + /// + /// [Bit 7] CR3 filter. + /// + UINT32 CR3:1; + /// + /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn. + /// + UINT32 ToPA:1; + /// + /// [Bit 9] MTCEn. + /// + UINT32 MTCEn:1; + /// + /// [Bit 10] TSCEn. + /// + UINT32 TSCEn:1; + /// + /// [Bit 11] DisRETC. + /// + UINT32 DisRETC:1; + UINT32 Reserved2:1; + /// + /// [Bit 13] BranchEn. + /// + UINT32 BranchEn:1; + /// + /// [Bits 17:14] MTCFreq. + /// + UINT32 MTCFreq:4; + UINT32 Reserved3:1; + /// + /// [Bits 22:19] CYCThresh. + /// + UINT32 CYCThresh:4; + UINT32 Reserved4:1; + /// + /// [Bits 27:24] PSBFreq. + /// + UINT32 PSBFreq:4; + UINT32 Reserved5:4; + /// + /// [Bits 35:32] ADDR0_CFG. + /// + UINT32 ADDR0_CFG:4; + /// + /// [Bits 39:36] ADDR1_CFG. + /// + UINT32 ADDR1_CFG:4; + UINT32 Reserved6:24; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER; + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, + "RAPL Interfaces.". + + @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT); + @endcode + @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Power Units. Power related information (in Watts) is in + /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits + /// 3:0. Default value is 1000b, indicating power unit is in 3.9 + /// milliWatts increment. + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Energy Status Units. Energy related information (in + /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned + /// integer represented by bits 12:8. Default value is 01110b, indicating + /// energy unit is in 61 microJoules. + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Time Unit. Time related information (in seconds) is in + /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits + /// 19:16. Default value is 1010b, indicating power unit is in 0.977 + /// millisecond. + /// + UINT32 TimeUnit:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. + + @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL); + AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM. +**/ +#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C3 state. + /// + UINT32 InterruptResponseTimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit + /// of the interrupt response time limit. See Table 2-19 for supported + /// time unit encodings. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PKGC3_IRTL_REGISTER; + + +/** + Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines + the interrupt response time limit used by the processor to manage transition + to package C6 or C7S state. Note: C-state values are processor specific + C-state code names, unrelated to MWAIT extension C-state parameters or ACPI + CStates. + + @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1); + AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM. +**/ +#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C6 or C7S state. + /// + UINT32 InterruptResponseTimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit + /// of the interrupt response time limit. See Table 2-19 for supported + /// time unit encodings. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PKGC_IRTL1_REGISTER; + + +/** + Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the + interrupt response time limit used by the processor to manage transition to + package C7 state. Note: C-state values are processor specific C-state code + names, unrelated to MWAIT extension C-state parameters or ACPI CStates. + + @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2); + AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM. +**/ +#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C7 state. + /// + UINT32 InterruptResponseTimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit + /// of the interrupt response time limit. See Table 2-19 for supported + /// time unit encodings. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PKGC_IRTL2_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C2 states. Count at the same frequency as the TSC. + + @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr); + @endcode + @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. +**/ +#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D + + +/** + Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package + RAPL Domain.". + + @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr); + @endcode + @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. +**/ +#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610 + + +/** + Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS); + @endcode + @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. +**/ +#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611 + + +/** + Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS); + @endcode + @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. +**/ +#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613 + + +/** + Package. PKG RAPL Parameters (R/W). + + @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. +**/ +#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package + /// RAPL Domain.". + /// + UINT32 ThermalSpecPower:15; + UINT32 Reserved1:1; + /// + /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL + /// Domain.". + /// + UINT32 MinimumPower:15; + UINT32 Reserved2:1; + /// + /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL + /// Domain.". + /// + UINT32 MaximumPower:15; + UINT32 Reserved3:1; + /// + /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 + + /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value + /// represented. by bits 52:48, "Z" is an unsigned integer represented by + /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of + /// MSR_RAPL_POWER_UNIT. + /// + UINT32 MaximumTimeWindow:7; + UINT32 Reserved4:9; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER; + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS); + @endcode + @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619 + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS); + @endcode + @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Note: C-state values are processor specific C-state code names,. + Package C10 Residency Counter. (R/O) Value since last reset that the entire + SOC is in an S0i3 state. Count at the same frequency as the TSC. + + @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY); + AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr); + @endcode + @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM. +**/ +#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632 + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS); + @endcode + @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS); + @endcode + @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. +**/ +#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641 + + +/** + Package. ConfigTDP Control (R/W). + + @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER. + + Example usage + @code + MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO); + AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. +**/ +#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C + +/** + MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this + /// field. + /// + UINT32 MAX_NON_TURBO_RATIO:8; + UINT32 Reserved1:23; + /// + /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the + /// content of this register is locked until a reset. + /// + UINT32 TURBO_ACTIVATION_RATIO_Lock:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER; + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F + +/** + MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is + /// reduced below the operating system request due to assertion of + /// external PROCHOT. + /// + UINT32 PROCHOTStatus:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + /// + /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL1. + /// + UINT32 PL1Status:1; + /// + /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL2. + /// + UINT32 PL2Status:1; + UINT32 Reserved1:5; + /// + /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced + /// below the operating system request due to domain-level power limiting. + /// + UINT32 PowerLimitingStatus:1; + /// + /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + /// + /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced + /// below the operating system request due to multi-core turbo limits. + /// + UINT32 MaxTurboLimitStatus:1; + /// + /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + /// + /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency + /// is reduced below the operating system request due to Turbo transition + /// attenuation. This prevents performance degradation due to frequent + /// operating ratio changes. + /// + UINT32 TurboTransitionAttenuationStatus:1; + /// + /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency + /// is reduced below the maximum efficiency frequency. + /// + UINT32 MaximumEfficiencyFrequencyStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + /// + /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates + /// that the Package Level PL1 Power Limiting Status bit has asserted + /// since the log bit was last cleared. This log bit will remain set until + /// cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that + /// the Package Level PL2 Power Limiting Status bit has asserted since the + /// log bit was last cleared. This log bit will remain set until cleared + /// by software writing 0. + /// + UINT32 PL2Log:1; + UINT32 Reserved3:5; + /// + /// [Bit 25] Core Power Limiting Log When set, indicates that the Core + /// Power Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CorePowerLimitingLog:1; + /// + /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + /// + /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo + /// Limit Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MaxTurboLimitLog:1; + /// + /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + /// + /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the + /// Turbo Transition Attenuation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 TurboTransitionAttenuationLog:1; + /// + /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that + /// the Maximum Efficiency Frequency Status bit has asserted since the log + /// bit was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 MaximumEfficiencyFrequencyLog:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER; + + +/** + Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch + record registers on the last branch record stack. The From_IP part of the + stack contains pointers to the source instruction . See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.6 and record format in Section + 17.4.8.1. + + @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER. + + Example usage + @code + MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP); + AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM. + @{ +**/ +#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680 +#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681 +#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682 +#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683 +#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684 +#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685 +#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686 +#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687 +#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688 +#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689 +#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A +#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B +#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C +#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D +#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E +#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F +#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690 +#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691 +#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692 +#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693 +#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694 +#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695 +#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696 +#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697 +#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698 +#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699 +#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A +#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B +#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C +#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D +#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E +#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F +/// @} + +/** + MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP + to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] From Linear Address (R/W). + /// + UINT32 FromLinearAddress:32; + /// + /// [Bit 47:32] From Linear Address (R/W). + /// + UINT32 FromLinearAddressHi:16; + /// + /// [Bits 62:48] Signed extension of bits 47:0. + /// + UINT32 SignedExtension:15; + /// + /// [Bit 63] Mispred. + /// + UINT32 Mispred:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER; + + +/** + Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record + registers on the last branch record stack. The To_IP part of the stack + contains pointers to the Destination instruction and elapsed cycles from + last LBR update. See also: - Section 17.6. + + @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER. + + Example usage + @code + MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. + MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM. + @{ +**/ +#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0 +#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1 +#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2 +#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3 +#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4 +#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5 +#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6 +#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7 +#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8 +#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9 +#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA +#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB +#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC +#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD +#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE +#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF +#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0 +#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1 +#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2 +#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3 +#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4 +#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5 +#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6 +#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7 +#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8 +#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9 +#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA +#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB +#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC +#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD +#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE +#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF +/// @} + +/** + MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to + #MSR_GOLDMONT_LASTBRANCH_31_TO_IP. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Target Linear Address (R/W). + /// + UINT32 TargetLinearAddress:32; + /// + /// [Bit 47:32] Target Linear Address (R/W). + /// + UINT32 TargetLinearAddressHi:16; + /// + /// [Bits 63:48] Elapsed cycles from last update to the LBR. + /// + UINT32 ElapsedCycles:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER; + + +/** + Core. Resource Association Register (R/W). + + @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. +**/ +#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F + +/** + MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + /// + /// [Bits 33:32] COS (R/W). + /// + UINT32 COS:2; + UINT32 Reserved2:30; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER; + + +/** + Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, + ECX=1):EDX.COS_MAX[15:0] >=n. + + @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM. + MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM. + MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM. + @{ +**/ +#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10 +#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11 +#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12 +/// @} + +/** + MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to + #MSR_GOLDMONT_IA32_L2_QOS_MASK_2. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement + /// + UINT32 CBM:8; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER; + + +/** + Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H, + ECX=1):EDX.COS_MAX[15:0] >=3. + + @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3 + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER. + + Example usage + @code + MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3); + AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64); + @endcode + @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM. +**/ +#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement + /// + UINT32 CBM:20; + UINT32 Reserved1:12; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER; + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h new file mode 100644 index 0000000000..95e7de91df --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h @@ -0,0 +1,266 @@ +/** @file + MSR Definitions for Intel Atom processors based on the Goldmont Plus microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __GOLDMONT_PLUS_MSR_H__ +#define __GOLDMONT_PLUS_MSR_H__ + +#include + +/** + Is Intel Atom processors based on the Goldmont plus microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x7A \ + ) \ + ) + +/** + Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based + Sampling (PEBS).". + + @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE); + AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64); + @endcode +**/ +#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS trigger and recording for the programmed event + /// (precise or otherwise) on IA32_PMC0. + /// + UINT32 Fix_Me_1:1; + /// + /// [Bit 1] Enable PEBS trigger and recording for the programmed event + /// (precise or otherwise) on IA32_PMC1. + /// + UINT32 Fix_Me_2:1; + /// + /// [Bit 2] Enable PEBS trigger and recording for the programmed event + /// (precise or otherwise) on IA32_PMC2. + /// + UINT32 Fix_Me_3:1; + /// + /// [Bit 3] Enable PEBS trigger and recording for the programmed event + /// (precise or otherwise) on IA32_PMC3. + /// + UINT32 Fix_Me_4:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0. + /// + UINT32 Fix_Me_5:1; + /// + /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1. + /// + UINT32 Fix_Me_6:1; + /// + /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2. + /// + UINT32 Fix_Me_7:1; + UINT32 Reserved2:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER; + + +/** + Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up + the first entry of the 32-entry LBR stack. The From_IP part of the stack + contains pointers to the source instruction. See also: - Last Branch Record + Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and + .. Exception Recording for Processors based on Goldmont Plus + Microarchitecture.". + + @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP); + AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr); + @endcode +**/ +#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A +#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B +#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C +#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D +#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E +#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F +#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A +#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B +#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C +#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D +#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E +#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F + +/** + Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up + the first entry of the 32-entry LBR stack. The To_IP part of the stack + contains pointers to the Destination instruction. See also: - Section 17.7, + "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors + based on Goldmont Plus Microarchitecture.". + + @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP); + AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr); + @endcode +**/ +#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA +#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB +#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC +#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD +#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE +#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF +#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA +#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB +#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC +#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD +#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE +#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF + + +/** + Core. Last Branch Record N Additional Information (R/W) One of the three + MSRs that make up the first entry of the 32-entry LBR stack. This part of + the stack contains flag and elapsed cycle information. See also: - Last + Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.". + + @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N); + AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr); + @endcode +**/ +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9 +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE +#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h new file mode 100644 index 0000000000..4fa6000f70 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h @@ -0,0 +1,6400 @@ +/** @file + MSR Definitions for Intel processors based on the Haswell-E microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __HASWELL_E_MSR_H__ +#define __HASWELL_E_MSR_H__ + +#include + +/** + Is Intel processors based on the Haswell-E microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x3F \ + ) \ + ) + +/** + Package. Configured State of Enabled Processor Core Count and Logical + Processor Count (RO) - After a Power-On RESET, enumerates factory + configuration of the number of processor cores and logical processors in the + physical package. - Following the sequence of (i) BIOS modified a + Configuration Mask which selects a subset of processor cores to be active + post RESET and (ii) a RESET event after the modification, enumerates the + current configuration of enabled processor core count and logical processor + count in the physical package. + + @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER. + + Example usage + @code + MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT); + @endcode + @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM. +**/ +#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are + /// currently enabled (by either factory configuration or BIOS + /// configuration) in the physical package. + /// + UINT32 Core_Count:16; + /// + /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that + /// are currently enabled (by either factory configuration or BIOS + /// configuration) in the physical package. + /// + UINT32 Thread_Count:16; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER; + + +/** + Thread. A Hardware Assigned ID for the Logical Processor (RO). + + @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER. + + Example usage + @code + MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO); + @endcode + @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM. +**/ +#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific + /// numerical. value physically assigned to each logical processor. This + /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within + /// a physical package. + /// + UINT32 Logical_Processor_ID:8; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI C-states. `See http://biosbits.org. `__. + + @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) + /// 011b: C6 (retention) 111b: No Package C state limits. All C states + /// supported by the processor are available. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + /// + /// [Bit 29] Package C State Demotion Enable (R/W). + /// + UINT32 CStateDemotion:1; + /// + /// [Bit 30] Package C State UnDemotion Enable (R/W). + /// + UINT32 CStateUndemotion:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Thread. Global Machine Check Capability (R/O). + + @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP); + @endcode + @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. +**/ +#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count. + /// + UINT32 Count:8; + /// + /// [Bit 8] MCG_CTL_P. + /// + UINT32 MCG_CTL_P:1; + /// + /// [Bit 9] MCG_EXT_P. + /// + UINT32 MCG_EXT_P:1; + /// + /// [Bit 10] MCP_CMCI_P. + /// + UINT32 MCP_CMCI_P:1; + /// + /// [Bit 11] MCG_TES_P. + /// + UINT32 MCG_TES_P:1; + UINT32 Reserved1:4; + /// + /// [Bits 23:16] MCG_EXT_CNT. + /// + UINT32 MCG_EXT_CNT:8; + /// + /// [Bit 24] MCG_SER_P. + /// + UINT32 MCG_SER_P:1; + /// + /// [Bit 25] MCG_EM_P. + /// + UINT32 MCG_EM_P:1; + /// + /// [Bit 26] MCG_ELOG_P. + /// + UINT32 MCG_ELOG_P:1; + UINT32 Reserved2:5; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER; + + +/** + THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. +**/ +#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:26; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER; + + +/** + Package. MC Bank Error Configuration (R/W). + + @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER. + + Example usage + @code + MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL); + AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. +**/ +#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F + +/** + MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank + /// to log additional info in bits 36:32. + /// + UINT32 MemErrorLogEnable:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_ERROR_CONTROL_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT); + @endcode + @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5 core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6 core active. + /// + UINT32 Maximum6C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio + /// limit of 7 core active. + /// + UINT32 Maximum7C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio + /// limit of 8 core active. + /// + UINT32 Maximum8C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER. + + Example usage + @code + MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1); + @endcode + @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. +**/ +#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE + +/** + MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio + /// limit of 9 core active. + /// + UINT32 Maximum9C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio + /// limit of 10 core active. + /// + UINT32 Maximum10C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio + /// limit of 11 core active. + /// + UINT32 Maximum11C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio + /// limit of 12 core active. + /// + UINT32 Maximum12C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio + /// limit of 13 core active. + /// + UINT32 Maximum13C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio + /// limit of 14 core active. + /// + UINT32 Maximum14C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio + /// limit of 15 core active. + /// + UINT32 Maximum15C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio + /// limit of 16 core active. + /// + UINT32 Maximum16C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER. + + Example usage + @code + MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2); + @endcode + @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM. +**/ +#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF + +/** + MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio + /// limit of 17 core active. + /// + UINT32 Maximum17C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio + /// limit of 18 core active. + /// + UINT32 Maximum18C:8; + UINT32 Reserved1:16; + UINT32 Reserved2:31; + /// + /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, + /// the processor uses override configuration specified in + /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and + /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set + /// configuration (Default). + /// + UINT32 TurboRatioLimitConfigurationSemaphore:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER; + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O). + + @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT); + @endcode + @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Package. Energy Status Units Energy related information + /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 + /// micro-joules). + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL + /// Interfaces.". + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices. + + @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER. + + Example usage + @code + MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS); + @endcode + @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration + /// to enable DRAM RAPL mode 0 (Direct VR). + /// + UINT32 Energy:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER; + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS); + @endcode + @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Configuration of PCIE PLL Relative to BCLK(R/W). + + @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER. + + Example usage + @code + MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO); + AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM. +**/ +#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E + +/** + MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz + /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use + /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz + /// operation. + /// + UINT32 PCIERatio:2; + /// + /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of + /// PCIE Ratio. + /// + UINT32 LPLLSelect:1; + /// + /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out + /// before re-locking Gen2/Gen3 PLLs. + /// + UINT32 LONGRESET:1; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER; + + +/** + Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio + fields represent the widest possible range of uncore frequencies. Writing to + these fields allows software to control the minimum and the maximum + frequency that hardware will select. + + @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT); + AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 MAX_RATIO:7; + UINT32 Reserved1:1; + /// + /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 MIN_RATIO:7; + UINT32 Reserved2:17; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER; + +/** + Package. Reserved (R/O) Reads return 0. + + @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS); + @endcode + @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690 + +/** + MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is + /// reduced below the operating system request due to assertion of + /// external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + /// + /// [Bit 2] Power Budget Management Status (R0) When set, frequency is + /// reduced below the operating system request due to PBM limit. + /// + UINT32 PowerBudgetManagementStatus:1; + /// + /// [Bit 3] Platform Configuration Services Status (R0) When set, + /// frequency is reduced below the operating system request due to PCS + /// limit. + /// + UINT32 PlatformConfigurationServicesStatus:1; + UINT32 Reserved1:1; + /// + /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) + /// When set, frequency is reduced below the operating system request + /// because the processor has detected that utilization is low. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + UINT32 Reserved3:1; + /// + /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced + /// below the operating system request due to Multi-Core Turbo limits. + /// + UINT32 MultiCoreTurboStatus:1; + UINT32 Reserved4:2; + /// + /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced + /// below max non-turbo P1. + /// + UINT32 FrequencyP1Status:1; + /// + /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When + /// set, frequency is reduced below max n-core turbo frequency. + /// + UINT32 TurboFrequencyLimitingStatus:1; + /// + /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is + /// reduced below the operating system request. + /// + UINT32 FrequencyLimitingStatus:1; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + /// + /// [Bit 18] Power Budget Management Log When set, indicates that the PBM + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 PowerBudgetManagementLog:1; + /// + /// [Bit 19] Platform Configuration Services Log When set, indicates that + /// the PCS Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 PlatformConfigurationServicesLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, + /// indicates that the AUBFC Status bit has asserted since the log bit was + /// last cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + UINT32 Reserved6:1; + /// + /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + UINT32 Reserved7:1; + /// + /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core + /// Turbo Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MultiCoreTurboLog:1; + UINT32 Reserved8:2; + /// + /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core + /// Frequency P1 Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CoreFrequencyP1Log:1; + /// + /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, + /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 TurboFrequencyLimitingLog:1; + /// + /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core + /// Frequency Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CoreFrequencyLimitingLog:1; + UINT32 Reserved9:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER; + + +/** + THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H, + ECX=0):EBX.RDT-M[bit 12] = 1. + + @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER. + + Example usage + @code + MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL); + AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. +**/ +#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D + +/** + MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3 + /// occupancy monitoring all other encoding reserved.. + /// + UINT32 EventID:8; + UINT32 Reserved1:24; + /// + /// [Bits 41:32] RMID (RW). + /// + UINT32 RMID:10; + UINT32 Reserved2:22; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER; + + +/** + THREAD. Resource Association Register (R/W).. + + @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER. + + Example usage + @code + MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC); + AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64); + @endcode + @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. +**/ +#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F + +/** + MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] RMID. + /// + UINT32 RMID:10; + UINT32 Reserved1:22; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER; + + +/** + Package. Uncore perfmon per-socket global control. + + @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr); + @endcode + @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM. +**/ +#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700 + + +/** + Package. Uncore perfmon per-socket global status. + + @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM. +**/ +#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701 + + +/** + Package. Uncore perfmon per-socket global configuration. + + @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG); + AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr); + @endcode + @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM. +**/ +#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702 + + +/** + Package. Uncore U-box UCLK fixed counter control. + + @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703 + + +/** + Package. Uncore U-box UCLK fixed counter. + + @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704 + + +/** + Package. Uncore U-box perfmon event select for U-box counter 0. + + @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705 + + +/** + Package. Uncore U-box perfmon event select for U-box counter 1. + + @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706 + + +/** + Package. Uncore U-box perfmon U-box wide status. + + @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708 + + +/** + Package. Uncore U-box perfmon counter 0. + + @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709 + + +/** + Package. Uncore U-box perfmon counter 1. + + @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A + + +/** + Package. Uncore PCU perfmon for PCU-box-wide control. + + @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 0. + + @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 1. + + @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 2. + + @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 3. + + @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714 + + +/** + Package. Uncore PCU perfmon box-wide filter. + + @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715 + + +/** + Package. Uncore PCU perfmon box wide status. + + @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716 + + +/** + Package. Uncore PCU perfmon counter 0. + + @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717 + + +/** + Package. Uncore PCU perfmon counter 1. + + @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718 + + +/** + Package. Uncore PCU perfmon counter 2. + + @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719 + + +/** + Package. Uncore PCU perfmon counter 3. + + @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A + + +/** + Package. Uncore SBo 0 perfmon for SBo 0 box-wide control. + + @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720 + + +/** + Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0. + + @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721 + + +/** + Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1. + + @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722 + + +/** + Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2. + + @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723 + + +/** + Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3. + + @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724 + + +/** + Package. Uncore SBo 0 perfmon box-wide filter. + + @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725 + + +/** + Package. Uncore SBo 0 perfmon counter 0. + + @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726 + + +/** + Package. Uncore SBo 0 perfmon counter 1. + + @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727 + + +/** + Package. Uncore SBo 0 perfmon counter 2. + + @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728 + + +/** + Package. Uncore SBo 0 perfmon counter 3. + + @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729 + + +/** + Package. Uncore SBo 1 perfmon for SBo 1 box-wide control. + + @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A + + +/** + Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0. + + @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B + + +/** + Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1. + + @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C + + +/** + Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2. + + @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D + + +/** + Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3. + + @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E + + +/** + Package. Uncore SBo 1 perfmon box-wide filter. + + @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F + + +/** + Package. Uncore SBo 1 perfmon counter 0. + + @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730 + + +/** + Package. Uncore SBo 1 perfmon counter 1. + + @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731 + + +/** + Package. Uncore SBo 1 perfmon counter 2. + + @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732 + + +/** + Package. Uncore SBo 1 perfmon counter 3. + + @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733 + + +/** + Package. Uncore SBo 2 perfmon for SBo 2 box-wide control. + + @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734 + + +/** + Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0. + + @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735 + + +/** + Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1. + + @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736 + + +/** + Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2. + + @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737 + + +/** + Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3. + + @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738 + + +/** + Package. Uncore SBo 2 perfmon box-wide filter. + + @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739 + + +/** + Package. Uncore SBo 2 perfmon counter 0. + + @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A + + +/** + Package. Uncore SBo 2 perfmon counter 1. + + @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B + + +/** + Package. Uncore SBo 2 perfmon counter 2. + + @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C + + +/** + Package. Uncore SBo 2 perfmon counter 3. + + @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D + + +/** + Package. Uncore SBo 3 perfmon for SBo 3 box-wide control. + + @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E + + +/** + Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0. + + @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F + + +/** + Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1. + + @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740 + + +/** + Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2. + + @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741 + + +/** + Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3. + + @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742 + + +/** + Package. Uncore SBo 3 perfmon box-wide filter. + + @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743 + + +/** + Package. Uncore SBo 3 perfmon counter 0. + + @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744 + + +/** + Package. Uncore SBo 3 perfmon counter 1. + + @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745 + + +/** + Package. Uncore SBo 3 perfmon counter 2. + + @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746 + + +/** + Package. Uncore SBo 3 perfmon counter 3. + + @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747 + + +/** + Package. Uncore C-box 0 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0. + + @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1. + + @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2. + + @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3. + + @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04 + + +/** + Package. Uncore C-box 0 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05 + + +/** + Package. Uncore C-box 0 perfmon box wide filter 1. + + @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06 + + +/** + Package. Uncore C-box 0 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07 + + +/** + Package. Uncore C-box 0 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08 + + +/** + Package. Uncore C-box 0 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09 + + +/** + Package. Uncore C-box 0 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A + + +/** + Package. Uncore C-box 0 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B + + +/** + Package. Uncore C-box 1 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0. + + @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1. + + @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2. + + @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3. + + @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14 + + +/** + Package. Uncore C-box 1 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15 + + +/** + Package. Uncore C-box 1 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16 + + +/** + Package. Uncore C-box 1 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17 + + +/** + Package. Uncore C-box 1 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18 + + +/** + Package. Uncore C-box 1 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19 + + +/** + Package. Uncore C-box 1 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A + + +/** + Package. Uncore C-box 1 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B + + +/** + Package. Uncore C-box 2 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0. + + @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1. + + @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2. + + @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3. + + @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24 + + +/** + Package. Uncore C-box 2 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25 + + +/** + Package. Uncore C-box 2 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26 + + +/** + Package. Uncore C-box 2 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27 + + +/** + Package. Uncore C-box 2 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28 + + +/** + Package. Uncore C-box 2 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29 + + +/** + Package. Uncore C-box 2 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A + + +/** + Package. Uncore C-box 2 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B + + +/** + Package. Uncore C-box 3 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0. + + @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1. + + @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2. + + @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3. + + @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34 + + +/** + Package. Uncore C-box 3 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35 + + +/** + Package. Uncore C-box 3 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36 + + +/** + Package. Uncore C-box 3 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37 + + +/** + Package. Uncore C-box 3 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38 + + +/** + Package. Uncore C-box 3 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39 + + +/** + Package. Uncore C-box 3 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A + + +/** + Package. Uncore C-box 3 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B + + +/** + Package. Uncore C-box 4 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0. + + @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1. + + @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2. + + @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3. + + @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44 + + +/** + Package. Uncore C-box 4 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45 + + +/** + Package. Uncore C-box 4 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46 + + +/** + Package. Uncore C-box 4 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47 + + +/** + Package. Uncore C-box 4 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48 + + +/** + Package. Uncore C-box 4 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49 + + +/** + Package. Uncore C-box 4 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A + + +/** + Package. Uncore C-box 4 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B + + +/** + Package. Uncore C-box 5 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0. + + @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1. + + @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2. + + @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3. + + @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54 + + +/** + Package. Uncore C-box 5 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55 + + +/** + Package. Uncore C-box 5 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56 + + +/** + Package. Uncore C-box 5 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57 + + +/** + Package. Uncore C-box 5 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58 + + +/** + Package. Uncore C-box 5 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59 + + +/** + Package. Uncore C-box 5 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A + + +/** + Package. Uncore C-box 5 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B + + +/** + Package. Uncore C-box 6 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0. + + @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1. + + @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2. + + @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3. + + @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64 + + +/** + Package. Uncore C-box 6 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65 + + +/** + Package. Uncore C-box 6 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66 + + +/** + Package. Uncore C-box 6 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67 + + +/** + Package. Uncore C-box 6 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68 + + +/** + Package. Uncore C-box 6 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69 + + +/** + Package. Uncore C-box 6 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A + + +/** + Package. Uncore C-box 6 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B + + +/** + Package. Uncore C-box 7 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0. + + @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1. + + @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2. + + @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3. + + @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74 + + +/** + Package. Uncore C-box 7 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75 + + +/** + Package. Uncore C-box 7 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76 + + +/** + Package. Uncore C-box 7 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77 + + +/** + Package. Uncore C-box 7 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78 + + +/** + Package. Uncore C-box 7 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79 + + +/** + Package. Uncore C-box 7 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A + + +/** + Package. Uncore C-box 7 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B + + +/** + Package. Uncore C-box 8 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0. + + @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1. + + @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2. + + @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3. + + @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84 + + +/** + Package. Uncore C-box 8 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85 + + +/** + Package. Uncore C-box 8 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86 + + +/** + Package. Uncore C-box 8 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87 + + +/** + Package. Uncore C-box 8 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88 + + +/** + Package. Uncore C-box 8 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89 + + +/** + Package. Uncore C-box 8 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A + + +/** + Package. Uncore C-box 8 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B + + +/** + Package. Uncore C-box 9 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0. + + @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1. + + @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2. + + @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3. + + @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94 + + +/** + Package. Uncore C-box 9 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95 + + +/** + Package. Uncore C-box 9 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96 + + +/** + Package. Uncore C-box 9 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97 + + +/** + Package. Uncore C-box 9 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98 + + +/** + Package. Uncore C-box 9 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99 + + +/** + Package. Uncore C-box 9 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A + + +/** + Package. Uncore C-box 9 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B + + +/** + Package. Uncore C-box 10 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0. + + @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1. + + @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2. + + @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3. + + @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4 + + +/** + Package. Uncore C-box 10 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5 + + +/** + Package. Uncore C-box 10 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6 + + +/** + Package. Uncore C-box 10 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7 + + +/** + Package. Uncore C-box 10 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8 + + +/** + Package. Uncore C-box 10 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9 + + +/** + Package. Uncore C-box 10 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA + + +/** + Package. Uncore C-box 10 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB + + +/** + Package. Uncore C-box 11 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0. + + @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1. + + @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2. + + @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3. + + @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4 + + +/** + Package. Uncore C-box 11 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5 + + +/** + Package. Uncore C-box 11 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6 + + +/** + Package. Uncore C-box 11 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7 + + +/** + Package. Uncore C-box 11 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8 + + +/** + Package. Uncore C-box 11 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9 + + +/** + Package. Uncore C-box 11 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA + + +/** + Package. Uncore C-box 11 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB + + +/** + Package. Uncore C-box 12 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0. + + @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1. + + @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2. + + @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3. + + @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4 + + +/** + Package. Uncore C-box 12 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5 + + +/** + Package. Uncore C-box 12 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6 + + +/** + Package. Uncore C-box 12 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7 + + +/** + Package. Uncore C-box 12 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8 + + +/** + Package. Uncore C-box 12 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9 + + +/** + Package. Uncore C-box 12 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA + + +/** + Package. Uncore C-box 12 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB + + +/** + Package. Uncore C-box 13 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0. + + @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1. + + @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2. + + @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3. + + @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4 + + +/** + Package. Uncore C-box 13 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5 + + +/** + Package. Uncore C-box 13 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6 + + +/** + Package. Uncore C-box 13 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7 + + +/** + Package. Uncore C-box 13 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8 + + +/** + Package. Uncore C-box 13 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9 + + +/** + Package. Uncore C-box 13 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA + + +/** + Package. Uncore C-box 13 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB + + +/** + Package. Uncore C-box 14 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0. + + @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1. + + @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2. + + @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3. + + @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4 + + +/** + Package. Uncore C-box 14 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5 + + +/** + Package. Uncore C-box 14 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6 + + +/** + Package. Uncore C-box 14 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7 + + +/** + Package. Uncore C-box 14 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8 + + +/** + Package. Uncore C-box 14 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9 + + +/** + Package. Uncore C-box 14 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA + + +/** + Package. Uncore C-box 14 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB + + +/** + Package. Uncore C-box 15 perfmon local box wide control. + + @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0 + + +/** + Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0. + + @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1 + + +/** + Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1. + + @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2 + + +/** + Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2. + + @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3 + + +/** + Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3. + + @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4 + + +/** + Package. Uncore C-box 15 perfmon box wide filter0. + + @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5 + + +/** + Package. Uncore C-box 15 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6 + + +/** + Package. Uncore C-box 15 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7 + + +/** + Package. Uncore C-box 15 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8 + + +/** + Package. Uncore C-box 15 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9 + + +/** + Package. Uncore C-box 15 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA + + +/** + Package. Uncore C-box 15 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB + + +/** + Package. Uncore C-box 16 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00 + + +/** + Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0. + + @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01 + + +/** + Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1. + + @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02 + + +/** + Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2. + + @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03 + + +/** + Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3. + + @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04 + + +/** + Package. Uncore C-box 16 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05 + + +/** + Package. Uncore C-box 16 perfmon box wide filter 1. + + @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06 + + +/** + Package. Uncore C-box 16 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07 + + +/** + Package. Uncore C-box 16 perfmon counter 0. + + @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08 + + +/** + Package. Uncore C-box 16 perfmon counter 1. + + @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09 + + +/** + Package. Uncore C-box 16 perfmon counter 2. + + @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A + + +/** + Package. Uncore C-box 16 perfmon counter 3. + + @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3); + AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr); + @endcode + @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM. +**/ +#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B + + +/** + Package. Uncore C-box 17 perfmon for box-wide control. + + @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10 + + +/** + Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0. + + @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11 + + +/** + Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1. + + @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12 + + +/** + Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2. + + @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13 + + +/** + Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3. + + @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14 + + +/** + Package. Uncore C-box 17 perfmon box wide filter 0. + + @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15 + + +/** + Package. Uncore C-box 17 perfmon box wide filter1. + + @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16 + +/** + Package. Uncore C-box 17 perfmon box wide status. + + @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM. +**/ +#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17 + + +/** + Package. Uncore C-box 17 perfmon counter n. + + @param ECX MSR_HASWELL_E_C17_PMON_CTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0); + AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr); + @endcode + @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM. + MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM. + MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM. + MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM. + @{ +**/ +#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18 +#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19 +#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A +#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B +/// @} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h new file mode 100644 index 0000000000..da5c2e497c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h @@ -0,0 +1,2631 @@ +/** @file + MSR Definitions for Intel processors based on the Haswell microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __HASWELL_MSR_H__ +#define __HASWELL_MSR_H__ + +#include + +/** + Is Intel processors based on the Haswell microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x3C || \ + DisplayModel == 0x45 || \ + DisplayModel == 0x46 \ + ) \ + ) + +/** + Package. + + @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_HASWELL_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO); + AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_HASWELL_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + UINT32 Reserved3:2; + /// + /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, + /// indicates that LPM is supported, and when set to 0, indicates LPM is + /// not supported. + /// + UINT32 LowPowerModeSupport:1; + /// + /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base + /// TDP level available. 01: One additional TDP level available. 02: Two + /// additional TDP level available. 11: Reserved. + /// + UINT32 ConfigTDPLevels:2; + UINT32 Reserved4:5; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + /// + /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the + /// minimum supported operating ratio in units of 100 MHz. + /// + UINT32 MinimumOperatingRatio:8; + UINT32 Reserved5:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PLATFORM_INFO_REGISTER; + + +/** + Thread. Performance Event Select for Counter n (R/W) Supports all fields + described inTable 2-2 and the fields below. + + @param ECX MSR_HASWELL_IA32_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER. + + Example usage + @code + MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64); + @endcode + @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM. + MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM. + MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186 +#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187 +#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189 +/// @} + +/** + MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0, + #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select: Selects a performance event logic unit. + /// + UINT32 EventSelect:8; + /// + /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to + /// detect on the selected event logic. + /// + UINT32 UMASK:8; + /// + /// [Bit 16] USR: Counts while in privilege level is not ring 0. + /// + UINT32 USR:1; + /// + /// [Bit 17] OS: Counts while in privilege level is ring 0. + /// + UINT32 OS:1; + /// + /// [Bit 18] Edge: Enables edge detection if set. + /// + UINT32 E:1; + /// + /// [Bit 19] PC: enables pin control. + /// + UINT32 PC:1; + /// + /// [Bit 20] INT: enables interrupt on counter overflow. + /// + UINT32 INT:1; + /// + /// [Bit 21] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. + /// + UINT32 ANY:1; + /// + /// [Bit 22] EN: enables the corresponding performance counter to commence + /// counting when this bit is set. + /// + UINT32 EN:1; + /// + /// [Bit 23] INV: invert the CMASK. + /// + UINT32 INV:1; + /// + /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding + /// performance counter increments each cycle if the event count is + /// greater than or equal to the CMASK. + /// + UINT32 CMASK:8; + UINT32 Reserved:32; + /// + /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, + /// AnyThread (bit 21) should be cleared to prevent incorrect results. + /// + UINT32 IN_TX:1; + UINT32 Reserved2:31; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER; + + +/** + Thread. Performance Event Select for Counter 2 (R/W) Supports all fields + described inTable 2-2 and the fields below. + + @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER. + + Example usage + @code + MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2); + AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64); + @endcode + @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM. +**/ +#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188 + +/** + MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select: Selects a performance event logic unit. + /// + UINT32 EventSelect:8; + /// + /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to + /// detect on the selected event logic. + /// + UINT32 UMASK:8; + /// + /// [Bit 16] USR: Counts while in privilege level is not ring 0. + /// + UINT32 USR:1; + /// + /// [Bit 17] OS: Counts while in privilege level is ring 0. + /// + UINT32 OS:1; + /// + /// [Bit 18] Edge: Enables edge detection if set. + /// + UINT32 E:1; + /// + /// [Bit 19] PC: enables pin control. + /// + UINT32 PC:1; + /// + /// [Bit 20] INT: enables interrupt on counter overflow. + /// + UINT32 INT:1; + /// + /// [Bit 21] AnyThread: When set to 1, it enables counting the associated + /// event conditions occurring across all logical processors sharing a + /// processor core. When set to 0, the counter only increments the + /// associated event conditions occurring in the logical processor which + /// programmed the MSR. + /// + UINT32 ANY:1; + /// + /// [Bit 22] EN: enables the corresponding performance counter to commence + /// counting when this bit is set. + /// + UINT32 EN:1; + /// + /// [Bit 23] INV: invert the CMASK. + /// + UINT32 INV:1; + /// + /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding + /// performance counter increments each cycle if the event count is + /// greater than or equal to the CMASK. + /// + UINT32 CMASK:8; + UINT32 Reserved:32; + /// + /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, + /// AnyThread (bit 21) should be cleared to prevent incorrect results. + /// + UINT32 IN_TX:1; + /// + /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and + /// in sampling, spurious PMI may occur and transactions may continuously + /// abort near overflow conditions. Software should favor using IN_TXCP + /// for counting over sampling. If sampling, software should use large + /// "sample-after" value after clearing the counter configured to use + /// IN_TXCP and also always reset the counter even when no overflow + /// condition was reported. + /// + UINT32 IN_TXCP:1; + UINT32 Reserved2:30; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER; + + +/** + Thread. Last Branch Record Filtering Select Register (R/W). + + @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_LBR_SELECT_REGISTER. + + Example usage + @code + MSR_HASWELL_LBR_SELECT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT); + AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64); + @endcode + @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_HASWELL_LBR_SELECT 0x000001C8 + +/** + MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + /// + /// [Bit 9] EN_CALL_STACK. + /// + UINT32 EN_CALL_STACK:1; + UINT32 Reserved1:22; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_LBR_SELECT_REGISTER; + + +/** + Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines + the interrupt response time limit used by the processor to manage transition + to package C6 or C7 state. The latency programmed in this register is for + the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state. + Note: C-state values are processor specific C-state code names, unrelated to + MWAIT extension C-state parameters or ACPI C-States. + + @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER. + + Example usage + @code + MSR_HASWELL_PKGC_IRTL1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1); + AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM. +**/ +#define MSR_HASWELL_PKGC_IRTL1 0x0000060B + +/** + MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C6 or C7 state. + /// + UINT32 InterruptResponseTimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit + /// of the interrupt response time limit. See Table 2-19 for supported + /// time unit encodings. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKGC_IRTL1_REGISTER; + + +/** + Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines + the interrupt response time limit used by the processor to manage transition + to package C6 or C7 state. The latency programmed in this register is for + the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state. + Note: C-state values are processor specific C-state code names, unrelated to + MWAIT extension C-state parameters or ACPI C-States. + + @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER. + + Example usage + @code + MSR_HASWELL_PKGC_IRTL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2); + AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM. +**/ +#define MSR_HASWELL_PKGC_IRTL2 0x0000060C + +/** + MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C6 or C7 state. + /// + UINT32 InterruptResponseTimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit + /// of the interrupt response time limit. See Table 2-19 for supported + /// time unit encodings. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKGC_IRTL2_REGISTER; + + +/** + Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS); + @endcode + @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. +**/ +#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613 + + +/** + Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS); + @endcode + @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619 + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS); + @endcode + @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. Base TDP Ratio (R/O). + + @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER. + + Example usage + @code + MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL); + @endcode + @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. +**/ +#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648 + +/** + MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this + /// specific processor (in units of 100 MHz). + /// + UINT32 Config_TDP_Base:8; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER; + + +/** + Package. ConfigTDP Level 1 ratio and power level (R/O). + + @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER. + + Example usage + @code + MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1); + @endcode + @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. +**/ +#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649 + +/** + MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. + /// + UINT32 PKG_TDP_LVL1:15; + UINT32 Reserved1:1; + /// + /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used + /// for this specific processor. + /// + UINT32 Config_TDP_LVL1_Ratio:8; + UINT32 Reserved2:8; + /// + /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP + /// Level 1. + /// + UINT32 PKG_MAX_PWR_LVL1:15; + /// + /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP + /// Level 1. + /// + UINT32 PKG_MIN_PWR_LVL1:16; + UINT32 Reserved3:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER; + + +/** + Package. ConfigTDP Level 2 ratio and power level (R/O). + + @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER. + + Example usage + @code + MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2); + @endcode + @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. +**/ +#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A + +/** + MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. + /// + UINT32 PKG_TDP_LVL2:15; + UINT32 Reserved1:1; + /// + /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used + /// for this specific processor. + /// + UINT32 Config_TDP_LVL2_Ratio:8; + UINT32 Reserved2:8; + /// + /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP + /// Level 2. + /// + UINT32 PKG_MAX_PWR_LVL2:15; + /// + /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP + /// Level 2. + /// + UINT32 PKG_MIN_PWR_LVL2:16; + UINT32 Reserved3:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER; + + +/** + Package. ConfigTDP Control (R/W). + + @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER. + + Example usage + @code + MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL); + AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64); + @endcode + @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. +**/ +#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B + +/** + MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. + /// + UINT32 TDP_LEVEL:2; + UINT32 Reserved1:29; + /// + /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of + /// this register is locked until a reset. + /// + UINT32 Config_TDP_Lock:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER; + + +/** + Package. ConfigTDP Control (R/W). + + @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER. + + Example usage + @code + MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO); + AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64); + @endcode + @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. +**/ +#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C + +/** + MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this + /// field. + /// + UINT32 MAX_NON_TURBO_RATIO:8; + UINT32 Reserved1:23; + /// + /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the + /// content of this register is locked until a reset. + /// + UINT32 TURBO_ACTIVATION_RATIO_Lock:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI Cstates. `See http://biosbits.org. `__. + + @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 0000b: + /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 + /// 0100b: C7 0101b: C7s Package C states C7 are not available to + /// processor with signature 06_3CH. + /// + UINT32 Limit:4; + UINT32 Reserved1:6; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + UINT32 Reserved4:3; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64); + @endcode + @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. +**/ +#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:26; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and the + /// MSR_SMM_FEATURE_CONTROL is supported. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is + /// supported. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_SMM_MCA_CAP_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT); + @endcode + @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Uncore PMU global control. + + @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391 + +/** + MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core 0 select. + /// + UINT32 PMI_Sel_Core0:1; + /// + /// [Bit 1] Core 1 select. + /// + UINT32 PMI_Sel_Core1:1; + /// + /// [Bit 2] Core 2 select. + /// + UINT32 PMI_Sel_Core2:1; + /// + /// [Bit 3] Core 3 select. + /// + UINT32 PMI_Sel_Core3:1; + UINT32 Reserved1:15; + UINT32 Reserved2:10; + /// + /// [Bit 29] Enable all uncore counters. + /// + UINT32 EN:1; + /// + /// [Bit 30] Enable wake on PMI. + /// + UINT32 WakePMI:1; + /// + /// [Bit 31] Enable Freezing counter when overflow. + /// + UINT32 FREEZE:1; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER; + + +/** + Package. Uncore PMU main status. + + @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392 + +/** + MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fixed counter overflowed. + /// + UINT32 Fixed:1; + /// + /// [Bit 1] An ARB counter overflowed. + /// + UINT32 ARB:1; + UINT32 Reserved1:1; + /// + /// [Bit 3] A CBox counter overflowed (on any slice). + /// + UINT32 CBox:1; + UINT32 Reserved2:28; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Package. Uncore fixed counter control (R/W). + + @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER. + + Example usage + @code + MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL); + AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64); + @endcode + @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. +**/ +#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394 + +/** + MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:20; + /// + /// [Bit 20] Enable overflow propagation. + /// + UINT32 EnableOverflow:1; + UINT32 Reserved2:1; + /// + /// [Bit 22] Enable counting. + /// + UINT32 EnableCounting:1; + UINT32 Reserved3:9; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER; + + +/** + Package. Uncore fixed counter. + + @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER. + + Example usage + @code + MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR); + AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64); + @endcode + @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. +**/ +#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395 + +/** + MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Current count. + /// + UINT32 CurrentCount:32; + /// + /// [Bits 47:32] Current count. + /// + UINT32 CurrentCountHi:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER; + + +/** + Package. Uncore C-Box configuration information (R/O). + + @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER. + + Example usage + @code + MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG); + @endcode + @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396 + +/** + MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Encoded number of C-Box, derive value by "-1". + /// + UINT32 CBox:4; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER; + + +/** + Package. Uncore Arb unit, performance counter 0. + + @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0); + AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr); + @endcode + @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. +**/ +#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0 + + +/** + Package. Uncore Arb unit, performance counter 1. + + @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1); + AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr); + @endcode + @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. +**/ +#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1 + + +/** + Package. Uncore Arb unit, counter 0 event select MSR. + + @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr); + @endcode + @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. +**/ +#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2 + + +/** + Package. Uncore Arb unit, counter 1 event select MSR. + + @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1); + AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr); + @endcode + @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. +**/ +#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3 + + +/** + Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM. +**/ +#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0 + +/** + MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from + /// further changes. + /// + UINT32 Lock:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if + /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the + /// logical processors are prevented from executing SMM code outside the + /// ranges defined by the SMRR. When set to '1' any logical processor in + /// the package that attempts to execute SMM code not within the ranges + /// defined by the SMRR will assert an unrecoverable MCE. + /// + UINT32 SMM_Code_Chk_En:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER; + + +/** + Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical + processors in the package. Available only while in SMM and + MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1. + + [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical + processor of its state in a long flow of internal operation which + delays servicing an interrupt. The corresponding bit will be set at + the start of long events such as: Microcode Update Load, C6, WBINVD, + Ratio Change, Throttle. The bit is automatically cleared at the end of + each long event. The reset value of this field is 0. Only bit + positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be + updated. + + [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical + processor of its state in a long flow of internal operation which + delays servicing an interrupt. The corresponding bit will be set at + the start of long events such as: Microcode Update Load, C6, WBINVD, + Ratio Change, Throttle. The bit is automatically cleared at the end of + each long event. The reset value of this field is 0. Only bit + positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be + updated. + + @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED); + @endcode + @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM. +**/ +#define MSR_HASWELL_SMM_DELAYED 0x000004E2 + + +/** + Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical + processors in the package. Available only while in SMM. + + [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical + processor of its blocked state to service an SMI. The corresponding + bit will be set if the logical processor is in one of the following + states: Wait For SIPI or SENTER Sleep. The reset value of this field + is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, + ECX=PKG_LVL):EBX[15:0] can be updated. + + + [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical + processor of its blocked state to service an SMI. The corresponding + bit will be set if the logical processor is in one of the following + states: Wait For SIPI or SENTER Sleep. The reset value of this field + is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH, + ECX=PKG_LVL):EBX[15:0] can be updated. + + @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED); + @endcode + @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM. +**/ +#define MSR_HASWELL_SMM_BLOCKED 0x000004E3 + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O). + + @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT); + @endcode + @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Package. Energy Status Units Energy related information + /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 + /// micro-joules). + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL + /// Interfaces.". + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS); + @endcode + @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 + RAPL Domains.". + + @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT); + AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr); + @endcode + @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. +**/ +#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640 + + +/** + Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS); + @endcode + @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. +**/ +#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641 + + +/** + Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_HASWELL_PP1_POLICY (0x00000642) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY); + AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr); + @endcode + @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. +**/ +#define MSR_HASWELL_PP1_POLICY 0x00000642 + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690 + +/** + MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is + /// reduced below the operating system request due to assertion of + /// external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:2; + /// + /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced + /// below the operating system request due to Processor Graphics driver + /// override. + /// + UINT32 GraphicsDriverStatus:1; + /// + /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) + /// When set, frequency is reduced below the operating system request + /// because the processor has detected that utilization is low. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + /// + /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced + /// below the operating system request due to domain-level power limiting. + /// + UINT32 PLStatus:1; + /// + /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL1. + /// + UINT32 PL1Status:1; + /// + /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL2. + /// + UINT32 PL2Status:1; + /// + /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced + /// below the operating system request due to multi-core turbo limits. + /// + UINT32 MaxTurboLimitStatus:1; + /// + /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency + /// is reduced below the operating system request due to Turbo transition + /// attenuation. This prevents performance degradation due to frequent + /// operating ratio changes. + /// + UINT32 TurboTransitionAttenuationStatus:1; + UINT32 Reserved3:2; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved4:2; + /// + /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics + /// Driver Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 GraphicsDriverLog:1; + /// + /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, + /// indicates that the Autonomous Utilization-Based Frequency Control + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + /// + /// [Bit 25] Core Power Limiting Log When set, indicates that the Core + /// Power Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 PLLog:1; + /// + /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates + /// that the Package Level PL1 Power Limiting Status bit has asserted + /// since the log bit was last cleared. This log bit will remain set until + /// cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that + /// the Package Level PL2 Power Limiting Status bit has asserted since the + /// log bit was last cleared. This log bit will remain set until cleared + /// by software writing 0. + /// + UINT32 PL2Log:1; + /// + /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo + /// Limit Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MaxTurboLimitLog:1; + /// + /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the + /// Turbo Transition Attenuation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 TurboTransitionAttenuationLog:1; + UINT32 Reserved6:2; + UINT32 Reserved7:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER; + + +/** + Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) + (frequency refers to processor graphics frequency). + + @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 + +/** + MSR information returned for MSR index + #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the + /// operating system request due to assertion of external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:2; + /// + /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced + /// below the operating system request due to Processor Graphics driver + /// override. + /// + UINT32 GraphicsDriverStatus:1; + /// + /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) + /// When set, frequency is reduced below the operating system request + /// because the processor has detected that utilization is low. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + /// + /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is + /// reduced below the operating system request due to domain-level power + /// limiting. + /// + UINT32 GraphicsPowerLimitingStatus:1; + /// + /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL1. + /// + UINT32 PL1STatus:1; + /// + /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL2. + /// + UINT32 PL2Status:1; + UINT32 Reserved3:4; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved4:2; + /// + /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics + /// Driver Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 GraphicsDriverLog:1; + /// + /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, + /// indicates that the Autonomous Utilization-Based Frequency Control + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + /// + /// [Bit 25] Core Power Limiting Log When set, indicates that the Core + /// Power Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CorePowerLimitingLog:1; + /// + /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates + /// that the Package Level PL1 Power Limiting Status bit has asserted + /// since the log bit was last cleared. This log bit will remain set until + /// cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that + /// the Package Level PL2 Power Limiting Status bit has asserted since the + /// log bit was last cleared. This log bit will remain set until cleared + /// by software writing 0. + /// + UINT32 PL2Log:1; + /// + /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo + /// Limit Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MaxTurboLimitLog:1; + /// + /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the + /// Turbo Transition Attenuation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 TurboTransitionAttenuationLog:1; + UINT32 Reserved6:2; + UINT32 Reserved7:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; + + +/** + Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) + (frequency refers to ring interconnect in the uncore). + + @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1 + +/** + MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the + /// operating system request due to assertion of external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:4; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + UINT32 Reserved3:1; + /// + /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL1. + /// + UINT32 PL1STatus:1; + /// + /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, + /// frequency is reduced below the operating system request due to + /// package-level power limiting PL2. + /// + UINT32 PL2Status:1; + UINT32 Reserved4:4; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved5:2; + /// + /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics + /// Driver Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 GraphicsDriverLog:1; + /// + /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, + /// indicates that the Autonomous Utilization-Based Frequency Control + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + UINT32 Reserved6:1; + /// + /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + /// + /// [Bit 25] Core Power Limiting Log When set, indicates that the Core + /// Power Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CorePowerLimitingLog:1; + /// + /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates + /// that the Package Level PL1 Power Limiting Status bit has asserted + /// since the log bit was last cleared. This log bit will remain set until + /// cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that + /// the Package Level PL2 Power Limiting Status bit has asserted since the + /// log bit was last cleared. This log bit will remain set until cleared + /// by software writing 0. + /// + UINT32 PL2Log:1; + /// + /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo + /// Limit Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MaxTurboLimitLog:1; + /// + /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the + /// Turbo Transition Attenuation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 TurboTransitionAttenuationLog:1; + UINT32 Reserved7:2; + UINT32 Reserved8:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER; + + +/** + Package. Uncore C-Box 0, counter 0 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700 + + +/** + Package. Uncore C-Box 0, counter 1 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701 + + +/** + Package. Uncore C-Box 0, performance counter 0. + + @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706 + + +/** + Package. Uncore C-Box 0, performance counter 1. + + @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707 + + +/** + Package. Uncore C-Box 1, counter 0 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710 + + +/** + Package. Uncore C-Box 1, counter 1 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711 + + +/** + Package. Uncore C-Box 1, performance counter 0. + + @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716 + + +/** + Package. Uncore C-Box 1, performance counter 1. + + @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717 + + +/** + Package. Uncore C-Box 2, counter 0 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720 + + +/** + Package. Uncore C-Box 2, counter 1 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721 + + +/** + Package. Uncore C-Box 2, performance counter 0. + + @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726 + + +/** + Package. Uncore C-Box 2, performance counter 1. + + @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727 + + +/** + Package. Uncore C-Box 3, counter 0 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730 + + +/** + Package. Uncore C-Box 3, counter 1 event select MSR. + + @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731 + + +/** + Package. Uncore C-Box 3, performance counter 0. + + @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736 + + +/** + Package. Uncore C-Box 3, performance counter 1. + + @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1); + AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr); + @endcode + @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. +**/ +#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. + + @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER. + + Example usage + @code + MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY); + AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM. +**/ +#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630 + +/** + MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset + /// that this package is in processor-specific C8 states. Count at the + /// same frequency as the TSC. + /// + UINT32 C8ResidencyCounter:32; + /// + /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last + /// reset that this package is in processor-specific C8 states. Count at + /// the same frequency as the TSC. + /// + UINT32 C8ResidencyCounterHi:28; + UINT32 Reserved:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. + + @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER. + + Example usage + @code + MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY); + AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM. +**/ +#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631 + +/** + MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset + /// that this package is in processor-specific C9 states. Count at the + /// same frequency as the TSC. + /// + UINT32 C9ResidencyCounter:32; + /// + /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last + /// reset that this package is in processor-specific C9 states. Count at + /// the same frequency as the TSC. + /// + UINT32 C9ResidencyCounterHi:28; + UINT32 Reserved:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. + + @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER. + + Example usage + @code + MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY); + AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64); + @endcode + @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM. +**/ +#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632 + +/** + MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last + /// reset that this package is in processor-specific C10 states. Count at + /// the same frequency as the TSC. + /// + UINT32 C10ResidencyCounter:32; + /// + /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last + /// reset that this package is in processor-specific C10 states. Count at + /// the same frequency as the TSC. + /// + UINT32 C10ResidencyCounterHi:28; + UINT32 Reserved:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h new file mode 100644 index 0000000000..57fde2c677 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h @@ -0,0 +1,2887 @@ +/** @file + MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __IVY_BRIDGE_MSR_H__ +#define __IVY_BRIDGE_MSR_H__ + +#include + +/** + Is Intel processors based on the Ivy Bridge microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x3A || \ + DisplayModel == 0x3E \ + ) \ + ) + +/** + Package. See http://biosbits.org. + + @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + UINT32 Reserved3:2; + /// + /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, + /// indicates that LPM is supported, and when set to 0, indicates LPM is + /// not supported. + /// + UINT32 LowPowerModeSupport:1; + /// + /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base + /// TDP level available. 01: One additional TDP level available. 02: Two + /// additional TDP level available. 11: Reserved. + /// + UINT32 ConfigTDPLevels:2; + UINT32 Reserved4:5; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + /// + /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the + /// minimum supported operating ratio in units of 100 MHz. + /// + UINT32 MinimumOperatingRatio:8; + UINT32 Reserved5:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI C-States. See http://biosbits.org. + + @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power). for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: + /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: + /// This field cannot be used to limit package C-state to C3. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map + /// IO_read instructions sent to IO register specified by + /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register + /// until next reset. + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C6/C7 requests to C3 based on uncore + /// auto-demote information. + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C3/C6/C7 requests to C1 based on uncore + /// auto-demote information. + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from + /// demoted C3. + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from + /// demoted C1. + /// + UINT32 C1Undemotion:1; + UINT32 Reserved4:3; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS); + @endcode + @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. Base TDP Ratio (R/O). + + @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL); + @endcode + @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. +**/ +#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648 + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this + /// specific processor (in units of 100 MHz). + /// + UINT32 Config_TDP_Base:8; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER; + + +/** + Package. ConfigTDP Level 1 ratio and power level (R/O). + + @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1); + @endcode + @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649 + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1. + /// + UINT32 PKG_TDP_LVL1:15; + UINT32 Reserved1:1; + /// + /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used + /// for this specific processor. + /// + UINT32 Config_TDP_LVL1_Ratio:8; + UINT32 Reserved2:8; + /// + /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP + /// Level 1. + /// + UINT32 PKG_MAX_PWR_LVL1:15; + UINT32 Reserved3:1; + /// + /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP + /// Level 1. + /// + UINT32 PKG_MIN_PWR_LVL1:15; + UINT32 Reserved4:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER; + + +/** + Package. ConfigTDP Level 2 ratio and power level (R/O). + + @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2); + @endcode + @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2. + /// + UINT32 PKG_TDP_LVL2:15; + UINT32 Reserved1:1; + /// + /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used + /// for this specific processor. + /// + UINT32 Config_TDP_LVL2_Ratio:8; + UINT32 Reserved2:8; + /// + /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP + /// Level 2. + /// + UINT32 PKG_MAX_PWR_LVL2:15; + UINT32 Reserved3:1; + /// + /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP + /// Level 2. + /// + UINT32 PKG_MIN_PWR_LVL2:15; + UINT32 Reserved4:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER; + + +/** + Package. ConfigTDP Control (R/W). + + @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. +**/ +#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field. + /// + UINT32 TDP_LEVEL:2; + UINT32 Reserved1:29; + /// + /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of + /// this register is locked until a reset. + /// + UINT32 Config_TDP_Lock:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER; + + +/** + Package. ConfigTDP Control (R/W). + + @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO); + AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. +**/ +#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this + /// field. + /// + UINT32 MAX_NON_TURBO_RATIO:8; + UINT32 Reserved1:23; + /// + /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the + /// content of this register is locked until a reset. + /// + UINT32 TURBO_ACTIVATION_RATIO_Lock:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER; + + +/** + Package. Protected Processor Inventory Number Enable Control (R/W). + + @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL. + /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit + /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to + /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged + /// inventory initialization agent to access MSR_PPIN. After reading + /// MSR_PPIN, the privileged inventory initialization agent should write + /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and + /// prevent unauthorized modification to MSR_PPIN_CTL. + /// + UINT32 LockOut:1; + /// + /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible + /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will + /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default + /// is 0. + /// + UINT32 Enable_PPIN:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER; + + +/** + Package. Protected Processor Inventory Number (R/O). Protected Processor + Inventory Number (R/O) A unique value within a given CPUID + family/model/stepping signature that a privileged inventory initialization + agent can access to identify each physical processor, when access to + MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if + MSR_PPIN_CTL[bits 1:0] = '10b'. + + @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN); + @endcode + @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM. +**/ +#define MSR_IVY_BRIDGE_PPIN 0x0000004F + + +/** + Package. See http://biosbits.org. + + @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM. +**/ +#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:7; + /// + /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that + /// Protected Processor Inventory Number (PPIN) capability can be enabled + /// for privileged system inventory agent to read PPIN from MSR_PPIN. When + /// set to 0, PPIN capability is not supported. An attempt to access + /// MSR_PPIN_CTL or MSR_PPIN will cause #GP. + /// + UINT32 PPIN_CAP:1; + UINT32 Reserved3:4; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + /// + /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, + /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to + /// specify an temperature offset. + /// + UINT32 TJOFFSET:1; + UINT32 Reserved4:1; + UINT32 Reserved5:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved6:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER; + + +/** + Package. MC Bank Error Configuration (R/W). + + @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. +**/ +#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank + /// to log additional info in bits 36:32. + /// + UINT32 MemErrorLogEnable:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER; + + +/** + Package. + + @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which + /// PROCHOT# will be asserted. The value is degree C. + /// + UINT32 TemperatureTarget:8; + /// + /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature + /// offset in degrees C from the temperature target (bits 23:16). PROCHOT# + /// will assert at the offset target temperature. Write is permitted only + /// MSR_PLATFORM_INFO.[30] is set. + /// + UINT32 TCCActivationOffset:4; + UINT32 Reserved2:4; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1); + @endcode + @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. +**/ +#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio + /// limit of 9 core active. + /// + UINT32 Maximum9C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio + /// limit of 10core active. + /// + UINT32 Maximum10C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio + /// limit of 11 core active. + /// + UINT32 Maximum11C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio + /// limit of 12 core active. + /// + UINT32 Maximum12C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio + /// limit of 13 core active. + /// + UINT32 Maximum13C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio + /// limit of 14 core active. + /// + UINT32 Maximum14C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio + /// limit of 15 core active. + /// + UINT32 Maximum15C:8; + UINT32 Reserved:7; + /// + /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, + /// the processor uses override configuration specified in + /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor + /// uses factory-set configuration (Default). + /// + UINT32 TurboRatioLimitConfigurationSemaphore:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER; + + +/** + Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4. + + @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC); + @endcode + @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM. +**/ +#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 5:0] Recoverable Address LSB. + /// + UINT32 RecoverableAddressLSB:6; + /// + /// [Bits 8:6] Address Mode. + /// + UINT32 AddressMode:3; + UINT32 Reserved1:7; + /// + /// [Bits 31:16] PCI Express Requestor ID. + /// + UINT32 PCIExpressRequestorID:16; + /// + /// [Bits 39:32] PCI Express Segment Number. + /// + UINT32 PCIExpressSegmentNumber:8; + UINT32 Reserved2:24; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER; + + +/** + Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section + 15.3.2.4, "IA32_MCi_MISC MSRs.". + + Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) + and its corresponding slice of L3. + + @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM. + MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM. + MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM. + @{ +**/ +#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474 +#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478 +#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C +/// @} + + +/** + Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section + 15.3.2.4, "IA32_MCi_MISC MSRs.". + + Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) + and its corresponding slice of L3. + + @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS); + AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr); + @endcode + @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM. + MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM. + MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM. + @{ +**/ +#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475 +#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479 +#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D +/// @} + + +/** + Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section + 15.3.2.4, "IA32_MCi_MISC MSRs.". + + Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) + and its corresponding slice of L3. + + @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR); + AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr); + @endcode + @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM. + MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM. + MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM. + @{ +**/ +#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476 +#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A +#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E +/// @} + + +/** + Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section + 15.3.2.4, "IA32_MCi_MISC MSRs.". + + Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast) + and its corresponding slice of L3. + + @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC); + AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr); + @endcode + @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM. + MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM. + MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM. + @{ +**/ +#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477 +#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B +#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F +/// @} + + +/** + Package. Package RAPL Perf Status (R/O). + + @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS); + @endcode + @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613 + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS); + @endcode + @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS); + @endcode + @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C + + +/** + Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).". + + @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). + /// + UINT32 PEBS_EN_PMC0:1; + /// + /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). + /// + UINT32 PEBS_EN_PMC1:1; + /// + /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). + /// + UINT32 PEBS_EN_PMC2:1; + /// + /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). + /// + UINT32 PEBS_EN_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). + /// + UINT32 LL_EN_PMC0:1; + /// + /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). + /// + UINT32 LL_EN_PMC1:1; + /// + /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). + /// + UINT32 LL_EN_PMC2:1; + /// + /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). + /// + UINT32 LL_EN_PMC3:1; + UINT32 Reserved2:28; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER; + + +/** + Package. Uncore perfmon per-socket global control. + + @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00 + + +/** + Package. Uncore perfmon per-socket global status. + + @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr); + @endcode + @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01 + + +/** + Package. Uncore perfmon per-socket global configuration. + + @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr); + @endcode + @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM. +**/ +#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06 + + +/** + Package. Uncore U-box perfmon U-box wide status. + + @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15 + + +/** + Package. Uncore PCU perfmon box wide status. + + @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM. +**/ +#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35 + + +/** + Package. Uncore C-box 0 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A + + +/** + Package. Uncore C-box 1 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A + + +/** + Package. Uncore C-box 2 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A + + +/** + Package. Uncore C-box 3 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A + + +/** + Package. Uncore C-box 4 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A + + +/** + Package. Uncore C-box 5 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA + + +/** + Package. Uncore C-box 6 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA + + +/** + Package. Uncore C-box 7 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA + + +/** + Package. Uncore C-box 8 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12 + + +/** + Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13 + + +/** + Package. Uncore C-box 8 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14 + + +/** + Package. Uncore C-box 8 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16 + + +/** + Package. Uncore C-box 8 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17 + + +/** + Package. Uncore C-box 8 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18 + + +/** + Package. Uncore C-box 8 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19 + + +/** + Package. Uncore C-box 8 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A + + +/** + Package. Uncore C-box 9 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32 + + +/** + Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33 + + +/** + Package. Uncore C-box 9 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34 + + +/** + Package. Uncore C-box 9 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36 + + +/** + Package. Uncore C-box 9 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37 + + +/** + Package. Uncore C-box 9 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38 + + +/** + Package. Uncore C-box 9 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39 + + +/** + Package. Uncore C-box 9 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A + + +/** + Package. Uncore C-box 10 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52 + + +/** + Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53 + + +/** + Package. Uncore C-box 10 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54 + + +/** + Package. Uncore C-box 10 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56 + + +/** + Package. Uncore C-box 10 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57 + + +/** + Package. Uncore C-box 10 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58 + + +/** + Package. Uncore C-box 10 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59 + + +/** + Package. Uncore C-box 10 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A + + +/** + Package. Uncore C-box 11 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72 + + +/** + Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73 + + +/** + Package. Uncore C-box 11 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74 + + +/** + Package. Uncore C-box 11 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76 + + +/** + Package. Uncore C-box 11 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77 + + +/** + Package. Uncore C-box 11 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78 + + +/** + Package. Uncore C-box 11 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79 + + +/** + Package. Uncore C-box 11 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A + + +/** + Package. Uncore C-box 12 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92 + + +/** + Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93 + + +/** + Package. Uncore C-box 12 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94 + + +/** + Package. Uncore C-box 12 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96 + + +/** + Package. Uncore C-box 12 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97 + + +/** + Package. Uncore C-box 12 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98 + + +/** + Package. Uncore C-box 12 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99 + + +/** + Package. Uncore C-box 12 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A + + +/** + Package. Uncore C-box 13 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2 + + +/** + Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3 + + +/** + Package. Uncore C-box 13 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4 + + +/** + Package. Uncore C-box 13 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6 + + +/** + Package. Uncore C-box 13 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7 + + +/** + Package. Uncore C-box 13 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8 + + +/** + Package. Uncore C-box 13 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9 + + +/** + Package. Uncore C-box 13 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA + + +/** + Package. Uncore C-box 14 perfmon local box wide control. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2 + + +/** + Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3 + + +/** + Package. Uncore C-box 14 perfmon box wide filter. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4 + + +/** + Package. Uncore C-box 14 perfmon counter 0. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6 + + +/** + Package. Uncore C-box 14 perfmon counter 1. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7 + + +/** + Package. Uncore C-box 14 perfmon counter 2. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8 + + +/** + Package. Uncore C-box 14 perfmon counter 3. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9 + + +/** + Package. Uncore C-box 14 perfmon box wide filter1. + + @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1); + AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr); + @endcode + @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM. +**/ +#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h new file mode 100644 index 0000000000..74eef33449 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h @@ -0,0 +1,7424 @@ +/** @file + MSR Definitions for Intel processors based on the Nehalem microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __NEHALEM_MSR_H__ +#define __NEHALEM_MSR_H__ + +#include + +/** + Is Intel processors based on the Nehalem microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x1A || \ + DisplayModel == 0x1E || \ + DisplayModel == 0x1F || \ + DisplayModel == 0x2E \ + ) \ + ) + +/** + Package. Model Specific Platform ID (R). + + @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_NEHALEM_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID); + @endcode + @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. +**/ +#define MSR_NEHALEM_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:18; + /// + /// [Bits 52:50] See Table 2-2. + /// + UINT32 PlatformId:3; + UINT32 Reserved3:11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PLATFORM_ID_REGISTER; + + +/** + Thread. SMI Counter (R/O). + + @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER. + + Example usage + @code + MSR_NEHALEM_SMI_COUNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT); + @endcode + @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. +**/ +#define MSR_NEHALEM_SMI_COUNT 0x00000034 + +/** + MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last + /// RESET. + /// + UINT32 SMICount:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_SMI_COUNT_REGISTER; + + +/** + Package. see http://biosbits.org. + + @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO); + AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. The invariant TSC + /// frequency can be computed by multiplying this ratio by 133.33 MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O) + /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are + /// programmable, and when set to 0, indicates TDC and TDP Limits for + /// Turbo mode are not programmable. + /// + UINT32 TDC_TDPLimit:1; + UINT32 Reserved3:2; + UINT32 Reserved4:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 133.33MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved5:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. See http://biosbits.org. + + @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power). for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) + /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package + /// C-state limit. Note: This field cannot be used to limit package + /// C-state to C3. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map + /// IO_read instructions sent to IO register specified by + /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register + /// until next reset. + /// + UINT32 CFGLock:1; + UINT32 Reserved3:8; + /// + /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores + /// in a deep C-State will wake only when the event message is destined + /// for that core. When 0, all processor cores in a deep C-State will wake + /// for an event message. + /// + UINT32 InterruptFiltering:1; + /// + /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C6/C7 requests to C3 based on uncore + /// auto-demote information. + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C3/C6/C7 requests to C1 based on uncore + /// auto-demote information. + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + /// + /// [Bit 29] Package C State Demotion Enable (R/W). + /// + UINT32 CStateDemotion:1; + /// + /// [Bit 30] Package C State UnDemotion Enable (R/W). + /// + UINT32 CStateUndemotion:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Core. Power Management IO Redirection in C-state (R/W) See + http://biosbits.org. + + @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER. + + Example usage + @code + MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE); + AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. +**/ +#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address + /// visible to software for IO redirection. If IO MWAIT Redirection is + /// enabled, reads to this address will be consumed by the power + /// management logic and decoded to MWAIT instructions. When IO port + /// address redirection is enabled, this is the IO port address reported + /// to the OS/software. + /// + UINT32 Lvl2Base:16; + /// + /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the + /// maximum C-State code name to be included when IO read to MWAIT + /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 + /// is the max C-State to include 001b - C6 is the max C-State to include + /// 010b - C7 is the max C-State to include. + /// + UINT32 CStateRange:3; + UINT32 Reserved1:13; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. Default value is 1. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:3; + /// + /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + UINT32 Reserved4:3; + /// + /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved6:3; + /// + /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved9:3; + /// + /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors + /// that support Intel Turbo Boost Technology, the turbo mode feature is + /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: + /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: + /// EAX[1] reports the processor's support of turbo mode is enabled. Note: + /// the power-on default value is used by BIOS to detect hardware support + /// of turbo mode. If power-on default value is 1, turbo mode is available + /// in the processor. If power-on default value is 0, turbo mode is not + /// available. + /// + UINT32 TurboModeDisable:1; + UINT32 Reserved10:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER; + + +/** + Thread. + + @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (R) The minimum temperature at which + /// PROCHOT# will be asserted. The value is degree C. + /// + UINT32 TemperatureTarget:8; + UINT32 Reserved2:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER; + + +/** + Miscellaneous Feature Control (R/W). + + @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. +**/ +#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4 + +/** + MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the + /// L2 hardware prefetcher, which fetches additional lines of code or data + /// into the L2 cache. + /// + UINT32 L2HardwarePrefetcherDisable:1; + /// + /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, + /// disables the adjacent cache line prefetcher, which fetches the cache + /// line that comprises a cache line pair (128 bytes). + /// + UINT32 L2AdjacentCacheLinePrefetcherDisable:1; + /// + /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables + /// the L1 data cache prefetcher, which fetches the next cache line into + /// L1 data cache. + /// + UINT32 DCUHardwarePrefetcherDisable:1; + /// + /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 + /// data cache IP prefetcher, which uses sequential load history (based on + /// instruction Pointer of previous loads) to determine whether to + /// prefetch additional lines. + /// + UINT32 DCUIPPrefetcherDisable:1; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER; + + +/** + Thread. Offcore Response Event Select Register (R/W). + + @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0); + AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr); + @endcode + @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. +**/ +#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6 + + +/** + See http://biosbits.org. + + @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER. + + Example usage + @code + MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT); + AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64); + @endcode + @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. +**/ +#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA + +/** + MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0, + /// enables hardware coordination of Enhanced Intel Speedstep Technology + /// request from processor cores; When 1, disables hardware coordination + /// of Enhanced Intel Speedstep Technology requests. + /// + UINT32 EISTHardwareCoordinationDisable:1; + /// + /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes + /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with + /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by + /// CPUID.(EAX=06h):ECX[3]. + /// + UINT32 EnergyPerformanceBiasEnable:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER; + + +/** + See http://biosbits.org. + + @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER. + + Example usage + @code + MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT); + AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64); + @endcode + @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM. +**/ +#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC + +/** + MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt + /// granularity. + /// + UINT32 TDPLimit:15; + /// + /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0 + /// indicates override is not active, and a value = 1 indicates active. + /// + UINT32 TDPLimitOverrideEnable:1; + /// + /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp + /// granularity. + /// + UINT32 TDCLimit:15; + /// + /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0 + /// indicates override is not active, and a value = 1 indicates active. + /// + UINT32 TDCLimitOverrideEnable:1; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT); + @endcode + @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, + "Filtering of Last Branch Records.". + + @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER. + + Example usage + @code + MSR_NEHALEM_LBR_SELECT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT); + AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64); + @endcode + @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_NEHALEM_LBR_SELECT 0x000001C8 + +/** + MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + UINT32 Reserved1:23; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_LBR_SELECT_REGISTER; + + +/** + Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) + that points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP (at 680H). + + @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9 + + +/** + Thread. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP); + @endcode + @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD + + +/** + Thread. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP); + @endcode + @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_NEHALEM_LER_TO_LIP 0x000001DE + + +/** + Core. Power Control Register. See http://biosbits.org. + + @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_POWER_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_POWER_CTL_REGISTER. + + Example usage + @code + MSR_NEHALEM_POWER_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL); + AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64); + @endcode + @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM. +**/ +#define MSR_NEHALEM_POWER_CTL 0x000001FC + +/** + MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the + /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology + /// operating point when all execution cores enter MWAIT (C1). + /// + UINT32 C1EEnable:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_POWER_CTL_REGISTER; + + +/** + Thread. (RO). + + @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS); + @endcode + @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:29; + /// + /// [Bit 61] UNC_Ovf Uncore overflowed if 1. + /// + UINT32 Ovf_Uncore:1; + UINT32 Reserved3:2; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Thread. (R/W). + + @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER. + + Example usage + @code + MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:29; + /// + /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf. + /// + UINT32 Ovf_Uncore:1; + UINT32 Reserved3:2; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER; + + +/** + Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).". + + @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE); + AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). + /// + UINT32 PEBS_EN_PMC0:1; + /// + /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). + /// + UINT32 PEBS_EN_PMC1:1; + /// + /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). + /// + UINT32 PEBS_EN_PMC2:1; + /// + /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). + /// + UINT32 PEBS_EN_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). + /// + UINT32 LL_EN_PMC0:1; + /// + /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). + /// + UINT32 LL_EN_PMC1:1; + /// + /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). + /// + UINT32 LL_EN_PMC2:1; + /// + /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). + /// + UINT32 LL_EN_PMC3:1; + UINT32 Reserved2:28; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PEBS_ENABLE_REGISTER; + + +/** + Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring + Facility.". + + @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER. + + Example usage + @code + MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT); + AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64); + @endcode + @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM. +**/ +#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6 + +/** + MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Minimum threshold latency value of tagged load operation + /// that will be counted. (R/W). + /// + UINT32 MinimumThreshold:16; + UINT32 Reserved1:16; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_PEBS_LD_LAT_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY); + AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr); + @endcode + @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. +**/ +#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C6 states. Count at the same frequency as the TSC. + + @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C7 states. Count at the same frequency as the TSC. + + @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY); + AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr); + @endcode + @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. +**/ +#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY); + AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr); + @endcode + @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. +**/ +#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C6 states. Count at the same frequency as the TSC. + + @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY); + AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr); + @endcode + @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. +**/ +#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD + + +/** + Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last + branch record registers on the last branch record stack. The From_IP part of + the stack contains pointers to the source instruction. See also: - Last + Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in + Section 17.4.8.1. + + @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. + MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. + @{ +**/ +#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680 +#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681 +#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682 +#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683 +#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684 +#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685 +#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686 +#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687 +#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688 +#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689 +#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A +#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B +#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C +#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D +#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E +#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F +/// @} + + +/** + Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch + record registers on the last branch record stack. This part of the stack + contains pointers to the destination instruction. + + @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. + MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. + @{ +**/ +#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0 +#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1 +#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2 +#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3 +#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4 +#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5 +#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6 +#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7 +#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8 +#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9 +#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA +#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB +#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC +#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD +#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE +#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF +/// @} + + +/** + Package. + + @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER. + + Example usage + @code + MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF); + AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64); + @endcode + @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM. +**/ +#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301 + +/** + MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] From M to S (R/W). + /// + UINT32 FromMtoS:1; + /// + /// [Bit 1] From E to S (R/W). + /// + UINT32 FromEtoS:1; + /// + /// [Bit 2] From S to S (R/W). + /// + UINT32 FromStoS:1; + /// + /// [Bit 3] From F to S (R/W). + /// + UINT32 FromFtoS:1; + /// + /// [Bit 4] From M to I (R/W). + /// + UINT32 FromMtoI:1; + /// + /// [Bit 5] From E to I (R/W). + /// + UINT32 FromEtoI:1; + /// + /// [Bit 6] From S to I (R/W). + /// + UINT32 FromStoI:1; + /// + /// [Bit 7] From F to I (R/W). + /// + UINT32 FromFtoI:1; + UINT32 Reserved1:24; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER; + + +/** + Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391 + + +/** + Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392 + + +/** + Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393 + + +/** + Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM. +**/ +#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394 + + +/** + Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM. +**/ +#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395 + + +/** + Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.". + + @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM. +**/ +#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396 + + +/** + Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_PMCi + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM. + MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM. + MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM. + MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM. + MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM. + MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM. + MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM. + MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM. + @{ +**/ +#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0 +#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1 +#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2 +#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3 +#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4 +#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5 +#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6 +#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7 +/// @} + +/** + Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration + Facility.". + + @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0); + AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr); + @endcode + @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM. + MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM. + @{ +**/ +#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6 +#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7 +/// @} + + +/** + Package. Uncore W-box perfmon fixed counter. + + @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM. +**/ +#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394 + + +/** + Package. Uncore U-box perfmon fixed counter control MSR. + + @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM. +**/ +#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395 + + +/** + Package. Uncore U-box perfmon global control MSR. + + @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr); + @endcode + @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM. +**/ +#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00 + + +/** + Package. Uncore U-box perfmon global status MSR. + + @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr); + @endcode + @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM. +**/ +#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01 + + +/** + Package. Uncore U-box perfmon global overflow control MSR. + + @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02 + + +/** + Package. Uncore U-box perfmon event select MSR. + + @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL); + AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr); + @endcode + @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM. +**/ +#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10 + + +/** + Package. Uncore U-box perfmon counter MSR. + + @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR); + AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr); + @endcode + @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM. +**/ +#define MSR_NEHALEM_U_PMON_CTR 0x00000C11 + + +/** + Package. Uncore B-box 0 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20 + + +/** + Package. Uncore B-box 0 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21 + + +/** + Package. Uncore B-box 0 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22 + + +/** + Package. Uncore B-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30 + + +/** + Package. Uncore B-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31 + + +/** + Package. Uncore B-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32 + + +/** + Package. Uncore B-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33 + + +/** + Package. Uncore B-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34 + + +/** + Package. Uncore B-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35 + + +/** + Package. Uncore B-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36 + + +/** + Package. Uncore B-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37 + + +/** + Package. Uncore S-box 0 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40 + + +/** + Package. Uncore S-box 0 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41 + + +/** + Package. Uncore S-box 0 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42 + + +/** + Package. Uncore S-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50 + + +/** + Package. Uncore S-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51 + + +/** + Package. Uncore S-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52 + + +/** + Package. Uncore S-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53 + + +/** + Package. Uncore S-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54 + + +/** + Package. Uncore S-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55 + + +/** + Package. Uncore S-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56 + + +/** + Package. Uncore S-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57 + + +/** + Package. Uncore B-box 1 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60 + + +/** + Package. Uncore B-box 1 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61 + + +/** + Package. Uncore B-box 1 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62 + + +/** + Package. Uncore B-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70 + + +/** + Package. Uncore B-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71 + + +/** + Package. Uncore B-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72 + + +/** + Package. Uncore B-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73 + + +/** + Package. Uncore B-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74 + + +/** + Package. Uncore B-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75 + + +/** + Package. Uncore B-box 1vperfmon event select MSR. + + @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76 + + +/** + Package. Uncore B-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77 + + +/** + Package. Uncore W-box perfmon local box control MSR. + + @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80 + + +/** + Package. Uncore W-box perfmon local box status MSR. + + @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81 + + +/** + Package. Uncore W-box perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82 + + +/** + Package. Uncore W-box perfmon event select MSR. + + @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90 + + +/** + Package. Uncore W-box perfmon counter MSR. + + @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91 + + +/** + Package. Uncore W-box perfmon event select MSR. + + @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92 + + +/** + Package. Uncore W-box perfmon counter MSR. + + @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93 + + +/** + Package. Uncore W-box perfmon event select MSR. + + @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94 + + +/** + Package. Uncore W-box perfmon counter MSR. + + @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95 + + +/** + Package. Uncore W-box perfmon event select MSR. + + @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96 + + +/** + Package. Uncore W-box perfmon counter MSR. + + @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97 + + +/** + Package. Uncore M-box 0 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0 + + +/** + Package. Uncore M-box 0 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1 + + +/** + Package. Uncore M-box 0 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2 + + +/** + Package. Uncore M-box 0 perfmon time stamp unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4 + + +/** + Package. Uncore M-box 0 perfmon DSP unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5 + + +/** + Package. Uncore M-box 0 perfmon ISS unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6 + + +/** + Package. Uncore M-box 0 perfmon MAP unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7 + + +/** + Package. Uncore M-box 0 perfmon MIC THR select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8 + + +/** + Package. Uncore M-box 0 perfmon PGT unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9 + + +/** + Package. Uncore M-box 0 perfmon PLD unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA + + +/** + Package. Uncore M-box 0 perfmon ZDP unit select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0 + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1 + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2 + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3 + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4 + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5 + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6 + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7 + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8 + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9 + + +/** + Package. Uncore M-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA + + +/** + Package. Uncore M-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB + + +/** + Package. Uncore S-box 1 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0 + + +/** + Package. Uncore S-box 1 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1 + + +/** + Package. Uncore S-box 1 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2 + + +/** + Package. Uncore S-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0 + + +/** + Package. Uncore S-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1 + + +/** + Package. Uncore S-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2 + + +/** + Package. Uncore S-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3 + + +/** + Package. Uncore S-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4 + + +/** + Package. Uncore S-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5 + + +/** + Package. Uncore S-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6 + + +/** + Package. Uncore S-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7 + + +/** + Package. Uncore M-box 1 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0 + + +/** + Package. Uncore M-box 1 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1 + + +/** + Package. Uncore M-box 1 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2 + + +/** + Package. Uncore M-box 1 perfmon time stamp unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4 + + +/** + Package. Uncore M-box 1 perfmon DSP unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5 + + +/** + Package. Uncore M-box 1 perfmon ISS unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6 + + +/** + Package. Uncore M-box 1 perfmon MAP unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7 + + +/** + Package. Uncore M-box 1 perfmon MIC THR select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8 + + +/** + Package. Uncore M-box 1 perfmon PGT unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9 + + +/** + Package. Uncore M-box 1 perfmon PLD unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA + + +/** + Package. Uncore M-box 1 perfmon ZDP unit select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0 + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1 + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2 + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3 + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4 + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5 + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6 + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7 + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8 + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9 + + +/** + Package. Uncore M-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA + + +/** + Package. Uncore M-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB + + +/** + Package. Uncore C-box 0 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00 + + +/** + Package. Uncore C-box 0 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01 + + +/** + Package. Uncore C-box 0 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10 + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12 + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14 + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16 + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18 + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19 + + +/** + Package. Uncore C-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A + + +/** + Package. Uncore C-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B + + +/** + Package. Uncore C-box 4 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20 + + +/** + Package. Uncore C-box 4 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21 + + +/** + Package. Uncore C-box 4 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30 + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32 + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34 + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36 + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38 + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39 + + +/** + Package. Uncore C-box 4 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A + + +/** + Package. Uncore C-box 4 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B + + +/** + Package. Uncore C-box 2 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40 + + +/** + Package. Uncore C-box 2 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41 + + +/** + Package. Uncore C-box 2 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50 + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52 + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54 + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56 + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58 + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59 + + +/** + Package. Uncore C-box 2 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A + + +/** + Package. Uncore C-box 2 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B + + +/** + Package. Uncore C-box 6 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60 + + +/** + Package. Uncore C-box 6 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61 + + +/** + Package. Uncore C-box 6 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70 + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72 + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74 + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76 + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78 + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79 + + +/** + Package. Uncore C-box 6 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A + + +/** + Package. Uncore C-box 6 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B + + +/** + Package. Uncore C-box 1 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80 + + +/** + Package. Uncore C-box 1 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81 + + +/** + Package. Uncore C-box 1 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90 + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92 + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94 + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96 + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98 + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99 + + +/** + Package. Uncore C-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A + + +/** + Package. Uncore C-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B + + +/** + Package. Uncore C-box 5 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0 + + +/** + Package. Uncore C-box 5 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1 + + +/** + Package. Uncore C-box 5 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0 + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2 + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4 + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6 + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8 + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9 + + +/** + Package. Uncore C-box 5 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA + + +/** + Package. Uncore C-box 5 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB + + +/** + Package. Uncore C-box 3 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0 + + +/** + Package. Uncore C-box 3 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1 + + +/** + Package. Uncore C-box 3 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0 + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2 + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4 + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6 + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8 + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9 + + +/** + Package. Uncore C-box 3 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA + + +/** + Package. Uncore C-box 3 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB + + +/** + Package. Uncore C-box 7 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0 + + +/** + Package. Uncore C-box 7 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1 + + +/** + Package. Uncore C-box 7 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0 + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2 + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4 + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6 + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8 + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9 + + +/** + Package. Uncore C-box 7 perfmon event select MSR. + + @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA + + +/** + Package. Uncore C-box 7 perfmon counter MSR. + + @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB + + +/** + Package. Uncore R-box 0 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00 + + +/** + Package. Uncore R-box 0 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01 + + +/** + Package. Uncore R-box 0 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09 + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A + + +/** + Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B + + +/** + Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C + + +/** + Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D + + +/** + Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E + + +/** + Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10 + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11 + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12 + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13 + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14 + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15 + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16 + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17 + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18 + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19 + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D + + +/** + Package. Uncore R-box 0 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E + + +/** + Package. Uncore R-box 0 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7); + AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr); + @endcode + @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM. +**/ +#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F + + +/** + Package. Uncore R-box 1 perfmon local box control MSR. + + @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20 + + +/** + Package. Uncore R-box 1 perfmon local box status MSR. + + @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21 + + +/** + Package. Uncore R-box 1 perfmon local box overflow control MSR. + + @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29 + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A + + +/** + Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B + + +/** + Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C + + +/** + Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D + + +/** + Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E + + +/** + Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30 + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31 + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32 + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33 + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34 + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35 + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36 + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37 + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38 + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39 + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A + + +/** + Package. Uncore R-box 1perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D + + +/** + Package. Uncore R-box 1 perfmon event select MSR. + + @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E + + +/** + Package. Uncore R-box 1 perfmon counter MSR. + + @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15); + AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr); + @endcode + @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM. +**/ +#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F + + +/** + Package. Uncore B-box 0 perfmon local box match MSR. + + @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45 + + +/** + Package. Uncore B-box 0 perfmon local box mask MSR. + + @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK); + AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr); + @endcode + @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM. +**/ +#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46 + + +/** + Package. Uncore S-box 0 perfmon local box match MSR. + + @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49 + + +/** + Package. Uncore S-box 0 perfmon local box mask MSR. + + @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK); + AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr); + @endcode + @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM. +**/ +#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A + + +/** + Package. Uncore B-box 1 perfmon local box match MSR. + + @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D + + +/** + Package. Uncore B-box 1 perfmon local box mask MSR. + + @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK); + AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr); + @endcode + @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM. +**/ +#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E + + +/** + Package. Uncore M-box 0 perfmon local box address match/mask config MSR. + + @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54 + + +/** + Package. Uncore M-box 0 perfmon local box address match MSR. + + @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55 + + +/** + Package. Uncore M-box 0 perfmon local box address mask MSR. + + @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK); + AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr); + @endcode + @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM. +**/ +#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56 + + +/** + Package. Uncore S-box 1 perfmon local box match MSR. + + @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59 + + +/** + Package. Uncore S-box 1 perfmon local box mask MSR. + + @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK); + AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr); + @endcode + @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM. +**/ +#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A + + +/** + Package. Uncore M-box 1 perfmon local box address match/mask config MSR. + + @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C + + +/** + Package. Uncore M-box 1 perfmon local box address match MSR. + + @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D + + +/** + Package. Uncore M-box 1 perfmon local box address mask MSR. + + @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK); + AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr); + @endcode + @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM. +**/ +#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/P6Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/P6Msr.h new file mode 100644 index 0000000000..db5396f74c --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/P6Msr.h @@ -0,0 +1,1658 @@ +/** @file + MSR Definitions for P6 Family Processors. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __P6_MSR_H__ +#define __P6_MSR_H__ + +#include + +/** + Is P6 Family Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x03 || \ + DisplayModel == 0x05 || \ + DisplayModel == 0x07 || \ + DisplayModel == 0x08 || \ + DisplayModel == 0x0A || \ + DisplayModel == 0x0B \ + ) \ + ) + +/** + See Section 2.22, "MSRs in Pentium Processors.". + + @param ECX MSR_P6_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR); + AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr); + @endcode + @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. +**/ +#define MSR_P6_P5_MC_ADDR 0x00000000 + + +/** + See Section 2.22, "MSRs in Pentium Processors.". + + @param ECX MSR_P6_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE); + AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr); + @endcode + @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. +**/ +#define MSR_P6_P5_MC_TYPE 0x00000001 + + +/** + See Section 17.17, "Time-Stamp Counter.". + + @param ECX MSR_P6_TSC (0x00000010) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_TSC); + AsmWriteMsr64 (MSR_P6_TSC, Msr); + @endcode + @note MSR_P6_TSC is defined as TSC in SDM. +**/ +#define MSR_P6_TSC 0x00000010 + + +/** + Platform ID (R) The operating system can use this MSR to determine "slot" + information for the processor and the proper microcode update to load. + + @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_P6_IA32_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID); + @endcode + @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM. +**/ +#define MSR_P6_IA32_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:18; + /// + /// [Bits 52:50] Platform Id (R) Contains information concerning the + /// intended platform for the processor. + /// + /// 52 51 50 + /// 0 0 0 Processor Flag 0. + /// 0 0 1 Processor Flag 1 + /// 0 1 0 Processor Flag 2 + /// 0 1 1 Processor Flag 3 + /// 1 0 0 Processor Flag 4 + /// 1 0 1 Processor Flag 5 + /// 1 1 0 Processor Flag 6 + /// 1 1 1 Processor Flag 7 + /// + UINT32 PlatformId:3; + /// + /// [Bits 56:53] L2 Cache Latency Read. + /// + UINT32 L2CacheLatencyRead:4; + UINT32 Reserved3:3; + /// + /// [Bit 60] Clock Frequency Ratio Read. + /// + UINT32 ClockFrequencyRatioRead:1; + UINT32 Reserved4:3; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_IA32_PLATFORM_ID_REGISTER; + + +/** + Section 10.4.4, "Local APIC Status and Location.". + + @param ECX MSR_P6_APIC_BASE (0x0000001B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_APIC_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_APIC_BASE_REGISTER. + + Example usage + @code + MSR_P6_APIC_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE); + AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64); + @endcode + @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM. +**/ +#define MSR_P6_APIC_BASE 0x0000001B + +/** + MSR information returned for MSR index #MSR_P6_APIC_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP. + /// + UINT32 BSP:1; + UINT32 Reserved2:2; + /// + /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 = + /// Disabled. + /// + UINT32 EN:1; + /// + /// [Bits 31:12] APIC Base Address. + /// + UINT32 ApicBase:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_APIC_BASE_REGISTER; + + +/** + Processor Hard Power-On Configuration (R/W) Enables and disables processor + features; (R) indicates current processor configuration. + + @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_P6_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM. +**/ +#define MSR_P6_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled. + /// + UINT32 DataErrorCheckingEnable:1; + /// + /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W) + /// 1 = Enabled 0 = Disabled. + /// + UINT32 ResponseErrorCheckingEnable:1; + /// + /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled. + /// + UINT32 AERR_DriveEnable:1; + /// + /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = + /// Disabled. + /// + UINT32 BERR_Enable:1; + UINT32 Reserved2:1; + /// + /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = + /// Enabled 0 = Disabled. + /// + UINT32 BERR_DriverEnable:1; + /// + /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled. + /// + UINT32 BINIT_DriverEnable:1; + /// + /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled. + /// + UINT32 OutputTriStateEnable:1; + /// + /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled. + /// + UINT32 AERR_ObservationEnabled:1; + UINT32 Reserved3:1; + /// + /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled. + /// + UINT32 BINIT_ObservationEnabled:1; + /// + /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8. + /// + UINT32 InOrderQueueDepth:1; + /// + /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes. + /// + UINT32 ResetVector:1; + /// + /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled. + /// + UINT32 FRCModeEnable:1; + /// + /// [Bits 17:16] APIC Cluster ID (R). + /// + UINT32 APICClusterID:2; + /// + /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = + /// 133MHz 11 = Reserved. + /// + UINT32 SystemBusFrequency:2; + /// + /// [Bits 21:20] Symmetric Arbitration ID (R). + /// + UINT32 SymmetricArbitrationID:2; + /// + /// [Bits 25:22] Clock Frequency Ratio (R). + /// + UINT32 ClockFrequencyRatio:4; + /// + /// [Bit 26] Low Power Mode Enable (R/W). + /// + UINT32 LowPowerModeEnable:1; + /// + /// [Bit 27] Clock Frequency Ratio. + /// + UINT32 ClockFrequencyRatio1:1; + UINT32 Reserved4:4; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_EBL_CR_POWERON_REGISTER; + + +/** + Test Control Register. + + @param ECX MSR_P6_TEST_CTL (0x00000033) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_TEST_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_TEST_CTL_REGISTER. + + Example usage + @code + MSR_P6_TEST_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL); + AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64); + @endcode + @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM. +**/ +#define MSR_P6_TEST_CTL 0x00000033 + +/** + MSR information returned for MSR index #MSR_P6_TEST_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:30; + /// + /// [Bit 30] Streaming Buffer Disable. + /// + UINT32 StreamingBufferDisable:1; + /// + /// [Bit 31] Disable LOCK# Assertion for split locked access. + /// + UINT32 Disable_LOCK:1; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_TEST_CTL_REGISTER; + + +/** + BIOS Update Trigger Register. + + @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG); + AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr); + @endcode + @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM. +**/ +#define MSR_P6_BIOS_UPDT_TRIG 0x00000079 + + +/** + Chunk n data register D[63:0]: used to write to and read from the L2. + + @param ECX MSR_P6_BBL_CR_Dn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0); + AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr); + @endcode + @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM. + MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM. + MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM. + @{ +**/ +#define MSR_P6_BBL_CR_D0 0x00000088 +#define MSR_P6_BBL_CR_D1 0x00000089 +#define MSR_P6_BBL_CR_D2 0x0000008A +/// @} + + +/** + BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to + write to and read from the L2 depending on the usage model. + + @param ECX MSR_P6_BIOS_SIGN (0x0000008B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN); + AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr); + @endcode + @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM. +**/ +#define MSR_P6_BIOS_SIGN 0x0000008B + + +/** + + + @param ECX MSR_P6_PERFCTR0 (0x000000C1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_PERFCTR0); + AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr); + @endcode + @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM. + MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM. + @{ +**/ +#define MSR_P6_PERFCTR0 0x000000C1 +#define MSR_P6_PERFCTR1 0x000000C2 +/// @} + + +/** + + + @param ECX MSR_P6_MTRRCAP (0x000000FE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRCAP); + AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr); + @endcode + @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM. +**/ +#define MSR_P6_MTRRCAP 0x000000FE + + +/** + Address register: used to send specified address (A31-A3) to L2 during cache + initialization accesses. + + @param ECX MSR_P6_BBL_CR_ADDR (0x00000116) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_ADDR_REGISTER. + + Example usage + @code + MSR_P6_BBL_CR_ADDR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR); + AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64); + @endcode + @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM. +**/ +#define MSR_P6_BBL_CR_ADDR 0x00000116 + +/** + MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:3; + /// + /// [Bits 31:3] Address bits + /// + UINT32 Address:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_BBL_CR_ADDR_REGISTER; + + +/** + Data ECC register D[7:0]: used to write ECC and read ECC to/from L2. + + @param ECX MSR_P6_BBL_CR_DECC (0x00000118) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC); + AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr); + @endcode + @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM. +**/ +#define MSR_P6_BBL_CR_DECC 0x00000118 + + +/** + Control register: used to program L2 commands to be issued via cache + configuration accesses mechanism. Also receives L2 lookup response. + + @param ECX MSR_P6_BBL_CR_CTL (0x00000119) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_CTL_REGISTER. + + Example usage + @code + MSR_P6_BBL_CR_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL); + AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64); + @endcode + @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM. +**/ +#define MSR_P6_BBL_CR_CTL 0x00000119 + +/** + MSR information returned for MSR index #MSR_P6_BBL_CR_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] L2 Command + /// Data Read w/ LRU update (RLU) + /// Tag Read w/ Data Read (TRR) + /// Tag Inquire (TI) + /// L2 Control Register Read (CR) + /// L2 Control Register Write (CW) + /// Tag Write w/ Data Read (TWR) + /// Tag Write w/ Data Write (TWW) + /// Tag Write (TW). + /// + UINT32 L2Command:5; + /// + /// [Bits 6:5] State to L2 + /// + UINT32 StateToL2:2; + UINT32 Reserved:1; + /// + /// [Bits 9:8] Way to L2. + /// + UINT32 WayToL2:2; + /// + /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11. + /// + UINT32 Way:2; + /// + /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00. + /// + UINT32 MESI:2; + /// + /// [Bits 15:14] State from L2. + /// + UINT32 StateFromL2:2; + UINT32 Reserved2:1; + /// + /// [Bit 17] L2 Hit. + /// + UINT32 L2Hit:1; + UINT32 Reserved3:1; + /// + /// [Bits 20:19] User supplied ECC. + /// + UINT32 UserEcc:2; + /// + /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved. + /// + UINT32 ProcessorNumber:1; + UINT32 Reserved4:10; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_BBL_CR_CTL_REGISTER; + + +/** + Trigger register: used to initiate a cache configuration accesses access, + Write only with Data = 0. + + @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG); + AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr); + @endcode + @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM. +**/ +#define MSR_P6_BBL_CR_TRIG 0x0000011A + + +/** + Busy register: indicates when a cache configuration accesses L2 command is + in progress. D[0] = 1 = BUSY. + + @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY); + AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr); + @endcode + @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM. +**/ +#define MSR_P6_BBL_CR_BUSY 0x0000011B + + +/** + Control register 3: used to configure the L2 Cache. + + @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_BBL_CR_CTL3_REGISTER. + + Example usage + @code + MSR_P6_BBL_CR_CTL3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3); + AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64); + @endcode + @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM. +**/ +#define MSR_P6_BBL_CR_CTL3 0x0000011E + +/** + MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] L2 Configured (read/write ). + /// + UINT32 L2Configured:1; + /// + /// [Bits 4:1] L2 Cache Latency (read/write). + /// + UINT32 L2CacheLatency:4; + /// + /// [Bit 5] ECC Check Enable (read/write). + /// + UINT32 ECCCheckEnable:1; + /// + /// [Bit 6] Address Parity Check Enable (read/write). + /// + UINT32 AddressParityCheckEnable:1; + /// + /// [Bit 7] CRTN Parity Check Enable (read/write). + /// + UINT32 CRTNParityCheckEnable:1; + /// + /// [Bit 8] L2 Enabled (read/write). + /// + UINT32 L2Enabled:1; + /// + /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way + /// Reserved. + /// + UINT32 L2Associativity:2; + /// + /// [Bits 12:11] Number of L2 banks (read only). + /// + UINT32 L2Banks:2; + /// + /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes + /// 1MByte 2MByte 4MBytes. + /// + UINT32 CacheSizePerBank:5; + /// + /// [Bit 18] Cache State error checking enable (read/write). + /// + UINT32 CacheStateErrorEnable:1; + UINT32 Reserved1:1; + /// + /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes + /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes. + /// + UINT32 L2AddressRange:3; + /// + /// [Bit 23] L2 Hardware Disable (read only). + /// + UINT32 L2HardwareDisable:1; + UINT32 Reserved2:1; + /// + /// [Bit 25] Cache bus fraction (read only). + /// + UINT32 CacheBusFraction:1; + UINT32 Reserved3:6; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_BBL_CR_CTL3_REGISTER; + + +/** + CS register target for CPL 0 code. + + @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR); + AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr); + @endcode + @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM. +**/ +#define MSR_P6_SYSENTER_CS_MSR 0x00000174 + + +/** + Stack pointer for CPL 0 stack. + + @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR); + AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr); + @endcode + @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM. +**/ +#define MSR_P6_SYSENTER_ESP_MSR 0x00000175 + + +/** + CPL 0 code entry point. + + @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR); + AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr); + @endcode + @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM. +**/ +#define MSR_P6_SYSENTER_EIP_MSR 0x00000176 + + +/** + + + @param ECX MSR_P6_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MCG_CAP); + AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr); + @endcode + @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM. +**/ +#define MSR_P6_MCG_CAP 0x00000179 + + +/** + + + @param ECX MSR_P6_MCG_STATUS (0x0000017A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS); + AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr); + @endcode + @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM. +**/ +#define MSR_P6_MCG_STATUS 0x0000017A + + +/** + + + @param ECX MSR_P6_MCG_CTL (0x0000017B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MCG_CTL); + AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr); + @endcode + @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM. +**/ +#define MSR_P6_MCG_CTL 0x0000017B + + +/** + + + @param ECX MSR_P6_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_PERFEVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_PERFEVTSEL_REGISTER. + + Example usage + @code + MSR_P6_PERFEVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0); + AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64); + @endcode + @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM. + MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM. + @{ +**/ +#define MSR_P6_PERFEVTSEL0 0x00000186 +#define MSR_P6_PERFEVTSEL1 0x00000187 +/// @} + +/** + MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and + #MSR_P6_PERFEVTSEL1. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Event Select Refer to Performance Counter section for a + /// list of event encodings. + /// + UINT32 EventSelect:8; + /// + /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable + /// all count options. + /// + UINT32 UMASK:8; + /// + /// [Bit 16] USER Controls the counting of events at Privilege levels of + /// 1, 2, and 3. + /// + UINT32 USR:1; + /// + /// [Bit 17] OS Controls the counting of events at Privilege level of 0. + /// + UINT32 OS:1; + /// + /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration. + /// + UINT32 E:1; + /// + /// [Bit 19] PC Enabled the signaling of performance counter overflow via + /// BP0 pin. + /// + UINT32 PC:1; + /// + /// [Bit 20] INT Enables the signaling of counter overflow via input to + /// APIC 1 = Enable 0 = Disable. + /// + UINT32 INT:1; + UINT32 Reserved1:1; + /// + /// [Bit 22] ENABLE Enables the counting of performance events in both + /// counters 1 = Enable 0 = Disable. + /// + UINT32 EN:1; + /// + /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0 + /// = Non-Inverted. + /// + UINT32 INV:1; + /// + /// [Bits 31:24] CMASK (Counter Mask). + /// + UINT32 CMASK:8; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_PERFEVTSEL_REGISTER; + + +/** + + + @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_DEBUGCTLMSR_REGISTER. + + Example usage + @code + MSR_P6_DEBUGCTLMSR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR); + AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64); + @endcode + @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM. +**/ +#define MSR_P6_DEBUGCTLMSR 0x000001D9 + +/** + MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable/Disable Last Branch Records. + /// + UINT32 LBR:1; + /// + /// [Bit 1] Branch Trap Flag. + /// + UINT32 BTF:1; + /// + /// [Bit 2] Performance Monitoring/Break Point Pins. + /// + UINT32 PB0:1; + /// + /// [Bit 3] Performance Monitoring/Break Point Pins. + /// + UINT32 PB1:1; + /// + /// [Bit 4] Performance Monitoring/Break Point Pins. + /// + UINT32 PB2:1; + /// + /// [Bit 5] Performance Monitoring/Break Point Pins. + /// + UINT32 PB3:1; + /// + /// [Bit 6] Enable/Disable Execution Trace Messages. + /// + UINT32 TR:1; + UINT32 Reserved1:25; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_DEBUGCTLMSR_REGISTER; + + +/** + + + @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP); + AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr); + @endcode + @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM. +**/ +#define MSR_P6_LASTBRANCHFROMIP 0x000001DB + + +/** + + + @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP); + AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr); + @endcode + @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM. +**/ +#define MSR_P6_LASTBRANCHTOIP 0x000001DC + + +/** + + + @param ECX MSR_P6_LASTINTFROMIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP); + AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr); + @endcode + @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM. +**/ +#define MSR_P6_LASTINTFROMIP 0x000001DD + + +/** + + + @param ECX MSR_P6_LASTINTTOIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP); + AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr); + @endcode + @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM. +**/ +#define MSR_P6_LASTINTTOIP 0x000001DE + +/** + + + @param ECX MSR_P6_MTRRPHYSBASEn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0); + AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr); + @endcode + @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM. + MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM. + MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM. + MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM. + MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM. + MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM. + MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM. + MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM. + @{ +**/ +#define MSR_P6_MTRRPHYSBASE0 0x00000200 +#define MSR_P6_MTRRPHYSBASE1 0x00000202 +#define MSR_P6_MTRRPHYSBASE2 0x00000204 +#define MSR_P6_MTRRPHYSBASE3 0x00000206 +#define MSR_P6_MTRRPHYSBASE4 0x00000208 +#define MSR_P6_MTRRPHYSBASE5 0x0000020A +#define MSR_P6_MTRRPHYSBASE6 0x0000020C +#define MSR_P6_MTRRPHYSBASE7 0x0000020E +/// @} + + +/** + + + @param ECX MSR_P6_MTRRPHYSMASKn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0); + AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr); + @endcode + @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM. + MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM. + MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM. + MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM. + MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM. + MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM. + MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM. + MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM. + @{ +**/ +#define MSR_P6_MTRRPHYSMASK0 0x00000201 +#define MSR_P6_MTRRPHYSMASK1 0x00000203 +#define MSR_P6_MTRRPHYSMASK2 0x00000205 +#define MSR_P6_MTRRPHYSMASK3 0x00000207 +#define MSR_P6_MTRRPHYSMASK4 0x00000209 +#define MSR_P6_MTRRPHYSMASK5 0x0000020B +#define MSR_P6_MTRRPHYSMASK6 0x0000020D +#define MSR_P6_MTRRPHYSMASK7 0x0000020F +/// @} + + +/** + + + @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000); + AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr); + @endcode + @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM. +**/ +#define MSR_P6_MTRRFIX64K_00000 0x00000250 + + +/** + + + @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000); + AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr); + @endcode + @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM. +**/ +#define MSR_P6_MTRRFIX16K_80000 0x00000258 + + +/** + + + @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000); + AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr); + @endcode + @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM. +**/ +#define MSR_P6_MTRRFIX16K_A0000 0x00000259 + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_C0000 0x00000268 + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_C8000 0x00000269 + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_D0000 0x0000026A + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_D8000 0x0000026B + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_E0000 0x0000026C + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_E8000 0x0000026D + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_F0000 0x0000026E + + +/** + + + @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000); + AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr); + @endcode + @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM. +**/ +#define MSR_P6_MTRRFIX4K_F8000 0x0000026F + + +/** + + + @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_MTRRDEFTYPE_REGISTER. + + Example usage + @code + MSR_P6_MTRRDEFTYPE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE); + AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64); + @endcode + @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM. +**/ +#define MSR_P6_MTRRDEFTYPE 0x000002FF + +/** + MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Default memory type. + /// + UINT32 Type:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] Fixed MTRR enable. + /// + UINT32 FE:1; + /// + /// [Bit 11] MTRR Enable. + /// + UINT32 E:1; + UINT32 Reserved2:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_MTRRDEFTYPE_REGISTER; + + +/** + + + @param ECX MSR_P6_MC0_CTL (0x00000400) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MC0_CTL); + AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr); + @endcode + @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM. + MSR_P6_MC1_CTL is defined as MC1_CTL in SDM. + MSR_P6_MC2_CTL is defined as MC2_CTL in SDM. + MSR_P6_MC3_CTL is defined as MC3_CTL in SDM. + MSR_P6_MC4_CTL is defined as MC4_CTL in SDM. + @{ +**/ +#define MSR_P6_MC0_CTL 0x00000400 +#define MSR_P6_MC1_CTL 0x00000404 +#define MSR_P6_MC2_CTL 0x00000408 +#define MSR_P6_MC3_CTL 0x00000410 +#define MSR_P6_MC4_CTL 0x0000040C +/// @} + + +/** + + Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS, + except bits 0, 4, 57, and 61 are hardcoded to 1. + + @param ECX MSR_P6_MCn_STATUS + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_P6_MC_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_P6_MC_STATUS_REGISTER. + + Example usage + @code + MSR_P6_MC_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS); + AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64); + @endcode + @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM. + MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM. + MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM. + MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM. + MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM. + @{ +**/ +#define MSR_P6_MC0_STATUS 0x00000401 +#define MSR_P6_MC1_STATUS 0x00000405 +#define MSR_P6_MC2_STATUS 0x00000409 +#define MSR_P6_MC3_STATUS 0x00000411 +#define MSR_P6_MC4_STATUS 0x0000040D +/// @} + +/** + MSR information returned for MSR index #MSR_P6_MC0_STATUS to + #MSR_P6_MC4_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] MC_STATUS_MCACOD. + /// + UINT32 MC_STATUS_MCACOD:16; + /// + /// [Bits 31:16] MC_STATUS_MSCOD. + /// + UINT32 MC_STATUS_MSCOD:16; + UINT32 Reserved:25; + /// + /// [Bit 57] MC_STATUS_DAM. + /// + UINT32 MC_STATUS_DAM:1; + /// + /// [Bit 58] MC_STATUS_ADDRV. + /// + UINT32 MC_STATUS_ADDRV:1; + /// + /// [Bit 59] MC_STATUS_MISCV. + /// + UINT32 MC_STATUS_MISCV:1; + /// + /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is + /// hardcoded to 1.). + /// + UINT32 MC_STATUS_EN:1; + /// + /// [Bit 61] MC_STATUS_UC. + /// + UINT32 MC_STATUS_UC:1; + /// + /// [Bit 62] MC_STATUS_O. + /// + UINT32 MC_STATUS_O:1; + /// + /// [Bit 63] MC_STATUS_V. + /// + UINT32 MC_STATUS_V:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_P6_MC_STATUS_REGISTER; + + +/** + + MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors. + + @param ECX MSR_P6_MC0_ADDR (0x00000402) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR); + AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr); + @endcode + @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM. + MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM. + MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM. + MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM. + MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM. + @{ +**/ +#define MSR_P6_MC0_ADDR 0x00000402 +#define MSR_P6_MC1_ADDR 0x00000406 +#define MSR_P6_MC2_ADDR 0x0000040A +#define MSR_P6_MC3_ADDR 0x00000412 +#define MSR_P6_MC4_ADDR 0x0000040E +/// @} + + +/** + Defined in MCA architecture but not implemented in the P6 family processors. + + @param ECX MSR_P6_MC0_MISC (0x00000403) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_P6_MC0_MISC); + AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr); + @endcode + @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM. + MSR_P6_MC1_MISC is defined as MC1_MISC in SDM. + MSR_P6_MC2_MISC is defined as MC2_MISC in SDM. + MSR_P6_MC3_MISC is defined as MC3_MISC in SDM. + MSR_P6_MC4_MISC is defined as MC4_MISC in SDM. + @{ +**/ +#define MSR_P6_MC0_MISC 0x00000403 +#define MSR_P6_MC1_MISC 0x00000407 +#define MSR_P6_MC2_MISC 0x0000040B +#define MSR_P6_MC3_MISC 0x00000413 +#define MSR_P6_MC4_MISC 0x0000040F +/// @} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h new file mode 100644 index 0000000000..0fb4bff64b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h @@ -0,0 +1,2724 @@ +/** @file + MSR Definitions for Pentium(R) 4 Processors. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __PENTIUM_4_MSR_H__ +#define __PENTIUM_4_MSR_H__ + +#include + +/** + Is Pentium(R) 4 Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x0F \ + ) + +/** + 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range + Determination.". + + @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE); + AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr); + @endcode + @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM. +**/ +#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006 + + +/** + 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W) + Enables and disables processor features; (R) indicates current processor + configuration. + + @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON); + AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64); + @endcode + @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM. +**/ +#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state + /// output is enabled (1) or disabled (0) as set by the strapping of SMI#. + /// The value in this bit is written on the deassertion of RESET#; the bit + /// is set to 1 when the address bus signal is asserted. + /// + UINT32 OutputTriStateEnabled:1; + /// + /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST + /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The + /// value in this bit is written on the deassertion of RESET#; the bit is + /// set to 1 when the address bus signal is asserted. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue + /// depth for the system bus is 1 (1) or up to 12 (0) as set by the + /// strapping of A7#. The value in this bit is written on the deassertion + /// of RESET#; the bit is set to 1 when the address bus signal is asserted. + /// + UINT32 InOrderQueueDepth:1; + /// + /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR# + /// observation is enabled (0) or disabled (1) as determined by the + /// strapping of A9#. The value in this bit is written on the deassertion + /// of RESET#; the bit is set to 1 when the address bus signal is asserted. + /// + UINT32 MCERR_ObservationDisabled:1; + /// + /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT# + /// observation is enabled (0) or disabled (1) as determined by the + /// strapping of A10#. The value in this bit is written on the deassertion + /// of RESET#; the bit is set to 1 when the address bus signal is asserted. + /// + UINT32 BINIT_ObservationEnabled:1; + /// + /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID + /// value as set by the strapping of A12# and A11#. The logical cluster ID + /// value is written into the field on the deassertion of RESET#; the + /// field is set to 1 when the address bus signal is asserted. + /// + UINT32 APICClusterID:2; + /// + /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled + /// (0) or disabled (1) as set by the strapping of A15#. The value in this + /// bit is written on the deassertion of RESET#; the bit is set to 1 when + /// the address bus signal is asserted. + /// + UINT32 BusParkDisable:1; + UINT32 Reserved1:4; + /// + /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set + /// by the strapping of BR[3:0]. The logical ID value is written into the + /// field on the deassertion of RESET#; the field is set to 1 when the + /// address bus signal is asserted. + /// + UINT32 AgentID:2; + UINT32 Reserved2:18; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER; + + +/** + 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W) + Enables and disables processor features. + + @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON); + AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64); + @endcode + @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM. +**/ +#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the + /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear + /// to disabled (0, default). + /// + UINT32 RCNT_SCNT:1; + /// + /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data + /// bus parity checking; clear to enable parity checking. + /// + UINT32 DataErrorCheckingDisable:1; + /// + /// [Bit 2] Response Error Checking Disable (R/W) Set to disable + /// (default); clear to enable. + /// + UINT32 ResponseErrorCheckingDisable:1; + /// + /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable + /// (default); clear to enable. + /// + UINT32 AddressRequestErrorCheckingDisable:1; + /// + /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving + /// for initiator bus requests (default); clear to enable. + /// + UINT32 InitiatorMCERR_Disable:1; + /// + /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving + /// for initiator internal errors (default); clear to enable. + /// + UINT32 InternalMCERR_Disable:1; + /// + /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver + /// (default); clear to enable driver. + /// + UINT32 BINIT_DriverDisable:1; + UINT32 Reserved1:25; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER; + + +/** + 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of + this MSR varies according to the MODEL value in the CPUID version + information. The following bit field layout applies to Pentium 4 and Xeon + Processors with MODEL encoding equal or greater than 2. (R) The field + Indicates the current processor frequency configuration. + + @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID); + @endcode + @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM. +**/ +#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable + /// bus speed: *EncodingScalable Bus Speed* + /// + /// 000B 100 MHz (Model 2). + /// 000B 266 MHz (Model 3 or 4) + /// 001B 133 MHz + /// 010B 200 MHz + /// 011B 166 MHz + /// 100B 333 MHz (Model 6) + /// + /// 133.33 MHz should be utilized if performing calculation with System + /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if + /// performing calculation with System Bus Speed when encoding is 011B. + /// 266.67 MHz should be utilized if performing calculation with System + /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33 + /// MHz should be utilized if performing calculation with System Bus + /// Speed when encoding is 100B and model encoding = 6. All other values + /// are reserved. + /// + UINT32 ScalableBusSpeed:3; + UINT32 Reserved2:5; + /// + /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R) + /// The processor core clock frequency to system bus frequency ratio + /// observed at the de-assertion of the reset pin. + /// + UINT32 ClockRatio:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER; + + +/** + 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of + this MSR varies according to the MODEL value of the CPUID version + information. This bit field layout applies to Pentium 4 and Xeon Processors + with MODEL encoding less than 2. Indicates current processor frequency + configuration. + + @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1); + @endcode + @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM. +**/ +#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:21; + /// + /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable + /// bus speed: *Encoding* *Scalable Bus Speed* + /// + /// 000B 100 MHz All others values reserved. + /// + UINT32 ScalableBusSpeed:3; + UINT32 Reserved2:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER; + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RAX 0x00000180 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RBX 0x00000181 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RCX 0x00000182 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RDX 0x00000183 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RSI 0x00000184 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RDI 0x00000185 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RBP 0x00000186 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RSP 0x00000187 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section + 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register + state at time of machine check error. When in non-64-bit modes at the time + of the error, bits 63-32 do not contain valid data. + + @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM. +**/ +#define MSR_PENTIUM_4_MCG_RIP 0x00000189 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6, + "IA32_MCG Extended Machine Check State MSRs.". + + @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_MCG_MISC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64); + @endcode + @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM. +**/ +#define MSR_PENTIUM_4_MCG_MISC 0x0000018A + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] DS When set, the bit indicates that a page assist or page + /// fault occurred during DS normal operation. The processors response is + /// to shut down. The bit is used as an aid for debugging DS handling + /// code. It is the responsibility of the user (BIOS or operating system) + /// to clear this bit for normal operation. + /// + UINT32 DS:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_MCG_MISC_REGISTER; + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R8 0x00000190 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6, + "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the + associated state-save MSRs) exist only in Intel 64 processors. These + registers contain valid information only when the processor is operating in + 64-bit mode at the time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R9 0x00000191 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R10 0x00000192 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R11 0x00000193 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R12 0x00000194 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R13 0x00000195 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R14 0x00000196 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG + Extended Machine Check State MSRs.". Registers R8-15 (and the associated + state-save MSRs) exist only in Intel 64 processors. These registers contain + valid information only when the processor is operating in 64-bit mode at the + time of the error. + + @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15); + AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr); + @endcode + @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM. +**/ +#define MSR_PENTIUM_4_MCG_R15 0x00000197 + + +/** + Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors: + When read, specifies the value of the target TM2 transition last written. + When set, it sets the next target value for TM2 transition. 4, 6. Shared. + For Family F, Model 4 and Model 6 processors: When read, specifies the value + of the target TM2 transition last written. Writes may cause #GP exceptions. + + @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL); + AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr); + @endcode + @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. +**/ +#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D + + +/** + 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W). + + @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable. See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable. + /// + UINT32 FPU:1; + /// + /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal + /// Monitor," and see Table 2-2. + /// + UINT32 TM1:1; + /// + /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception + /// to be issued instead of a split-lock cycle. Operating systems that set + /// this bit must align system structures to avoid split-lock scenarios. + /// When the bit is clear (default), normal split-locks are issued to the + /// bus. + /// This debug feature is specific to the Pentium 4 processor. + /// + UINT32 SplitLockDisable:1; + UINT32 Reserved2:1; + /// + /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level + /// cache is disabled; when clear (default) the third-level cache is + /// enabled. This flag is reserved for processors that do not have a + /// third-level cache. Note that the bit controls only the third-level + /// cache; and only if overall caching is enabled through the CD flag of + /// control register CR0, the page-level cache controls, and/or the MTRRs. + /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.". + /// + UINT32 ThirdLevelCacheDisable:1; + /// + /// [Bit 7] Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + /// + /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is + /// suppressed during a Split Lock access. When clear (default), LOCK is + /// not suppressed. + /// + UINT32 SuppressLockEnable:1; + /// + /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue. + /// When clear (default), enables the prefetch queue. + /// + UINT32 PrefetchQueueDisable:1; + /// + /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt + /// reporting through the FERR# pin is enabled; when clear, this interrupt + /// reporting function is disabled. + /// When this flag is set and the processor is in the stop-clock state + /// (STPCLK# is asserted), asserting the FERR# pin signals to the + /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, + /// SMI#, or RESET#) is pending and that the processor should return to + /// normal operation to handle the interrupt. This flag does not affect + /// the normal operation of the FERR# pin (to indicate an unmasked + /// floatingpoint error) when the STPCLK# pin is not asserted. + /// + UINT32 FERR:1; + /// + /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See + /// Table 2-2. When set, the processor does not support branch trace + /// storage (BTS); when clear, BTS is supported. + /// + UINT32 BTS:1; + /// + /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable + /// (R) See Table 2-2. When set, the processor does not support processor + /// event-based sampling (PEBS); when clear, PEBS is supported. + /// + UINT32 PEBS:1; + /// + /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal + /// sensor indicates that the die temperature is at the predetermined + /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce + /// the bus to core ratio and voltage according to the value last written + /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the + /// processor does not change the VID signals or the bus to core ratio + /// when the processor enters a thermal managed state. If the TM2 feature + /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then + /// this feature is not supported and BIOS must not alter the contents of + /// this bit location. The processor is operating out of spec if both this + /// bit and the TM1 bit are set to disabled states. + /// + UINT32 TM2:1; + UINT32 Reserved3:4; + /// + /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + /// + /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1, + /// the processor fetches the cache line of the 128-byte sector containing + /// currently required data. When set to 0, the processor fetches both + /// cache lines in the sector. + /// Single processor platforms should not set this bit. Server platforms + /// should set or clear this bit based on platform performance observed + /// in validation and testing. BIOS may contain a setup option that + /// controls the setting of this bit. + /// + UINT32 AdjacentCacheLinePrefetchDisable:1; + UINT32 Reserved4:2; + /// + /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this + /// can cause unexpected behavior to software that depends on the + /// availability of CPUID leaves greater than 3. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + /// + /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache + /// is placed in shared mode; when clear (default), the cache is placed in + /// adaptive mode. This bit is only enabled for IA-32 processors that + /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data + /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are + /// identical, data in L1 is shared across logical processors. Otherwise, + /// L1 is not shared and cache use is competitive. If the Context ID + /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, + /// the ability to switch modes is not supported. BIOS must not alter the + /// contents of IA32_MISC_ENABLE[24]. + /// + UINT32 L1DataCacheContextMode:1; + UINT32 Reserved5:7; + UINT32 Reserved6:2; + /// + /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved7:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER; + + +/** + 3, 4, 6. Shared. Platform Feature Requirements (R). + + @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV); + @endcode + @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM. +**/ +#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1 + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:18; + /// + /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor + /// has specific platform requirements. The details of the platform + /// requirements are listed in the respective data sheets of the processor. + /// + UINT32 PLATFORM:1; + UINT32 Reserved2:13; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER; + + +/** + 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains + a pointer to the last branch instruction that the processor executed prior + to the last exception that was generated or the last interrupt that was + handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear + IP Linear address of the last branch instruction (If IA-32e mode is active). + From Linear IP Linear address of the last branch instruction. Reserved. + + @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP); + @endcode + @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area + contains a pointer to the target of the last branch instruction that the + processor executed prior to the last exception that was generated or the + last interrupt that was handled. See Section 17.13.3, "Last Exception + Records.". Unique. From Linear IP Linear address of the target of the last + branch instruction (If IA-32e mode is active). From Linear IP Linear address + of the target of the last branch instruction. Reserved. + + @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP); + @endcode + @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug + features are used. Bit definitions are discussed in the referenced section. + See Section 17.13.1, "MSR_DEBUGCTLA MSR.". + + @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA); + AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr); + @endcode + @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM. +**/ +#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9 + + +/** + 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an + index (0-3 or 0-15) that points to the top of the last branch record stack + (that is, that points the index of the MSR containing the most recent branch + record). See Section 17.13.2, "LBR Stack for Processors Based on Intel + NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH. + + @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA + + +/** + 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record + registers on the last branch record stack. It contains pointers to the + source and destination instruction for one of the last four branches, + exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through + MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models + 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See + Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording + for Processors based on Skylake Microarchitecture.". + + @param ECX MSR_PENTIUM_4_LASTBRANCH_n + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0); + AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr); + @endcode + @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. + MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. + MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. + MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB +#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC +#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD +#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". + + @param ECX MSR_PENTIUM_4_BPU_COUNTERn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0); + AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr); + @endcode + @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. + MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. + MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. + MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300 +#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301 +#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302 +#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". + + @param ECX MSR_PENTIUM_4_MS_COUNTERn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0); + AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr); + @endcode + @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. + MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. + MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. + MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304 +#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305 +#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306 +#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". + + @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0); + AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr); + @endcode + @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. + MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. + MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. + MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308 +#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309 +#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A +#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". + + @param ECX MSR_PENTIUM_4_IQ_COUNTERn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0); + AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr); + @endcode + @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. + MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. + MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. + MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. + MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. + MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C +#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D +#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E +#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F +#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310 +#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". + + @param ECX MSR_PENTIUM_4_BPU_CCCRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr); + @endcode + @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. + MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. + MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. + MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360 +#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361 +#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362 +#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". + + @param ECX MSR_PENTIUM_4_MS_CCCRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr); + @endcode + @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. + MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. + MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. + MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_MS_CCCR0 0x00000364 +#define MSR_PENTIUM_4_MS_CCCR1 0x00000365 +#define MSR_PENTIUM_4_MS_CCCR2 0x00000366 +#define MSR_PENTIUM_4_MS_CCCR3 0x00000367 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". + + @param ECX MSR_PENTIUM_4_FLAME_CCCRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr); + @endcode + @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. + MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. + MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. + MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368 +#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369 +#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A +#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". + + @param ECX MSR_PENTIUM_4_IQ_CCCRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr); + @endcode + @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. + MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. + MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. + MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. + MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. + MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C +#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D +#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E +#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F +#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370 +#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9 + + +/** + 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not + available on later processors. It is only available on processor family 0FH, + models 01H-02H. + + @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA + + +/** + 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not + available on later processors. It is only available on processor family 0FH, + models 01H-02H. + + @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM. +**/ +#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1); + AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr); + @endcode + @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM. +**/ +#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9 + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_ALF_ESCRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0); + AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr); + @endcode + @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. + MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. + MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. + MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. + MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. + MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM. + @{ +**/ +#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA +#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB +#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC +#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD +#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0 +#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1 +/// @} + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". + + @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT); + AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr); + @endcode + @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM. +**/ +#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0 + + +/** + 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W) + Controls the enabling of processor event sampling and replay tagging. + + @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE); + AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 12:0] See Table 19-36. + /// + UINT32 EventNum:13; + UINT32 Reserved1:11; + /// + /// [Bit 24] UOP Tag Enables replay tagging when set. + /// + UINT32 UOP:1; + /// + /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical + /// processor when set; disables PEBS when clear (default). See Section + /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target + /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors + /// that do not support Intel HyperThreading Technology. + /// + UINT32 ENABLE_PEBS_MY_THR:1; + /// + /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical + /// processor when set; disables PEBS when clear (default). See Section + /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target + /// logical processor. This bit is reserved for IA-32 processors that do + /// not support Intel Hyper-Threading Technology. + /// + UINT32 ENABLE_PEBS_OTH_THR:1; + UINT32 Reserved2:5; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER; + + +/** + 0, 1, 2, 3, 4, 6. Shared. See Table 19-36. + + @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT); + AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr); + @endcode + @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM. +**/ +#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2 + + +/** + 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch + record registers on the last branch record stack (680H-68FH). This part of + the stack contains pointers to the source instruction for one of the last 16 + branches, exceptions, or interrupts taken by the processor. The MSRs at + 680H-68FH, 6C0H-6CfH are not available in processor releases before family + 0FH, model 03H. These MSRs replace MSRs previously located at + 1DBH-1DEH.which performed the same function for early releases. See Section + 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for + Processors based on Skylake Microarchitecture.". + + @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. + @{ +**/ +#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680 +#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681 +#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682 +#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683 +#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684 +#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685 +#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686 +#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687 +#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688 +#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689 +#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A +#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B +#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C +#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D +#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E +#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F +/// @} + + +/** + 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch + record registers on the last branch record stack (6C0H-6CFH). This part of + the stack contains pointers to the destination instruction for one of the + last 16 branches, exceptions, or interrupts that the processor took. See + Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording + for Processors based on Skylake Microarchitecture.". + + @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. + MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. + @{ +**/ +#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0 +#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1 +#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2 +#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3 +#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4 +#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5 +#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6 +#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7 +#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8 +#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9 +#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA +#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB +#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC +#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD +#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE +#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF +/// @} + + +/** + 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section + 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to + 8-MByte L3 Cache.". + + @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC + + +/** + 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD + + +/** + 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section + 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to + 8-MByte L3 Cache.". + + @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE + + +/** + 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF + + +/** + 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section + 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to + 8-MByte L3 Cache.". + + @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0); + AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr); + @endcode + @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM. +**/ +#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0 + + +/** + 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1); + AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr); + @endcode + @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM. +**/ +#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1 + + +/** + 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6, + "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte + L3 Cache.". + + @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2 + + +/** + 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6, + "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte + L3 Cache.". + + @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7); + AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr); + @endcode + @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM. +**/ +#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3 + + +/** + 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section + 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to + 8MByte L3 Cache.". + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC + + +/** + 6. Shared. GBUSQ Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD + + +/** + 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section + 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to + 8MByte L3 Cache.". + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE + + +/** + 6. Shared. GSNPQ Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF + + +/** + 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6, + "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte + L3 Cache.". + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0 + + +/** + 6. Shared. FSB Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1 + + +/** + 6. Shared. FSB Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2 + + +/** + 6. Shared. FSB Event Control and Counter Register (R/W). + + @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7); + AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr); + @endcode + @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM. +**/ +#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h new file mode 100644 index 0000000000..e2944f38a1 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h @@ -0,0 +1,678 @@ +/** @file + MSR Definitions for Pentium M Processors. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __PENTIUM_M_MSR_H__ +#define __PENTIUM_M_MSR_H__ + +#include + +/** + Is Pentium M Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x0D \ + ) \ + ) + +/** + See Section 2.22, "MSRs in Pentium Processors.". + + @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR); + AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr); + @endcode + @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. +**/ +#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000 + + +/** + See Section 2.22, "MSRs in Pentium Processors.". + + @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE); + AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr); + @endcode + @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. +**/ +#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001 + + +/** + Processor Hard Power-On Configuration (R/W) Enables and disables processor + features. (R) Indicates current processor configuration. + + @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. +**/ +#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the + /// Pentium M processor. + /// + UINT32 DataErrorCheckingEnable:1; + /// + /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on + /// the Pentium M processor. + /// + UINT32 ResponseErrorCheckingEnable:1; + /// + /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium + /// M processor. + /// + UINT32 MCERR_DriveEnable:1; + /// + /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium + /// M processor. + /// + UINT32 AddressParityEnable:1; + UINT32 Reserved2:2; + /// + /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on + /// the Pentium M processor. + /// + UINT32 BINIT_DriverEnable:1; + /// + /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 OutputTriStateEnable:1; + /// + /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled. + /// + UINT32 ExecuteBIST:1; + /// + /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled + /// Always 0 on the Pentium M processor. + /// + UINT32 MCERR_ObservationEnabled:1; + UINT32 Reserved3:1; + /// + /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled + /// Always 0 on the Pentium M processor. + /// + UINT32 BINIT_ObservationEnabled:1; + UINT32 Reserved4:1; + /// + /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes + /// Always 0 on the Pentium M processor. + /// + UINT32 ResetVector:1; + UINT32 Reserved5:1; + /// + /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M + /// processor. + /// + UINT32 APICClusterID:2; + /// + /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always + /// 0 on the Pentium M processor. + /// + UINT32 SystemBusFrequency:1; + UINT32 Reserved6:1; + /// + /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium + /// M processor. + /// + UINT32 SymmetricArbitrationID:2; + /// + /// [Bits 26:22] Clock Frequency Ratio (R/O). + /// + UINT32 ClockFrequencyRatio:5; + UINT32 Reserved7:5; + UINT32 Reserved8:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER; + + +/** + Last Branch Record n (R/W) One of 8 last branch record registers on the last + branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold + the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section + 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M + Processors)". + + @param ECX MSR_PENTIUM_M_LASTBRANCH_n + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0); + AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr); + @endcode + @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. + MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. + MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. + MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. + MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM. + MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM. + MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM. + MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM. + @{ +**/ +#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040 +#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041 +#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042 +#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043 +#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044 +#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045 +#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046 +#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047 +/// @} + + +/** + Reserved. + + @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL); + AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr); + @endcode + @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM. +**/ +#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119 + + +/** + + + @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER. + + Example usage + @code + MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3); + AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64); + @endcode + @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. +**/ +#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E + +/** + MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = + /// Indicates if the L2 is hardware-disabled. + /// + UINT32 L2HardwareEnabled:1; + UINT32 Reserved1:4; + /// + /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the + /// cache data bus. ECC is always generated on write cycles. 1. = Disabled + /// (default) 2. = Enabled For the Pentium M processor, ECC checking on + /// the cache data bus is always enabled. + /// + UINT32 ECCCheckEnable:1; + UINT32 Reserved2:2; + /// + /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = + /// Disabled (default) Until this bit is set the processor will not + /// respond to the WBINVD instruction or the assertion of the FLUSH# input. + /// + UINT32 L2Enabled:1; + UINT32 Reserved3:14; + /// + /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. + /// + UINT32 L2NotPresent:1; + UINT32 Reserved4:8; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER; + + +/** + + + @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER. + + Example usage + @code + MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL); + AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64); + @endcode + @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. +**/ +#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D + +/** + MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = + /// Thermal Monitor 1 (thermally-initiated on-die modulation of the + /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated + /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is + /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled. + /// + UINT32 TM_SELECT:1; + UINT32 Reserved2:15; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_M_THERM2_CTL_REGISTER; + + +/** + Enable Miscellaneous Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:3; + /// + /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting + /// this bit enables the thermal control circuit (TCC) portion of the + /// Intel Thermal Monitor feature. This allows processor clocks to be + /// automatically modulated based on the processor's thermal sensor + /// operation. 0 = Disabled (default). The automatic thermal control + /// circuit enable bit determines if the thermal control circuit (TCC) + /// will be activated when the processor's internal thermal sensor + /// determines the processor is about to exceed its maximum operating + /// temperature. When the TCC is activated and TM1 is enabled, the + /// processors clocks will be forced to a 50% duty cycle. BIOS must enable + /// this feature. The bit should not be confused with the on-demand + /// thermal control circuit enable bit. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Performance Monitoring Available (R) 1 = Performance + /// monitoring enabled 0 = Performance monitoring disabled. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:2; + /// + /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the + /// processor to indicate a pending break event within the processor 0 = + /// Indicates compatible FERR# signaling behavior This bit must be set to + /// 1 to support XAPIC interrupt model usage. + /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't + /// support branch trace storage (BTS) 0 = BTS is supported + /// + UINT32 FERR:1; + /// + /// [Bit 11] Branch Trace Storage Unavailable (RO) + /// 1 = Processor doesn't support branch trace storage (BTS) + /// 0 = BTS is supported + /// + UINT32 BTS:1; + /// + /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 = + /// Processor does not support processor event based sampling (PEBS); 0 = + /// PEBS is supported. The Pentium M processor does not support PEBS. + /// + UINT32 PEBS:1; + UINT32 Reserved5:3; + /// + /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 = + /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M + /// processor, this bit may be configured to be read-only. + /// + UINT32 EIST:1; + UINT32 Reserved6:6; + /// + /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are + /// disabled. xTPR messages are optional messages that allow the processor + /// to inform the chipset of its priority. The default is processor + /// specific. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER; + + +/** + Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points + to the MSR containing the most recent branch record. See also: - + MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt, + and Exception Recording (Pentium M Processors)". + + @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9 + + +/** + Debug Control (R/W) Controls how several debug features are used. Bit + definitions are discussed in the referenced section. See Section 17.15, + "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).". + + @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB); + AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr); + @endcode + @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM. +**/ +#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9 + + +/** + Last Exception Record To Linear IP (R) This area contains a pointer to the + target of the last branch instruction that the processor executed prior to + the last exception that was generated or the last interrupt that was + handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording + (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception + MSRs.". + + @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP); + @endcode + @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD + + +/** + Last Exception Record From Linear IP (R) Contains a pointer to the last + branch instruction that the processor executed prior to the last exception + that was generated or the last interrupt that was handled. See Section + 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M + Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.". + + @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP); + @endcode + @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE + + +/** + See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". + + @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL); + AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr); + @endcode + @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM. +**/ +#define MSR_PENTIUM_M_MC4_CTL 0x0000040C + + +/** + See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.". + + @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS); + AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr); + @endcode + @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM. +**/ +#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D + + +/** + See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is + either not implemented or contains no address if the ADDRV flag in the + MSR_MC4_STATUS register is clear. When not implemented in the processor, all + reads and writes to this MSR will cause a general-protection exception. + + @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR); + AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr); + @endcode + @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM. +**/ +#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E + + +/** + See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". + + @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL); + AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr); + @endcode + @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM. +**/ +#define MSR_PENTIUM_M_MC3_CTL 0x00000410 + + +/** + See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.". + + @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS); + AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr); + @endcode + @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM. +**/ +#define MSR_PENTIUM_M_MC3_STATUS 0x00000411 + + +/** + See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is + either not implemented or contains no address if the ADDRV flag in the + MSR_MC3_STATUS register is clear. When not implemented in the processor, all + reads and writes to this MSR will cause a general-protection exception. + + @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR); + AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr); + @endcode + @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM. +**/ +#define MSR_PENTIUM_M_MC3_ADDR 0x00000412 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h new file mode 100644 index 0000000000..2e4bf6a259 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h @@ -0,0 +1,139 @@ +/** @file + MSR Definitions for Pentium Processors. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __PENTIUM_MSR_H__ +#define __PENTIUM_MSR_H__ + +#include + +/** + Is Pentium Processors? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x05 && \ + ( \ + DisplayModel == 0x01 || \ + DisplayModel == 0x02 || \ + DisplayModel == 0x04 \ + ) \ + ) + +/** + See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.". + + @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR); + AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr); + @endcode + @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. +**/ +#define MSR_PENTIUM_P5_MC_ADDR 0x00000000 + + +/** + See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.". + + @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE); + AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr); + @endcode + @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. +**/ +#define MSR_PENTIUM_P5_MC_TYPE 0x00000001 + + +/** + See Section 17.17, "Time-Stamp Counter.". + + @param ECX MSR_PENTIUM_TSC (0x00000010) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_TSC); + AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr); + @endcode + @note MSR_PENTIUM_TSC is defined as TSC in SDM. +**/ +#define MSR_PENTIUM_TSC 0x00000010 + + +/** + See Section 18.6.9.1, "Control and Event Select Register (CESR).". + + @param ECX MSR_PENTIUM_CESR (0x00000011) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_CESR); + AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr); + @endcode + @note MSR_PENTIUM_CESR is defined as CESR in SDM. +**/ +#define MSR_PENTIUM_CESR 0x00000011 + + +/** + Section 18.6.9.3, "Events Counted.". + + @param ECX MSR_PENTIUM_CTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0); + AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr); + @endcode + @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM. + MSR_PENTIUM_CTR1 is defined as CTR1 in SDM. + @{ +**/ +#define MSR_PENTIUM_CTR0 0x00000012 +#define MSR_PENTIUM_CTR1 0x00000013 +/// @} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h new file mode 100644 index 0000000000..981e5ef2e5 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h @@ -0,0 +1,4791 @@ +/** @file + MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __SANDY_BRIDGE_MSR_H__ +#define __SANDY_BRIDGE_MSR_H__ + +#include + +/** + Is Intel processors based on the Sandy Bridge microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x2A || \ + DisplayModel == 0x2D \ + ) \ + ) + +/** + Thread. SMI Counter (R/O). + + @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT); + @endcode + @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. +**/ +#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] SMI Count (R/O) Count SMIs. + /// + UINT32 SMICount:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER; + + +/** + Package. Platform Information Contains power management and other model + specific features enumeration. See http://biosbits.org. + + @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + UINT32 Reserved3:2; + UINT32 Reserved4:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved5:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. See http://biosbits.org. + + @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power). for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: + /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: + /// This field cannot be used to limit package C-state to C3. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map + /// IO_read instructions sent to IO register specified by + /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register + /// until next reset. + /// + UINT32 CFGLock:1; + UINT32 Reserved3:9; + /// + /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C6/C7 requests to C3 based on uncore + /// auto-demote information. + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor + /// will conditionally demote C3/C6/C7 requests to C1 based on uncore + /// auto-demote information. + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from + /// demoted C3. + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from + /// demoted C1. + /// + UINT32 C1Undemotion:1; + UINT32 Reserved4:3; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Core. Power Management IO Redirection in C-state (R/W) See + http://biosbits.org. + + @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. +**/ +#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address + /// visible to software for IO redirection. If IO MWAIT Redirection is + /// enabled, reads to this address will be consumed by the power + /// management logic and decoded to MWAIT instructions. When IO port + /// address redirection is enabled, this is the IO port address reported + /// to the OS/software. + /// + UINT32 Lvl2Base:16; + /// + /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the + /// maximum C-State code name to be included when IO read to MWAIT + /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 + /// is the max C-State to include 001b - C6 is the max C-State to include + /// 010b - C7 is the max C-State to include. + /// + UINT32 CStateRange:3; + UINT32 Reserved1:13; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER; + + +/** + Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP + handler to handle unsuccessful read of this MSR. + + @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. +**/ +#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this + /// MSR, the configuration of AES instruction set availability is as + /// follows: 11b: AES instructions are not available until next RESET. + /// otherwise, AES instructions are available. Note, AES instruction set + /// is not available if read is unsuccessful. If the configuration is not + /// 01b, AES instruction can be mis-configured if a privileged agent + /// unintentionally writes 11b. + /// + UINT32 AESConfiguration:2; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER; + + +/** + Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8. + + @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr); + @endcode + @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM. + MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM. + MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM. + MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A +#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B +#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C +#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D +/// @} + + +/** + Package. + + @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + /// + /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed + /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13). + /// + UINT32 CoreVoltage:16; + UINT32 Reserved2:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER; + + +/** + Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was + originally named IA32_THERM_CONTROL MSR. + + @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25% + /// increment. + /// + UINT32 OnDemandClockModulationDutyCycle:4; + /// + /// [Bit 4] On demand Clock Modulation Enable (R/W). + /// + UINT32 OnDemandClockModulationEnable:1; + UINT32 Reserved1:27; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:6; + /// + /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved2:3; + /// + /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + UINT32 Reserved3:3; + /// + /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved4:1; + /// + /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved5:3; + /// + /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved6:8; + UINT32 Reserved7:2; + /// + /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved8:3; + /// + /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors + /// that support Intel Turbo Boost Technology, the turbo mode feature is + /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: + /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: + /// EAX[1] reports the processor's support of turbo mode is enabled. Note: + /// the power-on default value is used by BIOS to detect hardware support + /// of turbo mode. If power-on default value is 1, turbo mode is available + /// in the processor. If power-on default value is 0, turbo mode is not + /// available. + /// + UINT32 TurboModeDisable:1; + UINT32 Reserved9:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER; + + +/** + Unique. + + @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (R) The minimum temperature at which + /// PROCHOT# will be asserted. The value is degree C. + /// + UINT32 TemperatureTarget:8; + UINT32 Reserved2:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER; + + +/** + Miscellaneous Feature Control (R/W). + + @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. +**/ +#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the + /// L2 hardware prefetcher, which fetches additional lines of code or data + /// into the L2 cache. + /// + UINT32 L2HardwarePrefetcherDisable:1; + /// + /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, + /// disables the adjacent cache line prefetcher, which fetches the cache + /// line that comprises a cache line pair (128 bytes). + /// + UINT32 L2AdjacentCacheLinePrefetcherDisable:1; + /// + /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables + /// the L1 data cache prefetcher, which fetches the next cache line into + /// L1 data cache. + /// + UINT32 DCUHardwarePrefetcherDisable:1; + /// + /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 + /// data cache IP prefetcher, which uses sequential load history (based on + /// instruction Pointer of previous loads) to determine whether to + /// prefetch additional lines. + /// + UINT32 DCUIPPrefetcherDisable:1; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER; + + +/** + Thread. Offcore Response Event Select Register (R/W). + + @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6 + + +/** + Thread. Offcore Response Event Select Register (R/W). + + @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7 + + +/** + See http://biosbits.org. + + @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr); + @endcode + @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM. +**/ +#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA + + +/** + Thread. Last Branch Record Filtering Select Register (R/W) See Section + 17.9.2, "Filtering of Last Branch Records.". + + @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + UINT32 Reserved1:23; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER; + + +/** + Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) + that points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP (at 680H). + + @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9 + + +/** + Thread. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP); + @endcode + @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD + + +/** + Thread. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP); + @endcode + @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE + + +/** + Core. See http://biosbits.org. + + @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC + + +/** + Package. Always 0 (CMCI not supported). + + @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284 + + +/** + See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.". + + @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Thread. Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Thread. Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Thread. Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + /// + /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). + /// + UINT32 Ovf_PMC4:1; + /// + /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). + /// + UINT32 Ovf_PMC5:1; + /// + /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). + /// + UINT32 Ovf_PMC6:1; + /// + /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). + /// + UINT32 Ovf_PMC7:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Thread. Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Thread. Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:26; + /// + /// [Bit 61] Thread. Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Thread. Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + /// + /// [Bit 63] Thread. CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control + Facilities.". + + @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Set 1 to enable PMC0 to count. + /// + UINT32 PCM0_EN:1; + /// + /// [Bit 1] Thread. Set 1 to enable PMC1 to count. + /// + UINT32 PCM1_EN:1; + /// + /// [Bit 2] Thread. Set 1 to enable PMC2 to count. + /// + UINT32 PCM2_EN:1; + /// + /// [Bit 3] Thread. Set 1 to enable PMC3 to count. + /// + UINT32 PCM3_EN:1; + /// + /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > + /// 4). + /// + UINT32 PCM4_EN:1; + /// + /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > + /// 5). + /// + UINT32 PCM5_EN:1; + /// + /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > + /// 6). + /// + UINT32 PCM6_EN:1; + /// + /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > + /// 7). + /// + UINT32 PCM7_EN:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count. + /// + UINT32 FIXED_CTR0:1; + /// + /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count. + /// + UINT32 FIXED_CTR1:1; + /// + /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count. + /// + UINT32 FIXED_CTR2:1; + UINT32 Reserved2:29; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER; + + +/** + See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.". + + @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390 + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + /// + /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). + /// + UINT32 Ovf_PMC4:1; + /// + /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). + /// + UINT32 Ovf_PMC5:1; + /// + /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). + /// + UINT32 Ovf_PMC6:1; + /// + /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). + /// + UINT32 Ovf_PMC7:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:26; + /// + /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + /// + /// [Bit 63] Thread. Set 1 to clear CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER; + + +/** + Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).". + + @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W). + /// + UINT32 PEBS_EN_PMC0:1; + /// + /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W). + /// + UINT32 PEBS_EN_PMC1:1; + /// + /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W). + /// + UINT32 PEBS_EN_PMC2:1; + /// + /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W). + /// + UINT32 PEBS_EN_PMC3:1; + UINT32 Reserved1:28; + /// + /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W). + /// + UINT32 LL_EN_PMC0:1; + /// + /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W). + /// + UINT32 LL_EN_PMC1:1; + /// + /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W). + /// + UINT32 LL_EN_PMC2:1; + /// + /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W). + /// + UINT32 LL_EN_PMC3:1; + UINT32 Reserved2:27; + /// + /// [Bit 63] Enable Precise Store. (R/W). + /// + UINT32 PS_EN:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER; + + +/** + Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring + Facility.". + + @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM. +**/ +#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Minimum threshold latency value of tagged load operation + /// that will be counted. (R/W). + /// + UINT32 MinimumThreshold:16; + UINT32 Reserved1:16; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C6 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C7 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C3 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C6 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C7 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE + + +/** + Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.". + + @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU + /// hardware detected errors. + /// + UINT32 PCUHardwareError:1; + /// + /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU + /// controller detected errors. + /// + UINT32 PCUControllerError:1; + /// + /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU + /// firmware detected errors. + /// + UINT32 PCUFirmwareError:1; + UINT32 Reserved1:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER; + + +/** + Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. + + @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM); + @endcode + @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. +**/ +#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, + "RAPL Interfaces.". + + @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT); + @endcode + @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606 + + +/** + Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. + + @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C3 state. + /// + UINT32 TimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time + /// unit of the interrupt response time limit. The following time unit + /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: + /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER; + + +/** + Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the + budget allocated for the package to exit from C6 to a C0 state, where + interrupt request can be delivered to the core and serviced. Additional + core-exit latency amy be applicable depending on the actual C-state the core + is in. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. + + @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C6 state. + /// + UINT32 TimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time + /// unit of the interrupt response time limit. The following time unit + /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: + /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C2 states. Count at the same frequency as the TSC. + + @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D + + +/** + Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package + RAPL Domain.". + + @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610 + + +/** + Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611 + + +/** + Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL + Domain.". + + @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614 + + +/** + Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 + RAPL Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638 + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639 + + +/** + Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last + branch record registers on the last branch record stack. This part of the + stack contains pointers to the source instruction. See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section + 17.4.8.1. + + @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680 +#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681 +#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682 +#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683 +#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684 +#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685 +#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686 +#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687 +#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688 +#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689 +#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A +#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B +#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C +#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D +#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E +#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F +/// @} + + +/** + Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch + record registers on the last branch record stack. This part of the stack + contains pointers to the destination instruction. + + @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. + MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0 +#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1 +#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2 +#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3 +#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4 +#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5 +#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6 +#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7 +#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8 +#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9 +#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA +#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB +#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC +#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD +#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE +#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF +/// @} + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT); + @endcode + @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5 core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6 core active. + /// + UINT32 Maximum6C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio + /// limit of 7 core active. + /// + UINT32 Maximum7C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio + /// limit of 8 core active. + /// + UINT32 Maximum8C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Uncore PMU global control. + + @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Slice 0 select. + /// + UINT32 PMI_Sel_Slice0:1; + /// + /// [Bit 1] Slice 1 select. + /// + UINT32 PMI_Sel_Slice1:1; + /// + /// [Bit 2] Slice 2 select. + /// + UINT32 PMI_Sel_Slice2:1; + /// + /// [Bit 3] Slice 3 select. + /// + UINT32 PMI_Sel_Slice3:1; + /// + /// [Bit 4] Slice 4 select. + /// + UINT32 PMI_Sel_Slice4:1; + UINT32 Reserved1:14; + UINT32 Reserved2:10; + /// + /// [Bit 29] Enable all uncore counters. + /// + UINT32 EN:1; + /// + /// [Bit 30] Enable wake on PMI. + /// + UINT32 WakePMI:1; + /// + /// [Bit 31] Enable Freezing counter when overflow. + /// + UINT32 FREEZE:1; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER; + + +/** + Package. Uncore PMU main status. + + @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392 + +/** + MSR information returned for MSR index + #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fixed counter overflowed. + /// + UINT32 Fixed:1; + /// + /// [Bit 1] An ARB counter overflowed. + /// + UINT32 ARB:1; + UINT32 Reserved1:1; + /// + /// [Bit 3] A CBox counter overflowed (on any slice). + /// + UINT32 CBox:1; + UINT32 Reserved2:28; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Package. Uncore fixed counter control (R/W). + + @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:20; + /// + /// [Bit 20] Enable overflow propagation. + /// + UINT32 EnableOverflow:1; + UINT32 Reserved2:1; + /// + /// [Bit 22] Enable counting. + /// + UINT32 EnableCounting:1; + UINT32 Reserved3:9; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER; + + +/** + Package. Uncore fixed counter. + + @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Current count. + /// + UINT32 CurrentCount:32; + /// + /// [Bits 47:32] Current count. + /// + UINT32 CurrentCountHi:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER; + + +/** + Package. Uncore C-Box configuration information (R/O). + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396 + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Report the number of C-Box units with performance counters, + /// including processor cores and processor graphics". + /// + UINT32 CBox:4; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER; + + +/** + Package. Uncore Arb unit, performance counter 0. + + @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0 + + +/** + Package. Uncore Arb unit, performance counter 1. + + @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1 + + +/** + Package. Uncore Arb unit, counter 0 event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2 + + +/** + Package. Uncore Arb unit, counter 1 event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3 + + +/** + Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the + budget allocated for the package to exit from C7 to a C0 state, where + interrupt request can be delivered to the core and serviced. Additional + core-exit latency amy be applicable depending on the actual C-state the core + is in. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. + + @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit + /// that should be used to decide if the package should be put into a + /// package C7 state. + /// + UINT32 TimeLimit:10; + /// + /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time + /// unit of the interrupt response time limit. The following time unit + /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: + /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns. + /// + UINT32 TimeUnit:3; + UINT32 Reserved1:2; + /// + /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are + /// valid and can be used by the processor for package C-sate management. + /// + UINT32 Valid:1; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER; + + +/** + Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A + + +/** + Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 + RAPL Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640 + + +/** + Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641 + + +/** + Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM. +**/ +#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642 + + +/** + Package. Uncore C-Box 0, counter n event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703 +/// @} + + +/** + Package. Uncore C-Box n, unit status for counter 0-3. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745 +/// @} + + +/** + Package. Uncore C-Box 0, performance counter n. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708 +#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709 +/// @} + + +/** + Package. Uncore C-Box 1, counter n event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713 +/// @} + + +/** + Package. Uncore C-Box 1, performance counter n. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718 +#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719 +/// @} + + +/** + Package. Uncore C-Box 2, counter n event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723 +/// @} + + +/** + Package. Uncore C-Box 2, performance counter n. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728 +#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729 +/// @} + + +/** + Package. Uncore C-Box 3, counter n event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733 +/// @} + + +/** + Package. Uncore C-Box 3, performance counter n. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738 +#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739 +/// @} + + +/** + Package. Uncore C-Box 4, counter n event select MSR. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743 +/// @} + + +/** + Package. Uncore C-Box 4, performance counter n. + + @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM. + MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM. + @{ +**/ +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748 +#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749 +/// @} + + +/** + Package. MC Bank Error Configuration (R/W). + + @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM. +**/ +#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank + /// to log additional info in bits 36:32. + /// + UINT32 MemErrorLogEnable:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER; + + +/** + Package. + + @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER. + + Example usage + @code + MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64); + @endcode + @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM. +**/ +#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C + +/** + MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS + /// counting logic for specific events requiring additional configuration, + /// see Table 19-17. + /// + UINT32 ENABLE_PEBS_NUM_ALT:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER; + + +/** + Package. Package RAPL Perf Status (R/O). + + @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613 + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619 + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS); + @endcode + @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Uncore U-box UCLK fixed counter control. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08 + + +/** + Package. Uncore U-box UCLK fixed counter. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09 + + +/** + Package. Uncore U-box perfmon event select for U-box counter 0. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10 + + +/** + Package. Uncore U-box perfmon event select for U-box counter 1. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11 + + +/** + Package. Uncore U-box perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16 + + +/** + Package. Uncore U-box perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17 + + +/** + Package. Uncore PCU perfmon for PCU-box-wide control. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 0. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 1. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 2. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32 + + +/** + Package. Uncore PCU perfmon event select for PCU counter 3. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33 + + +/** + Package. Uncore PCU perfmon box-wide filter. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34 + + +/** + Package. Uncore PCU perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36 + + +/** + Package. Uncore PCU perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37 + + +/** + Package. Uncore PCU perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38 + + +/** + Package. Uncore PCU perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39 + + +/** + Package. Uncore C-box 0 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12 + + +/** + Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13 + + +/** + Package. Uncore C-box 0 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14 + + +/** + Package. Uncore C-box 0 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16 + + +/** + Package. Uncore C-box 0 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17 + + +/** + Package. Uncore C-box 0 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18 + + +/** + Package. Uncore C-box 0 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19 + + +/** + Package. Uncore C-box 1 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32 + + +/** + Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33 + + +/** + Package. Uncore C-box 1 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34 + + +/** + Package. Uncore C-box 1 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36 + + +/** + Package. Uncore C-box 1 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37 + + +/** + Package. Uncore C-box 1 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38 + + +/** + Package. Uncore C-box 1 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39 + + +/** + Package. Uncore C-box 2 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52 + + +/** + Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53 + + +/** + Package. Uncore C-box 2 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54 + + +/** + Package. Uncore C-box 2 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56 + + +/** + Package. Uncore C-box 2 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57 + + +/** + Package. Uncore C-box 2 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58 + + +/** + Package. Uncore C-box 2 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59 + + +/** + Package. Uncore C-box 3 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72 + + +/** + Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73 + + +/** + Package. Uncore C-box 3 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74 + + +/** + Package. Uncore C-box 3 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76 + + +/** + Package. Uncore C-box 3 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77 + + +/** + Package. Uncore C-box 3 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78 + + +/** + Package. Uncore C-box 3 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79 + + +/** + Package. Uncore C-box 4 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92 + + +/** + Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93 + + +/** + Package. Uncore C-box 4 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94 + + +/** + Package. Uncore C-box 4 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96 + + +/** + Package. Uncore C-box 4 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97 + + +/** + Package. Uncore C-box 4 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98 + + +/** + Package. Uncore C-box 4 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99 + + +/** + Package. Uncore C-box 5 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2 + + +/** + Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3 + + +/** + Package. Uncore C-box 5 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4 + + +/** + Package. Uncore C-box 5 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6 + + +/** + Package. Uncore C-box 5 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7 + + +/** + Package. Uncore C-box 5 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8 + + +/** + Package. Uncore C-box 5 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9 + + +/** + Package. Uncore C-box 6 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2 + + +/** + Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3 + + +/** + Package. Uncore C-box 6 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4 + + +/** + Package. Uncore C-box 6 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6 + + +/** + Package. Uncore C-box 6 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7 + + +/** + Package. Uncore C-box 6 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8 + + +/** + Package. Uncore C-box 6 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9 + + +/** + Package. Uncore C-box 7 perfmon local box wide control. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2 + + +/** + Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3 + + +/** + Package. Uncore C-box 7 perfmon box wide filter. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4 + + +/** + Package. Uncore C-box 7 perfmon counter 0. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6 + + +/** + Package. Uncore C-box 7 perfmon counter 1. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7 + + +/** + Package. Uncore C-box 7 perfmon counter 2. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8 + + +/** + Package. Uncore C-box 7 perfmon counter 3. + + @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3); + AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr); + @endcode + @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM. +**/ +#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h new file mode 100644 index 0000000000..8218346da9 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h @@ -0,0 +1,1612 @@ +/** @file + MSR Definitions for Intel processors based on the Silvermont microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __SILVERMONT_MSR_H__ +#define __SILVERMONT_MSR_H__ + +#include + +/** + Is Intel processors based on the Silvermont microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x37 || \ + DisplayModel == 0x4A || \ + DisplayModel == 0x4D || \ + DisplayModel == 0x5A || \ + DisplayModel == 0x5D \ + ) \ + ) + +/** + Module. Model Specific Platform ID (R). + + @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID); + @endcode + @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM. +**/ +#define MSR_SILVERMONT_PLATFORM_ID 0x00000017 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio. + /// + UINT32 MaximumQualifiedRatio:5; + UINT32 Reserved2:19; + UINT32 Reserved3:18; + /// + /// [Bits 52:50] See Table 2-2. + /// + UINT32 PlatformId:3; + UINT32 Reserved4:11; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PLATFORM_ID_REGISTER; + + +/** + Module. Processor Hard Power-On Configuration (R/W) Writes ignored. + + @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER. + + Example usage + @code + MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON); + AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM. +**/ +#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A + +/** + MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER; + + +/** + Core. SMI Counter (R/O). + + @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_SMI_COUNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT); + @endcode + @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. +**/ +#define MSR_SILVERMONT_SMI_COUNT 0x00000034 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last + /// RESET. + /// + UINT32 SMICount:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_SMI_COUNT_REGISTER; + + +/** + Core. Control Features in Intel 64 Processor (R/W). See Table 2-2. + + @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A) + @param EAX Lower 32-bits of MSR value. + Described by the type + MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type + MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM. +**/ +#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A + +/** + MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock (R/WL). + /// + UINT32 Lock:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] Enable VMX outside SMX operation (R/WL). + /// + UINT32 EnableVmxOutsideSmx:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER; + + +/** + Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch + record registers on the last branch record stack. The From_IP part of the + stack contains pointers to the source instruction. See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.5 and record format in Section + 17.4.8.1. + + @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP); + AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr); + @endcode + @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. + @{ +**/ +#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040 +#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041 +#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042 +#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043 +#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044 +#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045 +#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046 +#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047 +/// @} + + +/** + Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch + record registers on the last branch record stack. The To_IP part of the + stack contains pointers to the destination instruction. + + @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP); + AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr); + @endcode + @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. + MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. + @{ +**/ +#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060 +#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061 +#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062 +#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063 +#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064 +#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065 +#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066 +#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067 +/// @} + + +/** + Module. Scalable Bus Speed(RO) This field indicates the intended scalable + bus clock speed for processors based on Silvermont microarchitecture:. + + @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER. + + Example usage + @code + MSR_SILVERMONT_FSB_FREQ_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ); + @endcode + @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM. +**/ +#define MSR_SILVERMONT_FSB_FREQ 0x000000CD + +/** + MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Scalable Bus Speed + /// + /// Silvermont Processor Family + /// --------------------------- + /// 100B: 080.0 MHz + /// 000B: 083.3 MHz + /// 001B: 100.0 MHz + /// 010B: 133.3 MHz + /// 011B: 116.7 MHz + /// + /// Airmont Processor Family + /// --------------------------- + /// 0000B: 083.3 MHz + /// 0001B: 100.0 MHz + /// 0010B: 133.3 MHz + /// 0011B: 116.7 MHz + /// 0100B: 080.0 MHz + /// 0101B: 093.3 MHz + /// 0110B: 090.0 MHz + /// 0111B: 088.9 MHz + /// 1000B: 087.5 MHz + /// + UINT32 ScalableBusSpeed:4; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_FSB_FREQ_REGISTER; + + +/** + Package. Platform Information: Contains power management and other model + specific features enumeration. See http://biosbits.org. + + @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO); + AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64); + @endcode +**/ +#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio + /// of the maximum frequency that does not require turbo. Frequency = + /// ratio * Scalable Bus Frequency. + /// + UINT32 MaximumNon_TurboRatio:8; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PLATFORM_INFO_REGISTER; + +/** + Module. C-State Configuration Control (R/W) Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI CStates. See http://biosbits.org. + + @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power). for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) + /// 100b: C4 110b: C6 111b: C7 (Silvermont only). + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map + /// IO_read instructions sent to IO register specified by + /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions. + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register + /// until next reset. + /// + UINT32 CFGLock:1; + UINT32 Reserved3:16; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Module. Power Management IO Redirection in C-state (R/W) See + http://biosbits.org. + + @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE); + AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. +**/ +#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address + /// visible to software for IO redirection. If IO MWAIT Redirection is + /// enabled, reads to this address will be consumed by the power + /// management logic and decoded to MWAIT instructions. When IO port + /// address redirection is enabled, this is the IO port address reported + /// to the OS/software. + /// + UINT32 Lvl2Base:16; + /// + /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the + /// maximum C-State code name to be included when IO read to MWAIT + /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 + /// is the max C-State to include 110b - C6 is the max C-State to include + /// 111b - C7 is the max C-State to include. + /// + UINT32 CStateRange:3; + UINT32 Reserved1:13; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER; + + +/** + Module. + + @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER. + + Example usage + @code + MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3); + AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. +**/ +#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E + +/** + MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = + /// Indicates if the L2 is hardware-disabled. + /// + UINT32 L2HardwareEnabled:1; + UINT32 Reserved1:7; + /// + /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = + /// Disabled (default) Until this bit is set the processor will not + /// respond to the WBINVD instruction or the assertion of the FLUSH# input. + /// + UINT32 L2Enabled:1; + UINT32 Reserved2:14; + /// + /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. + /// + UINT32 L2NotPresent:1; + UINT32 Reserved3:8; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER; + + +/** + Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP + handler to handle unsuccessful read of this MSR. + + @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER. + + Example usage + @code + MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG); + AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. +**/ +#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C + +/** + MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this + /// MSR, the configuration of AES instruction set availability is as + /// follows: 11b: AES instructions are not available until next RESET. + /// otherwise, AES instructions are available. Note, AES instruction set + /// is not available if read is unsuccessful. If the configuration is not + /// 01b, AES instruction can be mis-configured if a privileged agent + /// unintentionally writes 11b. + /// + UINT32 AESConfiguration:2; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER; + + +/** + Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. Fast-Strings Enable See Table 2-2. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See + /// Table 2-2. Default value is 0. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2. + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:3; + /// + /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2. + /// + UINT32 BTS:1; + /// + /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See + /// Table 2-2. + /// + UINT32 PEBS:1; + UINT32 Reserved4:3; + /// + /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See + /// Table 2-2. + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2. + /// + UINT32 MONITOR:1; + UINT32 Reserved6:3; + /// + /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2. + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2. + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2. + /// + UINT32 XD:1; + UINT32 Reserved9:3; + /// + /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors + /// that support Intel Turbo Boost Technology, the turbo mode feature is + /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H: + /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: + /// EAX[1] reports the processor's support of turbo mode is enabled. Note: + /// the power-on default value is used by BIOS to detect hardware support + /// of turbo mode. If power-on default value is 1, turbo mode is available + /// in the processor. If power-on default value is 0, turbo mode is not + /// available. + /// + UINT32 TurboModeDisable:1; + UINT32 Reserved10:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER; + + +/** + Package. + + @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (R) The default thermal throttling or + /// PROCHOT# activation temperature in degree C, The effective temperature + /// for thermal throttling or PROCHOT# activation is "Temperature Target" + /// + "Target Offset". + /// + UINT32 TemperatureTarget:8; + /// + /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to + /// adjust the throttling and PROCHOT# activation temperature from the + /// default target specified in TEMPERATURE_TARGET (bits 23:16). + /// + UINT32 TargetOffset:6; + UINT32 Reserved2:2; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER; + + +/** + Miscellaneous Feature Control (R/W). + + @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. +**/ +#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the + /// L2 hardware prefetcher, which fetches additional lines of code or data + /// into the L2 cache. + /// + UINT32 L2HardwarePrefetcherDisable:1; + UINT32 Reserved1:1; + /// + /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables + /// the L1 data cache prefetcher, which fetches the next cache line into + /// L1 data cache. + /// + UINT32 DCUHardwarePrefetcherDisable:1; + UINT32 Reserved2:29; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER; + + +/** + Module. Offcore Response Event Select Register (R/W). + + @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0); + AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr); + @endcode + @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. +**/ +#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6 + + +/** + Module. Offcore Response Event Select Register (R/W). + + @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1); + AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr); + @endcode + @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. +**/ +#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7 + + +/** + Package. Maximum Ratio Limit of Turbo Mode (RW). + + @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT); + AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5 core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6 core active. + /// + UINT32 Maximum6C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio + /// limit of 7 core active. + /// + UINT32 Maximum7C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio + /// limit of 8 core active. + /// + UINT32 Maximum8C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2, + "Filtering of Last Branch Records.". + + @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_LBR_SELECT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT); + AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_SILVERMONT_LBR_SELECT 0x000001C8 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + UINT32 Reserved1:23; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_LBR_SELECT_REGISTER; + + +/** + Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that + points to the MSR containing the most recent branch record. See + MSR_LASTBRANCH_0_FROM_IP. + + @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9 + + +/** + Core. Last Exception Record From Linear IP (R) Contains a pointer to the + last branch instruction that the processor executed prior to the last + exception that was generated or the last interrupt that was handled. + + @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP); + @endcode + @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD + + +/** + Core. Last Exception Record To Linear IP (R) This area contains a pointer + to the target of the last branch instruction that the processor executed + prior to the last exception that was generated or the last interrupt that + was handled. + + @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP); + @endcode + @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE + + +/** + Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling + (PEBS).". + + @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE); + AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W). + /// + UINT32 PEBS:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PEBS_ENABLE_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6 + Residency Counter. (R/O) Value since last reset that this package is in + processor-specific C6 states. Counts at the TSC Frequency. + + @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C6 states. Counts at the TSC Frequency. + + @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY); + AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr); + @endcode + @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. +**/ +#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD + + +/** + Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. + + @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM); + @endcode + @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. +**/ +#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C + + +/** + Core. Capability Reporting Register of VM-Function Controls (R/O) See Table + 2-2. + + @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC); + @endcode + @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM. +**/ +#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491 + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1 + Residency Counter. (R/O) Value since last reset that this core is in + processor-specific C1 states. Counts at the TSC frequency. + + @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY); + AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr); + @endcode + @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM. +**/ +#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660 + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1, + "RAPL Interfaces.". + + @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT); + @endcode + @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Power Units. Power related information (in milliWatts) is + /// based on the multiplier, 2^PU; where PU is an unsigned integer + /// represented by bits 3:0. Default value is 0101b, indicating power unit + /// is in 32 milliWatts increment. + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Energy Status Units. Energy related information (in + /// microJoules) is based on the multiplier, 2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 00101b, + /// indicating energy unit is in 32 microJoules increment. + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in + /// one second. + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. PKG RAPL Power Limit Control (R/W). + + @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT); + AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. +**/ +#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package + /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8. + /// + UINT32 Limit:15; + /// + /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package + /// RAPL Domain.". + /// + UINT32 Enable:1; + /// + /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3, + /// "Package RAPL Domain.". + /// + UINT32 ClampingLimit:1; + /// + /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second. + /// If 0 is specified in bits [23:17], defaults to 1 second window. + /// + UINT32 Time:7; + UINT32 Reserved1:8; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER; + + +/** + Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain." + and MSR_RAPL_POWER_UNIT in Table 2-8. + + @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS); + @endcode + @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. +**/ +#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611 + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains." + and MSR_RAPL_POWER_UNIT in Table 2-8. + + @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS); + @endcode + @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion + policy. Writing a value of 0 disables core level HW demotion policy. + + @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG); + AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr); + @endcode + @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM. +**/ +#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668 + + +/** + Package. Module C6 demotion policy config MSR. Controls module (i.e. two + cores sharing the second-level cache) C6 demotion policy. Writing a value of + 0 disables module level HW demotion policy. + + @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG); + AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr); + @endcode + @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM. +**/ +#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669 + + +/** + Module. Module C6 Residency Counter (R/0) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI CStates. Time that this module is in module-specific C6 states since + last reset. Counts at 1 Mhz frequency. + + @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER); + @endcode + @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM. +**/ +#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664 + + +/** + Package. PKG RAPL Parameter (R/0). + + @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO); + @endcode + @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. +**/ +#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is + /// the equivalent of thermal specification power of the package domain. + /// The unit of this field is specified by the "Power Units" field of + /// MSR_RAPL_POWER_UNIT. + /// + UINT32 ThermalSpecPower:15; + UINT32 Reserved1:17; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER; + + +/** + Package. PP0 RAPL Power Limit Control (R/W). + + @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT); + AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64); + @endcode + @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. +**/ +#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638 + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 + /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8. + /// + UINT32 Limit:15; + /// + /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 + /// RAPL Domains.". + /// + UINT32 Enable:1; + UINT32 Reserved1:1; + /// + /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time + /// duration over which the average power must remain below + /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time + /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time + /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration. + /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35 + /// second time duration. 0x8: 40 second time duration. 0x9: 45 second + /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved. + /// + UINT32 Time:7; + UINT32 Reserved2:8; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h new file mode 100644 index 0000000000..a33b18ee0b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h @@ -0,0 +1,3810 @@ +/** @file + MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __SKYLAKE_MSR_H__ +#define __SKYLAKE_MSR_H__ + +#include + +/** + Is Intel processors based on the Skylake microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x4E || \ + DisplayModel == 0x5E || \ + DisplayModel == 0x55 || \ + DisplayModel == 0x8E || \ + DisplayModel == 0x9E || \ + DisplayModel == 0x66 \ + ) \ + ) + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT); + @endcode + @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) + that points to the MSR containing the most recent branch record. + + @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9 + + +/** + Core. Power Control Register See http://biosbits.org. + + @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_POWER_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL); + AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_POWER_CTL 0x000001FC + +/** + MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU + /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating + /// point when all execution cores enter MWAIT (C1). + /// + UINT32 C1EEnable:1; + UINT32 Reserved2:17; + /// + /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit + /// disables the Race to Halt optimization and avoids this optimization + /// limitation to execute below the most efficient frequency ratio. + /// Default value is 0 for processors that support Race to Halt + /// optimization. Default value is 1 for processors that do not support + /// Race to Halt optimization. + /// + UINT32 Fix_Me_1:1; + /// + /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit + /// disables the P-States energy efficiency optimization. Default value is + /// 0. Disable/enable the energy efficiency optimization in P-State legacy + /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the + /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP + /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS + /// desired or OS maximize to the OS minimize performance setting. + /// + UINT32 DisableEnergyEfficiencyOptimization:1; + UINT32 Reserved3:11; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_POWER_CTL_REGISTER; + + +/** + Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update + CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in + the package. Lower 64 bits of an 128-bit external entropy value for key + derivation of an enclave. + + @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr); + @endcode + @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM. +**/ +#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300 + +// +// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM. +// +#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 +/** + Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update + CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in + the package. Upper 64 bits of an 128-bit external entropy value for key + derivation of an enclave. + + @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = 0; + AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr); + @endcode + @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM. +**/ +#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301 + +// +// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM. +// +#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1 + + +/** + See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring + Version 4.". + + @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E + +/** + MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Thread. Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Thread. Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Thread. Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + /// + /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). + /// + UINT32 Ovf_PMC4:1; + /// + /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). + /// + UINT32 Ovf_PMC5:1; + /// + /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). + /// + UINT32 Ovf_PMC6:1; + /// + /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). + /// + UINT32 Ovf_PMC7:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Thread. Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Thread. Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Thread. Trace_ToPA_PMI. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] Thread. LBR_Frz. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Thread. CTR_Frz. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Thread. ASCI. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Thread. Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Thread. Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + /// + /// [Bit 63] Thread. CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER; + + +/** + See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring + Version 4.". + + @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. +**/ +#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 + +/** + MSR information returned for MSR index + #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. + /// + UINT32 Ovf_PMC3:1; + /// + /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). + /// + UINT32 Ovf_PMC4:1; + /// + /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). + /// + UINT32 Ovf_PMC5:1; + /// + /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). + /// + UINT32 Ovf_PMC6:1; + /// + /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). + /// + UINT32 Ovf_PMC7:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] Thread. Set 1 to clear LBR_Frz. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Thread. Set 1 to clear CTR_Frz. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Thread. Set 1 to clear ASCI. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + /// + /// [Bit 63] Thread. Set 1 to clear CondChgd. + /// + UINT32 CondChgd:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; + + +/** + See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring + Version 4.". + + @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. +**/ +#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 + +/** + MSR information returned for MSR index + #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1. + /// + UINT32 Ovf_PMC0:1; + /// + /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1. + /// + UINT32 Ovf_PMC1:1; + /// + /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1. + /// + UINT32 Ovf_PMC2:1; + /// + /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1. + /// + UINT32 Ovf_PMC3:1; + /// + /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). + /// + UINT32 Ovf_PMC4:1; + /// + /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). + /// + UINT32 Ovf_PMC5:1; + /// + /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). + /// + UINT32 Ovf_PMC6:1; + /// + /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). + /// + UINT32 Ovf_PMC7:1; + UINT32 Reserved1:24; + /// + /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1. + /// + UINT32 Ovf_FixedCtr0:1; + /// + /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1. + /// + UINT32 Ovf_FixedCtr1:1; + /// + /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1. + /// + UINT32 Ovf_FixedCtr2:1; + UINT32 Reserved2:20; + /// + /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1. + /// + UINT32 Trace_ToPA_PMI:1; + UINT32 Reserved3:2; + /// + /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1. + /// + UINT32 LBR_Frz:1; + /// + /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1. + /// + UINT32 CTR_Frz:1; + /// + /// [Bit 60] Thread. Set 1 to cause ASCI = 1. + /// + UINT32 ASCI:1; + /// + /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore. + /// + UINT32 Ovf_Uncore:1; + /// + /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE. + /// + UINT32 Ovf_BufDSSAVE:1; + UINT32 Reserved4:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; + + +/** + Thread. FrontEnd Precise Event Condition Select (R/W). + + @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND); + AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM. +**/ +#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Event Code Select. + /// + UINT32 EventCodeSelect:3; + UINT32 Reserved1:1; + /// + /// [Bit 4] Event Code Select High. + /// + UINT32 EventCodeSelectHigh:1; + UINT32 Reserved2:3; + /// + /// [Bits 19:8] IDQ_Bubble_Length Specifier. + /// + UINT32 IDQ_Bubble_Length:12; + /// + /// [Bits 22:20] IDQ_Bubble_Width Specifier. + /// + UINT32 IDQ_Bubble_Width:3; + UINT32 Reserved3:9; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER; + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS); + @endcode + @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 + + +/** + Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both + platform vendor hardware implementation and BIOS enablement support it. This + MSR will read 0 if not valid. + + @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER); + @endcode + @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM. +**/ +#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Total energy consumed by all devices in the platform that + /// receive power from integrated power delivery mechanism, Included + /// platform devices are processor cores, SOC, memory, add-on or + /// peripheral devices that get powered directly from the platform power + /// delivery means. The energy units are specified in the + /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit. + /// + UINT32 TotalEnergy:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER; + + +/** + Thread. Productive Performance Count. (R/O). Hardware's view of workload + scalability. See Section 14.4.5.1. + + @param ECX MSR_SKYLAKE_PPERF (0x0000064E) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF); + @endcode + @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM. +**/ +#define MSR_SKYLAKE_PPERF 0x0000064E + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F + +/** + MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the + /// operating system request due to assertion of external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:2; + /// + /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is + /// reduced below the operating system request due to residency state + /// regulation limit. + /// + UINT32 ResidencyStateRegulationStatus:1; + /// + /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency + /// is reduced below the operating system request due to Running Average + /// Thermal Limit (RATL). + /// + UINT32 RunningAverageThermalLimitStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from a + /// processor Voltage Regulator (VR). + /// + UINT32 VRThermAlertStatus:1; + /// + /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is + /// reduced below the operating system request due to VR thermal design + /// current limit. + /// + UINT32 VRThermDesignCurrentStatus:1; + /// + /// [Bit 8] Other Status (R0) When set, frequency is reduced below the + /// operating system request due to electrical or other constraints. + /// + UINT32 OtherStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When + /// set, frequency is reduced below the operating system request due to + /// package/platform-level power limiting PL1. + /// + UINT32 PL1Status:1; + /// + /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When + /// set, frequency is reduced below the operating system request due to + /// package/platform-level power limiting PL2/PL3. + /// + UINT32 PL2Status:1; + /// + /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced + /// below the operating system request due to multi-core turbo limits. + /// + UINT32 MaxTurboLimitStatus:1; + /// + /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency + /// is reduced below the operating system request due to Turbo transition + /// attenuation. This prevents performance degradation due to frequent + /// operating ratio changes. + /// + UINT32 TurboTransitionAttenuationStatus:1; + UINT32 Reserved3:2; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved4:2; + /// + /// [Bit 20] Residency State Regulation Log When set, indicates that the + /// Residency State Regulation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 ResidencyStateRegulationLog:1; + /// + /// [Bit 21] Running Average Thermal Limit Log When set, indicates that + /// the RATL Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 RunningAverageThermalLimitLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + /// + /// [Bit 23] VR Thermal Design Current Log When set, indicates that the + /// VR TDC Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermalDesignCurrentLog:1; + /// + /// [Bit 24] Other Log When set, indicates that the Other Status bit has + /// asserted since the log bit was last cleared. This log bit will remain + /// set until cleared by software writing 0. + /// + UINT32 OtherLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, + /// indicates that the Package or Platform Level PL1 Power Limiting Status + /// bit has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, + /// indicates that the Package or Platform Level PL2/PL3 Power Limiting + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 PL2Log:1; + /// + /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo + /// Limit Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MaxTurboLimitLog:1; + /// + /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the + /// Turbo Transition Attenuation Status bit has asserted since the log bit + /// was last cleared. This log bit will remain set until cleared by + /// software writing 0. + /// + UINT32 TurboTransitionAttenuationLog:1; + UINT32 Reserved6:2; + UINT32 Reserved7:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER; + + +/** + Package. HDC Configuration (R/W).. + + @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG); + AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM. +**/ +#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for + /// MSR_PKG_HDC_DEEP_RESIDENCY. + /// + UINT32 PKG_Cx_Monitor:3; + UINT32 Reserved1:29; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER; + + +/** + Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt. + + @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY); + @endcode + @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM. +**/ +#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653 + + +/** + Package. Accumulate the cycles the package was in C2 state and at least one + logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt. + + @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY); + @endcode + @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM. +**/ +#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655 + + +/** + Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt. + + @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY); + @endcode + @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM. +**/ +#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656 + + +/** + Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate + as the TSC. The increment each cycle is weighted by the number of processor + cores in the package that reside in C0. If N cores are simultaneously in C0, + then each cycle the counter increments by N. + + @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0); + @endcode + @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM. +**/ +#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658 + + +/** + Package. Any Core C0 Residency. (R/O). Increment at the same rate as the + TSC. The increment each cycle is one if any processor core in the package is + in C0. + + @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0); + @endcode + @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM. +**/ +#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659 + + +/** + Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate + as the TSC. The increment each cycle is one if any processor graphic + device's compute engines are in C0. + + @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0); + @endcode + @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM. +**/ +#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A + + +/** + Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment + at the same rate as the TSC. The increment each cycle is one if at least one + compute engine of the processor graphics is in C0 and at least one processor + core in the package is also in C0. + + @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0); + @endcode + @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM. +**/ +#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B + + +/** + Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to + limit power consumption of the platform devices to the specified values. The + Long Duration power consumption is specified via Platform_Power_Limit_1 and + Platform_Power_Limit_1_Time. The Short Duration power consumption limit is + specified via the Platform_Power_Limit_2 with duration chosen by the + processor. The processor implements an exponential-weighted algorithm in the + placement of the time windows. + + @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT); + AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM. +**/ +#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which + /// the platform must not exceed over a time window as specified by + /// Power_Limit_1_TIME field. The default value is the Thermal Design + /// Power (TDP) and varies with product skus. The unit is specified in + /// MSR_RAPLPOWER_UNIT. + /// + UINT32 PlatformPowerLimit1:15; + /// + /// [Bit 15] Enable Platform Power Limit #1. When set, enables the + /// processor to apply control policy such that the platform power does + /// not exceed Platform Power limit #1 over the time window specified by + /// Power Limit #1 Time Window. + /// + UINT32 EnablePlatformPowerLimit1:1; + /// + /// [Bit 16] Platform Clamping Limitation #1. When set, allows the + /// processor to go below the OS requested P states in order to maintain + /// the power below specified Platform Power Limit #1 value. This bit is + /// writeable only when CPUID (EAX=6):EAX[4] is set. + /// + UINT32 PlatformClampingLimitation1:1; + /// + /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the + /// duration of the time window over which Platform Power Limit 1 value + /// should be maintained for sustained long duration. This field is made + /// up of two numbers from the following equation: Time Window = (float) + /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. = + /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is + /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH, + /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit]. + /// + UINT32 Time:7; + UINT32 Reserved1:8; + /// + /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which + /// the platform must not exceed over the Short Duration time window + /// chosen by the processor. The recommended default value is 1.25 times + /// the Long Duration Power Limit (i.e. Platform Power Limit # 1). + /// + UINT32 PlatformPowerLimit2:15; + /// + /// [Bit 47] Enable Platform Power Limit #2. When set, enables the + /// processor to apply control policy such that the platform power does + /// not exceed Platform Power limit #2 over the Short Duration time window. + /// + UINT32 EnablePlatformPowerLimit2:1; + /// + /// [Bit 48] Platform Clamping Limitation #2. When set, allows the + /// processor to go below the OS requested P states in order to maintain + /// the power below specified Platform Power Limit #2 value. + /// + UINT32 PlatformClampingLimitation2:1; + UINT32 Reserved2:14; + /// + /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR + /// until system RESET. + /// + UINT32 Lock:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER; + + +/** + Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last + branch record registers on the last branch record stack. This part of the + stack contains pointers to the source instruction. See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.10. + + @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP); + AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr); + @endcode + @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM. + @{ +**/ +#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690 +#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691 +#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692 +#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693 +#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694 +#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695 +#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696 +#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697 +#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698 +#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699 +#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A +#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B +#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C +#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D +#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E +#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F +/// @} + + +/** + Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) + (frequency refers to processor graphics frequency). + + @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 + +/** + MSR information returned for MSR index + #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to + /// assertion of external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a + /// thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:3; + /// + /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency + /// is reduced due to running average thermal limit. + /// + UINT32 RunningAverageThermalLimitStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due + /// to a thermal alert from a processor Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + /// + /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is + /// reduced due to VR TDC limit. + /// + UINT32 VRThermalDesignCurrentStatus:1; + /// + /// [Bit 8] Other Status (R0) When set, frequency is reduced due to + /// electrical or other constraints. + /// + UINT32 OtherStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When + /// set, frequency is reduced due to package/platform-level power limiting + /// PL1. + /// + UINT32 PL1Status:1; + /// + /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When + /// set, frequency is reduced due to package/platform-level power limiting + /// PL2/PL3. + /// + UINT32 PL2Status:1; + /// + /// [Bit 12] Inefficient Operation Status (R0) When set, processor + /// graphics frequency is operating below target frequency. + /// + UINT32 InefficientOperationStatus:1; + UINT32 Reserved3:3; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved4:3; + /// + /// [Bit 21] Running Average Thermal Limit Log When set, indicates that + /// the RATL Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 RunningAverageThermalLimitLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + /// + /// [Bit 23] VR Thermal Design Current Log When set, indicates that the + /// VR Therm Alert Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 VRThermalDesignCurrentLog:1; + /// + /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has + /// asserted since the log bit was last cleared. This log bit will remain + /// set until cleared by software writing 0. + /// + UINT32 OtherLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, + /// indicates that the Package/Platform Level PL1 Power Limiting Status + /// bit has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, + /// indicates that the Package/Platform Level PL2 Power Limiting Status + /// bit has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PL2Log:1; + /// + /// [Bit 28] Inefficient Operation Log When set, indicates that the + /// Inefficient Operation Status bit has asserted since the log bit was + /// last cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 InefficientOperationLog:1; + UINT32 Reserved6:3; + UINT32 Reserved7:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; + + +/** + Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) + (frequency refers to ring interconnect in the uncore). + + @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to + /// assertion of external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a + /// thermal event. + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:3; + /// + /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency + /// is reduced due to running average thermal limit. + /// + UINT32 RunningAverageThermalLimitStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due + /// to a thermal alert from a processor Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + /// + /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is + /// reduced due to VR TDC limit. + /// + UINT32 VRThermalDesignCurrentStatus:1; + /// + /// [Bit 8] Other Status (R0) When set, frequency is reduced due to + /// electrical or other constraints. + /// + UINT32 OtherStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When + /// set, frequency is reduced due to package/Platform-level power limiting + /// PL1. + /// + UINT32 PL1Status:1; + /// + /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When + /// set, frequency is reduced due to package/Platform-level power limiting + /// PL2/PL3. + /// + UINT32 PL2Status:1; + UINT32 Reserved3:4; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + UINT32 Reserved4:3; + /// + /// [Bit 21] Running Average Thermal Limit Log When set, indicates that + /// the RATL Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 RunningAverageThermalLimitLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + /// + /// [Bit 23] VR Thermal Design Current Log When set, indicates that the + /// VR Therm Alert Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 VRThermalDesignCurrentLog:1; + /// + /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has + /// asserted since the log bit was last cleared. This log bit will remain + /// set until cleared by software writing 0. + /// + UINT32 OtherLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, + /// indicates that the Package/Platform Level PL1 Power Limiting Status + /// bit has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PL1Log:1; + /// + /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, + /// indicates that the Package/Platform Level PL2 Power Limiting Status + /// bit has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PL2Log:1; + UINT32 Reserved6:4; + UINT32 Reserved7:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER; + + +/** + Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch + record registers on the last branch record stack. This part of the stack + contains pointers to the destination instruction. See also: - Last Branch + Record Stack TOS at 1C9H - Section 17.10. + + @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP); + AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr); + @endcode + @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. + MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM. + @{ +**/ +#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0 +#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1 +#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2 +#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3 +#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4 +#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5 +#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6 +#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7 +#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8 +#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9 +#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA +#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB +#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC +#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD +#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE +#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF +/// @} + + +/** + Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet + of last branch record registers on the last branch record stack. This part + of the stack contains flag, TSX-related and elapsed cycle information. See + also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR + Stack.". + + @param ECX MSR_SKYLAKE_LBR_INFO_n + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0); + AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr); + @endcode + @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM. + MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM. + MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM. + MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM. + MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM. + MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM. + MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM. + MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM. + MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM. + MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM. + MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM. + MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM. + MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM. + MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM. + MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM. + MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM. + MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM. + MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM. + MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM. + MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM. + MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM. + MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM. + MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM. + MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM. + MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM. + MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM. + MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM. + MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM. + MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM. + MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM. + MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM. + MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM. + @{ +**/ +#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0 +#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1 +#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2 +#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3 +#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4 +#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5 +#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6 +#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7 +#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8 +#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9 +#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA +#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB +#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC +#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD +#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE +#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF +#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0 +#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1 +#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2 +#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3 +#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4 +#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5 +#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6 +#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7 +#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8 +#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9 +#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA +#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB +#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC +#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD +#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE +#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF +/// @} + + +/** + Package. Uncore fixed counter control (R/W). + + @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. +**/ +#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:20; + /// + /// [Bit 20] Enable overflow propagation. + /// + UINT32 EnableOverflow:1; + UINT32 Reserved2:1; + /// + /// [Bit 22] Enable counting. + /// + UINT32 EnableCounting:1; + UINT32 Reserved3:9; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER; + + +/** + Package. Uncore fixed counter. + + @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. +**/ +#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Current count. + /// + UINT32 CurrentCount:32; + /// + /// [Bits 43:32] Current count. + /// + UINT32 CurrentCountHi:12; + UINT32 Reserved:20; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER; + + +/** + Package. Uncore C-Box configuration information (R/O). + + @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG); + @endcode + @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Specifies the number of C-Box units with programmable + /// counters (including processor cores and processor graphics),. + /// + UINT32 CBox:4; + UINT32 Reserved1:28; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER; + + +/** + Package. Uncore Arb unit, performance counter 0. + + @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0 + + +/** + Package. Uncore Arb unit, performance counter 1. + + @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1 + + +/** + Package. Uncore Arb unit, counter 0 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2 + + +/** + Package. Uncore Arb unit, counter 1 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3 + + +/** + Package. Uncore C-Box 0, counter 0 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700 + + +/** + Package. Uncore C-Box 0, counter 1 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701 + + +/** + Package. Uncore C-Box 0, performance counter 0. + + @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706 + + +/** + Package. Uncore C-Box 0, performance counter 1. + + @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707 + + +/** + Package. Uncore C-Box 1, counter 0 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710 + + +/** + Package. Uncore C-Box 1, counter 1 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711 + + +/** + Package. Uncore C-Box 1, performance counter 0. + + @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716 + + +/** + Package. Uncore C-Box 1, performance counter 1. + + @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717 + + +/** + Package. Uncore C-Box 2, counter 0 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720 + + +/** + Package. Uncore C-Box 2, counter 1 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721 + + +/** + Package. Uncore C-Box 2, performance counter 0. + + @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726 + + +/** + Package. Uncore C-Box 2, performance counter 1. + + @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727 + + +/** + Package. Uncore C-Box 3, counter 0 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730 + + +/** + Package. Uncore C-Box 3, counter 1 event select MSR. + + @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731 + + +/** + Package. Uncore C-Box 3, performance counter 0. + + @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736 + + +/** + Package. Uncore C-Box 3, performance counter 1. + + @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr); + @endcode + @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. +**/ +#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737 + + +/** + Package. Uncore PMU global control. + + @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. +**/ +#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Slice 0 select. + /// + UINT32 PMI_Sel_Slice0:1; + /// + /// [Bit 1] Slice 1 select. + /// + UINT32 PMI_Sel_Slice1:1; + /// + /// [Bit 2] Slice 2 select. + /// + UINT32 PMI_Sel_Slice2:1; + /// + /// [Bit 3] Slice 3 select. + /// + UINT32 PMI_Sel_Slice3:1; + /// + /// [Bit 4] Slice 4select. + /// + UINT32 PMI_Sel_Slice4:1; + UINT32 Reserved1:14; + UINT32 Reserved2:10; + /// + /// [Bit 29] Enable all uncore counters. + /// + UINT32 EN:1; + /// + /// [Bit 30] Enable wake on PMI. + /// + UINT32 WakePMI:1; + /// + /// [Bit 31] Enable Freezing counter when overflow. + /// + UINT32 FREEZE:1; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER; + + +/** + Package. Uncore PMU main status. + + @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS); + AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); + @endcode + @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. +**/ +#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fixed counter overflowed. + /// + UINT32 Fixed:1; + /// + /// [Bit 1] An ARB counter overflowed. + /// + UINT32 ARB:1; + UINT32 Reserved1:1; + /// + /// [Bit 3] A CBox counter overflowed (on any slice). + /// + UINT32 CBox:1; + UINT32 Reserved2:28; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER; + + +/** + Package. NPK Address Used by AET Messages (R/W). + + @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER. + + Example usage + @code + MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE); + AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 + +/** + MSR information returned for MSR index + #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock + /// bit has to be set in order for the AET packets to be directed to NPK + /// MMIO. + /// + UINT32 Fix_Me_1:1; + UINT32 Reserved:17; + /// + /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space. + /// + UINT32 ACPIBAR_BASE_ADDRESS:14; + /// + /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space. + /// + UINT32 Fix_Me_2:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER; + + +/** + Core. Processor Reserved Memory Range Register - Physical Base Control + Register (R/W). + + @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE); + AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] MemType PRMRR BASE MemType. + /// + UINT32 MemTypePRMRRBASEMemType:3; + UINT32 Reserved1:9; + /// + /// [Bits 31:12] Base PRMRR Base Address. + /// + UINT32 BasePRMRRBaseAddress:20; + /// + /// [Bits 45:32] Base PRMRR Base Address. + /// + UINT32 Fix_Me_1:14; + UINT32 Reserved2:18; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER; + + +/** + Core. Processor Reserved Memory Range Register - Physical Mask Control + Register (R/W). + + @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK); + AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:10; + /// + /// [Bit 10] Lock Lock bit for the PRMRR. + /// + UINT32 Fix_Me_1:1; + /// + /// [Bit 11] VLD Enable bit for the PRMRR. + /// + UINT32 VLD:1; + /// + /// [Bits 31:12] Mask PRMRR MASK bits. + /// + UINT32 Fix_Me_2:20; + /// + /// [Bits 45:32] Mask PRMRR MASK bits. + /// + UINT32 Fix_Me_3:14; + UINT32 Reserved2:18; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER; + + +/** + Core. Valid PRMRR Configurations (R/W). + + @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG); + AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] 1M supported MEE size. + /// + UINT32 Fix_Me_1:1; + UINT32 Reserved1:4; + /// + /// [Bit 5] 32M supported MEE size. + /// + UINT32 Fix_Me_2:1; + /// + /// [Bit 6] 64M supported MEE size. + /// + UINT32 Fix_Me_3:1; + /// + /// [Bit 7] 128M supported MEE size. + /// + UINT32 Fix_Me_4:1; + UINT32 Reserved2:24; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER; + + +/** + Package. (R/W) The PRMRR range is used to protect Xucode memory from + unauthorized reads and writes. Any IO access to this range is aborted. This + register controls the location of the PRMRR range by indicating its starting + address. It functions in tandem with the PRMRR mask register. + + @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE); + AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:12; + /// + /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the + /// base address memory range which is allocated to PRMRR memory. + /// + UINT32 Fix_Me_1:20; + /// + /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the + /// base address memory range which is allocated to PRMRR memory. + /// + UINT32 Fix_Me_2:7; + UINT32 Reserved2:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER; + + +/** + Package. (R/W) This register controls the size of the PRMRR range by + indicating which address bits must match the PRMRR base register value. + + @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER. + + Example usage + @code + MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK); + AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:10; + /// + /// [Bit 10] Lock Setting this bit locks all writeable settings in this + /// register, including itself. + /// + UINT32 Fix_Me_1:1; + /// + /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and + /// valid. + /// + UINT32 Fix_Me_2:1; + UINT32 Reserved2:20; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER; + +/** + Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits + for the LLC and Ring. + + @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT); + AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 Fix_Me_1:7; + UINT32 Reserved1:1; + /// + /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 Fix_Me_2:7; + UINT32 Reserved2:17; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER; + + +/** + Branch Monitoring Global Control (R/W). + + @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL); + AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] EnMonitoring Global enable for branch monitoring. + /// + UINT32 EnMonitoring:1; + /// + /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold + /// trip. The branch monitoring event handler is signaled via the existing + /// PMI signaling mechanism as programmed from the corresponding local + /// APIC LVT entry. + /// + UINT32 EnExcept:1; + /// + /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause + /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a + /// triggering condition occurs and this bit is enabled. + /// + UINT32 EnLBRFrz:1; + /// + /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event + /// triggering and LBR freeze actions are disabled when operating at VMX + /// non-root operation. + /// + UINT32 DisableInGuest:1; + UINT32 Reserved1:4; + /// + /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 - + /// 1023 are supported. Once the Window counter reaches the WindowSize + /// count both the Window Counter and all Branch Monitoring Counters are + /// cleared. + /// + UINT32 WindowSize:10; + UINT32 Reserved2:6; + /// + /// [Bits 25:24] WindowCntSel Window event count select: '00 = + /// Instructions retired. '01 = Branch instructions retired '10 = Return + /// instructions retired. '11 = Indirect branch instructions retired. + /// + UINT32 WindowCntSel:2; + /// + /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring + /// event triggering condition is true only if all enabled counters' + /// threshold conditions are true. When '0', the threshold tripping + /// condition is true if any enabled counters' threshold is true. + /// + UINT32 CntAndMode:1; + UINT32 Reserved3:5; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER; + +/** + Branch Monitoring Global Status (R/W). + + @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS); + AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch + /// Monitoring event signaling is blocked until this bit is cleared by + /// software. + /// + UINT32 BranchMonitoringEventSignaled:1; + /// + /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is + /// considered valid for sampling by branch monitoring software. + /// + UINT32 LBRsValid:1; + UINT32 Reserved1:6; + /// + /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This + /// status bit is sticky and once set requires clearing by software. + /// Counter operation continues independent of the state of the bit. + /// + UINT32 CntrHit0:1; + /// + /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This + /// status bit is sticky and once set requires clearing by software. + /// Counter operation continues independent of the state of the bit. + /// + UINT32 CntrHit1:1; + UINT32 Reserved2:6; + /// + /// [Bits 25:16] CountWindow The current value of the window counter. The + /// count value is frozen on a valid branch monitoring triggering + /// condition. This is a 10-bit unsigned value. + /// + UINT32 CountWindow:10; + UINT32 Reserved3:6; + /// + /// [Bits 39:32] Count0 The current value of counter 0 updated after each + /// occurrence of the event being counted. The count value is frozen on a + /// valid branch monitoring triggering condition (in which case CntrHit0 + /// will also be set). This is an 8-bit signed value (2's complement). + /// Heuristic events which only increment will saturate and freeze at + /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum + /// value 0x7F (+127) and minimum value 0x80 (-128). + /// + UINT32 Count0:8; + /// + /// [Bits 47:40] Count1 The current value of counter 1 updated after each + /// occurrence of the event being counted. The count value is frozen on a + /// valid branch monitoring triggering condition (in which case CntrHit1 + /// will also be set). This is an 8-bit signed value (2's complement). + /// Heuristic events which only increment will saturate and freeze at + /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum + /// value 0x7F (+127) and minimum value 0x80 (-128). + /// + UINT32 Count1:8; + UINT32 Reserved4:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER; + + +/** + Package. Package C3 Residency Counter (R/O). Note: C-state values are + processor specific C-state code names, unrelated to MWAIT extension C-state + parameters or ACPI C-states. + + @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY); + @endcode +**/ +#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8 + + +/** + Core. Core C1 Residency Counter (R/O). Value since last reset for the Core + C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC). + This counter counts in case both of the core's threads are in an idle state + and at least one of the core's thread residency is in a C1 state or in one + of its sub states. The counter is updated only after a core C state exit. + Note: Always reads 0 if core C1 is unsupported. A value of zero indicates + that this processor does not support core C1 or never entered core C1 level + state. + + @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY); + @endcode +**/ +#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660 + + +/** + Core. Core C3 Residency Counter (R/O). Will always return 0. + + @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY); + @endcode +**/ +#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662 + + +/** + Package. Protected Processor Inventory Number Enable Control (R/W). + + @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PPIN_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL); + AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PPIN_CTL 0x0000004E + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LockOut (R/WO) See Table 2-25. + /// + UINT32 LockOut:1; + /// + /// [Bit 1] Enable_PPIN (R/W) See Table 2-25. + /// + UINT32 Enable_PPIN:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PPIN_CTL_REGISTER; + + +/** + Package. Protected Processor Inventory Number (R/O). Protected Processor + Inventory Number (R/O) See Table 2-25. + + @param ECX MSR_SKYLAKE_PPIN (0x0000004F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN); + @endcode +**/ +#define MSR_SKYLAKE_PPIN 0x0000004F + + +/** + Package. Platform Information Contains power management and other model + specific features enumeration. See http://biosbits.org. + + @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO); + AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25. + /// + UINT32 MaximumNon_TurboRatio:8; + UINT32 Reserved2:7; + /// + /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25. + /// + UINT32 PPIN_CAP:1; + UINT32 Reserved3:4; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See + /// Table 2-25. + /// + UINT32 ProgrammableRatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See + /// Table 2-25. + /// + UINT32 ProgrammableTDPLimit:1; + /// + /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25. + /// + UINT32 ProgrammableTJOFFSET:1; + UINT32 Reserved4:1; + UINT32 Reserved5:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved6:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI C-states. `See http://biosbits.org. `__. + + @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package Cstate + /// limit. The following C-state code name encodings are supported: 000b: + /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) + /// 011b: C6 (retention) 111b: No Package C state limits. All C states + /// supported by the processor are available. + /// + UINT32 C_StateLimit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 MWAITRedirectionEnable:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + /// + /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor + /// will convert HALT or MWAT(C1) to MWAIT(C6). + /// + UINT32 AutomaticC_StateConversionEnable:1; + UINT32 Reserved3:8; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3StateAutoDemotionEnable:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1StateAutoDemotionEnable:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 EnableC3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 EnableC1Undemotion:1; + /// + /// [Bit 29] Package C State Demotion Enable (R/W). + /// + UINT32 CStateDemotionEnable:1; + /// + /// [Bit 30] Package C State UnDemotion Enable (R/W). + /// + UINT32 CStateUnDemotionEnable:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Thread. Global Machine Check Capability (R/O). + + @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP); + @endcode +**/ +#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count. + /// + UINT32 Count:8; + /// + /// [Bit 8] MCG_CTL_P. + /// + UINT32 MCG_CTL_P:1; + /// + /// [Bit 9] MCG_EXT_P. + /// + UINT32 MCG_EXT_P:1; + /// + /// [Bit 10] MCP_CMCI_P. + /// + UINT32 MCP_CMCI_P:1; + /// + /// [Bit 11] MCG_TES_P. + /// + UINT32 MCG_TES_P:1; + UINT32 Reserved1:4; + /// + /// [Bits 23:16] MCG_EXT_CNT. + /// + UINT32 MCG_EXT_CNT:8; + /// + /// [Bit 24] MCG_SER_P. + /// + UINT32 MCG_SER_P:1; + /// + /// [Bit 25] MCG_EM_P. + /// + UINT32 MCG_EM_P:1; + /// + /// [Bit 26] MCG_ELOG_P. + /// + UINT32 MCG_ELOG_P:1; + UINT32 Reserved2:5; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER; + + +/** + THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:26; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and a host-space interface is + /// available to SMM handler. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and a host-space interface is + /// available to SMM handler. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER; + + +/** + Package. Temperature Target. + + @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (RO) See Table 2-25. + /// + UINT32 TemperatureTarget:8; + /// + /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25. + /// + UINT32 TCCActivationOffset:4; + UINT32 Reserved2:4; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER; + +/** + Package. This register defines the active core ranges for each frequency + point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must + be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. + The last valid entry must have NUMCORE >= the number of cores in the SKU. If + any of the rules above are broken, the configuration is silently rejected. + + @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER. + + Example usage + @code + MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES); + AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE + +/** + MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency + /// point. + /// + UINT32 NUMCORE_0:8; + /// + /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_1:8; + /// + /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_2:8; + /// + /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_3:8; + /// + /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_4:8; + /// + /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_5:8; + /// + /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_6:8; + /// + /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each + /// frequency point. + /// + UINT32 NUMCORE_7:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER; + + +/** + Package. Unit Multipliers Used in RAPL Interfaces (R/O). + + @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT); + @endcode +**/ +#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Package. Energy Status Units Energy related information + /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 + /// micro-joules). + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL + /// Interfaces.". + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr); + @endcode +**/ +#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices. + + @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER. + + Example usage + @code + MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS); + @endcode +**/ +#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration + /// to enable DRAM RAPL mode 0 (Direct VR). + /// + UINT32 Energy:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER; + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS); + @endcode +**/ +#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr); + @endcode +**/ +#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio + fields represent the widest possible range of uncore frequencies. Writing to + these fields allows software to control the minimum and the maximum + frequency that hardware will select. + + @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT); + AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 MAX_RATIO:7; + UINT32 Reserved1:1; + /// + /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 MIN_RATIO:7; + UINT32 Reserved2:17; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER; + + +/** + Package. Reserved (R/O) Reads return 0. + + @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS); + @endcode +**/ +#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 + + +/** + THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H, + ECX=0):EBX.RDT-M[bit 12] = 1. + + @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D + +/** + MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 + /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: + /// Local memory bandwidth monitoring. All other encoding reserved. + /// + UINT32 EventID:8; + UINT32 Reserved1:24; + /// + /// [Bits 41:32] RMID (RW). + /// + UINT32 RMID:10; + UINT32 Reserved2:22; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER; + + +/** + THREAD. Resource Association Register (R/W). + + @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F + +/** + MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] RMID. + /// + UINT32 RMID:10; + UINT32 Reserved1:22; + /// + /// [Bits 51:32] COS (R/W). + /// + UINT32 COS:20; + UINT32 Reserved2:12; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER; + + +/** + Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H, + ECX=1):EDX.COS_MAX[15:0] >=0. + + @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER. + + Example usage + @code + MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N); + AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64); + @endcode +**/ +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99 +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E +#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F + +/** + MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement. + /// + UINT32 CBM:20; + UINT32 Reserved2:12; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER; + + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h new file mode 100644 index 0000000000..7f7824a8d0 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h @@ -0,0 +1,197 @@ +/** @file + MSR Definitions for Intel(R) Xeon(R) Processor Series 5600. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __XEON_5600_MSR_H__ +#define __XEON_5600_MSR_H__ + +#include + +/** + Is Intel(R) Xeon(R) Processor Series 5600? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x25 || \ + DisplayModel == 0x2C \ + ) \ + ) + +/** + Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP + handler to handle unsuccessful read of this MSR. + + @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER. + + Example usage + @code + MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG); + AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64); + @endcode + @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. +**/ +#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C + +/** + MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this + /// MSR, the configuration of AES instruction set availability is as + /// follows: 11b: AES instructions are not available until next RESET. + /// otherwise, AES instructions are available. Note, AES instruction set + /// is not available if read is unsuccessful. If the configuration is not + /// 01b, AES instruction can be mis-configured if a privileged agent + /// unintentionally writes 11b. + /// + UINT32 AESConfiguration:2; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_5600_FEATURE_CONFIG_REGISTER; + + +/** + Thread. Offcore Response Event Select Register (R/W). + + @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1); + AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr); + @endcode + @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. +**/ +#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7 + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT); + @endcode + @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio + /// limit of 1 core active. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio + /// limit of 2 core active. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio + /// limit of 3 core active. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio + /// limit of 4 core active. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio + /// limit of 5 core active. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio + /// limit of 6 core active. + /// + UINT32 Maximum6C:8; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. See Table 2-2. + + @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS); + AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr); + @endcode + @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. +**/ +#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0 + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h new file mode 100644 index 0000000000..e50c520e2e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h @@ -0,0 +1,1267 @@ +/** @file + MSR Definitions for Intel(R) Xeon(R) Processor D product Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __XEON_D_MSR_H__ +#define __XEON_D_MSR_H__ + +#include + +/** + Is Intel(R) Xeon(R) Processor D product Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x4F || \ + DisplayModel == 0x56 \ + ) \ + ) + +/** + Package. Protected Processor Inventory Number Enable Control (R/W). + + @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. + + Example usage + @code + MSR_XEON_D_PPIN_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL); + AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64); + @endcode + @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. +**/ +#define MSR_XEON_D_PPIN_CTL 0x0000004E + +/** + MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LockOut (R/WO) See Table 2-25. + /// + UINT32 LockOut:1; + /// + /// [Bit 1] Enable_PPIN (R/W) See Table 2-25. + /// + UINT32 Enable_PPIN:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_PPIN_CTL_REGISTER; + + +/** + Package. Protected Processor Inventory Number (R/O). Protected Processor + Inventory Number (R/O) See Table 2-25. + + @param ECX MSR_XEON_D_PPIN (0x0000004F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_D_PPIN); + @endcode + @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM. +**/ +#define MSR_XEON_D_PPIN 0x0000004F + + +/** + Package. See http://biosbits.org. + + @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_XEON_D_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO); + AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_XEON_D_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:7; + /// + /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25. + /// + UINT32 PPIN_CAP:1; + UINT32 Reserved3:4; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See + /// Table 2-25. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See + /// Table 2-25. + /// + UINT32 TDPLimit:1; + /// + /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25. + /// + UINT32 TJOFFSET:1; + UINT32 Reserved4:1; + UINT32 Reserved5:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved6:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_PLATFORM_INFO_REGISTER; + + +/** + Core. C-State Configuration Control (R/W) Note: C-state values are processor + specific C-state code names, unrelated to MWAIT extension C-state parameters + or ACPI C-states. `See http://biosbits.org. `__. + + @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest + /// processor-specific C-state code name (consuming the least power) for + /// the package. The default is set as factory-configured package C-state + /// limit. The following C-state code name encodings are supported: 000b: + /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) + /// 011b: C6 (retention) 111b: No Package C state limits. All C states + /// supported by the processor are available. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + /// + /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor + /// will convert HALT or MWAT(C1) to MWAIT(C6). + /// + UINT32 CStateConversion:1; + UINT32 Reserved3:8; + /// + /// [Bit 25] C3 State Auto Demotion Enable (R/W). + /// + UINT32 C3AutoDemotion:1; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W). + /// + UINT32 C1AutoDemotion:1; + /// + /// [Bit 27] Enable C3 Undemotion (R/W). + /// + UINT32 C3Undemotion:1; + /// + /// [Bit 28] Enable C1 Undemotion (R/W). + /// + UINT32 C1Undemotion:1; + /// + /// [Bit 29] Package C State Demotion Enable (R/W). + /// + UINT32 CStateDemotion:1; + /// + /// [Bit 30] Package C State UnDemotion Enable (R/W). + /// + UINT32 CStateUndemotion:1; + UINT32 Reserved4:1; + UINT32 Reserved5:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Thread. Global Machine Check Capability (R/O). + + @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. + + Example usage + @code + MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP); + @endcode + @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. +**/ +#define MSR_XEON_D_IA32_MCG_CAP 0x00000179 + +/** + MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Count. + /// + UINT32 Count:8; + /// + /// [Bit 8] MCG_CTL_P. + /// + UINT32 MCG_CTL_P:1; + /// + /// [Bit 9] MCG_EXT_P. + /// + UINT32 MCG_EXT_P:1; + /// + /// [Bit 10] MCP_CMCI_P. + /// + UINT32 MCP_CMCI_P:1; + /// + /// [Bit 11] MCG_TES_P. + /// + UINT32 MCG_TES_P:1; + UINT32 Reserved1:4; + /// + /// [Bits 23:16] MCG_EXT_CNT. + /// + UINT32 MCG_EXT_CNT:8; + /// + /// [Bit 24] MCG_SER_P. + /// + UINT32 MCG_SER_P:1; + /// + /// [Bit 25] MCG_EM_P. + /// + UINT32 MCG_EM_P:1; + /// + /// [Bit 26] MCG_ELOG_P. + /// + UINT32 MCG_ELOG_P:1; + UINT32 Reserved2:5; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_IA32_MCG_CAP_REGISTER; + + +/** + THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64); + @endcode + @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. +**/ +#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:26; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_SMM_MCA_CAP_REGISTER; + + +/** + Package. + + @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (RO) See Table 2-25. + /// + UINT32 TemperatureTarget:8; + /// + /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25. + /// + UINT32 TCCActivationOffset:4; + UINT32 Reserved2:4; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT); + @endcode + @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 1C. + /// + UINT32 Maximum1C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 2C. + /// + UINT32 Maximum2C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 3C. + /// + UINT32 Maximum3C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 4C. + /// + UINT32 Maximum4C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 5C. + /// + UINT32 Maximum5C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 6C. + /// + UINT32 Maximum6C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 7C. + /// + UINT32 Maximum7C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for 8C. + /// + UINT32 Maximum8C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. + + Example usage + @code + MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1); + @endcode + @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. +**/ +#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE + +/** + MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Package. Maximum Ratio Limit for 9C. + /// + UINT32 Maximum9C:8; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for 10C. + /// + UINT32 Maximum10C:8; + /// + /// [Bits 23:16] Package. Maximum Ratio Limit for 11C. + /// + UINT32 Maximum11C:8; + /// + /// [Bits 31:24] Package. Maximum Ratio Limit for 12C. + /// + UINT32 Maximum12C:8; + /// + /// [Bits 39:32] Package. Maximum Ratio Limit for 13C. + /// + UINT32 Maximum13C:8; + /// + /// [Bits 47:40] Package. Maximum Ratio Limit for 14C. + /// + UINT32 Maximum14C:8; + /// + /// [Bits 55:48] Package. Maximum Ratio Limit for 15C. + /// + UINT32 Maximum15C:8; + /// + /// [Bits 63:56] Package. Maximum Ratio Limit for 16C. + /// + UINT32 Maximum16C:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER; + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O). + + @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT); + @endcode + @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Package. Energy Status Units Energy related information + /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 + /// micro-joules). + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL + /// Interfaces.". + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices. + + @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. + + Example usage + @code + MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS); + @endcode + @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619 + +/** + MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration + /// to enable DRAM RAPL mode 0 (Direct VR). + /// + UINT32 Energy:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER; + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS); + @endcode + @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio + fields represent the widest possible range of uncore frequencies. Writing to + these fields allows software to control the minimum and the maximum + frequency that hardware will select. + + @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT); + AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 MAX_RATIO:7; + UINT32 Reserved1:1; + /// + /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 MIN_RATIO:7; + UINT32 Reserved2:17; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER; + +/** + Package. Reserved (R/O) Reads return 0. + + @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS); + @endcode + @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690 + +/** + MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is + /// reduced below the operating system request due to assertion of + /// external PROCHOT. + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the + /// operating system request due to a thermal event. + /// + UINT32 ThermalStatus:1; + /// + /// [Bit 2] Power Budget Management Status (R0) When set, frequency is + /// reduced below the operating system request due to PBM limit. + /// + UINT32 PowerBudgetManagementStatus:1; + /// + /// [Bit 3] Platform Configuration Services Status (R0) When set, + /// frequency is reduced below the operating system request due to PCS + /// limit. + /// + UINT32 PlatformConfigurationServicesStatus:1; + UINT32 Reserved1:1; + /// + /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) + /// When set, frequency is reduced below the operating system request + /// because the processor has detected that utilization is low. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1; + /// + /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced + /// below the operating system request due to a thermal alert from the + /// Voltage Regulator. + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is + /// reduced below the operating system request due to electrical design + /// point constraints (e.g. maximum electrical current consumption). + /// + UINT32 ElectricalDesignPointStatus:1; + UINT32 Reserved3:1; + /// + /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced + /// below the operating system request due to Multi-Core Turbo limits. + /// + UINT32 MultiCoreTurboStatus:1; + UINT32 Reserved4:2; + /// + /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced + /// below max non-turbo P1. + /// + UINT32 FrequencyP1Status:1; + /// + /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When + /// set, frequency is reduced below max n-core turbo frequency. + /// + UINT32 TurboFrequencyLimitingStatus:1; + /// + /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is + /// reduced below the operating system request. + /// + UINT32 FrequencyLimitingStatus:1; + /// + /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 PROCHOT_Log:1; + /// + /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 ThermalLog:1; + /// + /// [Bit 18] Power Budget Management Log When set, indicates that the PBM + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 PowerBudgetManagementLog:1; + /// + /// [Bit 19] Platform Configuration Services Log When set, indicates that + /// the PCS Status bit has asserted since the log bit was last cleared. + /// This log bit will remain set until cleared by software writing 0. + /// + UINT32 PlatformConfigurationServicesLog:1; + UINT32 Reserved5:1; + /// + /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, + /// indicates that the AUBFC Status bit has asserted since the log bit was + /// last cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 AutonomousUtilizationBasedFrequencyControlLog:1; + /// + /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm + /// Alert Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 VRThermAlertLog:1; + UINT32 Reserved6:1; + /// + /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP + /// Status bit has asserted since the log bit was last cleared. This log + /// bit will remain set until cleared by software writing 0. + /// + UINT32 ElectricalDesignPointLog:1; + UINT32 Reserved7:1; + /// + /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core + /// Turbo Status bit has asserted since the log bit was last cleared. This + /// log bit will remain set until cleared by software writing 0. + /// + UINT32 MultiCoreTurboLog:1; + UINT32 Reserved8:2; + /// + /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core + /// Frequency P1 Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CoreFrequencyP1Log:1; + /// + /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, + /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit + /// has asserted since the log bit was last cleared. This log bit will + /// remain set until cleared by software writing 0. + /// + UINT32 TurboFrequencyLimitingLog:1; + /// + /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core + /// Frequency Limiting Status bit has asserted since the log bit was last + /// cleared. This log bit will remain set until cleared by software + /// writing 0. + /// + UINT32 CoreFrequencyLimitingLog:1; + UINT32 Reserved9:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER; + + +/** + THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H, + ECX=0):EBX.RDT-M[bit 12] = 1. + + @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. + + Example usage + @code + MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL); + AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64); + @endcode + @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. +**/ +#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D + +/** + MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3 + /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03: + /// Local memory bandwidth monitoring All other encoding reserved. + /// + UINT32 EventID:8; + UINT32 Reserved1:24; + /// + /// [Bits 41:32] RMID (RW). + /// + UINT32 RMID:10; + UINT32 Reserved2:22; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER; + + +/** + THREAD. Resource Association Register (R/W). + + @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. + + Example usage + @code + MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC); + AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64); + @endcode + @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. +**/ +#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F + +/** + MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 9:0] RMID. + /// + UINT32 RMID:10; + UINT32 Reserved1:22; + /// + /// [Bits 51:32] COS (R/W). + /// + UINT32 COS:20; + UINT32 Reserved2:12; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER; + + +/** + Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, + ECX=1):EDX.COS_MAX[15:0] >= n. + + @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. + + Example usage + @code + MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0); + AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64); + @endcode + @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. + MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM. + @{ +**/ +#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90 +#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91 +#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92 +#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93 +#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94 +#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95 +#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96 +#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97 +#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98 +#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99 +#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A +#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B +#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C +#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D +#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E +#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F +/// @} + +/** + MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0 + to #MSR_XEON_D_IA32_L3_QOS_MASK_15. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement. + /// + UINT32 CBM:20; + UINT32 Reserved2:12; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER; + + +/** + Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, + RW if MSR_PLATFORM_INFO.[28] = 1. + + @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. + + Example usage + @code + MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3); + @endcode + @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM. +**/ +#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC + +/** + MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3 +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:32; + UINT32 Reserved2:31; + /// + /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, + /// the processor uses override configuration specified in + /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor + /// uses factory-set configuration (Default). + /// + UINT32 TurboRatioLimitConfigurationSemaphore:1; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER; + + +/** + Package. Cache Allocation Technology Configuration (R/W). + + @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. + + Example usage + @code + MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG); + AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64); + @endcode + @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. +**/ +#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81 + +/** + MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology. + /// + UINT32 CAT:1; + UINT32 Reserved1:31; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h new file mode 100644 index 0000000000..895dd800f7 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h @@ -0,0 +1,367 @@ +/** @file + MSR Definitions for Intel(R) Xeon(R) Processor E7 Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __XEON_E7_MSR_H__ +#define __XEON_E7_MSR_H__ + +#include + +/** + Is Intel(R) Xeon(R) Processor E7 Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x2F \ + ) \ + ) + +/** + Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP + handler to handle unsuccessful read of this MSR. + + @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER. + + Example usage + @code + MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG); + AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64); + @endcode + @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. +**/ +#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C + +/** + MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this + /// MSR, the configuration of AES instruction set availability is as + /// follows: 11b: AES instructions are not available until next RESET. + /// otherwise, AES instructions are available. Note, AES instruction set + /// is not available if read is unsuccessful. If the configuration is not + /// 01b, AES instruction can be mis-configured if a privileged agent + /// unintentionally writes 11b. + /// + UINT32 AESConfiguration:2; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_E7_FEATURE_CONFIG_REGISTER; + + +/** + Thread. Offcore Response Event Select Register (R/W). + + @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1); + AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr); + @endcode + @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. +**/ +#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7 + + +/** + Package. Reserved Attempt to read/write will cause #UD. + + @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT); + AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr); + @endcode + @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD + + +/** + Package. Uncore C-box 8 perfmon local box control MSR. + + @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM. +**/ +#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40 + + +/** + Package. Uncore C-box 8 perfmon local box status MSR. + + @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM. +**/ +#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41 + + +/** + Package. Uncore C-box 8 perfmon local box overflow control MSR. + + @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42 + + +/** + Package. Uncore C-box 8 perfmon event select MSR. + + @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM. + @{ +**/ +#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50 +#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52 +#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54 +#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56 +#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58 +#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A +/// @} + + +/** + Package. Uncore C-box 8 perfmon counter MSR. + + @param ECX MSR_XEON_E7_C8_PMON_CTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0); + AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr); + @endcode + @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. + MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. + MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. + MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. + MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM. + MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM. + @{ +**/ +#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51 +#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53 +#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55 +#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57 +#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59 +#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B +/// @} + + +/** + Package. Uncore C-box 9 perfmon local box control MSR. + + @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL); + AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr); + @endcode + @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM. +**/ +#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0 + + +/** + Package. Uncore C-box 9 perfmon local box status MSR. + + @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS); + AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr); + @endcode + @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM. +**/ +#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1 + + +/** + Package. Uncore C-box 9 perfmon local box overflow control MSR. + + @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL); + AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr); + @endcode + @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM. +**/ +#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2 + + +/** + Package. Uncore C-box 9 perfmon event select MSR. + + @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0); + AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr); + @endcode + @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM. + @{ +**/ +#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0 +#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2 +#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4 +#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6 +#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8 +#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA +/// @} + + +/** + Package. Uncore C-box 9 perfmon counter MSR. + + @param ECX MSR_XEON_E7_C9_PMON_CTRn + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0); + AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr); + @endcode + @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. + MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. + MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. + MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. + MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM. + MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM. + @{ +**/ +#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1 +#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3 +#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5 +#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7 +#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9 +#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB +/// @} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h new file mode 100644 index 0000000000..74d1969d30 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h @@ -0,0 +1,1673 @@ +/** @file + MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, + May 2018, Volume 4: Model-Specific-Registers (MSR) + +**/ + +#ifndef __XEON_PHI_MSR_H__ +#define __XEON_PHI_MSR_H__ + +#include + +/** + Is Intel(R) Xeon(R) Phi(TM) processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x57 || \ + DisplayModel == 0x85 \ + ) \ + ) + +/** + Thread. SMI Counter (R/O). + + @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER. + + Example usage + @code + MSR_XEON_PHI_SMI_COUNT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT); + @endcode + @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. +**/ +#define MSR_XEON_PHI_SMI_COUNT 0x00000034 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] SMI Count (R/O). + /// + UINT32 SMICount:32; + UINT32 Reserved:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_SMI_COUNT_REGISTER; + +/** + Package. Protected Processor Inventory Number Enable Control (R/W). + + @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER. + + Example usage + @code + MSR_XEON_PHI_PPIN_CTL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL); + AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64); + @endcode +**/ +#define MSR_XEON_PHI_PPIN_CTL 0x0000004E + +/** + MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to + /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if + /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an + /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a + /// privileged inventory initialization agent to access MSR_PPIN. After + /// reading MSR_PPIN, the privileged inventory initialization agent should + /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and + /// prevent unauthorized modification to MSR_PPIN_CTL. + /// + UINT32 LockOut:1; + /// + /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible + /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0] + /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. + /// Default is 0. + /// + UINT32 Enable_PPIN:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_PPIN_CTL_REGISTER; + + +/** + Package. Protected Processor Inventory Number (R/O). Protected Processor + Inventory Number (R/O) A unique value within a given CPUID + family/model/stepping signature that a privileged inventory initialization + agent can access to identify each physical processor, when access to + MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if + MSR_PPIN_CTL[bits 1:0] = '10b'. + + @param ECX MSR_XEON_PHI_PPIN (0x0000004F) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN); + @endcode +**/ +#define MSR_XEON_PHI_PPIN 0x0000004F + +/** + Package. Platform Information Contains power management and other model + specific features enumeration. See http://biosbits.org. + + @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO); + AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. +**/ +#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio + /// of the frequency that invariant TSC runs at. Frequency = ratio * 100 + /// MHz. + /// + UINT32 MaximumNonTurboRatio:8; + UINT32 Reserved2:12; + /// + /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When + /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is + /// enabled, and when set to 0, indicates Programmable Ratio Limits for + /// Turbo mode is disabled. + /// + UINT32 RatioLimit:1; + /// + /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When + /// set to 1, indicates that TDP Limits for Turbo mode are programmable, + /// and when set to 0, indicates TDP Limit for Turbo mode is not + /// programmable. + /// + UINT32 TDPLimit:1; + UINT32 Reserved3:2; + UINT32 Reserved4:8; + /// + /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the + /// minimum ratio (maximum efficiency) that the processor can operates, in + /// units of 100MHz. + /// + UINT32 MaximumEfficiencyRatio:8; + UINT32 Reserved5:16; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_PLATFORM_INFO_REGISTER; + + +/** + Module. C-State Configuration Control (R/W). + + @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER. + + Example usage + @code + MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. +**/ +#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code + /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No + /// Retention 011b: C6 Retention 111b: No limit. + /// + UINT32 Limit:3; + UINT32 Reserved1:7; + /// + /// [Bit 10] I/O MWAIT Redirection Enable (R/W). + /// + UINT32 IO_MWAIT:1; + UINT32 Reserved2:4; + /// + /// [Bit 15] CFG Lock (R/WO). + /// + UINT32 CFGLock:1; + UINT32 Reserved5:10; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor + /// will conditionally demote C3/C6/C7 requests to C1 based on uncore + /// auto-demote information. + /// + UINT32 C1StateAutoDemotionEnable:1; + UINT32 Reserved6:1; + /// + /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables + /// Undemotion from Demoted C1. + /// + UINT32 C1StateAutoUndemotionEnable:1; + /// + /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables + /// Package C state demotion. + /// + UINT32 PKGC_StateAutoDemotionEnable:1; + UINT32 Reserved7:2; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER; + + +/** + Module. Power Management IO Redirection in C-state (R/W). + + @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER. + + Example usage + @code + MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE); + AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM. +**/ +#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] LVL_2 Base Address (R/W). + /// + UINT32 Lvl2Base:16; + /// + /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which + /// IO-redirection will be executed (0-127). Should be programmed based on + /// the number of LVLx registers existing in the chipset. + /// + UINT32 CStateRange:7; + UINT32 Reserved3:9; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; + + +/** + Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP + handler to handle unsuccessful read of this MSR. + + @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER. + + Example usage + @code + MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG); + AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. +**/ +#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C + +/** + MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this + /// MSR, the configuration of AES instruction set availability is as + /// follows: 11b: AES instructions are not available until next RESET. + /// otherwise, AES instructions are available. Note, AES instruction set + /// is not available if read is unsuccessful. If the configuration is not + /// 01b, AES instruction can be mis-configured if a privileged agent + /// unintentionally writes 11b. + /// + UINT32 AESConfiguration:2; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER; + + +/** + Thread. MISC_FEATURE_ENABLES. + + @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER. + + Example usage + @code + MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES); + AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64); + @endcode +**/ +#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:1; + /// + /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and + /// MWAIT instructions do not cause invalid-opcode exceptions when + /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed + /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state + /// other than C0 or C1, the instruction operates as if EAX indicated the + /// C-state C1. + /// + UINT32 UserModeMonitorAndMwait:1; + UINT32 Reserved2:30; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER; + +/** + THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability + Enhancement. Accessible only while in SMM. + + @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER. + + Example usage + @code + MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP); + AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. +**/ +#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D + +/** + MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is + /// set, that bank supports Enhanced MCA (Default all 0; does not support + /// EMCA). + /// + UINT32 BankSupport:32; + UINT32 Reserved4:24; + /// + /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported. + /// + UINT32 TargetedSMI:1; + /// + /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature + /// is supported. + /// + UINT32 SMM_CPU_SVRSTR:1; + /// + /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the + /// SMM code access restriction is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 SMM_Code_Access_Chk:1; + /// + /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the + /// SMM long flow indicator is supported and a host-space interface + /// available to SMM handler. + /// + UINT32 Long_Flow_Indication:1; + UINT32 Reserved3:4; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER; + + +/** + Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor + functions to be enabled and disabled. + + @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER. + + Example usage + @code + MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE); + AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. +**/ +#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Fast-Strings Enable. + /// + UINT32 FastStrings:1; + UINT32 Reserved1:2; + /// + /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value + /// is 1. + /// + UINT32 AutomaticThermalControlCircuit:1; + UINT32 Reserved2:3; + /// + /// [Bit 7] Performance Monitoring Available (R). + /// + UINT32 PerformanceMonitoring:1; + UINT32 Reserved3:3; + /// + /// [Bit 11] Branch Trace Storage Unavailable (RO). + /// + UINT32 BTS:1; + /// + /// [Bit 12] Processor Event Based Sampling Unavailable (RO). + /// + UINT32 PEBS:1; + UINT32 Reserved4:3; + /// + /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W). + /// + UINT32 EIST:1; + UINT32 Reserved5:1; + /// + /// [Bit 18] ENABLE MONITOR FSM (R/W). + /// + UINT32 MONITOR:1; + UINT32 Reserved6:3; + /// + /// [Bit 22] Limit CPUID Maxval (R/W). + /// + UINT32 LimitCpuidMaxval:1; + /// + /// [Bit 23] xTPR Message Disable (R/W). + /// + UINT32 xTPR_Message_Disable:1; + UINT32 Reserved7:8; + UINT32 Reserved8:2; + /// + /// [Bit 34] XD Bit Disable (R/W). + /// + UINT32 XD:1; + UINT32 Reserved9:3; + /// + /// [Bit 38] Turbo Mode Disable (R/W). + /// + UINT32 TurboModeDisable:1; + UINT32 Reserved10:25; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER; + + +/** + Package. + + @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER. + + Example usage + @code + MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET); + AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. +**/ +#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:16; + /// + /// [Bits 23:16] Temperature Target (R). + /// + UINT32 TemperatureTarget:8; + /// + /// [Bits 29:24] Target Offset (R/W). + /// + UINT32 TargetOffset:6; + UINT32 Reserved2:2; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER; + + +/** + Miscellaneous Feature Control (R/W). + + @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER. + + Example usage + @code + MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL); + AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM. +**/ +#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the + /// L1 data cache prefetcher. + /// + UINT32 DCUHardwarePrefetcherDisable:1; + /// + /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the + /// L2 hardware prefetcher. + /// + UINT32 L2HardwarePrefetcherDisable:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER; + + +/** + Shared. Offcore Response Event Select Register (R/W). + + @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0); + AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr); + @endcode + @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM. +**/ +#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6 + + +/** + Shared. Offcore Response Event Select Register (R/W). + + @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1); + AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr); + @endcode + @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. +**/ +#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7 + + +/** + Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW). + + @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT); + AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. +**/ +#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD + +/** + MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved:1; + /// + /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active + /// processor cores which operates under the maximum ratio limit for group + /// 0. + /// + UINT32 MaxCoresGroup0:7; + /// + /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo + /// ratio limit when the number of active cores are not more than the + /// group 0 maximum core count. + /// + UINT32 MaxRatioLimitGroup0:8; + /// + /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1 + /// Group 1, which includes the specified number of additional cores plus + /// the cores in group 0, operates under the group 1 turbo max ratio limit + /// = "group 0 Max ratio limit" - "group ratio delta for group 1". + /// + UINT32 MaxIncrementalCoresGroup1:5; + /// + /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// to Group 0. + /// + UINT32 DeltaRatioGroup1:3; + /// + /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2 + /// Group 2, which includes the specified number of additional cores plus + /// all the cores in group 1, operates under the group 2 turbo max ratio + /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2". + /// + UINT32 MaxIncrementalCoresGroup2:5; + /// + /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// for Group 1. + /// + UINT32 DeltaRatioGroup2:3; + /// + /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3 + /// Group 3, which includes the specified number of additional cores plus + /// all the cores in group 2, operates under the group 3 turbo max ratio + /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3". + /// + UINT32 MaxIncrementalCoresGroup3:5; + /// + /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// for Group 2. + /// + UINT32 DeltaRatioGroup3:3; + /// + /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4 + /// Group 4, which includes the specified number of additional cores plus + /// all the cores in group 3, operates under the group 4 turbo max ratio + /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4". + /// + UINT32 MaxIncrementalCoresGroup4:5; + /// + /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// for Group 3. + /// + UINT32 DeltaRatioGroup4:3; + /// + /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5 + /// Group 5, which includes the specified number of additional cores plus + /// all the cores in group 4, operates under the group 5 turbo max ratio + /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5". + /// + UINT32 MaxIncrementalCoresGroup5:5; + /// + /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// for Group 4. + /// + UINT32 DeltaRatioGroup5:3; + /// + /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6 + /// Group 6, which includes the specified number of additional cores plus + /// all the cores in group 5, operates under the group 6 turbo max ratio + /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6". + /// + UINT32 MaxIncrementalCoresGroup6:5; + /// + /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned + /// integer specifying the ratio decrement relative to the Max ratio limit + /// for Group 5. + /// + UINT32 DeltaRatioGroup6:3; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER; + + +/** + Thread. Last Branch Record Filtering Select Register (R/W). + + @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT); + AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr); + @endcode + @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. +**/ +#define MSR_XEON_PHI_LBR_SELECT 0x000001C8 + + +/** + MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] CPL_EQ_0. + /// + UINT32 CPL_EQ_0:1; + /// + /// [Bit 1] CPL_NEQ_0. + /// + UINT32 CPL_NEQ_0:1; + /// + /// [Bit 2] JCC. + /// + UINT32 JCC:1; + /// + /// [Bit 3] NEAR_REL_CALL. + /// + UINT32 NEAR_REL_CALL:1; + /// + /// [Bit 4] NEAR_IND_CALL. + /// + UINT32 NEAR_IND_CALL:1; + /// + /// [Bit 5] NEAR_RET. + /// + UINT32 NEAR_RET:1; + /// + /// [Bit 6] NEAR_IND_JMP. + /// + UINT32 NEAR_IND_JMP:1; + /// + /// [Bit 7] NEAR_REL_JMP. + /// + UINT32 NEAR_REL_JMP:1; + /// + /// [Bit 8] FAR_BRANCH. + /// + UINT32 FAR_BRANCH:1; + UINT32 Reserved1:23; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_LBR_SELECT_REGISTER; + +/** + Thread. Last Branch Record Stack TOS (R/W). + + @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS); + AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr); + @endcode + @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. +**/ +#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9 + + +/** + Thread. Last Exception Record From Linear IP (R). + + @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP); + @endcode + @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. +**/ +#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD + + +/** + Thread. Last Exception Record To Linear IP (R). + + @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP); + @endcode + @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. +**/ +#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE + + +/** + Thread. See Table 2-2. + + @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE); + AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr); + @endcode + @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. +**/ +#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1 + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3 + Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8 + + +/** + Package. Package C6 Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9 + + +/** + Package. Package C7 Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA + + +/** + Module. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0 + Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC + + +/** + Module. Module C6 Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD + + +/** + Core. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6 + Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF + + +/** + Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2. + + @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM); + @endcode + @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM. +**/ +#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C + + +/** + Core. Capability Reporting Register of VM-Function Controls (R/O) See Table + 2-2. + + @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC); + @endcode + @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM. +**/ +#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491 + + +/** + Package. Unit Multipliers used in RAPL Interfaces (R/O). + + @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER. + + Example usage + @code + MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT); + @endcode + @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. +**/ +#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". + /// + UINT32 PowerUnits:4; + UINT32 Reserved1:4; + /// + /// [Bits 12:8] Package. Energy Status Units Energy related information + /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an + /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 + /// micro-joules). + /// + UINT32 EnergyStatusUnits:5; + UINT32 Reserved2:3; + /// + /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL + /// Interfaces.". + /// + UINT32 TimeUnits:4; + UINT32 Reserved3:12; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER; + + +/** + Package. Note: C-state values are processor specific C-state code names, + unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2 + Residency Counter. (R/O). + + @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr); + @endcode + @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM. +**/ +#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D + + +/** + Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package + RAPL Domain.". + + @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr); + @endcode + @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM. +**/ +#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610 + + +/** + Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS); + @endcode + @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM. +**/ +#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611 + + +/** + Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.". + + @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS); + @endcode + @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM. +**/ +#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613 + + +/** + Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL + Domain.". + + @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO); + AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr); + @endcode + @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM. +**/ +#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614 + + +/** + Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL + Domain.". + + @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT); + AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr); + @endcode + @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. +**/ +#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618 + + +/** + Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS); + @endcode + @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. +**/ +#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619 + + +/** + Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM + RAPL Domain.". + + @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS); + @endcode + @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. +**/ +#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B + + +/** + Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". + + @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO); + AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr); + @endcode + @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. +**/ +#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C + + +/** + Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio + fields represent the widest possible range of uncore frequencies. Writing to + these fields allows software to control the minimum and the maximum + frequency that hardware will select. + + @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER. + + Example usage + @code + MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT); + AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); + @endcode +**/ +#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the + /// LLC/Ring. + /// + UINT32 MAX_RATIO:7; + UINT32 Reserved1:1; + /// + /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum + /// possible ratio of the LLC/Ring. + /// + UINT32 MIN_RATIO:7; + UINT32 Reserved2:17; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER; + + +/** + Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1 + RAPL Domains.". + + @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT); + AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr); + @endcode + @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM. +**/ +#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638 + + +/** + Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL + Domains.". + + @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS); + @endcode + @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. +**/ +#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639 + + +/** + Package. Base TDP Ratio (R/O) See Table 2-24. + + @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL); + @endcode + @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM. +**/ +#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648 + + +/** + Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24. + + @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1); + @endcode + @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM. +**/ +#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649 + + +/** + Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24. + + @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2); + @endcode + @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM. +**/ +#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A + + +/** + Package. ConfigTDP Control (R/W) See Table 2-24. + + @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL); + AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr); + @endcode + @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM. +**/ +#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B + + +/** + Package. ConfigTDP Control (R/W) See Table 2-24. + + @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C) + @param EAX Lower 32-bits of MSR value. + @param EDX Upper 32-bits of MSR value. + + Example usage + @code + UINT64 Msr; + + Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO); + AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr); + @endcode + @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM. +**/ +#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C + + +/** + Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency + refers to processor core frequency). + + @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER. + + Example usage + @code + MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS); + AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64); + @endcode + @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. +**/ +#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690 + +/** + MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] PROCHOT Status (R0). + /// + UINT32 PROCHOT_Status:1; + /// + /// [Bit 1] Thermal Status (R0). + /// + UINT32 ThermalStatus:1; + UINT32 Reserved1:4; + /// + /// [Bit 6] VR Therm Alert Status (R0). + /// + UINT32 VRThermAlertStatus:1; + UINT32 Reserved2:1; + /// + /// [Bit 8] Electrical Design Point Status (R0). + /// + UINT32 ElectricalDesignPointStatus:1; + UINT32 Reserved3:23; + UINT32 Reserved4:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER; + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/SmramSaveStateMap.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/SmramSaveStateMap.h new file mode 100644 index 0000000000..ecdfca8fd4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/SmramSaveStateMap.h @@ -0,0 +1,184 @@ +/** @file +SMRAM Save State Map Definitions. + +SMRAM Save State Map definitions based on contents of the +Intel(R) 64 and IA-32 Architectures Software Developer's Manual + Volume 3C, Section 34.4 SMRAM + Volume 3C, Section 34.5 SMI Handler Execution Environment + Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs + +Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INTEL_SMRAM_SAVE_STATE_MAP_H__ +#define __INTEL_SMRAM_SAVE_STATE_MAP_H__ + +/// +/// Default SMBASE address +/// +#define SMM_DEFAULT_SMBASE 0x30000 + +/// +/// Offset of SMM handler from SMBASE +/// +#define SMM_HANDLER_OFFSET 0x8000 + +/// +/// Offset of SMRAM Save State Map from SMBASE +/// +#define SMRAM_SAVE_STATE_MAP_OFFSET 0xfc00 + +#pragma pack (1) + +/// +/// 32-bit SMRAM Save State Map +/// +typedef struct { + UINT8 Reserved[0x200]; // 7c00h + // Padded an extra 0x200 bytes so 32-bit and 64-bit + // SMRAM Save State Maps are the same size + UINT8 Reserved1[0xf8]; // 7e00h + UINT32 SMBASE; // 7ef8h + UINT32 SMMRevId; // 7efch + UINT16 IORestart; // 7f00h + UINT16 AutoHALTRestart; // 7f02h + UINT8 Reserved2[0x9C]; // 7f08h + UINT32 IOMemAddr; // 7fa0h + UINT32 IOMisc; // 7fa4h + UINT32 _ES; // 7fa8h + UINT32 _CS; // 7fach + UINT32 _SS; // 7fb0h + UINT32 _DS; // 7fb4h + UINT32 _FS; // 7fb8h + UINT32 _GS; // 7fbch + UINT32 Reserved3; // 7fc0h + UINT32 _TR; // 7fc4h + UINT32 _DR7; // 7fc8h + UINT32 _DR6; // 7fcch + UINT32 _EAX; // 7fd0h + UINT32 _ECX; // 7fd4h + UINT32 _EDX; // 7fd8h + UINT32 _EBX; // 7fdch + UINT32 _ESP; // 7fe0h + UINT32 _EBP; // 7fe4h + UINT32 _ESI; // 7fe8h + UINT32 _EDI; // 7fech + UINT32 _EIP; // 7ff0h + UINT32 _EFLAGS; // 7ff4h + UINT32 _CR3; // 7ff8h + UINT32 _CR0; // 7ffch +} SMRAM_SAVE_STATE_MAP32; + +/// +/// 64-bit SMRAM Save State Map +/// +typedef struct { + UINT8 Reserved1[0x1d0]; // 7c00h + UINT32 GdtBaseHiDword; // 7dd0h + UINT32 LdtBaseHiDword; // 7dd4h + UINT32 IdtBaseHiDword; // 7dd8h + UINT8 Reserved2[0xc]; // 7ddch + UINT64 IO_EIP; // 7de8h + UINT8 Reserved3[0x50]; // 7df0h + UINT32 _CR4; // 7e40h + UINT8 Reserved4[0x48]; // 7e44h + UINT32 GdtBaseLoDword; // 7e8ch + UINT32 Reserved5; // 7e90h + UINT32 IdtBaseLoDword; // 7e94h + UINT32 Reserved6; // 7e98h + UINT32 LdtBaseLoDword; // 7e9ch + UINT8 Reserved7[0x38]; // 7ea0h + UINT64 EptVmxControl; // 7ed8h + UINT32 EnEptVmxControl; // 7ee0h + UINT8 Reserved8[0x14]; // 7ee4h + UINT32 SMBASE; // 7ef8h + UINT32 SMMRevId; // 7efch + UINT16 IORestart; // 7f00h + UINT16 AutoHALTRestart; // 7f02h + UINT8 Reserved9[0x18]; // 7f04h + UINT64 _R15; // 7f1ch + UINT64 _R14; + UINT64 _R13; + UINT64 _R12; + UINT64 _R11; + UINT64 _R10; + UINT64 _R9; + UINT64 _R8; + UINT64 _RAX; // 7f5ch + UINT64 _RCX; + UINT64 _RDX; + UINT64 _RBX; + UINT64 _RSP; + UINT64 _RBP; + UINT64 _RSI; + UINT64 _RDI; + UINT64 IOMemAddr; // 7f9ch + UINT32 IOMisc; // 7fa4h + UINT32 _ES; // 7fa8h + UINT32 _CS; + UINT32 _SS; + UINT32 _DS; + UINT32 _FS; + UINT32 _GS; + UINT32 _LDTR; // 7fc0h + UINT32 _TR; + UINT64 _DR7; // 7fc8h + UINT64 _DR6; + UINT64 _RIP; // 7fd8h + UINT64 IA32_EFER; // 7fe0h + UINT64 _RFLAGS; // 7fe8h + UINT64 _CR3; // 7ff0h + UINT64 _CR0; // 7ff8h +} SMRAM_SAVE_STATE_MAP64; + +/// +/// Union of 32-bit and 64-bit SMRAM Save State Maps +/// +typedef union { + SMRAM_SAVE_STATE_MAP32 x86; + SMRAM_SAVE_STATE_MAP64 x64; +} SMRAM_SAVE_STATE_MAP; + +/// +/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map +/// +#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC 0x30004 + +/// +/// SMRAM Save State Map IOMisc I/O Length Values +/// +#define SMM_IO_LENGTH_BYTE 0x01 +#define SMM_IO_LENGTH_WORD 0x02 +#define SMM_IO_LENGTH_DWORD 0x04 + +/// +/// SMRAM Save State Map IOMisc I/O Instruction Type Values +/// +#define SMM_IO_TYPE_IN_IMMEDIATE 0x9 +#define SMM_IO_TYPE_IN_DX 0x1 +#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8 +#define SMM_IO_TYPE_OUT_DX 0x0 +#define SMM_IO_TYPE_INS 0x3 +#define SMM_IO_TYPE_OUTS 0x2 +#define SMM_IO_TYPE_REP_INS 0x7 +#define SMM_IO_TYPE_REP_OUTS 0x6 + +/// +/// SMRAM Save State Map IOMisc structure +/// +typedef union { + struct { + UINT32 SmiFlag:1; + UINT32 Length:3; + UINT32 Type:4; + UINT32 Reserved1:8; + UINT32 Port:16; + } Bits; + UINT32 Uint32; +} SMRAM_SAVE_STATE_IOMISC; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmApi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmApi.h new file mode 100644 index 0000000000..15d66aaf7a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmApi.h @@ -0,0 +1,948 @@ +/** @file + STM API definition + + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SMI Transfer Monitor (STM) User Guide Revision 1.00 + +**/ + +#ifndef _INTEL_STM_API_H_ +#define _INTEL_STM_API_H_ + +#include +#include +#include + +#pragma pack (1) + +/** + STM Header Structures +**/ + +typedef struct { + UINT32 Intel64ModeSupported :1; ///> bitfield + UINT32 EptSupported :1; ///> bitfield + UINT32 Reserved :30; ///> must be 0 +} STM_FEAT; + +#define STM_SPEC_VERSION_MAJOR 1 +#define STM_SPEC_VERSION_MINOR 0 + +typedef struct { + UINT8 StmSpecVerMajor; + UINT8 StmSpecVerMinor; + /// + /// Must be zero + /// + UINT16 Reserved; + UINT32 StaticImageSize; + UINT32 PerProcDynamicMemorySize; + UINT32 AdditionalDynamicMemorySize; + STM_FEAT StmFeatures; + UINT32 NumberOfRevIDs; + UINT32 StmSmmRevID[1]; + /// + /// The total STM_HEADER should be 4K. + /// +} SOFTWARE_STM_HEADER; + +typedef struct { + MSEG_HEADER HwStmHdr; + SOFTWARE_STM_HEADER SwStmHdr; +} STM_HEADER; + + +/** + VMCALL API Numbers + API number convention: BIOS facing VMCALL interfaces have bit 16 clear +**/ + +/** + StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to + physical mapping of an address range into the SMM guest's virtual + memory space. + + @param EAX #STM_API_MAP_ADDRESS_RANGE (0x00000001) + @param EBX Low 32 bits of physical address of caller allocated + STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. + @param ECX High 32 bits of physical address of caller allocated + STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is + clear (0), ECX must be 0. + + @note All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They + are not modified by StmMapAddressRange. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. + The memory range was mapped as requested. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_SECURITY_VIOLATION + The requested mapping contains a protected resource. + @retval EAX #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED + The requested cache type could not be satisfied. + @retval EAX #ERROR_STM_PAGE_NOT_FOUND + Page count must not be zero. + @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED + STM supports EPT and has not implemented StmMapAddressRange(). + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_MAP_ADDRESS_RANGE 0x00000001 + +/** + STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL +**/ +typedef struct { + UINT64 PhysicalAddress; + UINT64 VirtualAddress; + UINT32 PageCount; + UINT32 PatCacheType; +} STM_MAP_ADDRESS_RANGE_DESCRIPTOR; + +/** + Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR + @{ +**/ +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC 0x00 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC 0x01 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT 0x04 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP 0x05 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB 0x06 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC 0x07 +#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR 0xFFFFFFFF +/// @} + +/** + StmUnmapAddressRange enables a SMM guest to remove mappings from its page + table. + + If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can + control its own page tables. In this case, the STM implementation may + optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED. + + @param EAX #STM_API_UNMAP_ADDRESS_RANGE (0x00000002) + @param EBX Low 32 bits of virtual address of caller allocated + STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. + @param ECX High 32 bits of virtual address of caller allocated + STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is + clear (0), ECX must be zero. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The memory range was unmapped + as requested. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_FUNCTION_NOT_SUPPORTED + STM supports EPT and has not implemented StmUnmapAddressRange(). + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002 + +/** + STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL +**/ +typedef struct { + UINT64 VirtualAddress; + UINT32 Length; +} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR; + + +/** + Since the normal OS environment runs with a different set of page tables than + the SMM guest, virtual mappings will certainly be different. In order to do a + guest virtual to host physical translation of an address from the normal OS + code (EIP for example), it is necessary to walk the page tables governing the + OS page mappings. Since the SMM guest has no direct access to the page tables, + it must ask the STM to do this page table walk. This is supported via the + StmAddressLookup VMCALL. All OS page table formats need to be supported, + (e.g. PAE, PSE, Intel64, EPT, etc.) + + StmAddressLookup takes a CR3 value and a virtual address from the interrupted + code as input and returns the corresponding physical address. It also + optionally maps the physical address into the SMM guest's virtual address + space. This new mapping persists ONLY for the duration of the SMI and if + needed in subsequent SMIs it must be remapped. PAT cache types follow the + interrupted environment's page table. + + If EPT is enabled, OS CR3 only provides guest physical address information, + but the SMM guest might also need to know the host physical address. Since + SMM does not have direct access rights to EPT (it is protected by the STM), + SMM can input InterruptedEptp to let STM help to walk through it, and output + the host physical address. + + @param EAX #STM_API_ADDRESS_LOOKUP (0x00000003) + @param EBX Low 32 bits of virtual address of caller allocated + STM_ADDRESS_LOOKUP_DESCRIPTOR structure. + @param ECX High 32 bits of virtual address of caller allocated + STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is + clear (0), ECX must be zero. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. PhysicalAddress contains the + host physical address determined by walking the interrupted SMM + guest's page tables. SmmGuestVirtualAddress contains the SMM + guest's virtual mapping of the requested address. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_SECURITY_VIOLATION + The requested page was a protected page. + @retval EAX #ERROR_STM_PAGE_NOT_FOUND + The requested virtual address did not exist in the page given + page table. + @retval EAX #ERROR_STM_BAD_CR3 + The CR3 input was invalid. CR3 values must be from one of the + interrupted guest, or from the interrupted guest of another + processor. + @retval EAX #ERROR_STM_PHYSICAL_OVER_4G + The resulting physical address is greater than 4G and no virtual + address was supplied. The STM could not determine what address + within the SMM guest's virtual address space to do the mapping. + STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the + physical address determined by walking the interrupted + environment's page tables. + @retval EAX #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL + A specific virtual mapping was requested, but + SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler + is running in 32 bit mode. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_ADDRESS_LOOKUP 0x00000003 + +/** + STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL +**/ +typedef struct { + UINT64 InterruptedGuestVirtualAddress; + UINT32 Length; + UINT64 InterruptedCr3; + UINT64 InterruptedEptp; + UINT32 MapToSmmGuest:2; + UINT32 InterruptedCr4Pae:1; + UINT32 InterruptedCr4Pse:1; + UINT32 InterruptedIa32eMode:1; + UINT32 Reserved1:27; + UINT32 Reserved2; + UINT64 PhysicalAddress; + UINT64 SmmGuestVirtualAddress; +} STM_ADDRESS_LOOKUP_DESCRIPTOR; + +/** + Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR + @{ +**/ +#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP 0 +#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE 1 +#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3 +/// @} + + +/** + When returning from a protection exception (see section 6.2), the SMM guest + can instruct the STM to take one of two paths. It can either request a value + be logged to the TXT.ERRORCODE register and subsequently reset the machine + (indicating it couldn't resolve the problem), or it can request that the STM + resume the SMM guest again with the specified register state. + + Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more + like a jump or an IRET instruction than a "call". It does not return directly + to the caller, but indirectly to a different location specified on the + caller's stack (see section 6.2) or not at all. + + If the SMM guest STM protection exception handler itself causes a protection + exception (e.g. a single nested exception), or more than 100 un-nested + exceptions occur within the scope of a single SMI event, the STM must write + STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and + assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify + the code requirements while still enabling a reasonable debugging capability. + + @param EAX #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004) + @param EBX If 0, resume SMM guest using register state found on exception + stack. If in range 0x01..0x0F, EBX contains a BIOS error code + which the STM must record in the TXT.ERRORCODE register and + subsequently reset the system via TXT.CMD.SYS_RESET. The value + of the TXT.ERRORCODE register is calculated as follows: + + TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC + + Values 0x10..0xFFFFFFFF are reserved, do not use. + +**/ +#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004 + + +/** + VMCALL API Numbers + API number convention: MLE facing VMCALL interfaces have bit 16 set. + + The STM configuration lifecycle is as follows: + 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked). + 2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for + setup of initial protection profile. This is done on a single CPU and + has global effect. + 3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial + protection profile. The protection profile is global across all CPUs. + 4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving + SMI events. This must be done on every logical CPU. + 5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or + #STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as + necessary. + 6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked + following #STM_API_STOP VMCALL. +**/ + +/** + StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs + should remain disabled from the invocation of GETSEC[SENTER] until they are + re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is + enabled and the STM has been started and is active. Prior to invoking + StartStmVMCALL(), the MLE root should first invoke + InitializeProtectionVMCALL() followed by as many iterations of + ProtectResourceVMCALL() as necessary to establish the initial protection + profile. StartStmVmcall() must be invoked on all processor threads. + + @param EAX #STM_API_START (0x00010001) + @param EDX STM configuration options. These provide the MLE with the + ability to pass configuration parameters to the STM. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The STM has been configured + and is now active and the guarding all requested resources. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_ALREADY_STARTED + The STM is already configured and active. STM remains active and + guarding previously enabled resource list. + @retval EAX #ERROR_STM_WITHOUT_SMX_UNSUPPORTED + The StartStmVMCALL() was invoked from VMX root mode, but outside + of SMX. This error code indicates the STM or platform does not + support the STM outside of SMX. The SMI handler remains active + and operates in legacy mode. See Appendix C + @retval EAX #ERROR_STM_UNSUPPORTED_MSR_BIT + The CPU doesn't support the MSR bit. The STM is not active. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_START (BIT16 | 1) + +/** + Bit values for EDX input parameter to #STM_API_START VMCALL + @{ +**/ +#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0 +/// @} + + +/** + The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is + normally done as part of a full teardown of the SMX environment when the + system is being shut down. At the time the call is invoked, SMI is enabled + and the STM is active. When the call returns, the STM has been stopped and + all STM context is discarded and SMI is disabled. + + @param EAX #STM_API_STOP (0x00010002) + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The STM has been stopped and + is no longer processing SMI events. SMI is blocked. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_STOPPED + The STM was not active. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_STOP (BIT16 | 2) + + +/** + The ProtectResourceVMCALL() is invoked by the MLE root to request protection + of specific resources. The request is defined by a STM_RESOURCE_LIST, which + may contain more than one resource descriptor. Each resource descriptor is + processed separately by the STM. Whether or not protection for any specific + resource is granted is returned by the STM via the ReturnStatus bit in the + associated STM_RSC_DESC_HEADER. + + @param EAX #STM_API_PROTECT_RESOURCE (0x00010003) + @param EBX Low 32 bits of physical address of caller allocated + STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero, + making the buffer 4K aligned. + @param ECX High 32 bits of physical address of caller allocated + STM_RESOURCE_LIST. + + @note All fields of STM_RESOURCE_LIST are inputs only, except for the + ReturnStatus bit. On input, the ReturnStatus bit must be clear. On + return, the ReturnStatus bit is set for each resource request granted, + and clear for each resource request denied. There are no other fields + modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be + contained entirely within a single 4K page. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The STM has successfully + merged the entire protection request into the active protection + profile. There is therefore no need to check the ReturnStatus + bits in the STM_RESOURCE_LIST. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_UNPROTECTABLE_RESOURCE + At least one of the requested resource protections intersects a + BIOS required resource. Therefore, the caller must walk through + the STM_RESOURCE_LIST to determine which of the requested + resources was not granted protection. The entire list must be + traversed since there may be multiple failures. + @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST + The resource list could not be parsed correctly, or did not + terminate before crossing a 4K page boundary. The caller must + walk through the STM_RESOURCE_LIST to determine which of the + requested resources was not granted protection. The entire list + must be traversed since there may be multiple failures. + @retval EAX #ERROR_STM_OUT_OF_RESOURCES + The STM has encountered an internal error and cannot complete + the request. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_PROTECT_RESOURCE (BIT16 | 3) + + +/** + The UnProtectResourceVMCALL() is invoked by the MLE root to request that the + STM allow the SMI handler access to the specified resources. + + @param EAX #STM_API_UNPROTECT_RESOURCE (0x00010004) + @param EBX Low 32 bits of physical address of caller allocated + STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero, + making the buffer 4K aligned. + @param ECX High 32 bits of physical address of caller allocated + STM_RESOURCE_LIST. + + @note All fields of STM_RESOURCE_LIST are inputs only, except for the + ReturnStatus bit. On input, the ReturnStatus bit must be clear. On + return, the ReturnStatus bit is set for each resource processed. For + a properly formed STM_RESOURCE_LIST, this should be all resources + listed. There are no other fields modified by + UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained + entirely within a single 4K page. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The requested resources are + not being guarded by the STM. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_MALFORMED_RESOURCE_LIST + The resource list could not be parsed correctly, or did not + terminate before crossing a 4K page boundary. The caller must + walk through the STM_RESOURCE_LIST to determine which of the + requested resources were not able to be unprotected. The entire + list must be traversed since there may be multiple failures. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4) + + +/** + The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list + of BIOS required resources from the STM. + + @param EAX #STM_API_GET_BIOS_RESOURCES (0x00010005) + @param EBX Low 32 bits of physical address of caller allocated destination + buffer. Bits 11:0 are ignored and assumed to be zero, making the + buffer 4K aligned. + @param ECX High 32 bits of physical address of caller allocated destination + buffer. + @param EDX Indicates which page of the BIOS resource list to copy into the + destination buffer. The first page is indicated by 0, the second + page by 1, etc. + + @retval CF 0 + No error, EAX set to STM_SUCCESS. The destination buffer + contains the BIOS required resources. If the page retrieved is + the last page, EDX will be cleared to 0. If there are more pages + to retrieve, EDX is incremented to the next page index. Calling + software should iterate on GetBiosResourcesVMCALL() until EDX is + returned cleared to 0. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_PAGE_NOT_FOUND + The page index supplied in EDX input was out of range. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + @retval EDX Page index of next page to read. A return of EDX=0 signifies + that the entire list has been read. + @note EDX is both an input and an output register. + + @note All other registers unmodified. +**/ +#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5) + + +/** + The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an + MLE guest (including the MLE root) from the list of protected domains. + + @param EAX #STM_API_MANAGE_VMCS_DATABASE (0x00010006) + @param EBX Low 32 bits of physical address of caller allocated + STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to + be zero, making the buffer 4K aligned. + @param ECX High 32 bits of physical address of caller allocated + STM_VMCS_DATABASE_REQUEST. + + @note All fields of STM_VMCS_DATABASE_REQUEST are inputs only. They are not + modified by ManageVmcsDatabaseVMCALL(). + + @retval CF 0 + No error, EAX set to STM_SUCCESS. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_INVALID_VMCS + Indicates a request to remove a VMCS from the database was made, + but the referenced VMCS was not found in the database. + @retval EAX #ERROR_STM_VMCS_PRESENT + Indicates a request to add a VMCS to the database was made, but + the referenced VMCS was already present in the database. + @retval EAX #ERROR_INVALID_PARAMETER + Indicates non-zero reserved field. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred + + @note All other registers unmodified. +**/ +#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6) + +/** + STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL +**/ +typedef struct { + /// + /// bits 11:0 are reserved and must be 0 + /// + UINT64 VmcsPhysPointer; + UINT32 DomainType :4; + UINT32 XStatePolicy :2; + UINT32 DegradationPolicy :4; + /// + /// Must be 0 + /// + UINT32 Reserved1 :22; + UINT32 AddOrRemove; +} STM_VMCS_DATABASE_REQUEST; + +/** + Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST + @{ +**/ +#define DOMAIN_UNPROTECTED 0 +#define DOMAIN_DISALLOWED_IO_OUT BIT0 +#define DOMAIN_DISALLOWED_IO_IN BIT1 +#define DOMAIN_INTEGRITY BIT2 +#define DOMAIN_CONFIDENTIALITY BIT3 +#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY) +#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY) +#define DOMAIN_FULLY_PROT (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT) +/// @} + +/** + Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST + @{ +**/ +#define XSTATE_READWRITE 0x00 +#define XSTATE_READONLY 0x01 +#define XSTATE_SCRUB 0x03 +/// @} + +/** + Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST + @{ +**/ +#define STM_VMCS_DATABASE_REQUEST_ADD 1 +#define STM_VMCS_DATABASE_REQUEST_REMOVE 0 +/// @} + + +/** + InitializeProtectionVMCALL() prepares the STM for setup of the initial + protection profile which is subsequently communicated via one or more + invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL(). + It is only necessary to invoke InitializeProtectionVMCALL() on one processor + thread. InitializeProtectionVMCALL() does not alter whether SMIs are masked + or unmasked. The STM should return back to the MLE with "Blocking by SMI" set + to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the + MLE guest. + + @param EAX #STM_API_INITIALIZE_PROTECTION (0x00010007) + + @retval CF 0 + No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM + capabilities as defined below. The STM has set up an empty + protection profile, except for the resources that it sets up to + protect itself. The STM must not allow the SMI handler to map + any pages from the MSEG Base to the top of TSEG. The STM must + also not allow SMI handler access to those MSRs which the STM + requires for its own protection. + @retval CF 1 + An error occurred, EAX holds relevant error value. + @retval EAX #ERROR_STM_ALREADY_STARTED + The STM is already configured and active. The STM remains active + and guarding the previously enabled resource list. + @retval EAX #ERROR_STM_UNPROTECTABLE + The STM determines that based on the platform configuration, the + STM is unable to protect itself. For example, the BIOS required + resource list contains memory pages in MSEG. + @retval EAX #ERROR_STM_UNSPECIFIED + An unspecified error occurred. + + @note All other registers unmodified. +**/ +#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7) + +/** + Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION + @{ +**/ +#define STM_RSC_BGI BIT1 +#define STM_RSC_BGM BIT2 +#define STM_RSC_MSR BIT3 +/// @} + + +/** + The ManageEventLogVMCALL() is invoked by the MLE root to control the logging + feature. It consists of several sub-functions to facilitate establishment of + the log itself, configuring what events will be logged, and functions to + start, stop, and clear the log. + + @param EAX #STM_API_MANAGE_EVENT_LOG (0x00010008) + @param EBX Low 32 bits of physical address of caller allocated + STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and + assumed to be zero, making the buffer 4K aligned. + @param ECX High 32 bits of physical address of caller allocated + STM_EVENT_LOG_MANAGEMENT_REQUEST. + + @retval CF=0 + No error, EAX set to STM_SUCCESS. + @retval CF=1 + An error occurred, EAX holds relevant error value. See subfunction + descriptions below for details. + + @note All other registers unmodified. +**/ +#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8) + +/// +/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL +/// +typedef struct { + UINT32 SubFunctionIndex; + union { + struct { + UINT32 PageCount; + // + // number of elements is PageCount + // + UINT64 Pages[]; + } LogBuffer; + // + // bitmap of EVENT_TYPE + // + UINT32 EventEnableBitmap; + } Data; +} STM_EVENT_LOG_MANAGEMENT_REQUEST; + +/** + Defines values for the SubFunctionIndex field of + #STM_EVENT_LOG_MANAGEMENT_REQUEST + @{ +**/ +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG 1 +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG 2 +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG 3 +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG 4 +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG 5 +#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG 6 +/// @} + +/** + Log Entry Header +**/ +typedef struct { + UINT32 EventSerialNumber; + UINT16 Type; + UINT16 Lock :1; + UINT16 Valid :1; + UINT16 ReadByMle :1; + UINT16 Wrapped :1; + UINT16 Reserved :12; +} LOG_ENTRY_HEADER; + +/** + Enum values for the Type field of #LOG_ENTRY_HEADER +**/ +typedef enum { + EvtLogStarted, + EvtLogStopped, + EvtLogInvalidParameterDetected, + EvtHandledProtectionException, + /// + /// unhandled protection exceptions result in reset & cannot be logged + /// + EvtBiosAccessToUnclaimedResource, + EvtMleResourceProtectionGranted, + EvtMleResourceProtectionDenied, + EvtMleResourceUnprotect, + EvtMleResourceUnprotectError, + EvtMleDomainTypeDegraded, + /// + /// add more here + /// + EvtMleMax, + /// + /// Not used + /// + EvtInvalid = 0xFFFFFFFF, +} EVENT_TYPE; + +typedef struct { + UINT32 Reserved; +} ENTRY_EVT_LOG_STARTED; + +typedef struct { + UINT32 Reserved; +} ENTRY_EVT_LOG_STOPPED; + +typedef struct { + UINT32 VmcallApiNumber; +} ENTRY_EVT_LOG_INVALID_PARAM; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_GRANTED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_DENIED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT_ERROR; + +typedef struct { + UINT64 VmcsPhysPointer; + UINT8 ExpectedDomainType; + UINT8 DegradedDomainType; +} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED; + +typedef union { + ENTRY_EVT_LOG_STARTED Started; + ENTRY_EVT_LOG_STOPPED Stopped; + ENTRY_EVT_LOG_INVALID_PARAM InvalidParam; + ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException; + ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc; + ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted; + ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied; + ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot; + ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError; + ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded; +} LOG_ENTRY_DATA; + +typedef struct { + LOG_ENTRY_HEADER Hdr; + LOG_ENTRY_DATA Data; +} STM_LOG_ENTRY; + +/** + Maximum STM Log Entry Size +**/ +#define STM_LOG_ENTRY_SIZE 256 + + +/** + STM Protection Exception Stack Frame Structures +**/ + +typedef struct { + UINT32 Rdi; + UINT32 Rsi; + UINT32 Rbp; + UINT32 Rdx; + UINT32 Rcx; + UINT32 Rbx; + UINT32 Rax; + UINT32 Cr3; + UINT32 Cr2; + UINT32 Cr0; + UINT32 VmcsExitInstructionInfo; + UINT32 VmcsExitInstructionLength; + UINT64 VmcsExitQualification; + /// + /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value + /// + UINT32 ErrorCode; + UINT32 Rip; + UINT32 Cs; + UINT32 Rflags; + UINT32 Rsp; + UINT32 Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32; + +typedef struct { + UINT64 R15; + UINT64 R14; + UINT64 R13; + UINT64 R12; + UINT64 R11; + UINT64 R10; + UINT64 R9; + UINT64 R8; + UINT64 Rdi; + UINT64 Rsi; + UINT64 Rbp; + UINT64 Rdx; + UINT64 Rcx; + UINT64 Rbx; + UINT64 Rax; + UINT64 Cr8; + UINT64 Cr3; + UINT64 Cr2; + UINT64 Cr0; + UINT64 VmcsExitInstructionInfo; + UINT64 VmcsExitInstructionLength; + UINT64 VmcsExitQualification; + /// + /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value + /// + UINT64 ErrorCode; + UINT64 Rip; + UINT64 Cs; + UINT64 Rflags; + UINT64 Rsp; + UINT64 Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64; + +typedef union { + STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame; + STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame; +} STM_PROTECTION_EXCEPTION_STACK_FRAME; + +/** + Enum values for the ErrorCode field in + #STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and + #STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 +**/ +typedef enum { + TxtSmmPageViolation = 1, + TxtSmmMsrViolation, + TxtSmmRegisterViolation, + TxtSmmIoViolation, + TxtSmmPciViolation +} TXT_SMM_PROTECTION_EXCEPTION_TYPE; + +/** + TXT Pocessor SMM Descriptor (PSD) structures +**/ + +typedef struct { + UINT64 SpeRip; + UINT64 SpeRsp; + UINT16 SpeSs; + UINT16 PageViolationException:1; + UINT16 MsrViolationException:1; + UINT16 RegisterViolationException:1; + UINT16 IoViolationException:1; + UINT16 PciViolationException:1; + UINT16 Reserved1:11; + UINT32 Reserved2; +} STM_PROTECTION_EXCEPTION_HANDLER; + +typedef struct { + UINT8 ExecutionDisableOutsideSmrr:1; + UINT8 Intel64Mode:1; + UINT8 Cr4Pae : 1; + UINT8 Cr4Pse : 1; + UINT8 Reserved1 : 4; +} STM_SMM_ENTRY_STATE; + +typedef struct { + UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint + UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request + UINT8 Reserved2 : 6; +} STM_SMM_RESUME_STATE; + +typedef struct { + UINT8 DomainType : 4; ///> STM input to BIOS on each SMI + UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI + UINT8 EptEnabled : 1; + UINT8 Reserved3 : 1; +} STM_SMM_STATE; + +#define TXT_SMM_PSD_OFFSET 0xfb00 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G') +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0 + +typedef struct { + UINT64 Signature; + UINT16 Size; + UINT8 SmmDescriptorVerMajor; + UINT8 SmmDescriptorVerMinor; + UINT32 LocalApicId; + STM_SMM_ENTRY_STATE SmmEntryState; + STM_SMM_RESUME_STATE SmmResumeState; + STM_SMM_STATE StmSmmState; + UINT8 Reserved4; + UINT16 SmmCs; + UINT16 SmmDs; + UINT16 SmmSs; + UINT16 SmmOtherSegment; + UINT16 SmmTr; + UINT16 Reserved5; + UINT64 SmmCr3; + UINT64 SmmStmSetupRip; + UINT64 SmmStmTeardownRip; + UINT64 SmmSmiHandlerRip; + UINT64 SmmSmiHandlerRsp; + UINT64 SmmGdtPtr; + UINT32 SmmGdtSize; + UINT32 RequiredStmSmmRevId; + STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler; + UINT64 Reserved6; + UINT64 BiosHwResourceRequirementsPtr; + // extend area + UINT64 AcpiRsdp; + UINT8 PhysicalAddressBits; +} TXT_PROCESSOR_SMM_DESCRIPTOR; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmResourceDescriptor.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmResourceDescriptor.h new file mode 100644 index 0000000000..3f9e2b8aac --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmResourceDescriptor.h @@ -0,0 +1,222 @@ +/** @file + STM Resource Descriptor + + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SMI Transfer Monitor (STM) User Guide Revision 1.00 + +**/ + +#ifndef _INTEL_STM_RESOURCE_DESCRIPTOR_H_ +#define _INTEL_STM_RESOURCE_DESCRIPTOR_H_ + +#pragma pack (1) + +/** + STM Resource Descriptor Header +**/ +typedef struct { + UINT32 RscType; + UINT16 Length; + UINT16 ReturnStatus:1; + UINT16 Reserved:14; + UINT16 IgnoreResource:1; +} STM_RSC_DESC_HEADER; + +/** + Define values for the RscType field of #STM_RSC_DESC_HEADER + @{ +**/ +#define END_OF_RESOURCES 0 +#define MEM_RANGE 1 +#define IO_RANGE 2 +#define MMIO_RANGE 3 +#define MACHINE_SPECIFIC_REG 4 +#define PCI_CFG_RANGE 5 +#define TRAPPED_IO_RANGE 6 +#define ALL_RESOURCES 7 +#define REGISTER_VIOLATION 8 +#define MAX_DESC_TYPE 8 +/// @} + +/** + STM Resource End Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT64 ResourceListContinuation; +} STM_RSC_END; + +/** + STM Resource Memory Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT64 Base; + UINT64 Length; + UINT32 RWXAttributes:3; + UINT32 Reserved:29; + UINT32 Reserved_2; +} STM_RSC_MEM_DESC; + +/** + Define values for the RWXAttributes field of #STM_RSC_MEM_DESC + @{ +**/ +#define STM_RSC_MEM_R 0x1 +#define STM_RSC_MEM_W 0x2 +#define STM_RSC_MEM_X 0x4 +/// @} + +/** + STM Resource I/O Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT16 Base; + UINT16 Length; + UINT32 Reserved; +} STM_RSC_IO_DESC; + +/** + STM Resource MMIO Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT64 Base; + UINT64 Length; + UINT32 RWXAttributes:3; + UINT32 Reserved:29; + UINT32 Reserved_2; +} STM_RSC_MMIO_DESC; + +/** + Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC + @{ +**/ +#define STM_RSC_MMIO_R 0x1 +#define STM_RSC_MMIO_W 0x2 +#define STM_RSC_MMIO_X 0x4 +/// @} + +/** + STM Resource MSR Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT32 MsrIndex; + UINT32 KernelModeProcessing:1; + UINT32 Reserved:31; + UINT64 ReadMask; + UINT64 WriteMask; +} STM_RSC_MSR_DESC; + +/** + STM PCI Device Path node used for the PciDevicePath field of + #STM_RSC_PCI_CFG_DESC +**/ +typedef struct { + /// + /// Must be 1, indicating Hardware Device Path + /// + UINT8 Type; + /// + /// Must be 1, indicating PCI + /// + UINT8 Subtype; + /// + /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6 + /// + UINT16 Length; + UINT8 PciFunction; + UINT8 PciDevice; +} STM_PCI_DEVICE_PATH_NODE; + +/** + STM Resource PCI Configuration Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT16 RWAttributes:2; + UINT16 Reserved:14; + UINT16 Base; + UINT16 Length; + UINT8 OriginatingBusNumber; + UINT8 LastNodeIndex; + STM_PCI_DEVICE_PATH_NODE PciDevicePath[1]; +//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1]; +} STM_RSC_PCI_CFG_DESC; + +/** + Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC + @{ +**/ +#define STM_RSC_PCI_CFG_R 0x1 +#define STM_RSC_PCI_CFG_W 0x2 +/// @} + +/** + STM Resource Trapped I/O Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT16 Base; + UINT16 Length; + UINT16 In:1; + UINT16 Out:1; + UINT16 Api:1; + UINT16 Reserved1:13; + UINT16 Reserved2; +} STM_RSC_TRAPPED_IO_DESC; + +/** + STM Resource All Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; +} STM_RSC_ALL_RESOURCES_DESC; + +/** + STM Register Violation Descriptor +**/ +typedef struct { + STM_RSC_DESC_HEADER Hdr; + UINT32 RegisterType; + UINT32 Reserved; + UINT64 ReadMask; + UINT64 WriteMask; +} STM_REGISTER_VIOLATION_DESC; + +/** + Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC +**/ +typedef enum { + StmRegisterCr0, + StmRegisterCr2, + StmRegisterCr3, + StmRegisterCr4, + StmRegisterCr8, + StmRegisterMax, +} STM_REGISTER_VIOLATION_TYPE; + +/** + Union of all STM resource types +**/ +typedef union { + STM_RSC_DESC_HEADER Header; + STM_RSC_END End; + STM_RSC_MEM_DESC Mem; + STM_RSC_IO_DESC Io; + STM_RSC_MMIO_DESC Mmio; + STM_RSC_MSR_DESC Msr; + STM_RSC_PCI_CFG_DESC PciCfg; + STM_RSC_TRAPPED_IO_DESC TrappedIo; + STM_RSC_ALL_RESOURCES_DESC All; + STM_REGISTER_VIOLATION_DESC RegisterViolation; +} STM_RSC; + +#pragma pack () + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmStatusCode.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmStatusCode.h new file mode 100644 index 0000000000..7bac69dbcd --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Register/Intel/StmStatusCode.h @@ -0,0 +1,72 @@ +/** @file + STM Status Codes + + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SMI Transfer Monitor (STM) User Guide Revision 1.00 + +**/ + +#ifndef _INTEL_STM_STATUS_CODE_H_ +#define _INTEL_STM_STATUS_CODE_H_ + +/** + STM Status Codes +**/ +typedef UINT32 STM_STATUS; + +/** + Success code have BIT31 clear. + All error codes have BIT31 set. + STM errors have BIT16 set. + SMM errors have BIT17 set + Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set. + STM TXT.ERRORCODE codes have BIT30 set. + @{ +**/ +#define STM_SUCCESS 0x00000000 +#define SMM_SUCCESS 0x00000000 +#define ERROR_STM_SECURITY_VIOLATION (BIT31 | BIT16 | 0x0001) +#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED (BIT31 | BIT16 | 0x0002) +#define ERROR_STM_PAGE_NOT_FOUND (BIT31 | BIT16 | 0x0003) +#define ERROR_STM_BAD_CR3 (BIT31 | BIT16 | 0x0004) +#define ERROR_STM_PHYSICAL_OVER_4G (BIT31 | BIT16 | 0x0005) +#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL (BIT31 | BIT16 | 0x0006) +#define ERROR_STM_UNPROTECTABLE_RESOURCE (BIT31 | BIT16 | 0x0007) +#define ERROR_STM_ALREADY_STARTED (BIT31 | BIT16 | 0x0008) +#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED (BIT31 | BIT16 | 0x0009) +#define ERROR_STM_STOPPED (BIT31 | BIT16 | 0x000A) +#define ERROR_STM_BUFFER_TOO_SMALL (BIT31 | BIT16 | 0x000B) +#define ERROR_STM_INVALID_VMCS_DATABASE (BIT31 | BIT16 | 0x000C) +#define ERROR_STM_MALFORMED_RESOURCE_LIST (BIT31 | BIT16 | 0x000D) +#define ERROR_STM_INVALID_PAGECOUNT (BIT31 | BIT16 | 0x000E) +#define ERROR_STM_LOG_ALLOCATED (BIT31 | BIT16 | 0x000F) +#define ERROR_STM_LOG_NOT_ALLOCATED (BIT31 | BIT16 | 0x0010) +#define ERROR_STM_LOG_NOT_STOPPED (BIT31 | BIT16 | 0x0011) +#define ERROR_STM_LOG_NOT_STARTED (BIT31 | BIT16 | 0x0012) +#define ERROR_STM_RESERVED_BIT_SET (BIT31 | BIT16 | 0x0013) +#define ERROR_STM_NO_EVENTS_ENABLED (BIT31 | BIT16 | 0x0014) +#define ERROR_STM_OUT_OF_RESOURCES (BIT31 | BIT16 | 0x0015) +#define ERROR_STM_FUNCTION_NOT_SUPPORTED (BIT31 | BIT16 | 0x0016) +#define ERROR_STM_UNPROTECTABLE (BIT31 | BIT16 | 0x0017) +#define ERROR_STM_UNSUPPORTED_MSR_BIT (BIT31 | BIT16 | 0x0018) +#define ERROR_STM_UNSPECIFIED (BIT31 | BIT16 | 0xFFFF) +#define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001) +#define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004) +#define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005) +#define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006) +#define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007) +#define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008) +#define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009) +#define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF) +#define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001) +#define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002) +#define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001) +#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002) +#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003) +#define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000) +/// @} + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/RiscV64/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/RiscV64/ProcessorBind.h new file mode 100644 index 0000000000..84fce5ce38 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PROCESSOR_BIND_H__ +#define PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +/// +/// 8-byte unsigned value +/// +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); +/// +/// 8-byte signed value +/// +typedef long long INT64 __attribute__ ((aligned (8))); +/// +/// 4-byte unsigned value +/// +typedef unsigned int UINT32 __attribute__ ((aligned (4))); +/// +/// 4-byte signed value +/// +typedef int INT32 __attribute__ ((aligned (4))); +/// +/// 2-byte unsigned value +/// +typedef unsigned short UINT16 __attribute__ ((aligned (2))); +/// +/// 2-byte Character. Unless otherwise specified all strings are stored in the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. +/// +typedef unsigned short CHAR16 __attribute__ ((aligned (2))); +/// +/// 2-byte signed value +/// +typedef short INT16 __attribute__ ((aligned (2))); +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN __attribute__ ((aligned (8))); +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN __attribute__ ((aligned (8))); + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal RV64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization level + /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for + /// x64. Warning the assembly code in the MDE x64 does not follow the correct + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi.h new file mode 100644 index 0000000000..dd0ece6103 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi.h @@ -0,0 +1,21 @@ +/** @file + + Root include file for Mde Package UEFI, UEFI_APPLICATION type modules. + + This is the include file for any module of type UEFI and UEFI_APPLICATION. Uefi modules only use + types defined via this include file and can be ported easily to any + environment. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PI_UEFI_H__ +#define __PI_UEFI_H__ + +#include +#include + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiAcpiDataTable.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiAcpiDataTable.h new file mode 100644 index 0000000000..df0fc5561a --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiAcpiDataTable.h @@ -0,0 +1,23 @@ +/** @file + UEFI ACPI Data Table Definition. + +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_ACPI_DATA_TABLE_H__ +#define __UEFI_ACPI_DATA_TABLE_H__ + +#include + +#pragma pack(1) +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + GUID Identifier; + UINT16 DataOffset; +} EFI_ACPI_DATA_TABLE; +#pragma pack() + +#endif + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiBaseType.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiBaseType.h new file mode 100644 index 0000000000..b9183fda48 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiBaseType.h @@ -0,0 +1,311 @@ +/** @file + Defines data types and constants introduced in UEFI. + +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_BASETYPE_H__ +#define __UEFI_BASETYPE_H__ + +#include + +// +// Basic data type definitions introduced in UEFI. +// + +/// +/// 128-bit buffer containing a unique identifier value. +/// +typedef GUID EFI_GUID; +/// +/// Function return status for EFI API. +/// +typedef RETURN_STATUS EFI_STATUS; +/// +/// A collection of related interfaces. +/// +typedef VOID *EFI_HANDLE; +/// +/// Handle to an event structure. +/// +typedef VOID *EFI_EVENT; +/// +/// Task priority level. +/// +typedef UINTN EFI_TPL; +/// +/// Logical block address. +/// +typedef UINT64 EFI_LBA; + +/// +/// 64-bit physical memory address. +/// +typedef UINT64 EFI_PHYSICAL_ADDRESS; + +/// +/// 64-bit virtual memory address. +/// +typedef UINT64 EFI_VIRTUAL_ADDRESS; + +/// +/// EFI Time Abstraction: +/// Year: 1900 - 9999 +/// Month: 1 - 12 +/// Day: 1 - 31 +/// Hour: 0 - 23 +/// Minute: 0 - 59 +/// Second: 0 - 59 +/// Nanosecond: 0 - 999,999,999 +/// TimeZone: -1440 to 1440 or 2047 +/// +typedef struct { + UINT16 Year; + UINT8 Month; + UINT8 Day; + UINT8 Hour; + UINT8 Minute; + UINT8 Second; + UINT8 Pad1; + UINT32 Nanosecond; + INT16 TimeZone; + UINT8 Daylight; + UINT8 Pad2; +} EFI_TIME; + + +/// +/// 4-byte buffer. An IPv4 internet protocol address. +/// +typedef IPv4_ADDRESS EFI_IPv4_ADDRESS; + +/// +/// 16-byte buffer. An IPv6 internet protocol address. +/// +typedef IPv6_ADDRESS EFI_IPv6_ADDRESS; + +/// +/// 32-byte buffer containing a network Media Access Control address. +/// +typedef struct { + UINT8 Addr[32]; +} EFI_MAC_ADDRESS; + +/// +/// 16-byte buffer aligned on a 4-byte boundary. +/// An IPv4 or IPv6 internet protocol address. +/// +typedef union { + UINT32 Addr[4]; + EFI_IPv4_ADDRESS v4; + EFI_IPv6_ADDRESS v6; +} EFI_IP_ADDRESS; + + +/// +/// Enumeration of EFI_STATUS. +///@{ +#define EFI_SUCCESS RETURN_SUCCESS +#define EFI_LOAD_ERROR RETURN_LOAD_ERROR +#define EFI_INVALID_PARAMETER RETURN_INVALID_PARAMETER +#define EFI_UNSUPPORTED RETURN_UNSUPPORTED +#define EFI_BAD_BUFFER_SIZE RETURN_BAD_BUFFER_SIZE +#define EFI_BUFFER_TOO_SMALL RETURN_BUFFER_TOO_SMALL +#define EFI_NOT_READY RETURN_NOT_READY +#define EFI_DEVICE_ERROR RETURN_DEVICE_ERROR +#define EFI_WRITE_PROTECTED RETURN_WRITE_PROTECTED +#define EFI_OUT_OF_RESOURCES RETURN_OUT_OF_RESOURCES +#define EFI_VOLUME_CORRUPTED RETURN_VOLUME_CORRUPTED +#define EFI_VOLUME_FULL RETURN_VOLUME_FULL +#define EFI_NO_MEDIA RETURN_NO_MEDIA +#define EFI_MEDIA_CHANGED RETURN_MEDIA_CHANGED +#define EFI_NOT_FOUND RETURN_NOT_FOUND +#define EFI_ACCESS_DENIED RETURN_ACCESS_DENIED +#define EFI_NO_RESPONSE RETURN_NO_RESPONSE +#define EFI_NO_MAPPING RETURN_NO_MAPPING +#define EFI_TIMEOUT RETURN_TIMEOUT +#define EFI_NOT_STARTED RETURN_NOT_STARTED +#define EFI_ALREADY_STARTED RETURN_ALREADY_STARTED +#define EFI_ABORTED RETURN_ABORTED +#define EFI_ICMP_ERROR RETURN_ICMP_ERROR +#define EFI_TFTP_ERROR RETURN_TFTP_ERROR +#define EFI_PROTOCOL_ERROR RETURN_PROTOCOL_ERROR +#define EFI_INCOMPATIBLE_VERSION RETURN_INCOMPATIBLE_VERSION +#define EFI_SECURITY_VIOLATION RETURN_SECURITY_VIOLATION +#define EFI_CRC_ERROR RETURN_CRC_ERROR +#define EFI_END_OF_MEDIA RETURN_END_OF_MEDIA +#define EFI_END_OF_FILE RETURN_END_OF_FILE +#define EFI_INVALID_LANGUAGE RETURN_INVALID_LANGUAGE +#define EFI_COMPROMISED_DATA RETURN_COMPROMISED_DATA +#define EFI_HTTP_ERROR RETURN_HTTP_ERROR + +#define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH +#define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE +#define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE +#define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL +#define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA +#define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM +///@} + +/// +/// Define macro to encode the status code. +/// +#define EFIERR(_a) ENCODE_ERROR(_a) + +#define EFI_ERROR(A) RETURN_ERROR(A) + +/// +/// ICMP error definitions +///@{ +#define EFI_NETWORK_UNREACHABLE EFIERR(100) +#define EFI_HOST_UNREACHABLE EFIERR(101) +#define EFI_PROTOCOL_UNREACHABLE EFIERR(102) +#define EFI_PORT_UNREACHABLE EFIERR(103) +///@} + +/// +/// Tcp connection status definitions +///@{ +#define EFI_CONNECTION_FIN EFIERR(104) +#define EFI_CONNECTION_RESET EFIERR(105) +#define EFI_CONNECTION_REFUSED EFIERR(106) +///@} + +// +// The EFI memory allocation functions work in units of EFI_PAGEs that are +// 4KB. This should in no way be confused with the page size of the processor. +// An EFI_PAGE is just the quanta of memory in EFI. +// +#define EFI_PAGE_SIZE SIZE_4KB +#define EFI_PAGE_MASK 0xFFF +#define EFI_PAGE_SHIFT 12 + +/** + Macro that converts a size, in bytes, to a number of EFI_PAGESs. + + @param Size A size in bytes. This parameter is assumed to be type UINTN. + Passing in a parameter that is larger than UINTN may produce + unexpected results. + + @return The number of EFI_PAGESs associated with the number of bytes specified + by Size. + +**/ +#define EFI_SIZE_TO_PAGES(Size) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0)) + +/** + Macro that converts a number of EFI_PAGEs to a size in bytes. + + @param Pages The number of EFI_PAGES. This parameter is assumed to be + type UINTN. Passing in a parameter that is larger than + UINTN may produce unexpected results. + + @return The number of bytes associated with the number of EFI_PAGEs specified + by Pages. + +**/ +#define EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT) + +/// +/// PE32+ Machine type for IA32 UEFI images. +/// +#define EFI_IMAGE_MACHINE_IA32 0x014C + +/// +/// PE32+ Machine type for IA64 UEFI images. +/// +#define EFI_IMAGE_MACHINE_IA64 0x0200 + +/// +/// PE32+ Machine type for EBC UEFI images. +/// +#define EFI_IMAGE_MACHINE_EBC 0x0EBC + +/// +/// PE32+ Machine type for X64 UEFI images. +/// +#define EFI_IMAGE_MACHINE_X64 0x8664 + +/// +/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images. +/// +#define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2 + +/// +/// PE32+ Machine type for AARCH64 A64 images. +/// +#define EFI_IMAGE_MACHINE_AARCH64 0xAA64 + +/// +/// PE32+ Machine type for RISC-V 32/64/128 +/// +#define EFI_IMAGE_MACHINE_RISCV32 0x5032 +#define EFI_IMAGE_MACHINE_RISCV64 0x5064 +#define EFI_IMAGE_MACHINE_RISCV128 0x5128 + +#if !defined(EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined(EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE) +#if defined (MDE_CPU_IA32) + +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) == EFI_IMAGE_MACHINE_IA32) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64) + +#elif defined (MDE_CPU_X64) + +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) == EFI_IMAGE_MACHINE_X64) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32) + +#elif defined (MDE_CPU_ARM) + +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#elif defined (MDE_CPU_AARCH64) + +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) == EFI_IMAGE_MACHINE_AARCH64) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#elif defined (MDE_CPU_RISCV64) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \ + ((Machine) == EFI_IMAGE_MACHINE_RISCV64) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#elif defined (MDE_CPU_EBC) + +/// +/// This is just to make sure you can cross compile with the EBC compiler. +/// It does not make sense to have a PE loader coded in EBC. +/// +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC) + +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) + +#else +#error Unknown Processor Type +#endif +#else +#if defined (EFI_IMAGE_MACHINE_TYPE_VALUE) +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE) +#else +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE) +#endif +#if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE) +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE) +#else +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) +#endif +#endif + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiGpt.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiGpt.h new file mode 100644 index 0000000000..af0556131b --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiGpt.h @@ -0,0 +1,139 @@ +/** @file + EFI Guid Partition Table Format Definition. + +Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_GPT_H__ +#define __UEFI_GPT_H__ + +/// +/// The primary GUID Partition Table Header must be +/// located in LBA 1 (i.e., the second logical block). +/// +#define PRIMARY_PART_HEADER_LBA 1 +/// +/// EFI Partition Table Signature: "EFI PART". +/// +#define EFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T') +/// +/// Minimum bytes reserve for EFI entry array buffer. +/// +#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384 + +#pragma pack(1) + +/// +/// GPT Partition Table Header. +/// +typedef struct { + /// + /// The table header for the GPT partition Table. + /// This header contains EFI_PTAB_HEADER_ID. + /// + EFI_TABLE_HEADER Header; + /// + /// The LBA that contains this data structure. + /// + EFI_LBA MyLBA; + /// + /// LBA address of the alternate GUID Partition Table Header. + /// + EFI_LBA AlternateLBA; + /// + /// The first usable logical block that may be used + /// by a partition described by a GUID Partition Entry. + /// + EFI_LBA FirstUsableLBA; + /// + /// The last usable logical block that may be used + /// by a partition described by a GUID Partition Entry. + /// + EFI_LBA LastUsableLBA; + /// + /// GUID that can be used to uniquely identify the disk. + /// + EFI_GUID DiskGUID; + /// + /// The starting LBA of the GUID Partition Entry array. + /// + EFI_LBA PartitionEntryLBA; + /// + /// The number of Partition Entries in the GUID Partition Entry array. + /// + UINT32 NumberOfPartitionEntries; + /// + /// The size, in bytes, of each the GUID Partition + /// Entry structures in the GUID Partition Entry + /// array. This field shall be set to a value of 128 x 2^n where n is + /// an integer greater than or equal to zero (e.g., 128, 256, 512, etc.). + /// + UINT32 SizeOfPartitionEntry; + /// + /// The CRC32 of the GUID Partition Entry array. + /// Starts at PartitionEntryLBA and is + /// computed over a byte length of + /// NumberOfPartitionEntries * SizeOfPartitionEntry. + /// + UINT32 PartitionEntryArrayCRC32; +} EFI_PARTITION_TABLE_HEADER; + +/// +/// GPT Partition Entry. +/// +typedef struct { + /// + /// Unique ID that defines the purpose and type of this Partition. A value of + /// zero defines that this partition entry is not being used. + /// + EFI_GUID PartitionTypeGUID; + /// + /// GUID that is unique for every partition entry. Every partition ever + /// created will have a unique GUID. + /// This GUID must be assigned when the GUID Partition Entry is created. + /// + EFI_GUID UniquePartitionGUID; + /// + /// Starting LBA of the partition defined by this entry + /// + EFI_LBA StartingLBA; + /// + /// Ending LBA of the partition defined by this entry. + /// + EFI_LBA EndingLBA; + /// + /// Attribute bits, all bits reserved by UEFI + /// Bit 0: If this bit is set, the partition is required for the platform to function. The owner/creator of the + /// partition indicates that deletion or modification of the contents can result in loss of platform + /// features or failure for the platform to boot or operate. The system cannot function normally if + /// this partition is removed, and it should be considered part of the hardware of the system. + /// Actions such as running diagnostics, system recovery, or even OS install or boot, could + /// potentially stop working if this partition is removed. Unless OS software or firmware + /// recognizes this partition, it should never be removed or modified as the UEFI firmware or + /// platform hardware may become non-functional. + /// Bit 1: If this bit is set, then firmware must not produce an EFI_BLOCK_IO_PROTOCOL device for + /// this partition. By not producing an EFI_BLOCK_IO_PROTOCOL partition, file system + /// mappings will not be created for this partition in UEFI. + /// Bit 2: This bit is set aside to let systems with traditional PC-AT BIOS firmware implementations + /// inform certain limited, special-purpose software running on these systems that a GPT + /// partition may be bootable. The UEFI boot manager must ignore this bit when selecting + /// a UEFI-compliant application, e.g., an OS loader. + /// Bits 3-47: Undefined and must be zero. Reserved for expansion by future versions of the UEFI + /// specification. + /// Bits 48-63: Reserved for GUID specific use. The use of these bits will vary depending on the + /// PartitionTypeGUID. Only the owner of the PartitionTypeGUID is allowed + /// to modify these bits. They must be preserved if Bits 0-47 are modified.. + /// + UINT64 Attributes; + /// + /// Null-terminated name of the partition. + /// + CHAR16 PartitionName[36]; +} EFI_PARTITION_ENTRY; + +#pragma pack() +#endif + + diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h new file mode 100644 index 0000000000..0c7835c8e4 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h @@ -0,0 +1,2130 @@ +/** @file + This file defines the encoding for the VFR (Visual Form Representation) language. + IFR is primarily consumed by the EFI presentation engine, and produced by EFI + internal application and drivers as well as all add-in card option-ROM drivers + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + These definitions are from UEFI 2.1 and 2.2. + +**/ + +#ifndef __UEFI_INTERNAL_FORMREPRESENTATION_H__ +#define __UEFI_INTERNAL_FORMREPRESENTATION_H__ + +#include + +/// +/// The following types are currently defined: +/// +typedef VOID* EFI_HII_HANDLE; +typedef CHAR16* EFI_STRING; +typedef UINT16 EFI_IMAGE_ID; +typedef UINT16 EFI_QUESTION_ID; +typedef UINT16 EFI_STRING_ID; +typedef UINT16 EFI_FORM_ID; +typedef UINT16 EFI_VARSTORE_ID; +typedef UINT16 EFI_ANIMATION_ID; + +typedef UINT16 EFI_DEFAULT_ID; + +typedef UINT32 EFI_HII_FONT_STYLE; + + + +#pragma pack(1) + +// +// Definitions for Package Lists and Package Headers +// Section 27.3.1 +// + +/// +/// The header found at the start of each package list. +/// +typedef struct { + EFI_GUID PackageListGuid; + UINT32 PackageLength; +} EFI_HII_PACKAGE_LIST_HEADER; + +/// +/// The header found at the start of each package. +/// +typedef struct { + UINT32 Length:24; + UINT32 Type:8; + // UINT8 Data[...]; +} EFI_HII_PACKAGE_HEADER; + +// +// Value of HII package type +// +#define EFI_HII_PACKAGE_TYPE_ALL 0x00 +#define EFI_HII_PACKAGE_TYPE_GUID 0x01 +#define EFI_HII_PACKAGE_FORMS 0x02 +#define EFI_HII_PACKAGE_STRINGS 0x04 +#define EFI_HII_PACKAGE_FONTS 0x05 +#define EFI_HII_PACKAGE_IMAGES 0x06 +#define EFI_HII_PACKAGE_SIMPLE_FONTS 0x07 +#define EFI_HII_PACKAGE_DEVICE_PATH 0x08 +#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09 +#define EFI_HII_PACKAGE_ANIMATIONS 0x0A +#define EFI_HII_PACKAGE_END 0xDF +#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0 +#define EFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF + +// +// Definitions for Simplified Font Package +// + +/// +/// Contents of EFI_NARROW_GLYPH.Attributes. +///@{ +#define EFI_GLYPH_NON_SPACING 0x01 +#define EFI_GLYPH_WIDE 0x02 +#define EFI_GLYPH_HEIGHT 19 +#define EFI_GLYPH_WIDTH 8 +///@} + +/// +/// The EFI_NARROW_GLYPH has a preferred dimension (w x h) of 8 x 19 pixels. +/// +typedef struct { + /// + /// The Unicode representation of the glyph. The term weight is the + /// technical term for a character code. + /// + CHAR16 UnicodeWeight; + /// + /// The data element containing the glyph definitions. + /// + UINT8 Attributes; + /// + /// The column major glyph representation of the character. Bits + /// with values of one indicate that the corresponding pixel is to be + /// on when normally displayed; those with zero are off. + /// + UINT8 GlyphCol1[EFI_GLYPH_HEIGHT]; +} EFI_NARROW_GLYPH; + +/// +/// The EFI_WIDE_GLYPH has a preferred dimension (w x h) of 16 x 19 pixels, which is large enough +/// to accommodate logographic characters. +/// +typedef struct { + /// + /// The Unicode representation of the glyph. The term weight is the + /// technical term for a character code. + /// + CHAR16 UnicodeWeight; + /// + /// The data element containing the glyph definitions. + /// + UINT8 Attributes; + /// + /// The column major glyph representation of the character. Bits + /// with values of one indicate that the corresponding pixel is to be + /// on when normally displayed; those with zero are off. + /// + UINT8 GlyphCol1[EFI_GLYPH_HEIGHT]; + /// + /// The column major glyph representation of the character. Bits + /// with values of one indicate that the corresponding pixel is to be + /// on when normally displayed; those with zero are off. + /// + UINT8 GlyphCol2[EFI_GLYPH_HEIGHT]; + /// + /// Ensures that sizeof (EFI_WIDE_GLYPH) is twice the + /// sizeof (EFI_NARROW_GLYPH). The contents of Pad must + /// be zero. + /// + UINT8 Pad[3]; +} EFI_WIDE_GLYPH; + +/// +/// A simplified font package consists of a font header +/// followed by a series of glyph structures. +/// +typedef struct _EFI_HII_SIMPLE_FONT_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + UINT16 NumberOfNarrowGlyphs; + UINT16 NumberOfWideGlyphs; + // EFI_NARROW_GLYPH NarrowGlyphs[]; + // EFI_WIDE_GLYPH WideGlyphs[]; +} EFI_HII_SIMPLE_FONT_PACKAGE_HDR; + +// +// Definitions for Font Package +// Section 27.3.3 +// + +// +// Value for font style +// +#define EFI_HII_FONT_STYLE_NORMAL 0x00000000 +#define EFI_HII_FONT_STYLE_BOLD 0x00000001 +#define EFI_HII_FONT_STYLE_ITALIC 0x00000002 +#define EFI_HII_FONT_STYLE_EMBOSS 0x00010000 +#define EFI_HII_FONT_STYLE_OUTLINE 0x00020000 +#define EFI_HII_FONT_STYLE_SHADOW 0x00040000 +#define EFI_HII_FONT_STYLE_UNDERLINE 0x00080000 +#define EFI_HII_FONT_STYLE_DBL_UNDER 0x00100000 + +typedef struct _EFI_HII_GLYPH_INFO { + UINT16 Width; + UINT16 Height; + INT16 OffsetX; + INT16 OffsetY; + INT16 AdvanceX; +} EFI_HII_GLYPH_INFO; + +/// +/// The fixed header consists of a standard record header, +/// then the character values in this section, the flags +/// (including the encoding method) and the offsets of the glyph +/// information, the glyph bitmaps and the character map. +/// +typedef struct _EFI_HII_FONT_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + UINT32 HdrSize; + UINT32 GlyphBlockOffset; + EFI_HII_GLYPH_INFO Cell; + EFI_HII_FONT_STYLE FontStyle; + CHAR16 FontFamily[1]; +} EFI_HII_FONT_PACKAGE_HDR; + +// +// Value of different glyph info block types +// +#define EFI_HII_GIBT_END 0x00 +#define EFI_HII_GIBT_GLYPH 0x10 +#define EFI_HII_GIBT_GLYPHS 0x11 +#define EFI_HII_GIBT_GLYPH_DEFAULT 0x12 +#define EFI_HII_GIBT_GLYPHS_DEFAULT 0x13 +#define EFI_HII_GIBT_GLYPH_VARIABILITY 0x14 +#define EFI_HII_GIBT_DUPLICATE 0x20 +#define EFI_HII_GIBT_SKIP2 0x21 +#define EFI_HII_GIBT_SKIP1 0x22 +#define EFI_HII_GIBT_DEFAULTS 0x23 +#define EFI_HII_GIBT_EXT1 0x30 +#define EFI_HII_GIBT_EXT2 0x31 +#define EFI_HII_GIBT_EXT4 0x32 + +typedef struct _EFI_HII_GLYPH_BLOCK { + UINT8 BlockType; +} EFI_HII_GLYPH_BLOCK; + +// +// Definition of different glyph info block types +// + +typedef struct _EFI_HII_GIBT_DEFAULTS_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + EFI_HII_GLYPH_INFO Cell; +} EFI_HII_GIBT_DEFAULTS_BLOCK; + +typedef struct _EFI_HII_GIBT_DUPLICATE_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + CHAR16 CharValue; +} EFI_HII_GIBT_DUPLICATE_BLOCK; + +typedef struct _EFI_GLYPH_GIBT_END_BLOCK { + EFI_HII_GLYPH_BLOCK Header; +} EFI_GLYPH_GIBT_END_BLOCK; + +typedef struct _EFI_HII_GIBT_EXT1_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT8 BlockType2; + UINT8 Length; +} EFI_HII_GIBT_EXT1_BLOCK; + +typedef struct _EFI_HII_GIBT_EXT2_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT8 BlockType2; + UINT16 Length; +} EFI_HII_GIBT_EXT2_BLOCK; + +typedef struct _EFI_HII_GIBT_EXT4_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT8 BlockType2; + UINT32 Length; +} EFI_HII_GIBT_EXT4_BLOCK; + +typedef struct _EFI_HII_GIBT_GLYPH_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + EFI_HII_GLYPH_INFO Cell; + UINT8 BitmapData[1]; +} EFI_HII_GIBT_GLYPH_BLOCK; + +typedef struct _EFI_HII_GIBT_GLYPHS_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + EFI_HII_GLYPH_INFO Cell; + UINT16 Count; + UINT8 BitmapData[1]; +} EFI_HII_GIBT_GLYPHS_BLOCK; + +typedef struct _EFI_HII_GIBT_GLYPH_DEFAULT_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT8 BitmapData[1]; +} EFI_HII_GIBT_GLYPH_DEFAULT_BLOCK; + +typedef struct _EFI_HII_GIBT_GLYPHS_DEFAULT_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT16 Count; + UINT8 BitmapData[1]; +} EFI_HII_GIBT_GLYPHS_DEFAULT_BLOCK; + +typedef struct _EFI_HII_GIBT_VARIABILITY_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + EFI_HII_GLYPH_INFO Cell; + UINT8 GlyphPackInBits; + UINT8 BitmapData [1]; +} EFI_HII_GIBT_VARIABILITY_BLOCK; + +typedef struct _EFI_HII_GIBT_SKIP1_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT8 SkipCount; +} EFI_HII_GIBT_SKIP1_BLOCK; + +typedef struct _EFI_HII_GIBT_SKIP2_BLOCK { + EFI_HII_GLYPH_BLOCK Header; + UINT16 SkipCount; +} EFI_HII_GIBT_SKIP2_BLOCK; + +// +// Definitions for Device Path Package +// Section 27.3.4 +// + +/// +/// The device path package is used to carry a device path +/// associated with the package list. +/// +typedef struct _EFI_HII_DEVICE_PATH_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + // EFI_DEVICE_PATH_PROTOCOL DevicePath[]; +} EFI_HII_DEVICE_PATH_PACKAGE_HDR; + +// +// Definitions for GUID Package +// Section 27.3.5 +// + +/// +/// The GUID package is used to carry data where the format is defined by a GUID. +/// +typedef struct _EFI_HII_GUID_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + EFI_GUID Guid; + // Data per GUID definition may follow +} EFI_HII_GUID_PACKAGE_HDR; + +// +// Definitions for String Package +// Section 27.3.6 +// + +#define UEFI_CONFIG_LANG "x-UEFI" +#define UEFI_CONFIG_LANG_2 "x-i-UEFI" + +/// +/// The fixed header consists of a standard record header and then the string identifiers +/// contained in this section and the offsets of the string and language information. +/// +typedef struct _EFI_HII_STRING_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + UINT32 HdrSize; + UINT32 StringInfoOffset; + CHAR16 LanguageWindow[16]; + EFI_STRING_ID LanguageName; + CHAR8 Language[1]; +} EFI_HII_STRING_PACKAGE_HDR; + +typedef struct { + UINT8 BlockType; +} EFI_HII_STRING_BLOCK; + +// +// Value of different string information block types +// +#define EFI_HII_SIBT_END 0x00 +#define EFI_HII_SIBT_STRING_SCSU 0x10 +#define EFI_HII_SIBT_STRING_SCSU_FONT 0x11 +#define EFI_HII_SIBT_STRINGS_SCSU 0x12 +#define EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13 +#define EFI_HII_SIBT_STRING_UCS2 0x14 +#define EFI_HII_SIBT_STRING_UCS2_FONT 0x15 +#define EFI_HII_SIBT_STRINGS_UCS2 0x16 +#define EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17 +#define EFI_HII_SIBT_DUPLICATE 0x20 +#define EFI_HII_SIBT_SKIP2 0x21 +#define EFI_HII_SIBT_SKIP1 0x22 +#define EFI_HII_SIBT_EXT1 0x30 +#define EFI_HII_SIBT_EXT2 0x31 +#define EFI_HII_SIBT_EXT4 0x32 +#define EFI_HII_SIBT_FONT 0x40 + +// +// Definition of different string information block types +// + +typedef struct _EFI_HII_SIBT_DUPLICATE_BLOCK { + EFI_HII_STRING_BLOCK Header; + EFI_STRING_ID StringId; +} EFI_HII_SIBT_DUPLICATE_BLOCK; + +typedef struct _EFI_HII_SIBT_END_BLOCK { + EFI_HII_STRING_BLOCK Header; +} EFI_HII_SIBT_END_BLOCK; + +typedef struct _EFI_HII_SIBT_EXT1_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 BlockType2; + UINT8 Length; +} EFI_HII_SIBT_EXT1_BLOCK; + +typedef struct _EFI_HII_SIBT_EXT2_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 BlockType2; + UINT16 Length; +} EFI_HII_SIBT_EXT2_BLOCK; + +typedef struct _EFI_HII_SIBT_EXT4_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 BlockType2; + UINT32 Length; +} EFI_HII_SIBT_EXT4_BLOCK; + +typedef struct _EFI_HII_SIBT_FONT_BLOCK { + EFI_HII_SIBT_EXT2_BLOCK Header; + UINT8 FontId; + UINT16 FontSize; + EFI_HII_FONT_STYLE FontStyle; + CHAR16 FontName[1]; +} EFI_HII_SIBT_FONT_BLOCK; + +typedef struct _EFI_HII_SIBT_SKIP1_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 SkipCount; +} EFI_HII_SIBT_SKIP1_BLOCK; + +typedef struct _EFI_HII_SIBT_SKIP2_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT16 SkipCount; +} EFI_HII_SIBT_SKIP2_BLOCK; + +typedef struct _EFI_HII_SIBT_STRING_SCSU_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 StringText[1]; +} EFI_HII_SIBT_STRING_SCSU_BLOCK; + +typedef struct _EFI_HII_SIBT_STRING_SCSU_FONT_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 FontIdentifier; + UINT8 StringText[1]; +} EFI_HII_SIBT_STRING_SCSU_FONT_BLOCK; + +typedef struct _EFI_HII_SIBT_STRINGS_SCSU_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT16 StringCount; + UINT8 StringText[1]; +} EFI_HII_SIBT_STRINGS_SCSU_BLOCK; + +typedef struct _EFI_HII_SIBT_STRINGS_SCSU_FONT_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 FontIdentifier; + UINT16 StringCount; + UINT8 StringText[1]; +} EFI_HII_SIBT_STRINGS_SCSU_FONT_BLOCK; + +typedef struct _EFI_HII_SIBT_STRING_UCS2_BLOCK { + EFI_HII_STRING_BLOCK Header; + CHAR16 StringText[1]; +} EFI_HII_SIBT_STRING_UCS2_BLOCK; + +typedef struct _EFI_HII_SIBT_STRING_UCS2_FONT_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 FontIdentifier; + CHAR16 StringText[1]; +} EFI_HII_SIBT_STRING_UCS2_FONT_BLOCK; + +typedef struct _EFI_HII_SIBT_STRINGS_UCS2_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT16 StringCount; + CHAR16 StringText[1]; +} EFI_HII_SIBT_STRINGS_UCS2_BLOCK; + +typedef struct _EFI_HII_SIBT_STRINGS_UCS2_FONT_BLOCK { + EFI_HII_STRING_BLOCK Header; + UINT8 FontIdentifier; + UINT16 StringCount; + CHAR16 StringText[1]; +} EFI_HII_SIBT_STRINGS_UCS2_FONT_BLOCK; + +// +// Definitions for Image Package +// Section 27.3.7 +// + +typedef struct _EFI_HII_IMAGE_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + UINT32 ImageInfoOffset; + UINT32 PaletteInfoOffset; +} EFI_HII_IMAGE_PACKAGE_HDR; + +typedef struct _EFI_HII_IMAGE_BLOCK { + UINT8 BlockType; +} EFI_HII_IMAGE_BLOCK; + +// +// Value of different image information block types +// +#define EFI_HII_IIBT_END 0x00 +#define EFI_HII_IIBT_IMAGE_1BIT 0x10 +#define EFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11 +#define EFI_HII_IIBT_IMAGE_4BIT 0x12 +#define EFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13 +#define EFI_HII_IIBT_IMAGE_8BIT 0x14 +#define EFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15 +#define EFI_HII_IIBT_IMAGE_24BIT 0x16 +#define EFI_HII_IIBT_IMAGE_24BIT_TRANS 0x17 +#define EFI_HII_IIBT_IMAGE_JPEG 0x18 +#define EFI_HII_IIBT_IMAGE_PNG 0x19 +#define EFI_HII_IIBT_DUPLICATE 0x20 +#define EFI_HII_IIBT_SKIP2 0x21 +#define EFI_HII_IIBT_SKIP1 0x22 +#define EFI_HII_IIBT_EXT1 0x30 +#define EFI_HII_IIBT_EXT2 0x31 +#define EFI_HII_IIBT_EXT4 0x32 + +// +// Definition of different image information block types +// + +typedef struct _EFI_HII_IIBT_END_BLOCK { + EFI_HII_IMAGE_BLOCK Header; +} EFI_HII_IIBT_END_BLOCK; + +typedef struct _EFI_HII_IIBT_EXT1_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 BlockType2; + UINT8 Length; +} EFI_HII_IIBT_EXT1_BLOCK; + +typedef struct _EFI_HII_IIBT_EXT2_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 BlockType2; + UINT16 Length; +} EFI_HII_IIBT_EXT2_BLOCK; + +typedef struct _EFI_HII_IIBT_EXT4_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 BlockType2; + UINT32 Length; +} EFI_HII_IIBT_EXT4_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BASE { + UINT16 Width; + UINT16 Height; + UINT8 Data[1]; +} EFI_HII_IIBT_IMAGE_1BIT_BASE; + +typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_1BIT_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK; + +typedef struct _EFI_HII_RGB_PIXEL { + UINT8 b; + UINT8 g; + UINT8 r; +} EFI_HII_RGB_PIXEL; + +typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BASE { + UINT16 Width; + UINT16 Height; + EFI_HII_RGB_PIXEL Bitmap[1]; +} EFI_HII_IIBT_IMAGE_24BIT_BASE; + +typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_24BIT_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BASE { + UINT16 Width; + UINT16 Height; + UINT8 Data[1]; +} EFI_HII_IIBT_IMAGE_4BIT_BASE; + +typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_4BIT_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_8BIT_BASE { + UINT16 Width; + UINT16 Height; + UINT8 Data[1]; +} EFI_HII_IIBT_IMAGE_8BIT_BASE; + +typedef struct _EFI_HII_IIBT_IMAGE_8BIT_PALETTE_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_8BIT_BLOCK; + +typedef struct _EFI_HII_IIBT_IMAGE_8BIT_TRANS_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 PaletteIndex; + EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap; +} EFI_HII_IIBT_IMAGE_8BIT_TRAN_BLOCK; + +typedef struct _EFI_HII_IIBT_DUPLICATE_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + EFI_IMAGE_ID ImageId; +} EFI_HII_IIBT_DUPLICATE_BLOCK; + +typedef struct _EFI_HII_IIBT_JPEG_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT32 Size; + UINT8 Data[1]; +} EFI_HII_IIBT_JPEG_BLOCK; + +typedef struct _EFI_HII_IIBT_PNG_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT32 Size; + UINT8 Data[1]; +} EFI_HII_IIBT_PNG_BLOCK; + +typedef struct _EFI_HII_IIBT_SKIP1_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT8 SkipCount; +} EFI_HII_IIBT_SKIP1_BLOCK; + +typedef struct _EFI_HII_IIBT_SKIP2_BLOCK { + EFI_HII_IMAGE_BLOCK Header; + UINT16 SkipCount; +} EFI_HII_IIBT_SKIP2_BLOCK; + +// +// Definitions for Palette Information +// + +typedef struct _EFI_HII_IMAGE_PALETTE_INFO_HEADER { + UINT16 PaletteCount; +} EFI_HII_IMAGE_PALETTE_INFO_HEADER; + +typedef struct _EFI_HII_IMAGE_PALETTE_INFO { + UINT16 PaletteSize; + EFI_HII_RGB_PIXEL PaletteValue[1]; +} EFI_HII_IMAGE_PALETTE_INFO; + +// +// Definitions for Forms Package +// Section 27.3.8 +// + +/// +/// The Form package is used to carry form-based encoding data. +/// +typedef struct _EFI_HII_FORM_PACKAGE_HDR { + EFI_HII_PACKAGE_HEADER Header; + // EFI_IFR_OP_HEADER OpCodeHeader; + // More op-codes follow +} EFI_HII_FORM_PACKAGE_HDR; + +typedef struct { + UINT8 Hour; + UINT8 Minute; + UINT8 Second; +} EFI_HII_TIME; + +typedef struct { + UINT16 Year; + UINT8 Month; + UINT8 Day; +} EFI_HII_DATE; + +typedef struct { + EFI_QUESTION_ID QuestionId; + EFI_FORM_ID FormId; + EFI_GUID FormSetGuid; + EFI_STRING_ID DevicePath; +} EFI_HII_REF; + +typedef union { + UINT8 u8; + UINT16 u16; + UINT32 u32; + UINT64 u64; + BOOLEAN b; + EFI_HII_TIME time; + EFI_HII_DATE date; + EFI_STRING_ID string; ///< EFI_IFR_TYPE_STRING, EFI_IFR_TYPE_ACTION + EFI_HII_REF ref; ///< EFI_IFR_TYPE_REF + // UINT8 buffer[]; ///< EFI_IFR_TYPE_BUFFER +} EFI_IFR_TYPE_VALUE; + +// +// IFR Opcodes +// +#define EFI_IFR_FORM_OP 0x01 +#define EFI_IFR_SUBTITLE_OP 0x02 +#define EFI_IFR_TEXT_OP 0x03 +#define EFI_IFR_IMAGE_OP 0x04 +#define EFI_IFR_ONE_OF_OP 0x05 +#define EFI_IFR_CHECKBOX_OP 0x06 +#define EFI_IFR_NUMERIC_OP 0x07 +#define EFI_IFR_PASSWORD_OP 0x08 +#define EFI_IFR_ONE_OF_OPTION_OP 0x09 +#define EFI_IFR_SUPPRESS_IF_OP 0x0A +#define EFI_IFR_LOCKED_OP 0x0B +#define EFI_IFR_ACTION_OP 0x0C +#define EFI_IFR_RESET_BUTTON_OP 0x0D +#define EFI_IFR_FORM_SET_OP 0x0E +#define EFI_IFR_REF_OP 0x0F +#define EFI_IFR_NO_SUBMIT_IF_OP 0x10 +#define EFI_IFR_INCONSISTENT_IF_OP 0x11 +#define EFI_IFR_EQ_ID_VAL_OP 0x12 +#define EFI_IFR_EQ_ID_ID_OP 0x13 +#define EFI_IFR_EQ_ID_VAL_LIST_OP 0x14 +#define EFI_IFR_AND_OP 0x15 +#define EFI_IFR_OR_OP 0x16 +#define EFI_IFR_NOT_OP 0x17 +#define EFI_IFR_RULE_OP 0x18 +#define EFI_IFR_GRAY_OUT_IF_OP 0x19 +#define EFI_IFR_DATE_OP 0x1A +#define EFI_IFR_TIME_OP 0x1B +#define EFI_IFR_STRING_OP 0x1C +#define EFI_IFR_REFRESH_OP 0x1D +#define EFI_IFR_DISABLE_IF_OP 0x1E +#define EFI_IFR_ANIMATION_OP 0x1F +#define EFI_IFR_TO_LOWER_OP 0x20 +#define EFI_IFR_TO_UPPER_OP 0x21 +#define EFI_IFR_MAP_OP 0x22 +#define EFI_IFR_ORDERED_LIST_OP 0x23 +#define EFI_IFR_VARSTORE_OP 0x24 +#define EFI_IFR_VARSTORE_NAME_VALUE_OP 0x25 +#define EFI_IFR_VARSTORE_EFI_OP 0x26 +#define EFI_IFR_VARSTORE_DEVICE_OP 0x27 +#define EFI_IFR_VERSION_OP 0x28 +#define EFI_IFR_END_OP 0x29 +#define EFI_IFR_MATCH_OP 0x2A +#define EFI_IFR_GET_OP 0x2B +#define EFI_IFR_SET_OP 0x2C +#define EFI_IFR_READ_OP 0x2D +#define EFI_IFR_WRITE_OP 0x2E +#define EFI_IFR_EQUAL_OP 0x2F +#define EFI_IFR_NOT_EQUAL_OP 0x30 +#define EFI_IFR_GREATER_THAN_OP 0x31 +#define EFI_IFR_GREATER_EQUAL_OP 0x32 +#define EFI_IFR_LESS_THAN_OP 0x33 +#define EFI_IFR_LESS_EQUAL_OP 0x34 +#define EFI_IFR_BITWISE_AND_OP 0x35 +#define EFI_IFR_BITWISE_OR_OP 0x36 +#define EFI_IFR_BITWISE_NOT_OP 0x37 +#define EFI_IFR_SHIFT_LEFT_OP 0x38 +#define EFI_IFR_SHIFT_RIGHT_OP 0x39 +#define EFI_IFR_ADD_OP 0x3A +#define EFI_IFR_SUBTRACT_OP 0x3B +#define EFI_IFR_MULTIPLY_OP 0x3C +#define EFI_IFR_DIVIDE_OP 0x3D +#define EFI_IFR_MODULO_OP 0x3E +#define EFI_IFR_RULE_REF_OP 0x3F +#define EFI_IFR_QUESTION_REF1_OP 0x40 +#define EFI_IFR_QUESTION_REF2_OP 0x41 +#define EFI_IFR_UINT8_OP 0x42 +#define EFI_IFR_UINT16_OP 0x43 +#define EFI_IFR_UINT32_OP 0x44 +#define EFI_IFR_UINT64_OP 0x45 +#define EFI_IFR_TRUE_OP 0x46 +#define EFI_IFR_FALSE_OP 0x47 +#define EFI_IFR_TO_UINT_OP 0x48 +#define EFI_IFR_TO_STRING_OP 0x49 +#define EFI_IFR_TO_BOOLEAN_OP 0x4A +#define EFI_IFR_MID_OP 0x4B +#define EFI_IFR_FIND_OP 0x4C +#define EFI_IFR_TOKEN_OP 0x4D +#define EFI_IFR_STRING_REF1_OP 0x4E +#define EFI_IFR_STRING_REF2_OP 0x4F +#define EFI_IFR_CONDITIONAL_OP 0x50 +#define EFI_IFR_QUESTION_REF3_OP 0x51 +#define EFI_IFR_ZERO_OP 0x52 +#define EFI_IFR_ONE_OP 0x53 +#define EFI_IFR_ONES_OP 0x54 +#define EFI_IFR_UNDEFINED_OP 0x55 +#define EFI_IFR_LENGTH_OP 0x56 +#define EFI_IFR_DUP_OP 0x57 +#define EFI_IFR_THIS_OP 0x58 +#define EFI_IFR_SPAN_OP 0x59 +#define EFI_IFR_VALUE_OP 0x5A +#define EFI_IFR_DEFAULT_OP 0x5B +#define EFI_IFR_DEFAULTSTORE_OP 0x5C +#define EFI_IFR_FORM_MAP_OP 0x5D +#define EFI_IFR_CATENATE_OP 0x5E +#define EFI_IFR_GUID_OP 0x5F +#define EFI_IFR_SECURITY_OP 0x60 +#define EFI_IFR_MODAL_TAG_OP 0x61 +#define EFI_IFR_REFRESH_ID_OP 0x62 +#define EFI_IFR_WARNING_IF_OP 0x63 +#define EFI_IFR_MATCH2_OP 0x64 + +// +// Definitions of IFR Standard Headers +// Section 27.3.8.2 +// + +typedef struct _EFI_IFR_OP_HEADER { + UINT8 OpCode; + UINT8 Length:7; + UINT8 Scope:1; +} EFI_IFR_OP_HEADER; + +typedef struct _EFI_IFR_STATEMENT_HEADER { + EFI_STRING_ID Prompt; + EFI_STRING_ID Help; +} EFI_IFR_STATEMENT_HEADER; + +typedef struct _EFI_IFR_QUESTION_HEADER { + EFI_IFR_STATEMENT_HEADER Header; + EFI_QUESTION_ID QuestionId; + EFI_VARSTORE_ID VarStoreId; + union { + EFI_STRING_ID VarName; + UINT16 VarOffset; + } VarStoreInfo; + UINT8 Flags; +} EFI_IFR_QUESTION_HEADER; + +// +// Flag values of EFI_IFR_QUESTION_HEADER +// +#define EFI_IFR_FLAG_READ_ONLY 0x01 +#define EFI_IFR_FLAG_CALLBACK 0x04 +#define EFI_IFR_FLAG_RESET_REQUIRED 0x10 +#define EFI_IFR_FLAG_REST_STYLE 0x20 +#define EFI_IFR_FLAG_RECONNECT_REQUIRED 0x40 +#define EFI_IFR_FLAG_OPTIONS_ONLY 0x80 + +// +// Definition for Opcode Reference +// Section 27.3.8.3 +// +typedef struct _EFI_IFR_DEFAULTSTORE { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID DefaultName; + UINT16 DefaultId; +} EFI_IFR_DEFAULTSTORE; + +// +// Default Identifier of default store +// +#define EFI_HII_DEFAULT_CLASS_STANDARD 0x0000 +#define EFI_HII_DEFAULT_CLASS_MANUFACTURING 0x0001 +#define EFI_HII_DEFAULT_CLASS_SAFE 0x0002 +#define EFI_HII_DEFAULT_CLASS_PLATFORM_BEGIN 0x4000 +#define EFI_HII_DEFAULT_CLASS_PLATFORM_END 0x7fff +#define EFI_HII_DEFAULT_CLASS_HARDWARE_BEGIN 0x8000 +#define EFI_HII_DEFAULT_CLASS_HARDWARE_END 0xbfff +#define EFI_HII_DEFAULT_CLASS_FIRMWARE_BEGIN 0xc000 +#define EFI_HII_DEFAULT_CLASS_FIRMWARE_END 0xffff + +typedef struct _EFI_IFR_VARSTORE { + EFI_IFR_OP_HEADER Header; + EFI_GUID Guid; + EFI_VARSTORE_ID VarStoreId; + UINT16 Size; + UINT8 Name[1]; +} EFI_IFR_VARSTORE; + +typedef struct _EFI_IFR_VARSTORE_EFI { + EFI_IFR_OP_HEADER Header; + EFI_VARSTORE_ID VarStoreId; + EFI_GUID Guid; + UINT32 Attributes; + UINT16 Size; + UINT8 Name[1]; +} EFI_IFR_VARSTORE_EFI; + +typedef struct _EFI_IFR_VARSTORE_NAME_VALUE { + EFI_IFR_OP_HEADER Header; + EFI_VARSTORE_ID VarStoreId; + EFI_GUID Guid; +} EFI_IFR_VARSTORE_NAME_VALUE; + +typedef struct _EFI_IFR_FORM_SET { + EFI_IFR_OP_HEADER Header; + EFI_GUID Guid; + EFI_STRING_ID FormSetTitle; + EFI_STRING_ID Help; + UINT8 Flags; + // EFI_GUID ClassGuid[]; +} EFI_IFR_FORM_SET; + +typedef struct _EFI_IFR_END { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_END; + +typedef struct _EFI_IFR_FORM { + EFI_IFR_OP_HEADER Header; + UINT16 FormId; + EFI_STRING_ID FormTitle; +} EFI_IFR_FORM; + +typedef struct _EFI_IFR_IMAGE { + EFI_IFR_OP_HEADER Header; + EFI_IMAGE_ID Id; +} EFI_IFR_IMAGE; + +typedef struct _EFI_IFR_MODAL_TAG { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MODAL_TAG; + +typedef struct _EFI_IFR_LOCKED { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_LOCKED; + +typedef struct _EFI_IFR_RULE { + EFI_IFR_OP_HEADER Header; + UINT8 RuleId; +} EFI_IFR_RULE; + +typedef struct _EFI_IFR_DEFAULT { + EFI_IFR_OP_HEADER Header; + UINT16 DefaultId; + UINT8 Type; + EFI_IFR_TYPE_VALUE Value; +} EFI_IFR_DEFAULT; + +typedef struct _EFI_IFR_DEFAULT_2 { + EFI_IFR_OP_HEADER Header; + UINT16 DefaultId; + UINT8 Type; +} EFI_IFR_DEFAULT_2; + +typedef struct _EFI_IFR_VALUE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_VALUE; + +typedef struct _EFI_IFR_SUBTITLE { + EFI_IFR_OP_HEADER Header; + EFI_IFR_STATEMENT_HEADER Statement; + UINT8 Flags; +} EFI_IFR_SUBTITLE; + +#define EFI_IFR_FLAGS_HORIZONTAL 0x01 + +typedef struct _EFI_IFR_CHECKBOX { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 Flags; +} EFI_IFR_CHECKBOX; + +#define EFI_IFR_CHECKBOX_DEFAULT 0x01 +#define EFI_IFR_CHECKBOX_DEFAULT_MFG 0x02 + +typedef struct _EFI_IFR_TEXT { + EFI_IFR_OP_HEADER Header; + EFI_IFR_STATEMENT_HEADER Statement; + EFI_STRING_ID TextTwo; +} EFI_IFR_TEXT; + +typedef struct _EFI_IFR_REF { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + EFI_FORM_ID FormId; +} EFI_IFR_REF; + +typedef struct _EFI_IFR_REF2 { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + EFI_FORM_ID FormId; + EFI_QUESTION_ID QuestionId; +} EFI_IFR_REF2; + +typedef struct _EFI_IFR_REF3 { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + EFI_FORM_ID FormId; + EFI_QUESTION_ID QuestionId; + EFI_GUID FormSetId; +} EFI_IFR_REF3; + +typedef struct _EFI_IFR_REF4 { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + EFI_FORM_ID FormId; + EFI_QUESTION_ID QuestionId; + EFI_GUID FormSetId; + EFI_STRING_ID DevicePath; +} EFI_IFR_REF4; + +typedef struct _EFI_IFR_REF5 { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; +} EFI_IFR_REF5; + +typedef struct _EFI_IFR_RESET_BUTTON { + EFI_IFR_OP_HEADER Header; + EFI_IFR_STATEMENT_HEADER Statement; + EFI_DEFAULT_ID DefaultId; +} EFI_IFR_RESET_BUTTON; + +typedef struct _EFI_IFR_ACTION { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + EFI_STRING_ID QuestionConfig; +} EFI_IFR_ACTION; + +typedef struct _EFI_IFR_ACTION_1 { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; +} EFI_IFR_ACTION_1; + +typedef struct _EFI_IFR_DATE { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 Flags; +} EFI_IFR_DATE; + +// +// Flags that describe the behavior of the question. +// +#define EFI_QF_DATE_YEAR_SUPPRESS 0x01 +#define EFI_QF_DATE_MONTH_SUPPRESS 0x02 +#define EFI_QF_DATE_DAY_SUPPRESS 0x04 + +#define EFI_QF_DATE_STORAGE 0x30 +#define QF_DATE_STORAGE_NORMAL 0x00 +#define QF_DATE_STORAGE_TIME 0x10 +#define QF_DATE_STORAGE_WAKEUP 0x20 + +typedef union { + struct { + UINT8 MinValue; + UINT8 MaxValue; + UINT8 Step; + } u8; + struct { + UINT16 MinValue; + UINT16 MaxValue; + UINT16 Step; + } u16; + struct { + UINT32 MinValue; + UINT32 MaxValue; + UINT32 Step; + } u32; + struct { + UINT64 MinValue; + UINT64 MaxValue; + UINT64 Step; + } u64; +} MINMAXSTEP_DATA; + +typedef struct _EFI_IFR_NUMERIC { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 Flags; + MINMAXSTEP_DATA data; +} EFI_IFR_NUMERIC; + +// +// Flags related to the numeric question +// +#define EFI_IFR_NUMERIC_SIZE 0x03 +#define EFI_IFR_NUMERIC_SIZE_1 0x00 +#define EFI_IFR_NUMERIC_SIZE_2 0x01 +#define EFI_IFR_NUMERIC_SIZE_4 0x02 +#define EFI_IFR_NUMERIC_SIZE_8 0x03 + +#define EFI_IFR_DISPLAY 0x30 +#define EFI_IFR_DISPLAY_INT_DEC 0x00 +#define EFI_IFR_DISPLAY_UINT_DEC 0x10 +#define EFI_IFR_DISPLAY_UINT_HEX 0x20 + +typedef struct _EFI_IFR_ONE_OF { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 Flags; + MINMAXSTEP_DATA data; +} EFI_IFR_ONE_OF; + +typedef struct _EFI_IFR_STRING { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 MinSize; + UINT8 MaxSize; + UINT8 Flags; +} EFI_IFR_STRING; + +#define EFI_IFR_STRING_MULTI_LINE 0x01 + +typedef struct _EFI_IFR_PASSWORD { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT16 MinSize; + UINT16 MaxSize; +} EFI_IFR_PASSWORD; + +typedef struct _EFI_IFR_ORDERED_LIST { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 MaxContainers; + UINT8 Flags; +} EFI_IFR_ORDERED_LIST; + +#define EFI_IFR_UNIQUE_SET 0x01 +#define EFI_IFR_NO_EMPTY_SET 0x02 + +typedef struct _EFI_IFR_TIME { + EFI_IFR_OP_HEADER Header; + EFI_IFR_QUESTION_HEADER Question; + UINT8 Flags; +} EFI_IFR_TIME; + +// +// A bit-mask that determines which unique settings are active for this opcode. +// +#define QF_TIME_HOUR_SUPPRESS 0x01 +#define QF_TIME_MINUTE_SUPPRESS 0x02 +#define QF_TIME_SECOND_SUPPRESS 0x04 + +#define QF_TIME_STORAGE 0x30 +#define QF_TIME_STORAGE_NORMAL 0x00 +#define QF_TIME_STORAGE_TIME 0x10 +#define QF_TIME_STORAGE_WAKEUP 0x20 + +typedef struct _EFI_IFR_DISABLE_IF { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_DISABLE_IF; + +typedef struct _EFI_IFR_SUPPRESS_IF { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_SUPPRESS_IF; + +typedef struct _EFI_IFR_GRAY_OUT_IF { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_GRAY_OUT_IF; + +typedef struct _EFI_IFR_INCONSISTENT_IF { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID Error; +} EFI_IFR_INCONSISTENT_IF; + +typedef struct _EFI_IFR_NO_SUBMIT_IF { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID Error; +} EFI_IFR_NO_SUBMIT_IF; + +typedef struct _EFI_IFR_WARNING_IF { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID Warning; + UINT8 TimeOut; +} EFI_IFR_WARNING_IF; + +typedef struct _EFI_IFR_REFRESH { + EFI_IFR_OP_HEADER Header; + UINT8 RefreshInterval; +} EFI_IFR_REFRESH; + +typedef struct _EFI_IFR_VARSTORE_DEVICE { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID DevicePath; +} EFI_IFR_VARSTORE_DEVICE; + +typedef struct _EFI_IFR_ONE_OF_OPTION { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID Option; + UINT8 Flags; + UINT8 Type; + EFI_IFR_TYPE_VALUE Value; +} EFI_IFR_ONE_OF_OPTION; + +// +// Types of the option's value. +// +#define EFI_IFR_TYPE_NUM_SIZE_8 0x00 +#define EFI_IFR_TYPE_NUM_SIZE_16 0x01 +#define EFI_IFR_TYPE_NUM_SIZE_32 0x02 +#define EFI_IFR_TYPE_NUM_SIZE_64 0x03 +#define EFI_IFR_TYPE_BOOLEAN 0x04 +#define EFI_IFR_TYPE_TIME 0x05 +#define EFI_IFR_TYPE_DATE 0x06 +#define EFI_IFR_TYPE_STRING 0x07 +#define EFI_IFR_TYPE_OTHER 0x08 +#define EFI_IFR_TYPE_UNDEFINED 0x09 +#define EFI_IFR_TYPE_ACTION 0x0A +#define EFI_IFR_TYPE_BUFFER 0x0B +#define EFI_IFR_TYPE_REF 0x0C + +#define EFI_IFR_OPTION_DEFAULT 0x10 +#define EFI_IFR_OPTION_DEFAULT_MFG 0x20 + +typedef struct _EFI_IFR_GUID { + EFI_IFR_OP_HEADER Header; + EFI_GUID Guid; + //Optional Data Follows +} EFI_IFR_GUID; + +typedef struct _EFI_IFR_REFRESH_ID { + EFI_IFR_OP_HEADER Header; + EFI_GUID RefreshEventGroupId; +} EFI_IFR_REFRESH_ID; + +typedef struct _EFI_IFR_DUP { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_DUP; + +typedef struct _EFI_IFR_EQ_ID_ID { + EFI_IFR_OP_HEADER Header; + EFI_QUESTION_ID QuestionId1; + EFI_QUESTION_ID QuestionId2; +} EFI_IFR_EQ_ID_ID; + +typedef struct _EFI_IFR_EQ_ID_VAL { + EFI_IFR_OP_HEADER Header; + EFI_QUESTION_ID QuestionId; + UINT16 Value; +} EFI_IFR_EQ_ID_VAL; + +typedef struct _EFI_IFR_EQ_ID_VAL_LIST { + EFI_IFR_OP_HEADER Header; + EFI_QUESTION_ID QuestionId; + UINT16 ListLength; + UINT16 ValueList[1]; +} EFI_IFR_EQ_ID_VAL_LIST; + +typedef struct _EFI_IFR_UINT8 { + EFI_IFR_OP_HEADER Header; + UINT8 Value; +} EFI_IFR_UINT8; + +typedef struct _EFI_IFR_UINT16 { + EFI_IFR_OP_HEADER Header; + UINT16 Value; +} EFI_IFR_UINT16; + +typedef struct _EFI_IFR_UINT32 { + EFI_IFR_OP_HEADER Header; + UINT32 Value; +} EFI_IFR_UINT32; + +typedef struct _EFI_IFR_UINT64 { + EFI_IFR_OP_HEADER Header; + UINT64 Value; +} EFI_IFR_UINT64; + +typedef struct _EFI_IFR_QUESTION_REF1 { + EFI_IFR_OP_HEADER Header; + EFI_QUESTION_ID QuestionId; +} EFI_IFR_QUESTION_REF1; + +typedef struct _EFI_IFR_QUESTION_REF2 { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_QUESTION_REF2; + +typedef struct _EFI_IFR_QUESTION_REF3 { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_QUESTION_REF3; + +typedef struct _EFI_IFR_QUESTION_REF3_2 { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID DevicePath; +} EFI_IFR_QUESTION_REF3_2; + +typedef struct _EFI_IFR_QUESTION_REF3_3 { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID DevicePath; + EFI_GUID Guid; +} EFI_IFR_QUESTION_REF3_3; + +typedef struct _EFI_IFR_RULE_REF { + EFI_IFR_OP_HEADER Header; + UINT8 RuleId; +} EFI_IFR_RULE_REF; + +typedef struct _EFI_IFR_STRING_REF1 { + EFI_IFR_OP_HEADER Header; + EFI_STRING_ID StringId; +} EFI_IFR_STRING_REF1; + +typedef struct _EFI_IFR_STRING_REF2 { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_STRING_REF2; + +typedef struct _EFI_IFR_THIS { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_THIS; + +typedef struct _EFI_IFR_TRUE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TRUE; + +typedef struct _EFI_IFR_FALSE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_FALSE; + +typedef struct _EFI_IFR_ONE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_ONE; + +typedef struct _EFI_IFR_ONES { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_ONES; + +typedef struct _EFI_IFR_ZERO { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_ZERO; + +typedef struct _EFI_IFR_UNDEFINED { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_UNDEFINED; + +typedef struct _EFI_IFR_VERSION { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_VERSION; + +typedef struct _EFI_IFR_LENGTH { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_LENGTH; + +typedef struct _EFI_IFR_NOT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_NOT; + +typedef struct _EFI_IFR_BITWISE_NOT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_BITWISE_NOT; + +typedef struct _EFI_IFR_TO_BOOLEAN { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TO_BOOLEAN; + +/// +/// For EFI_IFR_TO_STRING, when converting from +/// unsigned integers, these flags control the format: +/// 0 = unsigned decimal. +/// 1 = signed decimal. +/// 2 = hexadecimal (lower-case alpha). +/// 3 = hexadecimal (upper-case alpha). +///@{ +#define EFI_IFR_STRING_UNSIGNED_DEC 0 +#define EFI_IFR_STRING_SIGNED_DEC 1 +#define EFI_IFR_STRING_LOWERCASE_HEX 2 +#define EFI_IFR_STRING_UPPERCASE_HEX 3 +///@} + +/// +/// When converting from a buffer, these flags control the format: +/// 0 = ASCII. +/// 8 = Unicode. +///@{ +#define EFI_IFR_STRING_ASCII 0 +#define EFI_IFR_STRING_UNICODE 8 +///@} + +typedef struct _EFI_IFR_TO_STRING { + EFI_IFR_OP_HEADER Header; + UINT8 Format; +} EFI_IFR_TO_STRING; + +typedef struct _EFI_IFR_TO_UINT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TO_UINT; + +typedef struct _EFI_IFR_TO_UPPER { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TO_UPPER; + +typedef struct _EFI_IFR_TO_LOWER { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TO_LOWER; + +typedef struct _EFI_IFR_ADD { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_ADD; + +typedef struct _EFI_IFR_AND { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_AND; + +typedef struct _EFI_IFR_BITWISE_AND { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_BITWISE_AND; + +typedef struct _EFI_IFR_BITWISE_OR { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_BITWISE_OR; + +typedef struct _EFI_IFR_CATENATE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_CATENATE; + +typedef struct _EFI_IFR_DIVIDE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_DIVIDE; + +typedef struct _EFI_IFR_EQUAL { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_EQUAL; + +typedef struct _EFI_IFR_GREATER_EQUAL { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_GREATER_EQUAL; + +typedef struct _EFI_IFR_GREATER_THAN { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_GREATER_THAN; + +typedef struct _EFI_IFR_LESS_EQUAL { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_LESS_EQUAL; + +typedef struct _EFI_IFR_LESS_THAN { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_LESS_THAN; + +typedef struct _EFI_IFR_MATCH { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MATCH; + +typedef struct _EFI_IFR_MATCH2 { + EFI_IFR_OP_HEADER Header; + EFI_GUID SyntaxType; +} EFI_IFR_MATCH2; + +typedef struct _EFI_IFR_MULTIPLY { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MULTIPLY; + +typedef struct _EFI_IFR_MODULO { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MODULO; + +typedef struct _EFI_IFR_NOT_EQUAL { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_NOT_EQUAL; + +typedef struct _EFI_IFR_OR { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_OR; + +typedef struct _EFI_IFR_SHIFT_LEFT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_SHIFT_LEFT; + +typedef struct _EFI_IFR_SHIFT_RIGHT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_SHIFT_RIGHT; + +typedef struct _EFI_IFR_SUBTRACT { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_SUBTRACT; + +typedef struct _EFI_IFR_CONDITIONAL { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_CONDITIONAL; + +// +// Flags governing the matching criteria of EFI_IFR_FIND +// +#define EFI_IFR_FF_CASE_SENSITIVE 0x00 +#define EFI_IFR_FF_CASE_INSENSITIVE 0x01 + +typedef struct _EFI_IFR_FIND { + EFI_IFR_OP_HEADER Header; + UINT8 Format; +} EFI_IFR_FIND; + +typedef struct _EFI_IFR_MID { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MID; + +typedef struct _EFI_IFR_TOKEN { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_TOKEN; + +// +// Flags specifying whether to find the first matching string +// or the first non-matching string. +// +#define EFI_IFR_FLAGS_FIRST_MATCHING 0x00 +#define EFI_IFR_FLAGS_FIRST_NON_MATCHING 0x01 + +typedef struct _EFI_IFR_SPAN { + EFI_IFR_OP_HEADER Header; + UINT8 Flags; +} EFI_IFR_SPAN; + +typedef struct _EFI_IFR_SECURITY { + /// + /// Standard opcode header, where Header.Op = EFI_IFR_SECURITY_OP. + /// + EFI_IFR_OP_HEADER Header; + /// + /// Security permission level. + /// + EFI_GUID Permissions; +} EFI_IFR_SECURITY; + +typedef struct _EFI_IFR_FORM_MAP_METHOD { + /// + /// The string identifier which provides the human-readable name of + /// the configuration method for this standards map form. + /// + EFI_STRING_ID MethodTitle; + /// + /// Identifier which uniquely specifies the configuration methods + /// associated with this standards map form. + /// + EFI_GUID MethodIdentifier; +} EFI_IFR_FORM_MAP_METHOD; + +typedef struct _EFI_IFR_FORM_MAP { + /// + /// The sequence that defines the type of opcode as well as the length + /// of the opcode being defined. Header.OpCode = EFI_IFR_FORM_MAP_OP. + /// + EFI_IFR_OP_HEADER Header; + /// + /// The unique identifier for this particular form. + /// + EFI_FORM_ID FormId; + /// + /// One or more configuration method's name and unique identifier. + /// + // EFI_IFR_FORM_MAP_METHOD Methods[]; +} EFI_IFR_FORM_MAP; + +typedef struct _EFI_IFR_SET { + /// + /// The sequence that defines the type of opcode as well as the length + /// of the opcode being defined. Header.OpCode = EFI_IFR_SET_OP. + /// + EFI_IFR_OP_HEADER Header; + /// + /// Specifies the identifier of a previously declared variable store to + /// use when storing the question's value. + /// + EFI_VARSTORE_ID VarStoreId; + union { + /// + /// A 16-bit Buffer Storage offset. + /// + EFI_STRING_ID VarName; + /// + /// A Name Value or EFI Variable name (VarName). + /// + UINT16 VarOffset; + } VarStoreInfo; + /// + /// Specifies the type used for storage. + /// + UINT8 VarStoreType; +} EFI_IFR_SET; + +typedef struct _EFI_IFR_GET { + /// + /// The sequence that defines the type of opcode as well as the length + /// of the opcode being defined. Header.OpCode = EFI_IFR_GET_OP. + /// + EFI_IFR_OP_HEADER Header; + /// + /// Specifies the identifier of a previously declared variable store to + /// use when retrieving the value. + /// + EFI_VARSTORE_ID VarStoreId; + union { + /// + /// A 16-bit Buffer Storage offset. + /// + EFI_STRING_ID VarName; + /// + /// A Name Value or EFI Variable name (VarName). + /// + UINT16 VarOffset; + } VarStoreInfo; + /// + /// Specifies the type used for storage. + /// + UINT8 VarStoreType; +} EFI_IFR_GET; + +typedef struct _EFI_IFR_READ { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_READ; + +typedef struct _EFI_IFR_WRITE { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_WRITE; + +typedef struct _EFI_IFR_MAP { + EFI_IFR_OP_HEADER Header; +} EFI_IFR_MAP; +// +// Definitions for Keyboard Package +// Releated definitions are in Section of EFI_HII_DATABASE_PROTOCOL +// + +/// +/// Each enumeration values maps a physical key on a keyboard. +/// +typedef enum { + EfiKeyLCtrl, + EfiKeyA0, + EfiKeyLAlt, + EfiKeySpaceBar, + EfiKeyA2, + EfiKeyA3, + EfiKeyA4, + EfiKeyRCtrl, + EfiKeyLeftArrow, + EfiKeyDownArrow, + EfiKeyRightArrow, + EfiKeyZero, + EfiKeyPeriod, + EfiKeyEnter, + EfiKeyLShift, + EfiKeyB0, + EfiKeyB1, + EfiKeyB2, + EfiKeyB3, + EfiKeyB4, + EfiKeyB5, + EfiKeyB6, + EfiKeyB7, + EfiKeyB8, + EfiKeyB9, + EfiKeyB10, + EfiKeyRShift, + EfiKeyUpArrow, + EfiKeyOne, + EfiKeyTwo, + EfiKeyThree, + EfiKeyCapsLock, + EfiKeyC1, + EfiKeyC2, + EfiKeyC3, + EfiKeyC4, + EfiKeyC5, + EfiKeyC6, + EfiKeyC7, + EfiKeyC8, + EfiKeyC9, + EfiKeyC10, + EfiKeyC11, + EfiKeyC12, + EfiKeyFour, + EfiKeyFive, + EfiKeySix, + EfiKeyPlus, + EfiKeyTab, + EfiKeyD1, + EfiKeyD2, + EfiKeyD3, + EfiKeyD4, + EfiKeyD5, + EfiKeyD6, + EfiKeyD7, + EfiKeyD8, + EfiKeyD9, + EfiKeyD10, + EfiKeyD11, + EfiKeyD12, + EfiKeyD13, + EfiKeyDel, + EfiKeyEnd, + EfiKeyPgDn, + EfiKeySeven, + EfiKeyEight, + EfiKeyNine, + EfiKeyE0, + EfiKeyE1, + EfiKeyE2, + EfiKeyE3, + EfiKeyE4, + EfiKeyE5, + EfiKeyE6, + EfiKeyE7, + EfiKeyE8, + EfiKeyE9, + EfiKeyE10, + EfiKeyE11, + EfiKeyE12, + EfiKeyBackSpace, + EfiKeyIns, + EfiKeyHome, + EfiKeyPgUp, + EfiKeyNLck, + EfiKeySlash, + EfiKeyAsterisk, + EfiKeyMinus, + EfiKeyEsc, + EfiKeyF1, + EfiKeyF2, + EfiKeyF3, + EfiKeyF4, + EfiKeyF5, + EfiKeyF6, + EfiKeyF7, + EfiKeyF8, + EfiKeyF9, + EfiKeyF10, + EfiKeyF11, + EfiKeyF12, + EfiKeyPrint, + EfiKeySLck, + EfiKeyPause +} EFI_KEY; + +typedef struct { + /// + /// Used to describe a physical key on a keyboard. + /// + EFI_KEY Key; + /// + /// Unicode character code for the Key. + /// + CHAR16 Unicode; + /// + /// Unicode character code for the key with the shift key being held down. + /// + CHAR16 ShiftedUnicode; + /// + /// Unicode character code for the key with the Alt-GR being held down. + /// + CHAR16 AltGrUnicode; + /// + /// Unicode character code for the key with the Alt-GR and shift keys being held down. + /// + CHAR16 ShiftedAltGrUnicode; + /// + /// Modifier keys are defined to allow for special functionality that is not necessarily + /// accomplished by a printable character. Many of these modifier keys are flags to toggle + /// certain state bits on and off inside of a keyboard driver. + /// + UINT16 Modifier; + UINT16 AffectedAttribute; +} EFI_KEY_DESCRIPTOR; + +/// +/// A key which is affected by all the standard shift modifiers. +/// Most keys would be expected to have this bit active. +/// +#define EFI_AFFECTED_BY_STANDARD_SHIFT 0x0001 + +/// +/// This key is affected by the caps lock so that if a keyboard driver +/// would need to disambiguate between a key which had a "1" defined +/// versus an "a" character. Having this bit turned on would tell +/// the keyboard driver to use the appropriate shifted state or not. +/// +#define EFI_AFFECTED_BY_CAPS_LOCK 0x0002 + +/// +/// Similar to the case of CAPS lock, if this bit is active, the key +/// is affected by the num lock being turned on. +/// +#define EFI_AFFECTED_BY_NUM_LOCK 0x0004 + +typedef struct { + UINT16 LayoutLength; + EFI_GUID Guid; + UINT32 LayoutDescriptorStringOffset; + UINT8 DescriptorCount; + // EFI_KEY_DESCRIPTOR Descriptors[]; +} EFI_HII_KEYBOARD_LAYOUT; + +typedef struct { + EFI_HII_PACKAGE_HEADER Header; + UINT16 LayoutCount; + // EFI_HII_KEYBOARD_LAYOUT Layout[]; +} EFI_HII_KEYBOARD_PACKAGE_HDR; + +// +// Modifier values +// +#define EFI_NULL_MODIFIER 0x0000 +#define EFI_LEFT_CONTROL_MODIFIER 0x0001 +#define EFI_RIGHT_CONTROL_MODIFIER 0x0002 +#define EFI_LEFT_ALT_MODIFIER 0x0003 +#define EFI_RIGHT_ALT_MODIFIER 0x0004 +#define EFI_ALT_GR_MODIFIER 0x0005 +#define EFI_INSERT_MODIFIER 0x0006 +#define EFI_DELETE_MODIFIER 0x0007 +#define EFI_PAGE_DOWN_MODIFIER 0x0008 +#define EFI_PAGE_UP_MODIFIER 0x0009 +#define EFI_HOME_MODIFIER 0x000A +#define EFI_END_MODIFIER 0x000B +#define EFI_LEFT_SHIFT_MODIFIER 0x000C +#define EFI_RIGHT_SHIFT_MODIFIER 0x000D +#define EFI_CAPS_LOCK_MODIFIER 0x000E +#define EFI_NUM_LOCK_MODIFIER 0x000F +#define EFI_LEFT_ARROW_MODIFIER 0x0010 +#define EFI_RIGHT_ARROW_MODIFIER 0x0011 +#define EFI_DOWN_ARROW_MODIFIER 0x0012 +#define EFI_UP_ARROW_MODIFIER 0x0013 +#define EFI_NS_KEY_MODIFIER 0x0014 +#define EFI_NS_KEY_DEPENDENCY_MODIFIER 0x0015 +#define EFI_FUNCTION_KEY_ONE_MODIFIER 0x0016 +#define EFI_FUNCTION_KEY_TWO_MODIFIER 0x0017 +#define EFI_FUNCTION_KEY_THREE_MODIFIER 0x0018 +#define EFI_FUNCTION_KEY_FOUR_MODIFIER 0x0019 +#define EFI_FUNCTION_KEY_FIVE_MODIFIER 0x001A +#define EFI_FUNCTION_KEY_SIX_MODIFIER 0x001B +#define EFI_FUNCTION_KEY_SEVEN_MODIFIER 0x001C +#define EFI_FUNCTION_KEY_EIGHT_MODIFIER 0x001D +#define EFI_FUNCTION_KEY_NINE_MODIFIER 0x001E +#define EFI_FUNCTION_KEY_TEN_MODIFIER 0x001F +#define EFI_FUNCTION_KEY_ELEVEN_MODIFIER 0x0020 +#define EFI_FUNCTION_KEY_TWELVE_MODIFIER 0x0021 + +// +// Keys that have multiple control functions based on modifier +// settings are handled in the keyboard driver implementation. +// For instance, PRINT_KEY might have a modifier held down and +// is still a nonprinting character, but might have an alternate +// control function like SYSREQUEST +// +#define EFI_PRINT_MODIFIER 0x0022 +#define EFI_SYS_REQUEST_MODIFIER 0x0023 +#define EFI_SCROLL_LOCK_MODIFIER 0x0024 +#define EFI_PAUSE_MODIFIER 0x0025 +#define EFI_BREAK_MODIFIER 0x0026 + +#define EFI_LEFT_LOGO_MODIFIER 0x0027 +#define EFI_RIGHT_LOGO_MODIFIER 0x0028 +#define EFI_MENU_MODIFIER 0x0029 + +/// +/// Animation IFR opcode +/// +typedef struct _EFI_IFR_ANIMATION { + /// + /// Standard opcode header, where Header.OpCode is + /// EFI_IFR_ANIMATION_OP. + /// + EFI_IFR_OP_HEADER Header; + /// + /// Animation identifier in the HII database. + /// + EFI_ANIMATION_ID Id; +} EFI_IFR_ANIMATION; + +/// +/// HII animation package header. +/// +typedef struct _EFI_HII_ANIMATION_PACKAGE_HDR { + /// + /// Standard package header, where Header.Type = EFI_HII_PACKAGE_ANIMATIONS. + /// + EFI_HII_PACKAGE_HEADER Header; + /// + /// Offset, relative to this header, of the animation information. If + /// this is zero, then there are no animation sequences in the package. + /// + UINT32 AnimationInfoOffset; +} EFI_HII_ANIMATION_PACKAGE_HDR; + +/// +/// Animation information is encoded as a series of blocks, +/// with each block prefixed by a single byte header EFI_HII_ANIMATION_BLOCK. +/// +typedef struct _EFI_HII_ANIMATION_BLOCK { + UINT8 BlockType; + //UINT8 BlockBody[]; +} EFI_HII_ANIMATION_BLOCK; + +/// +/// Animation block types. +/// +#define EFI_HII_AIBT_END 0x00 +#define EFI_HII_AIBT_OVERLAY_IMAGES 0x10 +#define EFI_HII_AIBT_CLEAR_IMAGES 0x11 +#define EFI_HII_AIBT_RESTORE_SCRN 0x12 +#define EFI_HII_AIBT_OVERLAY_IMAGES_LOOP 0x18 +#define EFI_HII_AIBT_CLEAR_IMAGES_LOOP 0x19 +#define EFI_HII_AIBT_RESTORE_SCRN_LOOP 0x1A +#define EFI_HII_AIBT_DUPLICATE 0x20 +#define EFI_HII_AIBT_SKIP2 0x21 +#define EFI_HII_AIBT_SKIP1 0x22 +#define EFI_HII_AIBT_EXT1 0x30 +#define EFI_HII_AIBT_EXT2 0x31 +#define EFI_HII_AIBT_EXT4 0x32 + +/// +/// Extended block headers used for variable sized animation records +/// which need an explicit length. +/// + +typedef struct _EFI_HII_AIBT_EXT1_BLOCK { + /// + /// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT1. + /// + EFI_HII_ANIMATION_BLOCK Header; + /// + /// The block type. + /// + UINT8 BlockType2; + /// + /// Size of the animation block, in bytes, including the animation block header. + /// + UINT8 Length; +} EFI_HII_AIBT_EXT1_BLOCK; + +typedef struct _EFI_HII_AIBT_EXT2_BLOCK { + /// + /// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT2. + /// + EFI_HII_ANIMATION_BLOCK Header; + /// + /// The block type + /// + UINT8 BlockType2; + /// + /// Size of the animation block, in bytes, including the animation block header. + /// + UINT16 Length; +} EFI_HII_AIBT_EXT2_BLOCK; + +typedef struct _EFI_HII_AIBT_EXT4_BLOCK { + /// + /// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT4. + /// + EFI_HII_ANIMATION_BLOCK Header; + /// + /// The block type + /// + UINT8 BlockType2; + /// + /// Size of the animation block, in bytes, including the animation block header. + /// + UINT32 Length; +} EFI_HII_AIBT_EXT4_BLOCK; + +typedef struct _EFI_HII_ANIMATION_CELL { + /// + /// The X offset from the upper left hand corner of the logical + /// window to position the indexed image. + /// + UINT16 OffsetX; + /// + /// The Y offset from the upper left hand corner of the logical + /// window to position the indexed image. + /// + UINT16 OffsetY; + /// + /// The image to display at the specified offset from the upper left + /// hand corner of the logical window. + /// + EFI_IMAGE_ID ImageId; + /// + /// The number of milliseconds to delay after displaying the indexed + /// image and before continuing on to the next linked image. If value + /// is zero, no delay. + /// + UINT16 Delay; +} EFI_HII_ANIMATION_CELL; + +/// +/// An animation block to describe an animation sequence that does not cycle, and +/// where one image is simply displayed over the previous image. +/// +typedef struct _EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK { + /// + /// This is image that is to be reference by the image protocols, if the + /// animation function is not supported or disabled. This image can + /// be one particular image from the animation sequence (if any one + /// of the animation frames has a complete image) or an alternate + /// image that can be displayed alone. If the value is zero, no image + /// is displayed. + /// + EFI_IMAGE_ID DftImageId; + /// + /// The overall width of the set of images (logical window width). + /// + UINT16 Width; + /// + /// The overall height of the set of images (logical window height). + /// + UINT16 Height; + /// + /// The number of EFI_HII_ANIMATION_CELL contained in the + /// animation sequence. + /// + UINT16 CellCount; + /// + /// An array of CellCount animation cells. + /// + EFI_HII_ANIMATION_CELL AnimationCell[1]; +} EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK; + +/// +/// An animation block to describe an animation sequence that does not cycle, +/// and where the logical window is cleared to the specified color before +/// the next image is displayed. +/// +typedef struct _EFI_HII_AIBT_CLEAR_IMAGES_BLOCK { + /// + /// This is image that is to be reference by the image protocols, if the + /// animation function is not supported or disabled. This image can + /// be one particular image from the animation sequence (if any one + /// of the animation frames has a complete image) or an alternate + /// image that can be displayed alone. If the value is zero, no image + /// is displayed. + /// + EFI_IMAGE_ID DftImageId; + /// + /// The overall width of the set of images (logical window width). + /// + UINT16 Width; + /// + /// The overall height of the set of images (logical window height). + /// + UINT16 Height; + /// + /// The number of EFI_HII_ANIMATION_CELL contained in the + /// animation sequence. + /// + UINT16 CellCount; + /// + /// The color to clear the logical window to before displaying the + /// indexed image. + /// + EFI_HII_RGB_PIXEL BackgndColor; + /// + /// An array of CellCount animation cells. + /// + EFI_HII_ANIMATION_CELL AnimationCell[1]; +} EFI_HII_AIBT_CLEAR_IMAGES_BLOCK; + +/// +/// An animation block to describe an animation sequence that does not cycle, +/// and where the screen is restored to the original state before the next +/// image is displayed. +/// +typedef struct _EFI_HII_AIBT_RESTORE_SCRN_BLOCK { + /// + /// This is image that is to be reference by the image protocols, if the + /// animation function is not supported or disabled. This image can + /// be one particular image from the animation sequence (if any one + /// of the animation frames has a complete image) or an alternate + /// image that can be displayed alone. If the value is zero, no image + /// is displayed. + /// + EFI_IMAGE_ID DftImageId; + /// + /// The overall width of the set of images (logical window width). + /// + UINT16 Width; + /// + /// The overall height of the set of images (logical window height). + /// + UINT16 Height; + /// + /// The number of EFI_HII_ANIMATION_CELL contained in the + /// animation sequence. + /// + UINT16 CellCount; + /// + /// An array of CellCount animation cells. + /// + EFI_HII_ANIMATION_CELL AnimationCell[1]; +} EFI_HII_AIBT_RESTORE_SCRN_BLOCK; + +/// +/// An animation block to describe an animation sequence that continuously cycles, +/// and where one image is simply displayed over the previous image. +/// +typedef EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOCK; + +/// +/// An animation block to describe an animation sequence that continuously cycles, +/// and where the logical window is cleared to the specified color before +/// the next image is displayed. +/// +typedef EFI_HII_AIBT_CLEAR_IMAGES_BLOCK EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK; + +/// +/// An animation block to describe an animation sequence that continuously cycles, +/// and where the screen is restored to the original state before +/// the next image is displayed. +/// +typedef EFI_HII_AIBT_RESTORE_SCRN_BLOCK EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK; + +/// +/// Assigns a new character value to a previously defined animation sequence. +/// +typedef struct _EFI_HII_AIBT_DUPLICATE_BLOCK { + /// + /// The previously defined animation ID with the exact same + /// animation information. + /// + EFI_ANIMATION_ID AnimationId; +} EFI_HII_AIBT_DUPLICATE_BLOCK; + +/// +/// Skips animation IDs. +/// +typedef struct _EFI_HII_AIBT_SKIP1_BLOCK { + /// + /// The unsigned 8-bit value to add to AnimationIdCurrent. + /// + UINT8 SkipCount; +} EFI_HII_AIBT_SKIP1_BLOCK; + +/// +/// Skips animation IDs. +/// +typedef struct _EFI_HII_AIBT_SKIP2_BLOCK { + /// + /// The unsigned 16-bit value to add to AnimationIdCurrent. + /// + UINT16 SkipCount; +} EFI_HII_AIBT_SKIP2_BLOCK; + +#pragma pack() + + + +/// +/// References to string tokens must use this macro to enable scanning for +/// token usages. +/// +/// +/// STRING_TOKEN is not defined in UEFI specification. But it is placed +/// here for the easy access by C files and VFR source files. +/// +#define STRING_TOKEN(t) t + +/// +/// IMAGE_TOKEN is not defined in UEFI specification. But it is placed +/// here for the easy access by C files and VFR source files. +/// +#define IMAGE_TOKEN(t) t + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiMultiPhase.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiMultiPhase.h new file mode 100644 index 0000000000..dd97e4e3bf --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiMultiPhase.h @@ -0,0 +1,229 @@ +/** @file + This includes some definitions introduced in UEFI that will be used in both PEI and DXE phases. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_MULTIPHASE_H__ +#define __UEFI_MULTIPHASE_H__ + +/// +/// Attributes of variable. +/// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +/// +/// This attribute is identified by the mnemonic 'HR' +/// elsewhere in this specification. +/// +#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008 +/// +/// Attributes of Authenticated Variable +/// +#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020 +#define EFI_VARIABLE_APPEND_WRITE 0x00000040 +/// +/// NOTE: EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and should be considered reserved. +/// +#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010 + +#ifndef VFRCOMPILE +#include +/// +/// Enumeration of memory types introduced in UEFI. +/// +typedef enum { + /// + /// Not used. + /// + EfiReservedMemoryType, + /// + /// The code portions of a loaded application. + /// (Note that UEFI OS loaders are UEFI applications.) + /// + EfiLoaderCode, + /// + /// The data portions of a loaded application and the default data allocation + /// type used by an application to allocate pool memory. + /// + EfiLoaderData, + /// + /// The code portions of a loaded Boot Services Driver. + /// + EfiBootServicesCode, + /// + /// The data portions of a loaded Boot Serves Driver, and the default data + /// allocation type used by a Boot Services Driver to allocate pool memory. + /// + EfiBootServicesData, + /// + /// The code portions of a loaded Runtime Services Driver. + /// + EfiRuntimeServicesCode, + /// + /// The data portions of a loaded Runtime Services Driver and the default + /// data allocation type used by a Runtime Services Driver to allocate pool memory. + /// + EfiRuntimeServicesData, + /// + /// Free (unallocated) memory. + /// + EfiConventionalMemory, + /// + /// Memory in which errors have been detected. + /// + EfiUnusableMemory, + /// + /// Memory that holds the ACPI tables. + /// + EfiACPIReclaimMemory, + /// + /// Address space reserved for use by the firmware. + /// + EfiACPIMemoryNVS, + /// + /// Used by system firmware to request that a memory-mapped IO region + /// be mapped by the OS to a virtual address so it can be accessed by EFI runtime services. + /// + EfiMemoryMappedIO, + /// + /// System memory-mapped IO region that is used to translate memory + /// cycles to IO cycles by the processor. + /// + EfiMemoryMappedIOPortSpace, + /// + /// Address space reserved by the firmware for code that is part of the processor. + /// + EfiPalCode, + /// + /// A memory region that operates as EfiConventionalMemory, + /// however it happens to also support byte-addressable non-volatility. + /// + EfiPersistentMemory, + EfiMaxMemoryType +} EFI_MEMORY_TYPE; + +/// +/// Enumeration of reset types. +/// +typedef enum { + /// + /// Used to induce a system-wide reset. This sets all circuitry within the + /// system to its initial state. This type of reset is asynchronous to system + /// operation and operates withgout regard to cycle boundaries. EfiColdReset + /// is tantamount to a system power cycle. + /// + EfiResetCold, + /// + /// Used to induce a system-wide initialization. The processors are set to their + /// initial state, and pending cycles are not corrupted. If the system does + /// not support this reset type, then an EfiResetCold must be performed. + /// + EfiResetWarm, + /// + /// Used to induce an entry into a power state equivalent to the ACPI G2/S5 or G3 + /// state. If the system does not support this reset type, then when the system + /// is rebooted, it should exhibit the EfiResetCold attributes. + /// + EfiResetShutdown, + /// + /// Used to induce a system-wide reset. The exact type of the reset is defined by + /// the EFI_GUID that follows the Null-terminated Unicode string passed into + /// ResetData. If the platform does not recognize the EFI_GUID in ResetData the + /// platform must pick a supported reset type to perform. The platform may + /// optionally log the parameters from any non-normal reset that occurs. + /// + EfiResetPlatformSpecific +} EFI_RESET_TYPE; + +/// +/// Data structure that precedes all of the standard EFI table types. +/// +typedef struct { + /// + /// A 64-bit signature that identifies the type of table that follows. + /// Unique signatures have been generated for the EFI System Table, + /// the EFI Boot Services Table, and the EFI Runtime Services Table. + /// + UINT64 Signature; + /// + /// The revision of the EFI Specification to which this table + /// conforms. The upper 16 bits of this field contain the major + /// revision value, and the lower 16 bits contain the minor revision + /// value. The minor revision values are limited to the range of 00..99. + /// + UINT32 Revision; + /// + /// The size, in bytes, of the entire table including the EFI_TABLE_HEADER. + /// + UINT32 HeaderSize; + /// + /// The 32-bit CRC for the entire table. This value is computed by + /// setting this field to 0, and computing the 32-bit CRC for HeaderSize bytes. + /// + UINT32 CRC32; + /// + /// Reserved field that must be set to 0. + /// + UINT32 Reserved; +} EFI_TABLE_HEADER; + +/// +/// AuthInfo is a WIN_CERTIFICATE using the wCertificateType +/// WIN_CERTIFICATE_UEFI_GUID and the CertType +/// EFI_CERT_TYPE_RSA2048_SHA256_GUID. If the attribute specifies +/// authenticated access, then the Data buffer should begin with an +/// authentication descriptor prior to the data payload and DataSize +/// should reflect the the data.and descriptor size. The caller +/// shall digest the Monotonic Count value and the associated data +/// for the variable update using the SHA-256 1-way hash algorithm. +/// The ensuing the 32-byte digest will be signed using the private +/// key associated w/ the public/private 2048-bit RSA key-pair. The +/// WIN_CERTIFICATE shall be used to describe the signature of the +/// Variable data *Data. In addition, the signature will also +/// include the MonotonicCount value to guard against replay attacks. +/// +typedef struct { + /// + /// Included in the signature of + /// AuthInfo.Used to ensure freshness/no + /// replay. Incremented during each + /// "Write" access. + /// + UINT64 MonotonicCount; + /// + /// Provides the authorization for the variable + /// access. It is a signature across the + /// variable data and the Monotonic Count + /// value. Caller uses Private key that is + /// associated with a public key that has been + /// provisioned via the key exchange. + /// + WIN_CERTIFICATE_UEFI_GUID AuthInfo; +} EFI_VARIABLE_AUTHENTICATION; + +/// +/// When the attribute EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS is +/// set, then the Data buffer shall begin with an instance of a complete (and serialized) +/// EFI_VARIABLE_AUTHENTICATION_2 descriptor. The descriptor shall be followed by the new +/// variable value and DataSize shall reflect the combined size of the descriptor and the new +/// variable value. The authentication descriptor is not part of the variable data and is not +/// returned by subsequent calls to GetVariable(). +/// +typedef struct { + /// + /// For the TimeStamp value, components Pad1, Nanosecond, TimeZone, Daylight and + /// Pad2 shall be set to 0. This means that the time shall always be expressed in GMT. + /// + EFI_TIME TimeStamp; + /// + /// Only a CertType of EFI_CERT_TYPE_PKCS7_GUID is accepted. + /// + WIN_CERTIFICATE_UEFI_GUID AuthInfo; + } EFI_VARIABLE_AUTHENTICATION_2; +#endif // VFRCOMPILE + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiPxe.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiPxe.h new file mode 100644 index 0000000000..6b92b3e44e --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiPxe.h @@ -0,0 +1,1786 @@ +/** @file + This header file contains all of the PXE type definitions, + structure prototypes, global variables and constants that + are needed for porting PXE to EFI. + +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + 32/64-bit PXE specification: + alpha-4, 99-Dec-17. + +**/ + +#ifndef __EFI_PXE_H__ +#define __EFI_PXE_H__ + +#pragma pack(1) + +#define PXE_BUSTYPE(a, b, c, d) \ + ( \ + (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \ + ((PXE_UINT32) (a) & 0xFF) \ + ) + +/// +/// UNDI ROM ID and devive ID signature. +/// +#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E') + +/// +/// BUS ROM ID signatures. +/// +#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R') +#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R') +#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R') +#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4') + +#define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8)) + +#define PXE_SWAP_UINT32(n) \ + ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \ + (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \ + (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \ + (((PXE_UINT32)(n) & 0xFF000000) >> 24)) + +#define PXE_SWAP_UINT64(n) \ + ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \ + (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \ + (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \ + (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \ + (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \ + (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \ + (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \ + (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56)) + + +#define PXE_CPBSIZE_NOT_USED 0 ///< zero +#define PXE_DBSIZE_NOT_USED 0 ///< zero +#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero +#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero +#define PXE_CONST CONST + +#define PXE_VOLATILE volatile + +typedef VOID PXE_VOID; +typedef UINT8 PXE_UINT8; +typedef UINT16 PXE_UINT16; +typedef UINT32 PXE_UINT32; +typedef UINTN PXE_UINTN; + +/// +/// Typedef unsigned long PXE_UINT64. +/// +typedef UINT64 PXE_UINT64; + +typedef PXE_UINT8 PXE_BOOL; +#define PXE_FALSE 0 ///< zero +#define PXE_TRUE (!PXE_FALSE) + +typedef PXE_UINT16 PXE_OPCODE; + +/// +/// Return UNDI operational state. +/// +#define PXE_OPCODE_GET_STATE 0x0000 + +/// +/// Change UNDI operational state from Stopped to Started. +/// +#define PXE_OPCODE_START 0x0001 + +/// +/// Change UNDI operational state from Started to Stopped. +/// +#define PXE_OPCODE_STOP 0x0002 + +/// +/// Get UNDI initialization information. +/// +#define PXE_OPCODE_GET_INIT_INFO 0x0003 + +/// +/// Get NIC configuration information. +/// +#define PXE_OPCODE_GET_CONFIG_INFO 0x0004 + +/// +/// Changed UNDI operational state from Started to Initialized. +/// +#define PXE_OPCODE_INITIALIZE 0x0005 + +/// +/// Re-initialize the NIC H/W. +/// +#define PXE_OPCODE_RESET 0x0006 + +/// +/// Change the UNDI operational state from Initialized to Started. +/// +#define PXE_OPCODE_SHUTDOWN 0x0007 + +/// +/// Read & change state of external interrupt enables. +/// +#define PXE_OPCODE_INTERRUPT_ENABLES 0x0008 + +/// +/// Read & change state of packet receive filters. +/// +#define PXE_OPCODE_RECEIVE_FILTERS 0x0009 + +/// +/// Read & change station MAC address. +/// +#define PXE_OPCODE_STATION_ADDRESS 0x000A + +/// +/// Read traffic statistics. +/// +#define PXE_OPCODE_STATISTICS 0x000B + +/// +/// Convert multicast IP address to multicast MAC address. +/// +#define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C + +/// +/// Read or change non-volatile storage on the NIC. +/// +#define PXE_OPCODE_NVDATA 0x000D + +/// +/// Get & clear interrupt status. +/// +#define PXE_OPCODE_GET_STATUS 0x000E + +/// +/// Fill media header in packet for transmit. +/// +#define PXE_OPCODE_FILL_HEADER 0x000F + +/// +/// Transmit packet(s). +/// +#define PXE_OPCODE_TRANSMIT 0x0010 + +/// +/// Receive packet. +/// +#define PXE_OPCODE_RECEIVE 0x0011 + +/// +/// Last valid PXE UNDI OpCode number. +/// +#define PXE_OPCODE_LAST_VALID 0x0011 + +typedef PXE_UINT16 PXE_OPFLAGS; + +#define PXE_OPFLAGS_NOT_USED 0x0000 + +// +// ////////////////////////////////////// +// UNDI Get State +// +// No OpFlags + +//////////////////////////////////////// +// UNDI Start +// +// No OpFlags + +//////////////////////////////////////// +// UNDI Stop +// +// No OpFlags + +//////////////////////////////////////// +// UNDI Get Init Info +// +// No Opflags + +//////////////////////////////////////// +// UNDI Get Config Info +// +// No Opflags + +/// +/// UNDI Initialize +/// +#define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001 +#define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000 +#define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001 + +/// +/// +/// UNDI Reset +/// +#define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001 +#define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002 + +/// +/// UNDI Shutdown. +/// +/// No OpFlags. + +/// +/// UNDI Interrupt Enables. +/// +/// +/// Select whether to enable or disable external interrupt signals. +/// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS. +/// +#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000 +#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000 +#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000 +#define PXE_OPFLAGS_INTERRUPT_READ 0x0000 + +/// +/// Enable receive interrupts. An external interrupt will be generated +/// after a complete non-error packet has been received. +/// +#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001 + +/// +/// Enable transmit interrupts. An external interrupt will be generated +/// after a complete non-error packet has been transmitted. +/// +#define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002 + +/// +/// Enable command interrupts. An external interrupt will be generated +/// when command execution stops. +/// +#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004 + +/// +/// Generate software interrupt. Setting this bit generates an external +/// interrupt, if it is supported by the hardware. +/// +#define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008 + +/// +/// UNDI Receive Filters. +/// +/// +/// Select whether to enable or disable receive filters. +/// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE. +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000 +#define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000 +#define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000 +#define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000 + +/// +/// To reset the contents of the multicast MAC address filter list, +/// set this OpFlag: +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000 + +/// +/// Enable unicast packet receiving. Packets sent to the current station +/// MAC address will be received. +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001 + +/// +/// Enable broadcast packet receiving. Packets sent to the broadcast +/// MAC address will be received. +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 + +/// +/// Enable filtered multicast packet receiving. Packets sent to any +/// of the multicast MAC addresses in the multicast MAC address filter +/// list will be received. If the filter list is empty, no multicast +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 + +/// +/// Enable promiscuous packet receiving. All packets will be received. +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 + +/// +/// Enable promiscuous multicast packet receiving. All multicast +/// packets will be received. +/// +#define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 + +/// +/// UNDI Station Address. +/// +#define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000 +#define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000 +#define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001 + +/// +/// UNDI Statistics. +/// +#define PXE_OPFLAGS_STATISTICS_READ 0x0000 +#define PXE_OPFLAGS_STATISTICS_RESET 0x0001 + +/// +/// UNDI MCast IP to MAC. +/// +/// +/// Identify the type of IP address in the CPB. +/// +#define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003 +#define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000 +#define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001 + +/// +/// UNDI NvData. +/// +/// +/// Select the type of non-volatile data operation. +/// +#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001 +#define PXE_OPFLAGS_NVDATA_READ 0x0000 +#define PXE_OPFLAGS_NVDATA_WRITE 0x0001 + +/// +/// UNDI Get Status. +/// +/// +/// Return current interrupt status. This will also clear any interrupts +/// that are currently set. This can be used in a polling routine. The +/// interrupt flags are still set and cleared even when the interrupts +/// are disabled. +/// +#define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001 + +/// +/// Return list of transmitted buffers for recycling. Transmit buffers +/// must not be changed or unallocated until they have recycled. After +/// issuing a transmit command, wait for a transmit complete interrupt. +/// When a transmit complete interrupt is received, read the transmitted +/// buffers. Do not plan on getting one buffer per interrupt. Some +/// NICs and UNDIs may transmit multiple buffers per interrupt. +/// +#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002 + +/// +/// Return current media status. +/// +#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004 + +/// +/// UNDI Fill Header. +/// +#define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001 +#define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001 +#define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000 + +/// +/// UNDI Transmit. +/// +/// +/// S/W UNDI only. Return after the packet has been transmitted. A +/// transmit complete interrupt will still be generated and the transmit +/// buffer will have to be recycled. +/// +#define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001 +#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001 +#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000 + +#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002 +#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002 +#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000 + +/// +/// UNDI Receive. +/// +/// No OpFlags. +/// + +/// +/// PXE STATFLAGS. +/// +typedef PXE_UINT16 PXE_STATFLAGS; + +#define PXE_STATFLAGS_INITIALIZE 0x0000 + +/// +/// Common StatFlags that can be returned by all commands. +/// +/// +/// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be +/// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs +/// that support command queuing. +/// +#define PXE_STATFLAGS_STATUS_MASK 0xC000 +#define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000 +#define PXE_STATFLAGS_COMMAND_FAILED 0x8000 +#define PXE_STATFLAGS_COMMAND_QUEUED 0x4000 + +/// +/// UNDI Get State. +/// +#define PXE_STATFLAGS_GET_STATE_MASK 0x0003 +#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002 +#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001 +#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000 + +/// +/// UNDI Start. +/// +/// No additional StatFlags. +/// + +/// +/// UNDI Get Init Info. +/// +#define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001 +#define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000 +#define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001 + +#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002 +#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000 +#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002 + +/// +/// UNDI Initialize. +/// +#define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001 + +/// +/// UNDI Reset. +/// +#define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001 + +/// +/// UNDI Shutdown. +/// +/// No additional StatFlags. + +/// +/// UNDI Interrupt Enables. +/// +/// +/// If set, receive interrupts are enabled. +/// +#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001 + +/// +/// If set, transmit interrupts are enabled. +/// +#define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002 + +/// +/// If set, command interrupts are enabled. +/// +#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004 + +/// +/// UNDI Receive Filters. +/// + +/// +/// If set, unicast packets will be received. +/// +#define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001 + +/// +/// If set, broadcast packets will be received. +/// +#define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 + +/// +/// If set, multicast packets that match up with the multicast address +/// filter list will be received. +/// +#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 + +/// +/// If set, all packets will be received. +/// +#define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 + +/// +/// If set, all multicast packets will be received. +/// +#define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 + +/// +/// UNDI Station Address. +/// +/// No additional StatFlags. +/// + +/// +/// UNDI Statistics. +/// +/// No additional StatFlags. +/// + +/// +//// UNDI MCast IP to MAC. +//// +//// No additional StatFlags. + +/// +/// UNDI NvData. +/// +/// No additional StatFlags. +/// + +/// +/// UNDI Get Status. +/// + +/// +/// Use to determine if an interrupt has occurred. +/// +#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F +#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000 + +/// +/// If set, at least one receive interrupt occurred. +/// +#define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001 + +/// +/// If set, at least one transmit interrupt occurred. +/// +#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002 + +/// +/// If set, at least one command interrupt occurred. +/// +#define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004 + +/// +/// If set, at least one software interrupt occurred. +/// +#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008 + +/// +/// This flag is set if the transmitted buffer queue is empty. This flag +/// will be set if all transmitted buffer addresses get written into the DB. +/// +#define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010 + +/// +/// This flag is set if no transmitted buffer addresses were written +/// into the DB. (This could be because DBsize was too small.) +/// +#define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020 + +/// +/// This flag is set if there is no media detected. +/// +#define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040 + +/// +/// UNDI Fill Header. +/// +/// No additional StatFlags. +/// + +/// +/// UNDI Transmit. +/// +/// No additional StatFlags. + +/// +/// UNDI Receive +///. + +/// +/// No additional StatFlags. +/// +typedef PXE_UINT16 PXE_STATCODE; + +#define PXE_STATCODE_INITIALIZE 0x0000 + +/// +/// Common StatCodes returned by all UNDI commands, UNDI protocol functions +/// and BC protocol functions. +/// +#define PXE_STATCODE_SUCCESS 0x0000 + +#define PXE_STATCODE_INVALID_CDB 0x0001 +#define PXE_STATCODE_INVALID_CPB 0x0002 +#define PXE_STATCODE_BUSY 0x0003 +#define PXE_STATCODE_QUEUE_FULL 0x0004 +#define PXE_STATCODE_ALREADY_STARTED 0x0005 +#define PXE_STATCODE_NOT_STARTED 0x0006 +#define PXE_STATCODE_NOT_SHUTDOWN 0x0007 +#define PXE_STATCODE_ALREADY_INITIALIZED 0x0008 +#define PXE_STATCODE_NOT_INITIALIZED 0x0009 +#define PXE_STATCODE_DEVICE_FAILURE 0x000A +#define PXE_STATCODE_NVDATA_FAILURE 0x000B +#define PXE_STATCODE_UNSUPPORTED 0x000C +#define PXE_STATCODE_BUFFER_FULL 0x000D +#define PXE_STATCODE_INVALID_PARAMETER 0x000E +#define PXE_STATCODE_INVALID_UNDI 0x000F +#define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010 +#define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011 +#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012 +#define PXE_STATCODE_NO_DATA 0x0013 + +typedef PXE_UINT16 PXE_IFNUM; + +/// +/// This interface number must be passed to the S/W UNDI Start command. +/// +#define PXE_IFNUM_START 0x0000 + +/// +/// This interface number is returned by the S/W UNDI Get State and +/// Start commands if information in the CDB, CPB or DB is invalid. +/// +#define PXE_IFNUM_INVALID 0x0000 + +typedef PXE_UINT16 PXE_CONTROL; + +/// +/// Setting this flag directs the UNDI to queue this command for later +/// execution if the UNDI is busy and it supports command queuing. +/// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error +/// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL +/// error is returned. +/// +#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002 + +/// +/// These two bit values are used to determine if there are more UNDI +/// CDB structures following this one. If the link bit is set, there +/// must be a CDB structure following this one. Execution will start +/// on the next CDB structure as soon as this one completes successfully. +/// If an error is generated by this command, execution will stop. +/// +#define PXE_CONTROL_LINK 0x0001 +#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000 + +typedef PXE_UINT8 PXE_FRAME_TYPE; + +#define PXE_FRAME_TYPE_NONE 0x00 +#define PXE_FRAME_TYPE_UNICAST 0x01 +#define PXE_FRAME_TYPE_BROADCAST 0x02 +#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03 +#define PXE_FRAME_TYPE_PROMISCUOUS 0x04 +#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05 + +#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST + +typedef PXE_UINT32 PXE_IPV4; + +typedef PXE_UINT32 PXE_IPV6[4]; +#define PXE_MAC_LENGTH 32 + +typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH]; + +typedef PXE_UINT8 PXE_IFTYPE; +typedef UINT16 PXE_MEDIA_PROTOCOL; + +/// +/// This information is from the ARP section of RFC 1700. +/// +/// 1 Ethernet (10Mb) [JBP] +/// 2 Experimental Ethernet (3Mb) [JBP] +/// 3 Amateur Radio AX.25 [PXK] +/// 4 Proteon ProNET Token Ring [JBP] +/// 5 Chaos [GXP] +/// 6 IEEE 802 Networks [JBP] +/// 7 ARCNET [JBP] +/// 8 Hyperchannel [JBP] +/// 9 Lanstar [TU] +/// 10 Autonet Short Address [MXB1] +/// 11 LocalTalk [JKR1] +/// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM] +/// 13 Ultra link [RXD2] +/// 14 SMDS [GXC1] +/// 15 Frame Relay [AGM] +/// 16 Asynchronous Transmission Mode (ATM) [JXB2] +/// 17 HDLC [JBP] +/// 18 Fibre Channel [Yakov Rekhter] +/// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach] +/// 20 Serial Line [JBP] +/// 21 Asynchronous Transmission Mode (ATM) [MXB1] +/// +/// * Other names and brands may be claimed as the property of others. +/// +#define PXE_IFTYPE_ETHERNET 0x01 +#define PXE_IFTYPE_TOKENRING 0x04 +#define PXE_IFTYPE_FIBRE_CHANNEL 0x12 + +typedef struct s_pxe_hw_undi { + PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE. + PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI). + PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero. + PXE_UINT8 Rev; ///< PXE_ROMID_REV. + PXE_UINT8 IFcnt; ///< physical connector count lower byte. + PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER. + PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER. + PXE_UINT8 IFcntExt; ///< physical connector count upper byte. + PXE_UINT8 reserved; ///< zero, not used. + PXE_UINT32 Implementation; ///< implementation flags. + ///< reserved ///< vendor use. + ///< UINT32 Status; ///< status port. + ///< UINT32 Command; ///< command port. + ///< UINT64 CDBaddr; ///< CDB address port. + ///< +} PXE_HW_UNDI; + +/// +/// Status port bit definitions. +/// + +/// +/// UNDI operation state. +/// +#define PXE_HWSTAT_STATE_MASK 0xC0000000 +#define PXE_HWSTAT_BUSY 0xC0000000 +#define PXE_HWSTAT_INITIALIZED 0x80000000 +#define PXE_HWSTAT_STARTED 0x40000000 +#define PXE_HWSTAT_STOPPED 0x00000000 + +/// +/// If set, last command failed. +/// +#define PXE_HWSTAT_COMMAND_FAILED 0x20000000 + +/// +/// If set, identifies enabled receive filters. +/// +#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000 +#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800 +#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400 +#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200 +#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100 + +/// +/// If set, identifies enabled external interrupts. +/// +#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080 +#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040 +#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020 +#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010 + +/// +/// If set, identifies pending interrupts. +/// +#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008 +#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004 +#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002 +#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001 + +/// +/// Command port definitions. +/// + +/// +/// If set, CDB identified in CDBaddr port is given to UNDI. +/// If not set, other bits in this word will be processed. +/// +#define PXE_HWCMD_ISSUE_COMMAND 0x80000000 +#define PXE_HWCMD_INTS_AND_FILTS 0x00000000 + +/// +/// Use these to enable/disable receive filters. +/// +#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000 +#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800 +#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400 +#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200 +#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100 + +/// +/// Use these to enable/disable external interrupts. +/// +#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080 +#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040 +#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020 +#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010 + +/// +/// Use these to clear pending external interrupts. +/// +#define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008 +#define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004 +#define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002 +#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001 + +typedef struct s_pxe_sw_undi { + PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE. + PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI). + PXE_UINT8 Fudge; ///< makes 8-bit cksum zero. + PXE_UINT8 Rev; ///< PXE_ROMID_REV. + PXE_UINT8 IFcnt; ///< physical connector count lower byte. + PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER. + PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER. + PXE_UINT8 IFcntExt; ///< physical connector count upper byte. + PXE_UINT8 reserved1; ///< zero, not used. + PXE_UINT32 Implementation; ///< Implementation flags. + PXE_UINT64 EntryPoint; ///< API entry point. + PXE_UINT8 reserved2[3]; ///< zero, not used. + PXE_UINT8 BusCnt; ///< number of bustypes supported. + PXE_UINT32 BusType[1]; ///< list of supported bustypes. +} PXE_SW_UNDI; + +typedef union u_pxe_undi { + PXE_HW_UNDI hw; + PXE_SW_UNDI sw; +} PXE_UNDI; + +/// +/// Signature of !PXE structure. +/// +#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E') + +/// +/// !PXE structure format revision +///. +#define PXE_ROMID_REV 0x02 + +/// +/// UNDI command interface revision. These are the values that get sent +/// in option 94 (Client Network Interface Identifier) in the DHCP Discover +/// and PXE Boot Server Request packets. +/// +#define PXE_ROMID_MAJORVER 0x03 +#define PXE_ROMID_MINORVER 0x01 + +/// +/// Implementation flags. +/// +#define PXE_ROMID_IMP_HW_UNDI 0x80000000 +#define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000 +#define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000 +#define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000 +#define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000 +#define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000 +#define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000 +#define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00 +#define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00 +#define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800 +#define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400 +#define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000 +#define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200 +#define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100 +#define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080 +#define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040 +#define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020 +#define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010 +#define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008 +#define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004 +#define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002 +#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001 + +typedef struct s_pxe_cdb { + PXE_OPCODE OpCode; + PXE_OPFLAGS OpFlags; + PXE_UINT16 CPBsize; + PXE_UINT16 DBsize; + PXE_UINT64 CPBaddr; + PXE_UINT64 DBaddr; + PXE_STATCODE StatCode; + PXE_STATFLAGS StatFlags; + PXE_UINT16 IFnum; + PXE_CONTROL Control; +} PXE_CDB; + +typedef union u_pxe_ip_addr { + PXE_IPV6 IPv6; + PXE_IPV4 IPv4; +} PXE_IP_ADDR; + +typedef union pxe_device { + /// + /// PCI and PC Card NICs are both identified using bus, device + /// and function numbers. For PC Card, this may require PC + /// Card services to be loaded in the BIOS or preboot + /// environment. + /// + struct { + /// + /// See S/W UNDI ROMID structure definition for PCI and + /// PCC BusType definitions. + /// + PXE_UINT32 BusType; + + /// + /// Bus, device & function numbers that locate this device. + /// + PXE_UINT16 Bus; + PXE_UINT8 Device; + PXE_UINT8 Function; + } + PCI, PCC; + +} PXE_DEVICE; + +/// +/// cpb and db definitions +/// +#define MAX_PCI_CONFIG_LEN 64 ///< # of dwords. +#define MAX_EEPROM_LEN 128 ///< # of dwords. +#define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done. +#define MAX_MCAST_ADDRESS_CNT 8 + +typedef struct s_pxe_cpb_start_30 { + /// + /// PXE_VOID Delay(UINTN microseconds); + /// + /// UNDI will never request a delay smaller than 10 microseconds + /// and will always request delays in increments of 10 microseconds. + /// The Delay() CallBack routine must delay between n and n + 10 + /// microseconds before returning control to the UNDI. + /// + /// This field cannot be set to zero. + /// + UINT64 Delay; + + /// + /// PXE_VOID Block(UINT32 enable); + /// + /// UNDI may need to block multi-threaded/multi-processor access to + /// critical code sections when programming or accessing the network + /// device. To this end, a blocking service is needed by the UNDI. + /// When UNDI needs a block, it will call Block() passing a non-zero + /// value. When UNDI no longer needs a block, it will call Block() + /// with a zero value. When called, if the Block() is already enabled, + /// do not return control to the UNDI until the previous Block() is + /// disabled. + /// + /// This field cannot be set to zero. + /// + UINT64 Block; + + /// + /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr); + /// + /// UNDI will pass the virtual address of a buffer and the virtual + /// address of a 64-bit physical buffer. Convert the virtual address + /// to a physical address and write the result to the physical address + /// buffer. If virtual and physical addresses are the same, just + /// copy the virtual address to the physical address buffer. + /// + /// This field can be set to zero if virtual and physical addresses + /// are equal. + /// + UINT64 Virt2Phys; + /// + /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port, + /// UINT64 buf_addr); + /// + /// UNDI will read or write the device io space using this call back + /// function. It passes the number of bytes as the len parameter and it + /// will be either 1,2,4 or 8. + /// + /// This field can not be set to zero. + /// + UINT64 Mem_IO; +} PXE_CPB_START_30; + +typedef struct s_pxe_cpb_start_31 { + /// + /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds); + /// + /// UNDI will never request a delay smaller than 10 microseconds + /// and will always request delays in increments of 10 microseconds. + /// The Delay() CallBack routine must delay between n and n + 10 + /// microseconds before returning control to the UNDI. + /// + /// This field cannot be set to zero. + /// + UINT64 Delay; + + /// + /// PXE_VOID Block(UINT64 unq_id, UINT32 enable); + /// + /// UNDI may need to block multi-threaded/multi-processor access to + /// critical code sections when programming or accessing the network + /// device. To this end, a blocking service is needed by the UNDI. + /// When UNDI needs a block, it will call Block() passing a non-zero + /// value. When UNDI no longer needs a block, it will call Block() + /// with a zero value. When called, if the Block() is already enabled, + /// do not return control to the UNDI until the previous Block() is + /// disabled. + /// + /// This field cannot be set to zero. + /// + UINT64 Block; + + /// + /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr); + /// + /// UNDI will pass the virtual address of a buffer and the virtual + /// address of a 64-bit physical buffer. Convert the virtual address + /// to a physical address and write the result to the physical address + /// buffer. If virtual and physical addresses are the same, just + /// copy the virtual address to the physical address buffer. + /// + /// This field can be set to zero if virtual and physical addresses + /// are equal. + /// + UINT64 Virt2Phys; + /// + /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port, + /// UINT64 buf_addr); + /// + /// UNDI will read or write the device io space using this call back + /// function. It passes the number of bytes as the len parameter and it + /// will be either 1,2,4 or 8. + /// + /// This field can not be set to zero. + /// + UINT64 Mem_IO; + /// + /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size, + /// UINT32 Direction, UINT64 mapped_addr); + /// + /// UNDI will pass the virtual address of a buffer, direction of the data + /// flow from/to the mapped buffer (the constants are defined below) + /// and a place holder (pointer) for the mapped address. + /// This call will Map the given address to a physical DMA address and write + /// the result to the mapped_addr pointer. If there is no need to + /// map the given address to a lower address (i.e. the given address is + /// associated with a physical address that is already compatible to be + /// used with the DMA, it converts the given virtual address to it's + /// physical address and write that in the mapped address pointer. + /// + /// This field can be set to zero if there is no mapping service available. + /// + UINT64 Map_Mem; + + /// + /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size, + /// UINT32 Direction, UINT64 mapped_addr); + /// + /// UNDI will pass the virtual and mapped addresses of a buffer. + /// This call will un map the given address. + /// + /// This field can be set to zero if there is no unmapping service available. + /// + UINT64 UnMap_Mem; + + /// + /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual, + /// UINT32 size, UINT32 Direction, UINT64 mapped_addr); + /// + /// UNDI will pass the virtual and mapped addresses of a buffer. + /// This call will synchronize the contents of both the virtual and mapped. + /// buffers for the given Direction. + /// + /// This field can be set to zero if there is no service available. + /// + UINT64 Sync_Mem; + + /// + /// protocol driver can provide anything for this Unique_ID, UNDI remembers + /// that as just a 64bit value associated to the interface specified by + /// the ifnum and gives it back as a parameter to all the call-back routines + /// when calling for that interface! + /// + UINT64 Unique_ID; +} PXE_CPB_START_31; + +#define TO_AND_FROM_DEVICE 0 +#define FROM_DEVICE 1 +#define TO_DEVICE 2 + +#define PXE_DELAY_MILLISECOND 1000 +#define PXE_DELAY_SECOND 1000000 +#define PXE_IO_READ 0 +#define PXE_IO_WRITE 1 +#define PXE_MEM_READ 2 +#define PXE_MEM_WRITE 4 + +typedef struct s_pxe_db_get_init_info { + /// + /// Minimum length of locked memory buffer that must be given to + /// the Initialize command. Giving UNDI more memory will generally + /// give better performance. + /// + /// If MemoryRequired is zero, the UNDI does not need and will not + /// use system memory to receive and transmit packets. + /// + PXE_UINT32 MemoryRequired; + + /// + /// Maximum frame data length for Tx/Rx excluding the media header. + /// + PXE_UINT32 FrameDataLen; + + /// + /// Supported link speeds are in units of mega bits. Common ethernet + /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero + /// filled. + /// + PXE_UINT32 LinkSpeeds[4]; + + /// + /// Number of non-volatile storage items. + /// + PXE_UINT32 NvCount; + + /// + /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4 + /// + PXE_UINT16 NvWidth; + + /// + /// Media header length. This is the typical media header length for + /// this UNDI. This information is needed when allocating receive + /// and transmit buffers. + /// + PXE_UINT16 MediaHeaderLen; + + /// + /// Number of bytes in the NIC hardware (MAC) address. + /// + PXE_UINT16 HWaddrLen; + + /// + /// Maximum number of multicast MAC addresses in the multicast + /// MAC address filter list. + /// + PXE_UINT16 MCastFilterCnt; + + /// + /// Default number and size of transmit and receive buffers that will + /// be allocated by the UNDI. If MemoryRequired is non-zero, this + /// allocation will come out of the memory buffer given to the Initialize + /// command. If MemoryRequired is zero, this allocation will come out of + /// memory on the NIC. + /// + PXE_UINT16 TxBufCnt; + PXE_UINT16 TxBufSize; + PXE_UINT16 RxBufCnt; + PXE_UINT16 RxBufSize; + + /// + /// Hardware interface types defined in the Assigned Numbers RFC + /// and used in DHCP and ARP packets. + /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros. + /// + PXE_UINT8 IFtype; + + /// + /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below. + /// + PXE_UINT8 SupportedDuplexModes; + + /// + /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below. + /// + PXE_UINT8 SupportedLoopBackModes; +} PXE_DB_GET_INIT_INFO; + +#define PXE_MAX_TXRX_UNIT_ETHER 1500 + +#define PXE_HWADDR_LEN_ETHER 0x0006 +#define PXE_MAC_HEADER_LEN_ETHER 0x000E + +#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1 +#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2 + +#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1 +#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2 + +typedef struct s_pxe_pci_config_info { + /// + /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union. + /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI. + /// + UINT32 BusType; + + /// + /// This identifies the PCI network device that this UNDI interface. + /// is bound to. + /// + UINT16 Bus; + UINT8 Device; + UINT8 Function; + + /// + /// This is a copy of the PCI configuration space for this + /// network device. + /// + union { + UINT8 Byte[256]; + UINT16 Word[128]; + UINT32 Dword[64]; + } Config; +} PXE_PCI_CONFIG_INFO; + +typedef struct s_pxe_pcc_config_info { + /// + /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union. + /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC. + /// + PXE_UINT32 BusType; + + /// + /// This identifies the PCC network device that this UNDI interface + /// is bound to. + /// + PXE_UINT16 Bus; + PXE_UINT8 Device; + PXE_UINT8 Function; + + /// + /// This is a copy of the PCC configuration space for this + /// network device. + /// + union { + PXE_UINT8 Byte[256]; + PXE_UINT16 Word[128]; + PXE_UINT32 Dword[64]; + } Config; +} PXE_PCC_CONFIG_INFO; + +typedef union u_pxe_db_get_config_info { + PXE_PCI_CONFIG_INFO pci; + PXE_PCC_CONFIG_INFO pcc; +} PXE_DB_GET_CONFIG_INFO; + +typedef struct s_pxe_cpb_initialize { + /// + /// Address of first (lowest) byte of the memory buffer. This buffer must + /// be in contiguous physical memory and cannot be swapped out. The UNDI + /// will be using this for transmit and receive buffering. + /// + PXE_UINT64 MemoryAddr; + + /// + /// MemoryLength must be greater than or equal to MemoryRequired + /// returned by the Get Init Info command. + /// + PXE_UINT32 MemoryLength; + + /// + /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100 + /// and 1000. Setting a value of zero will auto-detect and/or use the + /// default link speed (operation depends on UNDI/NIC functionality). + /// + PXE_UINT32 LinkSpeed; + + /// + /// Suggested number and size of receive and transmit buffers to + /// allocate. If MemoryAddr and MemoryLength are non-zero, this + /// allocation comes out of the supplied memory buffer. If MemoryAddr + /// and MemoryLength are zero, this allocation comes out of memory + /// on the NIC. + /// + /// If these fields are set to zero, the UNDI will allocate buffer + /// counts and sizes as it sees fit. + /// + PXE_UINT16 TxBufCnt; + PXE_UINT16 TxBufSize; + PXE_UINT16 RxBufCnt; + PXE_UINT16 RxBufSize; + + /// + /// The following configuration parameters are optional and must be zero + /// to use the default values. + /// + PXE_UINT8 DuplexMode; + + PXE_UINT8 LoopBackMode; +} PXE_CPB_INITIALIZE; + +#define PXE_DUPLEX_DEFAULT 0x00 +#define PXE_FORCE_FULL_DUPLEX 0x01 +#define PXE_ENABLE_FULL_DUPLEX 0x02 +#define PXE_FORCE_HALF_DUPLEX 0x04 +#define PXE_DISABLE_FULL_DUPLEX 0x08 + +#define LOOPBACK_NORMAL 0 +#define LOOPBACK_INTERNAL 1 +#define LOOPBACK_EXTERNAL 2 + +typedef struct s_pxe_db_initialize { + /// + /// Actual amount of memory used from the supplied memory buffer. This + /// may be less that the amount of memory suppllied and may be zero if + /// the UNDI and network device do not use external memory buffers. + /// + /// Memory used by the UNDI and network device is allocated from the + /// lowest memory buffer address. + /// + PXE_UINT32 MemoryUsed; + + /// + /// Actual number and size of receive and transmit buffers that were + /// allocated. + /// + PXE_UINT16 TxBufCnt; + PXE_UINT16 TxBufSize; + PXE_UINT16 RxBufCnt; + PXE_UINT16 RxBufSize; +} PXE_DB_INITIALIZE; + +typedef struct s_pxe_cpb_receive_filters { + /// + /// List of multicast MAC addresses. This list, if present, will + /// replace the existing multicast MAC address filter list. + /// + PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; +} PXE_CPB_RECEIVE_FILTERS; + +typedef struct s_pxe_db_receive_filters { + /// + /// Filtered multicast MAC address list. + /// + PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; +} PXE_DB_RECEIVE_FILTERS; + +typedef struct s_pxe_cpb_station_address { + /// + /// If supplied and supported, the current station MAC address + /// will be changed. + /// + PXE_MAC_ADDR StationAddr; +} PXE_CPB_STATION_ADDRESS; + +typedef struct s_pxe_dpb_station_address { + /// + /// Current station MAC address. + /// + PXE_MAC_ADDR StationAddr; + + /// + /// Station broadcast MAC address. + /// + PXE_MAC_ADDR BroadcastAddr; + + /// + /// Permanent station MAC address. + /// + PXE_MAC_ADDR PermanentAddr; +} PXE_DB_STATION_ADDRESS; + +typedef struct s_pxe_db_statistics { + /// + /// Bit field identifying what statistic data is collected by the + /// UNDI/NIC. + /// If bit 0x00 is set, Data[0x00] is collected. + /// If bit 0x01 is set, Data[0x01] is collected. + /// If bit 0x20 is set, Data[0x20] is collected. + /// If bit 0x21 is set, Data[0x21] is collected. + /// Etc. + /// + PXE_UINT64 Supported; + + /// + /// Statistic data. + /// + PXE_UINT64 Data[64]; +} PXE_DB_STATISTICS; + +/// +/// Total number of frames received. Includes frames with errors and +/// dropped frames. +/// +#define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00 + +/// +/// Number of valid frames received and copied into receive buffers. +/// +#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01 + +/// +/// Number of frames below the minimum length for the media. +/// This would be <64 for ethernet. +/// +#define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02 + +/// +/// Number of frames longer than the maxminum length for the +/// media. This would be >1500 for ethernet. +/// +#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03 + +/// +/// Valid frames that were dropped because receive buffers were full. +/// +#define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04 + +/// +/// Number of valid unicast frames received and not dropped. +/// +#define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05 + +/// +/// Number of valid broadcast frames received and not dropped. +/// +#define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06 + +/// +/// Number of valid mutlicast frames received and not dropped. +/// +#define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07 + +/// +/// Number of frames w/ CRC or alignment errors. +/// +#define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08 + +/// +/// Total number of bytes received. Includes frames with errors +/// and dropped frames. +/// +#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09 + +/// +/// Transmit statistics. +/// +#define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A +#define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B +#define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C +#define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D +#define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E +#define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F +#define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10 +#define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11 +#define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12 +#define PXE_STATISTICS_TX_TOTAL_BYTES 0x13 + +/// +/// Number of collisions detection on this subnet. +/// +#define PXE_STATISTICS_COLLISIONS 0x14 + +/// +/// Number of frames destined for unsupported protocol. +/// +#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15 + +/// +/// Number of valid frames received that were duplicated. +/// +#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16 + +/// +/// Number of encrypted frames received that failed to decrypt. +/// +#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17 + +/// +/// Number of frames that failed to transmit after exceeding the retry limit. +/// +#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18 + +/// +/// Number of frames transmitted successfully after more than one attempt. +/// +#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19 + +typedef struct s_pxe_cpb_mcast_ip_to_mac { + /// + /// Multicast IP address to be converted to multicast MAC address. + /// + PXE_IP_ADDR IP; +} PXE_CPB_MCAST_IP_TO_MAC; + +typedef struct s_pxe_db_mcast_ip_to_mac { + /// + /// Multicast MAC address. + /// + PXE_MAC_ADDR MAC; +} PXE_DB_MCAST_IP_TO_MAC; + +typedef struct s_pxe_cpb_nvdata_sparse { + /// + /// NvData item list. Only items in this list will be updated. + /// + struct { + /// + /// Non-volatile storage address to be changed. + /// + PXE_UINT32 Addr; + + /// + /// Data item to write into above storage address. + /// + union { + PXE_UINT8 Byte; + PXE_UINT16 Word; + PXE_UINT32 Dword; + } Data; + } Item[MAX_EEPROM_LEN]; +} PXE_CPB_NVDATA_SPARSE; + +/// +/// When using bulk update, the size of the CPB structure must be +/// the same size as the non-volatile NIC storage. +/// +typedef union u_pxe_cpb_nvdata_bulk { + /// + /// Array of byte-wide data items. + /// + PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; + + /// + /// Array of word-wide data items. + /// + PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; + + /// + /// Array of dword-wide data items. + /// + PXE_UINT32 Dword[MAX_EEPROM_LEN]; +} PXE_CPB_NVDATA_BULK; + +typedef struct s_pxe_db_nvdata { + /// + /// Arrays of data items from non-volatile storage. + /// + union { + /// + /// Array of byte-wide data items. + /// + PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; + + /// + /// Array of word-wide data items. + /// + PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; + + /// + /// Array of dword-wide data items. + /// + PXE_UINT32 Dword[MAX_EEPROM_LEN]; + } Data; +} PXE_DB_NVDATA; + +typedef struct s_pxe_db_get_status { + /// + /// Length of next receive frame (header + data). If this is zero, + /// there is no next receive frame available. + /// + PXE_UINT32 RxFrameLen; + + /// + /// Reserved, set to zero. + /// + PXE_UINT32 reserved; + + /// + /// Addresses of transmitted buffers that need to be recycled. + /// + PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS]; +} PXE_DB_GET_STATUS; + +typedef struct s_pxe_cpb_fill_header { + /// + /// Source and destination MAC addresses. These will be copied into + /// the media header without doing byte swapping. + /// + PXE_MAC_ADDR SrcAddr; + PXE_MAC_ADDR DestAddr; + + /// + /// Address of first byte of media header. The first byte of packet data + /// follows the last byte of the media header. + /// + PXE_UINT64 MediaHeader; + + /// + /// Length of packet data in bytes (not including the media header). + /// + PXE_UINT32 PacketLen; + + /// + /// Protocol type. This will be copied into the media header without + /// doing byte swapping. Protocol type numbers can be obtained from + /// the Assigned Numbers RFC 1700. + /// + PXE_UINT16 Protocol; + + /// + /// Length of the media header in bytes. + /// + PXE_UINT16 MediaHeaderLen; +} PXE_CPB_FILL_HEADER; + +#define PXE_PROTOCOL_ETHERNET_IP 0x0800 +#define PXE_PROTOCOL_ETHERNET_ARP 0x0806 +#define MAX_XMIT_FRAGMENTS 16 + +typedef struct s_pxe_cpb_fill_header_fragmented { + /// + /// Source and destination MAC addresses. These will be copied into + /// the media header without doing byte swapping. + /// + PXE_MAC_ADDR SrcAddr; + PXE_MAC_ADDR DestAddr; + + /// + /// Length of packet data in bytes (not including the media header). + /// + PXE_UINT32 PacketLen; + + /// + /// Protocol type. This will be copied into the media header without + /// doing byte swapping. Protocol type numbers can be obtained from + /// the Assigned Numbers RFC 1700. + /// + PXE_MEDIA_PROTOCOL Protocol; + + /// + /// Length of the media header in bytes. + /// + PXE_UINT16 MediaHeaderLen; + + /// + /// Number of packet fragment descriptors. + /// + PXE_UINT16 FragCnt; + + /// + /// Reserved, must be set to zero. + /// + PXE_UINT16 reserved; + + /// + /// Array of packet fragment descriptors. The first byte of the media + /// header is the first byte of the first fragment. + /// + struct { + /// + /// Address of this packet fragment. + /// + PXE_UINT64 FragAddr; + + /// + /// Length of this packet fragment. + /// + PXE_UINT32 FragLen; + + /// + /// Reserved, must be set to zero. + /// + PXE_UINT32 reserved; + } FragDesc[MAX_XMIT_FRAGMENTS]; +} +PXE_CPB_FILL_HEADER_FRAGMENTED; + +typedef struct s_pxe_cpb_transmit { + /// + /// Address of first byte of frame buffer. This is also the first byte + /// of the media header. + /// + PXE_UINT64 FrameAddr; + + /// + /// Length of the data portion of the frame buffer in bytes. Do not + /// include the length of the media header. + /// + PXE_UINT32 DataLen; + + /// + /// Length of the media header in bytes. + /// + PXE_UINT16 MediaheaderLen; + + /// + /// Reserved, must be zero. + /// + PXE_UINT16 reserved; +} PXE_CPB_TRANSMIT; + +typedef struct s_pxe_cpb_transmit_fragments { + /// + /// Length of packet data in bytes (not including the media header). + /// + PXE_UINT32 FrameLen; + + /// + /// Length of the media header in bytes. + /// + PXE_UINT16 MediaheaderLen; + + /// + /// Number of packet fragment descriptors. + /// + PXE_UINT16 FragCnt; + + /// + /// Array of frame fragment descriptors. The first byte of the first + /// fragment is also the first byte of the media header. + /// + struct { + /// + /// Address of this frame fragment. + /// + PXE_UINT64 FragAddr; + + /// + /// Length of this frame fragment. + /// + PXE_UINT32 FragLen; + + /// + /// Reserved, must be set to zero. + /// + PXE_UINT32 reserved; + } FragDesc[MAX_XMIT_FRAGMENTS]; +} +PXE_CPB_TRANSMIT_FRAGMENTS; + +typedef struct s_pxe_cpb_receive { + /// + /// Address of first byte of receive buffer. This is also the first byte + /// of the frame header. + /// + PXE_UINT64 BufferAddr; + + /// + /// Length of receive buffer. This must be large enough to hold the + /// received frame (media header + data). If the length of smaller than + /// the received frame, data will be lost. + /// + PXE_UINT32 BufferLen; + + /// + /// Reserved, must be set to zero. + /// + PXE_UINT32 reserved; +} PXE_CPB_RECEIVE; + +typedef struct s_pxe_db_receive { + /// + /// Source and destination MAC addresses from media header. + /// + PXE_MAC_ADDR SrcAddr; + PXE_MAC_ADDR DestAddr; + + /// + /// Length of received frame. May be larger than receive buffer size. + /// The receive buffer will not be overwritten. This is how to tell + /// if data was lost because the receive buffer was too small. + /// + PXE_UINT32 FrameLen; + + /// + /// Protocol type from media header. + /// + PXE_MEDIA_PROTOCOL Protocol; + + /// + /// Length of media header in received frame. + /// + PXE_UINT16 MediaHeaderLen; + + /// + /// Type of receive frame. + /// + PXE_FRAME_TYPE Type; + + /// + /// Reserved, must be zero. + /// + PXE_UINT8 reserved[7]; + +} PXE_DB_RECEIVE; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiSpec.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiSpec.h new file mode 100644 index 0000000000..54639be437 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Uefi/UefiSpec.h @@ -0,0 +1,2240 @@ +/** @file + Include file that supports UEFI. + + This include file must contain things defined in the UEFI 2.7 specification. + If a code construct is defined in the UEFI 2.7 specification it must be included + by this include file. + +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __UEFI_SPEC_H__ +#define __UEFI_SPEC_H__ + +#include + +#include +#include +#include +#include + +/// +/// Enumeration of EFI memory allocation types. +/// +typedef enum { + /// + /// Allocate any available range of pages that satisfies the request. + /// + AllocateAnyPages, + /// + /// Allocate any available range of pages whose uppermost address is less than + /// or equal to a specified maximum address. + /// + AllocateMaxAddress, + /// + /// Allocate pages at a specified address. + /// + AllocateAddress, + /// + /// Maximum enumeration value that may be used for bounds checking. + /// + MaxAllocateType +} EFI_ALLOCATE_TYPE; + +// +// Bit definitions for EFI_TIME.Daylight +// +#define EFI_TIME_ADJUST_DAYLIGHT 0x01 +#define EFI_TIME_IN_DAYLIGHT 0x02 + +/// +/// Value definition for EFI_TIME.TimeZone. +/// +#define EFI_UNSPECIFIED_TIMEZONE 0x07FF + +// +// Memory cacheability attributes +// +#define EFI_MEMORY_UC 0x0000000000000001ULL +#define EFI_MEMORY_WC 0x0000000000000002ULL +#define EFI_MEMORY_WT 0x0000000000000004ULL +#define EFI_MEMORY_WB 0x0000000000000008ULL +#define EFI_MEMORY_UCE 0x0000000000000010ULL +// +// Physical memory protection attributes +// +// Note: UEFI spec 2.5 and following: use EFI_MEMORY_RO as write-protected physical memory +// protection attribute. Also, EFI_MEMORY_WP means cacheability attribute. +// +#define EFI_MEMORY_WP 0x0000000000001000ULL +#define EFI_MEMORY_RP 0x0000000000002000ULL +#define EFI_MEMORY_XP 0x0000000000004000ULL +#define EFI_MEMORY_RO 0x0000000000020000ULL +// +// Physical memory persistence attribute. +// The memory region supports byte-addressable non-volatility. +// +#define EFI_MEMORY_NV 0x0000000000008000ULL +// +// The memory region provides higher reliability relative to other memory in the system. +// If all memory has the same reliability, then this bit is not used. +// +#define EFI_MEMORY_MORE_RELIABLE 0x0000000000010000ULL + +// +// Note: UEFI spec 2.8 and following: +// +// Specific-purpose memory (SPM). The memory is earmarked for +// specific purposes such as for specific device drivers or applications. +// The SPM attribute serves as a hint to the OS to avoid allocating this +// memory for core OS data or code that can not be relocated. +// +#define EFI_MEMORY_SP 0x0000000000040000ULL +// +// If this flag is set, the memory region is capable of being +// protected with the CPU's memory cryptographic +// capabilities. If this flag is clear, the memory region is not +// capable of being protected with the CPU's memory +// cryptographic capabilities or the CPU does not support CPU +// memory cryptographic capabilities. +// +#define EFI_MEMORY_CPU_CRYPTO 0x0000000000080000ULL + +// +// Runtime memory attribute +// +#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL + +// +// Attributes bitmasks, grouped by type +// +#define EFI_CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP) +#define EFI_MEMORY_ACCESS_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO) +#define EFI_MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_ACCESS_MASK | EFI_MEMORY_SP | EFI_MEMORY_CPU_CRYPTO) + +/// +/// Memory descriptor version number. +/// +#define EFI_MEMORY_DESCRIPTOR_VERSION 1 + +/// +/// Definition of an EFI memory descriptor. +/// +typedef struct { + /// + /// Type of the memory region. + /// Type EFI_MEMORY_TYPE is defined in the + /// AllocatePages() function description. + /// + UINT32 Type; + /// + /// Physical address of the first byte in the memory region. PhysicalStart must be + /// aligned on a 4 KiB boundary, and must not be above 0xfffffffffffff000. Type + /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function description + /// + EFI_PHYSICAL_ADDRESS PhysicalStart; + /// + /// Virtual address of the first byte in the memory region. + /// VirtualStart must be aligned on a 4 KiB boundary, + /// and must not be above 0xfffffffffffff000. + /// + EFI_VIRTUAL_ADDRESS VirtualStart; + /// + /// NumberOfPagesNumber of 4 KiB pages in the memory region. + /// NumberOfPages must not be 0, and must not be any value + /// that would represent a memory page with a start address, + /// either physical or virtual, above 0xfffffffffffff000. + /// + UINT64 NumberOfPages; + /// + /// Attributes of the memory region that describe the bit mask of capabilities + /// for that memory region, and not necessarily the current settings for that + /// memory region. + /// + UINT64 Attribute; +} EFI_MEMORY_DESCRIPTOR; + +/** + Allocates memory pages from the system. + + @param[in] Type The type of allocation to perform. + @param[in] MemoryType The type of memory to allocate. + MemoryType values in the range 0x70000000..0x7FFFFFFF + are reserved for OEM use. MemoryType values in the range + 0x80000000..0xFFFFFFFF are reserved for use by UEFI OS loaders + that are provided by operating system vendors. + @param[in] Pages The number of contiguous 4 KB pages to allocate. + @param[in, out] Memory The pointer to a physical address. On input, the way in which the address is + used depends on the value of Type. + + @retval EFI_SUCCESS The requested pages were allocated. + @retval EFI_INVALID_PARAMETER 1) Type is not AllocateAnyPages or + AllocateMaxAddress or AllocateAddress. + 2) MemoryType is in the range + EfiMaxMemoryType..0x6FFFFFFF. + 3) Memory is NULL. + 4) MemoryType is EfiPersistentMemory. + @retval EFI_OUT_OF_RESOURCES The pages could not be allocated. + @retval EFI_NOT_FOUND The requested pages could not be found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ALLOCATE_PAGES)( + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT EFI_PHYSICAL_ADDRESS *Memory + ); + +/** + Frees memory pages. + + @param[in] Memory The base physical address of the pages to be freed. + @param[in] Pages The number of contiguous 4 KB pages to free. + + @retval EFI_SUCCESS The requested pages were freed. + @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid. + @retval EFI_NOT_FOUND The requested memory pages were not allocated with + AllocatePages(). + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FREE_PAGES)( + IN EFI_PHYSICAL_ADDRESS Memory, + IN UINTN Pages + ); + +/** + Returns the current memory map. + + @param[in, out] MemoryMapSize A pointer to the size, in bytes, of the MemoryMap buffer. + On input, this is the size of the buffer allocated by the caller. + On output, it is the size of the buffer returned by the firmware if + the buffer was large enough, or the size of the buffer needed to contain + the map if the buffer was too small. + @param[out] MemoryMap A pointer to the buffer in which firmware places the current memory + map. + @param[out] MapKey A pointer to the location in which firmware returns the key for the + current memory map. + @param[out] DescriptorSize A pointer to the location in which firmware returns the size, in bytes, of + an individual EFI_MEMORY_DESCRIPTOR. + @param[out] DescriptorVersion A pointer to the location in which firmware returns the version number + associated with the EFI_MEMORY_DESCRIPTOR. + + @retval EFI_SUCCESS The memory map was returned in the MemoryMap buffer. + @retval EFI_BUFFER_TOO_SMALL The MemoryMap buffer was too small. The current buffer size + needed to hold the memory map is returned in MemoryMapSize. + @retval EFI_INVALID_PARAMETER 1) MemoryMapSize is NULL. + 2) The MemoryMap buffer is not too small and MemoryMap is + NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_MEMORY_MAP)( + IN OUT UINTN *MemoryMapSize, + OUT EFI_MEMORY_DESCRIPTOR *MemoryMap, + OUT UINTN *MapKey, + OUT UINTN *DescriptorSize, + OUT UINT32 *DescriptorVersion + ); + +/** + Allocates pool memory. + + @param[in] PoolType The type of pool to allocate. + MemoryType values in the range 0x70000000..0x7FFFFFFF + are reserved for OEM use. MemoryType values in the range + 0x80000000..0xFFFFFFFF are reserved for use by UEFI OS loaders + that are provided by operating system vendors. + @param[in] Size The number of bytes to allocate from the pool. + @param[out] Buffer A pointer to a pointer to the allocated buffer if the call succeeds; + undefined otherwise. + + @retval EFI_SUCCESS The requested number of bytes was allocated. + @retval EFI_OUT_OF_RESOURCES The pool requested could not be allocated. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + PoolType is in the range EfiMaxMemoryType..0x6FFFFFFF. + PoolType is EfiPersistentMemory. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ALLOCATE_POOL)( + IN EFI_MEMORY_TYPE PoolType, + IN UINTN Size, + OUT VOID **Buffer + ); + +/** + Returns pool memory to the system. + + @param[in] Buffer The pointer to the buffer to free. + + @retval EFI_SUCCESS The memory was returned to the system. + @retval EFI_INVALID_PARAMETER Buffer was invalid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_FREE_POOL)( + IN VOID *Buffer + ); + +/** + Changes the runtime addressing mode of EFI firmware from physical to virtual. + + @param[in] MemoryMapSize The size in bytes of VirtualMap. + @param[in] DescriptorSize The size in bytes of an entry in the VirtualMap. + @param[in] DescriptorVersion The version of the structure entries in VirtualMap. + @param[in] VirtualMap An array of memory descriptors which contain new virtual + address mapping information for all runtime ranges. + + @retval EFI_SUCCESS The virtual address map has been applied. + @retval EFI_UNSUPPORTED EFI firmware is not at runtime, or the EFI firmware is already in + virtual address mapped mode. + @retval EFI_INVALID_PARAMETER DescriptorSize or DescriptorVersion is invalid. + @retval EFI_NO_MAPPING A virtual address was not supplied for a range in the memory + map that requires a mapping. + @retval EFI_NOT_FOUND A virtual address was supplied for an address that is not found + in the memory map. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_VIRTUAL_ADDRESS_MAP)( + IN UINTN MemoryMapSize, + IN UINTN DescriptorSize, + IN UINT32 DescriptorVersion, + IN EFI_MEMORY_DESCRIPTOR *VirtualMap + ); + +/** + Connects one or more drivers to a controller. + + @param[in] ControllerHandle The handle of the controller to which driver(s) are to be connected. + @param[in] DriverImageHandle A pointer to an ordered list handles that support the + EFI_DRIVER_BINDING_PROTOCOL. + @param[in] RemainingDevicePath A pointer to the device path that specifies a child of the + controller specified by ControllerHandle. + @param[in] Recursive If TRUE, then ConnectController() is called recursively + until the entire tree of controllers below the controller specified + by ControllerHandle have been created. If FALSE, then + the tree of controllers is only expanded one level. + + @retval EFI_SUCCESS 1) One or more drivers were connected to ControllerHandle. + 2) No drivers were connected to ControllerHandle, but + RemainingDevicePath is not NULL, and it is an End Device + Path Node. + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL. + @retval EFI_NOT_FOUND 1) There are no EFI_DRIVER_BINDING_PROTOCOL instances + present in the system. + 2) No drivers were connected to ControllerHandle. + @retval EFI_SECURITY_VIOLATION + The user has no permission to start UEFI device drivers on the device path + associated with the ControllerHandle or specified by the RemainingDevicePath. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CONNECT_CONTROLLER)( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE *DriverImageHandle, OPTIONAL + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, OPTIONAL + IN BOOLEAN Recursive + ); + +/** + Disconnects one or more drivers from a controller. + + @param[in] ControllerHandle The handle of the controller from which driver(s) are to be disconnected. + @param[in] DriverImageHandle The driver to disconnect from ControllerHandle. + If DriverImageHandle is NULL, then all the drivers currently managing + ControllerHandle are disconnected from ControllerHandle. + @param[in] ChildHandle The handle of the child to destroy. + If ChildHandle is NULL, then all the children of ControllerHandle are + destroyed before the drivers are disconnected from ControllerHandle. + + @retval EFI_SUCCESS 1) One or more drivers were disconnected from the controller. + 2) On entry, no drivers are managing ControllerHandle. + 3) DriverImageHandle is not NULL, and on entry + DriverImageHandle is not managing ControllerHandle. + @retval EFI_INVALID_PARAMETER 1) ControllerHandle is NULL. + 2) DriverImageHandle is not NULL, and it is not a valid EFI_HANDLE. + 3) ChildHandle is not NULL, and it is not a valid EFI_HANDLE. + 4) DriverImageHandle does not support the EFI_DRIVER_BINDING_PROTOCOL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to disconnect any drivers from + ControllerHandle. + @retval EFI_DEVICE_ERROR The controller could not be disconnected because of a device error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_DISCONNECT_CONTROLLER)( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE DriverImageHandle, OPTIONAL + IN EFI_HANDLE ChildHandle OPTIONAL + ); + + + +// +// ConvertPointer DebugDisposition type. +// +#define EFI_OPTIONAL_PTR 0x00000001 + +/** + Determines the new virtual address that is to be used on subsequent memory accesses. + + @param[in] DebugDisposition Supplies type information for the pointer being converted. + @param[in, out] Address A pointer to a pointer that is to be fixed to be the value needed + for the new virtual address mappings being applied. + + @retval EFI_SUCCESS The pointer pointed to by Address was modified. + @retval EFI_INVALID_PARAMETER 1) Address is NULL. + 2) *Address is NULL and DebugDisposition does + not have the EFI_OPTIONAL_PTR bit set. + @retval EFI_NOT_FOUND The pointer pointed to by Address was not found to be part + of the current memory map. This is normally fatal. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CONVERT_POINTER)( + IN UINTN DebugDisposition, + IN OUT VOID **Address + ); + + +// +// These types can be ORed together as needed - for example, +// EVT_TIMER might be Ored with EVT_NOTIFY_WAIT or +// EVT_NOTIFY_SIGNAL. +// +#define EVT_TIMER 0x80000000 +#define EVT_RUNTIME 0x40000000 +#define EVT_NOTIFY_WAIT 0x00000100 +#define EVT_NOTIFY_SIGNAL 0x00000200 + +#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201 +#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202 + +// +// The event's NotifyContext pointer points to a runtime memory +// address. +// The event is deprecated in UEFI2.0 and later specifications. +// +#define EVT_RUNTIME_CONTEXT 0x20000000 + + +/** + Invoke a notification event + + @param[in] Event Event whose notification function is being invoked. + @param[in] Context The pointer to the notification function's context, + which is implementation-dependent. + +**/ +typedef +VOID +(EFIAPI *EFI_EVENT_NOTIFY)( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + Creates an event. + + @param[in] Type The type of event to create and its mode and attributes. + @param[in] NotifyTpl The task priority level of event notifications, if needed. + @param[in] NotifyFunction The pointer to the event's notification function, if any. + @param[in] NotifyContext The pointer to the notification function's context; corresponds to parameter + Context in the notification function. + @param[out] Event The pointer to the newly created event if the call succeeds; undefined + otherwise. + + @retval EFI_SUCCESS The event structure was created. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The event could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREATE_EVENT)( + IN UINT32 Type, + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction, + IN VOID *NotifyContext, + OUT EFI_EVENT *Event + ); + +/** + Creates an event in a group. + + @param[in] Type The type of event to create and its mode and attributes. + @param[in] NotifyTpl The task priority level of event notifications,if needed. + @param[in] NotifyFunction The pointer to the event's notification function, if any. + @param[in] NotifyContext The pointer to the notification function's context; corresponds to parameter + Context in the notification function. + @param[in] EventGroup The pointer to the unique identifier of the group to which this event belongs. + If this is NULL, then the function behaves as if the parameters were passed + to CreateEvent. + @param[out] Event The pointer to the newly created event if the call succeeds; undefined + otherwise. + + @retval EFI_SUCCESS The event structure was created. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The event could not be allocated. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CREATE_EVENT_EX)( + IN UINT32 Type, + IN EFI_TPL NotifyTpl, + IN EFI_EVENT_NOTIFY NotifyFunction OPTIONAL, + IN CONST VOID *NotifyContext OPTIONAL, + IN CONST EFI_GUID *EventGroup OPTIONAL, + OUT EFI_EVENT *Event + ); + +/// +/// Timer delay types +/// +typedef enum { + /// + /// An event's timer settings is to be cancelled and not trigger time is to be set/ + /// + TimerCancel, + /// + /// An event is to be signaled periodically at a specified interval from the current time. + /// + TimerPeriodic, + /// + /// An event is to be signaled once at a specified interval from the current time. + /// + TimerRelative +} EFI_TIMER_DELAY; + +/** + Sets the type of timer and the trigger time for a timer event. + + @param[in] Event The timer event that is to be signaled at the specified time. + @param[in] Type The type of time that is specified in TriggerTime. + @param[in] TriggerTime The number of 100ns units until the timer expires. + A TriggerTime of 0 is legal. + If Type is TimerRelative and TriggerTime is 0, then the timer + event will be signaled on the next timer tick. + If Type is TimerPeriodic and TriggerTime is 0, then the timer + event will be signaled on every timer tick. + + @retval EFI_SUCCESS The event has been set to be signaled at the requested time. + @retval EFI_INVALID_PARAMETER Event or Type is not valid. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIMER)( + IN EFI_EVENT Event, + IN EFI_TIMER_DELAY Type, + IN UINT64 TriggerTime + ); + +/** + Signals an event. + + @param[in] Event The event to signal. + + @retval EFI_SUCCESS The event has been signaled. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SIGNAL_EVENT)( + IN EFI_EVENT Event + ); + +/** + Stops execution until an event is signaled. + + @param[in] NumberOfEvents The number of events in the Event array. + @param[in] Event An array of EFI_EVENT. + @param[out] Index The pointer to the index of the event which satisfied the wait condition. + + @retval EFI_SUCCESS The event indicated by Index was signaled. + @retval EFI_INVALID_PARAMETER 1) NumberOfEvents is 0. + 2) The event indicated by Index is of type + EVT_NOTIFY_SIGNAL. + @retval EFI_UNSUPPORTED The current TPL is not TPL_APPLICATION. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_WAIT_FOR_EVENT)( + IN UINTN NumberOfEvents, + IN EFI_EVENT *Event, + OUT UINTN *Index + ); + +/** + Closes an event. + + @param[in] Event The event to close. + + @retval EFI_SUCCESS The event has been closed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CLOSE_EVENT)( + IN EFI_EVENT Event + ); + +/** + Checks whether an event is in the signaled state. + + @param[in] Event The event to check. + + @retval EFI_SUCCESS The event is in the signaled state. + @retval EFI_NOT_READY The event is not in the signaled state. + @retval EFI_INVALID_PARAMETER Event is of type EVT_NOTIFY_SIGNAL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CHECK_EVENT)( + IN EFI_EVENT Event + ); + + +// +// Task priority level +// +#define TPL_APPLICATION 4 +#define TPL_CALLBACK 8 +#define TPL_NOTIFY 16 +#define TPL_HIGH_LEVEL 31 + + +/** + Raises a task's priority level and returns its previous level. + + @param[in] NewTpl The new task priority level. + + @return Previous task priority level + +**/ +typedef +EFI_TPL +(EFIAPI *EFI_RAISE_TPL)( + IN EFI_TPL NewTpl + ); + +/** + Restores a task's priority level to its previous value. + + @param[in] OldTpl The previous task priority level to restore. + +**/ +typedef +VOID +(EFIAPI *EFI_RESTORE_TPL)( + IN EFI_TPL OldTpl + ); + +/** + Returns the value of a variable. + + @param[in] VariableName A Null-terminated string that is the name of the vendor's + variable. + @param[in] VendorGuid A unique identifier for the vendor. + @param[out] Attributes If not NULL, a pointer to the memory location to return the + attributes bitmask for the variable. + @param[in, out] DataSize On input, the size in bytes of the return Data buffer. + On output the size of data returned in Data. + @param[out] Data The buffer to return the contents of the variable. May be NULL + with a zero DataSize in order to determine the size buffer needed. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result. + @retval EFI_INVALID_PARAMETER VariableName is NULL. + @retval EFI_INVALID_PARAMETER VendorGuid is NULL. + @retval EFI_INVALID_PARAMETER DataSize is NULL. + @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error. + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_VARIABLE)( + IN CHAR16 *VariableName, + IN EFI_GUID *VendorGuid, + OUT UINT32 *Attributes, OPTIONAL + IN OUT UINTN *DataSize, + OUT VOID *Data OPTIONAL + ); + +/** + Enumerates the current variable names. + + @param[in, out] VariableNameSize The size of the VariableName buffer. The size must be large + enough to fit input string supplied in VariableName buffer. + @param[in, out] VariableName On input, supplies the last VariableName that was returned + by GetNextVariableName(). On output, returns the Nullterminated + string of the current variable. + @param[in, out] VendorGuid On input, supplies the last VendorGuid that was returned by + GetNextVariableName(). On output, returns the + VendorGuid of the current variable. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The next variable was not found. + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the result. + VariableNameSize has been updated with the size needed to complete the request. + @retval EFI_INVALID_PARAMETER VariableNameSize is NULL. + @retval EFI_INVALID_PARAMETER VariableName is NULL. + @retval EFI_INVALID_PARAMETER VendorGuid is NULL. + @retval EFI_INVALID_PARAMETER The input values of VariableName and VendorGuid are not a name and + GUID of an existing variable. + @retval EFI_INVALID_PARAMETER Null-terminator is not found in the first VariableNameSize bytes of + the input VariableName buffer. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_NEXT_VARIABLE_NAME)( + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VendorGuid + ); + +/** + Sets the value of a variable. + + @param[in] VariableName A Null-terminated string that is the name of the vendor's variable. + Each VariableName is unique for each VendorGuid. VariableName must + contain 1 or more characters. If VariableName is an empty string, + then EFI_INVALID_PARAMETER is returned. + @param[in] VendorGuid A unique identifier for the vendor. + @param[in] Attributes Attributes bitmask to set for the variable. + @param[in] DataSize The size in bytes of the Data buffer. Unless the EFI_VARIABLE_APPEND_WRITE or + EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set, a size of zero + causes the variable to be deleted. When the EFI_VARIABLE_APPEND_WRITE attribute is + set, then a SetVariable() call with a DataSize of zero will not cause any change to + the variable value (the timestamp associated with the variable may be updated however + even if no new data value is provided,see the description of the + EFI_VARIABLE_AUTHENTICATION_2 descriptor below. In this case the DataSize will not + be zero since the EFI_VARIABLE_AUTHENTICATION_2 descriptor will be populated). + @param[in] Data The contents for the variable. + + @retval EFI_SUCCESS The firmware has successfully stored the variable and its data as + defined by the Attributes. + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits, name, and GUID was supplied, or the + DataSize exceeds the maximum allowed. + @retval EFI_INVALID_PARAMETER VariableName is an empty string. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data. + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error. + @retval EFI_WRITE_PROTECTED The variable in question is read-only. + @retval EFI_WRITE_PROTECTED The variable in question cannot be deleted. + @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS being set, + but the AuthInfo does NOT pass the validation check carried out by the firmware. + + @retval EFI_NOT_FOUND The variable trying to be updated or deleted was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_VARIABLE)( + IN CHAR16 *VariableName, + IN EFI_GUID *VendorGuid, + IN UINT32 Attributes, + IN UINTN DataSize, + IN VOID *Data + ); + + +/// +/// This provides the capabilities of the +/// real time clock device as exposed through the EFI interfaces. +/// +typedef struct { + /// + /// Provides the reporting resolution of the real-time clock device in + /// counts per second. For a normal PC-AT CMOS RTC device, this + /// value would be 1 Hz, or 1, to indicate that the device only reports + /// the time to the resolution of 1 second. + /// + UINT32 Resolution; + /// + /// Provides the timekeeping accuracy of the real-time clock in an + /// error rate of 1E-6 parts per million. For a clock with an accuracy + /// of 50 parts per million, the value in this field would be + /// 50,000,000. + /// + UINT32 Accuracy; + /// + /// A TRUE indicates that a time set operation clears the device's + /// time below the Resolution reporting level. A FALSE + /// indicates that the state below the Resolution level of the + /// device is not cleared when the time is set. Normal PC-AT CMOS + /// RTC devices set this value to FALSE. + /// + BOOLEAN SetsToZero; +} EFI_TIME_CAPABILITIES; + +/** + Returns the current time and date information, and the time-keeping capabilities + of the hardware platform. + + @param[out] Time A pointer to storage to receive a snapshot of the current time. + @param[out] Capabilities An optional pointer to a buffer to receive the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_TIME)( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL + ); + +/** + Sets the current local time and date information. + + @param[in] Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIME)( + IN EFI_TIME *Time + ); + +/** + Returns the current wakeup alarm clock setting. + + @param[out] Enabled Indicates if the alarm is currently enabled or disabled. + @param[out] Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param[out] Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Enabled is NULL. + @retval EFI_INVALID_PARAMETER Pending is NULL. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_WAKEUP_TIME)( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ); + +/** + Sets the system wakeup alarm clock time. + + @param[in] Enable Enable or disable the wakeup alarm. + @param[in] Time If Enable is TRUE, the time to set the wakeup alarm for. + If Enable is FALSE, then this parameter is optional, and may be NULL. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_WAKEUP_TIME)( + IN BOOLEAN Enable, + IN EFI_TIME *Time OPTIONAL + ); + +/** + Loads an EFI image into memory. + + @param[in] BootPolicy If TRUE, indicates that the request originates from the boot + manager, and that the boot manager is attempting to load + FilePath as a boot selection. Ignored if SourceBuffer is + not NULL. + @param[in] ParentImageHandle The caller's image handle. + @param[in] DevicePath The DeviceHandle specific file path from which the image is + loaded. + @param[in] SourceBuffer If not NULL, a pointer to the memory location containing a copy + of the image to be loaded. + @param[in] SourceSize The size in bytes of SourceBuffer. Ignored if SourceBuffer is NULL. + @param[out] ImageHandle The pointer to the returned image handle that is created when the + image is successfully loaded. + + @retval EFI_SUCCESS Image was loaded into memory correctly. + @retval EFI_NOT_FOUND Both SourceBuffer and DevicePath are NULL. + @retval EFI_INVALID_PARAMETER One or more parametes are invalid. + @retval EFI_UNSUPPORTED The image type is not supported. + @retval EFI_OUT_OF_RESOURCES Image was not loaded due to insufficient resources. + @retval EFI_LOAD_ERROR Image was not loaded because the image format was corrupt or not + understood. + @retval EFI_DEVICE_ERROR Image was not loaded because the device returned a read error. + @retval EFI_ACCESS_DENIED Image was not loaded because the platform policy prohibits the + image from being loaded. NULL is returned in *ImageHandle. + @retval EFI_SECURITY_VIOLATION Image was loaded and an ImageHandle was created with a + valid EFI_LOADED_IMAGE_PROTOCOL. However, the current + platform policy specifies that the image should not be started. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IMAGE_LOAD)( + IN BOOLEAN BootPolicy, + IN EFI_HANDLE ParentImageHandle, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN VOID *SourceBuffer OPTIONAL, + IN UINTN SourceSize, + OUT EFI_HANDLE *ImageHandle + ); + +/** + Transfers control to a loaded image's entry point. + + @param[in] ImageHandle Handle of image to be started. + @param[out] ExitDataSize The pointer to the size, in bytes, of ExitData. + @param[out] ExitData The pointer to a pointer to a data buffer that includes a Null-terminated + string, optionally followed by additional binary data. + + @retval EFI_INVALID_PARAMETER ImageHandle is either an invalid image handle or the image + has already been initialized with StartImage. + @retval EFI_SECURITY_VIOLATION The current platform policy specifies that the image should not be started. + @return Exit code from image + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IMAGE_START)( + IN EFI_HANDLE ImageHandle, + OUT UINTN *ExitDataSize, + OUT CHAR16 **ExitData OPTIONAL + ); + +/** + Terminates a loaded EFI image and returns control to boot services. + + @param[in] ImageHandle Handle that identifies the image. This parameter is passed to the + image on entry. + @param[in] ExitStatus The image's exit code. + @param[in] ExitDataSize The size, in bytes, of ExitData. Ignored if ExitStatus is EFI_SUCCESS. + @param[in] ExitData The pointer to a data buffer that includes a Null-terminated string, + optionally followed by additional binary data. The string is a + description that the caller may use to further indicate the reason + for the image's exit. ExitData is only valid if ExitStatus + is something other than EFI_SUCCESS. The ExitData buffer + must be allocated by calling AllocatePool(). + + @retval EFI_SUCCESS The image specified by ImageHandle was unloaded. + @retval EFI_INVALID_PARAMETER The image specified by ImageHandle has been loaded and + started with LoadImage() and StartImage(), but the + image is not the currently executing image. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXIT)( + IN EFI_HANDLE ImageHandle, + IN EFI_STATUS ExitStatus, + IN UINTN ExitDataSize, + IN CHAR16 *ExitData OPTIONAL + ); + +/** + Unloads an image. + + @param[in] ImageHandle Handle that identifies the image to be unloaded. + + @retval EFI_SUCCESS The image has been unloaded. + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IMAGE_UNLOAD)( + IN EFI_HANDLE ImageHandle + ); + +/** + Terminates all boot services. + + @param[in] ImageHandle Handle that identifies the exiting image. + @param[in] MapKey Key to the latest memory map. + + @retval EFI_SUCCESS Boot services have been terminated. + @retval EFI_INVALID_PARAMETER MapKey is incorrect. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_EXIT_BOOT_SERVICES)( + IN EFI_HANDLE ImageHandle, + IN UINTN MapKey + ); + +/** + Induces a fine-grained stall. + + @param[in] Microseconds The number of microseconds to stall execution. + + @retval EFI_SUCCESS Execution was stalled at least the requested number of + Microseconds. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_STALL)( + IN UINTN Microseconds + ); + +/** + Sets the system's watchdog timer. + + @param[in] Timeout The number of seconds to set the watchdog timer to. + @param[in] WatchdogCode The numeric code to log on a watchdog timer timeout event. + @param[in] DataSize The size, in bytes, of WatchdogData. + @param[in] WatchdogData A data buffer that includes a Null-terminated string, optionally + followed by additional binary data. + + @retval EFI_SUCCESS The timeout has been set. + @retval EFI_INVALID_PARAMETER The supplied WatchdogCode is invalid. + @retval EFI_UNSUPPORTED The system does not have a watchdog timer. + @retval EFI_DEVICE_ERROR The watchdog timer could not be programmed due to a hardware + error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SET_WATCHDOG_TIMER)( + IN UINTN Timeout, + IN UINT64 WatchdogCode, + IN UINTN DataSize, + IN CHAR16 *WatchdogData OPTIONAL + ); + +/** + Resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + string, optionally followed by additional binary data. + The string is a description that the caller may use to further + indicate the reason for the system reset. + For a ResetType of EfiResetPlatformSpecific the data buffer + also starts with a Null-terminated string that is followed + by an EFI_GUID that describes the specific type of reset to perform. +**/ +typedef +VOID +(EFIAPI *EFI_RESET_SYSTEM)( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Returns a monotonically increasing count for the platform. + + @param[out] Count The pointer to returned value. + + @retval EFI_SUCCESS The next monotonic count was returned. + @retval EFI_INVALID_PARAMETER Count is NULL. + @retval EFI_DEVICE_ERROR The device is not functioning properly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_NEXT_MONOTONIC_COUNT)( + OUT UINT64 *Count + ); + +/** + Returns the next high 32 bits of the platform's monotonic counter. + + @param[out] HighCount The pointer to returned value. + + @retval EFI_SUCCESS The next high monotonic count was returned. + @retval EFI_INVALID_PARAMETER HighCount is NULL. + @retval EFI_DEVICE_ERROR The device is not functioning properly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_GET_NEXT_HIGH_MONO_COUNT)( + OUT UINT32 *HighCount + ); + +/** + Computes and returns a 32-bit CRC for a data buffer. + + @param[in] Data A pointer to the buffer on which the 32-bit CRC is to be computed. + @param[in] DataSize The number of bytes in the buffer Data. + @param[out] Crc32 The 32-bit CRC that was computed for the data buffer specified by Data + and DataSize. + + @retval EFI_SUCCESS The 32-bit CRC was computed for the data buffer and returned in + Crc32. + @retval EFI_INVALID_PARAMETER Data is NULL. + @retval EFI_INVALID_PARAMETER Crc32 is NULL. + @retval EFI_INVALID_PARAMETER DataSize is 0. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CALCULATE_CRC32)( + IN VOID *Data, + IN UINTN DataSize, + OUT UINT32 *Crc32 + ); + +/** + Copies the contents of one buffer to another buffer. + + @param[in] Destination The pointer to the destination buffer of the memory copy. + @param[in] Source The pointer to the source buffer of the memory copy. + @param[in] Length Number of bytes to copy from Source to Destination. + +**/ +typedef +VOID +(EFIAPI *EFI_COPY_MEM)( + IN VOID *Destination, + IN VOID *Source, + IN UINTN Length + ); + +/** + The SetMem() function fills a buffer with a specified value. + + @param[in] Buffer The pointer to the buffer to fill. + @param[in] Size Number of bytes in Buffer to fill. + @param[in] Value Value to fill Buffer with. + +**/ +typedef +VOID +(EFIAPI *EFI_SET_MEM)( + IN VOID *Buffer, + IN UINTN Size, + IN UINT8 Value + ); + +/// +/// Enumeration of EFI Interface Types +/// +typedef enum { + /// + /// Indicates that the supplied protocol interface is supplied in native form. + /// + EFI_NATIVE_INTERFACE +} EFI_INTERFACE_TYPE; + +/** + Installs a protocol interface on a device handle. If the handle does not exist, it is created and added + to the list of handles in the system. InstallMultipleProtocolInterfaces() performs + more error checking than InstallProtocolInterface(), so it is recommended that + InstallMultipleProtocolInterfaces() be used in place of + InstallProtocolInterface() + + @param[in, out] Handle A pointer to the EFI_HANDLE on which the interface is to be installed. + @param[in] Protocol The numeric ID of the protocol interface. + @param[in] InterfaceType Indicates whether Interface is supplied in native form. + @param[in] Interface A pointer to the protocol interface. + + @retval EFI_SUCCESS The protocol interface was installed. + @retval EFI_OUT_OF_RESOURCES Space for a new handle could not be allocated. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + @retval EFI_INVALID_PARAMETER InterfaceType is not EFI_NATIVE_INTERFACE. + @retval EFI_INVALID_PARAMETER Protocol is already installed on the handle specified by Handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INSTALL_PROTOCOL_INTERFACE)( + IN OUT EFI_HANDLE *Handle, + IN EFI_GUID *Protocol, + IN EFI_INTERFACE_TYPE InterfaceType, + IN VOID *Interface + ); + +/** + Installs one or more protocol interfaces into the boot services environment. + + @param[in, out] Handle The pointer to a handle to install the new protocol interfaces on, + or a pointer to NULL if a new handle is to be allocated. + @param ... A variable argument list containing pairs of protocol GUIDs and protocol + interfaces. + + @retval EFI_SUCCESS All the protocol interface was installed. + @retval EFI_OUT_OF_RESOURCES There was not enough memory in pool to install all the protocols. + @retval EFI_ALREADY_STARTED A Device Path Protocol instance was passed in that is already present in + the handle database. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Protocol is already installed on the handle specified by Handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INSTALL_MULTIPLE_PROTOCOL_INTERFACES)( + IN OUT EFI_HANDLE *Handle, + ... + ); + +/** + Reinstalls a protocol interface on a device handle. + + @param[in] Handle Handle on which the interface is to be reinstalled. + @param[in] Protocol The numeric ID of the interface. + @param[in] OldInterface A pointer to the old interface. NULL can be used if a structure is not + associated with Protocol. + @param[in] NewInterface A pointer to the new interface. + + @retval EFI_SUCCESS The protocol interface was reinstalled. + @retval EFI_NOT_FOUND The OldInterface on the handle was not found. + @retval EFI_ACCESS_DENIED The protocol interface could not be reinstalled, + because OldInterface is still being used by a + driver that will not release it. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REINSTALL_PROTOCOL_INTERFACE)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + IN VOID *OldInterface, + IN VOID *NewInterface + ); + +/** + Removes a protocol interface from a device handle. It is recommended that + UninstallMultipleProtocolInterfaces() be used in place of + UninstallProtocolInterface(). + + @param[in] Handle The handle on which the interface was installed. + @param[in] Protocol The numeric ID of the interface. + @param[in] Interface A pointer to the interface. + + @retval EFI_SUCCESS The interface was removed. + @retval EFI_NOT_FOUND The interface was not found. + @retval EFI_ACCESS_DENIED The interface was not removed because the interface + is still being used by a driver. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UNINSTALL_PROTOCOL_INTERFACE)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + IN VOID *Interface + ); + +/** + Removes one or more protocol interfaces into the boot services environment. + + @param[in] Handle The handle to remove the protocol interfaces from. + @param ... A variable argument list containing pairs of protocol GUIDs and + protocol interfaces. + + @retval EFI_SUCCESS All the protocol interfaces were removed. + @retval EFI_INVALID_PARAMETER One of the protocol interfaces was not previously installed on Handle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES)( + IN EFI_HANDLE Handle, + ... + ); + +/** + Queries a handle to determine if it supports a specified protocol. + + @param[in] Handle The handle being queried. + @param[in] Protocol The published unique identifier of the protocol. + @param[out] Interface Supplies the address where a pointer to the corresponding Protocol + Interface is returned. + + @retval EFI_SUCCESS The interface information for the specified protocol was returned. + @retval EFI_UNSUPPORTED The device does not support the specified protocol. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + @retval EFI_INVALID_PARAMETER Interface is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_HANDLE_PROTOCOL)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + OUT VOID **Interface + ); + +#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001 +#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002 +#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004 +#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008 +#define EFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010 +#define EFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020 + +/** + Queries a handle to determine if it supports a specified protocol. If the protocol is supported by the + handle, it opens the protocol on behalf of the calling agent. + + @param[in] Handle The handle for the protocol interface that is being opened. + @param[in] Protocol The published unique identifier of the protocol. + @param[out] Interface Supplies the address where a pointer to the corresponding Protocol + Interface is returned. + @param[in] AgentHandle The handle of the agent that is opening the protocol interface + specified by Protocol and Interface. + @param[in] ControllerHandle If the agent that is opening a protocol is a driver that follows the + UEFI Driver Model, then this parameter is the controller handle + that requires the protocol interface. If the agent does not follow + the UEFI Driver Model, then this parameter is optional and may + be NULL. + @param[in] Attributes The open mode of the protocol interface specified by Handle + and Protocol. + + @retval EFI_SUCCESS An item was added to the open list for the protocol interface, and the + protocol interface was returned in Interface. + @retval EFI_UNSUPPORTED Handle does not support Protocol. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_ACCESS_DENIED Required attributes can't be supported in current environment. + @retval EFI_ALREADY_STARTED Item on the open list already has requierd attributes whose agent + handle is the same as AgentHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_OPEN_PROTOCOL)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + OUT VOID **Interface, OPTIONAL + IN EFI_HANDLE AgentHandle, + IN EFI_HANDLE ControllerHandle, + IN UINT32 Attributes + ); + + +/** + Closes a protocol on a handle that was opened using OpenProtocol(). + + @param[in] Handle The handle for the protocol interface that was previously opened + with OpenProtocol(), and is now being closed. + @param[in] Protocol The published unique identifier of the protocol. + @param[in] AgentHandle The handle of the agent that is closing the protocol interface. + @param[in] ControllerHandle If the agent that opened a protocol is a driver that follows the + UEFI Driver Model, then this parameter is the controller handle + that required the protocol interface. + + @retval EFI_SUCCESS The protocol instance was closed. + @retval EFI_INVALID_PARAMETER 1) Handle is NULL. + 2) AgentHandle is NULL. + 3) ControllerHandle is not NULL and ControllerHandle is not a valid EFI_HANDLE. + 4) Protocol is NULL. + @retval EFI_NOT_FOUND 1) Handle does not support the protocol specified by Protocol. + 2) The protocol interface specified by Handle and Protocol is not + currently open by AgentHandle and ControllerHandle. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_CLOSE_PROTOCOL)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + IN EFI_HANDLE AgentHandle, + IN EFI_HANDLE ControllerHandle + ); + +/// +/// EFI Oprn Protocol Information Entry +/// +typedef struct { + EFI_HANDLE AgentHandle; + EFI_HANDLE ControllerHandle; + UINT32 Attributes; + UINT32 OpenCount; +} EFI_OPEN_PROTOCOL_INFORMATION_ENTRY; + +/** + Retrieves the list of agents that currently have a protocol interface opened. + + @param[in] Handle The handle for the protocol interface that is being queried. + @param[in] Protocol The published unique identifier of the protocol. + @param[out] EntryBuffer A pointer to a buffer of open protocol information in the form of + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY structures. + @param[out] EntryCount A pointer to the number of entries in EntryBuffer. + + @retval EFI_SUCCESS The open protocol information was returned in EntryBuffer, and the + number of entries was returned EntryCount. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate EntryBuffer. + @retval EFI_NOT_FOUND Handle does not support the protocol specified by Protocol. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_OPEN_PROTOCOL_INFORMATION)( + IN EFI_HANDLE Handle, + IN EFI_GUID *Protocol, + OUT EFI_OPEN_PROTOCOL_INFORMATION_ENTRY **EntryBuffer, + OUT UINTN *EntryCount + ); + +/** + Retrieves the list of protocol interface GUIDs that are installed on a handle in a buffer allocated + from pool. + + @param[in] Handle The handle from which to retrieve the list of protocol interface + GUIDs. + @param[out] ProtocolBuffer A pointer to the list of protocol interface GUID pointers that are + installed on Handle. + @param[out] ProtocolBufferCount A pointer to the number of GUID pointers present in + ProtocolBuffer. + + @retval EFI_SUCCESS The list of protocol interface GUIDs installed on Handle was returned in + ProtocolBuffer. The number of protocol interface GUIDs was + returned in ProtocolBufferCount. + @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the results. + @retval EFI_INVALID_PARAMETER Handle is NULL. + @retval EFI_INVALID_PARAMETER Handle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ProtocolBuffer is NULL. + @retval EFI_INVALID_PARAMETER ProtocolBufferCount is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PROTOCOLS_PER_HANDLE)( + IN EFI_HANDLE Handle, + OUT EFI_GUID ***ProtocolBuffer, + OUT UINTN *ProtocolBufferCount + ); + +/** + Creates an event that is to be signaled whenever an interface is installed for a specified protocol. + + @param[in] Protocol The numeric ID of the protocol for which the event is to be registered. + @param[in] Event Event that is to be signaled whenever a protocol interface is registered + for Protocol. + @param[out] Registration A pointer to a memory location to receive the registration value. + + @retval EFI_SUCCESS The notification event has been registered. + @retval EFI_OUT_OF_RESOURCES Space for the notification event could not be allocated. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + @retval EFI_INVALID_PARAMETER Event is NULL. + @retval EFI_INVALID_PARAMETER Registration is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_REGISTER_PROTOCOL_NOTIFY)( + IN EFI_GUID *Protocol, + IN EFI_EVENT Event, + OUT VOID **Registration + ); + +/// +/// Enumeration of EFI Locate Search Types +/// +typedef enum { + /// + /// Retrieve all the handles in the handle database. + /// + AllHandles, + /// + /// Retrieve the next handle fron a RegisterProtocolNotify() event. + /// + ByRegisterNotify, + /// + /// Retrieve the set of handles from the handle database that support a + /// specified protocol. + /// + ByProtocol +} EFI_LOCATE_SEARCH_TYPE; + +/** + Returns an array of handles that support a specified protocol. + + @param[in] SearchType Specifies which handle(s) are to be returned. + @param[in] Protocol Specifies the protocol to search by. + @param[in] SearchKey Specifies the search key. + @param[in, out] BufferSize On input, the size in bytes of Buffer. On output, the size in bytes of + the array returned in Buffer (if the buffer was large enough) or the + size, in bytes, of the buffer needed to obtain the array (if the buffer was + not large enough). + @param[out] Buffer The buffer in which the array is returned. + + @retval EFI_SUCCESS The array of handles was returned. + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small for the result. + @retval EFI_INVALID_PARAMETER SearchType is not a member of EFI_LOCATE_SEARCH_TYPE. + @retval EFI_INVALID_PARAMETER SearchType is ByRegisterNotify and SearchKey is NULL. + @retval EFI_INVALID_PARAMETER SearchType is ByProtocol and Protocol is NULL. + @retval EFI_INVALID_PARAMETER One or more matches are found and BufferSize is NULL. + @retval EFI_INVALID_PARAMETER BufferSize is large enough for the result and Buffer is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOCATE_HANDLE)( + IN EFI_LOCATE_SEARCH_TYPE SearchType, + IN EFI_GUID *Protocol, OPTIONAL + IN VOID *SearchKey, OPTIONAL + IN OUT UINTN *BufferSize, + OUT EFI_HANDLE *Buffer + ); + +/** + Locates the handle to a device on the device path that supports the specified protocol. + + @param[in] Protocol Specifies the protocol to search for. + @param[in, out] DevicePath On input, a pointer to a pointer to the device path. On output, the device + path pointer is modified to point to the remaining part of the device + path. + @param[out] Device A pointer to the returned device handle. + + @retval EFI_SUCCESS The resulting handle was returned. + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_INVALID_PARAMETER Protocol is NULL. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_INVALID_PARAMETER A handle matched the search and Device is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOCATE_DEVICE_PATH)( + IN EFI_GUID *Protocol, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath, + OUT EFI_HANDLE *Device + ); + +/** + Adds, updates, or removes a configuration table entry from the EFI System Table. + + @param[in] Guid A pointer to the GUID for the entry to add, update, or remove. + @param[in] Table A pointer to the configuration table for the entry to add, update, or + remove. May be NULL. + + @retval EFI_SUCCESS The (Guid, Table) pair was added, updated, or removed. + @retval EFI_NOT_FOUND An attempt was made to delete a nonexistent entry. + @retval EFI_INVALID_PARAMETER Guid is NULL. + @retval EFI_OUT_OF_RESOURCES There is not enough memory available to complete the operation. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_INSTALL_CONFIGURATION_TABLE)( + IN EFI_GUID *Guid, + IN VOID *Table + ); + +/** + Returns an array of handles that support the requested protocol in a buffer allocated from pool. + + @param[in] SearchType Specifies which handle(s) are to be returned. + @param[in] Protocol Provides the protocol to search by. + This parameter is only valid for a SearchType of ByProtocol. + @param[in] SearchKey Supplies the search key depending on the SearchType. + @param[out] NoHandles The number of handles returned in Buffer. + @param[out] Buffer A pointer to the buffer to return the requested array of handles that + support Protocol. + + @retval EFI_SUCCESS The array of handles was returned in Buffer, and the number of + handles in Buffer was returned in NoHandles. + @retval EFI_NOT_FOUND No handles match the search. + @retval EFI_OUT_OF_RESOURCES There is not enough pool memory to store the matching results. + @retval EFI_INVALID_PARAMETER NoHandles is NULL. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOCATE_HANDLE_BUFFER)( + IN EFI_LOCATE_SEARCH_TYPE SearchType, + IN EFI_GUID *Protocol, OPTIONAL + IN VOID *SearchKey, OPTIONAL + OUT UINTN *NoHandles, + OUT EFI_HANDLE **Buffer + ); + +/** + Returns the first protocol instance that matches the given protocol. + + @param[in] Protocol Provides the protocol to search for. + @param[in] Registration Optional registration key returned from + RegisterProtocolNotify(). + @param[out] Interface On return, a pointer to the first interface that matches Protocol and + Registration. + + @retval EFI_SUCCESS A protocol instance matching Protocol was found and returned in + Interface. + @retval EFI_NOT_FOUND No protocol instances were found that match Protocol and + Registration. + @retval EFI_INVALID_PARAMETER Interface is NULL. + Protocol is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LOCATE_PROTOCOL)( + IN EFI_GUID *Protocol, + IN VOID *Registration, OPTIONAL + OUT VOID **Interface + ); + +/// +/// EFI Capsule Block Descriptor +/// +typedef struct { + /// + /// Length in bytes of the data pointed to by DataBlock/ContinuationPointer. + /// + UINT64 Length; + union { + /// + /// Physical address of the data block. This member of the union is + /// used if Length is not equal to zero. + /// + EFI_PHYSICAL_ADDRESS DataBlock; + /// + /// Physical address of another block of + /// EFI_CAPSULE_BLOCK_DESCRIPTOR structures. This + /// member of the union is used if Length is equal to zero. If + /// ContinuationPointer is zero this entry represents the end of the list. + /// + EFI_PHYSICAL_ADDRESS ContinuationPointer; + } Union; +} EFI_CAPSULE_BLOCK_DESCRIPTOR; + +/// +/// EFI Capsule Header. +/// +typedef struct { + /// + /// A GUID that defines the contents of a capsule. + /// + EFI_GUID CapsuleGuid; + /// + /// The size of the capsule header. This may be larger than the size of + /// the EFI_CAPSULE_HEADER since CapsuleGuid may imply + /// extended header entries + /// + UINT32 HeaderSize; + /// + /// Bit-mapped list describing the capsule attributes. The Flag values + /// of 0x0000 - 0xFFFF are defined by CapsuleGuid. Flag values + /// of 0x10000 - 0xFFFFFFFF are defined by this specification + /// + UINT32 Flags; + /// + /// Size in bytes of the capsule. + /// + UINT32 CapsuleImageSize; +} EFI_CAPSULE_HEADER; + +/// +/// The EFI System Table entry must point to an array of capsules +/// that contain the same CapsuleGuid value. The array must be +/// prefixed by a UINT32 that represents the size of the array of capsules. +/// +typedef struct { + /// + /// the size of the array of capsules. + /// + UINT32 CapsuleArrayNumber; + /// + /// Point to an array of capsules that contain the same CapsuleGuid value. + /// + VOID* CapsulePtr[1]; +} EFI_CAPSULE_TABLE; + +#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000 +#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000 +#define CAPSULE_FLAGS_INITIATE_RESET 0x00040000 + +/** + Passes capsules to the firmware with both virtual and physical mapping. Depending on the intended + consumption, the firmware may process the capsule immediately. If the payload should persist + across a system reset, the reset value returned from EFI_QueryCapsuleCapabilities must + be passed into ResetSystem() and will cause the capsule to be processed by the firmware as + part of the reset process. + + @param[in] CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules + being passed into update capsule. + @param[in] CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in + CaspuleHeaderArray. + @param[in] ScatterGatherList Physical pointer to a set of + EFI_CAPSULE_BLOCK_DESCRIPTOR that describes the + location in physical memory of a set of capsules. + + @retval EFI_SUCCESS Valid capsule was passed. If + CAPSULE_FLAGS_PERSIT_ACROSS_RESET is not set, the + capsule has been successfully processed by the firmware. + @retval EFI_INVALID_PARAMETER CapsuleSize is NULL, or an incompatible set of flags were + set in the capsule header. + @retval EFI_INVALID_PARAMETER CapsuleCount is 0. + @retval EFI_DEVICE_ERROR The capsule update was started, but failed due to a device error. + @retval EFI_UNSUPPORTED The capsule type is not supported on this platform. + @retval EFI_OUT_OF_RESOURCES When ExitBootServices() has been previously called this error indicates the capsule + is compatible with this platform but is not capable of being submitted or processed + in runtime. The caller may resubmit the capsule prior to ExitBootServices(). + @retval EFI_OUT_OF_RESOURCES When ExitBootServices() has not been previously called then this error indicates + the capsule is compatible with this platform but there are insufficient resources to process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_UPDATE_CAPSULE)( + IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, + IN UINTN CapsuleCount, + IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL + ); + +/** + Returns if the capsule can be supported via UpdateCapsule(). + + @param[in] CapsuleHeaderArray Virtual pointer to an array of virtual pointers to the capsules + being passed into update capsule. + @param[in] CapsuleCount Number of pointers to EFI_CAPSULE_HEADER in + CaspuleHeaderArray. + @param[out] MaxiumCapsuleSize On output the maximum size that UpdateCapsule() can + support as an argument to UpdateCapsule() via + CapsuleHeaderArray and ScatterGatherList. + @param[out] ResetType Returns the type of reset required for the capsule update. + + @retval EFI_SUCCESS Valid answer returned. + @retval EFI_UNSUPPORTED The capsule type is not supported on this platform, and + MaximumCapsuleSize and ResetType are undefined. + @retval EFI_INVALID_PARAMETER MaximumCapsuleSize is NULL. + @retval EFI_OUT_OF_RESOURCES When ExitBootServices() has been previously called this error indicates the capsule + is compatible with this platform but is not capable of being submitted or processed + in runtime. The caller may resubmit the capsule prior to ExitBootServices(). + @retval EFI_OUT_OF_RESOURCES When ExitBootServices() has not been previously called then this error indicates + the capsule is compatible with this platform but there are insufficient resources to process. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_QUERY_CAPSULE_CAPABILITIES)( + IN EFI_CAPSULE_HEADER **CapsuleHeaderArray, + IN UINTN CapsuleCount, + OUT UINT64 *MaximumCapsuleSize, + OUT EFI_RESET_TYPE *ResetType + ); + +/** + Returns information about the EFI variables. + + @param[in] Attributes Attributes bitmask to specify the type of variables on + which to return information. + @param[out] MaximumVariableStorageSize On output the maximum size of the storage space + available for the EFI variables associated with the + attributes specified. + @param[out] RemainingVariableStorageSize Returns the remaining size of the storage space + available for the EFI variables associated with the + attributes specified. + @param[out] MaximumVariableSize Returns the maximum size of the individual EFI + variables associated with the attributes specified. + + @retval EFI_SUCCESS Valid answer returned. + @retval EFI_INVALID_PARAMETER An invalid combination of attribute bits was supplied + @retval EFI_UNSUPPORTED The attribute is not supported on this platform, and the + MaximumVariableStorageSize, + RemainingVariableStorageSize, MaximumVariableSize + are undefined. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_QUERY_VARIABLE_INFO)( + IN UINT32 Attributes, + OUT UINT64 *MaximumVariableStorageSize, + OUT UINT64 *RemainingVariableStorageSize, + OUT UINT64 *MaximumVariableSize + ); + +// +// Firmware should stop at a firmware user interface on next boot +// +#define EFI_OS_INDICATIONS_BOOT_TO_FW_UI 0x0000000000000001 +#define EFI_OS_INDICATIONS_TIMESTAMP_REVOCATION 0x0000000000000002 +#define EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED 0x0000000000000004 +#define EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED 0x0000000000000008 +#define EFI_OS_INDICATIONS_CAPSULE_RESULT_VAR_SUPPORTED 0x0000000000000010 +#define EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY 0x0000000000000040 +#define EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH 0x0000000000000080 + +// +// EFI Runtime Services Table +// +#define EFI_SYSTEM_TABLE_SIGNATURE SIGNATURE_64 ('I','B','I',' ','S','Y','S','T') +#define EFI_2_80_SYSTEM_TABLE_REVISION ((2 << 16) | (80)) +#define EFI_2_70_SYSTEM_TABLE_REVISION ((2 << 16) | (70)) +#define EFI_2_60_SYSTEM_TABLE_REVISION ((2 << 16) | (60)) +#define EFI_2_50_SYSTEM_TABLE_REVISION ((2 << 16) | (50)) +#define EFI_2_40_SYSTEM_TABLE_REVISION ((2 << 16) | (40)) +#define EFI_2_31_SYSTEM_TABLE_REVISION ((2 << 16) | (31)) +#define EFI_2_30_SYSTEM_TABLE_REVISION ((2 << 16) | (30)) +#define EFI_2_20_SYSTEM_TABLE_REVISION ((2 << 16) | (20)) +#define EFI_2_10_SYSTEM_TABLE_REVISION ((2 << 16) | (10)) +#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | (00)) +#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | (10)) +#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | (02)) +#define EFI_SYSTEM_TABLE_REVISION EFI_2_70_SYSTEM_TABLE_REVISION +#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION + +#define EFI_RUNTIME_SERVICES_SIGNATURE SIGNATURE_64 ('R','U','N','T','S','E','R','V') +#define EFI_RUNTIME_SERVICES_REVISION EFI_SPECIFICATION_VERSION + +/// +/// EFI Runtime Services Table. +/// +typedef struct { + /// + /// The table header for the EFI Runtime Services Table. + /// + EFI_TABLE_HEADER Hdr; + + // + // Time Services + // + EFI_GET_TIME GetTime; + EFI_SET_TIME SetTime; + EFI_GET_WAKEUP_TIME GetWakeupTime; + EFI_SET_WAKEUP_TIME SetWakeupTime; + + // + // Virtual Memory Services + // + EFI_SET_VIRTUAL_ADDRESS_MAP SetVirtualAddressMap; + EFI_CONVERT_POINTER ConvertPointer; + + // + // Variable Services + // + EFI_GET_VARIABLE GetVariable; + EFI_GET_NEXT_VARIABLE_NAME GetNextVariableName; + EFI_SET_VARIABLE SetVariable; + + // + // Miscellaneous Services + // + EFI_GET_NEXT_HIGH_MONO_COUNT GetNextHighMonotonicCount; + EFI_RESET_SYSTEM ResetSystem; + + // + // UEFI 2.0 Capsule Services + // + EFI_UPDATE_CAPSULE UpdateCapsule; + EFI_QUERY_CAPSULE_CAPABILITIES QueryCapsuleCapabilities; + + // + // Miscellaneous UEFI 2.0 Service + // + EFI_QUERY_VARIABLE_INFO QueryVariableInfo; +} EFI_RUNTIME_SERVICES; + + +#define EFI_BOOT_SERVICES_SIGNATURE SIGNATURE_64 ('B','O','O','T','S','E','R','V') +#define EFI_BOOT_SERVICES_REVISION EFI_SPECIFICATION_VERSION + +/// +/// EFI Boot Services Table. +/// +typedef struct { + /// + /// The table header for the EFI Boot Services Table. + /// + EFI_TABLE_HEADER Hdr; + + // + // Task Priority Services + // + EFI_RAISE_TPL RaiseTPL; + EFI_RESTORE_TPL RestoreTPL; + + // + // Memory Services + // + EFI_ALLOCATE_PAGES AllocatePages; + EFI_FREE_PAGES FreePages; + EFI_GET_MEMORY_MAP GetMemoryMap; + EFI_ALLOCATE_POOL AllocatePool; + EFI_FREE_POOL FreePool; + + // + // Event & Timer Services + // + EFI_CREATE_EVENT CreateEvent; + EFI_SET_TIMER SetTimer; + EFI_WAIT_FOR_EVENT WaitForEvent; + EFI_SIGNAL_EVENT SignalEvent; + EFI_CLOSE_EVENT CloseEvent; + EFI_CHECK_EVENT CheckEvent; + + // + // Protocol Handler Services + // + EFI_INSTALL_PROTOCOL_INTERFACE InstallProtocolInterface; + EFI_REINSTALL_PROTOCOL_INTERFACE ReinstallProtocolInterface; + EFI_UNINSTALL_PROTOCOL_INTERFACE UninstallProtocolInterface; + EFI_HANDLE_PROTOCOL HandleProtocol; + VOID *Reserved; + EFI_REGISTER_PROTOCOL_NOTIFY RegisterProtocolNotify; + EFI_LOCATE_HANDLE LocateHandle; + EFI_LOCATE_DEVICE_PATH LocateDevicePath; + EFI_INSTALL_CONFIGURATION_TABLE InstallConfigurationTable; + + // + // Image Services + // + EFI_IMAGE_LOAD LoadImage; + EFI_IMAGE_START StartImage; + EFI_EXIT Exit; + EFI_IMAGE_UNLOAD UnloadImage; + EFI_EXIT_BOOT_SERVICES ExitBootServices; + + // + // Miscellaneous Services + // + EFI_GET_NEXT_MONOTONIC_COUNT GetNextMonotonicCount; + EFI_STALL Stall; + EFI_SET_WATCHDOG_TIMER SetWatchdogTimer; + + // + // DriverSupport Services + // + EFI_CONNECT_CONTROLLER ConnectController; + EFI_DISCONNECT_CONTROLLER DisconnectController; + + // + // Open and Close Protocol Services + // + EFI_OPEN_PROTOCOL OpenProtocol; + EFI_CLOSE_PROTOCOL CloseProtocol; + EFI_OPEN_PROTOCOL_INFORMATION OpenProtocolInformation; + + // + // Library Services + // + EFI_PROTOCOLS_PER_HANDLE ProtocolsPerHandle; + EFI_LOCATE_HANDLE_BUFFER LocateHandleBuffer; + EFI_LOCATE_PROTOCOL LocateProtocol; + EFI_INSTALL_MULTIPLE_PROTOCOL_INTERFACES InstallMultipleProtocolInterfaces; + EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES UninstallMultipleProtocolInterfaces; + + // + // 32-bit CRC Services + // + EFI_CALCULATE_CRC32 CalculateCrc32; + + // + // Miscellaneous Services + // + EFI_COPY_MEM CopyMem; + EFI_SET_MEM SetMem; + EFI_CREATE_EVENT_EX CreateEventEx; +} EFI_BOOT_SERVICES; + +/// +/// Contains a set of GUID/pointer pairs comprised of the ConfigurationTable field in the +/// EFI System Table. +/// +typedef struct { + /// + /// The 128-bit GUID value that uniquely identifies the system configuration table. + /// + EFI_GUID VendorGuid; + /// + /// A pointer to the table associated with VendorGuid. + /// + VOID *VendorTable; +} EFI_CONFIGURATION_TABLE; + +/// +/// EFI System Table +/// +typedef struct { + /// + /// The table header for the EFI System Table. + /// + EFI_TABLE_HEADER Hdr; + /// + /// A pointer to a null terminated string that identifies the vendor + /// that produces the system firmware for the platform. + /// + CHAR16 *FirmwareVendor; + /// + /// A firmware vendor specific value that identifies the revision + /// of the system firmware for the platform. + /// + UINT32 FirmwareRevision; + /// + /// The handle for the active console input device. This handle must support + /// EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. + /// + EFI_HANDLE ConsoleInHandle; + /// + /// A pointer to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL interface that is + /// associated with ConsoleInHandle. + /// + EFI_SIMPLE_TEXT_INPUT_PROTOCOL *ConIn; + /// + /// The handle for the active console output device. + /// + EFI_HANDLE ConsoleOutHandle; + /// + /// A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface + /// that is associated with ConsoleOutHandle. + /// + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *ConOut; + /// + /// The handle for the active standard error console device. + /// This handle must support the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL. + /// + EFI_HANDLE StandardErrorHandle; + /// + /// A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface + /// that is associated with StandardErrorHandle. + /// + EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *StdErr; + /// + /// A pointer to the EFI Runtime Services Table. + /// + EFI_RUNTIME_SERVICES *RuntimeServices; + /// + /// A pointer to the EFI Boot Services Table. + /// + EFI_BOOT_SERVICES *BootServices; + /// + /// The number of system configuration tables in the buffer ConfigurationTable. + /// + UINTN NumberOfTableEntries; + /// + /// A pointer to the system configuration tables. + /// The number of entries in the table is NumberOfTableEntries. + /// + EFI_CONFIGURATION_TABLE *ConfigurationTable; +} EFI_SYSTEM_TABLE; + +/** + This is the declaration of an EFI image entry point. This entry point is + the same for UEFI Applications, UEFI OS Loaders, and UEFI Drivers including + both device drivers and bus drivers. + + @param[in] ImageHandle The firmware allocated handle for the UEFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Others An unexpected error occurred. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_IMAGE_ENTRY_POINT)( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +// +// EFI Load Option. This data structure describes format of UEFI boot option variables. +// +// NOTE: EFI Load Option is a byte packed buffer of variable length fields. +// The first two fields have fixed length. They are declared as members of the +// EFI_LOAD_OPTION structure. All the other fields are variable length fields. +// They are listed in the comment block below for reference purposes. +// +#pragma pack(1) +typedef struct _EFI_LOAD_OPTION { + /// + /// The attributes for this load option entry. All unused bits must be zero + /// and are reserved by the UEFI specification for future growth. + /// + UINT32 Attributes; + /// + /// Length in bytes of the FilePathList. OptionalData starts at offset + /// sizeof(UINT32) + sizeof(UINT16) + StrSize(Description) + FilePathListLength + /// of the EFI_LOAD_OPTION descriptor. + /// + UINT16 FilePathListLength; + /// + /// The user readable description for the load option. + /// This field ends with a Null character. + /// + // CHAR16 Description[]; + /// + /// A packed array of UEFI device paths. The first element of the array is a + /// device path that describes the device and location of the Image for this + /// load option. The FilePathList[0] is specific to the device type. Other + /// device paths may optionally exist in the FilePathList, but their usage is + /// OSV specific. Each element in the array is variable length, and ends at + /// the device path end structure. Because the size of Description is + /// arbitrary, this data structure is not guaranteed to be aligned on a + /// natural boundary. This data structure may have to be copied to an aligned + /// natural boundary before it is used. + /// + // EFI_DEVICE_PATH_PROTOCOL FilePathList[]; + /// + /// The remaining bytes in the load option descriptor are a binary data buffer + /// that is passed to the loaded image. If the field is zero bytes long, a + /// NULL pointer is passed to the loaded image. The number of bytes in + /// OptionalData can be computed by subtracting the starting offset of + /// OptionalData from total size in bytes of the EFI_LOAD_OPTION. + /// + // UINT8 OptionalData[]; +} EFI_LOAD_OPTION; +#pragma pack() + +// +// EFI Load Options Attributes +// +#define LOAD_OPTION_ACTIVE 0x00000001 +#define LOAD_OPTION_FORCE_RECONNECT 0x00000002 +#define LOAD_OPTION_HIDDEN 0x00000008 +#define LOAD_OPTION_CATEGORY 0x00001F00 + +#define LOAD_OPTION_CATEGORY_BOOT 0x00000000 +#define LOAD_OPTION_CATEGORY_APP 0x00000100 + +#define EFI_BOOT_OPTION_SUPPORT_KEY 0x00000001 +#define EFI_BOOT_OPTION_SUPPORT_APP 0x00000002 +#define EFI_BOOT_OPTION_SUPPORT_SYSPREP 0x00000010 +#define EFI_BOOT_OPTION_SUPPORT_COUNT 0x00000300 + +/// +/// EFI Boot Key Data +/// +typedef union { + struct { + /// + /// Indicates the revision of the EFI_KEY_OPTION structure. This revision level should be 0. + /// + UINT32 Revision : 8; + /// + /// Either the left or right Shift keys must be pressed (1) or must not be pressed (0). + /// + UINT32 ShiftPressed : 1; + /// + /// Either the left or right Control keys must be pressed (1) or must not be pressed (0). + /// + UINT32 ControlPressed : 1; + /// + /// Either the left or right Alt keys must be pressed (1) or must not be pressed (0). + /// + UINT32 AltPressed : 1; + /// + /// Either the left or right Logo keys must be pressed (1) or must not be pressed (0). + /// + UINT32 LogoPressed : 1; + /// + /// The Menu key must be pressed (1) or must not be pressed (0). + /// + UINT32 MenuPressed : 1; + /// + /// The SysReq key must be pressed (1) or must not be pressed (0). + /// + UINT32 SysReqPressed : 1; + UINT32 Reserved : 16; + /// + /// Specifies the actual number of entries in EFI_KEY_OPTION.Keys, from 0-3. If + /// zero, then only the shift state is considered. If more than one, then the boot option will + /// only be launched if all of the specified keys are pressed with the same shift state. + /// + UINT32 InputKeyCount : 2; + } Options; + UINT32 PackedValue; +} EFI_BOOT_KEY_DATA; + +/// +/// EFI Key Option. +/// +#pragma pack(1) +typedef struct { + /// + /// Specifies options about how the key will be processed. + /// + EFI_BOOT_KEY_DATA KeyData; + /// + /// The CRC-32 which should match the CRC-32 of the entire EFI_LOAD_OPTION to + /// which BootOption refers. If the CRC-32s do not match this value, then this key + /// option is ignored. + /// + UINT32 BootOptionCrc; + /// + /// The Boot#### option which will be invoked if this key is pressed and the boot option + /// is active (LOAD_OPTION_ACTIVE is set). + /// + UINT16 BootOption; + /// + /// The key codes to compare against those returned by the + /// EFI_SIMPLE_TEXT_INPUT and EFI_SIMPLE_TEXT_INPUT_EX protocols. + /// The number of key codes (0-3) is specified by the EFI_KEY_CODE_COUNT field in KeyOptions. + /// + //EFI_INPUT_KEY Keys[]; +} EFI_KEY_OPTION; +#pragma pack() + +// +// EFI File location to boot from on removable media devices +// +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI" +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI" + +#if !defined(EFI_REMOVABLE_MEDIA_FILE_NAME) +#if defined (MDE_CPU_IA32) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 +#elif defined (MDE_CPU_X64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64 +#elif defined (MDE_CPU_EBC) +#elif defined (MDE_CPU_ARM) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM +#elif defined (MDE_CPU_AARCH64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 +#elif defined (MDE_CPU_RISCV64) + #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 +#else + #error Unknown Processor Type +#endif +#endif + +// +// The directory within the active EFI System Partition defined for delivery of capsule to firmware +// +#define EFI_CAPSULE_FILE_DIRECTORY L"\\EFI\\UpdateCapsule\\" + +#include +#include +#include + +#endif diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/Nasm.inc b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/Nasm.inc new file mode 100644 index 0000000000..51dc5341ae --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/Nasm.inc @@ -0,0 +1,88 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Abstract: +; +; This file provides macro definitions for NASM files. +; +;------------------------------------------------------------------------------ + +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_RAX 0 + DB 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_RAX 0 + DB 0xF3, 0x0F, 0x01, 0x28 +%endmacro + +%macro SETSSBSY 0 + DB 0xF3, 0x0F, 0x01, 0xE8 +%endmacro + +%macro READSSP_RAX 0 + DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8 +%endmacro + +%macro INCSSP_RAX 0 + DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8 +%endmacro + +; +; Macro for the PVALIDATE instruction, defined in AMD APM volume 3. +; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753 +; +%macro PVALIDATE 0 + DB 0xF2, 0x0F, 0x01, 0xFF +%endmacro + +; +; Macro for the RMPADJUST instruction, defined in AMD APM volume 3. +; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392754 +; +%macro RMPADJUST 0 + DB 0xF3, 0x0F, 0x01, 0xFE +%endmacro + +; NASM provides built-in macros STRUC and ENDSTRUC for structure definition. +; For example, to define a structure called mytype containing a longword, +; a word, a byte and a string of bytes, you might code +; +; struc mytype +; +; mt_long: resd 1 +; mt_word: resw 1 +; mt_byte: resb 1 +; mt_str: resb 32 +; +; endstruc +; +; Below macros are help to map the C types and the RESB family of pseudo-instructions. +; So that the above structure definition can be coded as +; +; struc mytype +; +; mt_long: CTYPE_UINT32 1 +; mt_word: CTYPE_UINT16 1 +; mt_byte: CTYPE_UINT8 1 +; mt_str: CTYPE_CHAR8 32 +; +; endstruc +%define CTYPE_UINT64 resq +%define CTYPE_INT64 resq +%define CTYPE_UINT32 resd +%define CTYPE_INT32 resd +%define CTYPE_UINT16 resw +%define CTYPE_INT16 resw +%define CTYPE_BOOLEAN resb +%define CTYPE_UINT8 resb +%define CTYPE_CHAR8 resb +%define CTYPE_INT8 resb + +%define CTYPE_UINTN resq +%define CTYPE_INTN resq diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/ProcessorBind.h b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/ProcessorBind.h new file mode 100644 index 0000000000..a1b947c5a3 --- /dev/null +++ b/src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/X64/ProcessorBind.h @@ -0,0 +1,341 @@ +/** @file + Processor or Compiler specific defines and types x64 (Intel 64, AMD64). + + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PROCESSOR_BIND_H__ +#define __PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_X64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +#if defined(__GNUC__) && defined(__pic__) && !defined(USING_LTO) && !defined(__APPLE__) +// +// Mark all symbol declarations and references as hidden, meaning they will +// not be subject to symbol preemption. This allows the compiler to refer to +// symbols directly using relative references rather than via the GOT, which +// contains absolute symbol addresses that are subject to runtime relocation. +// +// The LTO linker will not emit GOT based relocations when all symbol +// references can be resolved locally, and so there is no need to set the +// pragma in that case (and doing so will cause other issues). +// +#pragma GCC visibility push (hidden) +#endif + +#if defined(__INTEL_COMPILER) +// +// Disable ICC's remark #869: "Parameter" was never referenced warning. +// This is legal ANSI C code so we disable the remark that is turned on with -Wall +// +#pragma warning ( disable : 869 ) + +// +// Disable ICC's remark #1418: external function definition with no prior declaration. +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 1418 ) + +// +// Disable ICC's remark #1419: external declaration in primary source file +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 1419 ) + +// +// Disable ICC's remark #593: "Variable" was set but never used. +// This is legal ANSI C code so we disable the remark that is turned on with /W4 +// +#pragma warning ( disable : 593 ) + +#endif + + +#if defined(_MSC_EXTENSIONS) + +// +// Disable warning that make it impossible to compile at /W4 +// This only works for Microsoft* tools +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompiled header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For precompiled header only. +// +#pragma warning ( disable : 4206 ) + +#if defined(_MSC_VER) && _MSC_VER >= 1800 + +// +// Disable these warnings for VS2013. +// + +// +// This warning is for potentially uninitialized local variable, and it may cause false +// positive issues in VS2013 and VS2015 build +// +#pragma warning ( disable : 4701 ) + +// +// This warning is for potentially uninitialized local pointer variable, and it may cause +// false positive issues in VS2013 and VS2015 build +// +#pragma warning ( disable : 4703 ) + +#endif + +#endif + + +#if defined(_MSC_EXTENSIONS) + // + // use Microsoft C compiler dependent integer width types + // + + /// + /// 8-byte unsigned value + /// + typedef unsigned __int64 UINT64; + /// + /// 8-byte signed value + /// + typedef __int64 INT64; + /// + /// 4-byte unsigned value + /// + typedef unsigned __int32 UINT32; + /// + /// 4-byte signed value + /// + typedef __int32 INT32; + /// + /// 2-byte unsigned value + /// + typedef unsigned short UINT16; + /// + /// 2-byte Character. Unless otherwise specified all strings are stored in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. + /// + typedef unsigned short CHAR16; + /// + /// 2-byte signed value + /// + typedef short INT16; + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character + /// + typedef char CHAR8; + /// + /// 1-byte signed value + /// + typedef signed char INT8; +#else + /// + /// 8-byte unsigned value + /// + typedef unsigned long long UINT64; + /// + /// 8-byte signed value + /// + typedef long long INT64; + /// + /// 4-byte unsigned value + /// + typedef unsigned int UINT32; + /// + /// 4-byte signed value + /// + typedef int INT32; + /// + /// 2-byte unsigned value + /// + typedef unsigned short UINT16; + /// + /// 2-byte Character. Unless otherwise specified all strings are stored in the + /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. + /// + typedef unsigned short CHAR16; + /// + /// 2-byte signed value + /// + typedef short INT16; + /// + /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other + /// values are undefined. + /// + typedef unsigned char BOOLEAN; + /// + /// 1-byte unsigned value + /// + typedef unsigned char UINT8; + /// + /// 1-byte Character + /// + typedef char CHAR8; + /// + /// 1-byte signed value + /// + typedef signed char INT8; +#endif + +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN; +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN; + + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal x64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + +/// +/// Maximum legal x64 INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// Minimum legal x64 INTN value. +/// +#define MIN_INTN (((INTN)-9223372036854775807LL) - 1) + +/// +/// The stack alignment required for x64 +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for x64 +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(_MSC_EXTENSIONS) + /// + /// Microsoft* compiler specific method for EFIAPI calling convention. + /// + #define EFIAPI __cdecl +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization level. + /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for + /// x64. Warning the assembly code in the MDE x64 does not follow the correct + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) || defined(__clang__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif + diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 9e1a414f48..a687eb0ad1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -78,69 +78,85 @@ typedef struct { **/ UINT8 CpuCrashLogDevice; -/** Offset 0x004C - MemorySpdPtr00 +/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr00; + UINT32 MemorySpdPtr000; -/** Offset 0x0050 - MemorySpdPtr01 +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr01; + UINT32 MemorySpdPtr001; -/** Offset 0x0054 - MemorySpdPtr02 +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr02; + UINT32 MemorySpdPtr010; -/** Offset 0x0058 - MemorySpdPtr03 +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr03; + UINT32 MemorySpdPtr011; -/** Offset 0x005C - MemorySpdPtr04 +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr04; + UINT32 MemorySpdPtr020; -/** Offset 0x0060 - MemorySpdPtr05 +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr05; + UINT32 MemorySpdPtr021; -/** Offset 0x0064 - MemorySpdPtr06 +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr06; + UINT32 MemorySpdPtr030; -/** Offset 0x0068 - MemorySpdPtr07 +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr07; + UINT32 MemorySpdPtr031; -/** Offset 0x006C - MemorySpdPtr08 +/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr08; + UINT32 MemorySpdPtr100; -/** Offset 0x0070 - MemorySpdPtr09 +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr09; + UINT32 MemorySpdPtr101; -/** Offset 0x0074 - MemorySpdPtr10 +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr10; + UINT32 MemorySpdPtr110; -/** Offset 0x0078 - MemorySpdPtr11 +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr11; + UINT32 MemorySpdPtr111; -/** Offset 0x007C - MemorySpdPtr12 +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr12; + UINT32 MemorySpdPtr120; -/** Offset 0x0080 - MemorySpdPtr13 +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr13; + UINT32 MemorySpdPtr121; -/** Offset 0x0084 - MemorySpdPtr14 +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr14; + UINT32 MemorySpdPtr130; -/** Offset 0x0088 - MemorySpdPtr15 +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ - UINT32 MemorySpdPtr15; + UINT32 MemorySpdPtr131; /** Offset 0x008C - RcompResistor settings Indicates RcompResistor settings: Board-dependent @@ -152,69 +168,85 @@ typedef struct { **/ UINT16 RcompTarget[5]; -/** Offset 0x0098 - DqsMapCpu2DramCh0 +/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ - UINT8 DqsMapCpu2DramCh0[2]; + UINT8 DqsMapCpu2DramMc0Ch0[2]; -/** Offset 0x009A - DqsMapCpu2DramCh1 +/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ - UINT8 DqsMapCpu2DramCh1[2]; + UINT8 DqsMapCpu2DramMc0Ch1[2]; -/** Offset 0x009C - DqsMapCpu2DramCh2 +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ - UINT8 DqsMapCpu2DramCh2[2]; + UINT8 DqsMapCpu2DramMc0Ch2[2]; -/** Offset 0x009E - DqsMapCpu2DramCh3 +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ - UINT8 DqsMapCpu2DramCh3[2]; + UINT8 DqsMapCpu2DramMc0Ch3[2]; -/** Offset 0x00A0 - DqsMapCpu2DramCh4 +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ - UINT8 DqsMapCpu2DramCh4[2]; + UINT8 DqsMapCpu2DramMc1Ch0[2]; -/** Offset 0x00A2 - DqsMapCpu2DramCh5 +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ - UINT8 DqsMapCpu2DramCh5[2]; + UINT8 DqsMapCpu2DramMc1Ch1[2]; -/** Offset 0x00A4 - DqsMapCpu2DramCh6 +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ - UINT8 DqsMapCpu2DramCh6[2]; + UINT8 DqsMapCpu2DramMc1Ch2[2]; -/** Offset 0x00A6 - DqsMapCpu2DramCh7 +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ - UINT8 DqsMapCpu2DramCh7[2]; + UINT8 DqsMapCpu2DramMc1Ch3[2]; -/** Offset 0x00A8 - DqMapCpu2DramCh0 +/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ - UINT8 DqMapCpu2DramCh0[16]; + UINT8 DqMapCpu2DramMc0Ch0[16]; -/** Offset 0x00B8 - DqMapCpu2DramCh1 +/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ - UINT8 DqMapCpu2DramCh1[16]; + UINT8 DqMapCpu2DramMc0Ch1[16]; -/** Offset 0x00C8 - DqMapCpu2DramCh2 +/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet **/ - UINT8 DqMapCpu2DramCh2[16]; + UINT8 DqMapCpu2DramMc0Ch2[16]; -/** Offset 0x00D8 - DqMapCpu2DramCh3 +/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ - UINT8 DqMapCpu2DramCh3[16]; + UINT8 DqMapCpu2DramMc0Ch3[16]; -/** Offset 0x00E8 - DqMapCpu2DramCh4 +/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ - UINT8 DqMapCpu2DramCh4[16]; + UINT8 DqMapCpu2DramMc1Ch0[16]; -/** Offset 0x00F8 - DqMapCpu2DramCh5 +/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ - UINT8 DqMapCpu2DramCh5[16]; + UINT8 DqMapCpu2DramMc1Ch1[16]; -/** Offset 0x0108 - DqMapCpu2DramCh6 +/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ - UINT8 DqMapCpu2DramCh6[16]; + UINT8 DqMapCpu2DramMc1Ch2[16]; -/** Offset 0x0118 - DqMapCpu2DramCh7 +/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ - UINT8 DqMapCpu2DramCh7[16]; + UINT8 DqMapCpu2DramMc1Ch3[16]; /** Offset 0x0128 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent @@ -454,10 +486,10 @@ typedef struct { UINT8 ApertureSize; /** Offset 0x01D0 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC - DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 2:Desktop 2DPC DDR5, 5:ULT/ULX/Mobile Halo - Type3, 6:ULT/ULX/Mobile Halo Type4, 8:UP Server + MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server + 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server **/ UINT8 UserBd; @@ -474,7 +506,7 @@ typedef struct { /** Offset 0x01D4 - SA GV System Agent dynamic frequency support and when enabled memory will be training - at three different frequencies. + at four different frequencies. 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled **/ UINT8 SaGv; @@ -899,13 +931,18 @@ typedef struct { **/ UINT8 CpuPcieRpLinkDownGpios; -/** Offset 0x0271 - RpClockReqMsgEnable +/** Offset 0x0271 - Enable ClockReq Messaging + ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): + Enable ClockReq Messaging + 0:Disable, 1:Enable **/ - UINT8 RpClockReqMsgEnable[3]; + UINT8 CpuPcieRpClockReqMsgEnable[3]; -/** Offset 0x0274 - RpPcieThresholdBytes +/** Offset 0x0274 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: CPU_PCIE_SPEED). **/ - UINT8 RpPcieThresholdBytes[4]; + UINT8 CpuPcieRpPcieSpeed[4]; /** Offset 0x0278 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support @@ -1966,9 +2003,11 @@ typedef struct { **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x080D - Reserved +/** Offset 0x080D - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS **/ - UINT8 Reserved27; + UINT8 CnviDdrRfim; /** Offset 0x080E - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1991,7 +2030,7 @@ typedef struct { /** Offset 0x0811 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved27[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2019,7 +2058,7 @@ typedef struct { /** Offset 0x081B - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved28; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2339,7 +2378,7 @@ typedef struct { /** Offset 0x0854 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2379,7 +2418,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2485,7 +2524,7 @@ typedef struct { /** Offset 0x086D - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2544,7 +2583,7 @@ typedef struct { /** Offset 0x087E - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -2754,7 +2793,7 @@ typedef struct { /** Offset 0x08A8 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2786,7 +2825,7 @@ typedef struct { /** Offset 0x08AF - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2860,7 +2899,7 @@ typedef struct { /** Offset 0x08BB - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -2887,7 +2926,7 @@ typedef struct { /** Offset 0x08C1 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2937,7 +2976,7 @@ typedef struct { /** Offset 0x08DB - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x08DE - REFRESH_PANIC_WM DEPRECATED @@ -2963,7 +3002,7 @@ typedef struct { /** Offset 0x08E2 - Reserved **/ - UINT8 Reserved39[9]; + UINT8 Reserved38[9]; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2986,7 +3025,7 @@ typedef struct { /** Offset 0x08EE - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -3003,7 +3042,7 @@ typedef struct { /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved40[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3017,7 +3056,7 @@ typedef struct { /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved42[95]; + UINT8 Reserved41[95]; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3033,7 +3072,7 @@ typedef struct { /** Offset 0x095C - Reserved **/ - UINT8 Reserved43[12]; + UINT8 Reserved42[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3099,7 +3138,7 @@ typedef struct { /** Offset 0x0972 - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved43[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3136,7 +3175,7 @@ typedef struct { /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved44; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3162,7 +3201,7 @@ typedef struct { /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved46[104]; + UINT8 Reserved45[144]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3181,11 +3220,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0B10 +/** Offset 0x0B38 **/ - UINT8 UnusedUpdSpace31[6]; + UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0B16 +/** Offset 0x0B3E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index ddf6ca87ff..6e7ebfd922 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -2852,9 +2852,11 @@ typedef struct { **/ UINT8 CpuPcieRpLtrConfigLock[4]; -/** Offset 0x0C38 - RpPtmBytes +/** Offset 0x0C38 - PTM for PCIE RP Mask + Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ - UINT8 RpPtmBytes[4]; + UINT8 CpuPcieRpPtmEnabled[4]; /** Offset 0x0C3C - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to @@ -3380,8 +3382,7 @@ typedef struct { UINT8 ProcHotLock; /** Offset 0x0CF3 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate + Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; @@ -3766,9 +3767,12 @@ typedef struct { **/ UINT8 PchXhciOcLock; -/** Offset 0x0F55 - LpmStateEnableMask +/** Offset 0x0F55 - Low Power Mode Enable/Disable config mask + Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds + to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ - UINT8 LpmStateEnableMask; + UINT8 PmcLpmS0ixSubStateEnableMask; /** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3869,7 +3873,7 @@ typedef struct { /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved56[19]; + UINT8 Reserved56[123]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3888,11 +3892,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0FE8 +/** Offset 0x1050 **/ UINT8 UnusedUpdSpace42[6]; -/** Offset 0x0FEE +/** Offset 0x1056 **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h similarity index 100% rename from src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FirmwareVersionInfoHob.h rename to src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h similarity index 83% rename from src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h rename to src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h index 20f6d63a64..ff33917f68 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,11 +37,11 @@ are permitted provided that the following conditions are met: #pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C4845 /* 'EHLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4845 /* 'EHLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C4845 /* 'EHLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */ #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h new file mode 100644 index 0000000000..a687eb0ad1 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h @@ -0,0 +1,3234 @@ +/** @file + +Copyright (c) 2022, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include + +#pragma pack(1) + + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x004B - Enable/Disable CrashLog Device 10 + Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog + $EN_DIS +**/ + UINT8 CpuCrashLogDevice; + +/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr000; + +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr001; + +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr010; + +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr011; + +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr020; + +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr021; + +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr030; + +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr031; + +/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr100; + +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr101; + +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr110; + +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr111; + +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr120; + +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr121; + +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr130; + +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr131; + +/** Offset 0x008C - RcompResistor settings + Indicates RcompResistor settings: Board-dependent +**/ + UINT16 RcompResistor; + +/** Offset 0x008E - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch0[2]; + +/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch1[2]; + +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch2[2]; + +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc0Ch3[2]; + +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch0[2]; + +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch1[2]; + +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 + Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch2[2]; + +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 + Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqsMapCpu2DramMc1Ch3[2]; + +/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch0[16]; + +/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch1[16]; + +/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet +**/ + UINT8 DqMapCpu2DramMc0Ch2[16]; + +/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc0Ch3[16]; + +/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 + Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch0[16]; + +/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 + Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch1[16]; + +/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 + Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch2[16]; + +/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 + Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent +**/ + UINT8 DqMapCpu2DramMc1Ch3[16]; + +/** Offset 0x0128 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0129 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x012A - Ibecc + Enable/Disable Ibecc + $EN_DIS +**/ + UINT8 Ibecc; + +/** Offset 0x012B - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1:Non-protected, 2:All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x012C - IbeccProtectedRangeEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRangeEnable[8]; + +/** Offset 0x0134 - IbeccProtectedRangeBase + IBECC Protected Region Base +**/ + UINT32 IbeccProtectedRangeBase[8]; + +/** Offset 0x0154 - IbeccProtectedRangeMask + IBECC Protected Region Mask +**/ + UINT32 IbeccProtectedRangeMask[8]; + +/** Offset 0x0174 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0175 - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x0176 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x0177 - Reserved +**/ + UINT8 Reserved0; + +/** Offset 0x0178 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x017C - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x017E - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x017F - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x0180 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[16]; + +/** Offset 0x0190 - Platform Debug Consent + Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks + s0ix\n + \n + Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by + default, s0ix is viable\n + \n + Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users + 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x0191 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x0192 - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x0193 - Enable DCI ModPHY Power Gate + DEPRECATED + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x0194 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x0195 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0196 - PCH Trace Hub Memory Region 0 buffer Size + Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg0Size; + +/** Offset 0x0197 - PCH Trace Hub Memory Region 1 buffer Size + Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg1Size; + +/** Offset 0x0198 - HD Audio DMIC Link Clock Select + Determines DMIC Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB +**/ + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x019A - Reserved +**/ + UINT8 Reserved1[5]; + +/** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x01A0 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x01A1 - Reserved +**/ + UINT8 Reserved2[3]; + +/** Offset 0x01A4 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x01C8 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x01C9 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x01CA - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x01CB - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x01CC - Vtd Programming for ITbt + DEPRECATED + $EN_DIS +**/ + UINT8 VtdItbtEnable; + +/** Offset 0x01CD - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x01CE - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x01CF - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x01D0 - Board Type + MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server + 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, + 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x01D1 - Reserved +**/ + UINT8 Reserved3; + +/** Offset 0x01D2 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x01D4 - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at four different frequencies. + 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x01D5 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x01D6 - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x01D7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc0Ch0; + +/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc0Ch1; + +/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc0Ch2; + +/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 0 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc0Ch3; + +/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 0 + $EN_DIS +**/ + UINT8 DisableMc1Ch0; + +/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 1 + $EN_DIS +**/ + UINT8 DisableMc1Ch1; + +/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 2 + $EN_DIS +**/ + UINT8 DisableMc1Ch2; + +/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control + Enable / Disable DIMMs on Controller 1 Channel 3 + $EN_DIS +**/ + UINT8 DisableMc1Ch3; + +/** Offset 0x01E0 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x01E1 - SPD Profile Selected + Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, + 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP + User Profile 5 + 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP + Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x01E2 - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x01E3 - Reserved +**/ + UINT8 Reserved4; + +/** Offset 0x01E4 - Memory Voltage + DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM + chips) in millivolts from 0 - default to 1435mv. +**/ + UINT16 VddVoltage; + +/** Offset 0x01E6 - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 Ratio; + +/** Offset 0x01E7 - tCL + CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCL; + +/** Offset 0x01E8 - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tCWL; + +/** Offset 0x01E9 - Reserved +**/ + UINT8 Reserved5; + +/** Offset 0x01EA - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tFAW; + +/** Offset 0x01EC - tRAS + RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRAS; + +/** Offset 0x01EE - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRCDtRP; + +/** Offset 0x01EF - Reserved +**/ + UINT8 Reserved6; + +/** Offset 0x01F0 - tREFI + Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tREFI; + +/** Offset 0x01F2 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC; + +/** Offset 0x01F4 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRRD; + +/** Offset 0x01F5 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal + values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tRTP; + +/** Offset 0x01F6 - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x01F7 - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT8 tWTR; + +/** Offset 0x01F8 - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x01F9 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x01FA - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x01FB - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x01FC - CPU Trace Hub Memory Region 0 + CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg0Size; + +/** Offset 0x01FD - CPU Trace Hub Memory Region 1 + CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg1Size; + +/** Offset 0x01FE - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 SaGvGear[4]; + +/** Offset 0x0202 - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x020A - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; + +/** Offset 0x020B - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x020C - HECI1 BAR address + BAR address of HECI1 +**/ + UINT32 Heci1BarAddress; + +/** Offset 0x0210 - HECI2 BAR address + BAR address of HECI2 +**/ + UINT32 Heci2BarAddress; + +/** Offset 0x0214 - HECI3 BAR address + BAR address of HECI3 +**/ + UINT32 Heci3BarAddress; + +/** Offset 0x0218 - HG dGPU Power Delay + HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is + 300=300 microseconds +**/ + UINT16 HgDelayAfterPwrEn; + +/** Offset 0x021A - HG dGPU Reset Delay + HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 + microseconds +**/ + UINT16 HgDelayAfterHoldReset; + +/** Offset 0x021C - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x021E - PCIe ASPM programming will happen in relation to the Oprom + Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): + Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after + Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume + 0:Before, 1:After +**/ + UINT8 InitPcieAspmAfterOprom; + +/** Offset 0x021F - Selection of the primary display device + 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0220 - Selection of PSMI Region size + 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 + 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB +**/ + UINT8 PsmiRegionSize; + +/** Offset 0x0221 - Reserved +**/ + UINT8 Reserved7[3]; + +/** Offset 0x0224 - Temporary MMIO address for GMADR + Obsolete field now and it has been extended to 64 bit address, used GmAdr64 +**/ + UINT32 GmAdr; + +/** Offset 0x0228 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x022C - Selection of iGFX GTT Memory size + 1=2MB, 2=4MB, 3=8MB, Default is 3 + 1:2MB, 2:4MB, 3:8MB +**/ + UINT16 GttSize; + +/** Offset 0x022E - Hybrid Graphics GPIO information for PEG 0 + Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + UINT8 CpuPcie0Rtd3Gpio[24]; + +/** Offset 0x0246 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x0247 - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x0248 - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x0249 - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x024A - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x024C - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x024E - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtExtraTurboVoltage; + +/** Offset 0x0250 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x0252 - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x0253 - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x0254 - iTBT PCIe Multiple Segment setting + DEPRECATED + $EN_DIS +**/ + UINT8 PcieMultipleSegmentEnabled; + +/** Offset 0x0255 - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0256 - Lane Used of CSI port + Lane Used of each CSI port + 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 +**/ + UINT8 IpuLaneUsed[8]; + +/** Offset 0x025E - Lane Used of CSI port + Speed of each CSI port + 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps +**/ + UINT8 CsiSpeed[8]; + +/** Offset 0x0266 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[6]; + +/** Offset 0x026C - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0270 - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpLinkDownGpios; + +/** Offset 0x0271 - Enable ClockReq Messaging + ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): + Enable ClockReq Messaging + 0:Disable, 1:Enable +**/ + UINT8 CpuPcieRpClockReqMsgEnable[3]; + +/** Offset 0x0274 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: CPU_PCIE_SPEED). +**/ + UINT8 CpuPcieRpPcieSpeed[4]; + +/** Offset 0x0278 - Selection of PSMI Support On/Off + 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support + $EN_DIS +**/ + UINT8 GtPsmiSupport; + +/** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x027A - Program GPIOs for LFP on DDI port-B device + 0(Default)=Disabled,1=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortBConfig; + +/** Offset 0x027B - Enable or disable HPD of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortAHpd; + +/** Offset 0x027C - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x027D - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x027E - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x027F - Enable or disable HPD of DDI port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0280 - Enable or disable HPD of DDI port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0281 - Enable or disable HPD of DDI port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0282 - Enable or disable DDC of DDI port A + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortADdc; + +/** Offset 0x0283 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0284 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0285 - Enable DDC setting of DDI Port 1 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x0286 - Enable DDC setting of DDI Port 2 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x0287 - Enable DDC setting of DDI Port 3 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x0288 - Enable DDC setting of DDI Port 4 + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x0289 - Reserved +**/ + UINT8 Reserved8[7]; + +/** Offset 0x0290 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress + - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB) +**/ + UINT64 GmAdr64; + +/** Offset 0x0298 - Per-core HT Disable + Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, + 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value + of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have + HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. +**/ + UINT16 PerCoreHtDisable; + +/** Offset 0x029A - SA/Uncore voltage mode + SA/Uncore voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 SaVoltageMode; + +/** Offset 0x029B - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x029C - SA/Uncore Voltage Override + The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override + mode. Valid Range 0 to 2000 +**/ + UINT16 SaVoltageOverride; + +/** Offset 0x029E - SA/Uncore Extra Turbo voltage + Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. + Valid Range 0 to 2000 +**/ + UINT16 SaExtraTurboVoltage; + +/** Offset 0x02A0 - Thermal Velocity Boost Ratio clipping + 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction + caused by high package temperatures for processors that implement the Intel Thermal + Velocity Boost (TVB) feature + 0: Disabled, 1: Enabled +**/ + UINT8 TvbRatioClipping; + +/** Offset 0x02A1 - Thermal Velocity Boost voltage optimization + 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations + for processors that implement the Intel Thermal Velocity Boost (TVB) feature. + 0: Disabled, 1: Enabled +**/ + UINT8 TvbVoltageOptimization; + +/** Offset 0x02A2 - Reserved +**/ + UINT8 Reserved10[111]; + +/** Offset 0x0311 - Enable Gt CLOS + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 GtClosEnable; + +/** Offset 0x0312 - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0313 - DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 DmiGen3EqPh2Enable; + +/** Offset 0x0314 - DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 DmiGen3EqPh3Method; + +/** Offset 0x0315 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x0316 - DeEmphasis control for DMI + DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB + 0: -6dB, 1: -3.5dB +**/ + UINT8 DmiDeEmphasis; + +/** Offset 0x0317 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x031F - DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 DmiGen3EndPointPreset[8]; + +/** Offset 0x0327 - DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 DmiGen3EndPointHint[8]; + +/** Offset 0x032F - DMI Gen3 RxCTLEp per-Bundle control + Range: 0-15, 0 is default for each bundle, must be specified based upon platform design +**/ + UINT8 DmiGen3RxCtlePeaking[4]; + +/** Offset 0x0333 - DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x0334 - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq, + Enabled(0x1): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass + CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase23Bypass; + +/** Offset 0x0336 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass + CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase3Bypass; + +/** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen3LtcoEnable; + +/** Offset 0x0338 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x0339 - DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 DmiGen3Ltcpre[8]; + +/** Offset 0x0341 - DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 DmiGen3Ltcpo[8]; + +/** Offset 0x0349 - PCIE Hw Eq Gen3 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x0351 - PCIE Hw Eq Gen3 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0359 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable + Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, + Manual(0x1): Enable DmiGen3DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3DsPresetEnable; + +/** Offset 0x035A - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3DsPortRxPreset[8]; + +/** Offset 0x0362 - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3DsPortTxPreset[8]; + +/** Offset 0x036A - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable + Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, + Manual(0x1): Enable DmiGen3UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3UsPresetEnable; + +/** Offset 0x036B - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortRxPreset[8]; + +/** Offset 0x0373 - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortTxPreset[8]; + +/** Offset 0x037B - Reserved +**/ + UINT8 Reserved11[54]; + +/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo + Set ASPM Control configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspmCtrl; + +/** Offset 0x03B2 - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x03B3 - BIST on Reset + Enable or Disable BIST on Reset; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x03B4 - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x03B5 - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x03B6 - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x03B7 - Over clocking Lock + Over clocking Lock Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x03B8 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x03B9 - Core voltage mode + Core voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x03BA - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x03BB - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x03BC - Enable or Disable CPU Ratio Override + Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuRatioOverride; + +/** Offset 0x03BD - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x03BE - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. + 1: Maximum non-turbo performance. 2: Turbo performance + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x03BF - Number of active big cores + Number of active big cores(Depends on Number of big cores). Default 0xFF means to + active all system supported big cores. 0xFF: Active all big cores; 0: Disable + all big cores; 1: 1; 2: 2; 3: 3; + 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x03C0 - Processor Early Power On Configuration FCLK setting + 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x03C1 - Set JTAG power in C10 and deeper power states + False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 + and deeper power states for debug purpose. 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 JtagC10PowerGateDisable; + +/** Offset 0x03C2 - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x03C3 - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x03C4 - AVX3 Ratio Offset + DEPRECATED +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x03C5 - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x03C6 - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x03C8 - Core Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageAdaptive; + +/** Offset 0x03CA - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x03CC - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x03CD - Reserved +**/ + UINT8 Reserved12; + +/** Offset 0x03CE - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x03CF - Ring voltage mode + Ring voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x03D0 - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x03D1 - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x03D2 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x03D4 - Ring Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageAdaptive; + +/** Offset 0x03D6 - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x03D8 - Enable or Disable TME + Enable or Disable TME; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x03D9 - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x03DA - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x03DB - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x03DC - Reserved +**/ + UINT8 Reserved14[24]; + +/** Offset 0x03F4 - Core VF Point Offset Mode + Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 CoreVfPointOffsetMode; + +/** Offset 0x03F5 - Reserved +**/ + UINT8 Reserved15; + +/** Offset 0x03F6 - Core VF Point Offset + Array used to specifies the Core Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x0414 - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x0423 - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x0432 - Core VF Point Count + Number of supported Core Voltage & Frequency Point Offset +**/ + UINT8 CoreVfPointCount; + +/** Offset 0x0433 - Reserved +**/ + UINT8 Reserved16[25]; + +/** Offset 0x044C - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x044D - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[8]; + +/** Offset 0x0455 - Reserved +**/ + UINT8 Reserved17[5]; + +/** Offset 0x045A - Pvd Ratio Threshold + Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. +**/ + UINT8 PvdRatioThreshold; + +/** Offset 0x045B - Support Unlimited ICCMAX + DEPRECATED + $EN_DIS +**/ + UINT8 UnlimitedIccMax; + +/** Offset 0x045C - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x045D - Reserved +**/ + UINT8 Reserved18[62]; + +/** Offset 0x049B - BCLK Frequency Source + Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK + 1:CPU BCLK, 2:PCH BCLK, 3:External CLK +**/ + UINT8 BclkSource; + +/** Offset 0x049C - GPIO Override + Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings + before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO + configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use +**/ + UINT8 GpioOverride; + +/** Offset 0x049D - Reserved +**/ + UINT8 Reserved19[3]; + +/** Offset 0x04A0 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 + - Auto. Range is 8000-50000 (10KHz). +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x04A4 - Reserved +**/ + UINT8 Reserved20[40]; + +/** Offset 0x04CC - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x04CD +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x04CE - Txt + Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x04CF - Reserved +**/ + UINT8 Reserved21; + +/** Offset 0x04D0 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x04D4 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x04D8 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x04E0 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x04E4 - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x04E8 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x04EC - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x04F0 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x04F4 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x04F8 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0500 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0508 - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x0509 - Reserved +**/ + UINT8 Reserved22[32]; + +/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[28]; + +/** Offset 0x0545 - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[28]; + +/** Offset 0x0561 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; + +/** Offset 0x057D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; + +/** Offset 0x0599 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; + +/** Offset 0x05B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; + +/** Offset 0x05D1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; + +/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; + +/** Offset 0x0609 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; + +/** Offset 0x0625 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[28]; + +/** Offset 0x0641 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; + +/** Offset 0x065D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; + +/** Offset 0x0679 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; + +/** Offset 0x0695 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; + +/** Offset 0x06B1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x06B9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x06C1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x06C9 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x06D1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x06D9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x06E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x06E9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x06F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x06F9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x0701 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x0709 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x0711 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x0719 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x0721 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x0729 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x0731 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x0739 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x0741 - PCH LPC Enhanced Port 80 Decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x0742 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + 0:LPC, 1:PCI +**/ + UINT8 PchPort80Route; + +/** Offset 0x0743 - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x0744 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0745 - Reserved +**/ + UINT8 Reserved23; + +/** Offset 0x0746 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0748 - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0749 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[18]; + +/** Offset 0x075B - Reserved +**/ + UINT8 Reserved24[14]; + +/** Offset 0x0769 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[18]; + +/** Offset 0x077B - Reserved +**/ + UINT8 Reserved25[93]; + +/** Offset 0x07D8 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x07DC - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x07DD - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x07DE - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x07DF - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. +**/ + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x07E1 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; + +/** Offset 0x07E2 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x07E4 - DMIC ClkA Pin Muxing (N - DMIC number) + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* +**/ + UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; + +/** Offset 0x07EC - DMIC ClkB Pin Muxing + Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* +**/ + UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; + +/** Offset 0x07F4 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x07F5 - Reserved +**/ + UINT8 Reserved26[3]; + +/** Offset 0x07F8 - DMIC Data Pin Muxing + Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* +**/ + UINT32 PchHdaAudioLinkDmicDataPinMux[2]; + +/** Offset 0x0800 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0806 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x080A - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x080B - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x080C - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x080D - CNVi DDR RFI Mitigation + Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviDdrRfim; + +/** Offset 0x080E - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x080F - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x0810 - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0811 - Reserved +**/ + UINT8 Reserved27[3]; + +/** Offset 0x0814 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0818 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0819 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x081A - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x081B - Reserved +**/ + UINT8 Reserved28; + +/** Offset 0x081C - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; + +/** Offset 0x0820 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0821 - GT PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 GtPllVoltageOffset; + +/** Offset 0x0822 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0823 - System Agent PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0824 - Memory Controller PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-15 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0825 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x082A - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x082B - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x082C - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x082D - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x082E - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x082F - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x0830 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x0831 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x0832 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x0833 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x0834 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x0835 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x0836 - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x0837 - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x0838 - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x0839 - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x083A - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x083B - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x083C - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x083D - Write Drive Strength/Equalization 2D + Enables/Disable Write Drive Strength/Equalization 2D + $EN_DIS +**/ + UINT8 WRDSEQT; + +/** Offset 0x083E - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x083F - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x0840 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x0841 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x0842 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x0843 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x0844 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x0845 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x0846 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x0847 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x0848 - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x0849 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x084A - Memory Test + Enables/Disable Memory Test + $EN_DIS +**/ + UINT8 MEMTST; + +/** Offset 0x084B - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x084C - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x084D - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x084E - Write Drive Strength Up/Dn independently + Enables/Disable Write Drive Strength Up/Dn independently + $EN_DIS +**/ + UINT8 WRDSUDT; + +/** Offset 0x084F - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0850 - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0851 - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x0852 - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x0853 - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x0854 - Reserved +**/ + UINT8 Reserved29; + +/** Offset 0x0855 - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x0856 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x0857 - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0858 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0859 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x085A - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x085B - Reserved +**/ + UINT8 Reserved30; + +/** Offset 0x085C - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x085D - New Features 1 - MRC + New Feature Enabling 1, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 NewFeatureEnable1; + +/** Offset 0x085E - New Features 2 - MRC + New Feature Enabling 2, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 NewFeatureEnable2; + +/** Offset 0x085F - Duty Cycle Correction Training + Enable/Disable Duty Cycle Correction Training + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0860 - Read Voltage Centering 1D + Enable/Disable Read Voltage Centering 1D + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x0861 - TxDqTCO Comp Training + Enable/Disable TxDqTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x0862 - ClkTCO Comp Training + Enable/Disable ClkTCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x0863 - CMD Slew Rate Training + Enable/Disable CMD Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x0864 - CMD Drive Strength and Tx Equalization + Enable/Disable CMD Drive Strength and Tx Equalization + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x0865 - DIMM CA ODT Training + Enable/Disable DIMM CA ODT Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x0866 - TxDqsTCO Comp Training + Enable/Disable TxDqsTCO Comp Training + $EN_DIS +**/ + UINT8 TXTCODQS; + +/** Offset 0x0867 - CMD/CTL Drive Strength Up/Dn 2D + Enable/Disable CMD/CTL Drive Strength Up/Dn 2D + $EN_DIS +**/ + UINT8 CMDDRUD; + +/** Offset 0x0868 - VccDLL Bypass Training + Enable/Disable VccDLL Bypass Training + $EN_DIS +**/ + UINT8 VCCDLLBP; + +/** Offset 0x0869 - PanicVttDnLp Training + Enable/Disable PanicVttDnLp Training + $EN_DIS +**/ + UINT8 PVTTDNLP; + +/** Offset 0x086A - Read Vref Decap Training* + Enable/Disable Read Vref Decap Training* + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x086B - Vddq Training + Enable/Disable Vddq Training + $EN_DIS +**/ + UINT8 VDDQT; + +/** Offset 0x086C - Rank Margin Tool Per Bit + Enable/Disable Rank Margin Tool Per Bit + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x086D - Reserved +**/ + UINT8 Reserved31[2]; + +/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedClock; + +/** Offset 0x0870 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x0871 - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0872 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0874 - Base reference clock value + Base reference clock value, in Hertz(Default is 100Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0878 - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x087A - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x087C - CMD Normalization + Enable/Disable CMD Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x087D - Early DQ Write Drive Strength and Equalization Training + Enable/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x087E - Reserved +**/ + UINT8 Reserved32; + +/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm0; + +/** Offset 0x0880 - Idle Energy Mc0Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm1; + +/** Offset 0x0881 - Idle Energy Mc0Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm0; + +/** Offset 0x0882 - Idle Energy Mc0Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm1; + +/** Offset 0x0883 - Idle Energy Mc1Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm0; + +/** Offset 0x0884 - Idle Energy Mc1Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm1; + +/** Offset 0x0885 - Idle Energy Mc1Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm0; + +/** Offset 0x0886 - Idle Energy Mc1Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm1; + +/** Offset 0x0887 - PowerDown Energy Mc0Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm0; + +/** Offset 0x0888 - PowerDown Energy Mc0Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm1; + +/** Offset 0x0889 - PowerDown Energy Mc0Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm0; + +/** Offset 0x088A - PowerDown Energy Mc0Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm1; + +/** Offset 0x088B - PowerDown Energy Mc1Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm0; + +/** Offset 0x088C - PowerDown Energy Mc1Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm1; + +/** Offset 0x088D - PowerDown Energy Mc1Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm0; + +/** Offset 0x088E - PowerDown Energy Mc1Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm1; + +/** Offset 0x088F - Activate Energy Mc0Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm0; + +/** Offset 0x0890 - Activate Energy Mc0Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm1; + +/** Offset 0x0891 - Activate Energy Mc0Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm0; + +/** Offset 0x0892 - Activate Energy Mc0Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm1; + +/** Offset 0x0893 - Activate Energy Mc1Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm0; + +/** Offset 0x0894 - Activate Energy Mc1Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm1; + +/** Offset 0x0895 - Activate Energy Mc1Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm0; + +/** Offset 0x0896 - Activate Energy Mc1Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm1; + +/** Offset 0x0897 - Read Energy Mc0Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm0; + +/** Offset 0x0898 - Read Energy Mc0Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm1; + +/** Offset 0x0899 - Read Energy Mc0Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm0; + +/** Offset 0x089A - Read Energy Mc0Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm1; + +/** Offset 0x089B - Read Energy Mc1Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm0; + +/** Offset 0x089C - Read Energy Mc1Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm1; + +/** Offset 0x089D - Read Energy Mc1Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm0; + +/** Offset 0x089E - Read Energy Mc1Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm1; + +/** Offset 0x089F - Write Energy Mc0Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm0; + +/** Offset 0x08A0 - Write Energy Mc0Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm1; + +/** Offset 0x08A1 - Write Energy Mc0Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm0; + +/** Offset 0x08A2 - Write Energy Mc0Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm1; + +/** Offset 0x08A3 - Write Energy Mc1Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm0; + +/** Offset 0x08A4 - Write Energy Mc1Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm1; + +/** Offset 0x08A5 - Write Energy Mc1Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm0; + +/** Offset 0x08A6 - Write Energy Mc1Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm1; + +/** Offset 0x08A7 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x08A8 - Reserved +**/ + UINT8 Reserved33[2]; + +/** Offset 0x08AA - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x08AB - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x08AC - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x08AD - REFRESH_2X_MODE + 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot + 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only +**/ + UINT8 Refresh2X; + +/** Offset 0x08AE - Energy Performance Gain + Enable/disable(default) Energy Performance Gain. + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x08AF - Reserved +**/ + UINT8 Reserved34; + +/** Offset 0x08B0 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x08B1 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x08B2 - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto +**/ + UINT8 PowerDownMode; + +/** Offset 0x08B3 - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x08B4 - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled +**/ + UINT8 DisPgCloseIdleTimeout; + +/** Offset 0x08B5 - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, + Rank0 is terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x08B6 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x08B7 - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x08B8 - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x08B9 - LpDdrDqDqsReTraining + Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5 + $EN_DIS +**/ + UINT8 LpDdrDqDqsReTraining; + +/** Offset 0x08BA - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x08BB - Reserved +**/ + UINT8 Reserved35; + +/** Offset 0x08BC - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x08BE - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x08BF - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x08C0 - WRC Feature + Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports + IO devices allocating onto the ring and into LLC. WRC is fused on by default. + $EN_DIS +**/ + UINT8 WrcFeatureEnable; + +/** Offset 0x08C1 - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x08C4 - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No + RFI Tuning. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; + +/** Offset 0x08D4 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x08D6 - Enable PCIe IMR + 0: Disable(AUTO), 1: Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x08D7 - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS +**/ + UINT8 PcieImrRpLocation; + +/** Offset 0x08D8 - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; + +/** Offset 0x08D9 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x08DA - Ddr4OneDpc + DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 Ddr4OneDpc; + +/** Offset 0x08DB - Reserved +**/ + UINT8 Reserved37[3]; + +/** Offset 0x08DE - REFRESH_PANIC_WM + DEPRECATED +**/ + UINT8 RefreshPanicWm; + +/** Offset 0x08DF - REFRESH_HP_WM + DEPRECATED +**/ + UINT8 RefreshHpWm; + +/** Offset 0x08E0 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x08E1 - Command Pins Mirrored + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. +**/ + UINT8 CmdMirror; + +/** Offset 0x08E2 - Reserved +**/ + UINT8 Reserved38[9]; + +/** Offset 0x08EB - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x08EC - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x08ED - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x08EE - Reserved +**/ + UINT8 Reserved39; + +/** Offset 0x08EF - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x08F0 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x08F1 - Reserved +**/ + UINT8 Reserved40[3]; + +/** Offset 0x08F4 - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot +**/ + UINT32 DmaBufferSize; + +/** Offset 0x08F8 - VT-d/IOMMU Boot Policy + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x08F9 - Reserved +**/ + UINT8 Reserved41[95]; + +/** Offset 0x0958 - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + UINT16 TotalFlashSize; + +/** Offset 0x095A - BiosSize + The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != + 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected + Range) so that a BIOS Update Script can be stored in the DPR. +**/ + UINT16 BiosSize; + +/** Offset 0x095C - Reserved +**/ + UINT8 Reserved42[12]; + +/** Offset 0x0968 - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x0969 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x096A - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x096B - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x096C - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x096D - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x096E - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x096F - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x0970 - Enable KT device + Test, 0: disable, 1: enable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x0971 - Skip CPU replacement check + Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check + $EN_DIS +**/ + UINT8 SkipCpuReplacementCheck; + +/** Offset 0x0972 - Reserved +**/ + UINT8 Reserved43[2]; + +/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 + Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie1Rtd3Gpio[24]; + +/** Offset 0x09D4 - Hybrid Graphics GPIO information for PEG 2 + Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie2Rtd3Gpio[24]; + +/** Offset 0x0A34 - Hybrid Graphics GPIO information for PEG 3 + Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie3Rtd3Gpio[24]; + +/** Offset 0x0A94 - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor + DEPRECATED +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x0A96 - Serial Io Uart Debug Mode + Select SerialIo Uart Controller mode + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartDebugMode; + +/** Offset 0x0A97 - Reserved +**/ + UINT8 Reserved44; + +/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x0A9C - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x0AA0 - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x0AA4 - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x0AA8 - Reserved +**/ + UINT8 Reserved45[144]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0B38 +**/ + UINT8 UnusedUpdSpace34[6]; + +/** Offset 0x0B3E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h similarity index 51% rename from src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h rename to src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h index a4bd70a5d3..b7cb818e4d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -85,624 +85,289 @@ typedef struct { **/ typedef struct { -/** Offset 0x0020 - Logo Pointer +/** Offset 0x0040 - Logo Pointer Points to PEI Display Logo Image **/ UINT32 LogoPtr; -/** Offset 0x0024 - Logo Size +/** Offset 0x0044 - Logo Size Size of PEI Display Logo Image **/ UINT32 LogoSize; -/** Offset 0x0028 - Blt Buffer Address +/** Offset 0x0048 - Blt Buffer Address Address of Blt buffer **/ UINT32 BltBufferAddress; -/** Offset 0x002C - Blt Buffer Size +/** Offset 0x004C - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) **/ UINT32 BltBufferSize; -/** Offset 0x0030 - Graphics Configuration Ptr +/** Offset 0x0050 - Graphics Configuration Ptr Points to VBT **/ UINT32 GraphicsConfigPtr; -/** Offset 0x0034 - Enable Device 4 +/** Offset 0x0054 - Enable Device 4 Enable/disable Device 4 $EN_DIS **/ UINT8 Device4Enable; -/** Offset 0x0035 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0036 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0037 - Enable eMMC DDR50 Mode - Enable eMMC DDR50 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcDdr50Enabled; - -/** Offset 0x0038 - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0039 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x003C - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0040 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x0044 - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x004C - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x0050 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x0054 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0055 - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x0056 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x0057 -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x0058 - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x005C - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0060 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0064 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x0068 - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x006C - SdCard Power Enable Pin Mux - Select Power Enable pin muxing. Refer to GPIO_*_MUXING_SDCARD_PWR_EN* for possible values. -**/ - UINT32 SdCardGpioPrwEnBPinMux; - -/** Offset 0x0070 - SdCard Power Enable Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioPrwEnBPadTermination; - -/** Offset 0x0071 -**/ - UINT8 UnusedUpdSpace2[3]; - -/** Offset 0x0074 - SdCard Command Pin Mux - Select Command pin muxing. Refer to GPIO_*_MUXING_SDCARD_CMD* for possible values. -**/ - UINT32 SdCardGpioCmdPinMux; - -/** Offset 0x0078 - SdCard Command Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioCmdPadTermination; - -/** Offset 0x0079 -**/ - UINT8 UnusedUpdSpace3[3]; - -/** Offset 0x007C - SdCard Data Pin Mux - Select Data pin muxing. Refer to GPIO_*_MUXING_SDCARD_DATAx_* for possible values. - One UINT32 for each data pin [0-4] -**/ - UINT32 SdCardGpioDataPinMux[4]; - -/** Offset 0x008C - SdCard Data Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up. One byte for each data pin [0-4] -**/ - UINT8 SdCardGpioDataPadTermination[4]; - -/** Offset 0x0090 - SdCard Cdb Pin Mux - Select Cdb pin muxing. Refer to GPIO_*_MUXING_SDCARD_CDB* for possible values. -**/ - UINT32 SdCardGpioCdbPinMux; - -/** Offset 0x0094 - SdCard Cdb Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioCdbPadTermination; - -/** Offset 0x0095 -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0098 - SdCard Clock Pin Mux - Select Clock pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK* for possible values. -**/ - UINT32 SdCardGpioClkPinMux; - -/** Offset 0x009C - SdCard Clock Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioClkPadTermination; - -/** Offset 0x009D -**/ - UINT8 UnusedUpdSpace5[3]; - -/** Offset 0x00A0 - SdCard Wp PinMux - Select Wp pin muxing. Refer to GPIO_*_MUXING_SDCARD_WP* for possible values. -**/ - UINT32 SdCardGpioWpPinMux; - -/** Offset 0x00A4 - SdCard Wp Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioWpPadTermination; - -/** Offset 0x00A5 -**/ - UINT8 UnusedUpdSpace6[3]; - -/** Offset 0x00A8 - SdCard Clock Feedback Pin Mux - Select pin muxing. Refer to GPIO_*_MUXING_SDCARD_CLK_FB* for possible values. -**/ - UINT32 SdCardGpioClkFbPinMux; - -/** Offset 0x00AC - SdCard Clock Feedback Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 SdCardGpioClkFbPadTermination; - -/** Offset 0x00AD -**/ - UINT8 UnusedUpdSpace7[3]; - -/** Offset 0x00B0 - Emmc Command Pin Mux - Select pin muxing. Refer to GPIO_*_MUXING_EMMC_CMD* for possible values. -**/ - UINT32 EmmcGpioCmdPinMux; - -/** Offset 0x00B4 - Emmc Command Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 EmmcGpioCmdPadTermination; - -/** Offset 0x00B5 - Emmc Data Pin Mux - Select pin muxing. Refer to GPIO_*_MUXING_EMMC_DATA_x* for possible values. One - UINT32 for each data pin [0-8] -**/ - UINT8 EmmcGpioDataPinMux[32]; - -/** Offset 0x00D5 - Emmc Data Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up. One byte for each data pin [0-8] -**/ - UINT8 EmmcGpioDataPadTermination[8]; - -/** Offset 0x00DD -**/ - UINT8 UnusedUpdSpace8[3]; - -/** Offset 0x00E0 - Emmc Rclk PinMux - Select Rclk pin muxing. Refer to GPIO_*_MUXING_EMMC_RCLK* for possible values. -**/ - UINT32 EmmcGpioRclkPinMux; - -/** Offset 0x00E4 - Emmc Rclk Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 EmmcGpioRclkPadTermination; - -/** Offset 0x00E5 -**/ - UINT8 UnusedUpdSpace9[3]; - -/** Offset 0x00E8 - Emmc Clock Pin Mux - Select Clock pin muxing. Refer to GPIO_*_MUXING_EMMC_CLK* for possible values. -**/ - UINT32 EmmcGpioClkPinMux; - -/** Offset 0x00EC - Emmc Clock Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 EmmcGpioClkPadTermination; - -/** Offset 0x00ED -**/ - UINT8 UnusedUpdSpace10[3]; - -/** Offset 0x00F0 - Emmc Resetb PinMux - Select Resetb pin muxing. Refer to GPIO_*_MUXING_EMMC_RESETB* for possible values. -**/ - UINT32 EmmcGpioResetbPinMux; - -/** Offset 0x00F4 - Emmc Resetb Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 EmmcGpioResetbPadTermination; - -/** Offset 0x00F5 -**/ - UINT8 UnusedUpdSpace11[3]; - -/** Offset 0x00F8 - Emmc HipMon PinMux - Select HipMon pin muxing. Refer to GPIO_MUXING_EMMC_HIP_MON for possible values. -**/ - UINT32 EmmcGpioHipMonPinMux; - -/** Offset 0x00FC - Emmc HipMon Pad Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up -**/ - UINT8 EmmcGpioHipMonPadTermination; - -/** Offset 0x00FD - Show SPI controller +/** Offset 0x0055 - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x00FE +/** Offset 0x0056 - Reserved **/ - UINT8 UnusedUpdSpace12[2]; + UINT8 Reserved0[2]; -/** Offset 0x0100 - MicrocodeRegionBase +/** Offset 0x0058 - MicrocodeRegionBase Memory Base of Microcode Updates **/ UINT32 MicrocodeRegionBase; -/** Offset 0x0104 - MicrocodeRegionSize +/** Offset 0x005C - MicrocodeRegionSize Size of Microcode Updates **/ UINT32 MicrocodeRegionSize; -/** Offset 0x0108 - Turbo Mode +/** Offset 0x0060 - Turbo Mode Enable/Disable Turbo mode. 0: disable, 1: enable $EN_DIS **/ UINT8 TurboMode; -/** Offset 0x0109 -**/ - UINT8 UnusedUpdSpace13[3]; - -/** Offset 0x010C - SiipRegionBase - Memory Base of Siip Firmware -**/ - UINT32 SiipRegionBase; - -/** Offset 0x0110 - SiipRegionSize - Size of Siip Firmware -**/ - UINT32 SiipRegionSize; - -/** Offset 0x0114 - IsiRegionBase - Memory Base of Isi Config -**/ - UINT32 IsiRegionBase; - -/** Offset 0x0118 - IsiRegionSize - Size of Isi Config -**/ - UINT32 IsiRegionSize; - -/** Offset 0x011C - Enable SATA SALP Support +/** Offset 0x0061 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x011D - PCH Sata Port Multiplier - Enable / Disable SATA Port Multiplier - $EN_DIS -**/ - UINT8 SataPortMultiplier; - -/** Offset 0x011E - Enable SATA ports +/** Offset 0x0062 - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x0126 - Enable SATA DEVSLP Feature +/** Offset 0x006A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x012E - Enable USB2 ports +/** Offset 0x0072 - Reserved +**/ + UINT8 Reserved1[34]; + +/** Offset 0x0094 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x013E - Select USB2 ports Operation Mode - Selectively Enable USB2 Host/Device Mode. 1 is Device Mode, 2 is Host Mode. One - byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 USB20Otg[16]; - -/** Offset 0x014E - Select USB3 ports Operation Mode - Selectively Enable USB3 Host/Device Mode. 1 is Device Mode, 2 is Host Mode. One - byte for each port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 USB30Otg[10]; - -/** Offset 0x0158 - Enable USB3 ports +/** Offset 0x00A4 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x0162 - Enable xDCI controller +/** Offset 0x00AE - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x0163 +/** Offset 0x00AF - Reserved **/ - UINT8 UnusedUpdSpace14; + UINT8 Reserved2; -/** Offset 0x0164 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x0168 - Number of DevIntConfig Entry +/** Offset 0x00B4 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0169 - PIRQx to IRQx Map Config +/** Offset 0x00B5 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x0171 - Select GPIO IRQ Route +/** Offset 0x00BD - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x0172 - Select SciIrqSelect +/** Offset 0x00BE - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x0173 - Select TcoIrqSelect +/** Offset 0x00BF - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x0174 - Enable/Disable Tco IRQ +/** Offset 0x00C0 - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x0175 - PCH HDA Verb Table Entry Number +/** Offset 0x00C1 - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x0176 +/** Offset 0x00C2 - Reserved **/ - UINT8 UnusedUpdSpace15[2]; + UINT8 Reserved3[2]; -/** Offset 0x0178 - PCH HDA Verb Table Pointer +/** Offset 0x00C4 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x017C - PCH HDA Codec Sx Wake Capability +/** Offset 0x00C8 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x017D - Enable SATA +/** Offset 0x00C9 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x017E - SATA Mode +/** Offset 0x00CA - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x017F - SPIn Device Mode +/** Offset 0x00CB - SPIn Device Mode Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden **/ UINT8 SerialIoSpiMode[7]; -/** Offset 0x0186 - SPI Chip Select Polarity +/** Offset 0x00D2 - SPI Chip Select Polarity Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh **/ UINT8 SerialIoSpiCsPolarity[14]; -/** Offset 0x0194 - SPI Chip Select Enable +/** Offset 0x00E0 - SPI Chip Select Enable 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ UINT8 SerialIoSpiCsEnable[14]; -/** Offset 0x01A2 - SPIn Default Chip Select Output +/** Offset 0x00EE - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available options: 0:CS0, 1:CS1 **/ UINT8 SerialIoSpiDefaultCsOutput[7]; -/** Offset 0x01A9 - SPIn Default Chip Select Mode HW/SW +/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, SPI1, ... Available options: 0:HW, 1:SW **/ UINT8 SerialIoSpiCsMode[7]; -/** Offset 0x01B0 - SPIn Default Chip Select State Low/High +/** Offset 0x00FC - SPIn Default Chip Select State Low/High Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High **/ UINT8 SerialIoSpiCsState[7]; -/** Offset 0x01B7 - SPIn Master Input Slave Output Enable/Disable - 0:Disabled, 1:Enabled. Sets Native Mode for SPIx MISO GPIO if it is Enabled -**/ - UINT8 SerialIoSpiMisoEnable[3]; - -/** Offset 0x01BA - SPIn Delayed Rx Clock setting - 00:default, 01:Internal, 10:NegEdge Tx Clock, 11:NegEdge Delayed Rx Clk. Configure - Delayed Rx Clock -**/ - UINT8 SerialIoSpiDelayRxClk[3]; - -/** Offset 0x01BD - UARTn Device Mode +/** Offset 0x0103 - UARTn Device Mode Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x01C4 - Default BaudRate for each Serial IO UART +/** Offset 0x010A - Reserved +**/ + UINT8 Reserved4[2]; + +/** Offset 0x010C - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 **/ UINT32 SerialIoUartBaudRate[7]; -/** Offset 0x01E0 - Default ParityType for each Serial IO UART +/** Offset 0x0128 - Default ParityType for each Serial IO UART Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartParity[7]; -/** Offset 0x01E7 - Default DataBits for each Serial IO UART +/** Offset 0x012F - Default DataBits for each Serial IO UART Set default word length. 0: Default, 5,6,7,8 **/ UINT8 SerialIoUartDataBits[7]; -/** Offset 0x01EE - Default StopBits for each Serial IO UART +/** Offset 0x0136 - Default StopBits for each Serial IO UART Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartStopBits[7]; -/** Offset 0x01F5 - Power Gating mode for each Serial IO UART that works in COM mode +/** Offset 0x013D - Power Gating mode for each Serial IO UART that works in COM mode Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto **/ UINT8 SerialIoUartPowerGating[7]; -/** Offset 0x01FC - Enable Dma for each Serial IO UART that supports it +/** Offset 0x0144 - Enable Dma for each Serial IO UART that supports it Set DMA/PIO mode. 0: Disabled, 1: Enabled **/ UINT8 SerialIoUartDmaEnable[7]; -/** Offset 0x0203 - Enables UART hardware flow control, CTS and RTS lines +/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS lines. **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x020A +/** Offset 0x0152 - Reserved **/ - UINT8 UnusedUpdSpace16[2]; + UINT8 Reserved5[2]; -/** Offset 0x020C - SerialIoUartRtsPinMuxPolicy +/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartRtsPinMuxPolicy[7]; -/** Offset 0x0228 - SerialIoUartCtsPinMuxPolicy +/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values. **/ UINT32 SerialIoUartCtsPinMuxPolicy[7]; -/** Offset 0x0244 - SerialIoUartRxPinMuxPolicy +/** Offset 0x018C - SerialIoUartRxPinMuxPolicy Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for possible values. **/ UINT32 SerialIoUartRxPinMuxPolicy[7]; -/** Offset 0x0260 - SerialIoUartTxPinMuxPolicy +/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for possible values. **/ UINT32 SerialIoUartTxPinMuxPolicy[7]; -/** Offset 0x027C - UART Number For Debug Purpose +/** Offset 0x01C4 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. @@ -710,37 +375,187 @@ typedef struct { **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x027D - Serial IO UART DBG2 table +/** Offset 0x01C5 - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[7]; -/** Offset 0x0284 - I2Cn Device Mode +/** Offset 0x01CC - I2Cn Device Mode Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden **/ UINT8 SerialIoI2cMode[8]; -/** Offset 0x028C - Serial IO I2C SDA Pin Muxing +/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for possible values. **/ UINT32 PchSerialIoI2cSdaPinMux[8]; -/** Offset 0x02AC - Serial IO I2C SCL Pin Muxing +/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for possible values. **/ UINT32 PchSerialIoI2cSclPinMux[8]; -/** Offset 0x02CC - PCH SerialIo I2C Pads Termination +/** Offset 0x0214 - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. **/ UINT8 PchSerialIoI2cPadsTermination[8]; +/** Offset 0x021C - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER +**/ + UINT32 IshGpGpioPinMuxing[8]; + +/** Offset 0x023C - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x0248 - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0254 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0260 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x026C - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x0278 - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0284 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x028C - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0294 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x029C - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x02AC - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[8]; + +/** Offset 0x02B4 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x02B7 - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x02BA - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x02BD - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x02C0 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x02C3 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x02C6 - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x02C8 - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x02CA - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x02CC - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x02D0 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; + /** Offset 0x02D4 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. @@ -833,2458 +648,1801 @@ typedef struct { **/ UINT8 PchTsnEnable; -/** Offset 0x038E - PCH TSN Multi VC Enable - Enable/Disable PCH TSN GBE Multiple Virtual Channel - $EN_DIS -**/ - UINT8 PchTsnGbeMultiVcEnable; - -/** Offset 0x038F - PCH TSN Link Speed - Set PCH TSN Link Speed. - 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps -**/ - UINT8 PchTsnGbeLinkSpeed; - -/** Offset 0x0390 - PCH TSN SGMII Support - Enable/disable SGMII support - $EN_DIS -**/ - UINT8 PchTsnGbeSgmiiEnable; - -/** Offset 0x0391 - PSE TSN Multi VC Enable - Enable/Disable PSE TSN GBE Multiple Virtual Channel - $EN_DIS -**/ - UINT8 PseTsnGbeMultiVcEnable[2]; - -/** Offset 0x0393 - PSE TSN Link Speed +/** Offset 0x038E - TSN Link Speed Set TSN Link Speed. 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps **/ - UINT8 PseTsnGbeLinkSpeed[2]; + UINT8 PchTsnLinkSpeed; -/** Offset 0x0395 - PSE TSN SGMII Support - Enable/disable SGMII support - $EN_DIS +/** Offset 0x038F - Reserved **/ - UINT8 PseTsnGbeSgmiiEnable[2]; + UINT8 Reserved6[9]; -/** Offset 0x0397 - PSE TSN Phy Interface Type - Set PSE TSN Phy Interface Type - 0: Not Connected, 1: RGMII, 2: SGMII, 3:SGMII+ -**/ - UINT8 PseTsnGbePhyInterfaceType[2]; - -/** Offset 0x0399 -**/ - UINT8 UnusedUpdSpace17[3]; - -/** Offset 0x039C - Tsn Mac Address Sub Region Base - Base address of TSN MAC Address Sub Region -**/ - UINT32 TsnMacAddrBase; - -/** Offset 0x03A0 - Tsn Mac Address Sub Region Size - Size of TSN MAC Address Sub Region -**/ - UINT32 TsnMacAddrSize; - -/** Offset 0x03A4 - PSE Tsn Ip Config Sub Region Base - Base address of PSE TSN IP Config Sub Region -**/ - UINT32 PseTsnIpConfigBase; - -/** Offset 0x03A8 - PSE Tsn Ip Config Sub Region Size - Size of PSE TSN IP Config Sub Region -**/ - UINT32 PseTsnIpConfigSize; - -/** Offset 0x03AC - Tsn Config Sub Region Base - Base address of TSN Config Sub Region -**/ - UINT32 TsnConfigBase; - -/** Offset 0x03B0 - Tsn Config Sub Region Size - Size of TSN Config Sub Region -**/ - UINT32 TsnConfigSize; - -/** Offset 0x03B4 - PSE GBE0 DLL OVERRIDE - Enable/Disable PSE GBE DLL OVERRIDE - $EN_DIS -**/ - UINT8 PseGbeDllOverride[2]; - -/** Offset 0x03B6 - PSE GBE TX_Delay - PSE GBE TX_Delay configuration. -**/ - UINT8 PseGbeTxDelay[2]; - -/** Offset 0x03B8 - PCIe PTM enable/disable +/** Offset 0x0398 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. **/ - UINT8 PciePtm[24]; + UINT8 PciePtm[28]; -/** Offset 0x03D0 - PCIe DPC enable/disable +/** Offset 0x03B4 - PCIe DPC enable/disable Enable/disable Downstream Port Containment for PCIE Root Ports. **/ - UINT8 PcieDpc[24]; + UINT8 PcieDpc[28]; -/** Offset 0x03E8 - PCIe DPC extensions enable/disable +/** Offset 0x03D0 - PCIe DPC extensions enable/disable Enable/disable Downstream Port Containment Extensions for PCIE Root Ports. **/ - UINT8 PcieEdpc[24]; + UINT8 PcieEdpc[28]; -/** Offset 0x0400 - USB PDO Programming +/** Offset 0x03EC - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x0401 +/** Offset 0x03ED - Reserved **/ - UINT8 UnusedUpdSpace18[3]; + UINT8 Reserved7[3]; -/** Offset 0x0404 - Power button debounce configuration +/** Offset 0x03F0 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x0408 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled +/** Offset 0x03F4 - PCH eSPI Host and Device BME enabled + PCH eSPI Host and Device BME enabled $EN_DIS **/ UINT8 PchEspiBmeMasterSlaveEnabled; -/** Offset 0x0409 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x040A - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states - Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtV1p05RailEnabledStates; - -/** Offset 0x040B - Mask to enable the platform configuration of external V1p05 VR rail - External V1P05 Rail Supported Configuration -**/ - UINT8 PchFivrExtV1p05RailSupportedVoltageStates; - -/** Offset 0x040C - External V1P05 Voltage Value that will be used in S0i2/S0i3 states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtV1p05RailVoltage; - -/** Offset 0x040E - External V1P05 Icc Max Value - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtV1p05RailIccMax; - -/** Offset 0x040F - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states - Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtVnnRailEnabledStates; - -/** Offset 0x0410 - Mask to enable the platform configuration of external Vnn VR rail - External Vnn Rail Supported Configuration -**/ - UINT8 PchFivrExtVnnRailSupportedVoltageStates; - -/** Offset 0x0411 -**/ - UINT8 UnusedUpdSpace19; - -/** Offset 0x0412 - External Vnn Voltage Value that will be used in S0ix/Sx states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 -**/ - UINT16 PchFivrExtVnnRailVoltage; - -/** Offset 0x0414 - External Vnn Icc Max Value that will be used in S0ix/Sx states - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailIccMax; - -/** Offset 0x0415 - Mask to enable the usage of external Vnn VR rail in Sx states - Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in - Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtVnnRailSxEnabledStates; - -/** Offset 0x0416 - External Vnn Voltage Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments - (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtVnnRailSxVoltage; - -/** Offset 0x0418 - External Vnn Icc Max Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting - is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailSxIccMax; - -/** Offset 0x0419 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to low current mode voltage. -**/ - UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; - -/** Offset 0x041A - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; - -/** Offset 0x041B - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; - -/** Offset 0x041C - Transition time in microseconds from Off (0V) to High Current Mode Voltage - This field has 1us resolution. When value is 0 Transition to 0V is disabled. -**/ - UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; - -/** Offset 0x041E -**/ - UINT8 UnusedUpdSpace20[2]; - -/** Offset 0x0420 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x0424 - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x0425 -**/ - UINT8 UnusedUpdSpace21[3]; - -/** Offset 0x0428 - Pointer of ChipsetInit Binary - ChipsetInit Binary Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x042C - Length of ChipsetInit Binary - ChipsetInit Binary Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x0430 - ChipsetInit Sync Enable - Enable/Disable. 0: Disable, 1: Enable -**/ - UINT8 ChipsetInitSyncEnable; - -/** Offset 0x0431 - FIVR Dynamic Power Management - Enable/Disable FIVR Dynamic Power Management. - $EN_DIS -**/ - UINT8 PchFivrDynPm; - -/** Offset 0x0432 - External V1P05 Icc Max Value - Granularity of this setting is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtV1p05RailIccMaximum; - -/** Offset 0x0434 - External Vnn Icc Max Value that will be used in S0ix/Sx states - Granularity of this setting is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtVnnRailIccMaximum; - -/** Offset 0x0436 - External Vnn Icc Max Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting - is 1mA and maximal possible value is 500mA -**/ - UINT16 PchFivrExtVnnRailSxIccMaximum; - -/** Offset 0x0438 - PCH eSPI Link Configuration Lock (SBLCL) +/** Offset 0x03F5 - PCH eSPI Link Configuration Lock (SBLCL) Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves addresseses from range 0x0 - 0x7FF $EN_DIS **/ UINT8 PchEspiLockLinkConfiguration; -/** Offset 0x0439 - Extented BIOS Direct Read Decode enable +/** Offset 0x03F6 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x03F7 - Mask to enable the platform configuration of external V1p05 VR rail + External V1P05 Rail Supported Configuration +**/ + UINT8 PchFivrExtV1p05RailSupportedVoltageStates; + +/** Offset 0x03F8 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x03FA - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x03FB - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x03FC - Mask to enable the platform configuration of external Vnn VR rail + External Vnn Rail Supported Configuration +**/ + UINT8 PchFivrExtVnnRailSupportedVoltageStates; + +/** Offset 0x03FD - Reserved +**/ + UINT8 Reserved8; + +/** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x0400 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x0401 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT4:S5, BIT5:S0 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x0402 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x0404 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage. +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x0407 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled. +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x040A - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x040B - Reserved +**/ + UINT8 Reserved9; + +/** Offset 0x040C - Pointer of ChipsetInit Binary + ChipsetInit Binary Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x0410 - Length of ChipsetInit Binary + ChipsetInit Binary Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x0414 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x0415 - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x0416 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtV1p05RailIccMaximum; + +/** Offset 0x0418 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x041A - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x041C - Extented BIOS Direct Read Decode enable Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. 0: disabled (default), 1: enabled $EN_DIS **/ UINT8 PchSpiExtendedBiosDecodeRangeEnable; -/** Offset 0x043A - PchPostMemRsvd - Reserved for PCH Post-Mem - $EN_DIS +/** Offset 0x041D - Reserved **/ - UINT8 PchPostMemRsvd[11]; + UINT8 Reserved11[3]; -/** Offset 0x0445 -**/ - UINT8 UnusedUpdSpace22[3]; - -/** Offset 0x0448 - Extended BIOS Direct Read Decode Range base +/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. **/ UINT32 PchSpiExtendedBiosDecodeRangeBase; -/** Offset 0x044C - Extended BIOS Direct Read Decode Range limit +/** Offset 0x0424 - Extended BIOS Direct Read Decode Range limit Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. **/ UINT32 PchSpiExtendedBiosDecodeRangeLimit; -/** Offset 0x0450 - CNVi Configuration +/** Offset 0x0428 - Reserved +**/ + UINT8 Reserved12[12]; + +/** Offset 0x0434 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x0451 - CNVi BT Core +/** Offset 0x0435 - Reserved +**/ + UINT8 Reserved13; + +/** Offset 0x0436 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x0452 - CNVi BT Audio Offload +/** Offset 0x0437 - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x0453 -**/ - UINT8 UnusedUpdSpace23; - -/** Offset 0x0454 - CNVi RF_RESET pin muxing - Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) - or GPP_F4 = 0x194BE404. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* - in GpioPins*.h. +/** Offset 0x0438 - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default) + or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0458 - CNVi CLKREQ pin muxing - Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default) - or GPP_F5 = 0x394BE605. TGP-H: 0. TGP-K: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* +/** Offset 0x043C - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default) + or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x045C - Enable Host C10 reporting through eSPI - Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire. +/** Offset 0x0440 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. $EN_DIS **/ UINT8 PchEspiHostC10ReportEnable; -/** Offset 0x045D - PCH USB2 PHY Power Gating enable +/** Offset 0x0441 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PmcUsb2PhySusPgEnable; -/** Offset 0x045E - PCH USB OverCurrent mapping enable +/** Offset 0x0442 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x045F - Espi Lgmr Memory Range decode +/** Offset 0x0443 - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x0460 - External V1P05 Control Ramp Timer value +/** Offset 0x0444 - External V1P05 Control Ramp Timer value Hold off time to be used when changing the v1p05_ctrl for external bypass value in us **/ UINT8 PchFivrExtV1p05RailCtrlRampTmr; -/** Offset 0x0461 - External VNN Control Ramp Timer value +/** Offset 0x0445 - External VNN Control Ramp Timer value Hold off time to be used when changing the vnn_ctrl for external bypass value in us **/ UINT8 PchFivrExtVnnRailCtrlRampTmr; -/** Offset 0x0462 - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS +/** Offset 0x0446 - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. **/ - UINT8 Heci3Enabled; + UINT8 SataPortsDevSlpResetConfig[8]; -/** Offset 0x0463 - PCHHOT# pin +/** Offset 0x044E - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x0464 - SATA LED +/** Offset 0x044F - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x0465 - VRAlert# Pin +/** Offset 0x0450 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x0466 - AMT Switch +/** Offset 0x0451 - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x0467 - WatchDog Timer Switch +/** Offset 0x0452 - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x0468 - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x0469 - PET Progress +/** Offset 0x0453 - PET Progress Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 FwProgress; -/** Offset 0x046A - SOL Switch +/** Offset 0x0454 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x046B +/** Offset 0x0455 - Reserved **/ - UINT8 UnusedUpdSpace24; + UINT8 Reserved14; -/** Offset 0x046C - OS Timer +/** Offset 0x0456 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x046E - BIOS Timer +/** Offset 0x0458 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x0470 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx. - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x0471 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting - is invalid if AmtEnabled is 0. - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x0472 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. +/** Offset 0x045A - Force MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution. $EN_DIS **/ UINT8 ForcMebxSyncUp; -/** Offset 0x0473 - PCH PCIe root port connection type +/** Offset 0x045B - PCH PCIe root port connection type 0: built-in device, 1:slot **/ - UINT8 PcieRpSlotImplemented[24]; + UINT8 PcieRpSlotImplemented[28]; -/** Offset 0x048B - PCIE RP Access Control Services Extended Capability +/** Offset 0x0477 - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ - UINT8 PcieRpAcsEnabled[24]; + UINT8 PcieRpAcsEnabled[28]; -/** Offset 0x04A3 - PCIE RP Clock Power Management +/** Offset 0x0493 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ - UINT8 PcieRpEnableCpm[24]; + UINT8 PcieRpEnableCpm[28]; -/** Offset 0x04BB - PCIE RP Multi VC Enabled - Enable/Disable PCIE RP Multiple Virtual Channels +/** Offset 0x04AF - Reserved **/ - UINT8 PcieRpMultiVcEnabled[24]; + UINT8 Reserved15; -/** Offset 0x04D3 - PCIE RP VC1 to TC Mapping - PCIE RP Virtual Channel 1 to Traffic Class mapping -**/ - UINT8 PcieRpVc1TcMap[24]; - -/** Offset 0x04EB -**/ - UINT8 UnusedUpdSpace25[1]; - -/** Offset 0x04EC - PCIE RP Detect Timeout Ms +/** Offset 0x04B0 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ - UINT16 PcieRpDetectTimeoutMs[24]; + UINT16 PcieRpDetectTimeoutMs[28]; -/** Offset 0x051C - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x04E8 - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x051D - V1p05-PHY supply external FET control +/** Offset 0x04E9 - V1p05-PHY supply external FET control Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05PhyExtFetControlEn; -/** Offset 0x051E - V1p05-IS supply external FET control +/** Offset 0x04EA - V1p05-IS supply external FET control Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05IsExtFetControlEn; -/** Offset 0x051F - Enable/Disable PavpEnable +/** Offset 0x04EB - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x0520 - CdClock Frequency selection - 0 (Default) Auto (Max based on reference clock frequency), 0: 172.8 Mhz, 1: 307.2, - 2: 312 Mhz, 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz - 0xFF: Auto (Max based on reference clock frequency), 0: 172.8 Mhz, 1: 307.2, 2: - 312 Mhz, 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz +/** Offset 0x04EC - CdClock Frequency selection + 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: + 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz, + 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz **/ UINT8 CdClock; -/** Offset 0x0521 - Enable/Disable PeiGraphicsPeimInit - Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit +/** Offset 0x04ED - Enable/Disable PeiGraphicsPeimInit + Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. + Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x0522 - Enable D3 Hot in TCSS +/** Offset 0x04EE - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x0523 - Enable or disable GNA device +/** Offset 0x04EF - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 GnaEnable; -/** Offset 0x0524 - Enable or disable HPD of DDI port-A device - 0=Disabled,1(Default)=eDP, 2=MIPI DSI, - 0:Disabled, 1:eDP, 2:MIPI DSI -**/ - UINT8 DdiPortAConfig; - -/** Offset 0x0525 - Enable or disable HPD of DDI port-B device - 1(Default)=DP, 2=MIPI DSI, 3=HDMI - 1:DP, 2:MIPI DSI, 3:HDMI -**/ - UINT8 DdiPortBConfig; - -/** Offset 0x0526 - Enable or disable HPD of DDI port-C device - 1(Default)= HDMI, 2=DP - 1:HDMI, 2:DP -**/ - UINT8 DdiPortCConfig; - -/** Offset 0x0527 - Enable or disable HPD of DDI port A - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortAHpd; - -/** Offset 0x0528 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0529 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x052A - Enable or disable HPD of DDI port 1 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort1Hpd; - -/** Offset 0x052B - Enable or disable HPD of DDI port 2 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort2Hpd; - -/** Offset 0x052C - Enable or disable HPD of DDI port 3 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort3Hpd; - -/** Offset 0x052D - Enable or disable HPD of DDI port 4 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort4Hpd; - -/** Offset 0x052E - Enable or disable DDC of DDI port A - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortADdc; - -/** Offset 0x052F - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x0530 - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x0531 - Enable DDC setting of DDI Port 1 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort1Ddc; - -/** Offset 0x0532 - Enable DDC setting of DDI Port 2 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort2Ddc; - -/** Offset 0x0533 - Enable DDC setting of DDI Port 3 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort3Ddc; - -/** Offset 0x0534 - Enable DDC setting of DDI Port 4 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort4Ddc; - -/** Offset 0x0535 -**/ - UINT8 UnusedUpdSpace26[3]; - -/** Offset 0x0538 - TypeC port GPIO setting +/** Offset 0x04F0 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined - in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Ehl - = ElkhartLake) + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl + = AlderLake) **/ UINT32 IomTypeCPortPadCfg[8]; -/** Offset 0x0558 - CPU USB3 Port Over Current Pin +/** Offset 0x0510 - CPU USB3 Port Over Current Pin Describe the specific over current pin number of USBC Port N. **/ UINT8 CpuUsb3OverCurrentPin[8]; -/** Offset 0x0560 - Enable D3 Cold in TCSS +/** Offset 0x0518 - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x0561 - Enable VMD controller - Enable/disable to VMD controller.0: Disable(Default); 1: Enable +/** Offset 0x0519 - Enable/Disable PCIe tunneling for USB4 + Enable/Disable PCIe tunneling for USB4, default is enable + $EN_DIS +**/ + UINT8 ITbtPcieTunnelingForUsb4; + +/** Offset 0x051A - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS +**/ + UINT8 SkipFspGop; + +/** Offset 0x051B - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; + +/** Offset 0x051C - Intel Graphics VBT (Video BIOS Table) Size + Size of Internal Graphics VBT Image +**/ + UINT32 VbtSize; + +/** Offset 0x0520 - Platform LID Status for LFP Displays. + LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. + 0: LidClosed, 1: LidOpen +**/ + UINT8 LidStatus; + +/** Offset 0x0521 - Reserved +**/ + UINT8 Reserved16[8]; + +/** Offset 0x0529 - Enable VMD controller + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x0562 - Enable VMD portA Support - Enable/disable to VMD portA Support. +/** Offset 0x052A - Map port under VMD + Map/UnMap port under VMD $EN_DIS **/ - UINT8 VmdPortA; + UINT8 VmdPort[31]; -/** Offset 0x0563 - Enable VMD portB Support - Enable/disable to VMD portB Support. - $EN_DIS +/** Offset 0x0549 - VMD Port Device + VMD Root port device number. **/ - UINT8 VmdPortB; + UINT8 VmdPortDev[31]; -/** Offset 0x0564 - Enable VMD portC Support - Enable/disable to VMD portC Support. - $EN_DIS +/** Offset 0x0568 - VMD Port Func + VMD Root port function number. **/ - UINT8 VmdPortC; + UINT8 VmdPortFunc[31]; -/** Offset 0x0565 - Enable VMD portD Support - Enable/disable to VMD portD Support. - $EN_DIS -**/ - UINT8 VmdPortD; - -/** Offset 0x0566 - VMD Config Bar size +/** Offset 0x0587 - VMD Config Bar size Set The VMD Config Bar Size. **/ - UINT8 VmdCfgBarSz; + UINT8 VmdCfgBarSize; -/** Offset 0x0567 - VMD Config Bar Attributes - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) +/** Offset 0x0588 - VMD Config Bar Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH **/ UINT8 VmdCfgBarAttr; -/** Offset 0x0568 - VMD Mem Bar1 size +/** Offset 0x0589 - VMD Mem Bar1 size Set The VMD Mem Bar1 Size. **/ - UINT8 VmdMemBarSz1; + UINT8 VmdMemBarSize1; -/** Offset 0x0569 - VMD Mem Bar1 Attributes +/** Offset 0x058A - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH **/ UINT8 VmdMemBar1Attr; -/** Offset 0x056A - VMD Mem Bar2 size +/** Offset 0x058B - VMD Mem Bar2 size Set The VMD Mem Bar2 Size. **/ - UINT8 VmdMemBarSz2; + UINT8 VmdMemBarSize2; -/** Offset 0x056B - VMD Mem Bar2 Attributes +/** Offset 0x058C - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH **/ UINT8 VmdMemBar2Attr; -/** Offset 0x056C - Enable/Disable PMC-PD Solution +/** Offset 0x058D - Reserved +**/ + UINT8 Reserved17[3]; + +/** Offset 0x0590 - VMD Variable + VMD Variable Pointer. +**/ + UINT32 VmdVariablePtr; + +/** Offset 0x0594 - Temporary CfgBar address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x0598 - Temporary MemBar1 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x059C - Temporary MemBar2 address for VMD + VMD Variable Pointer. +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x05A0 - Reserved +**/ + UINT8 Reserved18; + +/** Offset 0x05A1 - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution $EN_DIS **/ UINT8 PmcPdEnable; -/** Offset 0x056D -**/ - UINT8 UnusedUpdSpace27; - -/** Offset 0x056E - TCSS Aux Orientation Override Enable +/** Offset 0x05A2 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x0570 - TCSS HSL Orientation Override Enable +/** Offset 0x05A4 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x0572 - USB override in IOM +/** Offset 0x05A6 - USB override in IOM This policy will enable/disable USB Connect override in IOM $EN_DIS **/ UINT8 UsbOverride; -/** Offset 0x0573 - TCSS USB Port Enable - Bits 0, 1, ... max Type C port control enables -**/ - UINT8 UsbTcPortEn; - -/** Offset 0x0574 - ITBT Root Port Enable +/** Offset 0x05A7 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x0578 - ITBTForcePowerOn Timeout value +/** Offset 0x05AB - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x05AC - ITBTForcePowerOn Timeout value ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms. **/ UINT16 ITbtForcePowerOnTimeoutInMs; -/** Offset 0x057A - ITbtConnectTopology Timeout value +/** Offset 0x05AE - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x057C - VCCST request for IOM +/** Offset 0x05B0 - VCCST request for IOM This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 $EN_DIS **/ UINT8 VccSt; -/** Offset 0x057D +/** Offset 0x05B1 - Reserved **/ - UINT8 UnusedUpdSpace28[1]; + UINT8 Reserved19; -/** Offset 0x057E - ITBT DMA LTR +/** Offset 0x05B2 - ITBT DMA LTR TCSS DMA1, DMA2 LTR value **/ UINT16 ITbtDmaLtr[2]; -/** Offset 0x0582 - Enable/Disable CrashLog - Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog - $EN_DIS +/** Offset 0x05B6 - Reserved **/ - UINT8 CpuCrashLogEnable; + UINT8 Reserved20; -/** Offset 0x0583 - Enable/Disable PTM +/** Offset 0x05B7 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x0587 - PCIE RP Ltr Enable +/** Offset 0x05BB - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 SaPcieItbtRpLtrEnable[4]; -/** Offset 0x058B - PCIE RP Snoop Latency Override Mode +/** Offset 0x05BF - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; -/** Offset 0x058F - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x05C3 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x0593 +/** Offset 0x05C7 - Reserved **/ - UINT8 UnusedUpdSpace29[1]; + UINT8 Reserved21; -/** Offset 0x0594 - PCIE RP Snoop Latency Override Value +/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; -/** Offset 0x059C - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x05D0 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x05A0 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x05D4 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x05A4 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x05D8 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x05AC - Force LTR Override +/** Offset 0x05E0 - Force LTR Override Force LTR Override. **/ UINT8 SaPcieItbtRpForceLtrOverride[4]; -/** Offset 0x05B0 - PCIE RP Ltr Config Lock +/** Offset 0x05E4 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 SaPcieItbtRpLtrConfigLock[4]; -/** Offset 0x05B4 - Advanced Encryption Standard (AES) feature +/** Offset 0x05E8 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 AesEnable; -/** Offset 0x05B5 - Power State 3 enable/disable +/** Offset 0x05E9 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. For all VR Indexes **/ UINT8 Psi3Enable[5]; -/** Offset 0x05BA - Power State 4 enable/disable +/** Offset 0x05EE - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 Psi4Enable[5]; -/** Offset 0x05BF +/** Offset 0x05F3 - Reserved **/ - UINT8 UnusedUpdSpace30[1]; + UINT8 Reserved22; -/** Offset 0x05C0 - Imon slope correction +/** Offset 0x05F4 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes **/ UINT16 ImonSlope[5]; -/** Offset 0x05CA - Imon offset correction +/** Offset 0x05FE - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto **/ UINT16 ImonOffset[5]; -/** Offset 0x05D4 - Enable/Disable BIOS configuration of VR +/** Offset 0x0608 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 VrConfigEnable[5]; -/** Offset 0x05D9 - Thermal Design Current enable/disable +/** Offset 0x060D - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcEnable[5]; -/** Offset 0x05DE +/** Offset 0x0612 - Reserved **/ - UINT8 UnusedUpdSpace31[2]; + UINT8 Reserved23[2]; -/** Offset 0x05E0 - Thermal Design Current time window +/** Offset 0x0614 - Thermal Design Current time window PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. Range 1ms to 448s **/ UINT32 TdcTimeWindow[5]; -/** Offset 0x05F4 - Thermal Design Current Lock +/** Offset 0x0628 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes **/ UINT8 TdcLock[5]; -/** Offset 0x05F9 - Platform Psys slope correction +/** Offset 0x062D - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25 **/ UINT8 PsysSlope; -/** Offset 0x05FA - Platform Psys offset correction +/** Offset 0x062E - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348. **/ UINT16 PsysOffset; -/** Offset 0x05FC - Acoustic Noise Mitigation feature +/** Offset 0x0630 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 AcousticNoiseMitigation; -/** Offset 0x05FD - Disable Fast Slew Rate for Deep Package C States for VR domains +/** Offset 0x0631 - Disable Fast Slew Rate for Deep Package C States for VR domains Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisable[5]; -/** Offset 0x0602 - Slew Rate configuration for Deep Package C States for VR domains +/** Offset 0x0636 - Slew Rate configuration for Deep Package C States for VR domains Slew Rate configuration for Deep Package C States for VR domains based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + Noise Mitigation feature enabled. ADL supports VCCIA FAST/2/4/8/16, VCCGT FAST/2/4/8 + and VCCSA FAST/2 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRate[5]; -/** Offset 0x0607 +/** Offset 0x063B - Reserved **/ - UINT8 UnusedUpdSpace32[1]; + UINT8 Reserved24; -/** Offset 0x0608 - Thermal Design Current current limit +/** Offset 0x063C - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes **/ UINT16 TdcCurrentLimit[5]; -/** Offset 0x0612 - AcLoadline +/** Offset 0x0646 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU. **/ UINT16 AcLoadline[5]; -/** Offset 0x061C - DcLoadline +/** Offset 0x0650 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU. **/ UINT16 DcLoadline[5]; -/** Offset 0x0626 - Power State 1 Threshold current +/** Offset 0x065A - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi1Threshold[5]; -/** Offset 0x0630 - Power State 2 Threshold current +/** Offset 0x0664 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi2Threshold[5]; -/** Offset 0x063A - Power State 3 Threshold current +/** Offset 0x066E - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. **/ UINT16 Psi3Threshold[5]; -/** Offset 0x0644 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A +/** Offset 0x0678 - Icc Max limit + PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A **/ UINT16 IccMax[5]; -/** Offset 0x064E - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x064F - Enable or Disable TXT +/** Offset 0x0682 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TxtEnable; -/** Offset 0x0650 - Skip Multi-Processor Initialization +/** Offset 0x0683 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize; 1: Skip $EN_DIS **/ UINT8 SkipMpInit; -/** Offset 0x0651 -**/ - UINT8 UnusedUpdSpace33; - -/** Offset 0x0652 - FIVR RFI Frequency +/** Offset 0x0684 - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock. **/ UINT16 FivrRfiFrequency; -/** Offset 0x0654 - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. 0: 0%; - Range: 0.0% to 10.0% (0-100). +/** Offset 0x0686 - FIVR RFI Spread Spectrum + Set the Spread Spectrum Range. 1.5%; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, + 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% + = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x0655 +/** Offset 0x0687 - Reserved **/ - UINT8 UnusedUpdSpace34[3]; + UINT8 Reserved25; -/** Offset 0x0658 - UFS Soft Strap Start Address - UFS Soft Strap Start Address, Value will be based on the CSE IFWI Layout -**/ - UINT32 UfsStrapAddress; - -/** Offset 0x065C - CpuBistData +/** Offset 0x0688 - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; -/** Offset 0x0660 - CpuMpPpi +/** Offset 0x068C - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x0664 - CpuMpHob - Optional pointer for CpuMpHob. If the boot loader is a UEFI boot loader using - API mode instead of dispatch mode, and FspsUpd->FspsConfig.CpuMpPpi != NULL, then - FspsUpd->FspsConfig.CpuMpHob must be != NULL. See section 5.1.4 of the FSP Integration - Guide for more details. +/** Offset 0x0690 - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled. Range 0-255 0. **/ - UINT32 CpuMpHob; + UINT8 PreWake; -/** Offset 0x0668 +/** Offset 0x0691 - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. **/ - UINT8 CpuPostMemRsvd[16]; + UINT8 RampUp; -/** Offset 0x0678 - PpinSupport to view Protected Processor Inventory Number +/** Offset 0x0692 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x0693 - Reserved +**/ + UINT8 Reserved26; + +/** Offset 0x0694 - VR Voltage Limit + PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV +**/ + UINT16 VrVoltageLimit[5]; + +/** Offset 0x069E - VccIn Aux Imon IccMax + PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp + increments. Range is 0-512. +**/ + UINT16 VccInAuxImonIccImax; + +/** Offset 0x06A0 - Reserved +**/ + UINT8 Reserved27[10]; + +/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable + Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable +**/ + UINT8 FivrSpectrumEnable; + +/** Offset 0x06AB - Reserved +**/ + UINT8 Reserved28[13]; + +/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this flag is set) for PPIN Support 0: Disable, 1: Enable, 2: Auto **/ UINT8 PpinSupport; -/** Offset 0x0679 - Enable or Disable Minimum Voltage Override +/** Offset 0x06B9 - Enable or Disable Minimum Voltage Override Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 EnableMinVoltageOverride; -/** Offset 0x067A - Min Voltage for Runtime +/** Offset 0x06BA - Min Voltage for Runtime PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV **/ UINT16 MinVoltageRuntime; -/** Offset 0x067C +/** Offset 0x06BC - Reserved **/ - UINT8 UnusedUpdSpace35[4]; + UINT8 Reserved29[2]; -/** Offset 0x0680 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0688 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x068C - Min Voltage for C8 +/** Offset 0x06BE - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV **/ UINT16 MinVoltageC8; -/** Offset 0x068E - Smbios Type4 Max Speed Override +/** Offset 0x06C0 - Smbios Type4 Max Speed Override Provide the option for platform to override the MaxSpeed field of Smbios Type 4. If this value is not zero, it dominates the field. **/ UINT16 SmbiosType4MaxSpeedOverride; -/** Offset 0x0690 - ReservedCpuPostMemProduction - Reserved for CPU Post-Mem Production - $EN_DIS +/** Offset 0x06C2 - Current root mean square + PCODE MMIO Mailbox: Current root mean square; 0: Disable; 1: Enable.For all + VR Indexes **/ - UINT8 ReservedCpuPostMemProduction[6]; + UINT8 Irms[5]; -/** Offset 0x0696 - AC Split Lock - Enable/Disable #AC check on split lock. 0: Disable; 1: Enable. - $EN_DIS +/** Offset 0x06C7 - AvxDisable + Enable or Disable AVX Support. This only applicable when all small core is disabled. + 0: Enable, 1: Disable **/ - UINT8 AcSplitLock; + UINT8 AvxDisable; -/** Offset 0x0697 - PCH Master Clock Gating Control - Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default - $EN_DIS +/** Offset 0x06C8 - Avx3Disable + DEPRECATED + 0: Enable, 1: Disable **/ - UINT8 PchPostMasterClockGating; + UINT8 Avx3Disable; -/** Offset 0x0698 - PCH Master Power Gating Control - Provide a master control for power gating for all PCH devices, 0: Disabled; 1: Default - $EN_DIS +/** Offset 0x06C9 - Reserved **/ - UINT8 PchPostMasterPowerGating; + UINT8 Reserved30; -/** Offset 0x0699 - Sci Pin Mux Enable - Enable/Disable Sci Gpio Pin Mux. 0: Disable; 1: Enable. - $EN_DIS +/** Offset 0x06CA - CPU VR Power Delivery Design + Used to communicate the power delivery design capability of the board. This value + is an enum of the available power delivery segments that are defined in the Platform + Design Guide. **/ - UINT8 SciPinMuxEnable; + UINT8 VrPowerDeliveryDesign; -/** Offset 0x069A - Enable Power Optimizer +/** Offset 0x06CB - Reserved +**/ + UINT8 Reserved31[32]; + +/** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x069B - PCH Flash Protection Ranges Write Enble +/** Offset 0x06EC - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x06A0 - PCH Flash Protection Ranges Read Enble +/** Offset 0x06F1 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x06A5 -**/ - UINT8 UnusedUpdSpace36[1]; - -/** Offset 0x06A6 - PCH Protect Range Limit +/** Offset 0x06F6 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x06B0 - PCH Protect Range Base +/** Offset 0x0700 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x06BA - Enable Pme +/** Offset 0x070A - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x06BB - HD Audio Link Frequency +/** Offset 0x070B - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x06BC - Enable PCH Io Apic Entry 24-119 +/** Offset 0x070C - Enable PCH ISH SPI Cs0 pins assigned + Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. +**/ + UINT8 PchIshSpiCs0Enable[1]; + +/** Offset 0x070D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x06BD - PCH Io Apic ID +/** Offset 0x070E - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x06BE +/** Offset 0x070F - Enable PCH ISH SPI pins assigned + Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ - UINT8 UnusedUpdSpace37[2]; + UINT8 PchIshSpiEnable[1]; -/** Offset 0x06C0 - PCH PSE Log Output Channel - Set PSE Log Output Channel. 0: internal memory; 1 to 6: UART channels; Other: shut down +/** Offset 0x0710 - Enable PCH ISH UART pins assigned + Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ - UINT32 PchPseLogOutputChannel; + UINT8 PchIshUartEnable[2]; -/** Offset 0x06C4 - PCH PSE Log Output Size - Set PSE Log Output Size +/** Offset 0x0712 - Enable PCH ISH I2C pins assigned + Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ - UINT16 PchPseLogOutputSize; + UINT8 PchIshI2cEnable[3]; -/** Offset 0x06C6 - PCH PSE Log Output Offset - Set PSE Log Output Offset +/** Offset 0x0715 - Enable PCH ISH GP pins assigned + Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ - UINT16 PchPseLogOutputOffset; + UINT8 PchIshGpEnable[8]; -/** Offset 0x06C8 - PCH PSE OOB Prov State Offset - Set PSE OOB Prov State Offset +/** Offset 0x071D - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS **/ - UINT16 PchPseOobProvDone; + UINT8 PchIshPdtUnlock; -/** Offset 0x06CA - Enable PCH PSE I2S pins assigned - Set if PSE I2S native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseI2sEnable[2]; - -/** Offset 0x06CC - PchPseI2sTxPinMux - Select PSE I2S Tx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_TXD* for possible values. -**/ - UINT32 PchPseI2sTxPinMux[2]; - -/** Offset 0x06D4 - PchPseI2sRxPinMux - Select PSE I2S Rx pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_RXD* for possible values. -**/ - UINT32 PchPseI2sRxPinMux[2]; - -/** Offset 0x06DC - PchPseI2sSfrmPinMux - Select PSE I2S Sfrm pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SFRM* for possible values. -**/ - UINT32 PchPseI2sSfrmPinMux[2]; - -/** Offset 0x06E4 - PchPseI2sSclkPinMux - Select PSE I2S Sclk pin muxing. Refer to GPIO_*_MUXING_PSE_I2Sx_SCLK* for possible values. -**/ - UINT32 PchPseI2sSclkPinMux[2]; - -/** Offset 0x06EC - Enable PCH PSE PWM pins assigned - Set if PSE PWM native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPsePwmEnable; - -/** Offset 0x06ED - PchPsePwmPinEnable - Set PWM pin to PSE PWM native function. 0: Disable; 1: Enable. -**/ - UINT8 PchPsePwmPinEnable[16]; - -/** Offset 0x06FD -**/ - UINT8 UnusedUpdSpace38[3]; - -/** Offset 0x0700 - PchPsePwmPinMux - Select PSE Pwm pin muxing start from PWM0 to PWM15. Refer to GPIO_*_MUXING_PSE_PWM* - for possible values. -**/ - UINT32 PchPsePwmPinMux[16]; - -/** Offset 0x0740 - Enable PCH PSE UART pins assigned - Set if PSE UART native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseUartEnable[6]; - -/** Offset 0x0746 - Enable PCH PSE HSUART pins assigned - Set if PSE HSUART native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseHsuartEnable[4]; - -/** Offset 0x074A - Enable PCH PSE QEP pins assigned - Set if PSE QEP native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseQepEnable[4]; - -/** Offset 0x074E - Enable PCH PSE DMA pins assigned - Set if PSE DMA native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseDmaEnable[3]; - -/** Offset 0x0751 - Enable PCH PSE GBE pins assigned - Set if PSE GBE native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseGbeEnable[2]; - -/** Offset 0x0753 - Enable PCH PSE I2C pins assigned - Set if PSE I2C native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseI2cEnable[8]; - -/** Offset 0x075B - Enable PCH PSE SPI pins assigned - Set if PSE SPI native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseSpiEnable[4]; - -/** Offset 0x075F - Enable PCH PSE SPI CS0 pins assigned - Set if PSE SPI CS0 pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseSpiCs0Enable[4]; - -/** Offset 0x0763 - Enable PCH PSE SPI CS1 pins assigned - Set if PSE SPI CS1 pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseSpiCs1Enable[4]; - -/** Offset 0x0767 -**/ - UINT8 UnusedUpdSpace39[1]; - -/** Offset 0x0768 - PchPseSpiMosiPinMux - Select PSE Spi Mosi pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MOSI* for possible values. -**/ - UINT32 PchPseSpiMosiPinMux[4]; - -/** Offset 0x0778 - PchPseSpiMisoPinMux - Select PSE Spi Miso pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_MISO* for possible values. -**/ - UINT32 PchPseSpiMisoPinMux[4]; - -/** Offset 0x0788 - PchPseSpiClkPinMux - Select PSE Spi Clk pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_SCLK* for possible values. -**/ - UINT32 PchPseSpiClkPinMux[4]; - -/** Offset 0x0798 - PchPseSpiCs0PinMux - Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values. -**/ - UINT32 PchPseSpiCs0PinMux[4]; - -/** Offset 0x07A8 - PchPseSpiCs1PinMux - Select PSE Spi Cs pin muxing. Refer to GPIO_*_MUXING_PSE_SPIx_Cs* for possible values. -**/ - UINT32 PchPseSpiCs1PinMux[4]; - -/** Offset 0x07B8 - Enable PCH PSE SPI Delay RxClk - Set if PSE SPI native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseSpiDelayRxClk[4]; - -/** Offset 0x07BC - Enable PCH PSE ADC pins assigned - Set if PSE ADC native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseAdcEnable; - -/** Offset 0x07BD - Enable PCH PSE CAN pins assigned - Set if PSE CAN native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseCanEnable[2]; - -/** Offset 0x07BF - Enable PCH PSE I2S sideband interrupt - Set if PSE I2S are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseI2sSbInterruptEnable[2]; - -/** Offset 0x07C1 - Enable PCH PSE PWM sideband interrupt - Set if PSE PWM are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPsePwmSbInterruptEnable; - -/** Offset 0x07C2 - Enable PCH PSE UART sideband interrupt - Set if PSE UART are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseUartSbInterruptEnable[6]; - -/** Offset 0x07C8 - Enable PCH PSE QEP sideband interrupt - Set if PSE QEP are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseQepSbInterruptEnable[4]; - -/** Offset 0x07CC - Enable PCH PSE DMA sideband interrupt - Set if PSE DMA are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseDmaSbInterruptEnable[3]; - -/** Offset 0x07CF - Enable PCH PSE I2C sideband interrupt - Set if PSE I2C are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseI2cSbInterruptEnable[8]; - -/** Offset 0x07D7 - Enable PCH PSE SPI sideband interrupt - Set if PSE SPI are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseSpiSbInterruptEnable[4]; - -/** Offset 0x07DB - Enable PCH PSE ADC sideband interrupt - Set if PSE ADC are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseAdcSbInterruptEnable; - -/** Offset 0x07DC - Enable PCH PSE LH2OSE sideband interrupt - Set if PSE LH2OSE are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseLh2PseSbInterruptEnable; - -/** Offset 0x07DD - Enable PCH PSE CAN sideband interrupt - Set if PSE CAN are to be set to sideband interrupt. 0: Disable; 1: Enable. -**/ - UINT8 PchPseCanSbInterruptEnable[2]; - -/** Offset 0x07DF - Enable PCH PSE Timed GPIO pins assigned - Set if PSE Timed GPIO native pins and ownership are to be enabled by BIOS. 0: Disable/pins - are not owned by PSE/host; 1: Pins are muxed to PSE IP, the IO is owned by PSE; - 2: Pins are muxed to PSE IP, the IO is owned by host; -**/ - UINT8 PchPseTimedGpioEnable[2]; - -/** Offset 0x07E1 - Enable PCH PSE Timed GPIO 20 pins allocation - Allocate 20 pins for PCH PSE Timed GPIO. 0: Top 20 pins; 1: Mid 20 pins; 2: Lower 20 pins. -**/ - UINT8 PchPseTimedGpioPinAllocation[2]; - -/** Offset 0x07E3 - Enable PCH PSE Timed GPIO Pin to PSE TGPIO native function - Set TGPIO pin to PSE TGPIO native function. 0: Disable; 1: Enable. -**/ - UINT8 PchPseTimedGpioPinEnable[60]; - -/** Offset 0x081F -**/ - UINT8 UnusedUpdSpace40; - -/** Offset 0x0820 - Pch Pse Tgpio6 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio6PinMux; - -/** Offset 0x0824 - Pch Pse Tgpio7 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio7PinMux; - -/** Offset 0x0828 - Pch Pse Tgpio8 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio8PinMux; - -/** Offset 0x082C - Pch Pse Tgpio9 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio9PinMux; - -/** Offset 0x0830 - Pch Pse Tgpio10 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio10PinMux; - -/** Offset 0x0834 - Pch Pse Tgpio11 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio11PinMux; - -/** Offset 0x0838 - Pch Pse Tgpio12 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio12PinMux; - -/** Offset 0x083C - Pch Pse Tgpio13 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio13PinMux; - -/** Offset 0x0840 - Pch Pse Tgpio14 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio14PinMux; - -/** Offset 0x0844 - Pch Pse Tgpio15 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio15PinMux; - -/** Offset 0x0848 - Pch Pse Tgpio16 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio16PinMux; - -/** Offset 0x084C - Pch Pse Tgpio17 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio17PinMux; - -/** Offset 0x0850 - Pch Pse Tgpio18 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio18PinMux; - -/** Offset 0x0854 - Pch Pse Tgpio19 Pin Mux - Select PSE Timed Gpio pin muxing. Refer to GPIO_*_MUXING_PSE_TGPIO* for possible values. -**/ - UINT32 PchPseTgpio19PinMux; - -/** Offset 0x0858 - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x071E - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x0859 - Enable LOCKDOWN BIOS LOCK +/** Offset 0x071F - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x085A - PCH Compatibility Revision ID +/** Offset 0x0720 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x085B - RTC BIOS Interface Lock +/** Offset 0x0721 - RTC BIOS Interface Lock Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. $EN_DIS **/ UINT8 RtcBiosInterfaceLock; -/** Offset 0x085C - RTC Cmos Memory Lock +/** Offset 0x0722 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x085D - Enable PCIE RP HotPlug +/** Offset 0x0723 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ - UINT8 PcieRpHotPlug[24]; + UINT8 PcieRpHotPlug[28]; -/** Offset 0x0875 - Enable PCIE RP Pm Sci +/** Offset 0x073F - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ - UINT8 PcieRpPmSci[24]; + UINT8 PcieRpPmSci[28]; -/** Offset 0x088D - Enable PCIE RP Transmitter Half Swing +/** Offset 0x075B - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ - UINT8 PcieRpTransmitterHalfSwing[24]; + UINT8 PcieRpTransmitterHalfSwing[28]; -/** Offset 0x08A5 - Enable PCIE RP Clk Req Detect +/** Offset 0x0777 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ - UINT8 PcieRpClkReqDetect[24]; + UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x08BD - PCIE RP Advanced Error Report +/** Offset 0x0793 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ - UINT8 PcieRpAdvancedErrorReporting[24]; + UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x08D5 - PCIE RP Unsupported Request Report +/** Offset 0x07AF - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ - UINT8 PcieRpUnsupportedRequestReport[24]; + UINT8 PcieRpUnsupportedRequestReport[28]; -/** Offset 0x08ED - PCIE RP Fatal Error Report +/** Offset 0x07CB - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ - UINT8 PcieRpFatalErrorReport[24]; + UINT8 PcieRpFatalErrorReport[28]; -/** Offset 0x0905 - PCIE RP No Fatal Error Report +/** Offset 0x07E7 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ - UINT8 PcieRpNoFatalErrorReport[24]; + UINT8 PcieRpNoFatalErrorReport[28]; -/** Offset 0x091D - PCIE RP Correctable Error Report +/** Offset 0x0803 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ - UINT8 PcieRpCorrectableErrorReport[24]; + UINT8 PcieRpCorrectableErrorReport[28]; -/** Offset 0x0935 - PCIE RP System Error On Fatal Error +/** Offset 0x081F - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ - UINT8 PcieRpSystemErrorOnFatalError[24]; + UINT8 PcieRpSystemErrorOnFatalError[28]; -/** Offset 0x094D - PCIE RP System Error On Non Fatal Error +/** Offset 0x083B - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; + UINT8 PcieRpSystemErrorOnNonFatalError[28]; -/** Offset 0x0965 - PCIE RP System Error On Correctable Error +/** Offset 0x0857 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; + UINT8 PcieRpSystemErrorOnCorrectableError[28]; -/** Offset 0x097D - PCIE RP Max Payload +/** Offset 0x0873 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ - UINT8 PcieRpMaxPayload[24]; + UINT8 PcieRpMaxPayload[28]; -/** Offset 0x0995 - Touch Host Controller Port 0 Assignment +/** Offset 0x088F - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x0996 -**/ - UINT8 UnusedUpdSpace41[2]; - -/** Offset 0x0998 - THC Port 0 Interrupt Pin Mux +/** Offset 0x0890 - Touch Host Controller Port 0 Interrupt Pin Mux Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT32 ThcPort0InterruptPinMuxing; -/** Offset 0x099C - Touch Host Controller Port 1 Assignment +/** Offset 0x0894 - Reserved +**/ + UINT8 Reserved32; + +/** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x099D - Touch Host Controller Port 1 ReadFrequency - Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz - 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz +/** Offset 0x0896 - Reserved **/ - UINT8 ThcPort1ReadFrequency; + UINT8 Reserved33[2]; -/** Offset 0x099E - Touch Host Controller Port 1 WriteFrequency - Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz - 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz -**/ - UINT8 ThcPort1WriteFrequency; - -/** Offset 0x099F -**/ - UINT8 UnusedUpdSpace42; - -/** Offset 0x09A0 - THC Port 1 Interrupt Pin Mux +/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT32 ThcPort1InterruptPinMuxing; -/** Offset 0x09A4 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). +/** Offset 0x089C - Reserved **/ - UINT8 PcieRpPcieSpeed[24]; + UINT8 Reserved34; -/** Offset 0x09BC - PCIE RP Physical Slot Number +/** Offset 0x089D - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; + 4: Gen4 (see: PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[28]; + +/** Offset 0x08B9 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ - UINT8 PcieRpPhysicalSlotNumber[24]; + UINT8 PcieRpPhysicalSlotNumber[28]; -/** Offset 0x09D4 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +/** Offset 0x08D5 - PCIE RP Completion Timeout + The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ - UINT8 PcieRpCompletionTimeout[24]; + UINT8 PcieRpCompletionTimeout[28]; -/** Offset 0x09EC - PCIE RP Aspm +/** Offset 0x08F1 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ - UINT8 PcieRpAspm[24]; + UINT8 PcieRpAspm[28]; -/** Offset 0x0A04 - PCIE RP L1 Substates +/** Offset 0x090D - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ - UINT8 PcieRpL1Substates[24]; + UINT8 PcieRpL1Substates[28]; -/** Offset 0x0A1C - PCIE RP Ltr Enable +/** Offset 0x0929 - Reserved +**/ + UINT8 Reserved35[28]; + +/** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ - UINT8 PcieRpLtrEnable[24]; + UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0A34 - PCIE RP Ltr Config Lock +/** Offset 0x0961 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ - UINT8 PcieRpLtrConfigLock[24]; + UINT8 PcieRpLtrConfigLock[28]; -/** Offset 0x0A4C - PCIe override default settings for EQ +/** Offset 0x097D - PCIe override default settings for EQ Choose PCIe EQ method $EN_DIS **/ UINT8 PcieEqOverrideDefault; -/** Offset 0x0A4D - PCIe choose EQ method +/** Offset 0x097E - PCIe choose EQ method Choose PCIe EQ method 0: HardwareEq, 1: FixedEq **/ UINT8 PcieEqMethod; -/** Offset 0x0A4E - PCIe choose EQ mode +/** Offset 0x097F - PCIe choose EQ mode Choose PCIe EQ mode 0: PresetEq, 1: CoefficientEq **/ UINT8 PcieEqMode; -/** Offset 0x0A4F - PCIe EQ local transmitter override +/** Offset 0x0980 - PCIe EQ local transmitter override Enable/Disable local transmitter override $EN_DIS **/ UINT8 PcieEqLocalTransmitterOverrideEnable; -/** Offset 0x0A50 - PCIe number of valid list entries +/** Offset 0x0981 - PCIe number of valid list entries Select number of presets or coefficients depending on the mode **/ UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; -/** Offset 0x0A51 - PCIe pre-cursor coefficient list +/** Offset 0x0982 - PCIe pre-cursor coefficient list Provide a list of pre-cursor coefficients to be used during phase 3 EQ **/ UINT8 PcieEqPh3PreCursorList[10]; -/** Offset 0x0A5B - PCIe post-cursor coefficient list +/** Offset 0x098C - PCIe post-cursor coefficient list Provide a list of post-cursor coefficients to be used during phase 3 EQ **/ UINT8 PcieEqPh3PostCursorList[10]; -/** Offset 0x0A65 - PCIe preset list +/** Offset 0x0996 - PCIe preset list Provide a list of presets to be used during phase 3 EQ **/ UINT8 PcieEqPh3PresetList[11]; -/** Offset 0x0A70 - PCIe EQ phase 1 downstream transmitter port preset +/** Offset 0x09A1 - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase 1 of equalization **/ UINT32 PcieEqPh1DownstreamPortTransmitterPreset; -/** Offset 0x0A74 - PCIe EQ phase 1 upstream tranmitter port preset +/** Offset 0x09A8 - PCIe EQ phase 1 upstream tranmitter port preset Allows to select the upstream port preset value that will be used during phase 1 of equalization **/ UINT32 PcieEqPh1UpstreamPortTransmitterPreset; -/** Offset 0x0A78 - PCIe EQ phase 2 local transmitter override preset +/** Offset 0x09AC - PCIe EQ phase 2 local transmitter override preset Allows to select the value of the preset used during phase 2 local transmitter override **/ UINT8 PcieEqPh2LocalTransmitterOverridePreset; -/** Offset 0x0A79 - PCIE Enable Peer Memory Write +/** Offset 0x09AD - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ - UINT8 PcieEnablePeerMemoryWrite; + UINT8 PcieEnablePeerMemoryWrite[28]; -/** Offset 0x0A7A - PCIE Compliance Test Mode +/** Offset 0x09C9 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0A7B - PCI Express Clock Gating - Enable/Disable Clock Gating, 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 TestPcieClockGating; - -/** Offset 0x0A7C - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. +/** Offset 0x09CA - PCIE Rp Function Swap + DEPRECATED. Allows BIOS to use root port function number swapping when root port + of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0A7D - Enable/Disable PEG GEN3 Static EQ Phase1 programming +/** Offset 0x09CB - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 CpuPcieGen3ProgramStaticEq; -/** Offset 0x0A7E - Enable/Disable GEN4 Static EQ Phase1 programming +/** Offset 0x09CC - Enable/Disable GEN4 Static EQ Phase1 programming Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 CpuPcieGen4ProgramStaticEq; -/** Offset 0x0A7F - PCH Pm PME_B0_S5_DIS +/** Offset 0x09CD - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0A80 - PCIE IMR +/** Offset 0x09CE - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0A81 - PCIE IMR port number +/** Offset 0x09CF - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0A82 - PCH Pm Wol Enable Override +/** Offset 0x09D0 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x0A83 - PCH Pm Pcie Wake From DeepSx +/** Offset 0x09D1 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x0A84 - PCH Pm WoW lan Enable +/** Offset 0x09D2 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x0A85 - PCH Pm WoW lan DeepSx Enable +/** Offset 0x09D3 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x0A86 - PCH Pm Lan Wake From DeepSx +/** Offset 0x09D4 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x0A87 - PCH Pm Deep Sx Pol +/** Offset 0x09D5 - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x0A88 - PCH Pm Slp S3 Min Assert +/** Offset 0x09D6 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0A89 - PCH Pm Slp S4 Min Assert +/** Offset 0x09D7 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0A8A - PCH Pm Slp Sus Min Assert +/** Offset 0x09D8 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0A8B - PCH Pm Slp A Min Assert +/** Offset 0x09D9 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0A8C - USB Overcurrent Override for DbC +/** Offset 0x09DA - USB Overcurrent Override for VISA This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. + after enabling this option. Enable when VISA pin is muxed with USB OC $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0A8D - PCH Pm Slp Strch Sus Up +/** Offset 0x09DB - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0A8E - PCH Pm Slp Lan Low Dc +/** Offset 0x09DC - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x0A8F - PCH Pm Pwr Btn Override Period +/** Offset 0x09DD - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x0A90 - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x09DE - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x0A91 - PCH Pm Disable Native Power Button +/** Offset 0x09DF - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x0A92 - PCH Pm ME_WAKE_STS +/** Offset 0x09E0 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x0A93 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x09E1 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x0A94 - PCH Pm Reset Power Cycle Duration +/** Offset 0x09E2 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x0A95 - PCH Pm Pcie Pll Ssc +/** Offset 0x09E3 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x0A96 - PCH Legacy IO Low Latency Enable +/** Offset 0x09E4 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x0A97 - PCH Sata Pwr Opt Enable +/** Offset 0x09E5 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0A98 - PCH Sata eSATA Speed Limit +/** Offset 0x09E6 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x0A99 - PCH Sata Speed Limit +/** Offset 0x09E7 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x0A9A - Enable SATA Port HotPlug +/** Offset 0x09E8 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x0AA2 - Enable SATA Port Interlock Sw +/** Offset 0x09F0 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x0AAA - Enable SATA Port External +/** Offset 0x09F8 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x0AB2 - Enable SATA Port SpinUp +/** Offset 0x0A00 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0ABA - Enable SATA Port Solid State Drive +/** Offset 0x0A08 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x0AC2 - Enable SATA Port Enable Dito Config +/** Offset 0x0A10 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0ACA - Enable SATA Port DmVal +/** Offset 0x0A18 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0AD2 - Enable SATA Port DmVal +/** Offset 0x0A20 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x0AE2 - Enable SATA Port ZpOdd +/** Offset 0x0A30 - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x0AEA - Enable SATA Port RxPolarity - Reverse RxPolarity. -**/ - UINT8 SataPortsRxPolarity[8]; - -/** Offset 0x0AF2 - PCH Sata Rst Raid Alternate Id +/** Offset 0x0A38 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. $EN_DIS **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x0AF3 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x0AF4 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x0AF5 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x0AF6 - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x0AF7 - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x0AF8 - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x0AF9 - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x0AFA - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x0AFB - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0AFC - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0AFD - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0AFE - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x0A39 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x0B01 - PCH Sata Rst Pcie Storage Port +/** Offset 0x0A3C - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x0B04 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x0A3F - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x0B07 - UFS enable/disable +/** Offset 0x0A42 - UFS enable/disable PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x0B09 - IEH Mode +/** Offset 0x0A44 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable 0: Bypass, 1:Enable **/ UINT8 IehMode; -/** Offset 0x0B0A - PSF Tcc - Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency - by disable some psf power management features, 0: Disable, 1: Enable - $EN_DIS +/** Offset 0x0A45 - Reserved **/ - UINT8 PsfTccEnable; + UINT8 Reserved37; -/** Offset 0x0B0B - TCC Mode Default Flag - Variable to determine TCC mode default value, 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 TccModeInitFlag; - -/** Offset 0x0B0C - Tcc Tuning enable/disable - Tcc (Time Coordinated Computing) Tuning Enabled - $EN_DIS -**/ - UINT8 TccTuningEnable; - -/** Offset 0x0B0D -**/ - UINT8 UnusedUpdSpace43[3]; - -/** Offset 0x0B10 - Tcc BIOS Config File Base Address - Tcc (Time Coordinated Computing) TCC BIOS Config File Base Address -**/ - UINT32 TccBiosCfgBase; - -/** Offset 0x0B14 - Tcc BIOS Config File Size - Tcc (Time Coordinated Computing) TCC BIOS Config File Size -**/ - UINT32 TccBiosCfgSize; - -/** Offset 0x0B18 - Tcc Cache Config File Base Address - Tcc (Time Coordinated Computing) Cache Config File Base Address -**/ - UINT32 TccCacheCfgBase; - -/** Offset 0x0B1C - Tcc Cache Config File Size - Tcc (Time Coordinated Computing) Cache Config File Size -**/ - UINT32 TccCacheCfgSize; - -/** Offset 0x0B20 - Tcc Stream Buffer Config File Base Address - Tcc (Time Coordinated Computing) Stream Buffer Config File Base Address -**/ - UINT32 TccStreamCfgBase; - -/** Offset 0x0B24 - Tcc Stream Buffer Config File Size - Tcc (Time Coordinated Computing) Stream Buffer Config File Size -**/ - UINT32 TccStreamCfgSize; - -/** Offset 0x0B28 - Tcc PTCM Binary File Base Address - Tcc (Time Coordinated Computing) PTCM Binary File Base Address -**/ - UINT32 TccPtcmBinBase; - -/** Offset 0x0B2C - Tcc PTCM Binary File Size - Tcc (Time Coordinated Computing) PTCM Binary Config File Size -**/ - UINT32 TccPtcmBinSize; - -/** Offset 0x0B30 - Fusa Display Configuration - Fusa (Functional Safety) Enable Fusa Feature on Display, 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 DisplayFusaConfigEnable; - -/** Offset 0x0B31 - Fusa Graphics Configuration - Fusa (Functional Safety) Enable Fusa Feature on Graphics, 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 GraphicFusaConfigEnable; - -/** Offset 0x0B32 - Fusa Opio Configuration - Fusa (Functional Safety) Enable Fusa Feature on Opio, 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 OpioFusaConfigEnable; - -/** Offset 0x0B33 - Fusa Psf Configuration - Fusa (Functional Safety) Enable Fusa Feature on Psf, 0: Disable, 1: Enable - $EN_DIS -**/ - UINT8 PsfFusaConfigEnable; - -/** Offset 0x0B34 - Thermal Throttling Custimized T0Level Value +/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x0B36 - Thermal Throttling Custimized T1Level Value +/** Offset 0x0A48 - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x0B38 - Thermal Throttling Custimized T2Level Value +/** Offset 0x0A4A - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x0B3A - Enable The Thermal Throttle +/** Offset 0x0A4C - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x0B3B - PMSync State 13 +/** Offset 0x0A4D - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x0B3C - Thermal Throttle Lock +/** Offset 0x0A4E - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x0B3D - Thermal Throttling Suggested Setting +/** Offset 0x0A4F - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x0B3E - Enable PCH Cross Throttling +/** Offset 0x0A50 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x0B3F - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x0A51 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x0B40 - DMI Thermal Sensor Suggested Setting +/** Offset 0x0A52 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x0B41 - Thermal Sensor 0 Target Width +/** Offset 0x0A53 - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x0B42 - Thermal Sensor 1 Target Width +/** Offset 0x0A54 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x0B43 - Thermal Sensor 2 Target Width +/** Offset 0x0A55 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x0B44 - Thermal Sensor 3 Target Width +/** Offset 0x0A56 - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x0B45 - Port 0 T1 Multipler +/** Offset 0x0A57 - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x0B46 - Port 0 T2 Multipler +/** Offset 0x0A58 - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x0B47 - Port 0 T3 Multipler +/** Offset 0x0A59 - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x0B48 - Port 0 Tdispatch +/** Offset 0x0A5A - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x0B49 - Port 1 T1 Multipler +/** Offset 0x0A5B - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x0B4A - Port 1 T2 Multipler +/** Offset 0x0A5C - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x0B4B - Port 1 T3 Multipler +/** Offset 0x0A5D - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x0B4C - Port 1 Tdispatch +/** Offset 0x0A5E - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x0B4D - Port 0 Tinactive +/** Offset 0x0A5F - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x0B4E - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x0A60 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x0B4F - Port 1 Tinactive +/** Offset 0x0A61 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x0B50 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x0A62 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x0B51 - Sata Thermal Throttling Suggested Setting +/** Offset 0x0A63 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x0B52 - Enable Memory Thermal Throttling +/** Offset 0x0A64 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x0B53 - Memory Thermal Throttling +/** Offset 0x0A65 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x0B55 - Enable Memory Thermal Throttling +/** Offset 0x0A67 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x0B57 - Enable Memory Thermal Throttling +/** Offset 0x0A69 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x0B59 +/** Offset 0x0A6B - Reserved **/ - UINT8 UnusedUpdSpace44; + UINT8 Reserved38; -/** Offset 0x0B5A - Thermal Device Temperature +/** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x0B5C - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x0B5D - USB2 Port Over Current Pin +/** Offset 0x0A6E - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0B6D - USB3 Port Over Current Pin +/** Offset 0x0A7E - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0B77 - Enable xHCI LTR override +/** Offset 0x0A88 - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x0B78 - USB Clock Gating Enable - Enable or disable USB clock gating - $EN_DIS +/** Offset 0x0A89 - Reserved **/ - UINT8 UsbClockGatingEnable; + UINT8 Reserved39[3]; -/** Offset 0x0B79 - USB Power Gating Enable - Enable or disable USB power gating - $EN_DIS -**/ - UINT8 UsbPowerGatingEnable; - -/** Offset 0x0B7A - USB3 LINK SPEED - Set USB3 LINK SPEED=0 for GEN2, Set USB3 LINK SPEED=1 for GEN1 -**/ - UINT8 USB3LinkSpeed; - -/** Offset 0x0B7B -**/ - UINT8 UnusedUpdSpace45; - -/** Offset 0x0B7C - xHCI High Idle Time LTR override +/** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x0B80 - xHCI Medium Idle Time LTR override +/** Offset 0x0A90 - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x0B84 - xHCI Low Idle Time LTR override +/** Offset 0x0A94 - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x0B88 - Enable 8254 Static Clock Gating +/** Offset 0x0A98 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -3292,7 +2450,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x0B89 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A99 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -3300,19 +2458,7 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0B8A - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x0B8B - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x0B8C - Enable TCO timer. +/** Offset 0x0A9A - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -3320,104 +2466,101 @@ typedef struct { **/ UINT8 EnableTcoTimer; -/** Offset 0x0B8D - Enable Timed GPIO 0. - When FALSE, it disables Timed GPIO 0. - $EN_DIS +/** Offset 0x0A9B - Hybrid Storage Detection and Configuration Mode + Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. + Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration **/ - UINT8 EnableTimedGpio0; + UINT8 HybridStorageMode; -/** Offset 0x0B8E - Enable Timed GPIO 1. - When FALSE, it disables Timed GPIO 1. - $EN_DIS +/** Offset 0x0A9C - Reserved **/ - UINT8 EnableTimedGpio1; + UINT8 Reserved40[4]; -/** Offset 0x0B8F - Enable VNN Voltage Raise. - When TRUE, it enable VNN Voltage Raise. - $EN_DIS -**/ - UINT8 EnableVnnVoltageRaise; - -/** Offset 0x0B90 - BgpdtHash[4] +/** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0BB0 - BiosGuardAttr +/** Offset 0x0AC0 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x0BB4 +/** Offset 0x0AC4 - Reserved **/ - UINT8 UnusedUpdSpace46[4]; + UINT8 Reserved41[4]; -/** Offset 0x0BB8 - BiosGuardModulePtr +/** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0BC0 - SendEcCmd +/** Offset 0x0AD0 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0BC8 - EcCmdProvisionEav +/** Offset 0x0AD8 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0BC9 - EcCmdLock +/** Offset 0x0AD9 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x0BCA - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x0BCB - Skip Ssid Programming. +/** Offset 0x0ADA - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. $EN_DIS **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x0BCC - Change Default SVID +/** Offset 0x0ADB - Reserved +**/ + UINT8 Reserved42; + +/** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSvid; -/** Offset 0x0BCE - Change Default SSID +/** Offset 0x0ADE - Change Default SSID Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSsid; -/** Offset 0x0BD0 - SVID SDID table Poniter. +/** Offset 0x0AE0 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT32 SiSsidTablePtr; -/** Offset 0x0BD4 - Number of ssid table. +/** Offset 0x0AE4 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x0BD6 - SATA RST Interrupt Mode +/** Offset 0x0AE6 - USB2 Port Reset Message Enable + 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must + be enable for USB2 Port those are paired with CPU XHCI Port +**/ + UINT8 PortResetMessageEnable[16]; + +/** Offset 0x0AF6 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x0BD7 - ME Unconfig on RTC clear +/** Offset 0x0AF7 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -3425,7 +2568,13 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0BD8 - Enable PS_ON. +/** Offset 0x0AF8 - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x0AF9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -3433,167 +2582,142 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0BD9 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x0AFA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x0BDA - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig +/** Offset 0x0AFB - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmL1 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x0BDB - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default +/** Offset 0x0AFC - PchDmiCwbEnable + Central Write Buffer feature configurable and enabled by default $EN_DIS **/ UINT8 PchDmiCwbEnable; -/** Offset 0x0BDC - OS IDLE Mode Enable +/** Offset 0x0AFD - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x0BDD - S0ix Auto-Demotion +/** Offset 0x0AFE - S0ix Auto-Demotion Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. $EN_DIS **/ UINT8 PchS0ixAutoDemotion; -/** Offset 0x0BDE - Global Reset TSC Enable - Enable/Disable PMC Global Reset Three Strike Counter feature. If enabled, PMC will - keep the platform in S5 after the third consecutive type 7 global reset occurs - during boot flow - $EN_DIS -**/ - UINT8 PmcGrTscEnable; - -/** Offset 0x0BDF - Latch Events C10 Exit +/** Offset 0x0AFF - Latch Events C10 Exit When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) $EN_DIS **/ UINT8 PchPmLatchEventsC10Exit; -/** Offset 0x0BE0 - PCIE Eq Ph3 Lane Param Cm +/** Offset 0x0B00 - Reserved +**/ + UINT8 Reserved43[12]; + +/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. **/ UINT8 CpuPcieEqPh3LaneParamCm[32]; -/** Offset 0x0C00 - PCIE Eq Ph3 Lane Param Cp +/** Offset 0x0B2C - PCIE Eq Ph3 Lane Param Cp CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. **/ UINT8 CpuPcieEqPh3LaneParamCp[32]; -/** Offset 0x0C20 - PCIE Hw Eq Gen3 CoeffList Cm - CPU_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 CpuPcieHwEqGen3CoeffListCm[5]; - -/** Offset 0x0C25 - PCIE Hw Eq Gen3 CoeffList Cp - CPU_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 CpuPcieHwEqGen3CoeffListCp[5]; - -/** Offset 0x0C2A - PCIE Hw Eq Gen4 CoeffList Cm - CPU_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 CpuPcieHwEqGen4CoeffListCm[5]; - -/** Offset 0x0C2F - PCIE Hw Eq Gen4 CoeffList Cp - CPU_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 CpuPcieHwEqGen4CoeffListCp[5]; - -/** Offset 0x0C34 - Gen3 Root port preset values per lane +/** Offset 0x0B4C - Gen3 Root port preset values per lane Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 CpuPcieGen3RootPortPreset[20]; -/** Offset 0x0C48 - Pcie Gen4 Root port preset values per lane +/** Offset 0x0B60 - Pcie Gen4 Root port preset values per lane Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 CpuPcieGen4RootPortPreset[20]; -/** Offset 0x0C5C - Pcie Gen3 End port preset values per lane +/** Offset 0x0B74 - Pcie Gen3 End port preset values per lane Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 CpuPcieGen3EndPointPreset[20]; -/** Offset 0x0C70 - Pcie Gen4 End port preset values per lane +/** Offset 0x0B88 - Pcie Gen4 End port preset values per lane Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 CpuPcieGen4EndPointPreset[20]; -/** Offset 0x0C84 - Pcie Gen3 End port Hint values per lane +/** Offset 0x0B9C - Pcie Gen3 End port Hint values per lane Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 CpuPcieGen3EndPointHint[20]; -/** Offset 0x0C98 - Pcie Gen4 End port Hint values per lane +/** Offset 0x0BB0 - Pcie Gen4 End port Hint values per lane Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 CpuPcieGen4EndPointHint[20]; -/** Offset 0x0CAC - Skip Cpu Fia Programming - Skip Fia configuration and lock if enable. 0: Disable; 1: Enable. +/** Offset 0x0BC4 - CPU PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). $EN_DIS **/ - UINT8 CpuPcieSkipCpuFiaProgramming; + UINT8 CpuPcieFiaProgramming; -/** Offset 0x0CAD - PCIE Disable RootPort Clock Gating +/** Offset 0x0BC5 - CPU PCIe RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. + platform modules. 0: Disable; 1: Enable(Default). $EN_DIS **/ - UINT8 CpuPcieDisableRootPortClockGating; + UINT8 CpuPcieClockGating[4]; -/** Offset 0x0CAE - PCIE Disable RootPort Power Gating +/** Offset 0x0BC9 - CPU PCIe RootPort Power Gating Describes whether the PCI Express Power Gating for each root port is enabled by - platform modules. 0: Disable; 1: Enable. + platform modules. 0: Disable; 1: Enable(Default). $EN_DIS **/ - UINT8 CpuPcieDisableRootPortPowerGating; + UINT8 CpuPciePowerGating[4]; -/** Offset 0x0CAF - PCIE Compliance Test Mode +/** Offset 0x0BCD - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 CpuPcieComplianceTestMode; -/** Offset 0x0CB0 - PCIE Secure Register Lock - Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, - load CpuPcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable - $EN_DIS -**/ - UINT8 CpuPcieSetSecuredRegisterLock; - -/** Offset 0x0CB1 - PCIE Enable Peer Memory Write +/** Offset 0x0BCE - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 CpuPcieEnablePeerMemoryWrite; -/** Offset 0x0CB2 - PCIE Rp Function Swap +/** Offset 0x0BCF - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 CpuPcieRpFunctionSwap; -/** Offset 0x0CB3 +/** Offset 0x0BD0 - PCI Express Slot Selection + Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default). + $EN_DIS **/ - UINT8 UnusedUpdSpace47; + UINT8 CpuPcieSlotSelection; -/** Offset 0x0CB4 - Pch PCIE device override table pointer +/** Offset 0x0BD1 - Reserved +**/ + UINT8 Reserved44[3]; + +/** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -3601,296 +2725,233 @@ typedef struct { **/ UINT32 CpuPcieDeviceOverrideTablePtr; -/** Offset 0x0CB8 - Enable PCIE RP HotPlug +/** Offset 0x0BD8 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 CpuPcieRpHotPlug[4]; -/** Offset 0x0CBC - Enable PCIE RP Pm Sci +/** Offset 0x0BDC - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 CpuPcieRpPmSci[4]; -/** Offset 0x0CC0 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x0BE0 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 CpuPcieRpTransmitterHalfSwing[4]; -/** Offset 0x0CC4 - PCIE RP Access Control Services Extended Capability +/** Offset 0x0BE4 - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 CpuPcieRpAcsEnabled[4]; -/** Offset 0x0CC8 - PCIE RP Clock Power Management +/** Offset 0x0BE8 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 CpuPcieRpEnableCpm[4]; -/** Offset 0x0CCC - PCIE RP Advanced Error Report +/** Offset 0x0BEC - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 CpuPcieRpAdvancedErrorReporting[4]; -/** Offset 0x0CD0 - PCIE RP Unsupported Request Report +/** Offset 0x0BF0 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 CpuPcieRpUnsupportedRequestReport[4]; -/** Offset 0x0CD4 - PCIE RP Fatal Error Report +/** Offset 0x0BF4 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 CpuPcieRpFatalErrorReport[4]; -/** Offset 0x0CD8 - PCIE RP No Fatal Error Report +/** Offset 0x0BF8 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 CpuPcieRpNoFatalErrorReport[4]; -/** Offset 0x0CDC - PCIE RP Correctable Error Report +/** Offset 0x0BFC - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 CpuPcieRpCorrectableErrorReport[4]; -/** Offset 0x0CE0 - PCIE RP System Error On Fatal Error +/** Offset 0x0C00 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnFatalError[4]; -/** Offset 0x0CE4 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0C04 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; -/** Offset 0x0CE8 - PCIE RP System Error On Correctable Error +/** Offset 0x0C08 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; -/** Offset 0x0CEC - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +/** Offset 0x0C0C - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD. **/ UINT8 CpuPcieRpMaxPayload[4]; -/** Offset 0x0CF0 - DPC for PCIE RP Mask +/** Offset 0x0C10 - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpDpcEnabled[4]; -/** Offset 0x0CF4 - DPC Extensions PCIE RP Mask +/** Offset 0x0C14 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpDpcExtensionsEnabled[4]; -/** Offset 0x0CF8 - PCH PCIe root port connection type +/** Offset 0x0C18 - CPU PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 CpuPcieRpSlotImplemented[4]; -/** Offset 0x0CFC - PCIE RP Gen3 Equalization Phase Method +/** Offset 0x0C1C - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 CpuPcieRpGen3EqPh3Method[4]; -/** Offset 0x0D00 - PCIE RP Gen4 Equalization Phase Method +/** Offset 0x0C20 - PCIE RP Gen4 Equalization Phase Method PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 CpuPcieRpGen4EqPh3Method[4]; -/** Offset 0x0D04 - Phase3 RP Gen3 EQ enable - Phase3 Gen3 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase - 3, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 CpuPcieRpGen3EqPh3Enable[4]; - -/** Offset 0x0D08 - Phase3 RP Gen4 EQ enable - Phase3 Gen4 EQ enable. Disabled(0x0): Disable phase 3, Enabled(0x1): Enable phase - 3, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 CpuPcieRpGen4EqPh3Enable[4]; - -/** Offset 0x0D0C - Phase2-3 RP Gen3 EQ enable - Phase2-3 Gen3 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3, - Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 CpuPcieRpGen3EqPh23Enable[4]; - -/** Offset 0x0D10 - Phase2-3 RP Gen4 EQ enable - Phase2-3 Gen4 EQ enable. Disabled(0x0): Disable Phase2-3, Enabled(0x1): Enable Phase2-3, - Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 CpuPcieRpGen4EqPh23Enable[4]; - -/** Offset 0x0D14 - PCET Timer - Preset/Coefficient Evaluation Timeout. See CPU_PCIE_PCET. Default is 0x4 -**/ - UINT8 CpuPciePcetTimer[4]; - -/** Offset 0x0D18 - Gen3 Preset/Coeffiecient List Count - Select Gen3 Hardware Autonomous Preset/Coefficient Count. See Gen3 CPU_PCIE_PRESETCOEFF_LIST. - Default is 0x3 -**/ - UINT8 Gen3CpuPciePresetCoeffList[4]; - -/** Offset 0x0D1C - Gen4 Preset/Coeffiecient List Count - Select Gen4 Hardware Autonomous Preset/Coefficient Count. See CPU_PCIE_PRESETCOEFF_LIST. - Default is 0x3 -**/ - UINT8 Gen4CpuPciePresetCoeffList[4]; - -/** Offset 0x0D20 - Presets/Coefficients Evaluation for Gen3 - 8.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See - CPU_PCIE_PX8GTSWLPCE. Default is 0x3 -**/ - UINT8 CpuPciePx8gtswlpce[4]; - -/** Offset 0x0D24 - Presets/Coefficients Evaluation for Gen4 - 16.0GT/s Training Sequence Wait Latency For Presets/Coefficients Evaluation. See - CPU_PCIE_PX16GTSWLPCE. Default is 0x4 -**/ - UINT8 CpuPciePx16gtswlpce[4]; - -/** Offset 0x0D28 - PCIE RP Physical Slot Number +/** Offset 0x0C24 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 CpuPcieRpPhysicalSlotNumber[4]; -/** Offset 0x0D2C - PCIE RP Aspm - The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is - CpuPcieAspmAutoConfig. +/** Offset 0x0C28 - PCIE RP Aspm + The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; + 1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default) **/ UINT8 CpuPcieRpAspm[4]; -/** Offset 0x0D30 - PCIE RP L1 Substates +/** Offset 0x0C2C - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). - Default is CpuPcieL1SubstatesDisabled. + Default is CpuPcieL1SubstatesL1_1_2. **/ UINT8 CpuPcieRpL1Substates[4]; -/** Offset 0x0D34 - PCIE RP Ltr Enable +/** Offset 0x0C30 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 CpuPcieRpLtrEnable[4]; -/** Offset 0x0D38 - PCIE RP Ltr Config Lock +/** Offset 0x0C34 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 CpuPcieRpLtrConfigLock[4]; -/** Offset 0x0D3C - PTM for PCIE RP Mask +/** Offset 0x0C38 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpPtmEnabled[4]; -/** Offset 0x0D40 - PCIE RP Detect Timeout Ms +/** Offset 0x0C3C - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 CpuPcieRpDetectTimeoutMs[4]; -/** Offset 0x0D48 - VC for PCIE RP Mask - Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. +/** Offset 0x0C44 - Multi-VC for PCIE RP Mask + Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ - UINT8 CpuPcieRpVcEnabled[4]; + UINT8 CpuPcieRpMultiVcEnabled[4]; -/** Offset 0x0D4C - Force GT CLOS on LLC for Real Time Performance - 0(Default)=Disable, 1=Enable - $EN_DIS -**/ - UINT8 GtClosEnable; - -/** Offset 0x0D4D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x0C48 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x0D57 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x0C52 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x0D61 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x0C5C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x0D6B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x0C66 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x0D75 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x0C70 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x0D7F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x0C7A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x0D89 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x0C84 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x0D93 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x0C8E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x0D9D - Skip PAM regsiter lock +/** Offset 0x0C98 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x0D9E - EDRAM Test Mode +/** Offset 0x0C99 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x0D9F - Enable/Disable IGFX RenderStandby +/** Offset 0x0C9A - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x0DA0 - Enable/Disable IGFX PmSupport +/** Offset 0x0C9B - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0DA1 - Enable/Disable CdynmaxClamp +/** Offset 0x0C9C - Enable/Disable CdynmaxClamp Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x0DA2 - GT Frequency Limit +/** Offset 0x0C9D - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -3904,127 +2965,113 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x0DA3 - Disable Turbo GT +/** Offset 0x0C9E - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x0DA4 - Enable/Disable CdClock Init +/** Offset 0x0C9F - Enable/Disable CdClock Init Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock if not initialized by Gfx PEIM $EN_DIS **/ UINT8 SkipCdClockInit; -/** Offset 0x0DA5 +/** Offset 0x0CA0 - Enable RC1p frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS **/ - UINT8 UnusedUpdSpace48[3]; + UINT8 RC1pFreqEnable; -/** Offset 0x0DA8 - LogoPixelHeight Address +/** Offset 0x0CA1 - Enable TSN Multi-VC + Enable/disable Multi Virtual Channels(VC) in TSN. + $EN_DIS +**/ + UINT8 PchTsnMultiVcEnable; + +/** Offset 0x0CA2 - Reserved +**/ + UINT8 Reserved45[2]; + +/** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight **/ UINT32 LogoPixelHeight; -/** Offset 0x0DAC - LogoPixelWidth Address +/** Offset 0x0CA8 - LogoPixelWidth Address Address of LogoPixelWidth **/ UINT32 LogoPixelWidth; -/** Offset 0x0DB0 - SaPostMemTestRsvd - Reserved for SA Post-Mem Test - $EN_DIS +/** Offset 0x0CAC - Reserved **/ - UINT8 SaPostMemTestRsvd[6]; + UINT8 Reserved46[5]; -/** Offset 0x0DB6 - RSR feature +/** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableRsr; -/** Offset 0x0DB7 - 1-Core Ratio Limit - 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal - to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 +/** Offset 0x0CB2 - Reserved **/ - UINT8 OneCoreRatioLimit; + UINT8 Reserved47[4]; -/** Offset 0x0DB8 - 2-Core Ratio Limit - 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x0DB9 - 3-Core Ratio Limit - 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x0DBA - 4-Core Ratio Limit - 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x0DBB - Enable or Disable HWP +/** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0DBC - Hardware Duty Cycle Control +/** Offset 0x0CB7 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x0DBD - Package Long duration turbo mode time +/** Offset 0x0CB8 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x0DBE - Short Duration Turbo Mode +/** Offset 0x0CB9 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x0DBF - Turbo settings Lock +/** Offset 0x0CBA - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0DC0 - Package PL3 time window +/** Offset 0x0CBB - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x0DC1 - Package PL3 Duty Cycle +/** Offset 0x0CBC - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x0DC2 - Package PL3 Lock +/** Offset 0x0CBD - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x0DC3 - Package PL4 Lock +/** Offset 0x0CBE - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x0DC4 - TCC Activation Offset +/** Offset 0x0CBF - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -4032,7 +3079,7 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0DC5 - Tcc Offset Clamp Enable/Disable +/** Offset 0x0CC0 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -4040,326 +3087,318 @@ typedef struct { **/ UINT8 TccOffsetClamp; -/** Offset 0x0DC6 - Tcc Offset Lock +/** Offset 0x0CC1 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x0DC7 - Custom Ratio State Entries +/** Offset 0x0CC2 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x0DC8 - Custom Short term Power Limit time window +/** Offset 0x0CC3 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x0DC9 - Custom Turbo Activation Ratio +/** Offset 0x0CC4 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x0DCA - Custom Config Tdp Control +/** Offset 0x0CC5 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x0DCB - Custom Short term Power Limit time window +/** Offset 0x0CC6 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x0DCC - Custom Turbo Activation Ratio +/** Offset 0x0CC7 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x0DCD - Custom Config Tdp Control +/** Offset 0x0CC8 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x0DCE - Custom Short term Power Limit time window +/** Offset 0x0CC9 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x0DCF - Custom Turbo Activation Ratio +/** Offset 0x0CCA - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x0DD0 - Custom Config Tdp Control +/** Offset 0x0CCB - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x0DD1 - ConfigTdp mode settings Lock +/** Offset 0x0CCC - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x0DD2 - Load Configurable TDP SSDT +/** Offset 0x0CCD - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x0DD3 - PL1 Enable value +/** Offset 0x0CCE - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x0DD4 - PL1 timewindow +/** Offset 0x0CCF - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x0DD5 - PL2 Enable Value +/** Offset 0x0CD0 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x0DD6 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0CD1 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0DD7 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0CD2 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0DD8 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0CD3 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0DD9 - Enable or Disable initialization of machine check registers +/** Offset 0x0CD4 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0DDA - Check if FUSA is supported - Check if FUSA is supported; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 IsFusaSupported; - -/** Offset 0x0DDB - AP Idle Manner of waiting for SIPI +/** Offset 0x0CD5 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x0DDC - Control on Processor Trace output scheme +/** Offset 0x0CD6 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0DDD - Enable or Disable Processor Trace feature +/** Offset 0x0CD7 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0DDE - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0CD8 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x0DDF - Enable or Disable Energy Efficient P-state +/** Offset 0x0CD9 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x0DE0 - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable +/** Offset 0x0CDA - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0DE1 - Enable or Disable T states +/** Offset 0x0CDB - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0DE2 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0CDC - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x0DE3 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x0CDD - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x0DE4 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. +/** Offset 0x0CDE - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x0DE5 - Enable or Disable VR Thermal Alert +/** Offset 0x0CDF - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0DE6 - Enable or Disable Thermal Reporting +/** Offset 0x0CE0 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 EnableAllThermalFunctions; -/** Offset 0x0DE7 - Enable or Disable Thermal Monitor +/** Offset 0x0CE1 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x0DE8 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CE2 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0DE9 - Configure C-State Configuration Lock +/** Offset 0x0CE3 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0DEA - Enable or Disable Enhanced C-states +/** Offset 0x0CE4 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x0DEB - Enable or Disable Package Cstate Demotion +/** Offset 0x0CE5 - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x0DEC - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0CE6 - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x0DED - Enable or Disable CState-Pre wake +/** Offset 0x0CE7 - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x0DEE - Enable or Disable TimedMwait Support. +/** Offset 0x0CE8 - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x0DEF - Enable or Disable IO to MWAIT redirection +/** Offset 0x0CE9 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x0DF0 - Set the Max Pkg Cstate +/** Offset 0x0CEA - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0DF1 - TimeUnit for C-State Latency Control0 +/** Offset 0x0CEB - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0DF2 - TimeUnit for C-State Latency Control1 +/** Offset 0x0CEC - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x0DF3 - TimeUnit for C-State Latency Control2 +/** Offset 0x0CED - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x0DF4 - TimeUnit for C-State Latency Control3 +/** Offset 0x0CEE - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x0DF5 - TimeUnit for C-State Latency Control4 +/** Offset 0x0CEF - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x0DF6 - TimeUnit for C-State Latency Control5 +/** Offset 0x0CF0 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x0DF7 - Interrupt Redirection Mode Select +/** Offset 0x0CF1 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x0DF8 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable +/** Offset 0x0CF2 - Lock prochot configuration + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0DF9 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate +/** Offset 0x0CF3 - Configuration for boot TDP selection + Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; -/** Offset 0x0DFA - Max P-State Ratio +/** Offset 0x0CF4 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0DFB - P-state ratios for custom P-state table +/** Offset 0x0CF5 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0E23 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0D1D - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -4368,125 +3407,129 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0E33 +/** Offset 0x0D2D - Reserved **/ - UINT8 UnusedUpdSpace49; + UINT8 Reserved48; -/** Offset 0x0E34 - Platform Power Pmax +/** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0E36 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0D30 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x0E38 - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0D32 - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x0E3A - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0D34 - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x0E3C - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0D36 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0E3E - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0E40 - Package Long duration turbo mode power limit +/** Offset 0x0D3A - Reserved +**/ + UINT8 Reserved49[2]; + +/** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0E44 - Package Short duration turbo mode power limit +/** Offset 0x0D40 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x0E48 - Package PL3 power limit +/** Offset 0x0D44 - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0E4C - Package PL4 power limit +/** Offset 0x0D48 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0E50 - Tcc Offset Time Window for RATL +/** Offset 0x0D4C - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0E54 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0D50 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x0E58 - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0D54 - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0E5C - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0E60 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0E64 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x0E68 - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0E6C - Platform PL1 power +/** Offset 0x0D68 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0E70 - Platform PL2 power +/** Offset 0x0D6C - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0E74 - Race To Halt +/** Offset 0x0D70 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -4494,373 +3537,399 @@ typedef struct { **/ UINT8 RaceToHalt; -/** Offset 0x0E75 - Set Three Strike Counter Disable +/** Offset 0x0D71 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0E76 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x0D72 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x0E77 - 5-Core Ratio Limit - 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF +/** Offset 0x0D73 - Reserved **/ - UINT8 FiveCoreRatioLimit; + UINT8 Reserved50[4]; -/** Offset 0x0E78 - 6-Core Ratio Limit - 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x0E79 - 7-Core Ratio Limit - 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x0E7A - 8-Core Ratio Limit - 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x0E7B - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x0E7C - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x0E7D - Enable or Disable C1 Cstate Demotion +/** Offset 0x0D78 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0E7E - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0D79 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0E7F - Minimum Ring ratio limit override +/** Offset 0x0D7A - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0E80 - Maximum Ring ratio limit override +/** Offset 0x0D7B - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0E81 - Enable or Disable Per Core P State OS control +/** Offset 0x0D7C - Enable or Disable Per Core P State OS control Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnablePerCorePState; -/** Offset 0x0E82 - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x0D7D - Enable or Disable HwP Autonomous Per Core P State OS control Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x0E83 - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x0D7E - Enable or Disable HwP Autonomous EPP Grouping Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x0E84 - Enable or Disable EPB override over PECI +/** Offset 0x0D7F - Enable or Disable EPB override over PECI Enable or Disable EPB override over PECI. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableEpbPeciOverride; -/** Offset 0x0E85 - Enable or Disable Fast MSR for IA32_HWP_REQUEST +/** Offset 0x0D80 - Enable or Disable Fast MSR for IA32_HWP_REQUEST Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableFastMsrHwpReq; -/** Offset 0x0E86 - Enable Configurable TDP +/** Offset 0x0D81 - Enable Configurable TDP Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; 1: Applies to cTDP $EN_DIS **/ UINT8 ApplyConfigTdp; -/** Offset 0x0E87 - ReservedCpuPostMemTest - Reserved for CPU Post-Mem Test +/** Offset 0x0D82 - Reserved +**/ + UINT8 Reserved51; + +/** Offset 0x0D83 - Dual Tau Boost + Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: + Disable; 1: Enable $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[16]; + UINT8 DualTauBoost; -/** Offset 0x0E97 +/** Offset 0x0D84 - Reserved **/ - UINT8 SecurityPostMemRsvd[16]; + UINT8 Reserved52[32]; -/** Offset 0x0EA7 - D0I3 Setting for HECI Disable +/** Offset 0x0DA4 - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x0DA5 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x0EA8 - Enable LOCKDOWN SMI +/** Offset 0x0DA6 - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x0DA7 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0EA9 - Enable LOCKDOWN BIOS Interface +/** Offset 0x0DA8 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0EAA - Unlock all GPIO pads +/** Offset 0x0DA9 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0EAB - PCH Unlock SideBand access +/** Offset 0x0DAA - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x0EAC - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0DAB - Reserved +**/ + UINT8 Reserved53; + +/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; + UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0EDC - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DE4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0F0C - PCIE RP Snoop Latency Override Mode +/** Offset 0x0E1C - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; + UINT8 PcieRpSnoopLatencyOverrideMode[28]; -/** Offset 0x0F24 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0E38 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; + UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0F3C - PCIE RP Snoop Latency Override Value +/** Offset 0x0E54 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; + UINT16 PcieRpSnoopLatencyOverrideValue[28]; -/** Offset 0x0F6C - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0E8C - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; + UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; -/** Offset 0x0F84 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0EA8 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0F9C - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0EC4 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; + UINT16 PcieRpNonSnoopLatencyOverrideValue[28]; -/** Offset 0x0FCC - PCIE RP Slot Power Limit Scale +/** Offset 0x0EFC - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ - UINT8 PcieRpSlotPowerLimitScale[24]; + UINT8 PcieRpSlotPowerLimitScale[28]; -/** Offset 0x0FE4 - PCIE RP Slot Power Limit Value +/** Offset 0x0F18 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ - UINT16 PcieRpSlotPowerLimitValue[24]; + UINT16 PcieRpSlotPowerLimitValue[28]; -/** Offset 0x1014 - PCIE RP Enable Port8xh Decode +/** Offset 0x0F50 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x1015 - PCIE Port8xh Decode Port Index +/** Offset 0x0F51 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x1016 - PCH Energy Reporting +/** Offset 0x0F52 - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x1017 - PCH Sata Test Mode +/** Offset 0x0F53 - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x1018 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0F54 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x1019 - Low Power Mode Enable/Disable config mask +/** Offset 0x0F55 - Low Power Mode Enable/Disable config mask Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ UINT8 PmcLpmS0ixSubStateEnableMask; -/** Offset 0x101A - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x101B -**/ - UINT8 UnusedUpdSpace50[1]; - -/** Offset 0x101C - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; -/** Offset 0x1024 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0F5E - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; -/** Offset 0x102C - PCIE RP Snoop Latency Override Mode +/** Offset 0x0F66 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; -/** Offset 0x1030 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0F6A - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x1034 - PCIE RP Snoop Latency Override Value +/** Offset 0x0F6E - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; -/** Offset 0x103C - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0F76 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x1040 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0F7A - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x1044 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x104C - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0F86 - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 CpuPcieRpGen3Uptp[4]; -/** Offset 0x1050 - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0F8A - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 CpuPcieRpGen3Dptp[4]; -/** Offset 0x1054 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 8. **/ UINT8 CpuPcieRpGen4Uptp[4]; -/** Offset 0x1058 - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 9. **/ UINT8 CpuPcieRpGen4Dptp[4]; -/** Offset 0x105C - Enable PSE JTAG debug option - Set if to enable JTAG debug feature for PSE. 0: Disable; 1: Enable. +/** Offset 0x0F96 - Reserved **/ - UINT8 PchPseJtagEnabled; + UINT8 Reserved54[16]; -/** Offset 0x105D - Enable PSE JTAG pin option - This option is used to enable or disable PSE JTAG pin pad mode. 0: Disable; 1: Enable. +/** Offset 0x0FA6 - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms **/ - UINT8 PchPseJtagPinMux; + UINT8 CpuPcieFomsCp[4]; -/** Offset 0x105E - Enable PSE SHELL option - Set if to enable PSE Shell feature. 0: Disable; 1: Enable. +/** Offset 0x0FAA - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS **/ - UINT8 PchPseShellEnabled; + UINT8 PmcC10DynamicThresholdAdjustment; -/** Offset 0x105F - Enable PSE ECLITE option - Set if to enable PSE Eclite feature. 0: Disable; 1: Enable. +/** Offset 0x0FAB - P2P mode for PCIE RP + Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable. + 0: Disable, 1: Enable **/ - UINT8 PchPseEcliteEnabled; + UINT8 CpuPcieRpPeerToPeerMode[4]; -/** Offset 0x1060 - Enable PSE OOB option - Set if to enable PSE OOB feature. 0: Disable; 1: Enable. +/** Offset 0x0FAF - Reserved **/ - UINT8 PchPseOobEnabled; + UINT8 Reserved55[33]; -/** Offset 0x1061 - Enable CPU Temperature Read - Set to enable CPU Temperature Read feature. 0: Disable; 1: Enable. +/** Offset 0x0FD0 - FspEventHandler + Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. **/ - UINT8 PchCpuTempSensorEnable; + UINT32 FspEventHandler; -/** Offset 0x1062 - Enable PSE WoL option - Set if to enable PSE WoL feature. 0: Disable; 1: Enable. +/** Offset 0x0FD4 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS **/ - UINT8 PchPseWoLEnabled; + UINT8 ScsEmmcEnabled; -/** Offset 0x1063 - Enable PSE AIC SPI1 option - Set if to enable PSE AIC SPI1. 0: Disable; 1: Enable. +/** Offset 0x0FD5 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS **/ - UINT8 PchPseAicEnabled; + UINT8 ScsEmmcHs400Enabled; -/** Offset 0x1064 - Enable LPSS Device D3 state - Enable LPSS Device D3 state. 0: Disable; 1: Enable. +/** Offset 0x0FD6 - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS **/ - UINT8 SerialIoLpssD3; + UINT8 EmmcUseCustomDlls; -/** Offset 0x1065 +/** Offset 0x0FD7 - Reserved **/ - UINT8 ReservedFspsUpd[3]; + UINT8 Reserved56; + +/** Offset 0x0FD8 - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x0FDC - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x0FE0 - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x0FE4 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x0FE8 - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x0FEC - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x0FF0 - Reserved +**/ + UINT8 Reserved57[69]; + +/** Offset 0x1035 - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable; 1: Enable(Default) + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x1036 - Reserved +**/ + UINT8 Reserved58[122]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -4872,14 +3941,18 @@ typedef struct { FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 +**/ + FSPS_ARCH_UPD FspsArchUpd; + +/** Offset 0x0040 **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1068 +/** Offset 0x10B0 **/ - UINT8 UnusedUpdSpace51[6]; + UINT8 UnusedUpdSpace45[6]; -/** Offset 0x106E +/** Offset 0x10B6 **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h similarity index 68% rename from src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h rename to src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h index 30d61e60b0..73a8d29cfe 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h @@ -4,7 +4,7 @@ data hobs. @copyright - Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -18,9 +18,6 @@ #ifndef _MEM_INFO_HOB_H_ #define _MEM_INFO_HOB_H_ -#include -#include -#include #pragma pack (push, 1) @@ -28,11 +25,12 @@ extern EFI_GUID gSiMemoryS3DataGuid; extern EFI_GUID gSiMemoryInfoDataGuid; extern EFI_GUID gSiMemoryPlatformDataGuid; -#define MAX_TRACE_CACHE_TYPE 3 - -#define MAX_NODE 1 -#define MAX_CH 2 +#define MAX_NODE 2 +#define MAX_CH 4 #define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 /// /// Host reset states from MRC. @@ -45,6 +43,25 @@ extern EFI_GUID gSiMemoryPlatformDataGuid; #define B_RANK2_PRS BIT4 #define B_RANK3_PRS BIT5 +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + /// /// Defines taken from MRC so avoid having to include MrcInterface.h /// @@ -66,6 +83,19 @@ typedef struct { UINT8 Build; ///< Build number } SiMrcVersion; +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + // // Matches MrcDimmSts enum in MRC // @@ -103,21 +133,24 @@ typedef enum { // // Matches MrcDdrType enum in MRC // -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 #endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 #endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 #endif #ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 +#define MRC_DDR_TYPE_UNKNOWN 4 #endif -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 // // DIMM timings @@ -147,6 +180,10 @@ typedef struct { UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. } MRC_CH_TIMING; +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + /// /// Memory SMBIOS & OC Memory Data Hob /// @@ -189,6 +226,20 @@ typedef struct { UINT8 Rsvd[2]; } PSMI_MEM_INFO; +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + typedef struct { UINT8 Revision; UINT16 DataWidth; ///< Data width, in bits, of this memory device @@ -206,13 +257,32 @@ typedef struct { SiMrcVersion Version; BOOLEAN EccSupport; UINT8 MemoryProfile; + UINT8 IsDMBRunning; ///< Deprecated. UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; + /// + /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. + /// Bit 0: XMP Profile 1 capability status + /// Bit 1: XMP Profile 2 capability status + /// Bit 2: XMP Profile 3 capability status + /// Bit 3: User Profile 4 capability status + /// Bit 4: User Profile 5 capability status + /// + UINT8 XmpProfileEnable; + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; + UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population + BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. } MEMORY_INFO_DATA_HOB; /** @@ -231,14 +301,12 @@ typedef struct { UINT32 TsegBase; UINT32 PrmrrSize; UINT64 PrmrrBase; - UINT32 PramSize; - UINT64 PramBase; - UINT64 DismLimit; - UINT64 DismBase; UINT32 GttBase; UINT32 MmioSize; UINT32 PciEBaseAddress; PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; } MEMORY_PLATFORM_DATA; typedef struct { diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h deleted file mode 100644 index af987bbdd8..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FspmUpd.h +++ /dev/null @@ -1,3042 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0048 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x004A - Enable above 4GB MMIO resource support - Enable/disable above 4GB MMIO resource support - $EN_DIS -**/ - UINT8 EnableAbove4GBMmio; - -/** Offset 0x004B - Enable/Disable CrashLog Device 10 - Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog - $EN_DIS -**/ - UINT8 CpuCrashLogDevice; - -/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x005C - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0068 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x007C - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x0084 - RcompResister settings - Indicates RcompReister settings: Board-dependent -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x008A - RcompTarget settings - RcompTarget settings: board-dependent -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x0094 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x0095 - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x0096 - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x0097 - LPDDR4 Write DQ/DQS Retraining - Enables/Disable LPDDR4 Write DQ/DQS Retraining - $EN_DIS -**/ - UINT8 Lp4DqsOscEn; - -/** Offset 0x0098 - Ibecc - Enables/Disable Ibecc - $EN_DIS -**/ - UINT8 Ibecc; - -/** Offset 0x0099 - IbeccParity - In-Band ECC Parity Control - $EN_DIS -**/ - UINT8 IbeccParity; - -/** Offset 0x009A - IbeccOperationMode - In-Band ECC Operation Mode - 0:Protect base on address range, 1: Non-protected, 2: All protected -**/ - UINT8 IbeccOperationMode; - -/** Offset 0x009B - IbeccErrorInj Note: Modification accepts the disclaimer shown in the Help text - Disclaimer: Warning: This must NOT be enabled for production!!! Enabling Error Injection - allows attackers who have access to the Host Operating System to inject IBECC errors - that can cause unintended memory corruption and enable the leak of security data - in the BIOS stolen memory regions. - $EN_DIS -**/ - UINT8 IbeccErrorInj; - -/** Offset 0x009C - IbeccProtectedRegionEnable - In-Band ECC Protected Region Enable - $EN_DIS -**/ - UINT8 IbeccProtectedRegionEnable[8]; - -/** Offset 0x00A4 - IbeccProtectedRegionBases - IBECC Protected Region Bases -**/ - UINT16 IbeccProtectedRegionBase[8]; - -/** Offset 0x00B4 - IbeccProtectedRegionMasks - IBECC Protected Region Masks -**/ - UINT16 IbeccProtectedRegionMask[8]; - -/** Offset 0x00C4 - MrcTaskDebugPrintEnable - Mrc Task Debug Print Enable. 0(Default)=Disable, non-Zero=Enable Task Debug print -**/ - UINT8 MrcTaskDebugEnable; - -/** Offset 0x00C5 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x00C6 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x00C7 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x00C8 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x00CC - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x00D0 - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x00D2 - LowSupplyEnData - Enable: Enable Low Supply for LPDDR4 Data, Disable(Default) - $EN_DIS -**/ - UINT8 LowSupplyEnData; - -/** Offset 0x00D3 - LowSupplyEnCcc - Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default) - $EN_DIS -**/ - UINT8 LowSupplyEnCcc; - -/** Offset 0x00D4 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x00D5 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00D6 - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x00D7 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x00DB - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options.\Manual: Do not use Platform Debug Consent to override other debug-relevant - policies, but the user must set each debug option manually, aimed at advanced users.\n - Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting. - 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), - 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x00DC - DCI Enable - Determine if to enable DCI debug from host - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x00DD - DCI DbC Mode - Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: - Set both USB2/3DBCEN; No Change: Comply with HW value - 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change -**/ - UINT8 DciDbcMode; - -/** Offset 0x00DE - Enable DCI ModPHY Pwoer Gate - Enable ModPHY Pwoer Gate when DCI is enabled - $EN_DIS -**/ - UINT8 DciModphyPg; - -/** Offset 0x00DF - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x00E0 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x00E1 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x00E2 - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x00E3 - PchPreMemRsvd - Reserved for PCH Pre-Mem Reserved - $EN_DIS -**/ - UINT8 PchPreMemRsvd[7]; - -/** Offset 0x00EA - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x00EB - State of DMA_CONTROL_GUARANTEE bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 DmaControlGuarantee; - -/** Offset 0x00EC - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[9]; - -/** Offset 0x0110 - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x0111 - Vtd Programming for Igd - 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIgdEnable; - -/** Offset 0x0112 - Vtd Programming for Ipu - 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIpuEnable; - -/** Offset 0x0113 - Vtd Programming for Iop - 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdIopEnable; - -/** Offset 0x0114 - Vtd Programming for ITbt - 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar - programming disabled) - $EN_DIS -**/ - UINT8 VtdItbtEnable; - -/** Offset 0x0115 - Disable Te Igd - 0=Enable/FALSE(Te Igd enabled), 1=Disable/TRUE (Te Igd disabled) - $EN_DIS -**/ - UINT8 DisableTeIgd; - -/** Offset 0x0116 - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, - 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, - 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x0117 - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x0118 - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x0119 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x011A - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, - 2133, 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x011C - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at three different frequencies. - 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x011D - DDR Speed Control - DDR Frequency and Gear control for all SAGV points. - 0:Auto, 1:Manual -**/ - UINT8 DdrSpeedControl; - -/** Offset 0x011E - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x0120 - Mid Frequency - SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvMid; - -/** Offset 0x0122 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x0123 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x0124 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x0125 - Ddr4OneDpc - DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, - or on both (default) - 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled -**/ - UINT8 Ddr4OneDpc; - -/** Offset 0x0126 -**/ - UINT8 UnusedUpdSpace1[2]; - -/** Offset 0x0128 - MMA Test Content Pointer - Pointer to MMA Test Content in Memory -**/ - UINT32 MmaTestContentPtr; - -/** Offset 0x012C - MMA Test Content Size - Size of MMA Test Content in Memory -**/ - UINT32 MmaTestContentSize; - -/** Offset 0x0130 - MMA Test Config Pointer - Pointer to MMA Test Config in Memory -**/ - UINT32 MmaTestConfigPtr; - -/** Offset 0x0134 - MMA Test Config Size - Size of MMA Test Config in Memory -**/ - UINT32 MmaTestConfigSize; - -/** Offset 0x0138 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x0139 -**/ - UINT8 UnusedUpdSpace2; - -/** Offset 0x013A - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x013C - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x013D - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x013E - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x013F - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x0140 - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x0142 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x0144 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x0145 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x0146 - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x0148 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x014A - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x014B - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x014C - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x014D - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x014E - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x014F - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x0150 - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x0151 - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x0152 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x0153 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x0154 - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x0155 - Enable PSE Controller - 0: Disable; 1: Enable (Default) PSE controller - $EN_DIS -**/ - UINT8 PchPseEnable; - -/** Offset 0x0156 - CPU Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x0157 - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x0158 - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x0159 - SA GV Low Gear - Gear Selection for SAGV Low point - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvLowGear2; - -/** Offset 0x015A - SA GV Mid Gear - Gear Selection for SAGV Mid point - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvMidGear2; - -/** Offset 0x015B - SA GV High Gear - Gear Selection for SAGV High point, or when SAGV is disabled - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvHighGear2; - -/** Offset 0x015C - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x015D -**/ - UINT8 UnusedUpdSpace4[3]; - -/** Offset 0x0160 - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x0164 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x0168 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x016C - HG dGPU Power Delay - HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 HgDelayAfterPwrEn; - -/** Offset 0x016E - HG dGPU Reset Delay - HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 HgDelayAfterHoldReset; - -/** Offset 0x0170 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x0172 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0173 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0174 - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x0175 -**/ - UINT8 UnusedUpdSpace5[3]; - -/** Offset 0x0178 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x017C - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0180 - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x0182 - Hybrid Graphics GPIO information for PEG 0 - Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT8 CpuPcie0Rtd3Gpio[24]; - -/** Offset 0x019A - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x019B - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x019C - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x019D - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 60=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x019E - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x01A0 - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x01A2 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x01A4 - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x01A6 - PCIe root port Function number for Hybrid Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x01A7 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x01A8 - This is policy to control iTBT PCIe Multiple Segment setting. - When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the - TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieMultipleSegmentEnabled; - -/** Offset 0x01A9 - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x01AA - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x01AB - IMGU CLKOUT Configuration - The configuration of IMGU CLKOUT, 0: Disable;1: Enable. - $EN_DIS -**/ - UINT8 ImguClkOutEn[5]; - -/** Offset 0x01B0 - IPU FUSA Configuration - 0:FUSA Disable, 1:FUSA Enable Default is 0 - 0:FUSA Disable, 1:FUSA Enable -**/ - UINT8 SaIpuFusaConfigEnable; - -/** Offset 0x01B1 -**/ - UINT8 UnusedUpdSpace6[3]; - -/** Offset 0x01B4 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 CpuPcieRpEnableMask; - -/** Offset 0x01B8 - Assertion on Link Down GPIOs - GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down - GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs - 0:Disable, 1:Enable -**/ - UINT8 CpuPcieRpLinkDownGpios; - -/** Offset 0x01B9 - Enable ClockReq Messaging - ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): - Enable ClockReq Messaging - 0:Disable, 1:Enable -**/ - UINT8 CpuPcieRpClockReqMsgEnable; - -/** Offset 0x01BA - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; - 4: Gen4 (see: CPU_PCIE_SPEED). -**/ - UINT8 CpuPcieRpPcieSpeed[4]; - -/** Offset 0x01BE - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x01BF - Selection of DiSM Region Size - DiSM Size to be allocated for 2LM Sku Default is 0 - 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB -**/ - UINT8 DismSize; - -/** Offset 0x01C0 - Pram Size - Persisted Ram Size. Default is Disabled - 0x30:Disable, 0x31:4MB, 0x32:16MB, 0x33:64MB -**/ - UINT8 PramSize; - -/** Offset 0x01C1 - SaPreMemProductionRsvd - Reserved for SA Pre-Mem Production - $EN_DIS -**/ - UINT8 SaPreMemProductionRsvd[138]; - -/** Offset 0x024B - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x024C - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x024D - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x024E - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x024F - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0250 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x0258 - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0260 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x0268 - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x026C - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x026D - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x026E - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x026F - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x0270 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x0271 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x0272 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x0273 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x0274 - Enable or Disable CPU Ratio Override - Enable or Disable CPU Ratio Override; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CpuRatioOverride; - -/** Offset 0x0275 - CPU ratio value - CPU ratio value. Valid Range 0 to 63 -**/ - UINT8 CpuRatio; - -/** Offset 0x0276 - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x0277 - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x0278 - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x0279 - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x027A - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x027B - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x027C - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x027D - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x027E - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x0280 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x0282 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x0284 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x0285 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x0286 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x0287 - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x0288 - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x028A - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x028C - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x028E -**/ - UINT8 UnusedUpdSpace7[2]; - -/** Offset 0x0290 - ElixirSpringsPatchAddr - Address of Elixir Springs Patches -**/ - UINT32 ElixirSpringsPatchAddr; - -/** Offset 0x0294 - ElixirSpringsPatchSize - Size of Elixir Springs Patches -**/ - UINT32 ElixirSpringsPatchSize; - -/** Offset 0x0298 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x0299 - CPU Run Control Lock - Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x029A - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x029B -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x029C - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x029D - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x029E -**/ - UINT8 UnusedUpdSpace8[2]; - -/** Offset 0x02A0 - PrmrrSize - Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable -**/ - UINT32 PrmrrSize; - -/** Offset 0x02A4 - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x02A8 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x02B0 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x02B4 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x02B8 - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x02BC - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x02C0 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x02C4 - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x02C8 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x02D0 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x02D8 - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x02D9 - ReservedSecurityPreMem - Reserved for Security Pre-Mem - $EN_DIS -**/ - UINT8 ReservedSecurityPreMem[6]; - -/** Offset 0x02DF - PCH Master Clock Gating Control - Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default - $EN_DIS -**/ - UINT8 PchMasterClockGating; - -/** Offset 0x02E0 - PCH Master Power Gating Control - Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default - $EN_DIS -**/ - UINT8 PchMasterPowerGating; - -/** Offset 0x02E1 -**/ - UINT8 UnusedUpdSpace9; - -/** Offset 0x02E2 - FIA Lane Reversal Enable/Disable config mask - Enable/Disable. 0: Disable, 1: enable, Enable or disable Lane Reversal. If Enabled, - the x2 FIA Lane will be flipped -**/ - UINT16 FiaLaneReversalEnable; - -/** Offset 0x02E4 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x02FC - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0314 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x032C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x0344 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x035C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x0374 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x038C - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x03A4 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x03BC - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x03D4 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x03EC - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0404 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x041C - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x0434 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x043C - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x0444 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x044C - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x0454 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x045C - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x0464 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x046C - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x0474 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x047C - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x0484 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x048C - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x0494 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x049C - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x04A4 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x04AC - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x04B4 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x04BC - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x04C4 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x04C5 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x04C6 - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x04C7 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x04C8 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x04CA - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x04CB - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x04DB - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x04EB -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x04EC - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x04F0 - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x04F4 - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x04F5 - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x04F6 - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x04F7 -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x04F8 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x04FC - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x04FD - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x04FE - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x04FF -**/ - UINT8 UnusedUpdSpace12; - -/** Offset 0x0500 - Serial Io Uart Debug Mmio Base - Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode - = SerialIoUartPci. -**/ - UINT32 SerialIoUartDebugMmioBase; - -/** Offset 0x0504 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0505 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0506 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0507 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0508 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0509 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x050A - TCSS Thunderbolt PCIE Root Port 0 Enable - Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie0En; - -/** Offset 0x050B - TCSS Thunderbolt PCIE Root Port 1 Enable - Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie1En; - -/** Offset 0x050C - TCSS Thunderbolt PCIE Root Port 2 Enable - Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie2En; - -/** Offset 0x050D - TCSS Thunderbolt PCIE Root Port 3 Enable - Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie3En; - -/** Offset 0x050E - TCSS USB HOST (xHCI) Enable - Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below - $EN_DIS -**/ - UINT8 TcssXhciEn; - -/** Offset 0x050F - TCSS USB DEVICE (xDCI) Enable - Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled - $EN_DIS -**/ - UINT8 TcssXdciEn; - -/** Offset 0x0510 - TCSS DMA0 Enable - Set TCSS DMA0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma0En; - -/** Offset 0x0511 - TCSS DMA1 Enable - Set TCSS DMA1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma1En; - -/** Offset 0x0512 - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x0513 - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x0514 - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x0515 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x0516 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x0517 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x0518 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x0519 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x051A - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x051B - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x051C - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x051D - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x051E - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x051F - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x0520 - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x0521 - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x0522 - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x0523 - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x0524 - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x0525 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x0526 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x0527 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x0528 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x0529 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x052A - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x052B - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x052C - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x052D - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x052E - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x052F - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x0530 - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x0531 -**/ - UINT8 UnusedUpdSpace13; - -/** Offset 0x0532 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x0534 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x0535 - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x0536 - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x0537 - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x0538 - Command Slew Rate Training - Enables/Disable Command Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x0539 - Command Drive Strength and Equalization 2D - Enables/Disable Command Drive Strength and Equalization 2D - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x053A - Command Normalization - Enables/Disable Command Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x053B - Early DQ Write Drive Strength and Equalization Training - Enables/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x053C - Read Voltage Centering - Enables/Disable Read Voltage Centering - $EN_DIS -**/ - UINT8 RDVC1D; - -/** Offset 0x053D - Write TCO Comp Training - Enables/Disable Write TCO Comp Training - $EN_DIS -**/ - UINT8 TXTCO; - -/** Offset 0x053E - Clock TCO Comp Training - Enables/Disable Clock TCO Comp Training - $EN_DIS -**/ - UINT8 CLKTCO; - -/** Offset 0x053F - Dimm ODT CA Training - Enables/Disable Dimm ODT CA Training - $EN_DIS -**/ - UINT8 DIMMODTCA; - -/** Offset 0x0540 - Write TCO Dqs Training - Enables/Disable Write TCO Dqs Training - $EN_DIS -**/ - UINT8 TXTCODQS; - -/** Offset 0x0541 - Duty Cycle Correction - Enables/Disable Duty Cycle Correction - $EN_DIS -**/ - UINT8 DCC; - -/** Offset 0x0542 - DQ DFE Training - Enable/Disable DQ DFE Training - $EN_DIS -**/ - UINT8 DQDFE; - -/** Offset 0x0543 - Sense Amplifier Correction Training - Enable/Disable Sense Amplifier Correction Training - $EN_DIS -**/ - UINT8 SOTC; - -/** Offset 0x0544 - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x0545 - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0546 - MRC Time Measure - Enable/Disable MRC Time Measure - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0547 - MRC Fast Boot - Enable/Disable MRC Fast flow - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0548 - MRC Force Training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x0549 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x054A - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x054B - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x054C - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x054D - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x054E - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x054F - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x0550 - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x0551 - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0552 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x0553 - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x0554 - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x0555 - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x0556 - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x0557 - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x0558 - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x0559 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x055A - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x055B - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x055C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x055D - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x055E -**/ - UINT8 UnusedUpdSpace14[2]; - -/** Offset 0x0560 - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x0564 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x0565 -**/ - UINT8 UnusedUpdSpace15; - -/** Offset 0x0566 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6] Default is 0x30CC -**/ - UINT16 ChHashMask; - -/** Offset 0x0568 - Extended Bank Hashing - Eanble/Disable ExtendedBankHashing - $EN_DIS -**/ - UINT8 ExtendedBankHashing; - -/** Offset 0x0569 - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x056A - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x056C - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x056E - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x056F - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x0570 - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x0571 - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x0572 - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x0573 -**/ - UINT8 UnusedUpdSpace16; - -/** Offset 0x0574 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x0576 - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x0578 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x0579 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x057A - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x057B - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x057C - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x057D - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x057E - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x057F - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x0580 - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x0581 - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x0582 - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x0583 - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x0584 - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x0585 - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x0586 - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x0587 - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x0588 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x0589 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x058A - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x058B - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x058C - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x058D - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x058E - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x058F - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x0590 - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x0591 - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x0592 - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x0593 - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x0594 - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x0595 - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x0596 - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x0597 - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x0598 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x0599 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x059A - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x059B - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x059C - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Dfault is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x059D - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x059E - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x059F - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x05A0 - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x05A1 - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x05A2 - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x05A3 - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is 2x Refresh - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x05A4 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x05A5 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x05A6 - Power Down Mode - This option controls command bus tristating during idle periods - 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto -**/ - UINT8 PowerDownMode; - -/** Offset 0x05A7 - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x05A8 - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x05A9 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x05AA - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x05AB - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x05AC - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x05AD - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x05AE - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x05AF - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x05B0 - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x05B1 - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x05B2 - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x05B3 - Page Close Idle Timeout - This option controls Page Close Idle Timeout - 0:Enabled, 1:Disabled -**/ - UINT8 DisPgCloseIdleTimeout; - -/** Offset 0x05B4 - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x05B5 - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x05B6 - Throttler CKEMin Timer for LPDDR - LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH - (4). Dfault is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x05B7 - Retrain on Fast Fail - Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled - $EN_DIS -**/ - UINT8 RetrainOnFastFail; - -/** Offset 0x05B8 - Rank Margin Tool Per Bit - Enable/disable Rank Margin Tool Per Bit. - $EN_DIS -**/ - UINT8 RMTBIT; - -/** Offset 0x05B9 - Read Timing Optimization - Enables/Disable Read Timing Optimization - $EN_DIS -**/ - UINT8 RDTOPT; - -/** Offset 0x05BA - REFRESH_PANIC_WM - Refresh Panic Watermark, range 1-9, Default is 9 -**/ - UINT8 RefreshPanicWm; - -/** Offset 0x05BB - REFRESH_HP_WM - Refresh High Priority Watermark, range 1-9, Default is 8 -**/ - UINT8 RefreshHpWm; - -/** Offset 0x05BC - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x05BD - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x05BE - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x05BF - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x05C0 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x05C1 - TCSS USB Port Enable - Bitmap for per port enabling -**/ - UINT8 UsbTcPortEnPreMem; - -/** Offset 0x05C2 - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x05C4 - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x05C5 -**/ - UINT8 UnusedUpdSpace17[3]; - -/** Offset 0x05C8 - BCLK RFI Frequency - Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No - RFI Tuning. Range is 98Mhz-100Mhz. -**/ - UINT32 BclkRfiFreq[4]; - -/** Offset 0x05D8 - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x05DA - Enable PCIe IMR - 0: Disable(AUTO), 1: Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x05DB - Enable PCIe IMR - 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select - the Root port location from PCH PCIe or SA PCIe - $EN_DIS -**/ - UINT8 PcieImrRpLocation; - -/** Offset 0x05DC - Root port number for IMR. - Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port - from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 -**/ - UINT8 PcieImrRpSelection; - -/** Offset 0x05DD - Mem Boot Mode - 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION - 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION -**/ - UINT8 MemBootMode; - -/** Offset 0x05DE - PCIe ASPM programming will happen in relation to the Oprom - This option is specifically needed for ASPM configuration in 2LM feature - 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto -**/ - UINT8 Peg3Aspm; - -/** Offset 0x05DF - MFVC WRR VC Arbitration - 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES - 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES -**/ - UINT8 MfvcWrrArb; - -/** Offset 0x05E0 - VcId_7_0 values - Select VC ID for arbitration -**/ - UINT8 VcId_7_0[16]; - -/** Offset 0x05F0 - Set Hw Parameters enable/disable - 1: enable, 0: disable, Enable/disable setting of HW parameters - $EN_DIS -**/ - UINT8 SetHwParameters; - -/** Offset 0x05F1 -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x05F2 - LTR L1.2 Threshold Value - LTR L1.2 Threshold Value -**/ - UINT16 Ltr_L1D2_ThVal; - -/** Offset 0x05F4 - LTR L1.2 Threshold Scale - LTR L1.2 Threshold Scale -**/ - UINT8 Ltr_L1D2_ThScale; - -/** Offset 0x05F5 - system power state - system power state indicates the platform power state -**/ - UINT8 SysPwrState; - -/** Offset 0x05F6 - Media Death Notification Enable/Disable - 1: enable, 0: disable, Enable/disable for Media Death Notification - $EN_DIS -**/ - UINT8 MediaDeathNotification; - -/** Offset 0x05F7 - Health Log Notification Enable/Disable - 1: enable, 0: disable, Enable/disable for Health Log Notification - $EN_DIS -**/ - UINT8 HealthLogNotification; - -/** Offset 0x05F8 - Temp crosses below TempThrottle Notification Enable/Disable - 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification - $EN_DIS -**/ - UINT8 TempBelowThrottleNotification; - -/** Offset 0x05F9 - Temp crosses above TempThrottle Notification Enable/Disable - 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification - $EN_DIS -**/ - UINT8 TempAboveThrottleNotification; - -/** Offset 0x05FA - Missing Commit Bit Notification Enable/Disable - 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification - $EN_DIS -**/ - UINT8 MissingCommitBitNotification; - -/** Offset 0x05FB - NVMeHoldDisableBit - 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit - $EN_DIS -**/ - UINT8 NVMeHoldDisableBit; - -/** Offset 0x05FC - PreMemRsvd - Reserved for Pre-Mem - $EN_DIS -**/ - UINT8 ReservedFspmUpd[18]; - -/** Offset 0x060E - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x060F - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0610 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0611 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0612 - Rsvd - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3Rsvd; - -/** Offset 0x0613 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x0614 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x0615 - SaPreMemTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SaPreMemTestRsvd[98]; - -/** Offset 0x0677 -**/ - UINT8 UnusedUpdSpace19; - -/** Offset 0x0678 - TotalFlashSize - Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable -**/ - UINT16 TotalFlashSize; - -/** Offset 0x067A - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x067C - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x067D - SecurityTestRsvd - Reserved for SA Pre-Mem Test - $EN_DIS -**/ - UINT8 SecurityTestRsvd[11]; - -/** Offset 0x0688 - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x0689 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x068A - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x068B - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x068C - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x068D - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHdaEnable; - -/** Offset 0x068E - Enable HDA SDI lanes - Enable/disable HDA SDI lanes. -**/ - UINT8 PchHdaSdiEnable[2]; - -/** Offset 0x0690 - HDA Power/Clock Gating (PGD/CGD) - Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: - FORCE_ENABLE, 2: FORCE_DISABLE. - 0: POR, 1: Force Enable, 2: Force Disable -**/ - UINT8 PchHdaTestPowerClockGating; - -/** Offset 0x0691 - Enable HD Audio DMIC_N Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. -**/ - UINT8 PchHdaAudioLinkDmicEnable[2]; - -/** Offset 0x0693 -**/ - UINT8 UnusedUpdSpace20[1]; - -/** Offset 0x0694 - DMIC ClkA Pin Muxing (N - DMIC number) - Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* -**/ - UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; - -/** Offset 0x069C - DMIC ClkB Pin Muxing - Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* -**/ - UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; - -/** Offset 0x06A4 - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x06A5 -**/ - UINT8 UnusedUpdSpace21[3]; - -/** Offset 0x06A8 - DMIC Data Pin Muxing - Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* -**/ - UINT32 PchHdaAudioLinkDmicDataPinMux[2]; - -/** Offset 0x06B0 - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 -**/ - UINT8 PchHdaAudioLinkSspEnable[6]; - -/** Offset 0x06B6 - Enable HD Audio SoundWire#N Link - Enable/disable HD Audio SNDW#N link. Muxed with HDA. -**/ - UINT8 PchHdaAudioLinkSndwEnable[4]; - -/** Offset 0x06BA - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x06BB - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T - 0: 2T, 2: 4T, 3: 8T, 4: 16T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x06BC - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x06BD - Tcc Tuning enable/disable - Tcc (Time Coordinated Computing) Tuning Enabled - $EN_DIS -**/ - UINT8 TccTuningEnablePreMem; - -/** Offset 0x06BE -**/ - UINT8 UnusedUpdSpace22[2]; - -/** Offset 0x06C0 - Tcc Buffer Config File Base Address - Tcc (Time Coordinated Computing) Buffer Config File File Base Address -**/ - UINT32 TccBufferCfgBase; - -/** Offset 0x06C4 - Tcc Buffer Config File Size - Tcc (Time Coordinated Computing) Buffer Config File Size -**/ - UINT32 TccBufferCfgSize; - -/** Offset 0x06C8 - Tcc BIOS Config File Base Address - Tcc (Time Coordinated Computing) TCC BIOS Config File Base Address -**/ - UINT32 TccStreamCfgBasePreMem; - -/** Offset 0x06CC - Tcc BIOS Config File Size - Tcc (Time Coordinated Computing) TCC BIOS Config File Size -**/ - UINT32 TccStreamCfgSizePreMem; - -/** Offset 0x06D0 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x06D1 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x06D2 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x06D3 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x06D4 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x06D5 - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x06D6 - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x06D7 - Skip CPU replacement check - Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check - $EN_DIS -**/ - UINT8 SkipCpuReplacementCheck; - -/** Offset 0x06D8 -**/ - UINT8 UnusedUpdSpace23[4]; - -/** Offset 0x06DC -**/ - UINT8 ReservedFspmUpd2[20]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x06F0 -**/ - UINT8 UnusedUpdSpace24[6]; - -/** Offset 0x06F6 -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h deleted file mode 100644 index 5fcc4f12a6..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/elkhartlake/FsptUpd.h +++ /dev/null @@ -1,202 +0,0 @@ -/** @file - -Copyright (c) 2021, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionSize; - -/** Offset 0x0030 -**/ - UINT8 Reserved[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - PcdSerialIoUartDebugEnable - Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. - 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing -**/ - UINT8 PcdSerialIoUartDebugEnable; - -/** Offset 0x0041 - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 PcdSerialIoUartNumber; - -/** Offset 0x0042 - PcdSerialIoUartMode - FSPT - Select SerialIo Uart Controller mode - 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 PcdSerialIoUartMode; - -/** Offset 0x0043 -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 PcdSerialIoUartBaudRate; - -/** Offset 0x0048 - Pci Express Base Address - Base address to be programmed for Pci Express -**/ - UINT64 PcdPciExpressBaseAddress; - -/** Offset 0x0050 - Pci Express Region Length - Region Length to be programmed for Pci Express -**/ - UINT32 PcdPciExpressRegionLength; - -/** Offset 0x0054 - PcdSerialIoUartParity - FSPT - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 PcdSerialIoUartParity; - -/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 PcdSerialIoUartDataBits; - -/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 PcdSerialIoUartStopBits; - -/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT - Enables UART hardware flow control, CTS and RTS lines. - 0: Disable, 1:Enable -**/ - UINT8 PcdSerialIoUartAutoFlow; - -/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT - Select RX pin muxing for SerialIo UART used for debug -**/ - UINT32 PcdSerialIoUartRxPinMux; - -/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT - Select TX pin muxing for SerialIo UART used for debug -**/ - UINT32 PcdSerialIoUartTxPinMux; - -/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT - Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 PcdSerialIoUartRtsPinMux; - -/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT - Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 PcdSerialIoUartCtsPinMux; - -/** Offset 0x0068 - PcdSerialIoUartDebugMmioBase - FSPT - Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode - = SerialIoUartPci. -**/ - UINT32 PcdSerialIoUartDebugMmioBase; - -/** Offset 0x006C - PcdLpcUartDebugEnable - Enable to initialize LPC Uart device in FSP. - 0:Disable, 1:Enable -**/ - UINT8 PcdLpcUartDebugEnable; - -/** Offset 0x006D -**/ - UINT8 UnusedUpdSpace1[7]; - -/** Offset 0x0074 -**/ - UINT8 ReservedFsptUpd1[20]; -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0088 -**/ - UINT8 UnusedUpdSpace2[6]; - -/** Offset 0x008E -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h index dd7db9dae3..02d9d76616 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h @@ -875,11 +875,8 @@ typedef struct { UINT8 PavpEnable; /** Offset 0x0436 - CdClock Frequency selection - 0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 - Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, - 9: 652.8 Mhz - 0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190 - Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz + 0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz, + 7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default) **/ UINT8 CdClock; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index e7e8f899a5..e3baf7bba2 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -1946,6 +1946,11 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e #endif } + if (p->support_rank_num == RANK_SINGLE){ + CKEFixOnOff(p, RANK_1, CKE_DYNAMIC, TO_ALL_CHANNEL); + mcSHOW_DBG_MSG(("Set RANK1 CKE to DYNAMIC\n")); + } + #if (FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0) U32 backup_broadcast; backup_broadcast = GetDramcBroadcast(); diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 6397e9b670..847beaf199 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -45,6 +45,7 @@ TEST_CFLAGS += -I$(src) -I$(src)/include -I$(src)/commonlib/include \ # Only put conservative warnings here that really detect code that's obviously # unintentional. TEST_CFLAGS += -Wall -Werror -Wundef -Wstrict-prototypes -Wno-inline-asm +TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type # Path for Kconfig autoheader TEST_CFLAGS += -I$(dir $(TEST_KCONFIG_AUTOHEADER)) @@ -156,10 +157,11 @@ $($(1)-objs): $(testobj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) -MF $$(basename $$@).d -MT $$@ -c $$< -o $$@.orig objcopy_wrap_flags=''; \ for sym in $$($(1)-mocks); do \ - sym_line="$$$$($(OBJDUMP) -t $$@.orig | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$")"; \ + sym_line="$$$$($(OBJDUMP) -t $$@.orig \ + | grep -E "[0-9a-fA-F]+\\s+w\\s+F\\s+.*\\s$$$$sym$$$$")"; \ if [ ! -z "$$$$sym_line" ] ; then \ - addr="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$1 }')"; \ - section="$$$$(echo \"$$$$sym_line\" | awk '{ print $$$$(NF - 2) }')"; \ + addr="$$$$(echo "$$$$sym_line" | awk '{ print $$$$1 }')"; \ + section="$$$$(echo "$$$$sym_line" | awk '{ print $$$$(NF - 2) }')"; \ objcopy_wrap_flags="$$$$objcopy_wrap_flags --add-symbol __real_$$$${sym}=$$$${section}:0x$$$${addr},function,global"; \ fi \ done ; \ @@ -232,7 +234,7 @@ endif $(alltests): $$($$(@)-bin) rm -f $(testobj)/junit-$(subst /,_,$(patsubst $(testobj)/%/,%,$(dir $^)))\(*\).xml rm -f $(testobj)/$(subst /,_,$^).failed - -./$^ || echo failed > $(testobj)/$(subst /,_,$^).failed + -$^ || echo failed > $(testobj)/$(subst /,_,$^).failed # Build a code coverage report by collecting all the gcov files into a single # report. If COV is not set, this might be a user error, and they're trying diff --git a/tests/acpi/acpigen-test.c b/tests/acpi/acpigen-test.c index 6bd1d02689..156b544095 100644 --- a/tests/acpi/acpigen-test.c +++ b/tests/acpi/acpigen-test.c @@ -13,7 +13,7 @@ static u32 decode_package_length(const char *ptr) { const u8 *aml = (u8 *)ptr; const u32 offset = (aml[0] == EXT_OP_PREFIX ? 2 : 1); - u32 byte_zero_mask = 0x3F; /* Bits [0:5] */ + u32 byte_zero_mask = 0x3F; /* Bits [0:5] */ u32 byte_count = aml[offset] >> 6; u32 package_length = 0; @@ -106,7 +106,7 @@ static void test_acpigen_nested_ifs(void **state) for (int i = 0; i < nesting_level; ++i) assert_int_equal(decode_package_length(block_start[i]), - block_end[i] - block_start[i] - 1); + block_end[i] - block_start[i] - 1); } static void test_acpigen_write_package(void **state) @@ -203,14 +203,14 @@ static void test_acpigen_scope_with_contents(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_acpigen_single_if, - setup_acpigen, teardown_acpigen), - cmocka_unit_test_setup_teardown(test_acpigen_nested_ifs, - setup_acpigen, teardown_acpigen), - cmocka_unit_test_setup_teardown(test_acpigen_write_package, - setup_acpigen, teardown_acpigen), - cmocka_unit_test_setup_teardown(test_acpigen_scope_with_contents, - setup_acpigen, teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_single_if, setup_acpigen, + teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_nested_ifs, setup_acpigen, + teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_write_package, setup_acpigen, + teardown_acpigen), + cmocka_unit_test_setup_teardown(test_acpigen_scope_with_contents, setup_acpigen, + teardown_acpigen), }; return cb_run_group_tests(tests, NULL, NULL); diff --git a/tests/commonlib/region-test.c b/tests/commonlib/region-test.c index 59f272a7d9..32804825a6 100644 --- a/tests/commonlib/region-test.c +++ b/tests/commonlib/region-test.c @@ -14,30 +14,30 @@ static void test_region(void **state) assert_true(VAL(5) + VAL(10) > VAL(10)); assert_true(VAL(7) + VAL(10) < VAL(10)); - struct region outer = { .offset = VAL(2), .size = VAL(4) }; + struct region outer = {.offset = VAL(2), .size = VAL(4)}; assert_int_equal(region_offset(&outer), VAL(2)); assert_int_equal(region_sz(&outer), VAL(4)); assert_int_equal(region_end(&outer), VAL(6)); - struct region inner = { .offset = VAL(3), .size = VAL(2) }; + struct region inner = {.offset = VAL(3), .size = VAL(2)}; assert_true(region_is_subregion(&outer, &inner)); - struct region touching_bottom = { .offset = VAL(2), .size = VAL(1) }; + struct region touching_bottom = {.offset = VAL(2), .size = VAL(1)}; assert_true(region_is_subregion(&outer, &touching_bottom)); - struct region touching_top = { .offset = VAL(5), .size = VAL(1) }; + struct region touching_top = {.offset = VAL(5), .size = VAL(1)}; assert_true(region_is_subregion(&outer, &touching_top)); - struct region overlap_bottom = { .offset = VAL(1), .size = VAL(2) }; + struct region overlap_bottom = {.offset = VAL(1), .size = VAL(2)}; assert_false(region_is_subregion(&outer, &overlap_bottom)); - struct region overlap_top = { .offset = VAL(5), .size = VAL(2) }; + struct region overlap_top = {.offset = VAL(5), .size = VAL(2)}; assert_false(region_is_subregion(&outer, &overlap_top)); - struct region below = { .offset = 0, .size = VAL(1) }; + struct region below = {.offset = 0, .size = VAL(1)}; assert_false(region_is_subregion(&outer, &below)); - struct region above = { .offset = VAL(0xf), .size = VAL(1) }; + struct region above = {.offset = VAL(0xf), .size = VAL(1)}; assert_false(region_is_subregion(&outer, &above)); } @@ -58,8 +58,8 @@ static int mock_unmap(const struct region_device *rdev, void *mapping) return mock(); } -static ssize_t mock_readat(const struct region_device *rdev, void *buffer, - size_t offset, size_t size) +static ssize_t mock_readat(const struct region_device *rdev, void *buffer, size_t offset, + size_t size) { check_expected_ptr(rdev); check_expected_ptr(buffer); @@ -73,8 +73,8 @@ static ssize_t mock_readat(const struct region_device *rdev, void *buffer, return ret; } -static ssize_t mock_writeat(const struct region_device *rdev, const void *buffer, - size_t offset, size_t size) +static ssize_t mock_writeat(const struct region_device *rdev, const void *buffer, size_t offset, + size_t size) { check_expected_ptr(rdev); check_expected_ptr(buffer); @@ -365,7 +365,7 @@ static void test_mem_rdev(void **state) /* Test read/write/erase of larger chunk. */ size_t offs = 0x47; - size_t chunk = 0x72; + size_t chunk = 0x72; memset(backing, 0, size); memset(scratch, 0, size); memset(scratch + offs, 0x39, chunk); diff --git a/tests/console/routing-test.c b/tests/console/routing-test.c index 153ca77c19..3cba51f7c4 100644 --- a/tests/console/routing-test.c +++ b/tests/console/routing-test.c @@ -42,7 +42,7 @@ static void test_console_log_level(void **state) for (int i = 0; i < ARRAY_SIZE(combinations); i++) { console_loglevel = combinations[i].log_lvl; assert_int_equal(combinations[i].behavior, - console_log_level(combinations[i].msg_lvl)); + console_log_level(combinations[i].msg_lvl)); } } @@ -61,8 +61,7 @@ static int teardown_console_log_level(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_console_log_level, - setup_console_log_level, + cmocka_unit_test_setup_teardown(test_console_log_level, setup_console_log_level, teardown_console_log_level), }; diff --git a/tests/device/ddr4-test.c b/tests/device/ddr4-test.c index 3ee1e79f1d..d5d7ee7d36 100644 --- a/tests/device/ddr4-test.c +++ b/tests/device/ddr4-test.c @@ -33,9 +33,7 @@ static void ddr4_speed_mhz_to_mts_test(void **state) int main(void) { - const struct CMUnitTest tests[] = { - cmocka_unit_test(ddr4_speed_mhz_to_mts_test) - }; + const struct CMUnitTest tests[] = {cmocka_unit_test(ddr4_speed_mhz_to_mts_test)}; return cb_run_group_tests(tests, NULL, NULL); } diff --git a/tests/device/i2c-test.c b/tests/device/i2c-test.c index 010b8688f9..4b96d940f9 100644 --- a/tests/device/i2c-test.c +++ b/tests/device/i2c-test.c @@ -18,20 +18,27 @@ typedef struct { } i2c_ex_devs_t; i2c_ex_devs_t i2c_ex_devs[] = { - {.bus = 0, .slave = 0xA, .regs = { - {.reg = 0x0, .data = 0xB}, - {.reg = 0x1, .data = 0x6}, - {.reg = 0x2, .data = 0xF}, - } }, - {.bus = 0, .slave = 0x3, .regs = { - {.reg = 0x0, .data = 0xDE}, - {.reg = 0x1, .data = 0xAD}, - {.reg = 0x2, .data = 0xBE}, - } }, + { + .bus = 0, + .slave = 0xA, + .regs = { + {.reg = 0x0, .data = 0xB}, + {.reg = 0x1, .data = 0x6}, + {.reg = 0x2, .data = 0xF}, + } + }, + { + .bus = 0, + .slave = 0x3, + .regs = { + {.reg = 0x0, .data = 0xDE}, + {.reg = 0x1, .data = 0xAD}, + {.reg = 0x2, .data = 0xBE}, + } + }, }; -int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, - int count) +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) { int i; int reg; @@ -73,22 +80,19 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, static void mock_expect_params_platform_i2c_transfer(void) { - unsigned long int expected_flags[] = {0, I2C_M_RD, I2C_M_TEN, - I2C_M_RECV_LEN, I2C_M_NOSTART}; + unsigned long int expected_flags[] = {0, I2C_M_RD, I2C_M_TEN, I2C_M_RECV_LEN, + I2C_M_NOSTART}; /* Flags should always be only within supported range */ - expect_in_set_count(platform_i2c_transfer, segments->flags, - expected_flags, -1); + expect_in_set_count(platform_i2c_transfer, segments->flags, expected_flags, -1); - expect_not_value_count(platform_i2c_transfer, segments->buf, - NULL, -1); + expect_not_value_count(platform_i2c_transfer, segments->buf, NULL, -1); - expect_in_range_count(platform_i2c_transfer, count, 1, INT_MAX, - -1); + expect_in_range_count(platform_i2c_transfer, count, 1, INT_MAX, -1); } -#define MASK 0x3 -#define SHIFT 0x1 +#define MASK 0x3 +#define SHIFT 0x1 static void i2c_read_field_test(void **state) { @@ -101,21 +105,17 @@ static void i2c_read_field_test(void **state) with expected value. */ for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { - i2c_read_field(i2c_ex_devs[i].bus, - i2c_ex_devs[i].slave, - i2c_ex_devs[i].regs[j].reg, - &buf, MASK, SHIFT); - assert_int_equal((i2c_ex_devs[i].regs[j].data & - (MASK << SHIFT)) >> SHIFT, buf); + i2c_read_field(i2c_ex_devs[i].bus, i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, &buf, MASK, SHIFT); + assert_int_equal( + (i2c_ex_devs[i].regs[j].data & (MASK << SHIFT)) >> SHIFT, buf); }; /* Read whole registers */ for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { - i2c_read_field(i2c_ex_devs[i].bus, - i2c_ex_devs[i].slave, - i2c_ex_devs[i].regs[j].reg, - &buf, 0xFF, 0); + i2c_read_field(i2c_ex_devs[i].bus, i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, &buf, 0xFF, 0); assert_int_equal(i2c_ex_devs[i].regs[j].data, buf); }; } @@ -133,36 +133,28 @@ static void i2c_write_field_test(void **state) for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { buf = 0x0; tmp = i2c_ex_devs[i].regs[j].data; - i2c_write_field(i2c_ex_devs[i].bus, - i2c_ex_devs[i].slave, - i2c_ex_devs[i].regs[j].reg, - buf, MASK, SHIFT); + i2c_write_field(i2c_ex_devs[i].bus, i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, buf, MASK, SHIFT); assert_int_equal(i2c_ex_devs[i].regs[j].data, - (tmp & ~(MASK << SHIFT)) | (buf << SHIFT)); + (tmp & ~(MASK << SHIFT)) | (buf << SHIFT)); }; /* Set all bits in all registers, this time verify using i2c_read_field() accessor. */ for (i = 0; i < ARRAY_SIZE(i2c_ex_devs); i++) for (j = 0; j < ARRAY_SIZE(i2c_ex_devs[0].regs); j++) { - i2c_write_field(i2c_ex_devs[i].bus, - i2c_ex_devs[i].slave, - i2c_ex_devs[i].regs[j].reg, - 0xFF, 0xFF, 0); - i2c_read_field(i2c_ex_devs[i].bus, - i2c_ex_devs[i].slave, - i2c_ex_devs[i].regs[j].reg, - &buf, 0xFF, 0); + i2c_write_field(i2c_ex_devs[i].bus, i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, 0xFF, 0xFF, 0); + i2c_read_field(i2c_ex_devs[i].bus, i2c_ex_devs[i].slave, + i2c_ex_devs[i].regs[j].reg, &buf, 0xFF, 0); assert_int_equal(buf, 0xFF); }; } int main(void) { - const struct CMUnitTest tests[] = { - cmocka_unit_test(i2c_read_field_test), - cmocka_unit_test(i2c_write_field_test) - }; + const struct CMUnitTest tests[] = {cmocka_unit_test(i2c_read_field_test), + cmocka_unit_test(i2c_write_field_test)}; return cb_run_group_tests(tests, NULL, NULL); } diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h deleted file mode 100644 index 8327748b66..0000000000 --- a/tests/include/lib/edid-test.h +++ /dev/null @@ -1,197 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - - -struct edid_raw { - uint8_t header[8]; - - /* Display product identification */ - uint16_t manufacturer_id; - uint16_t product_code; - uint32_t serial_number; - uint8_t manufacture_week; - uint8_t manufacture_year; - - /* EDID version information */ - uint8_t edid_version; - uint8_t edid_revision; - - /* Basic display parameters */ - uint8_t video_input_type; - uint8_t horizontal_size; /* [cm] */ - uint8_t vertical_size; /* [cm] */ - uint8_t display_gamma; - uint8_t supported_features; - - /* Color space definition */ - uint8_t color_characteristics[10]; - - /* Timing information */ - uint8_t established_supported_timings[2]; - uint8_t manufacturers_reserved_timing; - uint8_t standard_timings_supported[16]; - uint8_t descriptor_block_1[18]; - uint8_t descriptor_block_2[18]; - uint8_t descriptor_block_3[18]; - uint8_t descriptor_block_4[18]; - - /* Number of optional 128-byte extension blocks */ - uint8_t extension_flag; - - uint8_t checksum; -} __packed; - -_Static_assert(sizeof(struct edid_raw) == 128, - "assert failed: edid_raw size mismatch"); - -#define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 } -#define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 } - -#define EDID_MANUFACTURER_ID 0xcb55 -#define EDID_MANUFACTURER_NAME "UNK" -#define EDID_PRODUCT_CODE 0x1234 -#define EDID_SERIAL_NUMBER 0x56789ABC -#define EDID_MANUFACTURE_WEEK 23u -#define EDID_MANUFACTURE_NO_WEEK 0u -#define EDID_MANUFACTURE_YEAR (2015u - 1990u) - -/* Video Input Definition for Analog Video Signal Interface */ -#define EDID_ANALOG_VSI (0u << 7) -#define EDID_SIGNAL_LEVEL_0 0u -#define EDID_SIGNAL_LEVEL_1 (1u << 5) -#define EDID_SIGNAL_LEVEL_2 (2u << 5) -#define EDID_SIGNAL_LEVEL_3 (3u << 5) -#define EDID_VIDEO_SETUP_BLANK_EQ_BLACK 0u -#define EDID_VIDEO_SETUP_BLANK_TO_BLACK (1u << 4) -#define EDID_SEPARATE_SYNC_H_AND_V(v) ((v != 0 ? 0x1 : 0x0) << 3) -#define EDID_COMPOSITE_SYNC_H(v) ((v != 0 ? 0x1 : 0x0) << 2) -#define EDID_COMPOSITE_SYNC_ON_GREEN(v) ((v != 0 ? 0x1 : 0x0) << 1) -#define EDID_SERRATION_VSYNC(v) (v != 0 ? 0x1 : 0x0) - -/* Video Input Definition for Digital Video Signal Interface */ -#define EDID_DIGITAL_VSI (1u << 7) -#define EDID_COLOR_BIT_DEPTH_UNDEFINED 0u -#define EDID_COLOR_BIT_DEPTH_6B (1u << 4) -#define EDID_COLOR_BIT_DEPTH_8B (2u << 4) -#define EDID_COLOR_BIT_DEPTH_10B (3u << 4) -#define EDID_COLOR_BIT_DEPTH_12B (4u << 4) -#define EDID_COLOR_BIT_DEPTH_14B (5u << 4) -#define EDID_COLOR_BIT_DEPTH_16B (6u << 4) -#define EDID_INTERFACE_UNDEFINED 0u -#define EDID_INTERFACE_DVI 1u -#define EDID_INTERFACE_HDMI_A 2u -#define EDID_INTERFACE_HDMI_B 3u -#define EDID_INTERFACE_MDDI 4u -#define EDID_INTERFACE_DP 5u - -/* BEGIN Supported features */ -#define EDID_STANDBY_MODE(v) ((v != 0 ? 0x1 : 0x0) << 7) -#define EDID_SUSPEND_MODE(v) ((v != 0 ? 0x1 : 0x0) << 6) -#define EDID_ACTIVE_OFF(v) ((v != 0 ? 0x1 : 0x0) << 5) -/* For analog interface */ -#define EDID_COLOR_TYPE_MONO 0u -#define EDID_COLOR_TYPE_RGB (1u << 3) -#define EDID_COLOR_TYPE_NON_RGB (2u << 3) -#define EDID_COLOR_TYPE_UNDEFINED (3u << 3) -/* For digital interface */ -#define EDID_COLOR_FORMAT_RGB444 0u -#define EDID_COLOR_FORMAT_RGB444_YCRCB444 (1u << 3) -#define EDID_COLOR_FORMAT_RGB444_YCRCB422 (2u << 3) -#define EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 (3u << 3) - -#define EDID_SRGB_SUPPORTED(v) (((v) == 0 ? 0u : 1u) << 2) -#define EDID_PREFERRED_TIMING_EXTENDED_INFO (1u << 1) -#define EDID_PREFERRED_TIMING_NO_EXTENDED_INFO 0u -#define EDID_DISPLAY_FREQUENCY_CONTINUOUS 1u -#define EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS 0u -/* END Supported features */ - -/* Red X 0.640 */ -#define EDID_COLOR_R_X 0x25 -/* Red Y 0.330 */ -#define EDID_COLOR_R_Y 0x152 -/* Green X 0.300 */ -#define EDID_COLOR_G_X 0x13a -/* Green Y 0.600 */ -#define EDID_COLOR_G_Y 0x267 -/* Blue X 0.150 */ -#define EDID_COLOR_B_X 0x9a -/* Blue Y 0.060 */ -#define EDID_COLOR_B_Y 0x3e -/* White X 0.3125 */ -#define EDID_COLOR_W_X 0xa -/* White Y 0.3291 */ -#define EDID_COLOR_W_Y 0x22a - -/* 1 and 0 bits of each color */ -#define EDID_COLOR_R_X10_Y10 (((EDID_COLOR_R_X & 0x3) << 2) | (EDID_COLOR_R_Y & 0x3)) -#define EDID_COLOR_G_X10_Y10 (((EDID_COLOR_G_X & 0x3) << 2) | (EDID_COLOR_G_Y & 0x3)) -#define EDID_COLOR_B_X10_Y10 (((EDID_COLOR_B_X & 0x3) << 2) | (EDID_COLOR_B_Y & 0x3)) -#define EDID_COLOR_W_X10_Y10 (((EDID_COLOR_W_X & 0x3) << 2) | (EDID_COLOR_W_Y & 0x3)) - -/* Concatenated 0 and 1 bits of each color. To be put - * as first and second byte of color characteristic. */ -#define EDID_COLOR_RG_XY ((EDID_COLOR_R_X10_Y10 << 4) | EDID_COLOR_G_X10_Y10) -#define EDID_COLOR_BW_XY ((EDID_COLOR_B_X10_Y10 << 4) | EDID_COLOR_W_X10_Y10) - -/* Bits 9 through 2 of each color */ -#define EDID_COLOR_R_X92 (EDID_COLOR_R_X >> 2) -#define EDID_COLOR_R_Y92 (EDID_COLOR_R_Y >> 2) -#define EDID_COLOR_G_X92 (EDID_COLOR_G_X >> 2) -#define EDID_COLOR_G_Y92 (EDID_COLOR_G_Y >> 2) -#define EDID_COLOR_B_X92 (EDID_COLOR_B_X >> 2) -#define EDID_COLOR_B_Y92 (EDID_COLOR_B_Y >> 2) -#define EDID_COLOR_W_X92 (EDID_COLOR_W_X >> 2) -#define EDID_COLOR_W_Y92 (EDID_COLOR_W_Y >> 2) - -#define EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz 1u -#define EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz (1u << 1) -#define EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz (1u << 2) -#define EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz (1u << 3) -#define EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz (1u << 4) -#define EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz (1u << 5) -#define EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz (1u << 6) -#define EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz (1u << 7) - -#define EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz 1u -#define EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz (1u << 1) -#define EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz (1u << 2) -#define EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz (1u << 3) -#define EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI (1u << 4) -#define EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz (1u << 5) -#define EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz (1u << 6) -#define EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz (1u << 7) - -#define EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz (1u << 7) - -#define EDID_HORIZONTAL_ACCESSIBLE_PIXELS(px) (((px) / 8 - 31) & 0xFF) -#define EDID_ASPECT_RATIO_16_10 0u -#define EDID_ASPECT_RATIO_4_3 (1u << 6) -#define EDID_ASPECT_RATIO_5_4 (2u << 6) -#define EDID_ASPECT_RATIO_16_9 (3u << 6) -#define EDID_FIELD_REFRESH_RATE(hz) (((hz) - 60) & 0x1f) - -#define EDID_PIXEL_CLOCK(v) (((v) / 10000) & 0xFFFF) - -#define EDID_RAW_DEFAULT_PARAMS .header = EDID_HEADER_RAW, \ - .edid_version = 1, \ - .edid_revision = 4, \ - .manufacturer_id = EDID_MANUFACTURER_ID, \ - .product_code = EDID_PRODUCT_CODE, \ - .serial_number = EDID_SERIAL_NUMBER, \ - .manufacture_week = EDID_MANUFACTURE_NO_WEEK, \ - .manufacture_year = EDID_MANUFACTURE_YEAR, \ - .color_characteristics = { \ - EDID_COLOR_RG_XY, \ - EDID_COLOR_BW_XY, \ - EDID_COLOR_R_X92, \ - EDID_COLOR_R_Y92, \ - EDID_COLOR_G_X92, \ - EDID_COLOR_G_Y92, \ - EDID_COLOR_B_X92, \ - EDID_COLOR_B_Y92, \ - EDID_COLOR_W_X92, \ - EDID_COLOR_W_Y92, \ - } diff --git a/tests/include/tests/lib/cbfs_util.h b/tests/include/tests/lib/cbfs_util.h index 8475946382..64096d285f 100644 --- a/tests/include/tests/lib/cbfs_util.h +++ b/tests/include/tests/lib/cbfs_util.h @@ -44,9 +44,6 @@ struct cbfs_test_file { #define HASH_ATTR_SIZE (offsetof(struct cbfs_file_attr_hash, hash.raw) + VB2_SHA256_DIGEST_SIZE) -/* This macro basically does nothing but suppresses linter messages */ -#define EMPTY_WRAP(...) __VA_ARGS__ - #define TEST_DATA_1_FILENAME "test/data/1" #define TEST_DATA_1_SIZE sizeof((u8[]){TEST_DATA_1}) #define TEST_DATA_1 EMPTY_WRAP( \ diff --git a/tests/include/tests/lib/edid.h b/tests/include/tests/lib/edid.h new file mode 100644 index 0000000000..7d59ed4bc1 --- /dev/null +++ b/tests/include/tests/lib/edid.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TESTS_LIB_EDID_H +#define TESTS_LIB_EDID_H + +#include +#include + + +struct edid_raw { + uint8_t header[8]; + + /* Display product identification */ + uint16_t manufacturer_id; + uint16_t product_code; + uint32_t serial_number; + uint8_t manufacture_week; + uint8_t manufacture_year; + + /* EDID version information */ + uint8_t edid_version; + uint8_t edid_revision; + + /* Basic display parameters */ + uint8_t video_input_type; + uint8_t horizontal_size; /* [cm] */ + uint8_t vertical_size; /* [cm] */ + uint8_t display_gamma; + uint8_t supported_features; + + /* Color space definition */ + uint8_t color_characteristics[10]; + + /* Timing information */ + uint8_t established_supported_timings[2]; + uint8_t manufacturers_reserved_timing; + uint8_t standard_timings_supported[16]; + uint8_t descriptor_block_1[18]; + uint8_t descriptor_block_2[18]; + uint8_t descriptor_block_3[18]; + uint8_t descriptor_block_4[18]; + + /* Number of optional 128-byte extension blocks */ + uint8_t extension_flag; + + uint8_t checksum; +} __packed; + +_Static_assert(sizeof(struct edid_raw) == 128, "assert failed: edid_raw size mismatch"); + +#define EDID_HEADER_RAW \ + { \ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 \ + } +#define EDID_HEADER_INVALID_RAW \ + { \ + 0, 0, 0, 0, 0, 0, 0, 0 \ + } + +#define EDID_MANUFACTURER_ID 0xcb55 +#define EDID_MANUFACTURER_NAME "UNK" +#define EDID_PRODUCT_CODE 0x1234 +#define EDID_SERIAL_NUMBER 0x56789ABC +#define EDID_MANUFACTURE_WEEK 23u +#define EDID_MANUFACTURE_NO_WEEK 0u +#define EDID_MANUFACTURE_YEAR (2015u - 1990u) + +/* Video Input Definition for Analog Video Signal Interface */ +#define EDID_ANALOG_VSI (0u << 7) +#define EDID_SIGNAL_LEVEL_0 0u +#define EDID_SIGNAL_LEVEL_1 (1u << 5) +#define EDID_SIGNAL_LEVEL_2 (2u << 5) +#define EDID_SIGNAL_LEVEL_3 (3u << 5) +#define EDID_VIDEO_SETUP_BLANK_EQ_BLACK 0u +#define EDID_VIDEO_SETUP_BLANK_TO_BLACK (1u << 4) +#define EDID_SEPARATE_SYNC_H_AND_V(v) ((v != 0 ? 0x1 : 0x0) << 3) +#define EDID_COMPOSITE_SYNC_H(v) ((v != 0 ? 0x1 : 0x0) << 2) +#define EDID_COMPOSITE_SYNC_ON_GREEN(v) ((v != 0 ? 0x1 : 0x0) << 1) +#define EDID_SERRATION_VSYNC(v) (v != 0 ? 0x1 : 0x0) + +/* Video Input Definition for Digital Video Signal Interface */ +#define EDID_DIGITAL_VSI (1u << 7) +#define EDID_COLOR_BIT_DEPTH_UNDEFINED 0u +#define EDID_COLOR_BIT_DEPTH_6B (1u << 4) +#define EDID_COLOR_BIT_DEPTH_8B (2u << 4) +#define EDID_COLOR_BIT_DEPTH_10B (3u << 4) +#define EDID_COLOR_BIT_DEPTH_12B (4u << 4) +#define EDID_COLOR_BIT_DEPTH_14B (5u << 4) +#define EDID_COLOR_BIT_DEPTH_16B (6u << 4) +#define EDID_INTERFACE_UNDEFINED 0u +#define EDID_INTERFACE_DVI 1u +#define EDID_INTERFACE_HDMI_A 2u +#define EDID_INTERFACE_HDMI_B 3u +#define EDID_INTERFACE_MDDI 4u +#define EDID_INTERFACE_DP 5u + +/* BEGIN Supported features */ +#define EDID_STANDBY_MODE(v) ((v != 0 ? 0x1 : 0x0) << 7) +#define EDID_SUSPEND_MODE(v) ((v != 0 ? 0x1 : 0x0) << 6) +#define EDID_ACTIVE_OFF(v) ((v != 0 ? 0x1 : 0x0) << 5) +/* For analog interface */ +#define EDID_COLOR_TYPE_MONO 0u +#define EDID_COLOR_TYPE_RGB (1u << 3) +#define EDID_COLOR_TYPE_NON_RGB (2u << 3) +#define EDID_COLOR_TYPE_UNDEFINED (3u << 3) +/* For digital interface */ +#define EDID_COLOR_FORMAT_RGB444 0u +#define EDID_COLOR_FORMAT_RGB444_YCRCB444 (1u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422 (2u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 (3u << 3) + +#define EDID_SRGB_SUPPORTED(v) (((v) == 0 ? 0u : 1u) << 2) +#define EDID_PREFERRED_TIMING_EXTENDED_INFO (1u << 1) +#define EDID_PREFERRED_TIMING_NO_EXTENDED_INFO 0u +#define EDID_DISPLAY_FREQUENCY_CONTINUOUS 1u +#define EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS 0u +/* END Supported features */ + +/* Red X 0.640 */ +#define EDID_COLOR_R_X 0x25 +/* Red Y 0.330 */ +#define EDID_COLOR_R_Y 0x152 +/* Green X 0.300 */ +#define EDID_COLOR_G_X 0x13a +/* Green Y 0.600 */ +#define EDID_COLOR_G_Y 0x267 +/* Blue X 0.150 */ +#define EDID_COLOR_B_X 0x9a +/* Blue Y 0.060 */ +#define EDID_COLOR_B_Y 0x3e +/* White X 0.3125 */ +#define EDID_COLOR_W_X 0xa +/* White Y 0.3291 */ +#define EDID_COLOR_W_Y 0x22a + +/* 1 and 0 bits of each color */ +#define EDID_COLOR_R_X10_Y10 (((EDID_COLOR_R_X & 0x3) << 2) | (EDID_COLOR_R_Y & 0x3)) +#define EDID_COLOR_G_X10_Y10 (((EDID_COLOR_G_X & 0x3) << 2) | (EDID_COLOR_G_Y & 0x3)) +#define EDID_COLOR_B_X10_Y10 (((EDID_COLOR_B_X & 0x3) << 2) | (EDID_COLOR_B_Y & 0x3)) +#define EDID_COLOR_W_X10_Y10 (((EDID_COLOR_W_X & 0x3) << 2) | (EDID_COLOR_W_Y & 0x3)) + +/* Concatenated 0 and 1 bits of each color. To be put + * as first and second byte of color characteristic. */ +#define EDID_COLOR_RG_XY ((EDID_COLOR_R_X10_Y10 << 4) | EDID_COLOR_G_X10_Y10) +#define EDID_COLOR_BW_XY ((EDID_COLOR_B_X10_Y10 << 4) | EDID_COLOR_W_X10_Y10) + +/* Bits 9 through 2 of each color */ +#define EDID_COLOR_R_X92 (EDID_COLOR_R_X >> 2) +#define EDID_COLOR_R_Y92 (EDID_COLOR_R_Y >> 2) +#define EDID_COLOR_G_X92 (EDID_COLOR_G_X >> 2) +#define EDID_COLOR_G_Y92 (EDID_COLOR_G_Y >> 2) +#define EDID_COLOR_B_X92 (EDID_COLOR_B_X >> 2) +#define EDID_COLOR_B_Y92 (EDID_COLOR_B_Y >> 2) +#define EDID_COLOR_W_X92 (EDID_COLOR_W_X >> 2) +#define EDID_COLOR_W_Y92 (EDID_COLOR_W_Y >> 2) + +#define EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz 1u +#define EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz (1u << 7) + +#define EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz 1u +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz (1u << 7) + +#define EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz (1u << 7) + +#define EDID_HORIZONTAL_ACCESSIBLE_PIXELS(px) (((px) / 8 - 31) & 0xFF) +#define EDID_ASPECT_RATIO_16_10 0u +#define EDID_ASPECT_RATIO_4_3 (1u << 6) +#define EDID_ASPECT_RATIO_5_4 (2u << 6) +#define EDID_ASPECT_RATIO_16_9 (3u << 6) +#define EDID_FIELD_REFRESH_RATE(hz) (((hz)-60) & 0x1f) + +#define EDID_PIXEL_CLOCK(v) (((v) / 10000) & 0xFFFF) + +#define EDID_RAW_DEFAULT_PARAMS \ + .header = EDID_HEADER_RAW, .edid_version = 1, .edid_revision = 4, \ + .manufacturer_id = EDID_MANUFACTURER_ID, .product_code = EDID_PRODUCT_CODE, \ + .serial_number = EDID_SERIAL_NUMBER, .manufacture_week = EDID_MANUFACTURE_NO_WEEK, \ + .manufacture_year = EDID_MANUFACTURE_YEAR, \ + .color_characteristics = { \ + EDID_COLOR_RG_XY, EDID_COLOR_BW_XY, EDID_COLOR_R_X92, EDID_COLOR_R_Y92, \ + EDID_COLOR_G_X92, EDID_COLOR_G_Y92, EDID_COLOR_B_X92, EDID_COLOR_B_Y92, \ + EDID_COLOR_W_X92, EDID_COLOR_W_Y92, \ + } + +#endif /* TESTS_LIB_EDID_H */ diff --git a/tests/include/tests/test.h b/tests/include/tests/test.h index 523f8fafe9..45b542ed9f 100644 --- a/tests/include/tests/test.h +++ b/tests/include/tests/test.h @@ -14,6 +14,9 @@ #include #include +/* This macro basically does nothing but suppresses linter messages */ +#define EMPTY_WRAP(...) __VA_ARGS__ + /* * Set symbol value and make it global. */ diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 0aba0f5513..9a624767ca 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only +tests-y += lib-test tests-y += string-test tests-y += b64_decode-test tests-y += hexstrtobin-test @@ -40,6 +41,8 @@ tests-y += cbfs-lookup-no-mcache-test tests-y += cbfs-lookup-has-mcache-test tests-y += lzma-test +lib-test-srcs += tests/lib/lib-test.c + string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -138,6 +141,7 @@ bootmem-test-srcs += src/lib/bootmem.c bootmem-test-srcs += src/lib/memrange.c dimm_info_util-test-srcs += tests/lib/dimm_info_util-test.c +dimm_info_util-test-srcs += src/device/dram/spd.c dimm_info_util-test-srcs += src/lib/dimm_info_util.c dimm_info_util-test-srcs += tests/stubs/console.c diff --git a/tests/lib/cbfs-lookup-test.c b/tests/lib/cbfs-lookup-test.c index 27abca3bd5..63a8298cf7 100644 --- a/tests/lib/cbfs-lookup-test.c +++ b/tests/lib/cbfs-lookup-test.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -11,8 +12,8 @@ static struct cbfs_boot_device cbd; -static u8 aligned_cbfs_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT) * 10] - __aligned(CBFS_ALIGNMENT); +static u8 aligned_cbfs_buffer[(sizeof(struct cbfs_test_file) + CBFS_ALIGNMENT) * 10] __aligned( + CBFS_ALIGNMENT); static u8 *unaligned_cbfs_buffer = &aligned_cbfs_buffer[3]; static uintptr_t unaligned_cbfs_buffer_size = sizeof(aligned_cbfs_buffer) - 3; @@ -21,7 +22,7 @@ static u8 cbfs_mcache[TEST_MCACHE_SIZE] __aligned(CBFS_MCACHE_ALIGNMENT); /* Add files to CBFS buffer. NULL in files list equals to one CBFS_ALIGNMENT of spacing. */ static int create_cbfs(const struct cbfs_test_file *files[], const size_t nfiles, u8 *buffer, - const size_t buffer_size) + const size_t buffer_size) { u8 *data_ptr = buffer; size_t file_size = 0; @@ -33,7 +34,7 @@ static int create_cbfs(const struct cbfs_test_file *files[], const size_t nfiles assert_true(&data_ptr[file_size] < &buffer[buffer_size]); } else { file_size = be32_to_cpu(files[i]->header.len) - + be32_to_cpu(files[i]->header.offset); + + be32_to_cpu(files[i]->header.offset); assert_true(&data_ptr[file_size] < &buffer[buffer_size]); memcpy(data_ptr, files[i], file_size); } @@ -385,7 +386,8 @@ static void test_cbfs_image_not_aligned(void **state) size_t size_out; struct cbfs_test_state *s = *state; const struct cbfs_test_file *cbfs_files[] = { - &test_file_int_1, &test_file_2, + &test_file_int_1, + &test_file_2, }; assert_int_equal(0, create_cbfs(cbfs_files, ARRAY_SIZE(cbfs_files), &s->cbfs_buf[5], s->cbfs_size - 5)); @@ -662,8 +664,9 @@ static void test_cbfs_two_files_with_same_name(void **state) size_out = 0; expect_lookup_result(CB_SUCCESS); mapping = cbfs_map(TEST_DATA_INT_1_FILENAME, &size_out); - assert_ptr_equal(mapping, &s->cbfs_buf[third_file_start - + be32_to_cpu(test_file_int_1.header.offset)]); + assert_ptr_equal( + mapping, + &s->cbfs_buf[third_file_start + be32_to_cpu(test_file_int_1.header.offset)]); assert_int_equal(size_out, be32_to_cpu(test_file_int_1.header.len)); } @@ -722,9 +725,8 @@ static void test_cbfs_attributes_offset_larger_than_offset(void **state) assert_true(be32_to_cpu(test_file_2.header.attributes_offset) != 0); memcpy(s->cbfs_buf, &test_file_2, sizeof(test_file_2)); f = (struct cbfs_test_file *)s->cbfs_buf; - f->header.attributes_offset = cpu_to_be32( - sizeof(struct cbfs_file) + FILENAME_SIZE - + sizeof(struct cbfs_file_attr_compression)); + f->header.attributes_offset = cpu_to_be32(sizeof(struct cbfs_file) + FILENAME_SIZE + + sizeof(struct cbfs_file_attr_compression)); f->header.offset = cpu_to_be32(sizeof(struct cbfs_file) + FILENAME_SIZE); assert_int_equal(CB_SUCCESS, cbfs_init_boot_device(&cbd, NULL)); @@ -942,8 +944,9 @@ static void test_cbfs_attributes_offset_uint32_max(void **state) EMPTY_WRAP( \ CBFS_LOOKUP_NAME_SETUP_PRESTATE_COMMON_TEST( \ ("aligned, " name), (test_fn), setup_test_cbfs_aligned, (prestate)), \ - CBFS_LOOKUP_NAME_SETUP_PRESTATE_COMMON_TEST( \ - ("unaligned, " name), (test_fn), setup_test_cbfs_unaligned, (prestate))) + CBFS_LOOKUP_NAME_SETUP_PRESTATE_COMMON_TEST(("unaligned, " name), (test_fn), \ + setup_test_cbfs_unaligned, \ + (prestate))) #define CBFS_LOOKUP_TEST(test_fn) CBFS_LOOKUP_NAME_PRESTATE_TEST(#test_fn, test_fn, NULL) diff --git a/tests/lib/cbfs-verification-test.c b/tests/lib/cbfs-verification-test.c index 3f3573961f..1f46c7d983 100644 --- a/tests/lib/cbfs-verification-test.c +++ b/tests/lib/cbfs-verification-test.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/tests/lib/cbmem_console-test.c b/tests/lib/cbmem_console-test.c index fca84a7bd4..a5ca3b0933 100644 --- a/tests/lib/cbmem_console-test.c +++ b/tests/lib/cbmem_console-test.c @@ -47,10 +47,11 @@ void test_cbmemc_tx_byte(void **state) { int i; u32 cursor; - const unsigned char data[] = "Random testing string\n" - "`1234567890-=~!@#$%^&*()_+\n" - "abcdefghijklmnopqrstuvwxyz\n" - "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n"; + const unsigned char data[] = + "Random testing string\n" + "`1234567890-=~!@#$%^&*()_+\n" + "abcdefghijklmnopqrstuvwxyz\n" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n"; for (i = 0; i < ARRAY_SIZE(data); ++i) cbmemc_tx_byte(data[i]); @@ -69,15 +70,16 @@ void test_cbmemc_tx_byte_overflow(void **state) u32 cursor; u32 flags; const uint32_t console_size = current_console->size; - const unsigned char data[] = "Another random string\n" - "abcdefghijklmnopqrstuvwxyz\n" - "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n" - "`1234567890-=~!@#$%^&*()_+\n"; + const unsigned char data[] = + "Another random string\n" + "abcdefghijklmnopqrstuvwxyz\n" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n" + "`1234567890-=~!@#$%^&*()_+\n"; const int data_size = ARRAY_SIZE(data) - 1; const int data_stream_length = console_size + data_size; const int overflow_bytes = data_stream_length % console_size; unsigned char *check_buffer = - (unsigned char *)malloc(sizeof(unsigned char) * console_size); + (unsigned char *)malloc(sizeof(unsigned char) * console_size); /* Fill console buffer */ for (i = 0; i < console_size; ++i) @@ -102,16 +104,13 @@ void test_cbmemc_tx_byte_overflow(void **state) assert_int_equal(data_size, cursor); /* Check if overflow buffer was overwritten */ - assert_memory_not_equal(current_console->body, - data, - overflow_bytes); + assert_memory_not_equal(current_console->body, data, overflow_bytes); /* Check if rest of the buffer contents, that should not be overridden, * is the same. */ assert_memory_equal(¤t_console->body[overflow_bytes], - check_buffer + overflow_bytes, - console_size - overflow_bytes); + check_buffer + overflow_bytes, console_size - overflow_bytes); free(check_buffer); } @@ -120,10 +119,10 @@ int main(void) { const struct CMUnitTest tests[] = { cmocka_unit_test_teardown(test_cbmemc_init, teardown_cbmemc), - cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte, - setup_cbmemc, teardown_cbmemc), - cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte_overflow, - setup_cbmemc, teardown_cbmemc), + cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte, setup_cbmemc, + teardown_cbmemc), + cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte_overflow, setup_cbmemc, + teardown_cbmemc), }; return cb_run_group_tests(tests, NULL, NULL); diff --git a/tests/lib/cbmem_stage_cache-test.c b/tests/lib/cbmem_stage_cache-test.c index 8a07e6fabe..7256a270c1 100644 --- a/tests/lib/cbmem_stage_cache-test.c +++ b/tests/lib/cbmem_stage_cache-test.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #define CBMEM_SIZE (32 * KiB) @@ -180,14 +180,14 @@ void test_stage_cache_load_stage(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_stage_cache_add, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_stage_cache_add_raw, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_stage_cache_get_raw, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_stage_cache_load_stage, - setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_add, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_add_raw, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_get_raw, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_load_stage, setup_test, + teardown_test), }; return cb_run_group_tests(tests, NULL, NULL); diff --git a/tests/lib/compute_ip_checksum-test.c b/tests/lib/compute_ip_checksum-test.c index 18e7ff0f84..d465bfc4d0 100644 --- a/tests/lib/compute_ip_checksum-test.c +++ b/tests/lib/compute_ip_checksum-test.c @@ -7,12 +7,9 @@ #include static const uint8_t test_data_simple[] = { - 0x64, 0x3b, 0x33, 0x17, 0x34, 0x74, 0x62, 0x30, - 0x75, 0x73, 0xf3, 0x11, 0x30, 0x2c, 0x34, 0x35, - 0x6d, 0x39, 0x69, 0x32, 0x23, 0x24, 0x76, 0x71, - 0x77, 0x30, 0x39, 0x75, 0x76, 0x35, 0x71, 0x32, - 0x40, 0x46, 0x34, 0x34, 0xBB, 0x03, 0x66, 0x52 -}; + 0x64, 0x3b, 0x33, 0x17, 0x34, 0x74, 0x62, 0x30, 0x75, 0x73, 0xf3, 0x11, 0x30, 0x2c, + 0x34, 0x35, 0x6d, 0x39, 0x69, 0x32, 0x23, 0x24, 0x76, 0x71, 0x77, 0x30, 0x39, 0x75, + 0x76, 0x35, 0x71, 0x32, 0x40, 0x46, 0x34, 0x34, 0xBB, 0x03, 0x66, 0x52}; static const size_t test_data_simple_sz = ARRAY_SIZE(test_data_simple); static const unsigned long test_data_simple_checksum = 0x4267; @@ -81,7 +78,7 @@ static void test_add_ip_checksums(void **state) { unsigned long res_1 = compute_ip_checksum(test_data_simple, test_data_simple_sz / 2); unsigned long res_2 = compute_ip_checksum(test_data_simple + test_data_simple_sz / 2, - test_data_simple_sz / 2); + test_data_simple_sz / 2); unsigned long res_sum = add_ip_checksums(test_data_simple_sz / 2, res_1, res_2); assert_int_equal(test_data_simple_checksum, res_sum); diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 7668941243..f9d963de2d 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -43,11 +43,10 @@ static struct lb_record *lb_first_record(struct lb_header *header) return rec; } -#define LB_RECORD_FOR_EACH(record_ptr, index, header) \ - for (index = 0, record_ptr = lb_first_record(header); \ - index < header->table_entries; \ - record_ptr = (struct lb_record *)((uintptr_t)record_ptr \ - + record_ptr->size), index++) +#define LB_RECORD_FOR_EACH(record_ptr, index, header) \ + for (index = 0, record_ptr = lb_first_record(header); index < header->table_entries; \ + record_ptr = (struct lb_record *)((uintptr_t)record_ptr + record_ptr->size), \ + index++) static void test_lb_add_gpios(void **state) { @@ -77,7 +76,7 @@ static void test_lb_add_gpios(void **state) assert_int_equal(sizeof(gpios) + 2 * sizeof(gpios[0]), gpios_table->size); assert_memory_equal(&gpios_table->gpios[0], gpios, sizeof(gpios)); assert_memory_equal(&gpios_table->gpios[ARRAY_SIZE(gpios)], &gpios[1], - 2 * sizeof(gpios[0])); + 2 * sizeof(gpios[0])); } uint8_t tables_buffer[sizeof(struct lb_header) + 10 * KiB]; @@ -169,20 +168,18 @@ static void test_write_coreboot_forwarding_table(void **state) uint8_t forwarding_table_buffer[sizeof(struct lb_header) + 2 * sizeof(struct lb_forward)]; struct lb_header *forward_header = - (struct lb_header *)ALIGN_UP((uintptr_t)forwarding_table_buffer, 16); - size_t forwarding_table_size = - write_coreboot_forwarding_table((uintptr_t)forwarding_table_buffer, - (uintptr_t)header); - size_t expected_forwarding_table_size = ALIGN_UP((uintptr_t)forwarding_table_buffer, 16) - + sizeof(struct lb_header) - + sizeof(struct lb_forward) - - (uintptr_t)forwarding_table_buffer; + (struct lb_header *)ALIGN_UP((uintptr_t)forwarding_table_buffer, 16); + size_t forwarding_table_size = write_coreboot_forwarding_table( + (uintptr_t)forwarding_table_buffer, (uintptr_t)header); + size_t expected_forwarding_table_size = + ALIGN_UP((uintptr_t)forwarding_table_buffer, 16) + sizeof(struct lb_header) + + sizeof(struct lb_forward) - (uintptr_t)forwarding_table_buffer; assert_int_equal(expected_forwarding_table_size, forwarding_table_size); assert_int_equal(1, forward_header->table_entries); assert_int_equal(sizeof(struct lb_forward), forward_header->table_bytes); assert_ptr_equal(header, - ((struct lb_forward *)lb_first_record(forward_header))->forward); + ((struct lb_forward *)lb_first_record(forward_header))->forward); } /* Mocks for write_tables() */ @@ -214,8 +211,8 @@ void arch_write_tables(uintptr_t coreboot_table) } struct resource mock_bootmem_ranges[] = { - { .base = 0x1000, .size = 0x2000, .flags = LB_MEM_RAM }, - { .base = 0x0000, .size = 0x4000, .flags = LB_MEM_RAM }, + {.base = 0x1000, .size = 0x2000, .flags = LB_MEM_RAM}, + {.base = 0x0000, .size = 0x4000, .flags = LB_MEM_RAM}, }; void bootmem_write_memory_table(struct lb_memory *mem) @@ -346,14 +343,15 @@ static void test_write_tables(void **state) /* At least one entry should be present. */ assert_int_not_equal(0, header->table_entries); - LB_RECORD_FOR_EACH(record, i, header) { + LB_RECORD_FOR_EACH(record, i, header) + { switch (record->tag) { case LB_TAG_MEMORY: /* Should be the same as in bootmem_write_memory_table() */ assert_int_equal(sizeof(struct lb_memory) - + ARRAY_SIZE(mock_bootmem_ranges) - * sizeof(struct lb_memory_range), - record->size); + + ARRAY_SIZE(mock_bootmem_ranges) + * sizeof(struct lb_memory_range), + record->size); const struct lb_memory *memory = (struct lb_memory *)record; const struct lb_memory_range *range; @@ -366,38 +364,45 @@ static void test_write_tables(void **state) value = pack_lb64(res->base); assert_memory_equal(&value, &range->start, - sizeof(struct lb_uint64)); + sizeof(struct lb_uint64)); value = pack_lb64(res->size); assert_memory_equal(&value, &range->size, - sizeof(struct lb_uint64)); + sizeof(struct lb_uint64)); assert_int_equal(range->type, res->flags); } break; case LB_TAG_MAINBOARD: /* Mainboard record contains its header followed by two null-terminated strings */ - assert_int_equal(ALIGN_UP(sizeof(struct lb_mainboard) + - ARRAY_SIZE(mainboard_vendor) + - ARRAY_SIZE(mainboard_part_number), 8), record->size); + assert_int_equal(ALIGN_UP(sizeof(struct lb_mainboard) + + ARRAY_SIZE(mainboard_vendor) + + ARRAY_SIZE(mainboard_part_number), + 8), + record->size); break; case LB_TAG_VERSION: assert_int_equal(ALIGN_UP(sizeof(struct lb_string) - + ARRAY_SIZE(coreboot_version), 8), record->size); + + ARRAY_SIZE(coreboot_version), + 8), + record->size); break; case LB_TAG_EXTRA_VERSION: assert_int_equal(ALIGN_UP(sizeof(struct lb_string) - + ARRAY_SIZE(coreboot_extra_version), 8), - record->size); + + ARRAY_SIZE(coreboot_extra_version), + 8), + record->size); break; case LB_TAG_BUILD: - assert_int_equal(ALIGN_UP(sizeof(struct lb_string) - + ARRAY_SIZE(coreboot_build), 8), - record->size); + assert_int_equal( + ALIGN_UP(sizeof(struct lb_string) + ARRAY_SIZE(coreboot_build), + 8), + record->size); break; case LB_TAG_COMPILE_TIME: assert_int_equal(ALIGN_UP(sizeof(struct lb_string) - + ARRAY_SIZE(coreboot_compile_time), 8), - record->size); + + ARRAY_SIZE(coreboot_compile_time), + 8), + record->size); break; case LB_TAG_SERIAL: assert_int_equal(sizeof(struct lb_serial), record->size); @@ -428,7 +433,7 @@ static void test_write_tables(void **state) assert_int_equal(sizeof(struct lb_boot_media_params), record->size); const struct lb_boot_media_params *bmp = - (struct lb_boot_media_params *)record; + (struct lb_boot_media_params *)record; const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); const struct region_device *boot_dev = boot_device_ro(); assert_int_equal(region_device_offset(&cbd->rdev), bmp->cbfs_offset); @@ -441,13 +446,11 @@ static void test_write_tables(void **state) assert_int_equal(sizeof(struct lb_cbmem_entry), record->size); const struct lb_cbmem_entry *cbmem_entry = - (struct lb_cbmem_entry *)record; - const LargestIntegralType expected_tags[] = { - CBMEM_ID_CBTABLE, - CBMEM_ID_MMC_STATUS - }; - assert_in_set(cbmem_entry->id, - expected_tags, ARRAY_SIZE(expected_tags)); + (struct lb_cbmem_entry *)record; + const LargestIntegralType expected_tags[] = {CBMEM_ID_CBTABLE, + CBMEM_ID_MMC_STATUS}; + assert_in_set(cbmem_entry->id, expected_tags, + ARRAY_SIZE(expected_tags)); break; case LB_TAG_TSC_INFO: assert_int_equal(sizeof(struct lb_tsc_info), record->size); @@ -465,10 +468,10 @@ static void test_write_tables(void **state) assert_int_equal(sizeof(struct lb_board_config), record->size); const struct lb_board_config *board_config = - (struct lb_board_config *)record; + (struct lb_board_config *)record; const struct lb_uint64 expected_fw_version = pack_lb64(fw_config_get()); - assert_memory_equal(&expected_fw_version, - &board_config->fw_config, sizeof(struct lb_uint64)); + assert_memory_equal(&expected_fw_version, &board_config->fw_config, + sizeof(struct lb_uint64)); assert_int_equal(board_id(), board_config->board_id); assert_int_equal(ram_code(), board_config->ram_code); assert_int_equal(sku_id(), board_config->sku_id); @@ -488,8 +491,7 @@ int main(void) cmocka_unit_test_setup(test_lb_add_console, setup_test_header), cmocka_unit_test_setup(test_multiple_entries, setup_test_header), cmocka_unit_test_setup(test_write_coreboot_forwarding_table, setup_test_header), - cmocka_unit_test_setup_teardown(test_write_tables, - setup_write_tables_test, + cmocka_unit_test_setup_teardown(test_write_tables, setup_write_tables_test, teardown_write_tables_test), }; diff --git a/tests/lib/crc_byte-test.c b/tests/lib/crc_byte-test.c index 86249420c8..16850f033f 100644 --- a/tests/lib/crc_byte-test.c +++ b/tests/lib/crc_byte-test.c @@ -4,38 +4,25 @@ #include static const uint8_t test_data_bytes[] = { - 0x2f, 0x8f, 0x2d, 0x06, 0xc2, 0x11, 0x0c, 0xaf, - 0xd7, 0x4b, 0x48, 0x71, 0xce, 0x3c, 0xfe, 0x29, - 0x90, 0xf6, 0x33, 0x6d, 0x79, 0x23, 0x9d, 0x84, - 0x58, 0x5c, 0xcc, 0xf1, 0xa1, 0xf2, 0x39, 0x22, - 0xdc, 0x63, 0xe0, 0x44, 0x0a, 0x95, 0x36, 0xee, - 0x53, 0xb3, 0x61, 0x2c, 0x4a, 0xf4, 0x8b, 0x32, - 0xeb, 0x94, 0x86, 0x55, 0x41, 0x27, 0xa4, 0xbd, - 0x0f, 0xc1, 0x4f, 0xfb, 0xb6, 0xa3, 0xc5, 0x38, - 0x99, 0xfc, 0xca, 0xf8, 0x8e, 0x72, 0xaa, 0xed, - 0x6b, 0xb2, 0xd3, 0xd4, 0xd6, 0x81, 0x7d, 0x24, - 0x56, 0x9f, 0x7a, 0x21, 0x67, 0xac, 0x6a, 0x98, - 0xf7, 0xd1, 0xad, 0x01, 0xdb, 0xc6, 0x80, 0x34, - 0x8d, 0x51, 0x60, 0x3e, 0xd2, 0x52, 0x0e, 0x26, - 0x12, 0xb1, 0x13, 0xa2, 0x88, 0x04, 0x66, 0xb0, - 0x3b, 0xc8, 0x1b, 0x7f, 0x92, 0x4e, 0xb8, 0xe9, - 0x70, 0xe3, 0xfa, 0x76, 0x3a, 0xa7, 0x4c, 0x25, - 0x91, 0x54, 0x19, 0xea, 0x50, 0x37, 0xd8, 0xb4, - 0x47, 0x49, 0xbf, 0xc4, 0xb7, 0xd0, 0x93, 0xda, - 0x6c, 0x03, 0x9b, 0x15, 0xbb, 0xfd, 0xe7, 0xdd, - 0x2e, 0x31, 0x68, 0x46, 0xa0, 0x43, 0xcd, 0x08, - 0x8c, 0xff, 0x40, 0xcf, 0x1a, 0x7c, 0x69, 0x59, - 0xc0, 0x5b, 0x83, 0x17, 0x10, 0x14, 0x9e, 0x1d, - 0xc3, 0xa6, 0x5f, 0x4d, 0x9c, 0xa5, 0x73, 0x77, - 0x87, 0x96, 0x65, 0x0b, 0xec, 0xc7, 0xd9, 0x85, - 0x1c, 0xae, 0x18, 0x5e, 0x09, 0x78, 0x2b, 0x82, - 0x1f, 0xe6, 0xc9, 0x64, 0x6f, 0x20, 0x16, 0x57, - 0x9a, 0xbe, 0xd5, 0xe2, 0x89, 0x3f, 0xdf, 0xe4, - 0x7e, 0xde, 0x30, 0xa9, 0x74, 0xe5, 0xab, 0x07, - 0x35, 0x5d, 0x2a, 0x28, 0xcb, 0xf0, 0x8a, 0xef, - 0x5a, 0xe1, 0x75, 0x42, 0xf9, 0xba, 0x02, 0xbc, - 0xf5, 0x45, 0x05, 0x0d, 0x3d, 0x62, 0xb9, 0x00, - 0x7b, 0x1e, 0xe8, 0xb5, 0x97, 0x6e, 0xa8, 0xf3, + 0x2f, 0x8f, 0x2d, 0x06, 0xc2, 0x11, 0x0c, 0xaf, 0xd7, 0x4b, 0x48, 0x71, 0xce, 0x3c, + 0xfe, 0x29, 0x90, 0xf6, 0x33, 0x6d, 0x79, 0x23, 0x9d, 0x84, 0x58, 0x5c, 0xcc, 0xf1, + 0xa1, 0xf2, 0x39, 0x22, 0xdc, 0x63, 0xe0, 0x44, 0x0a, 0x95, 0x36, 0xee, 0x53, 0xb3, + 0x61, 0x2c, 0x4a, 0xf4, 0x8b, 0x32, 0xeb, 0x94, 0x86, 0x55, 0x41, 0x27, 0xa4, 0xbd, + 0x0f, 0xc1, 0x4f, 0xfb, 0xb6, 0xa3, 0xc5, 0x38, 0x99, 0xfc, 0xca, 0xf8, 0x8e, 0x72, + 0xaa, 0xed, 0x6b, 0xb2, 0xd3, 0xd4, 0xd6, 0x81, 0x7d, 0x24, 0x56, 0x9f, 0x7a, 0x21, + 0x67, 0xac, 0x6a, 0x98, 0xf7, 0xd1, 0xad, 0x01, 0xdb, 0xc6, 0x80, 0x34, 0x8d, 0x51, + 0x60, 0x3e, 0xd2, 0x52, 0x0e, 0x26, 0x12, 0xb1, 0x13, 0xa2, 0x88, 0x04, 0x66, 0xb0, + 0x3b, 0xc8, 0x1b, 0x7f, 0x92, 0x4e, 0xb8, 0xe9, 0x70, 0xe3, 0xfa, 0x76, 0x3a, 0xa7, + 0x4c, 0x25, 0x91, 0x54, 0x19, 0xea, 0x50, 0x37, 0xd8, 0xb4, 0x47, 0x49, 0xbf, 0xc4, + 0xb7, 0xd0, 0x93, 0xda, 0x6c, 0x03, 0x9b, 0x15, 0xbb, 0xfd, 0xe7, 0xdd, 0x2e, 0x31, + 0x68, 0x46, 0xa0, 0x43, 0xcd, 0x08, 0x8c, 0xff, 0x40, 0xcf, 0x1a, 0x7c, 0x69, 0x59, + 0xc0, 0x5b, 0x83, 0x17, 0x10, 0x14, 0x9e, 0x1d, 0xc3, 0xa6, 0x5f, 0x4d, 0x9c, 0xa5, + 0x73, 0x77, 0x87, 0x96, 0x65, 0x0b, 0xec, 0xc7, 0xd9, 0x85, 0x1c, 0xae, 0x18, 0x5e, + 0x09, 0x78, 0x2b, 0x82, 0x1f, 0xe6, 0xc9, 0x64, 0x6f, 0x20, 0x16, 0x57, 0x9a, 0xbe, + 0xd5, 0xe2, 0x89, 0x3f, 0xdf, 0xe4, 0x7e, 0xde, 0x30, 0xa9, 0x74, 0xe5, 0xab, 0x07, + 0x35, 0x5d, 0x2a, 0x28, 0xcb, 0xf0, 0x8a, 0xef, 0x5a, 0xe1, 0x75, 0x42, 0xf9, 0xba, + 0x02, 0xbc, 0xf5, 0x45, 0x05, 0x0d, 0x3d, 0x62, 0xb9, 0x00, 0x7b, 0x1e, 0xe8, 0xb5, + 0x97, 0x6e, 0xa8, 0xf3, }; static const size_t test_data_bytes_sz = ARRAY_SIZE(test_data_bytes); static const uint8_t test_data_crc7_checksum = 0x30; @@ -191,9 +178,8 @@ static void test_crc16_byte_static_data(void **state) /* Calculating CRC of data with its CRC should yield zero if data and/or checksum is correct */ - assert_int_equal(0, - crc16_byte(crc16_byte(crc_value, test_data_crc16_checksum >> 8), - test_data_crc16_checksum & 0xFF)); + assert_int_equal(0, crc16_byte(crc16_byte(crc_value, test_data_crc16_checksum >> 8), + test_data_crc16_checksum & 0xFF)); } static void test_crc32_byte_zeros(void **state) diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 4b3f979d2b..cecbacbb85 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -4,28 +4,48 @@ #include #include -static void test_smbios_bus_width_to_spd_width(void **state) +#define MAX_ALLOWED_MODULE_TYPE 3 + +static void test_smbios_bus_width_to_spd_width_parametrized(smbios_memory_type ddr_type) { /* Non-ECC variants */ - assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(64, 64)); - assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(32, 32)); - assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(16, 16)); - assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(8, 8)); + assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(ddr_type, 64, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(ddr_type, 32, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(ddr_type, 16, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 8, 8)); /* Incorrect data width. Fallback to 8-bit */ - assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(15, 15)); + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(ddr_type, 15, 15)); /* ECC variants */ - assert_int_equal(MEMORY_BUS_WIDTH_64 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(64 + 8, 64)); - assert_int_equal(MEMORY_BUS_WIDTH_32 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(32 + 8, 32)); - assert_int_equal(MEMORY_BUS_WIDTH_16 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(16 + 8, 16)); - assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(8 + 8, 8)); + uint8_t extension_8bits = SPD_ECC_8BIT; + if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5) + extension_8bits = SPD_ECC_8BIT_LP5_DDR5; + + assert_int_equal(MEMORY_BUS_WIDTH_64 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 64 + 8, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 32 + 8, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 16 + 8, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 8 + 8, 8)); /* Incorrect data width. Fallback to 8-bit */ - assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, - smbios_bus_width_to_spd_width(15 + 8, 15)); + assert_int_equal(MEMORY_BUS_WIDTH_8 | extension_8bits, + smbios_bus_width_to_spd_width(ddr_type, 15 + 8, 15)); +} + +static void test_smbios_bus_width_to_spd_width(void **state) +{ + smbios_memory_type memory_type[] = { + MEMORY_TYPE_DDR2, MEMORY_TYPE_DDR3, MEMORY_TYPE_DDR4, MEMORY_TYPE_DDR5, + MEMORY_TYPE_LPDDR3, MEMORY_TYPE_LPDDR4, MEMORY_TYPE_LPDDR5, + }; + + for (int i = 0; i < ARRAY_SIZE(memory_type); i++) { + print_message("test_smbios_bus_width_to_spd_width_parametrized(%d)\n", + memory_type[i]); + test_smbios_bus_width_to_spd_width_parametrized(memory_type[i]); + } } static void test_smbios_memory_size_to_mib(void **state) @@ -63,43 +83,100 @@ static void test_smbios_memory_size_to_mib(void **state) assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 694735)); } -static void test_smbios_form_factor_to_spd_mod_type(void **state) +static void test_smbios_form_factor_to_spd_mod_type_ddr(smbios_memory_type memory_type) { - /* Form factors defined in coreboot */ - const LargestIntegralType udimm_allowed[] = { - SPD_UDIMM, SPD_MICRO_DIMM, SPD_MINI_UDIMM, - }; - assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_DIMM), - udimm_allowed, ARRAY_SIZE(udimm_allowed)); - - const LargestIntegralType rdimm_allowed[] = { SPD_RDIMM, SPD_MINI_RDIMM }; - assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_RIMM), - rdimm_allowed, ARRAY_SIZE(rdimm_allowed)); - - assert_int_equal(SPD_SODIMM, - smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_SODIMM)); - const smbios_memory_form_factor undefined_factors[] = { - MEMORY_FORMFACTOR_OTHER, - MEMORY_FORMFACTOR_UNKNOWN, - MEMORY_FORMFACTOR_SIMM, - MEMORY_FORMFACTOR_SIP, - MEMORY_FORMFACTOR_CHIP, - MEMORY_FORMFACTOR_DIP, - MEMORY_FORMFACTOR_ZIP, - MEMORY_FORMFACTOR_PROPRIETARY_CARD, - MEMORY_FORMFACTOR_TSOP, - MEMORY_FORMFACTOR_ROC, - MEMORY_FORMFACTOR_SRIMM, - MEMORY_FORMFACTOR_FBDIMM, + MEMORY_FORMFACTOR_OTHER, MEMORY_FORMFACTOR_UNKNOWN, + MEMORY_FORMFACTOR_SIMM, MEMORY_FORMFACTOR_SIP, + MEMORY_FORMFACTOR_CHIP, MEMORY_FORMFACTOR_DIP, + MEMORY_FORMFACTOR_ZIP, MEMORY_FORMFACTOR_PROPRIETARY_CARD, + MEMORY_FORMFACTOR_TSOP, MEMORY_FORMFACTOR_ROC, + MEMORY_FORMFACTOR_SRIMM, MEMORY_FORMFACTOR_FBDIMM, MEMORY_FORMFACTOR_DIE, }; for (int i = 0; i < ARRAY_SIZE(undefined_factors); ++i) { - assert_int_equal(SPD_UNDEFINED, - smbios_form_factor_to_spd_mod_type(undefined_factors[i])); + assert_int_equal(SPD_UNDEFINED, smbios_form_factor_to_spd_mod_type( + memory_type, undefined_factors[i])); } } +static void test_smbios_form_factor_to_spd_mod_type_ddrx_parametrized( + smbios_memory_type memory_type, const LargestIntegralType udimm_allowed[], + const LargestIntegralType rdimm_allowed[], LargestIntegralType expected_module_type) +{ + print_message("%s(%d)\n", __func__, memory_type); + + assert_in_set(smbios_form_factor_to_spd_mod_type(memory_type, MEMORY_FORMFACTOR_DIMM), + udimm_allowed, MAX_ALLOWED_MODULE_TYPE); + + assert_in_set(smbios_form_factor_to_spd_mod_type(memory_type, MEMORY_FORMFACTOR_RIMM), + rdimm_allowed, MAX_ALLOWED_MODULE_TYPE); + + assert_int_equal(expected_module_type, smbios_form_factor_to_spd_mod_type( + memory_type, MEMORY_FORMFACTOR_SODIMM)); + + test_smbios_form_factor_to_spd_mod_type_ddr(memory_type); +} + +static void test_smbios_form_factor_to_spd_mod_type_lpddrx(smbios_memory_type memory_type) +{ + print_message("%s(%d)\n", __func__, memory_type); + /* Form factors defined in coreboot */ + assert_int_equal(LPX_SPD_NONDIMM, smbios_form_factor_to_spd_mod_type( + memory_type, MEMORY_FORMFACTOR_ROC)); +} + +static void test_smbios_form_factor_to_spd_mod_type(void **state) +{ + const struct smbios_form_factor_test_info_ddrx { + smbios_memory_type memory_type; + const LargestIntegralType udimm_allowed[MAX_ALLOWED_MODULE_TYPE]; + const LargestIntegralType rdimm_allowed[MAX_ALLOWED_MODULE_TYPE]; + LargestIntegralType expected_module_type; + } ddrx_info[] = { + { + .memory_type = MEMORY_TYPE_DDR2, + .udimm_allowed = {DDR2_SPD_UDIMM, DDR2_SPD_MICRO_DIMM, + DDR2_SPD_MINI_UDIMM}, + .rdimm_allowed = {DDR2_SPD_RDIMM, DDR2_SPD_MINI_RDIMM}, + .expected_module_type = DDR2_SPD_SODIMM, + }, + { + .memory_type = MEMORY_TYPE_DDR3, + .udimm_allowed = {DDR3_SPD_UDIMM, DDR3_SPD_MICRO_DIMM, + DDR3_SPD_MINI_UDIMM}, + .rdimm_allowed = {DDR3_SPD_RDIMM, DDR3_SPD_MINI_RDIMM}, + .expected_module_type = DDR3_SPD_SODIMM, + }, + { + .memory_type = MEMORY_TYPE_DDR4, + .udimm_allowed = {DDR4_SPD_UDIMM, DDR4_SPD_MINI_UDIMM}, + .rdimm_allowed = {DDR4_SPD_RDIMM, DDR4_SPD_MINI_RDIMM}, + .expected_module_type = DDR4_SPD_SODIMM, + }, + {.memory_type = MEMORY_TYPE_DDR5, + .udimm_allowed = {DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM}, + .rdimm_allowed = {DDR5_SPD_RDIMM, DDR5_SPD_MINI_RDIMM}, + .expected_module_type = DDR5_SPD_SODIMM}, + }; + + /* Test for DDRx DIMM Modules */ + for (int i = 0; i < ARRAY_SIZE(ddrx_info); i++) + test_smbios_form_factor_to_spd_mod_type_ddrx_parametrized( + ddrx_info[i].memory_type, ddrx_info[i].udimm_allowed, + ddrx_info[i].rdimm_allowed, ddrx_info[i].expected_module_type); + + smbios_memory_type lpddrx_memory_type[] = { + MEMORY_TYPE_LPDDR3, + MEMORY_TYPE_LPDDR4, + MEMORY_TYPE_LPDDR5, + }; + + /* Test for Lpddrx DIMM Modules */ + for (int i = 0; i < ARRAY_SIZE(lpddrx_memory_type); i++) + test_smbios_form_factor_to_spd_mod_type_lpddrx(lpddrx_memory_type[i]); +} + int main(void) { const struct CMUnitTest tests[] = { diff --git a/tests/lib/edid-test.c b/tests/lib/edid-test.c index 73ce4ecaf7..5a22e6bd95 100644 --- a/tests/lib/edid-test.c +++ b/tests/lib/edid-test.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include struct test_state { int data_size; @@ -34,22 +34,20 @@ static void test_decode_edid_no_edid(void **state) static void test_decode_edid_invalid_header(void **state) { - struct edid_raw raw = { - .header = EDID_HEADER_INVALID_RAW - }; + struct edid_raw raw = {.header = EDID_HEADER_INVALID_RAW}; raw.checksum = get_raw_edid_checksum((const unsigned char *)&raw); assert_int_equal(EDID_ABSENT, decode_edid((unsigned char *)&raw, sizeof(raw), NULL)); } /* Frame is modified example of an LCD Desktop IT display - * from VESA E-EDID Standard Release A2. - */ + from VESA E-EDID Standard Release A2. */ static int setup_decode_edid_basic_frame(void **state) { struct edid_raw raw = { EDID_RAW_DEFAULT_PARAMS, - .video_input_type = EDID_ANALOG_VSI + .video_input_type = + EDID_ANALOG_VSI | EDID_SIGNAL_LEVEL_0 | EDID_VIDEO_SETUP_BLANK_EQ_BLACK | EDID_SEPARATE_SYNC_H_AND_V(1) @@ -57,9 +55,10 @@ static int setup_decode_edid_basic_frame(void **state) | EDID_COMPOSITE_SYNC_ON_GREEN(1) | EDID_SERRATION_VSYNC(1), .horizontal_size = 43, /* [cm] */ - .vertical_size = 32, /* [cm] */ - .display_gamma = 120, /* 220% */ - .supported_features = EDID_STANDBY_MODE(0) + .vertical_size = 32, /* [cm] */ + .display_gamma = 120, /* 220% */ + .supported_features = + EDID_STANDBY_MODE(0) | EDID_SUSPEND_MODE(0) | EDID_ACTIVE_OFF(1) | EDID_COLOR_FORMAT_RGB444 @@ -68,21 +67,21 @@ static int setup_decode_edid_basic_frame(void **state) | EDID_DISPLAY_FREQUENCY_CONTINUOUS, .established_supported_timings = { [0] = EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz - | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz - | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz - | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz, + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz, [1] = EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz - | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz - | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI - | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz - | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz, + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz, }, .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, .standard_timings_supported = { @@ -114,64 +113,69 @@ static int setup_decode_edid_basic_frame(void **state) [0] = EDID_PIXEL_CLOCK(162000000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(162000000u) >> 8) & 0xFF, - /* - * Horizontal Addressable Video is 1600px - * Horizontal Blanking is 560px - */ - [2] = 0x40, [3] = 0x30, [4] = 0x62, + /* Horizontal Addressable Video is 1600px, + Horizontal Blanking is 560px. */ + [2] = 0x40, + [3] = 0x30, + [4] = 0x62, - /* - * Vertical Addressable Video is 1200 lines - * Vertical Blanking is 50 lines - */ - [5] = 0xB0, [6] = 0x32, [7] = 0x40, + /* Vertical Addressable Video is 1200 lines, + Vertical Blanking is 50 lines. */ + [5] = 0xB0, + [6] = 0x32, + [7] = 0x40, - [8] = 64u, /* Horizontal Front Porch in pixels */ - [9] = 192u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 0x13, /* Vertical Front Porch is 1 line */ - [11] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + [8] = 64u, /* Horizontal Front Porch in pixels. */ + [9] = 192u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 0x13, /* Vertical Front Porch is 1 line. */ + [11] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */ - /* - * Horizontal Addressable Image Size is 427mm - * Vertical Addressable Image Size is 320mm - */ - [12] = 0xAB, [13] = 0x40, [14] = 0x11, + /* Horizontal Addressable Image Size is 427mm, + Vertical Addressable Image Size is 320mm. */ + [12] = 0xAB, + [13] = 0x40, + [14] = 0x11, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal Border Size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ - /* - * Timing is Non-Interlaced Video, - * Stereo Video is not supported, - * Digital separate syncs are requires. - * */ + /* Timing is Non-Interlaced Video, + Stereo Video is not supported, + Digital separate syncs are requires. */ [17] = 0x1E, }, .descriptor_block_2 = { /* Display Range Limits Block Tag */ - [0] = 0, [1] = 0, [2] = 0, [3] = 0xFD, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0xFD, - [4] = 0, /* Horizontal and Vertical Rate Offsets are zero */ - [5] = 50u, /* Minimum Vertical Freq is 50Hz */ - [6] = 90u, /* Maximum Vertical Freq is 90Hz */ + [4] = 0, /* Horizontal and Vertical Rate Offsets are zero. */ + [5] = 50u, /* Minimum Vertical Freq is 50Hz. */ + [6] = 90u, /* Maximum Vertical Freq is 90Hz. */ - [7] = 30u, /* Minimum Horizontal Freq is 30kHz */ - [8] = 110u, /* Maximum Horizontal Freq is 110kHz */ - [9] = 23u, /* Maximum Pixel Clock Freq i 230MHz */ - [10] = 0x4, /* Begin CVT Support Info */ + [7] = 30u, /* Minimum Horizontal Freq is 30kHz. */ + [8] = 110u, /* Maximum Horizontal Freq is 110kHz. */ + [9] = 23u, /* Maximum Pixel Clock Freq is 230MHz. */ + [10] = 0x4, /* Begin CVT Support Info */ [11] = 0x11, /* Compatible with CVT Version 1.1 */ - [12] = 0, /* Maimum Pixel Clock Freq remains at 230MHz */ - [13] = 200, /* Maximum Active Pixels per Pile is 1600 */ - [14] = 0x90, /* Supported aspect ratios: 4:3, 5:4 */ + [12] = 0, /* Maximum Pixel Clock Freq remains at 230MHz. */ + [13] = 200, /* Maximum Active Pixels per Line is 1600. */ + [14] = 0x90, /* Supported aspect ratios: 4:3, 5:4. */ - /* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported */ + /* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported. */ [15] = 0, - [16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not */ - [17] = 60u, /* Preferred Refresh Rate is 60Hz */ + [16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not. */ + [17] = 60u, /* Preferred Refresh Rate is 60Hz. */ }, .descriptor_block_3 = { /* Established Timings III Block Tag */ - [0] = 0, [1] = 0, [2] = 0, [3] = 0xF7, [4] = 0, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0xF7, + [4] = 0, [5] = 10u, /* VESA DMT Standard Version #10 */ /* @@ -181,7 +185,7 @@ static int setup_decode_edid_basic_frame(void **state) * 640x480@85Hz, * 800x600@85Hz, * 1024x768@85Hz, - * 1152x864@75Hz + * 1152x864@75Hz are supported. */ [6] = 0x7F, @@ -189,7 +193,7 @@ static int setup_decode_edid_basic_frame(void **state) * 1280x960@60Hz, * 1280x960@85Hz, * 1280x1024@60Hz, - * 1280x1024@85Hz + * 1280x1024@85Hz are supported. */ [7] = 0x0F, @@ -213,14 +217,18 @@ static int setup_decode_edid_basic_frame(void **state) */ [10] = 0xC0, - /* 1920 timings not supported */ + /* 1920 timings not supported. */ [11] = 0x0, [12 ... 17] = 0, }, .descriptor_block_4 = { /* Display Product Name Block Tag */ - [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0xFC, + [4] = 0, /* Product name */ [5] = 'A', @@ -244,10 +252,8 @@ static int setup_decode_edid_basic_frame(void **state) *state = malloc(sizeof(struct test_state)); - struct test_state ts = { - .data_size = sizeof(struct edid_raw), - .data = malloc(sizeof(struct edid_raw)) - }; + struct test_state ts = {.data_size = sizeof(struct edid_raw), + .data = malloc(sizeof(struct edid_raw))}; memcpy(ts.data, &raw, sizeof(raw)); memcpy(*state, &ts, sizeof(ts)); @@ -255,18 +261,16 @@ static int setup_decode_edid_basic_frame(void **state) return 0; } -/* Test decoding of EDID frame without extensions. - */ +/* Test decoding of EDID frame without extensions. */ static void test_decode_edid_basic_frame(void **state) { struct edid out; struct test_state *ts = *state; /* In real-life situations frames often are not 100% conformant, - * but are at least correct when it comes to key data fields. - */ + but are at least correct when it comes to key data fields. */ assert_int_equal(EDID_CONFORMANT, - decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); assert_int_equal(32, out.framebuffer_bits_per_pixel); assert_int_equal(0, out.panel_bits_per_color); @@ -305,19 +309,20 @@ static void test_decode_edid_basic_frame(void **state) } /* Frame is modified example of base EDID frame with CEA861 extension - * for DTV Display from VESA E-EDID Standard Release A2. - */ + for DTV Display from VESA E-EDID Standard Release A2. */ static int setup_decode_edid_dtv_frame_with_extension(void **state) { struct edid_raw raw = { EDID_RAW_DEFAULT_PARAMS, - .video_input_type = EDID_DIGITAL_VSI + .video_input_type = + EDID_DIGITAL_VSI | EDID_INTERFACE_HDMI_A | EDID_COLOR_BIT_DEPTH_8B, - .horizontal_size = 16, /* Aspect ratio 16:9 in landscape */ - .vertical_size = 0, /* Landscape flag */ - .display_gamma = 120, /* 220% */ - .supported_features = EDID_STANDBY_MODE(0) + .horizontal_size = 16, /* Aspect ratio 16:9 in landscape. */ + .vertical_size = 0, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = + EDID_STANDBY_MODE(0) | EDID_SUSPEND_MODE(0) | EDID_ACTIVE_OFF(0) | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 @@ -330,109 +335,121 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) [1] = 0, }, .manufacturers_reserved_timing = 0, - .standard_timings_supported = { [0 ... 15] = 0, }, + .standard_timings_supported = { + [0 ... 15] = 0, + }, .descriptor_block_1 = { [0] = EDID_PIXEL_CLOCK(148500000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(148500000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1920px - * Horizontal Blanking is 280px - */ - [2] = 0x80, [3] = 0x18, [4] = 0x71, + /* Horizontal Addressable Video is 1920px, + Horizontal Blanking is 280px. */ + [2] = 0x80, + [3] = 0x18, + [4] = 0x71, - /* Vertical Addressable Video is 1080 lines - * Vertical Blanking is 45 lines - */ - [5] = 0x38, [6] = 0x2D, [7] = 0x40, + /* Vertical Addressable Video is 1080 lines, + Vertical Blanking is 45 lines. */ + [5] = 0x38, + [6] = 0x2D, + [7] = 0x40, - [8] = 88u, /* Horizontal Front Porch in pixels */ - [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 4u, /* Vertical Front Porch is 4 lines */ - [11] = 5u, /* Vertical Sync Pulse Width is 5 lines */ + [8] = 88u, /* Horizontal Front Porch in pixels. */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 4u, /* Vertical Front Porch is 4 lines. */ + [11] = 5u, /* Vertical Sync Pulse Width is 5 lines. */ - /* Horizontal Addressable Image Size is 1039mm - * Vertical Addressable Image Size is 584mm - */ - [12] = 0x0F, [13] = 0x48, [14] = 0x42, + /* Horizontal Addressable Image Size is 1039mm, + Vertical Addressable Image Size is 584mm. */ + [12] = 0x0F, + [13] = 0x48, + [14] = 0x42, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal Border Size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ /* Timing is Non-Interlaced Video, - * Stereo Video is not supported, - * Digital separate and syncs are requires. - */ + Stereo Video is not supported, + Digital separate and syncs are requires. */ [17] = 0x1E, }, .descriptor_block_2 = { [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1920px - * Horizontal Blanking is 280px - */ - [2] = 0x80, [3] = 0x18, [4] = 0x71, + /* Horizontal Addressable Video is 1920px, + Horizontal Blanking is 280px. */ + [2] = 0x80, + [3] = 0x18, + [4] = 0x71, - /* Vertical Addressable Video is 540 lines - * Vertical Blanking is 22 lines - */ - [5] = 0x1C, [6] = 0x16, [7] = 0x20, + /* Vertical Addressable Video is 540 lines, + Vertical Blanking is 22 lines. */ + [5] = 0x1C, + [6] = 0x16, + [7] = 0x20, - [8] = 88u, /* Horizontal Front Porch in pixels */ - [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 0x25, /* Vertical Front Porch is 2 lines */ - [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + [8] = 88u, /* Horizontal Front Porch in pixels. */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 0x25, /* Vertical Front Porch is 2 lines. */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */ - /* Horizontal Addressable Image Size is 1039mm - * Vertical Addressable Image Size is 584mm - */ - [12] = 0x0F, [13] = 0x48, [14] = 0x42, + /* Horizontal Addressable Image Size is 1039mm, + Vertical Addressable Image Size is 584mm. */ + [12] = 0x0F, + [13] = 0x48, + [14] = 0x42, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal Border Size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ /* Timing is Interlaced Video, - * Stereo Video is not supported, - * Digital separate and syncs are requires. - */ + Stereo Video is not supported, + Digital separate and syncs are requires. */ [17] = 0x9E, }, .descriptor_block_3 = { [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1280px - * Horizontal Blanking is 370px - */ - [2] = 0x00, [3] = 0x72, [4] = 0x51, + /* Horizontal Addressable Video is 1280px, + Horizontal Blanking is 370px. */ + [2] = 0x00, + [3] = 0x72, + [4] = 0x51, - /* Vertical Addressable Video is 720 lines - * Vertical Blanking is 30 lines - */ - [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + /* Vertical Addressable Video is 720 lines, + Vertical Blanking is 30 lines. */ + [5] = 0xD0, + [6] = 0x1E, + [7] = 0x20, - [8] = 110u, /* Horizontal Front Porch in pixels */ - [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 0x55u, /* Vertical Front Porch is 5 lines */ - [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + [8] = 110u, /* Horizontal Front Porch in pixels. */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 0x55u, /* Vertical Front Porch is 5 lines. */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */ - /* Horizontal Addressable Image Size is 1039mm - * Vertical Addressable Image Size is 584mm - */ - [12] = 0x0F, [13] = 0x48, [14] = 0x42, + /* Horizontal Addressable Image Size is 1039mm, + Vertical Addressable Image Size is 584mm. */ + [12] = 0x0F, + [13] = 0x48, + [14] = 0x42, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal Border Size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ /* Timing is Non-Interlaced Video, - * Stereo Video is not supported, - * Digital separate syncs are requires. - */ + Stereo Video is not supported, + Digital separate syncs are requires. */ [17] = 0x1E, }, .descriptor_block_4 = { /* Display Product Name Block Tag */ - [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0xFC, + [4] = 0, /* Product name */ [5] = 'A', @@ -458,26 +475,24 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) [0] = 0x02, /* CEA 861 Extension Block Tag Code */ [1] = 0x03, /* CEA 861 Block Version */ - [2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here */ + [2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here. */ - /* Underscan is not supported - * Basic Audio is supported - * YCbCr 4:4:4 & YCbCr 4:2:2 are supported - * Number of native formats: 2 - */ + /* Underscan is not supported, + Basic Audio is supported, + YCbCr 4:4:4 & YCbCr 4:2:2 are supported, + Number of native formats: 2. */ [3] = 0x72, - /* Video Data Block Tag Code is 2 - * Number of Short Video Descriptor Bytes i 7 - */ + /* Video Data Block Tag Code is 2, + Number of Short Video Descriptor Bytes is 7. */ [4] = 0x47, /* 1920x1080p 59.94/60 Hz 16 : 9 AR (CEA Format #16) - * is a supported Native Format. */ + is a supported Native Format. */ [5] = 0x90, /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) - * is a supported Native Format. */ + is a supported Native Format. */ [6] = 0x85, /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ @@ -495,14 +510,12 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ [11] = 0x06, - /* Audio Data Block Tag Code is 1. - * Number of Short Audio Descriptor Bytes is 3. - */ + /* Audio Data Block Tag Code is 1, + Number of Short Audio Descriptor Bytes is 3. */ [12] = 0x23, - /* Audio Format Tag Code is 1 --- LPCM is supported. - * Maximum number of audio channels is 2 - */ + /* Audio Format Tag Code is 1 --- LPCM is supported, + Maximum number of audio channels is 2. */ [13] = 0x09, /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ @@ -511,59 +524,63 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ [15] = 0x07, - /* Speaker Allocation Block Tag Code is 4. - * Number of Speaker Allocation - * Descriptor Bytes is 3. - */ + /* Speaker Allocation Block Tag Code is 4, + Number of Speaker Allocation Descriptor Bytes is 3. */ [16] = 0x83, - /* Speaker Allocation is Front-Left & Front-Right */ + /* Speaker Allocation is Front-Left & Front-Right. */ [17] = 0x01, /* Reserved */ [18 ... 19] = 0, - /* Vendor Specific Data Block Tag Code is 3. - * Number of Vendor Specific Data Bytes is 5. - */ + /* Vendor Specific Data Block Tag Code is 3, + Number of Vendor Specific Data Bytes is 5. */ [20] = 0x65, - /* 24bit IEEE registration Identifier is 0x000C03 */ - [21] = 0x03, [22] = 0x0C, [23] = 0x00, + /* 24bit IEEE registration Identifier is 0x000C03. */ + [21] = 0x03, + [22] = 0x0C, + [23] = 0x00, - /* Vendor Specific Data is 0x10000 */ - [24] = 0x01, [25] = 0x00, + /* Vendor Specific Data is 0x10000. */ + [24] = 0x01, + [25] = 0x00, /* Descriptor Block 5 [18 Bytes] */ [26] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, [27] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 720px. - * Horizontal Blanking is 138 px. - */ - [28] = 0xD0, [29] = 0x8A, [30] = 0x20, + /* Horizontal Addressable Video is 720px, + Horizontal Blanking is 138 px. */ + [28] = 0xD0, + [29] = 0x8A, + [30] = 0x20, - /* Vertical Addressable Video is 480 lines. - * Vertical Blanking is 45 lines. - */ - [31] = 0xE0, [32] = 0x2D, [33] = 0x10, + /* Vertical Addressable Video is 480 lines, + Vertical Blanking is 45 lines. */ + [31] = 0xE0, + [32] = 0x2D, + [33] = 0x10, - [34] = 16u, /* Horizontal Front Porch in pixels */ - [35] = 62u, /* Horizontal Sync Pulse Width in pixels */ - [36] = 0x96, /* Vertical Front Porch is 9 lines */ - [37] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + [34] = 16u, /* Horizontal Front Porch in pixels. */ + [35] = 62u, /* Horizontal Sync Pulse Width in pixels. */ + [36] = 0x96, /* Vertical Front Porch is 9 lines. */ + [37] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */ /* Displayed Image Aspect Ratio is 16:9 */ - [38] = 16u, [39] = 9u, [40] = 0u, + [38] = 16u, + [39] = 9u, + [40] = 0u, /* Horizontal and Vertical Border Size is 0 px */ - [41] = 0u, [42] = 0u, + [41] = 0u, + [42] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [43] = 0x18, /* Descriptor Block 6 [18 Bytes] */ @@ -571,31 +588,35 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) [44] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, [45] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 720px. - * Horizontal Blanking is 138 px. - */ - [46] = 0xD0, [47] = 0x8A, [48] = 0x20, + /* Horizontal Addressable Video is 720px, + Horizontal Blanking is 138 px. */ + [46] = 0xD0, + [47] = 0x8A, + [48] = 0x20, - /* Vertical Addressable Video is 480 lines. - * Vertical Blanking is 45 lines. - */ - [49] = 0xE0, [50] = 0x2D, [51] = 0x10, + /* Vertical Addressable Video is 480 lines, + Vertical Blanking is 45 lines. */ + [49] = 0xE0, + [50] = 0x2D, + [51] = 0x10, - [52] = 16u, /* Horizontal Front Porch in pixels */ - [53] = 62u, /* Horizontal Sync Pulse Width in pixels */ - [54] = 0x96, /* Vertical Front Porch is 9 lines */ - [55] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + [52] = 16u, /* Horizontal Front Porch in pixels. */ + [53] = 62u, /* Horizontal Sync Pulse Width in pixels. */ + [54] = 0x96, /* Vertical Front Porch is 9 lines. */ + [55] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */ - /* Displayed Image Aspect Ratio is 4:3 */ - [56] = 4u, [57] = 3u, [58] = 0u, + /* Displayed Image Aspect Ratio is 4:3. */ + [56] = 4u, + [57] = 3u, + [58] = 0u, - /* Horizontal and Vertical Border Size is 0 px */ - [59] = 0u, [60] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [59] = 0u, + [60] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [61] = 0x18, /* Descriptor Block 7 [18 Bytes] */ @@ -603,31 +624,35 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) [62] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, [63] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1440px. - * Horizontal Blanking is 276 px. - */ - [64] = 0xA0, [65] = 0x14, [66] = 0x51, + /* Horizontal Addressable Video is 1440px, + Horizontal Blanking is 276 px. */ + [64] = 0xA0, + [65] = 0x14, + [66] = 0x51, - /* Vertical Addressable Video is 240 lines. - * Vertical Blanking is 23 lines. - */ - [67] = 0xF0, [68] = 0x16, [69] = 0x00, + /* Vertical Addressable Video is 240 lines, + Vertical Blanking is 23 lines. */ + [67] = 0xF0, + [68] = 0x16, + [69] = 0x00, - [70] = 38u, /* Horizontal Front Porch in pixels */ - [71] = 124u, /* Horizontal Sync Pulse Width in pixels */ - [72] = 0x43, /* Vertical Front Porch is 9 lines */ - [73] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + [70] = 38u, /* Horizontal Front Porch in pixels. */ + [71] = 124u, /* Horizontal Sync Pulse Width in pixels. */ + [72] = 0x43, /* Vertical Front Porch is 9 lines. */ + [73] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */ /* Displayed Image Aspect Ratio is 16:9 */ - [74] = 16u, [75] = 9u, [76] = 0u, + [74] = 16u, + [75] = 9u, + [76] = 0u, - /* Horizontal and Vertical Border Size is 0 px */ - [77] = 0u, [78] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [77] = 0u, + [78] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [79] = 0x98, /* Descriptor Block 8 [18 Bytes] */ @@ -635,44 +660,45 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) [80] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, [81] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1440px. - * Horizontal Blanking is 276 px. - */ - [82] = 0xA0, [83] = 0x14, [84] = 0x51, + /* Horizontal Addressable Video is 1440px, + Horizontal Blanking is 276 px. */ + [82] = 0xA0, + [83] = 0x14, + [84] = 0x51, - /* Vertical Addressable Video is 240 lines. - * Vertical Blanking is 23 lines. - */ - [85] = 0xF0, [86] = 0x16, [87] = 0x00, + /* Vertical Addressable Video is 240 lines, + Vertical Blanking is 23 lines. */ + [85] = 0xF0, + [86] = 0x16, + [87] = 0x00, - [88] = 38u, /* Horizontal Front Porch in pixels */ - [89] = 124u, /* Horizontal Sync Pulse Width in pixels */ - [90] = 0x43, /* Vertical Front Porch is 9 lines */ - [91] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + [88] = 38u, /* Horizontal Front Porch in pixels. */ + [89] = 124u, /* Horizontal Sync Pulse Width in pixels. */ + [90] = 0x43, /* Vertical Front Porch is 9 lines. */ + [91] = 0x00, /* Vertical Sync Pulse Width is 6 lines. */ - /* Displayed Image Aspect Ratio is 4:3 */ - [92] = 4u, [93] = 3u, [94] = 0u, + /* Displayed Image Aspect Ratio is 4:3. */ + [92] = 4u, + [93] = 3u, + [94] = 0u, - /* Horizontal and Vertical Border Size is 0 px */ - [95] = 0u, [96] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [95] = 0u, + [96] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [97] = 0x98, - [99 ... 126] = 0 - }; + [99 ... 126] = 0}; ext[127] = get_raw_edid_checksum(ext); *state = malloc(sizeof(struct test_state)); - struct test_state ts = { - .data_size = sizeof(raw) + sizeof(ext), - .data = malloc(sizeof(raw) + sizeof(ext)) - }; + struct test_state ts = {.data_size = sizeof(raw) + sizeof(ext), + .data = malloc(sizeof(raw) + sizeof(ext))}; memcpy(ts.data, &raw, sizeof(raw)); memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext)); @@ -682,18 +708,16 @@ static int setup_decode_edid_dtv_frame_with_extension(void **state) return 0; } -/* Test decoding of EDID frame with one extension. - */ +/* Test decoding of EDID frame with one extension. */ static void test_decode_edid_dtv_frame_with_extension(void **state) { struct edid out; struct test_state *ts = *state; /* In real-life situations frames often are not 100% conformant, - * but are at least correct when it comes to key data fields. - */ + but are at least correct when it comes to key data fields. */ assert_int_equal(EDID_CONFORMANT, - decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); assert_int_equal(32, out.framebuffer_bits_per_pixel); assert_int_equal(8, out.panel_bits_per_color); @@ -733,20 +757,21 @@ static void test_decode_edid_dtv_frame_with_extension(void **state) /* Test decoding of EDID frame with one extension. Tested frame is modified - * example of base EDID frame with CEA861 extension for IT/DTV Display from - * VESA E-EDID Standard Release A2. - */ + example of base EDID frame with CEA861 extension for IT/DTV Display from + VESA E-EDID Standard Release A2. */ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) { struct edid_raw raw = { EDID_RAW_DEFAULT_PARAMS, - .video_input_type = EDID_DIGITAL_VSI + .video_input_type = + EDID_DIGITAL_VSI | EDID_INTERFACE_HDMI_A | EDID_COLOR_BIT_DEPTH_8B, .horizontal_size = 121, /* Aspect ratio 16:9 in landscape */ - .vertical_size = 68, /* Landscape flag */ - .display_gamma = 120, /* 220% */ - .supported_features = EDID_STANDBY_MODE(0) + .vertical_size = 68, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = + EDID_STANDBY_MODE(0) | EDID_SUSPEND_MODE(0) | EDID_ACTIVE_OFF(0) | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 @@ -755,20 +780,20 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, .established_supported_timings = { [0] = EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz - | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz - | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz - | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz - | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz, + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz, [1] = EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz - | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz - | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz - | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz - | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz, + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz, }, .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, .standard_timings_supported = { @@ -800,78 +825,83 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) [0] = EDID_PIXEL_CLOCK(85500000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(85500000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1360px - * Horizontal Blanking is 432px - */ - [2] = 0x50, [3] = 0xB0, [4] = 0x51, + /* Horizontal Addressable Video is 1360px, + Horizontal Blanking is 432px. */ + [2] = 0x50, + [3] = 0xB0, + [4] = 0x51, - /* Vertical Addressable Video is 768 lines - * Vertical Blanking is 27 lines - */ - [5] = 0x00, [6] = 0x1B, [7] = 0x30, + /* Vertical Addressable Video is 768 lines, + Vertical Blanking is 27 lines. */ + [5] = 0x00, + [6] = 0x1B, + [7] = 0x30, - [8] = 64u, /* Horizontal Front Porch in pixels */ - [9] = 112u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 0x36, /* Vertical Front Porch is 3 lines */ - [11] = 0u, /* Vertical Sync Pulse Width is 6 lines */ + [8] = 64u, /* Horizontal Front Porch in pixels. */ + [9] = 112u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 0x36, /* Vertical Front Porch is 3 lines. */ + [11] = 0u, /* Vertical Sync Pulse Width is 6 lines. */ - /* Horizontal Addressable Image Size is 1214mm - * Vertical Addressable Image Size is 683mm - */ - [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + /* Horizontal Addressable Image Size is 1214mm, + Vertical Addressable Image Size is 683mm. */ + [12] = 0xBE, + [13] = 0xAB, + [14] = 0x42, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal border size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ /* Timing is Non-Interlaced Video, - * Stereo Video is not supported, - * Digital separate and syncs are requires. - */ + Stereo Video is not supported, + Digital separate and syncs are requires. */ [17] = 0x1E, }, .descriptor_block_2 = { [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1280px - * Horizontal Blanking is 370px - */ - [2] = 0x00, [3] = 0x72, [4] = 0x51, + /* Horizontal Addressable Video is 1280px, + Horizontal Blanking is 370px. */ + [2] = 0x00, + [3] = 0x72, + [4] = 0x51, - /* Vertical Addressable Video is 720 lines - * Vertical Blanking is 30 lines - */ - [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + /* Vertical Addressable Video is 720 lines, + Vertical Blanking is 30 lines. */ + [5] = 0xD0, + [6] = 0x1E, + [7] = 0x20, - [8] = 110u, /* Horizontal Front Porch in pixels */ - [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ - [10] = 0x55, /* Vertical Front Porch is 5 lines */ - [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + [8] = 110u, /* Horizontal Front Porch in pixels. */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels. */ + [10] = 0x55, /* Vertical Front Porch is 5 lines. */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */ - /* Horizontal Addressable Image Size is 1214mm - * Vertical Addressable Image Size is 683mm - */ - [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + /* Horizontal Addressable Image Size is 1214mm, + Vertical Addressable Image Size is 683mm. */ + [12] = 0xBE, + [13] = 0xAB, + [14] = 0x42, - [15] = 0x00, /* Horizontal border size is 0px*/ - [16] = 0x00, /* Vertical Border Size is 0px */ + [15] = 0x00, /* Horizontal border size is 0px. */ + [16] = 0x00, /* Vertical Border Size is 0px. */ /* Timing is Non-Interlaced Video, - * Stereo Video is not supported, - * Digital separate and syncs are requires. - */ + Stereo Video is not supported, + Digital separate and syncs are required. */ [17] = 0x1E, }, .descriptor_block_3 = { /* Established timings III Block Tag */ - [0 ... 2] = 0u, [3] = 0xF7, [4] = 0u, + [0 ... 2] = 0u, + [3] = 0xF7, + [4] = 0u, - /* - * VESA DMT Standard Version #10 - */ + /* VESA DMT Standard Version #10 */ [5] = 10u, - /* 640x350@85Hz, + /* + * 640x350@85Hz, * 640x400@85Hz, * 720x400@85Hz, * 640x480@85Hz, @@ -881,26 +911,30 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) */ [6] = 0x7F, - /* 1280x960@60Hz, + /* + * 1280x960@60Hz, * 1280x960@85Hz, * 1280x1024@60Hz, * 1280x1024@85Hz */ [7] = 0x0F, - /* 1400x1050@60Hz (Normal Blanking), + /* + * 1400x1050@60Hz (Normal Blanking), * 1400x1050@75Hz are supported. */ [8] = 0x03, - /* 1400x1050@85Hz, + /* + * 1400x1050@85Hz, * 1600x1200@60Hz, * 1600x1200@65Hz, * 1600x1200@70Hz are supported. */ [9] = 0x87, - /* 1600x1200@75Hz, + /* + * 1600x1200@75Hz, * 1600x1200@85Hz are supported. */ [10] = 0xC0, @@ -913,7 +947,11 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) }, .descriptor_block_4 = { /* Display Product Name Block Tag */ - [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0xFC, + [4] = 0, /* Product name */ [5] = 'A', @@ -940,16 +978,14 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) [1] = 0x03, /* CEA 861 Block Version */ [2] = 0x17, /* Detail Timing Descriptors start 0x17 bytesfrom here */ - /* Underscan is supported - * Basic Audio is supported - * YCbCr 4:4:4 & YCbCr 4:2:2 are supported - * Number of native formats: 0 - */ + /* Underscan is supported, + Basic Audio is supported, + YCbCr 4:4:4 & YCbCr 4:2:2 are supported, + Number of native formats: 0. */ [3] = 0xF0, - /* Video Data Block Tag Code is 2 - * Number of Short Video Descriptor Bytes i 6 - */ + /* Video Data Block Tag Code is 2. + Number of Short Video Descriptor Bytes is 6. */ [4] = 0x46, /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) is a supported format. */ @@ -970,14 +1006,12 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ [10] = 0x06, - /* Audio Data Block Tag Code is 1. - * Number of Short Audio Descriptor Bytes is 3. - */ + /* Audio Data Block Tag Code is 1, + Number of Short Audio Descriptor Bytes is 3. */ [11] = 0x23, - /* Audio Format Tag Code is 1 --- LPCM is supported. - * Maximum number of audio channels is 2 - */ + /* Audio Format Tag Code is 1 --- LPCM is supported, + Maximum number of audio channels is 2. */ [12] = 0x09, /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ @@ -986,10 +1020,8 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ [14] = 0x07, - /* Speaker Allocation Block Tag Code is 4. - * Number of Speaker Allocation - * Descriptor Bytes is 3. - */ + /* Speaker Allocation Block Tag Code is 4, + Number of Speaker Allocation Descriptor Bytes is 3. */ [15] = 0x83, /* Speaker Allocation is Front-Left & Front-Right */ @@ -998,47 +1030,53 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) /* Reserved */ [17 ... 18] = 0, - /* Vendor Specific Data Block Tag Code is 3. - * Number of Vendor Specific Data Bytes is 5. - */ + /* Vendor Specific Data Block Tag Code is 3, + Number of Vendor Specific Data Bytes is 5. */ [19] = 0x65, - /* 24bit IEEE registration Identifier is 0x000C03 */ - [20] = 0x03, [21] = 0x0C, [22] = 0x00, + /* 24bit IEEE registration Identifier is 0x000C03. */ + [20] = 0x03, + [21] = 0x0C, + [22] = 0x00, - /* Vendor Specific Data is 0x10000 */ - [23] = 0x01, [24] = 0x00, + /* Vendor Specific Data is 0x10000. */ + [23] = 0x01, + [24] = 0x00, /* Descriptor Block 5 [18 Bytes] */ [25] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, [26] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1920px. - * Horizontal Blanking is 280px. - */ - [27] = 0x80, [28] = 0x18, [29] = 0x71, + /* Horizontal Addressable Video is 1920px, + Horizontal Blanking is 280px. */ + [27] = 0x80, + [28] = 0x18, + [29] = 0x71, - /* Vertical Addressable Video is 540 lines. - * Vertical Blanking is 22 lines. - */ - [30] = 0x1C, [31] = 0x16, [32] = 0x20, + /* Vertical Addressable Video is 540 lines, + Vertical Blanking is 22 lines. */ + [30] = 0x1C, + [31] = 0x16, + [32] = 0x20, - [33] = 88u, /* Horizontal Front Porch in pixels */ - [34] = 44u, /* Horizontal Sync Pulse Width in pixels */ - [35] = 0x25, /* Vertical Front Porch is 2 lines */ - [36] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + [33] = 88u, /* Horizontal Front Porch in pixels. */ + [34] = 44u, /* Horizontal Sync Pulse Width in pixels. */ + [35] = 0x25, /* Vertical Front Porch is 2 lines. */ + [36] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */ /* Image size: 1039mm x 584mm */ - [37] = 0x0F, [38] = 0x48, [39] = 0x42, + [37] = 0x0F, + [38] = 0x48, + [39] = 0x42, - /* Horizontal and Vertical Border Size is 0 px */ - [40] = 0u, [41] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [40] = 0u, + [41] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [42] = 0x9E, /* Descriptor Block 6 [18 Bytes] */ @@ -1046,31 +1084,35 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) [43] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, [44] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1280px. - * Horizontal Blanking is 370 px. - */ - [45] = 0x00, [46] = 0x72, [47] = 0x51, + /* Horizontal Addressable Video is 1280px, + Horizontal Blanking is 370 px. */ + [45] = 0x00, + [46] = 0x72, + [47] = 0x51, - /* Vertical Addressable Video is 720 lines. - * Vertical Blanking is 30 lines. - */ - [48] = 0xD0, [49] = 0x1E, [50] = 0x20, + /* Vertical Addressable Video is 720 lines, + Vertical Blanking is 30 lines. */ + [48] = 0xD0, + [49] = 0x1E, + [50] = 0x20, - [51] = 110u, /* Horizontal Front Porch in pixels */ - [52] = 40u, /* Horizontal Sync Pulse Width in pixels */ - [53] = 0x55, /* Vertical Front Porch is 5 lines */ - [54] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + [51] = 110u, /* Horizontal Front Porch in pixels. */ + [52] = 40u, /* Horizontal Sync Pulse Width in pixels. */ + [53] = 0x55, /* Vertical Front Porch is 5 lines. */ + [54] = 0x00, /* Vertical Sync Pulse Width is 5 lines. */ /* Image size: 1039mm x 584mm */ - [55] = 0x0F, [56] = 0x48, [57] = 0x42, + [55] = 0x0F, + [56] = 0x48, + [57] = 0x42, - /* Horizontal and Vertical Border Size is 0 px */ - [58] = 0u, [59] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [58] = 0u, + [59] = 0u, - /* Timing is Non-Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Non-Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [60] = 0x1E, /* Descriptor Block 7 [18 Bytes] */ @@ -1078,31 +1120,35 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) [61] = EDID_PIXEL_CLOCK(27000000u) & 0xFF, [62] = (EDID_PIXEL_CLOCK(27000000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1440px. - * Horizontal Blanking is 276 px. - */ - [63] = 0xA0, [64] = 0x14, [65] = 0x51, + /* Horizontal Addressable Video is 1440px, + Horizontal Blanking is 276 px. */ + [63] = 0xA0, + [64] = 0x14, + [65] = 0x51, - /* Vertical Addressable Video is 240 lines. - * Vertical Blanking is 23 lines. - */ - [66] = 0xF0, [67] = 0x16, [68] = 0x00, + /* Vertical Addressable Video is 240 lines, + Vertical Blanking is 23 lines. */ + [66] = 0xF0, + [67] = 0x16, + [68] = 0x00, - [69] = 38u, /* Horizontal Front Porch in pixels */ - [70] = 124u, /* Horizontal Sync Pulse Width in pixels */ - [71] = 0x43, /* Vertical Front Porch is 4 lines */ - [72] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + [69] = 38u, /* Horizontal Front Porch in pixels. */ + [70] = 124u, /* Horizontal Sync Pulse Width in pixels. */ + [71] = 0x43, /* Vertical Front Porch is 4 lines. */ + [72] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */ /* Image size: 1039mm x 584mm */ - [73] = 0x0F, [74] = 0x48, [75] = 0x42, + [73] = 0x0F, + [74] = 0x48, + [75] = 0x42, - /* Horizontal and Vertical Border Size is 0 px */ - [76] = 0u, [77] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [76] = 0u, + [77] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [78] = 0x18, /* Descriptor Block 8 [18 Bytes] */ @@ -1110,31 +1156,35 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) [79] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, [80] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, - /* Horizontal Addressable Video is 1440px. - * Horizontal Blanking is 276 px. - */ - [81] = 0xA0, [82] = 0x14, [83] = 0x51, + /* Horizontal Addressable Video is 1440px, + Horizontal Blanking is 276 px. */ + [81] = 0xA0, + [82] = 0x14, + [83] = 0x51, - /* Vertical Addressable Video is 240 lines. - * Vertical Blanking is 23 lines. - */ - [84] = 0xF0, [85] = 0x16, [86] = 0x00, + /* Vertical Addressable Video is 240 lines, + Vertical Blanking is 23 lines. */ + [84] = 0xF0, + [85] = 0x16, + [86] = 0x00, - [87] = 38u, /* Horizontal Front Porch in pixels */ - [88] = 124u, /* Horizontal Sync Pulse Width in pixels */ - [89] = 0x43, /* Vertical Front Porch is 4 lines */ - [90] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + [87] = 38u, /* Horizontal Front Porch in pixels. */ + [88] = 124u, /* Horizontal Sync Pulse Width in pixels. */ + [89] = 0x43, /* Vertical Front Porch is 4 lines. */ + [90] = 0x00, /* Vertical Sync Pulse Width is 3 lines. */ /* Image size: 1039mm x 584mm */ - [91] = 0x0F, [92] = 0x48, [93] = 0x42, + [91] = 0x0F, + [92] = 0x48, + [93] = 0x42, - /* Horizontal and Vertical Border Size is 0 px */ - [94] = 0u, [95] = 0u, + /* Horizontal and Vertical Border Size is 0px. */ + [94] = 0u, + [95] = 0u, - /* Timing is Interlaced Video - * Stereo Video is not supported - * Digital Separate Syncs are required - */ + /* Timing is Interlaced Video, + Stereo Video is not supported, + Digital Separate Syncs are required. */ [96] = 0x98, [97 ... 126] = 0, @@ -1144,10 +1194,8 @@ static int setup_decode_edid_it_dtv_frame_with_extension(void **state) *state = malloc(sizeof(struct test_state)); - struct test_state ts = { - .data_size = sizeof(raw) + sizeof(ext), - .data = malloc(sizeof(raw) + sizeof(ext)) - }; + struct test_state ts = {.data_size = sizeof(raw) + sizeof(ext), + .data = malloc(sizeof(raw) + sizeof(ext))}; memcpy(ts.data, &raw, sizeof(raw)); memcpy(ts.data + sizeof(raw), &ext[0], sizeof(ext)); @@ -1163,10 +1211,9 @@ static void test_decode_edid_it_dtv_frame_with_extension(void **state) struct test_state *ts = *state; /* In real-life situations frames often are not 100% conformant, - * but are at least correct when it comes to key data fields. - */ + but are at least correct when it comes to key data fields. */ assert_int_equal(EDID_CONFORMANT, - decode_edid((unsigned char *)ts->data, ts->data_size, &out)); + decode_edid((unsigned char *)ts->data, ts->data_size, &out)); assert_int_equal(32, out.framebuffer_bits_per_pixel); assert_int_equal(8, out.panel_bits_per_color); diff --git a/tests/lib/fmap-test.c b/tests/lib/fmap-test.c index 044c3121a9..1cc8246b4b 100644 --- a/tests/lib/fmap-test.c +++ b/tests/lib/fmap-test.c @@ -31,7 +31,7 @@ static void prepare_flash_buffer(void) /* Fill rest of buffer with dummy data */ for (int i = FMAP_SECTION_FMAP_START + FMAP_SECTION_FMAP_SIZE; - i < FMAP_SECTION_FLASH_SIZE; ++i) + i < FMAP_SECTION_FLASH_SIZE; ++i) flash_buffer[i] = 'a' + i % ('z' - 'a'); } @@ -140,13 +140,13 @@ static void test_fmap_locate_area_as_rdev_rw(void **state) /* Test if returned section region device is writable */ assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("MISC_RW", &rdev)); assert_int_equal(ro_rw_section_size, - rdev_readat(&rdev, buffer1, 0, ro_rw_section_size)); + rdev_readat(&rdev, buffer1, 0, ro_rw_section_size)); assert_int_equal(ro_rw_section_size, - rdev_writeat(&rdev, dummy_data, 0, ro_rw_section_size)); + rdev_writeat(&rdev, dummy_data, 0, ro_rw_section_size)); /* Check if written data is visible and correct after locating area as RO */ assert_int_not_equal(-1, fmap_locate_area_as_rdev("MISC_RW", &rdev)); assert_int_equal(ro_rw_section_size, - rdev_readat(&rdev, buffer2, 0, ro_rw_section_size)); + rdev_readat(&rdev, buffer2, 0, ro_rw_section_size)); assert_memory_not_equal(buffer1, buffer2, ro_rw_section_size); assert_memory_equal(dummy_data, buffer2, ro_rw_section_size); @@ -261,7 +261,7 @@ static void test_fmap_overwrite_area(void **state) /* Overwrite part of section. */ assert_int_equal(section_size / 2, - fmap_overwrite_area(section_name, new_data, section_size / 2)); + fmap_overwrite_area(section_name, new_data, section_size / 2)); /* Read and check if memory has changed as expected */ assert_int_equal(section_size, fmap_read_area(section_name, buffer2, section_size)); @@ -272,8 +272,8 @@ static void test_fmap_overwrite_area(void **state) assert_memory_equal(buffer2 + (section_size / 2), zero_buffer, section_size / 2); /* Expect error when overwriting incorrect section */ - assert_int_equal(-1, fmap_overwrite_area("NONEXISTENT_SECTION", - new_data, section_size / 2)); + assert_int_equal( + -1, fmap_overwrite_area("NONEXISTENT_SECTION", new_data, section_size / 2)); assert_int_equal(-1, fmap_overwrite_area(NULL, new_data, section_size / 2)); /* Function fmap_overwrite_area is not tested with NULL @@ -288,18 +288,17 @@ static void test_fmap_overwrite_area(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev, - setup_fmap, teardown_fmap), - cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev_rw, - setup_fmap, teardown_fmap), - cmocka_unit_test_setup_teardown(test_fmap_locate_area, - setup_fmap, teardown_fmap), - cmocka_unit_test_setup_teardown(test_fmap_find_region_name, - setup_fmap, teardown_fmap), - cmocka_unit_test_setup_teardown(test_fmap_read_area, - setup_fmap, teardown_fmap), - cmocka_unit_test_setup_teardown(test_fmap_overwrite_area, - setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev, setup_fmap, + teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev_rw, setup_fmap, + teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_locate_area, setup_fmap, + teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_find_region_name, setup_fmap, + teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_read_area, setup_fmap, teardown_fmap), + cmocka_unit_test_setup_teardown(test_fmap_overwrite_area, setup_fmap, + teardown_fmap), }; return cb_run_group_tests(tests, NULL, NULL); diff --git a/tests/lib/hexstrtobin-test.c b/tests/lib/hexstrtobin-test.c index f096b9b9e7..aaad0d6b31 100644 --- a/tests/lib/hexstrtobin-test.c +++ b/tests/lib/hexstrtobin-test.c @@ -12,11 +12,11 @@ struct hexstr_t { size_t res; } hexstr[] = { {.str = "A", .res = 0}, - {.str = "AB", .val = (int[]) {171}, .res = 1}, - {.str = "277a", .val = (int[]) {39, 122}, .res = 2}, - {.str = "277ab", .val = (int[]) {39, 122}, .res = 2}, - {.str = "\n\rx1234567ijkl", .val = (int[]) {18, 52, 86}, .res = 3}, - {.str = "\nB*e/ef-", .val = (int[]) {190, 239}, .res = 2}, + {.str = "AB", .val = (int[]){171}, .res = 1}, + {.str = "277a", .val = (int[]){39, 122}, .res = 2}, + {.str = "277ab", .val = (int[]){39, 122}, .res = 2}, + {.str = "\n\rx1234567ijkl", .val = (int[]){18, 52, 86}, .res = 3}, + {.str = "\nB*e/ef-", .val = (int[]){190, 239}, .res = 2}, }; static void test_hexstrtobin(void **state) diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c index 6da1ac926c..28a4456b27 100644 --- a/tests/lib/imd-test.c +++ b/tests/lib/imd-test.c @@ -12,8 +12,9 @@ /* Auxiliary functions and definitions. */ -#define LG_ROOT_SIZE align_up_pow2(sizeof(struct imd_root_pointer) +\ - sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)) +#define LG_ROOT_SIZE \ + align_up_pow2(sizeof(struct imd_root_pointer) + sizeof(struct imd_root) \ + + 3 * sizeof(struct imd_entry)) #define LG_ENTRY_ALIGN (2 * sizeof(int32_t)) #define LG_ENTRY_SIZE (2 * sizeof(int32_t)) #define LG_ENTRY_ID 0xA001 @@ -33,7 +34,7 @@ static uint32_t align_up_pow2(uint32_t x) static size_t max_entries(size_t root_size) { return (root_size - sizeof(struct imd_root_pointer) - sizeof(struct imd_root)) - / sizeof(struct imd_entry); + / sizeof(struct imd_entry); } /* @@ -47,14 +48,14 @@ static void test_imd_handle_init(void **state) void *base; struct imd imd; uintptr_t test_inputs[] = { - 0, /* Lowest possible address */ - 0xA000, /* Fits in 16 bits, should not get rounded down*/ - 0xDEAA, /* Fits in 16 bits */ - 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ - 0xF0F0F0F0, /* Fits in 32 bits */ - ((1ULL << 32) + 4), /* Just above 32-bit limit */ - 0x6666777788889000, /* Fits in 64 bits, should not get rounded down */ - ((1ULL << 60) - 100) /* Very large address, fitting in 64 bits */ + 0, /* Lowest possible address */ + 0xA000, /* Fits in 16 bits, should not get rounded down*/ + 0xDEAA, /* Fits in 16 bits */ + 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ + 0xF0F0F0F0, /* Fits in 32 bits */ + ((1ULL << 32) + 4), /* Just above 32-bit limit */ + 0x6666777788889000, /* Fits in 64 bits, should not get rounded down */ + ((1ULL << 60) - 100) /* Very large address, fitting in 64 bits */ }; for (i = 0; i < ARRAY_SIZE(test_inputs); i++) { @@ -122,16 +123,15 @@ static void test_imd_create_empty(void **state) imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); /* Try incorrect sizes */ - assert_int_equal(-1, imd_create_empty(&imd, - sizeof(struct imd_root_pointer), - LG_ENTRY_ALIGN)); + assert_int_equal( + -1, imd_create_empty(&imd, sizeof(struct imd_root_pointer), LG_ENTRY_ALIGN)); assert_int_equal(-1, imd_create_empty(&imd, LG_ROOT_SIZE, 2 * LG_ROOT_SIZE)); /* Working case */ assert_int_equal(0, imd_create_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN)); /* Only large allocation initialized with one entry for the root region */ - r = (struct imd_root *) (imd.lg.r); + r = (struct imd_root *)(imd.lg.r); assert_non_null(r); e = &r->entries[r->num_entries - 1]; @@ -171,15 +171,13 @@ static void test_imd_create_tiered_empty(void **state) /* Too small root_size for small region */ assert_int_equal(-1, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, - sizeof(int32_t), 2 * sizeof(int32_t))); + sizeof(int32_t), 2 * sizeof(int32_t))); /* Fail when large region doesn't have capacity for more than 1 entry */ - lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + - sizeof(struct imd_entry); - expect_assert_failure( - imd_create_tiered_empty(&imd, lg_region_wrong_size, LG_ENTRY_ALIGN, - SM_ROOT_SIZE, SM_ENTRY_ALIGN) - ); + lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + sizeof(struct imd_entry); + expect_assert_failure(imd_create_tiered_empty( + &imd, lg_region_wrong_size, LG_ENTRY_ALIGN, SM_ROOT_SIZE, SM_ENTRY_ALIGN)); assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, SM_ENTRY_ALIGN)); @@ -230,11 +228,11 @@ static void test_imd_recover(void **state) struct imd imd = {0}; struct imd_root_pointer *rp; struct imd_root *r; - struct imd_entry *lg_root_entry, *sm_root_entry, *ptr; + struct imd_entry *lg_root_entry, *sm_root_entry, *ptr; const struct imd_entry *lg_entry; /* Fail when the limit for lg was not set. */ - imd.lg.limit = (uintptr_t) NULL; + imd.lg.limit = (uintptr_t)NULL; assert_int_equal(-1, imd_recover(&imd)); /* Set the limit for lg. */ @@ -327,8 +325,8 @@ static void test_imd_limit_size(void **state) struct imd imd = {0}; size_t root_size, max_size; - max_size = align_up_pow2(sizeof(struct imd_root_pointer) - + sizeof(struct imd_root) + 3 * sizeof(struct imd_entry)); + max_size = align_up_pow2(sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + 3 * sizeof(struct imd_entry)); assert_int_equal(-1, imd_limit_size(&imd, max_size)); @@ -337,8 +335,8 @@ static void test_imd_limit_size(void **state) fail_msg("Cannot allocate enough memory - fail test"); imd_handle_init(&imd, (void *)(LIMIT_ALIGN + (uintptr_t)base)); - root_size = align_up_pow2(sizeof(struct imd_root_pointer) - + sizeof(struct imd_root) + 2 * sizeof(struct imd_entry)); + root_size = align_up_pow2(sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + + 2 * sizeof(struct imd_entry)); imd.lg.r = (void *)imd.lg.limit - root_size; imd_create_empty(&imd, root_size, LG_ENTRY_ALIGN); @@ -362,7 +360,7 @@ static void test_imd_lockdown(void **state) if (imd.lg.r == NULL) fail_msg("Cannot allocate enough memory - fail test"); - r_lg = (struct imd_root *) (imd.lg.r); + r_lg = (struct imd_root *)(imd.lg.r); assert_int_equal(0, imd_lockdown(&imd)); assert_true(r_lg->flags & IMD_FLAG_LOCKED); @@ -370,7 +368,7 @@ static void test_imd_lockdown(void **state) imd.sm.r = malloc(sizeof(struct imd_root)); if (imd.sm.r == NULL) fail_msg("Cannot allocate enough memory - fail test"); - r_sm = (struct imd_root *) (imd.sm.r); + r_sm = (struct imd_root *)(imd.sm.r); assert_int_equal(0, imd_lockdown(&imd)); assert_true(r_sm->flags & IMD_FLAG_LOCKED); @@ -492,7 +490,7 @@ static void test_imd_entry_add(void **state) /* All five new entries should be added to small allocations */ for (i = 0; i < 5; i++) { assert_non_null(imd_entry_add(&imd, SM_ENTRY_ID, SM_ENTRY_SIZE)); - assert_int_equal(i+2, sm_r->num_entries); + assert_int_equal(i + 2, sm_r->num_entries); assert_int_equal(2, lg_r->num_entries); } @@ -579,7 +577,7 @@ static void test_imd_entry_find_or_add(void **state) static void test_imd_entry_size(void **state) { - struct imd_entry entry = { .size = LG_ENTRY_SIZE }; + struct imd_entry entry = {.size = LG_ENTRY_SIZE}; assert_int_equal(LG_ENTRY_SIZE, imd_entry_size(&entry)); @@ -616,7 +614,7 @@ static void test_imd_entry_at(void **state) static void test_imd_entry_id(void **state) { - struct imd_entry entry = { .id = LG_ENTRY_ID }; + struct imd_entry entry = {.id = LG_ENTRY_ID}; assert_int_equal(LG_ENTRY_ID, imd_entry_id(&entry)); } @@ -761,4 +759,3 @@ int main(void) return cb_run_group_tests(tests, NULL, NULL); } - diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c index 1a1756c9d3..fe25285b68 100644 --- a/tests/lib/imd_cbmem-test.c +++ b/tests/lib/imd_cbmem-test.c @@ -441,14 +441,13 @@ static void test_cbmem_entry_start(void **state) /* Check if start address of found entry is the same as the one returned by cbmem_find() function */ assert_ptr_equal(cbmem_find(CBMEM_ENTRY_ID), - cbmem_entry_start(cbmem_entry_find(CBMEM_ENTRY_ID))); + cbmem_entry_start(cbmem_entry_find(CBMEM_ENTRY_ID))); assert_ptr_equal(cbmem_find(id1), cbmem_entry_start(cbmem_entry_find(id1))); assert_ptr_equal(cbmem_find(id2), cbmem_entry_start(cbmem_entry_find(id2))); } /* Reimplementation for testing purposes */ -void bootmem_add_range(uint64_t start, uint64_t size, - const enum bootmem_type tag) +void bootmem_add_range(uint64_t start, uint64_t size, const enum bootmem_type tag) { check_expected(start); check_expected(size); diff --git a/tests/lib/lib-test.c b/tests/lib/lib-test.c new file mode 100644 index 0000000000..826c6c563a --- /dev/null +++ b/tests/lib/lib-test.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void test_popcnt(void **state) +{ + assert_int_equal(popcnt(0x0), 0); + assert_int_equal(popcnt(0x10), 1); + assert_int_equal(popcnt(0x10010010), 3); + assert_int_equal(popcnt(0xffffffff), 32); +} + +void test_clz(void **state) +{ + assert_int_equal(clz(0x0), 32); + assert_int_equal(clz(0xf), 28); + assert_int_equal(clz(0x80000000), 0); + assert_int_equal(clz(0xffffffff), 0); +} + +void test_log2(void **state) +{ + assert_int_equal(log2(0x0), -1); + assert_int_equal(log2(0x1), 0); + assert_int_equal(log2(0x5), 2); + assert_int_equal(log2(0x80000000), 31); + assert_int_equal(log2(0xffffffff), 31); +} + +void test_ffs(void **state) +{ + assert_int_equal(__ffs(0x0), -1); + assert_int_equal(__ffs(0x1), 0); + assert_int_equal(__ffs(0x1010), 4); + assert_int_equal(__ffs(0x10000000), 28); + assert_int_equal(__ffs(0xffffffff), 0); +} + +void test_fls(void **state) +{ + assert_int_equal(__fls(0x0), -1); + assert_int_equal(__fls(0x1), 0); + assert_int_equal(__fls(0x5), 2); + assert_int_equal(__fls(0x80000000), 31); + assert_int_equal(__fls(0xffffffff), 31); +} + +void test_log2_ceil(void **state) +{ + assert_int_equal(log2_ceil(0x0), -1); + assert_int_equal(log2_ceil(0x1), 0); + assert_int_equal(log2_ceil(0x5), 3); + assert_int_equal(log2_ceil(0x80000000), 31); + assert_int_equal(log2_ceil(0xffffffff), 32); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_popcnt), + cmocka_unit_test(test_clz), + cmocka_unit_test(test_log2), + cmocka_unit_test(test_ffs), + cmocka_unit_test(test_fls), + cmocka_unit_test(test_log2_ceil), + }; + + return cb_run_group_tests(tests, NULL, NULL); +} diff --git a/tests/lib/libgcc-test.c b/tests/lib/libgcc-test.c index d089f646b9..1a567e91c0 100644 --- a/tests/lib/libgcc-test.c +++ b/tests/lib/libgcc-test.c @@ -12,108 +12,108 @@ struct { } test_data[] = { /* GCC documentation says, __clzsi2() has undefined result for zero as an input value, but coreboot implementation can handle this. */ - { .value = 0, .expected_output = 32 }, + {.value = 0, .expected_output = 32}, - { .value = 1, .expected_output = 31 }, - { .value = 2, .expected_output = 30 }, - { .value = 3, .expected_output = 30 }, - { .value = 4, .expected_output = 29 }, - { .value = 5, .expected_output = 29 }, - { .value = 6, .expected_output = 29 }, - { .value = 7, .expected_output = 29 }, + {.value = 1, .expected_output = 31}, + {.value = 2, .expected_output = 30}, + {.value = 3, .expected_output = 30}, + {.value = 4, .expected_output = 29}, + {.value = 5, .expected_output = 29}, + {.value = 6, .expected_output = 29}, + {.value = 7, .expected_output = 29}, - { .value = 0xF, .expected_output = 28 }, - { .value = 0x10, .expected_output = 27 }, - { .value = 0x25, .expected_output = 26 }, - { .value = 0x5D, .expected_output = 25 }, - { .value = 0xB7, .expected_output = 24 }, + {.value = 0xF, .expected_output = 28}, + {.value = 0x10, .expected_output = 27}, + {.value = 0x25, .expected_output = 26}, + {.value = 0x5D, .expected_output = 25}, + {.value = 0xB7, .expected_output = 24}, - { .value = 0x133, .expected_output = 23 }, - { .value = 0x3DC, .expected_output = 22 }, - { .value = 0x6F1, .expected_output = 21 }, - { .value = 0x897, .expected_output = 20 }, + {.value = 0x133, .expected_output = 23}, + {.value = 0x3DC, .expected_output = 22}, + {.value = 0x6F1, .expected_output = 21}, + {.value = 0x897, .expected_output = 20}, - { .value = 0x1FFF, .expected_output = 19 }, - { .value = 0x2222, .expected_output = 18 }, - { .value = 0x7BAD, .expected_output = 17 }, - { .value = 0xE708, .expected_output = 16 }, + {.value = 0x1FFF, .expected_output = 19}, + {.value = 0x2222, .expected_output = 18}, + {.value = 0x7BAD, .expected_output = 17}, + {.value = 0xE708, .expected_output = 16}, - { .value = 0x1DABD, .expected_output = 15 }, - { .value = 0x29876, .expected_output = 14 }, - { .value = 0x56665, .expected_output = 13 }, - { .value = 0xABCDE, .expected_output = 12 }, + {.value = 0x1DABD, .expected_output = 15}, + {.value = 0x29876, .expected_output = 14}, + {.value = 0x56665, .expected_output = 13}, + {.value = 0xABCDE, .expected_output = 12}, - { .value = 0x18365F, .expected_output = 11 }, - { .value = 0x3D0115, .expected_output = 10 }, - { .value = 0x4B07EB, .expected_output = 9 }, - { .value = 0xCCC74D, .expected_output = 8 }, + {.value = 0x18365F, .expected_output = 11}, + {.value = 0x3D0115, .expected_output = 10}, + {.value = 0x4B07EB, .expected_output = 9}, + {.value = 0xCCC74D, .expected_output = 8}, - { .value = 0x17933ED, .expected_output = 7 }, - { .value = 0x2B00071, .expected_output = 6 }, - { .value = 0x4D4C1A5, .expected_output = 5 }, - { .value = 0xAD01FFF, .expected_output = 4 }, + {.value = 0x17933ED, .expected_output = 7}, + {.value = 0x2B00071, .expected_output = 6}, + {.value = 0x4D4C1A5, .expected_output = 5}, + {.value = 0xAD01FFF, .expected_output = 4}, - { .value = 0x1C5A8057, .expected_output = 3 }, - { .value = 0x35AB23C3, .expected_output = 2 }, - { .value = 0x7017013B, .expected_output = 1 }, - { .value = 0xAD01EB15, .expected_output = 0 }, + {.value = 0x1C5A8057, .expected_output = 3}, + {.value = 0x35AB23C3, .expected_output = 2}, + {.value = 0x7017013B, .expected_output = 1}, + {.value = 0xAD01EB15, .expected_output = 0}, - { .value = 0xFFFFFFFF, .expected_output = 0 }, - { .value = 0x80000000, .expected_output = 0 }, - { .value = 0x7FFFFFFF, .expected_output = 1 }, - { .value = 0x30000000, .expected_output = 2 }, - { .value = 0x10000000, .expected_output = 3 }, - { .value = 0x0FFFFFFF, .expected_output = 4 }, + {.value = 0xFFFFFFFF, .expected_output = 0}, + {.value = 0x80000000, .expected_output = 0}, + {.value = 0x7FFFFFFF, .expected_output = 1}, + {.value = 0x30000000, .expected_output = 2}, + {.value = 0x10000000, .expected_output = 3}, + {.value = 0x0FFFFFFF, .expected_output = 4}, - { .value = 0xFF000000, .expected_output = 0 }, - { .value = 0x00FF0000, .expected_output = 8 }, - { .value = 0x0000FF00, .expected_output = 16 }, - { .value = 0x000000FF, .expected_output = 24 }, + {.value = 0xFF000000, .expected_output = 0}, + {.value = 0x00FF0000, .expected_output = 8}, + {.value = 0x0000FF00, .expected_output = 16}, + {.value = 0x000000FF, .expected_output = 24}, - { .value = 0x8F000000, .expected_output = 0 }, - { .value = 0x008F0000, .expected_output = 8 }, - { .value = 0x00008F00, .expected_output = 16 }, - { .value = 0x0000008F, .expected_output = 24 }, + {.value = 0x8F000000, .expected_output = 0}, + {.value = 0x008F0000, .expected_output = 8}, + {.value = 0x00008F00, .expected_output = 16}, + {.value = 0x0000008F, .expected_output = 24}, - { .value = 0x7F000000, .expected_output = 1 }, - { .value = 0x007F0000, .expected_output = 9 }, - { .value = 0x00007F00, .expected_output = 17 }, - { .value = 0x0000007F, .expected_output = 25 }, + {.value = 0x7F000000, .expected_output = 1}, + {.value = 0x007F0000, .expected_output = 9}, + {.value = 0x00007F00, .expected_output = 17}, + {.value = 0x0000007F, .expected_output = 25}, - { .value = 0x3F000000, .expected_output = 2 }, - { .value = 0x003F0000, .expected_output = 10 }, - { .value = 0x00003F00, .expected_output = 18 }, - { .value = 0x0000003F, .expected_output = 26 }, + {.value = 0x3F000000, .expected_output = 2}, + {.value = 0x003F0000, .expected_output = 10}, + {.value = 0x00003F00, .expected_output = 18}, + {.value = 0x0000003F, .expected_output = 26}, - { .value = 0x1F000000, .expected_output = 3 }, - { .value = 0x001F0000, .expected_output = 11 }, - { .value = 0x00001F00, .expected_output = 19 }, - { .value = 0x0000001F, .expected_output = 27 }, + {.value = 0x1F000000, .expected_output = 3}, + {.value = 0x001F0000, .expected_output = 11}, + {.value = 0x00001F00, .expected_output = 19}, + {.value = 0x0000001F, .expected_output = 27}, - { .value = 0x0F000000, .expected_output = 4 }, - { .value = 0x000F0000, .expected_output = 12 }, - { .value = 0x00000F00, .expected_output = 20 }, - { .value = 0x0000000F, .expected_output = 28 }, + {.value = 0x0F000000, .expected_output = 4}, + {.value = 0x000F0000, .expected_output = 12}, + {.value = 0x00000F00, .expected_output = 20}, + {.value = 0x0000000F, .expected_output = 28}, - { .value = 0x08000000, .expected_output = 4 }, - { .value = 0x00080000, .expected_output = 12 }, - { .value = 0x00000800, .expected_output = 20 }, - { .value = 0x00000008, .expected_output = 28 }, + {.value = 0x08000000, .expected_output = 4}, + {.value = 0x00080000, .expected_output = 12}, + {.value = 0x00000800, .expected_output = 20}, + {.value = 0x00000008, .expected_output = 28}, - { .value = 0x07000000, .expected_output = 5 }, - { .value = 0x00070000, .expected_output = 13 }, - { .value = 0x00000700, .expected_output = 21 }, - { .value = 0x00000007, .expected_output = 29 }, + {.value = 0x07000000, .expected_output = 5}, + {.value = 0x00070000, .expected_output = 13}, + {.value = 0x00000700, .expected_output = 21}, + {.value = 0x00000007, .expected_output = 29}, - { .value = 0x03000000, .expected_output = 6 }, - { .value = 0x00030000, .expected_output = 14 }, - { .value = 0x00000300, .expected_output = 22 }, - { .value = 0x00000003, .expected_output = 30 }, + {.value = 0x03000000, .expected_output = 6}, + {.value = 0x00030000, .expected_output = 14}, + {.value = 0x00000300, .expected_output = 22}, + {.value = 0x00000003, .expected_output = 30}, - { .value = 0x01000000, .expected_output = 7 }, - { .value = 0x00010000, .expected_output = 15 }, - { .value = 0x00000100, .expected_output = 23 }, - { .value = 0x00000001, .expected_output = 31 }, + {.value = 0x01000000, .expected_output = 7}, + {.value = 0x00010000, .expected_output = 15}, + {.value = 0x00000100, .expected_output = 23}, + {.value = 0x00000001, .expected_output = 31}, }; void test_clzsi2_with_data(void **state) diff --git a/tests/lib/list-test.c b/tests/lib/list-test.c index 309346abec..39bfb17f7c 100644 --- a/tests/lib/list-test.c +++ b/tests/lib/list-test.c @@ -116,12 +116,32 @@ void test_list_remove(void **state) free(c1); } +void test_list_append(void **state) +{ + size_t idx; + struct test_container *node; + struct list_node root = {}; + struct test_container nodes[] = { + {1}, {2}, {3} + }; + + for (idx = 0; idx < ARRAY_SIZE(nodes); ++idx) + list_append(&nodes[idx].list_node, &root); + + idx = 0; + list_for_each(node, root, list_node) { + assert_ptr_equal(node, &nodes[idx]); + idx++; + } +} + int main(void) { const struct CMUnitTest tests[] = { cmocka_unit_test(test_list_insert_after), cmocka_unit_test(test_list_insert_before), cmocka_unit_test(test_list_remove), + cmocka_unit_test(test_list_append), }; diff --git a/tests/lib/lzma-test.c b/tests/lib/lzma-test.c index 3918890e8e..b68d38e122 100644 --- a/tests/lib/lzma-test.c +++ b/tests/lib/lzma-test.c @@ -51,12 +51,12 @@ static int setup_ulzman_file(void **state) if (!s) return 1; - const size_t raw_filename_size = strlen(path_prefix) + strlen(fname_base) - + ARRAY_SIZE(raw_file_suffix); + const size_t raw_filename_size = + strlen(path_prefix) + strlen(fname_base) + ARRAY_SIZE(raw_file_suffix); s->raw_filename = test_malloc(raw_filename_size); - const size_t comp_filename_size = strlen(path_prefix) + strlen(fname_base) - + ARRAY_SIZE(comp_file_suffix); + const size_t comp_filename_size = + strlen(path_prefix) + strlen(fname_base) + ARRAY_SIZE(comp_file_suffix); s->comp_filename = test_malloc(comp_filename_size); if (!s->raw_filename || !s->comp_filename) { @@ -67,7 +67,7 @@ static int setup_ulzman_file(void **state) snprintf(s->raw_filename, raw_filename_size, path_prefix, fname_base, raw_file_suffix); snprintf(s->comp_filename, comp_filename_size, path_prefix, fname_base, - comp_file_suffix); + comp_file_suffix); s->raw_file_sz = get_file_size(s->raw_filename); s->comp_file_sz = get_file_size(s->comp_filename); @@ -117,10 +117,10 @@ static void test_ulzman_correct_file(void **state) assert_non_null(comp_buf); assert_int_equal(s->raw_file_sz, read_file(s->raw_filename, raw_buf, s->raw_file_sz)); assert_int_equal(s->comp_file_sz, - read_file(s->comp_filename, comp_buf, s->comp_file_sz)); + read_file(s->comp_filename, comp_buf, s->comp_file_sz)); assert_int_equal(s->raw_file_sz, - ulzman(comp_buf, s->comp_file_sz, decomp_buf, s->raw_file_sz)); + ulzman(comp_buf, s->comp_file_sz, decomp_buf, s->raw_file_sz)); assert_memory_equal(raw_buf, decomp_buf, s->raw_file_sz); test_free(raw_buf); @@ -130,7 +130,7 @@ static void test_ulzman_correct_file(void **state) static void test_ulzman_input_too_small(void **state) { - uint8_t in_buf[32]; + uint8_t in_buf[32] = {0}; uint8_t out_buf[32]; assert_int_equal(0, ulzman(in_buf, LZMA_PROPERTIES_SIZE, out_buf, sizeof(out_buf))); @@ -148,13 +148,11 @@ static void test_ulzman_zero_buffer(void **state) } #define ULZMAN_CORRECT_FILE_TEST(_file_prefix) \ -{ \ - .name = "test_ulzman_correct_file(" _file_prefix ")", \ - .test_func = test_ulzman_correct_file, \ - .setup_func = setup_ulzman_file, \ - .teardown_func = teardown_ulzman_file, \ - .initial_state = (_file_prefix) \ -} + { \ + .name = "test_ulzman_correct_file(" _file_prefix ")", \ + .test_func = test_ulzman_correct_file, .setup_func = setup_ulzman_file, \ + .teardown_func = teardown_ulzman_file, .initial_state = (_file_prefix) \ + } int main(void) { diff --git a/tests/lib/memchr-test.c b/tests/lib/memchr-test.c index eadabc7c9d..2575ce8b65 100644 --- a/tests/lib/memchr-test.c +++ b/tests/lib/memchr-test.c @@ -5,42 +5,28 @@ #include static const char test_data1[] = - "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; + "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; static const size_t test_data1_sz = sizeof(test_data1); static const char test_data2[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, - 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, - 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, - 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, - 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, - 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, - 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, - 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff - }; + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, + 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, + 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, + 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, + 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, + 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, + 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, + 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, + 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, + 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, + 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, + 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, + 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, + 0xfc, 0xfd, 0xfe, 0xff}; static const size_t test_data2_sz = sizeof(test_data2); static void test_memchr_existing_value(void **state) diff --git a/tests/lib/memcpy-test.c b/tests/lib/memcpy-test.c index f4f6e185a6..98303a49aa 100644 --- a/tests/lib/memcpy-test.c +++ b/tests/lib/memcpy-test.c @@ -116,7 +116,7 @@ static void test_memcpy_buffer_part(void **state) assert_memory_equal(s->buffer_to, s->helper_buffer, offset); assert_memory_equal(s->buffer_to + offset, s->buffer_from, sz); assert_memory_equal(s->buffer_to + offset + sz, s->helper_buffer + offset + sz, - MEMCPY_BUFFER_SZ - (offset + sz)); + MEMCPY_BUFFER_SZ - (offset + sz)); } static void test_memcpy_buffer_part_unaligned(void **state) @@ -138,7 +138,7 @@ static void test_memcpy_buffer_part_unaligned(void **state) assert_memory_equal(s->buffer_to, s->helper_buffer, dst_offset); assert_memory_equal(s->buffer_to + dst_offset, s->buffer_from + src_offset, sz); assert_memory_equal(s->buffer_to + dst_offset + sz, s->helper_buffer + dst_offset + sz, - MEMCPY_BUFFER_SZ - (dst_offset + sz)); + MEMCPY_BUFFER_SZ - (dst_offset + sz)); } static void test_memcpy_copy_to_itself(void **state) @@ -178,16 +178,16 @@ static void test_memcpy_copy_part_of_itself_to_itself(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_memcpy_full_buffer_copy, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memcpy_zero_size, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memcpy_buffer_part, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memcpy_buffer_part_unaligned, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memcpy_copy_to_itself, - setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memcpy_full_buffer_copy, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memcpy_zero_size, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memcpy_buffer_part, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memcpy_buffer_part_unaligned, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memcpy_copy_to_itself, setup_test, + teardown_test), cmocka_unit_test_setup_teardown(test_memcpy_copy_part_of_itself_to_itself, setup_test, teardown_test), }; diff --git a/tests/lib/memmove-test.c b/tests/lib/memmove-test.c index 87cace9c6a..3854dd65ac 100644 --- a/tests/lib/memmove-test.c +++ b/tests/lib/memmove-test.c @@ -115,7 +115,7 @@ static void test_memmove_buffer_part(void **state) assert_memory_equal(s->buffer_to, s->helper_buffer, offset); assert_memory_equal(s->buffer_to + offset, s->buffer_from, sz); assert_memory_equal(s->buffer_to + offset + sz, s->helper_buffer + offset + sz, - MEMMOVE_BUFFER_SZ - (offset + sz)); + MEMMOVE_BUFFER_SZ - (offset + sz)); } static void test_memmove_buffer_part_unaligned(void **state) @@ -137,7 +137,7 @@ static void test_memmove_buffer_part_unaligned(void **state) assert_memory_equal(s->buffer_to, s->helper_buffer, dst_offset); assert_memory_equal(s->buffer_to + dst_offset, s->buffer_from + src_offset, sz); assert_memory_equal(s->buffer_to + dst_offset + sz, s->helper_buffer + dst_offset + sz, - MEMMOVE_BUFFER_SZ - (dst_offset + sz)); + MEMMOVE_BUFFER_SZ - (dst_offset + sz)); } static void test_memmove_copy_to_itself(void **state) @@ -225,26 +225,25 @@ static void test_memmove_self_lower_to_higher_unaligned(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_memmove_full_buffer_copy, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_zero_size, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_buffer_part, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_buffer_part_unaligned, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_copy_to_itself, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_self_higher_to_lower, - setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_full_buffer_copy, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_zero_size, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_buffer_part, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_buffer_part_unaligned, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_copy_to_itself, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_higher_to_lower, setup_test, + teardown_test), cmocka_unit_test_setup_teardown(test_memmove_self_higher_to_lower_unaligned, setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memmove_self_lower_to_higher, - setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_lower_to_higher, setup_test, + teardown_test), cmocka_unit_test_setup_teardown(test_memmove_self_lower_to_higher_unaligned, setup_test, teardown_test), }; return cb_run_group_tests(tests, NULL, NULL); } - diff --git a/tests/lib/memrange-test.c b/tests/lib/memrange-test.c index 1bdd62e028..25eb1aaaa4 100644 --- a/tests/lib/memrange-test.c +++ b/tests/lib/memrange-test.c @@ -22,36 +22,54 @@ enum mem_types { /* Indices of entries matters, since it must reflect mem_types enum */ struct resource res_mock_1[] = { - [CACHEABLE_TAG] = { .base = 0xE000, .size = 0xF2000, - .next = &res_mock_1[RESERVED_TAG], .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM }, - [RESERVED_TAG] = { .base = 4ULL * GiB, .size = 4ULL * KiB, - .next = &res_mock_1[READONLY_TAG], .flags = IORESOURCE_RESERVE | IORESOURCE_MEM }, - [READONLY_TAG] = { .base = 0xFF0000, .size = 0x10000, .next = NULL, - .flags = IORESOURCE_READONLY | IORESOURCE_MEM } + [CACHEABLE_TAG] = {.base = 0xE000, + .size = 0xF2000, + .next = &res_mock_1[RESERVED_TAG], + .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM}, + [RESERVED_TAG] = {.base = 4ULL * GiB, + .size = 4ULL * KiB, + .next = &res_mock_1[READONLY_TAG], + .flags = IORESOURCE_RESERVE | IORESOURCE_MEM}, + [READONLY_TAG] = {.base = 0xFF0000, + .size = 0x10000, + .next = NULL, + .flags = IORESOURCE_READONLY | IORESOURCE_MEM} }; /* Boundary 1 byte below 4GiB and 1 byte above 4GiB. */ struct resource res_mock_2[] = { - [CACHEABLE_TAG] = { .base = 0x1000000, .size = 4ULL * GiB - 0x1000001ULL, - .next = &res_mock_2[RESERVED_TAG], .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM }, - [RESERVED_TAG] = { .base = 4ULL * GiB + 1ULL, .size = 4ULL * GiB, - .next = &res_mock_2[READONLY_TAG], .flags = IORESOURCE_RESERVE | IORESOURCE_MEM }, - [READONLY_TAG] = { .base = 0, .size = 0x10000, .next = NULL, - .flags = IORESOURCE_READONLY | IORESOURCE_MEM} + [CACHEABLE_TAG] = {.base = 0x1000000, + .size = 4ULL * GiB - 0x1000001ULL, + .next = &res_mock_2[RESERVED_TAG], + .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM}, + [RESERVED_TAG] = {.base = 4ULL * GiB + 1ULL, + .size = 4ULL * GiB, + .next = &res_mock_2[READONLY_TAG], + .flags = IORESOURCE_RESERVE | IORESOURCE_MEM}, + [READONLY_TAG] = {.base = 0, + .size = 0x10000, + .next = NULL, + .flags = IORESOURCE_READONLY | IORESOURCE_MEM} }; /* Boundary crossing 4GiB. */ struct resource res_mock_3[] = { - [CACHEABLE_TAG] = { .base = 0xD000, .size = 0xF3000, - .next = &res_mock_3[RESERVED_TAG], .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM }, - [RESERVED_TAG] = { .base = 1ULL * GiB, .size = 4ULL * GiB, - .next = &res_mock_3[READONLY_TAG], .flags = IORESOURCE_RESERVE | IORESOURCE_MEM }, - [READONLY_TAG] = { .base = 0xFF0000, .size = 0x10000, .next = NULL, - .flags = IORESOURCE_READONLY | IORESOURCE_MEM} + [CACHEABLE_TAG] = {.base = 0xD000, + .size = 0xF3000, + .next = &res_mock_3[RESERVED_TAG], + .flags = IORESOURCE_CACHEABLE | IORESOURCE_MEM}, + [RESERVED_TAG] = {.base = 1ULL * GiB, + .size = 4ULL * GiB, + .next = &res_mock_3[READONLY_TAG], + .flags = IORESOURCE_RESERVE | IORESOURCE_MEM}, + [READONLY_TAG] = {.base = 0xFF0000, + .size = 0x10000, + .next = NULL, + .flags = IORESOURCE_READONLY | IORESOURCE_MEM} }; -struct device mock_device = { .enabled = 1 }; +struct device mock_device = {.enabled = 1}; /* Fake memory devices handle */ struct device *all_devices = &mock_device; @@ -87,9 +105,8 @@ resource_t get_aligned_base(struct resource *res, struct range_entry *entry) resource_t get_aligned_end(struct resource *res, struct range_entry *entry) { - resource_t end = res[range_entry_tag(entry)].base + - res[range_entry_tag(entry)].size + - (res[range_entry_tag(entry)].base - range_entry_base(entry)); + resource_t end = res[range_entry_tag(entry)].base + res[range_entry_tag(entry)].size + + (res[range_entry_tag(entry)].base - range_entry_base(entry)); return ALIGN_UP(end, MEMRANGE_ALIGN); } @@ -136,7 +153,8 @@ static void test_memrange_basic(void **state) /* There should be two entries, since cacheable and reserved regions are not neighbors */ - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { assert_in_range(range_entry_tag(ptr), CACHEABLE_TAG, RESERVED_TAG); assert_int_equal(range_entry_base(ptr), get_aligned_base(res_mock, ptr)); @@ -153,8 +171,7 @@ static void test_memrange_basic(void **state) /* Remove initial memrange */ memranges_teardown(&test_memrange); - memranges_each_entry(ptr, &test_memrange) - counter++; + memranges_each_entry(ptr, &test_memrange) counter++; assert_int_equal(counter, 0); } @@ -205,7 +222,8 @@ static void test_memrange_clone_insert(void **state) memranges_teardown(&test_memrange); /* Verify that new one is really a clone */ - memranges_each_entry(ptr, &clone_memrange) { + memranges_each_entry(ptr, &clone_memrange) + { assert_in_range(range_entry_tag(ptr), CACHEABLE_TAG, END_OF_RESOURCES - 1); assert_int_equal(range_entry_base(ptr), get_aligned_base(res_mock, ptr)); @@ -221,7 +239,8 @@ static void test_memrange_clone_insert(void **state) res_mock[CACHEABLE_TAG].size, INSERTED_TAG); /* Three ranges should be there - CACHEABLE(shrunk), INSERTED and RESERVED */ - memranges_each_entry(ptr, &clone_memrange) { + memranges_each_entry(ptr, &clone_memrange) + { resource_t expected_end; if (range_entry_tag(ptr) == CACHEABLE_TAG) { @@ -234,10 +253,10 @@ static void test_memrange_clone_insert(void **state) assert_int_equal(range_entry_base(ptr), res_mock[CACHEABLE_TAG].base + new_range_begin_offset); - expected_end = res_mock[CACHEABLE_TAG].base + new_range_begin_offset + - res_mock[CACHEABLE_TAG].size; + expected_end = res_mock[CACHEABLE_TAG].base + new_range_begin_offset + + res_mock[CACHEABLE_TAG].size; assert_int_equal(range_entry_end(ptr), - ALIGN_UP(expected_end, MEMRANGE_ALIGN)); + ALIGN_UP(expected_end, MEMRANGE_ALIGN)); } counter++; } @@ -248,7 +267,8 @@ static void test_memrange_clone_insert(void **state) * Additionally verify API for updating tags */ memranges_update_tag(&clone_memrange, INSERTED_TAG, READONLY_TAG); - memranges_each_entry(ptr, &clone_memrange) { + memranges_each_entry(ptr, &clone_memrange) + { resource_t expected_end; assert_int_not_equal(range_entry_tag(ptr), INSERTED_TAG); @@ -256,10 +276,10 @@ static void test_memrange_clone_insert(void **state) assert_int_equal(range_entry_base(ptr), res_mock[CACHEABLE_TAG].base + new_range_begin_offset); - expected_end = res_mock[CACHEABLE_TAG].base + new_range_begin_offset + - res_mock[CACHEABLE_TAG].size; + expected_end = res_mock[CACHEABLE_TAG].base + new_range_begin_offset + + res_mock[CACHEABLE_TAG].size; assert_int_equal(range_entry_end(ptr), - ALIGN_UP(expected_end, MEMRANGE_ALIGN)); + ALIGN_UP(expected_end, MEMRANGE_ALIGN)); } }; @@ -267,17 +287,18 @@ static void test_memrange_clone_insert(void **state) memranges_insert(&clone_memrange, res_mock[RESERVED_TAG].base + 0xAD, res_mock[RESERVED_TAG].size, INSERTED_TAG); - memranges_each_entry(ptr, &clone_memrange) { + memranges_each_entry(ptr, &clone_memrange) + { resource_t expected_end; assert_int_not_equal(range_entry_tag(ptr), RESERVED_TAG); if (range_entry_tag(ptr) == INSERTED_TAG) { - assert_int_equal(range_entry_base(ptr), - ALIGN_DOWN(res_mock[RESERVED_TAG].base, - MEMRANGE_ALIGN)); + assert_int_equal( + range_entry_base(ptr), + ALIGN_DOWN(res_mock[RESERVED_TAG].base, MEMRANGE_ALIGN)); - expected_end = ALIGN_DOWN(res_mock[RESERVED_TAG].base, MEMRANGE_ALIGN) + - new_range_begin_offset + res_mock[RESERVED_TAG].size; + expected_end = ALIGN_DOWN(res_mock[RESERVED_TAG].base, MEMRANGE_ALIGN) + + new_range_begin_offset + res_mock[RESERVED_TAG].size; expected_end = ALIGN_UP(expected_end, MEMRANGE_ALIGN); assert_int_equal(range_entry_end(ptr), expected_end); @@ -329,7 +350,8 @@ static void test_memrange_holes(void **state) memranges_add_resources(&test_memrange, reserved, reserved, RESERVED_TAG); /* Count holes in ranges */ - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { if (!last_range_end) { last_range_end = range_entry_end(ptr); continue; @@ -349,12 +371,13 @@ static void test_memrange_holes(void **state) (but with different tags) */ memranges_fill_holes_up_to(&test_memrange, holes_fill_end, HOLE_TAG); - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { if (range_entry_tag(ptr) == HOLE_TAG) { assert_int_equal(range_entry_base(ptr), - ALIGN_UP(res_mock[CACHEABLE_TAG].base + - res_mock[CACHEABLE_TAG].size, - MEMRANGE_ALIGN)); + ALIGN_UP(res_mock[CACHEABLE_TAG].base + + res_mock[CACHEABLE_TAG].size, + MEMRANGE_ALIGN)); assert_int_equal(range_entry_end(ptr), holes_fill_end); /* Store pointer to HOLE_TAG region for future use */ hole_ptr = ptr; @@ -372,15 +395,16 @@ static void test_memrange_holes(void **state) /* Create hole crossing the border of two range entries */ const resource_t new_cacheable_end = ALIGN_DOWN( - res_mock[CACHEABLE_TAG].base + res_mock[CACHEABLE_TAG].size - 4 * KiB, - MEMRANGE_ALIGN); - const resource_t new_hole_begin = ALIGN_UP(range_entry_base(hole_ptr) + 4 * KiB, - MEMRANGE_ALIGN); + res_mock[CACHEABLE_TAG].base + res_mock[CACHEABLE_TAG].size - 4 * KiB, + MEMRANGE_ALIGN); + const resource_t new_hole_begin = + ALIGN_UP(range_entry_base(hole_ptr) + 4 * KiB, MEMRANGE_ALIGN); const resource_t ranges_diff = new_hole_begin - new_cacheable_end; memranges_create_hole(&test_memrange, new_cacheable_end, ranges_diff); - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { switch (range_entry_tag(ptr)) { case CACHEABLE_TAG: assert_int_equal(range_entry_base(ptr), res_mock[CACHEABLE_TAG].base); @@ -388,8 +412,9 @@ static void test_memrange_holes(void **state) break; case RESERVED_TAG: assert_int_equal(range_entry_base(ptr), res_mock[RESERVED_TAG].base); - assert_int_equal(range_entry_end(ptr), res_mock[RESERVED_TAG].base + - res_mock[RESERVED_TAG].size); + assert_int_equal(range_entry_end(ptr), + res_mock[RESERVED_TAG].base + + res_mock[RESERVED_TAG].size); break; case HOLE_TAG: assert_int_equal(range_entry_base(ptr), new_hole_begin); @@ -448,18 +473,19 @@ static void test_memrange_steal(void **state) memranges_add_resources(&test_memrange, reserved, reserved, RESERVED_TAG); memranges_add_resources(&test_memrange, readonly, readonly, READONLY_TAG); - status = memranges_steal(&test_memrange, res_mock[RESERVED_TAG].base + - res_mock[RESERVED_TAG].size, + status = memranges_steal(&test_memrange, + res_mock[RESERVED_TAG].base + res_mock[RESERVED_TAG].size, stolen_range_size, 12, READONLY_TAG, &stolen); assert_true(status); - assert_in_range(stolen, res_mock[READONLY_TAG].base, res_mock[READONLY_TAG].base + - res_mock[READONLY_TAG].size); + assert_in_range(stolen, res_mock[READONLY_TAG].base, + res_mock[READONLY_TAG].base + res_mock[READONLY_TAG].size); - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { if (range_entry_tag(ptr) == READONLY_TAG) { assert_int_equal(range_entry_base(ptr), - ALIGN_DOWN(res_mock[READONLY_TAG].base, MEMRANGE_ALIGN) - + stolen_range_size); + ALIGN_DOWN(res_mock[READONLY_TAG].base, MEMRANGE_ALIGN) + + stolen_range_size); } count++; } @@ -468,16 +494,17 @@ static void test_memrange_steal(void **state) /* Check if inserting range in previously stolen area will merge it. */ memranges_insert(&test_memrange, res_mock[READONLY_TAG].base + 0xCC, stolen_range_size, - READONLY_TAG); - memranges_each_entry(ptr, &test_memrange) { + READONLY_TAG); + memranges_each_entry(ptr, &test_memrange) + { if (range_entry_tag(ptr) == READONLY_TAG) { - assert_int_equal(range_entry_base(ptr), - ALIGN_DOWN(res_mock[READONLY_TAG].base, - MEMRANGE_ALIGN)); - assert_int_equal(range_entry_end(ptr), - ALIGN_UP(range_entry_base(ptr) + - res_mock[READONLY_TAG].size, - MEMRANGE_ALIGN)); + assert_int_equal( + range_entry_base(ptr), + ALIGN_DOWN(res_mock[READONLY_TAG].base, MEMRANGE_ALIGN)); + assert_int_equal( + range_entry_end(ptr), + ALIGN_UP(range_entry_base(ptr) + res_mock[READONLY_TAG].size, + MEMRANGE_ALIGN)); } count++; } @@ -489,12 +516,13 @@ static void test_memrange_steal(void **state) /* Utility function checking number of entries and alignment of their base and end pointers */ static void check_range_entries_count_and_alignment(struct memranges *ranges, - size_t ranges_count, resource_t alignment) + size_t ranges_count, resource_t alignment) { size_t count = 0; struct range_entry *ptr; - memranges_each_entry(ptr, ranges) { + memranges_each_entry(ptr, ranges) + { assert_true(IS_ALIGNED(range_entry_base(ptr), alignment)); assert_true(IS_ALIGNED(range_entry_end(ptr), alignment)); @@ -511,7 +539,7 @@ static void test_memrange_init_and_teardown(void **state) const unsigned long reserved = IORESOURCE_RESERVE; const unsigned long readonly = IORESOURCE_READONLY; struct memranges test_memrange; - struct range_entry range_entries[4] = { 0 }; + struct range_entry range_entries[4] = {0}; /* Test memranges_init() correctness */ memranges_init(&test_memrange, cacheable, cacheable, CACHEABLE_TAG); @@ -527,8 +555,7 @@ static void test_memrange_init_and_teardown(void **state) /* Test memranges_init_with_alignment() correctness with alignment of 1KiB (2^10) */ - memranges_init_with_alignment(&test_memrange, cacheable, cacheable, - CACHEABLE_TAG, 10); + memranges_init_with_alignment(&test_memrange, cacheable, cacheable, CACHEABLE_TAG, 10); memranges_add_resources(&test_memrange, reserved, reserved, RESERVED_TAG); memranges_add_resources(&test_memrange, readonly, readonly, READONLY_TAG); @@ -554,7 +581,7 @@ static void test_memrange_init_and_teardown(void **state) /* Test memranges_init_with_alignment() correctness with alignment of 8KiB (2^13) */ memranges_init_empty_with_alignment(&test_memrange, &range_entries[0], - ARRAY_SIZE(range_entries), 13); + ARRAY_SIZE(range_entries), 13); assert_true(memranges_is_empty(&test_memrange)); memranges_add_resources(&test_memrange, cacheable, cacheable, CACHEABLE_TAG); @@ -595,10 +622,11 @@ static void test_memrange_add_resources_filter(void **state) /* Check if filter accepts range correctly */ memranges_init(&test_memrange, reserved, reserved, RESERVED_TAG); memranges_add_resources_filter(&test_memrange, cacheable, cacheable, CACHEABLE_TAG, - memrange_filter_mem_only); + memrange_filter_mem_only); /* Check if filter accepted desired range. */ - memranges_each_entry(ptr, &test_memrange) { + memranges_each_entry(ptr, &test_memrange) + { assert_in_set(range_entry_tag(ptr), accepted_tags, ARRAY_SIZE(accepted_tags)); assert_true(IS_ALIGNED(range_entry_base(ptr), MEMRANGE_ALIGN)); assert_true(IS_ALIGNED(range_entry_end(ptr), MEMRANGE_ALIGN)); @@ -611,7 +639,7 @@ static void test_memrange_add_resources_filter(void **state) /* Check if filter rejects range correctly */ memranges_init(&test_memrange, reserved, reserved, RESERVED_TAG); memranges_add_resources_filter(&test_memrange, cacheable, cacheable, CACHEABLE_TAG, - memrange_filter_non_mem); + memrange_filter_non_mem); check_range_entries_count_and_alignment(&test_memrange, 1, MEMRANGE_ALIGN); @@ -629,10 +657,10 @@ int main(void) cmocka_unit_test(test_memrange_add_resources_filter), }; - return cmocka_run_group_tests_name(__TEST_NAME__"(Boundary on 4GiB)", - tests, setup_test_1, NULL) + - cmocka_run_group_tests_name(__TEST_NAME__"(Boundaries 1 byte from 4GiB)", - tests, setup_test_2, NULL) + - cmocka_run_group_tests_name(__TEST_NAME__"(Range over 4GiB boundary)", - tests, setup_test_3, NULL); + return cmocka_run_group_tests_name(__TEST_NAME__ "(Boundary on 4GiB)", tests, + setup_test_1, NULL) + + cmocka_run_group_tests_name(__TEST_NAME__ "(Boundaries 1 byte from 4GiB)", + tests, setup_test_2, NULL) + + cmocka_run_group_tests_name(__TEST_NAME__ "(Range over 4GiB boundary)", tests, + setup_test_3, NULL); } diff --git a/tests/lib/memset-test.c b/tests/lib/memset-test.c index bdc3cb3104..b0be91f477 100644 --- a/tests/lib/memset-test.c +++ b/tests/lib/memset-test.c @@ -106,14 +106,14 @@ static void test_memset_one_byte(void **state) int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_memset_full_range, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memset_subrange, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memset_zero_size, - setup_test, teardown_test), - cmocka_unit_test_setup_teardown(test_memset_one_byte, - setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memset_full_range, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memset_subrange, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memset_zero_size, setup_test, + teardown_test), + cmocka_unit_test_setup_teardown(test_memset_one_byte, setup_test, + teardown_test), }; return cb_run_group_tests(tests, NULL, NULL); diff --git a/tests/lib/region_file-test.c b/tests/lib/region_file-test.c index 98c4eb650b..56bb8e4f01 100644 --- a/tests/lib/region_file-test.c +++ b/tests/lib/region_file-test.c @@ -243,12 +243,12 @@ static void test_region_file_update_data_arr(void **state) for (int i = 0; i < dummy_data_size; ++i) dummy_data[i] = 'A' + i % ('Z' - 'A'); - update_entries[0] = (struct update_region_file_entry) - { .size = data1_size, .data = &dummy_data[data1_offset] }; - update_entries[1] = (struct update_region_file_entry) - { .size = data2_size, .data = &dummy_data[data2_offset] }; - update_entries[2] = (struct update_region_file_entry) - { .size = data3_size, .data = &dummy_data[data3_offset] }; + update_entries[0] = (struct update_region_file_entry){ + .size = data1_size, .data = &dummy_data[data1_offset]}; + update_entries[1] = (struct update_region_file_entry){ + .size = data2_size, .data = &dummy_data[data2_offset]}; + update_entries[2] = (struct update_region_file_entry){ + .size = data3_size, .data = &dummy_data[data3_offset]}; ret = region_file_init(®f, rdev); assert_int_equal(0, ret); @@ -274,10 +274,9 @@ static void test_region_file_update_data_arr(void **state) ret = rdev_readat(&read_rdev, output_buffer, 0, data1_size + data2_size + data3_size); assert_int_equal(data1_size + data2_size + data3_size, ret); assert_memory_equal(&dummy_data[data1_offset], output_buffer, data1_size); - assert_memory_equal(&dummy_data[data2_offset], - &output_buffer[data1_size], data2_size); - assert_memory_equal(&dummy_data[data3_offset], - &output_buffer[data1_size + data2_size], data3_size); + assert_memory_equal(&dummy_data[data2_offset], &output_buffer[data1_size], data2_size); + assert_memory_equal(&dummy_data[data3_offset], &output_buffer[data1_size + data2_size], + data3_size); /* Check if data is correctly shrunk down to smaller size and different content */ ret = region_file_update_data_arr(®f, &update_entries[1], 2); @@ -294,35 +293,35 @@ int main(void) { const struct CMUnitTest tests[] = { cmocka_unit_test_setup_teardown(test_region_file_init_empty, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_invalid_metadata, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_valid_no_data, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_invalid_data_offset, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_correct_data_offset, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_real_data, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_init_invalid_region_device, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_data, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_update_data, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), cmocka_unit_test_setup_teardown(test_region_file_update_data_arr, - setup_teardown_region_file_test, - setup_teardown_region_file_test), + setup_teardown_region_file_test, + setup_teardown_region_file_test), }; return cb_run_group_tests(tests, setup_region_file_test_group, diff --git a/tests/lib/rtc-test.c b/tests/lib/rtc-test.c index e9415714a5..c3c7403a4b 100644 --- a/tests/lib/rtc-test.c +++ b/tests/lib/rtc-test.c @@ -163,37 +163,37 @@ static void test_rtc_mktime_with_rtc_to_tm(void **state) /* Conversion from rtc_time to timestamp and back to rtc_time */ tm_in = (struct rtc_time){ - .year = 1970, .mon = 1, .mday = 1, .hour = 0, .min = 0, .sec = 0, .wday = 4 + .year = 1970, .mon = 1, .mday = 1, .hour = 0, .min = 0, .sec = 0, .wday = 4, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); tm_in = (struct rtc_time){ - .year = 2000, .mon = 2, .mday = 29, .hour = 13, .min = 4, .sec = 15, .wday = 2 + .year = 2000, .mon = 2, .mday = 29, .hour = 13, .min = 4, .sec = 15, .wday = 2, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); tm_in = (struct rtc_time){ - .year = 2000, .mon = 3, .mday = 1, .hour = 13, .min = 8, .sec = 37, .wday = 3 + .year = 2000, .mon = 3, .mday = 1, .hour = 13, .min = 8, .sec = 37, .wday = 3, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); tm_in = (struct rtc_time){ - .year = 2017, .mon = 12, .mday = 7, .hour = 8, .min = 18, .sec = 9, .wday = 4 + .year = 2017, .mon = 12, .mday = 7, .hour = 8, .min = 18, .sec = 9, .wday = 4, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); tm_in = (struct rtc_time){ - .year = 2020, .mon = 2, .mday = 29, .hour = 18, .min = 50, .sec = 0, .wday = 6 + .year = 2020, .mon = 2, .mday = 29, .hour = 18, .min = 50, .sec = 0, .wday = 6, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); tm_in = (struct rtc_time){ - .year = 2020, .mon = 3, .mday = 1, .hour = 1, .min = 20, .sec = 23, .wday = 0 + .year = 2020, .mon = 3, .mday = 1, .hour = 1, .min = 20, .sec = 23, .wday = 0, }; assert_int_equal(0, rtc_to_tm(rtc_mktime(&tm_in), &tm_out)); assert_rtc_time_equal(&tm_in, &tm_out); @@ -246,53 +246,53 @@ static void test_leap_day_secday(void **state) memset(&tm_out, 0, sizeof(tm_out)); /* Non-leap year */ - tm_in = (struct rtc_time) { - .year = 1999, .mon = 2, .mday = 28, .hour = 5, .min = 37, .sec = 15, .wday = 0 + tm_in = (struct rtc_time){ + .year = 1999, .mon = 2, .mday = 28, .hour = 5, .min = 37, .sec = 15, .wday = 0, }; tim = rtc_mktime(&tm_in) + secday; - tm_expected = (struct rtc_time) { - .year = 1999, .mon = 3, .mday = 1, .hour = 5, .min = 37, .sec = 15, .wday = 1 + tm_expected = (struct rtc_time){ + .year = 1999, .mon = 3, .mday = 1, .hour = 5, .min = 37, .sec = 15, .wday = 1, }; assert_int_equal(0, rtc_to_tm(tim, &tm_out)); assert_rtc_time_equal(&tm_out, &tm_expected); /* Leap-year February 28 to February 29 */ - tm_in = (struct rtc_time) { + tm_in = (struct rtc_time){ .year = 2000, .mon = 2, .mday = 28, .hour = 0, .min = 33, .sec = 11, .wday = 1, }; tim = rtc_mktime(&tm_in) + secday; - tm_expected = (struct rtc_time) { + tm_expected = (struct rtc_time){ .year = 2000, .mon = 2, .mday = 29, .hour = 0, .min = 33, .sec = 11, .wday = 2, }; assert_int_equal(0, rtc_to_tm(tim, &tm_out)); assert_rtc_time_equal(&tm_out, &tm_expected); - tm_in = (struct rtc_time) { + tm_in = (struct rtc_time){ .year = 2004, .mon = 2, .mday = 28, .hour = 9, .min = 13, .sec = 45, .wday = 6, }; tim = rtc_mktime(&tm_in) + secday; - tm_expected = (struct rtc_time) { + tm_expected = (struct rtc_time){ .year = 2004, .mon = 2, .mday = 29, .hour = 9, .min = 13, .sec = 45, .wday = 0, }; assert_int_equal(0, rtc_to_tm(tim, &tm_out)); assert_rtc_time_equal(&tm_out, &tm_expected); /* Leap-year February 29 to March 1 */ - tm_in = (struct rtc_time) { + tm_in = (struct rtc_time){ .year = 2000, .mon = 2, .mday = 29, .hour = 22, .min = 50, .sec = 25, .wday = 2, }; tim = rtc_mktime(&tm_in) + secday; - tm_expected = (struct rtc_time) { + tm_expected = (struct rtc_time){ .year = 2000, .mon = 3, .mday = 1, .hour = 22, .min = 50, .sec = 25, .wday = 3, }; assert_int_equal(0, rtc_to_tm(tim, &tm_out)); assert_rtc_time_equal(&tm_out, &tm_expected); - tm_in = (struct rtc_time) { + tm_in = (struct rtc_time){ .year = 2004, .mon = 2, .mday = 29, .hour = 17, .min = 56, .sec = 27, .wday = 0, }; tim = rtc_mktime(&tm_in) + secday; - tm_expected = (struct rtc_time) { + tm_expected = (struct rtc_time){ .year = 2004, .mon = 3, .mday = 1, .hour = 17, .min = 56, .sec = 27, .wday = 1, }; assert_int_equal(0, rtc_to_tm(tim, &tm_out)); diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c index 4f75690979..e1c1777bc6 100644 --- a/tests/lib/spd_cache-test.c +++ b/tests/lib/spd_cache-test.c @@ -62,12 +62,10 @@ static void test_load_spd_cache(void **state) static void calc_spd_cache_crc(uint8_t *spd_cache) { - *(uint16_t *)(spd_cache + SC_CRC_OFFSET) = - CRC(spd_cache, SC_SPD_TOTAL_LEN, crc16_byte); + *(uint16_t *)(spd_cache + SC_CRC_OFFSET) = CRC(spd_cache, SC_SPD_TOTAL_LEN, crc16_byte); } -__attribute__((unused)) -static void fill_spd_cache_ddr3(uint8_t *spd_cache, size_t spd_cache_sz) +__attribute__((unused)) static void fill_spd_cache_ddr3(uint8_t *spd_cache, size_t spd_cache_sz) { assert_true(spd_cache_sz >= (spd_data_ddr3_1_sz + sizeof(uint16_t))); @@ -76,16 +74,15 @@ static void fill_spd_cache_ddr3(uint8_t *spd_cache, size_t spd_cache_sz) calc_spd_cache_crc(spd_cache); } -__attribute__((unused)) -static void fill_spd_cache_ddr4(uint8_t *spd_cache, size_t spd_cache_sz) +__attribute__((unused)) static void fill_spd_cache_ddr4(uint8_t *spd_cache, size_t spd_cache_sz) { - assert_true(spd_cache_sz >= - (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz + sizeof(uint16_t))); + assert_true(spd_cache_sz + >= (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz + sizeof(uint16_t))); memcpy(spd_cache, spd_data_ddr4_1, spd_data_ddr4_1_sz); memcpy(spd_cache + spd_data_ddr4_1_sz, spd_data_ddr4_2, spd_data_ddr4_2_sz); memset(spd_cache + spd_data_ddr4_1_sz + spd_data_ddr4_2_sz, 0, - spd_cache_sz - (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz)); + spd_cache_sz - (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz)); calc_spd_cache_crc(spd_cache); } @@ -127,7 +124,7 @@ static void test_spd_cache_is_valid(void **state) /* Used for setting `sn` parameter value */ -static u32 get_spd_sn_ret_sn[SC_SPD_NUMS] = { 0 }; +static u32 get_spd_sn_ret_sn[SC_SPD_NUMS] = {0}; static size_t get_spd_sn_ret_sn_idx = 0; /* Implementation for testing purposes. */ enum cb_err get_spd_sn(u8 addr, u32 *sn) @@ -145,12 +142,11 @@ static void get_sn_from_spd_cache(uint8_t *spd_cache, u32 arr[]) } /* check_if_dimm_changed() has is used only with DDR4, so there tests are not used for DDR3 */ -__attribute__((unused)) -static void test_check_if_dimm_changed_not_changed(void **state) +__attribute__((unused)) static void test_check_if_dimm_changed_not_changed(void **state) { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = { .addr_map = {0}, .spd_array = {0}, .len = 0 }; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -162,12 +158,11 @@ static void test_check_if_dimm_changed_not_changed(void **state) assert_false(check_if_dimm_changed(spd_cache, &blk)); } -__attribute__((unused)) -static void test_check_if_dimm_changed_sn_error(void **state) +__attribute__((unused)) static void test_check_if_dimm_changed_sn_error(void **state) { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = { .addr_map = {0}, .spd_array = {0}, .len = 0 }; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -178,12 +173,11 @@ static void test_check_if_dimm_changed_sn_error(void **state) assert_true(check_if_dimm_changed(spd_cache, &blk)); } -__attribute__((unused)) -static void test_check_if_dimm_changed_sodimm_lost(void **state) +__attribute__((unused)) static void test_check_if_dimm_changed_sodimm_lost(void **state) { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = { .addr_map = {0}, .spd_array = {0}, .len = 0 }; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -196,31 +190,29 @@ static void test_check_if_dimm_changed_sodimm_lost(void **state) assert_true(check_if_dimm_changed(spd_cache, &blk)); } -__attribute__((unused)) -static void test_check_if_dimm_changed_new_sodimm(void **state) +__attribute__((unused)) static void test_check_if_dimm_changed_new_sodimm(void **state) { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = { .addr_map = {0}, .spd_array = {0}, .len = 0 }; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); - memcpy(spd_cache + spd_data_ddr4_1_sz + spd_data_ddr4_2_sz, - spd_data_ddr4_2, spd_data_ddr4_2_sz); + memcpy(spd_cache + spd_data_ddr4_1_sz + spd_data_ddr4_2_sz, spd_data_ddr4_2, + spd_data_ddr4_2_sz); get_spd_sn_ret_sn_idx = 0; will_return_always(get_spd_sn, CB_SUCCESS); assert_true(check_if_dimm_changed(spd_cache, &blk)); } -__attribute__((unused)) -static void test_check_if_dimm_changed_sn_changed(void **state) +__attribute__((unused)) static void test_check_if_dimm_changed_sn_changed(void **state) { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = { .addr_map = {0}, .spd_array = {0}, .len = 0 }; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); fill_spd_cache_ddr4(spd_cache, spd_cache_sz); @@ -241,15 +233,15 @@ int main(void) cmocka_unit_test_setup(test_spd_cache_is_valid, setup_spd_cache_test), #if __TEST_SPD_CACHE_DDR == 4 cmocka_unit_test_setup(test_check_if_dimm_changed_not_changed, - setup_spd_cache_test), + setup_spd_cache_test), cmocka_unit_test_setup(test_check_if_dimm_changed_sn_error, - setup_spd_cache_test), + setup_spd_cache_test), cmocka_unit_test_setup(test_check_if_dimm_changed_sodimm_lost, - setup_spd_cache_test), + setup_spd_cache_test), cmocka_unit_test_setup(test_check_if_dimm_changed_new_sodimm, - setup_spd_cache_test), + setup_spd_cache_test), cmocka_unit_test_setup(test_check_if_dimm_changed_sn_changed, - setup_spd_cache_test), + setup_spd_cache_test), #endif }; diff --git a/tests/lib/stack-test.c b/tests/lib/stack-test.c index 1f671f39cb..583fe4954f 100644 --- a/tests/lib/stack-test.c +++ b/tests/lib/stack-test.c @@ -6,9 +6,9 @@ #if CONFIG_STACK_SIZE == 0 -# define STACK_SIZE 0x1000 +#define STACK_SIZE 0x1000 #else -# define STACK_SIZE CONFIG_STACK_SIZE +#define STACK_SIZE CONFIG_STACK_SIZE #endif /* Value used for stack initialization. Change if implementation changes. */ diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c index ad33ed08c0..06a5a00142 100644 --- a/tests/lib/timestamp-test.c +++ b/tests/lib/timestamp-test.c @@ -32,7 +32,7 @@ void test_timestamp_add(void **state) entry = &glob_ts_table->entries[0]; assert_int_equal(1, entry->entry_id); assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ - entry->entry_stamp); + entry->entry_stamp); /* Add few timestamps to check if all of them will be added properly */ for (i = 1; i < 10; ++i) @@ -43,8 +43,7 @@ void test_timestamp_add(void **state) for (i = 0; i < 10; ++i) { entry = &glob_ts_table->entries[i]; assert_int_equal(i + 1, entry->entry_id); - assert_int_equal(base_multipler * (i + 1) - timestamp_base, - entry->entry_stamp); + assert_int_equal(base_multipler * (i + 1) - timestamp_base, entry->entry_stamp); } } @@ -70,7 +69,7 @@ void test_timestamp_add_now(void **state) assert_int_equal(1, entry->entry_id); assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ - entry->entry_stamp); + entry->entry_stamp); } void test_timestamp_rescale_table(void **state) diff --git a/tests/mock/cbfs_file_mock.c b/tests/mock/cbfs_file_mock.c index 2be89b06b3..09e23e2a7d 100644 --- a/tests/mock/cbfs_file_mock.c +++ b/tests/mock/cbfs_file_mock.c @@ -4,14 +4,14 @@ TEST_REGION(cbfs_cache, TEST_CBFS_CACHE_SIZE); -const u8 test_data_1[TEST_DATA_1_SIZE] = { TEST_DATA_1 }; -const u8 test_data_2[TEST_DATA_2_SIZE] = { TEST_DATA_2 }; -const u8 test_data_int_1[TEST_DATA_INT_1_SIZE] = { LE64(TEST_DATA_INT_1) }; -const u8 test_data_int_2[TEST_DATA_INT_2_SIZE] = { LE64(TEST_DATA_INT_2) }; -const u8 test_data_int_3[TEST_DATA_INT_3_SIZE] = { LE64(TEST_DATA_INT_3) }; +const u8 test_data_1[TEST_DATA_1_SIZE] = {TEST_DATA_1}; +const u8 test_data_2[TEST_DATA_2_SIZE] = {TEST_DATA_2}; +const u8 test_data_int_1[TEST_DATA_INT_1_SIZE] = {LE64(TEST_DATA_INT_1)}; +const u8 test_data_int_2[TEST_DATA_INT_2_SIZE] = {LE64(TEST_DATA_INT_2)}; +const u8 test_data_int_3[TEST_DATA_INT_3_SIZE] = {LE64(TEST_DATA_INT_3)}; -const u8 good_hash[VB2_SHA256_DIGEST_SIZE] = { TEST_SHA256 }; -const u8 bad_hash[VB2_SHA256_DIGEST_SIZE] = { INVALID_SHA256 }; +const u8 good_hash[VB2_SHA256_DIGEST_SIZE] = {TEST_SHA256}; +const u8 bad_hash[VB2_SHA256_DIGEST_SIZE] = {INVALID_SHA256}; const struct cbfs_test_file file_no_hash = { .header = HEADER_INITIALIZER(CBFS_TYPE_RAW, 0, TEST_DATA_1_SIZE), diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index ee0e2232d5..f5b73d2e6c 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -165,6 +165,7 @@ static void usage(void) printf("--load-s0i3 Set if load s0i3 firmware\n"); printf("--verstage Add verstage\n"); printf("--verstage_sig Add verstage signature\n"); + printf("--recovery-ab Use the recovery A/B layout\n"); printf("\nBIOS options:\n"); printf("--instance Sets instance field for the next BIOS\n"); printf(" firmware\n"); @@ -220,59 +221,60 @@ static void usage(void) } amd_fw_entry amd_psp_fw_table[] = { - { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL1_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, - { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, - { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 }, - { .type = AMD_HW_IPCFG, .level = PSP_LVL2 }, - { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH }, - { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH }, - { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 }, - { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 }, - { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 }, - { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 }, - { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2}, - { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 }, - { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH }, - { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH }, - { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 }, - { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 }, - { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH }, - { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 }, - { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, - { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, - { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, - { .type = AMD_ABL0, .level = PSP_BOTH }, - { .type = AMD_ABL1, .level = PSP_BOTH }, - { .type = AMD_ABL2, .level = PSP_BOTH }, - { .type = AMD_ABL3, .level = PSP_BOTH }, - { .type = AMD_ABL4, .level = PSP_BOTH }, - { .type = AMD_ABL5, .level = PSP_BOTH }, - { .type = AMD_ABL6, .level = PSP_BOTH }, - { .type = AMD_ABL7, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, + { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, - { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, - { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_INVALID }, }; @@ -323,10 +325,14 @@ amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, @@ -343,16 +349,51 @@ amd_bios_entry amd_bios_table[] = { typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ + uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */ uint32_t current; /* pointer within flash & proxy buffer */ + uint32_t current_table; } context; -#define RUN_BASE(ctx) (0) -#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) +#define ADDRESS_MODE_0_PHY 0 +#define ADDRESS_MODE_1_REL_BIOS 1 +#define ADDRESS_MODE_2_REL_TAB 2 +#define ADDRESS_MODE_3_REL_SLOT 3 + +#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) +#define RUN_OFFSET_MODE(ctx, offset, mode) \ + ((mode) == ADDRESS_MODE_0_PHY ? RUN_BASE(ctx) + (offset) : \ + ((mode) == ADDRESS_MODE_1_REL_BIOS ? (offset) : \ + ((mode) == ADDRESS_MODE_2_REL_TAB ? (offset) - ctx.current_table : (offset)))) +#define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode) +#define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == ADDRESS_MODE_0_PHY ? \ + (run) - RUN_BASE(ctx) : (run)) /* TODO: */ #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) +/* The mode in entry can not be higher than the header's. + For example, if table mode is 0, all the entry mode will be 0. */ +#define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \ + (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) +#define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \ + (ctx).address_mode < (mode) ? (ctx).address_mode : (mode)) #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) +/* Only set the address mode in entry if the table is mode 2. */ +#define SET_ADDR_MODE(table, mode) \ + ((table)->header.additional_info_fields.address_mode == \ + ADDRESS_MODE_2_REL_TAB ? (mode) : 0) +#define SET_ADDR_MODE_BY_TABLE(table) \ + SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode) + +void assert_fw_entry(uint32_t count, uint32_t max, context *ctx) +{ + if (count >= max) { + fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " + "(%d)\n", count, max); + free(ctx->rom); + exit(1); + } +} static void *new_psp_dir(context *ctx, int multi) { @@ -369,7 +410,9 @@ static void *new_psp_dir(context *ctx, int multi) ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); - ((psp_directory_header *)ptr)->additional_info = ctx->current; + ((psp_directory_header *)ptr)->num_entries = 0; + ((psp_directory_header *)ptr)->additional_info = 0; + ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; ctx->current += sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); return ptr; @@ -421,14 +464,16 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, co break; case PSP_COOKIE: case PSPL2_COOKIE: - table_size = ctx->current - dir->header.additional_info; + table_size = ctx->current - ctx->current_table; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The PSP table size should be 4K aligned\n"); exit(1); } dir->header.cookie = cookie; dir->header.num_entries = count; - dir->header.additional_info = (table_size / 0x1000) | (1 << 10); + dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; + dir->header.additional_info_fields.spi_block_size = 1; + dir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ dir->header.checksum = fletcher32(&dir->header.num_entries, count * sizeof(psp_directory_entry) @@ -437,14 +482,16 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, co break; case BDT1_COOKIE: case BDT2_COOKIE: - table_size = ctx->current - bdir->header.additional_info; + table_size = ctx->current - ctx->current_table; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The BIOS table size should be 4K aligned\n"); exit(1); } bdir->header.cookie = cookie; bdir->header.num_entries = count; - bdir->header.additional_info = (table_size / 0x1000) | (1 << 10); + bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT; + bdir->header.additional_info_fields.spi_block_size = 1; + bdir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ bdir->header.checksum = fletcher32(&bdir->header.num_entries, count * sizeof(bios_directory_entry) @@ -601,6 +648,7 @@ static void free_psp_firmware_filenames(amd_fw_entry *fw_table) if (index->filename && index->type != AMD_FW_VERSTAGE_SIG && index->type != AMD_FW_PSP_VERSTAGE && + index->type != AMD_FW_SPL && index->type != AMD_FW_PSP_WHITELIST) { free(index->filename); } @@ -620,9 +668,34 @@ static void free_bdt_firmware_filenames(amd_bios_entry *fw_table) } } +static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, + psp_directory_table *pspdir2, amd_fw_type ab) +{ + uint32_t count; + uint32_t current_table_save; + + current_table_save = ctx->current_table; + ctx->current_table = (char *)pspdir - ctx->rom; + count = pspdir->header.num_entries; + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); + pspdir->entries[count].type = (uint8_t)ab; + pspdir->entries[count].subprog = 0; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, pspdir2, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].size = pspdir2->header.num_entries * + sizeof(psp_directory_entry) + + sizeof(psp_directory_header); + + count++; + pspdir->header.num_entries = count; + ctx->current_table = current_table_save; +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, + psp_directory_table *pspdir2_b, amd_fw_entry *fw_table, uint32_t cookie, amd_cb_config *cb_config) @@ -630,6 +703,8 @@ static void integrate_psp_firmwares(context *ctx, ssize_t bytes; unsigned int i, count; int level; + uint32_t current_table_save; + bool recovery_ab = cb_config->recovery_ab; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -638,7 +713,7 @@ static void integrate_psp_firmwares(context *ctx, * 1st-level cookie may indicate level 1 or flattened. If the caller * passes a pointer to a 2nd-level table, then assume not flat. */ - if (cb_config->multi_level == 0) + if (!cb_config->multi_level) level = PSP_BOTH; else if (cookie == PSPL2_COOKIE) level = PSP_LVL2; @@ -647,12 +722,24 @@ static void integrate_psp_firmwares(context *ctx, else level = PSP_BOTH; + if (recovery_ab) { + if (cookie == PSPL2_COOKIE) + level = PSP_LVL2_AB; + else if (pspdir2) + level = PSP_LVL1_AB; + else + level = PSP_BOTH_AB; + } + current_table_save = ctx->current_table; + ctx->current_table = (char *)pspdir - ctx->rom; ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { if (!(fw_table[i].level & level)) continue; + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); + if (fw_table[i].type == AMD_TOKEN_UNLOCK) { if (!fw_table[i].other) continue; @@ -660,6 +747,7 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].type = fw_table[i].type; pspdir->entries[count].size = 4096; /* TODO: doc? */ pspdir->entries[count].addr = RUN_CURRENT(*ctx); + pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); pspdir->entries[count].subprog = fw_table[i].subprog; pspdir->entries[count].rsvd = 0; ctx->current = ALIGN(ctx->current + 4096, 0x100U); @@ -670,6 +758,7 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = 0xFFFFFFFF; pspdir->entries[count].addr = fw_table[i].other; + pspdir->entries[count].address_mode = 0; count++; } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { if (fw_table[i].filename == NULL) @@ -691,7 +780,10 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = ALIGN(bytes, ERASE_ALIGNMENT); - pspdir->entries[count].addr = RUN_CURRENT(*ctx); + pspdir->entries[count].addr = + RUN_CURRENT_MODE(*ctx, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].address_mode = + SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); ctx->current = ALIGN(ctx->current + bytes, BLOB_ERASE_ALIGNMENT); @@ -709,6 +801,7 @@ static void integrate_psp_firmwares(context *ctx, pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = (uint32_t)bytes; pspdir->entries[count].addr = RUN_CURRENT(*ctx); + pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); ctx->current = ALIGN(ctx->current + bytes, BLOB_ALIGNMENT); @@ -718,7 +811,14 @@ static void integrate_psp_firmwares(context *ctx, } } - if (pspdir2) { + if (recovery_ab && (pspdir2 != NULL)) { + pspdir->header.num_entries = count; + integrate_psp_ab(ctx, pspdir, pspdir2, AMD_FW_RECOVERYAB_A); + if (pspdir2_b != NULL) + integrate_psp_ab(ctx, pspdir, pspdir2_b, AMD_FW_RECOVERYAB_B); + count = pspdir->header.num_entries; + } else if (pspdir2 != NULL) { + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); pspdir->entries[count].type = AMD_FW_L2_PTR; pspdir->entries[count].subprog = 0; pspdir->entries[count].rsvd = 0; @@ -726,20 +826,54 @@ static void integrate_psp_firmwares(context *ctx, + pspdir2->header.num_entries * sizeof(psp_directory_entry); - pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2); + pspdir->entries[count].addr = + BUFF_TO_RUN_MODE(*ctx, pspdir2, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].address_mode = + SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); count++; } - if (count > MAX_PSP_ENTRIES) { - fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); - free(ctx->rom); - exit(1); - } - fill_dir_header(pspdir, count, cookie, ctx); + ctx->current_table = current_table_save; } -static void *new_bios_dir(context *ctx, int multi) +static void add_psp_firmware_entry(context *ctx, + psp_directory_table *pspdir, + void *table, amd_fw_type type, uint32_t size) +{ + uint32_t count = pspdir->header.num_entries; + uint32_t index; + uint32_t current_table_save; + + current_table_save = ctx->current_table; + ctx->current_table = (char *)pspdir - ctx->rom; + + /* If there is an entry of "type", replace it. */ + for (index = 0; index < count; index++) { + if (pspdir->entries[index].type == (uint8_t)type) + break; + } + + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); + pspdir->entries[index].type = (uint8_t)type; + pspdir->entries[index].subprog = 0; + pspdir->entries[index].rsvd = 0; + pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table); + pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir); + pspdir->entries[index].size = size; + if (index == count) + count++; + + pspdir->header.num_entries = count; + pspdir->header.checksum = fletcher32(&pspdir->header.num_entries, + count * sizeof(psp_directory_entry) + + sizeof(pspdir->header.num_entries) + + sizeof(pspdir->header.additional_info)); + + ctx->current_table = current_table_save; +} + +static void *new_bios_dir(context *ctx, bool multi) { void *ptr; @@ -753,7 +887,9 @@ static void *new_bios_dir(context *ctx, int multi) else ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); - ((bios_directory_hdr *) ptr)->additional_info = ctx->current; + ((bios_directory_hdr *) ptr)->additional_info = 0; + ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; + ctx->current_table = ctx->current; ctx->current += sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry); return ptr; @@ -822,7 +958,7 @@ static void integrate_bios_firmwares(context *ctx, * 1st-level cookie may indicate level 1 or flattened. If the caller * passes a pointer to a 2nd-level table, then assume not flat. */ - if (cb_config->multi_level == 0) + if (!cb_config->multi_level) level = BDT_BOTH; else if (cookie == BDT2_COOKIE) level = BDT_LVL2; @@ -888,6 +1024,7 @@ static void integrate_bios_firmwares(context *ctx, if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && (!fw_table[i].dest || !fw_table[i].size)) continue; + assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); biosdir->entries[count].type = fw_table[i].type; biosdir->entries[count].region_type = fw_table[i].region_type; @@ -904,16 +1041,21 @@ static void integrate_bios_firmwares(context *ctx, case AMD_BIOS_APOB: biosdir->entries[count].size = fw_table[i].size; biosdir->entries[count].source = fw_table[i].src; + biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); break; case AMD_BIOS_APOB_NV: if (fw_table[i].src) { /* If source is given, use that and its size */ biosdir->entries[count].source = fw_table[i].src; + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); biosdir->entries[count].size = fw_table[i].size; } else { /* Else reserve size bytes within amdfw.rom */ ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); biosdir->entries[count].source = RUN_CURRENT(*ctx); + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); biosdir->entries[count].size = ALIGN( fw_table[i].size, ERASE_ALIGNMENT); memset(BUFF_CURRENT(*ctx), 0xff, @@ -926,12 +1068,16 @@ static void integrate_bios_firmwares(context *ctx, /* Don't make a 2nd copy, point to the same one */ if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) { biosdir->entries[count].source = source; + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); biosdir->entries[count].size = size; break; } /* level 2, or level 1 and no copy found in level 2 */ biosdir->entries[count].source = fw_table[i].src; + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); biosdir->entries[count].dest = fw_table[i].dest; biosdir->entries[count].size = fw_table[i].size; @@ -945,7 +1091,10 @@ static void integrate_bios_firmwares(context *ctx, exit(1); } - biosdir->entries[count].source = RUN_CURRENT(*ctx); + biosdir->entries[count].source = + RUN_CURRENT_MODE(*ctx, ADDRESS_MODE_1_REL_BIOS); + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); ctx->current = ALIGN(ctx->current + bytes, 0x100U); break; @@ -968,6 +1117,7 @@ static void integrate_bios_firmwares(context *ctx, biosdir->entries[count].size = (uint32_t)bytes; biosdir->entries[count].source = RUN_CURRENT(*ctx); + biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); ctx->current = ALIGN(ctx->current + bytes, 0x100U); break; @@ -977,6 +1127,7 @@ static void integrate_bios_firmwares(context *ctx, } if (biosdir2) { + assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); biosdir->entries[count].type = AMD_BIOS_L2_PTR; biosdir->entries[count].region_type = 0; biosdir->entries[count].size = @@ -984,6 +1135,8 @@ static void integrate_bios_firmwares(context *ctx, * sizeof(bios_directory_entry); biosdir->entries[count].source = BUFF_TO_RUN(*ctx, biosdir2); + biosdir->entries[count].address_mode = + SET_ADDR_MODE(biosdir, ADDRESS_MODE_1_REL_BIOS); biosdir->entries[count].subprog = 0; biosdir->entries[count].inst = 0; biosdir->entries[count].copy = 0; @@ -994,13 +1147,6 @@ static void integrate_bios_firmwares(context *ctx, count++; } - if (count > MAX_BIOS_ENTRIES) { - fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " - "(%d)\n", count, MAX_BIOS_ENTRIES); - free(ctx->rom); - exit(1); - } - fill_dir_header(biosdir, count, cookie, ctx); } @@ -1014,6 +1160,7 @@ enum { AMDFW_OPT_IMC, AMDFW_OPT_GEC, AMDFW_OPT_COMBO, + AMDFW_OPT_RECOVERY_AB, AMDFW_OPT_MULTILEVEL, AMDFW_OPT_NVRAM, @@ -1023,6 +1170,7 @@ enum { AMDFW_OPT_USE_PSPSECUREOS, AMDFW_OPT_LOAD_MP2FW, AMDFW_OPT_LOAD_S0I3, + AMDFW_OPT_SPL_TABLE, AMDFW_OPT_VERSTAGE, AMDFW_OPT_VERSTAGE_SIG, @@ -1060,6 +1208,7 @@ static struct option long_options[] = { {"gec", required_argument, 0, AMDFW_OPT_GEC }, /* PSP Directory Table items */ {"combo-capable", no_argument, 0, AMDFW_OPT_COMBO }, + {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, @@ -1068,6 +1217,7 @@ static struct option long_options[] = { {"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS }, {"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW }, {"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 }, + {"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE }, {"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE }, {"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG }, /* BIOS Directory Table items */ @@ -1271,8 +1421,10 @@ int main(int argc, char **argv) char *tmp; char *rom = NULL; embedded_firmware *amd_romsig; - psp_directory_table *pspdir; - int comboable = 0; + psp_directory_table *pspdir = NULL; + psp_directory_table *pspdir2 = NULL; + psp_directory_table *pspdir2_b = NULL; + bool comboable = false; int fuse_defined = 0; int targetfd; char *output = NULL, *config = NULL; @@ -1293,12 +1445,13 @@ int main(int argc, char **argv) int debug = 0; int list_deps = 0; - cb_config.have_whitelist = 0; - cb_config.unlock_secure = 0; - cb_config.use_secureos = 0; - cb_config.load_mp2_fw = 0; - cb_config.s0i3 = 0; - cb_config.multi_level = 0; + cb_config.have_whitelist = false; + cb_config.unlock_secure = false; + cb_config.use_secureos = false; + cb_config.load_mp2_fw = false; + cb_config.s0i3 = false; + cb_config.multi_level = false; + cb_config.recovery_ab = false; while (1) { int optindex = 0; @@ -1322,24 +1475,27 @@ int main(int argc, char **argv) sub = instance = 0; break; case AMDFW_OPT_COMBO: - comboable = 1; + comboable = true; + break; + case AMDFW_OPT_RECOVERY_AB: + cb_config.recovery_ab = true; break; case AMDFW_OPT_MULTILEVEL: - cb_config.multi_level = 1; + cb_config.multi_level = true; break; case AMDFW_OPT_UNLOCK: register_fw_token_unlock(); - cb_config.unlock_secure = 1; + cb_config.unlock_secure = true; sub = instance = 0; break; case AMDFW_OPT_USE_PSPSECUREOS: - cb_config.use_secureos = 1; + cb_config.use_secureos = true; break; case AMDFW_OPT_INSTANCE: instance = strtoul(optarg, &tmp, 16); break; case AMDFW_OPT_LOAD_MP2FW: - cb_config.load_mp2_fw = 1; + cb_config.load_mp2_fw = true; break; case AMDFW_OPT_NVRAM: register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg); @@ -1398,12 +1554,17 @@ int main(int argc, char **argv) sub = instance = 0; break; case AMDFW_OPT_LOAD_S0I3: - cb_config.s0i3 = 1; + cb_config.s0i3 = true; + break; + case AMDFW_OPT_SPL_TABLE: + register_fw_filename(AMD_FW_SPL, sub, optarg); + sub = instance = 0; + cb_config.have_mb_spl = true; break; case AMDFW_OPT_WHITELIST: register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg); sub = instance = 0; - cb_config.have_whitelist = 1; + cb_config.have_whitelist = true; break; case AMDFW_OPT_VERSTAGE: register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); @@ -1523,6 +1684,10 @@ int main(int argc, char **argv) retval = 1; } + if (cb_config.recovery_ab) { + cb_config.multi_level = true; + } + if (retval) { usage(); return retval; @@ -1574,8 +1739,6 @@ int main(int argc, char **argv) romsig_offset = ctx.current = dir_location - rom_base_address; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; - printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", - RUN_CURRENT(ctx)); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; @@ -1594,28 +1757,46 @@ int main(int argc, char **argv) fprintf(stderr, "WARNING: No SOC name specified.\n"); } + if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) + ctx.address_mode = ADDRESS_MODE_1_REL_BIOS; + else + ctx.address_mode = ADDRESS_MODE_0_PHY; + printf(" AMDFWTOOL Using firmware directory location of %s address: 0x%08x\n", + ctx.address_mode == ADDRESS_MODE_0_PHY ? "absolute" : "relative", + RUN_CURRENT(ctx)); + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ + ctx.current_table = 0; if (cb_config.multi_level) { /* Do 2nd PSP directory followed by 1st */ - psp_directory_table *pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); - integrate_psp_firmwares(&ctx, pspdir2, 0, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); - + pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); + integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, + amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + if (cb_config.recovery_ab) { + /* B is same as above directories for A */ + /* Skip creating pspdir2_b here to save flash space. Related + * biosdir2_b will be skipped automatically. */ + pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); + integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, + amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + } else { + pspdir2_b = NULL; /* More explicitly */ + } pspdir = new_psp_dir(&ctx, cb_config.multi_level); - integrate_psp_firmwares(&ctx, pspdir, pspdir2, + integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, amd_psp_fw_table, PSP_COOKIE, &cb_config); } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ pspdir = new_psp_dir(&ctx, cb_config.multi_level); - integrate_psp_firmwares(&ctx, pspdir, 0, + integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, amd_psp_fw_table, PSP_COOKIE, &cb_config); } if (comboable) - amd_romsig->combo_psp_directory = BUFF_TO_RUN(ctx, pspdir); + amd_romsig->new_psp_directory = BUFF_TO_RUN(ctx, pspdir); else amd_romsig->psp_directory = BUFF_TO_RUN(ctx, pspdir); @@ -1632,28 +1813,44 @@ int main(int argc, char **argv) #endif if (have_bios_tables(amd_bios_table)) { - bios_directory_table *biosdir; + bios_directory_table *biosdir = NULL; if (cb_config.multi_level) { /* Do 2nd level BIOS directory followed by 1st */ - bios_directory_table *biosdir2 = - new_bios_dir(&ctx, cb_config.multi_level); - integrate_bios_firmwares(&ctx, biosdir2, 0, - amd_bios_table, BDT2_COOKIE, &cb_config); + bios_directory_table *biosdir2 = NULL; + bios_directory_table *biosdir2_b = NULL; - biosdir = new_bios_dir(&ctx, cb_config.multi_level); - integrate_bios_firmwares(&ctx, biosdir, biosdir2, + biosdir2 = new_bios_dir(&ctx, cb_config.multi_level); + + integrate_bios_firmwares(&ctx, biosdir2, NULL, + amd_bios_table, BDT2_COOKIE, &cb_config); + if (cb_config.recovery_ab) { + if (pspdir2_b != NULL) { + biosdir2_b = new_bios_dir(&ctx, cb_config.multi_level); + integrate_bios_firmwares(&ctx, biosdir2_b, NULL, + amd_bios_table, BDT2_COOKIE, &cb_config); + } + add_psp_firmware_entry(&ctx, pspdir2, biosdir2, + AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); + if (pspdir2_b != NULL) + add_psp_firmware_entry(&ctx, pspdir2_b, biosdir2_b, + AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT); + } else { + biosdir = new_bios_dir(&ctx, cb_config.multi_level); + integrate_bios_firmwares(&ctx, biosdir, biosdir2, amd_bios_table, BDT1_COOKIE, &cb_config); + } } else { /* flat: BDT1 cookie and no pointer to 2nd table */ biosdir = new_bios_dir(&ctx, cb_config.multi_level); - integrate_bios_firmwares(&ctx, biosdir, 0, + integrate_bios_firmwares(&ctx, biosdir, NULL, amd_bios_table, BDT1_COOKIE, &cb_config); } switch (soc_id) { case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: case PLATFORM_CEZANNE: - amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); + if (!cb_config.recovery_ab) + amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir); break; case PLATFORM_MENDOCINO: break; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d7f0f5db96..70afe3c6df 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -4,6 +4,7 @@ #define _AMD_FW_TOOL_H_ #include +#include typedef enum _amd_fw_type { AMD_FW_PSP_PUBKEY = 0, @@ -42,11 +43,15 @@ typedef enum _amd_fw_type { AMD_FW_USB_PHY = 0x44, AMD_FW_TOS_SEC_POLICY = 0x45, AMD_FW_DRTM_TA = 0x47, + AMD_FW_RECOVERYAB_A = 0x48, + AMD_FW_RECOVERYAB_B = 0x4A, + AMD_FW_BIOS_TABLE = 0x49, AMD_FW_KEYDB_BL = 0x50, AMD_FW_KEYDB_TOS = 0x51, AMD_FW_PSP_VERSTAGE = 0x52, AMD_FW_VERSTAGE_SIG = 0x53, AMD_RPMC_NVRAM = 0x54, + AMD_FW_SPL = 0x55, AMD_FW_DMCU_ERAM = 0x58, AMD_FW_DMCU_ISR = 0x59, AMD_FW_PSP_BOOTLOADER_AB = 0x73, @@ -87,7 +92,10 @@ typedef struct _embedded_firmware { uint32_t gec_entry; uint32_t xhci_entry; uint32_t psp_directory; - uint32_t combo_psp_directory; + union { + uint32_t new_psp_directory; + uint32_t combo_psp_directory; + }; uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; @@ -117,7 +125,16 @@ typedef struct _psp_directory_header { uint32_t cookie; uint32_t checksum; uint32_t num_entries; - uint32_t additional_info; + union { + uint32_t additional_info; + struct { + uint32_t dir_size:10; + uint32_t spi_block_size:4; + uint32_t base_addr:15; + uint32_t address_mode:2; + uint32_t not_used:1; + } __attribute__((packed)) additional_info_fields; + }; } __attribute__((packed, aligned(16))) psp_directory_header; typedef struct _psp_directory_entry { @@ -125,7 +142,8 @@ typedef struct _psp_directory_entry { uint8_t subprog; uint16_t rsvd; uint32_t size; - uint64_t addr; /* or a value in some cases */ + uint64_t addr:62; /* or a value in some cases */ + uint64_t address_mode:2; } __attribute__((packed)) psp_directory_entry; typedef struct _psp_directory_table { @@ -160,7 +178,16 @@ typedef struct _bios_directory_hdr { uint32_t cookie; uint32_t checksum; uint32_t num_entries; - uint32_t additional_info; + union { + uint32_t additional_info; + struct { + uint32_t dir_size:10; + uint32_t spi_block_size:4; + uint32_t base_addr:15; + uint32_t address_mode:2; + uint32_t not_used:1; + } __attribute__((packed)) additional_info_fields; + }; } __attribute__((packed, aligned(16))) bios_directory_hdr; typedef struct _bios_directory_entry { @@ -173,7 +200,8 @@ typedef struct _bios_directory_entry { int inst:4; uint8_t subprog; /* b[7:3] reserved */ uint32_t size; - uint64_t source; + uint64_t source:62; + uint64_t address_mode:2; uint64_t dest; } __attribute__((packed)) bios_directory_entry; @@ -182,9 +210,12 @@ typedef struct _bios_directory_table { bios_directory_entry entries[]; } bios_directory_table; -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 +#define BDT_LVL1 (1 << 0) +#define BDT_LVL2 (1 << 1) +#define BDT_LVL1_AB (1 << 2) +#define BDT_LVL2_AB (1 << 3) #define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +#define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB) typedef struct _amd_bios_entry { amd_bios_type type; char *filename; @@ -208,9 +239,12 @@ typedef struct _amd_bios_entry { #define BDT1_COOKIE 0x44484224 /* 'DHB$ */ #define BDT2_COOKIE 0x324c4224 /* '2LB$ */ -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 +#define PSP_LVL1 (1 << 0) +#define PSP_LVL2 (1 << 1) +#define PSP_LVL1_AB (1 << 2) +#define PSP_LVL2_AB (1 << 3) #define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +#define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB) typedef struct _amd_fw_entry { amd_fw_type type; char *filename; @@ -220,12 +254,14 @@ typedef struct _amd_fw_entry { } amd_fw_entry; typedef struct _amd_cb_config { - uint8_t have_whitelist; - uint8_t unlock_secure; - uint8_t use_secureos; - uint8_t load_mp2_fw; - uint8_t multi_level; - uint8_t s0i3; + bool have_whitelist; + bool unlock_secure; + bool use_secureos; + bool load_mp2_fw; + bool multi_level; + bool s0i3; + bool have_mb_spl; + bool recovery_ab; } amd_cb_config; void register_fw_fuse(char *str); diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 784ee67026..a6b73ee1ec 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -78,18 +78,18 @@ void compile_reg_expr(int cflags, const char *expr, regex_t *reg) } } -#define SET_LEVEL(tableptr, l, TABLE) \ +#define SET_LEVEL(tableptr, l, TABLE, ab) \ do { \ switch ((l)) { \ case '1': \ - (tableptr)->level = TABLE##_LVL1;\ + (tableptr)->level = ab ? TABLE##_LVL1_AB : TABLE##_LVL1; \ break; \ case '2': \ - (tableptr)->level = TABLE##_LVL2;\ + (tableptr)->level = ab ? TABLE##_LVL2_AB : TABLE##_LVL2; \ break; \ case 'b': \ case 'B': \ - (tableptr)->level = TABLE##_BOTH;\ + (tableptr)->level = ab ? TABLE##_BOTH_AB : TABLE##_BOTH; \ break; \ default: \ /* use default value */ \ @@ -108,15 +108,26 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, uint8_t subprog; if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { - if (cb_config->have_whitelist == 1) { + if (cb_config->have_whitelist) { fw_type = AMD_FW_PSP_BOOTLOADER_AB; subprog = 0; } else { fw_type = AMD_FW_SKIP; } + } else if (strcmp(fw_name, "PSPBTLDR_AB_STAGE1_FILE") == 0) { + if (cb_config->recovery_ab) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { - fw_type = AMD_FW_PSP_BOOTLOADER; - subprog = 0; + if (!cb_config->recovery_ab) { + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { fw_type = AMD_FW_PSP_PUBKEY; subprog = 0; @@ -160,14 +171,14 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_FW_PSP_SMU_FIRMWARE2; subprog = 2; } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { - if (cb_config->unlock_secure == 1) { + if (cb_config->unlock_secure) { fw_type = AMD_FW_PSP_SECURED_DEBUG; subprog = 0; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { - if (cb_config->unlock_secure == 1) { + if (cb_config->unlock_secure) { fw_type = AMD_DEBUG_UNLOCK; subprog = 0; } else { @@ -198,7 +209,7 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_ABL7; subprog = 0; } else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) { - if (cb_config->use_secureos == 1) { + if (cb_config->use_secureos) { fw_type = AMD_FW_PSP_SECURED_OS; subprog = 0; } else { @@ -231,21 +242,21 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_SEC_GASKET; subprog = 2; } else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 0; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 1; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_MP2_FW; subprog = 2; } else { @@ -255,7 +266,7 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_DRIVER_ENTRIES; subprog = 0; } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { - if (cb_config->s0i3 == 1) { + if (cb_config->s0i3) { fw_type = AMD_S0I3_DRIVER; subprog = 0; } else { @@ -282,6 +293,13 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, } else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) { fw_type = AMD_FW_KEYDB_TOS; subprog = 0; + } else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) { + if (cb_config->have_mb_spl) { + fw_type = AMD_FW_SPL; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) { fw_type = AMD_FW_DMCU_ERAM; subprog = 0; @@ -295,7 +313,7 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, fw_type = AMD_RPMC_NVRAM; subprog = 0; } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - if (cb_config->have_whitelist == 0) { + if (!cb_config->have_whitelist || cb_config->recovery_ab) { fw_type = AMD_FW_PSP_BOOTLOADER_AB; subprog = 0; } else { @@ -313,7 +331,8 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, /* instance are not used in PSP table */ if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { psp_tableptr->filename = filename; - SET_LEVEL(psp_tableptr, level_to_set, PSP); + SET_LEVEL(psp_tableptr, level_to_set, PSP, + cb_config->recovery_ab); break; } psp_tableptr++; @@ -324,6 +343,12 @@ static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename, else return 1; } +#define PMUI_STR_BASE "PSP_PMUI_FILE" +#define PMUD_STR_BASE "PSP_PMUD_FILE" +#define PMU_STR_BASE_LEN strlen(PMUI_STR_BASE) +#define PMU_STR_SUB_INDEX strlen(PMUI_STR_BASE"_SUB") +#define PMU_STR_INS_INDEX strlen(PMUI_STR_BASE"_SUBx_INS") +#define PMU_STR_ALL_LEN strlen(PMUI_STR_BASE"_SUBx_INSx") static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, char level_to_set, amd_cb_config *cb_config) @@ -335,44 +360,22 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, (void) (cb_config); /* Remove warning and reserved for future. */ - if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + if (strncmp(fw_name, PMUI_STR_BASE, PMU_STR_BASE_LEN) == 0) { + assert(strlen(fw_name) == PMU_STR_ALL_LEN); fw_type = AMD_BIOS_PMUI; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 0; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 1; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { - fw_type = AMD_BIOS_PMUI; - subprog = 1; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + subprog = fw_name[PMU_STR_SUB_INDEX] - '0'; + instance = fw_name[PMU_STR_INS_INDEX] - '0'; + } else if (strncmp(fw_name, PMUD_STR_BASE, PMU_STR_BASE_LEN) == 0) { + assert(strlen(fw_name) == PMU_STR_ALL_LEN); fw_type = AMD_BIOS_PMUD; - subprog = 0; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 0; - instance = 4; - } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 1; - instance = 1; - } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { - fw_type = AMD_BIOS_PMUD; - subprog = 1; - instance = 4; + subprog = fw_name[PMU_STR_SUB_INDEX] - '0'; + instance = fw_name[PMU_STR_INS_INDEX] - '0'; } else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) { fw_type = AMD_BIOS_RTM_PUBKEY; subprog = 0; instance = 0; } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { + if (cb_config->load_mp2_fw) { fw_type = AMD_BIOS_MP2_CFG; subprog = 0; } else { @@ -390,7 +393,8 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, bhd_tableptr->subpr == subprog && bhd_tableptr->inst == instance) { bhd_tableptr->filename = filename; - SET_LEVEL(bhd_tableptr, level_to_set, BDT); + SET_LEVEL(bhd_tableptr, level_to_set, BDT, + cb_config->recovery_ab); break; } bhd_tableptr++; @@ -524,7 +528,10 @@ uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_dep /* If the optional level field is present, extract the level char. */ if (match[3].rm_so != 0) { - ch_lvl = oneline[match[3].rm_so + 1]; + if (cb_config->recovery_ab == 0) + ch_lvl = oneline[match[3].rm_so + 1]; + else + ch_lvl = oneline[match[3].rm_so + 2]; } if (find_register_fw_filename_psp_dir( diff --git a/util/amdtools/README b/util/amdtools/README deleted file mode 100644 index 06e691008b..0000000000 --- a/util/amdtools/README +++ /dev/null @@ -1,31 +0,0 @@ - - -This is a set of tools to compare (extended) K8 memory settings. - -Before you can use them, you need to massage the relevant BKDG sections into -useable data. Here's how. - -First, you need to acquire a copy of the K8 BKDG. Go here: - - Rev F: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf - -Then make sure pdftotext is installed (it's in the poppler-utils package on Debian/Ubuntu). - -Now run the bkdg through pdftotext: - - pdftotext -layout 32559.pdf 32559.txt - -Now extract sections 4.5.15 - 4.5.19 from the file, and save it separately, say as bkdg-raw.data. - -Finally run the txt file through the parse-bkdg.pl script like so: - - parse-bkdg.pl < bkdg-raw.data > bkdg.data - -Now we have the bkdg.data file that is used by the other scripts. - -If you want to test the scripts without doing all this work, you can use some -sample input files from the 'example_input/' directory. - --- -Ward Vandewege, 2009-10-28. -ward@jhvc.com diff --git a/util/amdtools/README.md b/util/amdtools/README.md new file mode 100644 index 0000000000..0e48d89fdc --- /dev/null +++ b/util/amdtools/README.md @@ -0,0 +1,31 @@ +# amdtools +Various tools for AMD platforms + +## A tool to update the SPI speed set in the EFS table +This works for Stoney Ridge and Zen class AMD processors. + - update_efs_spi_speed + +## A set of tools to compare (extended) K8 memory settings. + - k8-compare-pci-space.pl + - k8-interpret-extended-memory-settings.pl + - k8-read-mem-settings.sh + - parse-bkdg.pl + +Before you can use them, you need to massage the relevant BKDG +sections into useable data. Here's how. + + 1. First, you need to acquire a copy of the K8 BKDG. Go here: + Rev F: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf + 2. Make sure pdftotext is installed (it's in the poppler-utils + package on Debian/Ubuntu). + 3. Run the bkdg through pdftotext: + `pdftotext -layout 32559.pdf 32559.txt` + 4. Extract sections 4.5.15 - 4.5.19 from the file, and save it + separately, say as bkdg-raw.data. + 5. Finally run the txt file through the parse-bkdg.pl script like so: + `parse-bkdg.pl < bkdg-raw.data > bkdg.data` + +Now we have the bkdg.data file that is used by the other scripts. + +If you want to test the scripts without doing all this work, you +can use some sample input files from the 'example_input/' directory. diff --git a/util/amdtools/description.md b/util/amdtools/description.md index 17642ab1e3..fc9f1c5d46 100644 --- a/util/amdtools/description.md +++ b/util/amdtools/description.md @@ -1 +1,11 @@ -A set of tools to compare extended) K8 memory settings. `Perl` +Various tools for AMD processors +* update_efs_spi_speed - Change SPI speed in binary. `Bash` +* A set of tools to compare extended K8 memory settings. `Perl` + * k8-compare-pci-space.pl - Shows differences between values + in PCI space and the default value. `Perl` + * k8-interpret-extended-memory-settings.pl - Shows differences + between memory controller values and the default value. `Perl` + * k8-read-mem-settings.sh - Makes data files understood by the + k8-interpret-extended-memory-settings script. `Bash` + * parse-bkdg.pl - Make bkdg.data file used by above scripts. `Perl` + * example_input - Sample input for the above scripts. `Text` diff --git a/util/apcb/apcb_v3_edit.py b/util/apcb/apcb_v3_edit.py new file mode 100755 index 0000000000..9a70bace3e --- /dev/null +++ b/util/apcb/apcb_v3_edit.py @@ -0,0 +1,156 @@ +#!/usr/bin/env python3 + +# Script for editing APCB_V3 binaries, such as injecting SPDs. + +import sys +import re +import argparse +from collections import namedtuple +from struct import * +import binascii +import os + +# SPD_MAGIC matches the expected SPD header: +# Byte 0 = 0x23 = 512 bytes total / 384 bytes used +# Byte 1 = 0x11 = Revision 1.1 +# Byte 2 = 0x11 = LPDDR4X SDRAM +# Byte 3 = 0x0E = Non-DIMM Solution +SPD_MAGIC = bytes.fromhex('2311110E') +EMPTY_SPD = b'\x00' * 512 + +spd_ssp_struct_fmt = '??B?IIBBBxIIBBBx' +spd_ssp_struct = namedtuple( + 'spd_ssp_struct', 'SpdValid, DimmPresent, \ + PageAddress, NvDimmPresent, \ + DramManufacturersIDCode, Address, \ + SpdMuxPresent, MuxI2CAddress, MuxChannel, \ + Technology, Package, SocketNumber, \ + ChannelNumber, DimmNumber') + +apcb_v3_header_fmt = 'HHHHBBBBBBH' +apcb_v3_header = namedtuple( + 'apcb_v3_header', 'GroupId, TypeId, SizeOfType, \ + InstanceId, ContextType, ContextFormat, UnitSize, \ + PriorityMask, KeySize, KeyPos, BoardMask') + +def parseargs(): + parser = argparse.ArgumentParser(description='Inject SPDs into APCB binaries') + parser.add_argument( + 'apcb_in', + type=str, + help='APCB input file') + parser.add_argument( + 'apcb_out', + type=str, + help='APCB output file') + parser.add_argument( + '--spd_sources', + nargs='+', + help='List of SPD sources') + return parser.parse_args() + + +def chksum(data): + sum = 0 + for b in data[:16] + data[17:]: + sum = (sum + b) & 0xff + return (0x100 - sum) & 0xff + + +def inject(orig, insert, offset): + return b''.join([orig[:offset], insert, orig[offset + len(insert):]]) + + +def main(): + args = parseargs() + + print(f'Reading input APCB from {args.apcb_in}') + + with open(args.apcb_in, 'rb') as f: + apcb = f.read() + + orig_apcb_len = len(apcb) + + assert chksum(apcb) == apcb[16], f'ERROR: {args.apcb_in} checksum is invalid' + + print(f'Using SPD Sources = {args.spd_sources}') + + spds = [] + for spd_source in args.spd_sources: + with open(spd_source, 'rb') as f: + spd_data = bytes.fromhex(re.sub(r'\s+', '', f.read().decode())) + assert(len(spd_data) == 512), f'ERROR: {spd_source} not 512 bytes' + spds.append(spd_data) + + spd_offset = 0 + instance = 0 + while True: + spd_offset = apcb.find(SPD_MAGIC, spd_offset) + if spd_offset < 0: + print('No more SPD magic numbers in APCB') + break + + spd_ssp_offset = spd_offset - calcsize(spd_ssp_struct_fmt) + spd_ssp_bytes = apcb[spd_ssp_offset:spd_offset] + spd_ssp = spd_ssp_struct._make( + unpack(spd_ssp_struct_fmt, spd_ssp_bytes)) + + assert spd_ssp.DimmNumber >= 0 and spd_ssp.DimmNumber <= 1, \ + 'ERROR: Unexpected dimm number found in APCB' + assert spd_ssp.ChannelNumber >= 0 and spd_ssp.ChannelNumber <= 1, \ + 'ERROR: Unexpected channel number found in APCB' + + print(f'Found SPD instance {instance} with channel {spd_ssp.ChannelNumber} ' + f'and dimm {spd_ssp.DimmNumber} at offset {spd_offset}') + + # APCB V3 header is above first channel 0 entry + if spd_ssp.ChannelNumber == 0: + apcb_v3_header_offset = spd_ssp_offset - \ + calcsize(apcb_v3_header_fmt) - 4 + apcb_v3_header_bytes = apcb[apcb_v3_header_offset: + apcb_v3_header_offset + calcsize(apcb_v3_header_fmt)] + apcb_v3 = apcb_v3_header._make( + unpack(apcb_v3_header_fmt, apcb_v3_header_bytes)) + apcb_v3 = apcb_v3._replace(BoardMask=(1 << instance)) + + if instance < len(spds): + print(f'Enabling channel {spd_ssp.ChannelNumber}, ' + f'dimm {spd_ssp.DimmNumber} and injecting SPD') + spd_ssp = spd_ssp._replace(SpdValid=True, DimmPresent=True) + spd = spds[instance] + else: + print(f'Disabling channel {spd_ssp.ChannelNumber}, ' + f'dimm {spd_ssp.DimmNumber} and clearing SPD') + spd_ssp = spd_ssp._replace(SpdValid=False, DimmPresent=False) + spd = EMPTY_SPD + + assert len(spd) == 512, f'ERROR: Expected SPD to be 512 bytes, got {len(spd)}' + + apcb = inject(apcb, pack(spd_ssp_struct_fmt, *spd_ssp), spd_ssp_offset) + apcb = inject(apcb, spd, spd_offset) + if spd_ssp.ChannelNumber == 0: + apcb = inject(apcb, pack(apcb_v3_header_fmt, *apcb_v3), apcb_v3_header_offset) + else: + instance += 1 + + spd_offset += 512 + + assert instance >= len(spds), \ + f'ERROR: Not enough SPD slots in APCB, found {instance}, need {len(spds)}' + + print(f'Fixing checksum and writing to {args.apcb_out}') + + apcb = inject(apcb, bytes([chksum(apcb)]), 16) + + assert chksum(apcb) == apcb[16], 'ERROR: Final checksum is invalid' + assert orig_apcb_len == len(apcb), \ + 'ERROR: The size of the APCB binary changed.' + + print(f'Writing {len(apcb)} bytes to {args.apcb_out}') + + with open(args.apcb_out, 'wb') as f: + f.write(apcb) + + +if __name__ == "__main__": + main() diff --git a/util/apcb/description.md b/util/apcb/description.md index 674243ac2d..46fd4281e4 100644 --- a/util/apcb/description.md +++ b/util/apcb/description.md @@ -2,3 +2,6 @@ AMD PSP Control Block tools * _apcb_edit.py_ - This tool allows patching an existing APCB binary with specific SPDs and GPIO selection pins. `Python3` + +* _apcb_v3_edit.py_ - This tool allows patching an existing APCB v3 binary with + up to 16 specific SPDs. `Python3` diff --git a/util/cbfstool/.gitignore b/util/cbfstool/.gitignore index 2de3ccb633..0470a4565c 100644 --- a/util/cbfstool/.gitignore +++ b/util/cbfstool/.gitignore @@ -1,5 +1,7 @@ cbfs-compression-tool cbfstool +cse_fpt +cse_serger elogtool fmaptool ifittool diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 4651f512a3..3787a56578 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -134,10 +134,6 @@ TOOLCPPFLAGS += -I$(top)/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include TOOLLDFLAGS ?= HOSTCFLAGS += -fms-extensions -ifneq ($(shell uname -o 2>/dev/null), FreeBSD) -TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h -endif - ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) TOOLCFLAGS += -mno-ms-bitfields endif diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 7f4a38bef6..be8573861b 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -80,9 +80,9 @@ static int fill_cbfs_stageheader(struct cbfs_file_attr_stageheader *stageheader, return -1; } - stageheader->loadaddr = htonll(loadaddr); - stageheader->memlen = htonl(memsize); - stageheader->entry_offset = htonl(entry - loadaddr); + stageheader->loadaddr = htobe64(loadaddr); + stageheader->memlen = htobe32(memsize); + stageheader->entry_offset = htobe32(entry - loadaddr); return 0; } diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 67dc6163f0..21a5d6f8c5 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -54,7 +54,7 @@ static struct typedesc_t filetypes[] unused = { {0, NULL} }; -#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) +#define CBFS_SUBHEADER(_p) ((void *) ((((uint8_t *) (_p)) + be32toh((_p)->offset)))) static inline size_t cbfs_file_attr_hash_size(enum vb2_hash_algorithm algo) { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 1fb19bacd6..5f30877df2 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -86,16 +86,15 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image, char *hdr_loc) entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { /* Is the header guarded by a CBFS file entry? Then exit */ - if (((char *)entry) + ntohl(entry->offset) == hdr_loc) { + if (((char *)entry) + be32toh(entry->offset) == hdr_loc) return 0; - } last = entry; } if ((char *)first < (char *)hdr_loc && (char *)entry > (char *)hdr_loc) { WARN("CBFS image was created with old cbfstool with size bug. " "Fixing size in last entry...\n"); - last->len = htonl(ntohl(last->len) - image->header.align); + last->len = htobe32(be32toh(last->len) - image->header.align); DEBUG("Last entry has been changed from 0x%x to 0x%x.\n", cbfs_get_entry_addr(image, entry), cbfs_get_entry_addr(image, @@ -141,17 +140,17 @@ static int cbfs_file_get_compression_info(struct cbfs_file *entry, { unsigned int compression = CBFS_COMPRESS_NONE; if (decompressed_size) - *decompressed_size = ntohl(entry->len); + *decompressed_size = be32toh(entry->len); for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry); attr != NULL; attr = cbfs_file_next_attr(entry, attr)) { - if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION) { + if (be32toh(attr->tag) == CBFS_FILE_ATTR_TAG_COMPRESSION) { struct cbfs_file_attr_compression *ac = (struct cbfs_file_attr_compression *)attr; - compression = ntohl(ac->compression); + compression = be32toh(ac->compression); if (decompressed_size) *decompressed_size = - ntohl(ac->decompressed_size); + be32toh(ac->decompressed_size); } } return compression; @@ -165,11 +164,11 @@ static struct cbfs_file_attr_hash *cbfs_file_get_next_hash( attr = cbfs_file_first_attr(entry); if (attr == NULL) return NULL; - if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_HASH) + if (be32toh(attr->tag) == CBFS_FILE_ATTR_TAG_HASH) return (struct cbfs_file_attr_hash *)attr; } while ((attr = cbfs_file_next_attr(entry, attr)) != NULL) { - if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_HASH) + if (be32toh(attr->tag) == CBFS_FILE_ATTR_TAG_HASH) return (struct cbfs_file_attr_hash *)attr; }; return NULL; @@ -375,12 +374,12 @@ int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) src_entry = cbfs_find_next_entry(image, src_entry)) { size_t entry_size; - if ((src_entry->type == htonl(CBFS_TYPE_NULL)) || - (src_entry->type == htonl(CBFS_TYPE_CBFSHEADER)) || - (src_entry->type == htonl(CBFS_TYPE_DELETED))) + if ((src_entry->type == htobe32(CBFS_TYPE_NULL)) || + (src_entry->type == htobe32(CBFS_TYPE_CBFSHEADER)) || + (src_entry->type == htobe32(CBFS_TYPE_DELETED))) continue; - entry_size = htonl(src_entry->len) + htonl(src_entry->offset); + entry_size = htobe32(src_entry->len) + htobe32(src_entry->offset); memcpy(dst_entry, src_entry, entry_size); dst_entry = (struct cbfs_file *)( (uintptr_t)dst_entry + align_up(entry_size, align)); @@ -473,8 +472,8 @@ int cbfs_truncate_space(struct buffer *region, uint32_t *size) * maximum size. */ if ((strlen(trailer->filename) != 0) && - (trailer->type != htonl(CBFS_TYPE_NULL)) && - (trailer->type != htonl(CBFS_TYPE_DELETED))) { + (trailer->type != htobe32(CBFS_TYPE_NULL)) && + (trailer->type != htobe32(CBFS_TYPE_DELETED))) { /* nothing to truncate. Return de-facto CBFS size in case it * was already truncated. */ *size = (uint8_t *)entry - (uint8_t *)buffer_get(region); @@ -488,12 +487,12 @@ int cbfs_truncate_space(struct buffer *region, uint32_t *size) static size_t cbfs_file_entry_metadata_size(const struct cbfs_file *f) { - return ntohl(f->offset); + return be32toh(f->offset); } static size_t cbfs_file_entry_data_size(const struct cbfs_file *f) { - return ntohl(f->len); + return be32toh(f->len); } static size_t cbfs_file_entry_size(const struct cbfs_file *f) @@ -525,11 +524,9 @@ int cbfs_compact_instance(struct cbfs_image *image) size_t cur_size; size_t empty_metadata_size; size_t spill_size; - uint32_t type = htonl(cur->type); /* Current entry is empty. Kepp track of it. */ - if ((type == htonl(CBFS_TYPE_NULL)) || - (type == htonl(CBFS_TYPE_DELETED))) { + if (cur->type == CBFS_TYPE_NULL || cur->type == CBFS_TYPE_DELETED) { prev = cur; continue; } @@ -631,7 +628,7 @@ static int cbfs_add_entry_at(struct cbfs_image *image, uint32_t len, header_offset; uint32_t align = image->has_header ? image->header.align : CBFS_ALIGNMENT; - uint32_t header_size = ntohl(header->offset); + uint32_t header_size = be32toh(header->offset); header_offset = content_offset - header_size; if (header_offset % align) @@ -660,8 +657,8 @@ static int cbfs_add_entry_at(struct cbfs_image *image, * to file data. Move attributes forward so the end of the * attribute list still matches the end of the metadata. */ - uint32_t offset = ntohl(entry->offset); - uint32_t attrs = ntohl(entry->attributes_offset); + uint32_t offset = be32toh(entry->offset); + uint32_t attrs = be32toh(entry->attributes_offset); DEBUG("|..|header|content|... \n"); DEBUG("before: attr_offset=0x%x, offset=0x%x\n", attrs, offset); if (attrs == 0) { @@ -671,10 +668,10 @@ static int cbfs_add_entry_at(struct cbfs_image *image, memmove(p + len, p, offset - attrs); memset(p, 0, len); attrs += len; - entry->attributes_offset = htonl(attrs); + entry->attributes_offset = htobe32(attrs); } offset += len; - entry->offset = htonl(offset); + entry->offset = htobe32(offset); DEBUG("after: attr_offset=0x%x, offset=0x%x\n", attrs, offset); } @@ -684,14 +681,14 @@ static int cbfs_add_entry_at(struct cbfs_image *image, image->buffer.data)); assert((char*)CBFS_SUBHEADER(entry) - image->buffer.data == (ptrdiff_t)content_offset); - memcpy(CBFS_SUBHEADER(entry), data, ntohl(entry->len)); + memcpy(CBFS_SUBHEADER(entry), data, be32toh(entry->len)); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); // Align the length to a multiple of len_align if (len_align && - ((ntohl(entry->offset) + ntohl(entry->len)) % len_align)) { - size_t off = (ntohl(entry->offset) + ntohl(entry->len)) % len_align; - entry->len = htonl(ntohl(entry->len) + len_align - off); + ((be32toh(entry->offset) + be32toh(entry->len)) % len_align)) { + size_t off = (be32toh(entry->offset) + be32toh(entry->len)) % len_align; + entry->len = htobe32(be32toh(entry->len) + len_align - off); } // Process buffer AFTER entry. @@ -738,7 +735,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, uint32_t addr, addr_next; struct cbfs_file *entry, *next; uint32_t need_size; - uint32_t header_size = ntohl(header->offset); + uint32_t header_size = be32toh(header->offset); need_size = header_size + buffer->size; DEBUG("cbfs_add_entry('%s'@0x%x) => need_size = %u+%zu=%u\n", @@ -752,7 +749,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { - entry_type = ntohl(entry->type); + entry_type = be32toh(entry->type); if (entry_type != CBFS_TYPE_NULL) continue; @@ -975,7 +972,7 @@ static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch, struct cbfs_file_attr_stageheader *stage = NULL; for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry); attr != NULL; attr = cbfs_file_next_attr(entry, attr)) { - if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { + if (be32toh(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { stage = (struct cbfs_file_attr_stageheader *)attr; break; } @@ -1000,7 +997,7 @@ static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch, /* Rmodule couldn't do anything with the data. Continue on with SELF. */ - ehdr.e_entry = ntohll(stage->loadaddr) + ntohl(stage->entry_offset); + ehdr.e_entry = be64toh(stage->loadaddr) + be32toh(stage->entry_offset); ew = elf_writer_init(&ehdr); if (ew == NULL) { @@ -1011,9 +1008,9 @@ static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch, memset(&shdr, 0, sizeof(shdr)); shdr.sh_type = SHT_PROGBITS; shdr.sh_flags = SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR; - shdr.sh_addr = ntohll(stage->loadaddr); + shdr.sh_addr = be64toh(stage->loadaddr); shdr.sh_size = buffer_size(buff); - empty_sz = ntohl(stage->memlen) - buffer_size(buff); + empty_sz = be32toh(stage->memlen) - buffer_size(buff); if (elf_writer_add_section(ew, &shdr, buff, ".program")) { ERROR("Unable to add ELF section: .program\n"); @@ -1028,7 +1025,7 @@ static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch, memset(&shdr, 0, sizeof(shdr)); shdr.sh_type = SHT_NOBITS; shdr.sh_flags = SHF_WRITE | SHF_ALLOC; - shdr.sh_addr = ntohl(stage->loadaddr) + buffer_size(buff); + shdr.sh_addr = be64toh(stage->loadaddr) + buffer_size(buff); shdr.sh_size = empty_sz; if (elf_writer_add_section(ew, &shdr, &b, ".empty")) { ERROR("Unable to add ELF section: .empty\n"); @@ -1230,7 +1227,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, return -1; } - unsigned int compressed_size = ntohl(entry->len); + unsigned int compressed_size = be32toh(entry->len); unsigned int decompressed_size = 0; unsigned int compression = cbfs_file_get_compression_info(entry, &decompressed_size); @@ -1252,7 +1249,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, LOG("Found file %.30s at 0x%x, type %.12s, compressed %d, size %d\n", entry_name, cbfs_get_entry_addr(image, entry), - get_cbfs_entry_type_name(ntohl(entry->type)), compressed_size, + get_cbfs_entry_type_name(be32toh(entry->type)), compressed_size, decompressed_size); buffer_init(&buffer, strdup("(cbfs_export_entry)"), NULL, 0); @@ -1274,7 +1271,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, if (do_processing) { int (*make_elf)(struct buffer *, uint32_t, struct cbfs_file *) = NULL; - switch (ntohl(entry->type)) { + switch (be32toh(entry->type)) { case CBFS_TYPE_STAGE: make_elf = cbfs_stage_make_elf; break; @@ -1312,7 +1309,7 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name) } DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n", entry->filename, cbfs_get_entry_addr(image, entry)); - entry->type = htonl(CBFS_TYPE_DELETED); + entry->type = htobe32(CBFS_TYPE_DELETED); cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); return 0; } @@ -1340,7 +1337,7 @@ static int cbfs_print_stage_info(struct cbfs_file *entry, FILE* fp) struct cbfs_file_attr_stageheader *stage = NULL; for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry); attr != NULL; attr = cbfs_file_next_attr(entry, attr)) { - if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { + if (be32toh(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { stage = (struct cbfs_file_attr_stageheader *)attr; break; } @@ -1354,9 +1351,9 @@ static int cbfs_print_stage_info(struct cbfs_file *entry, FILE* fp) fprintf(fp, " entry: 0x%" PRIx64 ", load: 0x%" PRIx64 ", " "memlen: %d\n", - ntohll(stage->loadaddr) + ntohl(stage->entry_offset), - ntohll(stage->loadaddr), - ntohl(stage->memlen)); + be64toh(stage->loadaddr) + be32toh(stage->entry_offset), + be64toh(stage->loadaddr), + be32toh(stage->memlen)); return 0; } @@ -1434,16 +1431,16 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, fprintf(fp, "%-30s 0x%-8x %-12s %8d %-4s\n", *name ? name : "(empty)", cbfs_get_entry_addr(image, entry), - get_cbfs_entry_type_name(ntohl(entry->type)), - ntohl(entry->len), + get_cbfs_entry_type_name(be32toh(entry->type)), + be32toh(entry->len), compression_name ); else fprintf(fp, "%-30s 0x%-8x %-12s %8d %-4s (%d decompressed)\n", *name ? name : "(empty)", cbfs_get_entry_addr(image, entry), - get_cbfs_entry_type_name(ntohl(entry->type)), - ntohl(entry->len), + get_cbfs_entry_type_name(be32toh(entry->type)), + be32toh(entry->len), compression_name, decompressed_size ); @@ -1461,7 +1458,7 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, } char *hash_str = bintohex(attr->hash.raw, hash_len); int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), - ntohl(entry->len), &attr->hash) == VB2_SUCCESS; + be32toh(entry->len), &attr->hash) == VB2_SUCCESS; const char *valid_str = valid ? "valid" : "invalid"; fprintf(fp, " hash %s:%s %s\n", @@ -1471,12 +1468,12 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, } DEBUG(" cbfs_file=0x%x, offset=0x%x, content_address=0x%x+0x%x\n", - cbfs_get_entry_addr(image, entry), ntohl(entry->offset), - cbfs_get_entry_addr(image, entry) + ntohl(entry->offset), - ntohl(entry->len)); + cbfs_get_entry_addr(image, entry), be32toh(entry->offset), + cbfs_get_entry_addr(image, entry) + be32toh(entry->offset), + be32toh(entry->len)); /* note the components of the subheader may be in host order ... */ - switch (ntohl(entry->type)) { + switch (be32toh(entry->type)) { case CBFS_TYPE_STAGE: cbfs_print_stage_info(entry, fp); break; @@ -1521,9 +1518,9 @@ static int cbfs_print_parseable_entry_info(struct cbfs_image *image, name = entry->filename; if (*name == '\0') name = "(empty)"; - type = get_cbfs_entry_type_name(ntohl(entry->type)), - metadata_size = ntohl(entry->offset); - data_size = ntohl(entry->len); + type = get_cbfs_entry_type_name(be32toh(entry->type)), + metadata_size = be32toh(entry->offset); + data_size = be32toh(entry->len); offset = cbfs_get_entry_addr(image, entry); fprintf(fp, "%s%s", name, sep); @@ -1549,7 +1546,7 @@ static int cbfs_print_parseable_entry_info(struct cbfs_image *image, continue; char *hash_str = bintohex(attr->hash.raw, hash_len); int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), - ntohl(entry->len), &attr->hash) == VB2_SUCCESS; + be32toh(entry->len), &attr->hash) == VB2_SUCCESS; fprintf(fp, "%shash:%s:%s:%s", sep, vb2_get_hash_algorithm_name(attr->hash.algo), hash_str, valid ? "valid" : "invalid"); @@ -1600,8 +1597,8 @@ int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, /* Loop until non-empty entry is found, starting from the current entry. After the loop, next_addr points to the next non-empty entry. */ next = entry; - while (ntohl(next->type) == CBFS_TYPE_DELETED || - ntohl(next->type) == CBFS_TYPE_NULL) { + while (be32toh(next->type) == CBFS_TYPE_DELETED || + be32toh(next->type) == CBFS_TYPE_NULL) { next = cbfs_find_next_entry(image, next); if (!next) break; @@ -1644,10 +1641,10 @@ int cbfs_legacy_walk(struct cbfs_image *image, cbfs_entry_callback callback, static int cbfs_header_valid(struct cbfs_header *header) { - if ((ntohl(header->magic) == CBFS_HEADER_MAGIC) && - ((ntohl(header->version) == CBFS_HEADER_VERSION1) || - (ntohl(header->version) == CBFS_HEADER_VERSION2)) && - (ntohl(header->offset) < ntohl(header->romsize))) + if ((be32toh(header->magic) == CBFS_HEADER_MAGIC) && + ((be32toh(header->version) == CBFS_HEADER_VERSION1) || + (be32toh(header->version) == CBFS_HEADER_VERSION2)) && + (be32toh(header->offset) < be32toh(header->romsize))) return 1; return 0; } @@ -1718,7 +1715,7 @@ struct cbfs_file *cbfs_find_next_entry(struct cbfs_image *image, uint32_t addr = cbfs_get_entry_addr(image, entry); int align = image->has_header ? image->header.align : CBFS_ALIGNMENT; assert(entry && cbfs_is_valid_entry(image, entry)); - addr += ntohl(entry->offset) + ntohl(entry->len); + addr += be32toh(entry->offset) + be32toh(entry->len); addr = align_up(addr, align); return (struct cbfs_file *)(image->buffer.data + addr); } @@ -1760,11 +1757,11 @@ struct cbfs_file *cbfs_create_file_header(int type, struct cbfs_file *entry = malloc(CBFS_METADATA_MAX_SIZE); memset(entry, CBFS_CONTENT_DEFAULT_VALUE, CBFS_METADATA_MAX_SIZE); memcpy(entry->magic, CBFS_FILE_MAGIC, sizeof(entry->magic)); - entry->type = htonl(type); - entry->len = htonl(len); + entry->type = htobe32(type); + entry->len = htobe32(len); entry->attributes_offset = 0; - entry->offset = htonl(cbfs_calculate_file_header_size(name)); - memset(entry->filename, 0, ntohl(entry->offset) - sizeof(*entry)); + entry->offset = htobe32(cbfs_calculate_file_header_size(name)); + memset(entry->filename, 0, be32toh(entry->offset) - sizeof(*entry)); strcpy(entry->filename, name); return entry; } @@ -1773,7 +1770,7 @@ int cbfs_create_empty_entry(struct cbfs_file *entry, int type, size_t len, const char *name) { struct cbfs_file *tmp = cbfs_create_file_header(type, len, name); - memcpy(entry, tmp, ntohl(tmp->offset)); + memcpy(entry, tmp, be32toh(tmp->offset)); free(tmp); memset(CBFS_SUBHEADER(entry), CBFS_CONTENT_DEFAULT_VALUE, len); return 0; @@ -1783,17 +1780,17 @@ struct cbfs_file_attribute *cbfs_file_first_attr(struct cbfs_file *file) { /* attributes_offset should be 0 when there is no attribute, but all * values that point into the cbfs_file header are invalid, too. */ - if (ntohl(file->attributes_offset) <= sizeof(*file)) + if (be32toh(file->attributes_offset) <= sizeof(*file)) return NULL; /* There needs to be enough space for the file header and one * attribute header for this to make sense. */ - if (ntohl(file->offset) <= + if (be32toh(file->offset) <= sizeof(*file) + sizeof(struct cbfs_file_attribute)) return NULL; return (struct cbfs_file_attribute *) - (((uint8_t *)file) + ntohl(file->attributes_offset)); + (((uint8_t *)file) + be32toh(file->attributes_offset)); } struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file, @@ -1804,17 +1801,17 @@ struct cbfs_file_attribute *cbfs_file_next_attr(struct cbfs_file *file, return NULL; /* Is there enough space for another attribute? */ - if ((uint8_t *)attr + ntohl(attr->len) + + if ((uint8_t *)attr + be32toh(attr->len) + sizeof(struct cbfs_file_attribute) > - (uint8_t *)file + ntohl(file->offset)) + (uint8_t *)file + be32toh(file->offset)) return NULL; struct cbfs_file_attribute *next = (struct cbfs_file_attribute *) - (((uint8_t *)attr) + ntohl(attr->len)); + (((uint8_t *)attr) + be32toh(attr->len)); /* If any, "unused" attributes must come last. */ - if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED) + if (be32toh(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED) return NULL; - if (ntohl(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED2) + if (be32toh(next->tag) == CBFS_FILE_ATTR_TAG_UNUSED2) return NULL; return next; @@ -1831,7 +1828,7 @@ struct cbfs_file_attribute *cbfs_add_file_attr(struct cbfs_file *header, attr = next; next = cbfs_file_next_attr(header, attr); } while (next != NULL); - uint32_t header_size = ntohl(header->offset) + size; + uint32_t header_size = be32toh(header->offset) + size; if (header_size > CBFS_METADATA_MAX_SIZE) { DEBUG("exceeding allocated space for cbfs_file headers"); return NULL; @@ -1847,20 +1844,20 @@ struct cbfs_file_attribute *cbfs_add_file_attr(struct cbfs_file *header, header->attributes_offset = header->offset; attr = (struct cbfs_file_attribute *) (((uint8_t *)header) + - ntohl(header->attributes_offset)); + be32toh(header->attributes_offset)); } else { attr = (struct cbfs_file_attribute *) (((uint8_t *)attr) + - ntohl(attr->len)); + be32toh(attr->len)); } - header->offset = htonl(header_size); + header->offset = htobe32(header_size); /* Attributes are expected to be small (much smaller than a flash page) and not really meant to be overwritten in-place. To avoid surprising values in reserved fields of attribute structures, initialize them to 0, not 0xff. */ memset(attr, 0, size); - attr->tag = htonl(tag); - attr->len = htonl(size); + attr->tag = htobe32(tag); + attr->len = htobe32(size); return attr; } @@ -1965,7 +1962,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, entry && cbfs_is_valid_entry(image, entry); entry = cbfs_find_next_entry(image, entry)) { - uint32_t type = ntohl(entry->type); + uint32_t type = be32toh(entry->type); if (type != CBFS_TYPE_NULL) continue; diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c9db45a22f..b76534057a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -169,11 +169,11 @@ static struct mh_cache *get_mh_cache(void) if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset)) goto no_metadata_hash; bootblock = cbfs_get_entry(&cbfs, "bootblock"); - if (!bootblock || ntohl(bootblock->type) != CBFS_TYPE_BOOTBLOCK) + if (!bootblock || be32toh(bootblock->type) != CBFS_TYPE_BOOTBLOCK) goto no_metadata_hash; - offset = (void *)bootblock + ntohl(bootblock->offset) - + offset = (void *)bootblock + be32toh(bootblock->offset) - buffer_get(&cbfs.buffer); - size = ntohl(bootblock->len); + size = be32toh(bootblock->len); } /* Find and validate the metadata hash anchor inside the bootblock and @@ -507,13 +507,9 @@ static int convert_region_offset(unsigned int offset, uint32_t *region_offset) return 0; } -static int do_cbfs_locate(uint32_t *cbfs_addr, size_t metadata_size, - size_t data_size) +static int do_cbfs_locate(uint32_t *cbfs_addr, size_t data_size) { - if (!param.filename) { - ERROR("You need to specify -f/--filename.\n"); - return 1; - } + uint32_t metadata_size = 0; if (!param.name) { ERROR("You need to specify -n/--name.\n"); @@ -529,17 +525,10 @@ static int do_cbfs_locate(uint32_t *cbfs_addr, size_t metadata_size, WARN("'%s' already in CBFS.\n", param.name); if (!data_size) { - struct buffer buffer; - if (buffer_from_file(&buffer, param.filename) != 0) { - ERROR("Cannot load %s.\n", param.filename); - return 1; - } - data_size = buffer.size; - buffer_delete(&buffer); + ERROR("File '%s' is empty?\n", param.name); + return 1; } - DEBUG("File size is %zd (0x%zx)\n", data_size, data_size); - /* Compute required page size */ if (param.force_pow2_pagesize) { param.pagesize = 1; @@ -559,6 +548,8 @@ static int do_cbfs_locate(uint32_t *cbfs_addr, size_t metadata_size, } if (param.precompression || param.compression != CBFS_COMPRESS_NONE) metadata_size += sizeof(struct cbfs_file_attr_compression); + if (param.type == CBFS_TYPE_STAGE) + metadata_size += sizeof(struct cbfs_file_attr_stageheader); /* Take care of the hash attribute if it is used */ if (param.hash != VB2_HASH_INVALID) @@ -568,8 +559,8 @@ static int do_cbfs_locate(uint32_t *cbfs_addr, size_t metadata_size, param.alignment, metadata_size); if (address < 0) { - ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", - param.name, param.pagesize, param.alignment); + ERROR("'%s'(%u + %zu) can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, metadata_size, data_size, param.pagesize, param.alignment); return 1; } @@ -673,7 +664,7 @@ static int update_master_header_loc_topswap(struct cbfs_image *image, * Check if the existing topswap boundary matches with * the one provided. */ - if (param.topswap_size != ntohl(entry->len)/2) { + if (param.topswap_size != be32toh(entry->len)/2) { ERROR("Top swap boundary does not match\n"); return 1; } @@ -710,16 +701,16 @@ static int cbfs_add_master_header(void) return 1; struct cbfs_header *h = (struct cbfs_header *)buffer.data; - h->magic = htonl(CBFS_HEADER_MAGIC); - h->version = htonl(CBFS_HEADER_VERSION); + h->magic = htobe32(CBFS_HEADER_MAGIC); + h->version = htobe32(CBFS_HEADER_VERSION); /* The 4 bytes are left out for two reasons: * 1. the cbfs master header pointer resides there * 2. some cbfs implementations assume that an image that resides * below 4GB has a bootblock and get confused when the end of the * image is at 4GB == 0. */ - h->bootblocksize = htonl(4); - h->align = htonl(CBFS_ALIGNMENT); + h->bootblocksize = htobe32(4); + h->align = htobe32(CBFS_ALIGNMENT); /* The offset and romsize fields within the master header are absolute * values within the boot media. As such, romsize needs to relfect * the end 'offset' for a CBFS. To achieve that the current buffer @@ -729,9 +720,9 @@ static int cbfs_add_master_header(void) offset = buffer_get(param.image_region) - buffer_get_original_backing(param.image_region); size = buffer_size(param.image_region); - h->romsize = htonl(size + offset); - h->offset = htonl(offset); - h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN); + h->romsize = htobe32(size + offset); + h->offset = htobe32(offset); + h->architecture = htobe32(CBFS_ARCHITECTURE_UNKNOWN); /* Never add a hash attribute to the master header. */ header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER, @@ -812,18 +803,39 @@ static int add_topswap_bootblock(struct buffer *buffer, uint32_t *offset) static int cbfs_add_component(const char *filename, const char *name, - uint32_t type, uint32_t headeroffset, convert_buffer_t convert) { - size_t len_align = 0; + /* + * The steps used to determine the final placement offset in CBFS, in order: + * + * 1. If --base-address was passed, that value is used. If it was passed in the host + * address space, convert it to flash address space. (After that, |*offset| is always + * in the flash address space.) + * + * 2. The convert() function may write a location back to |offset|, usually by calling + * do_cbfs_locate(). In this case, it needs to ensure that the location found can fit + * the CBFS file in its final form (after any compression and conversion). + * + * 3. If --align was passed and the offset is still undecided at this point, + * do_cbfs_locate() is called to find an appropriately aligned location. + * + * 4. If |offset| is still 0 at the end, cbfs_add_entry() will find the first available + * location that fits. + */ uint32_t offset = param.baseaddress_assigned ? param.baseaddress : 0; + size_t len_align = 0; if (param.alignment && param.baseaddress_assigned) { ERROR("Cannot specify both alignment and base address\n"); return 1; } + if (param.stage_xip && param.compression != CBFS_COMPRESS_NONE) { + ERROR("Cannot specify compression for XIP.\n"); + return 1; + } + if (!filename) { ERROR("You need to specify -f/--filename.\n"); return 1; @@ -834,7 +846,7 @@ static int cbfs_add_component(const char *filename, return 1; } - if (type == 0) { + if (param.type == 0) { ERROR("You need to specify a valid -t/--type.\n"); return 1; } @@ -855,12 +867,12 @@ static int cbfs_add_component(const char *filename, } struct cbfs_file *header = - cbfs_create_file_header(type, buffer.size, name); + cbfs_create_file_header(param.type, buffer.size, name); /* Bootblock and CBFS header should never have file hashes. When adding the bootblock it is important that we *don't* look up the metadata hash yet (before it is added) or we'll cache an outdated result. */ - if (type != CBFS_TYPE_BOOTBLOCK && type != CBFS_TYPE_CBFSHEADER) { + if (param.type != CBFS_TYPE_BOOTBLOCK && param.type != CBFS_TYPE_CBFSHEADER) { enum vb2_hash_algorithm mh_algo = get_mh_cache()->cbfs_hash.algo; if (mh_algo != VB2_HASH_INVALID && param.hash != mh_algo) { if (param.hash == VB2_HASH_INVALID) { @@ -874,25 +886,29 @@ static int cbfs_add_component(const char *filename, } } - /* This needs to run after potentially updating param.hash above. */ - if (param.alignment) - if (do_cbfs_locate(&offset, 0, 0)) - goto error; - /* * Check if Intel CPU topswap is specified this will require a * second bootblock to be added. */ - if (type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) + if (param.type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) if (add_topswap_bootblock(&buffer, &offset)) goto error; + /* With --base-address we allow host space addresses -- if so, convert it here. */ + if (IS_HOST_SPACE_ADDRESS(offset)) + offset = convert_addr_space(param.image_region, offset); + if (convert && convert(&buffer, &offset, header) != 0) { ERROR("Failed to parse file '%s'.\n", filename); goto error; } - /* This needs to run after convert(). */ + /* This needs to run after convert() to take compression into account. */ + if (!offset && param.alignment) + if (do_cbfs_locate(&offset, buffer_size(&buffer))) + goto error; + + /* This needs to run after convert() to hash the actual final file data. */ if (param.hash != VB2_HASH_INVALID && cbfs_add_file_hash(header, &buffer, param.hash) == -1) { ERROR("couldn't add hash for '%s'\n", name); @@ -909,7 +925,7 @@ static int cbfs_add_component(const char *filename, sizeof(struct cbfs_file_attr_position)); if (attrs == NULL) goto error; - attrs->position = htonl(offset); + attrs->position = htobe32(offset); } /* Add alignment attribute if used */ if (param.alignment) { @@ -920,7 +936,7 @@ static int cbfs_add_component(const char *filename, sizeof(struct cbfs_file_attr_align)); if (attrs == NULL) goto error; - attrs->alignment = htonl(param.alignment); + attrs->alignment = htobe32(param.alignment); } } @@ -948,9 +964,6 @@ static int cbfs_add_component(const char *filename, goto error; } - if (IS_HOST_SPACE_ADDRESS(offset)) - offset = convert_addr_space(param.image_region, offset); - if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); goto error; @@ -1011,15 +1024,15 @@ static int cbfstool_convert_raw(struct buffer *buffer, free(compressed); return -1; } - attrs->compression = htonl(param.compression); - attrs->decompressed_size = htonl(decompressed_size); + attrs->compression = htobe32(param.compression); + attrs->decompressed_size = htobe32(decompressed_size); free(buffer->data); buffer->data = compressed; buffer->size = compressed_size; out: - header->len = htonl(buffer->size); + header->len = htobe32(buffer->size); return 0; } @@ -1028,45 +1041,44 @@ static int cbfstool_convert_fsp(struct buffer *buffer, { uint32_t address; struct buffer fsp; - int do_relocation = 1; - - address = *offset; /* - * If the FSP component is xip, then ensure that the address is a memory - * mapped one. - * If the FSP component is not xip, then use param.baseaddress that is - * passed in by the caller. + * There are 4 different cases here: + * + * 1. --xip and --base-address: we need to place the binary at the given base address + * in the CBFS image and relocate it to that address. *offset was already filled in, + * but we need to convert it to the host address space for relocation. + * + * 2. --xip but no --base-address: we implicitly force a 4K minimum alignment so that + * relocation can occur. Call do_cbfs_locate() here to find an appropriate *offset. + * This also needs to be converted to the host address space for relocation. + * + * 3. No --xip but a --base-address: special case where --base-address does not have its + * normal meaning, instead we use it as the relocation target address. We explicitly + * reset *offset to 0 so that the file will be placed wherever it fits in CBFS. + * + * 4. No --xip and no --base-address: this means that the FSP was pre-linked and should + * not be relocated. Just chain directly to convert_raw() for compression. */ + if (param.stage_xip) { - if (!IS_HOST_SPACE_ADDRESS(address)) - address = convert_addr_space(param.image_region, address); + if (!param.baseaddress_assigned) { + param.alignment = 4*1024; + if (do_cbfs_locate(offset, buffer_size(buffer))) + return -1; + } + assert(!IS_HOST_SPACE_ADDRESS(*offset)); + address = convert_addr_space(param.image_region, *offset); } else { if (param.baseaddress_assigned == 0) { - INFO("Honoring pre-linked FSP module.\n"); - do_relocation = 0; + INFO("Honoring pre-linked FSP module, no relocation.\n"); + return cbfstool_convert_raw(buffer, offset, header); } else { address = param.baseaddress; - /* - * *offset should either be 0 or the value returned by - * do_cbfs_locate. do_cbfs_locate is called only when param.baseaddress - * is not provided by user. Thus, set *offset to 0 if user provides - * a baseaddress i.e. params.baseaddress_assigned is set. The only - * requirement in this case is that the binary should be relocated to - * the base address that is requested. There is no requirement on where - * the file ends up in the cbfs. - */ *offset = 0; } } - /* - * Nothing left to do if relocation is not being attempted. Just add - * the file. - */ - if (!do_relocation) - return cbfstool_convert_raw(buffer, offset, header); - /* Create a copy of the buffer to attempt relocation. */ if (buffer_create(&fsp, buffer_size(buffer), "fsp")) return -1; @@ -1100,15 +1112,12 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, } /* - * If we already did a locate for alignment we need to locate again to - * take the stage header into account. XIP stage parsing also needs the - * location. But don't locate in other cases, because it will ignore - * compression (not applied yet) and thus may cause us to refuse adding - * stages that would actually fit once compressed. + * We need a final location for XIP parsing, so we need to call do_cbfs_locate() early + * here. That is okay because XIP stages may not be compressed, so their size cannot + * change anymore at a later point. */ - if ((param.alignment || param.stage_xip) && - do_cbfs_locate(offset, sizeof(struct cbfs_file_attr_stageheader), - data_size)) { + if (param.stage_xip && + do_cbfs_locate(offset, data_size)) { ERROR("Could not find location for stage.\n"); return 1; } @@ -1120,16 +1129,10 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, return -1; if (param.stage_xip) { - /* - * Ensure the address is a memory mapped one. This assumes - * x86 semantics about the boot media being directly mapped - * below 4GiB in the CPU address space. - **/ - *offset = convert_addr_space(param.image_region, *offset); - - ret = parse_elf_to_xip_stage(buffer, &output, *offset, - param.ignore_section, - stageheader); + uint32_t host_space_address = convert_addr_space(param.image_region, *offset); + assert(IS_HOST_SPACE_ADDRESS(host_space_address)); + ret = parse_elf_to_xip_stage(buffer, &output, host_space_address, + param.ignore_section, stageheader); } else { ret = parse_elf_to_stage(buffer, &output, param.ignore_section, stageheader); @@ -1149,7 +1152,7 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, /* Special care must be taken for LZ4-compressed stages that the BSS is large enough to provide scratch space for in-place decompression. */ if (!param.precompression && param.compression == CBFS_COMPRESS_LZ4) { - size_t memlen = ntohl(stageheader->memlen); + size_t memlen = be32toh(stageheader->memlen); size_t compressed_size = buffer_size(&output); uint8_t *compare_buffer = malloc(memlen); uint8_t *start = compare_buffer + memlen - compressed_size; @@ -1193,7 +1196,7 @@ static int cbfstool_convert_mkpayload(struct buffer *buffer, if (ret != 0) { ret = parse_fit_to_payload(buffer, &output, param.compression); if (ret == 0) - header->type = htonl(CBFS_TYPE_FIT); + header->type = htobe32(CBFS_TYPE_FIT); } /* If it's not an FIT, see if it's a UEFI FV */ @@ -1215,7 +1218,7 @@ static int cbfstool_convert_mkpayload(struct buffer *buffer, buffer_delete(buffer); // Direct assign, no dupe. memcpy(buffer, &output, sizeof(*buffer)); - header->len = htonl(output.size); + header->len = htobe32(output.size); return 0; } @@ -1232,7 +1235,7 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer, buffer_delete(buffer); // Direct assign, no dupe. memcpy(buffer, &output, sizeof(*buffer)); - header->len = htonl(output.size); + header->len = htobe32(output.size); return 0; } @@ -1240,50 +1243,41 @@ static int cbfs_add(void) { convert_buffer_t convert = cbfstool_convert_raw; - /* Set the alignment to 4KiB minimum for FSP blobs when no base address - * is provided so that relocation can occur. */ if (param.type == CBFS_TYPE_FSP) { - if (!param.baseaddress_assigned) - param.alignment = 4*1024; convert = cbfstool_convert_fsp; + } else if (param.type == CBFS_TYPE_STAGE) { + ERROR("stages can only be added with cbfstool add-stage\n"); + return 1; } else if (param.stage_xip) { - ERROR("cbfs add supports xip only for FSP component type\n"); + ERROR("cbfstool add supports xip only for FSP component type\n"); return 1; } return cbfs_add_component(param.filename, param.name, - param.type, param.headeroffset, convert); } static int cbfs_add_stage(void) { - if (param.stage_xip) { - if (param.baseaddress_assigned) { - ERROR("Cannot specify base address for XIP.\n"); - return 1; - } - - if (param.compression != CBFS_COMPRESS_NONE) { - ERROR("Cannot specify compression for XIP.\n"); - return 1; - } + if (param.stage_xip && param.baseaddress_assigned) { + ERROR("Cannot specify base address for XIP.\n"); + return 1; } + param.type = CBFS_TYPE_STAGE; return cbfs_add_component(param.filename, param.name, - CBFS_TYPE_STAGE, param.headeroffset, cbfstool_convert_mkstage); } static int cbfs_add_payload(void) { + param.type = CBFS_TYPE_SELF; return cbfs_add_component(param.filename, param.name, - CBFS_TYPE_SELF, param.headeroffset, cbfstool_convert_mkpayload); } @@ -1300,9 +1294,9 @@ static int cbfs_add_flat_binary(void) "-e/--entry-point.\n"); return 1; } + param.type = CBFS_TYPE_SELF; return cbfs_add_component(param.filename, param.name, - CBFS_TYPE_SELF, param.headeroffset, cbfstool_convert_mkflatpayload); } @@ -1777,7 +1771,6 @@ static struct option long_options[] = { {"pow2page", no_argument, 0, 'Q' }, {"ucode-region", required_argument, 0, 'q' }, {"size", required_argument, 0, 's' }, - {"top-aligned", required_argument, 0, 'T' }, {"type", required_argument, 0, 't' }, {"verbose", no_argument, 0, 'v' }, {"with-readonly", no_argument, 0, 'w' }, @@ -1933,9 +1926,6 @@ static void usage(char *name) "Create a legacy ROM file with CBFS master header*\n" " create -M flashmap [-r list,of,regions,containing,cbfses] " "Create a new-style partitioned firmware image\n" - " locate [-r image,regions] -f FILE -n NAME [-P page-size] \\\n" - " [-a align] [-T] " - "Find a place for a file of that size\n" " layout [-w] " "List mutable (or, with -w, readable) image regions\n" " print [-r image,regions] [-k] " @@ -1970,8 +1960,7 @@ static void usage(char *name) " specifying the location of this FMAP itself and a '%s'\n" " section describing the primary CBFS. It should also be noted\n" " that, when working with such images, the -F and -r switches\n" - " default to '%s' for convenience, and both the -b switch to\n" - " CBFS operations and the output of the locate action become\n" + " default to '%s' for convenience, and the -b switch becomes\n" " relative to the selected CBFS region's lowest address.\n" " The one exception to this rule is the top-aligned address,\n" " which is always relative to the end of the entire image\n" diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 5889e2a937..ea22bd6460 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -15,17 +15,6 @@ /* Utilities */ int verbose = 0; -/* Small, OS/libc independent runtime check for endianness */ -int is_big_endian(void) -{ - static const uint32_t inttest = 0x12345678; - const uint8_t inttest_lsb = *(const uint8_t *)&inttest; - if (inttest_lsb == 0x12) { - return 1; - } - return 0; -} - static off_t get_file_size(FILE *f) { off_t fsize; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index b23c8d21b0..d39f8fbfbd 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -10,11 +10,10 @@ #include #include +#include #include #include -#include "swab.h" - /* * There are two address spaces that this tool deals with - SPI flash address space and host * address space. This macros checks if the address is greater than 2GiB under the assumption diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 3ea352e6eb..1fd4113f52 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -157,6 +157,7 @@ static void eventlog_print_type(const struct event_header *event) {ELOG_TYPE_CR50_NEED_RESET, "cr50 Reset Required"}, {ELOG_TYPE_EC_DEVICE_EVENT, "EC Device"}, {ELOG_TYPE_EXTENDED_EVENT, "Extended Event"}, + {ELOG_TYPE_CROS_DIAGNOSTICS, "Diagnostics Mode"}, {ELOG_TYPE_EOL, "End of log"}, }; @@ -533,6 +534,11 @@ static int eventlog_print_data(const struct event_header *event) {0, NULL}, }; + static const struct valstr cros_diagnostics_types[] = { + {ELOG_CROS_LAUNCH_DIAGNOSTICS, "Launch Diagnostics"}, + {0, NULL}, + }; + switch (event->type) { case ELOG_TYPE_LOG_CLEAR: { const uint16_t *bytes = event_get_data(event); @@ -614,6 +620,10 @@ static int eventlog_print_data(const struct event_header *event) eventlog_printf("0x%X", ext_event->event_complement); break; } + case ELOG_TYPE_CROS_DIAGNOSTICS: { + const uint8_t *type = event_get_data(event); + eventlog_printf("%s", val2str(*type, cros_diagnostics_types)); + } default: break; } diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index b7a748ce61..7010dbc367 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause or GPL-2.0-only */ -#define _XOPEN_SOURCE 700 - #include #include #include @@ -15,6 +13,7 @@ #include #include #include +#include #include "fmap.h" #include "kv_pair.h" @@ -35,7 +34,7 @@ int fmap_size(const struct fmap *fmap) if (!fmap) return -1; - return sizeof(*fmap) + (fmap->nareas * sizeof(struct fmap_area)); + return sizeof(*fmap) + (le16toh(fmap->nareas) * sizeof(struct fmap_area)); } /* Make a best-effort assessment if the given fmap is real */ @@ -47,8 +46,8 @@ static int is_valid_fmap(const struct fmap *fmap) if (fmap->ver_major != FMAP_VER_MAJOR) return 0; /* a basic consistency check: flash should be larger than fmap */ - if (fmap->size < - sizeof(*fmap) + fmap->nareas * sizeof(struct fmap_area)) + if (le32toh(fmap->size) < + sizeof(*fmap) + le16toh(fmap->nareas) * sizeof(struct fmap_area)) return 0; /* fmap-alikes along binary data tend to fail on having a valid, @@ -177,14 +176,14 @@ int fmap_print(const struct fmap *fmap) kv_pair_fmt(kv, "fmap_ver_major", "%d", fmap->ver_major); kv_pair_fmt(kv, "fmap_ver_minor","%d", fmap->ver_minor); kv_pair_fmt(kv, "fmap_base", "0x%016llx", - (unsigned long long)fmap->base); - kv_pair_fmt(kv, "fmap_size", "0x%04x", fmap->size); + (unsigned long long)le64toh(fmap->base)); + kv_pair_fmt(kv, "fmap_size", "0x%04x", le32toh(fmap->size)); kv_pair_fmt(kv, "fmap_name", "%s", fmap->name); - kv_pair_fmt(kv, "fmap_nareas", "%d", fmap->nareas); + kv_pair_fmt(kv, "fmap_nareas", "%d", le16toh(fmap->nareas)); kv_pair_print(kv); kv_pair_free(kv); - for (i = 0; i < fmap->nareas; i++) { + for (i = 0; i < le16toh(fmap->nareas); i++) { struct kv_pair *pair; uint16_t flags; char *str; @@ -194,16 +193,16 @@ int fmap_print(const struct fmap *fmap) return -1; kv_pair_fmt(pair, "area_offset", "0x%08x", - fmap->areas[i].offset); + le32toh(fmap->areas[i].offset)); kv_pair_fmt(pair, "area_size", "0x%08x", - fmap->areas[i].size); + le32toh(fmap->areas[i].size)); kv_pair_fmt(pair, "area_name", "%s", fmap->areas[i].name); kv_pair_fmt(pair, "area_flags_raw", "0x%02x", - fmap->areas[i].flags); + le16toh(fmap->areas[i].flags)); /* Print descriptive strings for flags rather than the field */ - flags = fmap->areas[i].flags; + flags = le16toh(fmap->areas[i].flags); str = fmap_flags_to_string(flags); if (str == NULL) { kv_pair_free(pair); @@ -265,8 +264,8 @@ struct fmap *fmap_create(uint64_t base, uint32_t size, uint8_t *name) memcpy(&fmap->signature, FMAP_SIGNATURE, strlen(FMAP_SIGNATURE)); fmap->ver_major = FMAP_VER_MAJOR; fmap->ver_minor = FMAP_VER_MINOR; - fmap->base = base; - fmap->size = size; + fmap->base = htole64(base); + fmap->size = htole32(size); memccpy(&fmap->name, name, '\0', FMAP_STRLEN); return fmap; @@ -289,7 +288,7 @@ int fmap_append_area(struct fmap **fmap, return -1; /* too many areas */ - if ((*fmap)->nareas >= 0xffff) + if (le16toh((*fmap)->nareas) >= 0xffff) return -1; orig_size = fmap_size(*fmap); @@ -301,12 +300,12 @@ int fmap_append_area(struct fmap **fmap, area = (struct fmap_area *)((uint8_t *)*fmap + orig_size); memset(area, 0, sizeof(*area)); - memcpy(&area->offset, &offset, sizeof(area->offset)); - memcpy(&area->size, &size, sizeof(area->size)); memccpy(&area->name, name, '\0', FMAP_STRLEN); - memcpy(&area->flags, &flags, sizeof(area->flags)); + area->offset = htole32(offset); + area->size = htole32(size); + area->flags = htole16(flags); - (*fmap)->nareas++; + (*fmap)->nareas = htole16(le16toh((*fmap)->nareas) + 1); return new_size; } @@ -319,7 +318,7 @@ const struct fmap_area *fmap_find_area(const struct fmap *fmap, if (!fmap || !name) return NULL; - for (i = 0; i < fmap->nareas; i++) { + for (i = 0; i < le16toh(fmap->nareas); i++) { if (!strcmp((const char *)fmap->areas[i].name, name)) { area = &fmap->areas[i]; break; @@ -358,12 +357,12 @@ static struct fmap *fmap_create_test(void) goto fmap_create_test_exit; } - if (fmap->base != base) { + if (le64toh(fmap->base) != base) { printf("FAILURE: base is incorrect\n"); goto fmap_create_test_exit; } - if (fmap->size != 0x100000) { + if (le32toh(fmap->size) != 0x100000) { printf("FAILURE: size is incorrect\n"); goto fmap_create_test_exit; } @@ -373,7 +372,7 @@ static struct fmap *fmap_create_test(void) goto fmap_create_test_exit; } - if (fmap->nareas != 0) { + if (le16toh(fmap->nareas) != 0) { printf("FAILURE: number of areas is incorrect\n"); goto fmap_create_test_exit; } @@ -414,10 +413,10 @@ static int fmap_append_area_test(struct fmap **fmap) uint16_t nareas_orig; /* test_area will be used by fmap_csum_test and find_area_test */ struct fmap_area test_area = { - .offset = 0x400, - .size = 0x10000, + .offset = htole32(0x400), + .size = htole32(0x10000), .name = "test_area_1", - .flags = FMAP_AREA_STATIC, + .flags = htole16(FMAP_AREA_STATIC), }; status = fail; @@ -428,26 +427,26 @@ static int fmap_append_area_test(struct fmap **fmap) goto fmap_append_area_test_exit; } - nareas_orig = (*fmap)->nareas; - (*fmap)->nareas = ~(0); + nareas_orig = le16toh((*fmap)->nareas); + (*fmap)->nareas = htole16(~(0)); if (fmap_append_area(fmap, 0, 0, (const uint8_t *)"foo", 0) >= 0) { printf("FAILURE: failed to abort with too many areas\n"); goto fmap_append_area_test_exit; } - (*fmap)->nareas = nareas_orig; + (*fmap)->nareas = htole16(nareas_orig); total_size = sizeof(**fmap) + sizeof(test_area); if (fmap_append_area(fmap, - test_area.offset, - test_area.size, + le32toh(test_area.offset), + le32toh(test_area.size), test_area.name, - test_area.flags + le16toh(test_area.flags) ) != total_size) { printf("failed to append area\n"); goto fmap_append_area_test_exit; } - if ((*fmap)->nareas != 1) { + if (le16toh((*fmap)->nareas) != 1) { printf("FAILURE: failed to increment number of areas\n"); goto fmap_append_area_test_exit; } diff --git a/util/cbfstool/ifittool.c b/util/cbfstool/ifittool.c index 264f538a22..c2a5221f0c 100644 --- a/util/cbfstool/ifittool.c +++ b/util/cbfstool/ifittool.c @@ -356,11 +356,11 @@ int main(int argc, char *argv[]) return 1; } - len = ntohl(cbfs_file->len); + len = be32toh(cbfs_file->len); offset = offset_to_ptr(convert_to_from_top_aligned, &image.buffer, cbfs_get_entry_addr(&image, cbfs_file) + - ntohl(cbfs_file->offset)); + be32toh(cbfs_file->offset)); if (fit_add_entry(fit, offset, len, fit_type, @@ -384,7 +384,7 @@ int main(int argc, char *argv[]) fit_address = offset_to_ptr(convert_to_from_top_aligned, &image.buffer, cbfs_get_entry_addr(&image, cbfs_file) - + ntohl(cbfs_file->offset)); + + be32toh(cbfs_file->offset)); if (set_fit_pointer(&bootblock, fit_address, convert_to_from_top_aligned, diff --git a/util/cbfstool/swab.h b/util/cbfstool/swab.h deleted file mode 100644 index a45a7673d9..0000000000 --- a/util/cbfstool/swab.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef _SWAB_H -#define _SWAB_H - -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and suches for examples of how to provide - * architecture-dependent optimized versions - * - */ - -#if !defined(__APPLE__) && !defined(__NetBSD__) -#define ntohl(x) (is_big_endian() ? (uint32_t)(x) : swab32(x)) -#define htonl(x) (is_big_endian() ? (uint32_t)(x) : swab32(x)) -#else -#include -#endif -#define ntohll(x) (is_big_endian() ? (uint64_t)(x) : swab64(x)) -#define htonll(x) (is_big_endian() ? (uint64_t)(x) : swab64(x)) - -/* casts are necessary for constants, because we never know how for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define swab16(x) \ - ((unsigned short)( \ - (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ - (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) )) - -#define swab32(x) \ - ((unsigned int)( \ - (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ - (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ - (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ - (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) - -#define swab64(x) \ - ((uint64_t)( \ - (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ - (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ - (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ - (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ - (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ - (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ - (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ - (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) )) - -/* common.c */ -int is_big_endian(void); - -#endif /* _SWAB_H */ diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 085e004606..a39ef2ab8e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -17,7 +17,8 @@ #include #include #include -#include +#include +#include #include #include #include @@ -621,23 +622,30 @@ static void dump_timestamps(int mach_readable) if (!tst_p) die("Unable to map full timestamp table\n"); - /* Report the base time within the table. */ - prev_stamp = 0; - if (mach_readable) - timestamp_print_parseable_entry(0, tst_p->base_time, - prev_stamp); - else - timestamp_print_entry(0, tst_p->base_time, prev_stamp); - prev_stamp = tst_p->base_time; - - sorted_tst_p = malloc(size); + sorted_tst_p = malloc(size + sizeof(struct timestamp_entry)); if (!sorted_tst_p) die("Failed to allocate memory"); aligned_memcpy(sorted_tst_p, tst_p, size); + /* + * Insert a timestamp to represent the base time (start of coreboot), + * in case we have to rebase for negative timestamps below. + */ + sorted_tst_p->entries[tst_p->num_entries].entry_id = 0; + sorted_tst_p->entries[tst_p->num_entries].entry_stamp = 0; + sorted_tst_p->num_entries += 1; + qsort(&sorted_tst_p->entries[0], sorted_tst_p->num_entries, sizeof(struct timestamp_entry), compare_timestamp_entries); + /* + * If there are negative timestamp entries, rebase all of the + * timestamps to the lowest one in the list. + */ + if (sorted_tst_p->entries[0].entry_stamp < 0) + sorted_tst_p->base_time = -sorted_tst_p->entries[0].entry_stamp; + prev_stamp = 0; + total_time = 0; for (uint32_t i = 0; i < sorted_tst_p->num_entries; i++) { uint64_t stamp; @@ -721,8 +729,31 @@ enum console_print_type { CONSOLE_PRINT_PREVIOUS, }; +static int parse_loglevel(char *arg, int *print_unknown_logs) +{ + if (arg[0] == '+') { + *print_unknown_logs = 1; + arg++; + } else { + *print_unknown_logs = 0; + } + + char *endptr; + int loglevel = strtol(arg, &endptr, 0); + if (*endptr == '\0' && loglevel >= BIOS_EMERG && loglevel <= BIOS_LOG_PREFIX_MAX_LEVEL) + return loglevel; + + /* Only match first 3 characters so `NOTE` and `NOTICE` both match. */ + for (int i = BIOS_EMERG; i <= BIOS_LOG_PREFIX_MAX_LEVEL; i++) + if (!strncasecmp(arg, bios_log_prefix[i], 3)) + return i; + + *print_unknown_logs = 1; + return BIOS_NEVER; +} + /* dump the cbmem console */ -static void dump_console(enum console_print_type type) +static void dump_console(enum console_print_type type, int max_loglevel, int print_unknown_logs) { const struct cbmem_console *console_p; char *console_c; @@ -776,7 +807,8 @@ static void dump_console(enum console_print_type type) /* Slight memory corruption may occur between reboots and give us a few unprintable characters like '\0'. Replace them with '?' on output. */ for (cursor = 0; cursor < size; cursor++) - if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) + if (!isprint(console_c[cursor]) && !isspace(console_c[cursor]) + && !BIOS_LOG_IS_MARKER(console_c[cursor])) console_c[cursor] = '?'; /* We detect the reboot cutoff by looking for a bootblock, romstage or @@ -815,7 +847,33 @@ static void dump_console(enum console_print_type type) cursor = previous; } - puts(console_c + cursor); + char c; + int suppressed = 0; + int tty = isatty(fileno(stdout)); + while ((c = console_c[cursor++])) { + if (BIOS_LOG_IS_MARKER(c)) { + int lvl = BIOS_LOG_MARKER_TO_LEVEL(c); + if (lvl > max_loglevel) { + suppressed = 1; + continue; + } + suppressed = 0; + if (tty) + printf(BIOS_LOG_ESCAPE_PATTERN, bios_log_escape[lvl]); + printf(BIOS_LOG_PREFIX_PATTERN, bios_log_prefix[lvl]); + } else { + if (!suppressed) + putchar(c); + if (c == '\n') { + if (tty && !suppressed) + printf(BIOS_LOG_ESCAPE_RESET); + suppressed = !print_unknown_logs; + } + } + } + if (tty) + printf(BIOS_LOG_ESCAPE_RESET); + free(console_c); unmap_memory(&console_mapping); } @@ -1101,6 +1159,7 @@ static void print_usage(const char *name, int exit_code) " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" " -2 | --2ndtolast: print cbmem console for the boot that came before the last one only\n" + " -B | --loglevel: maximum loglevel to print; prefix `+` (e.g. -B +INFO) to also print lines that have no level\n" " -C | --coverage: dump coverage information\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" @@ -1243,12 +1302,15 @@ int main(int argc, char** argv) int machine_readable_timestamps = 0; enum console_print_type console_type = CONSOLE_PRINT_FULL; unsigned int rawdump_id = 0; + int max_loglevel = BIOS_NEVER; + int print_unknown_logs = 1; int opt, option_index = 0; static struct option long_options[] = { {"console", 0, 0, 'c'}, {"oneboot", 0, 0, '1'}, {"2ndtolast", 0, 0, '2'}, + {"loglevel", required_argument, 0, 'B'}, {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, {"tcpa-log", 0, 0, 'L'}, @@ -1261,7 +1323,7 @@ int main(int argc, char** argv) {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c12CltTLxVvh?r:", + while ((opt = getopt_long(argc, argv, "c12B:CltTLxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1278,6 +1340,9 @@ int main(int argc, char** argv) console_type = CONSOLE_PRINT_PREVIOUS; print_defaults = 0; break; + case 'B': + max_loglevel = parse_loglevel(optarg, &print_unknown_logs); + break; case 'C': print_coverage = 1; print_defaults = 0; @@ -1403,7 +1468,7 @@ int main(int argc, char** argv) die("Table not found.\n"); if (print_console) - dump_console(console_type); + dump_console(console_type, max_loglevel, print_unknown_logs); if (print_coverage) dump_coverage(); diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 25c88fa346..3d0f0612f8 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -28,73 +28,98 @@ exit_if_dependencies_are_missing() { exit_if_uninstalled "unzip" "unzip" } -get_inventory() -{ +get_inventory() { _conf=$1 _url=https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf echo "Downloading recovery image inventory..." - curl -s "$_url" > $_conf + curl -s "$_url" >$_conf } -download_image() -{ +download_image() { _url=$1 _file=$2 echo "Downloading recovery image" - curl "$_url" > "$_file.zip" + curl "$_url" >"$_file.zip" echo "Decompressing recovery image" unzip -q "$_file.zip" rm "$_file.zip" } -extract_partition() -{ +extract_partition() { NAME=$1 FILE=$2 ROOTFS=$3 _bs=1024 echo "Extracting ROOT-A partition" - ROOTP=$( printf "unit\nB\nprint\nquit\n" | \ - parted $FILE 2>/dev/null | grep $NAME ) + ROOTP=$(printf "unit\nB\nprint\nquit\n" | + parted $FILE 2>/dev/null | grep $NAME) - START=$(( $( echo $ROOTP | cut -f2 -d\ | tr -d "B" ) )) - SIZE=$(( $( echo $ROOTP | cut -f4 -d\ | tr -d "B" ) )) + if [ "$ROOTP" == "" ]; then + # Automatic extraction failed, likely due to parted detecting + # overlapping partitions. Fall back to using fdisk and assume + # ROOT-A is partition #3 + echo "(Extracting via parted failed; falling back to fdisk)" + _ssize=$(printf "p q" | fdisk $FILE | grep "Sector size" | + cut -f2 -d: | cut -f2 -d ' ') + _start=$(printf "p q" | fdisk $FILE | grep "bin3" | tr -s ' ' | + cut -f2 -d ' ') + _nsec=$(printf "p q" | fdisk $FILE | grep "bin3" | tr -s ' ' | + cut -f4 -d ' ') + START=$(($_ssize * $_start)) + SIZE=$(($_ssize * $_nsec)) + else + START=$(($(echo $ROOTP | cut -f2 -d\ | tr -d "B"))) + SIZE=$(($(echo $ROOTP | cut -f4 -d\ | tr -d "B"))) + fi - dd if=$FILE of=$ROOTFS bs=$_bs skip=$(( $START / $_bs )) \ - count=$(( $SIZE / $_bs )) > /dev/null + dd if=$FILE of=$ROOTFS bs=$_bs skip=$(($START / $_bs)) \ + count=$(($SIZE / $_bs)) >/dev/null 2>&1 } -extract_shellball() -{ +extract_shellball() { ROOTFS=$1 SHELLBALL=$2 echo "Extracting chromeos-firmwareupdate" - printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | \ - debugfs $ROOTFS > /dev/null 2>&1 + printf "cd /usr/sbin\ndump chromeos-firmwareupdate $SHELLBALL\nquit" | + debugfs $ROOTFS >/dev/null 2>&1 } -extract_coreboot() -{ +extract_coreboot() { _shellball=$1 - _unpacked=$( mktemp -d ) + _unpacked=$(mktemp -d) echo "Extracting coreboot image" - sh $_shellball --sb_extract $_unpacked > /dev/null + if ! sh $_shellball --unpack $_unpacked >/dev/null 2>&1; then + sh $_shellball --sb_extract $_unpacked >/dev/null 2>&1 + fi - _version=$( cat $_unpacked/VERSION | grep BIOS\ version: | \ - cut -f2 -d: | tr -d \ ) - - cp $_unpacked/bios.bin coreboot-$_version.bin - rm -r "$_unpacked" + if [ -d $_unpacked/models/ ]; then + _version=$(cat $_unpacked/VERSION | grep -m 1 -e Model.*$_board -A5 | + grep "BIOS (RW) version:" | cut -f2 -d: | tr -d \ ) + if [ "$_version" == "" ]; then + _version=$(cat $_unpacked/VERSION | grep -m 1 -e Model.*$_board -A5 | + grep "BIOS version:" | cut -f2 -d: | tr -d \ ) + fi + _bios_image=$(grep "IMAGE_MAIN" $_unpacked/models/$_board/setvars.sh | + cut -f2 -d\") + else + _version=$(cat $_unpacked/VERSION | grep BIOS\ version: | + cut -f2 -d: | tr -d \ ) + _bios_image=bios.bin + fi + if cp $_unpacked/$_bios_image coreboot-$_version.bin; then + echo "Extracted coreboot-$_version.bin" + fi + rm -rf "$_unpacked" + rm $_shellball } -do_one_board() -{ +do_one_board() { _board=$1 _url=$2 _file=$3 @@ -117,25 +142,25 @@ BOARD=$1 exit_if_dependencies_are_missing if [ "$BOARD" == "all" ]; then - CONF=$( mktemp ) + CONF=$(mktemp) get_inventory $CONF - grep ^name= $CONF| while read _line; do - name=$( echo $_line | cut -f2 -d= ) + grep ^name= $CONF | while read _line; do + name=$(echo $_line | cut -f2 -d=) echo Processing board $name - eval $( grep -v hwid= $CONF | grep -A11 "$_line" | \ - grep '\(url=\|file=\)' ) - BOARD=$( echo $url | cut -f3 -d_ ) + eval $(grep -v hwid= $CONF | grep -A11 "$_line" | + grep '\(url=\|file=\)') + BOARD=$(echo $url | cut -f3 -d_) do_one_board $BOARD $url $file done rm "$CONF" elif [ "$BOARD" != "" ]; then - CONF=$( mktemp ) + CONF=$(mktemp) get_inventory $CONF echo Processing board $BOARD - eval $( grep $BOARD $CONF | grep '\(url=\|file=\)' ) + eval $(grep -i $BOARD -A8 $CONF | grep '\(url=\|file=\)') do_one_board $BOARD $url $file rm "$CONF" diff --git a/util/chromeos/extract_blobs.sh b/util/chromeos/extract_blobs.sh index 39f2a3b4e9..74b52205ea 100755 --- a/util/chromeos/extract_blobs.sh +++ b/util/chromeos/extract_blobs.sh @@ -2,40 +2,116 @@ # # SPDX-License-Identifier: GPL-2.0-only -set -x +if [ ! -f "$1" ]; then + echo "Error: You must provide a valid filename" + exit 1 +fi IMAGE=$1 +# create new dir '$IMAGE-blobs' (less file extension) +DIR=$(basename $IMAGE) +DIR="${DIR%.*}-blobs" +mkdir -p $DIR -if [ ! -r "$IMAGE" ]; then - echo "Can't find image $IMAGE." - exit 1 +if [ -f ./cbfstool ]; then + CBFSTOOL="./cbfstool" +else + CBFSTOOL=$(command -v cbfstool) +fi +if [[ "$CBFSTOOL" = "" ]]; then + echo "Error: cbfstool must be in your path or exist locally" + exit 1 fi -CBFSTOOL=$(which cbfstool) -if [ $? != 0 ]; then - echo "Can't find cbfstool." - exit 1 +if [ -f ./ifdtool ]; then + IFDTOOL="./ifdtool" +else + IFDTOOL=$(which ifdtool) +fi +if [[ "$IFDTOOL" = "" ]]; then + echo "Error: ifdtool must be in your path or exist locally" + exit 1 fi -IFDTOOL=$(which ifdtool) -if [ $? != 0 ]; then - echo "Can't find ifdtool." - exit 1 +# ensure valid coreboot image / get list of main COREBOOT CBFS contents +REGION="" +if ! $CBFSTOOL $IMAGE print >$DIR/cbfs.txt 2>/dev/null; then + # try using BOOT_STUB region + if ! $CBFSTOOL $IMAGE print -r BOOT_STUB >$DIR/cbfs.txt; then + echo "Error reading CBFS: $IMAGE is not a valid coreboot image" + exit 1 + else + REGION="-r BOOT_STUB" + fi fi -$CBFSTOOL $IMAGE print +echo "" +echo "Extracting blobs..." +echo "" -if [ $? -ne 0 ]; then - echo "Not a coreboot image: $IMAGE" - exit 1 +# extract flash regions +if ! $IFDTOOL -x $IMAGE >/dev/null; then + echo "Error reading flash descriptor/extracting flash regions" + exit 1 fi - -PCI=$($CBFSTOOL $IMAGE print|grep pci|cut -f1 -d\ ) -MRC=$($CBFSTOOL $IMAGE print|grep mrc.bin|cut -f1 -d\ ) - -$CBFSTOOL $IMAGE extract -n $PCI -f $PCI -$CBFSTOOL $IMAGE extract -n $MRC -f $MRC -$IFDTOOL -x $IMAGE -mv flashregion_0_flashdescriptor.bin flashdescriptor.bin -mv flashregion_2_intel_me.bin me.bin +# rename to normal convention; drop unused regions +mv flashregion_0_flashdescriptor.bin $DIR/flashdescriptor.bin +[ -f flashregion_2_intel_me.bin ] && mv flashregion_2_intel_me.bin $DIR/me.bin rm flashregion_*.bin + +# extract microcode +$CBFSTOOL $IMAGE extract $REGION -n cpu_microcode_blob.bin -f $DIR/cpu_microcode_blob.bin + +# extract VGA BIOS +VGA=$(grep pci $DIR/cbfs.txt | cut -f1 -d\ ) +if [ "$VGA" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n $VGA -f $DIR/vgabios.bin +fi + +# extract MRC.bin +MRC=$(grep mrc.bin $DIR/cbfs.txt | cut -f1 -d\ ) +if [ "$MRC" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n "$MRC" -f "$DIR/$MRC" +fi + +# extract refcode +REF=$(grep refcode $DIR/cbfs.txt | cut -f1 -d\ ) +if [ "$REF" != "" ]; then + $CBFSTOOL $IMAGE extract $REGION -n fallback/refcode -f "$DIR/refcode.elf" -m x86 +fi + +# extract FSP blobs +for FSP in $(grep fsp $DIR/cbfs.txt | cut -f1 -d\ ); do + $CBFSTOOL $IMAGE extract $REGION -n $FSP -f $DIR/$FSP +done + +# extract audio blobs +for AUD in $(grep -e "-2ch-" -e "-4ch-" $DIR/cbfs.txt | cut -f1 -d\ ); do + $CBFSTOOL $IMAGE extract $REGION -n $AUD -f $DIR/$AUD +done + +# extract VBTs +for VBT in $(grep vbt $DIR/cbfs.txt | cut -f1 -d\ ); do + $CBFSTOOL $IMAGE extract $REGION -n $VBT -f $DIR/$VBT +done + +# extract IFWI +IFWI=$(cbfstool $IMAGE layout -w | grep IFWI) +if [ "$IFWI" != "" ]; then + $CBFSTOOL $IMAGE read -r IFWI -f $DIR/ifwi.bin +fi + +# generate hashes +( + cd $DIR + : >hashes.txt + for FILE in $(ls *.{bin,elf} 2>/dev/null); do + sha256sum $FILE >>hashes.txt + done +) + +# a little housekeeping +rm $DIR/cbfs.txt + +echo "" +echo "All done" diff --git a/util/coreboot-configurator/README.md b/util/coreboot-configurator/README.md new file mode 100644 index 0000000000..baf04903b2 --- /dev/null +++ b/util/coreboot-configurator/README.md @@ -0,0 +1,65 @@ +# coreboot-configurator ![alt text](images/StarLabs_Logo.png "Star Labs Systems") + +A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility. + +![coreboot-configurator](images/coreboot-configurator.gif) +# How to install +## Ubuntu, Linux Mint, elementary OS, Zorin OS and other derivates +##### Install +``` +sudo add-apt-repository ppa:starlabs/coreboot +sudo apt update +sudo apt install coreboot-configurator +``` +##### Uninstall +``` +sudo apt purge coreboot-configurator +``` + +## Debian 11 +##### Install +``` +echo "deb http://ppa.launchpad.net/starlabs/ppa/ubuntu focal main" | sudo tee -a /etc/apt/sources.list.d/starlabs-ubuntu-ppa-focal.list +sudo apt-key adv --keyserver keyserver.ubuntu.com --recv-keys 17A20BAF70BEC3904545ACFF8F21C26C794386E3 +sudo apt update +sudo apt install coreboot-configurator +``` + +##### Uninstall +``` +sudo apt purge coreboot-configurator +``` + +## Manjaro +##### Install +``` +sudo pamac install coreboot-configurator +``` +##### Uninstall +``` +sudo pamac remove coreboot-configurator +``` + +## Other Distributions +##### Install +``` +git clone https://github.com/StarLabsLtd/coreboot-configurator.git +cd coreboot-configurator +meson build +ninja -C build install +``` +##### Uninstall +``` +sudo ninja -C uninstall +``` + +# Advanced Mode +Enabling advanced mode will all you to see all settings contained inside coreboot. Tread carefully :) + +## Copying or Reusing +Included scripts are free software licensed under the terms of the [GNU General Public License, version 2](https://www.gnu.org/licenses/gpl-2.0.txt). + +# [© Star Labs® / All Rights Reserved.](https://starlabs.systems) +Any issues or questions, please contact us at [support@starlabs.systems](mailto:supportstarlabs.systems) + +View our full range of Linux laptops at: [https://starlabs.systems](https://starlabs.systems) diff --git a/util/coreboot-configurator/contrib/PKGBUILD b/util/coreboot-configurator/contrib/PKGBUILD new file mode 100644 index 0000000000..931dff2468 --- /dev/null +++ b/util/coreboot-configurator/contrib/PKGBUILD @@ -0,0 +1,24 @@ +# Maintainer: Bernhard Landauer + +pkgname=coreboot-configurator +pkgver=8 +pkgrel=2 +pkgdesc="A graphical interface to set options on devices with coreboot firmware" +arch=('x86_64') +url="https://github.com/StarLabsLtd/coreboot-configurator" +license=('GPL3') +depends=('nvramtool' 'qt5-base' 'qt5-svg' 'yaml-cpp') +makedepends=('inkscape' 'meson' 'qt5-tools' 'cmake') +source=("$pkgname-$pkgver.tar.gz::$url/archive/refs/tags/$pkgver.tar.gz") +sha256sums=('176d7f64ee32d3d03bbc3674d48ffe479d8450068a4b7bd26d328ed80d2a1c75') + +build() { + arch-meson "$pkgname-$pkgver" build + meson compile -C build +} + +package() { + meson install -C build --destdir "$pkgdir" + + install -d "$pkgdir/usr/bin/" +} diff --git a/util/coreboot-configurator/contrib/README.md b/util/coreboot-configurator/contrib/README.md new file mode 100644 index 0000000000..8b57580480 --- /dev/null +++ b/util/coreboot-configurator/contrib/README.md @@ -0,0 +1,36 @@ +# Distribution Packages ![alt text](images/StarLabs_Logo.png "Star Labs Systems") +The relevant packaging necessary to generate DEB, flatpak and PKG distribution packages is contained here. The generated packages can be used on a distribution such as Fedora, Debian, Ubuntu or Manjaro. + +# DEB packages +To build the DEBs, run these commands (from the root of your git checkout): +```bash +cp -r contrib/debian . +debuild --no-lintian +``` +To build source files, modify the [change log](debian/changelog) accordingly and run: +```bash +cp -r contrib/debian . +debuild -S +``` + +# PKG +A sample [PKGBUILD](PKGBUILD) is included. + +# Flatpak +To build the Flatpak, run these commands (from the root of your git checkout): +```bash +meson build --prefix=/usr +pushd build +meson dist +popd +cp contrib/flatpak/org.coreboot.coreboot-configurator.json . +flatpak-builder build-dir org.coreboot.coreboot-configurator.json +``` + +## Copying or Reusing +Included scripts are free software licensed under the terms of the [GNU General Public License, version 3](https://www.gnu.org/licenses/gpl-3.0.txt). + +# [© Star Labs® / All Rights Reserved.](https://starlabs.systems) +Any issues or questions, please contact us at [support@starlabs.systems](mailto:supportstarlabs.systems) + +View our full range of Linux laptops at: [https://starlabs.systems](https://starlabs.systems) diff --git a/util/coreboot-configurator/contrib/debian/changelog b/util/coreboot-configurator/contrib/debian/changelog new file mode 100644 index 0000000000..dc664b0fd6 --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/changelog @@ -0,0 +1,50 @@ +coreboot-configurator (8) impish; urgency=medium + + * Release version 8 + + -- Sean Rhodes Wed, 03 Nov 2021 21:06:03 +0000 + +coreboot-configurator (7+a) focal; urgency=medium + + * Version 7 to match coreboot 7 + + -- Sean Rhodes Tue, 24 Aug 2021 07:35:16 +0100 + +coreboot-configurator (6.h) hirsute; urgency=medium + + * Version 6 to match coreboot 6 + * Adds support to disable or enable VT-d, wireless, webcam, microphone and clock gating + * Adds support to select TDP + + -- Sean Rhodes Fri, 11 Jun 2021 08:40:38 +0100 + +coreboot-configurator (5) hirsute; urgency=medium + + * Version 5 to match coreboot 5 + * Adds support to disable or enable IME + + -- Sean Rhodes Thu, 29 Apr 2021 14:39:40 +0100 + +coreboot-configurator (3) hirsute; urgency=medium + + * Added qt5-default dependency + + -- Sean Rhodes Wed, 14 Apr 2021 16:44:13 +0100 + +coreboot-configurator (2) hirsute; urgency=medium + + * Fixed values that a read + + -- Sean Rhodes Tue, 13 Apr 2021 16:40:04 +0100 + +coreboot-configurator (1) hirsute; urgency=medium + + * Fixed icon + + -- Sean Rhodes Tue, 13 Apr 2021 11:47:04 +0100 + +coreboot-configurator (0) hirsute; urgency=medium + + * Initial release. + + -- Sean Rhodes Mon, 12 Apr 2021 21:14:48 +0100 diff --git a/util/coreboot-configurator/contrib/debian/compat b/util/coreboot-configurator/contrib/debian/compat new file mode 100644 index 0000000000..f599e28b8a --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/compat @@ -0,0 +1 @@ +10 diff --git a/util/coreboot-configurator/contrib/debian/control b/util/coreboot-configurator/contrib/debian/control new file mode 100644 index 0000000000..20174a4bcb --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/control @@ -0,0 +1,11 @@ +Source: coreboot-configurator +Section: utils +Priority: optional +Maintainer: Star Labs +Build-Depends: build-essential, cmake, debhelper (>= 7), inkscape, libqt5gui5, libqt5svg5-dev, libyaml-cpp-dev, libqt5gui5, meson, pkg-config, qtbase5-dev, qttools5-dev-tools +Standards-Version: 4.1.1 + +Package: coreboot-configurator +Depends: nvramtool, ${shlibs:Depends}, ${misc:Depends}, libqt5gui5, qt5-style-plugins, libyaml-cpp0.6 +Architecture: all +Description: Graphical interface to change settings available in coreboot CBFS diff --git a/util/coreboot-configurator/contrib/debian/files b/util/coreboot-configurator/contrib/debian/files new file mode 100644 index 0000000000..db63f72d47 --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/files @@ -0,0 +1,2 @@ +coreboot-configurator_7+a_all.deb utils optional +coreboot-configurator_7+a_amd64.buildinfo utils optional diff --git a/util/coreboot-configurator/contrib/debian/rules b/util/coreboot-configurator/contrib/debian/rules new file mode 100755 index 0000000000..a27f212560 --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/rules @@ -0,0 +1,11 @@ +#!/usr/bin/make -f +#export DH_VERBOSE = 1 + +%: + dh $@ --buildsystem=meson + +override_dh_install: + dh_install + +override_dh_missing: + dh_missing --fail-missing diff --git a/util/coreboot-configurator/contrib/debian/source/format b/util/coreboot-configurator/contrib/debian/source/format new file mode 100644 index 0000000000..89ae9db8f8 --- /dev/null +++ b/util/coreboot-configurator/contrib/debian/source/format @@ -0,0 +1 @@ +3.0 (native) diff --git a/util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json b/util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json new file mode 100644 index 0000000000..96509113c6 --- /dev/null +++ b/util/coreboot-configurator/contrib/flatpak/coreboot-configurator.json @@ -0,0 +1,3 @@ +{ + "skip-appstream-check": true +} diff --git a/util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json b/util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json new file mode 100644 index 0000000000..b83bbcebdd --- /dev/null +++ b/util/coreboot-configurator/contrib/flatpak/org.coreboot.coreboot-configurator.json @@ -0,0 +1,36 @@ +{ + "app-id": "org.coreboot.coreboot-configurator", + "runtime": "org.kde.Platform", + "runtime-version": "5.12", + "sdk": "org.kde.Platform", + "branch": "stable", + "command": "/usr/sbin/coreboot-configurator", + "modules": [ + { + "name": "coreboot-configurator", + "buildsystem": "meson", + "cleanup ": [ + "/usr/sbin/coreboot-configurator", + "/usr/share/coreboot-configurator/aboutIcon.png", + "/usr/share/polkit-1/actions/org.coreboot.nvramtool.policy", + "/usr/share/polkit-1/actions/org.coreboot.reboot.policy", + "usr/share/applications/coreboot-configurator.desktop", + "/usr/share/icons/hicolor/24x24/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/48x48/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/96x96/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/16x16/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/32x32/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/64x64/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/128x128/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/256x256/apps/coreboot-configurator.png", + "/usr/share/icons/hicolor/512x512/apps/coreboot-configurator.png" + ], + "sources": [ + { + "type": "archive", + "path": "build/meson-dist/coreboot-configurator-8.tar.xz" + } + ] + } + ] +} diff --git a/util/coreboot-configurator/images/StarLabs_Logo.png b/util/coreboot-configurator/images/StarLabs_Logo.png new file mode 100644 index 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@@ +## SPDX-License-Identifier: GPL-2.0-only + +project('coreboot-configurator', + 'cpp', + version: '8', + license: ['GPL2', 'CC BY-SA 4.0'], + meson_version: '>= 0.53.0', + default_options: ['prefix=/usr', + 'cpp_std=c++14'], +) + +subdir('src') diff --git a/util/coreboot-configurator/meson_options.txt b/util/coreboot-configurator/meson_options.txt new file mode 100644 index 0000000000..2dedd74024 --- /dev/null +++ b/util/coreboot-configurator/meson_options.txt @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +option('sizes', + type: 'array', + choices: ['24', '48', '96', '16', '32', '64', '128', '256', '512'], + description: 'Choose icon size(s)', +) + +option('mock', + type : 'boolean', + value : false +) diff --git a/util/coreboot-configurator/src/README.md b/util/coreboot-configurator/src/README.md new file mode 100644 index 0000000000..e3386242a2 --- /dev/null +++ b/util/coreboot-configurator/src/README.md @@ -0,0 +1,31 @@ +# Categories ![alt text](images/StarLabs_Logo.png "Star Labs Systems") + +CMOS values should be added to [categories.yaml](src/application/categories.yaml]. + +This allows `coreboot-configurator` to display them in a relavant tab, with a nice +name and help text. Without this, they will still be visible in the **Raw** tab. + +An example entry is below: +``` +processor: + displayName: Processor + me_state: + displayName: Intel Management Engine + type: bool + help: Enable or disable the Intel Management Engine +``` + +To explain the options: +``` +**tabgroup**: <- This is the reference to the tab group + displayName: **Hello World** <- This is the name of the group that the user + will see + **setting_1**: <- This is the value that should match the CMOS + option. + displayName: **Hi World** <- This is the name of the option that the user + will see. + type: **bool** <- Valid type are: bool (checkbox) and enum + <- (dropdown). + help: **Greet the World** <- Help text that is displayed when hovering on the + option. +``` diff --git a/util/coreboot-configurator/src/application/AboutDialog.cpp b/util/coreboot-configurator/src/application/AboutDialog.cpp new file mode 100644 index 0000000000..8282e0c063 --- /dev/null +++ b/util/coreboot-configurator/src/application/AboutDialog.cpp @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "AboutDialog.h" +#include "NvramToolCli.h" +#include "ui_AboutDialog.h" + +AboutDialog::AboutDialog(QWidget *parent) : + QDialog(parent), + ui(new Ui::AboutDialog) +{ + ui->setupUi(this); + + ui->logoLabel->setPixmap(QPixmap(":/images/star.svg")); + + ui->versionLabel->setText(""+NvramToolCli::version()+""); +} + +AboutDialog::~AboutDialog() +{ + delete ui; +} diff --git a/util/coreboot-configurator/src/application/AboutDialog.h b/util/coreboot-configurator/src/application/AboutDialog.h new file mode 100644 index 0000000000..7a3123335d --- /dev/null +++ b/util/coreboot-configurator/src/application/AboutDialog.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include + +namespace Ui { +class AboutDialog; +} + +class AboutDialog : public QDialog +{ + Q_OBJECT + +public: + explicit AboutDialog(QWidget *parent = nullptr); + ~AboutDialog(); + +private: + Ui::AboutDialog *ui; +}; diff --git a/util/coreboot-configurator/src/application/AboutDialog.ui b/util/coreboot-configurator/src/application/AboutDialog.ui new file mode 100644 index 0000000000..009acc24b9 --- /dev/null +++ b/util/coreboot-configurator/src/application/AboutDialog.ui @@ -0,0 +1,141 @@ + + + AboutDialog + + + + 0 + 0 + 412 + 273 + + + + About + + + + + + <html><head/><body><p><span style=" font-size:16pt; font-weight:600;">coreboot configurator</span></p></body></html> + + + Qt::AlignCenter + + + + + + + + 0 + 0 + + + + + + + Qt::AlignCenter + + + + + + + + 0 + 0 + + + + <html><head/><body><p>A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.</p></body></html> + + + Qt::AlignCenter + + + true + + + + + + + + + + Qt::AlignCenter + + + + + + + + 0 + 0 + + + + <html><head/><body><p><a href="https://support.starlabs.systems"><span style=" text-decoration: underline; color:#0000ff;">starlabs.systems</span></a></p></body></html> + + + Qt::AlignCenter + + + true + + + + + + + Qt::Horizontal + + + QDialogButtonBox::Ok + + + true + + + + + + + + + buttonBox + accepted() + AboutDialog + accept() + + + 248 + 254 + + + 157 + 274 + + + + + buttonBox + rejected() + AboutDialog + reject() + + + 316 + 260 + + + 286 + 274 + + + + + diff --git a/util/coreboot-configurator/src/application/Configuration.cpp b/util/coreboot-configurator/src/application/Configuration.cpp new file mode 100644 index 0000000000..9f383f83e2 --- /dev/null +++ b/util/coreboot-configurator/src/application/Configuration.cpp @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "Configuration.h" +#include "Util.h" + +QMap Configuration::fromFile(const QString &curr_path) +{ + QFile curr_file(curr_path); + + if ( !curr_file.open(QFile::ReadOnly) + || !curr_file.isReadable() + || curr_file.atEnd()) { + return {}; + } + + auto result = Util::parseParameters(curr_file); + + curr_file.close(); + return result; +} + + +bool Configuration::toFile(const QString &curr_path, const Parameters ¶ms) +{ + QFile output(curr_path); + + if(!output.open(QFile::WriteOnly|QFile::Truncate)){ + return false; + } + QTextStream outStream(&output); + for(auto it = params.begin(); it != params.end(); ++it){ + outStream << it.key() << " = " << it.value() << "\n"; + } + + output.close(); + return true; +} diff --git a/util/coreboot-configurator/src/application/Configuration.h b/util/coreboot-configurator/src/application/Configuration.h new file mode 100644 index 0000000000..b2559d4960 --- /dev/null +++ b/util/coreboot-configurator/src/application/Configuration.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include +#include +#include +#include + + +namespace Configuration { + +using Parameters = QMap; + +Parameters fromFile(const QString& curr_path); +bool toFile(const QString& curr_path, const Parameters& params); + +} diff --git a/util/coreboot-configurator/src/application/MainWindow.cpp b/util/coreboot-configurator/src/application/MainWindow.cpp new file mode 100644 index 0000000000..d51937d161 --- /dev/null +++ b/util/coreboot-configurator/src/application/MainWindow.cpp @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include "AboutDialog.h" +#include "Configuration.h" +#include "MainWindow.h" +#include "NvramToolCli.h" +#include "ToggleSwitch.h" +#include "ui_MainWindow.h" + +static auto s_errorWindowTitle = MainWindow::tr("Error Occured"); +static auto s_nvramErrorMessage = MainWindow::tr("Nvramtool was not able to access cmos settings. Look at documentation for possible causes of errors."); + +QString makeNvramErrorMessage(const QString& error){ + if(!error.trimmed().isEmpty()){ + return QString(MainWindow::tr("%1

    Error message:
    %2")).arg(s_nvramErrorMessage, + Qt::convertFromPlainText(error)); + } + return s_nvramErrorMessage; +} + +namespace YAML { +template <> +struct convert{ + static Node encode(const QString& rhs) { return Node(rhs.toUtf8().data()); } + + static bool decode(const Node& node, QString& rhs) { + if (!node.IsScalar()) + return false; + rhs = QString::fromStdString(node.Scalar()); + return true; + } +}; +} + +static auto s_metadataErrorMessage = MainWindow::tr("Can't load categories metadata file. Check your installation."); +static constexpr char s_sudoProg[] = "/usr/bin/pkexec"; + +MainWindow::MainWindow(QWidget *parent) + : QMainWindow(parent) + , ui(new Ui::MainWindow) +{ + ui->setupUi(this); + + connect(ui->actionAbout, &QAction::triggered, this, [](){ + AboutDialog().exec(); + }); + +#if MOCK + this->setWindowTitle("coreboot configurator "+tr("[MOCKED DATA]")); +#else + this->setWindowTitle("coreboot configurator"); +#endif + this->setWindowIcon(QIcon::fromTheme("coreboot_configurator")); + + QFile catFile(":/config/categories.yaml"); + + if(!catFile.open(QFile::ReadOnly)){ + QMessageBox::critical(this, s_errorWindowTitle, s_metadataErrorMessage); + this->close(); + return; + } + + m_categories = YAML::Load(catFile.readAll()); + + if(m_categories.IsNull() || !m_categories.IsDefined()){ + QMessageBox::critical(this, s_errorWindowTitle, s_metadataErrorMessage); + this->close(); + return; + } + + QShortcut* returnAction = new QShortcut(QKeySequence("Ctrl+Return"), this); + connect(returnAction, &QShortcut::activated, this, &MainWindow::on_saveButton_clicked); + + generateUi(); +} + +MainWindow::~MainWindow() +{ + delete ui; +} + +void MainWindow::pullSettings() +{ + QString error; + m_parameters = NvramToolCli::readParameters(&error); + + if(m_parameters.isEmpty()){ + QMessageBox::critical(this, s_errorWindowTitle, makeNvramErrorMessage(error)); + + /* we need delayed close as initialization error happened before event loop start so we can't stop application properly */ + QTimer::singleShot(0, this, &MainWindow::close); + } +} + +void MainWindow::pushSettings() +{ + QString error; + if(!NvramToolCli::writeParameters(m_parameters, &error)){ + QMessageBox::critical(this, s_errorWindowTitle, makeNvramErrorMessage(error)); + } +} + + +QComboBox* MainWindow::createComboBox(const QString& key) { + auto box = new QComboBox(this); + + auto opts = NvramToolCli::readOptions(key); + + box->addItems(opts); + box->setCurrentText(m_parameters[key]); + + connect(ui->advancedModeCheckBox, &QCheckBox::clicked, this, [box](bool clicked){ + box->setEditable(clicked); + }); + + connect(this, &MainWindow::updateValue, this, [box, this, key](const QString& name){ + if(key!=name || m_parameters[name]==box->currentText()){ + return; + } + box->setCurrentText(m_parameters[name]); + }); + + connect(box, &QComboBox::currentTextChanged, this, [key, this](const QString& value){ + if(value==m_parameters[key]){ + return; + } + m_parameters[key] = value; + emit updateValue(key); + }); + + return box; +} +QString boolToString(bool value){ + return value?QStringLiteral("Enable"):QStringLiteral("Disable"); +} +bool stringToBool(const QString& str){ + return str==QStringLiteral("Enable"); +} +QCheckBox* MainWindow::createCheckBox(const QString& key) { + auto box = new ToggleSwitch(this); + + box->setChecked(stringToBool(m_parameters[key])); + + connect(this, &MainWindow::updateValue, this, [box, this, key](const QString& name){ + + if(key!=name || m_parameters[name]==boolToString(box->isChecked())){ + return; + } + auto newValue = stringToBool(m_parameters[name]); + + box->setChecked(newValue); + }); + + connect(box, &QCheckBox::clicked, this, [key, this](bool checked){ + auto value = boolToString(checked); + if(value==m_parameters[key]){ + return; + } + m_parameters[key] = value; + emit updateValue(key); + }); + + return box; +} + + +QTableWidget *MainWindow::createRawTable() +{ + /* Create Raw values table */ + auto table = new QTableWidget(m_parameters.size(), 2); + table->setHorizontalHeaderLabels({tr("Key"), tr("Value")}); + table->horizontalHeader()->setSectionResizeMode(0,QHeaderView::Stretch); + table->verticalHeader()->hide(); + table->setSelectionBehavior(QTableWidget::SelectRows); + + connect(table, &QTableWidget::cellChanged, this, [table, this](int row, int column){ + if(column != 1 || row >= table->rowCount() || row < 0 ){ + /* Weird state when changed cell is not a value cell */ + return; + } + auto keyItem = table->item(row, 0); + auto valueItem = table->item(row, 1); + + if(keyItem == nullptr || valueItem == nullptr){ + /* Invalid cells */ + return; + } + + if(valueItem->text()==m_parameters[keyItem->text()]){ + return; + } + + m_parameters[keyItem->text()] = valueItem->text(); + emit updateValue(keyItem->text()); + }); + + auto it = m_parameters.begin(); + for(int i = 0; isetFlags(item->flags() ^ Qt::ItemIsEditable); + table->setItem(i,0,item); + + item = new QTableWidgetItem(it.value()); + connect(this, &MainWindow::updateValue, this, [item, it, this](const QString& name){ + if(it.key()!=name || m_parameters[name]==item->text()){ + return; + } + item->setText(m_parameters[name]); + }); + + table->setItem(i,1,item); + } + return table; +} + +void MainWindow::generateUi() +{ + pullSettings(); + + if(!m_categories.IsMap()){ + return; + } + for(const auto& category : m_categories){ + if(!category.second.IsMap()){ + continue; + } + auto name = category.second["displayName"].as(); + + auto layout = new QVBoxLayout; + + auto tabPage = new QWidget(this); + tabPage->setLayout(layout); + + ui->centralTabWidget->addTab(tabPage, name); + + for(const auto& value : category.second){ + if(!value.second.IsMap() || !m_parameters.contains(value.first.as())){ + continue; + } + auto displayName = value.second["displayName"]; + if(!displayName.IsDefined()){ + continue; + } + auto type = value.second["type"]; + if(!type.IsDefined()){ + continue; + } + + auto controlLayout = new QHBoxLayout(); + + auto help = value.second["help"]; + + if(help.IsDefined()){ + auto labelWithTooltip = new QWidget; + labelWithTooltip->setToolTip(help.as()); + labelWithTooltip->setCursor({Qt::WhatsThisCursor}); + labelWithTooltip->setLayout(new QHBoxLayout); + + auto helpButton = new QLabel(); + helpButton->setPixmap(QIcon::fromTheme("help-hint").pixmap(16,16)); + + { + auto layout = qobject_cast(labelWithTooltip->layout()); + layout->addWidget(new QLabel(displayName.as())); + layout->addWidget(helpButton,1); + } + controlLayout->addWidget(labelWithTooltip, 0); + } else { + controlLayout->addWidget(new QLabel(displayName.as()), 0); + } + + controlLayout->addStretch(1); + + QWidget* res = nullptr; + + if(type.as() == QStringLiteral("bool")){ + res = createCheckBox(value.first.as()); + } else if (type.as() == QStringLiteral("enum")){ + res = createComboBox(value.first.as()); + } else { + controlLayout->deleteLater(); + continue; + } + res->setObjectName(value.first.as()); + + controlLayout->addWidget(res, 0); + + layout->addLayout(controlLayout); + } + } + + auto table = createRawTable(); + + connect(ui->advancedModeCheckBox, &QCheckBox::clicked, this, [table,this](bool clicked){ + if(clicked && ui->centralTabWidget->widget(ui->centralTabWidget->count()-1) != table){ + ui->centralTabWidget->addTab(table, tr("Raw")); + } else if(!clicked && ui->centralTabWidget->widget(ui->centralTabWidget->count()-1) == table) { + ui->centralTabWidget->removeTab(ui->centralTabWidget->count()-1); + } + }); +} + +void MainWindow::askForReboot() +{ + QMessageBox rebootDialog(QMessageBox::Question, + tr("Reboot"), + tr("Changes are saved. Do you want to reboot to apply changes?")); + + auto nowButton = rebootDialog.addButton(tr("Reboot now"), QMessageBox::AcceptRole); + rebootDialog.addButton(tr("Reboot later"), QMessageBox::RejectRole); + + rebootDialog.exec(); + if(rebootDialog.clickedButton()==nowButton){ + QProcess::startDetached(s_sudoProg, {"/usr/bin/systemctl", "reboot"}); + this->close(); + } +} + +void MainWindow::readSettings(const QString &fileName) +{ + if(fileName.isEmpty()){ + return; + } + + auto configValues = Configuration::fromFile(fileName); + + for(auto it = configValues.begin(); it != configValues.end(); ++it){ + if(!m_parameters.contains(it.key())){ + continue; + } + m_parameters[it.key()]=it.value(); + emit updateValue(it.key()); + } +} + +void MainWindow::writeSettings(const QString &fileName) +{ + if(fileName.isEmpty()){ + return; + } + if(!Configuration::toFile(fileName, m_parameters)){ + QMessageBox::critical(this, tr("Error Occured"), tr("Can't open file to write")); + this->close(); + } +} + + +void MainWindow::on_actionSave_triggered() +{ + auto filename = QFileDialog::getSaveFileName(this, + tr("Select File To Save"), + QDir::homePath(), + tr("Coreboot Configuration Files")+"(*.cfg)"); + writeSettings(filename); +} + + +void MainWindow::on_actionLoad_triggered() +{ + auto filename = QFileDialog::getOpenFileName(this, + tr("Select File To Load"), + QDir::homePath(), + tr("Coreboot Configuration Files")+"(*.cfg)"); + + readSettings(filename); +} + + +void MainWindow::on_saveButton_clicked() +{ + ui->centralwidget->setEnabled(false); + ui->menubar->setEnabled(false); + + pushSettings(); + + askForReboot(); + + ui->centralwidget->setEnabled(true); + ui->menubar->setEnabled(true); +} diff --git a/util/coreboot-configurator/src/application/MainWindow.h b/util/coreboot-configurator/src/application/MainWindow.h new file mode 100644 index 0000000000..bf317a814f --- /dev/null +++ b/util/coreboot-configurator/src/application/MainWindow.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +QT_BEGIN_NAMESPACE +namespace Ui { class MainWindow; } +QT_END_NAMESPACE + +class MainWindow : public QMainWindow +{ + Q_OBJECT + +public: + MainWindow(QWidget *parent = nullptr); + ~MainWindow(); + +signals: + void updateValue(const QString& key); + +private slots: + void on_actionSave_triggered(void); + + void on_actionLoad_triggered(void); + + void on_saveButton_clicked(void); + +private: + void pullSettings(void); + void pushSettings(void); + + void generateUi(void); + void askForReboot(void); + + void readSettings(const QString& fileName); + void writeSettings(const QString& fileName); + + Configuration::Parameters m_parameters; + YAML::Node m_categories; + + Ui::MainWindow *ui; + + QComboBox *createComboBox(const QString &key); + QCheckBox *createCheckBox(const QString &key); + + QTableWidget *createRawTable(); +}; diff --git a/util/coreboot-configurator/src/application/MainWindow.ui b/util/coreboot-configurator/src/application/MainWindow.ui new file mode 100644 index 0000000000..0f59d80585 --- /dev/null +++ b/util/coreboot-configurator/src/application/MainWindow.ui @@ -0,0 +1,118 @@ + + + MainWindow + + + + 0 + 0 + 600 + 400 + + + + + 0 + 0 + + + + + 600 + 400 + + + + + 600 + 400 + + + + coreboot configurator + + + + + + + + + + + + Advanced mode + + + + + + + Qt::Horizontal + + + + 40 + 20 + + + + + + + + Save + + + + + + + + + + + + + + 0 + 0 + 600 + 25 + + + + + File + + + + + + + Help + + + + + + + + + Save to File... + + + + + Load from File... + + + + + About... + + + + + + diff --git a/util/coreboot-configurator/src/application/NvramToolCli.cpp b/util/coreboot-configurator/src/application/NvramToolCli.cpp new file mode 100644 index 0000000000..da844a043b --- /dev/null +++ b/util/coreboot-configurator/src/application/NvramToolCli.cpp @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "NvramToolCli.h" +#include "Util.h" + +static constexpr char s_sudoProg[] = "/usr/bin/pkexec"; +static constexpr char s_nvramToolProg[] = "/usr/sbin/nvramtool"; + +#if MOCK + +QMap NvramToolCli::readParameters(QString *error) { + return QMap({ + {"boot_option","Normal"}, + {"reboot_counter","0x0"}, + {"debug_level","Spew"}, + {"vtd","Enable"}, + {"power_profile","Performance"}, + {"wireless","Enable"}, + {"webcam","Enable"}, + {"microphone","Enable"}, + {"legacy_8254_timer","Enable"}, + {"usb_always_on","Disable"}, + {"kbl_timeout","Never"}, + {"fn_ctrl_swap","Enable"}, + {"max_charge","100%"}, + {"power_on_after_fail","Disable"}, + {"fn_lock_state","0x2"}, + {"trackpad_state","0x40"}, + {"kbl_brightness","0xc4"}, + {"kbl_state","0x22"} + }); +} + +QStringList NvramToolCli::readOptions(const QString ¶meter, QString *error){ + return (parameter=="power_profile")? + QStringList{ + "Power Saver","Balanced","Performance" + } : QStringList{}; +} + +#else + +QMap NvramToolCli::readParameters(QString *error) +{ + QProcess nvramtoolProcess; + nvramtoolProcess.start(s_sudoProg, {s_nvramToolProg, "-a"}); + + nvramtoolProcess.waitForFinished(); + + if(error) *error = nvramtoolProcess.readAllStandardError(); + + if(nvramtoolProcess.exitCode() != 0){ + return {}; + } + + return Util::parseParameters(nvramtoolProcess); +} + +QStringList NvramToolCli::readOptions(const QString ¶meter, QString *error) +{ + QStringList result; + + QProcess nvramtoolProcess; + nvramtoolProcess.start(s_sudoProg, {s_nvramToolProg, "-e", parameter}); + nvramtoolProcess.waitForFinished(); + + if(error) *error = nvramtoolProcess.readAllStandardError(); + + while (nvramtoolProcess.canReadLine()) { + result.append(nvramtoolProcess.readLine().trimmed()); + } + + return result; +} +#endif + +bool NvramToolCli::writeParameters(const QMap ¶meters, QString *error) +{ + +#if MOCK + QTextStream outStream(stdout); +#else + QProcess nvramtoolProcess; + nvramtoolProcess.start(s_sudoProg, {s_nvramToolProg, "-i"}); + nvramtoolProcess.waitForStarted(); + QTextStream outStream(&nvramtoolProcess); +#endif + for(auto it = parameters.begin(); it != parameters.end(); ++it){ + outStream << it.key() << " = " << it.value() << "\n"; + } + + outStream.flush(); +#if MOCK + return true; +#else + nvramtoolProcess.closeWriteChannel(); + nvramtoolProcess.waitForFinished(); + + if(error){ + *error = nvramtoolProcess.readAllStandardError(); + } + + return nvramtoolProcess.exitCode()==0; +#endif +} + + + +QString NvramToolCli::version() +{ + QProcess nvramtoolProcess; + nvramtoolProcess.start(s_nvramToolProg, {"-v"}); + + nvramtoolProcess.waitForFinished(); + + return nvramtoolProcess.readAll(); +} diff --git a/util/coreboot-configurator/src/application/NvramToolCli.h b/util/coreboot-configurator/src/application/NvramToolCli.h new file mode 100644 index 0000000000..3bb5d0a6ea --- /dev/null +++ b/util/coreboot-configurator/src/application/NvramToolCli.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include +#include +#include + +#include "Configuration.h" + +/* + * Namespace for convinient functions to work with nvramtool CLI utility + */ +namespace NvramToolCli { + +Configuration::Parameters readParameters(QString* error = nullptr); +QStringList readOptions(const QString& parameter, QString* error = nullptr); +bool writeParameters(const Configuration::Parameters& parameters, QString* error = nullptr); +QString version(); + +} diff --git a/util/coreboot-configurator/src/application/ToggleSwitch.cpp b/util/coreboot-configurator/src/application/ToggleSwitch.cpp new file mode 100644 index 0000000000..b0a399e01c --- /dev/null +++ b/util/coreboot-configurator/src/application/ToggleSwitch.cpp @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "ToggleSwitch.h" +#include "ToggleSwitch.svg.h" + +const QByteArray ToggleSwitch::s_toggleOffSvgContent = ToggleSwitchSVG::s_toggledOffContent; +const QByteArray ToggleSwitch::s_toggleOnSvgContent = ToggleSwitchSVG::s_toggledOnContent; +const int ToggleSwitch::s_colorPosInToggleOn = ToggleSwitch::s_toggleOnSvgContent.indexOf("#1a73e8"); + +ToggleSwitch::ToggleSwitch(QWidget *parent) : QCheckBox(parent){ + + setFixedWidth(50); + setFixedHeight(width()/2); + + m_toggleOnSvgContentColored = s_toggleOnSvgContent; +} + +void ToggleSwitch::paintEvent(QPaintEvent *event){ + QPainter p(this); + + if(isChecked()){ + auto accent = palette().highlight().color(); + m_toggleOnSvgContentColored = m_toggleOnSvgContentColored.replace(s_colorPosInToggleOn, 7, accent.name().toLatin1()); + + m_svgr.load(m_toggleOnSvgContentColored); + } else { + m_svgr.load(s_toggleOffSvgContent); + } + + m_svgr.render(&p, this->rect()); + p.end(); +} diff --git a/util/coreboot-configurator/src/application/ToggleSwitch.h b/util/coreboot-configurator/src/application/ToggleSwitch.h new file mode 100644 index 0000000000..191dc5ef96 --- /dev/null +++ b/util/coreboot-configurator/src/application/ToggleSwitch.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include +#include +#include +#include + + +/* + * The ToggleSwitch class represents Toggle Switch widget based on QCheckBox and toggles svg with colorscheme support + */ +class ToggleSwitch : public QCheckBox { + Q_OBJECT +public: + explicit ToggleSwitch(QWidget* parent = nullptr); + +private: + QSvgRenderer m_svgr; + + static const QByteArray s_toggleOnSvgContent; + static const QByteArray s_toggleOffSvgContent; + static const int s_colorPosInToggleOn; + + QByteArray m_toggleOnSvgContentColored; + + /* QWidget interface */ +protected: + void paintEvent(QPaintEvent *event) override; + + /* QAbstractButton interface */ +protected: + bool hitButton(const QPoint &pos) const override + { + /* needs to be clickable on */ + return rect().contains(pos); + } +}; diff --git a/util/coreboot-configurator/src/application/ToggleSwitch.svg.h b/util/coreboot-configurator/src/application/ToggleSwitch.svg.h new file mode 100644 index 0000000000..4aeb12b122 --- /dev/null +++ b/util/coreboot-configurator/src/application/ToggleSwitch.svg.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +/* Embed SVG files into code as debian packages does weird things when svgs are included as qrc */ +namespace ToggleSwitchSVG { +static constexpr char s_toggledOnContent[] = + "\n" + "\n" + " \n" + " \n" + " \n" + " image/svg+xml\n" + " \n" + " \n" + " \n" + " \n" + " \n" + " \n" + " \n" + " \n" + "\n"; +static constexpr char s_toggledOffContent[] = + "\n" + " \n" + " \n" + ""; +} diff --git a/util/coreboot-configurator/src/application/Util.h b/util/coreboot-configurator/src/application/Util.h new file mode 100644 index 0000000000..55553f2981 --- /dev/null +++ b/util/coreboot-configurator/src/application/Util.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#pragma once + +#include +#include +#include + +namespace Util { + inline QMap parseParameters(QIODevice& dev){ + QString curr_line; + QMap result; + + while (!dev.atEnd()) { + curr_line = dev.readLine().trimmed(); + + auto split = curr_line.split('='); + if(split.size()!=2){ + continue; + } + + result.insert(split[0].trimmed(), split[1].trimmed()); + } + return result; + } +} diff --git a/util/coreboot-configurator/src/application/lang.qrc b/util/coreboot-configurator/src/application/lang.qrc new file mode 100644 index 0000000000..e25d9df240 --- /dev/null +++ b/util/coreboot-configurator/src/application/lang.qrc @@ -0,0 +1,3 @@ + + + diff --git a/util/coreboot-configurator/src/application/main.cpp b/util/coreboot-configurator/src/application/main.cpp new file mode 100644 index 0000000000..94b10d9fff --- /dev/null +++ b/util/coreboot-configurator/src/application/main.cpp @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "MainWindow.h" + +int main(int argc, char *argv[]) +{ + QApplication a(argc, argv); + + QTranslator translator; + if (translator.load(QLocale(), QLatin1String("corebootconfigurator"), QLatin1String("_"), QLatin1String(":/lang/i18n"))){ + a.installTranslator(&translator); + } + + MainWindow w; + w.show(); + return a.exec(); +} diff --git a/util/coreboot-configurator/src/application/meson.build b/util/coreboot-configurator/src/application/meson.build new file mode 100644 index 0000000000..cb9b50e8d1 --- /dev/null +++ b/util/coreboot-configurator/src/application/meson.build @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Documentation: https://mesonbuild.com/Qt5-module.html +qt5 = import('qt5') +qt5_dep = dependency('qt5', modules : ['Core', 'Widgets', 'Svg']) +yamlcpp_dep = dependency('yaml-cpp', version: '>= 0.5.1', required: true) + +# TODO: Translations +# lang_cpp = qt5.compile_translations(qresource: 'lang.qrc') + +generated_files = qt5.preprocess( + moc_headers : ['MainWindow.h', 'AboutDialog.h', 'ToggleSwitch.h'], + ui_files : ['MainWindow.ui', 'AboutDialog.ui'], + dependencies : [qt5_dep], + qresources : ['resources.qrc'], +) + +mock = get_option('mock') + +if mock + add_project_arguments('-DMOCK', language : 'cpp') +endif + +executable('coreboot-configurator', + 'main.cpp', + 'MainWindow.cpp', + 'AboutDialog.cpp', + 'Configuration.cpp', + 'ToggleSwitch.cpp', + 'NvramToolCli.cpp', +# lang_cpp, + generated_files, + dependencies : [qt5_dep, yamlcpp_dep], + install : true +) diff --git a/util/coreboot-configurator/src/application/qrc/categories.yaml b/util/coreboot-configurator/src/application/qrc/categories.yaml new file mode 100644 index 0000000000..21419511fe --- /dev/null +++ b/util/coreboot-configurator/src/application/qrc/categories.yaml @@ -0,0 +1,119 @@ + processor: + displayName: Processor + hyper_threading: + displayName: Hyper-Threading + type: bool + help: Enable or disable Hyper-Threading + vtd: + displayName: Intel VT-d + type: bool + help: Enable or disable Intel VT-d (virtualisation) + power_profile: + displayName: Power Profile + type: enum + help: Select whether to maximise performance, battery life or both + me_state: + displayName: Intel Management Engine + type: bool + help: Enable or disable the Intel Management Engine + + devices: + displayName: Devices + wireless: + displayName: Wireless + type: bool + help: Enable or disable the built-in wireless card + wlan: + displayName: Wireless + type: bool + help: Enable or disable the built-in wireless card + bluetooth: + displayName: Bluetooth + type: bool + help: Enable or disable the built-in bluetooth + wwan: + displayName: Mobile Network + type: bool + help: Enable or disable the built-in mobile network + ethernet1: + displayName: Ethernet 1 + type: bool + help: Enable or disable the built-in Ethernet Port 1 + ethernet2: + displayName: Ethernet 2 + type: bool + help: Enable or disable the built-in Ethernet Port 2 + ethernet3: + displayName: Ethernet 3 + type: bool + help: Enable or disable the built-in Ethernet Port 3 + webcam: + displayName: Webcam + type: bool + help: Enable or disable the built-in webcam + microphone: + displayName: Microphone + type: bool + help: Enable or disable the built-in microphone + legacy_8254_timer: + displayName: Clock Gating + type: bool + help: Enable or disable the legacy 8254 timer. Reduces power consumption when enabled but must be disabled for certain distributions such as Qubes + usb_always_on: + displayName: USB Always On + type: bool + help: Allow the USB ports to provide power to connected devices when the computer is suspended + touchpad: + displayName: Touchpad + type: bool + help: Enable or disable the built-in touchpad + trackpoint: + displayName: Trackpoint + type: bool + help: Enable or disable the built-in trackpoint + sata_mode: + displayName: SATA Mode + type: enum + help: Set the mode of the SATA controller from AHCI or Compatible + thunderbolt: + displayName: Thunderbolt + type: bool + help: Enable or disable Thunderbolt functionality + + system: + displayName: System + kbl_timeout: + displayName: Keyboard Backlight Timeout + type: enum + help: Adjust the amout of time before the keyboard backlight turns off when un-used + fn_ctrl_swap: + displayName: Fn Ctrl Reverse + type: bool + help: Swap the functions of the [Fn] and [Ctrl] keys + max_charge: + displayName: Max Charge + type: enum + help: Set the maximum level the battery will charge to + fan_mode: + displayName: Fan Mode + type: enum + help: Adjust the fan curve to priotise performance or noise levels + f1_to_f12_as_primary: + displayName: Function Lock + type: bool + help: Make the F-keys behave as if you are holding down the Fn key + + advanced: + displayName: Advanced + boot_option: + displayName: Boot Options + type: enum + help: Change the boot device in the event of a failed boot + debug_level: + displayName: Debug Level + type: enum + help: Set the verbosity of the debug output + power_on_after_fail: + displayName: Power on Behaviour + type: enum + help: Select whether to power on in the event of a power failure diff --git a/util/coreboot-configurator/src/application/qrc/star.svg b/util/coreboot-configurator/src/application/qrc/star.svg new file mode 100644 index 0000000000..3bb9802ff5 --- /dev/null +++ b/util/coreboot-configurator/src/application/qrc/star.svg @@ -0,0 +1,391 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/util/coreboot-configurator/src/application/qrc/toggle-off.svg b/util/coreboot-configurator/src/application/qrc/toggle-off.svg new file mode 100644 index 0000000000..504ea58c5f --- /dev/null +++ b/util/coreboot-configurator/src/application/qrc/toggle-off.svg @@ -0,0 +1,4 @@ + + + + diff --git a/util/coreboot-configurator/src/application/qrc/toggle-on.svg b/util/coreboot-configurator/src/application/qrc/toggle-on.svg new file mode 100644 index 0000000000..0b8e61848c --- /dev/null +++ b/util/coreboot-configurator/src/application/qrc/toggle-on.svg @@ -0,0 +1,65 @@ + + + + + + image/svg+xml + + + + + + + + + diff --git a/util/coreboot-configurator/src/application/resources.qrc b/util/coreboot-configurator/src/application/resources.qrc new file mode 100644 index 0000000000..06264d63d1 --- /dev/null +++ b/util/coreboot-configurator/src/application/resources.qrc @@ -0,0 +1,12 @@ + + + qrc/toggle-off.svg + qrc/toggle-on.svg + + + qrc/categories.yaml + + + qrc/star.svg + + diff --git a/util/coreboot-configurator/src/meson.build b/util/coreboot-configurator/src/meson.build new file mode 100644 index 0000000000..cb73f0818b --- /dev/null +++ b/util/coreboot-configurator/src/meson.build @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdir('application') +subdir('resources') diff --git a/util/coreboot-configurator/src/resources/coreboot-configurator.desktop b/util/coreboot-configurator/src/resources/coreboot-configurator.desktop new file mode 100644 index 0000000000..5f17d000e4 --- /dev/null +++ b/util/coreboot-configurator/src/resources/coreboot-configurator.desktop @@ -0,0 +1,9 @@ +[Desktop Entry] +Name=coreboot configurator +StartupWMCLass=coreboot_configurator +Exec=/usr/bin/coreboot-configurator +Icon=coreboot-configurator.png +Type=Application +Categories=Settings;System +Comment=A graphical interface to set options on devices with coreboot firmware. +Keywords=coreboot;BIOS;Firmware;uefi; diff --git a/util/coreboot-configurator/src/resources/coreboot_configurator.svg b/util/coreboot-configurator/src/resources/coreboot_configurator.svg new file mode 100644 index 0000000000..33a7229891 --- /dev/null +++ b/util/coreboot-configurator/src/resources/coreboot_configurator.svg @@ -0,0 +1,748 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + diff --git a/util/coreboot-configurator/src/resources/meson.build b/util/coreboot-configurator/src/resources/meson.build new file mode 100644 index 0000000000..12270ab14e --- /dev/null +++ b/util/coreboot-configurator/src/resources/meson.build @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Polkit Files +polkit_dir = join_paths(get_option('datadir'), 'polkit-1', 'actions') +polkit_sources = [ + 'org.coreboot.nvramtool.policy', + 'org.coreboot.reboot.policy', +] + +install_data(polkit_sources, + install_dir: polkit_dir) + +# Desktop Entry +desktop_dir = join_paths(get_option('datadir'), 'applications') +desktop_sources = [ + 'coreboot-configurator.desktop', +] + +install_data(desktop_sources, + install_dir: desktop_dir) + +# Icon +inkscape = find_program('inkscape') +icon_dir = join_paths(get_option('datadir'),'icons', 'hicolor') +foreach size: get_option('sizes') + target_temp_name = '@0@'.format(size) + dpi=size.to_int() * 2 + png = configure_file( + input: 'coreboot_configurator.svg', + output: target_temp_name + '.png', + command: [ + inkscape, + '--export-height=@0@'.format(size), + '--export-width=@0@'.format(size), + '--export-png=@OUTPUT@', + '@INPUT@', + ] + ) + + install_data(png, + rename: meson.project_name() + '.png', + install_dir: join_paths(icon_dir, '@0@x@1@'.format(size, size), 'apps')) +endforeach diff --git a/util/coreboot-configurator/src/resources/org.coreboot.nvramtool.policy b/util/coreboot-configurator/src/resources/org.coreboot.nvramtool.policy new file mode 100644 index 0000000000..c95bc8b9a3 --- /dev/null +++ b/util/coreboot-configurator/src/resources/org.coreboot.nvramtool.policy @@ -0,0 +1,13 @@ + + + + + Authentication is required to read and write to coreboot settings. + + auth_admin_keep + + /usr/sbin/nvramtool + + diff --git a/util/coreboot-configurator/src/resources/org.coreboot.reboot.policy b/util/coreboot-configurator/src/resources/org.coreboot.reboot.policy new file mode 100644 index 0000000000..5364c8c22c --- /dev/null +++ b/util/coreboot-configurator/src/resources/org.coreboot.reboot.policy @@ -0,0 +1,12 @@ + + + + + + yes + + /usr/sbin/reboot + + diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 34fb244425..cb552dd084 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -27,9 +27,6 @@ ifeq ($(SKIP_CLANG),) bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) endif -build_make: - bash ./buildgcc -P make $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) - build_nasm: bash ./buildgcc -P nasm $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) @@ -68,8 +65,9 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_clang all \ - build-i386 build-x64 build-arm \ - build-aarch64 build-riscv build-ppc64 build-nds32le build-nasm \ - clean distclean clean_tempfiles +.PHONY: all build_gcc build_iasl build_clang build_nasm \ + clean distclean clean_tempfiles \ + build-i386 build-x64 build-arm build-aarch64 \ + build-riscv build-ppc64 build-nds32le + .NOTPARALLEL: diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6c1a7a59dc..6b7558f2bd 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -36,12 +36,11 @@ GMP_VERSION=6.2.1 MPFR_VERSION=4.1.0 MPC_VERSION=1.2.1 GCC_VERSION=11.2.0 -GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.37 -IASL_VERSION=20210331 +IASL_VERSION=20211217 # CLANG version number -CLANG_VERSION=12.0.0 -CMAKE_VERSION=3.20.3 +CLANG_VERSION=13.0.1 +CMAKE_VERSION=3.22.2 NASM_VERSION=2.15.05 # GCC toolchain archive locations @@ -122,7 +121,7 @@ normalize_dirs() mkdir -p "$DESTDIR$TARGETDIR/lib" test -d "$DESTDIR$TARGETDIR/lib32" && mv "$DESTDIR$TARGETDIR"/lib32/* "$DESTDIR$TARGETDIR/lib" test -d "$DESTDIR$TARGETDIR/lib64" && mv "$DESTDIR$TARGETDIR"/lib64/* "$DESTDIR$TARGETDIR/lib" - rmdir -p "$DESTDIR$TARGETDIR/lib32" "$DESTDIR$TARGETDIR/lib64" + rm -rf "$DESTDIR$TARGETDIR/lib32" "$DESTDIR$TARGETDIR/lib64" perl -pi -e "s,/lib32,/lib," "$DESTDIR$TARGETDIR"/lib/*.la perl -pi -e "s,/lib64,/lib," "$DESTDIR$TARGETDIR"/lib/*.la @@ -835,8 +834,6 @@ build_CMAKE() { # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed - - normalize_dirs } build_NASM() { @@ -852,7 +849,6 @@ build_NASM() { print_supported() { case "$PRINTSUPPORTED" in - AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; BINUTILS|binutils) printf "%s\n" "$BINUTILS_VERSION";; CLANG|clang) printf "%s\n" "$CLANG_VERSION";; GCC|gcc) printf "%s\n" "$GCC_VERSION";; diff --git a/util/crossgcc/patches/acpica-unix2-20210331_iasl.patch b/util/crossgcc/patches/acpica-unix2-20211217_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20210331_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20211217_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum deleted file mode 100644 index 1aa77c238e..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -1a4006727962daf63a181c853695ca69bdf7d541 tarballs/acpica-unix2-20210331.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20211217.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20211217.tar.gz.cksum new file mode 100644 index 0000000000..dd961e0bca --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20211217.tar.gz.cksum @@ -0,0 +1 @@ +4337413d206a169a47d706fa2e5bdc9bc0855c04 tarballs/acpica-unix2-20211217.tar.gz diff --git a/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 42be5d9f3d..0000000000 --- a/util/crossgcc/sum/clang-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -51250856f368acef5ab335a16f994bf29ad3d115 tarballs/clang-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..e7393a4e66 --- /dev/null +++ b/util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +9cdc305550fbd27d52d023e8506c50c41e97b7fa tarballs/clang-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 63285948e2..0000000000 --- a/util/crossgcc/sum/clang-tools-extra-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5fe54db45be35b8f77acc32f08e01912f8e8b915 tarballs/clang-tools-extra-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..80c882aa75 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +ee28b71609e57e677205f44076e450fe5f577a22 tarballs/clang-tools-extra-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum deleted file mode 100644 index 2ac43e857d..0000000000 --- a/util/crossgcc/sum/cmake-3.20.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -96e498c4d1ac238b6852b1113102bf2301bb88d8 tarballs/cmake-3.20.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.22.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.22.2.tar.gz.cksum new file mode 100644 index 0000000000..c72aef2e90 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.22.2.tar.gz.cksum @@ -0,0 +1 @@ +672ec927c218a3f4ece5929d7b225fce6bc38187 tarballs/cmake-3.22.2.tar.gz diff --git a/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum deleted file mode 100644 index 650f8e5356..0000000000 --- a/util/crossgcc/sum/compiler-rt-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7b02a455fbc6fe395da8d5411072acc04d669d94 tarballs/compiler-rt-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..51cf82f233 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +68e9e2f569ccfe0af9f5df61ec74808688198946 tarballs/compiler-rt-13.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum deleted file mode 100644 index e4f3aa3893..0000000000 --- a/util/crossgcc/sum/llvm-12.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -dbc1cf6aa2dbdeccd7ad26c9215b56963a5686d3 tarballs/llvm-12.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum new file mode 100644 index 0000000000..6f343622c3 --- /dev/null +++ b/util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum @@ -0,0 +1 @@ +8e50e3e47b6a14a0848862c574fb0007db212482 tarballs/llvm-13.0.1.src.tar.xz diff --git a/util/docker/Makefile b/util/docker/Makefile index 87e21be8b1..cbe34f9291 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -24,7 +24,7 @@ export DOCKER_COMMIT?=$(shell git log -n 1 --pretty=%h) export DOCKER_CCACHE?=$(HOME)/.ccache # SDK architecture -export COREBOOT_CROSSGCC_PARAM?=all_without_gdb +export COREBOOT_CROSSGCC_PARAM?=all UID ?= $(shell id -u) GID ?= $(shell id -g) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 64854a4132..acd82429b8 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -21,6 +21,7 @@ RUN \ apt-get -qqy install \ bc \ bison \ + bsdextrautils \ bzip2 \ ccache \ cmake \ @@ -39,6 +40,7 @@ RUN \ gnat \ golang \ graphviz \ + lcov \ libcrypto++-dev \ libcurl4 \ libcurl4-openssl-dev \ diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index 9890339d46..45627a94ed 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -11,6 +11,7 @@ $(VBOOT_FUTILITY): | check-openssl-presence CC="$(HOSTCC)" \ PKG_CONFIG="$(HOSTPKGCONFIG)" \ V=$(V) \ + USE_FLASHROM=0 \ $@ .PHONY: check-openssl-presence diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index e8d818c021..83d19b892e 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -2,42 +2,26 @@ # # SPDX-License-Identifier: GPL-2.0-only -PROGRAM = ifdtool - CC ?= gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include -CFLAGS += -I../cbfstool/flashmap -CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h -LDFLAGS = -OBJS = ifdtool.o -OBJS += fmap.o -OBJS += kv_pair.o -OBJS += valstr.o +HOSTCC ?= $(CC) +HOSTCFLAGS ?= $(CFLAGS) +top := ../.. +objutil := .. +include Makefile.inc -all: dep $(PROGRAM) +PROGRAM=$(objutil)/ifdtool/ifdtool -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) +all: $(PROGRAM) clean: rm -f $(PROGRAM) *.o *~ .dependencies distclean: clean -dep: - @$(CC) $(CFLAGS) -MM *.c > .dependencies - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -%.o: ../cbfstool/flashmap/%.c - $(CC) $(CFLAGS) -c -o $@ $< - install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/bin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin -.PHONY: all clean distclean dep +.PHONY: all clean distclean install diff --git a/util/ifdtool/Makefile.inc b/util/ifdtool/Makefile.inc index b2d8f87804..eb3a700d43 100644 --- a/util/ifdtool/Makefile.inc +++ b/util/ifdtool/Makefile.inc @@ -6,6 +6,7 @@ IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h +IFDTOOLCFLAGS += -D_DEFAULT_SOURCE # for endianness converting functions $(objutil)/ifdtool/%.o: $(top)/util/ifdtool/%.c $(HOSTCC) $(IFDTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ca5d3b8d21..20c4ed417a 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -40,10 +40,17 @@ static const struct region_name region_names[MAX_REGIONS] = { { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, - { "Reserved", "res1", "flashregion_5_reserved.bin", NULL }, - { "Reserved", "res2", "flashregion_6_reserved.bin", NULL }, - { "Reserved", "res3", "flashregion_7_reserved.bin", NULL }, + { "Device Exp1", "devexp", "flashregion_5_device_exp.bin", "SI_DEVICEEXT" }, + { "Secondary BIOS", "bios2", "flashregion_6_bios2.bin", "SI_BIOS2" }, + { "Reserved", "res7", "flashregion_7_reserved.bin", NULL }, { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, + { "Device Exp2", "devexp2", "flashregion_9_device_exp.bin", "SI_DEVICEEXT2" }, + { "IE", "ie", "flashregion_10_ie.bin", "SI_IE" }, + { "10GbE_0", "10gbe_0", "flashregion_11_10gbe0.bin", "SI_10GBE0" }, + { "10GbE_1", "10gbe_1", "flashregion_12_10gbe1.bin", "SI_10GBE1" }, + { "Reserved", "res13", "flashregion_13_reserved.bin", NULL }, + { "Reserved", "res14", "flashregion_14_reserved.bin", NULL }, + { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT" }, }; /* port from flashrom */ @@ -224,6 +231,7 @@ static enum ich_chipset ifd2_platform_to_chipset(const int pindex) return CHIPSET_300_SERIES_CANNON_POINT; case PLATFORM_TGL: case PLATFORM_ADL: + case PLATFORM_IFD2: return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; case PLATFORM_ICL: return CHIPSET_400_SERIES_ICE_POINT; @@ -253,6 +261,7 @@ static int is_platform_ifd_2(void) PLATFORM_EHL, PLATFORM_ADL, PLATFORM_SKLKBL, + PLATFORM_IFD2, }; unsigned int i; @@ -1178,6 +1187,7 @@ static void lock_descriptor(const char *filename, char *image, int size) case PLATFORM_JSL: case PLATFORM_EHL: case PLATFORM_ADL: + case PLATFORM_IFD2: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1635,6 +1645,7 @@ static void print_usage(const char *name) " ehl - Elkhart Lake\n" " glk - Gemini Lake\n" " icl - Ice Lake\n" + " ifd2 - IFDv2 Platform\n" " jsl - Jasper Lake\n" " sklkbl - Sky Lake/Kaby Lake\n" " tgl - Tiger Lake\n" @@ -1642,7 +1653,8 @@ static void print_usage(const char *name) " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - " is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" + " is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, " + "Device Exp1, EC, Device Exp2, IE, 10GbE_0, 10GbE_1, PTT\n" "\n"); } @@ -1731,16 +1743,26 @@ int main(int argc, char *argv[]) region_type = 2; else if (!strcasecmp("GbE", region_type_string)) region_type = 3; - else if (!strcasecmp("Platform", region_type_string)) + else if (!strcasecmp("Platform Data", region_type_string)) region_type = 4; - else if (!strcasecmp("res1", region_type_string)) + else if (!strcasecmp("Device Exp1", region_type_string)) region_type = 5; - else if (!strcasecmp("res2", region_type_string)) + else if (!strcasecmp("Secondary BIOS", region_type_string)) region_type = 6; - else if (!strcasecmp("res3", region_type_string)) + else if (!strcasecmp("Reserved", region_type_string)) region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; + else if (!strcasecmp("Device Exp2", region_type_string)) + region_type = 9; + else if (!strcasecmp("IE", region_type_string)) + region_type = 10; + else if (!strcasecmp("10GbE_0", region_type_string)) + region_type = 11; + else if (!strcasecmp("10GbE_1", region_type_string)) + region_type = 12; + else if (!strcasecmp("PTT", region_type_string)) + region_type = 15; if (region_type == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); @@ -1891,6 +1913,8 @@ int main(int argc, char *argv[]) platform = PLATFORM_TGL; } else if (!strcmp(optarg, "adl")) { platform = PLATFORM_ADL; + } else if (!strcmp(optarg, "ifd2")) { + platform = PLATFORM_IFD2; } else { fprintf(stderr, "Unknown platform: %s\n", optarg); exit(EXIT_FAILURE); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 4f63e20c44..15e207d9aa 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -58,6 +58,7 @@ enum platform { PLATFORM_SKLKBL, PLATFORM_TGL, PLATFORM_ADL, + PLATFORM_IFD2, }; #define LAYOUT_LINELEN 80 @@ -117,7 +118,7 @@ typedef struct { } __attribute__((packed)) fdbar_t; // regions -#define MAX_REGIONS 9 +#define MAX_REGIONS 16 #define MAX_REGIONS_OLD 5 enum flash_regions { @@ -126,7 +127,14 @@ enum flash_regions { REGION_ME, REGION_GBE, REGION_PDR, + REGION_DEV_EXP1, + REGION_BIOS2, REGION_EC = 8, + REGION_DEV_EXP2, + REGION_IE, + REGION_10GB_0, + REGION_10GB_1, + REGION_PTT = 15, }; typedef struct { diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 9105d3b82b..4216189e0e 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -346,7 +346,7 @@ static void dump_bootguard_info(void) if (ME_major_ver && (ME_major_ver < 9 || (ME_major_ver == 9 && ME_minor_ver < 5))) { - printf(CGRN "Your system isn't BootGuard ready.\n" + printf(CGRN "Your system isn't Boot Guard ready.\n" "You can flash other firmware!\n" RESET); rehide_me(); return; @@ -354,7 +354,7 @@ static void dump_bootguard_info(void) if (pci_read_long(dev, 0x40) & 0x10) printf(CYEL "Your southbridge configuration is insecure!!\n" - "BootGuard keys can be overwritten or wiped, or you are " + "Boot Guard keys can be overwritten or wiped, or you are " "in developer mode.\n" RESET); rehide_me(); @@ -380,10 +380,10 @@ static void dump_bootguard_info(void) return; } - printf("BootGuard MSR Output : 0x%" PRIx64 "\n", btg.raw); + printf("Boot Guard MSR Output : 0x%" PRIx64 "\n", btg.raw); if (!btg.btg_capability) { - printf(CGRN "Your system isn't BootGuard ready.\n" + printf(CGRN "Your system isn't Boot Guard ready.\n" "You can flash other firmware!\n" RESET); return; } @@ -412,7 +412,7 @@ static void dump_bootguard_info(void) "Cache-As-RAM.\nIt might be possible to flash other firmware.\n" RESET); } else { - printf(CGRN "Your system is BootGuard ready but verified boot is disabled.\n" + printf(CGRN "Your system is Boot Guard ready but verified boot is disabled.\n" "You can flash other firmware!\n" RESET); } } diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c index 2080e3bab5..054c74fdb5 100644 --- a/util/inteltool/ahci.c +++ b/util/inteltool/ahci.c @@ -93,7 +93,7 @@ int print_ahci(struct pci_dev *ahci) size_t ahci_registers_size = 0, i; size_t ahci_cfg_registers_size = 0; const io_register_t *ahci_cfg_registers; - size_t ahci_sir_offset = 0; + size_t ahci_sir_index_offset = 0, ahci_sir_data_offset; size_t ahci_sir_registers_size = 0; const io_register_t *ahci_sir_registers; @@ -107,7 +107,7 @@ int print_ahci(struct pci_dev *ahci) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA: ahci_registers_size = 0x800; - ahci_sir_offset = 0xa0; + ahci_sir_index_offset = 0xa0; ahci_cfg_registers = sunrise_ahci_cfg_registers; ahci_cfg_registers_size = ARRAY_SIZE(sunrise_ahci_cfg_registers); ahci_sir_registers = sunrise_ahci_sir_registers; @@ -117,6 +117,8 @@ int print_ahci(struct pci_dev *ahci) ahci_registers_size = 0x400; } + ahci_sir_data_offset = ahci_sir_index_offset + 4; + printf("\n============= AHCI Configuration Registers ==============\n\n"); for (i = 0; i < ahci_cfg_registers_size; i++) { switch (ahci_cfg_registers[i].size) { @@ -143,24 +145,24 @@ int print_ahci(struct pci_dev *ahci) printf("\n============= SATA Initialization Registers ==============\n\n"); for (i = 0; i < ahci_sir_registers_size; i++) { - pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr); + pci_write_byte(ahci, ahci_sir_index_offset, ahci_sir_registers[i].addr); switch (ahci_sir_registers[i].size) { case 4: printf("0x%02x: 0x%08x (%s)\n", ahci_sir_registers[i].addr, - pci_read_long(ahci, ahci_sir_offset), + pci_read_long(ahci, ahci_sir_data_offset), ahci_sir_registers[i].name); break; case 2: printf("0x%02x: 0x%04x (%s)\n", ahci_sir_registers[i].addr, - pci_read_word(ahci, ahci_sir_offset), + pci_read_word(ahci, ahci_sir_data_offset), ahci_sir_registers[i].name); break; case 1: printf("0x%02x: 0x%02x (%s)\n", ahci_sir_registers[i].addr, - pci_read_byte(ahci, ahci_sir_offset), + pci_read_byte(ahci, ahci_sir_data_offset), ahci_sir_registers[i].name); break; } diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 53164e1cf9..f21e6c7d76 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -173,7 +173,7 @@ static const io_register_t ich10_gpio_registers[] = { { 0x3C, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, @@ -227,7 +227,7 @@ static const io_register_t pch_gpio_registers[] = { { 0x3c, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, @@ -943,6 +943,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; @@ -1039,6 +1040,11 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: @@ -1076,6 +1082,17 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_Q570: + case PCI_DEVICE_ID_INTEL_Z590: + case PCI_DEVICE_ID_INTEL_H570: + case PCI_DEVICE_ID_INTEL_B560: + case PCI_DEVICE_ID_INTEL_H510: + case PCI_DEVICE_ID_INTEL_WM590: + case PCI_DEVICE_ID_INTEL_QM580: + case PCI_DEVICE_ID_INTEL_HM570: + case PCI_DEVICE_ID_INTEL_C252: + case PCI_DEVICE_ID_INTEL_C256: + case PCI_DEVICE_ID_INTEL_W580: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: print_gpio_groups(sb); return 0; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 7be1d5abf8..4faecf3206 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -17,6 +17,7 @@ #include "gpio_names/icelake.h" #include "gpio_names/lewisburg.h" #include "gpio_names/sunrise.h" +#include "gpio_names/tigerlake.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) @@ -174,6 +175,28 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s *community_count = ARRAY_SIZE(icelake_pch_h_communities); *pad_stepping = 16; return icelake_pch_h_communities; + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: + *community_count = ARRAY_SIZE(tigerlake_pch_lp_communities); + *pad_stepping = 16; + return tigerlake_pch_lp_communities; + case PCI_DEVICE_ID_INTEL_Q570: + case PCI_DEVICE_ID_INTEL_Z590: + case PCI_DEVICE_ID_INTEL_H570: + case PCI_DEVICE_ID_INTEL_B560: + case PCI_DEVICE_ID_INTEL_H510: + case PCI_DEVICE_ID_INTEL_WM590: + case PCI_DEVICE_ID_INTEL_QM580: + case PCI_DEVICE_ID_INTEL_HM570: + case PCI_DEVICE_ID_INTEL_C252: + case PCI_DEVICE_ID_INTEL_C256: + case PCI_DEVICE_ID_INTEL_W580: + *community_count = ARRAY_SIZE(tigerlake_pch_h_communities); + *pad_stepping = 16; + return tigerlake_pch_h_communities; default: return NULL; } diff --git a/util/inteltool/gpio_names/tigerlake.h b/util/inteltool/gpio_names/tigerlake.h new file mode 100644 index 0000000000..095eb45867 --- /dev/null +++ b/util/inteltool/gpio_names/tigerlake.h @@ -0,0 +1,1371 @@ +#ifndef GPIO_NAMES_TIGERLAKE_LP +#define GPIO_NAMES_TIGERLAKE_LP + +#include "gpio_groups.h" + +/* ----------------------------- Tiger Lake LP ----------------------------- */ + +const char *const tigerlake_pch_lp_group_a_names[] = { + "GPP_A0", "ESPI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPP_A1", "ESPI_IO1", "n/a", "n/a", "n/a", "n/a", + "GPP_A2", "ESPI_IO2", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", "n/a", + "GPP_A3", "ESPI_IO3", "SUSACK#", "n/a", "n/a", "n/a", + "GPP_A4", "ESPI_CS#", "n/a", "n/a", "n/a", "n/a", + "GPP_A5", "ESPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPP_A6", "ESPI_RESET#", "n/a", "n/a", "n/a", "n/a", + "GPP_A7", "I2S2_SCLK", "n/a", "n/a", "n/a", "DMIC_CLK_A0", + "GPP_A8", "I2S2_SFRM", "CNV_RF_RESET#", "n/a", "n/a", "DMIC_DATA0", + "GPP_A9", "I2S2_TXD", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", "DMIC_CLK_A1", + "GPP_A10", "I2S2_RXD", "n/a", "n/a", "n/a", "DMIC_DATA1", + "GPP_A11", "PMC_I2C_SDA", "n/a", "I2S3_SCLK", "n/a", "n/a", + "GPP_A12", "SATAXPCIE1", "SATAGP1", "I2S3_SFRM", "n/a", "n/a", + "GPP_A13", "PMC_I2C_SCL", "n/a", "I2S3_TXD", "n/a", "DMIC_CLK_B0", + "GPP_A14", "USB_OC1#", "DDSP_HPD3", "I2S3_RXD", "DISP_MISC3", "DMIC_CLK_B1", + "GPP_A15", "USB_OC2#", "DDSP_HPD4", "I2S4_SCLK", "DISP_MISC4", "n/a", + "GPP_A16", "USB_OC3#", "n/a", "I2S4_SFRM", "n/a", "n/a", + "GPP_A17", "DDSP_HDPC", "DISP_MISCC", "I2S4_TXD", "n/a", "n/a", + "GPP_A18", "DDSP_HPDB", "DISP_MISCB", "I2S4_RXD", "n/a", "n/a", + "GPP_A19", "DDSP_HPD1", "DISP_MISC1", "I2S5_SCLK", "n/a", "n/a", + "GPP_A20", "DDSP_HPD2", "DISP_MISC2", "I2S5_SFRM", "n/a", "n/a", + "GPP_A21", "BKLTEN_SEC", "DDPC_CTRLCLK", "I2S5_TXD", "n/a", "n/a", + "GPP_A22", "BKLTCTL_SEC", "DDPC_CTRLDATA", "I2S5_RXD", "n/a", "n/a", + "GPP_A23", "I2S1_SCLK", "n/a", "n/a", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_a_names) / 6, + .func_count = 6, + .pad_names = tigerlake_pch_lp_group_a_names, +}; + +const char *const tigerlake_pch_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_B6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_B7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_B8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_B9", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_B10", "I2C5_SCL", "ISH_I2C2_SDL", "n/a", + "GPP_B11", "PMCALERT#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "TIME_SYNC1", "GSPI0_CS1#", + "GPP_B15", "GSPI0_CS0#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "GSPI1_CS1#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_b_names, +}; + +const char *const tigerlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_c_names, +}; + +const char *const tigerlake_pch_lp_group_d_names[] = { + "GPP_D0", "ISH_GP0", "BK0", "n/a", "n/a", "SBK0", "n/a", "n/a", + "GPP_D1", "ISH_GP1", "BK1", "n/a", "n/a", "SBK1", "n/a", "n/a", + "GPP_D2", "ISH_GP2", "BK2", "n/a", "n/a", "SBK2", "n/a", "n/a", + "GPP_D3", "ISH_GP3", "BK3", "n/a", "n/a", "SBK3", "n/a", "n/a", + "GPP_D4", "IMGCLKOUT0", "BK4", "n/a", "n/a", "SBK4", "n/a", "n/a", + "GPP_D5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "DDP3_CTRLCLK", "n/a", "TBT_LSX2_TXD", "BSSB_LS2_RX", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "DDP3_CTRLDATA", "n/a", "TBT_LSX2_RXD", "BSSB_LS2_TX", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "DDP4_CTRLCLK", "n/a", "TBT_LSX3_TXD", "BSSB_LS3_RX", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "n/a", "TBT_LSX3_RXD", "BSSB_LS3_TX", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C4_SDA", "n/a", "n/a", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C4_SCL", "n/a", "n/a", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "IMGCLKOUT5", "n/a", "n/a", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D17", "ISH_GP4", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D18", "ISH_GP5", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D19", "I2S_MCLK1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_d_names) / 8, + .func_count = 8, + .pad_names = tigerlake_pch_lp_group_d_names, +}; + +const char *const tigerlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", "n/a", + "GPP_E1", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", "n/a", + "GPP_E2", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", "n/a", "n/a", + "GPP_E6", "n/a", "THC0_SPI1_RST#", "n/a", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", "n/a", "n/a", + "GPP_E8", "n/a", "SATA_LED#", "n/a", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", "n/a", "n/a", + "GPP_E10", "n/a", "THC0_SPI1_CS#", "n/a", "n/a", "n/a", + "GPP_E11", "n/a", "THC0_SPI1_CLK", "n/a", "n/a", "n/a", + "GPP_E12", "n/a", "THC0_SPI1_IO1", "n/a", "n/a", "n/a", + "GPP_E13", "n/a", "THC0_SPI1_IO0", "n/a", "n/a", "n/a", + "GPP_E14", "DDSP_HPDA", "DISP_MISCA", "n/a", "n/a", "n/a", + "GPP_E15", "ISH_GP6", "Reserved", "n/a", "n/a", "n/a", + "GPP_E16", "ISH_GP7", "Reserved", "n/a", "n/a", "n/a", + "GPP_E17", "n/a", "THC0_SPI1_INT#", "n/a", "n/a", "n/a", + "GPP_E18", "DDP1_CTRLCLK", "n/a", "n/a", "TBT_LSX0_TXD", "BSSB_LS0_RX", + "GPP_E19", "DPP1_CTRLDATA", "n/a", "n/a", "TBT_LSX0_RXD", "BSSB_LS0_TX", + "GPP_E20", "DPP2_CTRLCLK", "n/a", "n/a", "TBT_LSX1_TXD", "BSSB_LS1_RX", + "GPP_E21", "DPP2_CTRLDATA", "n/a", "n/a", "TBT_LSX1_RXD", "BSSB_LS1_TX", + "GPP_E22", "DPAA_CTRLCLK", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", + "GPP_E23", "DPPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", + "GPPE_CLK_LOOPBK", "n/a", "THC0_CLK_LOOPBACK", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_e_names) / 6, + .func_count = 6, + .pad_names = tigerlake_pch_lp_group_e_names, +}; + +const char *const tigerlake_pch_lp_group_hvmos_names[] = { + "L_BKLTEN", "L_BKLTEN", + "L_BKLTCTL", "L_BKLTCTL", + "L_VDDEN", "L_VDDEN", + "SYS_PWROK", "SYS_PWROK", + "SYS_RESET#", "SYS_RESET#", + "MLK_RST#", "MLK_RST#", +}; + +const struct gpio_group tigerlake_pch_lp_group_hvmos = { + .display = "------- GPIO Group HVMOS -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_hvmos_names), + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_hvmos_names, +}; + +const char *const tigerlake_pch_lp_group_f_names[] = { + "GPP_F0", "CNV_BRI_DT", "UART0_RTS#", "n/a", + "GPP_F1", "CNV_BRI_RSP", "UART0_RXD", "n/a", + "GPP_F2", "CNV_RGI_DT", "UART0_TXD", "n/a", + "GPP_F3", "CNV_RGI_RSP", "UART0_CTS#", "n/a", + "GPP_F4", "CNV_RF_RESET#", "n/a", "n/a", + "GPP_F5", "n/a", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", + "GPP_F6", "CNV_PA_BLANKING", "n/a", "n/a", + "GPP_F7", "n/a", "n/a", "n/a", + "GPP_F8", "I2S_MCLK2_INOUT", "n/a", "n/a", + "GPP_F9", "Reserved", "n/a", "n/a", + "GPP_F10", "n/a", "n/a", "n/a", + "GPP_F11", "n/a", "n/a", "THC1_SPI2_CLK", + "GPP_F12", "GSXDOUT", "n/a", "THC1_SPI2_IO0", + "GPP_F13", "GSXSLOAD", "n/a", "THC1_SPI2_IO1", + "GPP_F14", "GSXDIN", "n/a", "THC1_SPI2_IO2", + "GPP_F15", "GSXSRESET#", "n/a", "THC1_SPI2_IO3", + "GPP_F16", "GSXCLK", "n/a", "THC1_SPI2_CS#", + "GPP_F17", "n/a", "n/a", "THC1_SPI2_RST#", + "GPP_F18", "n/a", "n/a", "THC1_SPI2_INT#", + "GPP_F19", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_F20", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_F21", "EXT_PWR_GATE2#", "n/a", "n/a", + "GPP_F22", "VNN_CTRL", "n/a", "n/a", + "GPP_F23", "V1P05_CTRL", "n/a", "n/a", + "GPPF_CLK_LOOPBK", "n/a", "THC1_CLK_LOOPBACK", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_f_names, +}; + +const char *const tigerlake_pch_lp_group_h_names[] = { + "GPP_H0", "n/a", "n/a", "n/a", + "GPP_H1", "n/a", "n/a", "n/a", + "GPP_H2", "n/a", "n/a", "n/a", + "GPP_H3", "SX_EXIT_HOLDOFF", "n/a", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "CNV_MFUART2_RXD", "n/a", + "GPP_H9", "I2C4_SCL", "CNV_MFUART2_TXD", "n/a", + "GPP_H10", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_H11", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "DDPB_CTRLCLK", "n/a", "PCIE_LNK_DOWN", + "GPP_H17", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "IMGCLKOUT2", "n/a", "n/a", + "GPP_H22", "IMGCLKOUT3", "n/a", "n/a", + "GPP_H23", "IMGCLKOUT4", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_h_names, +}; + +const char *const tigerlake_pch_lp_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", + "GPP_R2", "HDA_SDO", "I2S0_TXD", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", + "GPP_R4", "HDA_RST#", "n/a", + "GPP_R5", "HDA_SDI1", "I2S1_RXD", + "GPP_R6", "n/a", "I2S1_TXD", + "GPP_R7", "n/a", "I2S1_SFRM", +}; + +const struct gpio_group tigerlake_pch_lp_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_r_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_r_names, +}; + +const char *const tigerlake_pch_lp_group_s_names[] = { + "GPP_S0", "SNDW0_CLK", "N/A", + "GPP_S1", "SNDW0_DATA", "N/A", + "GPP_S2", "SNDW1_CLK", "DMIC_CLK_B0", + "GPP_S3", "SNDW1_DATA", "DMIC_CLK_B1", + "GPP_S4", "SNDW2_CLK#", "DMIC_CLK_A1", + "GPP_S5", "SNDW2_DATA", "DMIC_DATA1", + "GPP_S6", "SNDW3_CLK", "DMIC_CLK_A0", + "GPP_S7", "SNDW3_DATA", "DMIC_DATA0", +}; + +const struct gpio_group tigerlake_pch_lp_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_s_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_s_names, +}; + +const char *const tigerlake_pch_lp_group_gpp_t_names[] = { + "GPP_T0", + "GPP_T1", + "GPP_T2", + "GPP_T3", + "GPP_T4", + "GPP_T5", + "GPP_T6", + "GPP_T7", + "GPP_T8", + "GPP_T9", + "GPP_T10", + "GPP_T11", + "GPP_T12", + "GPP_T13", + "GPP_T14", + "GPP_T15", +}; + +const struct gpio_group tigerlake_pch_lp_group_t = { + .display = "------- GPIO Group GPP_T (TGL UP3 only) -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_gpp_t_names), + .func_count = 1, + .pad_names = tigerlake_pch_lp_group_gpp_t_names, +}; + +const char *const tigerlake_pch_lp_group_u_names[] = { + "GPP_U0", + "GPP_U1", + "GPP_U2", + "GPP_U3", + "GPP_U4", + "GPP_U5", + "GPP_U6", + "GPP_U7", + "GPP_U8", + "GPP_U9", + "GPP_U10", + "GPP_U11", + "GPP_U12", + "GPP_U13", + "GPP_U14", + "GPP_U15", + "GPP_U16", + "GPP_U17", + "GPP_U18", + "GPP_U19", + "GSPI3_CLK_LOOPBK", + "GSPI4_CLK_LOOPBK", + "GSPI5_CLK_LOOPBK", + "GSPI6_CLK_LOOPBK", +}; + +const struct gpio_group tigerlake_pch_lp_group_u = { + .display = "------- GPIO Group GPP_U (TGL UP3 only) -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_u_names), + .func_count = 1, + .pad_names = tigerlake_pch_lp_group_u_names, +}; + +const char *const tigerlake_pch_lp_group_vgpio_names[] = { + "VGPIO0", "VGPIO0", + "VGPIO4", "VGPIO4", + "VGPIO5", "VGPIO5", + "VGPIO6", "VGPIO6", + "VGPIO7", "VGPIO7", + "VGPIO8", "VGPIO8", + "VGPIO9", "VGPIO9", + "VGPIO10", "VGPIO10", + "VGPIO11", "VGPIO11", + "VGPIO12", "VGPIO12", + "VGPIO13", "VGPIO13", + "VGPIO18", "VGPIO18", + "VGPIO19", "VGPIO19", + "VGPIO20", "VGPIO20", + "VGPIO21", "VGPIO21", + "VGPIO22", "VGPIO22", + "VGPIO23", "VGPIO23", + "VGPIO24", "VGPIO24", + "VGPIO25", "VGPIO25", + "VGPIO30", "VGPIO30", + "VGPIO31", "VGPIO31", + "VGPIO32", "VGPIO32", + "VGPIO33", "VGPIO33", + "VGPIO34", "VGPIO34", + "VGPIO35", "VGPIO35", + "VGPIO36", "VGPIO36", + "VGPIO37", "VGPIO37", +}; + +const struct gpio_group tigerlake_pch_lp_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_vgpio_names, +}; + +const char *const tigerlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", + "INPUT3VSEL", "INPUT3VSEL", + "SLP_LAN#", "SLP_LAN#", + "SLP_SUS#", "SLP_SUS#", + "WAKE#", "WAKE#", + "DRAM_RESET#", "DRAM_RESET#", +}; + +const struct gpio_group tigerlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_gpd_names, +}; + +const char *const tigerlake_pch_lp_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_SCLK", "HDACPU_SCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIP#", "THRMTRIP#", + "PLTRST_CPU#", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", + "UFS_RESET#", "UFS_RESET#", + "CLKOUT_CPURTC", "CLKOUT_CPURTC", + "VCCST_OVERRIDE", "VCCST_OVERRIDE", + "C10_WAKE", "C10_WAKE", +}; + +const struct gpio_group tigerlake_pch_lp_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_cpu_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_cpu_names, +}; + +const char *const tigerlake_pch_lp_group_vgpio3_names[] = { + "VGPIO_PCIE_0", "VGPIO_PCIE_0", + "VGPIO_PCIE_1", "VGPIO_PCIE_1", + "VGPIO_PCIE_2", "VGPIO_PCIE_2", + "VGPIO_PCIE_3", "VGPIO_PCIE_3", + "VGPIO_PCIE_4", "VGPIO_PCIE_4", + "VGPIO_PCIE_5", "VGPIO_PCIE_5", + "VGPIO_PCIE_6", "VGPIO_PCIE_6", + "VGPIO_PCIE_7", "VGPIO_PCIE_7", + "VGPIO_PCIE_8", "VGPIO_PCIE_8", + "VGPIO_PCIE_9", "VGPIO_PCIE_9", + "VGPIO_PCIE_10", "VGPIO_PCIE_10", + "VGPIO_PCIE_11", "VGPIO_PCIE_11", + "VGPIO_PCIE_12", "VGPIO_PCIE_12", + "VGPIO_PCIE_13", "VGPIO_PCIE_13", + "VGPIO_PCIE_14", "VGPIO_PCIE_14", + "VGPIO_PCIE_15", "VGPIO_PCIE_15", + "VGPIO_PCIE_16", "VGPIO_PCIE_16", + "VGPIO_PCIE_17", "VGPIO_PCIE_17", + "VGPIO_PCIE_18", "VGPIO_PCIE_18", + "VGPIO_PCIE_19", "VGPIO_PCIE_19", + "VGPIO_PCIE_20", "VGPIO_PCIE_20", + "VGPIO_PCIE_21", "VGPIO_PCIE_21", + "VGPIO_PCIE_22", "VGPIO_PCIE_22", + "VGPIO_PCIE_23", "VGPIO_PCIE_23", + "VGPIO_PCIE_24", "VGPIO_PCIE_24", + "VGPIO_PCIE_25", "VGPIO_PCIE_25", + "VGPIO_PCIE_26", "VGPIO_PCIE_26", + "VGPIO_PCIE_27", "VGPIO_PCIE_27", + "VGPIO_PCIE_28", "VGPIO_PCIE_28", + "VGPIO_PCIE_29", "VGPIO_PCIE_29", + "VGPIO_PCIE_30", "VGPIO_PCIE_30", + "VGPIO_PCIE_31", "VGPIO_PCIE_31", + "VGPIO_PCIE_32", "VGPIO_PCIE_32", + "VGPIO_PCIE_33", "VGPIO_PCIE_33", + "VGPIO_PCIE_34", "VGPIO_PCIE_34", + "VGPIO_PCIE_35", "VGPIO_PCIE_35", + "VGPIO_PCIE_36", "VGPIO_PCIE_36", + "VGPIO_PCIE_37", "VGPIO_PCIE_37", + "VGPIO_PCIE_38", "VGPIO_PCIE_38", + "VGPIO_PCIE_39", "VGPIO_PCIE_39", + "VGPIO_PCIE_40", "VGPIO_PCIE_40", + "VGPIO_PCIE_41", "VGPIO_PCIE_41", + "VGPIO_PCIE_42", "VGPIO_PCIE_42", + "VGPIO_PCIE_43", "VGPIO_PCIE_43", + "VGPIO_PCIE_44", "VGPIO_PCIE_44", + "VGPIO_PCIE_45", "VGPIO_PCIE_45", + "VGPIO_PCIE_46", "VGPIO_PCIE_46", + "VGPIO_PCIE_47", "VGPIO_PCIE_47", + "VGPIO_PCIE_48", "VGPIO_PCIE_48", + "VGPIO_PCIE_49", "VGPIO_PCIE_49", + "VGPIO_PCIE_50", "VGPIO_PCIE_50", + "VGPIO_PCIE_51", "VGPIO_PCIE_51", + "VGPIO_PCIE_52", "VGPIO_PCIE_52", + "VGPIO_PCIE_53", "VGPIO_PCIE_53", + "VGPIO_PCIE_54", "VGPIO_PCIE_54", + "VGPIO_PCIE_55", "VGPIO_PCIE_55", + "VGPIO_PCIE_56", "VGPIO_PCIE_56", + "VGPIO_PCIE_57", "VGPIO_PCIE_57", + "VGPIO_PCIE_58", "VGPIO_PCIE_58", + "VGPIO_PCIE_59", "VGPIO_PCIE_59", + "VGPIO_PCIE_60", "VGPIO_PCIE_60", + "VGPIO_PCIE_61", "VGPIO_PCIE_61", + "VGPIO_PCIE_62", "VGPIO_PCIE_62", + "VGPIO_PCIE_63", "VGPIO_PCIE_63", + "VGPIO_PCIE_64", "VGPIO_PCIE_64", + "VGPIO_PCIE_65", "VGPIO_PCIE_65", + "VGPIO_PCIE_66", "VGPIO_PCIE_66", + "VGPIO_PCIE_67", "VGPIO_PCIE_67", + "VGPIO_PCIE_68", "VGPIO_PCIE_68", + "VGPIO_PCIE_69", "VGPIO_PCIE_69", + "VGPIO_PCIE_70", "VGPIO_PCIE_70", + "VGPIO_PCIE_71", "VGPIO_PCIE_71", + "VGPIO_PCIE_72", "VGPIO_PCIE_72", + "VGPIO_PCIE_73", "VGPIO_PCIE_73", + "VGPIO_PCIE_74", "VGPIO_PCIE_74", + "VGPIO_PCIE_75", "VGPIO_PCIE_75", + "VGPIO_PCIE_76", "VGPIO_PCIE_76", + "VGPIO_PCIE_77", "VGPIO_PCIE_77", + "VGPIO_PCIE_78", "VGPIO_PCIE_78", + "VGPIO_PCIE_79", "VGPIO_PCIE_79", + "VGPIO_USB_0", "VGPIO_USB_0", + "VGPIO_USB_1", "VGPIO_USB_1", + "VGPIO_USB_2", "VGPIO_USB_2", + "VGPIO_USB_3", "VGPIO_USB_3", + "VGPIO_USB_4", "VGPIO_USB_4", + "VGPIO_USB_5", "VGPIO_USB_5", + "VGPIO_USB_6", "VGPIO_USB_6", + "VGPIO_USB_7", "VGPIO_USB_7", + "VGPIO_PCIE_80", "VGPIO_PCIE_80", + "VGPIO_PCIE_81", "VGPIO_PCIE_81", + "VGPIO_PCIE_82", "VGPIO_PCIE_82", + "VGPIO_PCIE_83", "VGPIO_PCIE_83", +}; + +const struct gpio_group tigerlake_pch_lp_group_vgpio3 = { + .display = "------- GPIO Group VGPIO3 -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_vgpio3_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_vgpio3_names, +}; + +const char *const tigerlake_pch_lp_group_jtag_names[] = { + "JTAG_TDO", "JTAG_TDO", + "JTAGX", "JTAGX", + "PRDY#", "PRDY#", + "PREQ#", "PREQ#", + "CPU_TRST#", "CPU_TRST#", + "JTAG_TDI", "JTAG_TDI", + "JTAG_TMS", "JTAG_TMS", + "JTAG_TCK", "JTAG_TCK", + "DBG_PMODE", "DBG_PMODE", + "MLK", "MLK", +}; + +const struct gpio_group tigerlake_pch_lp_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_jtag_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_jtag_names, +}; + +const char *const tigerlake_pch_lp_group_spi_names[] = { + "SPI0_IO_2", "SPI0_IO_2", + "SPI0_IO_3", "SPI0_IO_3", + "SPI0_MOSI_IO_0", "SPI0_MOSI_IO_0", + "SPI0_MISO_IO_1", "SPI0_MISO_IO_1", + "SPI0_TPM_CS2#", "SPI0_TPM_CS2#", + "SPI0_FLASH_CS0#", "SPI0_FLASH_CS0#", + "SPI0_FLASH_CS1#", "SPI0_FLASH_CS1#", + "SPI0_CLK", "SPI0_CLK", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", +}; + +const struct gpio_group tigerlake_pch_lp_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_spi_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_spi_names, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_0_groups[] = { + &tigerlake_pch_lp_group_b, + &tigerlake_pch_lp_group_t, + &tigerlake_pch_lp_group_a, +}; + +const struct gpio_community tigerlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_0_groups), + .groups = tigerlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_1_groups[] = { + &tigerlake_pch_lp_group_s, + &tigerlake_pch_lp_group_h, + &tigerlake_pch_lp_group_d, + &tigerlake_pch_lp_group_u, + &tigerlake_pch_lp_group_vgpio, +}; +const struct gpio_community tigerlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_1_groups), + .groups = tigerlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_2_groups[] = { + &tigerlake_pch_lp_group_gpd, +}; + +const struct gpio_community tigerlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_2_groups), + .groups = tigerlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_3_groups[] = { + &tigerlake_pch_lp_group_cpu, + &tigerlake_pch_lp_group_vgpio3, +}; + +const struct gpio_community tigerlake_pch_lp_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_3_groups), + .groups = tigerlake_pch_lp_community_3_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_4_groups[] = { + &tigerlake_pch_lp_group_c, + &tigerlake_pch_lp_group_f, + &tigerlake_pch_lp_group_hvmos, + &tigerlake_pch_lp_group_e, + &tigerlake_pch_lp_group_jtag, +}; + +const struct gpio_community tigerlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_4_groups), + .groups = tigerlake_pch_lp_community_4_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_5_groups[] = { + &tigerlake_pch_lp_group_r, + &tigerlake_pch_lp_group_spi, +}; + +const struct gpio_community tigerlake_pch_lp_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_5_groups), + .groups = tigerlake_pch_lp_community_5_groups, +}; + +const struct gpio_community *const tigerlake_pch_lp_communities[] = { + &tigerlake_pch_lp_community_0, + &tigerlake_pch_lp_community_1, + &tigerlake_pch_lp_community_2, + &tigerlake_pch_lp_community_3, + &tigerlake_pch_lp_community_4, + &tigerlake_pch_lp_community_5, +}; + +/* ----------------------------- Tiger Lake H ----------------------------- */ + +const char *const tigerlake_pch_h_group_a_names[] = { +/* + * These pads start at offset 0x680, but according to EDS the PADBAR is 0x700. + * This would cause the tool to parse the GPIOs incorrectly. + * For informational purposes only. + */ +/* + "SPI0_IO_2", "SPI0_IO_2", "n/a", + "SPI0_IO_3", "SPI0_IO_3", "n/a", + "SPI0_MOSI_IO_0", "SPI0_MOSI_IO_0", "n/a", + "SPI0_MISO_IO_1", "SPI0_MISO_IO_1", "n/a", + "SPI0_TPM_CS2#", "SPI0_TPM_CS2#", "n/a", + "SPI0_FLASH_CS0#", "SPI0_FLASH_CS0#", "n/a", + "SPI0_FLASH_CS1#", "SPI0_FLASH_CS1#", "n/a", + "SPI0_CLK", "SPI0_CLK", "n/a", +*/ + "GPP_A0", "ESPI_IO0", "n/a", + "GPP_A1", "ESPI_IO1", "n/a", + "GPP_A2", "ESPI_IO2", "SUSWARN#/SUSPWRDNACK", + "GPP_A3", "ESPI_IO3", "SUSACK#", + "GPP_A4", "ESPI_CS0#", "n/a", + "GPP_A5", "ESPI_CLK", "n/a", + "GPP_A6", "ESPI_RESET#", "n/a", + "GPP_A7", "ESPI_CS1#", "n/a", + "GPP_A8", "ESPI_CS2#", "n/a", + "GPP_A9", "ESPI_CS3#", "n/a", + "GPP_A10", "ESPI_ALERT0#", "n/a", + "GPP_A11", "ESPI_ALERT1#", "n/a", + "GPP_A12", "ESPI_ALERT2#", "n/a", + "GPP_A13", "ESPI_ALERT3#", "n/a", + "GPP_A14", "n/a", "IMGCLKOUT0", + "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_a_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_a_names, +}; + +const char *const tigerlake_pch_h_group_b_names[] = { + "GPP_B0", "GSPI0_CS1#", "IMGCLKOUT1", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_b_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_b_names, +}; + +const char *const tigerlake_pch_h_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", "n/a", + "GPP_C3", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a", + "GPP_C4", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", "n/a", + "GPP_C6", "ISH_I2C2_SDA", "I2C3_SDA", "SBK4", "BK4", + "GPP_C7", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_c_names) / 5, + .func_count = 5, + .pad_names = tigerlake_pch_h_group_c_names, +}; + +const char *const tigerlake_pch_h_group_d_names[] = { + "GPP_D0", "n/a", "THC0_SPI1_CS#", "SBK0", "BK0", + "GPP_D1", "n/a", "THC0_SPI1_CLK", "SBK1", "BK1", + "GPP_D2", "n/a", "THC0_SPI1_IO1", "SBK2", "BK2", + "GPP_D3", "n/a", "THC0_SPI1_IO0", "SBK3", "BK3", + "GPP_D4", "SML1CLK", "n/a", "n/a", "n/a", + "GPP_D5", "I2S2_SFRM", "CNV_RF_RESET#", "n/a", "n/a", + "GPP_D6", "I2S2_TXD", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", + "GPP_D7", "I2S2_RXD", "THC0_SPI1_RST#", "n/a", "n/a", + "GPP_D8", "I2S2_SCLK", "THC0_SPI1_INT#", "n/a", "n/a", + "GPP_D9", "SML0CLK", "n/a", "n/a", "n/a", + "GPP_D10", "SML0DATA", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", "n/a", + "GPP_D12", "ISH_UART0_CTS#", "n/a", "n/a", "n/a", + "GPP_D13", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", + "GPP_D14", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", + "GPP_D15", "SML1DATA", "n/a", "n/a", "n/a", + "GPP_D16", "GSPI3_CS0#", "THC1_SPI2_CS#", "n/a", "n/a", + "GPP_D17", "GSPI3_CLK", "THC1_SPI2_CLK", "n/a", "n/a", + "GPP_D18", "GSPI3_MISO", "THC1_SPI2_IO0", "n/a", "n/a", + "GPP_D19", "GSPI3_MOSI", "THC1_SPI2_IO1", "n/a", "n/a", + "GPP_D20", "UART3_RXD", "THC1_SPI2_IO2", "n/a", "n/a", + "GPP_D21", "UART3_TXD", "THC1_SPI2_IO3", "n/a", "n/a", + "GPP_D22", "UART3_RTS#", "THC1_SPI2_RST#", "n/a", "n/a", + "GPP_D23", "UART3_CTS#", "THC1_SPI2_INT#", "n/a", "n/a", + /* Below are just guesses */ + "SPI1_CLK_LOOPBK", "n/a", "THC0_CLK_LOOPBK", "n/a", "n/a", + "GPI3_CLK_LOOPBK", "n/a", "THC1_CLK_LOOPBK", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_d_names) / 5, + .func_count = 5, + .pad_names = tigerlake_pch_h_group_d_names, +}; + +const char *const tigerlake_pch_h_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", + "GPP_E1", "SATAXPCIE1", "SATAGP1", + "GPP_E2", "SATAXPCIE2", "SATAGP2", + "GPP_E3", "CPU_GP0", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", + "GPP_E7", "CPU_GP1", "n/a", + "GPP_E8", "SATALED#", "n/a", + "GPP_E9", "USB_OC0#", "n/a", + "GPP_E10", "USB_OC1#", "n/a", + "GPP_E11", "USB_OC2#", "n/a", + "GPP_E12", "USB_OC3#", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_e_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_e_names, +}; + +const char *const tigerlake_pch_h_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", + "GPP_F14", "PS_ON#", "n/a", + "GPP_F15", "M2_SKT2_CFG0", "n/a", + "GPP_F16", "M2_SKT2_CFG1", "n/a", + "GPP_F17", "M2_SKT2_CFG2", "n/a", + "GPP_F18", "M2_SKT2_CFG3", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", + "GPP_F22", "VNN_CTRL", "n/a", + "GPP_F23", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_f_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_f_names, +}; + +const char *const tigerlake_pch_h_group_g_names[] = { + "GPP_G0", "DDPA_CTRLCLK", "n/a", "n/a", "n/a", "n/a", + "GPP_G1", "DDPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", + "GPP_G2", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", "n/a", + "GPP_G3", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G4", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_G5", "SLP_DRAM#", "n/a", "n/a", "n/a", "n/a", + "GPP_G6", "n/a", "Reserved", "n/a", "n/a", "n/a", + "GPP_G7", "n/a", "Reserved", "n/a", "n/a", "n/a", + "GPP_G8", "ISH_SPI_CS#", "DDP3_CTRLCLK", "GSPI2_CS0#", "TBT_LSX2_TXD", "BSSB_LS2_RX", + "GPP_G9", "ISH_SPI_CLK", "DDP3_CTRLDATA", "GSPI2_CLK", "TBT_LSX2_RXD", "BSSB_LS2_TX", + "GPP_G10", "ISH_SPI_MISO", "DDP4_CTRLCLK", "GSPI2_MISO", "TBT_LSX3_TXD", "BSSB_LS3_RX", + "GPP_G11", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "GSPI2_MOSI", "TBT_LSX3_RXD", "BSSB_LS3_TX", + "GPP_G12", "DDP1_CTRLCLK", "n/a", "TBT_LSX0_TXD", "BSSB_LS0_RX", "n/a", + "GPP_G13", "DDP1_CTRLDATA", "n/a", "TBT_LSX0_RXD", "BSSB_LS0_TX", "n/a", + "GPP_G14", "DDP2_CTRLCLK", "n/a", "TBT_LSX1_TXD", "BSSB_LS1_RX", "n/a", + "GPP_G15", "DDP2_CTRLDATA", "n/a", "TBT_LSX1_RXD", "BSSB_LS1_TX", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_g_names) / 6, + .func_count = 6, + .pad_names = tigerlake_pch_h_group_g_names, +}; + +const char *const tigerlake_pch_h_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", + "GPP_H10", "SML2CLK", "n/a", + "GPP_H11", "SML2DATA", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", + "GPP_H13", "SML3CLK", "n/a", + "GPP_H14", "SML3DATA", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", + "GPP_H16", "SML4CLK", "n/a", + "GPP_H17", "SML4DATA", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "SMI#", + "GPP_H22", "ISH_I2C1_SCL", "NMI#", + "GPP_H23", "TIME_SYNC0", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_h_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_h_names, +}; + +const char *const tigerlake_pch_h_group_i_names[] = { + "GPP_I0", "PMCALERT#", "n/a", + "GPP_I1", "DDSP_HPD1", "DISP_MISC1", + "GPP_I2", "DDSP_HPD2", "DISP_MISC2", + "GPP_I3", "DDSP_HPD3", "DISP_MISC3", + "GPP_I4", "DDSP_HPD4", "DISP_MISC4", + "GPP_I5", "DDPB_CTRLCLK", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", + "GPP_I9", "Reserved", "n/a", + "GPP_I10", "Reserved", "n/a", + "GPP_I11", "USB_OC4#", "I2C4_SDA", + "GPP_I12", "USB_OC5#", "I2C4_SCL", + "GPP_I13", "USB_OC6#", "I2C5_SDA", + "GPP_I14", "USB_OC7#", "I2C5_SCL", +}; + +const struct gpio_group tigerlake_pch_h_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_i_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_i_names, +}; + +const char *const tigerlake_pch_h_group_j_names[] = { + "GPP_J0", "CNV_PA_BLANKING", "n/a", + "GPP_J1", "CPU_C10_GATE#", "n/a", + "GPP_J2", "CNV_BRI_DT", "UART0_RTS#", + "GPP_J3", "CNV_BRI_RSP", "UART0_RXD", + "GPP_J4", "CNV_RGI_DT", "UART0_TXD", + "GPP_J5", "CNV_RGI_RSP", "UART0_CTS#", + "GPP_J6", "CNV_MFUART2_RXD", "n/a", + "GPP_J7", "CNV_MFUART2_TXD", "n/a", + "GPP_J8", "n/a", "n/a", + "GPP_J9", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_j_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_j_names, +}; + + +const char *const tigerlake_pch_h_group_k_names[] = { + "GPP_K0", "GSXDOUT", "n/a", + "GPP_K1", "GSXSLOAD", "n/a", + "GPP_K2", "GSXDIN", "n/a", + "GPP_K3", "GSXSRESET#", "n/a", + "GPP_K4", "GSXCLK", "n/a", + "GPP_K5", "ADR_COMPLETE", "n/a", + "GPP_K6", "DDSP_HPDA", "DISP_MISCA", + "GPP_K7", "DDSP_HPDB", "DISP_MISCB", + "GPP_K8", "CORE_VID0", "n/a", + "GPP_K9", "CORE_VID1", "n/a", + "GPP_K10", "DDSP_HPDC", "DISP_MISCC", + "GPP_K11", "n/a", "n/a", + "SYS_PWROK", "SYS_PWROK", "n/a", + "SYS_RESET#", "SYS_RESET#", "n/a", + "MLK_RST#", "MLK_RST#", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_k_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_k_names, +}; + +const char *const tigerlake_pch_h_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", "n/a", "HDACPU_BCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", "n/a", "n/a", + "GPP_R2", "HDA_SDO", "I2S0_TXD", "n/a", "HDACPU_SDO", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", "n/a", "HDACPU_SDI", + "GPP_R4", "HDA_RST#", "n/a", "n/a", "n/a", + "GPP_R5", "HDA_SDI1", "I2S1_RXD", "n/a", "n/a", + "GPP_R6", "n/a", "I2S1_TXD", "n/a", "n/a", + "GPP_R7", "n/a", "I2S1_SFRM", "n/a", "n/a", + "GPP_R8", "n/a", "I2S1_SCLK", "n/a", "n/a", + "GPP_R9", "PCIE_LNK_DOWN", "n/a", "n/a", "n/a", + "GPP_R10", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", "n/a", + "GPP_R11", "SX_EXIT_HOLDOFF#", "ISH_GP6", "n/a", "n/a", + "GPP_R12", "CLKOUT_48", "n/a", "n/a", "n/a", + "GPP_R13", "ISH_GP7", "n/a", "n/a", "n/a", + "GPP_R14", "ISH_GP0", "n/a", "n/a", "n/a", + "GPP_R15", "ISH_GP1", "n/a", "n/a", "n/a", + "GPP_R16", "ISH_GP2", "n/a", "n/a", "n/a", + "GPP_R17", "ISH_GP3", "n/a", "n/a", "n/a", + "GPP_R18", "ISH_GP4", "n/a", "n/a", "n/a", + "GPP_R19", "ISH_GP5", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_h_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_r_names) / 5, + .func_count = 5, + .pad_names = tigerlake_pch_h_group_r_names, +}; + +const char *const tigerlake_pch_h_group_s_names[] = { + "GPP_S0", "SNDW1_CLK", "n/a", + "GPP_S1", "SNDW1_DATA", "n/a", + "GPP_S2", "SNDW2_CLK", "DMIC_CKLB0", + "GPP_S3", "SNDW2_DATA", "DMIC_CLKB1", + "GPP_S4", "SNDW3_CLK", "DMIC_CLKA1", + "GPP_S5", "SNDW3_DATA", "DMIC_DATA1", + "GPP_S6", "SNDW4_CLK", "DMIC_CLKA0", + "GPP_S7", "SNDW4_DATA", "DMIC_DATA0", +}; + +const struct gpio_group tigerlake_pch_h_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_s_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_h_group_s_names, +}; + +const char *const tigerlake_pch_h_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PWRBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", + "GPD12", "n/a", + "SLP_LAN#", "SLP_LAN#", + "SLP_SUS#", "SLP_SUS#", + "WAKE#", "WAKE#", + "DRAM_RESET#", "DRAM_RESET#", +}; + +const struct gpio_group tigerlake_pch_h_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_gpd_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_gpd_names, +}; + +const char *const tigerlake_pch_h_group_vgpio0_names[] = { + "VGPIO_USB_0", "VGPIO_USB_0", + "VGPIO_USB_1", "VGPIO_USB_1", + "VGPIO_USB_2", "VGPIO_USB_2", + "VGPIO_USB_3", "VGPIO_USB_3", + "VGPIO_USB_8", "VGPIO_USB_8", + "VGPIO_USB_9", "VGPIO_USB_9", + "VGPIO_USB_10", "VGPIO_USB_10", + "VGPIO_USB_11", "VGPIO_USB_11", +}; + +const struct gpio_group tigerlake_pch_h_group_vgpio0 = { + .display = "------- GPIO Group VGPIO0 -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_vgpio0_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_vgpio0_names, +}; + +const char *const tigerlake_pch_h_group_vgpio_names[] = { + "VGPIO0", "VGPIO0", + "VGPIO4", "VGPIO4", + "VGPIO5", "VGPIO5", + "VGPIO6", "VGPIO6", + "VGPIO7", "VGPIO7", + "VGPIO8", "VGPIO8", + "VGPIO9", "VGPIO9", + "VGPIO10", "VGPIO10", + "VGPIO11", "VGPIO11", + "VGPIO12", "VGPIO12", + "VGPIO13", "VGPIO13", + "VGPIO18", "VGPIO18", + "VGPIO19", "VGPIO19", + "VGPIO20", "VGPIO20", + "VGPIO21", "VGPIO21", + "VGPIO22", "VGPIO22", + "VGPIO23", "VGPIO23", + "VGPIO24", "VGPIO24", + "VGPIO25", "VGPIO25", + "VGPIO30", "VGPIO30", + "VGPIO31", "VGPIO31", + "VGPIO32", "VGPIO32", + "VGPIO33", "VGPIO33", + "VGPIO34", "VGPIO34", + "VGPIO35", "VGPIO35", + "VGPIO36", "VGPIO36", + "VGPIO37", "VGPIO37", +}; + +const struct gpio_group tigerlake_pch_h_group_vgpio = { + .display = "------- GPIO Group VGPIO -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_vgpio_names, +}; + +const char *const tigerlake_pch_h_group_cpu_names[] = { + "HDACPU_SDI", "HDACPU_SDI", + "HDACPU_SDO", "HDACPU_SDO", + "HDACPU_BCLK", "HDACPU_BCLK", + "PM_SYNC", "PM_SYNC", + "PECI", "PECI", + "CPUPWRGD", "CPUPWRGD", + "THRMTRIP#", "THRMTRIP#", + "PLTRST_CPU#", "PLTRST_CPU#", + "PM_DOWN", "PM_DOWN", + "TRIGGER_IN", "TRIGGER_IN", + "TRIGGER_OUT", "TRIGGER_OUT", + "CLKOUT_CPURTC", "CLKOUT_CPURTC", + "VCCST_OVERRIDE", "VCCST_OVERRIDE", + "C10_WAKE", "C10_WAKE", +}; + +const struct gpio_group tigerlake_pch_h_group_cpu = { + .display = "------- GPIO Group CPU -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_cpu_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_cpu_names, +}; + +const char *const tigerlake_pch_h_group_vgpio3_names[] = { + "VGPIO_PCIE_0", "VGPIO_PCIE_0", + "VGPIO_PCIE_1", "VGPIO_PCIE_1", + "VGPIO_PCIE_2", "VGPIO_PCIE_2", + "VGPIO_PCIE_3", "VGPIO_PCIE_3", + "VGPIO_PCIE_4", "VGPIO_PCIE_4", + "VGPIO_PCIE_5", "VGPIO_PCIE_5", + "VGPIO_PCIE_6", "VGPIO_PCIE_6", + "VGPIO_PCIE_7", "VGPIO_PCIE_7", + "VGPIO_PCIE_8", "VGPIO_PCIE_8", + "VGPIO_PCIE_9", "VGPIO_PCIE_9", + "VGPIO_PCIE_10", "VGPIO_PCIE_10", + "VGPIO_PCIE_11", "VGPIO_PCIE_11", + "VGPIO_PCIE_12", "VGPIO_PCIE_12", + "VGPIO_PCIE_13", "VGPIO_PCIE_13", + "VGPIO_PCIE_14", "VGPIO_PCIE_14", + "VGPIO_PCIE_15", "VGPIO_PCIE_15", + "VGPIO_PCIE_16", "VGPIO_PCIE_16", + "VGPIO_PCIE_17", "VGPIO_PCIE_17", + "VGPIO_PCIE_18", "VGPIO_PCIE_18", + "VGPIO_PCIE_19", "VGPIO_PCIE_19", + "VGPIO_PCIE_20", "VGPIO_PCIE_20", + "VGPIO_PCIE_21", "VGPIO_PCIE_21", + "VGPIO_PCIE_22", "VGPIO_PCIE_22", + "VGPIO_PCIE_23", "VGPIO_PCIE_23", + "VGPIO_PCIE_24", "VGPIO_PCIE_24", + "VGPIO_PCIE_25", "VGPIO_PCIE_25", + "VGPIO_PCIE_26", "VGPIO_PCIE_26", + "VGPIO_PCIE_27", "VGPIO_PCIE_27", + "VGPIO_PCIE_28", "VGPIO_PCIE_28", + "VGPIO_PCIE_29", "VGPIO_PCIE_29", + "VGPIO_PCIE_30", "VGPIO_PCIE_30", + "VGPIO_PCIE_31", "VGPIO_PCIE_31", + "VGPIO_PCIE_32", "VGPIO_PCIE_32", + "VGPIO_PCIE_33", "VGPIO_PCIE_33", + "VGPIO_PCIE_34", "VGPIO_PCIE_34", + "VGPIO_PCIE_35", "VGPIO_PCIE_35", + "VGPIO_PCIE_36", "VGPIO_PCIE_36", + "VGPIO_PCIE_37", "VGPIO_PCIE_37", + "VGPIO_PCIE_38", "VGPIO_PCIE_38", + "VGPIO_PCIE_39", "VGPIO_PCIE_39", + "VGPIO_PCIE_40", "VGPIO_PCIE_40", + "VGPIO_PCIE_41", "VGPIO_PCIE_41", + "VGPIO_PCIE_42", "VGPIO_PCIE_42", + "VGPIO_PCIE_43", "VGPIO_PCIE_43", + "VGPIO_PCIE_44", "VGPIO_PCIE_44", + "VGPIO_PCIE_45", "VGPIO_PCIE_45", + "VGPIO_PCIE_46", "VGPIO_PCIE_46", + "VGPIO_PCIE_47", "VGPIO_PCIE_47", + "VGPIO_PCIE_48", "VGPIO_PCIE_48", + "VGPIO_PCIE_49", "VGPIO_PCIE_49", + "VGPIO_PCIE_50", "VGPIO_PCIE_50", + "VGPIO_PCIE_51", "VGPIO_PCIE_51", + "VGPIO_PCIE_52", "VGPIO_PCIE_52", + "VGPIO_PCIE_53", "VGPIO_PCIE_53", + "VGPIO_PCIE_54", "VGPIO_PCIE_54", + "VGPIO_PCIE_55", "VGPIO_PCIE_55", + "VGPIO_PCIE_56", "VGPIO_PCIE_56", + "VGPIO_PCIE_57", "VGPIO_PCIE_57", + "VGPIO_PCIE_58", "VGPIO_PCIE_58", + "VGPIO_PCIE_59", "VGPIO_PCIE_59", + "VGPIO_PCIE_60", "VGPIO_PCIE_60", + "VGPIO_PCIE_61", "VGPIO_PCIE_61", + "VGPIO_PCIE_62", "VGPIO_PCIE_62", + "VGPIO_PCIE_63", "VGPIO_PCIE_63", + "VGPIO_PCIE_64", "VGPIO_PCIE_64", + "VGPIO_PCIE_65", "VGPIO_PCIE_65", + "VGPIO_PCIE_66", "VGPIO_PCIE_66", + "VGPIO_PCIE_67", "VGPIO_PCIE_67", + "VGPIO_PCIE_68", "VGPIO_PCIE_68", + "VGPIO_PCIE_69", "VGPIO_PCIE_69", + "VGPIO_PCIE_70", "VGPIO_PCIE_70", + "VGPIO_PCIE_71", "VGPIO_PCIE_71", + "VGPIO_PCIE_72", "VGPIO_PCIE_72", + "VGPIO_PCIE_73", "VGPIO_PCIE_73", + "VGPIO_PCIE_74", "VGPIO_PCIE_74", + "VGPIO_PCIE_75", "VGPIO_PCIE_75", + "VGPIO_PCIE_76", "VGPIO_PCIE_76", + "VGPIO_PCIE_77", "VGPIO_PCIE_77", + "VGPIO_PCIE_78", "VGPIO_PCIE_78", + "VGPIO_PCIE_79", "VGPIO_PCIE_79", + "VGPIO_PCIE_80", "VGPIO_PCIE_80", + "VGPIO_PCIE_81", "VGPIO_PCIE_81", + "VGPIO_PCIE_82", "VGPIO_PCIE_82", + "VGPIO_PCIE_83", "VGPIO_PCIE_83", +}; + +const struct gpio_group tigerlake_pch_h_group_vgpio3 = { + .display = "------- GPIO Group VGPIO3 -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_vgpio3_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_vgpio3_names, +}; + +const char *const tigerlake_pch_h_group_jtag_names[] = { + "JTAG_TDO", "JTAG_TDO", + "JTAGX", "JTAGX", + "PRDY#", "PRDY#", + "PREQ#", "PREQ#", + "CPU_TRST#", "CPU_TRST#", + "JTAG_TDI", "JTAG_TDI", + "JTAG_TMS", "JTAG_TMS", + "JTAG_TCK", "JTAG_TCK", + "DBG_PMODE", "DBG_PMODE", + "MLK", "MLK", +}; + +const struct gpio_group tigerlake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_h_group_jtag_names, +}; + + +const struct gpio_group *const tigerlake_pch_h_community_0_groups[] = { + &tigerlake_pch_h_group_a, + &tigerlake_pch_h_group_r, + &tigerlake_pch_h_group_b, + &tigerlake_pch_h_group_vgpio0, +}; + +const struct gpio_community tigerlake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_0_groups), + .groups = tigerlake_pch_h_community_0_groups, +}; + +const struct gpio_group *const tigerlake_pch_h_community_1_groups[] = { + &tigerlake_pch_h_group_d, + &tigerlake_pch_h_group_c, + &tigerlake_pch_h_group_s, + &tigerlake_pch_h_group_g, + &tigerlake_pch_h_group_vgpio, +}; +const struct gpio_community tigerlake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_1_groups), + .groups = tigerlake_pch_h_community_1_groups, +}; + +const struct gpio_group *const tigerlake_pch_h_community_2_groups[] = { + &tigerlake_pch_h_group_gpd, +}; + +const struct gpio_community tigerlake_pch_h_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_2_groups), + .groups = tigerlake_pch_h_community_2_groups, +}; + +const struct gpio_group *const tigerlake_pch_h_community_3_groups[] = { + &tigerlake_pch_h_group_e, + &tigerlake_pch_h_group_f, + &tigerlake_pch_h_group_vgpio3, +}; + +const struct gpio_community tigerlake_pch_h_community_3 = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_3_groups), + .groups = tigerlake_pch_h_community_3_groups, +}; + +const struct gpio_group *const tigerlake_pch_h_community_4_groups[] = { + &tigerlake_pch_h_group_h, + &tigerlake_pch_h_group_j, + &tigerlake_pch_h_group_k, +}; + +const struct gpio_community tigerlake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_4_groups), + .groups = tigerlake_pch_h_community_4_groups, +}; + +const struct gpio_group *const tigerlake_pch_h_community_5_groups[] = { + &tigerlake_pch_h_group_i, + &tigerlake_pch_h_group_jtag, + &tigerlake_pch_h_group_cpu, +}; + +const struct gpio_community tigerlake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(tigerlake_pch_h_community_5_groups), + .groups = tigerlake_pch_h_community_5_groups, +}; + +const struct gpio_community *const tigerlake_pch_h_communities[] = { + &tigerlake_pch_h_community_0, + &tigerlake_pch_h_community_1, + &tigerlake_pch_h_community_2, + &tigerlake_pch_h_community_3, + &tigerlake_pch_h_community_4, + &tigerlake_pch_h_community_5, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 0a8431a329..460f3b1c6e 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -146,9 +146,24 @@ static const struct { "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP, "Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2, + "11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4, + "11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2, + "11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4, + "11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10D, "ICH10D" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10DO, "ICH10DO" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, @@ -266,6 +281,16 @@ static const struct { "Comet Point-LP U Premium/Cometlake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE, "Comet Point-LP U Base/Cometlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER, + "Tiger Point U Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM, + "Tiger Point U Premium/Tigerlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE, + "Tiger Point U Base/Tigerlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER, + "Tiger Point Y Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM, + "Tiger Point Y Premium/Tigerlake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, @@ -330,6 +355,17 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W580, "W580" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C256, "C256" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C252, "C252" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM570, "HM570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM580, "QM580" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM590, "WM590" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, "Intel(R) G35 Express Chipset Family" }, @@ -463,6 +499,18 @@ static const struct { "Intel(R) Iris Plus Graphics 655" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7, "Intel(R) Iris Plus Graphics G7" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_UY, + "Intel(R) Iris Xe Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_Y, + "Intel(R) Iris Xe Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1_2, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, "Intel(R) UHD Graphics" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 40b739f408..3c68b6671d 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -76,7 +76,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10DO 0x3a14 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 -#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 +#define PCI_DEVICE_ID_INTEL_ICH10 0x3a18 +#define PCI_DEVICE_ID_INTEL_ICH10D 0x3a1a #define PCI_DEVICE_ID_INTEL_3400_DESKTOP 0x3b00 #define PCI_DEVICE_ID_INTEL_3400_MOBILE 0x3b01 #define PCI_DEVICE_ID_INTEL_P55 0x3b02 @@ -148,6 +149,11 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -205,6 +211,18 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_HM370 0xa30d #define PCI_DEVICE_ID_INTEL_CM246 0xa30e +#define PCI_DEVICE_ID_INTEL_Q570 0x4384 +#define PCI_DEVICE_ID_INTEL_Z590 0x4385 +#define PCI_DEVICE_ID_INTEL_H570 0x4386 +#define PCI_DEVICE_ID_INTEL_B560 0x4387 +#define PCI_DEVICE_ID_INTEL_H510 0x4388 +#define PCI_DEVICE_ID_INTEL_WM590 0x4389 +#define PCI_DEVICE_ID_INTEL_QM580 0x438a +#define PCI_DEVICE_ID_INTEL_HM570 0x438b +#define PCI_DEVICE_ID_INTEL_C252 0x438c +#define PCI_DEVICE_ID_INTEL_C256 0x438d +#define PCI_DEVICE_ID_INTEL_W580 0x438f + #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -309,6 +327,13 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */ #define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */ #define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */ @@ -381,6 +406,12 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52 #define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70 #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 921fdf0445..590ae2c187 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -129,10 +129,26 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_Q570: + case PCI_DEVICE_ID_INTEL_Z590: + case PCI_DEVICE_ID_INTEL_H570: + case PCI_DEVICE_ID_INTEL_B560: + case PCI_DEVICE_ID_INTEL_H510: + case PCI_DEVICE_ID_INTEL_WM590: + case PCI_DEVICE_ID_INTEL_QM580: + case PCI_DEVICE_ID_INTEL_HM570: + case PCI_DEVICE_ID_INTEL_C252: + case PCI_DEVICE_ID_INTEL_C256: + case PCI_DEVICE_ID_INTEL_W580: case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: sbbar_phys = 0xfd000000; use_p2sb = false; break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index f4ebc5af6a..9e98809367 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -780,6 +780,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) pm_registers_size = ARRAY_SIZE(lynxpoint_lp_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index da9144a8d3..bdafa1ef55 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -29,6 +29,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index ad16cb8b9f..1bb5ba2727 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -107,6 +107,7 @@ static int print_bioscntl(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: @@ -259,6 +260,7 @@ static int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH10: + case PCI_DEVICE_ID_INTEL_ICH10D: case PCI_DEVICE_ID_INTEL_ICH10DO: case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: diff --git a/util/kconfig/conf.c b/util/kconfig/conf.c index 803447ae45..bc7b2f69e3 100644 --- a/util/kconfig/conf.c +++ b/util/kconfig/conf.c @@ -680,7 +680,7 @@ static void check_conf(struct menu *menu) check_conf(child); } -static struct option long_opts[] = { +static const struct option long_opts[] = { {"help", no_argument, NULL, 'h'}, {"silent", no_argument, NULL, 's'}, {"oldaskconfig", no_argument, &input_mode_opt, oldaskconfig}, diff --git a/util/kconfig/merge_config.sh b/util/kconfig/merge_config.sh index 63c8565206..e5b46980c2 100755 --- a/util/kconfig/merge_config.sh +++ b/util/kconfig/merge_config.sh @@ -28,6 +28,7 @@ usage() { echo " -r list redundant entries when merging fragments" echo " -y make builtin have precedence over modules" echo " -O dir to put generated output files. Consider setting \$KCONFIG_CONFIG instead." + echo " -s strict mode. Fail if the fragment redefines any value." echo echo "Used prefix: '$CONFIG_PREFIX'. You can redefine it with \$CONFIG_ environment variable." } @@ -37,6 +38,7 @@ ALLTARGET=alldefconfig WARNREDUN=false BUILTIN=false OUTPUT=. +STRICT=false CONFIG_PREFIX=${CONFIG_-CONFIG_} while true; do @@ -75,6 +77,11 @@ while true; do shift 2 continue ;; + "-s") + STRICT=true + shift + continue + ;; *) break ;; @@ -141,6 +148,9 @@ for ORIG_MERGE_FILE in $MERGE_LIST ; do echo Previous value: $PREV_VAL echo New value: $NEW_VAL echo + if [ "$STRICT" = "true" ]; then + STRICT_MODE_VIOLATED=true + fi elif [ "$WARNREDUN" = "true" ]; then echo Value of $CFG is redundant by fragment $ORIG_MERGE_FILE: fi @@ -153,6 +163,11 @@ for ORIG_MERGE_FILE in $MERGE_LIST ; do cat $MERGE_FILE >> $TMP_FILE done +if [ "$STRICT_MODE_VIOLATED" = "true" ]; then + echo "The fragment redefined a value and strict mode had been passed." + exit 1 +fi + if [ "$RUNMAKE" = "false" ]; then cp -T -- "$TMP_FILE" "$KCONFIG_CONFIG" echo "#" diff --git a/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch b/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch index 8442349941..931169d20a 100644 --- a/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch +++ b/util/kconfig/patches/0013-util-kconfig-detect-ncurses-on-FreeBSD.patch @@ -9,11 +9,11 @@ Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e util/kconfig/mconf-cfg.sh | 6 ++++++ 1 file changed, 6 insertions(+) -diff --git a/util/kconfig/mconf-cfg.sh b/util/kconfig/mconf-cfg.sh -index b520e407a8..2047e626b4 100755 ---- a/util/kconfig/mconf-cfg.sh -+++ b/util/kconfig/mconf-cfg.sh -@@ -33,6 +33,12 @@ if [ -f /usr/include/ncurses/ncurses.h ]; then +Index: kconfig/mconf-cfg.sh +=================================================================== +--- kconfig.orig/mconf-cfg.sh ++++ kconfig/mconf-cfg.sh +@@ -33,6 +33,12 @@ if [ -f /usr/include/ncurses/ncurses.h ] exit 0 fi @@ -26,6 +26,3 @@ index b520e407a8..2047e626b4 100755 # As a final fallback before giving up, check if $HOSTCC knows of a default # ncurses installation (e.g. from a vendor-specific sysroot). if echo '#include ' | ${HOSTCC} -E - >/dev/null 2>&1; then --- -2.31.1 - diff --git a/util/kconfig/streamline_config.pl b/util/kconfig/streamline_config.pl index 911c72a2db..1a5fea0519 100755 --- a/util/kconfig/streamline_config.pl +++ b/util/kconfig/streamline_config.pl @@ -601,12 +601,12 @@ if (defined($ENV{'LMC_KEEP'})) { sub in_preserved_kconfigs { my $kconfig = $config2kfile{$_[0]}; if (!defined($kconfig)) { - return 0; + return 0; } foreach my $excl (@preserved_kconfigs) { - if($kconfig =~ /^$excl/) { - return 1; - } + if($kconfig =~ /^$excl/) { + return 1; + } } return 0; } @@ -629,52 +629,52 @@ foreach my $line (@config_file) { } if (/CONFIG_MODULE_SIG_KEY="(.+)"/) { - my $orig_cert = $1; - my $default_cert = "certs/signing_key.pem"; + my $orig_cert = $1; + my $default_cert = "certs/signing_key.pem"; - # Check that the logic in this script still matches the one in Kconfig - if (!defined($depends{"MODULE_SIG_KEY"}) || - $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) { - print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ", - "update needed to ", __FILE__, " line ", __LINE__, "\n"; - print; - } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) { - print STDERR "Module signature verification enabled but ", - "module signing key \"$orig_cert\" not found. Resetting ", - "signing key to default value.\n"; - print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n"; - } else { - print; - } - next; + # Check that the logic in this script still matches the one in Kconfig + if (!defined($depends{"MODULE_SIG_KEY"}) || + $depends{"MODULE_SIG_KEY"} !~ /"\Q$default_cert\E"/) { + print STDERR "WARNING: MODULE_SIG_KEY assertion failure, ", + "update needed to ", __FILE__, " line ", __LINE__, "\n"; + print; + } elsif ($orig_cert ne $default_cert && ! -f $orig_cert) { + print STDERR "Module signature verification enabled but ", + "module signing key \"$orig_cert\" not found. Resetting ", + "signing key to default value.\n"; + print "CONFIG_MODULE_SIG_KEY=\"$default_cert\"\n"; + } else { + print; + } + next; } if (/CONFIG_SYSTEM_TRUSTED_KEYS="(.+)"/) { - my $orig_keys = $1; + my $orig_keys = $1; - if (! -f $orig_keys) { - print STDERR "System keyring enabled but keys \"$orig_keys\" ", - "not found. Resetting keys to default value.\n"; - print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n"; - } else { - print; - } - next; + if (! -f $orig_keys) { + print STDERR "System keyring enabled but keys \"$orig_keys\" ", + "not found. Resetting keys to default value.\n"; + print "CONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n"; + } else { + print; + } + next; } if (/^(CONFIG.*)=(m|y)/) { - if (in_preserved_kconfigs($1)) { - dprint "Preserve config $1"; - print; - next; - } + if (in_preserved_kconfigs($1)) { + dprint "Preserve config $1"; + print; + next; + } if (defined($configs{$1})) { if ($localyesconfig) { - $setconfigs{$1} = 'y'; + $setconfigs{$1} = 'y'; print "$1=y\n"; next; } else { - $setconfigs{$1} = $2; + $setconfigs{$1} = $2; } } elsif ($2 eq "m") { print "# $1 is not set\n"; @@ -702,3 +702,5 @@ foreach my $module (keys(%modules)) { print STDERR "\n"; } } + +# vim: softtabstop=4 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index f1c31c54c0..3cf249c4ed 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -42,6 +42,8 @@ my $list_types = 0; my $fix = 0; my $fix_inplace = 0; my $root = $P; #coreboot +my $gitroot = $ENV{'GIT_DIR'}; +$gitroot = ".git" if !defined($gitroot); my %debug; my %camelcase = (); my %use_type = (); @@ -62,7 +64,8 @@ my $conststructsfile = "$D/const_structs.checkpatch"; my $typedefsfile = ""; my $color = "auto"; my $allow_c99_comments = 1; - +my $git_command ='git'; # coreboot +my $tabsize = 8; # For coreboot jenkins # If taint mode is enabled, Untaint the path - files must be in /bin, /usr/bin or /usr/local/bin if ( ${^TAINT} ) { @@ -250,11 +253,11 @@ $check_orig = $check; my $exit = 0; +my $perl_version_ok = 1; if ($^V && $^V lt $minimum_perl_version) { + $perl_version_ok = 0; printf "$P: requires at least perl version %vd\n", $minimum_perl_version; - if (!$ignore_perl_version) { - exit(1); - } + exit(1) if (!$ignore_perl_version); } #if no filenames are given, push '-' to read patch from stdin @@ -867,8 +870,8 @@ sub seed_camelcase_includes { $camelcase_seeded = 1; - if (-e ".git") { - my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`; + if (-e "$gitroot") { + my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`; chomp $git_last_include_commit; $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; } else { @@ -895,8 +898,8 @@ sub seed_camelcase_includes { return; } - if (-e ".git") { - $files = `git ls-files "include/*.h"`; + if (-e "$gitroot") { + $files = `${git_command} ls-files "include/*.h"`; @include_files = split('\n', $files); } @@ -918,9 +921,9 @@ sub seed_camelcase_includes { sub git_commit_info { my ($commit, $id, $desc) = @_; - return ($id, $desc) if ((which("git") eq "") || !(-e ".git")); + return ($id, $desc) if ((which("git") eq "") || !(-e "$gitroot")); - my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`; + my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`; $output =~ s/^\s*//gm; my @lines = split("\n", $output); @@ -957,7 +960,7 @@ my $fixlinenr = -1; # If input is git commits, extract all commits from the commit expressions. # For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'. -die "$P: No git repository found\n" if ($git && !-e ".git"); +die "$P: No git repository found\n" if ($git && !-e "$gitroot"); if ($git) { my @commits = (); @@ -970,7 +973,7 @@ if ($git) { } else { $git_range = "-1 $commit_expr"; } - my $lines = `git log --no-color --no-merges --pretty=format:'%H %s' $git_range`; + my $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`; foreach my $line (split(/\n/, $lines)) { $line =~ /^([0-9a-fA-F]{40,40}) (.*)$/; next if (!defined($1) || !defined($2)); @@ -1040,11 +1043,11 @@ if (!$quiet) { hash_show_words(\%use_type, "Used"); hash_show_words(\%ignore_type, "Ignored"); - if ($^V lt 5.10.0) { + if (!$perl_version_ok) { print << "EOM" NOTE: perl $^V is not modern enough to detect all possible issues. - An upgrade to at least perl v5.10.0 is suggested. + An upgrade to at least perl $minimum_perl_version is suggested. EOM } if ($exit) { @@ -1178,7 +1181,7 @@ sub expand_tabs { if ($c eq "\t") { $res .= ' '; $n++; - for (; ($n % 8) != 0; $n++) { + for (; ($n % $tabsize) != 0; $n++) { $res .= ' '; } next; @@ -2199,7 +2202,7 @@ sub string_find_replace { sub tabify { my ($leading) = @_; - my $source_indent = 8; + my $source_indent = $tabsize; my $max_spaces_before_tab = $source_indent - 1; my $spaces_to_tab = " " x $source_indent; @@ -2655,18 +2658,19 @@ sub process { $commit_log_possible_stack_dump = 1; } -# Check for line lengths > 75 in commit log, warn once +# coreboot: The line lengeth limit is 72 +# Check for line lengths > 72 in commit log, warn once if ($in_commit_log && !$commit_log_long_line && - length($line) > 75 && + length($line) > 72 && !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ || # file delta changes - $line =~ /^\s*(?:[\w\.\-]+\/)++[\w\.\-]+:/ || + $line =~ /^\s*(?:[\w\.\-\+]*\/)++[\w\.\-\+]+:/ || # filename then : - $line =~ /^\s*(?:Fixes:|Link:)/i || - # A Fixes: or Link: line + $line =~ /^\s*(?:Fixes:|Link:|$signature_tags)/i || + # A Fixes: or Link: line or signature tag line $commit_log_possible_stack_dump)) { WARN("COMMIT_LOG_LONG_LINE", - "Possible unwrapped commit description (prefer a maximum 75 chars per line)\n" . $herecurr); + "Possible unwrapped commit description (prefer a maximum 72 chars per line)\n" . $herecurr); $commit_log_long_line = 1; } @@ -3074,7 +3078,7 @@ sub process { next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); # at the beginning of a line any tabs must come first and anything -# more than 8 must use tabs. +# more than $tabsize must use tabs. if ($rawline =~ /^\+\s* \t\s*\S/ || $rawline =~ /^\+\s* \s*/) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; @@ -3093,7 +3097,7 @@ sub process { "please, no space before tabs\n" . $herevet) && $fix) { while ($fixed[$fixlinenr] =~ - s/(^\+.*) {8,8}\t/$1\t\t/) {} + s/(^\+.*) {$tabsize,$tabsize}\t/$1\t\t/) {} while ($fixed[$fixlinenr] =~ s/(^\+.*) +\t/$1\t/) {} } @@ -3112,20 +3116,20 @@ sub process { } # check indentation starts on a tab stop - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) { my $indent = length($1); - if ($indent % 8) { + if ($indent % $tabsize) { if (WARN("TABSTOP", "Statements should start on a tabstop\n" . $herecurr) && $fix) { - $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/8)@e; + $fixed[$fixlinenr] =~ s@(^\+\t+) +@$1 . "\t" x ($indent/$tabsize)@e; } } } # check multi-line statement indentation matches previous line - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|(?:\*\s*)*$Lval\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) { $prevline =~ /^\+(\t*)(.*)$/; my $oldindent = $1; @@ -3137,8 +3141,8 @@ sub process { my $newindent = $2; my $goodtabindent = $oldindent . - "\t" x ($pos / 8) . - " " x ($pos % 8); + "\t" x ($pos / $tabsize) . + " " x ($pos % $tabsize); my $goodspaceindent = $oldindent . " " x $pos; if ($newindent ne $goodtabindent && @@ -3258,43 +3262,48 @@ sub process { } # check for missing blank lines after declarations - if ($sline =~ /^\+\s+\S/ && #Not at char 1 - # actual declarations - ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || +# (declarations must have the same indentation and not be at the start of line) + if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) { + # use temporaries + my $sl = $sline; + my $pl = $prevline; + # remove $Attribute/$Sparse uses to simplify comparisons + $sl =~ s/\b(?:$Attribute|$Sparse)\b//g; + $pl =~ s/\b(?:$Attribute|$Sparse)\b//g; + if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || # function pointer declarations - $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || # foo bar; where foo is some local typedef or #define - $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || # known declaration macros - $prevline =~ /^\+\s+$declaration_macros/) && + $pl =~ /^\+\s+$declaration_macros/) && # for "else if" which can look like "$Ident $Ident" - !($prevline =~ /^\+\s+$c90_Keywords\b/ || + !($pl =~ /^\+\s+$c90_Keywords\b/ || # other possible extensions of declaration lines - $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + $pl =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || # not starting a section or a macro "\" extended line - $prevline =~ /(?:\{\s*|\\)$/) && + $pl =~ /(?:\{\s*|\\)$/) && # looks like a declaration - !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || # function pointer declarations - $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || # foo bar; where foo is some local typedef or #define - $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || # known declaration macros - $sline =~ /^\+\s+$declaration_macros/ || + $sl =~ /^\+\s+$declaration_macros/ || # start of struct or union or enum - $sline =~ /^\+\s+(?:union|struct|enum|typedef)\b/ || + $sl =~ /^\+\s+(?:static\s+)?(?:const\s+)?(?:union|struct|enum|typedef)\b/ || # start or end of block or continuation of declaration - $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + $sl =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || # bitfield continuation - $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + $sl =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || # other possible extensions of declaration lines - $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) && - # indentation of previous and current line are the same - (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) { - if (WARN("LINE_SPACING", - "Missing a blank line after declarations\n" . $hereprev) && - $fix) { - fix_insert_line($fixlinenr, "\+"); + $sl =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/)) { + if (WARN("LINE_SPACING", + "Missing a blank line after declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } } } @@ -3609,11 +3618,11 @@ sub process { #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; if ($check && $s ne '' && - (($sindent % 8) != 0 || + (($sindent % $tabsize) != 0 || ($sindent < $indent) || ($sindent == $indent && ($s !~ /^\s*(?:\}|\{|else\b)/)) || - ($sindent > $indent + 8))) { + ($sindent > $indent + $tabsize))) { WARN("SUSPECT_CODE_INDENT", "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); } @@ -3870,7 +3879,7 @@ sub process { WARN("STATIC_CONST_CHAR_ARRAY", "static char array declaration should probably be static const char\n" . $herecurr); - } + } # check for const const where is not a pointer or array type if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) { @@ -3889,7 +3898,7 @@ sub process { WARN("STATIC_CONST_CHAR_ARRAY", "char * array declaration might be better as static const\n" . $herecurr); - } + } # check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo) if ($line =~ m@\bsizeof\s*\(\s*($Lval)\s*\)@) { @@ -4044,7 +4053,7 @@ sub process { # function brace can't be on same line, except for #defines of do while, # or if closed on same line - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $sline =~ /$Type\s*$Ident\s*$balanced_parens\s*\{/ && $sline !~ /\#\s*define\b.*do\s*\{/ && $sline !~ /}/) { @@ -4483,7 +4492,7 @@ sub process { ($op eq '>' && $ca =~ /<\S+\@\S+$/)) { - $ok = 1; + $ok = 1; } # for asm volatile statements @@ -4549,7 +4558,7 @@ sub process { ## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { ## ## # Remove any bracketed sections to ensure we do not -## # falsly report the parameters of functions. +## # falsely report the parameters of functions. ## my $ln = $line; ## while ($ln =~ s/\([^\(\)]*\)//g) { ## } @@ -4657,7 +4666,7 @@ sub process { # check for unnecessary parentheses around comparisons in if uses # when !drivers/staging or command-line uses --strict if (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) && - $^V && $^V ge 5.10.0 && defined($stat) && + $perl_version_ok && defined($stat) && $stat =~ /(^.\s*if\s*($balanced_parens))/) { my $if_stat = $1; my $test = substr($2, 1, -1); @@ -4694,7 +4703,7 @@ sub process { # return is not a function if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { my $spacing = $1; - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) { my $value = $1; $value = deparenthesize($value); @@ -4718,10 +4727,10 @@ sub process { $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { WARN("RETURN_VOID", "void function return statements are not generally useful\n" . $hereprev); - } + } # if statements using unnecessary parentheses - ie: if ((foo == bar)) - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /\bif\s*((?:\(\s*){2,})/) { my $openparens = $1; my $count = $openparens =~ tr@\(@\(@; @@ -4738,7 +4747,7 @@ sub process { # avoid cases like "foo + BAR < baz" # only fix matches surrounded by parentheses to avoid incorrect # conversions like "FOO < baz() + 5" being "misfixed" to "baz() > FOO + 5" - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /^\+(.*)\b($Constant|[A-Z_][A-Z0-9_]*)\s*($Compare)\s*($LvalOrFunc)/) { my $lead = $1; my $const = $2; @@ -4819,7 +4828,7 @@ sub process { # conditional. substr($s, 0, length($c), ''); $s =~ s/\n.*//g; - $s =~ s/$;//g; # Remove any comments + $s =~ s/$;//g; # Remove any comments if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && $c !~ /}\s*while\s*/) { @@ -4858,7 +4867,7 @@ sub process { # if and else should not have general statements after it if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { my $s = $1; - $s =~ s/$;//g; # Remove any comments + $s =~ s/$;//g; # Remove any comments if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { ERROR("TRAILING_STATEMENTS", "trailing statements should be on next line\n" . $herecurr); @@ -5043,7 +5052,7 @@ sub process { { } - # Flatten any obvious string concatentation. + # Flatten any obvious string concatenation. while ($dstat =~ s/($String)\s*$Ident/$1/ || $dstat =~ s/$Ident\s*($String)/$1/) { @@ -5163,7 +5172,7 @@ sub process { # do {} while (0) macro tests: # single-statement macros do not need to be enclosed in do while (0) loop, # macro should not end with a semicolon - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $realfile !~ m@/vmlinux.lds.h$@ && $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { my $ln = $linenr; @@ -5526,7 +5535,7 @@ sub process { } # check for mask then right shift without a parentheses - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /$LvalOrFunc\s*\&\s*($LvalOrFunc)\s*>>/ && $4 !~ /^\&/) { # $LvalOrFunc may be &foo, ignore if so WARN("MASK_THEN_SHIFT", @@ -5534,7 +5543,7 @@ sub process { } # check for pointer comparisons to NULL - if ($^V && $^V ge 5.10.0) { + if ($perl_version_ok) { while ($line =~ /\b$LvalOrFunc\s*(==|\!=)\s*NULL\b/g) { my $val = $1; my $equal = "!"; @@ -5806,7 +5815,7 @@ sub process { } # Check for __attribute__ weak, or __weak declarations (may have link issues) - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /(?:$Declare|$DeclareMisordered)\s*$Ident\s*$balanced_parens\s*(?:$Attribute)?\s*;/ && ($line =~ /\b__attribute__\s*\(\s*\(.*\bweak\b/ || $line =~ /\b__weak\b/)) { @@ -5888,7 +5897,7 @@ sub process { } # check for vsprintf extension %p misuses - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s && $1 !~ /^_*volatile_*$/) { @@ -5935,7 +5944,7 @@ sub process { } # Check for misused memsets - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/) { @@ -5953,7 +5962,7 @@ sub process { } # Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) -# if ($^V && $^V ge 5.10.0 && +# if ($perl_version_ok && # defined $stat && # $stat =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { # if (WARN("PREFER_ETHER_ADDR_COPY", @@ -5964,7 +5973,7 @@ sub process { # } # Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar) -# if ($^V && $^V ge 5.10.0 && +# if ($perl_version_ok && # defined $stat && # $stat =~ /^\+(?:.*?)\bmemcmp\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { # WARN("PREFER_ETHER_ADDR_EQUAL", @@ -5973,7 +5982,7 @@ sub process { # check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr # check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr -# if ($^V && $^V ge 5.10.0 && +# if ($perl_version_ok && # defined $stat && # $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/) { # @@ -5995,7 +6004,7 @@ sub process { # } # typecasts on min/max could be min_t/max_t - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { if (defined $2 || defined $7) { @@ -6019,7 +6028,7 @@ sub process { } # check usleep_range arguments - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { my $min = $1; @@ -6035,7 +6044,7 @@ sub process { } # check for naked sscanf - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $line =~ /\bsscanf\b/ && ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && @@ -6049,7 +6058,7 @@ sub process { } # check for simple sscanf that should be kstrto - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $line =~ /\bsscanf\b/) { my $lc = $stat =~ tr@\n@@; @@ -6121,7 +6130,7 @@ sub process { } # check for function definitions - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^.\s*(?:$Storage\s+)?$Type\s*($Ident)\s*$balanced_parens\s*{/s) { $context_function = $1; @@ -6161,14 +6170,14 @@ sub process { # alloc style # p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { CHK("ALLOC_SIZEOF_STRUCT", "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); } # check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+\s*($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { my $oldfunc = $3; @@ -6197,7 +6206,7 @@ sub process { } # check for krealloc arg reuse - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { WARN("KREALLOC_ARG_REUSE", "Reusing the krealloc arg is almost always a bug\n" . $herecurr); @@ -6256,7 +6265,7 @@ sub process { } # check for switch/default statements without a break; - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { my $cnt = statement_rawlines($stat); @@ -6366,7 +6375,7 @@ sub process { } # likely/unlikely comparisons similar to "(likely(foo) > 0)" - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && $line =~ /\b((?:un)?likely)\s*\(\s*$FuncArg\s*\)\s*$Compare/) { WARN("LIKELY_MISUSE", "Using $1 should generally have parentheses around the comparison\n" . $herecurr); @@ -6409,7 +6418,7 @@ sub process { # check for DEVICE_ATTR uses that could be DEVICE_ATTR_ # and whether or not function naming is typical and if # DEVICE_ATTR permissions uses are unusual too - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $stat =~ /\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?\s*(\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\s*)\s*\)?\s*,\s*(\w+)\s*,\s*(\w+)\s*\)/) { my $var = $1; @@ -6469,7 +6478,7 @@ sub process { # specific definition of not visible in sysfs. # o Ignore proc_create*(...) uses with a decimal 0 permission as that means # use the default permissions - if ($^V && $^V ge 5.10.0 && + if ($perl_version_ok && defined $stat && $line =~ /$mode_perms_search/) { foreach my $entry (@mode_permission_funcs) { @@ -6545,7 +6554,7 @@ sub process { exit(0); } - # This is not a patch, and we are are in 'no-patch' mode so + # This is not a patch, and we are in 'no-patch' mode so # just keep quiet. if (!$chk_patch && !$is_patch) { exit(0); diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index a3495ce2bf..32bf92dc4d 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1312,7 +1312,7 @@ sub print_wholeconfig { return unless $print_full_output; - for ( my $i = 0 ; $i < $#wholeconfig ; $i++ ) { + for ( my $i = 0 ; $i <= $#wholeconfig ; $i++ ) { my $line = $wholeconfig[$i]; chop( $line->{text} ); diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index 7a76878f60..d7443b3b2c 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -11,6 +11,7 @@ INCLUDED_FILES='.*\.[ch]\|Kconfig.*$' EXCLUDED_DIRS="^payloads/libpayload/util/kconfig\|\ ^payloads/libpayload/curses/PDCurses\|\ +^util/coreboot-configurator\|\ ^util/crossgcc/patches\|\ ^util/inteltool\|\ ^util/kconfig\|\ diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines index 3ab0fbfbc9..55b48cf644 100755 --- a/util/lint/lint-extended-015-final-newlines +++ b/util/lint/lint-extended-015-final-newlines @@ -9,7 +9,7 @@ LC_ALL=C export LC_ALL PIDS="" INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc' EXCLUDED_DIRS='src/vendorcode/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/' -EXCLUDED_FILES='\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$' +EXCLUDED_FILES='\.gif$\|\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$' # Use git ls-files if the code is in a git repo, otherwise use find. if [ -n "$(command -v git)" ] && \ diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index fd4d0e4d12..6f9d78849a 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -5,7 +5,7 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$' +EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.gif$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$' INCLUDELIST="src util payloads Makefile* toolchain.inc tests" # shellcheck disable=SC2086,SC2046 diff --git a/util/liveiso/build-console.sh b/util/liveiso/build-console.sh deleted file mode 100755 index ced2ca748c..0000000000 --- a/util/liveiso/build-console.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/usr/bin/env sh - -nix-build '' -A config.system.build.isoImage -I nixos-config=console.nix diff --git a/util/liveiso/build-graphical.sh b/util/liveiso/build-graphical.sh deleted file mode 100755 index 8e794787a1..0000000000 --- a/util/liveiso/build-graphical.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/usr/bin/env sh - -nix-build '' -A config.system.build.isoImage -I nixos-config=graphical.nix diff --git a/util/liveiso/build.sh b/util/liveiso/build.sh new file mode 100755 index 0000000000..702ace88cc --- /dev/null +++ b/util/liveiso/build.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env sh + +config=$1 + +if [ -z "$config" ] || [ ! -f "$config" ]; then + echo "Usage: $0 " + echo "No config given. Exiting." + exit 1 +fi + +nix-build '' \ + -A config.system.build.isoImage \ + -I nixos-config=$config \ + -I nixpkgs=https://github.com/NixOS/nixpkgs/archive/refs/heads/nixos-21.11.tar.gz diff --git a/util/liveiso/common.nix b/util/liveiso/common.nix index 3961aba488..881c5b84e2 100644 --- a/util/liveiso/common.nix +++ b/util/liveiso/common.nix @@ -8,7 +8,7 @@ ]; - system.stateVersion = "21.05"; + system.stateVersion = "21.11"; isoImage = { makeEfiBootable = true; @@ -33,6 +33,7 @@ "console=ttyS0,115200" "console=tty0" "iomem=relaxed" + "intel-spi.writeable=1" ]; # pkgs.linuxPackages == lts # pkgs.linuxPackages_latest == stable @@ -92,12 +93,14 @@ user = { isNormalUser = true; group = "user"; - extraGroups = [ "users" "wheel" "networkmanager" "uucp" ]; + extraGroups = [ "users" "wheel" "networkmanager" "uucp" "flashrom" ]; initialHashedPassword = ""; }; }; }; + programs.flashrom.enable = true; + environment.systemPackages = with pkgs; [ acpica-tools btrfs-progs @@ -115,7 +118,6 @@ efivar exfat f2fs-tools - flashrom fuse fuse3 fwts @@ -127,7 +129,6 @@ hexdump htop i2c-tools - iasl intel-gpu-tools inxi iotools @@ -138,6 +139,7 @@ mkpasswd ms-sys msr-tools + mtdutils neovim nixos-install-tools ntfsprogs diff --git a/util/liveiso/description.md b/util/liveiso/description.md index a9e2eb8b87..b056a9f313 100644 --- a/util/liveiso/description.md +++ b/util/liveiso/description.md @@ -5,8 +5,6 @@ NixOS configuration files for testing purposes and for working on firmware. ## TODO -- Use programs.flashrom.enable (#128205) and add `user` to `flashrom` group. - Will be usable from the next NixOS release. - Generate customized bootloader configs; FILO is WIP - Add coreboot toolchain - Switch to `programs.neovim` when the module is fixed. diff --git a/util/mainboard/google/brask/template/include/variant/ec.h b/util/mainboard/google/brask/template/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/util/mainboard/google/brask/template/include/variant/gpio.h b/util/mainboard/google/brask/template/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#endif diff --git a/util/mainboard/google/brask/template/overridetree.cb b/util/mainboard/google/brask/template/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/util/mainboard/google/brask/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/util/mainboard/google/brya0/template/memory/Makefile.inc b/util/mainboard/google/brya0/template/memory/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/brya0/template/memory/Makefile.inc +++ b/util/mainboard/google/brya0/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/dalboz/template/spd/Makefile.inc b/util/mainboard/google/dalboz/template/spd/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/dalboz/template/spd/Makefile.inc +++ b/util/mainboard/google/dalboz/template/spd/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/guybrush/template/memory/Makefile.inc b/util/mainboard/google/guybrush/template/memory/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/guybrush/template/memory/Makefile.inc +++ b/util/mainboard/google/guybrush/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/trembyle/template/spd/Makefile.inc b/util/mainboard/google/trembyle/template/spd/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/trembyle/template/spd/Makefile.inc +++ b/util/mainboard/google/trembyle/template/spd/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/volteer/template/memory/Makefile.inc b/util/mainboard/google/volteer/template/memory/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/volteer/template/memory/Makefile.inc +++ b/util/mainboard/google/volteer/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/waddledee/template/memory/Makefile.inc b/util/mainboard/google/waddledee/template/memory/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/waddledee/template/memory/Makefile.inc +++ b/util/mainboard/google/waddledee/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/mainboard/google/waddledoo/template/memory/Makefile.inc b/util/mainboard/google/waddledoo/template/memory/Makefile.inc index 6751a4283f..eace2e443e 100644 --- a/util/mainboard/google/waddledoo/template/memory/Makefile.inc +++ b/util/mainboard/google/waddledoo/template/memory/Makefile.inc @@ -1,5 +1,5 @@ -## SPDX-License-Identifier: GPL-2.0-or-later -## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. SPD_SOURCES = placeholder diff --git a/util/nixshell/documentation.nix b/util/nixshell/documentation.nix new file mode 100644 index 0000000000..595e94a122 --- /dev/null +++ b/util/nixshell/documentation.nix @@ -0,0 +1,13 @@ +with import {}; + +stdenvNoCC.mkDerivation { + name = "coreboot-documentation"; + + buildInputs = [ + git + gnumake + python3Packages.recommonmark + python3Packages.sphinx_rtd_theme + sphinx + ]; +} diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 07cb64b60f..647ec3d796 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ static void yynoreturn yy_fatal_error ( const char* msg ); (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 49 -#define YY_END_OF_BUFFER 50 +#define YY_NUM_RULES 50 +#define YY_END_OF_BUFFER 51 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,31 +358,31 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[202] = +static const flex_int16_t yy_accept[210] = { 0, - 0, 0, 50, 48, 1, 3, 48, 48, 48, 43, - 43, 40, 44, 48, 44, 44, 44, 44, 44, 48, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 41, - 48, 1, 3, 48, 0, 48, 48, 0, 2, 43, - 44, 48, 48, 48, 9, 48, 48, 44, 48, 48, - 48, 48, 48, 48, 48, 48, 48, 48, 34, 48, - 48, 48, 48, 48, 15, 48, 48, 48, 48, 48, - 48, 48, 48, 48, 47, 47, 48, 0, 42, 48, - 48, 48, 25, 48, 48, 33, 38, 48, 48, 48, - 48, 48, 22, 48, 48, 32, 48, 48, 48, 16, + 0, 0, 51, 49, 1, 3, 49, 49, 49, 44, + 44, 41, 45, 49, 45, 45, 45, 45, 45, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 42, + 49, 1, 3, 49, 0, 49, 49, 0, 2, 44, + 45, 49, 49, 49, 9, 49, 49, 45, 49, 49, + 49, 49, 49, 49, 49, 49, 49, 49, 34, 49, + 49, 49, 49, 49, 15, 49, 49, 49, 49, 49, + 49, 49, 49, 49, 48, 48, 49, 0, 43, 49, + 49, 49, 25, 49, 49, 33, 38, 49, 49, 49, + 49, 49, 22, 49, 49, 32, 49, 49, 49, 16, - 48, 19, 21, 48, 8, 48, 48, 29, 48, 30, - 7, 48, 0, 45, 48, 4, 48, 48, 48, 48, - 48, 48, 31, 48, 48, 48, 48, 48, 28, 48, - 48, 48, 48, 48, 46, 46, 6, 48, 48, 48, - 12, 48, 48, 48, 48, 48, 23, 48, 48, 14, - 48, 48, 48, 48, 5, 26, 48, 48, 17, 48, - 20, 48, 13, 48, 48, 48, 48, 48, 27, 36, - 48, 48, 48, 48, 48, 48, 48, 48, 48, 10, - 48, 48, 48, 11, 48, 18, 48, 48, 48, 35, - 48, 48, 24, 48, 37, 48, 48, 48, 48, 39, + 49, 19, 21, 49, 8, 49, 49, 29, 49, 30, + 7, 49, 0, 46, 49, 4, 49, 49, 49, 49, + 49, 49, 31, 49, 49, 49, 49, 49, 28, 49, + 49, 49, 49, 49, 47, 47, 6, 49, 49, 49, + 12, 49, 49, 49, 49, 49, 23, 49, 49, 14, + 49, 49, 49, 49, 5, 26, 49, 49, 17, 49, + 20, 49, 13, 49, 49, 49, 49, 49, 27, 36, + 49, 49, 49, 49, 49, 49, 49, 49, 49, 10, + 49, 49, 49, 49, 11, 49, 18, 49, 49, 49, + 49, 35, 49, 49, 49, 24, 49, 49, 37, 49, - 0 + 49, 49, 49, 49, 49, 40, 49, 39, 0 } ; static const YY_CHAR yy_ec[256] = @@ -425,136 +425,140 @@ static const YY_CHAR yy_meta[41] = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[209] = +static const flex_int16_t yy_base[217] = { 0, - 0, 0, 274, 0, 271, 275, 269, 39, 43, 40, - 233, 0, 46, 256, 56, 60, 64, 67, 72, 56, - 244, 74, 251, 39, 70, 59, 246, 77, 233, 0, - 0, 263, 275, 108, 259, 112, 116, 260, 275, 0, - 113, 116, 247, 236, 0, 235, 224, 122, 231, 226, - 236, 234, 238, 225, 227, 231, 231, 225, 231, 216, - 216, 217, 219, 221, 0, 208, 216, 210, 210, 117, - 220, 212, 218, 87, 0, 275, 139, 230, 0, 223, - 216, 202, 215, 205, 212, 0, 0, 202, 208, 205, - 196, 204, 0, 202, 192, 0, 196, 200, 190, 0, + 0, 0, 282, 0, 279, 283, 277, 39, 43, 40, + 241, 0, 46, 264, 56, 60, 64, 67, 72, 56, + 252, 74, 259, 39, 70, 59, 254, 77, 241, 0, + 0, 271, 283, 108, 267, 112, 116, 268, 283, 0, + 113, 116, 255, 244, 0, 243, 232, 122, 239, 234, + 244, 242, 246, 233, 235, 239, 239, 233, 239, 224, + 224, 225, 227, 229, 0, 216, 224, 218, 218, 117, + 228, 220, 226, 87, 0, 283, 139, 238, 0, 231, + 224, 210, 223, 213, 220, 0, 0, 210, 216, 213, + 204, 212, 0, 210, 200, 0, 204, 208, 198, 0, - 193, 0, 0, 199, 0, 191, 190, 0, 181, 0, - 0, 208, 207, 0, 178, 0, 191, 190, 183, 187, - 177, 173, 0, 183, 171, 177, 182, 183, 0, 170, - 177, 164, 167, 156, 0, 275, 0, 168, 172, 164, - 0, 163, 165, 161, 163, 168, 0, 152, 157, 0, - 150, 150, 149, 146, 0, 0, 158, 160, 0, 144, - 161, 147, 0, 154, 158, 139, 139, 146, 0, 0, - 132, 124, 123, 121, 132, 118, 128, 118, 110, 0, - 122, 120, 125, 0, 114, 0, 114, 107, 94, 0, - 82, 81, 0, 83, 0, 74, 67, 37, 31, 0, + 201, 0, 0, 207, 0, 199, 198, 0, 189, 0, + 0, 216, 215, 0, 186, 0, 199, 198, 191, 195, + 185, 181, 0, 191, 179, 185, 190, 191, 0, 178, + 185, 172, 175, 164, 0, 283, 0, 176, 180, 172, + 0, 171, 173, 169, 171, 176, 0, 160, 165, 0, + 158, 158, 157, 154, 0, 0, 166, 168, 0, 152, + 169, 155, 0, 162, 166, 147, 147, 154, 0, 0, + 153, 145, 144, 68, 154, 140, 150, 140, 132, 0, + 136, 130, 128, 133, 0, 122, 0, 116, 122, 125, + 117, 0, 132, 113, 126, 0, 120, 127, 0, 104, - 275, 42, 158, 160, 162, 164, 166, 168 + 106, 94, 78, 65, 37, 0, 31, 0, 283, 42, + 158, 160, 162, 164, 166, 168 } ; -static const flex_int16_t yy_def[209] = +static const flex_int16_t yy_def[217] = { 0, - 201, 1, 201, 202, 201, 201, 202, 203, 204, 202, - 10, 202, 10, 202, 10, 10, 10, 10, 10, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 201, 201, 203, 205, 206, 204, 207, 201, 10, - 10, 10, 202, 202, 202, 202, 202, 10, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 206, 208, 42, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 209, 1, 209, 210, 209, 209, 210, 211, 212, 210, + 10, 210, 10, 210, 10, 10, 10, 10, 10, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 209, 209, 211, 213, 214, 212, 215, 209, 10, + 10, 10, 210, 210, 210, 210, 210, 10, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 209, 214, 216, 42, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 201, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 209, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 209, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 210, 210, 210, 210, 210, - 0, 201, 201, 201, 201, 201, 201, 201 + 210, 210, 210, 210, 210, 210, 210, 210, 0, 209, + 209, 209, 209, 209, 209, 209 } ; -static const flex_int16_t yy_nxt[316] = +static const flex_int16_t yy_nxt[324] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 15, 13, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4, 25, 26, 4, 27, 28, 4, 29, 4, 4, 4, 4, 30, - 35, 35, 31, 36, 38, 39, 40, 40, 40, 200, + 35, 35, 31, 36, 38, 39, 40, 40, 40, 208, 41, 41, 41, 41, 41, 62, 41, 41, 41, 41, - 41, 41, 41, 41, 41, 63, 41, 41, 41, 199, + 41, 41, 41, 41, 41, 63, 41, 41, 41, 207, 41, 41, 41, 41, 41, 41, 54, 67, 41, 41, - 41, 44, 57, 46, 48, 55, 68, 198, 45, 47, - 69, 64, 49, 197, 51, 50, 52, 65, 196, 66, + 41, 44, 57, 46, 48, 55, 68, 181, 45, 47, + 69, 64, 49, 206, 51, 50, 52, 65, 205, 66, - 195, 58, 59, 71, 110, 60, 72, 111, 53, 35, - 35, 73, 75, 78, 78, 194, 31, 38, 39, 41, - 41, 41, 79, 79, 79, 193, 79, 79, 41, 41, - 41, 192, 79, 79, 79, 79, 79, 79, 105, 106, - 78, 78, 191, 112, 190, 189, 188, 187, 186, 185, - 184, 183, 182, 181, 180, 179, 178, 84, 34, 34, + 182, 58, 59, 71, 110, 60, 72, 111, 53, 35, + 35, 73, 75, 78, 78, 204, 31, 38, 39, 41, + 41, 41, 79, 79, 79, 203, 79, 79, 41, 41, + 41, 202, 79, 79, 79, 79, 79, 79, 105, 106, + 78, 78, 201, 112, 200, 199, 198, 197, 196, 195, + 194, 193, 192, 191, 190, 189, 188, 84, 34, 34, 37, 37, 35, 35, 77, 77, 38, 38, 78, 78, - 177, 176, 175, 174, 173, 172, 171, 170, 169, 168, - 167, 166, 165, 164, 163, 162, 161, 160, 159, 158, - 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, + 187, 186, 185, 184, 183, 180, 179, 178, 177, 176, + 175, 174, 173, 172, 171, 170, 169, 168, 167, 166, + 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, - 147, 146, 145, 144, 143, 142, 141, 140, 139, 138, - 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, - 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, - 117, 116, 115, 114, 113, 109, 108, 107, 104, 103, - 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, - 92, 91, 90, 89, 88, 87, 86, 85, 83, 82, - 81, 80, 39, 76, 32, 74, 70, 61, 56, 43, - 42, 33, 32, 201, 3, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, + 145, 144, 143, 142, 141, 140, 139, 138, 137, 136, + 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, + 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, + 115, 114, 113, 109, 108, 107, 104, 103, 102, 101, + 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, + 90, 89, 88, 87, 86, 85, 83, 82, 81, 80, + 39, 76, 32, 74, 70, 61, 56, 43, 42, 33, + 32, 209, 3, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201 + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209 } ; -static const flex_int16_t yy_chk[316] = +static const flex_int16_t yy_chk[324] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 8, 8, 202, 8, 9, 9, 10, 10, 10, 199, + 8, 8, 210, 8, 9, 9, 10, 10, 10, 207, 10, 10, 13, 13, 13, 24, 10, 10, 10, 10, - 10, 10, 15, 15, 15, 24, 16, 16, 16, 198, + 10, 10, 15, 15, 15, 24, 16, 16, 16, 205, 17, 17, 17, 18, 18, 18, 20, 26, 19, 19, - 19, 15, 22, 16, 17, 20, 26, 197, 15, 16, - 26, 25, 17, 196, 18, 17, 19, 25, 194, 25, + 19, 15, 22, 16, 17, 20, 26, 174, 15, 16, + 26, 25, 17, 204, 18, 17, 19, 25, 203, 25, - 192, 22, 22, 28, 74, 22, 28, 74, 19, 34, - 34, 28, 34, 36, 36, 191, 36, 37, 37, 41, - 41, 41, 42, 42, 42, 189, 42, 42, 48, 48, - 48, 188, 42, 42, 42, 42, 42, 42, 70, 70, - 77, 77, 187, 77, 185, 183, 182, 181, 179, 178, - 177, 176, 175, 174, 173, 172, 171, 48, 203, 203, - 204, 204, 205, 205, 206, 206, 207, 207, 208, 208, - 168, 167, 166, 165, 164, 162, 161, 160, 158, 157, - 154, 153, 152, 151, 149, 148, 146, 145, 144, 143, - 142, 140, 139, 138, 134, 133, 132, 131, 130, 128, + 174, 22, 22, 28, 74, 22, 28, 74, 19, 34, + 34, 28, 34, 36, 36, 202, 36, 37, 37, 41, + 41, 41, 42, 42, 42, 201, 42, 42, 48, 48, + 48, 200, 42, 42, 42, 42, 42, 42, 70, 70, + 77, 77, 198, 77, 197, 195, 194, 193, 191, 190, + 189, 188, 186, 184, 183, 182, 181, 48, 211, 211, + 212, 212, 213, 213, 214, 214, 215, 215, 216, 216, + 179, 178, 177, 176, 175, 173, 172, 171, 168, 167, + 166, 165, 164, 162, 161, 160, 158, 157, 154, 153, + 152, 151, 149, 148, 146, 145, 144, 143, 142, 140, - 127, 126, 125, 124, 122, 121, 120, 119, 118, 117, - 115, 113, 112, 109, 107, 106, 104, 101, 99, 98, - 97, 95, 94, 92, 91, 90, 89, 88, 85, 84, - 83, 82, 81, 80, 78, 73, 72, 71, 69, 68, - 67, 66, 64, 63, 62, 61, 60, 59, 58, 57, - 56, 55, 54, 53, 52, 51, 50, 49, 47, 46, - 44, 43, 38, 35, 32, 29, 27, 23, 21, 14, - 11, 7, 5, 3, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 139, 138, 134, 133, 132, 131, 130, 128, 127, 126, + 125, 124, 122, 121, 120, 119, 118, 117, 115, 113, + 112, 109, 107, 106, 104, 101, 99, 98, 97, 95, + 94, 92, 91, 90, 89, 88, 85, 84, 83, 82, + 81, 80, 78, 73, 72, 71, 69, 68, 67, 66, + 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, + 54, 53, 52, 51, 50, 49, 47, 46, 44, 43, + 38, 35, 32, 29, 27, 23, 21, 14, 11, 7, + 5, 3, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201 + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 209, 209, 209, 209, 209, 209, + 209, 209, 209 } ; static yy_state_type yy_last_accepting_state; @@ -819,13 +823,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 275 ); + while ( yy_base[yy_current_state] != 283 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -1009,15 +1013,15 @@ YY_RULE_SETUP YY_BREAK case 40: YY_RULE_SETUP -{return(EQUALS);} +{return(SMBIOS_DEV_INFO);} YY_BREAK case 41: YY_RULE_SETUP -{return(PIPE);} +{return(EQUALS);} YY_BREAK case 42: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(PIPE);} YY_BREAK case 43: YY_RULE_SETUP @@ -1029,12 +1033,11 @@ YY_RULE_SETUP YY_BREAK case 45: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 46: -/* rule 46 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 47: /* rule 47 can match eol */ @@ -1042,10 +1045,15 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 48: +/* rule 48 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 49: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 49: +case 50: YY_RULE_SETUP ECHO; YY_BREAK @@ -1345,7 +1353,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1373,11 +1381,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 210 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 201); + yy_is_jam = (yy_current_state == 209); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 685da9dbfe..1de98d481a 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1023,6 +1023,25 @@ void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, dev->smbios_slot_designation = designation; } +void add_smbios_dev_info(struct bus *bus, long instance_id, const char *refdes) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'dev_info' only allowed for PCI devices\n"); + exit(1); + } + + if (instance_id < 0 || instance_id > UINT8_MAX) { + printf("ERROR: SMBIOS dev info instance ID '%ld' out of range\n", instance_id); + exit(1); + } + + dev->smbios_instance_id_valid = 1; + dev->smbios_instance_id = (unsigned int)instance_id; + dev->smbios_refdes = refdes; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -1135,6 +1154,14 @@ static void emit_smbios_data(FILE *fil, struct device *ptr) fprintf(fil, "\t.smbios_slot_length = %s,\n", ptr->smbios_slot_length); + /* Fill in SMBIOS type41 fields */ + if (ptr->smbios_instance_id_valid) { + fprintf(fil, "\t.smbios_instance_id_valid = true,\n"); + fprintf(fil, "\t.smbios_instance_id = %u,\n", ptr->smbios_instance_id); + if (ptr->smbios_refdes) + fprintf(fil, "\t.smbios_refdes = \"%s\",\n", ptr->smbios_refdes); + } + fprintf(fil, "#endif\n"); fprintf(fil, "#endif\n"); } diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index e6bd5aadd3..5b50cc0158 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -177,6 +177,11 @@ struct device { /* SMBIOS slot length */ char *smbios_slot_length; + /* SMBIOS type41 fields */ + int smbios_instance_id_valid; + unsigned int smbios_instance_id; + const char *smbios_refdes; + /* List of field+option to probe. */ struct fw_config_probe *probe; }; @@ -203,6 +208,8 @@ void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin, void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, char *data_width); +void add_smbios_dev_info(struct bus *bus, long instance_id, const char *refdes); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 1111267278..0997ff6444 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -47,6 +47,7 @@ inherit {return(INHERIT);} subsystemid {return(SUBSYSTEMID);} end {return(END);} smbios_slot_desc {return(SLOT_DESC);} +smbios_dev_info {return(SMBIOS_DEV_INFO);} = {return(EQUALS);} \| {return(PIPE);} 0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index b07adcb25e..c319a79527 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.7.6. */ +/* A Bison parser, made by GNU Bison 3.8.1. */ /* Bison implementation for Yacc-like parsers in C @@ -46,10 +46,10 @@ USER NAME SPACE" below. */ /* Identify Bison output, and Bison version. */ -#define YYBISON 30706 +#define YYBISON 30801 /* Bison version string. */ -#define YYBISON_VERSION "3.7.6" +#define YYBISON_VERSION "3.8.1" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -138,54 +138,56 @@ enum yysymbol_kind_t YYSYMBOL_IRQ = 25, /* IRQ */ YYSYMBOL_DRQ = 26, /* DRQ */ YYSYMBOL_SLOT_DESC = 27, /* SLOT_DESC */ - YYSYMBOL_IO = 28, /* IO */ - YYSYMBOL_NUMBER = 29, /* NUMBER */ - YYSYMBOL_SUBSYSTEMID = 30, /* SUBSYSTEMID */ - YYSYMBOL_INHERIT = 31, /* INHERIT */ - YYSYMBOL_IOAPIC_IRQ = 32, /* IOAPIC_IRQ */ - YYSYMBOL_IOAPIC = 33, /* IOAPIC */ - YYSYMBOL_PCIINT = 34, /* PCIINT */ - YYSYMBOL_GENERIC = 35, /* GENERIC */ - YYSYMBOL_SPI = 36, /* SPI */ - YYSYMBOL_USB = 37, /* USB */ - YYSYMBOL_MMIO = 38, /* MMIO */ - YYSYMBOL_GPIO = 39, /* GPIO */ - YYSYMBOL_FW_CONFIG_TABLE = 40, /* FW_CONFIG_TABLE */ - YYSYMBOL_FW_CONFIG_FIELD = 41, /* FW_CONFIG_FIELD */ - YYSYMBOL_FW_CONFIG_OPTION = 42, /* FW_CONFIG_OPTION */ - YYSYMBOL_FW_CONFIG_PROBE = 43, /* FW_CONFIG_PROBE */ - YYSYMBOL_PIPE = 44, /* PIPE */ - YYSYMBOL_YYACCEPT = 45, /* $accept */ - YYSYMBOL_devtree = 46, /* devtree */ - YYSYMBOL_chipchild_nondev = 47, /* chipchild_nondev */ - YYSYMBOL_chipchild = 48, /* chipchild */ - YYSYMBOL_chipchildren = 49, /* chipchildren */ - YYSYMBOL_chipchildren_dev = 50, /* chipchildren_dev */ - YYSYMBOL_devicechildren = 51, /* devicechildren */ - YYSYMBOL_chip = 52, /* chip */ - YYSYMBOL_53_1 = 53, /* @1 */ - YYSYMBOL_device = 54, /* device */ - YYSYMBOL_55_2 = 55, /* @2 */ - YYSYMBOL_56_3 = 56, /* @3 */ - YYSYMBOL_alias = 57, /* alias */ - YYSYMBOL_status = 58, /* status */ - YYSYMBOL_resource = 59, /* resource */ - YYSYMBOL_reference = 60, /* reference */ - YYSYMBOL_registers = 61, /* registers */ - YYSYMBOL_subsystemid = 62, /* subsystemid */ - YYSYMBOL_ioapic_irq = 63, /* ioapic_irq */ - YYSYMBOL_smbios_slot_desc = 64, /* smbios_slot_desc */ - YYSYMBOL_fw_config_table = 65, /* fw_config_table */ - YYSYMBOL_fw_config_table_children = 66, /* fw_config_table_children */ - YYSYMBOL_fw_config_field_children = 67, /* fw_config_field_children */ - YYSYMBOL_fw_config_field_bits = 68, /* fw_config_field_bits */ - YYSYMBOL_fw_config_field_bits_repeating = 69, /* fw_config_field_bits_repeating */ - YYSYMBOL_fw_config_field = 70, /* fw_config_field */ - YYSYMBOL_71_4 = 71, /* $@4 */ - YYSYMBOL_72_5 = 72, /* $@5 */ - YYSYMBOL_73_6 = 73, /* $@6 */ - YYSYMBOL_fw_config_option = 74, /* fw_config_option */ - YYSYMBOL_fw_config_probe = 75 /* fw_config_probe */ + YYSYMBOL_SMBIOS_DEV_INFO = 28, /* SMBIOS_DEV_INFO */ + YYSYMBOL_IO = 29, /* IO */ + YYSYMBOL_NUMBER = 30, /* NUMBER */ + YYSYMBOL_SUBSYSTEMID = 31, /* SUBSYSTEMID */ + YYSYMBOL_INHERIT = 32, /* INHERIT */ + YYSYMBOL_IOAPIC_IRQ = 33, /* IOAPIC_IRQ */ + YYSYMBOL_IOAPIC = 34, /* IOAPIC */ + YYSYMBOL_PCIINT = 35, /* PCIINT */ + YYSYMBOL_GENERIC = 36, /* GENERIC */ + YYSYMBOL_SPI = 37, /* SPI */ + YYSYMBOL_USB = 38, /* USB */ + YYSYMBOL_MMIO = 39, /* MMIO */ + YYSYMBOL_GPIO = 40, /* GPIO */ + YYSYMBOL_FW_CONFIG_TABLE = 41, /* FW_CONFIG_TABLE */ + YYSYMBOL_FW_CONFIG_FIELD = 42, /* FW_CONFIG_FIELD */ + YYSYMBOL_FW_CONFIG_OPTION = 43, /* FW_CONFIG_OPTION */ + YYSYMBOL_FW_CONFIG_PROBE = 44, /* FW_CONFIG_PROBE */ + YYSYMBOL_PIPE = 45, /* PIPE */ + YYSYMBOL_YYACCEPT = 46, /* $accept */ + YYSYMBOL_devtree = 47, /* devtree */ + YYSYMBOL_chipchild_nondev = 48, /* chipchild_nondev */ + YYSYMBOL_chipchild = 49, /* chipchild */ + YYSYMBOL_chipchildren = 50, /* chipchildren */ + YYSYMBOL_chipchildren_dev = 51, /* chipchildren_dev */ + YYSYMBOL_devicechildren = 52, /* devicechildren */ + YYSYMBOL_chip = 53, /* chip */ + YYSYMBOL_54_1 = 54, /* @1 */ + YYSYMBOL_device = 55, /* device */ + YYSYMBOL_56_2 = 56, /* @2 */ + YYSYMBOL_57_3 = 57, /* @3 */ + YYSYMBOL_alias = 58, /* alias */ + YYSYMBOL_status = 59, /* status */ + YYSYMBOL_resource = 60, /* resource */ + YYSYMBOL_reference = 61, /* reference */ + YYSYMBOL_registers = 62, /* registers */ + YYSYMBOL_subsystemid = 63, /* subsystemid */ + YYSYMBOL_ioapic_irq = 64, /* ioapic_irq */ + YYSYMBOL_smbios_slot_desc = 65, /* smbios_slot_desc */ + YYSYMBOL_smbios_dev_info = 66, /* smbios_dev_info */ + YYSYMBOL_fw_config_table = 67, /* fw_config_table */ + YYSYMBOL_fw_config_table_children = 68, /* fw_config_table_children */ + YYSYMBOL_fw_config_field_children = 69, /* fw_config_field_children */ + YYSYMBOL_fw_config_field_bits = 70, /* fw_config_field_bits */ + YYSYMBOL_fw_config_field_bits_repeating = 71, /* fw_config_field_bits_repeating */ + YYSYMBOL_fw_config_field = 72, /* fw_config_field */ + YYSYMBOL_73_4 = 73, /* $@4 */ + YYSYMBOL_74_5 = 74, /* $@5 */ + YYSYMBOL_75_6 = 75, /* $@6 */ + YYSYMBOL_fw_config_option = 76, /* fw_config_option */ + YYSYMBOL_fw_config_probe = 77 /* fw_config_probe */ }; typedef enum yysymbol_kind_t yysymbol_kind_t; @@ -343,12 +345,18 @@ typedef int yy_state_fast_t; # define YY_USE(E) /* empty */ #endif -#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ /* Suppress an incorrect diagnostic about yylval being uninitialized. */ -# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ +#if defined __GNUC__ && ! defined __ICC && 406 <= __GNUC__ * 100 + __GNUC_MINOR__ +# if __GNUC__ * 100 + __GNUC_MINOR__ < 407 +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") +# else +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ _Pragma ("GCC diagnostic push") \ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"") \ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") +# endif # define YY_IGNORE_MAYBE_UNINITIALIZED_END \ _Pragma ("GCC diagnostic pop") #else @@ -507,19 +515,19 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 90 +#define YYLAST 98 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 45 +#define YYNTOKENS 46 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 31 +#define YYNNTS 32 /* YYNRULES -- Number of rules. */ -#define YYNRULES 57 +#define YYNRULES 60 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 101 +#define YYNSTATES 105 /* YYMAXUTOK -- Last valid token kind. */ -#define YYMAXUTOK 299 +#define YYMAXUTOK 300 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -562,19 +570,21 @@ static const yytype_int8 yytranslate[] = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37, 38, 39, 40, 41, 42, 43, 44 + 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, + 45 }; #if YYDEBUG - /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ +/* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { 0, 26, 26, 26, 26, 29, 29, 29, 30, 30, 31, 31, 32, 32, 34, 34, 34, 34, 34, 34, - 34, 34, 34, 36, 36, 45, 45, 53, 53, 61, - 63, 67, 67, 69, 72, 75, 78, 81, 84, 87, - 90, 93, 97, 100, 100, 103, 103, 106, 112, 112, - 115, 114, 119, 119, 127, 127, 133, 137 + 34, 34, 34, 34, 36, 36, 45, 45, 53, 53, + 61, 63, 67, 67, 69, 72, 75, 78, 81, 84, + 87, 90, 93, 96, 99, 103, 106, 106, 109, 109, + 112, 118, 118, 121, 120, 125, 125, 133, 133, 139, + 143 }; #endif @@ -594,17 +604,18 @@ static const char *const yytname[] = "REGISTER", "ALIAS", "REFERENCE", "ASSOCIATION", "BOOL", "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", - "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", - "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "GPIO", - "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", + "SLOT_DESC", "SMBIOS_DEV_INFO", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", + "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", + "GPIO", "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", "FW_CONFIG_PROBE", "PIPE", "$accept", "devtree", "chipchild_nondev", "chipchild", "chipchildren", "chipchildren_dev", "devicechildren", "chip", "@1", "device", "@2", "@3", "alias", "status", "resource", "reference", "registers", "subsystemid", "ioapic_irq", - "smbios_slot_desc", "fw_config_table", "fw_config_table_children", - "fw_config_field_children", "fw_config_field_bits", - "fw_config_field_bits_repeating", "fw_config_field", "$@4", "$@5", "$@6", - "fw_config_option", "fw_config_probe", YY_NULLPTR + "smbios_slot_desc", "smbios_dev_info", "fw_config_table", + "fw_config_table_children", "fw_config_field_children", + "fw_config_field_bits", "fw_config_field_bits_repeating", + "fw_config_field", "$@4", "$@5", "$@6", "fw_config_option", + "fw_config_probe", YY_NULLPTR }; static const char * @@ -614,20 +625,7 @@ yysymbol_name (yysymbol_kind_t yysymbol) } #endif -#ifdef YYPRINT -/* YYTOKNUM[NUM] -- (External) token number corresponding to the - (internal) symbol number NUM (which must be that of a token). */ -static const yytype_int16 yytoknum[] = -{ - 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, - 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, - 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, - 295, 296, 297, 298, 299 -}; -#endif - -#define YYPACT_NINF (-61) +#define YYPACT_NINF (-45) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -637,127 +635,129 @@ static const yytype_int16 yytoknum[] = #define yytable_value_is_error(Yyn) \ 0 - /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing - STATE-NUM. */ +/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ static const yytype_int8 yypact[] = { - -61, 12, -61, -7, -61, -61, -61, -61, -12, 46, - -61, 8, -61, 14, 11, 18, 46, 23, -61, -61, - -61, -61, 16, 24, 17, 25, 34, -61, -61, 46, - 26, 10, -61, 13, 51, 41, 42, -61, -61, -61, - -61, -61, 31, -61, -3, -61, -61, -61, 44, 13, - -61, -61, 2, 26, 10, -61, -61, 45, -61, -61, - -61, -61, -61, -61, 6, 35, 0, -61, -61, -61, - 37, -61, 50, 39, 40, 53, -61, -61, -61, -61, - -61, -61, -61, -61, 4, 48, 54, 43, 47, 56, - -61, 49, 57, 55, 58, -61, -61, 59, -61, -61, - -61 + -45, 6, -45, 4, -45, -45, -45, -45, -12, 45, + -45, 15, -45, 11, 17, 18, 45, -3, -45, -45, + -45, -45, 16, 34, 23, 14, 46, -45, -45, 45, + 25, 19, -45, 10, 51, 42, 43, -45, -45, -45, + -45, -45, 31, -45, -7, -45, -45, -45, 49, 10, + -45, -45, -6, 25, 19, -45, -45, 50, -45, -45, + -45, -45, -45, -45, -2, 32, 0, -45, -45, -45, + 33, -45, 52, 38, 40, 41, 55, -45, -45, -45, + -45, -45, -45, -45, -45, -45, 12, 58, 57, 59, + 47, 44, 61, -45, 53, 63, -45, 54, 60, -45, + -45, 64, -45, -45, -45 }; - /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. - Performed when YYTABLE does not specify something else to do. Zero - means the default is an error. */ +/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE does not specify something else to do. Zero + means the default is an error. */ static const yytype_int8 yydefact[] = { - 2, 0, 1, 0, 44, 3, 4, 23, 0, 0, - 42, 0, 43, 0, 0, 0, 0, 0, 5, 11, - 7, 6, 54, 0, 0, 0, 0, 13, 24, 12, - 52, 49, 46, 0, 29, 0, 0, 9, 10, 8, - 47, 46, 0, 50, 0, 31, 32, 27, 0, 0, - 35, 34, 0, 0, 49, 46, 55, 0, 45, 22, - 30, 25, 53, 48, 0, 0, 0, 22, 51, 56, - 0, 28, 0, 0, 0, 0, 15, 14, 16, 20, - 17, 18, 19, 21, 0, 0, 0, 0, 0, 0, - 26, 0, 41, 36, 0, 57, 33, 40, 37, 38, - 39 + 2, 0, 1, 0, 47, 3, 4, 24, 0, 0, + 45, 0, 46, 0, 0, 0, 0, 0, 5, 11, + 7, 6, 57, 0, 0, 0, 0, 13, 25, 12, + 55, 52, 49, 0, 30, 0, 0, 9, 10, 8, + 50, 49, 0, 53, 0, 32, 33, 28, 0, 0, + 36, 35, 0, 0, 52, 49, 58, 0, 48, 23, + 31, 26, 56, 51, 0, 0, 0, 23, 54, 59, + 0, 29, 0, 0, 0, 0, 0, 15, 14, 16, + 21, 17, 18, 19, 20, 22, 0, 0, 0, 44, + 0, 0, 0, 27, 0, 42, 43, 37, 0, 60, + 34, 41, 38, 39, 40 }; - /* YYPGOTO[NTERM-NUM]. */ +/* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -61, -61, 60, -61, -61, 61, 15, -1, -61, -28, - -61, -61, -61, 30, -61, -61, -60, -61, -61, -61, - -61, -61, -22, 33, 36, -61, -61, -61, -61, -61, - -61 + -45, -45, 62, -45, -45, 66, 8, -1, -45, -28, + -45, -45, -45, 35, -45, -45, -44, -45, -45, -45, + -45, -45, -45, -31, 56, 39, -45, -45, -45, -45, + -45, -45 }; - /* YYDEFGOTO[NTERM-NUM]. */ +/* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { 0, 1, 16, 38, 29, 17, 66, 18, 9, 19, - 67, 59, 49, 47, 78, 20, 21, 80, 81, 82, - 6, 8, 44, 31, 43, 12, 55, 41, 32, 58, - 83 + 67, 59, 49, 47, 79, 20, 21, 81, 82, 83, + 84, 6, 8, 44, 31, 43, 12, 55, 41, 32, + 58, 85 }; - /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If - positive, shift that token. If negative, reduce the rule whose - number is the opposite. If YYTABLE_NINF, syntax error. */ +/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule whose + number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 5, 39, 10, 3, 13, 14, 79, 3, 13, 14, - 7, 56, 2, 70, 71, 3, 62, 70, 90, 52, - 68, 23, 45, 46, 79, 22, 24, 72, 25, 11, - 73, 72, 74, 64, 73, 26, 74, 28, 77, 57, - 35, 33, 36, 75, 57, 30, 34, 75, 57, 3, - 13, 14, 4, 15, 42, 40, 77, 48, 50, 51, - 53, 60, 65, 91, 69, 76, 85, 86, 87, 88, - 89, 92, 93, 95, 97, 54, 100, 27, 96, 61, - 0, 94, 84, 76, 0, 0, 98, 99, 0, 37, - 63 + 5, 39, 10, 3, 13, 14, 2, 56, 62, 3, + 52, 28, 68, 70, 71, 3, 13, 14, 23, 45, + 46, 7, 80, 24, 64, 70, 93, 72, 73, 35, + 11, 74, 22, 75, 25, 26, 57, 57, 78, 72, + 73, 57, 80, 74, 76, 75, 30, 4, 3, 13, + 14, 33, 15, 34, 36, 40, 76, 48, 78, 50, + 51, 53, 69, 87, 42, 77, 60, 65, 89, 88, + 90, 91, 92, 94, 95, 86, 96, 97, 99, 98, + 101, 104, 27, 100, 61, 77, 102, 0, 0, 0, + 103, 37, 0, 63, 0, 0, 0, 0, 54 }; static const yytype_int8 yycheck[] = { - 1, 29, 14, 3, 4, 5, 66, 3, 4, 5, - 17, 14, 0, 13, 14, 3, 14, 13, 14, 41, - 14, 7, 9, 10, 84, 17, 12, 27, 17, 41, - 30, 27, 32, 55, 30, 17, 32, 14, 66, 42, - 15, 17, 8, 43, 42, 29, 29, 43, 42, 3, - 4, 5, 40, 7, 44, 29, 84, 6, 17, 17, - 29, 17, 17, 15, 29, 66, 29, 17, 29, 29, - 17, 17, 29, 17, 17, 42, 17, 16, 29, 49, - -1, 34, 67, 84, -1, -1, 31, 29, -1, 29, - 54 + 1, 29, 14, 3, 4, 5, 0, 14, 14, 3, + 41, 14, 14, 13, 14, 3, 4, 5, 7, 9, + 10, 17, 66, 12, 55, 13, 14, 27, 28, 15, + 42, 31, 17, 33, 17, 17, 43, 43, 66, 27, + 28, 43, 86, 31, 44, 33, 30, 41, 3, 4, + 5, 17, 7, 30, 8, 30, 44, 6, 86, 17, + 17, 30, 30, 30, 45, 66, 17, 17, 30, 17, + 30, 30, 17, 15, 17, 67, 17, 30, 17, 35, + 17, 17, 16, 30, 49, 86, 32, -1, -1, -1, + 30, 29, -1, 54, -1, -1, -1, -1, 42 }; - /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing - symbol of state STATE-NUM. */ +/* YYSTOS[STATE-NUM] -- The symbol kind of the accessing symbol of + state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 46, 0, 3, 40, 52, 65, 17, 66, 53, - 14, 41, 70, 4, 5, 7, 47, 50, 52, 54, - 60, 61, 17, 7, 12, 17, 17, 50, 14, 49, - 29, 68, 73, 17, 29, 15, 8, 47, 48, 54, - 29, 72, 44, 69, 67, 9, 10, 58, 6, 57, - 17, 17, 67, 29, 68, 71, 14, 42, 74, 56, - 17, 58, 14, 69, 67, 17, 51, 55, 14, 29, - 13, 14, 27, 30, 32, 43, 52, 54, 59, 61, - 62, 63, 64, 75, 51, 29, 17, 29, 29, 17, - 14, 15, 17, 29, 34, 17, 29, 17, 31, 29, - 17 + 0, 47, 0, 3, 41, 53, 67, 17, 68, 54, + 14, 42, 72, 4, 5, 7, 48, 51, 53, 55, + 61, 62, 17, 7, 12, 17, 17, 51, 14, 50, + 30, 70, 75, 17, 30, 15, 8, 48, 49, 55, + 30, 74, 45, 71, 69, 9, 10, 59, 6, 58, + 17, 17, 69, 30, 70, 73, 14, 43, 76, 57, + 17, 59, 14, 71, 69, 17, 52, 56, 14, 30, + 13, 14, 27, 28, 31, 33, 44, 53, 55, 60, + 62, 63, 64, 65, 66, 77, 52, 30, 17, 30, + 30, 30, 17, 14, 15, 17, 17, 30, 35, 17, + 30, 17, 32, 30, 17 }; - /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +/* YYR1[RULE-NUM] -- Symbol kind of the left-hand side of rule RULE-NUM. */ static const yytype_int8 yyr1[] = { - 0, 45, 46, 46, 46, 47, 47, 47, 48, 48, - 49, 49, 50, 50, 51, 51, 51, 51, 51, 51, - 51, 51, 51, 53, 52, 55, 54, 56, 54, 57, - 57, 58, 58, 59, 60, 61, 62, 62, 63, 64, - 64, 64, 65, 66, 66, 67, 67, 68, 69, 69, - 71, 70, 72, 70, 73, 70, 74, 75 + 0, 46, 47, 47, 47, 48, 48, 48, 49, 49, + 50, 50, 51, 51, 52, 52, 52, 52, 52, 52, + 52, 52, 52, 52, 54, 53, 56, 55, 57, 55, + 58, 58, 59, 59, 60, 61, 62, 63, 63, 64, + 65, 65, 65, 66, 66, 67, 68, 68, 69, 69, + 70, 71, 71, 73, 72, 74, 72, 75, 72, 76, + 77 }; - /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ +/* YYR2[RULE-NUM] -- Number of symbols on the right-hand side of rule RULE-NUM. */ static const yytype_int8 yyr2[] = { 0, 2, 0, 2, 2, 1, 1, 1, 1, 1, 2, 0, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 0, 0, 5, 0, 8, 0, 7, 0, - 2, 1, 1, 4, 4, 4, 3, 4, 4, 5, - 4, 3, 3, 2, 0, 2, 0, 2, 3, 0, - 0, 7, 0, 6, 0, 5, 3, 3 + 2, 2, 2, 0, 0, 5, 0, 8, 0, 7, + 0, 2, 1, 1, 4, 4, 4, 3, 4, 4, + 5, 4, 3, 3, 2, 3, 2, 0, 2, 0, + 2, 3, 0, 0, 7, 0, 6, 0, 5, 3, + 3 }; @@ -769,6 +769,7 @@ enum { YYENOMEM = -2 }; #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab +#define YYNOMEM goto yyexhaustedlab #define YYRECOVERING() (!!yyerrstatus) @@ -809,10 +810,7 @@ do { \ YYFPRINTF Args; \ } while (0) -/* This macro is provided for backward compatibility. */ -# ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -# endif + # define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ @@ -839,10 +837,6 @@ yy_symbol_value_print (FILE *yyo, YY_USE (yyoutput); if (!yyvaluep) return; -# ifdef YYPRINT - if (yykind < YYNTOKENS) - YYPRINT (yyo, yytoknum[yykind], *yyvaluep); -# endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN YY_USE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END @@ -1027,6 +1021,7 @@ yyparse (void) YYDPRINTF ((stderr, "Starting parse\n")); yychar = YYEMPTY; /* Cause a token to be read. */ + goto yysetstate; @@ -1052,7 +1047,7 @@ yysetstate: if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE - goto yyexhaustedlab; + YYNOMEM; #else { /* Get the current used size of the three stacks, in elements. */ @@ -1080,7 +1075,7 @@ yysetstate: # else /* defined YYSTACK_RELOCATE */ /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) - goto yyexhaustedlab; + YYNOMEM; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; @@ -1091,7 +1086,7 @@ yysetstate: YY_CAST (union yyalloc *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize)))); if (! yyptr) - goto yyexhaustedlab; + YYNOMEM; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); # undef YYSTACK_RELOCATE @@ -1113,6 +1108,7 @@ yysetstate: } #endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */ + if (yystate == YYFINAL) YYACCEPT; @@ -1228,7 +1224,7 @@ yyreduce: { cur_parent = root_parent; } break; - case 23: /* @1: %empty */ + case 24: /* @1: %empty */ { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); @@ -1236,105 +1232,113 @@ yyreduce: } break; - case 24: /* chip: CHIP STRING @1 chipchildren_dev END */ + case 25: /* chip: CHIP STRING @1 chipchildren_dev END */ { cur_chip_instance = chip_dequeue_tail(); } break; - case 25: /* @2: %empty */ + case 26: /* @2: %empty */ { (yyval.dev) = new_device_raw(cur_parent, cur_chip_instance, (yyvsp[-3].number), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 26: /* device: DEVICE BUS NUMBER alias status @2 devicechildren END */ + case 27: /* device: DEVICE BUS NUMBER alias status @2 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 27: /* @3: %empty */ + case 28: /* @3: %empty */ { (yyval.dev) = new_device_reference(cur_parent, cur_chip_instance, (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 28: /* device: DEVICE REFERENCE STRING status @3 devicechildren END */ + case 29: /* device: DEVICE REFERENCE STRING status @3 devicechildren END */ { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 29: /* alias: %empty */ + case 30: /* alias: %empty */ { (yyval.string) = NULL; } break; - case 30: /* alias: ALIAS STRING */ + case 31: /* alias: ALIAS STRING */ { (yyval.string) = (yyvsp[0].string); } break; - case 33: /* resource: RESOURCE NUMBER EQUALS NUMBER */ + case 34: /* resource: RESOURCE NUMBER EQUALS NUMBER */ { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 34: /* reference: REFERENCE STRING ASSOCIATION STRING */ + case 35: /* reference: REFERENCE STRING ASSOCIATION STRING */ { add_reference(cur_chip_instance, (yyvsp[0].string), (yyvsp[-2].string)); } break; - case 35: /* registers: REGISTER STRING EQUALS STRING */ + case 36: /* registers: REGISTER STRING EQUALS STRING */ { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 36: /* subsystemid: SUBSYSTEMID NUMBER NUMBER */ + case 37: /* subsystemid: SUBSYSTEMID NUMBER NUMBER */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 37: /* subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT */ + case 38: /* subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT */ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 38: /* ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER */ + case 39: /* ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER */ { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; - case 39: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING */ + case 40: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; - case 40: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING */ + case 41: /* smbios_slot_desc: SLOT_DESC STRING STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } break; - case 41: /* smbios_slot_desc: SLOT_DESC STRING STRING */ + case 42: /* smbios_slot_desc: SLOT_DESC STRING STRING */ { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; - case 42: /* fw_config_table: FW_CONFIG_TABLE fw_config_table_children END */ + case 43: /* smbios_dev_info: SMBIOS_DEV_INFO NUMBER STRING */ + { add_smbios_dev_info(cur_parent, strtol((yyvsp[-1].string), NULL, 0), (yyvsp[0].string)); } + break; + + case 44: /* smbios_dev_info: SMBIOS_DEV_INFO NUMBER */ + { add_smbios_dev_info(cur_parent, strtol((yyvsp[0].string), NULL, 0), NULL); } + break; + + case 45: /* fw_config_table: FW_CONFIG_TABLE fw_config_table_children END */ { } break; - case 47: /* fw_config_field_bits: NUMBER NUMBER */ + case 50: /* fw_config_field_bits: NUMBER NUMBER */ { append_fw_config_bits(&cur_bits, strtoul((yyvsp[-1].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; - case 50: /* $@4: %empty */ + case 53: /* $@4: %empty */ { cur_field = new_fw_config_field((yyvsp[-2].string), cur_bits); } break; - case 51: /* fw_config_field: FW_CONFIG_FIELD STRING fw_config_field_bits fw_config_field_bits_repeating $@4 fw_config_field_children END */ + case 54: /* fw_config_field: FW_CONFIG_FIELD STRING fw_config_field_bits fw_config_field_bits_repeating $@4 fw_config_field_children END */ { cur_bits = NULL; } break; - case 52: /* $@5: %empty */ + case 55: /* $@5: %empty */ { cur_bits = NULL; append_fw_config_bits(&cur_bits, strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); @@ -1342,25 +1346,25 @@ yyreduce: } break; - case 53: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER $@5 fw_config_field_children END */ + case 56: /* fw_config_field: FW_CONFIG_FIELD STRING NUMBER $@5 fw_config_field_children END */ { cur_bits = NULL; } break; - case 54: /* $@6: %empty */ + case 57: /* $@6: %empty */ { cur_field = get_fw_config_field((yyvsp[0].string)); } break; - case 55: /* fw_config_field: FW_CONFIG_FIELD STRING $@6 fw_config_field_children END */ + case 58: /* fw_config_field: FW_CONFIG_FIELD STRING $@6 fw_config_field_children END */ { cur_bits = NULL; } break; - case 56: /* fw_config_option: FW_CONFIG_OPTION STRING NUMBER */ + case 59: /* fw_config_option: FW_CONFIG_OPTION STRING NUMBER */ { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoull((yyvsp[0].string), NULL, 0)); } break; - case 57: /* fw_config_probe: FW_CONFIG_PROBE STRING STRING */ + case 60: /* fw_config_probe: FW_CONFIG_PROBE STRING STRING */ { add_fw_config_probe(cur_parent, (yyvsp[-1].string), (yyvsp[0].string)); } break; @@ -1446,6 +1450,7 @@ yyerrorlab: label yyerrorlab therefore never appears in user code. */ if (0) YYERROR; + ++yynerrs; /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ @@ -1506,7 +1511,7 @@ yyerrlab1: `-------------------------------------*/ yyacceptlab: yyresult = 0; - goto yyreturn; + goto yyreturnlab; /*-----------------------------------. @@ -1514,24 +1519,22 @@ yyacceptlab: `-----------------------------------*/ yyabortlab: yyresult = 1; - goto yyreturn; + goto yyreturnlab; -#if !defined yyoverflow -/*-------------------------------------------------. -| yyexhaustedlab -- memory exhaustion comes here. | -`-------------------------------------------------*/ +/*-----------------------------------------------------------. +| yyexhaustedlab -- YYNOMEM (memory exhaustion) comes here. | +`-----------------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; - goto yyreturn; -#endif + goto yyreturnlab; -/*-------------------------------------------------------. -| yyreturn -- parsing is finished, clean up and return. | -`-------------------------------------------------------*/ -yyreturn: +/*----------------------------------------------------------. +| yyreturnlab -- parsing is finished, clean up and return. | +`----------------------------------------------------------*/ +yyreturnlab: if (yychar != YYEMPTY) { /* Make sure we have latest lookahead translation. See comments at diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 1d96a35ab6..fb14adcf1d 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.7.6. */ +/* A Bison parser, made by GNU Bison 3.8.1. */ /* Bison interface for Yacc-like parsers in C @@ -35,8 +35,8 @@ especially those whose name start with YY_ or yy_. They are private implementation details that can be changed or removed. */ -#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -79,23 +79,24 @@ extern int yydebug; IRQ = 280, /* IRQ */ DRQ = 281, /* DRQ */ SLOT_DESC = 282, /* SLOT_DESC */ - IO = 283, /* IO */ - NUMBER = 284, /* NUMBER */ - SUBSYSTEMID = 285, /* SUBSYSTEMID */ - INHERIT = 286, /* INHERIT */ - IOAPIC_IRQ = 287, /* IOAPIC_IRQ */ - IOAPIC = 288, /* IOAPIC */ - PCIINT = 289, /* PCIINT */ - GENERIC = 290, /* GENERIC */ - SPI = 291, /* SPI */ - USB = 292, /* USB */ - MMIO = 293, /* MMIO */ - GPIO = 294, /* GPIO */ - FW_CONFIG_TABLE = 295, /* FW_CONFIG_TABLE */ - FW_CONFIG_FIELD = 296, /* FW_CONFIG_FIELD */ - FW_CONFIG_OPTION = 297, /* FW_CONFIG_OPTION */ - FW_CONFIG_PROBE = 298, /* FW_CONFIG_PROBE */ - PIPE = 299 /* PIPE */ + SMBIOS_DEV_INFO = 283, /* SMBIOS_DEV_INFO */ + IO = 284, /* IO */ + NUMBER = 285, /* NUMBER */ + SUBSYSTEMID = 286, /* SUBSYSTEMID */ + INHERIT = 287, /* INHERIT */ + IOAPIC_IRQ = 288, /* IOAPIC_IRQ */ + IOAPIC = 289, /* IOAPIC */ + PCIINT = 290, /* PCIINT */ + GENERIC = 291, /* GENERIC */ + SPI = 292, /* SPI */ + USB = 293, /* USB */ + MMIO = 294, /* MMIO */ + GPIO = 295, /* GPIO */ + FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ + FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ + FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ + FW_CONFIG_PROBE = 299, /* FW_CONFIG_PROBE */ + PIPE = 300 /* PIPE */ }; typedef enum yytokentype yytoken_kind_t; #endif @@ -120,6 +121,8 @@ typedef union YYSTYPE YYSTYPE; extern YYSTYPE yylval; + int yyparse (void); -#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ + +#endif /* !YY_YY_HOME_USUARIO_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index da6d97b1a6..1b611e4b85 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -21,7 +21,7 @@ static struct fw_config_field_bits *cur_bits; uint64_t number; } -%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO GPIO FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE PIPE +%token CHIP DEVICE REGISTER ALIAS REFERENCE ASSOCIATION BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC SMBIOS_DEV_INFO IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO GPIO FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE PIPE %% devtree: { cur_parent = root_parent; } | devtree chip | devtree fw_config_table; @@ -31,7 +31,7 @@ chipchild: device | chipchild_nondev; chipchildren: chipchildren chipchild | /* empty */ ; chipchildren_dev: device chipchildren | chipchild_nondev chipchildren_dev; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | devicechildren fw_config_probe | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren smbios_dev_info | devicechildren registers | devicechildren fw_config_probe | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip_instance($2); @@ -93,6 +93,12 @@ smbios_slot_desc: SLOT_DESC STRING STRING STRING smbios_slot_desc: SLOT_DESC STRING STRING { add_slot_desc(cur_parent, $2, $3, NULL, NULL); }; +smbios_dev_info: SMBIOS_DEV_INFO NUMBER STRING + { add_smbios_dev_info(cur_parent, strtol($2, NULL, 0), $3); }; + +smbios_dev_info: SMBIOS_DEV_INFO NUMBER + { add_smbios_dev_info(cur_parent, strtol($2, NULL, 0), NULL); }; + /* fw_config: firmware configuration table */ fw_config_table: FW_CONFIG_TABLE fw_config_table_children END { }; diff --git a/util/spd_tools/README.md b/util/spd_tools/README.md index 5be666bde4..3a1342c85a 100644 --- a/util/spd_tools/README.md +++ b/util/spd_tools/README.md @@ -8,6 +8,9 @@ The memory technologies currently supported are: * LPDDR4x - based on the JESD209-4C spec and Intel recommendations (docs #616599, #610202, #634730). * DDR4 - based on the JESD79-4C and Jedec 4.1.2.L-5 R29 v103 specs. +* LPDDR5 - based on the LPDDR5 spec JESD209-5B, the SPD spec SPD4.1.2.M-2 (the + LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5), + and Intel recommendations in advisory #616599. There are two tools provided to assist with generating SPDs and Makefiles to integrate into the coreboot build. These tools can also be used to allocate DRAM @@ -292,6 +295,100 @@ string like "9 10 11 12 14". } ``` +### LP5 attributes + +#### Mandatory + +* `densityPerDieGb`: Density per die in Gb. Valid values: `4, 6, 8, 12, 16, + 24, 32` Gb per die. + +* `diesPerPackage`: Number of physical dies in each SDRAM package. Valid + values: `2, 4, 8` dies per package. + +* `bitWidthPerChannel`: Width of each physical channel. Valid values: `8, 16` + bits. + +* `ranksPerChannel`: Number of ranks per physical channel. Valid values: `1, + 2`. If the channels across multiple dies share the same DQ/DQS pins but use + a separate CS, then ranks is 2 else it is 1. + +* `speedMbps`: Maximum data rate supported by the part in Mbps. Valid values: + `5500, 6400` Mbps. + +#### Optional + +* `trfcabNs`: Minimum Refresh Recovery Delay Time (tRFCab) for all banks in + nanoseconds. As per JESD209-5B, this is dependent on the density per die. + Default values used: + + * 4 Gb : 180 ns + * 6 Gb : 210 ns + * 8 Gb : 210 ns + * 12 Gb: 280 ns + * 16 Gb: 280 ns + * 24 Gb: 380 ns + * 32 Gb: 380 ns + +* `trfcpbNs`: Minimum Refresh Recovery Delay Time (tRFCpb) per bank in + nanoseconds. As per JESD209-5B, this is dependent on the density per die. + Default values used: + + * 4 Gb : 90 ns + * 6 Gb : 120 ns + * 8 Gb : 120 ns + * 12 Gb: 140 ns + * 16 Gb: 140 ns + * 24 Gb: 190 ns + * 32 Gb: 190 ns + +* `trpabMinNs`: Minimum Row Precharge Delay Time (tRPab) for all banks in + nanoseconds. As per JESD209-5B, this is max(21ns, 2nCK), which defaults to + `21 ns`. + +* `trppbMinNs`: Minimum Row Precharge Delay Time (tRPpb) per bank in + nanoseconds. As per JESD209-5B, this is max(18ns, 2nCK) which defaults to + `18 ns`. + +* `tckMinPs`: SDRAM minimum cycle time (tCKmin) value in picoseconds. LPDDR5 + has two clocks: the command/addrees clock (CK) and the data clock (WCK). + They are related by the WCK:CK ratio, which can be either 4:1 or 2:1. For + LPDDR5, tCKmin is the CK period, which can be calculated from the + `speedMbps` attribute and the WCK:CK ratio as follows: `tCKmin = 1 / + (speedMbps / 2 / WCK:CK)`. The default values used are for a 4:1 WCK:CK + ratio: + + * 6400 Mbps: 1250 ps + * 5500 Mbps: 1455 ps + +* `taaMinPs`: Minimum CAS Latency Time(tAAmin) in picoseconds. This value + defaults to nck * tCKmin, where nck is maximum CAS latency, and is + determined from the `speedMbps` attribute as per JESD209-5B: + + * 6400 Mbps: 17 + * 5500 Mbps: 15 + +* `trcdMinNs`: Minimum RAS# to CAS# Delay Time (tRCDmin) in nanoseconds. As + per JESD209-5B, this is max(18ns, 2nCK) which defaults to `18 ns`. + +#### Example `memory_parts.json` + +``` +{ + "parts": [ + { + "name": "MT62F1G32D4DR-031 WT:B", + "attribs": { + "densityPerDieGb": 8, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 6400 + } + }, + ] +} +``` + ### Output The `spd_gen` tool generates the directory structure shown below. The inputs to @@ -493,3 +590,48 @@ util/spd_tools/bin/part_id_gen \ `dram_id.generated.txt` with the new part. * Upload the changes to `Makefile.inc` and `dram_id.generated.txt` for review. + +## How to add support for a new memory technology + +### 1. Gather the SPD requirements + +To generate SPDs for the new memory technology, information is needed about the +list of bytes in the SPD and how the value of each byte should be determined. +This information usually comes from a combination of: + +* The JEDEC spec for the memory technology, e.g. JESD209-5B for LPDDR5. +* The JEDEC SPD spec for the memory technology, e.g. SPD4.1.2.M-2 for LPDDR3/4 + (also used for LP4x and LP5). +* Platform-specific requirements. SoC vendors often don't follow the JEDEC + specs exactly. E.g. the memory training code may expect certain SPD bytes to + encode a different value to what is stated in the spec. So for each SoC + platform using the new memory technology, any platform-specific requirements + need to be gathered. + +### 2. Implement support in spd_tools + +Support for the new memory technology needs to be added to both the `spd_gen` +and `part_id_gen` tools. + +#### `spd_gen` + +Adding support to `spd_gen` requires implementing the logic to generate SPDs for +the new memory technology. The changes required are: + +* Add the new memory technology to the `memTechMap` in `spd_gen/spd_gen.go`. +* Add a new file `spd_gen/.go`. This file will contain all the logic + for generating SPDs for the new memory technology. It needs to implement the + `memTech` interface defined in `spd_gen/spd_gen.go`. The interface functions + are documented inline. Examples of how the interface is implemented for + existing memory technologies can be found in the `spd_gen/` directory, e.g. + `lp4x.go`, `ddr4.go`, `lp5.go`. While not strictly necessary, it is + recommended to follow the overall structure of these existing files when + adding a new memory technology. + +#### `part_id_gen` + +The `part_id_gen` tool is memory technology-agnostic, so the only change +required is: + +* Add the new memory technology to the `supportedMemTechs` list in + `part_id_gen/part_id_gen.go`. diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index c67f1273ee..750b825e4e 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -45,6 +45,7 @@ var supportedPlatforms = [...]string{ var supportedMemTechs = [...]string{ "lp4x", "ddr4", + "lp5", } func usage() { diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go new file mode 100644 index 0000000000..c8bcaf5b23 --- /dev/null +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -0,0 +1,785 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +package main + +import ( + "encoding/json" + "fmt" +) + +/* ------------------------------------------------------------------------------------------ */ +/* LP5-defined types */ +/* ------------------------------------------------------------------------------------------ */ + +type lp5 struct { +} + +type LP5MemAttributes struct { + /* Primary attributes - must be provided by JSON file for each part */ + DensityPerDieGb int + DiesPerPackage int + BitWidthPerChannel int + RanksPerChannel int + SpeedMbps int + + /* + * All the following parameters are optional and required only if the part requires + * special parameters as per the datasheet. + */ + /* Timing parameters */ + TRFCABNs int + TRFCPBNs int + TRPABMinNs int + TRPPBMinNs int + TCKMinPs int + TAAMinPs int + TRCDMinNs int +} + +type LP5DensityParams struct { + DensityEncoding byte + RowAddressBitsx8Channel int + RowAddressBitsx16Channel int + TRFCABNs int + TRFCPBNs int +} + +type LP5SpeedParams struct { + TCKMinPs int + MaxCASLatency int +} + +type LP5BankArchParams struct { + NumBanks int + BankGroups int + BurstAddressBits int +} + +type LP5SPDAttribFunc func(*LP5MemAttributes) byte + +type LP5SPDAttribTableEntry struct { + constVal byte + getVal LP5SPDAttribFunc +} + +type LP5SetFunc func(*LP5MemAttributes) int + +type LP5Set struct { + SPDRevision byte + getBankArch LP5SetFunc + optionalFeatures byte + otherOptionalFeatures byte + busWidthEncoding byte +} + +/* ------------------------------------------------------------------------------------------ */ +/* Constants */ +/* ------------------------------------------------------------------------------------------ */ + +const ( + /* SPD Byte Index */ + LP5SPDIndexSize = 0 + LP5SPDIndexRevision = 1 + LP5SPDIndexMemoryType = 2 + LP5SPDIndexModuleType = 3 + LP5SPDIndexDensityBanks = 4 + LP5SPDIndexAddressing = 5 + LP5SPDIndexPackageType = 6 + LP5SPDIndexOptionalFeatures = 7 + LP5SPDIndexOtherOptionalFeatures = 9 + LP5SPDIndexModuleOrganization = 12 + LP5SPDIndexBusWidth = 13 + LP5SPDIndexTimebases = 17 + LP5SPDIndexTCKMin = 18 + LP5SPDIndexTAAMin = 24 + LP5SPDIndexTRCDMin = 26 + LP5SPDIndexTRPABMin = 27 + LP5SPDIndexTRPPBMin = 28 + LP5SPDIndexTRFCABMinLSB = 29 + LP5SPDIndexTRFCABMinMSB = 30 + LP5SPDIndexTRFCPBMinLSB = 31 + LP5SPDIndexTRFCPBMinMSB = 32 + LP5SPDIndexTRPPBMinFineOffset = 120 + LP5SPDIndexTRPABMinFineOffset = 121 + LP5SPDIndexTRCDMinFineOffset = 122 + LP5SPDIndexTAAMinFineOffset = 123 + LP5SPDIndexTCKMinFineOffset = 125 + LP5SPDIndexManufacturerPartNumberStartByte = 329 + LP5SPDIndexManufacturerPartNumberEndByte = 348 + + /* SPD Byte Value */ + + /* + * From JEDEC spec: + * 6:4 (Bytes total) = 2 (512 bytes) + * 3:0 (Bytes used) = 3 (384 bytes) + * Set to 0x23 for LPDDR5. + */ + LP5SPDValueSize = 0x23 + + /* + * Revision 1.0. Expected by ADL + */ + LP5SPDValueRevision1_0 = 0x10 + /* + * Revision 1.1. Expected by Sabrina + */ + LP5SPDValueRevision1_1 = 0x11 + + /* + * As per advisory #616599, ADL MRC expects LPDDR5 memory type = 0x13. + */ + LP5SPDValueMemoryType = 0x13 + + /* + * From JEDEC spec: + * 7:7 (Hybrid) = 0 (Not hybrid) + * 6:4 (Hybrid media) = 000 (Not hybrid) + * 3:0 (Base Module Type) = 1110 (Non-DIMM solution) + * + * This is dependent on hardware design. LPDDR5 only has memory down solution. + * Hence this is not hybrid non-DIMM solution. + * Set to 0x0E. + */ + LP5SPDValueModuleType = 0x0e + + /* + * From JEDEC spec: + * 3:2 (MTB) = 00 (0.125ns) + * 1:0 (FTB) = 00 (1ps) + * Set to 0x00. + */ + LP5SPDValueTimebases = 0x00 + + /* As per JEDEC spec, unused digits of manufacturer part number are left as blank. */ + LP5SPDValueManufacturerPartNumberBlank = 0x20 +) + +const ( + // The column addresses are the same for x8 & x16 and for all Bank Architectures. + LP5ColAddressBits = 6 +) + +const ( + // LPDDR5 has a flexible bank architecture with three programmable bank modes: BG, 8B, 16B. + LP5BGBankArch = iota + LP58BBankArch + LP516BBankArch +) + +/* ------------------------------------------------------------------------------------------ */ +/* Global variables */ +/* ------------------------------------------------------------------------------------------ */ + +var LP5PlatformSetMap = map[int][]int{ + 0: {PlatformADL}, + 1: {PlatformSBR}, +} + +var LP5SetInfo = map[int]LP5Set{ + 0: { + SPDRevision: LP5SPDValueRevision1_0, + getBankArch: LP5GetBankArchSet0, + /* + * From JEDEC spec: + * 5:4 (Maximum Activate Window) = 00 (8192 * tREFI) + * 3:0 (Maximum Activate Count) = 1000 (Unlimited MAC) + * Set to 0x08. + */ + optionalFeatures: 0x08, + /* + * For ADL (as per advisory #616599): + * 7:5 (Number of system channels) = 000 (1 channel always) + * 4:3 (Bus width extension) = 00 (no ECC) + * 2:0 (Bus width) = 001 (x16 always) + * Set to 0x01. + */ + busWidthEncoding: 0x01, + }, + 1: { + SPDRevision: LP5SPDValueRevision1_1, + getBankArch: LP5GetBankArchSet1, + /* + * For Sabrina (as per advisory b/211510456): + * 5:4 (Maximum Activate Window) = 01 (4096 * tREFI) + * 3:0 (Maximum Activate Count) = 1000 (Unlimited MAC) + * Set to 0x18. + */ + optionalFeatures: 0x18, + /* + * For Sabrina (as per advisory b/211510456): + * 7:6 (PPR) = 1 (Post Package Repair is supported) + * Set to 0x40. + */ + otherOptionalFeatures: 0x40, + /* + * For Sabrina (as per advisory b/211510456): + * 7:5 (Number of system channels) = 000 (1 channel always) + * 4:3 (Bus width extension) = 00 (no ECC) + * 2:0 (Bus width) = 010 (x32 always) + * Set to 0x02. + */ + busWidthEncoding: 0x02, + }, +} + +var LP5PartAttributeMap = map[string]LP5MemAttributes{} +var LP5CurrSet int + +/* + * DensityEncoding: Maps the die density in Gb to the SPD encoding of the die density + * as per JESD 21-C. + * + * RowAddressBits: Maps the die density to the number of row address bits. + * Tables 6-11 in JESD209-5B (same for all three bank modes). + * + * TRFCABNs/TRFCPBNs: Maps the die density to the refresh timings. + * Tables 235 and 236 in JESD209-5B (same for all three bank modes). + */ +var LP5DensityGbToSPDEncoding = map[int]LP5DensityParams{ + 4: { + DensityEncoding: 0x4, + RowAddressBitsx8Channel: 15, + RowAddressBitsx16Channel: 14, + TRFCABNs: 180, + TRFCPBNs: 90, + }, + 6: { + DensityEncoding: 0xb, + RowAddressBitsx8Channel: 16, + RowAddressBitsx16Channel: 15, + TRFCABNs: 210, + TRFCPBNs: 120, + }, + 8: { + DensityEncoding: 0x5, + RowAddressBitsx8Channel: 16, + RowAddressBitsx16Channel: 15, + TRFCABNs: 210, + TRFCPBNs: 120, + }, + 12: { + DensityEncoding: 0x8, + RowAddressBitsx8Channel: 17, + RowAddressBitsx16Channel: 16, + TRFCABNs: 280, + TRFCPBNs: 140, + }, + 16: { + DensityEncoding: 0x6, + RowAddressBitsx8Channel: 17, + RowAddressBitsx16Channel: 16, + TRFCABNs: 280, + TRFCPBNs: 140, + }, + 24: { + DensityEncoding: 0x9, + RowAddressBitsx8Channel: 18, + RowAddressBitsx16Channel: 17, + TRFCABNs: 380, + TRFCPBNs: 190, + }, + 32: { + DensityEncoding: 0x7, + RowAddressBitsx8Channel: 18, + RowAddressBitsx16Channel: 17, + TRFCABNs: 380, + TRFCPBNs: 190, + }, +} + +/* + * Maps the number of banks to the SPD encoding as per JESD 21-C. + */ +var LP5NumBanksEncoding = map[int]byte{ + 4: 0x0, + 8: 0x1, + 16: 0x2, +} + +/* + * Maps the Bank Group bits to the SPD encoding as per JESD 21-C. + */ +var LP5BankGroupsEncoding = map[int]byte{ + 1: 0x0, + 2: 0x1, + 4: 0x2, +} + +/* + * Maps the number of row address bits to the SPD encoding as per JESD 21-C. + */ +var LP5RowAddressBitsEncoding = map[int]byte{ + 14: 0x2, + 15: 0x3, + 16: 0x4, + 17: 0x5, + 18: 0x6, +} + +/* + * Maps the number of column address bits to the SPD encoding as per JESD 21-C. + */ +var LP5ColAddressBitsEncoding = map[int]byte{ + 9: 0x0, + 10: 0x1, + 11: 0x2, + 12: 0x3, +} + +var LP5BankArchToSPDEncoding = map[int]LP5BankArchParams{ + LP5BGBankArch: { + NumBanks: 4, + BankGroups: 4, + BurstAddressBits: 4, + }, + LP58BBankArch: { + NumBanks: 8, + BankGroups: 1, + BurstAddressBits: 5, + }, + LP516BBankArch: { + NumBanks: 16, + BankGroups: 1, + BurstAddressBits: 4, + }, +} + +/* + * TCKMinPs: + * LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are + * related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used. + * For ADL, the MRC expects the tCKmin to encode the CK period. This is calculated as: + * tCKmin = 1 / CK rate + * = 1 / (WCK rate / WCK:CK) + * = 1 / (speed grade / 2 / WCK:CK) // "double data rate" + * + * MaxCASLatency: + * From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0. + */ +var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{ + 6400: { + TCKMinPs: 1250, /* 1 / (6400 / 2 / 4) */ + MaxCASLatency: 17, + }, + 5500: { + TCKMinPs: 1455, /* 1 / (5500 / 2 / 4) */ + MaxCASLatency: 15, + }, +} + +var LP5SPDAttribTable = map[int]LP5SPDAttribTableEntry{ + LP5SPDIndexSize: {constVal: LP5SPDValueSize}, + LP5SPDIndexRevision: {getVal: LP5EncodeSPDRevision}, + LP5SPDIndexMemoryType: {constVal: LP5SPDValueMemoryType}, + LP5SPDIndexModuleType: {constVal: LP5SPDValueModuleType}, + LP5SPDIndexDensityBanks: {getVal: LP5EncodeDensityBanks}, + LP5SPDIndexAddressing: {getVal: LP5EncodeSdramAddressing}, + LP5SPDIndexPackageType: {getVal: LP5EncodePackageType}, + LP5SPDIndexOptionalFeatures: {getVal: LP5EncodeOptionalFeatures}, + LP5SPDIndexOtherOptionalFeatures: {getVal: LP5EncodeOtherOptionalFeatures}, + LP5SPDIndexModuleOrganization: {getVal: LP5EncodeModuleOrganization}, + LP5SPDIndexBusWidth: {getVal: LP5EncodeBusWidth}, + LP5SPDIndexTimebases: {constVal: LP5SPDValueTimebases}, + LP5SPDIndexTCKMin: {getVal: LP5EncodeTCKMin}, + LP5SPDIndexTCKMinFineOffset: {getVal: LP5EncodeTCKMinFineOffset}, + LP5SPDIndexTAAMin: {getVal: LP5EncodeTAAMin}, + LP5SPDIndexTAAMinFineOffset: {getVal: LP5EncodeTAAMinFineOffset}, + LP5SPDIndexTRCDMin: {getVal: LP5EncodeTRCDMin}, + LP5SPDIndexTRCDMinFineOffset: {getVal: LP5EncodeTRCDMinFineOffset}, + LP5SPDIndexTRPABMin: {getVal: LP5EncodeTRPABMin}, + LP5SPDIndexTRPABMinFineOffset: {getVal: LP5EncodeTRPABMinFineOffset}, + LP5SPDIndexTRPPBMin: {getVal: LP5EncodeTRPPBMin}, + LP5SPDIndexTRPPBMinFineOffset: {getVal: LP5EncodeTRPPBMinFineOffset}, + LP5SPDIndexTRFCABMinLSB: {getVal: LP5EncodeTRFCABMinLsb}, + LP5SPDIndexTRFCABMinMSB: {getVal: LP5EncodeTRFCABMinMsb}, + LP5SPDIndexTRFCPBMinLSB: {getVal: LP5EncodeTRFCPBMinLsb}, + LP5SPDIndexTRFCPBMinMSB: {getVal: LP5EncodeTRFCPBMinMsb}, +} + +/* ------------------------------------------------------------------------------------------ */ +/* Functions */ +/* ------------------------------------------------------------------------------------------ */ +func LP5EncodeSPDRevision(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.SPDRevision +} + +func LP5GetBankArchSet0(memAttribs *LP5MemAttributes) int { + // ADL will use 8B mode for all parts. + return LP58BBankArch +} + +func LP5GetBankArchSet1(memAttribs *LP5MemAttributes) int { + /* + * Sabrina does not support 8B. It uses 16B Bank Architecture for speed <= 3200 Mbps. + * It uses BG Bank Architecture for speed > 3200 Mbps. + */ + if memAttribs.SpeedMbps <= 3200 { + return LP516BBankArch + } + return LP5BGBankArch +} + +func LP5GetBankArch(memAttribs *LP5MemAttributes) int { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false || f.getBankArch == nil { + return LP5BGBankArch + } + + return f.getBankArch(memAttribs) +} + +func LP5GetNumBanks(memAttribs *LP5MemAttributes) int { + return LP5BankArchToSPDEncoding[LP5GetBankArch(memAttribs)].NumBanks +} + +func LP5GetBankGroups(memAttribs *LP5MemAttributes) int { + return LP5BankArchToSPDEncoding[LP5GetBankArch(memAttribs)].BankGroups +} + +func LP5EncodeDensityBanks(memAttribs *LP5MemAttributes) byte { + var b byte + + // 3:0 Density per die. + b = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].DensityEncoding + + // 5:4 Bank address bits. + b |= LP5NumBanksEncoding[LP5GetNumBanks(memAttribs)] << 4 + // 7:6 Bank group bits. + b |= LP5BankGroupsEncoding[LP5GetBankGroups(memAttribs)] << 6 + + return b +} + +func LP5GetBurstAddressBits(memAttribs *LP5MemAttributes) int { + return LP5BankArchToSPDEncoding[LP5GetBankArch(memAttribs)].BurstAddressBits +} + +func LP5EncodeSdramAddressing(memAttribs *LP5MemAttributes) byte { + var b byte + + // 2:0 Column address bits. + b = LP5ColAddressBitsEncoding[LP5ColAddressBits + LP5GetBurstAddressBits(memAttribs)] + + // 5:3 Row address bits. + density := memAttribs.DensityPerDieGb + var rowAddressBits int + if memAttribs.BitWidthPerChannel == 8 { + rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx8Channel + } else { + rowAddressBits = LP5DensityGbToSPDEncoding[density].RowAddressBitsx16Channel + } + b |= LP5RowAddressBitsEncoding[rowAddressBits] << 3 + + return b +} + +func LP5EncodePackageType(memAttribs *LP5MemAttributes) byte { + var b byte + + // 1:0 Signal loading index. + b = 1 + + // 3:2 Channels per package. + // Channels per package = package width (e.g. x32) / bitWidthPerChannel (x8 or x16). + // This can equivalently be calculated as diesPerPackage / ranksPerChannel. + // This calculation is used to avoid adding a redundant attribute for package width. + channels := memAttribs.DiesPerPackage / memAttribs.RanksPerChannel + b |= byte(channels>>1) << 2 + + // 6:4 Dies per package. + b |= (byte(memAttribs.DiesPerPackage) - 1) << 4 + + // 7:7 Package type. + var packageType byte + if memAttribs.DiesPerPackage > 1 { + packageType = 1 // Non-Monolithic + } else { + packageType = 0 // Monolithic + } + b |= packageType << 7 + + return b +} + +func LP5EncodeModuleOrganization(memAttribs *LP5MemAttributes) byte { + var b byte + + // 2:0 Device data width per channel + b = byte(memAttribs.BitWidthPerChannel / 8) + + // 5:3 Package ranks per channel + b |= byte(memAttribs.RanksPerChannel-1) << 3 + + return b +} + +func LP5EncodeOptionalFeatures(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.optionalFeatures +} + +func LP5EncodeOtherOptionalFeatures(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.otherOptionalFeatures +} + +func LP5EncodeBusWidth(memAttribs *LP5MemAttributes) byte { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false { + return 0 + } + + return f.busWidthEncoding +} + +func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte { + return convPsToMtbByte(memAttribs.TCKMinPs) +} + +func LP5EncodeTCKMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convPsToFtbByte(memAttribs.TCKMinPs) +} + +func LP5EncodeTAAMin(memAttribs *LP5MemAttributes) byte { + return convPsToMtbByte(memAttribs.TAAMinPs) +} + +func LP5EncodeTAAMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convPsToFtbByte(memAttribs.TAAMinPs) +} + +func LP5EncodeTRCDMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRCDMinNs) +} + +func LP5EncodeTRCDMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRCDMinNs) +} + +func LP5EncodeTRPABMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRPABMinNs) +} + +func LP5EncodeTRPABMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRPABMinNs) +} + +func LP5EncodeTRPPBMin(memAttribs *LP5MemAttributes) byte { + return convNsToMtbByte(memAttribs.TRPPBMinNs) +} + +func LP5EncodeTRPPBMinFineOffset(memAttribs *LP5MemAttributes) byte { + return convNsToFtbByte(memAttribs.TRPPBMinNs) +} + +func LP5EncodeTRFCABMinMsb(memAttribs *LP5MemAttributes) byte { + return byte((convNsToMtb(memAttribs.TRFCABNs) >> 8) & 0xff) +} + +func LP5EncodeTRFCABMinLsb(memAttribs *LP5MemAttributes) byte { + return byte(convNsToMtb(memAttribs.TRFCABNs) & 0xff) +} + +func LP5EncodeTRFCPBMinMsb(memAttribs *LP5MemAttributes) byte { + return byte((convNsToMtb(memAttribs.TRFCPBNs) >> 8) & 0xff) +} + +func LP5EncodeTRFCPBMinLsb(memAttribs *LP5MemAttributes) byte { + return byte(convNsToMtb(memAttribs.TRFCPBNs) & 0xff) +} + +func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) { + if memAttribs.TCKMinPs == 0 { + memAttribs.TCKMinPs = LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].TCKMinPs + } +} + +func LP5UpdateTAAMin(memAttribs *LP5MemAttributes) { + if memAttribs.TAAMinPs == 0 { + maxCAS := LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].MaxCASLatency + memAttribs.TAAMinPs = memAttribs.TCKMinPs * maxCAS + } +} + +func LP5UpdateTRFCAB(memAttribs *LP5MemAttributes) { + if memAttribs.TRFCABNs == 0 { + memAttribs.TRFCABNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCABNs + } +} + +func LP5UpdateTRFCPB(memAttribs *LP5MemAttributes) { + if memAttribs.TRFCPBNs == 0 { + memAttribs.TRFCPBNs = LP5DensityGbToSPDEncoding[memAttribs.DensityPerDieGb].TRFCPBNs + } +} + +func LP5UpdateTRCD(memAttribs *LP5MemAttributes) { + if memAttribs.TRCDMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRCDMinNs = 18 + } +} + +func LP5UpdateTRPAB(memAttribs *LP5MemAttributes) { + if memAttribs.TRPABMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRPABMinNs = 21 + } +} + +func LP5UpdateTRPPB(memAttribs *LP5MemAttributes) { + if memAttribs.TRPPBMinNs == 0 { + /* Table 372 from JESD209-5B */ + memAttribs.TRPPBMinNs = 18 + } +} + +func lp5UpdateMemoryAttributes(memAttribs *LP5MemAttributes) { + LP5UpdateTCKMin(memAttribs) + LP5UpdateTAAMin(memAttribs) + LP5UpdateTRFCAB(memAttribs) + LP5UpdateTRFCPB(memAttribs) + LP5UpdateTRCD(memAttribs) + LP5UpdateTRPAB(memAttribs) + LP5UpdateTRPPB(memAttribs) +} + +func LP5ValidateDensity(density int) error { + if _, ok := LP5DensityGbToSPDEncoding[density]; !ok { + return fmt.Errorf("Incorrect density per die: %d Gb", density) + } + return nil +} + +func LP5ValidateDies(dies int) error { + if dies != 2 && dies != 4 && dies != 8 { + return fmt.Errorf("Incorrect dies: %d", dies) + } + return nil +} + +func LP5ValidateDataWidth(width int) error { + if width != 8 && width != 16 { + return fmt.Errorf("Incorrect bit width: %d", width) + } + return nil +} + +func LP5ValidateRanks(ranks int) error { + if ranks != 1 && ranks != 2 { + return fmt.Errorf("Incorrect ranks: %d", ranks) + } + return nil +} + +func LP5ValidateSpeed(speed int) error { + if _, ok := LP5SpeedMbpsToSPDEncoding[speed]; !ok { + return fmt.Errorf("Incorrect speed: %d Mbps", speed) + } + return nil +} + +func lp5ValidateMemPartAttributes(memAttribs *LP5MemAttributes) error { + if err := LP5ValidateDensity(memAttribs.DensityPerDieGb); err != nil { + return err + } + if err := LP5ValidateDies(memAttribs.DiesPerPackage); err != nil { + return err + } + if err := LP5ValidateDataWidth(memAttribs.BitWidthPerChannel); err != nil { + return err + } + if err := LP5ValidateRanks(memAttribs.RanksPerChannel); err != nil { + return err + } + if err := LP5ValidateSpeed(memAttribs.SpeedMbps); err != nil { + return err + } + + return nil +} + +func LP5IsManufacturerPartNumberByte(index int) bool { + if index >= LP5SPDIndexManufacturerPartNumberStartByte && + index <= LP5SPDIndexManufacturerPartNumberEndByte { + return true + } + return false +} + +/* ------------------------------------------------------------------------------------------ */ +/* Interface Functions */ +/* ------------------------------------------------------------------------------------------ */ + +func (lp5) getSetMap() map[int][]int { + return LP5PlatformSetMap +} + +func (lp5) addNewPart(name string, attribs interface{}) error { + var lp5Attributes LP5MemAttributes + eByte, err := json.Marshal(attribs) + if err != nil { + return err + } + + if err := json.Unmarshal(eByte, &lp5Attributes); err != nil { + return err + } + + if err := lp5ValidateMemPartAttributes(&lp5Attributes); err != nil { + return err + } + + LP5PartAttributeMap[name] = lp5Attributes + return nil +} + +func (lp5) getSPDAttribs(name string, set int) (interface{}, error) { + lp5Attributes := LP5PartAttributeMap[name] + + LP5CurrSet = set + + lp5UpdateMemoryAttributes(&lp5Attributes) + + return lp5Attributes, nil +} + +func (lp5) getSPDLen() int { + return 512 +} + +func (lp5) getSPDByte(index int, attribs interface{}) byte { + e, ok := LP5SPDAttribTable[index] + if !ok { + if LP5IsManufacturerPartNumberByte(index) { + return LP5SPDValueManufacturerPartNumberBlank + } + return 0x00 + } + + if e.getVal != nil { + var lp5Attribs LP5MemAttributes + lp5Attribs = attribs.(LP5MemAttributes) + return e.getVal(&lp5Attribs) + } + + return e.constVal +} diff --git a/util/spd_tools/src/spd_gen/spd_gen.go b/util/spd_tools/src/spd_gen/spd_gen.go index 57b428b2b3..9e939f0fed 100644 --- a/util/spd_tools/src/spd_gen/spd_gen.go +++ b/util/spd_tools/src/spd_gen/spd_gen.go @@ -28,10 +28,37 @@ type memPart struct { } type memTech interface { + /* + * Returns the set -> platform mapping for the memory technology. Platforms with the + * same SPD requirements should be grouped together into a single set. + */ getSetMap() map[int][]int + + /* + * Takes the name and attributes of a part, as read from the memory_parts JSON file. + * Validates the attributes, returning an error if any attribute has an invalid value. + * Stores the name and attributes internally to be used later. + */ addNewPart(string, interface{}) error + + /* + * Takes the name of a part and a set number. + * Retrieves the part's attributes which were stored by addNewPart(). Updates them by + * setting any optional attributes which weren't specified in the JSON file to their + * default values. + * Returns these updated attributes. + */ getSPDAttribs(string, int) (interface{}, error) + + /* + * Returns the size of an SPD file for this memory technology. + */ getSPDLen() int + + /* + * Takes an SPD byte index and the attributes of a part. + * Returns the value which that SPD byte should be set to based on the attributes. + */ getSPDByte(int, interface{}) byte } @@ -45,6 +72,7 @@ const ( PlatformJSL PlatformPCO PlatformCZN + PlatformSBR PlatformMax ) @@ -63,6 +91,13 @@ var platformNames = map[int]string{ PlatformJSL: "JSL", PlatformPCO: "PCO", PlatformCZN: "CZN", + PlatformSBR: "SBR", +} + +var memTechMap = map[string]memTech{ + "lp4x": lp4x{}, + "ddr4": ddr4{}, + "lp5": lp5{}, } /* ------------------------------------------------------------------------------------------ */ @@ -211,7 +246,9 @@ func usage() { fmt.Printf("\nUsage: %s \n\n", os.Args[0]) fmt.Printf(" where,\n") fmt.Printf(" mem_parts_list_json = JSON File containing list of memory parts and attributes\n") - fmt.Printf(" mem_technology = Memory technology -- one of lp4x, ddr4\n\n\n") + fmt.Printf(" mem_technology = Memory technology for which to generate SPDs\n") + fmt.Printf(" supported technologies: %v\n\n\n", + reflect.ValueOf(memTechMap).MapKeys()) } func main() { @@ -223,11 +260,8 @@ func main() { var t memTech memPartsFilePath, memTechnology := os.Args[1], os.Args[2] - if strings.ToUpper(memTechnology) == "LP4X" { - t = lp4x{} - } else if strings.ToUpper(memTechnology) == "DDR4" { - t = ddr4{} - } else { + t, ok := memTechMap[strings.ToLower(memTechnology)] + if !ok { log.Fatal("Unsupported memory technology ", memTechnology) } diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index a9fd6488cc..0830aea501 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -54,6 +54,7 @@ amdfwtool \ cbmem \ ectool \ futility \ +ifdtool \ intelmetool \ inteltool \ intelvbttool \ @@ -85,6 +86,11 @@ ifneq ($(JENKINS_SKIP_LINT_TESTS),y) util/lint/lint lint-stable --junit util/lint/lint lint-extended --junit endif + if [ ! -f 3rdparty/intel-sec-tools/go.mod ]; then \ + echo "Please download 3rdparty/intel-sec-tools/:"; \ + echo "git submodule update --init 3rdparty/intel-sec-tools"; \ + exit 1; \ + fi cd 3rdparty/intel-sec-tools/ ; go mod vendor util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/chromeos $(ABUILD_OPTIONS) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -o $(COREBOOT_BUILD_DIR)/default $(ABUILD_OPTIONS) @@ -96,8 +102,10 @@ endif $(MAKE) xcompile=$(COREBOOT_BUILD_DIR)/xcompile $(COREBOOT_BUILD_DIR)/xcompile $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra124/lp0 BLD=tegra124_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml $(MAKE) CPUS=$(CPUS) V=$(V) Q=$(Q) BLD_DIR=src/soc/nvidia/tegra210/lp0 BLD=tegra120_lp0 MFLAGS= MAKEFLAGS=xcompile=$(COREBOOT_BUILD_DIR)/xcompile MAKETARGET=all junit.xml - $(MAKE) unit-tests JUNIT_OUTPUT=y - (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) unit-tests JUNIT_OUTPUT=y) + $(MAKE) unit-tests JUNIT_OUTPUT=y COV=1 + (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) unit-tests coverage-report JUNIT_OUTPUT=y COV=1) + $(MAKE) coverage-report JUNIT_OUTPUT=y COV=1 + find . -name 'tests.info' -exec cat {} + >$(COREBOOT_BUILD_DIR)/coverage.info test-basic: test-lint test-tools test-abuild test-payloads test-cleanup